From: lkcl <lkcl@web>
Date: Fri, 6 May 2022 13:39:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2370
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3846ee94625cc71d678d4eba4cec7b2a056eeb9e;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index b94578c40..4a6f61060 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -578,3 +578,22 @@ as powerful as OpenCAPI as part of that picture.
 
 **Snitch**
 
+Snitch is an elegant Memory-Coherent Barrel-Processor where registers
+become "tagged" with a Memory-access Mode that went out of fashion
+over forty years ago: Load-and-Increment. Expressed in c as
+`src = *x++`, and requiring special Address Registers (PDP-11, 68000)
+the efficiency of these Load-Store-with-Increment instructions has been
+forgotten until Snitch.
+
+What the designers did however was not to add new Load-Store
+or Arithmetic instructions to RISC-V, but instead to "mark"
+registers with a tag.  These tags tell the CPU: when you perform
+an add on r6 and r7, please perform a Cache-coherent Load-with-Increment
+on each, using special Address Registers for each.  Each reference
+to r6 therefore brings in an entirely new value *directly from
+memory*. Likewise on the second operand, r7, and likewise on
+the destination which can be automatic Store-and-increment.
+
+On top of a barrel-architecture the slowness of Memory access
+was not a problem because the Deterministic nature of classic
+Load-Store-Increment