From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Dec 2021 17:47:03 +0000 (+0000)
Subject: enable MMU in SimRunner if requested.  now HDL and ISACaller run MMU
X-Git-Tag: sv_maxu_works-initial~667
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3848bb6c6ba101febd690982cf239d00e7406586;p=openpower-isa.git

enable MMU in SimRunner if requested.  now HDL and ISACaller run MMU
---

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 089ac4f7..5d68ec74 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -42,6 +42,7 @@ class SimRunner(StateRunner):
         super().__init__("sim", SimRunner)
         self.dut = dut
 
+        self.mmu = pspec.mmu == True
         regreduce_en = pspec.regreduce_en == True
         self.simdec2 = simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
         m.submodules.simdec2 = simdec2  # pain in the neck
@@ -64,7 +65,8 @@ class SimRunner(StateRunner):
                   initial_insns=gen, respect_pc=True,
                   disassembly=insncode,
                   bigendian=bigendian,
-                  initial_svstate=test.svstate)
+                  initial_svstate=test.svstate,
+                  mmu=self.mmu)
 
         # run the loop of the instructions on the current test
         index = sim.pc.CIA.value//4