From: lkcl <lkcl@web>
Date: Fri, 8 May 2020 11:01:33 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2707
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3863afd0081993fe5f8a2cc0cefe8cfd4afb85e5;p=libreriscv.git

---

diff --git a/180nm_Oct2020.mdwn b/180nm_Oct2020.mdwn
index 27417ece8..e1f29df14 100644
--- a/180nm_Oct2020.mdwn
+++ b/180nm_Oct2020.mdwn
@@ -19,7 +19,7 @@ To be expanded with links to bugreports
 * a very very basic Common Data Bus infrastructure.
 * a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC)
 * neither in some ways is a L1 cache
-* [[180nm_oct2020/interfaces]] we need as a bare minimum include GPIO, EINT, SPI and QSPI,
+* [[180nm_Oct2020/interfaces]] we need as a bare minimum include GPIO, EINT, SPI and QSPI,
   I2C, UART16550, LPC (from Raptor Engineering) and that actually might
   even be it.