From: Andreas Hansson <andreas.hansson@arm.com>
Date: Fri, 19 Sep 2014 14:35:04 +0000 (-0400)
Subject: mem: Add checks to sendTimingReq in cache
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=38646d48ebd32c551ce3c478e9dee47f83acdf1e;p=gem5.git

mem: Add checks to sendTimingReq in cache

A small fix to ensure the return value is not ignored.
---

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a792de19d..8c091fa39 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -462,7 +462,9 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
 
     // Just forward the packet if caches are disabled.
     if (system->bypassCaches()) {
-        memSidePort->sendTimingReq(pkt);
+        // @todo This should really enqueue the packet rather
+        bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
+        assert(success);
         return true;
     }
 
@@ -483,7 +485,10 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
             snoopPkt->busFirstWordDelay = snoopPkt->busLastWordDelay = 0;
             snoopPkt->setExpressSnoop();
             snoopPkt->assertMemInhibit();
-            memSidePort->sendTimingReq(snoopPkt);
+            bool M5_VAR_USED success = memSidePort->sendTimingReq(snoopPkt);
+            // the packet is marked inhibited and will thus bypass any
+            // flow control
+            assert(success);
             // main memory will delete snoopPkt
         }
         // since we're the official target but we aren't responding,