From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 16 Dec 2021 14:55:38 +0000 (+0000)
Subject: give names to MMU records
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=386b44d4d41c8fefa0d03c80728fed2271da1638;p=soc.git

give names to MMU records
---

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index e7010584..1f69ec1f 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -113,11 +113,11 @@ class MMU(Elaboratable):
     (i.e. there is no gRA -> hRA translation).
     """
     def __init__(self):
-        self.l_in  = LoadStore1ToMMUType()
-        self.l_out = MMUToLoadStore1Type()
-        self.d_out = MMUToDCacheType()
-        self.d_in  = DCacheToMMUType()
-        self.i_out = MMUToICacheType()
+        self.l_in  = LoadStore1ToMMUType("l_in")
+        self.l_out = MMUToLoadStore1Type("l_out")
+        self.d_out = MMUToDCacheType("d_out")
+        self.d_in  = DCacheToMMUType("d_in")
+        self.i_out = MMUToICacheType("i_out")
 
     def radix_tree_idle(self, m, l_in, r, v):
         comb = m.d.comb