From: Luke Kenneth Casson Leighton Date: Fri, 23 Sep 2022 17:40:33 +0000 (+0100) Subject: remove need for explicit-hack for "pcdec." - rc column in minor_4.csv file X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=38802b1df42b147ebaa413e65c872510279b1429;p=openpower-isa.git remove need for explicit-hack for "pcdec." - rc column in minor_4.csv file can be set "rc=ONE" which tells ISACaller (and PowerDecoder2) to *always* write to CR0 --- diff --git a/openpower/isatables/minor_4.csv b/openpower/isatables/minor_4.csv index 75893e67..5cfcfd04 100644 --- a/openpower/isatables/minor_4.csv +++ b/openpower/isatables/minor_4.csv @@ -4,5 +4,5 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 48,ALU,OP_MADDHD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhd,VA,,, 49,ALU,OP_MADDHDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhdu,VA,,, 51,ALU,OP_MADDLD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddld,VA,,, -56,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,pcdec,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg -57,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,pcdec,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg +56,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg +57,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 15a4ad9f..74a63a18 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1695,10 +1695,6 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): if not self.is_svp64_mode or not pred_dst_zero: if hasattr(self.dec2.e.do, "rc"): rc_en = yield self.dec2.e.do.rc.rc - # argh - these are *always* Rc=1 (but not really, they do write to CR0) - if ins_name == 'pcdec': # TODO add stbcx etc. when supported - log ("hack-enable Rc=1 for %s - CR0" % ins_name, cr0) - rc_en = True # don't do Rc=1 for svstep it is handled explicitly. # XXX TODO: now that CR0 is supported, sort out svstep's pseudocode # to write directly to CR0 instead of in ISACaller. hooyahh.