From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 Dec 2021 23:57:33 +0000 (+0000)
Subject: another major bug, CacheTagArray valid was only 1 bit not NUM_WAYS
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3880c51305d4704e3654286de00218d3e336948a;p=soc.git

another major bug, CacheTagArray valid was only 1 bit not NUM_WAYS
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index b3b3fd57..3460e976 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -162,7 +162,7 @@ print ("    TAG_WIDTH", TAG_WIDTH)
 print ("     NUM_WAYS", NUM_WAYS)
 
 def CacheTagArray():
-    tag_layout = [('valid', 1),
+    tag_layout = [('valid', NUM_WAYS),
                   ('tag', TAG_RAM_WIDTH),
                  ]
     return Array(Record(tag_layout, name="tag%d" % x) for x in range(NUM_LINES))