From: Cole Poirier Date: Wed, 4 Nov 2020 01:09:32 +0000 (-0800) Subject: HDL_workflow/ECP5_FPGA provide two images showing different orientation X-Git-Tag: convert-csv-opcode-to-binary~1872 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=38c5b6f9e3eb20838650232d8f681985e9e9128d;p=libreriscv.git HDL_workflow/ECP5_FPGA provide two images showing different orientation of stlinkv2 --- diff --git a/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg b/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg deleted file mode 100644 index c03ef96ee..000000000 Binary files a/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg and /dev/null differ diff --git a/HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg b/HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg new file mode 100644 index 000000000..7d2687c5c Binary files /dev/null and b/HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg differ diff --git a/HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg b/HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg new file mode 100644 index 000000000..6e5f8f685 Binary files /dev/null and b/HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg differ