From: Luke Kenneth Casson Leighton Date: Thu, 1 Apr 2021 22:29:06 +0000 (+0000) Subject: update / refresh full core DFF X-Git-Tag: LS180_RC3~160 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=38cf7b92b813f2964627d8e9608369d28a34ab10;p=soclayout.git update / refresh full core DFF --- diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index b1f7178..5fb3a42 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -1,5 +1,5 @@ # Generated by Yosys 0.9+3981 (git sha1 a3528649, clang 9.0.1-12 -fPIC -Os) -autoidx 14636 +autoidx 14564 attribute \src "libresoc.v:5.1-335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" @@ -30909,9 +30909,9 @@ module \adr_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:21209.7-21209.15" wire \initial @@ -31113,9 +31113,9 @@ module \adrok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 6 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:21271.7-21271.15" wire \initial @@ -32209,9 +32209,9 @@ module \alu0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \cr_a_ok @@ -35324,9 +35324,9 @@ module \alu_alu0 wire input 18 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 28 \cr_a @@ -36367,9 +36367,9 @@ module \alu_branch0 wire input 13 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 20 \cr_a @@ -36713,9 +36713,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" attribute \generator "nMigen" module \alu_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 12 \cr_a @@ -37239,9 +37239,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" attribute \generator "nMigen" module \alu_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 35 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 27 \cr_a @@ -38761,9 +38761,9 @@ module \alu_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26289.7-26289.15" wire \initial @@ -38965,9 +38965,9 @@ module \alu_l$107 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26351.7-26351.15" wire \initial @@ -39169,9 +39169,9 @@ module \alu_l$125 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26413.7-26413.15" wire \initial @@ -39373,9 +39373,9 @@ module \alu_l$128 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26475.7-26475.15" wire \initial @@ -39577,9 +39577,9 @@ module \alu_l$16 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26537.7-26537.15" wire \initial @@ -39781,9 +39781,9 @@ module \alu_l$29 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26599.7-26599.15" wire \initial @@ -39985,9 +39985,9 @@ module \alu_l$45 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26661.7-26661.15" wire \initial @@ -40189,9 +40189,9 @@ module \alu_l$61 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26723.7-26723.15" wire \initial @@ -40393,9 +40393,9 @@ module \alu_l$73 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26785.7-26785.15" wire \initial @@ -40597,9 +40597,9 @@ module \alu_l$90 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26847.7-26847.15" wire \initial @@ -40759,9 +40759,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0" attribute \generator "nMigen" module \alu_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a @@ -41785,9 +41785,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" attribute \generator "nMigen" module \alu_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 21 \cr_a @@ -43017,9 +43017,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" attribute \generator "nMigen" module \alu_shift_rot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a @@ -44063,9 +44063,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" attribute \generator "nMigen" module \alu_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 16 \fast1 @@ -44632,9 +44632,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" attribute \generator "nMigen" module \alu_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 19 \fast1 @@ -45560,9 +45560,9 @@ module \alui_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31623.7-31623.15" wire \initial @@ -45764,9 +45764,9 @@ module \alui_l$106 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31685.7-31685.15" wire \initial @@ -45968,9 +45968,9 @@ module \alui_l$124 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31747.7-31747.15" wire \initial @@ -46172,9 +46172,9 @@ module \alui_l$15 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31809.7-31809.15" wire \initial @@ -46376,9 +46376,9 @@ module \alui_l$28 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31871.7-31871.15" wire \initial @@ -46580,9 +46580,9 @@ module \alui_l$44 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31933.7-31933.15" wire \initial @@ -46784,9 +46784,9 @@ module \alui_l$60 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31995.7-31995.15" wire \initial @@ -46988,9 +46988,9 @@ module \alui_l$72 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:32057.7-32057.15" wire \initial @@ -47192,9 +47192,9 @@ module \alui_l$89 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:32119.7-32119.15" wire \initial @@ -50637,9 +50637,9 @@ module \branch0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 11 \cu_busy_o @@ -52876,9 +52876,9 @@ module \busy_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:34588.7-34588.15" wire \initial @@ -56968,3548 +56968,3548 @@ module \clz connect \pair2 \sig_in [3:2] connect \pair0 \sig_in [1:0] end -attribute \src "libresoc.v:36261.1-49121.10" +attribute \src "libresoc.v:36261.1-48917.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core" attribute \generator "nMigen" module \core - attribute \src "libresoc.v:46594.3-46614.6" + attribute \src "libresoc.v:46390.3-46410.6" wire $0\core_terminate_o$next[0:0]$2679 - attribute \src "libresoc.v:42990.3-42991.49" + attribute \src "libresoc.v:42786.3-42787.49" wire $0\core_terminate_o[0:0] - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $0\corebusy_o[0:0] - attribute \src "libresoc.v:46424.3-46454.6" + attribute \src "libresoc.v:46220.3-46250.6" wire width 2 $0\counter$next[1:0]$2657 - attribute \src "libresoc.v:42992.3-42993.31" + attribute \src "libresoc.v:42788.3-42789.31" wire width 2 $0\counter[1:0] - attribute \src "libresoc.v:46396.3-46404.6" + attribute \src "libresoc.v:46192.3-46200.6" wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 - attribute \src "libresoc.v:42926.3-42927.57" + attribute \src "libresoc.v:42722.3-42723.57" wire $0\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:46377.3-46385.6" + attribute \src "libresoc.v:46173.3-46181.6" wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 - attribute \src "libresoc.v:42928.3-42929.49" + attribute \src "libresoc.v:42724.3-42725.49" wire $0\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46415.3-46423.6" + attribute \src "libresoc.v:46211.3-46219.6" wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2654 - attribute \src "libresoc.v:42924.3-42925.49" + attribute \src "libresoc.v:42720.3-42721.49" wire $0\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46465.3-46473.6" + attribute \src "libresoc.v:46261.3-46269.6" wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 - attribute \src "libresoc.v:42922.3-42923.49" + attribute \src "libresoc.v:42718.3-42719.49" wire $0\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:46358.3-46366.6" + attribute \src "libresoc.v:46154.3-46162.6" wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 - attribute \src "libresoc.v:42930.3-42931.55" + attribute \src "libresoc.v:42726.3-42727.55" wire $0\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46575.3-46583.6" + attribute \src "libresoc.v:46371.3-46379.6" wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2673 - attribute \src "libresoc.v:42920.3-42921.63" + attribute \src "libresoc.v:42716.3-42717.63" wire $0\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46682.3-46690.6" + attribute \src "libresoc.v:46478.3-46486.6" wire $0\dp_FAST_fast1_branch0_3$next[0:0]$2697 - attribute \src "libresoc.v:42914.3-42915.63" + attribute \src "libresoc.v:42710.3-42711.63" wire $0\dp_FAST_fast1_branch0_3[0:0] - attribute \src "libresoc.v:46634.3-46642.6" + attribute \src "libresoc.v:46430.3-46438.6" wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2690 - attribute \src "libresoc.v:42916.3-42917.57" + attribute \src "libresoc.v:42712.3-42713.57" wire $0\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46615.3-46623.6" + attribute \src "libresoc.v:46411.3-46419.6" wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 - attribute \src "libresoc.v:42918.3-42919.59" + attribute \src "libresoc.v:42714.3-42715.59" wire $0\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46701.3-46709.6" + attribute \src "libresoc.v:46497.3-46505.6" wire $0\dp_FAST_fast1_trap0_4$next[0:0]$2703 - attribute \src "libresoc.v:42912.3-42913.59" + attribute \src "libresoc.v:42708.3-42709.59" wire $0\dp_FAST_fast1_trap0_4[0:0] - attribute \src "libresoc.v:45807.3-45815.6" + attribute \src "libresoc.v:45603.3-45611.6" wire $0\dp_INT_rabc_alu0_0$next[0:0]$2474 - attribute \src "libresoc.v:42988.3-42989.53" + attribute \src "libresoc.v:42784.3-42785.53" wire $0\dp_INT_rabc_alu0_0[0:0] - attribute \src "libresoc.v:45997.3-46005.6" + attribute \src "libresoc.v:45793.3-45801.6" wire $0\dp_INT_rabc_alu0_10$next[0:0]$2530 - attribute \src "libresoc.v:42968.3-42969.55" + attribute \src "libresoc.v:42764.3-42765.55" wire $0\dp_INT_rabc_alu0_10[0:0] - attribute \src "libresoc.v:45826.3-45834.6" + attribute \src "libresoc.v:45622.3-45630.6" wire $0\dp_INT_rabc_cr0_1$next[0:0]$2478 - attribute \src "libresoc.v:46016.3-46024.6" + attribute \src "libresoc.v:45812.3-45820.6" wire $0\dp_INT_rabc_cr0_11$next[0:0]$2534 - attribute \src "libresoc.v:42966.3-42967.53" + attribute \src "libresoc.v:42762.3-42763.53" wire $0\dp_INT_rabc_cr0_11[0:0] - attribute \src "libresoc.v:42986.3-42987.51" + attribute \src "libresoc.v:42782.3-42783.51" wire $0\dp_INT_rabc_cr0_1[0:0] - attribute \src "libresoc.v:46092.3-46100.6" + attribute \src "libresoc.v:45888.3-45896.6" wire $0\dp_INT_rabc_div0_15$next[0:0]$2558 - attribute \src "libresoc.v:42958.3-42959.55" + attribute \src "libresoc.v:42754.3-42755.55" wire $0\dp_INT_rabc_div0_15[0:0] - attribute \src "libresoc.v:45883.3-45891.6" + attribute \src "libresoc.v:45679.3-45687.6" wire $0\dp_INT_rabc_div0_4$next[0:0]$2496 - attribute \src "libresoc.v:42980.3-42981.53" + attribute \src "libresoc.v:42776.3-42777.53" wire $0\dp_INT_rabc_div0_4[0:0] - attribute \src "libresoc.v:46149.3-46157.6" + attribute \src "libresoc.v:45945.3-45953.6" wire $0\dp_INT_rabc_ldst0_18$next[0:0]$2576 - attribute \src "libresoc.v:42952.3-42953.57" + attribute \src "libresoc.v:42748.3-42749.57" wire $0\dp_INT_rabc_ldst0_18[0:0] - attribute \src "libresoc.v:45940.3-45948.6" + attribute \src "libresoc.v:45736.3-45744.6" wire $0\dp_INT_rabc_ldst0_7$next[0:0]$2514 - attribute \src "libresoc.v:42974.3-42975.55" + attribute \src "libresoc.v:42770.3-42771.55" wire $0\dp_INT_rabc_ldst0_7[0:0] - attribute \src "libresoc.v:45978.3-45986.6" + attribute \src "libresoc.v:45774.3-45782.6" wire $0\dp_INT_rabc_ldst0_9$next[0:0]$2524 - attribute \src "libresoc.v:42970.3-42971.55" + attribute \src "libresoc.v:42766.3-42767.55" wire $0\dp_INT_rabc_ldst0_9[0:0] - attribute \src "libresoc.v:46054.3-46062.6" + attribute \src "libresoc.v:45850.3-45858.6" wire $0\dp_INT_rabc_logical0_13$next[0:0]$2546 - attribute \src "libresoc.v:42962.3-42963.63" + attribute \src "libresoc.v:42758.3-42759.63" wire $0\dp_INT_rabc_logical0_13[0:0] - attribute \src "libresoc.v:45864.3-45872.6" + attribute \src "libresoc.v:45660.3-45668.6" wire $0\dp_INT_rabc_logical0_3$next[0:0]$2490 - attribute \src "libresoc.v:42982.3-42983.61" + attribute \src "libresoc.v:42778.3-42779.61" wire $0\dp_INT_rabc_logical0_3[0:0] - attribute \src "libresoc.v:46111.3-46119.6" + attribute \src "libresoc.v:45907.3-45915.6" wire $0\dp_INT_rabc_mul0_16$next[0:0]$2564 - attribute \src "libresoc.v:42956.3-42957.55" + attribute \src "libresoc.v:42752.3-42753.55" wire $0\dp_INT_rabc_mul0_16[0:0] - attribute \src "libresoc.v:45902.3-45910.6" + attribute \src "libresoc.v:45698.3-45706.6" wire $0\dp_INT_rabc_mul0_5$next[0:0]$2502 - attribute \src "libresoc.v:42978.3-42979.53" + attribute \src "libresoc.v:42774.3-42775.53" wire $0\dp_INT_rabc_mul0_5[0:0] - attribute \src "libresoc.v:46130.3-46138.6" + attribute \src "libresoc.v:45926.3-45934.6" wire $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570 - attribute \src "libresoc.v:42954.3-42955.65" + attribute \src "libresoc.v:42750.3-42751.65" wire $0\dp_INT_rabc_shiftrot0_17[0:0] - attribute \src "libresoc.v:45921.3-45929.6" + attribute \src "libresoc.v:45717.3-45725.6" wire $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508 - attribute \src "libresoc.v:42976.3-42977.63" + attribute \src "libresoc.v:42772.3-42773.63" wire $0\dp_INT_rabc_shiftrot0_6[0:0] - attribute \src "libresoc.v:45959.3-45967.6" + attribute \src "libresoc.v:45755.3-45763.6" wire $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520 - attribute \src "libresoc.v:42972.3-42973.63" + attribute \src "libresoc.v:42768.3-42769.63" wire $0\dp_INT_rabc_shiftrot0_8[0:0] - attribute \src "libresoc.v:46073.3-46081.6" + attribute \src "libresoc.v:45869.3-45877.6" wire $0\dp_INT_rabc_spr0_14$next[0:0]$2552 - attribute \src "libresoc.v:42960.3-42961.55" + attribute \src "libresoc.v:42756.3-42757.55" wire $0\dp_INT_rabc_spr0_14[0:0] - attribute \src "libresoc.v:46035.3-46043.6" + attribute \src "libresoc.v:45831.3-45839.6" wire $0\dp_INT_rabc_trap0_12$next[0:0]$2540 - attribute \src "libresoc.v:42964.3-42965.57" + attribute \src "libresoc.v:42760.3-42761.57" wire $0\dp_INT_rabc_trap0_12[0:0] - attribute \src "libresoc.v:45845.3-45853.6" + attribute \src "libresoc.v:45641.3-45649.6" wire $0\dp_INT_rabc_trap0_2$next[0:0]$2484 - attribute \src "libresoc.v:42984.3-42985.55" + attribute \src "libresoc.v:42780.3-42781.55" wire $0\dp_INT_rabc_trap0_2[0:0] - attribute \src "libresoc.v:46749.3-46757.6" + attribute \src "libresoc.v:46545.3-46553.6" wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2710 - attribute \src "libresoc.v:42910.3-42911.53" + attribute \src "libresoc.v:42706.3-42707.53" wire $0\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:46282.3-46290.6" + attribute \src "libresoc.v:46078.3-46086.6" wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 - attribute \src "libresoc.v:42938.3-42939.57" + attribute \src "libresoc.v:42734.3-42735.57" wire $0\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:46320.3-46328.6" + attribute \src "libresoc.v:46116.3-46124.6" wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 - attribute \src "libresoc.v:42934.3-42935.67" + attribute \src "libresoc.v:42730.3-42731.67" wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:46301.3-46309.6" + attribute \src "libresoc.v:46097.3-46105.6" wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 - attribute \src "libresoc.v:42936.3-42937.57" + attribute \src "libresoc.v:42732.3-42733.57" wire $0\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:46339.3-46347.6" + attribute \src "libresoc.v:46135.3-46143.6" wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 - attribute \src "libresoc.v:42932.3-42933.57" + attribute \src "libresoc.v:42728.3-42729.57" wire $0\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:46168.3-46176.6" + attribute \src "libresoc.v:45964.3-45972.6" wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 - attribute \src "libresoc.v:42950.3-42951.57" + attribute \src "libresoc.v:42746.3-42747.57" wire $0\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:46225.3-46233.6" + attribute \src "libresoc.v:46021.3-46029.6" wire $0\dp_XER_xer_so_div0_3$next[0:0]$2598 - attribute \src "libresoc.v:42944.3-42945.57" + attribute \src "libresoc.v:42740.3-42741.57" wire $0\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:46187.3-46195.6" + attribute \src "libresoc.v:45983.3-45991.6" wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 - attribute \src "libresoc.v:42948.3-42949.65" + attribute \src "libresoc.v:42744.3-42745.65" wire $0\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:46244.3-46252.6" + attribute \src "libresoc.v:46040.3-46048.6" wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 - attribute \src "libresoc.v:42942.3-42943.57" + attribute \src "libresoc.v:42738.3-42739.57" wire $0\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:46263.3-46271.6" + attribute \src "libresoc.v:46059.3-46067.6" wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 - attribute \src "libresoc.v:42940.3-42941.67" + attribute \src "libresoc.v:42736.3-42737.67" wire $0\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:46206.3-46214.6" + attribute \src "libresoc.v:46002.3-46010.6" wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 - attribute \src "libresoc.v:42946.3-42947.57" + attribute \src "libresoc.v:42742.3-42743.57" wire $0\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:47563.3-47591.6" + attribute \src "libresoc.v:47359.3-47387.6" wire $0\fus_cu_issue_i$13[0:0]$2824 - attribute \src "libresoc.v:47888.3-47916.6" + attribute \src "libresoc.v:47684.3-47712.6" wire $0\fus_cu_issue_i$16[0:0]$2862 - attribute \src "libresoc.v:48207.3-48235.6" + attribute \src "libresoc.v:48003.3-48031.6" wire $0\fus_cu_issue_i$19[0:0]$2881 - attribute \src "libresoc.v:43852.3-43880.6" + attribute \src "libresoc.v:43648.3-43676.6" wire $0\fus_cu_issue_i$22[0:0]$2359 - attribute \src "libresoc.v:44026.3-44054.6" + attribute \src "libresoc.v:43822.3-43850.6" wire $0\fus_cu_issue_i$25[0:0]$2373 - attribute \src "libresoc.v:44522.3-44550.6" + attribute \src "libresoc.v:44318.3-44346.6" wire $0\fus_cu_issue_i$28[0:0]$2398 - attribute \src "libresoc.v:44844.3-44872.6" + attribute \src "libresoc.v:44640.3-44668.6" wire $0\fus_cu_issue_i$31[0:0]$2417 - attribute \src "libresoc.v:45311.3-45339.6" + attribute \src "libresoc.v:45107.3-45135.6" wire $0\fus_cu_issue_i$34[0:0]$2441 - attribute \src "libresoc.v:45749.3-45777.6" + attribute \src "libresoc.v:45545.3-45573.6" wire $0\fus_cu_issue_i$37[0:0]$2464 - attribute \src "libresoc.v:47355.3-47383.6" + attribute \src "libresoc.v:47151.3-47179.6" wire $0\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47610.3-47638.6" + attribute \src "libresoc.v:47406.3-47434.6" wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2835 - attribute \src "libresoc.v:47917.3-47945.6" + attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $0\fus_cu_rdmaskn_i$18[2:0]$2867 - attribute \src "libresoc.v:48236.3-48264.6" + attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $0\fus_cu_rdmaskn_i$21[3:0]$2886 - attribute \src "libresoc.v:43881.3-43909.6" + attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2364 - attribute \src "libresoc.v:44055.3-44083.6" + attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $0\fus_cu_rdmaskn_i$27[5:0]$2378 - attribute \src "libresoc.v:44551.3-44579.6" + attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2403 - attribute \src "libresoc.v:44873.3-44901.6" + attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $0\fus_cu_rdmaskn_i$33[2:0]$2422 - attribute \src "libresoc.v:45340.3-45368.6" + attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $0\fus_cu_rdmaskn_i$36[4:0]$2446 - attribute \src "libresoc.v:45778.3-45806.6" + attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $0\fus_cu_rdmaskn_i$39[2:0]$2469 - attribute \src "libresoc.v:47393.3-47421.6" + attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $0\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47270.3-47298.6" + attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46720.3-46748.6" + attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $0\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46768.3-46797.6" + attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46768.3-46797.6" + attribute \src "libresoc.v:46564.3-46593.6" wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47100.3-47128.6" + attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47308.3-47336.6" + attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46653.3-46681.6" + attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46939.3-46967.6" + attribute \src "libresoc.v:46735.3-46763.6" wire $0\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47015.3-47043.6" + attribute \src "libresoc.v:46811.3-46839.6" wire $0\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47185.3-47213.6" + attribute \src "libresoc.v:46981.3-47009.6" wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47223.3-47251.6" + attribute \src "libresoc.v:47019.3-47047.6" wire $0\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46882.3-46911.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46882.3-46911.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47147.3-47175.6" + attribute \src "libresoc.v:46943.3-46971.6" wire $0\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46825.3-46854.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46825.3-46854.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47053.3-47081.6" + attribute \src "libresoc.v:46849.3-46877.6" wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46977.3-47005.6" + attribute \src "libresoc.v:46773.3-46801.6" wire $0\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47648.3-47676.6" + attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47733.3-47761.6" + attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $0\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47800.3-47829.6" + attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47800.3-47829.6" + attribute \src "libresoc.v:47596.3-47625.6" wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47771.3-47799.6" + attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47686.3-47714.6" + attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47859.3-47887.6" + attribute \src "libresoc.v:47655.3-47683.6" wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47830.3-47858.6" + attribute \src "libresoc.v:47626.3-47654.6" wire $0\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47478.3-47506.6" + attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $0\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47525.3-47553.6" + attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47440.3-47468.6" + attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44464.3-44492.6" + attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44113.3-44141.6" + attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $0\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44142.3-44171.6" + attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44142.3-44171.6" + attribute \src "libresoc.v:43938.3-43967.6" wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44290.3-44318.6" + attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44493.3-44521.6" + attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44084.3-44112.6" + attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44232.3-44260.6" + attribute \src "libresoc.v:44028.3-44056.6" wire $0\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44319.3-44347.6" + attribute \src "libresoc.v:44115.3-44143.6" wire $0\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44406.3-44434.6" + attribute \src "libresoc.v:44202.3-44230.6" wire $0\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44435.3-44463.6" + attribute \src "libresoc.v:44231.3-44259.6" wire $0\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44202.3-44231.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $0\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44202.3-44231.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $0\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44377.3-44405.6" + attribute \src "libresoc.v:44173.3-44201.6" wire $0\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44172.3-44201.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $0\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44172.3-44201.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $0\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44348.3-44376.6" + attribute \src "libresoc.v:44144.3-44172.6" wire $0\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44261.3-44289.6" + attribute \src "libresoc.v:44057.3-44085.6" wire $0\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43794.3-43822.6" + attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48294.3-48322.6" + attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $0\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48323.3-48352.6" + attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48323.3-48352.6" + attribute \src "libresoc.v:48119.3-48148.6" wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48471.3-48499.6" + attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43823.3-43851.6" + attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48265.3-48293.6" + attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48413.3-48441.6" + attribute \src "libresoc.v:48209.3-48237.6" wire $0\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48500.3-48528.6" + attribute \src "libresoc.v:48296.3-48324.6" wire $0\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43736.3-43764.6" + attribute \src "libresoc.v:43532.3-43560.6" wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43765.3-43793.6" + attribute \src "libresoc.v:43561.3-43589.6" wire $0\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48383.3-48412.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48383.3-48412.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43707.3-43735.6" + attribute \src "libresoc.v:43503.3-43531.6" wire $0\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48353.3-48382.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48353.3-48382.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48529.3-48557.6" + attribute \src "libresoc.v:48325.3-48353.6" wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48442.3-48470.6" + attribute \src "libresoc.v:48238.3-48266.6" wire $0\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44609.3-44637.6" + attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $0\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44638.3-44667.6" + attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44638.3-44667.6" + attribute \src "libresoc.v:44434.3-44463.6" wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44815.3-44843.6" + attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44580.3-44608.6" + attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44757.3-44785.6" + attribute \src "libresoc.v:44553.3-44581.6" wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44786.3-44814.6" + attribute \src "libresoc.v:44582.3-44610.6" wire $0\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44698.3-44727.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44698.3-44727.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44668.3-44697.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44668.3-44697.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44728.3-44756.6" + attribute \src "libresoc.v:44524.3-44552.6" wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44931.3-44959.6" + attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44960.3-44989.6" + attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44960.3-44989.6" + attribute \src "libresoc.v:44756.3-44785.6" wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45108.3-45136.6" + attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45166.3-45194.6" + attribute \src "libresoc.v:44962.3-44990.6" wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45282.3-45310.6" + attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44902.3-44930.6" + attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45079.3-45107.6" + attribute \src "libresoc.v:44875.3-44903.6" wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45224.3-45252.6" + attribute \src "libresoc.v:45020.3-45048.6" wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45253.3-45281.6" + attribute \src "libresoc.v:45049.3-45077.6" wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45020.3-45049.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45020.3-45049.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45137.3-45165.6" + attribute \src "libresoc.v:44933.3-44961.6" wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45195.3-45223.6" + attribute \src "libresoc.v:44991.3-45019.6" wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44990.3-45019.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44990.3-45019.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45050.3-45078.6" + attribute \src "libresoc.v:44846.3-44874.6" wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43939.3-43967.6" + attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $0\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43968.3-43996.6" + attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43910.3-43938.6" + attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43997.3-44025.6" + attribute \src "libresoc.v:43793.3-43821.6" wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48062.3-48090.6" + attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47975.3-48003.6" + attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $0\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48004.3-48032.6" + attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47946.3-47974.6" + attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48091.3-48119.6" + attribute \src "libresoc.v:47887.3-47915.6" wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48178.3-48206.6" + attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48033.3-48061.6" + attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48149.3-48177.6" + attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48120.3-48148.6" + attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45633.3-45661.6" + attribute \src "libresoc.v:45429.3-45457.6" wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45604.3-45632.6" + attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45398.3-45426.6" + attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45427.3-45456.6" + attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45427.3-45456.6" + attribute \src "libresoc.v:45223.3-45252.6" wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45720.3-45748.6" + attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45369.3-45397.6" + attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45546.3-45574.6" + attribute \src "libresoc.v:45342.3-45370.6" wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45575.3-45603.6" + attribute \src "libresoc.v:45371.3-45399.6" wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45691.3-45719.6" + attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45516.3-45545.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45516.3-45545.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45486.3-45515.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45486.3-45515.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45662.3-45690.6" + attribute \src "libresoc.v:45458.3-45486.6" wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45457.3-45485.6" + attribute \src "libresoc.v:45253.3-45281.6" wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:46025.3-46034.6" + attribute \src "libresoc.v:45821.3-45830.6" wire width 64 $0\fus_src1_i$62[63:0]$2537 - attribute \src "libresoc.v:46044.3-46053.6" + attribute \src "libresoc.v:45840.3-45849.6" wire width 64 $0\fus_src1_i$63[63:0]$2543 - attribute \src "libresoc.v:46063.3-46072.6" + attribute \src "libresoc.v:45859.3-45868.6" wire width 64 $0\fus_src1_i$64[63:0]$2549 - attribute \src "libresoc.v:46082.3-46091.6" + attribute \src "libresoc.v:45878.3-45887.6" wire width 64 $0\fus_src1_i$67[63:0]$2555 - attribute \src "libresoc.v:46101.3-46110.6" + attribute \src "libresoc.v:45897.3-45906.6" wire width 64 $0\fus_src1_i$68[63:0]$2561 - attribute \src "libresoc.v:46120.3-46129.6" + attribute \src "libresoc.v:45916.3-45925.6" wire width 64 $0\fus_src1_i$69[63:0]$2567 - attribute \src "libresoc.v:46139.3-46148.6" + attribute \src "libresoc.v:45935.3-45944.6" wire width 64 $0\fus_src1_i$70[63:0]$2573 - attribute \src "libresoc.v:46158.3-46167.6" + attribute \src "libresoc.v:45954.3-45963.6" wire width 64 $0\fus_src1_i$71[63:0]$2579 - attribute \src "libresoc.v:46584.3-46593.6" + attribute \src "libresoc.v:46380.3-46389.6" wire width 64 $0\fus_src1_i$86[63:0]$2676 - attribute \src "libresoc.v:46006.3-46015.6" + attribute \src "libresoc.v:45802.3-45811.6" wire width 64 $0\fus_src1_i[63:0] - attribute \src "libresoc.v:45835.3-45844.6" + attribute \src "libresoc.v:45631.3-45640.6" wire width 64 $0\fus_src2_i$42[63:0]$2481 - attribute \src "libresoc.v:45854.3-45863.6" + attribute \src "libresoc.v:45650.3-45659.6" wire width 64 $0\fus_src2_i$45[63:0]$2487 - attribute \src "libresoc.v:45873.3-45882.6" + attribute \src "libresoc.v:45669.3-45678.6" wire width 64 $0\fus_src2_i$48[63:0]$2493 - attribute \src "libresoc.v:45892.3-45901.6" + attribute \src "libresoc.v:45688.3-45697.6" wire width 64 $0\fus_src2_i$51[63:0]$2499 - attribute \src "libresoc.v:45911.3-45920.6" + attribute \src "libresoc.v:45707.3-45716.6" wire width 64 $0\fus_src2_i$54[63:0]$2505 - attribute \src "libresoc.v:45930.3-45939.6" + attribute \src "libresoc.v:45726.3-45735.6" wire width 64 $0\fus_src2_i$57[63:0]$2511 - attribute \src "libresoc.v:45949.3-45958.6" + attribute \src "libresoc.v:45745.3-45754.6" wire width 64 $0\fus_src2_i$60[63:0]$2517 - attribute \src "libresoc.v:46691.3-46700.6" + attribute \src "libresoc.v:46487.3-46496.6" wire width 64 $0\fus_src2_i$89[63:0]$2700 - attribute \src "libresoc.v:46758.3-46767.6" + attribute \src "libresoc.v:46554.3-46563.6" wire width 64 $0\fus_src2_i$91[63:0]$2713 - attribute \src "libresoc.v:45816.3-45825.6" + attribute \src "libresoc.v:45612.3-45621.6" wire width 64 $0\fus_src2_i[63:0] - attribute \src "libresoc.v:45987.3-45996.6" + attribute \src "libresoc.v:45783.3-45792.6" wire width 64 $0\fus_src3_i$61[63:0]$2527 - attribute \src "libresoc.v:46177.3-46186.6" + attribute \src "libresoc.v:45973.3-45982.6" wire $0\fus_src3_i$72[0:0]$2585 - attribute \src "libresoc.v:46196.3-46205.6" + attribute \src "libresoc.v:45992.3-46001.6" wire $0\fus_src3_i$73[0:0]$2591 - attribute \src "libresoc.v:46234.3-46243.6" + attribute \src "libresoc.v:46030.3-46039.6" wire $0\fus_src3_i$74[0:0]$2601 - attribute \src "libresoc.v:46253.3-46262.6" + attribute \src "libresoc.v:46049.3-46058.6" wire $0\fus_src3_i$75[0:0]$2607 - attribute \src "libresoc.v:46367.3-46376.6" + attribute \src "libresoc.v:46163.3-46172.6" wire width 32 $0\fus_src3_i$79[31:0]$2639 - attribute \src "libresoc.v:46405.3-46414.6" + attribute \src "libresoc.v:46201.3-46210.6" wire width 4 $0\fus_src3_i$83[3:0]$2651 - attribute \src "libresoc.v:46624.3-46633.6" + attribute \src "libresoc.v:46420.3-46429.6" wire width 64 $0\fus_src3_i$87[63:0]$2687 - attribute \src "libresoc.v:46643.3-46652.6" + attribute \src "libresoc.v:46439.3-46448.6" wire width 64 $0\fus_src3_i$88[63:0]$2693 - attribute \src "libresoc.v:45968.3-45977.6" + attribute \src "libresoc.v:45764.3-45773.6" wire width 64 $0\fus_src3_i[63:0] - attribute \src "libresoc.v:46272.3-46281.6" + attribute \src "libresoc.v:46068.3-46077.6" wire $0\fus_src4_i$76[0:0]$2613 - attribute \src "libresoc.v:46291.3-46300.6" + attribute \src "libresoc.v:46087.3-46096.6" wire width 2 $0\fus_src4_i$77[1:0]$2619 - attribute \src "libresoc.v:46386.3-46395.6" + attribute \src "libresoc.v:46182.3-46191.6" wire width 4 $0\fus_src4_i$80[3:0]$2645 - attribute \src "libresoc.v:46710.3-46719.6" + attribute \src "libresoc.v:46506.3-46515.6" wire width 64 $0\fus_src4_i$90[63:0]$2706 - attribute \src "libresoc.v:46215.3-46224.6" + attribute \src "libresoc.v:46011.3-46020.6" wire $0\fus_src4_i[0:0] - attribute \src "libresoc.v:46348.3-46357.6" + attribute \src "libresoc.v:46144.3-46153.6" wire width 2 $0\fus_src5_i$78[1:0]$2633 - attribute \src "libresoc.v:46455.3-46464.6" + attribute \src "libresoc.v:46251.3-46260.6" wire width 4 $0\fus_src5_i$84[3:0]$2663 - attribute \src "libresoc.v:46329.3-46338.6" + attribute \src "libresoc.v:46125.3-46134.6" wire width 2 $0\fus_src5_i[1:0] - attribute \src "libresoc.v:46474.3-46483.6" + attribute \src "libresoc.v:46270.3-46279.6" wire width 4 $0\fus_src6_i$85[3:0]$2669 - attribute \src "libresoc.v:46310.3-46319.6" + attribute \src "libresoc.v:46106.3-46115.6" wire width 2 $0\fus_src6_i[1:0] attribute \src "libresoc.v:36262.7-36262.20" wire $0\initial[0:0] - attribute \src "libresoc.v:46816.3-46824.6" + attribute \src "libresoc.v:46612.3-46620.6" wire $0\wr_pick_dly$1008$next[0:0]$2723 - attribute \src "libresoc.v:42904.3-42905.51" + attribute \src "libresoc.v:42700.3-42701.51" wire $0\wr_pick_dly$1008[0:0]$2307 - attribute \src "libresoc.v:41734.7-41734.32" + attribute \src "libresoc.v:41530.7-41530.32" wire $0\wr_pick_dly$1008[0:0]$2945 - attribute \src "libresoc.v:46855.3-46863.6" + attribute \src "libresoc.v:46651.3-46659.6" wire $0\wr_pick_dly$1029$next[0:0]$2727 - attribute \src "libresoc.v:42902.3-42903.51" + attribute \src "libresoc.v:42698.3-42699.51" wire $0\wr_pick_dly$1029[0:0]$2305 - attribute \src "libresoc.v:41738.7-41738.32" + attribute \src "libresoc.v:41534.7-41534.32" wire $0\wr_pick_dly$1029[0:0]$2947 - attribute \src "libresoc.v:46864.3-46872.6" + attribute \src "libresoc.v:46660.3-46668.6" wire $0\wr_pick_dly$1047$next[0:0]$2730 - attribute \src "libresoc.v:42900.3-42901.51" + attribute \src "libresoc.v:42696.3-42697.51" wire $0\wr_pick_dly$1047[0:0]$2303 - attribute \src "libresoc.v:41742.7-41742.32" + attribute \src "libresoc.v:41538.7-41538.32" wire $0\wr_pick_dly$1047[0:0]$2949 - attribute \src "libresoc.v:46873.3-46881.6" + attribute \src "libresoc.v:46669.3-46677.6" wire $0\wr_pick_dly$1069$next[0:0]$2733 - attribute \src "libresoc.v:42898.3-42899.51" + attribute \src "libresoc.v:42694.3-42695.51" wire $0\wr_pick_dly$1069[0:0]$2301 - attribute \src "libresoc.v:41746.7-41746.32" + attribute \src "libresoc.v:41542.7-41542.32" wire $0\wr_pick_dly$1069[0:0]$2951 - attribute \src "libresoc.v:46912.3-46920.6" + attribute \src "libresoc.v:46708.3-46716.6" wire $0\wr_pick_dly$1089$next[0:0]$2737 - attribute \src "libresoc.v:42896.3-42897.51" + attribute \src "libresoc.v:42692.3-42693.51" wire $0\wr_pick_dly$1089[0:0]$2299 - attribute \src "libresoc.v:41750.7-41750.32" + attribute \src "libresoc.v:41546.7-41546.32" wire $0\wr_pick_dly$1089[0:0]$2953 - attribute \src "libresoc.v:46921.3-46929.6" + attribute \src "libresoc.v:46717.3-46725.6" wire $0\wr_pick_dly$1109$next[0:0]$2740 - attribute \src "libresoc.v:42894.3-42895.51" + attribute \src "libresoc.v:42690.3-42691.51" wire $0\wr_pick_dly$1109[0:0]$2297 - attribute \src "libresoc.v:41754.7-41754.32" + attribute \src "libresoc.v:41550.7-41550.32" wire $0\wr_pick_dly$1109[0:0]$2955 - attribute \src "libresoc.v:46930.3-46938.6" + attribute \src "libresoc.v:46726.3-46734.6" wire $0\wr_pick_dly$1128$next[0:0]$2743 - attribute \src "libresoc.v:42892.3-42893.51" + attribute \src "libresoc.v:42688.3-42689.51" wire $0\wr_pick_dly$1128[0:0]$2295 - attribute \src "libresoc.v:41758.7-41758.32" + attribute \src "libresoc.v:41554.7-41554.32" wire $0\wr_pick_dly$1128[0:0]$2957 - attribute \src "libresoc.v:46968.3-46976.6" + attribute \src "libresoc.v:46764.3-46772.6" wire $0\wr_pick_dly$1146$next[0:0]$2747 - attribute \src "libresoc.v:42890.3-42891.51" + attribute \src "libresoc.v:42686.3-42687.51" wire $0\wr_pick_dly$1146[0:0]$2293 - attribute \src "libresoc.v:41762.7-41762.32" + attribute \src "libresoc.v:41558.7-41558.32" wire $0\wr_pick_dly$1146[0:0]$2959 - attribute \src "libresoc.v:47006.3-47014.6" + attribute \src "libresoc.v:46802.3-46810.6" wire $0\wr_pick_dly$1220$next[0:0]$2751 - attribute \src "libresoc.v:42888.3-42889.51" + attribute \src "libresoc.v:42684.3-42685.51" wire $0\wr_pick_dly$1220[0:0]$2291 - attribute \src "libresoc.v:41766.7-41766.32" + attribute \src "libresoc.v:41562.7-41562.32" wire $0\wr_pick_dly$1220[0:0]$2961 - attribute \src "libresoc.v:47044.3-47052.6" + attribute \src "libresoc.v:46840.3-46848.6" wire $0\wr_pick_dly$1248$next[0:0]$2755 - attribute \src "libresoc.v:42886.3-42887.51" + attribute \src "libresoc.v:42682.3-42683.51" wire $0\wr_pick_dly$1248[0:0]$2289 - attribute \src "libresoc.v:41770.7-41770.32" + attribute \src "libresoc.v:41566.7-41566.32" wire $0\wr_pick_dly$1248[0:0]$2963 - attribute \src "libresoc.v:47082.3-47090.6" + attribute \src "libresoc.v:46878.3-46886.6" wire $0\wr_pick_dly$1268$next[0:0]$2759 - attribute \src "libresoc.v:42884.3-42885.51" + attribute \src "libresoc.v:42680.3-42681.51" wire $0\wr_pick_dly$1268[0:0]$2287 - attribute \src "libresoc.v:41774.7-41774.32" + attribute \src "libresoc.v:41570.7-41570.32" wire $0\wr_pick_dly$1268[0:0]$2965 - attribute \src "libresoc.v:47091.3-47099.6" + attribute \src "libresoc.v:46887.3-46895.6" wire $0\wr_pick_dly$1288$next[0:0]$2762 - attribute \src "libresoc.v:42882.3-42883.51" + attribute \src "libresoc.v:42678.3-42679.51" wire $0\wr_pick_dly$1288[0:0]$2285 - attribute \src "libresoc.v:41778.7-41778.32" + attribute \src "libresoc.v:41574.7-41574.32" wire $0\wr_pick_dly$1288[0:0]$2967 - attribute \src "libresoc.v:47129.3-47137.6" + attribute \src "libresoc.v:46925.3-46933.6" wire $0\wr_pick_dly$1308$next[0:0]$2766 - attribute \src "libresoc.v:42880.3-42881.51" + attribute \src "libresoc.v:42676.3-42677.51" wire $0\wr_pick_dly$1308[0:0]$2283 - attribute \src "libresoc.v:41782.7-41782.32" + attribute \src "libresoc.v:41578.7-41578.32" wire $0\wr_pick_dly$1308[0:0]$2969 - attribute \src "libresoc.v:47138.3-47146.6" + attribute \src "libresoc.v:46934.3-46942.6" wire $0\wr_pick_dly$1328$next[0:0]$2769 - attribute \src "libresoc.v:42878.3-42879.51" + attribute \src "libresoc.v:42674.3-42675.51" wire $0\wr_pick_dly$1328[0:0]$2281 - attribute \src "libresoc.v:41786.7-41786.32" + attribute \src "libresoc.v:41582.7-41582.32" wire $0\wr_pick_dly$1328[0:0]$2971 - attribute \src "libresoc.v:47176.3-47184.6" + attribute \src "libresoc.v:46972.3-46980.6" wire $0\wr_pick_dly$1348$next[0:0]$2773 - attribute \src "libresoc.v:42876.3-42877.51" + attribute \src "libresoc.v:42672.3-42673.51" wire $0\wr_pick_dly$1348[0:0]$2279 - attribute \src "libresoc.v:41790.7-41790.32" + attribute \src "libresoc.v:41586.7-41586.32" wire $0\wr_pick_dly$1348[0:0]$2973 - attribute \src "libresoc.v:47214.3-47222.6" + attribute \src "libresoc.v:47010.3-47018.6" wire $0\wr_pick_dly$1395$next[0:0]$2777 - attribute \src "libresoc.v:42874.3-42875.51" + attribute \src "libresoc.v:42670.3-42671.51" wire $0\wr_pick_dly$1395[0:0]$2277 - attribute \src "libresoc.v:41794.7-41794.32" + attribute \src "libresoc.v:41590.7-41590.32" wire $0\wr_pick_dly$1395[0:0]$2975 - attribute \src "libresoc.v:47252.3-47260.6" + attribute \src "libresoc.v:47048.3-47056.6" wire $0\wr_pick_dly$1411$next[0:0]$2781 - attribute \src "libresoc.v:42872.3-42873.51" + attribute \src "libresoc.v:42668.3-42669.51" wire $0\wr_pick_dly$1411[0:0]$2275 - attribute \src "libresoc.v:41798.7-41798.32" + attribute \src "libresoc.v:41594.7-41594.32" wire $0\wr_pick_dly$1411[0:0]$2977 - attribute \src "libresoc.v:47261.3-47269.6" + attribute \src "libresoc.v:47057.3-47065.6" wire $0\wr_pick_dly$1427$next[0:0]$2784 - attribute \src "libresoc.v:42870.3-42871.51" + attribute \src "libresoc.v:42666.3-42667.51" wire $0\wr_pick_dly$1427[0:0]$2273 - attribute \src "libresoc.v:41802.7-41802.32" + attribute \src "libresoc.v:41598.7-41598.32" wire $0\wr_pick_dly$1427[0:0]$2979 - attribute \src "libresoc.v:47299.3-47307.6" + attribute \src "libresoc.v:47095.3-47103.6" wire $0\wr_pick_dly$1461$next[0:0]$2788 - attribute \src "libresoc.v:42868.3-42869.51" + attribute \src "libresoc.v:42664.3-42665.51" wire $0\wr_pick_dly$1461[0:0]$2271 - attribute \src "libresoc.v:41806.7-41806.32" + attribute \src "libresoc.v:41602.7-41602.32" wire $0\wr_pick_dly$1461[0:0]$2981 - attribute \src "libresoc.v:47337.3-47345.6" + attribute \src "libresoc.v:47133.3-47141.6" wire $0\wr_pick_dly$1477$next[0:0]$2792 - attribute \src "libresoc.v:42866.3-42867.51" + attribute \src "libresoc.v:42662.3-42663.51" wire $0\wr_pick_dly$1477[0:0]$2269 - attribute \src "libresoc.v:41810.7-41810.32" + attribute \src "libresoc.v:41606.7-41606.32" wire $0\wr_pick_dly$1477[0:0]$2983 - attribute \src "libresoc.v:47346.3-47354.6" + attribute \src "libresoc.v:47142.3-47150.6" wire $0\wr_pick_dly$1493$next[0:0]$2795 - attribute \src "libresoc.v:42864.3-42865.51" + attribute \src "libresoc.v:42660.3-42661.51" wire $0\wr_pick_dly$1493[0:0]$2267 - attribute \src "libresoc.v:41814.7-41814.32" + attribute \src "libresoc.v:41610.7-41610.32" wire $0\wr_pick_dly$1493[0:0]$2985 - attribute \src "libresoc.v:47384.3-47392.6" + attribute \src "libresoc.v:47180.3-47188.6" wire $0\wr_pick_dly$1509$next[0:0]$2799 - attribute \src "libresoc.v:42862.3-42863.51" + attribute \src "libresoc.v:42658.3-42659.51" wire $0\wr_pick_dly$1509[0:0]$2265 - attribute \src "libresoc.v:41818.7-41818.32" + attribute \src "libresoc.v:41614.7-41614.32" wire $0\wr_pick_dly$1509[0:0]$2987 - attribute \src "libresoc.v:47422.3-47430.6" + attribute \src "libresoc.v:47218.3-47226.6" wire $0\wr_pick_dly$1545$next[0:0]$2803 - attribute \src "libresoc.v:42860.3-42861.51" + attribute \src "libresoc.v:42656.3-42657.51" wire $0\wr_pick_dly$1545[0:0]$2263 - attribute \src "libresoc.v:41822.7-41822.32" + attribute \src "libresoc.v:41618.7-41618.32" wire $0\wr_pick_dly$1545[0:0]$2989 - attribute \src "libresoc.v:47431.3-47439.6" + attribute \src "libresoc.v:47227.3-47235.6" wire $0\wr_pick_dly$1561$next[0:0]$2806 - attribute \src "libresoc.v:42858.3-42859.51" + attribute \src "libresoc.v:42654.3-42655.51" wire $0\wr_pick_dly$1561[0:0]$2261 - attribute \src "libresoc.v:41826.7-41826.32" + attribute \src "libresoc.v:41622.7-41622.32" wire $0\wr_pick_dly$1561[0:0]$2991 - attribute \src "libresoc.v:47469.3-47477.6" + attribute \src "libresoc.v:47265.3-47273.6" wire $0\wr_pick_dly$1577$next[0:0]$2810 - attribute \src "libresoc.v:42856.3-42857.51" + attribute \src "libresoc.v:42652.3-42653.51" wire $0\wr_pick_dly$1577[0:0]$2259 - attribute \src "libresoc.v:41830.7-41830.32" + attribute \src "libresoc.v:41626.7-41626.32" wire $0\wr_pick_dly$1577[0:0]$2993 - attribute \src "libresoc.v:47507.3-47515.6" + attribute \src "libresoc.v:47303.3-47311.6" wire $0\wr_pick_dly$1593$next[0:0]$2814 - attribute \src "libresoc.v:42854.3-42855.51" + attribute \src "libresoc.v:42650.3-42651.51" wire $0\wr_pick_dly$1593[0:0]$2257 - attribute \src "libresoc.v:41834.7-41834.32" + attribute \src "libresoc.v:41630.7-41630.32" wire $0\wr_pick_dly$1593[0:0]$2995 - attribute \src "libresoc.v:47516.3-47524.6" + attribute \src "libresoc.v:47312.3-47320.6" wire $0\wr_pick_dly$1635$next[0:0]$2817 - attribute \src "libresoc.v:42852.3-42853.51" + attribute \src "libresoc.v:42648.3-42649.51" wire $0\wr_pick_dly$1635[0:0]$2255 - attribute \src "libresoc.v:41838.7-41838.32" + attribute \src "libresoc.v:41634.7-41634.32" wire $0\wr_pick_dly$1635[0:0]$2997 - attribute \src "libresoc.v:47554.3-47562.6" + attribute \src "libresoc.v:47350.3-47358.6" wire $0\wr_pick_dly$1654$next[0:0]$2821 - attribute \src "libresoc.v:42850.3-42851.51" + attribute \src "libresoc.v:42646.3-42647.51" wire $0\wr_pick_dly$1654[0:0]$2253 - attribute \src "libresoc.v:41842.7-41842.32" + attribute \src "libresoc.v:41638.7-41638.32" wire $0\wr_pick_dly$1654[0:0]$2999 - attribute \src "libresoc.v:47592.3-47600.6" + attribute \src "libresoc.v:47388.3-47396.6" wire $0\wr_pick_dly$1670$next[0:0]$2829 - attribute \src "libresoc.v:42848.3-42849.51" + attribute \src "libresoc.v:42644.3-42645.51" wire $0\wr_pick_dly$1670[0:0]$2251 - attribute \src "libresoc.v:41846.7-41846.32" + attribute \src "libresoc.v:41642.7-41642.32" wire $0\wr_pick_dly$1670[0:0]$3001 - attribute \src "libresoc.v:47601.3-47609.6" + attribute \src "libresoc.v:47397.3-47405.6" wire $0\wr_pick_dly$1686$next[0:0]$2832 - attribute \src "libresoc.v:42846.3-42847.51" + attribute \src "libresoc.v:42642.3-42643.51" wire $0\wr_pick_dly$1686[0:0]$2249 - attribute \src "libresoc.v:41850.7-41850.32" + attribute \src "libresoc.v:41646.7-41646.32" wire $0\wr_pick_dly$1686[0:0]$3003 - attribute \src "libresoc.v:47639.3-47647.6" + attribute \src "libresoc.v:47435.3-47443.6" wire $0\wr_pick_dly$1702$next[0:0]$2840 - attribute \src "libresoc.v:42844.3-42845.51" + attribute \src "libresoc.v:42640.3-42641.51" wire $0\wr_pick_dly$1702[0:0]$2247 - attribute \src "libresoc.v:41854.7-41854.32" + attribute \src "libresoc.v:41650.7-41650.32" wire $0\wr_pick_dly$1702[0:0]$3005 - attribute \src "libresoc.v:47677.3-47685.6" + attribute \src "libresoc.v:47473.3-47481.6" wire $0\wr_pick_dly$1746$next[0:0]$2844 - attribute \src "libresoc.v:42842.3-42843.51" + attribute \src "libresoc.v:42638.3-42639.51" wire $0\wr_pick_dly$1746[0:0]$2245 - attribute \src "libresoc.v:41858.7-41858.32" + attribute \src "libresoc.v:41654.7-41654.32" wire $0\wr_pick_dly$1746[0:0]$3007 - attribute \src "libresoc.v:47715.3-47723.6" + attribute \src "libresoc.v:47511.3-47519.6" wire $0\wr_pick_dly$1762$next[0:0]$2848 - attribute \src "libresoc.v:42840.3-42841.51" + attribute \src "libresoc.v:42636.3-42637.51" wire $0\wr_pick_dly$1762[0:0]$2243 - attribute \src "libresoc.v:41862.7-41862.32" + attribute \src "libresoc.v:41658.7-41658.32" wire $0\wr_pick_dly$1762[0:0]$3009 - attribute \src "libresoc.v:47724.3-47732.6" + attribute \src "libresoc.v:47520.3-47528.6" wire $0\wr_pick_dly$1786$next[0:0]$2851 - attribute \src "libresoc.v:42838.3-42839.51" + attribute \src "libresoc.v:42634.3-42635.51" wire $0\wr_pick_dly$1786[0:0]$2241 - attribute \src "libresoc.v:41866.7-41866.32" + attribute \src "libresoc.v:41662.7-41662.32" wire $0\wr_pick_dly$1786[0:0]$3011 - attribute \src "libresoc.v:47762.3-47770.6" + attribute \src "libresoc.v:47558.3-47566.6" wire $0\wr_pick_dly$1806$next[0:0]$2855 - attribute \src "libresoc.v:42836.3-42837.51" + attribute \src "libresoc.v:42632.3-42633.51" wire $0\wr_pick_dly$1806[0:0]$2239 - attribute \src "libresoc.v:41870.7-41870.32" + attribute \src "libresoc.v:41666.7-41666.32" wire $0\wr_pick_dly$1806[0:0]$3013 - attribute \src "libresoc.v:46807.3-46815.6" + attribute \src "libresoc.v:46603.3-46611.6" wire $0\wr_pick_dly$989$next[0:0]$2720 - attribute \src "libresoc.v:42906.3-42907.49" + attribute \src "libresoc.v:42702.3-42703.49" wire $0\wr_pick_dly$989[0:0]$2309 - attribute \src "libresoc.v:41874.7-41874.31" + attribute \src "libresoc.v:41670.7-41670.31" wire $0\wr_pick_dly$989[0:0]$3015 - attribute \src "libresoc.v:46798.3-46806.6" + attribute \src "libresoc.v:46594.3-46602.6" wire $0\wr_pick_dly$next[0:0]$2717 - attribute \src "libresoc.v:42908.3-42909.39" + attribute \src "libresoc.v:42704.3-42705.39" wire $0\wr_pick_dly[0:0] - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $10\corebusy_o[0:0] - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $11\corebusy_o[0:0] - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $12\corebusy_o[0:0] - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $13\corebusy_o[0:0] - attribute \src "libresoc.v:46594.3-46614.6" + attribute \src "libresoc.v:46390.3-46410.6" wire $1\core_terminate_o$next[0:0]$2680 - attribute \src "libresoc.v:38307.7-38307.30" + attribute \src "libresoc.v:38103.7-38103.30" wire $1\core_terminate_o[0:0] - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $1\corebusy_o[0:0] - attribute \src "libresoc.v:46424.3-46454.6" + attribute \src "libresoc.v:46220.3-46250.6" wire width 2 $1\counter$next[1:0]$2658 - attribute \src "libresoc.v:38320.13-38320.27" + attribute \src "libresoc.v:38116.13-38116.27" wire width 2 $1\counter[1:0] - attribute \src "libresoc.v:46396.3-46404.6" + attribute \src "libresoc.v:46192.3-46200.6" wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 - attribute \src "libresoc.v:39487.7-39487.34" + attribute \src "libresoc.v:39283.7-39283.34" wire $1\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:46377.3-46385.6" + attribute \src "libresoc.v:46173.3-46181.6" wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 - attribute \src "libresoc.v:39491.7-39491.30" + attribute \src "libresoc.v:39287.7-39287.30" wire $1\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46415.3-46423.6" + attribute \src "libresoc.v:46211.3-46219.6" wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 - attribute \src "libresoc.v:39495.7-39495.30" + attribute \src "libresoc.v:39291.7-39291.30" wire $1\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46465.3-46473.6" + attribute \src "libresoc.v:46261.3-46269.6" wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 - attribute \src "libresoc.v:39499.7-39499.30" + attribute \src "libresoc.v:39295.7-39295.30" wire $1\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:46358.3-46366.6" + attribute \src "libresoc.v:46154.3-46162.6" wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 - attribute \src "libresoc.v:39503.7-39503.33" + attribute \src "libresoc.v:39299.7-39299.33" wire $1\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46575.3-46583.6" + attribute \src "libresoc.v:46371.3-46379.6" wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 - attribute \src "libresoc.v:39507.7-39507.37" + attribute \src "libresoc.v:39303.7-39303.37" wire $1\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46682.3-46690.6" + attribute \src "libresoc.v:46478.3-46486.6" wire $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 - attribute \src "libresoc.v:39511.7-39511.37" + attribute \src "libresoc.v:39307.7-39307.37" wire $1\dp_FAST_fast1_branch0_3[0:0] - attribute \src "libresoc.v:46634.3-46642.6" + attribute \src "libresoc.v:46430.3-46438.6" wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 - attribute \src "libresoc.v:39515.7-39515.34" + attribute \src "libresoc.v:39311.7-39311.34" wire $1\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46615.3-46623.6" + attribute \src "libresoc.v:46411.3-46419.6" wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 - attribute \src "libresoc.v:39519.7-39519.35" + attribute \src "libresoc.v:39315.7-39315.35" wire $1\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46701.3-46709.6" + attribute \src "libresoc.v:46497.3-46505.6" wire $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 - attribute \src "libresoc.v:39523.7-39523.35" + attribute \src "libresoc.v:39319.7-39319.35" wire $1\dp_FAST_fast1_trap0_4[0:0] - attribute \src "libresoc.v:45807.3-45815.6" + attribute \src "libresoc.v:45603.3-45611.6" wire $1\dp_INT_rabc_alu0_0$next[0:0]$2475 - attribute \src "libresoc.v:39527.7-39527.32" + attribute \src "libresoc.v:39323.7-39323.32" wire $1\dp_INT_rabc_alu0_0[0:0] - attribute \src "libresoc.v:45997.3-46005.6" + attribute \src "libresoc.v:45793.3-45801.6" wire $1\dp_INT_rabc_alu0_10$next[0:0]$2531 - attribute \src "libresoc.v:39531.7-39531.33" + attribute \src "libresoc.v:39327.7-39327.33" wire $1\dp_INT_rabc_alu0_10[0:0] - attribute \src "libresoc.v:45826.3-45834.6" + attribute \src "libresoc.v:45622.3-45630.6" wire $1\dp_INT_rabc_cr0_1$next[0:0]$2479 - attribute \src "libresoc.v:46016.3-46024.6" + attribute \src "libresoc.v:45812.3-45820.6" wire $1\dp_INT_rabc_cr0_11$next[0:0]$2535 - attribute \src "libresoc.v:39539.7-39539.32" + attribute \src "libresoc.v:39335.7-39335.32" wire $1\dp_INT_rabc_cr0_11[0:0] - attribute \src "libresoc.v:39535.7-39535.31" + attribute \src "libresoc.v:39331.7-39331.31" wire $1\dp_INT_rabc_cr0_1[0:0] - attribute \src "libresoc.v:46092.3-46100.6" + attribute \src "libresoc.v:45888.3-45896.6" wire $1\dp_INT_rabc_div0_15$next[0:0]$2559 - attribute \src "libresoc.v:39543.7-39543.33" + attribute \src "libresoc.v:39339.7-39339.33" wire $1\dp_INT_rabc_div0_15[0:0] - attribute \src "libresoc.v:45883.3-45891.6" + attribute \src "libresoc.v:45679.3-45687.6" wire $1\dp_INT_rabc_div0_4$next[0:0]$2497 - attribute \src "libresoc.v:39547.7-39547.32" + attribute \src "libresoc.v:39343.7-39343.32" wire $1\dp_INT_rabc_div0_4[0:0] - attribute \src "libresoc.v:46149.3-46157.6" + attribute \src "libresoc.v:45945.3-45953.6" wire $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 - attribute \src "libresoc.v:39551.7-39551.34" + attribute \src "libresoc.v:39347.7-39347.34" wire $1\dp_INT_rabc_ldst0_18[0:0] - attribute \src "libresoc.v:45940.3-45948.6" + attribute \src "libresoc.v:45736.3-45744.6" wire $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 - attribute \src "libresoc.v:39555.7-39555.33" + attribute \src "libresoc.v:39351.7-39351.33" wire $1\dp_INT_rabc_ldst0_7[0:0] - attribute \src "libresoc.v:45978.3-45986.6" + attribute \src "libresoc.v:45774.3-45782.6" wire $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 - attribute \src "libresoc.v:39559.7-39559.33" + attribute \src "libresoc.v:39355.7-39355.33" wire $1\dp_INT_rabc_ldst0_9[0:0] - attribute \src "libresoc.v:46054.3-46062.6" + attribute \src "libresoc.v:45850.3-45858.6" wire $1\dp_INT_rabc_logical0_13$next[0:0]$2547 - attribute \src "libresoc.v:39563.7-39563.37" + attribute \src "libresoc.v:39359.7-39359.37" wire $1\dp_INT_rabc_logical0_13[0:0] - attribute \src "libresoc.v:45864.3-45872.6" + attribute \src "libresoc.v:45660.3-45668.6" wire $1\dp_INT_rabc_logical0_3$next[0:0]$2491 - attribute \src "libresoc.v:39567.7-39567.36" + attribute \src "libresoc.v:39363.7-39363.36" wire $1\dp_INT_rabc_logical0_3[0:0] - attribute \src "libresoc.v:46111.3-46119.6" + attribute \src "libresoc.v:45907.3-45915.6" wire $1\dp_INT_rabc_mul0_16$next[0:0]$2565 - attribute \src "libresoc.v:39571.7-39571.33" + attribute \src "libresoc.v:39367.7-39367.33" wire $1\dp_INT_rabc_mul0_16[0:0] - attribute \src "libresoc.v:45902.3-45910.6" + attribute \src "libresoc.v:45698.3-45706.6" wire $1\dp_INT_rabc_mul0_5$next[0:0]$2503 - attribute \src "libresoc.v:39575.7-39575.32" + attribute \src "libresoc.v:39371.7-39371.32" wire $1\dp_INT_rabc_mul0_5[0:0] - attribute \src "libresoc.v:46130.3-46138.6" + attribute \src "libresoc.v:45926.3-45934.6" wire $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 - attribute \src "libresoc.v:39579.7-39579.38" + attribute \src "libresoc.v:39375.7-39375.38" wire $1\dp_INT_rabc_shiftrot0_17[0:0] - attribute \src "libresoc.v:45921.3-45929.6" + attribute \src "libresoc.v:45717.3-45725.6" wire $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 - attribute \src "libresoc.v:39583.7-39583.37" + attribute \src "libresoc.v:39379.7-39379.37" wire $1\dp_INT_rabc_shiftrot0_6[0:0] - attribute \src "libresoc.v:45959.3-45967.6" + attribute \src "libresoc.v:45755.3-45763.6" wire $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 - attribute \src "libresoc.v:39587.7-39587.37" + attribute \src "libresoc.v:39383.7-39383.37" wire $1\dp_INT_rabc_shiftrot0_8[0:0] - attribute \src "libresoc.v:46073.3-46081.6" + attribute \src "libresoc.v:45869.3-45877.6" wire $1\dp_INT_rabc_spr0_14$next[0:0]$2553 - attribute \src "libresoc.v:39591.7-39591.33" + attribute \src "libresoc.v:39387.7-39387.33" wire $1\dp_INT_rabc_spr0_14[0:0] - attribute \src "libresoc.v:46035.3-46043.6" + attribute \src "libresoc.v:45831.3-45839.6" wire $1\dp_INT_rabc_trap0_12$next[0:0]$2541 - attribute \src "libresoc.v:39595.7-39595.34" + attribute \src "libresoc.v:39391.7-39391.34" wire $1\dp_INT_rabc_trap0_12[0:0] - attribute \src "libresoc.v:45845.3-45853.6" + attribute \src "libresoc.v:45641.3-45649.6" wire $1\dp_INT_rabc_trap0_2$next[0:0]$2485 - attribute \src "libresoc.v:39599.7-39599.33" + attribute \src "libresoc.v:39395.7-39395.33" wire $1\dp_INT_rabc_trap0_2[0:0] - attribute \src "libresoc.v:46749.3-46757.6" + attribute \src "libresoc.v:46545.3-46553.6" wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 - attribute \src "libresoc.v:39603.7-39603.32" + attribute \src "libresoc.v:39399.7-39399.32" wire $1\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:46282.3-46290.6" + attribute \src "libresoc.v:46078.3-46086.6" wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 - attribute \src "libresoc.v:39607.7-39607.34" + attribute \src "libresoc.v:39403.7-39403.34" wire $1\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:46320.3-46328.6" + attribute \src "libresoc.v:46116.3-46124.6" wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 - attribute \src "libresoc.v:39611.7-39611.39" + attribute \src "libresoc.v:39407.7-39407.39" wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:46301.3-46309.6" + attribute \src "libresoc.v:46097.3-46105.6" wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 - attribute \src "libresoc.v:39615.7-39615.34" + attribute \src "libresoc.v:39411.7-39411.34" wire $1\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:46339.3-46347.6" + attribute \src "libresoc.v:46135.3-46143.6" wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 - attribute \src "libresoc.v:39619.7-39619.34" + attribute \src "libresoc.v:39415.7-39415.34" wire $1\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:46168.3-46176.6" + attribute \src "libresoc.v:45964.3-45972.6" wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 - attribute \src "libresoc.v:39623.7-39623.34" + attribute \src "libresoc.v:39419.7-39419.34" wire $1\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:46225.3-46233.6" + attribute \src "libresoc.v:46021.3-46029.6" wire $1\dp_XER_xer_so_div0_3$next[0:0]$2599 - attribute \src "libresoc.v:39627.7-39627.34" + attribute \src "libresoc.v:39423.7-39423.34" wire $1\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:46187.3-46195.6" + attribute \src "libresoc.v:45983.3-45991.6" wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 - attribute \src "libresoc.v:39631.7-39631.38" + attribute \src "libresoc.v:39427.7-39427.38" wire $1\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:46244.3-46252.6" + attribute \src "libresoc.v:46040.3-46048.6" wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 - attribute \src "libresoc.v:39635.7-39635.34" + attribute \src "libresoc.v:39431.7-39431.34" wire $1\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:46263.3-46271.6" + attribute \src "libresoc.v:46059.3-46067.6" wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 - attribute \src "libresoc.v:39639.7-39639.39" + attribute \src "libresoc.v:39435.7-39435.39" wire $1\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:46206.3-46214.6" + attribute \src "libresoc.v:46002.3-46010.6" wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 - attribute \src "libresoc.v:39643.7-39643.34" + attribute \src "libresoc.v:39439.7-39439.34" wire $1\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:47563.3-47591.6" + attribute \src "libresoc.v:47359.3-47387.6" wire $1\fus_cu_issue_i$13[0:0]$2825 - attribute \src "libresoc.v:47888.3-47916.6" + attribute \src "libresoc.v:47684.3-47712.6" wire $1\fus_cu_issue_i$16[0:0]$2863 - attribute \src "libresoc.v:48207.3-48235.6" + attribute \src "libresoc.v:48003.3-48031.6" wire $1\fus_cu_issue_i$19[0:0]$2882 - attribute \src "libresoc.v:43852.3-43880.6" + attribute \src "libresoc.v:43648.3-43676.6" wire $1\fus_cu_issue_i$22[0:0]$2360 - attribute \src "libresoc.v:44026.3-44054.6" + attribute \src "libresoc.v:43822.3-43850.6" wire $1\fus_cu_issue_i$25[0:0]$2374 - attribute \src "libresoc.v:44522.3-44550.6" + attribute \src "libresoc.v:44318.3-44346.6" wire $1\fus_cu_issue_i$28[0:0]$2399 - attribute \src "libresoc.v:44844.3-44872.6" + attribute \src "libresoc.v:44640.3-44668.6" wire $1\fus_cu_issue_i$31[0:0]$2418 - attribute \src "libresoc.v:45311.3-45339.6" + attribute \src "libresoc.v:45107.3-45135.6" wire $1\fus_cu_issue_i$34[0:0]$2442 - attribute \src "libresoc.v:45749.3-45777.6" + attribute \src "libresoc.v:45545.3-45573.6" wire $1\fus_cu_issue_i$37[0:0]$2465 - attribute \src "libresoc.v:47355.3-47383.6" + attribute \src "libresoc.v:47151.3-47179.6" wire $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47610.3-47638.6" + attribute \src "libresoc.v:47406.3-47434.6" wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2836 - attribute \src "libresoc.v:47917.3-47945.6" + attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $1\fus_cu_rdmaskn_i$18[2:0]$2868 - attribute \src "libresoc.v:48236.3-48264.6" + attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $1\fus_cu_rdmaskn_i$21[3:0]$2887 - attribute \src "libresoc.v:43881.3-43909.6" + attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2365 - attribute \src "libresoc.v:44055.3-44083.6" + attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $1\fus_cu_rdmaskn_i$27[5:0]$2379 - attribute \src "libresoc.v:44551.3-44579.6" + attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2404 - attribute \src "libresoc.v:44873.3-44901.6" + attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $1\fus_cu_rdmaskn_i$33[2:0]$2423 - attribute \src "libresoc.v:45340.3-45368.6" + attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $1\fus_cu_rdmaskn_i$36[4:0]$2447 - attribute \src "libresoc.v:45778.3-45806.6" + attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $1\fus_cu_rdmaskn_i$39[2:0]$2470 - attribute \src "libresoc.v:47393.3-47421.6" + attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47270.3-47298.6" + attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46720.3-46748.6" + attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $1\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46768.3-46797.6" + attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46768.3-46797.6" + attribute \src "libresoc.v:46564.3-46593.6" wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47100.3-47128.6" + attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47308.3-47336.6" + attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46653.3-46681.6" + attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46939.3-46967.6" + attribute \src "libresoc.v:46735.3-46763.6" wire $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47015.3-47043.6" + attribute \src "libresoc.v:46811.3-46839.6" wire $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47185.3-47213.6" + attribute \src "libresoc.v:46981.3-47009.6" wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47223.3-47251.6" + attribute \src "libresoc.v:47019.3-47047.6" wire $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46882.3-46911.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46882.3-46911.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47147.3-47175.6" + attribute \src "libresoc.v:46943.3-46971.6" wire $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46825.3-46854.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46825.3-46854.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47053.3-47081.6" + attribute \src "libresoc.v:46849.3-46877.6" wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46977.3-47005.6" + attribute \src "libresoc.v:46773.3-46801.6" wire $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47648.3-47676.6" + attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47733.3-47761.6" + attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $1\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47800.3-47829.6" + attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47800.3-47829.6" + attribute \src "libresoc.v:47596.3-47625.6" wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47771.3-47799.6" + attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47686.3-47714.6" + attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47859.3-47887.6" + attribute \src "libresoc.v:47655.3-47683.6" wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47830.3-47858.6" + attribute \src "libresoc.v:47626.3-47654.6" wire $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47478.3-47506.6" + attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $1\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47525.3-47553.6" + attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47440.3-47468.6" + attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44464.3-44492.6" + attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44113.3-44141.6" + attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $1\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44142.3-44171.6" + attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44142.3-44171.6" + attribute \src "libresoc.v:43938.3-43967.6" wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44290.3-44318.6" + attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44493.3-44521.6" + attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44084.3-44112.6" + attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44232.3-44260.6" + attribute \src "libresoc.v:44028.3-44056.6" wire $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44319.3-44347.6" + attribute \src "libresoc.v:44115.3-44143.6" wire $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44406.3-44434.6" + attribute \src "libresoc.v:44202.3-44230.6" wire $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44435.3-44463.6" + attribute \src "libresoc.v:44231.3-44259.6" wire $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44202.3-44231.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $1\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44202.3-44231.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44377.3-44405.6" + attribute \src "libresoc.v:44173.3-44201.6" wire $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44172.3-44201.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $1\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44172.3-44201.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44348.3-44376.6" + attribute \src "libresoc.v:44144.3-44172.6" wire $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44261.3-44289.6" + attribute \src "libresoc.v:44057.3-44085.6" wire $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43794.3-43822.6" + attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48294.3-48322.6" + attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $1\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48323.3-48352.6" + attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48323.3-48352.6" + attribute \src "libresoc.v:48119.3-48148.6" wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48471.3-48499.6" + attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43823.3-43851.6" + attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48265.3-48293.6" + attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48413.3-48441.6" + attribute \src "libresoc.v:48209.3-48237.6" wire $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48500.3-48528.6" + attribute \src "libresoc.v:48296.3-48324.6" wire $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43736.3-43764.6" + attribute \src "libresoc.v:43532.3-43560.6" wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43765.3-43793.6" + attribute \src "libresoc.v:43561.3-43589.6" wire $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48383.3-48412.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48383.3-48412.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43707.3-43735.6" + attribute \src "libresoc.v:43503.3-43531.6" wire $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48353.3-48382.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48353.3-48382.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48529.3-48557.6" + attribute \src "libresoc.v:48325.3-48353.6" wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48442.3-48470.6" + attribute \src "libresoc.v:48238.3-48266.6" wire $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44609.3-44637.6" + attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $1\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44638.3-44667.6" + attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44638.3-44667.6" + attribute \src "libresoc.v:44434.3-44463.6" wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44815.3-44843.6" + attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44580.3-44608.6" + attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44757.3-44785.6" + attribute \src "libresoc.v:44553.3-44581.6" wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44786.3-44814.6" + attribute \src "libresoc.v:44582.3-44610.6" wire $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44698.3-44727.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44698.3-44727.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44668.3-44697.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44668.3-44697.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44728.3-44756.6" + attribute \src "libresoc.v:44524.3-44552.6" wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44931.3-44959.6" + attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44960.3-44989.6" + attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44960.3-44989.6" + attribute \src "libresoc.v:44756.3-44785.6" wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45108.3-45136.6" + attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45166.3-45194.6" + attribute \src "libresoc.v:44962.3-44990.6" wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45282.3-45310.6" + attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44902.3-44930.6" + attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45079.3-45107.6" + attribute \src "libresoc.v:44875.3-44903.6" wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45224.3-45252.6" + attribute \src "libresoc.v:45020.3-45048.6" wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45253.3-45281.6" + attribute \src "libresoc.v:45049.3-45077.6" wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45020.3-45049.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45020.3-45049.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45137.3-45165.6" + attribute \src "libresoc.v:44933.3-44961.6" wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45195.3-45223.6" + attribute \src "libresoc.v:44991.3-45019.6" wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44990.3-45019.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44990.3-45019.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45050.3-45078.6" + attribute \src "libresoc.v:44846.3-44874.6" wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43939.3-43967.6" + attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $1\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43968.3-43996.6" + attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43910.3-43938.6" + attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43997.3-44025.6" + attribute \src "libresoc.v:43793.3-43821.6" wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48062.3-48090.6" + attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47975.3-48003.6" + attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $1\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48004.3-48032.6" + attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47946.3-47974.6" + attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48091.3-48119.6" + attribute \src "libresoc.v:47887.3-47915.6" wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48178.3-48206.6" + attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48033.3-48061.6" + attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48149.3-48177.6" + attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48120.3-48148.6" + attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45633.3-45661.6" + attribute \src "libresoc.v:45429.3-45457.6" wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45604.3-45632.6" + attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45398.3-45426.6" + attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45427.3-45456.6" + attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45427.3-45456.6" + attribute \src "libresoc.v:45223.3-45252.6" wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45720.3-45748.6" + attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45369.3-45397.6" + attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45546.3-45574.6" + attribute \src "libresoc.v:45342.3-45370.6" wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45575.3-45603.6" + attribute \src "libresoc.v:45371.3-45399.6" wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45691.3-45719.6" + attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45516.3-45545.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45516.3-45545.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45486.3-45515.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45486.3-45515.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45662.3-45690.6" + attribute \src "libresoc.v:45458.3-45486.6" wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45457.3-45485.6" + attribute \src "libresoc.v:45253.3-45281.6" wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:46025.3-46034.6" + attribute \src "libresoc.v:45821.3-45830.6" wire width 64 $1\fus_src1_i$62[63:0]$2538 - attribute \src "libresoc.v:46044.3-46053.6" + attribute \src "libresoc.v:45840.3-45849.6" wire width 64 $1\fus_src1_i$63[63:0]$2544 - attribute \src "libresoc.v:46063.3-46072.6" + attribute \src "libresoc.v:45859.3-45868.6" wire width 64 $1\fus_src1_i$64[63:0]$2550 - attribute \src "libresoc.v:46082.3-46091.6" + attribute \src "libresoc.v:45878.3-45887.6" wire width 64 $1\fus_src1_i$67[63:0]$2556 - attribute \src "libresoc.v:46101.3-46110.6" + attribute \src "libresoc.v:45897.3-45906.6" wire width 64 $1\fus_src1_i$68[63:0]$2562 - attribute \src "libresoc.v:46120.3-46129.6" + attribute \src "libresoc.v:45916.3-45925.6" wire width 64 $1\fus_src1_i$69[63:0]$2568 - attribute \src "libresoc.v:46139.3-46148.6" + attribute \src "libresoc.v:45935.3-45944.6" wire width 64 $1\fus_src1_i$70[63:0]$2574 - attribute \src "libresoc.v:46158.3-46167.6" + attribute \src "libresoc.v:45954.3-45963.6" wire width 64 $1\fus_src1_i$71[63:0]$2580 - attribute \src "libresoc.v:46584.3-46593.6" + attribute \src "libresoc.v:46380.3-46389.6" wire width 64 $1\fus_src1_i$86[63:0]$2677 - attribute \src "libresoc.v:46006.3-46015.6" + attribute \src "libresoc.v:45802.3-45811.6" wire width 64 $1\fus_src1_i[63:0] - attribute \src "libresoc.v:45835.3-45844.6" + attribute \src "libresoc.v:45631.3-45640.6" wire width 64 $1\fus_src2_i$42[63:0]$2482 - attribute \src "libresoc.v:45854.3-45863.6" + attribute \src "libresoc.v:45650.3-45659.6" wire width 64 $1\fus_src2_i$45[63:0]$2488 - attribute \src "libresoc.v:45873.3-45882.6" + attribute \src "libresoc.v:45669.3-45678.6" wire width 64 $1\fus_src2_i$48[63:0]$2494 - attribute \src "libresoc.v:45892.3-45901.6" + attribute \src "libresoc.v:45688.3-45697.6" wire width 64 $1\fus_src2_i$51[63:0]$2500 - attribute \src "libresoc.v:45911.3-45920.6" + attribute \src "libresoc.v:45707.3-45716.6" wire width 64 $1\fus_src2_i$54[63:0]$2506 - attribute \src "libresoc.v:45930.3-45939.6" + attribute \src "libresoc.v:45726.3-45735.6" wire width 64 $1\fus_src2_i$57[63:0]$2512 - attribute \src "libresoc.v:45949.3-45958.6" + attribute \src "libresoc.v:45745.3-45754.6" wire width 64 $1\fus_src2_i$60[63:0]$2518 - attribute \src "libresoc.v:46691.3-46700.6" + attribute \src "libresoc.v:46487.3-46496.6" wire width 64 $1\fus_src2_i$89[63:0]$2701 - attribute \src "libresoc.v:46758.3-46767.6" + attribute \src "libresoc.v:46554.3-46563.6" wire width 64 $1\fus_src2_i$91[63:0]$2714 - attribute \src "libresoc.v:45816.3-45825.6" + attribute \src "libresoc.v:45612.3-45621.6" wire width 64 $1\fus_src2_i[63:0] - attribute \src "libresoc.v:45987.3-45996.6" + attribute \src "libresoc.v:45783.3-45792.6" wire width 64 $1\fus_src3_i$61[63:0]$2528 - attribute \src "libresoc.v:46177.3-46186.6" + attribute \src "libresoc.v:45973.3-45982.6" wire $1\fus_src3_i$72[0:0]$2586 - attribute \src "libresoc.v:46196.3-46205.6" + attribute \src "libresoc.v:45992.3-46001.6" wire $1\fus_src3_i$73[0:0]$2592 - attribute \src "libresoc.v:46234.3-46243.6" + attribute \src "libresoc.v:46030.3-46039.6" wire $1\fus_src3_i$74[0:0]$2602 - attribute \src "libresoc.v:46253.3-46262.6" + attribute \src "libresoc.v:46049.3-46058.6" wire $1\fus_src3_i$75[0:0]$2608 - attribute \src "libresoc.v:46367.3-46376.6" + attribute \src "libresoc.v:46163.3-46172.6" wire width 32 $1\fus_src3_i$79[31:0]$2640 - attribute \src "libresoc.v:46405.3-46414.6" + attribute \src "libresoc.v:46201.3-46210.6" wire width 4 $1\fus_src3_i$83[3:0]$2652 - attribute \src "libresoc.v:46624.3-46633.6" + attribute \src "libresoc.v:46420.3-46429.6" wire width 64 $1\fus_src3_i$87[63:0]$2688 - attribute \src "libresoc.v:46643.3-46652.6" + attribute \src "libresoc.v:46439.3-46448.6" wire width 64 $1\fus_src3_i$88[63:0]$2694 - attribute \src "libresoc.v:45968.3-45977.6" + attribute \src "libresoc.v:45764.3-45773.6" wire width 64 $1\fus_src3_i[63:0] - attribute \src "libresoc.v:46272.3-46281.6" + attribute \src "libresoc.v:46068.3-46077.6" wire $1\fus_src4_i$76[0:0]$2614 - attribute \src "libresoc.v:46291.3-46300.6" + attribute \src "libresoc.v:46087.3-46096.6" wire width 2 $1\fus_src4_i$77[1:0]$2620 - attribute \src "libresoc.v:46386.3-46395.6" + attribute \src "libresoc.v:46182.3-46191.6" wire width 4 $1\fus_src4_i$80[3:0]$2646 - attribute \src "libresoc.v:46710.3-46719.6" + attribute \src "libresoc.v:46506.3-46515.6" wire width 64 $1\fus_src4_i$90[63:0]$2707 - attribute \src "libresoc.v:46215.3-46224.6" + attribute \src "libresoc.v:46011.3-46020.6" wire $1\fus_src4_i[0:0] - attribute \src "libresoc.v:46348.3-46357.6" + attribute \src "libresoc.v:46144.3-46153.6" wire width 2 $1\fus_src5_i$78[1:0]$2634 - attribute \src "libresoc.v:46455.3-46464.6" + attribute \src "libresoc.v:46251.3-46260.6" wire width 4 $1\fus_src5_i$84[3:0]$2664 - attribute \src "libresoc.v:46329.3-46338.6" + attribute \src "libresoc.v:46125.3-46134.6" wire width 2 $1\fus_src5_i[1:0] - attribute \src "libresoc.v:46474.3-46483.6" + attribute \src "libresoc.v:46270.3-46279.6" wire width 4 $1\fus_src6_i$85[3:0]$2670 - attribute \src "libresoc.v:46310.3-46319.6" + attribute \src "libresoc.v:46106.3-46115.6" wire width 2 $1\fus_src6_i[1:0] - attribute \src "libresoc.v:46816.3-46824.6" + attribute \src "libresoc.v:46612.3-46620.6" wire $1\wr_pick_dly$1008$next[0:0]$2724 - attribute \src "libresoc.v:46855.3-46863.6" + attribute \src "libresoc.v:46651.3-46659.6" wire $1\wr_pick_dly$1029$next[0:0]$2728 - attribute \src "libresoc.v:46864.3-46872.6" + attribute \src "libresoc.v:46660.3-46668.6" wire $1\wr_pick_dly$1047$next[0:0]$2731 - attribute \src "libresoc.v:46873.3-46881.6" + attribute \src "libresoc.v:46669.3-46677.6" wire $1\wr_pick_dly$1069$next[0:0]$2734 - attribute \src "libresoc.v:46912.3-46920.6" + attribute \src "libresoc.v:46708.3-46716.6" wire $1\wr_pick_dly$1089$next[0:0]$2738 - attribute \src "libresoc.v:46921.3-46929.6" + attribute \src "libresoc.v:46717.3-46725.6" wire $1\wr_pick_dly$1109$next[0:0]$2741 - attribute \src "libresoc.v:46930.3-46938.6" + attribute \src "libresoc.v:46726.3-46734.6" wire $1\wr_pick_dly$1128$next[0:0]$2744 - attribute \src "libresoc.v:46968.3-46976.6" + attribute \src "libresoc.v:46764.3-46772.6" wire $1\wr_pick_dly$1146$next[0:0]$2748 - attribute \src "libresoc.v:47006.3-47014.6" + attribute \src "libresoc.v:46802.3-46810.6" wire $1\wr_pick_dly$1220$next[0:0]$2752 - attribute \src "libresoc.v:47044.3-47052.6" + attribute \src "libresoc.v:46840.3-46848.6" wire $1\wr_pick_dly$1248$next[0:0]$2756 - attribute \src "libresoc.v:47082.3-47090.6" + attribute \src "libresoc.v:46878.3-46886.6" wire $1\wr_pick_dly$1268$next[0:0]$2760 - attribute \src "libresoc.v:47091.3-47099.6" + attribute \src "libresoc.v:46887.3-46895.6" wire $1\wr_pick_dly$1288$next[0:0]$2763 - attribute \src "libresoc.v:47129.3-47137.6" + attribute \src "libresoc.v:46925.3-46933.6" wire $1\wr_pick_dly$1308$next[0:0]$2767 - attribute \src "libresoc.v:47138.3-47146.6" + attribute \src "libresoc.v:46934.3-46942.6" wire $1\wr_pick_dly$1328$next[0:0]$2770 - attribute \src "libresoc.v:47176.3-47184.6" + attribute \src "libresoc.v:46972.3-46980.6" wire $1\wr_pick_dly$1348$next[0:0]$2774 - attribute \src "libresoc.v:47214.3-47222.6" + attribute \src "libresoc.v:47010.3-47018.6" wire $1\wr_pick_dly$1395$next[0:0]$2778 - attribute \src "libresoc.v:47252.3-47260.6" + attribute \src "libresoc.v:47048.3-47056.6" wire $1\wr_pick_dly$1411$next[0:0]$2782 - attribute \src "libresoc.v:47261.3-47269.6" + attribute \src "libresoc.v:47057.3-47065.6" wire $1\wr_pick_dly$1427$next[0:0]$2785 - attribute \src "libresoc.v:47299.3-47307.6" + attribute \src "libresoc.v:47095.3-47103.6" wire $1\wr_pick_dly$1461$next[0:0]$2789 - attribute \src "libresoc.v:47337.3-47345.6" + attribute \src "libresoc.v:47133.3-47141.6" wire $1\wr_pick_dly$1477$next[0:0]$2793 - attribute \src "libresoc.v:47346.3-47354.6" + attribute \src "libresoc.v:47142.3-47150.6" wire $1\wr_pick_dly$1493$next[0:0]$2796 - attribute \src "libresoc.v:47384.3-47392.6" + attribute \src "libresoc.v:47180.3-47188.6" wire $1\wr_pick_dly$1509$next[0:0]$2800 - attribute \src "libresoc.v:47422.3-47430.6" + attribute \src "libresoc.v:47218.3-47226.6" wire $1\wr_pick_dly$1545$next[0:0]$2804 - attribute \src "libresoc.v:47431.3-47439.6" + attribute \src "libresoc.v:47227.3-47235.6" wire $1\wr_pick_dly$1561$next[0:0]$2807 - attribute \src "libresoc.v:47469.3-47477.6" + attribute \src "libresoc.v:47265.3-47273.6" wire $1\wr_pick_dly$1577$next[0:0]$2811 - attribute \src "libresoc.v:47507.3-47515.6" + attribute \src "libresoc.v:47303.3-47311.6" wire $1\wr_pick_dly$1593$next[0:0]$2815 - attribute \src "libresoc.v:47516.3-47524.6" + attribute \src "libresoc.v:47312.3-47320.6" wire $1\wr_pick_dly$1635$next[0:0]$2818 - attribute \src "libresoc.v:47554.3-47562.6" + attribute \src "libresoc.v:47350.3-47358.6" wire $1\wr_pick_dly$1654$next[0:0]$2822 - attribute \src "libresoc.v:47592.3-47600.6" + attribute \src "libresoc.v:47388.3-47396.6" wire $1\wr_pick_dly$1670$next[0:0]$2830 - attribute \src "libresoc.v:47601.3-47609.6" + attribute \src "libresoc.v:47397.3-47405.6" wire $1\wr_pick_dly$1686$next[0:0]$2833 - attribute \src "libresoc.v:47639.3-47647.6" + attribute \src "libresoc.v:47435.3-47443.6" wire $1\wr_pick_dly$1702$next[0:0]$2841 - attribute \src "libresoc.v:47677.3-47685.6" + attribute \src "libresoc.v:47473.3-47481.6" wire $1\wr_pick_dly$1746$next[0:0]$2845 - attribute \src "libresoc.v:47715.3-47723.6" + attribute \src "libresoc.v:47511.3-47519.6" wire $1\wr_pick_dly$1762$next[0:0]$2849 - attribute \src "libresoc.v:47724.3-47732.6" + attribute \src "libresoc.v:47520.3-47528.6" wire $1\wr_pick_dly$1786$next[0:0]$2852 - attribute \src "libresoc.v:47762.3-47770.6" + attribute \src "libresoc.v:47558.3-47566.6" wire $1\wr_pick_dly$1806$next[0:0]$2856 - attribute \src "libresoc.v:46807.3-46815.6" + attribute \src "libresoc.v:46603.3-46611.6" wire $1\wr_pick_dly$989$next[0:0]$2721 - attribute \src "libresoc.v:46798.3-46806.6" + attribute \src "libresoc.v:46594.3-46602.6" wire $1\wr_pick_dly$next[0:0]$2718 - attribute \src "libresoc.v:41732.7-41732.25" + attribute \src "libresoc.v:41528.7-41528.25" wire $1\wr_pick_dly[0:0] - attribute \src "libresoc.v:46594.3-46614.6" + attribute \src "libresoc.v:46390.3-46410.6" wire $2\core_terminate_o$next[0:0]$2681 - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $2\corebusy_o[0:0] - attribute \src "libresoc.v:46424.3-46454.6" + attribute \src "libresoc.v:46220.3-46250.6" wire width 2 $2\counter$next[1:0]$2659 - attribute \src "libresoc.v:47563.3-47591.6" + attribute \src "libresoc.v:47359.3-47387.6" wire $2\fus_cu_issue_i$13[0:0]$2826 - attribute \src "libresoc.v:47888.3-47916.6" + attribute \src "libresoc.v:47684.3-47712.6" wire $2\fus_cu_issue_i$16[0:0]$2864 - attribute \src "libresoc.v:48207.3-48235.6" + attribute \src "libresoc.v:48003.3-48031.6" wire $2\fus_cu_issue_i$19[0:0]$2883 - attribute \src "libresoc.v:43852.3-43880.6" + attribute \src "libresoc.v:43648.3-43676.6" wire $2\fus_cu_issue_i$22[0:0]$2361 - attribute \src "libresoc.v:44026.3-44054.6" + attribute \src "libresoc.v:43822.3-43850.6" wire $2\fus_cu_issue_i$25[0:0]$2375 - attribute \src "libresoc.v:44522.3-44550.6" + attribute \src "libresoc.v:44318.3-44346.6" wire $2\fus_cu_issue_i$28[0:0]$2400 - attribute \src "libresoc.v:44844.3-44872.6" + attribute \src "libresoc.v:44640.3-44668.6" wire $2\fus_cu_issue_i$31[0:0]$2419 - attribute \src "libresoc.v:45311.3-45339.6" + attribute \src "libresoc.v:45107.3-45135.6" wire $2\fus_cu_issue_i$34[0:0]$2443 - attribute \src "libresoc.v:45749.3-45777.6" + attribute \src "libresoc.v:45545.3-45573.6" wire $2\fus_cu_issue_i$37[0:0]$2466 - attribute \src "libresoc.v:47355.3-47383.6" + attribute \src "libresoc.v:47151.3-47179.6" wire $2\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47610.3-47638.6" + attribute \src "libresoc.v:47406.3-47434.6" wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2837 - attribute \src "libresoc.v:47917.3-47945.6" + attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $2\fus_cu_rdmaskn_i$18[2:0]$2869 - attribute \src "libresoc.v:48236.3-48264.6" + attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $2\fus_cu_rdmaskn_i$21[3:0]$2888 - attribute \src "libresoc.v:43881.3-43909.6" + attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2366 - attribute \src "libresoc.v:44055.3-44083.6" + attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $2\fus_cu_rdmaskn_i$27[5:0]$2380 - attribute \src "libresoc.v:44551.3-44579.6" + attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2405 - attribute \src "libresoc.v:44873.3-44901.6" + attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $2\fus_cu_rdmaskn_i$33[2:0]$2424 - attribute \src "libresoc.v:45340.3-45368.6" + attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $2\fus_cu_rdmaskn_i$36[4:0]$2448 - attribute \src "libresoc.v:45778.3-45806.6" + attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $2\fus_cu_rdmaskn_i$39[2:0]$2471 - attribute \src "libresoc.v:47393.3-47421.6" + attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $2\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47270.3-47298.6" + attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46720.3-46748.6" + attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $2\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46768.3-46797.6" + attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46768.3-46797.6" + attribute \src "libresoc.v:46564.3-46593.6" wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47100.3-47128.6" + attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47308.3-47336.6" + attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46653.3-46681.6" + attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46939.3-46967.6" + attribute \src "libresoc.v:46735.3-46763.6" wire $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47015.3-47043.6" + attribute \src "libresoc.v:46811.3-46839.6" wire $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47185.3-47213.6" + attribute \src "libresoc.v:46981.3-47009.6" wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47223.3-47251.6" + attribute \src "libresoc.v:47019.3-47047.6" wire $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46882.3-46911.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46882.3-46911.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47147.3-47175.6" + attribute \src "libresoc.v:46943.3-46971.6" wire $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46825.3-46854.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46825.3-46854.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47053.3-47081.6" + attribute \src "libresoc.v:46849.3-46877.6" wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46977.3-47005.6" + attribute \src "libresoc.v:46773.3-46801.6" wire $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47648.3-47676.6" + attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47733.3-47761.6" + attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $2\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47800.3-47829.6" + attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47800.3-47829.6" + attribute \src "libresoc.v:47596.3-47625.6" wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47771.3-47799.6" + attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47686.3-47714.6" + attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47859.3-47887.6" + attribute \src "libresoc.v:47655.3-47683.6" wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47830.3-47858.6" + attribute \src "libresoc.v:47626.3-47654.6" wire $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47478.3-47506.6" + attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $2\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47525.3-47553.6" + attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47440.3-47468.6" + attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44464.3-44492.6" + attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44113.3-44141.6" + attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $2\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44142.3-44171.6" + attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44142.3-44171.6" + attribute \src "libresoc.v:43938.3-43967.6" wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44290.3-44318.6" + attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44493.3-44521.6" + attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44084.3-44112.6" + attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44232.3-44260.6" + attribute \src "libresoc.v:44028.3-44056.6" wire $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44319.3-44347.6" + attribute \src "libresoc.v:44115.3-44143.6" wire $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44406.3-44434.6" + attribute \src "libresoc.v:44202.3-44230.6" wire $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44435.3-44463.6" + attribute \src "libresoc.v:44231.3-44259.6" wire $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44202.3-44231.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $2\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44202.3-44231.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44377.3-44405.6" + attribute \src "libresoc.v:44173.3-44201.6" wire $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44172.3-44201.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $2\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44172.3-44201.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44348.3-44376.6" + attribute \src "libresoc.v:44144.3-44172.6" wire $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44261.3-44289.6" + attribute \src "libresoc.v:44057.3-44085.6" wire $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43794.3-43822.6" + attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48294.3-48322.6" + attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $2\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48323.3-48352.6" + attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48323.3-48352.6" + attribute \src "libresoc.v:48119.3-48148.6" wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48471.3-48499.6" + attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43823.3-43851.6" + attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48265.3-48293.6" + attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48413.3-48441.6" + attribute \src "libresoc.v:48209.3-48237.6" wire $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48500.3-48528.6" + attribute \src "libresoc.v:48296.3-48324.6" wire $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43736.3-43764.6" + attribute \src "libresoc.v:43532.3-43560.6" wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43765.3-43793.6" + attribute \src "libresoc.v:43561.3-43589.6" wire $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48383.3-48412.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48383.3-48412.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43707.3-43735.6" + attribute \src "libresoc.v:43503.3-43531.6" wire $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48353.3-48382.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48353.3-48382.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48529.3-48557.6" + attribute \src "libresoc.v:48325.3-48353.6" wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48442.3-48470.6" + attribute \src "libresoc.v:48238.3-48266.6" wire $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44609.3-44637.6" + attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $2\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44638.3-44667.6" + attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44638.3-44667.6" + attribute \src "libresoc.v:44434.3-44463.6" wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44815.3-44843.6" + attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44580.3-44608.6" + attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44757.3-44785.6" + attribute \src "libresoc.v:44553.3-44581.6" wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44786.3-44814.6" + attribute \src "libresoc.v:44582.3-44610.6" wire $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44698.3-44727.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44698.3-44727.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44668.3-44697.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44668.3-44697.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44728.3-44756.6" + attribute \src "libresoc.v:44524.3-44552.6" wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44931.3-44959.6" + attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44960.3-44989.6" + attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44960.3-44989.6" + attribute \src "libresoc.v:44756.3-44785.6" wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45108.3-45136.6" + attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45166.3-45194.6" + attribute \src "libresoc.v:44962.3-44990.6" wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45282.3-45310.6" + attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44902.3-44930.6" + attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45079.3-45107.6" + attribute \src "libresoc.v:44875.3-44903.6" wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45224.3-45252.6" + attribute \src "libresoc.v:45020.3-45048.6" wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45253.3-45281.6" + attribute \src "libresoc.v:45049.3-45077.6" wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45020.3-45049.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45020.3-45049.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45137.3-45165.6" + attribute \src "libresoc.v:44933.3-44961.6" wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45195.3-45223.6" + attribute \src "libresoc.v:44991.3-45019.6" wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44990.3-45019.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44990.3-45019.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45050.3-45078.6" + attribute \src "libresoc.v:44846.3-44874.6" wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43939.3-43967.6" + attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $2\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43968.3-43996.6" + attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43910.3-43938.6" + attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43997.3-44025.6" + attribute \src "libresoc.v:43793.3-43821.6" wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48062.3-48090.6" + attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47975.3-48003.6" + attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $2\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48004.3-48032.6" + attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47946.3-47974.6" + attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48091.3-48119.6" + attribute \src "libresoc.v:47887.3-47915.6" wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48178.3-48206.6" + attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48033.3-48061.6" + attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48149.3-48177.6" + attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48120.3-48148.6" + attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45633.3-45661.6" + attribute \src "libresoc.v:45429.3-45457.6" wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45604.3-45632.6" + attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45398.3-45426.6" + attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45427.3-45456.6" + attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45427.3-45456.6" + attribute \src "libresoc.v:45223.3-45252.6" wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45720.3-45748.6" + attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45369.3-45397.6" + attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45546.3-45574.6" + attribute \src "libresoc.v:45342.3-45370.6" wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45575.3-45603.6" + attribute \src "libresoc.v:45371.3-45399.6" wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45691.3-45719.6" + attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45516.3-45545.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45516.3-45545.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45486.3-45515.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45486.3-45515.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45662.3-45690.6" + attribute \src "libresoc.v:45458.3-45486.6" wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45457.3-45485.6" + attribute \src "libresoc.v:45253.3-45281.6" wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:46594.3-46614.6" + attribute \src "libresoc.v:46390.3-46410.6" wire $3\core_terminate_o$next[0:0]$2682 - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $3\corebusy_o[0:0] - attribute \src "libresoc.v:46424.3-46454.6" + attribute \src "libresoc.v:46220.3-46250.6" wire width 2 $3\counter$next[1:0]$2660 - attribute \src "libresoc.v:47563.3-47591.6" + attribute \src "libresoc.v:47359.3-47387.6" wire $3\fus_cu_issue_i$13[0:0]$2827 - attribute \src "libresoc.v:47888.3-47916.6" + attribute \src "libresoc.v:47684.3-47712.6" wire $3\fus_cu_issue_i$16[0:0]$2865 - attribute \src "libresoc.v:48207.3-48235.6" + attribute \src "libresoc.v:48003.3-48031.6" wire $3\fus_cu_issue_i$19[0:0]$2884 - attribute \src "libresoc.v:43852.3-43880.6" + attribute \src "libresoc.v:43648.3-43676.6" wire $3\fus_cu_issue_i$22[0:0]$2362 - attribute \src "libresoc.v:44026.3-44054.6" + attribute \src "libresoc.v:43822.3-43850.6" wire $3\fus_cu_issue_i$25[0:0]$2376 - attribute \src "libresoc.v:44522.3-44550.6" + attribute \src "libresoc.v:44318.3-44346.6" wire $3\fus_cu_issue_i$28[0:0]$2401 - attribute \src "libresoc.v:44844.3-44872.6" + attribute \src "libresoc.v:44640.3-44668.6" wire $3\fus_cu_issue_i$31[0:0]$2420 - attribute \src "libresoc.v:45311.3-45339.6" + attribute \src "libresoc.v:45107.3-45135.6" wire $3\fus_cu_issue_i$34[0:0]$2444 - attribute \src "libresoc.v:45749.3-45777.6" + attribute \src "libresoc.v:45545.3-45573.6" wire $3\fus_cu_issue_i$37[0:0]$2467 - attribute \src "libresoc.v:47355.3-47383.6" + attribute \src "libresoc.v:47151.3-47179.6" wire $3\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47610.3-47638.6" + attribute \src "libresoc.v:47406.3-47434.6" wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2838 - attribute \src "libresoc.v:47917.3-47945.6" + attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $3\fus_cu_rdmaskn_i$18[2:0]$2870 - attribute \src "libresoc.v:48236.3-48264.6" + attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $3\fus_cu_rdmaskn_i$21[3:0]$2889 - attribute \src "libresoc.v:43881.3-43909.6" + attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2367 - attribute \src "libresoc.v:44055.3-44083.6" + attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $3\fus_cu_rdmaskn_i$27[5:0]$2381 - attribute \src "libresoc.v:44551.3-44579.6" + attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2406 - attribute \src "libresoc.v:44873.3-44901.6" + attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $3\fus_cu_rdmaskn_i$33[2:0]$2425 - attribute \src "libresoc.v:45340.3-45368.6" + attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $3\fus_cu_rdmaskn_i$36[4:0]$2449 - attribute \src "libresoc.v:45778.3-45806.6" + attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $3\fus_cu_rdmaskn_i$39[2:0]$2472 - attribute \src "libresoc.v:47393.3-47421.6" + attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $3\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47270.3-47298.6" + attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46720.3-46748.6" + attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $3\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46768.3-46797.6" + attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46768.3-46797.6" + attribute \src "libresoc.v:46564.3-46593.6" wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47100.3-47128.6" + attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47308.3-47336.6" + attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46653.3-46681.6" + attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46939.3-46967.6" + attribute \src "libresoc.v:46735.3-46763.6" wire $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47015.3-47043.6" + attribute \src "libresoc.v:46811.3-46839.6" wire $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47185.3-47213.6" + attribute \src "libresoc.v:46981.3-47009.6" wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47223.3-47251.6" + attribute \src "libresoc.v:47019.3-47047.6" wire $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46882.3-46911.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46882.3-46911.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47147.3-47175.6" + attribute \src "libresoc.v:46943.3-46971.6" wire $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46825.3-46854.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46825.3-46854.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47053.3-47081.6" + attribute \src "libresoc.v:46849.3-46877.6" wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46977.3-47005.6" + attribute \src "libresoc.v:46773.3-46801.6" wire $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47648.3-47676.6" + attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47733.3-47761.6" + attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $3\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47800.3-47829.6" + attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47800.3-47829.6" + attribute \src "libresoc.v:47596.3-47625.6" wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47771.3-47799.6" + attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47686.3-47714.6" + attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47859.3-47887.6" + attribute \src "libresoc.v:47655.3-47683.6" wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47830.3-47858.6" + attribute \src "libresoc.v:47626.3-47654.6" wire $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47478.3-47506.6" + attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $3\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47525.3-47553.6" + attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47440.3-47468.6" + attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44464.3-44492.6" + attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44113.3-44141.6" + attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $3\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44142.3-44171.6" + attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44142.3-44171.6" + attribute \src "libresoc.v:43938.3-43967.6" wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44290.3-44318.6" + attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44493.3-44521.6" + attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44084.3-44112.6" + attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44232.3-44260.6" + attribute \src "libresoc.v:44028.3-44056.6" wire $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44319.3-44347.6" + attribute \src "libresoc.v:44115.3-44143.6" wire $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44406.3-44434.6" + attribute \src "libresoc.v:44202.3-44230.6" wire $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44435.3-44463.6" + attribute \src "libresoc.v:44231.3-44259.6" wire $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44202.3-44231.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $3\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44202.3-44231.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44377.3-44405.6" + attribute \src "libresoc.v:44173.3-44201.6" wire $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44172.3-44201.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $3\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44172.3-44201.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44348.3-44376.6" + attribute \src "libresoc.v:44144.3-44172.6" wire $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44261.3-44289.6" + attribute \src "libresoc.v:44057.3-44085.6" wire $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43794.3-43822.6" + attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48294.3-48322.6" + attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $3\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48323.3-48352.6" + attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48323.3-48352.6" + attribute \src "libresoc.v:48119.3-48148.6" wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48471.3-48499.6" + attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43823.3-43851.6" + attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48265.3-48293.6" + attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48413.3-48441.6" + attribute \src "libresoc.v:48209.3-48237.6" wire $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48500.3-48528.6" + attribute \src "libresoc.v:48296.3-48324.6" wire $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43736.3-43764.6" + attribute \src "libresoc.v:43532.3-43560.6" wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43765.3-43793.6" + attribute \src "libresoc.v:43561.3-43589.6" wire $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48383.3-48412.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48383.3-48412.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43707.3-43735.6" + attribute \src "libresoc.v:43503.3-43531.6" wire $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48353.3-48382.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48353.3-48382.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48529.3-48557.6" + attribute \src "libresoc.v:48325.3-48353.6" wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48442.3-48470.6" + attribute \src "libresoc.v:48238.3-48266.6" wire $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44609.3-44637.6" + attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $3\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44638.3-44667.6" + attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44638.3-44667.6" + attribute \src "libresoc.v:44434.3-44463.6" wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44815.3-44843.6" + attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44580.3-44608.6" + attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44757.3-44785.6" + attribute \src "libresoc.v:44553.3-44581.6" wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44786.3-44814.6" + attribute \src "libresoc.v:44582.3-44610.6" wire $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44698.3-44727.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44698.3-44727.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44668.3-44697.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44668.3-44697.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44728.3-44756.6" + attribute \src "libresoc.v:44524.3-44552.6" wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44931.3-44959.6" + attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44960.3-44989.6" + attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44960.3-44989.6" + attribute \src "libresoc.v:44756.3-44785.6" wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45108.3-45136.6" + attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45166.3-45194.6" + attribute \src "libresoc.v:44962.3-44990.6" wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45282.3-45310.6" + attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44902.3-44930.6" + attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45079.3-45107.6" + attribute \src "libresoc.v:44875.3-44903.6" wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45224.3-45252.6" + attribute \src "libresoc.v:45020.3-45048.6" wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45253.3-45281.6" + attribute \src "libresoc.v:45049.3-45077.6" wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45020.3-45049.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45020.3-45049.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45137.3-45165.6" + attribute \src "libresoc.v:44933.3-44961.6" wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45195.3-45223.6" + attribute \src "libresoc.v:44991.3-45019.6" wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44990.3-45019.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44990.3-45019.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45050.3-45078.6" + attribute \src "libresoc.v:44846.3-44874.6" wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43939.3-43967.6" + attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $3\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43968.3-43996.6" + attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43910.3-43938.6" + attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43997.3-44025.6" + attribute \src "libresoc.v:43793.3-43821.6" wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48062.3-48090.6" + attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47975.3-48003.6" + attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $3\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48004.3-48032.6" + attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47946.3-47974.6" + attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48091.3-48119.6" + attribute \src "libresoc.v:47887.3-47915.6" wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48178.3-48206.6" + attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48033.3-48061.6" + attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48149.3-48177.6" + attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48120.3-48148.6" + attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45633.3-45661.6" + attribute \src "libresoc.v:45429.3-45457.6" wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45604.3-45632.6" + attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45398.3-45426.6" + attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45427.3-45456.6" + attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45427.3-45456.6" + attribute \src "libresoc.v:45223.3-45252.6" wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45720.3-45748.6" + attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45369.3-45397.6" + attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45546.3-45574.6" + attribute \src "libresoc.v:45342.3-45370.6" wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45575.3-45603.6" + attribute \src "libresoc.v:45371.3-45399.6" wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45691.3-45719.6" + attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45516.3-45545.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45516.3-45545.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45486.3-45515.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45486.3-45515.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45662.3-45690.6" + attribute \src "libresoc.v:45458.3-45486.6" wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45457.3-45485.6" + attribute \src "libresoc.v:45253.3-45281.6" wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $4\corebusy_o[0:0] - attribute \src "libresoc.v:46424.3-46454.6" + attribute \src "libresoc.v:46220.3-46250.6" wire width 2 $4\counter$next[1:0]$2661 - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $5\corebusy_o[0:0] - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $6\corebusy_o[0:0] - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $7\corebusy_o[0:0] - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $8\corebusy_o[0:0] - attribute \src "libresoc.v:46484.3-46574.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $9\corebusy_o[0:0] - attribute \src "libresoc.v:42112.20-42112.122" - wire $and$libresoc.v:42112$1507_Y - attribute \src "libresoc.v:42113.20-42113.126" - wire $and$libresoc.v:42113$1508_Y - attribute \src "libresoc.v:42115.20-42115.110" - wire $and$libresoc.v:42115$1510_Y - attribute \src "libresoc.v:42116.20-42116.123" - wire $and$libresoc.v:42116$1511_Y - attribute \src "libresoc.v:42118.20-42118.122" - wire $and$libresoc.v:42118$1513_Y - attribute \src "libresoc.v:42119.20-42119.126" - wire $and$libresoc.v:42119$1514_Y + attribute \src "libresoc.v:41908.20-41908.122" + wire $and$libresoc.v:41908$1507_Y + attribute \src "libresoc.v:41909.20-41909.126" + wire $and$libresoc.v:41909$1508_Y + attribute \src "libresoc.v:41911.20-41911.110" + wire $and$libresoc.v:41911$1510_Y + attribute \src "libresoc.v:41912.20-41912.123" + wire $and$libresoc.v:41912$1511_Y + attribute \src "libresoc.v:41914.20-41914.122" + wire $and$libresoc.v:41914$1513_Y + attribute \src "libresoc.v:41915.20-41915.126" + wire $and$libresoc.v:41915$1514_Y + attribute \src "libresoc.v:41917.20-41917.110" + wire $and$libresoc.v:41917$1516_Y + attribute \src "libresoc.v:41918.20-41918.123" + wire $and$libresoc.v:41918$1517_Y + attribute \src "libresoc.v:41920.20-41920.123" + wire $and$libresoc.v:41920$1519_Y + attribute \src "libresoc.v:41921.20-41921.126" + wire $and$libresoc.v:41921$1520_Y + attribute \src "libresoc.v:41923.20-41923.110" + wire $and$libresoc.v:41923$1522_Y + attribute \src "libresoc.v:41924.20-41924.123" + wire $and$libresoc.v:41924$1523_Y + attribute \src "libresoc.v:41926.20-41926.123" + wire $and$libresoc.v:41926$1525_Y + attribute \src "libresoc.v:41927.20-41927.126" + wire $and$libresoc.v:41927$1526_Y + attribute \src "libresoc.v:41929.20-41929.110" + wire $and$libresoc.v:41929$1528_Y + attribute \src "libresoc.v:41930.20-41930.123" + wire $and$libresoc.v:41930$1529_Y + attribute \src "libresoc.v:41932.20-41932.123" + wire $and$libresoc.v:41932$1531_Y + attribute \src "libresoc.v:41933.20-41933.126" + wire $and$libresoc.v:41933$1532_Y + attribute \src "libresoc.v:41935.20-41935.110" + wire $and$libresoc.v:41935$1534_Y + attribute \src "libresoc.v:41936.20-41936.123" + wire $and$libresoc.v:41936$1535_Y + attribute \src "libresoc.v:41938.20-41938.123" + wire $and$libresoc.v:41938$1537_Y + attribute \src "libresoc.v:41939.20-41939.126" + wire $and$libresoc.v:41939$1538_Y + attribute \src "libresoc.v:41941.20-41941.110" + wire $and$libresoc.v:41941$1540_Y + attribute \src "libresoc.v:41942.20-41942.123" + wire $and$libresoc.v:41942$1541_Y + attribute \src "libresoc.v:41944.20-41944.113" + wire $and$libresoc.v:41944$1543_Y + attribute \src "libresoc.v:41945.20-41945.126" + wire $and$libresoc.v:41945$1544_Y + attribute \src "libresoc.v:41947.20-41947.110" + wire $and$libresoc.v:41947$1546_Y + attribute \src "libresoc.v:41948.20-41948.123" + wire $and$libresoc.v:41948$1547_Y + attribute \src "libresoc.v:41950.20-41950.114" + wire $and$libresoc.v:41950$1549_Y + attribute \src "libresoc.v:41951.20-41951.126" + wire $and$libresoc.v:41951$1550_Y + attribute \src "libresoc.v:41953.20-41953.110" + wire $and$libresoc.v:41953$1552_Y + attribute \src "libresoc.v:41954.20-41954.123" + wire $and$libresoc.v:41954$1553_Y + attribute \src "libresoc.v:41983.20-41983.123" + wire $and$libresoc.v:41983$1582_Y + attribute \src "libresoc.v:41984.20-41984.128" + wire $and$libresoc.v:41984$1583_Y + attribute \src "libresoc.v:41985.20-41985.133" + wire $and$libresoc.v:41985$1584_Y + attribute \src "libresoc.v:41987.20-41987.110" + wire $and$libresoc.v:41987$1586_Y + attribute \src "libresoc.v:41988.20-41988.128" + wire $and$libresoc.v:41988$1587_Y + attribute \src "libresoc.v:41990.20-41990.116" + wire $and$libresoc.v:41990$1589_Y + attribute \src "libresoc.v:41991.20-41991.123" + wire $and$libresoc.v:41991$1590_Y + attribute \src "libresoc.v:41992.20-41992.128" + wire $and$libresoc.v:41992$1591_Y + attribute \src "libresoc.v:41993.20-41993.128" + wire $and$libresoc.v:41993$1592_Y + attribute \src "libresoc.v:41994.20-41994.129" + wire $and$libresoc.v:41994$1593_Y + attribute \src "libresoc.v:41995.20-41995.129" + wire $and$libresoc.v:41995$1594_Y + attribute \src "libresoc.v:41996.20-41996.129" + wire $and$libresoc.v:41996$1595_Y + attribute \src "libresoc.v:41997.20-41997.130" + wire $and$libresoc.v:41997$1596_Y + attribute \src "libresoc.v:41999.20-41999.110" + wire $and$libresoc.v:41999$1598_Y + attribute \src "libresoc.v:42000.20-42000.125" + wire $and$libresoc.v:42000$1599_Y + attribute \src "libresoc.v:42004.20-42004.126" + wire $and$libresoc.v:42004$1603_Y + attribute \src "libresoc.v:42005.20-42005.130" + wire $and$libresoc.v:42005$1604_Y + attribute \src "libresoc.v:42007.20-42007.110" + wire $and$libresoc.v:42007$1606_Y + attribute \src "libresoc.v:42008.20-42008.125" + wire $and$libresoc.v:42008$1607_Y + attribute \src "libresoc.v:42012.20-42012.126" + wire $and$libresoc.v:42012$1611_Y + attribute \src "libresoc.v:42013.20-42013.130" + wire $and$libresoc.v:42013$1612_Y + attribute \src "libresoc.v:42015.20-42015.110" + wire $and$libresoc.v:42015$1614_Y + attribute \src "libresoc.v:42016.20-42016.125" + wire $and$libresoc.v:42016$1615_Y + attribute \src "libresoc.v:42020.20-42020.126" + wire $and$libresoc.v:42020$1619_Y + attribute \src "libresoc.v:42021.20-42021.130" + wire $and$libresoc.v:42021$1620_Y + attribute \src "libresoc.v:42023.20-42023.110" + wire $and$libresoc.v:42023$1622_Y + attribute \src "libresoc.v:42024.20-42024.125" + wire $and$libresoc.v:42024$1623_Y + attribute \src "libresoc.v:42028.20-42028.126" + wire $and$libresoc.v:42028$1627_Y + attribute \src "libresoc.v:42029.20-42029.130" + wire $and$libresoc.v:42029$1628_Y + attribute \src "libresoc.v:42031.20-42031.110" + wire $and$libresoc.v:42031$1630_Y + attribute \src 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$and$libresoc.v:42362$1966_Y + attribute \src "libresoc.v:42363.19-42363.114" + wire $and$libresoc.v:42363$1967_Y + attribute \src "libresoc.v:42365.19-42365.102" + wire $and$libresoc.v:42365$1969_Y + attribute \src "libresoc.v:42366.19-42366.131" + wire $and$libresoc.v:42366$1970_Y + attribute \src "libresoc.v:42368.19-42368.127" + wire $and$libresoc.v:42368$1972_Y + attribute \src "libresoc.v:42369.19-42369.114" + wire $and$libresoc.v:42369$1973_Y + attribute \src "libresoc.v:42371.19-42371.102" + wire $and$libresoc.v:42371$1975_Y + attribute \src "libresoc.v:42372.19-42372.131" + wire $and$libresoc.v:42372$1976_Y + attribute \src "libresoc.v:42374.19-42374.122" + wire $and$libresoc.v:42374$1978_Y + attribute \src "libresoc.v:42375.19-42375.114" + wire $and$libresoc.v:42375$1979_Y + attribute \src "libresoc.v:42377.19-42377.102" + wire $and$libresoc.v:42377$1981_Y + attribute \src "libresoc.v:42378.19-42378.132" + wire $and$libresoc.v:42378$1982_Y + attribute \src "libresoc.v:42380.19-42380.127" + wire $and$libresoc.v:42380$1984_Y + attribute \src "libresoc.v:42381.19-42381.114" + wire $and$libresoc.v:42381$1985_Y + attribute \src "libresoc.v:42383.19-42383.102" + wire $and$libresoc.v:42383$1987_Y + attribute \src "libresoc.v:42384.19-42384.132" + wire $and$libresoc.v:42384$1988_Y + attribute \src "libresoc.v:42386.19-42386.127" + wire $and$libresoc.v:42386$1990_Y + attribute \src "libresoc.v:42387.19-42387.114" + wire $and$libresoc.v:42387$1991_Y + attribute \src "libresoc.v:42389.19-42389.102" + wire $and$libresoc.v:42389$1993_Y + attribute \src "libresoc.v:42390.19-42390.132" + wire $and$libresoc.v:42390$1994_Y + attribute \src "libresoc.v:42392.19-42392.127" + wire $and$libresoc.v:42392$1996_Y + attribute \src "libresoc.v:42393.19-42393.114" + wire $and$libresoc.v:42393$1997_Y + attribute \src "libresoc.v:42395.19-42395.102" + wire $and$libresoc.v:42395$1999_Y + attribute \src "libresoc.v:42396.19-42396.132" + wire $and$libresoc.v:42396$2000_Y + attribute \src "libresoc.v:42398.19-42398.127" + wire $and$libresoc.v:42398$2002_Y + attribute \src "libresoc.v:42399.19-42399.114" + wire $and$libresoc.v:42399$2003_Y + attribute \src "libresoc.v:42401.19-42401.102" + wire $and$libresoc.v:42401$2005_Y + attribute \src "libresoc.v:42402.19-42402.132" + wire $and$libresoc.v:42402$2006_Y + attribute \src "libresoc.v:42404.19-42404.127" + wire $and$libresoc.v:42404$2008_Y + attribute \src "libresoc.v:42405.19-42405.114" + wire $and$libresoc.v:42405$2009_Y + attribute \src "libresoc.v:42407.19-42407.102" + wire $and$libresoc.v:42407$2011_Y + attribute \src "libresoc.v:42408.19-42408.132" + wire $and$libresoc.v:42408$2012_Y + attribute \src "libresoc.v:42410.19-42410.127" + wire $and$libresoc.v:42410$2014_Y + attribute \src "libresoc.v:42411.19-42411.114" + wire $and$libresoc.v:42411$2015_Y + attribute \src "libresoc.v:42413.19-42413.102" + wire $and$libresoc.v:42413$2017_Y + attribute \src "libresoc.v:42414.19-42414.132" + wire $and$libresoc.v:42414$2018_Y + attribute \src "libresoc.v:42416.19-42416.127" + wire $and$libresoc.v:42416$2020_Y + attribute \src "libresoc.v:42417.19-42417.114" + wire $and$libresoc.v:42417$2021_Y + attribute \src "libresoc.v:42419.19-42419.102" + wire $and$libresoc.v:42419$2023_Y + attribute \src "libresoc.v:42420.19-42420.132" + wire $and$libresoc.v:42420$2024_Y + attribute \src "libresoc.v:42422.19-42422.127" + wire $and$libresoc.v:42422$2026_Y + attribute \src "libresoc.v:42423.19-42423.114" + wire $and$libresoc.v:42423$2027_Y + attribute \src "libresoc.v:42425.19-42425.102" + wire $and$libresoc.v:42425$2029_Y + attribute \src "libresoc.v:42426.19-42426.132" + wire $and$libresoc.v:42426$2030_Y + attribute \src "libresoc.v:42447.19-42447.131" + wire $and$libresoc.v:42447$2051_Y + attribute \src "libresoc.v:42448.19-42448.119" + wire width 3 $and$libresoc.v:42448$2052_Y + attribute \src "libresoc.v:42451.19-42451.131" + wire $and$libresoc.v:42451$2055_Y + attribute \src "libresoc.v:42453.19-42453.122" + wire $and$libresoc.v:42453$2057_Y + attribute \src "libresoc.v:42454.19-42454.116" + wire $and$libresoc.v:42454$2058_Y + attribute \src "libresoc.v:42456.19-42456.102" + wire $and$libresoc.v:42456$2060_Y + attribute \src "libresoc.v:42457.19-42457.135" + wire $and$libresoc.v:42457$2061_Y + attribute \src "libresoc.v:42459.19-42459.127" + wire $and$libresoc.v:42459$2063_Y + attribute \src "libresoc.v:42460.19-42460.116" + wire $and$libresoc.v:42460$2064_Y + attribute \src "libresoc.v:42462.19-42462.102" + wire $and$libresoc.v:42462$2066_Y + attribute \src "libresoc.v:42463.19-42463.135" + wire $and$libresoc.v:42463$2067_Y + attribute \src "libresoc.v:42465.19-42465.127" + wire $and$libresoc.v:42465$2069_Y + attribute \src "libresoc.v:42466.19-42466.116" + wire $and$libresoc.v:42466$2070_Y + attribute \src "libresoc.v:42468.19-42468.102" + wire $and$libresoc.v:42468$2072_Y + attribute \src "libresoc.v:42469.19-42469.135" + wire $and$libresoc.v:42469$2073_Y + attribute \src "libresoc.v:42471.19-42471.127" + wire $and$libresoc.v:42471$2075_Y + attribute \src "libresoc.v:42472.19-42472.116" + wire $and$libresoc.v:42472$2076_Y + attribute \src "libresoc.v:42474.19-42474.102" + wire $and$libresoc.v:42474$2078_Y + attribute \src "libresoc.v:42475.19-42475.135" + wire $and$libresoc.v:42475$2079_Y + attribute \src "libresoc.v:42477.19-42477.127" + wire $and$libresoc.v:42477$2081_Y + attribute \src "libresoc.v:42478.19-42478.116" + wire $and$libresoc.v:42478$2082_Y + attribute \src "libresoc.v:42480.19-42480.102" + wire $and$libresoc.v:42480$2084_Y + attribute \src "libresoc.v:42481.19-42481.135" + wire $and$libresoc.v:42481$2085_Y + attribute \src "libresoc.v:42483.19-42483.127" + wire $and$libresoc.v:42483$2087_Y + attribute \src "libresoc.v:42484.19-42484.116" + wire $and$libresoc.v:42484$2088_Y + attribute \src "libresoc.v:42486.19-42486.102" + wire $and$libresoc.v:42486$2090_Y + attribute \src "libresoc.v:42487.19-42487.135" + wire $and$libresoc.v:42487$2091_Y + attribute \src "libresoc.v:42496.19-42496.119" + wire width 3 $and$libresoc.v:42496$2101_Y + attribute \src "libresoc.v:42499.19-42499.122" + wire $and$libresoc.v:42499$2104_Y + attribute \src "libresoc.v:42500.19-42500.116" + wire $and$libresoc.v:42500$2105_Y + attribute \src "libresoc.v:42502.19-42502.102" + wire $and$libresoc.v:42502$2107_Y + attribute \src "libresoc.v:42503.19-42503.135" + wire $and$libresoc.v:42503$2108_Y + attribute \src "libresoc.v:42505.19-42505.127" + wire $and$libresoc.v:42505$2110_Y + attribute \src "libresoc.v:42506.19-42506.116" + wire $and$libresoc.v:42506$2111_Y + attribute \src "libresoc.v:42508.19-42508.102" + wire $and$libresoc.v:42508$2113_Y + attribute \src "libresoc.v:42509.19-42509.135" + wire $and$libresoc.v:42509$2114_Y + attribute \src "libresoc.v:42511.19-42511.127" + wire $and$libresoc.v:42511$2116_Y + attribute \src "libresoc.v:42512.19-42512.116" + wire $and$libresoc.v:42512$2117_Y + attribute \src "libresoc.v:42514.19-42514.102" + wire $and$libresoc.v:42514$2119_Y + attribute \src "libresoc.v:42515.19-42515.135" + wire $and$libresoc.v:42515$2120_Y + attribute \src "libresoc.v:42520.19-42520.131" + wire $and$libresoc.v:42520$2126_Y + attribute \src "libresoc.v:42521.19-42521.119" + wire width 3 $and$libresoc.v:42521$2127_Y attribute \src "libresoc.v:42524.19-42524.127" - wire $and$libresoc.v:42524$1924_Y - attribute \src "libresoc.v:42525.19-42525.114" - wire $and$libresoc.v:42525$1925_Y + wire $and$libresoc.v:42524$2130_Y + attribute \src "libresoc.v:42525.19-42525.116" + wire $and$libresoc.v:42525$2131_Y attribute \src "libresoc.v:42527.19-42527.102" - wire $and$libresoc.v:42527$1927_Y - attribute \src "libresoc.v:42528.19-42528.131" - wire $and$libresoc.v:42528$1928_Y + wire $and$libresoc.v:42527$2133_Y + attribute \src "libresoc.v:42528.19-42528.132" + wire $and$libresoc.v:42528$2134_Y attribute \src "libresoc.v:42530.19-42530.127" - wire $and$libresoc.v:42530$1930_Y - attribute \src "libresoc.v:42531.19-42531.114" - wire $and$libresoc.v:42531$1931_Y + wire $and$libresoc.v:42530$2136_Y + attribute \src "libresoc.v:42531.19-42531.116" + wire $and$libresoc.v:42531$2137_Y attribute \src "libresoc.v:42533.19-42533.102" - wire $and$libresoc.v:42533$1933_Y - attribute \src "libresoc.v:42534.19-42534.131" - wire $and$libresoc.v:42534$1934_Y + wire $and$libresoc.v:42533$2139_Y + attribute \src "libresoc.v:42534.19-42534.132" + wire $and$libresoc.v:42534$2140_Y attribute \src "libresoc.v:42536.19-42536.127" - wire $and$libresoc.v:42536$1936_Y - attribute \src "libresoc.v:42537.19-42537.114" - wire $and$libresoc.v:42537$1937_Y + wire $and$libresoc.v:42536$2142_Y + attribute \src "libresoc.v:42537.19-42537.113" + wire $and$libresoc.v:42537$2143_Y attribute \src "libresoc.v:42539.19-42539.102" - wire $and$libresoc.v:42539$1939_Y - attribute \src "libresoc.v:42540.19-42540.131" - wire $and$libresoc.v:42540$1940_Y - attribute \src "libresoc.v:42542.19-42542.127" - wire $and$libresoc.v:42542$1942_Y - attribute \src "libresoc.v:42543.19-42543.114" - wire $and$libresoc.v:42543$1943_Y - attribute \src "libresoc.v:42545.19-42545.102" - wire $and$libresoc.v:42545$1945_Y - attribute \src "libresoc.v:42546.19-42546.131" - wire $and$libresoc.v:42546$1946_Y - attribute \src "libresoc.v:42548.19-42548.127" - wire $and$libresoc.v:42548$1948_Y - attribute \src "libresoc.v:42549.19-42549.114" - wire $and$libresoc.v:42549$1949_Y - attribute \src "libresoc.v:42551.19-42551.102" - wire $and$libresoc.v:42551$1951_Y - attribute \src "libresoc.v:42552.19-42552.131" - wire $and$libresoc.v:42552$1952_Y - attribute \src "libresoc.v:42554.19-42554.127" - wire $and$libresoc.v:42554$1954_Y - attribute \src "libresoc.v:42555.19-42555.114" - wire $and$libresoc.v:42555$1955_Y - attribute \src "libresoc.v:42557.19-42557.102" - wire $and$libresoc.v:42557$1957_Y - attribute \src "libresoc.v:42558.19-42558.131" - wire $and$libresoc.v:42558$1958_Y - attribute \src "libresoc.v:42560.19-42560.127" - wire $and$libresoc.v:42560$1960_Y - attribute \src "libresoc.v:42561.19-42561.114" - wire $and$libresoc.v:42561$1961_Y - attribute \src "libresoc.v:42563.19-42563.102" - wire $and$libresoc.v:42563$1963_Y - attribute \src "libresoc.v:42564.19-42564.131" - wire $and$libresoc.v:42564$1964_Y - attribute \src "libresoc.v:42566.19-42566.127" - wire $and$libresoc.v:42566$1966_Y - attribute \src "libresoc.v:42567.19-42567.114" - wire $and$libresoc.v:42567$1967_Y - attribute \src "libresoc.v:42569.19-42569.102" - wire $and$libresoc.v:42569$1969_Y - attribute \src "libresoc.v:42570.19-42570.131" - wire $and$libresoc.v:42570$1970_Y - attribute \src "libresoc.v:42572.19-42572.127" - wire $and$libresoc.v:42572$1972_Y - attribute \src "libresoc.v:42573.19-42573.114" - wire $and$libresoc.v:42573$1973_Y - attribute \src "libresoc.v:42575.19-42575.102" - wire $and$libresoc.v:42575$1975_Y - attribute \src "libresoc.v:42576.19-42576.131" - wire $and$libresoc.v:42576$1976_Y - attribute \src "libresoc.v:42578.19-42578.122" - wire $and$libresoc.v:42578$1978_Y - attribute \src "libresoc.v:42579.19-42579.114" - wire $and$libresoc.v:42579$1979_Y - attribute \src "libresoc.v:42581.19-42581.102" - wire $and$libresoc.v:42581$1981_Y - attribute \src "libresoc.v:42582.19-42582.132" - wire $and$libresoc.v:42582$1982_Y - attribute \src "libresoc.v:42584.19-42584.127" - wire $and$libresoc.v:42584$1984_Y - attribute \src "libresoc.v:42585.19-42585.114" - wire $and$libresoc.v:42585$1985_Y - attribute \src "libresoc.v:42587.19-42587.102" - wire $and$libresoc.v:42587$1987_Y - attribute \src "libresoc.v:42588.19-42588.132" - wire $and$libresoc.v:42588$1988_Y - attribute \src "libresoc.v:42590.19-42590.127" - wire $and$libresoc.v:42590$1990_Y - attribute \src "libresoc.v:42591.19-42591.114" - wire $and$libresoc.v:42591$1991_Y - attribute \src "libresoc.v:42593.19-42593.102" - wire $and$libresoc.v:42593$1993_Y - attribute \src "libresoc.v:42594.19-42594.132" - wire $and$libresoc.v:42594$1994_Y - attribute \src "libresoc.v:42596.19-42596.127" - wire $and$libresoc.v:42596$1996_Y - attribute \src "libresoc.v:42597.19-42597.114" - wire $and$libresoc.v:42597$1997_Y - attribute \src "libresoc.v:42599.19-42599.102" - wire $and$libresoc.v:42599$1999_Y - attribute \src "libresoc.v:42600.19-42600.132" - wire $and$libresoc.v:42600$2000_Y - attribute \src "libresoc.v:42602.19-42602.127" - wire $and$libresoc.v:42602$2002_Y - attribute \src "libresoc.v:42603.19-42603.114" - wire $and$libresoc.v:42603$2003_Y - attribute \src "libresoc.v:42605.19-42605.102" - wire $and$libresoc.v:42605$2005_Y - attribute \src "libresoc.v:42606.19-42606.132" - wire $and$libresoc.v:42606$2006_Y - attribute \src "libresoc.v:42608.19-42608.127" - wire $and$libresoc.v:42608$2008_Y - attribute \src "libresoc.v:42609.19-42609.114" - wire $and$libresoc.v:42609$2009_Y - attribute \src "libresoc.v:42611.19-42611.102" - wire $and$libresoc.v:42611$2011_Y - attribute \src "libresoc.v:42612.19-42612.132" - wire $and$libresoc.v:42612$2012_Y + wire $and$libresoc.v:42539$2145_Y + attribute \src "libresoc.v:42540.19-42540.129" + wire $and$libresoc.v:42540$2146_Y + attribute \src "libresoc.v:42544.19-42544.127" + wire $and$libresoc.v:42544$2150_Y + attribute \src "libresoc.v:42545.19-42545.113" + wire $and$libresoc.v:42545$2151_Y + attribute \src "libresoc.v:42547.19-42547.102" + wire $and$libresoc.v:42547$2153_Y + attribute \src "libresoc.v:42548.19-42548.129" + wire $and$libresoc.v:42548$2154_Y + attribute \src "libresoc.v:42553.19-42553.127" + wire $and$libresoc.v:42553$2159_Y + attribute \src "libresoc.v:42554.19-42554.113" + wire $and$libresoc.v:42554$2160_Y + attribute \src "libresoc.v:42556.19-42556.102" + wire $and$libresoc.v:42556$2162_Y + attribute \src "libresoc.v:42557.19-42557.126" + wire $and$libresoc.v:42557$2163_Y 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$eq$libresoc.v:42497$2102_Y + attribute \src "libresoc.v:42522.19-42522.115" + wire $eq$libresoc.v:42522$2128_Y + attribute \src "libresoc.v:42079.20-42079.95" + wire width 3 $extend$libresoc.v:42079$1678_Y + attribute \src "libresoc.v:42145.20-42145.95" + wire width 2 $extend$libresoc.v:42145$1745_Y + attribute \src "libresoc.v:42149.20-42149.95" + wire width 3 $extend$libresoc.v:42149$1750_Y + attribute \src "libresoc.v:42213.20-42213.95" + wire width 3 $extend$libresoc.v:42213$1815_Y + attribute \src "libresoc.v:42221.20-42221.104" + wire width 3 $extend$libresoc.v:42221$1824_Y + attribute \src "libresoc.v:42494.19-42494.93" + wire width 3 $extend$libresoc.v:42494$2098_Y + attribute \src "libresoc.v:42519.19-42519.93" + wire width 3 $extend$libresoc.v:42519$2124_Y + attribute \src "libresoc.v:42249.19-42249.103" + wire $ne$libresoc.v:42249$1853_Y + attribute \src "libresoc.v:42251.19-42251.103" + wire $ne$libresoc.v:42251$1855_Y + attribute \src "libresoc.v:41910.20-41910.106" + wire $not$libresoc.v:41910$1509_Y + attribute \src "libresoc.v:41916.20-41916.106" + wire $not$libresoc.v:41916$1515_Y + attribute \src "libresoc.v:41922.20-41922.106" + wire $not$libresoc.v:41922$1521_Y + attribute \src "libresoc.v:41928.20-41928.106" + wire $not$libresoc.v:41928$1527_Y + attribute \src "libresoc.v:41934.20-41934.106" + wire $not$libresoc.v:41934$1533_Y + attribute \src "libresoc.v:41940.20-41940.106" + wire $not$libresoc.v:41940$1539_Y + attribute \src "libresoc.v:41946.20-41946.106" + wire $not$libresoc.v:41946$1545_Y + attribute \src "libresoc.v:41952.20-41952.106" + wire $not$libresoc.v:41952$1551_Y + attribute \src "libresoc.v:41986.20-41986.106" + wire $not$libresoc.v:41986$1585_Y + attribute \src "libresoc.v:41998.20-41998.106" + wire $not$libresoc.v:41998$1597_Y + attribute \src "libresoc.v:42006.20-42006.106" + wire $not$libresoc.v:42006$1605_Y + attribute \src "libresoc.v:42014.20-42014.106" + wire $not$libresoc.v:42014$1613_Y + attribute \src "libresoc.v:42022.20-42022.106" + wire $not$libresoc.v:42022$1621_Y + attribute \src "libresoc.v:42030.20-42030.106" + wire $not$libresoc.v:42030$1629_Y + attribute \src "libresoc.v:42038.20-42038.106" + wire $not$libresoc.v:42038$1637_Y + attribute \src "libresoc.v:42059.20-42059.106" + wire $not$libresoc.v:42059$1658_Y + attribute \src "libresoc.v:42065.20-42065.106" + wire $not$libresoc.v:42065$1664_Y + attribute \src "libresoc.v:42071.20-42071.106" + wire $not$libresoc.v:42071$1670_Y + attribute \src "libresoc.v:42086.20-42086.106" + wire $not$libresoc.v:42086$1686_Y + attribute \src "libresoc.v:42092.20-42092.106" + wire $not$libresoc.v:42092$1692_Y + attribute \src "libresoc.v:42098.20-42098.106" + wire $not$libresoc.v:42098$1698_Y + attribute \src "libresoc.v:42104.20-42104.106" + wire $not$libresoc.v:42104$1704_Y attribute \src "libresoc.v:42120.20-42120.106" - wire $not$libresoc.v:42120$1515_Y + wire $not$libresoc.v:42120$1720_Y attribute \src "libresoc.v:42126.20-42126.106" - wire $not$libresoc.v:42126$1521_Y + wire $not$libresoc.v:42126$1726_Y attribute \src "libresoc.v:42132.20-42132.106" - wire $not$libresoc.v:42132$1527_Y + wire $not$libresoc.v:42132$1732_Y attribute \src "libresoc.v:42138.20-42138.106" - wire $not$libresoc.v:42138$1533_Y - attribute \src "libresoc.v:42144.20-42144.106" - wire $not$libresoc.v:42144$1539_Y - attribute \src "libresoc.v:42150.20-42150.106" - wire $not$libresoc.v:42150$1545_Y - attribute \src "libresoc.v:42156.20-42156.106" - wire $not$libresoc.v:42156$1551_Y - attribute \src "libresoc.v:42190.20-42190.106" - wire $not$libresoc.v:42190$1585_Y - attribute \src "libresoc.v:42202.20-42202.106" - wire $not$libresoc.v:42202$1597_Y - attribute \src "libresoc.v:42210.20-42210.106" - wire $not$libresoc.v:42210$1605_Y - attribute \src "libresoc.v:42218.20-42218.106" - wire $not$libresoc.v:42218$1613_Y - attribute \src "libresoc.v:42226.20-42226.106" - wire $not$libresoc.v:42226$1621_Y - attribute \src "libresoc.v:42234.20-42234.106" - wire $not$libresoc.v:42234$1629_Y - attribute \src "libresoc.v:42242.20-42242.106" - wire $not$libresoc.v:42242$1637_Y - attribute \src "libresoc.v:42263.20-42263.106" - wire $not$libresoc.v:42263$1658_Y - attribute \src "libresoc.v:42269.20-42269.106" - wire $not$libresoc.v:42269$1664_Y - attribute \src "libresoc.v:42275.20-42275.106" - wire $not$libresoc.v:42275$1670_Y - attribute \src "libresoc.v:42290.20-42290.106" - wire $not$libresoc.v:42290$1686_Y - attribute \src "libresoc.v:42296.20-42296.106" - wire $not$libresoc.v:42296$1692_Y - attribute \src "libresoc.v:42302.20-42302.106" - wire $not$libresoc.v:42302$1698_Y - attribute \src "libresoc.v:42308.20-42308.106" - wire $not$libresoc.v:42308$1704_Y - attribute \src "libresoc.v:42324.20-42324.106" - wire $not$libresoc.v:42324$1720_Y - attribute \src "libresoc.v:42330.20-42330.106" - wire $not$libresoc.v:42330$1726_Y - attribute \src "libresoc.v:42336.20-42336.106" - wire $not$libresoc.v:42336$1732_Y - attribute \src "libresoc.v:42342.20-42342.106" - wire $not$libresoc.v:42342$1738_Y - attribute \src "libresoc.v:42361.20-42361.106" - wire $not$libresoc.v:42361$1759_Y - attribute \src "libresoc.v:42367.20-42367.106" - wire $not$libresoc.v:42367$1765_Y - attribute \src "libresoc.v:42373.20-42373.106" - wire $not$libresoc.v:42373$1771_Y - attribute \src "libresoc.v:42379.20-42379.106" - wire $not$libresoc.v:42379$1777_Y - attribute \src "libresoc.v:42385.20-42385.106" - wire $not$libresoc.v:42385$1783_Y - attribute \src "libresoc.v:42405.20-42405.106" - wire $not$libresoc.v:42405$1803_Y - attribute \src "libresoc.v:42411.20-42411.106" - wire $not$libresoc.v:42411$1809_Y - attribute \src "libresoc.v:42421.20-42421.106" - wire $not$libresoc.v:42421$1820_Y - attribute \src "libresoc.v:42429.20-42429.106" - wire $not$libresoc.v:42429$1829_Y - attribute \src "libresoc.v:42466.19-42466.136" - wire width 4 $not$libresoc.v:42466$1866_Y - attribute \src "libresoc.v:42467.19-42467.192" - wire width 6 $not$libresoc.v:42467$1867_Y - attribute \src "libresoc.v:42468.19-42468.138" - wire width 3 $not$libresoc.v:42468$1868_Y - attribute \src "libresoc.v:42469.19-42469.150" - wire width 4 $not$libresoc.v:42469$1869_Y - attribute \src "libresoc.v:42476.19-42476.128" - wire width 3 $not$libresoc.v:42476$1876_Y - attribute \src "libresoc.v:42491.19-42491.159" - wire width 6 $not$libresoc.v:42491$1891_Y - attribute \src "libresoc.v:42498.19-42498.128" - wire width 3 $not$libresoc.v:42498$1898_Y - attribute \src "libresoc.v:42505.19-42505.128" - wire width 3 $not$libresoc.v:42505$1905_Y - attribute \src "libresoc.v:42516.19-42516.150" - wire width 5 $not$libresoc.v:42516$1916_Y - attribute \src "libresoc.v:42517.19-42517.134" - wire width 3 $not$libresoc.v:42517$1917_Y - attribute \src "libresoc.v:42520.19-42520.108" - wire $not$libresoc.v:42520$1920_Y - attribute \src "libresoc.v:42526.19-42526.107" - wire $not$libresoc.v:42526$1926_Y + wire $not$libresoc.v:42138$1738_Y + attribute \src "libresoc.v:42157.20-42157.106" + wire $not$libresoc.v:42157$1759_Y + attribute \src "libresoc.v:42163.20-42163.106" + wire $not$libresoc.v:42163$1765_Y + attribute \src "libresoc.v:42169.20-42169.106" + wire $not$libresoc.v:42169$1771_Y + attribute \src "libresoc.v:42175.20-42175.106" + wire $not$libresoc.v:42175$1777_Y + attribute \src "libresoc.v:42181.20-42181.106" + wire $not$libresoc.v:42181$1783_Y + attribute \src "libresoc.v:42201.20-42201.106" + wire $not$libresoc.v:42201$1803_Y + attribute \src "libresoc.v:42207.20-42207.106" + wire $not$libresoc.v:42207$1809_Y + attribute \src "libresoc.v:42217.20-42217.106" + wire $not$libresoc.v:42217$1820_Y + attribute \src "libresoc.v:42225.20-42225.106" + wire $not$libresoc.v:42225$1829_Y + attribute \src "libresoc.v:42262.19-42262.136" + wire width 4 $not$libresoc.v:42262$1866_Y + attribute \src "libresoc.v:42263.19-42263.192" + wire width 6 $not$libresoc.v:42263$1867_Y + attribute \src "libresoc.v:42264.19-42264.138" + wire width 3 $not$libresoc.v:42264$1868_Y + attribute \src "libresoc.v:42265.19-42265.150" + wire width 4 $not$libresoc.v:42265$1869_Y + attribute \src "libresoc.v:42272.19-42272.128" + wire width 3 $not$libresoc.v:42272$1876_Y + attribute \src "libresoc.v:42287.19-42287.159" + wire width 6 $not$libresoc.v:42287$1891_Y + attribute \src "libresoc.v:42294.19-42294.128" + wire width 3 $not$libresoc.v:42294$1898_Y + attribute \src "libresoc.v:42301.19-42301.128" + wire width 3 $not$libresoc.v:42301$1905_Y + attribute \src "libresoc.v:42312.19-42312.150" + wire width 5 $not$libresoc.v:42312$1916_Y + attribute \src "libresoc.v:42313.19-42313.134" + wire width 3 $not$libresoc.v:42313$1917_Y + attribute \src "libresoc.v:42316.19-42316.108" + wire $not$libresoc.v:42316$1920_Y + attribute \src "libresoc.v:42322.19-42322.107" + wire $not$libresoc.v:42322$1926_Y + attribute \src "libresoc.v:42328.19-42328.109" + wire $not$libresoc.v:42328$1932_Y + attribute \src "libresoc.v:42334.19-42334.112" + wire $not$libresoc.v:42334$1938_Y + attribute \src "libresoc.v:42340.19-42340.108" + wire $not$libresoc.v:42340$1944_Y + attribute \src "libresoc.v:42346.19-42346.108" + wire $not$libresoc.v:42346$1950_Y + attribute \src "libresoc.v:42352.19-42352.113" + wire $not$libresoc.v:42352$1956_Y + attribute \src "libresoc.v:42358.19-42358.109" + wire $not$libresoc.v:42358$1962_Y + attribute \src "libresoc.v:42364.19-42364.113" + wire $not$libresoc.v:42364$1968_Y + attribute \src "libresoc.v:42370.19-42370.109" + wire $not$libresoc.v:42370$1974_Y + attribute \src "libresoc.v:42376.19-42376.109" + wire $not$libresoc.v:42376$1980_Y + attribute \src "libresoc.v:42382.19-42382.108" + wire $not$libresoc.v:42382$1986_Y + attribute \src "libresoc.v:42388.19-42388.110" + wire $not$libresoc.v:42388$1992_Y + attribute \src "libresoc.v:42394.19-42394.113" + wire $not$libresoc.v:42394$1998_Y + attribute \src "libresoc.v:42400.19-42400.109" + wire $not$libresoc.v:42400$2004_Y + attribute \src "libresoc.v:42406.19-42406.109" + wire $not$libresoc.v:42406$2010_Y + attribute \src "libresoc.v:42412.19-42412.109" + wire $not$libresoc.v:42412$2016_Y + attribute \src "libresoc.v:42418.19-42418.114" + wire $not$libresoc.v:42418$2022_Y + attribute \src "libresoc.v:42424.19-42424.110" + wire $not$libresoc.v:42424$2028_Y + attribute \src "libresoc.v:42455.19-42455.110" + wire $not$libresoc.v:42455$2059_Y + attribute \src "libresoc.v:42461.19-42461.114" + wire $not$libresoc.v:42461$2065_Y + attribute \src "libresoc.v:42467.19-42467.110" + wire $not$libresoc.v:42467$2071_Y + attribute \src "libresoc.v:42473.19-42473.110" + wire $not$libresoc.v:42473$2077_Y + attribute \src "libresoc.v:42479.19-42479.110" + wire $not$libresoc.v:42479$2083_Y + attribute \src "libresoc.v:42485.19-42485.115" + wire $not$libresoc.v:42485$2089_Y + attribute \src "libresoc.v:42501.19-42501.110" + wire $not$libresoc.v:42501$2106_Y + attribute \src "libresoc.v:42507.19-42507.110" + wire $not$libresoc.v:42507$2112_Y + attribute \src "libresoc.v:42513.19-42513.115" + wire $not$libresoc.v:42513$2118_Y + attribute \src "libresoc.v:42526.19-42526.110" + wire $not$libresoc.v:42526$2132_Y attribute \src "libresoc.v:42532.19-42532.109" - wire $not$libresoc.v:42532$1932_Y - attribute \src "libresoc.v:42538.19-42538.112" - wire $not$libresoc.v:42538$1938_Y - attribute \src "libresoc.v:42544.19-42544.108" - wire $not$libresoc.v:42544$1944_Y - attribute \src "libresoc.v:42550.19-42550.108" - wire $not$libresoc.v:42550$1950_Y - attribute \src "libresoc.v:42556.19-42556.113" - wire $not$libresoc.v:42556$1956_Y - attribute \src "libresoc.v:42562.19-42562.109" - wire $not$libresoc.v:42562$1962_Y - attribute \src "libresoc.v:42568.19-42568.113" - wire $not$libresoc.v:42568$1968_Y - attribute \src "libresoc.v:42574.19-42574.109" - wire $not$libresoc.v:42574$1974_Y - attribute \src "libresoc.v:42580.19-42580.109" - wire $not$libresoc.v:42580$1980_Y - attribute \src "libresoc.v:42586.19-42586.108" - wire $not$libresoc.v:42586$1986_Y - attribute \src "libresoc.v:42592.19-42592.110" - wire $not$libresoc.v:42592$1992_Y - attribute \src "libresoc.v:42598.19-42598.113" - wire $not$libresoc.v:42598$1998_Y - attribute \src "libresoc.v:42604.19-42604.109" - wire $not$libresoc.v:42604$2004_Y - attribute \src "libresoc.v:42610.19-42610.109" - wire $not$libresoc.v:42610$2010_Y - attribute \src "libresoc.v:42616.19-42616.109" - wire $not$libresoc.v:42616$2016_Y - attribute \src "libresoc.v:42622.19-42622.114" - wire $not$libresoc.v:42622$2022_Y - attribute \src "libresoc.v:42628.19-42628.110" - wire $not$libresoc.v:42628$2028_Y - attribute \src "libresoc.v:42659.19-42659.110" - wire $not$libresoc.v:42659$2059_Y - attribute \src "libresoc.v:42665.19-42665.114" - wire $not$libresoc.v:42665$2065_Y - attribute \src "libresoc.v:42671.19-42671.110" - wire $not$libresoc.v:42671$2071_Y - attribute \src "libresoc.v:42677.19-42677.110" - wire $not$libresoc.v:42677$2077_Y - attribute \src "libresoc.v:42683.19-42683.110" - wire $not$libresoc.v:42683$2083_Y - attribute \src "libresoc.v:42689.19-42689.115" - wire $not$libresoc.v:42689$2089_Y - attribute \src "libresoc.v:42705.19-42705.110" - wire $not$libresoc.v:42705$2106_Y - attribute \src "libresoc.v:42711.19-42711.110" - wire $not$libresoc.v:42711$2112_Y - attribute \src "libresoc.v:42717.19-42717.115" - wire $not$libresoc.v:42717$2118_Y - attribute \src "libresoc.v:42730.19-42730.110" - wire $not$libresoc.v:42730$2132_Y - attribute \src "libresoc.v:42736.19-42736.109" - wire $not$libresoc.v:42736$2138_Y - attribute \src "libresoc.v:42742.19-42742.106" - wire $not$libresoc.v:42742$2144_Y - attribute \src "libresoc.v:42750.19-42750.110" - wire $not$libresoc.v:42750$2152_Y - attribute \src "libresoc.v:42759.19-42759.106" - wire $not$libresoc.v:42759$2161_Y - attribute \src "libresoc.v:42767.19-42767.106" - wire $not$libresoc.v:42767$2169_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1084 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1087 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1091 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1093 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1099 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1144 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1147 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1155 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 65 \$1157 @@ -60569,127 +60569,127 @@ module \core wire \$1209 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1211 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1213 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1215 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1218 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1221 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1226 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 8 \$1229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1231 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1233 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1235 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1237 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1239 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1241 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1243 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1246 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1249 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1251 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1254 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1257 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1259 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1261 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1263 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1266 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1269 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1271 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1274 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1277 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1279 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1281 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1283 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1286 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1289 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1291 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1294 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1297 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1299 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1301 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1303 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1306 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1309 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1311 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1314 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1317 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1319 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1321 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1323 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1326 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1329 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1331 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1334 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1337 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1339 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1341 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1343 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1346 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1349 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1351 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1354 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1357 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1359 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1361 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$1363 @@ -60713,47 +60713,47 @@ module \core wire width 256 \$1380 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 256 \$1382 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1384 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1386 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1388 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1390 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1393 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1396 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1398 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1401 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 2 \$1404 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1406 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1409 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1412 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1414 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1417 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 2 \$1420 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1422 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1425 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1428 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1430 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1433 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 2 \$1436 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$1438 @@ -60765,61 +60765,61 @@ module \core wire width 2 \$1443 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$1445 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1448 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1450 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1452 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1454 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1456 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1459 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1462 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1464 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1470 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1472 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1475 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1478 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1480 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1483 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1486 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1488 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1491 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1494 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1496 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1499 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1502 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1504 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1507 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1510 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1512 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1515 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1518 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$1520 @@ -60833,61 +60833,61 @@ module \core wire width 3 \$1528 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$1530 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1532 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1534 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1536 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1538 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1540 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1543 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1546 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1548 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1551 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1554 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1556 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1559 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1562 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1564 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1567 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1570 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1572 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1575 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1578 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1580 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1583 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1586 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1588 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1591 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1594 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1596 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1599 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1602 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$1604 @@ -60905,75 +60905,75 @@ module \core wire \$1615 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1617 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1620 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1622 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1624 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1626 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1628 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1630 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1633 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1637 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1639 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1644 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1647 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1649 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1652 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1655 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1657 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1660 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1663 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1665 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1668 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1671 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1673 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1676 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1679 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1681 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1684 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1687 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1689 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1692 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1695 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1697 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1700 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1703 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1705 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1708 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1711 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$1713 @@ -60999,33 +60999,33 @@ module \core wire \$1733 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1735 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1737 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1739 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1741 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1744 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1747 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1749 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1752 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1755 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1757 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1760 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1763 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1765 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1768 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1771 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$1773 @@ -61033,85 +61033,85 @@ module \core wire width 3 \$1775 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1776 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1779 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1781 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1784 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1787 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1789 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1792 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 2 \$1795 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" wire width 3 \$1797 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1799 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1801 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1804 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1807 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1809 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1812 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 10 \$1815 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$201 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$209 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$213 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$217 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" wire \$221 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" wire width 3 \$223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" wire width 3 \$224 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" wire \$226 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 4 \$228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$229 @@ -61133,13 +61133,13 @@ module \core wire \$245 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$247 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 6 \$250 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$252 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 4 \$254 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$256 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$257 @@ -61153,7 +61153,7 @@ module \core wire \$265 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 6 \$270 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$271 @@ -61183,7 +61183,7 @@ module \core wire \$295 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$297 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$300 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$301 @@ -61197,7 +61197,7 @@ module \core wire \$309 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$311 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$314 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$315 @@ -61211,7 +61211,7 @@ module \core wire \$323 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$325 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 5 \$328 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$329 @@ -61233,235 +61233,235 @@ module \core wire \$345 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$347 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$350 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$352 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$354 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$356 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$358 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$360 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$362 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$364 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$366 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$368 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$370 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$372 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$374 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$376 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$378 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$380 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$382 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$384 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$386 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$388 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$390 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$392 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$394 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$396 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$398 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$400 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$402 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$404 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$406 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$408 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$410 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$412 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$414 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$416 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$418 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$420 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$422 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$424 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$426 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$428 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$430 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$432 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$434 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$436 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$438 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$440 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$442 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$444 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$446 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$448 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$450 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$452 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$454 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$456 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$458 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$460 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$462 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$464 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$466 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$468 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$470 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$472 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$474 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$476 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$478 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$480 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$482 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$484 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$486 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$488 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$490 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$492 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$494 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$496 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$498 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$500 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$502 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$504 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$506 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$508 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$510 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$512 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$514 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$516 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$518 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$520 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$522 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$524 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$526 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$528 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$530 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$532 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$534 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$536 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$538 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$540 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$542 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$544 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$546 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$548 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$550 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$552 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$554 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$556 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$558 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$560 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$562 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$564 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$566 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$568 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$570 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$572 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$574 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$576 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$578 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$580 @@ -61501,7 +61501,7 @@ module \core wire width 7 \$613 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$615 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire \$617 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$619 @@ -61515,77 +61515,77 @@ module \core wire \$627 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$629 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$631 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$633 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$635 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$637 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$639 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$641 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$643 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$645 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$647 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$649 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$651 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$653 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$655 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$657 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$659 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$661 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$663 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$665 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$667 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$669 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$671 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$673 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$675 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$677 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$679 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$681 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$683 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$685 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$687 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$689 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$691 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$693 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$695 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$697 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$699 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$701 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$703 @@ -61607,41 +61607,41 @@ module \core wire \$719 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$721 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$723 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$725 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$727 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$729 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$731 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 2 \$733 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$735 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$737 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$739 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$741 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$743 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 2 \$745 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$747 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$749 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$751 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$753 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$755 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 2 \$757 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$759 @@ -61657,157 +61657,157 @@ module \core wire \$769 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" wire \$771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$773 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$775 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$777 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$779 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$781 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 3 \$783 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$785 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$787 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$789 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$791 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$793 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 8 \$795 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$797 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$799 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$801 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$803 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$805 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" wire width 8 \$807 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" wire width 256 \$809 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 256 \$811 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$813 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$815 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$817 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$819 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$821 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" wire width 8 \$823 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" wire width 256 \$825 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 256 \$827 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 256 \$829 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 256 \$830 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$832 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$834 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$836 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$838 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$840 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" wire width 8 \$842 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" wire width 256 \$844 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 256 \$846 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$848 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$850 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$852 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$854 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$856 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" wire width 8 \$858 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" wire width 256 \$860 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 256 \$862 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$864 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$866 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$868 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$870 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$872 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 3 \$874 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$876 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$878 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$880 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$882 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$884 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 3 \$886 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$888 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$890 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$892 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$894 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$896 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 3 \$898 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$900 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$902 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$904 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$906 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$908 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 3 \$910 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$912 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$914 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$916 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$918 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$920 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 3 \$922 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 3 \$924 @@ -61817,219 +61817,219 @@ module \core wire width 3 \$928 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$930 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire \$932 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$934 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$936 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$938 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$940 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$942 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 10 \$944 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire \$946 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$948 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$950 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$952 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$954 - attribute \src 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\addr_en_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_FAST_fast1_branch0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_FAST_fast1_trap0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_alu0_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_cr0_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_div0_15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_ldst0_18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_ldst0_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_logical0_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_mul0_16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_shiftrot0_17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_shiftrot0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_spr0_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_trap0_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 10 \addr_en_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 2 \addr_en_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 2 \addr_en_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 2 \addr_en_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire input 67 \bigendian_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 8 \cia__data_o @@ -62222,254 +62222,50 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 16 \core_rego attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 input 25 \core_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 26 \core_spr1_ok attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 input 24 \core_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire output 14 \core_terminate_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire \core_terminate_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 input 27 \core_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" wire output 2 \corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 97 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" wire width 2 \counter - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" wire width 2 \counter$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_data_i @@ -63634,187 +63430,187 @@ module \core wire width 64 output 76 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 75 \dmi__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_branch0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_b_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_c_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_full_cr_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_branch0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_branch0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_trap0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_trap0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_alu0_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_alu0_10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_cr0_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_cr0_11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_div0_15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_div0_15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_div0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_logical0_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_logical0_13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_mul0_16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_mul0_16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_mul0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_spr0_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_spr0_14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_trap0_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_trap0_12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_SPR_spr1_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_shiftrot0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_spr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ov_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_div0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_logical0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_mul0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_shiftrot0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_spr0_2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_ldst0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_shiftrot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_trap0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \fast_dest1__addr @@ -63828,7 +63624,7 @@ module \core wire width 64 \fast_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \fast_src1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire width 10 \fu_enable attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 output 78 \full_rd2__data_o @@ -65416,11 +65212,11 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \int_dest1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 \int_src__addr + wire width 5 \int_src1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \int_src__data_o + wire width 64 \int_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \int_src__ren + wire \int_src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 81 \issue__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -65433,9 +65229,9 @@ module \core wire input 82 \issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 85 \issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" wire input 72 \issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" wire input 71 \ivalid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 15 \msr__data_o @@ -65443,113 +65239,113 @@ module \core wire width 3 input 13 \msr__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_branch0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_trap0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_alu0_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_cr0_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_div0_15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_ldst0_18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_ldst0_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_logical0_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_mul0_16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_shiftrot0_17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_shiftrot0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_spr0_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_trap0_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" wire width 32 input 66 \raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_cr_a_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_cr_b_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_cr_c_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_full_cr_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_FAST_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_FAST_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_INT_rabc_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_INT_rabc_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_INT_rabc_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_SPR_spr1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_XER_xer_ca_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_XER_xer_ov_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_XER_xer_so_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_CR_cr_a_en_o @@ -65611,85 +65407,85 @@ module \core wire width 6 \rdpick_XER_xer_so_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 6 \rdpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_branch0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_trap0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_alu0_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_cr0_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_div0_15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_ldst0_18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_ldst0_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_logical0_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_mul0_16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_shiftrot0_17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_shiftrot0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_spr0_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_trap0_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \spr_spr1__addr @@ -65715,7 +65511,7 @@ module \core wire width 64 output 10 \sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 9 \sv__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire input 68 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \sv_a_nz$176 @@ -65733,153 +65529,153 @@ module \core wire width 3 input 11 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 69 \wen$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1018 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1036 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1058 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1078 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1098 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1225 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1253 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1273 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1293 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1313 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1333 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1353 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1400 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1416 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1432 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1466 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1482 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1498 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1514 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1550 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1566 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1582 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1598 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1643 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1659 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1675 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1691 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1707 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1751 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1767 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1791 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1811 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$997 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1005 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1026 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1044 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1066 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1086 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1217 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1245 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1285 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1305 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1325 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1345 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1392 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1408 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1424 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1458 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1474 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1490 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1506 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1542 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1558 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1574 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1590 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1632 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1651 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1667 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1683 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1699 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1743 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1759 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1783 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1803 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$986 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly @@ -66103,79 +65899,79 @@ module \core wire \wr_pick_rise$995 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$996 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_xer_ov_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_xer_so_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_branch0_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_branch0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_branch0_nia_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_cr0_cr_a_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_cr0_full_cr_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_cr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_ldst0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_ldst0_o_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_logical0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_logical0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_shiftrot0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_shiftrot0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_shiftrot0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_spr1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_xer_ca_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_xer_ov_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_msr_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_nia_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_o_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_CR_cr_a_en_o @@ -66261,8 +66057,8 @@ module \core wire width 3 \xer_wen$171 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_wen$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42112$1507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41908$1507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66270,10 +66066,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$95 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42112$1507_Y + connect \Y $and$libresoc.v:41908$1507_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42113$1508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41909$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66281,10 +66077,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [2] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42113$1508_Y + connect \Y $and$libresoc.v:41909$1508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42115$1510 + cell $and $and$libresoc.v:41911$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66292,10 +66088,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1005 connect \B \$1010 - connect \Y $and$libresoc.v:42115$1510_Y + connect \Y $and$libresoc.v:41911$1510_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42116$1511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41912$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66303,10 +66099,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1005 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42116$1511_Y + connect \Y $and$libresoc.v:41912$1511_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42118$1513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41914$1513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66314,10 +66110,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$98 connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:42118$1513_Y + connect \Y $and$libresoc.v:41914$1513_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42119$1514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41915$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66325,10 +66121,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42119$1514_Y + connect \Y $and$libresoc.v:41915$1514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42121$1516 + cell $and $and$libresoc.v:41917$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66336,10 +66132,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1026 connect \B \$1031 - connect \Y $and$libresoc.v:42121$1516_Y + connect \Y $and$libresoc.v:41917$1516_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42122$1517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41918$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66347,10 +66143,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1026 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42122$1517_Y + connect \Y $and$libresoc.v:41918$1517_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42124$1519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41920$1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66358,10 +66154,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$101 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42124$1519_Y + connect \Y $and$libresoc.v:41920$1519_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42125$1520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41921$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66369,10 +66165,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [4] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42125$1520_Y + connect \Y $and$libresoc.v:41921$1520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42127$1522 + cell $and $and$libresoc.v:41923$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66380,10 +66176,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1044 connect \B \$1049 - connect \Y $and$libresoc.v:42127$1522_Y + connect \Y $and$libresoc.v:41923$1522_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42128$1523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41924$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66391,10 +66187,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1044 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42128$1523_Y + connect \Y $and$libresoc.v:41924$1523_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42130$1525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41926$1525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66402,10 +66198,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$104 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42130$1525_Y + connect \Y $and$libresoc.v:41926$1525_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42131$1526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41927$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66413,10 +66209,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [5] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42131$1526_Y + connect \Y $and$libresoc.v:41927$1526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42133$1528 + cell $and $and$libresoc.v:41929$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66424,10 +66220,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1066 connect \B \$1071 - connect \Y $and$libresoc.v:42133$1528_Y + connect \Y $and$libresoc.v:41929$1528_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42134$1529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41930$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66435,10 +66231,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1066 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42134$1529_Y + connect \Y $and$libresoc.v:41930$1529_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42136$1531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41932$1531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66446,10 +66242,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$107 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42136$1531_Y + connect \Y $and$libresoc.v:41932$1531_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42137$1532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41933$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66457,10 +66253,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42137$1532_Y + connect \Y $and$libresoc.v:41933$1532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42139$1534 + cell $and $and$libresoc.v:41935$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66468,10 +66264,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1086 connect \B \$1091 - connect \Y $and$libresoc.v:42139$1534_Y + connect \Y $and$libresoc.v:41935$1534_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42140$1535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41936$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66479,10 +66275,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1086 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42140$1535_Y + connect \Y $and$libresoc.v:41936$1535_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42142$1537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41938$1537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66490,10 +66286,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$110 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:42142$1537_Y + connect \Y $and$libresoc.v:41938$1537_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42143$1538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41939$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66501,10 +66297,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [7] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42143$1538_Y + connect \Y $and$libresoc.v:41939$1538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42145$1540 + cell $and $and$libresoc.v:41941$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66512,10 +66308,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1106 connect \B \$1111 - connect \Y $and$libresoc.v:42145$1540_Y + connect \Y $and$libresoc.v:41941$1540_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42146$1541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41942$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66523,10 +66319,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1106 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42146$1541_Y + connect \Y $and$libresoc.v:41942$1541_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42148$1543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41944$1543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66534,10 +66330,10 @@ module \core parameter \Y_WIDTH 1 connect \A \o_ok connect \B \fus_cu_busy_o$38 - connect \Y $and$libresoc.v:42148$1543_Y + connect \Y $and$libresoc.v:41944$1543_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42149$1544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41945$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66545,10 +66341,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [8] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42149$1544_Y + connect \Y $and$libresoc.v:41945$1544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42151$1546 + cell $and $and$libresoc.v:41947$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66556,10 +66352,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1125 connect \B \$1130 - connect \Y $and$libresoc.v:42151$1546_Y + connect \Y $and$libresoc.v:41947$1546_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42152$1547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41948$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66567,10 +66363,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1125 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42152$1547_Y + connect \Y $and$libresoc.v:41948$1547_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42154$1549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41950$1549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66578,10 +66374,10 @@ module \core parameter \Y_WIDTH 1 connect \A \ea_ok connect \B \fus_cu_busy_o$38 - connect \Y $and$libresoc.v:42154$1549_Y + connect \Y $and$libresoc.v:41950$1549_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42155$1550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41951$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66589,10 +66385,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [9] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42155$1550_Y + connect \Y $and$libresoc.v:41951$1550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42157$1552 + cell $and $and$libresoc.v:41953$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66600,10 +66396,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1143 connect \B \$1147 - connect \Y $and$libresoc.v:42157$1552_Y + connect \Y $and$libresoc.v:41953$1552_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42158$1553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41954$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66611,10 +66407,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1143 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42158$1553_Y + connect \Y $and$libresoc.v:41954$1553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42187$1582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41983$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66622,10 +66418,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_full_cr_ok connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:42187$1582_Y + connect \Y $and$libresoc.v:41983$1582_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42188$1583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41984$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66633,10 +66429,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42188$1583_Y + connect \Y $and$libresoc.v:41984$1583_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42189$1584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41985$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66644,10 +66440,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42189$1584_Y + connect \Y $and$libresoc.v:41985$1584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42191$1586 + cell $and $and$libresoc.v:41987$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66655,10 +66451,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1217 connect \B \$1221 - connect \Y $and$libresoc.v:42191$1586_Y + connect \Y $and$libresoc.v:41987$1586_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42192$1587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41988$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66666,10 +66462,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1217 connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42192$1587_Y + connect \Y $and$libresoc.v:41988$1587_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42194$1589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41990$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66677,10 +66473,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42194$1589_Y + connect \Y $and$libresoc.v:41990$1589_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42195$1590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41991$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66688,10 +66484,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42195$1590_Y + connect \Y $and$libresoc.v:41991$1590_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42196$1591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41992$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66699,10 +66495,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42196$1591_Y + connect \Y $and$libresoc.v:41992$1591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42197$1592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41993$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66710,10 +66506,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42197$1592_Y + connect \Y $and$libresoc.v:41993$1592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42198$1593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41994$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66721,10 +66517,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42198$1593_Y + connect \Y $and$libresoc.v:41994$1593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42199$1594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41995$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66732,10 +66528,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42199$1594_Y + connect \Y $and$libresoc.v:41995$1594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42200$1595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41996$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66743,10 +66539,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42200$1595_Y + connect \Y $and$libresoc.v:41996$1595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42201$1596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41997$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66754,10 +66550,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42201$1596_Y + connect \Y $and$libresoc.v:41997$1596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42203$1598 + cell $and $and$libresoc.v:41999$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66765,10 +66561,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1245 connect \B \$1249 - connect \Y $and$libresoc.v:42203$1598_Y + connect \Y $and$libresoc.v:41999$1598_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42204$1599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42000$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66776,10 +66572,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1245 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42204$1599_Y + connect \Y $and$libresoc.v:42000$1599_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42208$1603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42004$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66787,10 +66583,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$122 connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:42208$1603_Y + connect \Y $and$libresoc.v:42004$1603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42209$1604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42005$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66798,10 +66594,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42209$1604_Y + connect \Y $and$libresoc.v:42005$1604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42211$1606 + cell $and $and$libresoc.v:42007$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66809,10 +66605,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1265 connect \B \$1269 - connect \Y $and$libresoc.v:42211$1606_Y + connect \Y $and$libresoc.v:42007$1606_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42212$1607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42008$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66820,10 +66616,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1265 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42212$1607_Y + connect \Y $and$libresoc.v:42008$1607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42216$1611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42012$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66831,10 +66627,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$123 connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:42216$1611_Y + connect \Y $and$libresoc.v:42012$1611_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42217$1612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42013$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66842,10 +66638,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42217$1612_Y + connect \Y $and$libresoc.v:42013$1612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42219$1614 + cell $and $and$libresoc.v:42015$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66853,10 +66649,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1285 connect \B \$1289 - connect \Y $and$libresoc.v:42219$1614_Y + connect \Y $and$libresoc.v:42015$1614_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42220$1615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42016$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66864,10 +66660,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1285 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42220$1615_Y + connect \Y $and$libresoc.v:42016$1615_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42224$1619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42020$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66875,10 +66671,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$124 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42224$1619_Y + connect \Y $and$libresoc.v:42020$1619_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42225$1620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42021$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66886,10 +66682,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42225$1620_Y + connect \Y $and$libresoc.v:42021$1620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42227$1622 + cell $and $and$libresoc.v:42023$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66897,10 +66693,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1305 connect \B \$1309 - connect \Y $and$libresoc.v:42227$1622_Y + connect \Y $and$libresoc.v:42023$1622_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42228$1623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42024$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66908,10 +66704,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1305 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42228$1623_Y + connect \Y $and$libresoc.v:42024$1623_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42232$1627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42028$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66919,10 +66715,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$125 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42232$1627_Y + connect \Y $and$libresoc.v:42028$1627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42233$1628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42029$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66930,10 +66726,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [4] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42233$1628_Y + connect \Y $and$libresoc.v:42029$1628_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42235$1630 + cell $and $and$libresoc.v:42031$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66941,10 +66737,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1325 connect \B \$1329 - connect \Y $and$libresoc.v:42235$1630_Y + connect \Y $and$libresoc.v:42031$1630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42236$1631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42032$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66952,10 +66748,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1325 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42236$1631_Y + connect \Y $and$libresoc.v:42032$1631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42240$1635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42036$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66963,10 +66759,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$126 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:42240$1635_Y + connect \Y $and$libresoc.v:42036$1635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42241$1636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42037$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66974,10 +66770,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [5] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42241$1636_Y + connect \Y $and$libresoc.v:42037$1636_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42243$1638 + cell $and $and$libresoc.v:42039$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66985,10 +66781,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1345 connect \B \$1349 - connect \Y $and$libresoc.v:42243$1638_Y + connect \Y $and$libresoc.v:42039$1638_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42244$1639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42040$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66996,10 +66792,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1345 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42244$1639_Y + connect \Y $and$libresoc.v:42040$1639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42258$1653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42054$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67007,10 +66803,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42258$1653_Y + connect \Y $and$libresoc.v:42054$1653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42259$1654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42055$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67018,10 +66814,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42259$1654_Y + connect \Y $and$libresoc.v:42055$1654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42260$1655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42056$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67029,10 +66825,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42260$1655_Y + connect \Y $and$libresoc.v:42056$1655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42261$1656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42057$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67040,10 +66836,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42261$1656_Y + connect \Y $and$libresoc.v:42057$1656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42262$1657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42058$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67051,10 +66847,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42262$1657_Y + connect \Y $and$libresoc.v:42058$1657_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42264$1659 + cell $and $and$libresoc.v:42060$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67062,10 +66858,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1392 connect \B \$1396 - connect \Y $and$libresoc.v:42264$1659_Y + connect \Y $and$libresoc.v:42060$1659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42265$1660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42061$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67073,10 +66869,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1392 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42265$1660_Y + connect \Y $and$libresoc.v:42061$1660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42267$1662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42063$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67084,10 +66880,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$132 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42267$1662_Y + connect \Y $and$libresoc.v:42063$1662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42268$1663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42064$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67095,10 +66891,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42268$1663_Y + connect \Y $and$libresoc.v:42064$1663_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42270$1665 + cell $and $and$libresoc.v:42066$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67106,10 +66902,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1408 connect \B \$1412 - connect \Y $and$libresoc.v:42270$1665_Y + connect \Y $and$libresoc.v:42066$1665_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42271$1666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42067$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67117,10 +66913,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1408 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42271$1666_Y + connect \Y $and$libresoc.v:42067$1666_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42273$1668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42069$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67128,10 +66924,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$133 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:42273$1668_Y + connect \Y $and$libresoc.v:42069$1668_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42274$1669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42070$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67139,10 +66935,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [2] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42274$1669_Y + connect \Y $and$libresoc.v:42070$1669_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42276$1671 + cell $and $and$libresoc.v:42072$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67150,10 +66946,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1424 connect \B \$1428 - connect \Y $and$libresoc.v:42276$1671_Y + connect \Y $and$libresoc.v:42072$1671_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42277$1672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42073$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67161,10 +66957,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1424 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42277$1672_Y + connect \Y $and$libresoc.v:42073$1672_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42284$1680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42080$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67172,10 +66968,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42284$1680_Y + connect \Y $and$libresoc.v:42080$1680_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42285$1681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42081$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67183,10 +66979,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42285$1681_Y + connect \Y $and$libresoc.v:42081$1681_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42286$1682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42082$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67194,10 +66990,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42286$1682_Y + connect \Y $and$libresoc.v:42082$1682_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42287$1683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42083$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67205,10 +67001,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42287$1683_Y + connect \Y $and$libresoc.v:42083$1683_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42288$1684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42084$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67216,10 +67012,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42288$1684_Y + connect \Y $and$libresoc.v:42084$1684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42289$1685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42085$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67227,10 +67023,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42289$1685_Y + connect \Y $and$libresoc.v:42085$1685_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42291$1687 + cell $and $and$libresoc.v:42087$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67238,10 +67034,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1458 connect \B \$1462 - connect \Y $and$libresoc.v:42291$1687_Y + connect \Y $and$libresoc.v:42087$1687_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42292$1688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42088$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67249,10 +67045,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1458 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42292$1688_Y + connect \Y $and$libresoc.v:42088$1688_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42294$1690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42090$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67260,10 +67056,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$136 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42294$1690_Y + connect \Y $and$libresoc.v:42090$1690_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42295$1691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42091$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67271,10 +67067,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [1] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42295$1691_Y + connect \Y $and$libresoc.v:42091$1691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42297$1693 + cell $and $and$libresoc.v:42093$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67282,10 +67078,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1474 connect \B \$1478 - connect \Y $and$libresoc.v:42297$1693_Y + connect \Y $and$libresoc.v:42093$1693_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42298$1694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42094$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67293,10 +67089,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1474 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42298$1694_Y + connect \Y $and$libresoc.v:42094$1694_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42300$1696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42096$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67304,10 +67100,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$137 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42300$1696_Y + connect \Y $and$libresoc.v:42096$1696_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42301$1697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42097$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67315,10 +67111,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [2] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42301$1697_Y + connect \Y $and$libresoc.v:42097$1697_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42303$1699 + cell $and $and$libresoc.v:42099$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67326,10 +67122,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1490 connect \B \$1494 - connect \Y $and$libresoc.v:42303$1699_Y + connect \Y $and$libresoc.v:42099$1699_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42304$1700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42100$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67337,10 +67133,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1490 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42304$1700_Y + connect \Y $and$libresoc.v:42100$1700_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42306$1702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42102$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67348,10 +67144,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$138 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42306$1702_Y + connect \Y $and$libresoc.v:42102$1702_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42307$1703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42103$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67359,10 +67155,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [3] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42307$1703_Y + connect \Y $and$libresoc.v:42103$1703_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42309$1705 + cell $and $and$libresoc.v:42105$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67370,10 +67166,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1506 connect \B \$1510 - connect \Y $and$libresoc.v:42309$1705_Y + connect \Y $and$libresoc.v:42105$1705_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42310$1706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42106$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67381,10 +67177,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1506 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42310$1706_Y + connect \Y $and$libresoc.v:42106$1706_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42318$1714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42114$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67392,10 +67188,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42318$1714_Y + connect \Y $and$libresoc.v:42114$1714_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42319$1715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42115$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67403,10 +67199,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [4] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42319$1715_Y + connect \Y $and$libresoc.v:42115$1715_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42320$1716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42116$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67414,10 +67210,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42320$1716_Y + connect \Y $and$libresoc.v:42116$1716_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42321$1717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42117$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67425,10 +67221,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [3] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42321$1717_Y + connect \Y $and$libresoc.v:42117$1717_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42322$1718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42118$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67436,10 +67232,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [3] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42322$1718_Y + connect \Y $and$libresoc.v:42118$1718_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42323$1719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42119$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67447,10 +67243,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42323$1719_Y + connect \Y $and$libresoc.v:42119$1719_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42325$1721 + cell $and $and$libresoc.v:42121$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67458,10 +67254,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1542 connect \B \$1546 - connect \Y $and$libresoc.v:42325$1721_Y + connect \Y $and$libresoc.v:42121$1721_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42326$1722 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42122$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67469,10 +67265,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1542 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42326$1722_Y + connect \Y $and$libresoc.v:42122$1722_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42328$1724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42124$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67480,10 +67276,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$141 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42328$1724_Y + connect \Y $and$libresoc.v:42124$1724_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42329$1725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42125$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67491,10 +67287,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [1] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42329$1725_Y + connect \Y $and$libresoc.v:42125$1725_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42331$1727 + cell $and $and$libresoc.v:42127$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67502,10 +67298,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1558 connect \B \$1562 - connect \Y $and$libresoc.v:42331$1727_Y + connect \Y $and$libresoc.v:42127$1727_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42332$1728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42128$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67513,10 +67309,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1558 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42332$1728_Y + connect \Y $and$libresoc.v:42128$1728_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42334$1730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42130$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67524,10 +67320,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$142 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42334$1730_Y + connect \Y $and$libresoc.v:42130$1730_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42335$1731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42131$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67535,10 +67331,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [2] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42335$1731_Y + connect \Y $and$libresoc.v:42131$1731_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42337$1733 + cell $and $and$libresoc.v:42133$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67546,10 +67342,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1574 connect \B \$1578 - connect \Y $and$libresoc.v:42337$1733_Y + connect \Y $and$libresoc.v:42133$1733_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42338$1734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42134$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67557,10 +67353,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1574 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42338$1734_Y + connect \Y $and$libresoc.v:42134$1734_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42340$1736 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42136$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67568,10 +67364,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$143 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42340$1736_Y + connect \Y $and$libresoc.v:42136$1736_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42341$1737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42137$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67579,10 +67375,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [3] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42341$1737_Y + connect \Y $and$libresoc.v:42137$1737_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42343$1739 + cell $and $and$libresoc.v:42139$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67590,10 +67386,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1590 connect \B \$1594 - connect \Y $and$libresoc.v:42343$1739_Y + connect \Y $and$libresoc.v:42139$1739_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42344$1740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42140$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67601,10 +67397,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1590 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42344$1740_Y + connect \Y $and$libresoc.v:42140$1740_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42354$1752 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42150$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67612,10 +67408,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42354$1752_Y + connect \Y $and$libresoc.v:42150$1752_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42355$1753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42151$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67623,10 +67419,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42355$1753_Y + connect \Y $and$libresoc.v:42151$1753_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42356$1754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42152$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67634,10 +67430,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42356$1754_Y + connect \Y $and$libresoc.v:42152$1754_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42357$1755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42153$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67645,10 +67441,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42357$1755_Y + connect \Y $and$libresoc.v:42153$1755_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42358$1756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42154$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67656,10 +67452,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42358$1756_Y + connect \Y $and$libresoc.v:42154$1756_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42359$1757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42155$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67667,10 +67463,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42359$1757_Y + connect \Y $and$libresoc.v:42155$1757_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42360$1758 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42156$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67678,10 +67474,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [0] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42360$1758_Y + connect \Y $and$libresoc.v:42156$1758_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42362$1760 + cell $and $and$libresoc.v:42158$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67689,10 +67485,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1632 connect \B \$1637 - connect \Y $and$libresoc.v:42362$1760_Y + connect \Y $and$libresoc.v:42158$1760_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42363$1761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42159$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67700,10 +67496,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1632 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42363$1761_Y + connect \Y $and$libresoc.v:42159$1761_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42365$1763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42161$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67711,10 +67507,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$150 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42365$1763_Y + connect \Y $and$libresoc.v:42161$1763_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42366$1764 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42162$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67722,10 +67518,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [1] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42366$1764_Y + connect \Y $and$libresoc.v:42162$1764_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42368$1766 + cell $and $and$libresoc.v:42164$1766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67733,10 +67529,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1651 connect \B \$1655 - connect \Y $and$libresoc.v:42368$1766_Y + connect \Y $and$libresoc.v:42164$1766_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42369$1767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42165$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67744,10 +67540,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1651 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42369$1767_Y + connect \Y $and$libresoc.v:42165$1767_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42371$1769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42167$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67755,10 +67551,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$151 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42371$1769_Y + connect \Y $and$libresoc.v:42167$1769_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42372$1770 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42168$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67766,10 +67562,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [2] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42372$1770_Y + connect \Y $and$libresoc.v:42168$1770_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42374$1772 + cell $and $and$libresoc.v:42170$1772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67777,10 +67573,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1667 connect \B \$1671 - connect \Y $and$libresoc.v:42374$1772_Y + connect \Y $and$libresoc.v:42170$1772_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42375$1773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42171$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67788,10 +67584,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1667 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42375$1773_Y + connect \Y $and$libresoc.v:42171$1773_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42377$1775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42173$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67799,10 +67595,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42377$1775_Y + connect \Y $and$libresoc.v:42173$1775_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42378$1776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42174$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67810,10 +67606,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [3] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42378$1776_Y + connect \Y $and$libresoc.v:42174$1776_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42380$1778 + cell $and $and$libresoc.v:42176$1778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67821,10 +67617,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1683 connect \B \$1687 - connect \Y $and$libresoc.v:42380$1778_Y + connect \Y $and$libresoc.v:42176$1778_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42381$1779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42177$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67832,10 +67628,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1683 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42381$1779_Y + connect \Y $and$libresoc.v:42177$1779_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42383$1781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42179$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67843,10 +67639,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok$152 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42383$1781_Y + connect \Y $and$libresoc.v:42179$1781_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42384$1782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42180$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67854,10 +67650,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [4] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42384$1782_Y + connect \Y $and$libresoc.v:42180$1782_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42386$1784 + cell $and $and$libresoc.v:42182$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67865,10 +67661,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1699 connect \B \$1703 - connect \Y $and$libresoc.v:42386$1784_Y + connect \Y $and$libresoc.v:42182$1784_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42387$1785 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42183$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67876,10 +67672,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1699 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42387$1785_Y + connect \Y $and$libresoc.v:42183$1785_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42401$1799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42197$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67887,10 +67683,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42401$1799_Y + connect \Y $and$libresoc.v:42197$1799_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42402$1800 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42198$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67898,10 +67694,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42402$1800_Y + connect \Y $and$libresoc.v:42198$1800_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42403$1801 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42199$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67909,10 +67705,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42403$1801_Y + connect \Y $and$libresoc.v:42199$1801_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42404$1802 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42200$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67920,10 +67716,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [0] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42404$1802_Y + connect \Y $and$libresoc.v:42200$1802_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42406$1804 + cell $and $and$libresoc.v:42202$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67931,10 +67727,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1743 connect \B \$1747 - connect \Y $and$libresoc.v:42406$1804_Y + connect \Y $and$libresoc.v:42202$1804_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42407$1805 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42203$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67942,10 +67738,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1743 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42407$1805_Y + connect \Y $and$libresoc.v:42203$1805_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42409$1807 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42205$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67953,10 +67749,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok$158 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42409$1807_Y + connect \Y $and$libresoc.v:42205$1807_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42410$1808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42206$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67964,10 +67760,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [1] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42410$1808_Y + connect \Y $and$libresoc.v:42206$1808_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42412$1810 + cell $and $and$libresoc.v:42208$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67975,10 +67771,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1759 connect \B \$1763 - connect \Y $and$libresoc.v:42412$1810_Y + connect \Y $and$libresoc.v:42208$1810_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42413$1811 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42209$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67986,10 +67782,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1759 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42413$1811_Y + connect \Y $and$libresoc.v:42209$1811_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42418$1817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42214$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67997,10 +67793,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_msr_ok connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42418$1817_Y + connect \Y $and$libresoc.v:42214$1817_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42419$1818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42215$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68008,10 +67804,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [4] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42419$1818_Y + connect \Y $and$libresoc.v:42215$1818_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42420$1819 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42216$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68019,10 +67815,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_msr_o connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:42420$1819_Y + connect \Y $and$libresoc.v:42216$1819_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42422$1821 + cell $and $and$libresoc.v:42218$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68030,10 +67826,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1783 connect \B \$1787 - connect \Y $and$libresoc.v:42422$1821_Y + connect \Y $and$libresoc.v:42218$1821_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42423$1822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42219$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68041,10 +67837,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1783 connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:42423$1822_Y + connect \Y $and$libresoc.v:42219$1822_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42426$1826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42222$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68052,10 +67848,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_spr1_ok connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42426$1826_Y + connect \Y $and$libresoc.v:42222$1826_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42427$1827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42223$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68063,10 +67859,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42427$1827_Y + connect \Y $and$libresoc.v:42223$1827_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42428$1828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42224$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68074,10 +67870,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_SPR_spr1_o connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42428$1828_Y + connect \Y $and$libresoc.v:42224$1828_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42430$1830 + cell $and $and$libresoc.v:42226$1830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68085,10 +67881,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1803 connect \B \$1807 - connect \Y $and$libresoc.v:42430$1830_Y + connect \Y $and$libresoc.v:42226$1830_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42431$1831 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42227$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68096,10 +67892,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1803 connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42431$1831_Y + connect \Y $and$libresoc.v:42227$1831_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $and $and$libresoc.v:42433$1833 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42229$1833 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68107,10 +67903,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 2'10 - connect \Y $and$libresoc.v:42433$1833_Y + connect \Y $and$libresoc.v:42229$1833_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $and $and$libresoc.v:42435$1835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42231$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68118,10 +67914,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 7'1000000 - connect \Y $and$libresoc.v:42435$1835_Y + connect \Y $and$libresoc.v:42231$1835_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $and $and$libresoc.v:42437$1837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42233$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68129,10 +67925,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 6'100000 - connect \Y $and$libresoc.v:42437$1837_Y + connect \Y $and$libresoc.v:42233$1837_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $and $and$libresoc.v:42439$1839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42235$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68140,10 +67936,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 8'10000000 - connect \Y $and$libresoc.v:42439$1839_Y + connect \Y $and$libresoc.v:42235$1839_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $and $and$libresoc.v:42441$1841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42237$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68151,10 +67947,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 5'10000 - connect \Y $and$libresoc.v:42441$1841_Y + connect \Y $and$libresoc.v:42237$1841_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $and $and$libresoc.v:42443$1843 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42239$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68162,10 +67958,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 11'10000000000 - connect \Y $and$libresoc.v:42443$1843_Y + connect \Y $and$libresoc.v:42239$1843_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $and $and$libresoc.v:42445$1845 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42241$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68173,10 +67969,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 10'1000000000 - connect \Y $and$libresoc.v:42445$1845_Y + connect \Y $and$libresoc.v:42241$1845_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $and $and$libresoc.v:42447$1847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42243$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68184,10 +67980,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 9'100000000 - connect \Y $and$libresoc.v:42447$1847_Y + connect \Y $and$libresoc.v:42243$1847_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $and $and$libresoc.v:42449$1849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42245$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68195,10 +67991,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 4'1000 - connect \Y $and$libresoc.v:42449$1849_Y + connect \Y $and$libresoc.v:42245$1849_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $and $and$libresoc.v:42451$1851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42247$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68206,10 +68002,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 3'100 - connect \Y $and$libresoc.v:42451$1851_Y + connect \Y $and$libresoc.v:42247$1851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42456$1856 + cell $and $and$libresoc.v:42252$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68217,10 +68013,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42456$1856_Y + connect \Y $and$libresoc.v:42252$1856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42457$1857 + cell $and $and$libresoc.v:42253$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68228,10 +68024,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42457$1857_Y + connect \Y $and$libresoc.v:42253$1857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42460$1860 + cell $and $and$libresoc.v:42256$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68239,10 +68035,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42460$1860_Y + connect \Y $and$libresoc.v:42256$1860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42463$1863 + cell $and $and$libresoc.v:42259$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68250,10 +68046,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42463$1863_Y + connect \Y $and$libresoc.v:42259$1863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42470$1870 + cell $and $and$libresoc.v:42266$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68261,10 +68057,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42470$1870_Y + connect \Y $and$libresoc.v:42266$1870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42471$1871 + cell $and $and$libresoc.v:42267$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68272,10 +68068,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42471$1871_Y + connect \Y $and$libresoc.v:42267$1871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42474$1874 + cell $and $and$libresoc.v:42270$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68283,10 +68079,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42474$1874_Y + connect \Y $and$libresoc.v:42270$1874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42477$1877 + cell $and $and$libresoc.v:42273$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68294,10 +68090,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42477$1877_Y + connect \Y $and$libresoc.v:42273$1877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42478$1878 + cell $and $and$libresoc.v:42274$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68305,10 +68101,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42478$1878_Y + connect \Y $and$libresoc.v:42274$1878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42481$1881 + cell $and $and$libresoc.v:42277$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68316,10 +68112,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42481$1881_Y + connect \Y $and$libresoc.v:42277$1881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42483$1883 + cell $and $and$libresoc.v:42279$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68327,10 +68123,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42483$1883_Y + connect \Y $and$libresoc.v:42279$1883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42484$1884 + cell $and $and$libresoc.v:42280$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68338,10 +68134,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:42484$1884_Y + connect \Y $and$libresoc.v:42280$1884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42488$1888 + cell $and $and$libresoc.v:42284$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68349,10 +68145,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42488$1888_Y + connect \Y $and$libresoc.v:42284$1888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42492$1892 + cell $and $and$libresoc.v:42288$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68360,10 +68156,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42492$1892_Y + connect \Y $and$libresoc.v:42288$1892_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42493$1893 + cell $and $and$libresoc.v:42289$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68371,10 +68167,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42493$1893_Y + connect \Y $and$libresoc.v:42289$1893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42496$1896 + cell $and $and$libresoc.v:42292$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68382,10 +68178,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42496$1896_Y + connect \Y $and$libresoc.v:42292$1896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42499$1899 + cell $and $and$libresoc.v:42295$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68393,10 +68189,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42499$1899_Y + connect \Y $and$libresoc.v:42295$1899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42500$1900 + cell $and $and$libresoc.v:42296$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68404,10 +68200,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42500$1900_Y + connect \Y $and$libresoc.v:42296$1900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42503$1903 + cell $and $and$libresoc.v:42299$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68415,10 +68211,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42503$1903_Y + connect \Y $and$libresoc.v:42299$1903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42506$1906 + cell $and $and$libresoc.v:42302$1906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68426,10 +68222,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42506$1906_Y + connect \Y $and$libresoc.v:42302$1906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42507$1907 + cell $and $and$libresoc.v:42303$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68437,10 +68233,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42507$1907_Y + connect \Y $and$libresoc.v:42303$1907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42510$1910 + cell $and $and$libresoc.v:42306$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68448,10 +68244,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42510$1910_Y + connect \Y $and$libresoc.v:42306$1910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42513$1913 + cell $and $and$libresoc.v:42309$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68459,10 +68255,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42513$1913_Y + connect \Y $and$libresoc.v:42309$1913_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42518$1918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42314$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68470,10 +68266,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42518$1918_Y + connect \Y $and$libresoc.v:42314$1918_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42519$1919 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42315$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68481,10 +68277,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$352 connect \B \rdflag_INT_rabc_0 - connect \Y $and$libresoc.v:42519$1919_Y + connect \Y $and$libresoc.v:42315$1919_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42521$1921 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42317$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68492,10 +68288,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$354 connect \B \$356 - connect \Y $and$libresoc.v:42521$1921_Y + connect \Y $and$libresoc.v:42317$1921_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42522$1922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42318$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68503,10 +68299,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [0] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42522$1922_Y + connect \Y $and$libresoc.v:42318$1922_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42524$1924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42320$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68514,10 +68310,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42524$1924_Y + connect \Y $and$libresoc.v:42320$1924_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42525$1925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42321$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68525,10 +68321,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$364 connect \B \rdflag_INT_rabc_0 - connect \Y $and$libresoc.v:42525$1925_Y + connect \Y $and$libresoc.v:42321$1925_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42527$1927 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42323$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68536,10 +68332,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$366 connect \B \$368 - connect \Y $and$libresoc.v:42527$1927_Y + connect \Y $and$libresoc.v:42323$1927_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42528$1928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42324$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68547,10 +68343,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [1] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42528$1928_Y + connect \Y $and$libresoc.v:42324$1928_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42530$1930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42326$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68558,10 +68354,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42530$1930_Y + connect \Y $and$libresoc.v:42326$1930_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42531$1931 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42327$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68569,10 +68365,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$376 connect \B \rdflag_INT_rabc_0 - connect \Y $and$libresoc.v:42531$1931_Y + connect \Y $and$libresoc.v:42327$1931_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42533$1933 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42329$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68580,10 +68376,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$378 connect \B \$380 - connect \Y $and$libresoc.v:42533$1933_Y + connect \Y $and$libresoc.v:42329$1933_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42534$1934 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42330$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68591,10 +68387,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [2] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42534$1934_Y + connect \Y $and$libresoc.v:42330$1934_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42536$1936 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42332$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68602,10 +68398,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42536$1936_Y + connect \Y $and$libresoc.v:42332$1936_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42537$1937 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42333$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68613,10 +68409,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$388 connect \B \rdflag_INT_rabc_0 - connect \Y $and$libresoc.v:42537$1937_Y + connect \Y $and$libresoc.v:42333$1937_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42539$1939 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42335$1939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68624,10 +68420,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$390 connect \B \$392 - connect \Y $and$libresoc.v:42539$1939_Y + connect \Y $and$libresoc.v:42335$1939_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42540$1940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42336$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68635,10 +68431,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [3] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42540$1940_Y + connect \Y $and$libresoc.v:42336$1940_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42542$1942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42338$1942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68646,10 +68442,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42542$1942_Y + connect \Y $and$libresoc.v:42338$1942_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42543$1943 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42339$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68657,10 +68453,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$400 connect \B \rdflag_INT_rabc_0 - connect \Y $and$libresoc.v:42543$1943_Y + connect \Y $and$libresoc.v:42339$1943_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42545$1945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42341$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68668,10 +68464,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$402 connect \B \$404 - connect \Y $and$libresoc.v:42545$1945_Y + connect \Y $and$libresoc.v:42341$1945_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42546$1946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42342$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68679,10 +68475,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [4] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42546$1946_Y + connect \Y $and$libresoc.v:42342$1946_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42548$1948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42344$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68690,10 +68486,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42548$1948_Y + connect \Y $and$libresoc.v:42344$1948_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42549$1949 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42345$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68701,10 +68497,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$412 connect \B \rdflag_INT_rabc_0 - connect \Y $and$libresoc.v:42549$1949_Y + connect \Y $and$libresoc.v:42345$1949_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42551$1951 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42347$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68712,10 +68508,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$414 connect \B \$416 - connect \Y $and$libresoc.v:42551$1951_Y + connect \Y $and$libresoc.v:42347$1951_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42552$1952 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42348$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68723,10 +68519,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [5] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42552$1952_Y + connect \Y $and$libresoc.v:42348$1952_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42554$1954 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42350$1954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68734,10 +68530,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42554$1954_Y + connect \Y $and$libresoc.v:42350$1954_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42555$1955 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42351$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68745,10 +68541,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$424 connect \B \rdflag_INT_rabc_0 - connect \Y $and$libresoc.v:42555$1955_Y + connect \Y $and$libresoc.v:42351$1955_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42557$1957 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42353$1957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68756,10 +68552,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$426 connect \B \$428 - connect \Y $and$libresoc.v:42557$1957_Y + connect \Y $and$libresoc.v:42353$1957_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42558$1958 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42354$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68767,10 +68563,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [6] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42558$1958_Y + connect \Y $and$libresoc.v:42354$1958_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42560$1960 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42356$1960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68778,10 +68574,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42560$1960_Y + connect \Y $and$libresoc.v:42356$1960_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42561$1961 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42357$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68789,10 +68585,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$436 connect \B \rdflag_INT_rabc_0 - connect \Y $and$libresoc.v:42561$1961_Y + connect \Y $and$libresoc.v:42357$1961_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42563$1963 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42359$1963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68800,10 +68596,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$438 connect \B \$440 - connect \Y $and$libresoc.v:42563$1963_Y + connect \Y $and$libresoc.v:42359$1963_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42564$1964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42360$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68811,10 +68607,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [7] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42564$1964_Y + connect \Y $and$libresoc.v:42360$1964_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42566$1966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42362$1966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68822,10 +68618,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42566$1966_Y + connect \Y $and$libresoc.v:42362$1966_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42567$1967 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42363$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68833,10 +68629,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$448 connect \B \rdflag_INT_rabc_1 - connect \Y $and$libresoc.v:42567$1967_Y + connect \Y $and$libresoc.v:42363$1967_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42569$1969 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42365$1969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68844,10 +68640,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$450 connect \B \$452 - connect \Y $and$libresoc.v:42569$1969_Y + connect \Y $and$libresoc.v:42365$1969_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42570$1970 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42366$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68855,10 +68651,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [8] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42570$1970_Y + connect \Y $and$libresoc.v:42366$1970_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42572$1972 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42368$1972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68866,10 +68662,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [2] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42572$1972_Y + connect \Y $and$libresoc.v:42368$1972_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42573$1973 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42369$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68877,10 +68673,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$460 connect \B \rdflag_INT_rabc_1 - connect \Y $and$libresoc.v:42573$1973_Y + connect \Y $and$libresoc.v:42369$1973_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42575$1975 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42371$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68888,10 +68684,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$462 connect \B \$464 - connect \Y $and$libresoc.v:42575$1975_Y + connect \Y $and$libresoc.v:42371$1975_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42576$1976 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42372$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68899,10 +68695,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [9] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42576$1976_Y + connect \Y $and$libresoc.v:42372$1976_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42578$1978 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42374$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68910,10 +68706,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42578$1978_Y + connect \Y $and$libresoc.v:42374$1978_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42579$1979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42375$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68921,10 +68717,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$472 connect \B \rdflag_INT_rabc_2 - connect \Y $and$libresoc.v:42579$1979_Y + connect \Y $and$libresoc.v:42375$1979_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42581$1981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42377$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68932,10 +68728,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$474 connect \B \$476 - connect \Y $and$libresoc.v:42581$1981_Y + connect \Y $and$libresoc.v:42377$1981_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42582$1982 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42378$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68943,10 +68739,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [10] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42582$1982_Y + connect \Y $and$libresoc.v:42378$1982_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42584$1984 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42380$1984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68954,10 +68750,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42584$1984_Y + connect \Y $and$libresoc.v:42380$1984_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42585$1985 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42381$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68965,10 +68761,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$484 connect \B \rdflag_INT_rabc_2 - connect \Y $and$libresoc.v:42585$1985_Y + connect \Y $and$libresoc.v:42381$1985_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42587$1987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42383$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68976,10 +68772,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$486 connect \B \$488 - connect \Y $and$libresoc.v:42587$1987_Y + connect \Y $and$libresoc.v:42383$1987_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42588$1988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42384$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68987,10 +68783,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [11] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42588$1988_Y + connect \Y $and$libresoc.v:42384$1988_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42590$1990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42386$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68998,10 +68794,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42590$1990_Y + connect \Y $and$libresoc.v:42386$1990_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42591$1991 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42387$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69009,10 +68805,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$496 connect \B \rdflag_INT_rabc_2 - connect \Y $and$libresoc.v:42591$1991_Y + connect \Y $and$libresoc.v:42387$1991_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42593$1993 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42389$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69020,10 +68816,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$498 connect \B \$500 - connect \Y $and$libresoc.v:42593$1993_Y + connect \Y $and$libresoc.v:42389$1993_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42594$1994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42390$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69031,10 +68827,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [12] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42594$1994_Y + connect \Y $and$libresoc.v:42390$1994_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42596$1996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42392$1996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69042,10 +68838,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42596$1996_Y + connect \Y $and$libresoc.v:42392$1996_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42597$1997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42393$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69053,10 +68849,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$508 connect \B \rdflag_INT_rabc_2 - connect \Y $and$libresoc.v:42597$1997_Y + connect \Y $and$libresoc.v:42393$1997_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42599$1999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42395$1999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69064,10 +68860,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$510 connect \B \$512 - connect \Y $and$libresoc.v:42599$1999_Y + connect \Y $and$libresoc.v:42395$1999_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42600$2000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42396$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69075,10 +68871,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [13] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42600$2000_Y + connect \Y $and$libresoc.v:42396$2000_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42602$2002 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42398$2002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69086,10 +68882,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42602$2002_Y + connect \Y $and$libresoc.v:42398$2002_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42603$2003 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42399$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69097,10 +68893,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$520 connect \B \rdflag_INT_rabc_2 - connect \Y $and$libresoc.v:42603$2003_Y + connect \Y $and$libresoc.v:42399$2003_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42605$2005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42401$2005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69108,10 +68904,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$522 connect \B \$524 - connect \Y $and$libresoc.v:42605$2005_Y + connect \Y $and$libresoc.v:42401$2005_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42606$2006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42402$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69119,10 +68915,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [14] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42606$2006_Y + connect \Y $and$libresoc.v:42402$2006_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42608$2008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42404$2008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69130,10 +68926,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42608$2008_Y + connect \Y $and$libresoc.v:42404$2008_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42609$2009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42405$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69141,10 +68937,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$532 connect \B \rdflag_INT_rabc_2 - connect \Y $and$libresoc.v:42609$2009_Y + connect \Y $and$libresoc.v:42405$2009_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42611$2011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42407$2011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69152,10 +68948,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$534 connect \B \$536 - connect \Y $and$libresoc.v:42611$2011_Y + connect \Y $and$libresoc.v:42407$2011_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42612$2012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42408$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69163,10 +68959,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [15] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42612$2012_Y + connect \Y $and$libresoc.v:42408$2012_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42614$2014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42410$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69174,10 +68970,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42614$2014_Y + connect \Y $and$libresoc.v:42410$2014_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42615$2015 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42411$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69185,10 +68981,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$544 connect \B \rdflag_INT_rabc_2 - connect \Y $and$libresoc.v:42615$2015_Y + connect \Y $and$libresoc.v:42411$2015_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42617$2017 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42413$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69196,10 +68992,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$546 connect \B \$548 - connect \Y $and$libresoc.v:42617$2017_Y + connect \Y $and$libresoc.v:42413$2017_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42618$2018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42414$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69207,10 +69003,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [16] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42618$2018_Y + connect \Y $and$libresoc.v:42414$2018_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42620$2020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42416$2020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69218,10 +69014,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42620$2020_Y + connect \Y $and$libresoc.v:42416$2020_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42621$2021 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42417$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69229,10 +69025,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$556 connect \B \rdflag_INT_rabc_2 - connect \Y $and$libresoc.v:42621$2021_Y + connect \Y $and$libresoc.v:42417$2021_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42623$2023 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42419$2023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69240,10 +69036,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$558 connect \B \$560 - connect \Y $and$libresoc.v:42623$2023_Y + connect \Y $and$libresoc.v:42419$2023_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42624$2024 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42420$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69251,10 +69047,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [17] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42624$2024_Y + connect \Y $and$libresoc.v:42420$2024_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42626$2026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42422$2026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69262,10 +69058,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42626$2026_Y + connect \Y $and$libresoc.v:42422$2026_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42627$2027 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42423$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69273,10 +69069,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$568 connect \B \rdflag_INT_rabc_2 - connect \Y $and$libresoc.v:42627$2027_Y + connect \Y $and$libresoc.v:42423$2027_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42629$2029 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42425$2029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69284,10 +69080,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$570 connect \B \$572 - connect \Y $and$libresoc.v:42629$2029_Y + connect \Y $and$libresoc.v:42425$2029_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42630$2030 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42426$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69295,10 +69091,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [18] connect \B \rdpick_INT_rabc_en_o - connect \Y $and$libresoc.v:42630$2030_Y + connect \Y $and$libresoc.v:42426$2030_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42651$2051 + cell $and $and$libresoc.v:42447$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69306,10 +69102,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42651$2051_Y + connect \Y $and$libresoc.v:42447$2051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42652$2052 + cell $and $and$libresoc.v:42448$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69317,10 +69113,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42652$2052_Y + connect \Y $and$libresoc.v:42448$2052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42655$2055 + cell $and $and$libresoc.v:42451$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69328,10 +69124,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42655$2055_Y + connect \Y $and$libresoc.v:42451$2055_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42657$2057 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42453$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69339,10 +69135,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42657$2057_Y + connect \Y $and$libresoc.v:42453$2057_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42658$2058 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42454$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69350,10 +69146,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$631 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42658$2058_Y + connect \Y $and$libresoc.v:42454$2058_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42660$2060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42456$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69361,10 +69157,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$633 connect \B \$635 - connect \Y $and$libresoc.v:42660$2060_Y + connect \Y $and$libresoc.v:42456$2060_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42661$2061 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42457$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69372,10 +69168,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [0] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42661$2061_Y + connect \Y $and$libresoc.v:42457$2061_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42663$2063 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42459$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69383,10 +69179,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [2] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42663$2063_Y + connect \Y $and$libresoc.v:42459$2063_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42664$2064 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42460$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69394,10 +69190,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$643 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42664$2064_Y + connect \Y $and$libresoc.v:42460$2064_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42666$2066 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42462$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69405,10 +69201,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$645 connect \B \$647 - connect \Y $and$libresoc.v:42666$2066_Y + connect \Y $and$libresoc.v:42462$2066_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42667$2067 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42463$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69416,10 +69212,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [1] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42667$2067_Y + connect \Y $and$libresoc.v:42463$2067_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42669$2069 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42465$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69427,10 +69223,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42669$2069_Y + connect \Y $and$libresoc.v:42465$2069_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42670$2070 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42466$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69438,10 +69234,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$655 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42670$2070_Y + connect \Y $and$libresoc.v:42466$2070_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42672$2072 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42468$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69449,10 +69245,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$657 connect \B \$659 - connect \Y $and$libresoc.v:42672$2072_Y + connect \Y $and$libresoc.v:42468$2072_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42673$2073 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42469$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69460,10 +69256,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [2] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42673$2073_Y + connect \Y $and$libresoc.v:42469$2073_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42675$2075 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42471$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69471,10 +69267,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42675$2075_Y + connect \Y $and$libresoc.v:42471$2075_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42676$2076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42472$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69482,10 +69278,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$667 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42676$2076_Y + connect \Y $and$libresoc.v:42472$2076_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42678$2078 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42474$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69493,10 +69289,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$669 connect \B \$671 - connect \Y $and$libresoc.v:42678$2078_Y + connect \Y $and$libresoc.v:42474$2078_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42679$2079 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42475$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69504,10 +69300,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [3] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42679$2079_Y + connect \Y $and$libresoc.v:42475$2079_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42681$2081 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42477$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69515,10 +69311,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42681$2081_Y + connect \Y $and$libresoc.v:42477$2081_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42682$2082 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42478$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69526,10 +69322,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$679 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42682$2082_Y + connect \Y $and$libresoc.v:42478$2082_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42684$2084 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42480$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69537,10 +69333,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$681 connect \B \$683 - connect \Y $and$libresoc.v:42684$2084_Y + connect \Y $and$libresoc.v:42480$2084_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42685$2085 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42481$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69548,10 +69344,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [4] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42685$2085_Y + connect \Y $and$libresoc.v:42481$2085_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42687$2087 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42483$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69559,10 +69355,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [3] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42687$2087_Y + connect \Y $and$libresoc.v:42483$2087_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42688$2088 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42484$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69570,10 +69366,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$691 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42688$2088_Y + connect \Y $and$libresoc.v:42484$2088_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42690$2090 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42486$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69581,10 +69377,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$693 connect \B \$695 - connect \Y $and$libresoc.v:42690$2090_Y + connect \Y $and$libresoc.v:42486$2090_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42691$2091 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42487$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69592,10 +69388,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [5] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42691$2091_Y + connect \Y $and$libresoc.v:42487$2091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42700$2101 + cell $and $and$libresoc.v:42496$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69603,10 +69399,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42700$2101_Y + connect \Y $and$libresoc.v:42496$2101_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42703$2104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42499$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69614,10 +69410,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42703$2104_Y + connect \Y $and$libresoc.v:42499$2104_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42704$2105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42500$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69625,10 +69421,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$723 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42704$2105_Y + connect \Y $and$libresoc.v:42500$2105_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42706$2107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42502$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69636,10 +69432,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$725 connect \B \$727 - connect \Y $and$libresoc.v:42706$2107_Y + connect \Y $and$libresoc.v:42502$2107_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42707$2108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42503$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69647,10 +69443,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [0] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42707$2108_Y + connect \Y $and$libresoc.v:42503$2108_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42709$2110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42505$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69658,10 +69454,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42709$2110_Y + connect \Y $and$libresoc.v:42505$2110_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42710$2111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42506$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69669,10 +69465,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$735 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42710$2111_Y + connect \Y $and$libresoc.v:42506$2111_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42712$2113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42508$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69680,10 +69476,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$737 connect \B \$739 - connect \Y $and$libresoc.v:42712$2113_Y + connect \Y $and$libresoc.v:42508$2113_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42713$2114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42509$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69691,10 +69487,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [1] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42713$2114_Y + connect \Y $and$libresoc.v:42509$2114_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42715$2116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42511$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69702,10 +69498,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [4] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42715$2116_Y + connect \Y $and$libresoc.v:42511$2116_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42716$2117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42512$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69713,10 +69509,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$747 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42716$2117_Y + connect \Y $and$libresoc.v:42512$2117_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42718$2119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42514$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69724,10 +69520,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$749 connect \B \$751 - connect \Y $and$libresoc.v:42718$2119_Y + connect \Y $and$libresoc.v:42514$2119_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42719$2120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42515$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69735,10 +69531,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [2] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42719$2120_Y + connect \Y $and$libresoc.v:42515$2120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42724$2126 + cell $and $and$libresoc.v:42520$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69746,10 +69542,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42724$2126_Y + connect \Y $and$libresoc.v:42520$2126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42725$2127 + cell $and $and$libresoc.v:42521$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69757,10 +69553,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:42725$2127_Y + connect \Y $and$libresoc.v:42521$2127_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42728$2130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42524$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69768,10 +69564,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42728$2130_Y + connect \Y $and$libresoc.v:42524$2130_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42729$2131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42525$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69779,10 +69575,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$773 connect \B \rdflag_XER_xer_ov_0 - connect \Y $and$libresoc.v:42729$2131_Y + connect \Y $and$libresoc.v:42525$2131_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42731$2133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42527$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69790,10 +69586,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$775 connect \B \$777 - connect \Y $and$libresoc.v:42731$2133_Y + connect \Y $and$libresoc.v:42527$2133_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42732$2134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42528$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69801,10 +69597,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ov_o connect \B \rdpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42732$2134_Y + connect \Y $and$libresoc.v:42528$2134_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42734$2136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42530$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69812,10 +69608,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42734$2136_Y + connect \Y $and$libresoc.v:42530$2136_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42735$2137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42531$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69823,10 +69619,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$785 connect \B \rdflag_CR_full_cr_0 - connect \Y $and$libresoc.v:42735$2137_Y + connect \Y $and$libresoc.v:42531$2137_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42737$2139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42533$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69834,10 +69630,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$787 connect \B \$789 - connect \Y $and$libresoc.v:42737$2139_Y + connect \Y $and$libresoc.v:42533$2139_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42738$2140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42534$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69845,10 +69641,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_full_cr_o connect \B \rdpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42738$2140_Y + connect \Y $and$libresoc.v:42534$2140_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42740$2142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42536$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69856,10 +69652,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [3] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42740$2142_Y + connect \Y $and$libresoc.v:42536$2142_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42741$2143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42537$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69867,10 +69663,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$797 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42741$2143_Y + connect \Y $and$libresoc.v:42537$2143_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42743$2145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42539$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69878,10 +69674,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$799 connect \B \$801 - connect \Y $and$libresoc.v:42743$2145_Y + connect \Y $and$libresoc.v:42539$2145_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42744$2146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42540$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69889,10 +69685,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [0] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42744$2146_Y + connect \Y $and$libresoc.v:42540$2146_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42748$2150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42544$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69900,10 +69696,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42748$2150_Y + connect \Y $and$libresoc.v:42544$2150_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42749$2151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42545$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69911,10 +69707,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$813 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42749$2151_Y + connect \Y $and$libresoc.v:42545$2151_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42751$2153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42547$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69922,10 +69718,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$815 connect \B \$817 - connect \Y $and$libresoc.v:42751$2153_Y + connect \Y $and$libresoc.v:42547$2153_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42752$2154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42548$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69933,10 +69729,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [1] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42752$2154_Y + connect \Y $and$libresoc.v:42548$2154_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42757$2159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42553$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69944,10 +69740,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [4] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42757$2159_Y + connect \Y $and$libresoc.v:42553$2159_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42758$2160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42554$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69955,10 +69751,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$832 connect \B \rdflag_CR_cr_b_0 - connect \Y $and$libresoc.v:42758$2160_Y + connect \Y $and$libresoc.v:42554$2160_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42760$2162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42556$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69966,10 +69762,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$834 connect \B \$836 - connect \Y $and$libresoc.v:42760$2162_Y + connect \Y $and$libresoc.v:42556$2162_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42761$2163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42557$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69977,10 +69773,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_b_o connect \B \rdpick_CR_cr_b_en_o - connect \Y $and$libresoc.v:42761$2163_Y + connect \Y $and$libresoc.v:42557$2163_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42765$2167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42561$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69988,10 +69784,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [5] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42765$2167_Y + connect \Y $and$libresoc.v:42561$2167_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42766$2168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42562$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69999,10 +69795,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$848 connect \B \rdflag_CR_cr_c_0 - connect \Y $and$libresoc.v:42766$2168_Y + connect \Y $and$libresoc.v:42562$2168_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42768$2170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42564$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70010,10 +69806,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$850 connect \B \$852 - connect \Y $and$libresoc.v:42768$2170_Y + connect \Y $and$libresoc.v:42564$2170_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42769$2171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42565$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70021,10 +69817,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_c_o connect \B \rdpick_CR_cr_c_en_o - connect \Y $and$libresoc.v:42769$2171_Y + connect \Y $and$libresoc.v:42565$2171_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42773$2175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42569$2175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70032,10 +69828,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42773$2175_Y + connect \Y $and$libresoc.v:42569$2175_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42774$2176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42570$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70043,10 +69839,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$864 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42774$2176_Y + connect \Y $and$libresoc.v:42570$2176_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42776$2178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42572$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70054,10 +69850,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$866 connect \B \$868 - connect \Y $and$libresoc.v:42776$2178_Y + connect \Y $and$libresoc.v:42572$2178_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42777$2179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42573$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70065,10 +69861,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [0] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42777$2179_Y + connect \Y $and$libresoc.v:42573$2179_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42779$2181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42575$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70076,10 +69872,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42779$2181_Y + connect \Y $and$libresoc.v:42575$2181_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42780$2182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42576$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70087,10 +69883,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$876 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42780$2182_Y + connect \Y $and$libresoc.v:42576$2182_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42782$2184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42578$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70098,10 +69894,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$878 connect \B \$880 - connect \Y $and$libresoc.v:42782$2184_Y + connect \Y $and$libresoc.v:42578$2184_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42783$2185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42579$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70109,10 +69905,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [1] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42783$2185_Y + connect \Y $and$libresoc.v:42579$2185_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42785$2187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42581$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70120,10 +69916,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42785$2187_Y + connect \Y $and$libresoc.v:42581$2187_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42786$2188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42582$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70131,10 +69927,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$888 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42786$2188_Y + connect \Y $and$libresoc.v:42582$2188_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42788$2190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42584$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70142,10 +69938,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$890 connect \B \$892 - connect \Y $and$libresoc.v:42788$2190_Y + connect \Y $and$libresoc.v:42584$2190_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42789$2191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42585$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70153,10 +69949,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [2] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42789$2191_Y + connect \Y $and$libresoc.v:42585$2191_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42791$2193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42587$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70164,10 +69960,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42791$2193_Y + connect \Y $and$libresoc.v:42587$2193_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42792$2194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42588$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70175,10 +69971,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$900 connect \B \rdflag_FAST_fast1_1 - connect \Y $and$libresoc.v:42792$2194_Y + connect \Y $and$libresoc.v:42588$2194_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42794$2196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42590$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70186,10 +69982,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$902 connect \B \$904 - connect \Y $and$libresoc.v:42794$2196_Y + connect \Y $and$libresoc.v:42590$2196_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42795$2197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42591$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70197,10 +69993,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [3] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42795$2197_Y + connect \Y $and$libresoc.v:42591$2197_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42797$2199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42593$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70208,10 +70004,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42797$2199_Y + connect \Y $and$libresoc.v:42593$2199_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42798$2200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42594$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70219,10 +70015,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$912 connect \B \rdflag_FAST_fast1_1 - connect \Y $and$libresoc.v:42798$2200_Y + connect \Y $and$libresoc.v:42594$2200_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42800$2202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42596$2202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70230,10 +70026,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$914 connect \B \$916 - connect \Y $and$libresoc.v:42800$2202_Y + connect \Y $and$libresoc.v:42596$2202_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42801$2203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42597$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70241,10 +70037,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [4] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42801$2203_Y + connect \Y $and$libresoc.v:42597$2203_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42808$2210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42604$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70252,10 +70048,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42808$2210_Y + connect \Y $and$libresoc.v:42604$2210_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" - cell $and $and$libresoc.v:42809$2211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42605$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70263,10 +70059,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$934 connect \B \rdflag_SPR_spr1_0 - connect \Y $and$libresoc.v:42809$2211_Y + connect \Y $and$libresoc.v:42605$2211_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $and $and$libresoc.v:42811$2213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42607$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70274,10 +70070,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$936 connect \B \$938 - connect \Y $and$libresoc.v:42811$2213_Y + connect \Y $and$libresoc.v:42607$2213_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" - cell $and $and$libresoc.v:42812$2214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42608$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70285,10 +70081,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_SPR_spr1_o connect \B \rdpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42812$2214_Y + connect \Y $and$libresoc.v:42608$2214_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42815$2217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42611$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70296,10 +70092,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42815$2217_Y + connect \Y $and$libresoc.v:42611$2217_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42816$2218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42612$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70307,10 +70103,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42816$2218_Y + connect \Y $and$libresoc.v:42612$2218_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42817$2219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42613$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70318,10 +70114,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42817$2219_Y + connect \Y $and$libresoc.v:42613$2219_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42818$2220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42614$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70329,10 +70125,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42818$2220_Y + connect \Y $and$libresoc.v:42614$2220_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42819$2221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42615$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70340,10 +70136,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42819$2221_Y + connect \Y $and$libresoc.v:42615$2221_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42820$2222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42616$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70351,10 +70147,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42820$2222_Y + connect \Y $and$libresoc.v:42616$2222_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42821$2223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42617$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70362,10 +70158,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42821$2223_Y + connect \Y $and$libresoc.v:42617$2223_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42822$2224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42618$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70373,10 +70169,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42822$2224_Y + connect \Y $and$libresoc.v:42618$2224_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42823$2225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42619$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70384,10 +70180,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42823$2225_Y + connect \Y $and$libresoc.v:42619$2225_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42824$2226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42620$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70395,10 +70191,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42824$2226_Y + connect \Y $and$libresoc.v:42620$2226_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - cell $and $and$libresoc.v:42825$2227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42621$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70406,10 +70202,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42825$2227_Y + connect \Y $and$libresoc.v:42621$2227_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42826$2228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42622$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70417,10 +70213,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42826$2228_Y + connect \Y $and$libresoc.v:42622$2228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42828$2230 + cell $and $and$libresoc.v:42624$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70428,10 +70224,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \$972 - connect \Y $and$libresoc.v:42828$2230_Y + connect \Y $and$libresoc.v:42624$2230_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42829$2231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42625$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70439,10 +70235,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42829$2231_Y + connect \Y $and$libresoc.v:42625$2231_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:42831$2233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42627$2233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70450,10 +70246,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$92 connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:42831$2233_Y + connect \Y $and$libresoc.v:42627$2233_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:42832$2234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42628$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70461,10 +70257,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42832$2234_Y + connect \Y $and$libresoc.v:42628$2234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42834$2236 + cell $and $and$libresoc.v:42630$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70472,10 +70268,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$986 connect \B \$991 - connect \Y $and$libresoc.v:42834$2236_Y + connect \Y $and$libresoc.v:42630$2236_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:424" - cell $and $and$libresoc.v:42835$2237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42631$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70483,10 +70279,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$986 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42835$2237_Y + connect \Y $and$libresoc.v:42631$2237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42458$1858 + cell $eq $eq$libresoc.v:42254$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70494,10 +70290,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$231 connect \B 1'1 - connect \Y $eq$libresoc.v:42458$1858_Y + connect \Y $eq$libresoc.v:42254$1858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42462$1862 + cell $eq $eq$libresoc.v:42258$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70505,10 +70301,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42462$1862_Y + connect \Y $eq$libresoc.v:42258$1862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42464$1864 + cell $eq $eq$libresoc.v:42260$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70516,10 +70312,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$243 connect \B 3'100 - connect \Y $eq$libresoc.v:42464$1864_Y + connect \Y $eq$libresoc.v:42260$1864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42472$1872 + cell $eq $eq$libresoc.v:42268$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70527,10 +70323,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$259 connect \B 1'1 - connect \Y $eq$libresoc.v:42472$1872_Y + connect \Y $eq$libresoc.v:42268$1872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42479$1879 + cell $eq $eq$libresoc.v:42275$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70538,10 +70334,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$273 connect \B 1'1 - connect \Y $eq$libresoc.v:42479$1879_Y + connect \Y $eq$libresoc.v:42275$1879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:42485$1885 + cell $eq $eq$libresoc.v:42281$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70549,10 +70345,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$285 connect \B 2'10 - connect \Y $eq$libresoc.v:42485$1885_Y + connect \Y $eq$libresoc.v:42281$1885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42487$1887 + cell $eq $eq$libresoc.v:42283$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70560,10 +70356,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42487$1887_Y + connect \Y $eq$libresoc.v:42283$1887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42489$1889 + cell $eq $eq$libresoc.v:42285$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70571,10 +70367,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$293 connect \B 3'100 - connect \Y $eq$libresoc.v:42489$1889_Y + connect \Y $eq$libresoc.v:42285$1889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42494$1894 + cell $eq $eq$libresoc.v:42290$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70582,10 +70378,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$303 connect \B 1'1 - connect \Y $eq$libresoc.v:42494$1894_Y + connect \Y $eq$libresoc.v:42290$1894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42501$1901 + cell $eq $eq$libresoc.v:42297$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70593,10 +70389,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$317 connect \B 1'1 - connect \Y $eq$libresoc.v:42501$1901_Y + connect \Y $eq$libresoc.v:42297$1901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42508$1908 + cell $eq $eq$libresoc.v:42304$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70604,10 +70400,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$331 connect \B 1'1 - connect \Y $eq$libresoc.v:42508$1908_Y + connect \Y $eq$libresoc.v:42304$1908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42512$1912 + cell $eq $eq$libresoc.v:42308$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70615,10 +70411,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42512$1912_Y + connect \Y $eq$libresoc.v:42308$1912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42514$1914 + cell $eq $eq$libresoc.v:42310$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70626,10 +70422,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$343 connect \B 3'100 - connect \Y $eq$libresoc.v:42514$1914_Y + connect \Y $eq$libresoc.v:42310$1914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42653$2053 + cell $eq $eq$libresoc.v:42449$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70637,10 +70433,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$621 connect \B 1'1 - connect \Y $eq$libresoc.v:42653$2053_Y + connect \Y $eq$libresoc.v:42449$2053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42699$2100 + cell $eq $eq$libresoc.v:42495$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70648,10 +70444,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42699$2100_Y + connect \Y $eq$libresoc.v:42495$2100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42701$2102 + cell $eq $eq$libresoc.v:42497$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70659,10 +70455,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$717 connect \B 3'100 - connect \Y $eq$libresoc.v:42701$2102_Y + connect \Y $eq$libresoc.v:42497$2102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:42726$2128 + cell $eq $eq$libresoc.v:42522$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70670,66 +70466,66 @@ module \core parameter \Y_WIDTH 1 connect \A \$767 connect \B 2'10 - connect \Y $eq$libresoc.v:42726$2128_Y + connect \Y $eq$libresoc.v:42522$2128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42283$1678 + cell $pos $extend$libresoc.v:42079$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \$1445 - connect \Y $extend$libresoc.v:42283$1678_Y + connect \Y $extend$libresoc.v:42079$1678_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42349$1745 + cell $pos $extend$libresoc.v:42145$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \$1609 - connect \Y $extend$libresoc.v:42349$1745_Y + connect \Y $extend$libresoc.v:42145$1745_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42353$1750 + cell $pos $extend$libresoc.v:42149$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$1617 - connect \Y $extend$libresoc.v:42353$1750_Y + connect \Y $extend$libresoc.v:42149$1750_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $pos $extend$libresoc.v:42417$1815 + cell $pos $extend$libresoc.v:42213$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$1776 - connect \Y $extend$libresoc.v:42417$1815_Y + connect \Y $extend$libresoc.v:42213$1815_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" - cell $pos $extend$libresoc.v:42425$1824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" + cell $pos $extend$libresoc.v:42221$1824 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \addr_en$1794 - connect \Y $extend$libresoc.v:42425$1824_Y + connect \Y $extend$libresoc.v:42221$1824_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42698$2098 + cell $pos $extend$libresoc.v:42494$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$712 - connect \Y $extend$libresoc.v:42698$2098_Y + connect \Y $extend$libresoc.v:42494$2098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42723$2124 + cell $pos $extend$libresoc.v:42519$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \$762 - connect \Y $extend$libresoc.v:42723$2124_Y + connect \Y $extend$libresoc.v:42519$2124_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" - cell $ne $ne$libresoc.v:42453$1853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + cell $ne $ne$libresoc.v:42249$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70737,10 +70533,10 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:42453$1853_Y + connect \Y $ne$libresoc.v:42249$1853_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" - cell $ne $ne$libresoc.v:42455$1855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + cell $ne $ne$libresoc.v:42251$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70748,706 +70544,706 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:42455$1855_Y + connect \Y $ne$libresoc.v:42251$1855_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42114$1509 + cell $not $not$libresoc.v:41910$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1008 - connect \Y $not$libresoc.v:42114$1509_Y + connect \Y $not$libresoc.v:41910$1509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42120$1515 + cell $not $not$libresoc.v:41916$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1029 - connect \Y $not$libresoc.v:42120$1515_Y + connect \Y $not$libresoc.v:41916$1515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42126$1521 + cell $not $not$libresoc.v:41922$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1047 - connect \Y $not$libresoc.v:42126$1521_Y + connect \Y $not$libresoc.v:41922$1521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42132$1527 + cell $not $not$libresoc.v:41928$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1069 - connect \Y $not$libresoc.v:42132$1527_Y + connect \Y $not$libresoc.v:41928$1527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42138$1533 + cell $not $not$libresoc.v:41934$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1089 - connect \Y $not$libresoc.v:42138$1533_Y + connect \Y $not$libresoc.v:41934$1533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42144$1539 + cell $not $not$libresoc.v:41940$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1109 - connect \Y $not$libresoc.v:42144$1539_Y + connect \Y $not$libresoc.v:41940$1539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42150$1545 + cell $not $not$libresoc.v:41946$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1128 - connect \Y $not$libresoc.v:42150$1545_Y + connect \Y $not$libresoc.v:41946$1545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42156$1551 + cell $not $not$libresoc.v:41952$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1146 - connect \Y $not$libresoc.v:42156$1551_Y + connect \Y $not$libresoc.v:41952$1551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42190$1585 + cell $not $not$libresoc.v:41986$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1220 - connect \Y $not$libresoc.v:42190$1585_Y + connect \Y $not$libresoc.v:41986$1585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42202$1597 + cell $not $not$libresoc.v:41998$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1248 - connect \Y $not$libresoc.v:42202$1597_Y + connect \Y $not$libresoc.v:41998$1597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42210$1605 + cell $not $not$libresoc.v:42006$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1268 - connect \Y $not$libresoc.v:42210$1605_Y + connect \Y $not$libresoc.v:42006$1605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42218$1613 + cell $not $not$libresoc.v:42014$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1288 - connect \Y $not$libresoc.v:42218$1613_Y + connect \Y $not$libresoc.v:42014$1613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42226$1621 + cell $not $not$libresoc.v:42022$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1308 - connect \Y $not$libresoc.v:42226$1621_Y + connect \Y $not$libresoc.v:42022$1621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42234$1629 + cell $not $not$libresoc.v:42030$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1328 - connect \Y $not$libresoc.v:42234$1629_Y + connect \Y $not$libresoc.v:42030$1629_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42242$1637 + cell $not $not$libresoc.v:42038$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1348 - connect \Y $not$libresoc.v:42242$1637_Y + connect \Y $not$libresoc.v:42038$1637_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42263$1658 + cell $not $not$libresoc.v:42059$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1395 - connect \Y $not$libresoc.v:42263$1658_Y + connect \Y $not$libresoc.v:42059$1658_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42269$1664 + cell $not $not$libresoc.v:42065$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1411 - connect \Y $not$libresoc.v:42269$1664_Y + connect \Y $not$libresoc.v:42065$1664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42275$1670 + cell $not $not$libresoc.v:42071$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1427 - connect \Y $not$libresoc.v:42275$1670_Y + connect \Y $not$libresoc.v:42071$1670_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42290$1686 + cell $not $not$libresoc.v:42086$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1461 - connect \Y $not$libresoc.v:42290$1686_Y + connect \Y $not$libresoc.v:42086$1686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42296$1692 + cell $not $not$libresoc.v:42092$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1477 - connect \Y $not$libresoc.v:42296$1692_Y + connect \Y $not$libresoc.v:42092$1692_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42302$1698 + cell $not $not$libresoc.v:42098$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1493 - connect \Y $not$libresoc.v:42302$1698_Y + connect \Y $not$libresoc.v:42098$1698_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42308$1704 + cell $not $not$libresoc.v:42104$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1509 - connect \Y $not$libresoc.v:42308$1704_Y + connect \Y $not$libresoc.v:42104$1704_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42324$1720 + cell $not $not$libresoc.v:42120$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1545 - connect \Y $not$libresoc.v:42324$1720_Y + connect \Y $not$libresoc.v:42120$1720_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42330$1726 + cell $not $not$libresoc.v:42126$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1561 - connect \Y $not$libresoc.v:42330$1726_Y + connect \Y $not$libresoc.v:42126$1726_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42336$1732 + cell $not $not$libresoc.v:42132$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1577 - connect \Y $not$libresoc.v:42336$1732_Y + connect \Y $not$libresoc.v:42132$1732_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42342$1738 + cell $not $not$libresoc.v:42138$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1593 - connect \Y $not$libresoc.v:42342$1738_Y + connect \Y $not$libresoc.v:42138$1738_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42361$1759 + cell $not $not$libresoc.v:42157$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1635 - connect \Y $not$libresoc.v:42361$1759_Y + connect \Y $not$libresoc.v:42157$1759_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42367$1765 + cell $not $not$libresoc.v:42163$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1654 - connect \Y $not$libresoc.v:42367$1765_Y + connect \Y $not$libresoc.v:42163$1765_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42373$1771 + cell $not $not$libresoc.v:42169$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1670 - connect \Y $not$libresoc.v:42373$1771_Y + connect \Y $not$libresoc.v:42169$1771_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42379$1777 + cell $not $not$libresoc.v:42175$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1686 - connect \Y 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"/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42526$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ov_spr0_0 - connect \Y $not$libresoc.v:42730$2132_Y + connect \Y $not$libresoc.v:42526$2132_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $not $not$libresoc.v:42736$2138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42532$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_full_cr_cr0_0 - connect \Y $not$libresoc.v:42736$2138_Y + connect \Y $not$libresoc.v:42532$2138_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $not $not$libresoc.v:42742$2144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42538$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_cr0_0 - connect \Y $not$libresoc.v:42742$2144_Y + connect \Y $not$libresoc.v:42538$2144_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $not $not$libresoc.v:42750$2152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42546$2152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_branch0_1 - connect \Y $not$libresoc.v:42750$2152_Y + connect \Y $not$libresoc.v:42546$2152_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $not $not$libresoc.v:42759$2161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42555$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_b_cr0_0 - connect \Y $not$libresoc.v:42759$2161_Y + connect \Y $not$libresoc.v:42555$2161_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $not $not$libresoc.v:42767$2169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42563$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_c_cr0_0 - connect \Y $not$libresoc.v:42767$2169_Y + connect \Y $not$libresoc.v:42563$2169_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $not $not$libresoc.v:42775$2177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42571$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_branch0_0 - connect \Y $not$libresoc.v:42775$2177_Y + connect \Y $not$libresoc.v:42571$2177_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $not $not$libresoc.v:42781$2183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42577$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_trap0_1 - connect \Y $not$libresoc.v:42781$2183_Y + connect \Y $not$libresoc.v:42577$2183_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $not $not$libresoc.v:42787$2189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42583$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_spr0_2 - connect \Y $not$libresoc.v:42787$2189_Y + connect \Y $not$libresoc.v:42583$2189_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $not $not$libresoc.v:42793$2195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42589$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_branch0_3 - connect \Y $not$libresoc.v:42793$2195_Y + connect \Y $not$libresoc.v:42589$2195_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $not $not$libresoc.v:42799$2201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42595$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_trap0_4 - connect \Y $not$libresoc.v:42799$2201_Y + connect \Y $not$libresoc.v:42595$2201_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $not $not$libresoc.v:42810$2212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42606$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_SPR_spr1_spr0_0 - connect \Y $not$libresoc.v:42810$2212_Y + connect \Y $not$libresoc.v:42606$2212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42827$2229 + cell $not $not$libresoc.v:42623$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly - connect \Y $not$libresoc.v:42827$2229_Y + connect \Y $not$libresoc.v:42623$2229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42833$2235 + cell $not $not$libresoc.v:42629$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$989 - connect \Y $not$libresoc.v:42833$2235_Y + connect \Y $not$libresoc.v:42629$2235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42160$1555 + cell $or $or$libresoc.v:41956$1555 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71455,10 +71251,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o connect \B \fus_dest1_o$115 - connect \Y $or$libresoc.v:42160$1555_Y + connect \Y $or$libresoc.v:41956$1555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42161$1556 + cell $or $or$libresoc.v:41957$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71466,10 +71262,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$117 connect \B \fus_dest1_o$118 - connect \Y $or$libresoc.v:42161$1556_Y + connect \Y $or$libresoc.v:41957$1556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42162$1557 + cell $or $or$libresoc.v:41958$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71477,10 +71273,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$116 connect \B \$1160 - connect \Y $or$libresoc.v:42162$1557_Y + connect \Y $or$libresoc.v:41958$1557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42163$1558 + cell $or $or$libresoc.v:41959$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71488,10 +71284,10 @@ module \core parameter \Y_WIDTH 64 connect \A \$1158 connect \B \$1162 - connect \Y $or$libresoc.v:42163$1558_Y + connect \Y $or$libresoc.v:41959$1558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42164$1559 + cell $or $or$libresoc.v:41960$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71499,10 +71295,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$119 connect \B \fus_dest1_o$120 - connect \Y $or$libresoc.v:42164$1559_Y + connect \Y $or$libresoc.v:41960$1559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42165$1560 + cell $or $or$libresoc.v:41961$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \B_SIGNED 0 @@ -71510,10 +71306,10 @@ module \core parameter \Y_WIDTH 65 connect \A { \o_ok \fus_o } connect \B { \ea_ok \fus_ea } - connect \Y $or$libresoc.v:42165$1560_Y + connect \Y $or$libresoc.v:41961$1560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42166$1561 + cell $or $or$libresoc.v:41962$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71521,10 +71317,10 @@ module \core parameter \Y_WIDTH 65 connect \A \fus_dest1_o$121 connect \B \$1168 - connect \Y $or$libresoc.v:42166$1561_Y + connect \Y $or$libresoc.v:41962$1561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42167$1562 + cell $or $or$libresoc.v:41963$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71532,10 +71328,10 @@ module \core parameter \Y_WIDTH 65 connect \A \$1166 connect \B \$1170 - connect \Y $or$libresoc.v:42167$1562_Y + connect \Y $or$libresoc.v:41963$1562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42168$1563 + cell $or $or$libresoc.v:41964$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71543,10 +71339,10 @@ module \core parameter \Y_WIDTH 65 connect \A \$1164 connect \B \$1172 - connect \Y $or$libresoc.v:42168$1563_Y + connect \Y $or$libresoc.v:41964$1563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42169$1564 + cell $or $or$libresoc.v:41965$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71554,10 +71350,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en connect \B \addr_en$1000 - connect \Y $or$libresoc.v:42169$1564_Y + connect \Y $or$libresoc.v:41965$1564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42170$1565 + cell $or $or$libresoc.v:41966$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71565,10 +71361,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1039 connect \B \addr_en$1061 - connect \Y $or$libresoc.v:42170$1565_Y + connect \Y $or$libresoc.v:41966$1565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42171$1566 + cell $or $or$libresoc.v:41967$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71576,10 +71372,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1021 connect \B \$1179 - connect \Y $or$libresoc.v:42171$1566_Y + connect \Y $or$libresoc.v:41967$1566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42172$1567 + cell $or $or$libresoc.v:41968$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71587,10 +71383,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$1177 connect \B \$1181 - connect \Y $or$libresoc.v:42172$1567_Y + connect \Y $or$libresoc.v:41968$1567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42173$1568 + cell $or $or$libresoc.v:41969$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71598,10 +71394,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1081 connect \B \addr_en$1101 - connect \Y $or$libresoc.v:42173$1568_Y + connect \Y $or$libresoc.v:41969$1568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42174$1569 + cell $or $or$libresoc.v:41970$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71609,10 +71405,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1138 connect \B \addr_en$1154 - connect \Y $or$libresoc.v:42174$1569_Y + connect \Y $or$libresoc.v:41970$1569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42175$1570 + cell $or $or$libresoc.v:41971$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71620,10 +71416,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1120 connect \B \$1187 - connect \Y $or$libresoc.v:42175$1570_Y + connect \Y $or$libresoc.v:41971$1570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42176$1571 + cell $or $or$libresoc.v:41972$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71631,10 +71427,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$1185 connect \B \$1189 - connect \Y $or$libresoc.v:42176$1571_Y + connect \Y $or$libresoc.v:41972$1571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42177$1572 + cell $or $or$libresoc.v:41973$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71642,10 +71438,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$1183 connect \B \$1191 - connect \Y $or$libresoc.v:42177$1572_Y + connect \Y $or$libresoc.v:41973$1572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42178$1573 + cell $or $or$libresoc.v:41974$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71653,10 +71449,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp connect \B \wp$997 - connect \Y $or$libresoc.v:42178$1573_Y + connect \Y $or$libresoc.v:41974$1573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42179$1574 + cell $or $or$libresoc.v:41975$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71664,10 +71460,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1036 connect \B \wp$1058 - connect \Y $or$libresoc.v:42179$1574_Y + connect \Y $or$libresoc.v:41975$1574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42180$1575 + cell $or $or$libresoc.v:41976$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71675,10 +71471,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1018 connect \B \$1197 - connect \Y $or$libresoc.v:42180$1575_Y + connect \Y $or$libresoc.v:41976$1575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42181$1576 + cell $or $or$libresoc.v:41977$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71686,10 +71482,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1195 connect \B \$1199 - connect \Y $or$libresoc.v:42181$1576_Y + connect \Y $or$libresoc.v:41977$1576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42182$1577 + cell $or $or$libresoc.v:41978$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71697,10 +71493,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1078 connect \B \wp$1098 - connect \Y $or$libresoc.v:42182$1577_Y + connect \Y $or$libresoc.v:41978$1577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42183$1578 + cell $or $or$libresoc.v:41979$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71708,10 +71504,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1135 connect \B \wp$1151 - connect \Y $or$libresoc.v:42183$1578_Y + connect \Y $or$libresoc.v:41979$1578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42184$1579 + cell $or $or$libresoc.v:41980$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71719,10 +71515,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1117 connect \B \$1205 - connect \Y $or$libresoc.v:42184$1579_Y + connect \Y $or$libresoc.v:41980$1579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42185$1580 + cell $or $or$libresoc.v:41981$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71730,10 +71526,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1203 connect \B \$1207 - connect \Y $or$libresoc.v:42185$1580_Y + connect \Y $or$libresoc.v:41981$1580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42186$1581 + cell $or $or$libresoc.v:41982$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71741,10 +71537,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1201 connect \B \$1209 - connect \Y $or$libresoc.v:42186$1581_Y + connect \Y $or$libresoc.v:41982$1581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42248$1643 + cell $or $or$libresoc.v:42044$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71752,10 +71548,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest3_o connect \B \fus_dest2_o$128 - connect \Y $or$libresoc.v:42248$1643_Y + connect \Y $or$libresoc.v:42044$1643_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42249$1644 + cell $or $or$libresoc.v:42045$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71763,10 +71559,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$127 connect \B \$1363 - connect \Y $or$libresoc.v:42249$1644_Y + connect \Y $or$libresoc.v:42045$1644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42250$1645 + cell $or $or$libresoc.v:42046$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71774,10 +71570,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$130 connect \B \fus_dest2_o$131 - connect \Y $or$libresoc.v:42250$1645_Y + connect \Y $or$libresoc.v:42046$1645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42251$1646 + cell $or $or$libresoc.v:42047$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71785,10 +71581,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$129 connect \B \$1367 - connect \Y $or$libresoc.v:42251$1646_Y + connect \Y $or$libresoc.v:42047$1646_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42252$1647 + cell $or $or$libresoc.v:42048$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71796,10 +71592,10 @@ module \core parameter \Y_WIDTH 4 connect \A \$1365 connect \B \$1369 - connect \Y $or$libresoc.v:42252$1647_Y + connect \Y $or$libresoc.v:42048$1647_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42253$1648 + cell $or $or$libresoc.v:42049$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71807,10 +71603,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1276 connect \B \addr_en$1296 - connect \Y $or$libresoc.v:42253$1648_Y + connect \Y $or$libresoc.v:42049$1648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42254$1649 + cell $or $or$libresoc.v:42050$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71818,10 +71614,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1256 connect \B \$1374 - connect \Y $or$libresoc.v:42254$1649_Y + connect \Y $or$libresoc.v:42050$1649_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42255$1650 + cell $or $or$libresoc.v:42051$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71829,10 +71625,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1336 connect \B \addr_en$1356 - connect \Y $or$libresoc.v:42255$1650_Y + connect \Y $or$libresoc.v:42051$1650_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42256$1651 + cell $or $or$libresoc.v:42052$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71840,10 +71636,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1316 connect \B \$1378 - connect \Y $or$libresoc.v:42256$1651_Y + connect \Y $or$libresoc.v:42052$1651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42257$1652 + cell $or $or$libresoc.v:42053$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71851,10 +71647,10 @@ module \core parameter \Y_WIDTH 256 connect \A \$1376 connect \B \$1380 - connect \Y $or$libresoc.v:42257$1652_Y + connect \Y $or$libresoc.v:42053$1652_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42279$1674 + cell $or $or$libresoc.v:42075$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71862,10 +71658,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest6_o connect \B \fus_dest3_o$135 - connect \Y $or$libresoc.v:42279$1674_Y + connect \Y $or$libresoc.v:42075$1674_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42280$1675 + cell $or $or$libresoc.v:42076$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71873,10 +71669,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest3_o$134 connect \B \$1438 - connect \Y $or$libresoc.v:42280$1675_Y + connect \Y $or$libresoc.v:42076$1675_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42281$1676 + cell $or $or$libresoc.v:42077$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71884,10 +71680,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en$1419 connect \B \addr_en$1435 - connect \Y $or$libresoc.v:42281$1676_Y + connect \Y $or$libresoc.v:42077$1676_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42282$1677 + cell $or $or$libresoc.v:42078$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71895,10 +71691,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en$1403 connect \B \$1443 - connect \Y $or$libresoc.v:42282$1677_Y + connect \Y $or$libresoc.v:42078$1677_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42312$1708 + cell $or $or$libresoc.v:42108$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71906,10 +71702,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest4_o connect \B \fus_dest5_o - connect \Y $or$libresoc.v:42312$1708_Y + connect \Y $or$libresoc.v:42108$1708_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42313$1709 + cell $or $or$libresoc.v:42109$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71917,10 +71713,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest3_o$139 connect \B \fus_dest3_o$140 - connect \Y $or$libresoc.v:42313$1709_Y + connect \Y $or$libresoc.v:42109$1709_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42314$1710 + cell $or $or$libresoc.v:42110$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71928,10 +71724,10 @@ module \core parameter \Y_WIDTH 2 connect \A \$1520 connect \B \$1522 - connect \Y $or$libresoc.v:42314$1710_Y + connect \Y $or$libresoc.v:42110$1710_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42315$1711 + cell $or $or$libresoc.v:42111$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71939,10 +71735,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1469 connect \B \addr_en$1485 - connect \Y $or$libresoc.v:42315$1711_Y + connect \Y $or$libresoc.v:42111$1711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42316$1712 + cell $or $or$libresoc.v:42112$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71950,10 +71746,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1501 connect \B \addr_en$1517 - connect \Y $or$libresoc.v:42316$1712_Y + connect \Y $or$libresoc.v:42112$1712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42317$1713 + cell $or $or$libresoc.v:42113$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71961,10 +71757,10 @@ module \core parameter \Y_WIDTH 3 connect \A \$1526 connect \B \$1528 - connect \Y $or$libresoc.v:42317$1713_Y + connect \Y $or$libresoc.v:42113$1713_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42346$1742 + cell $or $or$libresoc.v:42142$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71972,10 +71768,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest5_o$144 connect \B \fus_dest4_o$145 - connect \Y $or$libresoc.v:42346$1742_Y + connect \Y $or$libresoc.v:42142$1742_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42347$1743 + cell $or $or$libresoc.v:42143$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71983,10 +71779,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest4_o$146 connect \B \fus_dest4_o$147 - connect \Y $or$libresoc.v:42347$1743_Y + connect \Y $or$libresoc.v:42143$1743_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42348$1744 + cell $or $or$libresoc.v:42144$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71994,10 +71790,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1605 connect \B \$1607 - connect \Y $or$libresoc.v:42348$1744_Y + connect \Y $or$libresoc.v:42144$1744_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42350$1747 + cell $or $or$libresoc.v:42146$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72005,10 +71801,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en$1553 connect \B \addr_en$1569 - connect \Y $or$libresoc.v:42350$1747_Y + connect \Y $or$libresoc.v:42146$1747_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42351$1748 + cell $or $or$libresoc.v:42147$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72016,10 +71812,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en$1585 connect \B \addr_en$1601 - connect \Y $or$libresoc.v:42351$1748_Y + connect \Y $or$libresoc.v:42147$1748_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42352$1749 + cell $or $or$libresoc.v:42148$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72027,10 +71823,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1613 connect \B \$1615 - connect \Y $or$libresoc.v:42352$1749_Y + connect \Y $or$libresoc.v:42148$1749_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42389$1787 + cell $or $or$libresoc.v:42185$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72038,10 +71834,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$153 connect \B \fus_dest2_o$154 - connect \Y $or$libresoc.v:42389$1787_Y + connect \Y $or$libresoc.v:42185$1787_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42390$1788 + cell $or $or$libresoc.v:42186$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72049,10 +71845,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest2_o$156 connect \B \fus_dest3_o$157 - connect \Y $or$libresoc.v:42390$1788_Y + connect \Y $or$libresoc.v:42186$1788_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42391$1789 + cell $or $or$libresoc.v:42187$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72060,10 +71856,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest3_o$155 connect \B \$1715 - connect \Y $or$libresoc.v:42391$1789_Y + connect \Y $or$libresoc.v:42187$1789_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42392$1790 + cell $or $or$libresoc.v:42188$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72071,10 +71867,10 @@ module \core parameter \Y_WIDTH 64 connect \A \$1713 connect \B \$1717 - connect \Y $or$libresoc.v:42392$1790_Y + connect \Y $or$libresoc.v:42188$1790_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42393$1791 + cell $or $or$libresoc.v:42189$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72082,10 +71878,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1646 connect \B \addr_en$1662 - connect \Y $or$libresoc.v:42393$1791_Y + connect \Y $or$libresoc.v:42189$1791_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42394$1792 + cell $or $or$libresoc.v:42190$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72093,10 +71889,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1694 connect \B \addr_en$1710 - connect \Y $or$libresoc.v:42394$1792_Y + connect \Y $or$libresoc.v:42190$1792_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42395$1793 + cell $or $or$libresoc.v:42191$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72104,10 +71900,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1678 connect \B \$1723 - connect \Y $or$libresoc.v:42395$1793_Y + connect \Y $or$libresoc.v:42191$1793_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42396$1794 + cell $or $or$libresoc.v:42192$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72115,10 +71911,10 @@ module \core parameter \Y_WIDTH 3 connect \A \$1721 connect \B \$1725 - connect \Y $or$libresoc.v:42396$1794_Y + connect \Y $or$libresoc.v:42192$1794_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42397$1795 + cell $or $or$libresoc.v:42193$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72126,10 +71922,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1643 connect \B \wp$1659 - connect \Y $or$libresoc.v:42397$1795_Y + connect \Y $or$libresoc.v:42193$1795_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42398$1796 + cell $or $or$libresoc.v:42194$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72137,10 +71933,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1691 connect \B \wp$1707 - connect \Y $or$libresoc.v:42398$1796_Y + connect \Y $or$libresoc.v:42194$1796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42399$1797 + cell $or $or$libresoc.v:42195$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72148,10 +71944,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1675 connect \B \$1731 - connect \Y $or$libresoc.v:42399$1797_Y + connect \Y $or$libresoc.v:42195$1797_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42400$1798 + cell $or $or$libresoc.v:42196$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72159,10 +71955,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1729 connect \B \$1733 - connect \Y $or$libresoc.v:42400$1798_Y + connect \Y $or$libresoc.v:42196$1798_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42415$1813 + cell $or $or$libresoc.v:42211$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72170,10 +71966,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest3_o$159 connect \B \fus_dest4_o$160 - connect \Y $or$libresoc.v:42415$1813_Y + connect \Y $or$libresoc.v:42211$1813_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42416$1814 + cell $or $or$libresoc.v:42212$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72181,10 +71977,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en$1754 connect \B \addr_en$1770 - connect \Y $or$libresoc.v:42416$1814_Y + connect \Y $or$libresoc.v:42212$1814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42459$1859 + cell $or $or$libresoc.v:42255$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72192,10 +71988,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$229 connect \B \$233 - connect \Y $or$libresoc.v:42459$1859_Y + connect \Y $or$libresoc.v:42255$1859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42461$1861 + cell $or $or$libresoc.v:42257$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72203,10 +71999,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$235 connect \B \$237 - connect \Y $or$libresoc.v:42461$1861_Y + connect \Y $or$libresoc.v:42257$1861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42465$1865 + cell $or $or$libresoc.v:42261$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72214,10 +72010,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$241 connect \B \$245 - connect \Y $or$libresoc.v:42465$1865_Y + connect \Y $or$libresoc.v:42261$1865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42473$1873 + cell $or $or$libresoc.v:42269$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72225,10 +72021,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$257 connect \B \$261 - connect \Y $or$libresoc.v:42473$1873_Y + connect \Y $or$libresoc.v:42269$1873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42475$1875 + cell $or $or$libresoc.v:42271$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72236,10 +72032,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$263 connect \B \$265 - connect \Y $or$libresoc.v:42475$1875_Y + connect \Y $or$libresoc.v:42271$1875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42480$1880 + cell $or $or$libresoc.v:42276$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72247,10 +72043,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$271 connect \B \$275 - connect \Y $or$libresoc.v:42480$1880_Y + connect \Y $or$libresoc.v:42276$1880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42482$1882 + cell $or $or$libresoc.v:42278$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72258,10 +72054,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$277 connect \B \$279 - connect \Y $or$libresoc.v:42482$1882_Y + connect \Y $or$libresoc.v:42278$1882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:42486$1886 + cell $or $or$libresoc.v:42282$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72269,10 +72065,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$283 connect \B \$287 - connect \Y $or$libresoc.v:42486$1886_Y + connect \Y $or$libresoc.v:42282$1886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42490$1890 + cell $or $or$libresoc.v:42286$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72280,10 +72076,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$291 connect \B \$295 - connect \Y $or$libresoc.v:42490$1890_Y + connect \Y $or$libresoc.v:42286$1890_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42495$1895 + cell $or $or$libresoc.v:42291$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72291,10 +72087,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$301 connect \B \$305 - connect \Y $or$libresoc.v:42495$1895_Y + connect \Y $or$libresoc.v:42291$1895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42497$1897 + cell $or $or$libresoc.v:42293$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72302,10 +72098,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$307 connect \B \$309 - connect \Y $or$libresoc.v:42497$1897_Y + connect \Y $or$libresoc.v:42293$1897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42502$1902 + cell $or $or$libresoc.v:42298$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72313,10 +72109,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$315 connect \B \$319 - connect \Y $or$libresoc.v:42502$1902_Y + connect \Y $or$libresoc.v:42298$1902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42504$1904 + cell $or $or$libresoc.v:42300$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72324,10 +72120,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$321 connect \B \$323 - connect \Y $or$libresoc.v:42504$1904_Y + connect \Y $or$libresoc.v:42300$1904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42509$1909 + cell $or $or$libresoc.v:42305$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72335,10 +72131,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$329 connect \B \$333 - connect \Y $or$libresoc.v:42509$1909_Y + connect \Y $or$libresoc.v:42305$1909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42511$1911 + cell $or $or$libresoc.v:42307$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72346,10 +72142,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$335 connect \B \$337 - connect \Y $or$libresoc.v:42511$1911_Y + connect \Y $or$libresoc.v:42307$1911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42515$1915 + cell $or $or$libresoc.v:42311$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72357,10 +72153,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$341 connect \B \$345 - connect \Y $or$libresoc.v:42515$1915_Y + connect \Y $or$libresoc.v:42311$1915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42632$2032 + cell $or $or$libresoc.v:42428$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72368,10 +72164,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_alu0_0 connect \B \addr_en_INT_rabc_cr0_1 - connect \Y $or$libresoc.v:42632$2032_Y + connect \Y $or$libresoc.v:42428$2032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42633$2033 + cell $or $or$libresoc.v:42429$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72379,10 +72175,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_trap0_2 connect \B \addr_en_INT_rabc_logical0_3 - connect \Y $or$libresoc.v:42633$2033_Y + connect \Y $or$libresoc.v:42429$2033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42634$2034 + cell $or $or$libresoc.v:42430$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72390,10 +72186,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$581 connect \B \$583 - connect \Y $or$libresoc.v:42634$2034_Y + connect \Y $or$libresoc.v:42430$2034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42635$2035 + cell $or $or$libresoc.v:42431$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72401,10 +72197,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_div0_4 connect \B \addr_en_INT_rabc_mul0_5 - connect \Y $or$libresoc.v:42635$2035_Y + connect \Y $or$libresoc.v:42431$2035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42636$2036 + cell $or $or$libresoc.v:42432$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72412,10 +72208,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_ldst0_7 connect \B \addr_en_INT_rabc_shiftrot0_8 - connect \Y $or$libresoc.v:42636$2036_Y + connect \Y $or$libresoc.v:42432$2036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42637$2037 + cell $or $or$libresoc.v:42433$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72423,10 +72219,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_shiftrot0_6 connect \B \$589 - connect \Y $or$libresoc.v:42637$2037_Y + connect \Y $or$libresoc.v:42433$2037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42638$2038 + cell $or $or$libresoc.v:42434$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72434,10 +72230,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$587 connect \B \$591 - connect \Y $or$libresoc.v:42638$2038_Y + connect \Y $or$libresoc.v:42434$2038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42639$2039 + cell $or $or$libresoc.v:42435$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72445,10 +72241,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$585 connect \B \$593 - connect \Y $or$libresoc.v:42639$2039_Y + connect \Y $or$libresoc.v:42435$2039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42640$2040 + cell $or $or$libresoc.v:42436$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72456,10 +72252,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_ldst0_9 connect \B \addr_en_INT_rabc_alu0_10 - connect \Y $or$libresoc.v:42640$2040_Y + connect \Y $or$libresoc.v:42436$2040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42641$2041 + cell $or $or$libresoc.v:42437$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72467,10 +72263,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_trap0_12 connect \B \addr_en_INT_rabc_logical0_13 - connect \Y $or$libresoc.v:42641$2041_Y + connect \Y $or$libresoc.v:42437$2041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42642$2042 + cell $or $or$libresoc.v:42438$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72478,10 +72274,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_cr0_11 connect \B \$599 - connect \Y $or$libresoc.v:42642$2042_Y + connect \Y $or$libresoc.v:42438$2042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42643$2043 + cell $or $or$libresoc.v:42439$2043 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72489,10 +72285,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$597 connect \B \$601 - connect \Y $or$libresoc.v:42643$2043_Y + connect \Y $or$libresoc.v:42439$2043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42644$2044 + cell $or $or$libresoc.v:42440$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72500,10 +72296,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_spr0_14 connect \B \addr_en_INT_rabc_div0_15 - connect \Y $or$libresoc.v:42644$2044_Y + connect \Y $or$libresoc.v:42440$2044_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42645$2045 + cell $or $or$libresoc.v:42441$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72511,10 +72307,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_shiftrot0_17 connect \B \addr_en_INT_rabc_ldst0_18 - connect \Y $or$libresoc.v:42645$2045_Y + connect \Y $or$libresoc.v:42441$2045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42646$2046 + cell $or $or$libresoc.v:42442$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72522,10 +72318,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_mul0_16 connect \B \$607 - connect \Y $or$libresoc.v:42646$2046_Y + connect \Y $or$libresoc.v:42442$2046_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42647$2047 + cell $or $or$libresoc.v:42443$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72533,10 +72329,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$605 connect \B \$609 - connect \Y $or$libresoc.v:42647$2047_Y + connect \Y $or$libresoc.v:42443$2047_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42648$2048 + cell $or $or$libresoc.v:42444$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72544,10 +72340,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$603 connect \B \$611 - connect \Y $or$libresoc.v:42648$2048_Y + connect \Y $or$libresoc.v:42444$2048_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42649$2049 + cell $or $or$libresoc.v:42445$2049 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72555,10 +72351,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$595 connect \B \$613 - connect \Y $or$libresoc.v:42649$2049_Y + connect \Y $or$libresoc.v:42445$2049_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42654$2054 + cell $or $or$libresoc.v:42450$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72566,10 +72362,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$619 connect \B \$623 - connect \Y $or$libresoc.v:42654$2054_Y + connect \Y $or$libresoc.v:42450$2054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42656$2056 + cell $or $or$libresoc.v:42452$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72577,10 +72373,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$625 connect \B \$627 - connect \Y $or$libresoc.v:42656$2056_Y + connect \Y $or$libresoc.v:42452$2056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42693$2093 + cell $or $or$libresoc.v:42489$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72588,10 +72384,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_logical0_1 connect \B \addr_en_XER_xer_so_spr0_2 - connect \Y $or$libresoc.v:42693$2093_Y + connect \Y $or$libresoc.v:42489$2093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42694$2094 + cell $or $or$libresoc.v:42490$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72599,10 +72395,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_alu0_0 connect \B \$704 - connect \Y $or$libresoc.v:42694$2094_Y + connect \Y $or$libresoc.v:42490$2094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42695$2095 + cell $or $or$libresoc.v:42491$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72610,10 +72406,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_mul0_4 connect \B \addr_en_XER_xer_so_shiftrot0_5 - connect \Y $or$libresoc.v:42695$2095_Y + connect \Y $or$libresoc.v:42491$2095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42696$2096 + cell $or $or$libresoc.v:42492$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72621,10 +72417,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_div0_3 connect \B \$708 - connect \Y $or$libresoc.v:42696$2096_Y + connect \Y $or$libresoc.v:42492$2096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42697$2097 + cell $or $or$libresoc.v:42493$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72632,10 +72428,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$706 connect \B \$710 - connect \Y $or$libresoc.v:42697$2097_Y + connect \Y $or$libresoc.v:42493$2097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42702$2103 + cell $or $or$libresoc.v:42498$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72643,10 +72439,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$715 connect \B \$719 - connect \Y $or$libresoc.v:42702$2103_Y + connect \Y $or$libresoc.v:42498$2103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42721$2122 + cell $or $or$libresoc.v:42517$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72654,10 +72450,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_spr0_1 connect \B \addr_en_XER_xer_ca_shiftrot0_2 - connect \Y $or$libresoc.v:42721$2122_Y + connect \Y $or$libresoc.v:42517$2122_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42722$2123 + cell $or $or$libresoc.v:42518$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72665,10 +72461,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_alu0_0 connect \B \$760 - connect \Y $or$libresoc.v:42722$2123_Y + connect \Y $or$libresoc.v:42518$2123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:42727$2129 + cell $or $or$libresoc.v:42523$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72676,10 +72472,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$765 connect \B \$769 - connect \Y $or$libresoc.v:42727$2129_Y + connect \Y $or$libresoc.v:42523$2129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42756$2158 + cell $or $or$libresoc.v:42552$2158 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -72687,10 +72483,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en_CR_cr_a_cr0_0 connect \B \addr_en_CR_cr_a_branch0_1 - connect \Y $or$libresoc.v:42756$2158_Y + connect \Y $or$libresoc.v:42552$2158_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42803$2205 + cell $or $or$libresoc.v:42599$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72698,10 +72494,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_branch0_0 connect \B \addr_en_FAST_fast1_trap0_1 - connect \Y $or$libresoc.v:42803$2205_Y + connect \Y $or$libresoc.v:42599$2205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42804$2206 + cell $or $or$libresoc.v:42600$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72709,10 +72505,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_branch0_3 connect \B \addr_en_FAST_fast1_trap0_4 - connect \Y $or$libresoc.v:42804$2206_Y + connect \Y $or$libresoc.v:42600$2206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42805$2207 + cell $or $or$libresoc.v:42601$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72720,10 +72516,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_spr0_2 connect \B \$926 - connect \Y $or$libresoc.v:42805$2207_Y + connect \Y $or$libresoc.v:42601$2207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42806$2208 + cell $or $or$libresoc.v:42602$2208 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72731,170 +72527,170 @@ module \core parameter \Y_WIDTH 3 connect \A \$924 connect \B \$928 - connect \Y $or$libresoc.v:42806$2208_Y + connect \Y $or$libresoc.v:42602$2208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42283$1679 + cell $pos $pos$libresoc.v:42079$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42283$1678_Y - connect \Y $pos$libresoc.v:42283$1679_Y + connect \A $extend$libresoc.v:42079$1678_Y + connect \Y $pos$libresoc.v:42079$1679_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42349$1746 + cell $pos $pos$libresoc.v:42145$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:42349$1745_Y - connect \Y $pos$libresoc.v:42349$1746_Y + connect \A $extend$libresoc.v:42145$1745_Y + connect \Y $pos$libresoc.v:42145$1746_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42353$1751 + cell $pos $pos$libresoc.v:42149$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42353$1750_Y - connect \Y $pos$libresoc.v:42353$1751_Y + connect \A $extend$libresoc.v:42149$1750_Y + connect \Y $pos$libresoc.v:42149$1751_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $pos $pos$libresoc.v:42417$1816 + cell $pos $pos$libresoc.v:42213$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42417$1815_Y - connect \Y $pos$libresoc.v:42417$1816_Y + connect \A $extend$libresoc.v:42213$1815_Y + connect \Y $pos$libresoc.v:42213$1816_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" - cell $pos $pos$libresoc.v:42425$1825 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" + cell $pos $pos$libresoc.v:42221$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42425$1824_Y - connect \Y $pos$libresoc.v:42425$1825_Y + connect \A $extend$libresoc.v:42221$1824_Y + connect \Y $pos$libresoc.v:42221$1825_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42698$2099 + cell $pos $pos$libresoc.v:42494$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42698$2098_Y - connect \Y $pos$libresoc.v:42698$2099_Y + connect \A $extend$libresoc.v:42494$2098_Y + connect \Y $pos$libresoc.v:42494$2099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42723$2125 + cell $pos $pos$libresoc.v:42519$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42723$2124_Y - connect \Y $pos$libresoc.v:42723$2125_Y + connect \A $extend$libresoc.v:42519$2124_Y + connect \Y $pos$libresoc.v:42519$2125_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $reduce_or $reduce_or$libresoc.v:42434$1834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42230$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$182 - connect \Y $reduce_or$libresoc.v:42434$1834_Y + connect \Y $reduce_or$libresoc.v:42230$1834_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $reduce_or $reduce_or$libresoc.v:42436$1836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42232$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$186 - connect \Y $reduce_or$libresoc.v:42436$1836_Y + connect \Y $reduce_or$libresoc.v:42232$1836_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $reduce_or $reduce_or$libresoc.v:42438$1838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42234$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$190 - connect \Y $reduce_or$libresoc.v:42438$1838_Y + connect \Y $reduce_or$libresoc.v:42234$1838_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $reduce_or $reduce_or$libresoc.v:42440$1840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42236$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$194 - connect \Y $reduce_or$libresoc.v:42440$1840_Y + connect \Y $reduce_or$libresoc.v:42236$1840_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $reduce_or $reduce_or$libresoc.v:42442$1842 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42238$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$198 - connect \Y $reduce_or$libresoc.v:42442$1842_Y + connect \Y $reduce_or$libresoc.v:42238$1842_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $reduce_or $reduce_or$libresoc.v:42444$1844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42240$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$202 - connect \Y $reduce_or$libresoc.v:42444$1844_Y + connect \Y $reduce_or$libresoc.v:42240$1844_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $reduce_or $reduce_or$libresoc.v:42446$1846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42242$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$206 - connect \Y $reduce_or$libresoc.v:42446$1846_Y + connect \Y $reduce_or$libresoc.v:42242$1846_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $reduce_or $reduce_or$libresoc.v:42448$1848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42244$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$210 - connect \Y $reduce_or$libresoc.v:42448$1848_Y + connect \Y $reduce_or$libresoc.v:42244$1848_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $reduce_or $reduce_or$libresoc.v:42450$1850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42246$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$214 - connect \Y $reduce_or$libresoc.v:42450$1850_Y + connect \Y $reduce_or$libresoc.v:42246$1850_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - cell $reduce_or $reduce_or$libresoc.v:42452$1852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42248$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$218 - connect \Y $reduce_or$libresoc.v:42452$1852_Y + connect \Y $reduce_or$libresoc.v:42248$1852_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $reduce_or $reduce_or$libresoc.v:42650$2050 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" + cell $reduce_or $reduce_or$libresoc.v:42446$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 19 parameter \Y_WIDTH 1 connect \A { \rp_INT_rabc_ldst0_18 \rp_INT_rabc_shiftrot0_17 \rp_INT_rabc_mul0_16 \rp_INT_rabc_div0_15 \rp_INT_rabc_spr0_14 \rp_INT_rabc_logical0_13 \rp_INT_rabc_trap0_12 \rp_INT_rabc_cr0_11 \rp_INT_rabc_alu0_10 \rp_INT_rabc_ldst0_9 \rp_INT_rabc_shiftrot0_8 \rp_INT_rabc_ldst0_7 \rp_INT_rabc_shiftrot0_6 \rp_INT_rabc_mul0_5 \rp_INT_rabc_div0_4 \rp_INT_rabc_logical0_3 \rp_INT_rabc_trap0_2 \rp_INT_rabc_cr0_1 \rp_INT_rabc_alu0_0 } - connect \Y $reduce_or$libresoc.v:42650$2050_Y + connect \Y $reduce_or$libresoc.v:42446$2050_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $reduce_or $reduce_or$libresoc.v:42807$2209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" + cell $reduce_or $reduce_or$libresoc.v:42603$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast1_trap0_4 \rp_FAST_fast1_branch0_3 \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } - connect \Y $reduce_or$libresoc.v:42807$2209_Y + connect \Y $reduce_or$libresoc.v:42603$2209_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320" - cell $reduce_or $reduce_or$libresoc.v:42814$2216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" + cell $reduce_or $reduce_or$libresoc.v:42610$2216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rp_SPR_spr1_spr0_0 - connect \Y $reduce_or$libresoc.v:42814$2216_Y + connect \Y $reduce_or$libresoc.v:42610$2216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42206$1601 + cell $sshl $sshl$libresoc.v:42002$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72902,10 +72698,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1257 - connect \Y $sshl$libresoc.v:42206$1601_Y + connect \Y $sshl$libresoc.v:42002$1601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42214$1609 + cell $sshl $sshl$libresoc.v:42010$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72913,10 +72709,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1277 - connect \Y $sshl$libresoc.v:42214$1609_Y + connect \Y $sshl$libresoc.v:42010$1609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42222$1617 + cell $sshl $sshl$libresoc.v:42018$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72924,10 +72720,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1297 - connect \Y $sshl$libresoc.v:42222$1617_Y + connect \Y $sshl$libresoc.v:42018$1617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42230$1625 + cell $sshl $sshl$libresoc.v:42026$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72935,10 +72731,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1317 - connect \Y $sshl$libresoc.v:42230$1625_Y + connect \Y $sshl$libresoc.v:42026$1625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42238$1633 + cell $sshl $sshl$libresoc.v:42034$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72946,10 +72742,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1337 - connect \Y $sshl$libresoc.v:42238$1633_Y + connect \Y $sshl$libresoc.v:42034$1633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42246$1641 + cell $sshl $sshl$libresoc.v:42042$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72957,10 +72753,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1357 - connect \Y $sshl$libresoc.v:42246$1641_Y + connect \Y $sshl$libresoc.v:42042$1641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42746$2148 + cell $sshl $sshl$libresoc.v:42542$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72968,10 +72764,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$807 - connect \Y $sshl$libresoc.v:42746$2148_Y + connect \Y $sshl$libresoc.v:42542$2148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42754$2156 + cell $sshl $sshl$libresoc.v:42550$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72979,10 +72775,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$823 - connect \Y $sshl$libresoc.v:42754$2156_Y + connect \Y $sshl$libresoc.v:42550$2156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sshl $sshl$libresoc.v:42763$2165 + cell $sshl $sshl$libresoc.v:42559$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72990,10 +72786,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$842 - connect \Y $sshl$libresoc.v:42763$2165_Y + connect \Y $sshl$libresoc.v:42559$2165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sshl $sshl$libresoc.v:42771$2173 + cell $sshl $sshl$libresoc.v:42567$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -73001,10 +72797,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$858 - connect \Y $sshl$libresoc.v:42771$2173_Y + connect \Y $sshl$libresoc.v:42567$2173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42205$1600 + cell $sub $sub$libresoc.v:42001$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73012,10 +72808,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42205$1600_Y + connect \Y $sub$libresoc.v:42001$1600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42213$1608 + cell $sub $sub$libresoc.v:42009$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73023,10 +72819,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42213$1608_Y + connect \Y $sub$libresoc.v:42009$1608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42221$1616 + cell $sub $sub$libresoc.v:42017$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73034,10 +72830,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42221$1616_Y + connect \Y $sub$libresoc.v:42017$1616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42229$1624 + cell $sub $sub$libresoc.v:42025$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73045,10 +72841,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42229$1624_Y + connect \Y $sub$libresoc.v:42025$1624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42237$1632 + cell $sub $sub$libresoc.v:42033$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73056,10 +72852,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42237$1632_Y + connect \Y $sub$libresoc.v:42033$1632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42245$1640 + cell $sub $sub$libresoc.v:42041$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73067,10 +72863,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42245$1640_Y + connect \Y $sub$libresoc.v:42041$1640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" - cell $sub $sub$libresoc.v:42454$1854 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" + cell $sub $sub$libresoc.v:42250$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -73078,10 +72874,10 @@ module \core parameter \Y_WIDTH 3 connect \A \counter connect \B 1'1 - connect \Y $sub$libresoc.v:42454$1854_Y + connect \Y $sub$libresoc.v:42250$1854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42745$2147 + cell $sub $sub$libresoc.v:42541$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73089,10 +72885,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42745$2147_Y + connect \Y $sub$libresoc.v:42541$2147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42753$2155 + cell $sub $sub$libresoc.v:42549$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73100,10 +72896,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42753$2155_Y + connect \Y $sub$libresoc.v:42549$2155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sub $sub$libresoc.v:42762$2164 + cell $sub $sub$libresoc.v:42558$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73111,10 +72907,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2 - connect \Y $sub$libresoc.v:42762$2164_Y + connect \Y $sub$libresoc.v:42558$2164_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sub $sub$libresoc.v:42770$2172 + cell $sub $sub$libresoc.v:42566$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73122,626 +72918,626 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2$1 - connect \Y $sub$libresoc.v:42770$2172_Y + connect \Y $sub$libresoc.v:42566$2172_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42111$1506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41907$1506 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$997 - connect \Y $ternary$libresoc.v:42111$1506_Y + connect \Y $ternary$libresoc.v:41907$1506_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42117$1512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41913$1512 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1018 - connect \Y $ternary$libresoc.v:42117$1512_Y + connect \Y $ternary$libresoc.v:41913$1512_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42123$1518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41919$1518 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1036 - connect \Y $ternary$libresoc.v:42123$1518_Y + connect \Y $ternary$libresoc.v:41919$1518_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42129$1524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41925$1524 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1058 - connect \Y $ternary$libresoc.v:42129$1524_Y + connect \Y $ternary$libresoc.v:41925$1524_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42135$1530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41931$1530 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1078 - connect \Y $ternary$libresoc.v:42135$1530_Y + connect \Y $ternary$libresoc.v:41931$1530_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42141$1536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41937$1536 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1098 - connect \Y $ternary$libresoc.v:42141$1536_Y + connect \Y $ternary$libresoc.v:41937$1536_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42147$1542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41943$1542 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1117 - connect \Y $ternary$libresoc.v:42147$1542_Y + connect \Y $ternary$libresoc.v:41943$1542_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42153$1548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41949$1548 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1135 - connect \Y $ternary$libresoc.v:42153$1548_Y + connect \Y $ternary$libresoc.v:41949$1548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42159$1554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41955$1554 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_ea connect \S \wp$1151 - connect \Y $ternary$libresoc.v:42159$1554_Y + connect \Y $ternary$libresoc.v:41955$1554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42193$1588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41989$1588 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_wr connect \S \wp$1225 - connect \Y $ternary$libresoc.v:42193$1588_Y + connect \Y $ternary$libresoc.v:41989$1588_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42207$1602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42003$1602 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1259 connect \S \wp$1253 - connect \Y $ternary$libresoc.v:42207$1602_Y + connect \Y $ternary$libresoc.v:42003$1602_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42215$1610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42011$1610 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1279 connect \S \wp$1273 - connect \Y $ternary$libresoc.v:42215$1610_Y + connect \Y $ternary$libresoc.v:42011$1610_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42223$1618 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42019$1618 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1299 connect \S \wp$1293 - connect \Y $ternary$libresoc.v:42223$1618_Y + connect \Y $ternary$libresoc.v:42019$1618_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42231$1626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42027$1626 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1319 connect \S \wp$1313 - connect \Y $ternary$libresoc.v:42231$1626_Y + connect \Y $ternary$libresoc.v:42027$1626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42239$1634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42035$1634 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1339 connect \S \wp$1333 - connect \Y $ternary$libresoc.v:42239$1634_Y + connect \Y $ternary$libresoc.v:42035$1634_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42247$1642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42043$1642 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1359 connect \S \wp$1353 - connect \Y $ternary$libresoc.v:42247$1642_Y + connect \Y $ternary$libresoc.v:42043$1642_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42266$1661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42062$1661 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1400 - connect \Y $ternary$libresoc.v:42266$1661_Y + connect \Y $ternary$libresoc.v:42062$1661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42272$1667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42068$1667 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1416 - connect \Y $ternary$libresoc.v:42272$1667_Y + connect \Y $ternary$libresoc.v:42068$1667_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42278$1673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42074$1673 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1432 - connect \Y $ternary$libresoc.v:42278$1673_Y + connect \Y $ternary$libresoc.v:42074$1673_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42293$1689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42089$1689 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1466 - connect \Y $ternary$libresoc.v:42293$1689_Y + connect \Y $ternary$libresoc.v:42089$1689_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42299$1695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42095$1695 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1482 - connect \Y $ternary$libresoc.v:42299$1695_Y + connect \Y $ternary$libresoc.v:42095$1695_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42305$1701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42101$1701 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1498 - connect \Y $ternary$libresoc.v:42305$1701_Y + connect \Y $ternary$libresoc.v:42101$1701_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42311$1707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42107$1707 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1514 - connect \Y $ternary$libresoc.v:42311$1707_Y + connect \Y $ternary$libresoc.v:42107$1707_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42327$1723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42123$1723 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1550 - connect \Y $ternary$libresoc.v:42327$1723_Y + connect \Y $ternary$libresoc.v:42123$1723_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42333$1729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42129$1729 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1566 - connect \Y $ternary$libresoc.v:42333$1729_Y + connect \Y $ternary$libresoc.v:42129$1729_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42339$1735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42135$1735 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1582 - connect \Y $ternary$libresoc.v:42339$1735_Y + connect \Y $ternary$libresoc.v:42135$1735_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42345$1741 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42141$1741 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1598 - connect \Y $ternary$libresoc.v:42345$1741_Y + connect \Y $ternary$libresoc.v:42141$1741_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42364$1762 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42160$1762 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1643 - connect \Y $ternary$libresoc.v:42364$1762_Y + connect \Y $ternary$libresoc.v:42160$1762_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42370$1768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42166$1768 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1659 - connect \Y $ternary$libresoc.v:42370$1768_Y + connect \Y $ternary$libresoc.v:42166$1768_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42376$1774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42172$1774 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1675 - connect \Y $ternary$libresoc.v:42376$1774_Y + connect \Y $ternary$libresoc.v:42172$1774_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42382$1780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42178$1780 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 connect \S \wp$1691 - connect \Y $ternary$libresoc.v:42382$1780_Y + connect \Y $ternary$libresoc.v:42178$1780_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42388$1786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42184$1786 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 connect \S \wp$1707 - connect \Y $ternary$libresoc.v:42388$1786_Y + connect \Y $ternary$libresoc.v:42184$1786_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42408$1806 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42204$1806 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1751 - connect \Y $ternary$libresoc.v:42408$1806_Y + connect \Y $ternary$libresoc.v:42204$1806_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42414$1812 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42210$1812 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1767 - connect \Y $ternary$libresoc.v:42414$1812_Y + connect \Y $ternary$libresoc.v:42210$1812_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42424$1823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42220$1823 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1791 - connect \Y $ternary$libresoc.v:42424$1823_Y + connect \Y $ternary$libresoc.v:42220$1823_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42432$1832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42228$1832 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spro connect \S \wp$1811 - connect \Y $ternary$libresoc.v:42432$1832_Y + connect \Y $ternary$libresoc.v:42228$1832_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42523$1923 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42319$1923 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_alu0_0 - connect \Y $ternary$libresoc.v:42523$1923_Y + connect \Y $ternary$libresoc.v:42319$1923_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42529$1929 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42325$1929 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_cr0_1 - connect \Y $ternary$libresoc.v:42529$1929_Y + connect \Y $ternary$libresoc.v:42325$1929_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42535$1935 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42331$1935 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_trap0_2 - connect \Y $ternary$libresoc.v:42535$1935_Y + connect \Y $ternary$libresoc.v:42331$1935_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42541$1941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42337$1941 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_logical0_3 - connect \Y $ternary$libresoc.v:42541$1941_Y + connect \Y $ternary$libresoc.v:42337$1941_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42547$1947 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42343$1947 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_div0_4 - connect \Y $ternary$libresoc.v:42547$1947_Y + connect \Y $ternary$libresoc.v:42343$1947_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42553$1953 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42349$1953 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_mul0_5 - connect \Y $ternary$libresoc.v:42553$1953_Y + connect \Y $ternary$libresoc.v:42349$1953_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42559$1959 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42355$1959 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_shiftrot0_6 - connect \Y $ternary$libresoc.v:42559$1959_Y + connect \Y $ternary$libresoc.v:42355$1959_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42565$1965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42361$1965 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_ldst0_7 - connect \Y $ternary$libresoc.v:42565$1965_Y + connect \Y $ternary$libresoc.v:42361$1965_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42571$1971 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42367$1971 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rabc_shiftrot0_8 - connect \Y $ternary$libresoc.v:42571$1971_Y + connect \Y $ternary$libresoc.v:42367$1971_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42577$1977 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42373$1977 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rabc_ldst0_9 - connect \Y $ternary$libresoc.v:42577$1977_Y + connect \Y $ternary$libresoc.v:42373$1977_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42583$1983 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42379$1983 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_alu0_10 - connect \Y $ternary$libresoc.v:42583$1983_Y + connect \Y $ternary$libresoc.v:42379$1983_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42589$1989 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42385$1989 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_cr0_11 - connect \Y $ternary$libresoc.v:42589$1989_Y + connect \Y $ternary$libresoc.v:42385$1989_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42595$1995 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42391$1995 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_trap0_12 - connect \Y $ternary$libresoc.v:42595$1995_Y + connect \Y $ternary$libresoc.v:42391$1995_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42601$2001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42397$2001 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_logical0_13 - connect \Y $ternary$libresoc.v:42601$2001_Y + connect \Y $ternary$libresoc.v:42397$2001_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42607$2007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42403$2007 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_spr0_14 - connect \Y $ternary$libresoc.v:42607$2007_Y + connect \Y $ternary$libresoc.v:42403$2007_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42613$2013 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42409$2013 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_div0_15 - connect \Y $ternary$libresoc.v:42613$2013_Y + connect \Y $ternary$libresoc.v:42409$2013_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42619$2019 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42415$2019 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_mul0_16 - connect \Y $ternary$libresoc.v:42619$2019_Y + connect \Y $ternary$libresoc.v:42415$2019_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42625$2025 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42421$2025 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_shiftrot0_17 - connect \Y $ternary$libresoc.v:42625$2025_Y + connect \Y $ternary$libresoc.v:42421$2025_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42631$2031 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42427$2031 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_ldst0_18 - connect \Y $ternary$libresoc.v:42631$2031_Y + connect \Y $ternary$libresoc.v:42427$2031_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42662$2062 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42458$2062 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_alu0_0 - connect \Y $ternary$libresoc.v:42662$2062_Y + connect \Y $ternary$libresoc.v:42458$2062_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42668$2068 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42464$2068 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_logical0_1 - connect \Y $ternary$libresoc.v:42668$2068_Y + connect \Y $ternary$libresoc.v:42464$2068_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42674$2074 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42470$2074 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_spr0_2 - connect \Y $ternary$libresoc.v:42674$2074_Y + connect \Y $ternary$libresoc.v:42470$2074_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42680$2080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42476$2080 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_div0_3 - connect \Y $ternary$libresoc.v:42680$2080_Y + connect \Y $ternary$libresoc.v:42476$2080_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42686$2086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42482$2086 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_mul0_4 - connect \Y $ternary$libresoc.v:42686$2086_Y + connect \Y $ternary$libresoc.v:42482$2086_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42692$2092 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42488$2092 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_shiftrot0_5 - connect \Y $ternary$libresoc.v:42692$2092_Y + connect \Y $ternary$libresoc.v:42488$2092_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42708$2109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42504$2109 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $ternary$libresoc.v:42708$2109_Y + connect \Y $ternary$libresoc.v:42504$2109_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42714$2115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42510$2115 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $ternary$libresoc.v:42714$2115_Y + connect \Y $ternary$libresoc.v:42510$2115_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42720$2121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42516$2121 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $ternary$libresoc.v:42720$2121_Y + connect \Y $ternary$libresoc.v:42516$2121_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42733$2135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42529$2135 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $ternary$libresoc.v:42733$2135_Y + connect \Y $ternary$libresoc.v:42529$2135_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42739$2141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42535$2141 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_rd connect \S \rp_CR_full_cr_cr0_0 - connect \Y $ternary$libresoc.v:42739$2141_Y + connect \Y $ternary$libresoc.v:42535$2141_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42747$2149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42543$2149 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$809 connect \S \rp_CR_cr_a_cr0_0 - connect \Y $ternary$libresoc.v:42747$2149_Y + connect \Y $ternary$libresoc.v:42543$2149_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42755$2157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42551$2157 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$825 connect \S \rp_CR_cr_a_branch0_1 - connect \Y $ternary$libresoc.v:42755$2157_Y + connect \Y $ternary$libresoc.v:42551$2157_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42764$2166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42560$2166 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$844 connect \S \rp_CR_cr_b_cr0_0 - connect \Y $ternary$libresoc.v:42764$2166_Y + connect \Y $ternary$libresoc.v:42560$2166_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42772$2174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42568$2174 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$860 connect \S \rp_CR_cr_c_cr0_0 - connect \Y $ternary$libresoc.v:42772$2174_Y + connect \Y $ternary$libresoc.v:42568$2174_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42778$2180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42574$2180 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_branch0_0 - connect \Y $ternary$libresoc.v:42778$2180_Y + connect \Y $ternary$libresoc.v:42574$2180_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42784$2186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42580$2186 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_trap0_1 - connect \Y $ternary$libresoc.v:42784$2186_Y + connect \Y $ternary$libresoc.v:42580$2186_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42790$2192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42586$2192 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_spr0_2 - connect \Y $ternary$libresoc.v:42790$2192_Y + connect \Y $ternary$libresoc.v:42586$2192_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42796$2198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42592$2198 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast1_branch0_3 - connect \Y $ternary$libresoc.v:42796$2198_Y + connect \Y $ternary$libresoc.v:42592$2198_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42802$2204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42598$2204 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast1_trap0_4 - connect \Y $ternary$libresoc.v:42802$2204_Y + connect \Y $ternary$libresoc.v:42598$2204_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293" - cell $mux $ternary$libresoc.v:42813$2215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42609$2215 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spr1 connect \S \rp_SPR_spr1_spr0_0 - connect \Y $ternary$libresoc.v:42813$2215_Y + connect \Y $ternary$libresoc.v:42609$2215_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:425" - cell $mux $ternary$libresoc.v:42830$2232 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42626$2232 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp - connect \Y $ternary$libresoc.v:42830$2232_Y + connect \Y $ternary$libresoc.v:42626$2232_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:42994.6-43011.4" + attribute \src "libresoc.v:42790.6-42807.4" cell \cr \cr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73761,7 +73557,7 @@ module \core connect \wen \cr_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43012.11-43034.4" + attribute \src "libresoc.v:42808.11-42830.4" cell \dec_ALU \dec_ALU connect \ALU__data_len \dec_ALU_ALU__data_len connect \ALU__fn_unit \dec_ALU_ALU__fn_unit @@ -73786,7 +73582,7 @@ module \core connect \sv_a_nz \dec_ALU_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43035.14-43047.4" + attribute \src "libresoc.v:42831.14-42843.4" cell \dec_BRANCH \dec_BRANCH connect \BRANCH__cia \dec_BRANCH_BRANCH__cia connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit @@ -73801,7 +73597,7 @@ module \core connect \raw_opcode_in \dec_BRANCH_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43048.10-43054.4" + attribute \src "libresoc.v:42844.10-42850.4" cell \dec_CR \dec_CR connect \CR__fn_unit \dec_CR_CR__fn_unit connect \CR__insn \dec_CR_CR__insn @@ -73810,7 +73606,7 @@ module \core connect \raw_opcode_in \dec_CR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43055.11-43077.4" + attribute \src "libresoc.v:42851.11-42873.4" cell \dec_DIV \dec_DIV connect \DIV__data_len \dec_DIV_DIV__data_len connect \DIV__fn_unit \dec_DIV_DIV__fn_unit @@ -73835,7 +73631,7 @@ module \core connect \sv_a_nz \dec_DIV_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43078.12-43098.4" + attribute \src "libresoc.v:42874.12-42894.4" cell \dec_LDST \dec_LDST connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse connect \LDST__data_len \dec_LDST_LDST__data_len @@ -73858,7 +73654,7 @@ module \core connect \sv_a_nz \dec_LDST_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43099.15-43121.4" + attribute \src "libresoc.v:42895.15-42917.4" cell \dec_LOGICAL \dec_LOGICAL connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit @@ -73883,7 +73679,7 @@ module \core connect \sv_a_nz \dec_LOGICAL_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43122.11-43137.4" + attribute \src "libresoc.v:42918.11-42933.4" cell \dec_MUL \dec_MUL connect \MUL__fn_unit \dec_MUL_MUL__fn_unit connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data @@ -73901,7 +73697,7 @@ module \core connect \raw_opcode_in \dec_MUL_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43138.17-43158.4" + attribute \src "libresoc.v:42934.17-42954.4" cell \dec_SHIFT_ROT \dec_SHIFT_ROT connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data @@ -73924,7 +73720,7 @@ module \core connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43159.11-43166.4" + attribute \src "libresoc.v:42955.11-42962.4" cell \dec_SPR \dec_SPR connect \SPR__fn_unit \dec_SPR_SPR__fn_unit connect \SPR__insn \dec_SPR_SPR__insn @@ -73934,7 +73730,7 @@ module \core connect \raw_opcode_in \dec_SPR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43167.8-43182.4" + attribute \src "libresoc.v:42963.8-42978.4" cell \fast \fast connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73952,7 +73748,7 @@ module \core connect \src1__ren \fast_src1__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:43183.7-43514.4" + attribute \src "libresoc.v:42979.7-43310.4" cell \fus \fus connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74286,7 +74082,7 @@ module \core connect \xer_so_ok$131 \fus_xer_so_ok$143 end attribute \module_not_derived 1 - attribute \src "libresoc.v:43515.9-43527.4" + attribute \src "libresoc.v:43311.9-43323.4" cell \int \int connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74296,12 +74092,12 @@ module \core connect \dmi__addr \dmi__addr connect \dmi__data_o \dmi__data_o connect \dmi__ren \dmi__ren - connect \src__addr \int_src__addr - connect \src__data_o \int_src__data_o - connect \src__ren \int_src__ren + connect \src1__addr \int_src1__addr + connect \src1__data_o \int_src1__data_o + connect \src1__ren \int_src1__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:43528.6-43560.4" + attribute \src "libresoc.v:43324.6-43356.4" cell \l0 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74336,77 +74132,77 @@ module \core connect \wb_dcache_en \wb_dcache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:43561.18-43565.4" + attribute \src "libresoc.v:43357.18-43361.4" cell \rdpick_CR_cr_a \rdpick_CR_cr_a connect \en_o \rdpick_CR_cr_a_en_o connect \i \rdpick_CR_cr_a_i connect \o \rdpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43566.18-43570.4" + attribute \src "libresoc.v:43362.18-43366.4" cell \rdpick_CR_cr_b \rdpick_CR_cr_b connect \en_o \rdpick_CR_cr_b_en_o connect \i \rdpick_CR_cr_b_i connect \o \rdpick_CR_cr_b_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43571.18-43575.4" + attribute \src "libresoc.v:43367.18-43371.4" cell \rdpick_CR_cr_c \rdpick_CR_cr_c connect \en_o \rdpick_CR_cr_c_en_o connect \i \rdpick_CR_cr_c_i connect \o \rdpick_CR_cr_c_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43576.21-43580.4" + attribute \src "libresoc.v:43372.21-43376.4" cell \rdpick_CR_full_cr \rdpick_CR_full_cr connect \en_o \rdpick_CR_full_cr_en_o connect \i \rdpick_CR_full_cr_i connect \o \rdpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43581.21-43585.4" + attribute \src "libresoc.v:43377.21-43381.4" cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 connect \en_o \rdpick_FAST_fast1_en_o connect \i \rdpick_FAST_fast1_i connect \o \rdpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43586.19-43590.4" + attribute \src "libresoc.v:43382.19-43386.4" cell \rdpick_INT_rabc \rdpick_INT_rabc connect \en_o \rdpick_INT_rabc_en_o connect \i \rdpick_INT_rabc_i connect \o \rdpick_INT_rabc_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43591.19-43595.4" + attribute \src "libresoc.v:43387.19-43391.4" cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 connect \en_o \rdpick_SPR_spr1_en_o connect \i \rdpick_SPR_spr1_i connect \o \rdpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43596.21-43600.4" + attribute \src "libresoc.v:43392.21-43396.4" cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca connect \en_o \rdpick_XER_xer_ca_en_o connect \i \rdpick_XER_xer_ca_i connect \o \rdpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43601.21-43605.4" + attribute \src "libresoc.v:43397.21-43401.4" cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov connect \en_o \rdpick_XER_xer_ov_en_o connect \i \rdpick_XER_xer_ov_i connect \o \rdpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43606.21-43610.4" + attribute \src "libresoc.v:43402.21-43406.4" cell \rdpick_XER_xer_so \rdpick_XER_xer_so connect \en_o \rdpick_XER_xer_so_en_o connect \i \rdpick_XER_xer_so_i connect \o \rdpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43611.7-43620.4" + attribute \src "libresoc.v:43407.7-43416.4" cell \spr \spr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74418,7 +74214,7 @@ module \core connect \spr1__wen \spr_spr1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43621.9-43638.4" + attribute \src "libresoc.v:43417.9-43434.4" cell \state \state connect \cia__data_o \cia__data_o connect \cia__ren \cia__ren @@ -74438,77 +74234,77 @@ module \core connect \wen$5 \state_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43639.18-43643.4" + attribute \src "libresoc.v:43435.18-43439.4" cell \wrpick_CR_cr_a \wrpick_CR_cr_a connect \en_o \wrpick_CR_cr_a_en_o connect \i \wrpick_CR_cr_a_i connect \o \wrpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43644.21-43648.4" + attribute \src "libresoc.v:43440.21-43444.4" cell \wrpick_CR_full_cr \wrpick_CR_full_cr connect \en_o \wrpick_CR_full_cr_en_o connect \i \wrpick_CR_full_cr_i connect \o \wrpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43649.21-43653.4" + attribute \src "libresoc.v:43445.21-43449.4" cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 connect \en_o \wrpick_FAST_fast1_en_o connect \i \wrpick_FAST_fast1_i connect \o \wrpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43654.16-43658.4" + attribute \src "libresoc.v:43450.16-43454.4" cell \wrpick_INT_o \wrpick_INT_o connect \en_o \wrpick_INT_o_en_o connect \i \wrpick_INT_o_i connect \o \wrpick_INT_o_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43659.19-43663.4" + attribute \src "libresoc.v:43455.19-43459.4" cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 connect \en_o \wrpick_SPR_spr1_en_o connect \i \wrpick_SPR_spr1_i connect \o \wrpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43664.20-43668.4" + attribute \src "libresoc.v:43460.20-43464.4" cell \wrpick_STATE_msr \wrpick_STATE_msr connect \en_o \wrpick_STATE_msr_en_o connect \i \wrpick_STATE_msr_i connect \o \wrpick_STATE_msr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43669.20-43673.4" + attribute \src "libresoc.v:43465.20-43469.4" cell \wrpick_STATE_nia \wrpick_STATE_nia connect \en_o \wrpick_STATE_nia_en_o connect \i \wrpick_STATE_nia_i connect \o \wrpick_STATE_nia_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43674.21-43678.4" + attribute \src "libresoc.v:43470.21-43474.4" cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca connect \en_o \wrpick_XER_xer_ca_en_o connect \i \wrpick_XER_xer_ca_i connect \o \wrpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43679.21-43683.4" + attribute \src "libresoc.v:43475.21-43479.4" cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov connect \en_o \wrpick_XER_xer_ov_en_o connect \i \wrpick_XER_xer_ov_i connect \o \wrpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43684.21-43688.4" + attribute \src "libresoc.v:43480.21-43484.4" cell \wrpick_XER_xer_so \wrpick_XER_xer_so connect \en_o \wrpick_XER_xer_so_en_o connect \i \wrpick_XER_xer_so_i connect \o \wrpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43689.7-43706.4" + attribute \src "libresoc.v:43485.7-43502.4" cell \xer \xer connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74535,1209 +74331,1209 @@ module \core update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:38307.7-38307.30" - process $proc$libresoc.v:38307$2901 + attribute \src "libresoc.v:38103.7-38103.30" + process $proc$libresoc.v:38103$2901 assign { } { } assign $1\core_terminate_o[0:0] 1'0 sync always sync init update \core_terminate_o $1\core_terminate_o[0:0] end - attribute \src "libresoc.v:38320.13-38320.27" - process $proc$libresoc.v:38320$2902 + attribute \src "libresoc.v:38116.13-38116.27" + process $proc$libresoc.v:38116$2902 assign { } { } assign $1\counter[1:0] 2'00 sync always sync init update \counter $1\counter[1:0] end - attribute \src "libresoc.v:39487.7-39487.34" - process $proc$libresoc.v:39487$2903 + attribute \src "libresoc.v:39283.7-39283.34" + process $proc$libresoc.v:39283$2903 assign { } { } assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 sync always sync init update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:39491.7-39491.30" - process $proc$libresoc.v:39491$2904 + attribute \src "libresoc.v:39287.7-39287.30" + process $proc$libresoc.v:39287$2904 assign { } { } assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:39495.7-39495.30" - process $proc$libresoc.v:39495$2905 + attribute \src "libresoc.v:39291.7-39291.30" + process $proc$libresoc.v:39291$2905 assign { } { } assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:39499.7-39499.30" - process $proc$libresoc.v:39499$2906 + attribute \src "libresoc.v:39295.7-39295.30" + process $proc$libresoc.v:39295$2906 assign { } { } assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:39503.7-39503.33" - process $proc$libresoc.v:39503$2907 + attribute \src "libresoc.v:39299.7-39299.33" + process $proc$libresoc.v:39299$2907 assign { } { } assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:39507.7-39507.37" - process $proc$libresoc.v:39507$2908 + attribute \src "libresoc.v:39303.7-39303.37" + process $proc$libresoc.v:39303$2908 assign { } { } assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:39511.7-39511.37" - process $proc$libresoc.v:39511$2909 + attribute \src "libresoc.v:39307.7-39307.37" + process $proc$libresoc.v:39307$2909 assign { } { } assign $1\dp_FAST_fast1_branch0_3[0:0] 1'0 sync always sync init update \dp_FAST_fast1_branch0_3 $1\dp_FAST_fast1_branch0_3[0:0] end - attribute \src "libresoc.v:39515.7-39515.34" - process $proc$libresoc.v:39515$2910 + attribute \src "libresoc.v:39311.7-39311.34" + process $proc$libresoc.v:39311$2910 assign { } { } assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 sync always sync init update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:39519.7-39519.35" - process $proc$libresoc.v:39519$2911 + attribute \src "libresoc.v:39315.7-39315.35" + process $proc$libresoc.v:39315$2911 assign { } { } assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:39523.7-39523.35" - process $proc$libresoc.v:39523$2912 + attribute \src "libresoc.v:39319.7-39319.35" + process $proc$libresoc.v:39319$2912 assign { } { } assign $1\dp_FAST_fast1_trap0_4[0:0] 1'0 sync always sync init update \dp_FAST_fast1_trap0_4 $1\dp_FAST_fast1_trap0_4[0:0] end - attribute \src "libresoc.v:39527.7-39527.32" - process $proc$libresoc.v:39527$2913 + attribute \src "libresoc.v:39323.7-39323.32" + process $proc$libresoc.v:39323$2913 assign { } { } assign $1\dp_INT_rabc_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_rabc_alu0_0 $1\dp_INT_rabc_alu0_0[0:0] end - attribute \src "libresoc.v:39531.7-39531.33" - process $proc$libresoc.v:39531$2914 + attribute \src "libresoc.v:39327.7-39327.33" + process $proc$libresoc.v:39327$2914 assign { } { } assign $1\dp_INT_rabc_alu0_10[0:0] 1'0 sync always sync init update \dp_INT_rabc_alu0_10 $1\dp_INT_rabc_alu0_10[0:0] end - attribute \src "libresoc.v:39535.7-39535.31" - process $proc$libresoc.v:39535$2915 + attribute \src "libresoc.v:39331.7-39331.31" + process $proc$libresoc.v:39331$2915 assign { } { } assign $1\dp_INT_rabc_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_rabc_cr0_1 $1\dp_INT_rabc_cr0_1[0:0] end - attribute \src "libresoc.v:39539.7-39539.32" - process $proc$libresoc.v:39539$2916 + attribute \src "libresoc.v:39335.7-39335.32" + process $proc$libresoc.v:39335$2916 assign { } { } assign $1\dp_INT_rabc_cr0_11[0:0] 1'0 sync always sync init update \dp_INT_rabc_cr0_11 $1\dp_INT_rabc_cr0_11[0:0] end - attribute \src "libresoc.v:39543.7-39543.33" - process $proc$libresoc.v:39543$2917 + attribute \src "libresoc.v:39339.7-39339.33" + process $proc$libresoc.v:39339$2917 assign { } { } assign $1\dp_INT_rabc_div0_15[0:0] 1'0 sync always sync init update \dp_INT_rabc_div0_15 $1\dp_INT_rabc_div0_15[0:0] end - attribute \src "libresoc.v:39547.7-39547.32" - process $proc$libresoc.v:39547$2918 + attribute \src "libresoc.v:39343.7-39343.32" + process $proc$libresoc.v:39343$2918 assign { } { } assign $1\dp_INT_rabc_div0_4[0:0] 1'0 sync always sync init update \dp_INT_rabc_div0_4 $1\dp_INT_rabc_div0_4[0:0] end - attribute \src "libresoc.v:39551.7-39551.34" - process $proc$libresoc.v:39551$2919 + attribute \src "libresoc.v:39347.7-39347.34" + process $proc$libresoc.v:39347$2919 assign { } { } assign $1\dp_INT_rabc_ldst0_18[0:0] 1'0 sync always sync init update \dp_INT_rabc_ldst0_18 $1\dp_INT_rabc_ldst0_18[0:0] end - attribute \src "libresoc.v:39555.7-39555.33" - process $proc$libresoc.v:39555$2920 + attribute \src "libresoc.v:39351.7-39351.33" + process $proc$libresoc.v:39351$2920 assign { } { } assign $1\dp_INT_rabc_ldst0_7[0:0] 1'0 sync always sync init update \dp_INT_rabc_ldst0_7 $1\dp_INT_rabc_ldst0_7[0:0] end - attribute \src "libresoc.v:39559.7-39559.33" - process $proc$libresoc.v:39559$2921 + attribute \src "libresoc.v:39355.7-39355.33" + process $proc$libresoc.v:39355$2921 assign { } { } assign $1\dp_INT_rabc_ldst0_9[0:0] 1'0 sync always sync init update \dp_INT_rabc_ldst0_9 $1\dp_INT_rabc_ldst0_9[0:0] end - attribute \src "libresoc.v:39563.7-39563.37" - process $proc$libresoc.v:39563$2922 + attribute \src "libresoc.v:39359.7-39359.37" + process $proc$libresoc.v:39359$2922 assign { } { } assign $1\dp_INT_rabc_logical0_13[0:0] 1'0 sync always sync init update \dp_INT_rabc_logical0_13 $1\dp_INT_rabc_logical0_13[0:0] end - attribute \src "libresoc.v:39567.7-39567.36" - process $proc$libresoc.v:39567$2923 + attribute \src "libresoc.v:39363.7-39363.36" + process $proc$libresoc.v:39363$2923 assign { } { } assign $1\dp_INT_rabc_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_rabc_logical0_3 $1\dp_INT_rabc_logical0_3[0:0] end - attribute \src "libresoc.v:39571.7-39571.33" - process $proc$libresoc.v:39571$2924 + attribute \src "libresoc.v:39367.7-39367.33" + process $proc$libresoc.v:39367$2924 assign { } { } assign $1\dp_INT_rabc_mul0_16[0:0] 1'0 sync always sync init update \dp_INT_rabc_mul0_16 $1\dp_INT_rabc_mul0_16[0:0] end - attribute \src "libresoc.v:39575.7-39575.32" - process $proc$libresoc.v:39575$2925 + attribute \src "libresoc.v:39371.7-39371.32" + process $proc$libresoc.v:39371$2925 assign { } { } assign $1\dp_INT_rabc_mul0_5[0:0] 1'0 sync always sync init update \dp_INT_rabc_mul0_5 $1\dp_INT_rabc_mul0_5[0:0] end - attribute \src "libresoc.v:39579.7-39579.38" - process $proc$libresoc.v:39579$2926 + attribute \src "libresoc.v:39375.7-39375.38" + process $proc$libresoc.v:39375$2926 assign { } { } assign $1\dp_INT_rabc_shiftrot0_17[0:0] 1'0 sync always sync init update \dp_INT_rabc_shiftrot0_17 $1\dp_INT_rabc_shiftrot0_17[0:0] end - attribute \src "libresoc.v:39583.7-39583.37" - process $proc$libresoc.v:39583$2927 + attribute \src "libresoc.v:39379.7-39379.37" + process $proc$libresoc.v:39379$2927 assign { } { } assign $1\dp_INT_rabc_shiftrot0_6[0:0] 1'0 sync always sync init update \dp_INT_rabc_shiftrot0_6 $1\dp_INT_rabc_shiftrot0_6[0:0] end - attribute \src "libresoc.v:39587.7-39587.37" - process $proc$libresoc.v:39587$2928 + attribute \src "libresoc.v:39383.7-39383.37" + process $proc$libresoc.v:39383$2928 assign { } { } assign $1\dp_INT_rabc_shiftrot0_8[0:0] 1'0 sync always sync init update \dp_INT_rabc_shiftrot0_8 $1\dp_INT_rabc_shiftrot0_8[0:0] end - attribute \src "libresoc.v:39591.7-39591.33" - process $proc$libresoc.v:39591$2929 + attribute \src "libresoc.v:39387.7-39387.33" + process $proc$libresoc.v:39387$2929 assign { } { } assign $1\dp_INT_rabc_spr0_14[0:0] 1'0 sync always sync init update \dp_INT_rabc_spr0_14 $1\dp_INT_rabc_spr0_14[0:0] end - attribute \src "libresoc.v:39595.7-39595.34" - process $proc$libresoc.v:39595$2930 + attribute \src "libresoc.v:39391.7-39391.34" + process $proc$libresoc.v:39391$2930 assign { } { } assign $1\dp_INT_rabc_trap0_12[0:0] 1'0 sync always sync init update \dp_INT_rabc_trap0_12 $1\dp_INT_rabc_trap0_12[0:0] end - attribute \src "libresoc.v:39599.7-39599.33" - process $proc$libresoc.v:39599$2931 + attribute \src "libresoc.v:39395.7-39395.33" + process $proc$libresoc.v:39395$2931 assign { } { } assign $1\dp_INT_rabc_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_rabc_trap0_2 $1\dp_INT_rabc_trap0_2[0:0] end - attribute \src "libresoc.v:39603.7-39603.32" - process $proc$libresoc.v:39603$2932 + attribute \src "libresoc.v:39399.7-39399.32" + process $proc$libresoc.v:39399$2932 assign { } { } assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 sync always sync init update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:39607.7-39607.34" - process $proc$libresoc.v:39607$2933 + attribute \src "libresoc.v:39403.7-39403.34" + process $proc$libresoc.v:39403$2933 assign { } { } assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:39611.7-39611.39" - process $proc$libresoc.v:39611$2934 + attribute \src "libresoc.v:39407.7-39407.39" + process $proc$libresoc.v:39407$2934 assign { } { } assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:39615.7-39615.34" - process $proc$libresoc.v:39615$2935 + attribute \src "libresoc.v:39411.7-39411.34" + process $proc$libresoc.v:39411$2935 assign { } { } assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:39619.7-39619.34" - process $proc$libresoc.v:39619$2936 + attribute \src "libresoc.v:39415.7-39415.34" + process $proc$libresoc.v:39415$2936 assign { } { } assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:39623.7-39623.34" - process $proc$libresoc.v:39623$2937 + attribute \src "libresoc.v:39419.7-39419.34" + process $proc$libresoc.v:39419$2937 assign { } { } assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:39627.7-39627.34" - process $proc$libresoc.v:39627$2938 + attribute \src "libresoc.v:39423.7-39423.34" + process $proc$libresoc.v:39423$2938 assign { } { } assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 sync always sync init update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:39631.7-39631.38" - process $proc$libresoc.v:39631$2939 + attribute \src "libresoc.v:39427.7-39427.38" + process $proc$libresoc.v:39427$2939 assign { } { } assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:39635.7-39635.34" - process $proc$libresoc.v:39635$2940 + attribute \src "libresoc.v:39431.7-39431.34" + process $proc$libresoc.v:39431$2940 assign { } { } assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 sync always sync init update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:39639.7-39639.39" - process $proc$libresoc.v:39639$2941 + attribute \src "libresoc.v:39435.7-39435.39" + process $proc$libresoc.v:39435$2941 assign { } { } assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 sync always sync init update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:39643.7-39643.34" - process $proc$libresoc.v:39643$2942 + attribute \src "libresoc.v:39439.7-39439.34" + process $proc$libresoc.v:39439$2942 assign { } { } assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:41732.7-41732.25" - process $proc$libresoc.v:41732$2943 + attribute \src "libresoc.v:41528.7-41528.25" + process $proc$libresoc.v:41528$2943 assign { } { } assign $1\wr_pick_dly[0:0] 1'0 sync always sync init update \wr_pick_dly $1\wr_pick_dly[0:0] end - attribute \src "libresoc.v:41734.7-41734.32" - process $proc$libresoc.v:41734$2944 + attribute \src "libresoc.v:41530.7-41530.32" + process $proc$libresoc.v:41530$2944 assign { } { } assign $0\wr_pick_dly$1008[0:0]$2945 1'0 sync always sync init update \wr_pick_dly$1008 $0\wr_pick_dly$1008[0:0]$2945 end - attribute \src "libresoc.v:41738.7-41738.32" - process $proc$libresoc.v:41738$2946 + attribute \src "libresoc.v:41534.7-41534.32" + process $proc$libresoc.v:41534$2946 assign { } { } assign $0\wr_pick_dly$1029[0:0]$2947 1'0 sync always sync init update \wr_pick_dly$1029 $0\wr_pick_dly$1029[0:0]$2947 end - attribute \src "libresoc.v:41742.7-41742.32" - process $proc$libresoc.v:41742$2948 + attribute \src "libresoc.v:41538.7-41538.32" + process $proc$libresoc.v:41538$2948 assign { } { } assign $0\wr_pick_dly$1047[0:0]$2949 1'0 sync always sync init update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2949 end - attribute \src "libresoc.v:41746.7-41746.32" - process $proc$libresoc.v:41746$2950 + attribute \src "libresoc.v:41542.7-41542.32" + process $proc$libresoc.v:41542$2950 assign { } { } assign $0\wr_pick_dly$1069[0:0]$2951 1'0 sync always sync init update \wr_pick_dly$1069 $0\wr_pick_dly$1069[0:0]$2951 end - attribute \src "libresoc.v:41750.7-41750.32" - process $proc$libresoc.v:41750$2952 + attribute \src "libresoc.v:41546.7-41546.32" + process $proc$libresoc.v:41546$2952 assign { } { } assign $0\wr_pick_dly$1089[0:0]$2953 1'0 sync always sync init update \wr_pick_dly$1089 $0\wr_pick_dly$1089[0:0]$2953 end - attribute \src "libresoc.v:41754.7-41754.32" - process $proc$libresoc.v:41754$2954 + attribute \src "libresoc.v:41550.7-41550.32" + process $proc$libresoc.v:41550$2954 assign { } { } assign $0\wr_pick_dly$1109[0:0]$2955 1'0 sync always sync init update \wr_pick_dly$1109 $0\wr_pick_dly$1109[0:0]$2955 end - attribute \src "libresoc.v:41758.7-41758.32" - process $proc$libresoc.v:41758$2956 + attribute \src "libresoc.v:41554.7-41554.32" + process $proc$libresoc.v:41554$2956 assign { } { } assign $0\wr_pick_dly$1128[0:0]$2957 1'0 sync always sync init update \wr_pick_dly$1128 $0\wr_pick_dly$1128[0:0]$2957 end - attribute \src "libresoc.v:41762.7-41762.32" - process $proc$libresoc.v:41762$2958 + attribute \src "libresoc.v:41558.7-41558.32" + process $proc$libresoc.v:41558$2958 assign { } { } assign $0\wr_pick_dly$1146[0:0]$2959 1'0 sync always sync init update \wr_pick_dly$1146 $0\wr_pick_dly$1146[0:0]$2959 end - attribute \src "libresoc.v:41766.7-41766.32" - process $proc$libresoc.v:41766$2960 + attribute \src "libresoc.v:41562.7-41562.32" + process $proc$libresoc.v:41562$2960 assign { } { } assign $0\wr_pick_dly$1220[0:0]$2961 1'0 sync always sync init update \wr_pick_dly$1220 $0\wr_pick_dly$1220[0:0]$2961 end - attribute \src "libresoc.v:41770.7-41770.32" - process $proc$libresoc.v:41770$2962 + attribute \src "libresoc.v:41566.7-41566.32" + process $proc$libresoc.v:41566$2962 assign { } { } assign $0\wr_pick_dly$1248[0:0]$2963 1'0 sync always sync init update \wr_pick_dly$1248 $0\wr_pick_dly$1248[0:0]$2963 end - attribute \src "libresoc.v:41774.7-41774.32" - process $proc$libresoc.v:41774$2964 + attribute \src "libresoc.v:41570.7-41570.32" + process $proc$libresoc.v:41570$2964 assign { } { } assign $0\wr_pick_dly$1268[0:0]$2965 1'0 sync always sync init update \wr_pick_dly$1268 $0\wr_pick_dly$1268[0:0]$2965 end - attribute \src "libresoc.v:41778.7-41778.32" - process $proc$libresoc.v:41778$2966 + attribute \src "libresoc.v:41574.7-41574.32" + process $proc$libresoc.v:41574$2966 assign { } { } assign $0\wr_pick_dly$1288[0:0]$2967 1'0 sync always sync init update \wr_pick_dly$1288 $0\wr_pick_dly$1288[0:0]$2967 end - attribute \src "libresoc.v:41782.7-41782.32" - process $proc$libresoc.v:41782$2968 + attribute \src "libresoc.v:41578.7-41578.32" + process $proc$libresoc.v:41578$2968 assign { } { } assign $0\wr_pick_dly$1308[0:0]$2969 1'0 sync always sync init update \wr_pick_dly$1308 $0\wr_pick_dly$1308[0:0]$2969 end - attribute \src "libresoc.v:41786.7-41786.32" - process $proc$libresoc.v:41786$2970 + attribute \src "libresoc.v:41582.7-41582.32" + process $proc$libresoc.v:41582$2970 assign { } { } assign $0\wr_pick_dly$1328[0:0]$2971 1'0 sync always sync init update \wr_pick_dly$1328 $0\wr_pick_dly$1328[0:0]$2971 end - attribute \src "libresoc.v:41790.7-41790.32" - process $proc$libresoc.v:41790$2972 + attribute \src "libresoc.v:41586.7-41586.32" + process $proc$libresoc.v:41586$2972 assign { } { } assign $0\wr_pick_dly$1348[0:0]$2973 1'0 sync always sync init update \wr_pick_dly$1348 $0\wr_pick_dly$1348[0:0]$2973 end - attribute \src "libresoc.v:41794.7-41794.32" - process $proc$libresoc.v:41794$2974 + attribute \src "libresoc.v:41590.7-41590.32" + process $proc$libresoc.v:41590$2974 assign { } { } assign $0\wr_pick_dly$1395[0:0]$2975 1'0 sync always sync init update \wr_pick_dly$1395 $0\wr_pick_dly$1395[0:0]$2975 end - attribute \src "libresoc.v:41798.7-41798.32" - process $proc$libresoc.v:41798$2976 + attribute \src "libresoc.v:41594.7-41594.32" + process $proc$libresoc.v:41594$2976 assign { } { } assign $0\wr_pick_dly$1411[0:0]$2977 1'0 sync always sync init update \wr_pick_dly$1411 $0\wr_pick_dly$1411[0:0]$2977 end - attribute \src "libresoc.v:41802.7-41802.32" - process $proc$libresoc.v:41802$2978 + attribute \src "libresoc.v:41598.7-41598.32" + process $proc$libresoc.v:41598$2978 assign { } { } assign $0\wr_pick_dly$1427[0:0]$2979 1'0 sync always sync init update \wr_pick_dly$1427 $0\wr_pick_dly$1427[0:0]$2979 end - attribute \src "libresoc.v:41806.7-41806.32" - process $proc$libresoc.v:41806$2980 + attribute \src "libresoc.v:41602.7-41602.32" + process $proc$libresoc.v:41602$2980 assign { } { } assign $0\wr_pick_dly$1461[0:0]$2981 1'0 sync always sync init update \wr_pick_dly$1461 $0\wr_pick_dly$1461[0:0]$2981 end - attribute \src "libresoc.v:41810.7-41810.32" - process $proc$libresoc.v:41810$2982 + attribute \src "libresoc.v:41606.7-41606.32" + process $proc$libresoc.v:41606$2982 assign { } { } assign $0\wr_pick_dly$1477[0:0]$2983 1'0 sync always sync init update \wr_pick_dly$1477 $0\wr_pick_dly$1477[0:0]$2983 end - attribute \src "libresoc.v:41814.7-41814.32" - process $proc$libresoc.v:41814$2984 + attribute \src "libresoc.v:41610.7-41610.32" + process $proc$libresoc.v:41610$2984 assign { } { } assign $0\wr_pick_dly$1493[0:0]$2985 1'0 sync always sync init update \wr_pick_dly$1493 $0\wr_pick_dly$1493[0:0]$2985 end - attribute \src "libresoc.v:41818.7-41818.32" - process $proc$libresoc.v:41818$2986 + attribute \src "libresoc.v:41614.7-41614.32" + process $proc$libresoc.v:41614$2986 assign { } { } assign $0\wr_pick_dly$1509[0:0]$2987 1'0 sync always sync init update \wr_pick_dly$1509 $0\wr_pick_dly$1509[0:0]$2987 end - attribute \src "libresoc.v:41822.7-41822.32" - process $proc$libresoc.v:41822$2988 + attribute \src "libresoc.v:41618.7-41618.32" + process $proc$libresoc.v:41618$2988 assign { } { } assign $0\wr_pick_dly$1545[0:0]$2989 1'0 sync always sync init update \wr_pick_dly$1545 $0\wr_pick_dly$1545[0:0]$2989 end - attribute \src "libresoc.v:41826.7-41826.32" - process $proc$libresoc.v:41826$2990 + attribute \src "libresoc.v:41622.7-41622.32" + process $proc$libresoc.v:41622$2990 assign { } { } assign $0\wr_pick_dly$1561[0:0]$2991 1'0 sync always sync init update \wr_pick_dly$1561 $0\wr_pick_dly$1561[0:0]$2991 end - attribute \src "libresoc.v:41830.7-41830.32" - process $proc$libresoc.v:41830$2992 + attribute \src "libresoc.v:41626.7-41626.32" + process $proc$libresoc.v:41626$2992 assign { } { } assign $0\wr_pick_dly$1577[0:0]$2993 1'0 sync always sync init update \wr_pick_dly$1577 $0\wr_pick_dly$1577[0:0]$2993 end - attribute \src "libresoc.v:41834.7-41834.32" - process $proc$libresoc.v:41834$2994 + attribute \src "libresoc.v:41630.7-41630.32" + process $proc$libresoc.v:41630$2994 assign { } { } assign $0\wr_pick_dly$1593[0:0]$2995 1'0 sync always sync init update \wr_pick_dly$1593 $0\wr_pick_dly$1593[0:0]$2995 end - attribute \src "libresoc.v:41838.7-41838.32" - process $proc$libresoc.v:41838$2996 + attribute \src "libresoc.v:41634.7-41634.32" + process $proc$libresoc.v:41634$2996 assign { } { } assign $0\wr_pick_dly$1635[0:0]$2997 1'0 sync always sync init update \wr_pick_dly$1635 $0\wr_pick_dly$1635[0:0]$2997 end - attribute \src "libresoc.v:41842.7-41842.32" - process $proc$libresoc.v:41842$2998 + attribute \src "libresoc.v:41638.7-41638.32" + process $proc$libresoc.v:41638$2998 assign { } { } assign $0\wr_pick_dly$1654[0:0]$2999 1'0 sync always sync init update \wr_pick_dly$1654 $0\wr_pick_dly$1654[0:0]$2999 end - attribute \src "libresoc.v:41846.7-41846.32" - process $proc$libresoc.v:41846$3000 + attribute \src "libresoc.v:41642.7-41642.32" + process $proc$libresoc.v:41642$3000 assign { } { } assign $0\wr_pick_dly$1670[0:0]$3001 1'0 sync always sync init update \wr_pick_dly$1670 $0\wr_pick_dly$1670[0:0]$3001 end - attribute \src "libresoc.v:41850.7-41850.32" - process $proc$libresoc.v:41850$3002 + attribute \src "libresoc.v:41646.7-41646.32" + process $proc$libresoc.v:41646$3002 assign { } { } assign $0\wr_pick_dly$1686[0:0]$3003 1'0 sync always sync init update \wr_pick_dly$1686 $0\wr_pick_dly$1686[0:0]$3003 end - attribute \src "libresoc.v:41854.7-41854.32" - process $proc$libresoc.v:41854$3004 + attribute \src "libresoc.v:41650.7-41650.32" + process $proc$libresoc.v:41650$3004 assign { } { } assign $0\wr_pick_dly$1702[0:0]$3005 1'0 sync always sync init update \wr_pick_dly$1702 $0\wr_pick_dly$1702[0:0]$3005 end - attribute \src "libresoc.v:41858.7-41858.32" - process $proc$libresoc.v:41858$3006 + attribute \src "libresoc.v:41654.7-41654.32" + process $proc$libresoc.v:41654$3006 assign { } { } assign $0\wr_pick_dly$1746[0:0]$3007 1'0 sync always sync init update \wr_pick_dly$1746 $0\wr_pick_dly$1746[0:0]$3007 end - attribute \src "libresoc.v:41862.7-41862.32" - process $proc$libresoc.v:41862$3008 + attribute \src "libresoc.v:41658.7-41658.32" + process $proc$libresoc.v:41658$3008 assign { } { } assign $0\wr_pick_dly$1762[0:0]$3009 1'0 sync always sync init update \wr_pick_dly$1762 $0\wr_pick_dly$1762[0:0]$3009 end - attribute \src "libresoc.v:41866.7-41866.32" - process $proc$libresoc.v:41866$3010 + attribute \src "libresoc.v:41662.7-41662.32" + process $proc$libresoc.v:41662$3010 assign { } { } assign $0\wr_pick_dly$1786[0:0]$3011 1'0 sync always sync init update \wr_pick_dly$1786 $0\wr_pick_dly$1786[0:0]$3011 end - attribute \src "libresoc.v:41870.7-41870.32" - process $proc$libresoc.v:41870$3012 + attribute \src "libresoc.v:41666.7-41666.32" + process $proc$libresoc.v:41666$3012 assign { } { } assign $0\wr_pick_dly$1806[0:0]$3013 1'0 sync always sync init update \wr_pick_dly$1806 $0\wr_pick_dly$1806[0:0]$3013 end - attribute \src "libresoc.v:41874.7-41874.31" - process $proc$libresoc.v:41874$3014 + attribute \src "libresoc.v:41670.7-41670.31" + process $proc$libresoc.v:41670$3014 assign { } { } assign $0\wr_pick_dly$989[0:0]$3015 1'0 sync always sync init update \wr_pick_dly$989 $0\wr_pick_dly$989[0:0]$3015 end - attribute \src "libresoc.v:42836.3-42837.51" - process $proc$libresoc.v:42836$2238 + attribute \src "libresoc.v:42632.3-42633.51" + process $proc$libresoc.v:42632$2238 assign { } { } assign $0\wr_pick_dly$1806[0:0]$2239 \wr_pick_dly$1806$next sync posedge \coresync_clk update \wr_pick_dly$1806 $0\wr_pick_dly$1806[0:0]$2239 end - attribute \src "libresoc.v:42838.3-42839.51" - process $proc$libresoc.v:42838$2240 + attribute \src "libresoc.v:42634.3-42635.51" + process $proc$libresoc.v:42634$2240 assign { } { } assign $0\wr_pick_dly$1786[0:0]$2241 \wr_pick_dly$1786$next sync posedge \coresync_clk update \wr_pick_dly$1786 $0\wr_pick_dly$1786[0:0]$2241 end - attribute \src "libresoc.v:42840.3-42841.51" - process $proc$libresoc.v:42840$2242 + attribute \src "libresoc.v:42636.3-42637.51" + process $proc$libresoc.v:42636$2242 assign { } { } assign $0\wr_pick_dly$1762[0:0]$2243 \wr_pick_dly$1762$next sync posedge \coresync_clk update \wr_pick_dly$1762 $0\wr_pick_dly$1762[0:0]$2243 end - attribute \src "libresoc.v:42842.3-42843.51" - process $proc$libresoc.v:42842$2244 + attribute \src "libresoc.v:42638.3-42639.51" + process $proc$libresoc.v:42638$2244 assign { } { } assign $0\wr_pick_dly$1746[0:0]$2245 \wr_pick_dly$1746$next sync posedge \coresync_clk update \wr_pick_dly$1746 $0\wr_pick_dly$1746[0:0]$2245 end - attribute \src "libresoc.v:42844.3-42845.51" - process $proc$libresoc.v:42844$2246 + attribute \src "libresoc.v:42640.3-42641.51" + process $proc$libresoc.v:42640$2246 assign { } { } assign $0\wr_pick_dly$1702[0:0]$2247 \wr_pick_dly$1702$next sync posedge \coresync_clk update \wr_pick_dly$1702 $0\wr_pick_dly$1702[0:0]$2247 end - attribute \src "libresoc.v:42846.3-42847.51" - process $proc$libresoc.v:42846$2248 + attribute \src "libresoc.v:42642.3-42643.51" + process $proc$libresoc.v:42642$2248 assign { } { } assign $0\wr_pick_dly$1686[0:0]$2249 \wr_pick_dly$1686$next sync posedge \coresync_clk update \wr_pick_dly$1686 $0\wr_pick_dly$1686[0:0]$2249 end - attribute \src "libresoc.v:42848.3-42849.51" - process $proc$libresoc.v:42848$2250 + attribute \src "libresoc.v:42644.3-42645.51" + process $proc$libresoc.v:42644$2250 assign { } { } assign $0\wr_pick_dly$1670[0:0]$2251 \wr_pick_dly$1670$next sync posedge \coresync_clk update \wr_pick_dly$1670 $0\wr_pick_dly$1670[0:0]$2251 end - attribute \src "libresoc.v:42850.3-42851.51" - process $proc$libresoc.v:42850$2252 + attribute \src "libresoc.v:42646.3-42647.51" + process $proc$libresoc.v:42646$2252 assign { } { } assign $0\wr_pick_dly$1654[0:0]$2253 \wr_pick_dly$1654$next sync posedge \coresync_clk update \wr_pick_dly$1654 $0\wr_pick_dly$1654[0:0]$2253 end - attribute \src "libresoc.v:42852.3-42853.51" - process $proc$libresoc.v:42852$2254 + attribute \src "libresoc.v:42648.3-42649.51" + process $proc$libresoc.v:42648$2254 assign { } { } assign $0\wr_pick_dly$1635[0:0]$2255 \wr_pick_dly$1635$next sync posedge \coresync_clk update \wr_pick_dly$1635 $0\wr_pick_dly$1635[0:0]$2255 end - attribute \src "libresoc.v:42854.3-42855.51" - process $proc$libresoc.v:42854$2256 + attribute \src "libresoc.v:42650.3-42651.51" + process $proc$libresoc.v:42650$2256 assign { } { } assign $0\wr_pick_dly$1593[0:0]$2257 \wr_pick_dly$1593$next sync posedge \coresync_clk update \wr_pick_dly$1593 $0\wr_pick_dly$1593[0:0]$2257 end - attribute \src "libresoc.v:42856.3-42857.51" - process $proc$libresoc.v:42856$2258 + attribute \src "libresoc.v:42652.3-42653.51" + process $proc$libresoc.v:42652$2258 assign { } { } assign $0\wr_pick_dly$1577[0:0]$2259 \wr_pick_dly$1577$next sync posedge \coresync_clk update \wr_pick_dly$1577 $0\wr_pick_dly$1577[0:0]$2259 end - attribute \src "libresoc.v:42858.3-42859.51" - process $proc$libresoc.v:42858$2260 + attribute \src "libresoc.v:42654.3-42655.51" + process $proc$libresoc.v:42654$2260 assign { } { } assign $0\wr_pick_dly$1561[0:0]$2261 \wr_pick_dly$1561$next sync posedge \coresync_clk update \wr_pick_dly$1561 $0\wr_pick_dly$1561[0:0]$2261 end - attribute \src "libresoc.v:42860.3-42861.51" - process $proc$libresoc.v:42860$2262 + attribute \src "libresoc.v:42656.3-42657.51" + process $proc$libresoc.v:42656$2262 assign { } { } assign $0\wr_pick_dly$1545[0:0]$2263 \wr_pick_dly$1545$next sync posedge \coresync_clk update \wr_pick_dly$1545 $0\wr_pick_dly$1545[0:0]$2263 end - attribute \src "libresoc.v:42862.3-42863.51" - process $proc$libresoc.v:42862$2264 + attribute \src "libresoc.v:42658.3-42659.51" + process $proc$libresoc.v:42658$2264 assign { } { } assign $0\wr_pick_dly$1509[0:0]$2265 \wr_pick_dly$1509$next sync posedge \coresync_clk update \wr_pick_dly$1509 $0\wr_pick_dly$1509[0:0]$2265 end - attribute \src "libresoc.v:42864.3-42865.51" - process $proc$libresoc.v:42864$2266 + attribute \src "libresoc.v:42660.3-42661.51" + process $proc$libresoc.v:42660$2266 assign { } { } assign $0\wr_pick_dly$1493[0:0]$2267 \wr_pick_dly$1493$next sync posedge \coresync_clk update \wr_pick_dly$1493 $0\wr_pick_dly$1493[0:0]$2267 end - attribute \src "libresoc.v:42866.3-42867.51" - process $proc$libresoc.v:42866$2268 + attribute \src "libresoc.v:42662.3-42663.51" + process $proc$libresoc.v:42662$2268 assign { } { } assign $0\wr_pick_dly$1477[0:0]$2269 \wr_pick_dly$1477$next sync posedge \coresync_clk update \wr_pick_dly$1477 $0\wr_pick_dly$1477[0:0]$2269 end - attribute \src "libresoc.v:42868.3-42869.51" - process $proc$libresoc.v:42868$2270 + attribute \src "libresoc.v:42664.3-42665.51" + process $proc$libresoc.v:42664$2270 assign { } { } assign $0\wr_pick_dly$1461[0:0]$2271 \wr_pick_dly$1461$next sync posedge \coresync_clk update \wr_pick_dly$1461 $0\wr_pick_dly$1461[0:0]$2271 end - attribute \src "libresoc.v:42870.3-42871.51" - process $proc$libresoc.v:42870$2272 + attribute \src "libresoc.v:42666.3-42667.51" + process $proc$libresoc.v:42666$2272 assign { } { } assign $0\wr_pick_dly$1427[0:0]$2273 \wr_pick_dly$1427$next sync posedge \coresync_clk update \wr_pick_dly$1427 $0\wr_pick_dly$1427[0:0]$2273 end - attribute \src "libresoc.v:42872.3-42873.51" - process $proc$libresoc.v:42872$2274 + attribute \src "libresoc.v:42668.3-42669.51" + process $proc$libresoc.v:42668$2274 assign { } { } assign $0\wr_pick_dly$1411[0:0]$2275 \wr_pick_dly$1411$next sync posedge \coresync_clk update \wr_pick_dly$1411 $0\wr_pick_dly$1411[0:0]$2275 end - attribute \src "libresoc.v:42874.3-42875.51" - process $proc$libresoc.v:42874$2276 + attribute \src "libresoc.v:42670.3-42671.51" + process $proc$libresoc.v:42670$2276 assign { } { } assign $0\wr_pick_dly$1395[0:0]$2277 \wr_pick_dly$1395$next sync posedge \coresync_clk update \wr_pick_dly$1395 $0\wr_pick_dly$1395[0:0]$2277 end - attribute \src "libresoc.v:42876.3-42877.51" - process $proc$libresoc.v:42876$2278 + attribute \src "libresoc.v:42672.3-42673.51" + process $proc$libresoc.v:42672$2278 assign { } { } assign $0\wr_pick_dly$1348[0:0]$2279 \wr_pick_dly$1348$next sync posedge \coresync_clk update \wr_pick_dly$1348 $0\wr_pick_dly$1348[0:0]$2279 end - attribute \src "libresoc.v:42878.3-42879.51" - process $proc$libresoc.v:42878$2280 + attribute \src "libresoc.v:42674.3-42675.51" + process $proc$libresoc.v:42674$2280 assign { } { } assign $0\wr_pick_dly$1328[0:0]$2281 \wr_pick_dly$1328$next sync posedge \coresync_clk update \wr_pick_dly$1328 $0\wr_pick_dly$1328[0:0]$2281 end - attribute \src "libresoc.v:42880.3-42881.51" - process $proc$libresoc.v:42880$2282 + attribute \src "libresoc.v:42676.3-42677.51" + process $proc$libresoc.v:42676$2282 assign { } { } assign $0\wr_pick_dly$1308[0:0]$2283 \wr_pick_dly$1308$next sync posedge \coresync_clk update \wr_pick_dly$1308 $0\wr_pick_dly$1308[0:0]$2283 end - attribute \src "libresoc.v:42882.3-42883.51" - process $proc$libresoc.v:42882$2284 + attribute \src "libresoc.v:42678.3-42679.51" + process $proc$libresoc.v:42678$2284 assign { } { } assign $0\wr_pick_dly$1288[0:0]$2285 \wr_pick_dly$1288$next sync posedge \coresync_clk update \wr_pick_dly$1288 $0\wr_pick_dly$1288[0:0]$2285 end - attribute \src "libresoc.v:42884.3-42885.51" - process $proc$libresoc.v:42884$2286 + attribute \src "libresoc.v:42680.3-42681.51" + process $proc$libresoc.v:42680$2286 assign { } { } assign $0\wr_pick_dly$1268[0:0]$2287 \wr_pick_dly$1268$next sync posedge \coresync_clk update \wr_pick_dly$1268 $0\wr_pick_dly$1268[0:0]$2287 end - attribute \src "libresoc.v:42886.3-42887.51" - process $proc$libresoc.v:42886$2288 + attribute \src "libresoc.v:42682.3-42683.51" + process $proc$libresoc.v:42682$2288 assign { } { } assign $0\wr_pick_dly$1248[0:0]$2289 \wr_pick_dly$1248$next sync posedge \coresync_clk update \wr_pick_dly$1248 $0\wr_pick_dly$1248[0:0]$2289 end - attribute \src "libresoc.v:42888.3-42889.51" - process $proc$libresoc.v:42888$2290 + attribute \src "libresoc.v:42684.3-42685.51" + process $proc$libresoc.v:42684$2290 assign { } { } assign $0\wr_pick_dly$1220[0:0]$2291 \wr_pick_dly$1220$next sync posedge \coresync_clk update \wr_pick_dly$1220 $0\wr_pick_dly$1220[0:0]$2291 end - attribute \src "libresoc.v:42890.3-42891.51" - process $proc$libresoc.v:42890$2292 + attribute \src "libresoc.v:42686.3-42687.51" + process $proc$libresoc.v:42686$2292 assign { } { } assign $0\wr_pick_dly$1146[0:0]$2293 \wr_pick_dly$1146$next sync posedge \coresync_clk update \wr_pick_dly$1146 $0\wr_pick_dly$1146[0:0]$2293 end - attribute \src "libresoc.v:42892.3-42893.51" - process $proc$libresoc.v:42892$2294 + attribute \src "libresoc.v:42688.3-42689.51" + process $proc$libresoc.v:42688$2294 assign { } { } assign $0\wr_pick_dly$1128[0:0]$2295 \wr_pick_dly$1128$next sync posedge \coresync_clk update \wr_pick_dly$1128 $0\wr_pick_dly$1128[0:0]$2295 end - attribute \src "libresoc.v:42894.3-42895.51" - process $proc$libresoc.v:42894$2296 + attribute \src "libresoc.v:42690.3-42691.51" + process $proc$libresoc.v:42690$2296 assign { } { } assign $0\wr_pick_dly$1109[0:0]$2297 \wr_pick_dly$1109$next sync posedge \coresync_clk update \wr_pick_dly$1109 $0\wr_pick_dly$1109[0:0]$2297 end - attribute \src "libresoc.v:42896.3-42897.51" - process $proc$libresoc.v:42896$2298 + attribute \src "libresoc.v:42692.3-42693.51" + process $proc$libresoc.v:42692$2298 assign { } { } assign $0\wr_pick_dly$1089[0:0]$2299 \wr_pick_dly$1089$next sync posedge \coresync_clk update \wr_pick_dly$1089 $0\wr_pick_dly$1089[0:0]$2299 end - attribute \src "libresoc.v:42898.3-42899.51" - process $proc$libresoc.v:42898$2300 + attribute \src "libresoc.v:42694.3-42695.51" + process $proc$libresoc.v:42694$2300 assign { } { } assign $0\wr_pick_dly$1069[0:0]$2301 \wr_pick_dly$1069$next sync posedge \coresync_clk update \wr_pick_dly$1069 $0\wr_pick_dly$1069[0:0]$2301 end - attribute \src "libresoc.v:42900.3-42901.51" - process $proc$libresoc.v:42900$2302 + attribute \src "libresoc.v:42696.3-42697.51" + process $proc$libresoc.v:42696$2302 assign { } { } assign $0\wr_pick_dly$1047[0:0]$2303 \wr_pick_dly$1047$next sync posedge \coresync_clk update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2303 end - attribute \src "libresoc.v:42902.3-42903.51" - process $proc$libresoc.v:42902$2304 + attribute \src "libresoc.v:42698.3-42699.51" + process $proc$libresoc.v:42698$2304 assign { } { } assign $0\wr_pick_dly$1029[0:0]$2305 \wr_pick_dly$1029$next sync posedge \coresync_clk update \wr_pick_dly$1029 $0\wr_pick_dly$1029[0:0]$2305 end - attribute \src "libresoc.v:42904.3-42905.51" - process $proc$libresoc.v:42904$2306 + attribute \src "libresoc.v:42700.3-42701.51" + process $proc$libresoc.v:42700$2306 assign { } { } assign $0\wr_pick_dly$1008[0:0]$2307 \wr_pick_dly$1008$next sync posedge \coresync_clk update \wr_pick_dly$1008 $0\wr_pick_dly$1008[0:0]$2307 end - attribute \src "libresoc.v:42906.3-42907.49" - process $proc$libresoc.v:42906$2308 + attribute \src "libresoc.v:42702.3-42703.49" + process $proc$libresoc.v:42702$2308 assign { } { } assign $0\wr_pick_dly$989[0:0]$2309 \wr_pick_dly$989$next sync posedge \coresync_clk update \wr_pick_dly$989 $0\wr_pick_dly$989[0:0]$2309 end - attribute \src "libresoc.v:42908.3-42909.39" - process $proc$libresoc.v:42908$2310 + attribute \src "libresoc.v:42704.3-42705.39" + process $proc$libresoc.v:42704$2310 assign { } { } assign $0\wr_pick_dly[0:0] \wr_pick_dly$next sync posedge \coresync_clk update \wr_pick_dly $0\wr_pick_dly[0:0] end - attribute \src "libresoc.v:42910.3-42911.53" - process $proc$libresoc.v:42910$2311 + attribute \src "libresoc.v:42706.3-42707.53" + process $proc$libresoc.v:42706$2311 assign { } { } assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next sync posedge \coresync_clk update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:42912.3-42913.59" - process $proc$libresoc.v:42912$2312 + attribute \src "libresoc.v:42708.3-42709.59" + process $proc$libresoc.v:42708$2312 assign { } { } assign $0\dp_FAST_fast1_trap0_4[0:0] \dp_FAST_fast1_trap0_4$next sync posedge \coresync_clk update \dp_FAST_fast1_trap0_4 $0\dp_FAST_fast1_trap0_4[0:0] end - attribute \src "libresoc.v:42914.3-42915.63" - process $proc$libresoc.v:42914$2313 + attribute \src "libresoc.v:42710.3-42711.63" + process $proc$libresoc.v:42710$2313 assign { } { } assign $0\dp_FAST_fast1_branch0_3[0:0] \dp_FAST_fast1_branch0_3$next sync posedge \coresync_clk update \dp_FAST_fast1_branch0_3 $0\dp_FAST_fast1_branch0_3[0:0] end - attribute \src "libresoc.v:42916.3-42917.57" - process $proc$libresoc.v:42916$2314 + attribute \src "libresoc.v:42712.3-42713.57" + process $proc$libresoc.v:42712$2314 assign { } { } assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next sync posedge \coresync_clk update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:42918.3-42919.59" - process $proc$libresoc.v:42918$2315 + attribute \src "libresoc.v:42714.3-42715.59" + process $proc$libresoc.v:42714$2315 assign { } { } assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:42920.3-42921.63" - process $proc$libresoc.v:42920$2316 + attribute \src "libresoc.v:42716.3-42717.63" + process $proc$libresoc.v:42716$2316 assign { } { } assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:42922.3-42923.49" - process $proc$libresoc.v:42922$2317 + attribute \src "libresoc.v:42718.3-42719.49" + process $proc$libresoc.v:42718$2317 assign { } { } assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:42924.3-42925.49" - process $proc$libresoc.v:42924$2318 + attribute \src "libresoc.v:42720.3-42721.49" + process $proc$libresoc.v:42720$2318 assign { } { } assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:42926.3-42927.57" - process $proc$libresoc.v:42926$2319 + attribute \src "libresoc.v:42722.3-42723.57" + process $proc$libresoc.v:42722$2319 assign { } { } assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next sync posedge \coresync_clk update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:42928.3-42929.49" - process $proc$libresoc.v:42928$2320 + attribute \src "libresoc.v:42724.3-42725.49" + process $proc$libresoc.v:42724$2320 assign { } { } assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:42930.3-42931.55" - process $proc$libresoc.v:42930$2321 + attribute \src "libresoc.v:42726.3-42727.55" + process $proc$libresoc.v:42726$2321 assign { } { } assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next sync posedge \coresync_clk update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:42932.3-42933.57" - process $proc$libresoc.v:42932$2322 + attribute \src "libresoc.v:42728.3-42729.57" + process $proc$libresoc.v:42728$2322 assign { } { } assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next sync posedge \coresync_clk update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:42934.3-42935.67" - process $proc$libresoc.v:42934$2323 + attribute \src "libresoc.v:42730.3-42731.67" + process $proc$libresoc.v:42730$2323 assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next sync posedge \coresync_clk update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:42936.3-42937.57" - process $proc$libresoc.v:42936$2324 + attribute \src "libresoc.v:42732.3-42733.57" + process $proc$libresoc.v:42732$2324 assign { } { } assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next sync posedge \coresync_clk update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:42938.3-42939.57" - process $proc$libresoc.v:42938$2325 + attribute \src "libresoc.v:42734.3-42735.57" + process $proc$libresoc.v:42734$2325 assign { } { } assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:42940.3-42941.67" - process $proc$libresoc.v:42940$2326 + attribute \src "libresoc.v:42736.3-42737.67" + process $proc$libresoc.v:42736$2326 assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next sync posedge \coresync_clk update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:42942.3-42943.57" - process $proc$libresoc.v:42942$2327 + attribute \src "libresoc.v:42738.3-42739.57" + process $proc$libresoc.v:42738$2327 assign { } { } assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next sync posedge \coresync_clk update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:42944.3-42945.57" - process $proc$libresoc.v:42944$2328 + attribute \src "libresoc.v:42740.3-42741.57" + process $proc$libresoc.v:42740$2328 assign { } { } assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next sync posedge \coresync_clk update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:42946.3-42947.57" - process $proc$libresoc.v:42946$2329 + attribute \src "libresoc.v:42742.3-42743.57" + process $proc$libresoc.v:42742$2329 assign { } { } assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next sync posedge \coresync_clk update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:42948.3-42949.65" - process $proc$libresoc.v:42948$2330 + attribute \src "libresoc.v:42744.3-42745.65" + process $proc$libresoc.v:42744$2330 assign { } { } assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next sync posedge \coresync_clk update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:42950.3-42951.57" - process $proc$libresoc.v:42950$2331 + attribute \src "libresoc.v:42746.3-42747.57" + process $proc$libresoc.v:42746$2331 assign { } { } assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:42952.3-42953.57" - process $proc$libresoc.v:42952$2332 + attribute \src "libresoc.v:42748.3-42749.57" + process $proc$libresoc.v:42748$2332 assign { } { } assign $0\dp_INT_rabc_ldst0_18[0:0] \dp_INT_rabc_ldst0_18$next sync posedge \coresync_clk update \dp_INT_rabc_ldst0_18 $0\dp_INT_rabc_ldst0_18[0:0] end - attribute \src "libresoc.v:42954.3-42955.65" - process $proc$libresoc.v:42954$2333 + attribute \src "libresoc.v:42750.3-42751.65" + process $proc$libresoc.v:42750$2333 assign { } { } assign $0\dp_INT_rabc_shiftrot0_17[0:0] \dp_INT_rabc_shiftrot0_17$next sync posedge \coresync_clk update \dp_INT_rabc_shiftrot0_17 $0\dp_INT_rabc_shiftrot0_17[0:0] end - attribute \src "libresoc.v:42956.3-42957.55" - process $proc$libresoc.v:42956$2334 + attribute \src "libresoc.v:42752.3-42753.55" + process $proc$libresoc.v:42752$2334 assign { } { } assign $0\dp_INT_rabc_mul0_16[0:0] \dp_INT_rabc_mul0_16$next sync posedge \coresync_clk update \dp_INT_rabc_mul0_16 $0\dp_INT_rabc_mul0_16[0:0] end - attribute \src "libresoc.v:42958.3-42959.55" - process $proc$libresoc.v:42958$2335 + attribute \src "libresoc.v:42754.3-42755.55" + process $proc$libresoc.v:42754$2335 assign { } { } assign $0\dp_INT_rabc_div0_15[0:0] \dp_INT_rabc_div0_15$next sync posedge \coresync_clk update \dp_INT_rabc_div0_15 $0\dp_INT_rabc_div0_15[0:0] end - attribute \src "libresoc.v:42960.3-42961.55" - process $proc$libresoc.v:42960$2336 + attribute \src "libresoc.v:42756.3-42757.55" + process $proc$libresoc.v:42756$2336 assign { } { } assign $0\dp_INT_rabc_spr0_14[0:0] \dp_INT_rabc_spr0_14$next sync posedge \coresync_clk update \dp_INT_rabc_spr0_14 $0\dp_INT_rabc_spr0_14[0:0] end - attribute \src "libresoc.v:42962.3-42963.63" - process $proc$libresoc.v:42962$2337 + attribute \src "libresoc.v:42758.3-42759.63" + process $proc$libresoc.v:42758$2337 assign { } { } assign $0\dp_INT_rabc_logical0_13[0:0] \dp_INT_rabc_logical0_13$next sync posedge \coresync_clk update \dp_INT_rabc_logical0_13 $0\dp_INT_rabc_logical0_13[0:0] end - attribute \src "libresoc.v:42964.3-42965.57" - process $proc$libresoc.v:42964$2338 + attribute \src "libresoc.v:42760.3-42761.57" + process $proc$libresoc.v:42760$2338 assign { } { } assign $0\dp_INT_rabc_trap0_12[0:0] \dp_INT_rabc_trap0_12$next sync posedge \coresync_clk update \dp_INT_rabc_trap0_12 $0\dp_INT_rabc_trap0_12[0:0] end - attribute \src "libresoc.v:42966.3-42967.53" - process $proc$libresoc.v:42966$2339 + attribute \src "libresoc.v:42762.3-42763.53" + process $proc$libresoc.v:42762$2339 assign { } { } assign $0\dp_INT_rabc_cr0_11[0:0] \dp_INT_rabc_cr0_11$next sync posedge \coresync_clk update \dp_INT_rabc_cr0_11 $0\dp_INT_rabc_cr0_11[0:0] end - attribute \src "libresoc.v:42968.3-42969.55" - process $proc$libresoc.v:42968$2340 + attribute \src "libresoc.v:42764.3-42765.55" + process $proc$libresoc.v:42764$2340 assign { } { } assign $0\dp_INT_rabc_alu0_10[0:0] \dp_INT_rabc_alu0_10$next sync posedge \coresync_clk update \dp_INT_rabc_alu0_10 $0\dp_INT_rabc_alu0_10[0:0] end - attribute \src "libresoc.v:42970.3-42971.55" - process $proc$libresoc.v:42970$2341 + attribute \src "libresoc.v:42766.3-42767.55" + process $proc$libresoc.v:42766$2341 assign { } { } assign $0\dp_INT_rabc_ldst0_9[0:0] \dp_INT_rabc_ldst0_9$next sync posedge \coresync_clk update \dp_INT_rabc_ldst0_9 $0\dp_INT_rabc_ldst0_9[0:0] end - attribute \src "libresoc.v:42972.3-42973.63" - process $proc$libresoc.v:42972$2342 + attribute \src "libresoc.v:42768.3-42769.63" + process $proc$libresoc.v:42768$2342 assign { } { } assign $0\dp_INT_rabc_shiftrot0_8[0:0] \dp_INT_rabc_shiftrot0_8$next sync posedge \coresync_clk update \dp_INT_rabc_shiftrot0_8 $0\dp_INT_rabc_shiftrot0_8[0:0] end - attribute \src "libresoc.v:42974.3-42975.55" - process $proc$libresoc.v:42974$2343 + attribute \src "libresoc.v:42770.3-42771.55" + process $proc$libresoc.v:42770$2343 assign { } { } assign $0\dp_INT_rabc_ldst0_7[0:0] \dp_INT_rabc_ldst0_7$next sync posedge \coresync_clk update \dp_INT_rabc_ldst0_7 $0\dp_INT_rabc_ldst0_7[0:0] end - attribute \src "libresoc.v:42976.3-42977.63" - process $proc$libresoc.v:42976$2344 + attribute \src "libresoc.v:42772.3-42773.63" + process $proc$libresoc.v:42772$2344 assign { } { } assign $0\dp_INT_rabc_shiftrot0_6[0:0] \dp_INT_rabc_shiftrot0_6$next sync posedge \coresync_clk update \dp_INT_rabc_shiftrot0_6 $0\dp_INT_rabc_shiftrot0_6[0:0] end - attribute \src "libresoc.v:42978.3-42979.53" - process $proc$libresoc.v:42978$2345 + attribute \src "libresoc.v:42774.3-42775.53" + process $proc$libresoc.v:42774$2345 assign { } { } assign $0\dp_INT_rabc_mul0_5[0:0] \dp_INT_rabc_mul0_5$next sync posedge \coresync_clk update \dp_INT_rabc_mul0_5 $0\dp_INT_rabc_mul0_5[0:0] end - attribute \src "libresoc.v:42980.3-42981.53" - process $proc$libresoc.v:42980$2346 + attribute \src "libresoc.v:42776.3-42777.53" + process $proc$libresoc.v:42776$2346 assign { } { } assign $0\dp_INT_rabc_div0_4[0:0] \dp_INT_rabc_div0_4$next sync posedge \coresync_clk update \dp_INT_rabc_div0_4 $0\dp_INT_rabc_div0_4[0:0] end - attribute \src "libresoc.v:42982.3-42983.61" - process $proc$libresoc.v:42982$2347 + attribute \src "libresoc.v:42778.3-42779.61" + process $proc$libresoc.v:42778$2347 assign { } { } assign $0\dp_INT_rabc_logical0_3[0:0] \dp_INT_rabc_logical0_3$next sync posedge \coresync_clk update \dp_INT_rabc_logical0_3 $0\dp_INT_rabc_logical0_3[0:0] end - attribute \src "libresoc.v:42984.3-42985.55" - process $proc$libresoc.v:42984$2348 + attribute \src "libresoc.v:42780.3-42781.55" + process $proc$libresoc.v:42780$2348 assign { } { } assign $0\dp_INT_rabc_trap0_2[0:0] \dp_INT_rabc_trap0_2$next sync posedge \coresync_clk update \dp_INT_rabc_trap0_2 $0\dp_INT_rabc_trap0_2[0:0] end - attribute \src "libresoc.v:42986.3-42987.51" - process $proc$libresoc.v:42986$2349 + attribute \src "libresoc.v:42782.3-42783.51" + process $proc$libresoc.v:42782$2349 assign { } { } assign $0\dp_INT_rabc_cr0_1[0:0] \dp_INT_rabc_cr0_1$next sync posedge \coresync_clk update \dp_INT_rabc_cr0_1 $0\dp_INT_rabc_cr0_1[0:0] end - attribute \src "libresoc.v:42988.3-42989.53" - process $proc$libresoc.v:42988$2350 + attribute \src "libresoc.v:42784.3-42785.53" + process $proc$libresoc.v:42784$2350 assign { } { } assign $0\dp_INT_rabc_alu0_0[0:0] \dp_INT_rabc_alu0_0$next sync posedge \coresync_clk update \dp_INT_rabc_alu0_0 $0\dp_INT_rabc_alu0_0[0:0] end - attribute \src "libresoc.v:42990.3-42991.49" - process $proc$libresoc.v:42990$2351 + attribute \src "libresoc.v:42786.3-42787.49" + process $proc$libresoc.v:42786$2351 assign { } { } assign $0\core_terminate_o[0:0] \core_terminate_o$next sync posedge \coresync_clk update \core_terminate_o $0\core_terminate_o[0:0] end - attribute \src "libresoc.v:42992.3-42993.31" - process $proc$libresoc.v:42992$2352 + attribute \src "libresoc.v:42788.3-42789.31" + process $proc$libresoc.v:42788$2352 assign { } { } assign $0\counter[1:0] \counter$next sync posedge \coresync_clk update \counter $0\counter[1:0] end - attribute \src "libresoc.v:43707.3-43735.6" - process $proc$libresoc.v:43707$2353 + attribute \src "libresoc.v:43503.3-43531.6" + process $proc$libresoc.v:43503$2353 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:43708.5-43708.29" + attribute \src "libresoc.v:43504.5-43504.29" switch \initial - attribute \src "libresoc.v:43708.9-43708.17" + attribute \src "libresoc.v:43504.9-43504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75749,7 +75545,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75765,24 +75561,24 @@ module \core sync always update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] end - attribute \src "libresoc.v:43736.3-43764.6" - process $proc$libresoc.v:43736$2354 + attribute \src "libresoc.v:43532.3-43560.6" + process $proc$libresoc.v:43532$2354 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43737.5-43737.29" + attribute \src "libresoc.v:43533.5-43533.29" switch \initial - attribute \src "libresoc.v:43737.9-43737.17" + attribute \src "libresoc.v:43533.9-43533.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75794,7 +75590,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75810,24 +75606,24 @@ module \core sync always update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] end - attribute \src "libresoc.v:43765.3-43793.6" - process $proc$libresoc.v:43765$2355 + attribute \src "libresoc.v:43561.3-43589.6" + process $proc$libresoc.v:43561$2355 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:43766.5-43766.29" + attribute \src "libresoc.v:43562.5-43562.29" switch \initial - attribute \src "libresoc.v:43766.9-43766.17" + attribute \src "libresoc.v:43562.9-43562.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75839,7 +75635,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75855,24 +75651,24 @@ module \core sync always update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] end - attribute \src "libresoc.v:43794.3-43822.6" - process $proc$libresoc.v:43794$2356 + attribute \src "libresoc.v:43590.3-43618.6" + process $proc$libresoc.v:43590$2356 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:43795.5-43795.29" + attribute \src "libresoc.v:43591.5-43591.29" switch \initial - attribute \src "libresoc.v:43795.9-43795.17" + attribute \src "libresoc.v:43591.9-43591.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75884,7 +75680,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75900,24 +75696,24 @@ module \core sync always update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] end - attribute \src "libresoc.v:43823.3-43851.6" - process $proc$libresoc.v:43823$2357 + attribute \src "libresoc.v:43619.3-43647.6" + process $proc$libresoc.v:43619$2357 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:43824.5-43824.29" + attribute \src "libresoc.v:43620.5-43620.29" switch \initial - attribute \src "libresoc.v:43824.9-43824.17" + attribute \src "libresoc.v:43620.9-43620.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75929,7 +75725,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75945,24 +75741,24 @@ module \core sync always update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] end - attribute \src "libresoc.v:43852.3-43880.6" - process $proc$libresoc.v:43852$2358 + attribute \src "libresoc.v:43648.3-43676.6" + process $proc$libresoc.v:43648$2358 assign { } { } assign { } { } assign $0\fus_cu_issue_i$22[0:0]$2359 $1\fus_cu_issue_i$22[0:0]$2360 - attribute \src "libresoc.v:43853.5-43853.29" + attribute \src "libresoc.v:43649.5-43649.29" switch \initial - attribute \src "libresoc.v:43853.9-43853.17" + attribute \src "libresoc.v:43649.9-43649.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$22[0:0]$2360 $2\fus_cu_issue_i$22[0:0]$2361 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75974,7 +75770,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$22[0:0]$2361 $3\fus_cu_issue_i$22[0:0]$2362 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75990,24 +75786,24 @@ module \core sync always update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2359 end - attribute \src "libresoc.v:43881.3-43909.6" - process $proc$libresoc.v:43881$2363 + attribute \src "libresoc.v:43677.3-43705.6" + process $proc$libresoc.v:43677$2363 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$24[2:0]$2364 $1\fus_cu_rdmaskn_i$24[2:0]$2365 - attribute \src "libresoc.v:43882.5-43882.29" + attribute \src "libresoc.v:43678.5-43678.29" switch \initial - attribute \src "libresoc.v:43882.9-43882.17" + attribute \src "libresoc.v:43678.9-43678.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$24[2:0]$2365 $2\fus_cu_rdmaskn_i$24[2:0]$2366 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76019,7 +75815,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 $3\fus_cu_rdmaskn_i$24[2:0]$2367 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76035,24 +75831,24 @@ module \core sync always update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2364 end - attribute \src "libresoc.v:43910.3-43938.6" - process $proc$libresoc.v:43910$2368 + attribute \src "libresoc.v:43706.3-43734.6" + process $proc$libresoc.v:43706$2368 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43911.5-43911.29" + attribute \src "libresoc.v:43707.5-43707.29" switch \initial - attribute \src "libresoc.v:43911.9-43911.17" + attribute \src "libresoc.v:43707.9-43707.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76064,7 +75860,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76080,24 +75876,24 @@ module \core sync always update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] end - attribute \src "libresoc.v:43939.3-43967.6" - process $proc$libresoc.v:43939$2369 + attribute \src "libresoc.v:43735.3-43763.6" + process $proc$libresoc.v:43735$2369 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__fn_unit[13:0] $1\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43940.5-43940.29" + attribute \src "libresoc.v:43736.5-43736.29" switch \initial - attribute \src "libresoc.v:43940.9-43940.17" + attribute \src "libresoc.v:43736.9-43736.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__fn_unit[13:0] $2\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76109,7 +75905,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] $3\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76125,24 +75921,24 @@ module \core sync always update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[13:0] end - attribute \src "libresoc.v:43968.3-43996.6" - process $proc$libresoc.v:43968$2370 + attribute \src "libresoc.v:43764.3-43792.6" + process $proc$libresoc.v:43764$2370 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43969.5-43969.29" + attribute \src "libresoc.v:43765.5-43765.29" switch \initial - attribute \src "libresoc.v:43969.9-43969.17" + attribute \src "libresoc.v:43765.9-43765.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76154,7 +75950,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76170,24 +75966,24 @@ module \core sync always update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] end - attribute \src "libresoc.v:43997.3-44025.6" - process $proc$libresoc.v:43997$2371 + attribute \src "libresoc.v:43793.3-43821.6" + process $proc$libresoc.v:43793$2371 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:43998.5-43998.29" + attribute \src "libresoc.v:43794.5-43794.29" switch \initial - attribute \src "libresoc.v:43998.9-43998.17" + attribute \src "libresoc.v:43794.9-43794.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76199,7 +75995,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76215,24 +76011,24 @@ module \core sync always update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] end - attribute \src "libresoc.v:44026.3-44054.6" - process $proc$libresoc.v:44026$2372 + attribute \src "libresoc.v:43822.3-43850.6" + process $proc$libresoc.v:43822$2372 assign { } { } assign { } { } assign $0\fus_cu_issue_i$25[0:0]$2373 $1\fus_cu_issue_i$25[0:0]$2374 - attribute \src "libresoc.v:44027.5-44027.29" + attribute \src "libresoc.v:43823.5-43823.29" switch \initial - attribute \src "libresoc.v:44027.9-44027.17" + attribute \src "libresoc.v:43823.9-43823.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$25[0:0]$2374 $2\fus_cu_issue_i$25[0:0]$2375 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76244,7 +76040,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$25[0:0]$2375 $3\fus_cu_issue_i$25[0:0]$2376 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76260,24 +76056,24 @@ module \core sync always update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2373 end - attribute \src "libresoc.v:44055.3-44083.6" - process $proc$libresoc.v:44055$2377 + attribute \src "libresoc.v:43851.3-43879.6" + process $proc$libresoc.v:43851$2377 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$27[5:0]$2378 $1\fus_cu_rdmaskn_i$27[5:0]$2379 - attribute \src "libresoc.v:44056.5-44056.29" + attribute \src "libresoc.v:43852.5-43852.29" switch \initial - attribute \src "libresoc.v:44056.9-44056.17" + attribute \src "libresoc.v:43852.9-43852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$27[5:0]$2379 $2\fus_cu_rdmaskn_i$27[5:0]$2380 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76289,7 +76085,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 $3\fus_cu_rdmaskn_i$27[5:0]$2381 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76305,24 +76101,24 @@ module \core sync always update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[5:0]$2378 end - attribute \src "libresoc.v:44084.3-44112.6" - process $proc$libresoc.v:44084$2382 + attribute \src "libresoc.v:43880.3-43908.6" + process $proc$libresoc.v:43880$2382 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44085.5-44085.29" + attribute \src "libresoc.v:43881.5-43881.29" switch \initial - attribute \src "libresoc.v:44085.9-44085.17" + attribute \src "libresoc.v:43881.9-43881.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76334,7 +76130,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76350,24 +76146,24 @@ module \core sync always update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] end - attribute \src "libresoc.v:44113.3-44141.6" - process $proc$libresoc.v:44113$2383 + attribute \src "libresoc.v:43909.3-43937.6" + process $proc$libresoc.v:43909$2383 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__fn_unit[13:0] $1\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44114.5-44114.29" + attribute \src "libresoc.v:43910.5-43910.29" switch \initial - attribute \src "libresoc.v:44114.9-44114.17" + attribute \src "libresoc.v:43910.9-43910.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__fn_unit[13:0] $2\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76379,7 +76175,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__fn_unit[13:0] $3\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76395,21 +76191,21 @@ module \core sync always update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[13:0] end - attribute \src "libresoc.v:44142.3-44171.6" - process $proc$libresoc.v:44142$2384 + attribute \src "libresoc.v:43938.3-43967.6" + process $proc$libresoc.v:43938$2384 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44143.5-44143.29" + attribute \src "libresoc.v:43939.5-43939.29" switch \initial - attribute \src "libresoc.v:44143.9-44143.17" + attribute \src "libresoc.v:43939.9-43939.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76417,7 +76213,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76433,7 +76229,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76453,21 +76249,21 @@ module \core update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44172.3-44201.6" - process $proc$libresoc.v:44172$2385 + attribute \src "libresoc.v:43968.3-43997.6" + process $proc$libresoc.v:43968$2385 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44173.5-44173.29" + attribute \src "libresoc.v:43969.5-43969.29" switch \initial - attribute \src "libresoc.v:44173.9-44173.17" + attribute \src "libresoc.v:43969.9-43969.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76475,7 +76271,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76491,7 +76287,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76511,21 +76307,21 @@ module \core update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] end - attribute \src "libresoc.v:44202.3-44231.6" - process $proc$libresoc.v:44202$2386 + attribute \src "libresoc.v:43998.3-44027.6" + process $proc$libresoc.v:43998$2386 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44203.5-44203.29" + attribute \src "libresoc.v:43999.5-43999.29" switch \initial - attribute \src "libresoc.v:44203.9-44203.17" + attribute \src "libresoc.v:43999.9-43999.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76533,7 +76329,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76549,7 +76345,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76569,24 +76365,24 @@ module \core update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] end - attribute \src "libresoc.v:44232.3-44260.6" - process $proc$libresoc.v:44232$2387 + attribute \src "libresoc.v:44028.3-44056.6" + process $proc$libresoc.v:44028$2387 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44233.5-44233.29" + attribute \src "libresoc.v:44029.5-44029.29" switch \initial - attribute \src "libresoc.v:44233.9-44233.17" + attribute \src "libresoc.v:44029.9-44029.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76598,7 +76394,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76614,24 +76410,24 @@ module \core sync always update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] end - attribute \src "libresoc.v:44261.3-44289.6" - process $proc$libresoc.v:44261$2388 + attribute \src "libresoc.v:44057.3-44085.6" + process $proc$libresoc.v:44057$2388 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:44262.5-44262.29" + attribute \src "libresoc.v:44058.5-44058.29" switch \initial - attribute \src "libresoc.v:44262.9-44262.17" + attribute \src "libresoc.v:44058.9-44058.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76643,7 +76439,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76659,24 +76455,24 @@ module \core sync always update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] end - attribute \src "libresoc.v:44290.3-44318.6" - process $proc$libresoc.v:44290$2389 + attribute \src "libresoc.v:44086.3-44114.6" + process $proc$libresoc.v:44086$2389 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44291.5-44291.29" + attribute \src "libresoc.v:44087.5-44087.29" switch \initial - attribute \src "libresoc.v:44291.9-44291.17" + attribute \src "libresoc.v:44087.9-44087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76688,7 +76484,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76704,24 +76500,24 @@ module \core sync always update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] end - attribute \src "libresoc.v:44319.3-44347.6" - process $proc$libresoc.v:44319$2390 + attribute \src "libresoc.v:44115.3-44143.6" + process $proc$libresoc.v:44115$2390 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44320.5-44320.29" + attribute \src "libresoc.v:44116.5-44116.29" switch \initial - attribute \src "libresoc.v:44320.9-44320.17" + attribute \src "libresoc.v:44116.9-44116.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76733,7 +76529,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76749,24 +76545,24 @@ module \core sync always update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] end - attribute \src "libresoc.v:44348.3-44376.6" - process $proc$libresoc.v:44348$2391 + attribute \src "libresoc.v:44144.3-44172.6" + process $proc$libresoc.v:44144$2391 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44349.5-44349.29" + attribute \src "libresoc.v:44145.5-44145.29" switch \initial - attribute \src "libresoc.v:44349.9-44349.17" + attribute \src "libresoc.v:44145.9-44145.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76778,7 +76574,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76794,24 +76590,24 @@ module \core sync always update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] end - attribute \src "libresoc.v:44377.3-44405.6" - process $proc$libresoc.v:44377$2392 + attribute \src "libresoc.v:44173.3-44201.6" + process $proc$libresoc.v:44173$2392 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44378.5-44378.29" + attribute \src "libresoc.v:44174.5-44174.29" switch \initial - attribute \src "libresoc.v:44378.9-44378.17" + attribute \src "libresoc.v:44174.9-44174.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76823,7 +76619,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76839,24 +76635,24 @@ module \core sync always update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] end - attribute \src "libresoc.v:44406.3-44434.6" - process $proc$libresoc.v:44406$2393 + attribute \src "libresoc.v:44202.3-44230.6" + process $proc$libresoc.v:44202$2393 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44407.5-44407.29" + attribute \src "libresoc.v:44203.5-44203.29" switch \initial - attribute \src "libresoc.v:44407.9-44407.17" + attribute \src "libresoc.v:44203.9-44203.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76868,7 +76664,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76884,24 +76680,24 @@ module \core sync always update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] end - attribute \src "libresoc.v:44435.3-44463.6" - process $proc$libresoc.v:44435$2394 + attribute \src "libresoc.v:44231.3-44259.6" + process $proc$libresoc.v:44231$2394 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44436.5-44436.29" + attribute \src "libresoc.v:44232.5-44232.29" switch \initial - attribute \src "libresoc.v:44436.9-44436.17" + attribute \src "libresoc.v:44232.9-44232.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76913,7 +76709,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76929,24 +76725,24 @@ module \core sync always update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] end - attribute \src "libresoc.v:44464.3-44492.6" - process $proc$libresoc.v:44464$2395 + attribute \src "libresoc.v:44260.3-44288.6" + process $proc$libresoc.v:44260$2395 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44465.5-44465.29" + attribute \src "libresoc.v:44261.5-44261.29" switch \initial - attribute \src "libresoc.v:44465.9-44465.17" + attribute \src "libresoc.v:44261.9-44261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76958,7 +76754,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76974,24 +76770,24 @@ module \core sync always update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] end - attribute \src "libresoc.v:44493.3-44521.6" - process $proc$libresoc.v:44493$2396 + attribute \src "libresoc.v:44289.3-44317.6" + process $proc$libresoc.v:44289$2396 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44494.5-44494.29" + attribute \src "libresoc.v:44290.5-44290.29" switch \initial - attribute \src "libresoc.v:44494.9-44494.17" + attribute \src "libresoc.v:44290.9-44290.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77003,7 +76799,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77019,24 +76815,24 @@ module \core sync always update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] end - attribute \src "libresoc.v:44522.3-44550.6" - process $proc$libresoc.v:44522$2397 + attribute \src "libresoc.v:44318.3-44346.6" + process $proc$libresoc.v:44318$2397 assign { } { } assign { } { } assign $0\fus_cu_issue_i$28[0:0]$2398 $1\fus_cu_issue_i$28[0:0]$2399 - attribute \src "libresoc.v:44523.5-44523.29" + attribute \src "libresoc.v:44319.5-44319.29" switch \initial - attribute \src "libresoc.v:44523.9-44523.17" + attribute \src "libresoc.v:44319.9-44319.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$28[0:0]$2399 $2\fus_cu_issue_i$28[0:0]$2400 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77048,7 +76844,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$28[0:0]$2400 $3\fus_cu_issue_i$28[0:0]$2401 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77064,24 +76860,24 @@ module \core sync always update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2398 end - attribute \src "libresoc.v:44551.3-44579.6" - process $proc$libresoc.v:44551$2402 + attribute \src "libresoc.v:44347.3-44375.6" + process $proc$libresoc.v:44347$2402 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$30[2:0]$2403 $1\fus_cu_rdmaskn_i$30[2:0]$2404 - attribute \src "libresoc.v:44552.5-44552.29" + attribute \src "libresoc.v:44348.5-44348.29" switch \initial - attribute \src "libresoc.v:44552.9-44552.17" + attribute \src "libresoc.v:44348.9-44348.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$30[2:0]$2404 $2\fus_cu_rdmaskn_i$30[2:0]$2405 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77093,7 +76889,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 $3\fus_cu_rdmaskn_i$30[2:0]$2406 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77109,24 +76905,24 @@ module \core sync always update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2403 end - attribute \src "libresoc.v:44580.3-44608.6" - process $proc$libresoc.v:44580$2407 + attribute \src "libresoc.v:44376.3-44404.6" + process $proc$libresoc.v:44376$2407 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44581.5-44581.29" + attribute \src "libresoc.v:44377.5-44377.29" switch \initial - attribute \src "libresoc.v:44581.9-44581.17" + attribute \src "libresoc.v:44377.9-44377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77138,7 +76934,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77154,24 +76950,24 @@ module \core sync always update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] end - attribute \src "libresoc.v:44609.3-44637.6" - process $proc$libresoc.v:44609$2408 + attribute \src "libresoc.v:44405.3-44433.6" + process $proc$libresoc.v:44405$2408 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__fn_unit[13:0] $1\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44610.5-44610.29" + attribute \src "libresoc.v:44406.5-44406.29" switch \initial - attribute \src "libresoc.v:44610.9-44610.17" + attribute \src "libresoc.v:44406.9-44406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__fn_unit[13:0] $2\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77183,7 +76979,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] $3\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77199,21 +76995,21 @@ module \core sync always update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[13:0] end - attribute \src "libresoc.v:44638.3-44667.6" - process $proc$libresoc.v:44638$2409 + attribute \src "libresoc.v:44434.3-44463.6" + process $proc$libresoc.v:44434$2409 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44639.5-44639.29" + attribute \src "libresoc.v:44435.5-44435.29" switch \initial - attribute \src "libresoc.v:44639.9-44639.17" + attribute \src "libresoc.v:44435.9-44435.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77221,7 +77017,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77237,7 +77033,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77257,21 +77053,21 @@ module \core update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44668.3-44697.6" - process $proc$libresoc.v:44668$2410 + attribute \src "libresoc.v:44464.3-44493.6" + process $proc$libresoc.v:44464$2410 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44669.5-44669.29" + attribute \src "libresoc.v:44465.5-44465.29" switch \initial - attribute \src "libresoc.v:44669.9-44669.17" + attribute \src "libresoc.v:44465.9-44465.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77279,7 +77075,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77295,7 +77091,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77315,21 +77111,21 @@ module \core update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] end - attribute \src "libresoc.v:44698.3-44727.6" - process $proc$libresoc.v:44698$2411 + attribute \src "libresoc.v:44494.3-44523.6" + process $proc$libresoc.v:44494$2411 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44699.5-44699.29" + attribute \src "libresoc.v:44495.5-44495.29" switch \initial - attribute \src "libresoc.v:44699.9-44699.17" + attribute \src "libresoc.v:44495.9-44495.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77337,7 +77133,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77353,7 +77149,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77373,24 +77169,24 @@ module \core update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] end - attribute \src "libresoc.v:44728.3-44756.6" - process $proc$libresoc.v:44728$2412 + attribute \src "libresoc.v:44524.3-44552.6" + process $proc$libresoc.v:44524$2412 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44729.5-44729.29" + attribute \src "libresoc.v:44525.5-44525.29" switch \initial - attribute \src "libresoc.v:44729.9-44729.17" + attribute \src "libresoc.v:44525.9-44525.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77402,7 +77198,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77418,24 +77214,24 @@ module \core sync always update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] end - attribute \src "libresoc.v:44757.3-44785.6" - process $proc$libresoc.v:44757$2413 + attribute \src "libresoc.v:44553.3-44581.6" + process $proc$libresoc.v:44553$2413 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44758.5-44758.29" + attribute \src "libresoc.v:44554.5-44554.29" switch \initial - attribute \src "libresoc.v:44758.9-44758.17" + attribute \src "libresoc.v:44554.9-44554.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77447,7 +77243,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77463,24 +77259,24 @@ module \core sync always update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] end - attribute \src "libresoc.v:44786.3-44814.6" - process $proc$libresoc.v:44786$2414 + attribute \src "libresoc.v:44582.3-44610.6" + process $proc$libresoc.v:44582$2414 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44787.5-44787.29" + attribute \src "libresoc.v:44583.5-44583.29" switch \initial - attribute \src "libresoc.v:44787.9-44787.17" + attribute \src "libresoc.v:44583.9-44583.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77492,7 +77288,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77508,24 +77304,24 @@ module \core sync always update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] end - attribute \src "libresoc.v:44815.3-44843.6" - process $proc$libresoc.v:44815$2415 + attribute \src "libresoc.v:44611.3-44639.6" + process $proc$libresoc.v:44611$2415 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44816.5-44816.29" + attribute \src "libresoc.v:44612.5-44612.29" switch \initial - attribute \src "libresoc.v:44816.9-44816.17" + attribute \src "libresoc.v:44612.9-44612.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77537,7 +77333,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77553,24 +77349,24 @@ module \core sync always update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] end - attribute \src "libresoc.v:44844.3-44872.6" - process $proc$libresoc.v:44844$2416 + attribute \src "libresoc.v:44640.3-44668.6" + process $proc$libresoc.v:44640$2416 assign { } { } assign { } { } assign $0\fus_cu_issue_i$31[0:0]$2417 $1\fus_cu_issue_i$31[0:0]$2418 - attribute \src "libresoc.v:44845.5-44845.29" + attribute \src "libresoc.v:44641.5-44641.29" switch \initial - attribute \src "libresoc.v:44845.9-44845.17" + attribute \src "libresoc.v:44641.9-44641.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$31[0:0]$2418 $2\fus_cu_issue_i$31[0:0]$2419 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77582,7 +77378,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$31[0:0]$2419 $3\fus_cu_issue_i$31[0:0]$2420 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77598,24 +77394,24 @@ module \core sync always update \fus_cu_issue_i$31 $0\fus_cu_issue_i$31[0:0]$2417 end - attribute \src "libresoc.v:44873.3-44901.6" - process $proc$libresoc.v:44873$2421 + attribute \src "libresoc.v:44669.3-44697.6" + process $proc$libresoc.v:44669$2421 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$33[2:0]$2422 $1\fus_cu_rdmaskn_i$33[2:0]$2423 - attribute \src "libresoc.v:44874.5-44874.29" + attribute \src "libresoc.v:44670.5-44670.29" switch \initial - attribute \src "libresoc.v:44874.9-44874.17" + attribute \src "libresoc.v:44670.9-44670.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$33[2:0]$2423 $2\fus_cu_rdmaskn_i$33[2:0]$2424 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77627,7 +77423,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 $3\fus_cu_rdmaskn_i$33[2:0]$2425 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77643,24 +77439,24 @@ module \core sync always update \fus_cu_rdmaskn_i$33 $0\fus_cu_rdmaskn_i$33[2:0]$2422 end - attribute \src "libresoc.v:44902.3-44930.6" - process $proc$libresoc.v:44902$2426 + attribute \src "libresoc.v:44698.3-44726.6" + process $proc$libresoc.v:44698$2426 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44903.5-44903.29" + attribute \src "libresoc.v:44699.5-44699.29" switch \initial - attribute \src "libresoc.v:44903.9-44903.17" + attribute \src "libresoc.v:44699.9-44699.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77672,7 +77468,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77688,24 +77484,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] end - attribute \src "libresoc.v:44931.3-44959.6" - process $proc$libresoc.v:44931$2427 + attribute \src "libresoc.v:44727.3-44755.6" + process $proc$libresoc.v:44727$2427 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44932.5-44932.29" + attribute \src "libresoc.v:44728.5-44728.29" switch \initial - attribute \src "libresoc.v:44932.9-44932.17" + attribute \src "libresoc.v:44728.9-44728.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77717,7 +77513,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77733,21 +77529,21 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] end - attribute \src "libresoc.v:44960.3-44989.6" - process $proc$libresoc.v:44960$2428 + attribute \src "libresoc.v:44756.3-44785.6" + process $proc$libresoc.v:44756$2428 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44961.5-44961.29" + attribute \src "libresoc.v:44757.5-44757.29" switch \initial - attribute \src "libresoc.v:44961.9-44961.17" + attribute \src "libresoc.v:44757.9-44757.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77755,7 +77551,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77771,7 +77567,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77791,21 +77587,21 @@ module \core update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44990.3-45019.6" - process $proc$libresoc.v:44990$2429 + attribute \src "libresoc.v:44786.3-44815.6" + process $proc$libresoc.v:44786$2429 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44991.5-44991.29" + attribute \src "libresoc.v:44787.5-44787.29" switch \initial - attribute \src "libresoc.v:44991.9-44991.17" + attribute \src "libresoc.v:44787.9-44787.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77813,7 +77609,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77829,7 +77625,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77849,21 +77645,21 @@ module \core update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] end - attribute \src "libresoc.v:45020.3-45049.6" - process $proc$libresoc.v:45020$2430 + attribute \src "libresoc.v:44816.3-44845.6" + process $proc$libresoc.v:44816$2430 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45021.5-45021.29" + attribute \src "libresoc.v:44817.5-44817.29" switch \initial - attribute \src "libresoc.v:45021.9-45021.17" + attribute \src "libresoc.v:44817.9-44817.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77871,7 +77667,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77887,7 +77683,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77907,24 +77703,24 @@ module \core update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] end - attribute \src "libresoc.v:45050.3-45078.6" - process $proc$libresoc.v:45050$2431 + attribute \src "libresoc.v:44846.3-44874.6" + process $proc$libresoc.v:44846$2431 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:45051.5-45051.29" + attribute \src "libresoc.v:44847.5-44847.29" switch \initial - attribute \src "libresoc.v:45051.9-45051.17" + attribute \src "libresoc.v:44847.9-44847.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77936,7 +77732,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77952,24 +77748,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] end - attribute \src "libresoc.v:45079.3-45107.6" - process $proc$libresoc.v:45079$2432 + attribute \src "libresoc.v:44875.3-44903.6" + process $proc$libresoc.v:44875$2432 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45080.5-45080.29" + attribute \src "libresoc.v:44876.5-44876.29" switch \initial - attribute \src "libresoc.v:45080.9-45080.17" + attribute \src "libresoc.v:44876.9-44876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77981,7 +77777,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77997,24 +77793,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] end - attribute \src "libresoc.v:45108.3-45136.6" - process $proc$libresoc.v:45108$2433 + attribute \src "libresoc.v:44904.3-44932.6" + process $proc$libresoc.v:44904$2433 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45109.5-45109.29" + attribute \src "libresoc.v:44905.5-44905.29" switch \initial - attribute \src "libresoc.v:45109.9-45109.17" + attribute \src "libresoc.v:44905.9-44905.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78026,7 +77822,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78042,24 +77838,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] end - attribute \src "libresoc.v:45137.3-45165.6" - process $proc$libresoc.v:45137$2434 + attribute \src "libresoc.v:44933.3-44961.6" + process $proc$libresoc.v:44933$2434 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45138.5-45138.29" + attribute \src "libresoc.v:44934.5-44934.29" switch \initial - attribute \src "libresoc.v:45138.9-45138.17" + attribute \src "libresoc.v:44934.9-44934.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78071,7 +77867,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78087,24 +77883,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] end - attribute \src "libresoc.v:45166.3-45194.6" - process $proc$libresoc.v:45166$2435 + attribute \src "libresoc.v:44962.3-44990.6" + process $proc$libresoc.v:44962$2435 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45167.5-45167.29" + attribute \src "libresoc.v:44963.5-44963.29" switch \initial - attribute \src "libresoc.v:45167.9-45167.17" + attribute \src "libresoc.v:44963.9-44963.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78116,7 +77912,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78132,24 +77928,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] end - attribute \src "libresoc.v:45195.3-45223.6" - process $proc$libresoc.v:45195$2436 + attribute \src "libresoc.v:44991.3-45019.6" + process $proc$libresoc.v:44991$2436 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:45196.5-45196.29" + attribute \src "libresoc.v:44992.5-44992.29" switch \initial - attribute \src "libresoc.v:45196.9-45196.17" + attribute \src "libresoc.v:44992.9-44992.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78161,7 +77957,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78177,24 +77973,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] end - attribute \src "libresoc.v:45224.3-45252.6" - process $proc$libresoc.v:45224$2437 + attribute \src "libresoc.v:45020.3-45048.6" + process $proc$libresoc.v:45020$2437 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45225.5-45225.29" + attribute \src "libresoc.v:45021.5-45021.29" switch \initial - attribute \src "libresoc.v:45225.9-45225.17" + attribute \src "libresoc.v:45021.9-45021.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78206,7 +78002,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78222,24 +78018,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] end - attribute \src "libresoc.v:45253.3-45281.6" - process $proc$libresoc.v:45253$2438 + attribute \src "libresoc.v:45049.3-45077.6" + process $proc$libresoc.v:45049$2438 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45254.5-45254.29" + attribute \src "libresoc.v:45050.5-45050.29" switch \initial - attribute \src "libresoc.v:45254.9-45254.17" + attribute \src "libresoc.v:45050.9-45050.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78251,7 +78047,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78267,24 +78063,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] end - attribute \src "libresoc.v:45282.3-45310.6" - process $proc$libresoc.v:45282$2439 + attribute \src "libresoc.v:45078.3-45106.6" + process $proc$libresoc.v:45078$2439 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:45283.5-45283.29" + attribute \src "libresoc.v:45079.5-45079.29" switch \initial - attribute \src "libresoc.v:45283.9-45283.17" + attribute \src "libresoc.v:45079.9-45079.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78296,7 +78092,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78312,24 +78108,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] end - attribute \src "libresoc.v:45311.3-45339.6" - process $proc$libresoc.v:45311$2440 + attribute \src "libresoc.v:45107.3-45135.6" + process $proc$libresoc.v:45107$2440 assign { } { } assign { } { } assign $0\fus_cu_issue_i$34[0:0]$2441 $1\fus_cu_issue_i$34[0:0]$2442 - attribute \src "libresoc.v:45312.5-45312.29" + attribute \src "libresoc.v:45108.5-45108.29" switch \initial - attribute \src "libresoc.v:45312.9-45312.17" + attribute \src "libresoc.v:45108.9-45108.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$34[0:0]$2442 $2\fus_cu_issue_i$34[0:0]$2443 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78341,7 +78137,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$34[0:0]$2443 $3\fus_cu_issue_i$34[0:0]$2444 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78357,24 +78153,24 @@ module \core sync always update \fus_cu_issue_i$34 $0\fus_cu_issue_i$34[0:0]$2441 end - attribute \src "libresoc.v:45340.3-45368.6" - process $proc$libresoc.v:45340$2445 + attribute \src "libresoc.v:45136.3-45164.6" + process $proc$libresoc.v:45136$2445 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$36[4:0]$2446 $1\fus_cu_rdmaskn_i$36[4:0]$2447 - attribute \src "libresoc.v:45341.5-45341.29" + attribute \src "libresoc.v:45137.5-45137.29" switch \initial - attribute \src "libresoc.v:45341.9-45341.17" + attribute \src "libresoc.v:45137.9-45137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$36[4:0]$2447 $2\fus_cu_rdmaskn_i$36[4:0]$2448 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78386,7 +78182,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 $3\fus_cu_rdmaskn_i$36[4:0]$2449 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78402,24 +78198,24 @@ module \core sync always update \fus_cu_rdmaskn_i$36 $0\fus_cu_rdmaskn_i$36[4:0]$2446 end - attribute \src "libresoc.v:45369.3-45397.6" - process $proc$libresoc.v:45369$2450 + attribute \src "libresoc.v:45165.3-45193.6" + process $proc$libresoc.v:45165$2450 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45370.5-45370.29" + attribute \src "libresoc.v:45166.5-45166.29" switch \initial - attribute \src "libresoc.v:45370.9-45370.17" + attribute \src "libresoc.v:45166.9-45166.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78431,7 +78227,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78447,24 +78243,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] end - attribute \src "libresoc.v:45398.3-45426.6" - process $proc$libresoc.v:45398$2451 + attribute \src "libresoc.v:45194.3-45222.6" + process $proc$libresoc.v:45194$2451 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45399.5-45399.29" + attribute \src "libresoc.v:45195.5-45195.29" switch \initial - attribute \src "libresoc.v:45399.9-45399.17" + attribute \src "libresoc.v:45195.9-45195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78476,7 +78272,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78492,21 +78288,21 @@ module \core sync always update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] end - attribute \src "libresoc.v:45427.3-45456.6" - process $proc$libresoc.v:45427$2452 + attribute \src "libresoc.v:45223.3-45252.6" + process $proc$libresoc.v:45223$2452 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45428.5-45428.29" + attribute \src "libresoc.v:45224.5-45224.29" switch \initial - attribute \src "libresoc.v:45428.9-45428.17" + attribute \src "libresoc.v:45224.9-45224.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78514,7 +78310,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78530,7 +78326,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78550,24 +78346,24 @@ module \core update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] end - attribute \src "libresoc.v:45457.3-45485.6" - process $proc$libresoc.v:45457$2453 + attribute \src "libresoc.v:45253.3-45281.6" + process $proc$libresoc.v:45253$2453 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45458.5-45458.29" + attribute \src "libresoc.v:45254.5-45254.29" switch \initial - attribute \src "libresoc.v:45458.9-45458.17" + attribute \src "libresoc.v:45254.9-45254.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78579,7 +78375,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78595,21 +78391,21 @@ module \core sync always update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] end - attribute \src "libresoc.v:45486.3-45515.6" - process $proc$libresoc.v:45486$2454 + attribute \src "libresoc.v:45282.3-45311.6" + process $proc$libresoc.v:45282$2454 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45487.5-45487.29" + attribute \src "libresoc.v:45283.5-45283.29" switch \initial - attribute \src "libresoc.v:45487.9-45487.17" + attribute \src "libresoc.v:45283.9-45283.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78617,7 +78413,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78633,7 +78429,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78653,21 +78449,21 @@ module \core update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] end - attribute \src "libresoc.v:45516.3-45545.6" - process $proc$libresoc.v:45516$2455 + attribute \src "libresoc.v:45312.3-45341.6" + process $proc$libresoc.v:45312$2455 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45517.5-45517.29" + attribute \src "libresoc.v:45313.5-45313.29" switch \initial - attribute \src "libresoc.v:45517.9-45517.17" + attribute \src "libresoc.v:45313.9-45313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78675,7 +78471,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78691,7 +78487,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78711,24 +78507,24 @@ module \core update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] end - attribute \src "libresoc.v:45546.3-45574.6" - process $proc$libresoc.v:45546$2456 + attribute \src "libresoc.v:45342.3-45370.6" + process $proc$libresoc.v:45342$2456 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45547.5-45547.29" + attribute \src "libresoc.v:45343.5-45343.29" switch \initial - attribute \src "libresoc.v:45547.9-45547.17" + attribute \src "libresoc.v:45343.9-45343.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78740,7 +78536,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78756,24 +78552,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] end - attribute \src "libresoc.v:45575.3-45603.6" - process $proc$libresoc.v:45575$2457 + attribute \src "libresoc.v:45371.3-45399.6" + process $proc$libresoc.v:45371$2457 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45576.5-45576.29" + attribute \src "libresoc.v:45372.5-45372.29" switch \initial - attribute \src "libresoc.v:45576.9-45576.17" + attribute \src "libresoc.v:45372.9-45372.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78785,7 +78581,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78801,24 +78597,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] end - attribute \src "libresoc.v:45604.3-45632.6" - process $proc$libresoc.v:45604$2458 + attribute \src "libresoc.v:45400.3-45428.6" + process $proc$libresoc.v:45400$2458 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45605.5-45605.29" + attribute \src "libresoc.v:45401.5-45401.29" switch \initial - attribute \src "libresoc.v:45605.9-45605.17" + attribute \src "libresoc.v:45401.9-45401.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78830,7 +78626,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78846,24 +78642,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] end - attribute \src "libresoc.v:45633.3-45661.6" - process $proc$libresoc.v:45633$2459 + attribute \src "libresoc.v:45429.3-45457.6" + process $proc$libresoc.v:45429$2459 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45634.5-45634.29" + attribute \src "libresoc.v:45430.5-45430.29" switch \initial - attribute \src "libresoc.v:45634.9-45634.17" + attribute \src "libresoc.v:45430.9-45430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78875,7 +78671,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78891,24 +78687,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] end - attribute \src "libresoc.v:45662.3-45690.6" - process $proc$libresoc.v:45662$2460 + attribute \src "libresoc.v:45458.3-45486.6" + process $proc$libresoc.v:45458$2460 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45663.5-45663.29" + attribute \src "libresoc.v:45459.5-45459.29" switch \initial - attribute \src "libresoc.v:45663.9-45663.17" + attribute \src "libresoc.v:45459.9-45459.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78920,7 +78716,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78936,24 +78732,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] end - attribute \src "libresoc.v:45691.3-45719.6" - process $proc$libresoc.v:45691$2461 + attribute \src "libresoc.v:45487.3-45515.6" + process $proc$libresoc.v:45487$2461 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45692.5-45692.29" + attribute \src "libresoc.v:45488.5-45488.29" switch \initial - attribute \src "libresoc.v:45692.9-45692.17" + attribute \src "libresoc.v:45488.9-45488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78965,7 +78761,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78981,24 +78777,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] end - attribute \src "libresoc.v:45720.3-45748.6" - process $proc$libresoc.v:45720$2462 + attribute \src "libresoc.v:45516.3-45544.6" + process $proc$libresoc.v:45516$2462 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45721.5-45721.29" + attribute \src "libresoc.v:45517.5-45517.29" switch \initial - attribute \src "libresoc.v:45721.9-45721.17" + attribute \src "libresoc.v:45517.9-45517.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79010,7 +78806,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -79026,24 +78822,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] end - attribute \src "libresoc.v:45749.3-45777.6" - process $proc$libresoc.v:45749$2463 + attribute \src "libresoc.v:45545.3-45573.6" + process $proc$libresoc.v:45545$2463 assign { } { } assign { } { } assign $0\fus_cu_issue_i$37[0:0]$2464 $1\fus_cu_issue_i$37[0:0]$2465 - attribute \src "libresoc.v:45750.5-45750.29" + attribute \src "libresoc.v:45546.5-45546.29" switch \initial - attribute \src "libresoc.v:45750.9-45750.17" + attribute \src "libresoc.v:45546.9-45546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$37[0:0]$2465 $2\fus_cu_issue_i$37[0:0]$2466 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79055,7 +78851,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$37[0:0]$2466 $3\fus_cu_issue_i$37[0:0]$2467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -79071,24 +78867,24 @@ module \core sync always update \fus_cu_issue_i$37 $0\fus_cu_issue_i$37[0:0]$2464 end - attribute \src "libresoc.v:45778.3-45806.6" - process $proc$libresoc.v:45778$2468 + attribute \src "libresoc.v:45574.3-45602.6" + process $proc$libresoc.v:45574$2468 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$39[2:0]$2469 $1\fus_cu_rdmaskn_i$39[2:0]$2470 - attribute \src "libresoc.v:45779.5-45779.29" + attribute \src "libresoc.v:45575.5-45575.29" switch \initial - attribute \src "libresoc.v:45779.9-45779.17" + attribute \src "libresoc.v:45575.9-45575.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$39[2:0]$2470 $2\fus_cu_rdmaskn_i$39[2:0]$2471 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79100,7 +78896,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 $3\fus_cu_rdmaskn_i$39[2:0]$2472 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -79116,14 +78912,14 @@ module \core sync always update \fus_cu_rdmaskn_i$39 $0\fus_cu_rdmaskn_i$39[2:0]$2469 end - attribute \src "libresoc.v:45807.3-45815.6" - process $proc$libresoc.v:45807$2473 + attribute \src "libresoc.v:45603.3-45611.6" + process $proc$libresoc.v:45603$2473 assign { } { } assign { } { } assign $0\dp_INT_rabc_alu0_0$next[0:0]$2474 $1\dp_INT_rabc_alu0_0$next[0:0]$2475 - attribute \src "libresoc.v:45808.5-45808.29" + attribute \src "libresoc.v:45604.5-45604.29" switch \initial - attribute \src "libresoc.v:45808.9-45808.17" + attribute \src "libresoc.v:45604.9-45604.17" case 1'1 case end @@ -79139,37 +78935,37 @@ module \core sync always update \dp_INT_rabc_alu0_0$next $0\dp_INT_rabc_alu0_0$next[0:0]$2474 end - attribute \src "libresoc.v:45816.3-45825.6" - process $proc$libresoc.v:45816$2476 + attribute \src "libresoc.v:45612.3-45621.6" + process $proc$libresoc.v:45612$2476 assign { } { } assign { } { } assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] - attribute \src "libresoc.v:45817.5-45817.29" + attribute \src "libresoc.v:45613.5-45613.29" switch \initial - attribute \src "libresoc.v:45817.9-45817.17" + attribute \src "libresoc.v:45613.9-45613.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i[63:0] \int_src__data_o + assign $1\fus_src2_i[63:0] \int_src1__data_o case assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i $0\fus_src2_i[63:0] end - attribute \src "libresoc.v:45826.3-45834.6" - process $proc$libresoc.v:45826$2477 + attribute \src "libresoc.v:45622.3-45630.6" + process $proc$libresoc.v:45622$2477 assign { } { } assign { } { } assign $0\dp_INT_rabc_cr0_1$next[0:0]$2478 $1\dp_INT_rabc_cr0_1$next[0:0]$2479 - attribute \src "libresoc.v:45827.5-45827.29" + attribute \src "libresoc.v:45623.5-45623.29" switch \initial - attribute \src "libresoc.v:45827.9-45827.17" + attribute \src "libresoc.v:45623.9-45623.17" case 1'1 case end @@ -79185,37 +78981,37 @@ module \core sync always update \dp_INT_rabc_cr0_1$next $0\dp_INT_rabc_cr0_1$next[0:0]$2478 end - attribute \src "libresoc.v:45835.3-45844.6" - process $proc$libresoc.v:45835$2480 + attribute \src "libresoc.v:45631.3-45640.6" + process $proc$libresoc.v:45631$2480 assign { } { } assign { } { } assign $0\fus_src2_i$42[63:0]$2481 $1\fus_src2_i$42[63:0]$2482 - attribute \src "libresoc.v:45836.5-45836.29" + attribute \src "libresoc.v:45632.5-45632.29" switch \initial - attribute \src "libresoc.v:45836.9-45836.17" + attribute \src "libresoc.v:45632.9-45632.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_cr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$42[63:0]$2482 \int_src__data_o + assign $1\fus_src2_i$42[63:0]$2482 \int_src1__data_o case assign $1\fus_src2_i$42[63:0]$2482 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$42 $0\fus_src2_i$42[63:0]$2481 end - attribute \src "libresoc.v:45845.3-45853.6" - process $proc$libresoc.v:45845$2483 + attribute \src "libresoc.v:45641.3-45649.6" + process $proc$libresoc.v:45641$2483 assign { } { } assign { } { } assign $0\dp_INT_rabc_trap0_2$next[0:0]$2484 $1\dp_INT_rabc_trap0_2$next[0:0]$2485 - attribute \src "libresoc.v:45846.5-45846.29" + attribute \src "libresoc.v:45642.5-45642.29" switch \initial - attribute \src "libresoc.v:45846.9-45846.17" + attribute \src "libresoc.v:45642.9-45642.17" case 1'1 case end @@ -79231,37 +79027,37 @@ module \core sync always update \dp_INT_rabc_trap0_2$next $0\dp_INT_rabc_trap0_2$next[0:0]$2484 end - attribute \src "libresoc.v:45854.3-45863.6" - process $proc$libresoc.v:45854$2486 + attribute \src "libresoc.v:45650.3-45659.6" + process $proc$libresoc.v:45650$2486 assign { } { } assign { } { } assign $0\fus_src2_i$45[63:0]$2487 $1\fus_src2_i$45[63:0]$2488 - attribute \src "libresoc.v:45855.5-45855.29" + attribute \src "libresoc.v:45651.5-45651.29" switch \initial - attribute \src "libresoc.v:45855.9-45855.17" + attribute \src "libresoc.v:45651.9-45651.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_trap0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$45[63:0]$2488 \int_src__data_o + assign $1\fus_src2_i$45[63:0]$2488 \int_src1__data_o case assign $1\fus_src2_i$45[63:0]$2488 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$45 $0\fus_src2_i$45[63:0]$2487 end - attribute \src "libresoc.v:45864.3-45872.6" - process $proc$libresoc.v:45864$2489 + attribute \src "libresoc.v:45660.3-45668.6" + process $proc$libresoc.v:45660$2489 assign { } { } assign { } { } assign $0\dp_INT_rabc_logical0_3$next[0:0]$2490 $1\dp_INT_rabc_logical0_3$next[0:0]$2491 - attribute \src "libresoc.v:45865.5-45865.29" + attribute \src "libresoc.v:45661.5-45661.29" switch \initial - attribute \src "libresoc.v:45865.9-45865.17" + attribute \src "libresoc.v:45661.9-45661.17" case 1'1 case end @@ -79277,37 +79073,37 @@ module \core sync always update \dp_INT_rabc_logical0_3$next $0\dp_INT_rabc_logical0_3$next[0:0]$2490 end - attribute \src "libresoc.v:45873.3-45882.6" - process $proc$libresoc.v:45873$2492 + attribute \src "libresoc.v:45669.3-45678.6" + process $proc$libresoc.v:45669$2492 assign { } { } assign { } { } assign $0\fus_src2_i$48[63:0]$2493 $1\fus_src2_i$48[63:0]$2494 - attribute \src "libresoc.v:45874.5-45874.29" + attribute \src "libresoc.v:45670.5-45670.29" switch \initial - attribute \src "libresoc.v:45874.9-45874.17" + attribute \src "libresoc.v:45670.9-45670.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_logical0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$48[63:0]$2494 \int_src__data_o + assign $1\fus_src2_i$48[63:0]$2494 \int_src1__data_o case assign $1\fus_src2_i$48[63:0]$2494 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$48 $0\fus_src2_i$48[63:0]$2493 end - attribute \src "libresoc.v:45883.3-45891.6" - process $proc$libresoc.v:45883$2495 + attribute \src "libresoc.v:45679.3-45687.6" + process $proc$libresoc.v:45679$2495 assign { } { } assign { } { } assign $0\dp_INT_rabc_div0_4$next[0:0]$2496 $1\dp_INT_rabc_div0_4$next[0:0]$2497 - attribute \src "libresoc.v:45884.5-45884.29" + attribute \src "libresoc.v:45680.5-45680.29" switch \initial - attribute \src "libresoc.v:45884.9-45884.17" + attribute \src "libresoc.v:45680.9-45680.17" case 1'1 case end @@ -79323,37 +79119,37 @@ module \core sync always update \dp_INT_rabc_div0_4$next $0\dp_INT_rabc_div0_4$next[0:0]$2496 end - attribute \src "libresoc.v:45892.3-45901.6" - process $proc$libresoc.v:45892$2498 + attribute \src "libresoc.v:45688.3-45697.6" + process $proc$libresoc.v:45688$2498 assign { } { } assign { } { } assign $0\fus_src2_i$51[63:0]$2499 $1\fus_src2_i$51[63:0]$2500 - attribute \src "libresoc.v:45893.5-45893.29" + attribute \src "libresoc.v:45689.5-45689.29" switch \initial - attribute \src "libresoc.v:45893.9-45893.17" + attribute \src "libresoc.v:45689.9-45689.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_div0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$51[63:0]$2500 \int_src__data_o + assign $1\fus_src2_i$51[63:0]$2500 \int_src1__data_o case assign $1\fus_src2_i$51[63:0]$2500 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$51 $0\fus_src2_i$51[63:0]$2499 end - attribute \src "libresoc.v:45902.3-45910.6" - process $proc$libresoc.v:45902$2501 + attribute \src "libresoc.v:45698.3-45706.6" + process $proc$libresoc.v:45698$2501 assign { } { } assign { } { } assign $0\dp_INT_rabc_mul0_5$next[0:0]$2502 $1\dp_INT_rabc_mul0_5$next[0:0]$2503 - attribute \src "libresoc.v:45903.5-45903.29" + attribute \src "libresoc.v:45699.5-45699.29" switch \initial - attribute \src "libresoc.v:45903.9-45903.17" + attribute \src "libresoc.v:45699.9-45699.17" case 1'1 case end @@ -79369,37 +79165,37 @@ module \core sync always update \dp_INT_rabc_mul0_5$next $0\dp_INT_rabc_mul0_5$next[0:0]$2502 end - attribute \src "libresoc.v:45911.3-45920.6" - process $proc$libresoc.v:45911$2504 + attribute \src "libresoc.v:45707.3-45716.6" + process $proc$libresoc.v:45707$2504 assign { } { } assign { } { } assign $0\fus_src2_i$54[63:0]$2505 $1\fus_src2_i$54[63:0]$2506 - attribute \src "libresoc.v:45912.5-45912.29" + attribute \src "libresoc.v:45708.5-45708.29" switch \initial - attribute \src "libresoc.v:45912.9-45912.17" + attribute \src "libresoc.v:45708.9-45708.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_mul0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$54[63:0]$2506 \int_src__data_o + assign $1\fus_src2_i$54[63:0]$2506 \int_src1__data_o case assign $1\fus_src2_i$54[63:0]$2506 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$54 $0\fus_src2_i$54[63:0]$2505 end - attribute \src "libresoc.v:45921.3-45929.6" - process $proc$libresoc.v:45921$2507 + attribute \src "libresoc.v:45717.3-45725.6" + process $proc$libresoc.v:45717$2507 assign { } { } assign { } { } assign $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508 $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 - attribute \src "libresoc.v:45922.5-45922.29" + attribute \src "libresoc.v:45718.5-45718.29" switch \initial - attribute \src "libresoc.v:45922.9-45922.17" + attribute \src "libresoc.v:45718.9-45718.17" case 1'1 case end @@ -79415,37 +79211,37 @@ module \core sync always update \dp_INT_rabc_shiftrot0_6$next $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508 end - attribute \src "libresoc.v:45930.3-45939.6" - process $proc$libresoc.v:45930$2510 + attribute \src "libresoc.v:45726.3-45735.6" + process $proc$libresoc.v:45726$2510 assign { } { } assign { } { } assign $0\fus_src2_i$57[63:0]$2511 $1\fus_src2_i$57[63:0]$2512 - attribute \src "libresoc.v:45931.5-45931.29" + attribute \src "libresoc.v:45727.5-45727.29" switch \initial - attribute \src "libresoc.v:45931.9-45931.17" + attribute \src "libresoc.v:45727.9-45727.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_shiftrot0_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$57[63:0]$2512 \int_src__data_o + assign $1\fus_src2_i$57[63:0]$2512 \int_src1__data_o case assign $1\fus_src2_i$57[63:0]$2512 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$57 $0\fus_src2_i$57[63:0]$2511 end - attribute \src "libresoc.v:45940.3-45948.6" - process $proc$libresoc.v:45940$2513 + attribute \src "libresoc.v:45736.3-45744.6" + process $proc$libresoc.v:45736$2513 assign { } { } assign { } { } assign $0\dp_INT_rabc_ldst0_7$next[0:0]$2514 $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 - attribute \src "libresoc.v:45941.5-45941.29" + attribute \src "libresoc.v:45737.5-45737.29" switch \initial - attribute \src "libresoc.v:45941.9-45941.17" + attribute \src "libresoc.v:45737.9-45737.17" case 1'1 case end @@ -79461,37 +79257,37 @@ module \core sync always update \dp_INT_rabc_ldst0_7$next $0\dp_INT_rabc_ldst0_7$next[0:0]$2514 end - attribute \src "libresoc.v:45949.3-45958.6" - process $proc$libresoc.v:45949$2516 + attribute \src "libresoc.v:45745.3-45754.6" + process $proc$libresoc.v:45745$2516 assign { } { } assign { } { } assign $0\fus_src2_i$60[63:0]$2517 $1\fus_src2_i$60[63:0]$2518 - attribute \src "libresoc.v:45950.5-45950.29" + attribute \src "libresoc.v:45746.5-45746.29" switch \initial - attribute \src "libresoc.v:45950.9-45950.17" + attribute \src "libresoc.v:45746.9-45746.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_ldst0_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$60[63:0]$2518 \int_src__data_o + assign $1\fus_src2_i$60[63:0]$2518 \int_src1__data_o case assign $1\fus_src2_i$60[63:0]$2518 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$60 $0\fus_src2_i$60[63:0]$2517 end - attribute \src "libresoc.v:45959.3-45967.6" - process $proc$libresoc.v:45959$2519 + attribute \src "libresoc.v:45755.3-45763.6" + process $proc$libresoc.v:45755$2519 assign { } { } assign { } { } assign $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520 $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 - attribute \src "libresoc.v:45960.5-45960.29" + attribute \src "libresoc.v:45756.5-45756.29" switch \initial - attribute \src "libresoc.v:45960.9-45960.17" + attribute \src "libresoc.v:45756.9-45756.17" case 1'1 case end @@ -79507,37 +79303,37 @@ module \core sync always update \dp_INT_rabc_shiftrot0_8$next $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520 end - attribute \src "libresoc.v:45968.3-45977.6" - process $proc$libresoc.v:45968$2522 + attribute \src "libresoc.v:45764.3-45773.6" + process $proc$libresoc.v:45764$2522 assign { } { } assign { } { } assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] - attribute \src "libresoc.v:45969.5-45969.29" + attribute \src "libresoc.v:45765.5-45765.29" switch \initial - attribute \src "libresoc.v:45969.9-45969.17" + attribute \src "libresoc.v:45765.9-45765.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_shiftrot0_8 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i[63:0] \int_src__data_o + assign $1\fus_src3_i[63:0] \int_src1__data_o case assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src3_i $0\fus_src3_i[63:0] end - attribute \src "libresoc.v:45978.3-45986.6" - process $proc$libresoc.v:45978$2523 + attribute \src "libresoc.v:45774.3-45782.6" + process $proc$libresoc.v:45774$2523 assign { } { } assign { } { } assign $0\dp_INT_rabc_ldst0_9$next[0:0]$2524 $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 - attribute \src "libresoc.v:45979.5-45979.29" + attribute \src "libresoc.v:45775.5-45775.29" switch \initial - attribute \src "libresoc.v:45979.9-45979.17" + attribute \src "libresoc.v:45775.9-45775.17" case 1'1 case end @@ -79553,37 +79349,37 @@ module \core sync always update \dp_INT_rabc_ldst0_9$next $0\dp_INT_rabc_ldst0_9$next[0:0]$2524 end - attribute \src "libresoc.v:45987.3-45996.6" - process $proc$libresoc.v:45987$2526 + attribute \src "libresoc.v:45783.3-45792.6" + process $proc$libresoc.v:45783$2526 assign { } { } assign { } { } assign $0\fus_src3_i$61[63:0]$2527 $1\fus_src3_i$61[63:0]$2528 - attribute \src "libresoc.v:45988.5-45988.29" + attribute \src "libresoc.v:45784.5-45784.29" switch \initial - attribute \src "libresoc.v:45988.9-45988.17" + attribute \src "libresoc.v:45784.9-45784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_ldst0_9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$61[63:0]$2528 \int_src__data_o + assign $1\fus_src3_i$61[63:0]$2528 \int_src1__data_o case assign $1\fus_src3_i$61[63:0]$2528 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src3_i$61 $0\fus_src3_i$61[63:0]$2527 end - attribute \src "libresoc.v:45997.3-46005.6" - process $proc$libresoc.v:45997$2529 + attribute \src "libresoc.v:45793.3-45801.6" + process $proc$libresoc.v:45793$2529 assign { } { } assign { } { } assign $0\dp_INT_rabc_alu0_10$next[0:0]$2530 $1\dp_INT_rabc_alu0_10$next[0:0]$2531 - attribute \src "libresoc.v:45998.5-45998.29" + attribute \src "libresoc.v:45794.5-45794.29" switch \initial - attribute \src "libresoc.v:45998.9-45998.17" + attribute \src "libresoc.v:45794.9-45794.17" case 1'1 case end @@ -79599,37 +79395,37 @@ module \core sync always update \dp_INT_rabc_alu0_10$next $0\dp_INT_rabc_alu0_10$next[0:0]$2530 end - attribute \src "libresoc.v:46006.3-46015.6" - process $proc$libresoc.v:46006$2532 + attribute \src "libresoc.v:45802.3-45811.6" + process $proc$libresoc.v:45802$2532 assign { } { } assign { } { } assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] - attribute \src "libresoc.v:46007.5-46007.29" + attribute \src "libresoc.v:45803.5-45803.29" switch \initial - attribute \src "libresoc.v:46007.9-46007.17" + attribute \src "libresoc.v:45803.9-45803.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_alu0_10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i[63:0] \int_src__data_o + assign $1\fus_src1_i[63:0] \int_src1__data_o case assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i $0\fus_src1_i[63:0] end - attribute \src "libresoc.v:46016.3-46024.6" - process $proc$libresoc.v:46016$2533 + attribute \src "libresoc.v:45812.3-45820.6" + process $proc$libresoc.v:45812$2533 assign { } { } assign { } { } assign $0\dp_INT_rabc_cr0_11$next[0:0]$2534 $1\dp_INT_rabc_cr0_11$next[0:0]$2535 - attribute \src "libresoc.v:46017.5-46017.29" + attribute \src "libresoc.v:45813.5-45813.29" switch \initial - attribute \src "libresoc.v:46017.9-46017.17" + attribute \src "libresoc.v:45813.9-45813.17" case 1'1 case end @@ -79645,37 +79441,37 @@ module \core sync always update \dp_INT_rabc_cr0_11$next $0\dp_INT_rabc_cr0_11$next[0:0]$2534 end - attribute \src "libresoc.v:46025.3-46034.6" - process $proc$libresoc.v:46025$2536 + attribute \src "libresoc.v:45821.3-45830.6" + process $proc$libresoc.v:45821$2536 assign { } { } assign { } { } assign $0\fus_src1_i$62[63:0]$2537 $1\fus_src1_i$62[63:0]$2538 - attribute \src "libresoc.v:46026.5-46026.29" + attribute \src "libresoc.v:45822.5-45822.29" switch \initial - attribute \src "libresoc.v:46026.9-46026.17" + attribute \src "libresoc.v:45822.9-45822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_cr0_11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$62[63:0]$2538 \int_src__data_o + assign $1\fus_src1_i$62[63:0]$2538 \int_src1__data_o case assign $1\fus_src1_i$62[63:0]$2538 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$62 $0\fus_src1_i$62[63:0]$2537 end - attribute \src "libresoc.v:46035.3-46043.6" - process $proc$libresoc.v:46035$2539 + attribute \src "libresoc.v:45831.3-45839.6" + process $proc$libresoc.v:45831$2539 assign { } { } assign { } { } assign $0\dp_INT_rabc_trap0_12$next[0:0]$2540 $1\dp_INT_rabc_trap0_12$next[0:0]$2541 - attribute \src "libresoc.v:46036.5-46036.29" + attribute \src "libresoc.v:45832.5-45832.29" switch \initial - attribute \src "libresoc.v:46036.9-46036.17" + attribute \src "libresoc.v:45832.9-45832.17" case 1'1 case end @@ -79691,37 +79487,37 @@ module \core sync always update \dp_INT_rabc_trap0_12$next $0\dp_INT_rabc_trap0_12$next[0:0]$2540 end - attribute \src "libresoc.v:46044.3-46053.6" - process $proc$libresoc.v:46044$2542 + attribute \src "libresoc.v:45840.3-45849.6" + process $proc$libresoc.v:45840$2542 assign { } { } assign { } { } assign $0\fus_src1_i$63[63:0]$2543 $1\fus_src1_i$63[63:0]$2544 - attribute \src "libresoc.v:46045.5-46045.29" + attribute \src "libresoc.v:45841.5-45841.29" switch \initial - attribute \src "libresoc.v:46045.9-46045.17" + attribute \src "libresoc.v:45841.9-45841.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_trap0_12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$63[63:0]$2544 \int_src__data_o + assign $1\fus_src1_i$63[63:0]$2544 \int_src1__data_o case assign $1\fus_src1_i$63[63:0]$2544 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2543 end - attribute \src "libresoc.v:46054.3-46062.6" - process $proc$libresoc.v:46054$2545 + attribute \src "libresoc.v:45850.3-45858.6" + process $proc$libresoc.v:45850$2545 assign { } { } assign { } { } assign $0\dp_INT_rabc_logical0_13$next[0:0]$2546 $1\dp_INT_rabc_logical0_13$next[0:0]$2547 - attribute \src "libresoc.v:46055.5-46055.29" + attribute \src "libresoc.v:45851.5-45851.29" switch \initial - attribute \src "libresoc.v:46055.9-46055.17" + attribute \src "libresoc.v:45851.9-45851.17" case 1'1 case end @@ -79737,37 +79533,37 @@ module \core sync always update \dp_INT_rabc_logical0_13$next $0\dp_INT_rabc_logical0_13$next[0:0]$2546 end - attribute \src "libresoc.v:46063.3-46072.6" - process $proc$libresoc.v:46063$2548 + attribute \src "libresoc.v:45859.3-45868.6" + process $proc$libresoc.v:45859$2548 assign { } { } assign { } { } assign $0\fus_src1_i$64[63:0]$2549 $1\fus_src1_i$64[63:0]$2550 - attribute \src "libresoc.v:46064.5-46064.29" + attribute \src "libresoc.v:45860.5-45860.29" switch \initial - attribute \src "libresoc.v:46064.9-46064.17" + attribute \src "libresoc.v:45860.9-45860.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_logical0_13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$64[63:0]$2550 \int_src__data_o + assign $1\fus_src1_i$64[63:0]$2550 \int_src1__data_o case assign $1\fus_src1_i$64[63:0]$2550 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$64 $0\fus_src1_i$64[63:0]$2549 end - attribute \src "libresoc.v:46073.3-46081.6" - process $proc$libresoc.v:46073$2551 + attribute \src "libresoc.v:45869.3-45877.6" + process $proc$libresoc.v:45869$2551 assign { } { } assign { } { } assign $0\dp_INT_rabc_spr0_14$next[0:0]$2552 $1\dp_INT_rabc_spr0_14$next[0:0]$2553 - attribute \src "libresoc.v:46074.5-46074.29" + attribute \src "libresoc.v:45870.5-45870.29" switch \initial - attribute \src "libresoc.v:46074.9-46074.17" + attribute \src "libresoc.v:45870.9-45870.17" case 1'1 case end @@ -79783,37 +79579,37 @@ module \core sync always update \dp_INT_rabc_spr0_14$next $0\dp_INT_rabc_spr0_14$next[0:0]$2552 end - attribute \src "libresoc.v:46082.3-46091.6" - process $proc$libresoc.v:46082$2554 + attribute \src "libresoc.v:45878.3-45887.6" + process $proc$libresoc.v:45878$2554 assign { } { } assign { } { } assign $0\fus_src1_i$67[63:0]$2555 $1\fus_src1_i$67[63:0]$2556 - attribute \src "libresoc.v:46083.5-46083.29" + attribute \src "libresoc.v:45879.5-45879.29" switch \initial - attribute \src "libresoc.v:46083.9-46083.17" + attribute \src "libresoc.v:45879.9-45879.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_spr0_14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$67[63:0]$2556 \int_src__data_o + assign $1\fus_src1_i$67[63:0]$2556 \int_src1__data_o case assign $1\fus_src1_i$67[63:0]$2556 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$67 $0\fus_src1_i$67[63:0]$2555 end - attribute \src "libresoc.v:46092.3-46100.6" - process $proc$libresoc.v:46092$2557 + attribute \src "libresoc.v:45888.3-45896.6" + process $proc$libresoc.v:45888$2557 assign { } { } assign { } { } assign $0\dp_INT_rabc_div0_15$next[0:0]$2558 $1\dp_INT_rabc_div0_15$next[0:0]$2559 - attribute \src "libresoc.v:46093.5-46093.29" + attribute \src "libresoc.v:45889.5-45889.29" switch \initial - attribute \src "libresoc.v:46093.9-46093.17" + attribute \src "libresoc.v:45889.9-45889.17" case 1'1 case end @@ -79829,37 +79625,37 @@ module \core sync always update \dp_INT_rabc_div0_15$next $0\dp_INT_rabc_div0_15$next[0:0]$2558 end - attribute \src "libresoc.v:46101.3-46110.6" - process $proc$libresoc.v:46101$2560 + attribute \src "libresoc.v:45897.3-45906.6" + process $proc$libresoc.v:45897$2560 assign { } { } assign { } { } assign $0\fus_src1_i$68[63:0]$2561 $1\fus_src1_i$68[63:0]$2562 - attribute \src "libresoc.v:46102.5-46102.29" + attribute \src "libresoc.v:45898.5-45898.29" switch \initial - attribute \src "libresoc.v:46102.9-46102.17" + attribute \src "libresoc.v:45898.9-45898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_div0_15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$68[63:0]$2562 \int_src__data_o + assign $1\fus_src1_i$68[63:0]$2562 \int_src1__data_o case assign $1\fus_src1_i$68[63:0]$2562 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$68 $0\fus_src1_i$68[63:0]$2561 end - attribute \src "libresoc.v:46111.3-46119.6" - process $proc$libresoc.v:46111$2563 + attribute \src "libresoc.v:45907.3-45915.6" + process $proc$libresoc.v:45907$2563 assign { } { } assign { } { } assign $0\dp_INT_rabc_mul0_16$next[0:0]$2564 $1\dp_INT_rabc_mul0_16$next[0:0]$2565 - attribute \src "libresoc.v:46112.5-46112.29" + attribute \src "libresoc.v:45908.5-45908.29" switch \initial - attribute \src "libresoc.v:46112.9-46112.17" + attribute \src "libresoc.v:45908.9-45908.17" case 1'1 case end @@ -79875,37 +79671,37 @@ module \core sync always update \dp_INT_rabc_mul0_16$next $0\dp_INT_rabc_mul0_16$next[0:0]$2564 end - attribute \src "libresoc.v:46120.3-46129.6" - process $proc$libresoc.v:46120$2566 + attribute \src "libresoc.v:45916.3-45925.6" + process $proc$libresoc.v:45916$2566 assign { } { } assign { } { } assign $0\fus_src1_i$69[63:0]$2567 $1\fus_src1_i$69[63:0]$2568 - attribute \src "libresoc.v:46121.5-46121.29" + attribute \src "libresoc.v:45917.5-45917.29" switch \initial - attribute \src "libresoc.v:46121.9-46121.17" + attribute \src "libresoc.v:45917.9-45917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_mul0_16 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$69[63:0]$2568 \int_src__data_o + assign $1\fus_src1_i$69[63:0]$2568 \int_src1__data_o case assign $1\fus_src1_i$69[63:0]$2568 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$69 $0\fus_src1_i$69[63:0]$2567 end - attribute \src "libresoc.v:46130.3-46138.6" - process $proc$libresoc.v:46130$2569 + attribute \src "libresoc.v:45926.3-45934.6" + process $proc$libresoc.v:45926$2569 assign { } { } assign { } { } assign $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570 $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 - attribute \src "libresoc.v:46131.5-46131.29" + attribute \src "libresoc.v:45927.5-45927.29" switch \initial - attribute \src "libresoc.v:46131.9-46131.17" + attribute \src "libresoc.v:45927.9-45927.17" case 1'1 case end @@ -79921,37 +79717,37 @@ module \core sync always update \dp_INT_rabc_shiftrot0_17$next $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570 end - attribute \src "libresoc.v:46139.3-46148.6" - process $proc$libresoc.v:46139$2572 + attribute \src "libresoc.v:45935.3-45944.6" + process $proc$libresoc.v:45935$2572 assign { } { } assign { } { } assign $0\fus_src1_i$70[63:0]$2573 $1\fus_src1_i$70[63:0]$2574 - attribute \src "libresoc.v:46140.5-46140.29" + attribute \src "libresoc.v:45936.5-45936.29" switch \initial - attribute \src "libresoc.v:46140.9-46140.17" + attribute \src "libresoc.v:45936.9-45936.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_shiftrot0_17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$70[63:0]$2574 \int_src__data_o + assign $1\fus_src1_i$70[63:0]$2574 \int_src1__data_o case assign $1\fus_src1_i$70[63:0]$2574 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$70 $0\fus_src1_i$70[63:0]$2573 end - attribute \src "libresoc.v:46149.3-46157.6" - process $proc$libresoc.v:46149$2575 + attribute \src "libresoc.v:45945.3-45953.6" + process $proc$libresoc.v:45945$2575 assign { } { } assign { } { } assign $0\dp_INT_rabc_ldst0_18$next[0:0]$2576 $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 - attribute \src "libresoc.v:46150.5-46150.29" + attribute \src "libresoc.v:45946.5-45946.29" switch \initial - attribute \src "libresoc.v:46150.9-46150.17" + attribute \src "libresoc.v:45946.9-45946.17" case 1'1 case end @@ -79967,37 +79763,37 @@ module \core sync always update \dp_INT_rabc_ldst0_18$next $0\dp_INT_rabc_ldst0_18$next[0:0]$2576 end - attribute \src "libresoc.v:46158.3-46167.6" - process $proc$libresoc.v:46158$2578 + attribute \src "libresoc.v:45954.3-45963.6" + process $proc$libresoc.v:45954$2578 assign { } { } assign { } { } assign $0\fus_src1_i$71[63:0]$2579 $1\fus_src1_i$71[63:0]$2580 - attribute \src "libresoc.v:46159.5-46159.29" + attribute \src "libresoc.v:45955.5-45955.29" switch \initial - attribute \src "libresoc.v:46159.9-46159.17" + attribute \src "libresoc.v:45955.9-45955.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_ldst0_18 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$71[63:0]$2580 \int_src__data_o + assign $1\fus_src1_i$71[63:0]$2580 \int_src1__data_o case assign $1\fus_src1_i$71[63:0]$2580 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$71 $0\fus_src1_i$71[63:0]$2579 end - attribute \src "libresoc.v:46168.3-46176.6" - process $proc$libresoc.v:46168$2581 + attribute \src "libresoc.v:45964.3-45972.6" + process $proc$libresoc.v:45964$2581 assign { } { } assign { } { } assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 - attribute \src "libresoc.v:46169.5-46169.29" + attribute \src "libresoc.v:45965.5-45965.29" switch \initial - attribute \src "libresoc.v:46169.9-46169.17" + attribute \src "libresoc.v:45965.9-45965.17" case 1'1 case end @@ -80013,18 +79809,18 @@ module \core sync always update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 end - attribute \src "libresoc.v:46177.3-46186.6" - process $proc$libresoc.v:46177$2584 + attribute \src "libresoc.v:45973.3-45982.6" + process $proc$libresoc.v:45973$2584 assign { } { } assign { } { } assign $0\fus_src3_i$72[0:0]$2585 $1\fus_src3_i$72[0:0]$2586 - attribute \src "libresoc.v:46178.5-46178.29" + attribute \src "libresoc.v:45974.5-45974.29" switch \initial - attribute \src "libresoc.v:46178.9-46178.17" + attribute \src "libresoc.v:45974.9-45974.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80036,14 +79832,14 @@ module \core sync always update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2585 end - attribute \src "libresoc.v:46187.3-46195.6" - process $proc$libresoc.v:46187$2587 + attribute \src "libresoc.v:45983.3-45991.6" + process $proc$libresoc.v:45983$2587 assign { } { } assign { } { } assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 - attribute \src "libresoc.v:46188.5-46188.29" + attribute \src "libresoc.v:45984.5-45984.29" switch \initial - attribute \src "libresoc.v:46188.9-46188.17" + attribute \src "libresoc.v:45984.9-45984.17" case 1'1 case end @@ -80059,18 +79855,18 @@ module \core sync always update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 end - attribute \src "libresoc.v:46196.3-46205.6" - process $proc$libresoc.v:46196$2590 + attribute \src "libresoc.v:45992.3-46001.6" + process $proc$libresoc.v:45992$2590 assign { } { } assign { } { } assign $0\fus_src3_i$73[0:0]$2591 $1\fus_src3_i$73[0:0]$2592 - attribute \src "libresoc.v:46197.5-46197.29" + attribute \src "libresoc.v:45993.5-45993.29" switch \initial - attribute \src "libresoc.v:46197.9-46197.17" + attribute \src "libresoc.v:45993.9-45993.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_logical0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80082,14 +79878,14 @@ module \core sync always update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2591 end - attribute \src "libresoc.v:46206.3-46214.6" - process $proc$libresoc.v:46206$2593 + attribute \src "libresoc.v:46002.3-46010.6" + process $proc$libresoc.v:46002$2593 assign { } { } assign { } { } assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 - attribute \src "libresoc.v:46207.5-46207.29" + attribute \src "libresoc.v:46003.5-46003.29" switch \initial - attribute \src "libresoc.v:46207.9-46207.17" + attribute \src "libresoc.v:46003.9-46003.17" case 1'1 case end @@ -80105,18 +79901,18 @@ module \core sync always update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 end - attribute \src "libresoc.v:46215.3-46224.6" - process $proc$libresoc.v:46215$2596 + attribute \src "libresoc.v:46011.3-46020.6" + process $proc$libresoc.v:46011$2596 assign { } { } assign { } { } assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] - attribute \src "libresoc.v:46216.5-46216.29" + attribute \src "libresoc.v:46012.5-46012.29" switch \initial - attribute \src "libresoc.v:46216.9-46216.17" + attribute \src "libresoc.v:46012.9-46012.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80128,14 +79924,14 @@ module \core sync always update \fus_src4_i $0\fus_src4_i[0:0] end - attribute \src "libresoc.v:46225.3-46233.6" - process $proc$libresoc.v:46225$2597 + attribute \src "libresoc.v:46021.3-46029.6" + process $proc$libresoc.v:46021$2597 assign { } { } assign { } { } assign $0\dp_XER_xer_so_div0_3$next[0:0]$2598 $1\dp_XER_xer_so_div0_3$next[0:0]$2599 - attribute \src "libresoc.v:46226.5-46226.29" + attribute \src "libresoc.v:46022.5-46022.29" switch \initial - attribute \src "libresoc.v:46226.9-46226.17" + attribute \src "libresoc.v:46022.9-46022.17" case 1'1 case end @@ -80151,18 +79947,18 @@ module \core sync always update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2598 end - attribute \src "libresoc.v:46234.3-46243.6" - process $proc$libresoc.v:46234$2600 + attribute \src "libresoc.v:46030.3-46039.6" + process $proc$libresoc.v:46030$2600 assign { } { } assign { } { } assign $0\fus_src3_i$74[0:0]$2601 $1\fus_src3_i$74[0:0]$2602 - attribute \src "libresoc.v:46235.5-46235.29" + attribute \src "libresoc.v:46031.5-46031.29" switch \initial - attribute \src "libresoc.v:46235.9-46235.17" + attribute \src "libresoc.v:46031.9-46031.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_div0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80174,14 +79970,14 @@ module \core sync always update \fus_src3_i$74 $0\fus_src3_i$74[0:0]$2601 end - attribute \src "libresoc.v:46244.3-46252.6" - process $proc$libresoc.v:46244$2603 + attribute \src "libresoc.v:46040.3-46048.6" + process $proc$libresoc.v:46040$2603 assign { } { } assign { } { } assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 - attribute \src "libresoc.v:46245.5-46245.29" + attribute \src "libresoc.v:46041.5-46041.29" switch \initial - attribute \src "libresoc.v:46245.9-46245.17" + attribute \src "libresoc.v:46041.9-46041.17" case 1'1 case end @@ -80197,18 +79993,18 @@ module \core sync always update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 end - attribute \src "libresoc.v:46253.3-46262.6" - process $proc$libresoc.v:46253$2606 + attribute \src "libresoc.v:46049.3-46058.6" + process $proc$libresoc.v:46049$2606 assign { } { } assign { } { } assign $0\fus_src3_i$75[0:0]$2607 $1\fus_src3_i$75[0:0]$2608 - attribute \src "libresoc.v:46254.5-46254.29" + attribute \src "libresoc.v:46050.5-46050.29" switch \initial - attribute \src "libresoc.v:46254.9-46254.17" + attribute \src "libresoc.v:46050.9-46050.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_mul0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80220,14 +80016,14 @@ module \core sync always update \fus_src3_i$75 $0\fus_src3_i$75[0:0]$2607 end - attribute \src "libresoc.v:46263.3-46271.6" - process $proc$libresoc.v:46263$2609 + attribute \src "libresoc.v:46059.3-46067.6" + process $proc$libresoc.v:46059$2609 assign { } { } assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 - attribute \src "libresoc.v:46264.5-46264.29" + attribute \src "libresoc.v:46060.5-46060.29" switch \initial - attribute \src "libresoc.v:46264.9-46264.17" + attribute \src "libresoc.v:46060.9-46060.17" case 1'1 case end @@ -80243,18 +80039,18 @@ module \core sync always update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 end - attribute \src "libresoc.v:46272.3-46281.6" - process $proc$libresoc.v:46272$2612 + attribute \src "libresoc.v:46068.3-46077.6" + process $proc$libresoc.v:46068$2612 assign { } { } assign { } { } assign $0\fus_src4_i$76[0:0]$2613 $1\fus_src4_i$76[0:0]$2614 - attribute \src "libresoc.v:46273.5-46273.29" + attribute \src "libresoc.v:46069.5-46069.29" switch \initial - attribute \src "libresoc.v:46273.9-46273.17" + attribute \src "libresoc.v:46069.9-46069.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_shiftrot0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80266,14 +80062,14 @@ module \core sync always update \fus_src4_i$76 $0\fus_src4_i$76[0:0]$2613 end - attribute \src "libresoc.v:46282.3-46290.6" - process $proc$libresoc.v:46282$2615 + attribute \src "libresoc.v:46078.3-46086.6" + process $proc$libresoc.v:46078$2615 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 - attribute \src "libresoc.v:46283.5-46283.29" + attribute \src "libresoc.v:46079.5-46079.29" switch \initial - attribute \src "libresoc.v:46283.9-46283.17" + attribute \src "libresoc.v:46079.9-46079.17" case 1'1 case end @@ -80289,18 +80085,18 @@ module \core sync always update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 end - attribute \src "libresoc.v:46291.3-46300.6" - process $proc$libresoc.v:46291$2618 + attribute \src "libresoc.v:46087.3-46096.6" + process $proc$libresoc.v:46087$2618 assign { } { } assign { } { } assign $0\fus_src4_i$77[1:0]$2619 $1\fus_src4_i$77[1:0]$2620 - attribute \src "libresoc.v:46292.5-46292.29" + attribute \src "libresoc.v:46088.5-46088.29" switch \initial - attribute \src "libresoc.v:46292.9-46292.17" + attribute \src "libresoc.v:46088.9-46088.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ca_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80312,14 +80108,14 @@ module \core sync always update \fus_src4_i$77 $0\fus_src4_i$77[1:0]$2619 end - attribute \src "libresoc.v:46301.3-46309.6" - process $proc$libresoc.v:46301$2621 + attribute \src "libresoc.v:46097.3-46105.6" + process $proc$libresoc.v:46097$2621 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 - attribute \src "libresoc.v:46302.5-46302.29" + attribute \src "libresoc.v:46098.5-46098.29" switch \initial - attribute \src "libresoc.v:46302.9-46302.17" + attribute \src "libresoc.v:46098.9-46098.17" case 1'1 case end @@ -80335,18 +80131,18 @@ module \core sync always update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 end - attribute \src "libresoc.v:46310.3-46319.6" - process $proc$libresoc.v:46310$2624 + attribute \src "libresoc.v:46106.3-46115.6" + process $proc$libresoc.v:46106$2624 assign { } { } assign { } { } assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] - attribute \src "libresoc.v:46311.5-46311.29" + attribute \src "libresoc.v:46107.5-46107.29" switch \initial - attribute \src "libresoc.v:46311.9-46311.17" + attribute \src "libresoc.v:46107.9-46107.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ca_spr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80358,14 +80154,14 @@ module \core sync always update \fus_src6_i $0\fus_src6_i[1:0] end - attribute \src "libresoc.v:46320.3-46328.6" - process $proc$libresoc.v:46320$2625 + attribute \src "libresoc.v:46116.3-46124.6" + process $proc$libresoc.v:46116$2625 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 - attribute \src "libresoc.v:46321.5-46321.29" + attribute \src "libresoc.v:46117.5-46117.29" switch \initial - attribute \src "libresoc.v:46321.9-46321.17" + attribute \src "libresoc.v:46117.9-46117.17" case 1'1 case end @@ -80381,18 +80177,18 @@ module \core sync always update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 end - attribute \src "libresoc.v:46329.3-46338.6" - process $proc$libresoc.v:46329$2628 + attribute \src "libresoc.v:46125.3-46134.6" + process $proc$libresoc.v:46125$2628 assign { } { } assign { } { } assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] - attribute \src "libresoc.v:46330.5-46330.29" + attribute \src "libresoc.v:46126.5-46126.29" switch \initial - attribute \src "libresoc.v:46330.9-46330.17" + attribute \src "libresoc.v:46126.9-46126.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ca_shiftrot0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80404,14 +80200,14 @@ module \core sync always update \fus_src5_i $0\fus_src5_i[1:0] end - attribute \src "libresoc.v:46339.3-46347.6" - process $proc$libresoc.v:46339$2629 + attribute \src "libresoc.v:46135.3-46143.6" + process $proc$libresoc.v:46135$2629 assign { } { } assign { } { } assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 - attribute \src "libresoc.v:46340.5-46340.29" + attribute \src "libresoc.v:46136.5-46136.29" switch \initial - attribute \src "libresoc.v:46340.9-46340.17" + attribute \src "libresoc.v:46136.9-46136.17" case 1'1 case end @@ -80427,18 +80223,18 @@ module \core sync always update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 end - attribute \src "libresoc.v:46348.3-46357.6" - process $proc$libresoc.v:46348$2632 + attribute \src "libresoc.v:46144.3-46153.6" + process $proc$libresoc.v:46144$2632 assign { } { } assign { } { } assign $0\fus_src5_i$78[1:0]$2633 $1\fus_src5_i$78[1:0]$2634 - attribute \src "libresoc.v:46349.5-46349.29" + attribute \src "libresoc.v:46145.5-46145.29" switch \initial - attribute \src "libresoc.v:46349.9-46349.17" + attribute \src "libresoc.v:46145.9-46145.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ov_spr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80450,14 +80246,14 @@ module \core sync always update \fus_src5_i$78 $0\fus_src5_i$78[1:0]$2633 end - attribute \src "libresoc.v:46358.3-46366.6" - process $proc$libresoc.v:46358$2635 + attribute \src "libresoc.v:46154.3-46162.6" + process $proc$libresoc.v:46154$2635 assign { } { } assign { } { } assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 - attribute \src "libresoc.v:46359.5-46359.29" + attribute \src "libresoc.v:46155.5-46155.29" switch \initial - attribute \src "libresoc.v:46359.9-46359.17" + attribute \src "libresoc.v:46155.9-46155.17" case 1'1 case end @@ -80473,18 +80269,18 @@ module \core sync always update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 end - attribute \src "libresoc.v:46367.3-46376.6" - process $proc$libresoc.v:46367$2638 + attribute \src "libresoc.v:46163.3-46172.6" + process $proc$libresoc.v:46163$2638 assign { } { } assign { } { } assign $0\fus_src3_i$79[31:0]$2639 $1\fus_src3_i$79[31:0]$2640 - attribute \src "libresoc.v:46368.5-46368.29" + attribute \src "libresoc.v:46164.5-46164.29" switch \initial - attribute \src "libresoc.v:46368.9-46368.17" + attribute \src "libresoc.v:46164.9-46164.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_full_cr_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80496,14 +80292,14 @@ module \core sync always update \fus_src3_i$79 $0\fus_src3_i$79[31:0]$2639 end - attribute \src "libresoc.v:46377.3-46385.6" - process $proc$libresoc.v:46377$2641 + attribute \src "libresoc.v:46173.3-46181.6" + process $proc$libresoc.v:46173$2641 assign { } { } assign { } { } assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 - attribute \src "libresoc.v:46378.5-46378.29" + attribute \src "libresoc.v:46174.5-46174.29" switch \initial - attribute \src "libresoc.v:46378.9-46378.17" + attribute \src "libresoc.v:46174.9-46174.17" case 1'1 case end @@ -80519,18 +80315,18 @@ module \core sync always update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 end - attribute \src "libresoc.v:46386.3-46395.6" - process $proc$libresoc.v:46386$2644 + attribute \src "libresoc.v:46182.3-46191.6" + process $proc$libresoc.v:46182$2644 assign { } { } assign { } { } assign $0\fus_src4_i$80[3:0]$2645 $1\fus_src4_i$80[3:0]$2646 - attribute \src "libresoc.v:46387.5-46387.29" + attribute \src "libresoc.v:46183.5-46183.29" switch \initial - attribute \src "libresoc.v:46387.9-46387.17" + attribute \src "libresoc.v:46183.9-46183.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_cr_a_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80542,14 +80338,14 @@ module \core sync always update \fus_src4_i$80 $0\fus_src4_i$80[3:0]$2645 end - attribute \src "libresoc.v:46396.3-46404.6" - process $proc$libresoc.v:46396$2647 + attribute \src "libresoc.v:46192.3-46200.6" + process $proc$libresoc.v:46192$2647 assign { } { } assign { } { } assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 - attribute \src "libresoc.v:46397.5-46397.29" + attribute \src "libresoc.v:46193.5-46193.29" switch \initial - attribute \src "libresoc.v:46397.9-46397.17" + attribute \src "libresoc.v:46193.9-46193.17" case 1'1 case end @@ -80565,18 +80361,18 @@ module \core sync always update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 end - attribute \src "libresoc.v:46405.3-46414.6" - process $proc$libresoc.v:46405$2650 + attribute \src "libresoc.v:46201.3-46210.6" + process $proc$libresoc.v:46201$2650 assign { } { } assign { } { } assign $0\fus_src3_i$83[3:0]$2651 $1\fus_src3_i$83[3:0]$2652 - attribute \src "libresoc.v:46406.5-46406.29" + attribute \src "libresoc.v:46202.5-46202.29" switch \initial - attribute \src "libresoc.v:46406.9-46406.17" + attribute \src "libresoc.v:46202.9-46202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_cr_a_branch0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80588,14 +80384,14 @@ module \core sync always update \fus_src3_i$83 $0\fus_src3_i$83[3:0]$2651 end - attribute \src "libresoc.v:46415.3-46423.6" - process $proc$libresoc.v:46415$2653 + attribute \src "libresoc.v:46211.3-46219.6" + process $proc$libresoc.v:46211$2653 assign { } { } assign { } { } assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2654 $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 - attribute \src "libresoc.v:46416.5-46416.29" + attribute \src "libresoc.v:46212.5-46212.29" switch \initial - attribute \src "libresoc.v:46416.9-46416.17" + attribute \src "libresoc.v:46212.9-46212.17" case 1'1 case end @@ -80611,20 +80407,20 @@ module \core sync always update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2654 end - attribute \src "libresoc.v:46424.3-46454.6" - process $proc$libresoc.v:46424$2656 + attribute \src "libresoc.v:46220.3-46250.6" + process $proc$libresoc.v:46220$2656 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\counter$next[1:0]$2657 $4\counter$next[1:0]$2661 - attribute \src "libresoc.v:46425.5-46425.29" + attribute \src "libresoc.v:46221.5-46221.29" switch \initial - attribute \src "libresoc.v:46425.9-46425.17" + attribute \src "libresoc.v:46221.9-46221.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch \$221 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80633,13 +80429,13 @@ module \core case assign $1\counter$next[1:0]$2658 \counter end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\counter$next[1:0]$2659 $3\counter$next[1:0]$2660 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80666,18 +80462,18 @@ module \core sync always update \counter$next $0\counter$next[1:0]$2657 end - attribute \src "libresoc.v:46455.3-46464.6" - process $proc$libresoc.v:46455$2662 + attribute \src "libresoc.v:46251.3-46260.6" + process $proc$libresoc.v:46251$2662 assign { } { } assign { } { } assign $0\fus_src5_i$84[3:0]$2663 $1\fus_src5_i$84[3:0]$2664 - attribute \src "libresoc.v:46456.5-46456.29" + attribute \src "libresoc.v:46252.5-46252.29" switch \initial - attribute \src "libresoc.v:46456.9-46456.17" + attribute \src "libresoc.v:46252.9-46252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_cr_b_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80689,14 +80485,14 @@ module \core sync always update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2663 end - attribute \src "libresoc.v:46465.3-46473.6" - process $proc$libresoc.v:46465$2665 + attribute \src "libresoc.v:46261.3-46269.6" + process $proc$libresoc.v:46261$2665 assign { } { } assign { } { } assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 - attribute \src "libresoc.v:46466.5-46466.29" + attribute \src "libresoc.v:46262.5-46262.29" switch \initial - attribute \src "libresoc.v:46466.9-46466.17" + attribute \src "libresoc.v:46262.9-46262.17" case 1'1 case end @@ -80712,18 +80508,18 @@ module \core sync always update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 end - attribute \src "libresoc.v:46474.3-46483.6" - process $proc$libresoc.v:46474$2668 + attribute \src "libresoc.v:46270.3-46279.6" + process $proc$libresoc.v:46270$2668 assign { } { } assign { } { } assign $0\fus_src6_i$85[3:0]$2669 $1\fus_src6_i$85[3:0]$2670 - attribute \src "libresoc.v:46475.5-46475.29" + attribute \src "libresoc.v:46271.5-46271.29" switch \initial - attribute \src "libresoc.v:46475.9-46475.17" + attribute \src "libresoc.v:46271.9-46271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_cr_c_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80735,19 +80531,19 @@ module \core sync always update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2669 end - attribute \src "libresoc.v:46484.3-46574.6" - process $proc$libresoc.v:46484$2671 + attribute \src "libresoc.v:46280.3-46370.6" + process $proc$libresoc.v:46280$2671 assign { } { } assign { } { } assign { } { } assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] - attribute \src "libresoc.v:46485.5-46485.29" + attribute \src "libresoc.v:46281.5-46281.29" switch \initial - attribute \src "libresoc.v:46485.9-46485.17" + attribute \src "libresoc.v:46281.9-46281.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch \$226 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80756,13 +80552,13 @@ module \core case assign $1\corebusy_o[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80784,7 +80580,7 @@ module \core assign { } { } assign { } { } assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80793,7 +80589,7 @@ module \core case assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80802,7 +80598,7 @@ module \core case assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80811,7 +80607,7 @@ module \core case assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80820,7 +80616,7 @@ module \core case assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80829,7 +80625,7 @@ module \core case assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80838,7 +80634,7 @@ module \core case assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80847,7 +80643,7 @@ module \core case assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80856,7 +80652,7 @@ module \core case assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80865,7 +80661,7 @@ module \core case assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80881,14 +80677,14 @@ module \core sync always update \corebusy_o $0\corebusy_o[0:0] end - attribute \src "libresoc.v:46575.3-46583.6" - process $proc$libresoc.v:46575$2672 + attribute \src "libresoc.v:46371.3-46379.6" + process $proc$libresoc.v:46371$2672 assign { } { } assign { } { } assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2673 $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 - attribute \src "libresoc.v:46576.5-46576.29" + attribute \src "libresoc.v:46372.5-46372.29" switch \initial - attribute \src "libresoc.v:46576.9-46576.17" + attribute \src "libresoc.v:46372.9-46372.17" case 1'1 case end @@ -80904,18 +80700,18 @@ module \core sync always update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2673 end - attribute \src "libresoc.v:46584.3-46593.6" - process $proc$libresoc.v:46584$2675 + attribute \src "libresoc.v:46380.3-46389.6" + process $proc$libresoc.v:46380$2675 assign { } { } assign { } { } assign $0\fus_src1_i$86[63:0]$2676 $1\fus_src1_i$86[63:0]$2677 - attribute \src "libresoc.v:46585.5-46585.29" + attribute \src "libresoc.v:46381.5-46381.29" switch \initial - attribute \src "libresoc.v:46585.9-46585.17" + attribute \src "libresoc.v:46381.9-46381.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_FAST_fast1_branch0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80927,25 +80723,25 @@ module \core sync always update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2676 end - attribute \src "libresoc.v:46594.3-46614.6" - process $proc$libresoc.v:46594$2678 + attribute \src "libresoc.v:46390.3-46410.6" + process $proc$libresoc.v:46390$2678 assign { } { } assign { } { } assign { } { } assign $0\core_terminate_o$next[0:0]$2679 $3\core_terminate_o$next[0:0]$2682 - attribute \src "libresoc.v:46595.5-46595.29" + attribute \src "libresoc.v:46391.5-46391.29" switch \initial - attribute \src "libresoc.v:46595.9-46595.17" + attribute \src "libresoc.v:46391.9-46391.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\core_terminate_o$next[0:0]$2680 $2\core_terminate_o$next[0:0]$2681 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80969,14 +80765,14 @@ module \core sync always update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2679 end - attribute \src "libresoc.v:46615.3-46623.6" - process $proc$libresoc.v:46615$2683 + attribute \src "libresoc.v:46411.3-46419.6" + process $proc$libresoc.v:46411$2683 assign { } { } assign { } { } assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 - attribute \src "libresoc.v:46616.5-46616.29" + attribute \src "libresoc.v:46412.5-46412.29" switch \initial - attribute \src "libresoc.v:46616.9-46616.17" + attribute \src "libresoc.v:46412.9-46412.17" case 1'1 case end @@ -80992,18 +80788,18 @@ module \core sync always update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 end - attribute \src "libresoc.v:46624.3-46633.6" - process $proc$libresoc.v:46624$2686 + attribute \src "libresoc.v:46420.3-46429.6" + process $proc$libresoc.v:46420$2686 assign { } { } assign { } { } assign $0\fus_src3_i$87[63:0]$2687 $1\fus_src3_i$87[63:0]$2688 - attribute \src "libresoc.v:46625.5-46625.29" + attribute \src "libresoc.v:46421.5-46421.29" switch \initial - attribute \src "libresoc.v:46625.9-46625.17" + attribute \src "libresoc.v:46421.9-46421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_FAST_fast1_trap0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81015,14 +80811,14 @@ module \core sync always update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2687 end - attribute \src "libresoc.v:46634.3-46642.6" - process $proc$libresoc.v:46634$2689 + attribute \src "libresoc.v:46430.3-46438.6" + process $proc$libresoc.v:46430$2689 assign { } { } assign { } { } assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2690 $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 - attribute \src "libresoc.v:46635.5-46635.29" + attribute \src "libresoc.v:46431.5-46431.29" switch \initial - attribute \src "libresoc.v:46635.9-46635.17" + attribute \src "libresoc.v:46431.9-46431.17" case 1'1 case end @@ -81038,18 +80834,18 @@ module \core sync always update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2690 end - attribute \src "libresoc.v:46643.3-46652.6" - process $proc$libresoc.v:46643$2692 + attribute \src "libresoc.v:46439.3-46448.6" + process $proc$libresoc.v:46439$2692 assign { } { } assign { } { } assign $0\fus_src3_i$88[63:0]$2693 $1\fus_src3_i$88[63:0]$2694 - attribute \src "libresoc.v:46644.5-46644.29" + attribute \src "libresoc.v:46440.5-46440.29" switch \initial - attribute \src "libresoc.v:46644.9-46644.17" + attribute \src "libresoc.v:46440.9-46440.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_FAST_fast1_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81061,24 +80857,24 @@ module \core sync always update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2693 end - attribute \src "libresoc.v:46653.3-46681.6" - process $proc$libresoc.v:46653$2695 + attribute \src "libresoc.v:46449.3-46477.6" + process $proc$libresoc.v:46449$2695 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46654.5-46654.29" + attribute \src "libresoc.v:46450.5-46450.29" switch \initial - attribute \src "libresoc.v:46654.9-46654.17" + attribute \src "libresoc.v:46450.9-46450.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81090,7 +80886,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81106,14 +80902,14 @@ module \core sync always update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] end - attribute \src "libresoc.v:46682.3-46690.6" - process $proc$libresoc.v:46682$2696 + attribute \src "libresoc.v:46478.3-46486.6" + process $proc$libresoc.v:46478$2696 assign { } { } assign { } { } assign $0\dp_FAST_fast1_branch0_3$next[0:0]$2697 $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 - attribute \src "libresoc.v:46683.5-46683.29" + attribute \src "libresoc.v:46479.5-46479.29" switch \initial - attribute \src "libresoc.v:46683.9-46683.17" + attribute \src "libresoc.v:46479.9-46479.17" case 1'1 case end @@ -81129,18 +80925,18 @@ module \core sync always update \dp_FAST_fast1_branch0_3$next $0\dp_FAST_fast1_branch0_3$next[0:0]$2697 end - attribute \src "libresoc.v:46691.3-46700.6" - process $proc$libresoc.v:46691$2699 + attribute \src "libresoc.v:46487.3-46496.6" + process $proc$libresoc.v:46487$2699 assign { } { } assign { } { } assign $0\fus_src2_i$89[63:0]$2700 $1\fus_src2_i$89[63:0]$2701 - attribute \src "libresoc.v:46692.5-46692.29" + attribute \src "libresoc.v:46488.5-46488.29" switch \initial - attribute \src "libresoc.v:46692.9-46692.17" + attribute \src "libresoc.v:46488.9-46488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_FAST_fast1_branch0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81152,14 +80948,14 @@ module \core sync always update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2700 end - attribute \src "libresoc.v:46701.3-46709.6" - process $proc$libresoc.v:46701$2702 + attribute \src "libresoc.v:46497.3-46505.6" + process $proc$libresoc.v:46497$2702 assign { } { } assign { } { } assign $0\dp_FAST_fast1_trap0_4$next[0:0]$2703 $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 - attribute \src "libresoc.v:46702.5-46702.29" + attribute \src "libresoc.v:46498.5-46498.29" switch \initial - attribute \src "libresoc.v:46702.9-46702.17" + attribute \src "libresoc.v:46498.9-46498.17" case 1'1 case end @@ -81175,18 +80971,18 @@ module \core sync always update \dp_FAST_fast1_trap0_4$next $0\dp_FAST_fast1_trap0_4$next[0:0]$2703 end - attribute \src "libresoc.v:46710.3-46719.6" - process $proc$libresoc.v:46710$2705 + attribute \src "libresoc.v:46506.3-46515.6" + process $proc$libresoc.v:46506$2705 assign { } { } assign { } { } assign $0\fus_src4_i$90[63:0]$2706 $1\fus_src4_i$90[63:0]$2707 - attribute \src "libresoc.v:46711.5-46711.29" + attribute \src "libresoc.v:46507.5-46507.29" switch \initial - attribute \src "libresoc.v:46711.9-46711.17" + attribute \src "libresoc.v:46507.9-46507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_FAST_fast1_trap0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81198,24 +80994,24 @@ module \core sync always update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2706 end - attribute \src "libresoc.v:46720.3-46748.6" - process $proc$libresoc.v:46720$2708 + attribute \src "libresoc.v:46516.3-46544.6" + process $proc$libresoc.v:46516$2708 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__fn_unit[13:0] $1\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46721.5-46721.29" + attribute \src "libresoc.v:46517.5-46517.29" switch \initial - attribute \src "libresoc.v:46721.9-46721.17" + attribute \src "libresoc.v:46517.9-46517.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] $2\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81227,7 +81023,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] $3\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81243,14 +81039,14 @@ module \core sync always update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[13:0] end - attribute \src "libresoc.v:46749.3-46757.6" - process $proc$libresoc.v:46749$2709 + attribute \src "libresoc.v:46545.3-46553.6" + process $proc$libresoc.v:46545$2709 assign { } { } assign { } { } assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2710 $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 - attribute \src "libresoc.v:46750.5-46750.29" + attribute \src "libresoc.v:46546.5-46546.29" switch \initial - attribute \src "libresoc.v:46750.9-46750.17" + attribute \src "libresoc.v:46546.9-46546.17" case 1'1 case end @@ -81266,18 +81062,18 @@ module \core sync always update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2710 end - attribute \src "libresoc.v:46758.3-46767.6" - process $proc$libresoc.v:46758$2712 + attribute \src "libresoc.v:46554.3-46563.6" + process $proc$libresoc.v:46554$2712 assign { } { } assign { } { } assign $0\fus_src2_i$91[63:0]$2713 $1\fus_src2_i$91[63:0]$2714 - attribute \src "libresoc.v:46759.5-46759.29" + attribute \src "libresoc.v:46555.5-46555.29" switch \initial - attribute \src "libresoc.v:46759.9-46759.17" + attribute \src "libresoc.v:46555.9-46555.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_SPR_spr1_spr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81289,21 +81085,21 @@ module \core sync always update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2713 end - attribute \src "libresoc.v:46768.3-46797.6" - process $proc$libresoc.v:46768$2715 + attribute \src "libresoc.v:46564.3-46593.6" + process $proc$libresoc.v:46564$2715 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46769.5-46769.29" + attribute \src "libresoc.v:46565.5-46565.29" switch \initial - attribute \src "libresoc.v:46769.9-46769.17" + attribute \src "libresoc.v:46565.9-46565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81311,7 +81107,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81327,7 +81123,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81347,14 +81143,14 @@ module \core update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] end - attribute \src "libresoc.v:46798.3-46806.6" - process $proc$libresoc.v:46798$2716 + attribute \src "libresoc.v:46594.3-46602.6" + process $proc$libresoc.v:46594$2716 assign { } { } assign { } { } assign $0\wr_pick_dly$next[0:0]$2717 $1\wr_pick_dly$next[0:0]$2718 - attribute \src "libresoc.v:46799.5-46799.29" + attribute \src "libresoc.v:46595.5-46595.29" switch \initial - attribute \src "libresoc.v:46799.9-46799.17" + attribute \src "libresoc.v:46595.9-46595.17" case 1'1 case end @@ -81370,14 +81166,14 @@ module \core sync always update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2717 end - attribute \src "libresoc.v:46807.3-46815.6" - process $proc$libresoc.v:46807$2719 + attribute \src "libresoc.v:46603.3-46611.6" + process $proc$libresoc.v:46603$2719 assign { } { } assign { } { } assign $0\wr_pick_dly$989$next[0:0]$2720 $1\wr_pick_dly$989$next[0:0]$2721 - attribute \src "libresoc.v:46808.5-46808.29" + attribute \src "libresoc.v:46604.5-46604.29" switch \initial - attribute \src "libresoc.v:46808.9-46808.17" + attribute \src "libresoc.v:46604.9-46604.17" case 1'1 case end @@ -81393,14 +81189,14 @@ module \core sync always update \wr_pick_dly$989$next $0\wr_pick_dly$989$next[0:0]$2720 end - attribute \src "libresoc.v:46816.3-46824.6" - process $proc$libresoc.v:46816$2722 + attribute \src "libresoc.v:46612.3-46620.6" + process $proc$libresoc.v:46612$2722 assign { } { } assign { } { } assign $0\wr_pick_dly$1008$next[0:0]$2723 $1\wr_pick_dly$1008$next[0:0]$2724 - attribute \src "libresoc.v:46817.5-46817.29" + attribute \src "libresoc.v:46613.5-46613.29" switch \initial - attribute \src "libresoc.v:46817.9-46817.17" + attribute \src "libresoc.v:46613.9-46613.17" case 1'1 case end @@ -81416,21 +81212,21 @@ module \core sync always update \wr_pick_dly$1008$next $0\wr_pick_dly$1008$next[0:0]$2723 end - attribute \src "libresoc.v:46825.3-46854.6" - process $proc$libresoc.v:46825$2725 + attribute \src "libresoc.v:46621.3-46650.6" + process $proc$libresoc.v:46621$2725 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46826.5-46826.29" + attribute \src "libresoc.v:46622.5-46622.29" switch \initial - attribute \src "libresoc.v:46826.9-46826.17" + attribute \src "libresoc.v:46622.9-46622.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81438,7 +81234,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81454,7 +81250,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81474,14 +81270,14 @@ module \core update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] end - attribute \src "libresoc.v:46855.3-46863.6" - process $proc$libresoc.v:46855$2726 + attribute \src "libresoc.v:46651.3-46659.6" + process $proc$libresoc.v:46651$2726 assign { } { } assign { } { } assign $0\wr_pick_dly$1029$next[0:0]$2727 $1\wr_pick_dly$1029$next[0:0]$2728 - attribute \src "libresoc.v:46856.5-46856.29" + attribute \src "libresoc.v:46652.5-46652.29" switch \initial - attribute \src "libresoc.v:46856.9-46856.17" + attribute \src "libresoc.v:46652.9-46652.17" case 1'1 case end @@ -81497,14 +81293,14 @@ module \core sync always update \wr_pick_dly$1029$next $0\wr_pick_dly$1029$next[0:0]$2727 end - attribute \src "libresoc.v:46864.3-46872.6" - process $proc$libresoc.v:46864$2729 + attribute \src "libresoc.v:46660.3-46668.6" + process $proc$libresoc.v:46660$2729 assign { } { } assign { } { } assign $0\wr_pick_dly$1047$next[0:0]$2730 $1\wr_pick_dly$1047$next[0:0]$2731 - attribute \src "libresoc.v:46865.5-46865.29" + attribute \src "libresoc.v:46661.5-46661.29" switch \initial - attribute \src "libresoc.v:46865.9-46865.17" + attribute \src "libresoc.v:46661.9-46661.17" case 1'1 case end @@ -81520,14 +81316,14 @@ module \core sync always update \wr_pick_dly$1047$next $0\wr_pick_dly$1047$next[0:0]$2730 end - attribute \src "libresoc.v:46873.3-46881.6" - process $proc$libresoc.v:46873$2732 + attribute \src "libresoc.v:46669.3-46677.6" + process $proc$libresoc.v:46669$2732 assign { } { } assign { } { } assign $0\wr_pick_dly$1069$next[0:0]$2733 $1\wr_pick_dly$1069$next[0:0]$2734 - attribute \src "libresoc.v:46874.5-46874.29" + attribute \src "libresoc.v:46670.5-46670.29" switch \initial - attribute \src "libresoc.v:46874.9-46874.17" + attribute \src "libresoc.v:46670.9-46670.17" case 1'1 case end @@ -81543,21 +81339,21 @@ module \core sync always update \wr_pick_dly$1069$next $0\wr_pick_dly$1069$next[0:0]$2733 end - attribute \src "libresoc.v:46882.3-46911.6" - process $proc$libresoc.v:46882$2735 + attribute \src "libresoc.v:46678.3-46707.6" + process $proc$libresoc.v:46678$2735 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46883.5-46883.29" + attribute \src "libresoc.v:46679.5-46679.29" switch \initial - attribute \src "libresoc.v:46883.9-46883.17" + attribute \src "libresoc.v:46679.9-46679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81565,7 +81361,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81581,7 +81377,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81601,14 +81397,14 @@ module \core update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] end - attribute \src "libresoc.v:46912.3-46920.6" - process $proc$libresoc.v:46912$2736 + attribute \src "libresoc.v:46708.3-46716.6" + process $proc$libresoc.v:46708$2736 assign { } { } assign { } { } assign $0\wr_pick_dly$1089$next[0:0]$2737 $1\wr_pick_dly$1089$next[0:0]$2738 - attribute \src "libresoc.v:46913.5-46913.29" + attribute \src "libresoc.v:46709.5-46709.29" switch \initial - attribute \src "libresoc.v:46913.9-46913.17" + attribute \src "libresoc.v:46709.9-46709.17" case 1'1 case end @@ -81624,14 +81420,14 @@ module \core sync always update \wr_pick_dly$1089$next $0\wr_pick_dly$1089$next[0:0]$2737 end - attribute \src "libresoc.v:46921.3-46929.6" - process $proc$libresoc.v:46921$2739 + attribute \src "libresoc.v:46717.3-46725.6" + process $proc$libresoc.v:46717$2739 assign { } { } assign { } { } assign $0\wr_pick_dly$1109$next[0:0]$2740 $1\wr_pick_dly$1109$next[0:0]$2741 - attribute \src "libresoc.v:46922.5-46922.29" + attribute \src "libresoc.v:46718.5-46718.29" switch \initial - attribute \src "libresoc.v:46922.9-46922.17" + attribute \src "libresoc.v:46718.9-46718.17" case 1'1 case end @@ -81647,14 +81443,14 @@ module \core sync always update \wr_pick_dly$1109$next $0\wr_pick_dly$1109$next[0:0]$2740 end - attribute \src "libresoc.v:46930.3-46938.6" - process $proc$libresoc.v:46930$2742 + attribute \src "libresoc.v:46726.3-46734.6" + process $proc$libresoc.v:46726$2742 assign { } { } assign { } { } assign $0\wr_pick_dly$1128$next[0:0]$2743 $1\wr_pick_dly$1128$next[0:0]$2744 - attribute \src "libresoc.v:46931.5-46931.29" + attribute \src "libresoc.v:46727.5-46727.29" switch \initial - attribute \src "libresoc.v:46931.9-46931.17" + attribute \src "libresoc.v:46727.9-46727.17" case 1'1 case end @@ -81670,24 +81466,24 @@ module \core sync always update \wr_pick_dly$1128$next $0\wr_pick_dly$1128$next[0:0]$2743 end - attribute \src "libresoc.v:46939.3-46967.6" - process $proc$libresoc.v:46939$2745 + attribute \src "libresoc.v:46735.3-46763.6" + process $proc$libresoc.v:46735$2745 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46940.5-46940.29" + attribute \src "libresoc.v:46736.5-46736.29" switch \initial - attribute \src "libresoc.v:46940.9-46940.17" + attribute \src "libresoc.v:46736.9-46736.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81699,7 +81495,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81715,14 +81511,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] end - attribute \src "libresoc.v:46968.3-46976.6" - process $proc$libresoc.v:46968$2746 + attribute \src "libresoc.v:46764.3-46772.6" + process $proc$libresoc.v:46764$2746 assign { } { } assign { } { } assign $0\wr_pick_dly$1146$next[0:0]$2747 $1\wr_pick_dly$1146$next[0:0]$2748 - attribute \src "libresoc.v:46969.5-46969.29" + attribute \src "libresoc.v:46765.5-46765.29" switch \initial - attribute \src "libresoc.v:46969.9-46969.17" + attribute \src "libresoc.v:46765.9-46765.17" case 1'1 case end @@ -81738,24 +81534,24 @@ module \core sync always update \wr_pick_dly$1146$next $0\wr_pick_dly$1146$next[0:0]$2747 end - attribute \src "libresoc.v:46977.3-47005.6" - process $proc$libresoc.v:46977$2749 + attribute \src "libresoc.v:46773.3-46801.6" + process $proc$libresoc.v:46773$2749 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46978.5-46978.29" + attribute \src "libresoc.v:46774.5-46774.29" switch \initial - attribute \src "libresoc.v:46978.9-46978.17" + attribute \src "libresoc.v:46774.9-46774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81767,7 +81563,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81783,14 +81579,14 @@ module \core sync always update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] end - attribute \src "libresoc.v:47006.3-47014.6" - process $proc$libresoc.v:47006$2750 + attribute \src "libresoc.v:46802.3-46810.6" + process $proc$libresoc.v:46802$2750 assign { } { } assign { } { } assign $0\wr_pick_dly$1220$next[0:0]$2751 $1\wr_pick_dly$1220$next[0:0]$2752 - attribute \src "libresoc.v:47007.5-47007.29" + attribute \src "libresoc.v:46803.5-46803.29" switch \initial - attribute \src "libresoc.v:47007.9-47007.17" + attribute \src "libresoc.v:46803.9-46803.17" case 1'1 case end @@ -81806,24 +81602,24 @@ module \core sync always update \wr_pick_dly$1220$next $0\wr_pick_dly$1220$next[0:0]$2751 end - attribute \src "libresoc.v:47015.3-47043.6" - process $proc$libresoc.v:47015$2753 + attribute \src "libresoc.v:46811.3-46839.6" + process $proc$libresoc.v:46811$2753 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47016.5-47016.29" + attribute \src "libresoc.v:46812.5-46812.29" switch \initial - attribute \src "libresoc.v:47016.9-47016.17" + attribute \src "libresoc.v:46812.9-46812.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81835,7 +81631,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81851,14 +81647,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] end - attribute \src "libresoc.v:47044.3-47052.6" - process $proc$libresoc.v:47044$2754 + attribute \src "libresoc.v:46840.3-46848.6" + process $proc$libresoc.v:46840$2754 assign { } { } assign { } { } assign $0\wr_pick_dly$1248$next[0:0]$2755 $1\wr_pick_dly$1248$next[0:0]$2756 - attribute \src "libresoc.v:47045.5-47045.29" + attribute \src "libresoc.v:46841.5-46841.29" switch \initial - attribute \src "libresoc.v:47045.9-47045.17" + attribute \src "libresoc.v:46841.9-46841.17" case 1'1 case end @@ -81874,24 +81670,24 @@ module \core sync always update \wr_pick_dly$1248$next $0\wr_pick_dly$1248$next[0:0]$2755 end - attribute \src "libresoc.v:47053.3-47081.6" - process $proc$libresoc.v:47053$2757 + attribute \src "libresoc.v:46849.3-46877.6" + process $proc$libresoc.v:46849$2757 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:47054.5-47054.29" + attribute \src "libresoc.v:46850.5-46850.29" switch \initial - attribute \src "libresoc.v:47054.9-47054.17" + attribute \src "libresoc.v:46850.9-46850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81903,7 +81699,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81919,14 +81715,14 @@ module \core sync always update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] end - attribute \src "libresoc.v:47082.3-47090.6" - process $proc$libresoc.v:47082$2758 + attribute \src "libresoc.v:46878.3-46886.6" + process $proc$libresoc.v:46878$2758 assign { } { } assign { } { } assign $0\wr_pick_dly$1268$next[0:0]$2759 $1\wr_pick_dly$1268$next[0:0]$2760 - attribute \src "libresoc.v:47083.5-47083.29" + attribute \src "libresoc.v:46879.5-46879.29" switch \initial - attribute \src "libresoc.v:47083.9-47083.17" + attribute \src "libresoc.v:46879.9-46879.17" case 1'1 case end @@ -81942,14 +81738,14 @@ module \core sync always update \wr_pick_dly$1268$next $0\wr_pick_dly$1268$next[0:0]$2759 end - attribute \src "libresoc.v:47091.3-47099.6" - process $proc$libresoc.v:47091$2761 + attribute \src "libresoc.v:46887.3-46895.6" + process $proc$libresoc.v:46887$2761 assign { } { } assign { } { } assign $0\wr_pick_dly$1288$next[0:0]$2762 $1\wr_pick_dly$1288$next[0:0]$2763 - attribute \src "libresoc.v:47092.5-47092.29" + attribute \src "libresoc.v:46888.5-46888.29" switch \initial - attribute \src "libresoc.v:47092.9-47092.17" + attribute \src "libresoc.v:46888.9-46888.17" case 1'1 case end @@ -81965,24 +81761,24 @@ module \core sync always update \wr_pick_dly$1288$next $0\wr_pick_dly$1288$next[0:0]$2762 end - attribute \src "libresoc.v:47100.3-47128.6" - process $proc$libresoc.v:47100$2764 + attribute \src "libresoc.v:46896.3-46924.6" + process $proc$libresoc.v:46896$2764 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47101.5-47101.29" + attribute \src "libresoc.v:46897.5-46897.29" switch \initial - attribute \src "libresoc.v:47101.9-47101.17" + attribute \src "libresoc.v:46897.9-46897.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81994,7 +81790,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82010,14 +81806,14 @@ module \core sync always update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] end - attribute \src "libresoc.v:47129.3-47137.6" - process $proc$libresoc.v:47129$2765 + attribute \src "libresoc.v:46925.3-46933.6" + process $proc$libresoc.v:46925$2765 assign { } { } assign { } { } assign $0\wr_pick_dly$1308$next[0:0]$2766 $1\wr_pick_dly$1308$next[0:0]$2767 - attribute \src "libresoc.v:47130.5-47130.29" + attribute \src "libresoc.v:46926.5-46926.29" switch \initial - attribute \src "libresoc.v:47130.9-47130.17" + attribute \src "libresoc.v:46926.9-46926.17" case 1'1 case end @@ -82033,14 +81829,14 @@ module \core sync always update \wr_pick_dly$1308$next $0\wr_pick_dly$1308$next[0:0]$2766 end - attribute \src "libresoc.v:47138.3-47146.6" - process $proc$libresoc.v:47138$2768 + attribute \src "libresoc.v:46934.3-46942.6" + process $proc$libresoc.v:46934$2768 assign { } { } assign { } { } assign $0\wr_pick_dly$1328$next[0:0]$2769 $1\wr_pick_dly$1328$next[0:0]$2770 - attribute \src "libresoc.v:47139.5-47139.29" + attribute \src "libresoc.v:46935.5-46935.29" switch \initial - attribute \src "libresoc.v:47139.9-47139.17" + attribute \src "libresoc.v:46935.9-46935.17" case 1'1 case end @@ -82056,24 +81852,24 @@ module \core sync always update \wr_pick_dly$1328$next $0\wr_pick_dly$1328$next[0:0]$2769 end - attribute \src "libresoc.v:47147.3-47175.6" - process $proc$libresoc.v:47147$2771 + attribute \src "libresoc.v:46943.3-46971.6" + process $proc$libresoc.v:46943$2771 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:47148.5-47148.29" + attribute \src "libresoc.v:46944.5-46944.29" switch \initial - attribute \src "libresoc.v:47148.9-47148.17" + attribute \src "libresoc.v:46944.9-46944.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82085,7 +81881,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82101,14 +81897,14 @@ module \core sync always update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] end - attribute \src "libresoc.v:47176.3-47184.6" - process $proc$libresoc.v:47176$2772 + attribute \src "libresoc.v:46972.3-46980.6" + process $proc$libresoc.v:46972$2772 assign { } { } assign { } { } assign $0\wr_pick_dly$1348$next[0:0]$2773 $1\wr_pick_dly$1348$next[0:0]$2774 - attribute \src "libresoc.v:47177.5-47177.29" + attribute \src "libresoc.v:46973.5-46973.29" switch \initial - attribute \src "libresoc.v:47177.9-47177.17" + attribute \src "libresoc.v:46973.9-46973.17" case 1'1 case end @@ -82124,24 +81920,24 @@ module \core sync always update \wr_pick_dly$1348$next $0\wr_pick_dly$1348$next[0:0]$2773 end - attribute \src "libresoc.v:47185.3-47213.6" - process $proc$libresoc.v:47185$2775 + attribute \src "libresoc.v:46981.3-47009.6" + process $proc$libresoc.v:46981$2775 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47186.5-47186.29" + attribute \src "libresoc.v:46982.5-46982.29" switch \initial - attribute \src "libresoc.v:47186.9-47186.17" + attribute \src "libresoc.v:46982.9-46982.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82153,7 +81949,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82169,14 +81965,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] end - attribute \src "libresoc.v:47214.3-47222.6" - process $proc$libresoc.v:47214$2776 + attribute \src "libresoc.v:47010.3-47018.6" + process $proc$libresoc.v:47010$2776 assign { } { } assign { } { } assign $0\wr_pick_dly$1395$next[0:0]$2777 $1\wr_pick_dly$1395$next[0:0]$2778 - attribute \src "libresoc.v:47215.5-47215.29" + attribute \src "libresoc.v:47011.5-47011.29" switch \initial - attribute \src "libresoc.v:47215.9-47215.17" + attribute \src "libresoc.v:47011.9-47011.17" case 1'1 case end @@ -82192,24 +81988,24 @@ module \core sync always update \wr_pick_dly$1395$next $0\wr_pick_dly$1395$next[0:0]$2777 end - attribute \src "libresoc.v:47223.3-47251.6" - process $proc$libresoc.v:47223$2779 + attribute \src "libresoc.v:47019.3-47047.6" + process $proc$libresoc.v:47019$2779 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:47224.5-47224.29" + attribute \src "libresoc.v:47020.5-47020.29" switch \initial - attribute \src "libresoc.v:47224.9-47224.17" + attribute \src "libresoc.v:47020.9-47020.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82221,7 +82017,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82237,14 +82033,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] end - attribute \src "libresoc.v:47252.3-47260.6" - process $proc$libresoc.v:47252$2780 + attribute \src "libresoc.v:47048.3-47056.6" + process $proc$libresoc.v:47048$2780 assign { } { } assign { } { } assign $0\wr_pick_dly$1411$next[0:0]$2781 $1\wr_pick_dly$1411$next[0:0]$2782 - attribute \src "libresoc.v:47253.5-47253.29" + attribute \src "libresoc.v:47049.5-47049.29" switch \initial - attribute \src "libresoc.v:47253.9-47253.17" + attribute \src "libresoc.v:47049.9-47049.17" case 1'1 case end @@ -82260,14 +82056,14 @@ module \core sync always update \wr_pick_dly$1411$next $0\wr_pick_dly$1411$next[0:0]$2781 end - attribute \src "libresoc.v:47261.3-47269.6" - process $proc$libresoc.v:47261$2783 + attribute \src "libresoc.v:47057.3-47065.6" + process $proc$libresoc.v:47057$2783 assign { } { } assign { } { } assign $0\wr_pick_dly$1427$next[0:0]$2784 $1\wr_pick_dly$1427$next[0:0]$2785 - attribute \src "libresoc.v:47262.5-47262.29" + attribute \src "libresoc.v:47058.5-47058.29" switch \initial - attribute \src "libresoc.v:47262.9-47262.17" + attribute \src "libresoc.v:47058.9-47058.17" case 1'1 case end @@ -82283,24 +82079,24 @@ module \core sync always update \wr_pick_dly$1427$next $0\wr_pick_dly$1427$next[0:0]$2784 end - attribute \src "libresoc.v:47270.3-47298.6" - process $proc$libresoc.v:47270$2786 + attribute \src "libresoc.v:47066.3-47094.6" + process $proc$libresoc.v:47066$2786 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:47271.5-47271.29" + attribute \src "libresoc.v:47067.5-47067.29" switch \initial - attribute \src "libresoc.v:47271.9-47271.17" + attribute \src "libresoc.v:47067.9-47067.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82312,7 +82108,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82328,14 +82124,14 @@ module \core sync always update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] end - attribute \src "libresoc.v:47299.3-47307.6" - process $proc$libresoc.v:47299$2787 + attribute \src "libresoc.v:47095.3-47103.6" + process $proc$libresoc.v:47095$2787 assign { } { } assign { } { } assign $0\wr_pick_dly$1461$next[0:0]$2788 $1\wr_pick_dly$1461$next[0:0]$2789 - attribute \src "libresoc.v:47300.5-47300.29" + attribute \src "libresoc.v:47096.5-47096.29" switch \initial - attribute \src "libresoc.v:47300.9-47300.17" + attribute \src "libresoc.v:47096.9-47096.17" case 1'1 case end @@ -82351,24 +82147,24 @@ module \core sync always update \wr_pick_dly$1461$next $0\wr_pick_dly$1461$next[0:0]$2788 end - attribute \src "libresoc.v:47308.3-47336.6" - process $proc$libresoc.v:47308$2790 + attribute \src "libresoc.v:47104.3-47132.6" + process $proc$libresoc.v:47104$2790 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:47309.5-47309.29" + attribute \src "libresoc.v:47105.5-47105.29" switch \initial - attribute \src "libresoc.v:47309.9-47309.17" + attribute \src "libresoc.v:47105.9-47105.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82380,7 +82176,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82396,14 +82192,14 @@ module \core sync always update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] end - attribute \src "libresoc.v:47337.3-47345.6" - process $proc$libresoc.v:47337$2791 + attribute \src "libresoc.v:47133.3-47141.6" + process $proc$libresoc.v:47133$2791 assign { } { } assign { } { } assign $0\wr_pick_dly$1477$next[0:0]$2792 $1\wr_pick_dly$1477$next[0:0]$2793 - attribute \src "libresoc.v:47338.5-47338.29" + attribute \src "libresoc.v:47134.5-47134.29" switch \initial - attribute \src "libresoc.v:47338.9-47338.17" + attribute \src "libresoc.v:47134.9-47134.17" case 1'1 case end @@ -82419,14 +82215,14 @@ module \core sync always update \wr_pick_dly$1477$next $0\wr_pick_dly$1477$next[0:0]$2792 end - attribute \src "libresoc.v:47346.3-47354.6" - process $proc$libresoc.v:47346$2794 + attribute \src "libresoc.v:47142.3-47150.6" + process $proc$libresoc.v:47142$2794 assign { } { } assign { } { } assign $0\wr_pick_dly$1493$next[0:0]$2795 $1\wr_pick_dly$1493$next[0:0]$2796 - attribute \src "libresoc.v:47347.5-47347.29" + attribute \src "libresoc.v:47143.5-47143.29" switch \initial - attribute \src "libresoc.v:47347.9-47347.17" + attribute \src "libresoc.v:47143.9-47143.17" case 1'1 case end @@ -82442,24 +82238,24 @@ module \core sync always update \wr_pick_dly$1493$next $0\wr_pick_dly$1493$next[0:0]$2795 end - attribute \src "libresoc.v:47355.3-47383.6" - process $proc$libresoc.v:47355$2797 + attribute \src "libresoc.v:47151.3-47179.6" + process $proc$libresoc.v:47151$2797 assign { } { } assign { } { } assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47356.5-47356.29" + attribute \src "libresoc.v:47152.5-47152.29" switch \initial - attribute \src "libresoc.v:47356.9-47356.17" + attribute \src "libresoc.v:47152.9-47152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82471,7 +82267,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82487,14 +82283,14 @@ module \core sync always update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] end - attribute \src "libresoc.v:47384.3-47392.6" - process $proc$libresoc.v:47384$2798 + attribute \src "libresoc.v:47180.3-47188.6" + process $proc$libresoc.v:47180$2798 assign { } { } assign { } { } assign $0\wr_pick_dly$1509$next[0:0]$2799 $1\wr_pick_dly$1509$next[0:0]$2800 - attribute \src "libresoc.v:47385.5-47385.29" + attribute \src "libresoc.v:47181.5-47181.29" switch \initial - attribute \src "libresoc.v:47385.9-47385.17" + attribute \src "libresoc.v:47181.9-47181.17" case 1'1 case end @@ -82510,24 +82306,24 @@ module \core sync always update \wr_pick_dly$1509$next $0\wr_pick_dly$1509$next[0:0]$2799 end - attribute \src "libresoc.v:47393.3-47421.6" - process $proc$libresoc.v:47393$2801 + attribute \src "libresoc.v:47189.3-47217.6" + process $proc$libresoc.v:47189$2801 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47394.5-47394.29" + attribute \src "libresoc.v:47190.5-47190.29" switch \initial - attribute \src "libresoc.v:47394.9-47394.17" + attribute \src "libresoc.v:47190.9-47190.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82539,7 +82335,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82555,14 +82351,14 @@ module \core sync always update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] end - attribute \src "libresoc.v:47422.3-47430.6" - process $proc$libresoc.v:47422$2802 + attribute \src "libresoc.v:47218.3-47226.6" + process $proc$libresoc.v:47218$2802 assign { } { } assign { } { } assign $0\wr_pick_dly$1545$next[0:0]$2803 $1\wr_pick_dly$1545$next[0:0]$2804 - attribute \src "libresoc.v:47423.5-47423.29" + attribute \src "libresoc.v:47219.5-47219.29" switch \initial - attribute \src "libresoc.v:47423.9-47423.17" + attribute \src "libresoc.v:47219.9-47219.17" case 1'1 case end @@ -82578,14 +82374,14 @@ module \core sync always update \wr_pick_dly$1545$next $0\wr_pick_dly$1545$next[0:0]$2803 end - attribute \src "libresoc.v:47431.3-47439.6" - process $proc$libresoc.v:47431$2805 + attribute \src "libresoc.v:47227.3-47235.6" + process $proc$libresoc.v:47227$2805 assign { } { } assign { } { } assign $0\wr_pick_dly$1561$next[0:0]$2806 $1\wr_pick_dly$1561$next[0:0]$2807 - attribute \src "libresoc.v:47432.5-47432.29" + attribute \src "libresoc.v:47228.5-47228.29" switch \initial - attribute \src "libresoc.v:47432.9-47432.17" + attribute \src "libresoc.v:47228.9-47228.17" case 1'1 case end @@ -82601,24 +82397,24 @@ module \core sync always update \wr_pick_dly$1561$next $0\wr_pick_dly$1561$next[0:0]$2806 end - attribute \src "libresoc.v:47440.3-47468.6" - process $proc$libresoc.v:47440$2808 + attribute \src "libresoc.v:47236.3-47264.6" + process $proc$libresoc.v:47236$2808 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:47441.5-47441.29" + attribute \src "libresoc.v:47237.5-47237.29" switch \initial - attribute \src "libresoc.v:47441.9-47441.17" + attribute \src "libresoc.v:47237.9-47237.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82630,7 +82426,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82646,14 +82442,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] end - attribute \src "libresoc.v:47469.3-47477.6" - process $proc$libresoc.v:47469$2809 + attribute \src "libresoc.v:47265.3-47273.6" + process $proc$libresoc.v:47265$2809 assign { } { } assign { } { } assign $0\wr_pick_dly$1577$next[0:0]$2810 $1\wr_pick_dly$1577$next[0:0]$2811 - attribute \src "libresoc.v:47470.5-47470.29" + attribute \src "libresoc.v:47266.5-47266.29" switch \initial - attribute \src "libresoc.v:47470.9-47470.17" + attribute \src "libresoc.v:47266.9-47266.17" case 1'1 case end @@ -82669,24 +82465,24 @@ module \core sync always update \wr_pick_dly$1577$next $0\wr_pick_dly$1577$next[0:0]$2810 end - attribute \src "libresoc.v:47478.3-47506.6" - process $proc$libresoc.v:47478$2812 + attribute \src "libresoc.v:47274.3-47302.6" + process $proc$libresoc.v:47274$2812 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__fn_unit[13:0] $1\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47479.5-47479.29" + attribute \src "libresoc.v:47275.5-47275.29" switch \initial - attribute \src "libresoc.v:47479.9-47479.17" + attribute \src "libresoc.v:47275.9-47275.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__fn_unit[13:0] $2\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82698,7 +82494,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] $3\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82714,14 +82510,14 @@ module \core sync always update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[13:0] end - attribute \src "libresoc.v:47507.3-47515.6" - process $proc$libresoc.v:47507$2813 + attribute \src "libresoc.v:47303.3-47311.6" + process $proc$libresoc.v:47303$2813 assign { } { } assign { } { } assign $0\wr_pick_dly$1593$next[0:0]$2814 $1\wr_pick_dly$1593$next[0:0]$2815 - attribute \src "libresoc.v:47508.5-47508.29" + attribute \src "libresoc.v:47304.5-47304.29" switch \initial - attribute \src "libresoc.v:47508.9-47508.17" + attribute \src "libresoc.v:47304.9-47304.17" case 1'1 case end @@ -82737,14 +82533,14 @@ module \core sync always update \wr_pick_dly$1593$next $0\wr_pick_dly$1593$next[0:0]$2814 end - attribute \src "libresoc.v:47516.3-47524.6" - process $proc$libresoc.v:47516$2816 + attribute \src "libresoc.v:47312.3-47320.6" + process $proc$libresoc.v:47312$2816 assign { } { } assign { } { } assign $0\wr_pick_dly$1635$next[0:0]$2817 $1\wr_pick_dly$1635$next[0:0]$2818 - attribute \src "libresoc.v:47517.5-47517.29" + attribute \src "libresoc.v:47313.5-47313.29" switch \initial - attribute \src "libresoc.v:47517.9-47517.17" + attribute \src "libresoc.v:47313.9-47313.17" case 1'1 case end @@ -82760,24 +82556,24 @@ module \core sync always update \wr_pick_dly$1635$next $0\wr_pick_dly$1635$next[0:0]$2817 end - attribute \src "libresoc.v:47525.3-47553.6" - process $proc$libresoc.v:47525$2819 + attribute \src "libresoc.v:47321.3-47349.6" + process $proc$libresoc.v:47321$2819 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47526.5-47526.29" + attribute \src "libresoc.v:47322.5-47322.29" switch \initial - attribute \src "libresoc.v:47526.9-47526.17" + attribute \src "libresoc.v:47322.9-47322.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82789,7 +82585,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82805,14 +82601,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] end - attribute \src "libresoc.v:47554.3-47562.6" - process $proc$libresoc.v:47554$2820 + attribute \src "libresoc.v:47350.3-47358.6" + process $proc$libresoc.v:47350$2820 assign { } { } assign { } { } assign $0\wr_pick_dly$1654$next[0:0]$2821 $1\wr_pick_dly$1654$next[0:0]$2822 - attribute \src "libresoc.v:47555.5-47555.29" + attribute \src "libresoc.v:47351.5-47351.29" switch \initial - attribute \src "libresoc.v:47555.9-47555.17" + attribute \src "libresoc.v:47351.9-47351.17" case 1'1 case end @@ -82828,24 +82624,24 @@ module \core sync always update \wr_pick_dly$1654$next $0\wr_pick_dly$1654$next[0:0]$2821 end - attribute \src "libresoc.v:47563.3-47591.6" - process $proc$libresoc.v:47563$2823 + attribute \src "libresoc.v:47359.3-47387.6" + process $proc$libresoc.v:47359$2823 assign { } { } assign { } { } assign $0\fus_cu_issue_i$13[0:0]$2824 $1\fus_cu_issue_i$13[0:0]$2825 - attribute \src "libresoc.v:47564.5-47564.29" + attribute \src "libresoc.v:47360.5-47360.29" switch \initial - attribute \src "libresoc.v:47564.9-47564.17" + attribute \src "libresoc.v:47360.9-47360.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$13[0:0]$2825 $2\fus_cu_issue_i$13[0:0]$2826 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82857,7 +82653,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$13[0:0]$2826 $3\fus_cu_issue_i$13[0:0]$2827 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82873,14 +82669,14 @@ module \core sync always update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2824 end - attribute \src "libresoc.v:47592.3-47600.6" - process $proc$libresoc.v:47592$2828 + attribute \src "libresoc.v:47388.3-47396.6" + process $proc$libresoc.v:47388$2828 assign { } { } assign { } { } assign $0\wr_pick_dly$1670$next[0:0]$2829 $1\wr_pick_dly$1670$next[0:0]$2830 - attribute \src "libresoc.v:47593.5-47593.29" + attribute \src "libresoc.v:47389.5-47389.29" switch \initial - attribute \src "libresoc.v:47593.9-47593.17" + attribute \src "libresoc.v:47389.9-47389.17" case 1'1 case end @@ -82896,14 +82692,14 @@ module \core sync always update \wr_pick_dly$1670$next $0\wr_pick_dly$1670$next[0:0]$2829 end - attribute \src "libresoc.v:47601.3-47609.6" - process $proc$libresoc.v:47601$2831 + attribute \src "libresoc.v:47397.3-47405.6" + process $proc$libresoc.v:47397$2831 assign { } { } assign { } { } assign $0\wr_pick_dly$1686$next[0:0]$2832 $1\wr_pick_dly$1686$next[0:0]$2833 - attribute \src "libresoc.v:47602.5-47602.29" + attribute \src "libresoc.v:47398.5-47398.29" switch \initial - attribute \src "libresoc.v:47602.9-47602.17" + attribute \src "libresoc.v:47398.9-47398.17" case 1'1 case end @@ -82919,24 +82715,24 @@ module \core sync always update \wr_pick_dly$1686$next $0\wr_pick_dly$1686$next[0:0]$2832 end - attribute \src "libresoc.v:47610.3-47638.6" - process $proc$libresoc.v:47610$2834 + attribute \src "libresoc.v:47406.3-47434.6" + process $proc$libresoc.v:47406$2834 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$15[5:0]$2835 $1\fus_cu_rdmaskn_i$15[5:0]$2836 - attribute \src "libresoc.v:47611.5-47611.29" + attribute \src "libresoc.v:47407.5-47407.29" switch \initial - attribute \src "libresoc.v:47611.9-47611.17" + attribute \src "libresoc.v:47407.9-47407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$15[5:0]$2836 $2\fus_cu_rdmaskn_i$15[5:0]$2837 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82948,7 +82744,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$15[5:0]$2837 $3\fus_cu_rdmaskn_i$15[5:0]$2838 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82964,14 +82760,14 @@ module \core sync always update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2835 end - attribute \src "libresoc.v:47639.3-47647.6" - process $proc$libresoc.v:47639$2839 + attribute \src "libresoc.v:47435.3-47443.6" + process $proc$libresoc.v:47435$2839 assign { } { } assign { } { } assign $0\wr_pick_dly$1702$next[0:0]$2840 $1\wr_pick_dly$1702$next[0:0]$2841 - attribute \src "libresoc.v:47640.5-47640.29" + attribute \src "libresoc.v:47436.5-47436.29" switch \initial - attribute \src "libresoc.v:47640.9-47640.17" + attribute \src "libresoc.v:47436.9-47436.17" case 1'1 case end @@ -82987,24 +82783,24 @@ module \core sync always update \wr_pick_dly$1702$next $0\wr_pick_dly$1702$next[0:0]$2840 end - attribute \src "libresoc.v:47648.3-47676.6" - process $proc$libresoc.v:47648$2842 + attribute \src "libresoc.v:47444.3-47472.6" + process $proc$libresoc.v:47444$2842 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47649.5-47649.29" + attribute \src "libresoc.v:47445.5-47445.29" switch \initial - attribute \src "libresoc.v:47649.9-47649.17" + attribute \src "libresoc.v:47445.9-47445.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83016,7 +82812,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83032,14 +82828,14 @@ module \core sync always update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] end - attribute \src "libresoc.v:47677.3-47685.6" - process $proc$libresoc.v:47677$2843 + attribute \src "libresoc.v:47473.3-47481.6" + process $proc$libresoc.v:47473$2843 assign { } { } assign { } { } assign $0\wr_pick_dly$1746$next[0:0]$2844 $1\wr_pick_dly$1746$next[0:0]$2845 - attribute \src "libresoc.v:47678.5-47678.29" + attribute \src "libresoc.v:47474.5-47474.29" switch \initial - attribute \src "libresoc.v:47678.9-47678.17" + attribute \src "libresoc.v:47474.9-47474.17" case 1'1 case end @@ -83055,24 +82851,24 @@ module \core sync always update \wr_pick_dly$1746$next $0\wr_pick_dly$1746$next[0:0]$2844 end - attribute \src "libresoc.v:47686.3-47714.6" - process $proc$libresoc.v:47686$2846 + attribute \src "libresoc.v:47482.3-47510.6" + process $proc$libresoc.v:47482$2846 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47687.5-47687.29" + attribute \src "libresoc.v:47483.5-47483.29" switch \initial - attribute \src "libresoc.v:47687.9-47687.17" + attribute \src "libresoc.v:47483.9-47483.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83084,7 +82880,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83100,14 +82896,14 @@ module \core sync always update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] end - attribute \src "libresoc.v:47715.3-47723.6" - process $proc$libresoc.v:47715$2847 + attribute \src "libresoc.v:47511.3-47519.6" + process $proc$libresoc.v:47511$2847 assign { } { } assign { } { } assign $0\wr_pick_dly$1762$next[0:0]$2848 $1\wr_pick_dly$1762$next[0:0]$2849 - attribute \src "libresoc.v:47716.5-47716.29" + attribute \src "libresoc.v:47512.5-47512.29" switch \initial - attribute \src "libresoc.v:47716.9-47716.17" + attribute \src "libresoc.v:47512.9-47512.17" case 1'1 case end @@ -83123,14 +82919,14 @@ module \core sync always update \wr_pick_dly$1762$next $0\wr_pick_dly$1762$next[0:0]$2848 end - attribute \src "libresoc.v:47724.3-47732.6" - process $proc$libresoc.v:47724$2850 + attribute \src "libresoc.v:47520.3-47528.6" + process $proc$libresoc.v:47520$2850 assign { } { } assign { } { } assign $0\wr_pick_dly$1786$next[0:0]$2851 $1\wr_pick_dly$1786$next[0:0]$2852 - attribute \src "libresoc.v:47725.5-47725.29" + attribute \src "libresoc.v:47521.5-47521.29" switch \initial - attribute \src "libresoc.v:47725.9-47725.17" + attribute \src "libresoc.v:47521.9-47521.17" case 1'1 case end @@ -83146,24 +82942,24 @@ module \core sync always update \wr_pick_dly$1786$next $0\wr_pick_dly$1786$next[0:0]$2851 end - attribute \src "libresoc.v:47733.3-47761.6" - process $proc$libresoc.v:47733$2853 + attribute \src "libresoc.v:47529.3-47557.6" + process $proc$libresoc.v:47529$2853 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__fn_unit[13:0] $1\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47734.5-47734.29" + attribute \src "libresoc.v:47530.5-47530.29" switch \initial - attribute \src "libresoc.v:47734.9-47734.17" + attribute \src "libresoc.v:47530.9-47530.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__fn_unit[13:0] $2\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83175,7 +82971,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] $3\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83191,14 +82987,14 @@ module \core sync always update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[13:0] end - attribute \src "libresoc.v:47762.3-47770.6" - process $proc$libresoc.v:47762$2854 + attribute \src "libresoc.v:47558.3-47566.6" + process $proc$libresoc.v:47558$2854 assign { } { } assign { } { } assign $0\wr_pick_dly$1806$next[0:0]$2855 $1\wr_pick_dly$1806$next[0:0]$2856 - attribute \src "libresoc.v:47763.5-47763.29" + attribute \src "libresoc.v:47559.5-47559.29" switch \initial - attribute \src "libresoc.v:47763.9-47763.17" + attribute \src "libresoc.v:47559.9-47559.17" case 1'1 case end @@ -83214,24 +83010,24 @@ module \core sync always update \wr_pick_dly$1806$next $0\wr_pick_dly$1806$next[0:0]$2855 end - attribute \src "libresoc.v:47771.3-47799.6" - process $proc$libresoc.v:47771$2857 + attribute \src "libresoc.v:47567.3-47595.6" + process $proc$libresoc.v:47567$2857 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47772.5-47772.29" + attribute \src "libresoc.v:47568.5-47568.29" switch \initial - attribute \src "libresoc.v:47772.9-47772.17" + attribute \src "libresoc.v:47568.9-47568.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83243,7 +83039,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83259,21 +83055,21 @@ module \core sync always update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] end - attribute \src "libresoc.v:47800.3-47829.6" - process $proc$libresoc.v:47800$2858 + attribute \src "libresoc.v:47596.3-47625.6" + process $proc$libresoc.v:47596$2858 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47801.5-47801.29" + attribute \src "libresoc.v:47597.5-47597.29" switch \initial - attribute \src "libresoc.v:47801.9-47801.17" + attribute \src "libresoc.v:47597.9-47597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83281,7 +83077,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83297,7 +83093,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83317,24 +83113,24 @@ module \core update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] end - attribute \src "libresoc.v:47830.3-47858.6" - process $proc$libresoc.v:47830$2859 + attribute \src "libresoc.v:47626.3-47654.6" + process $proc$libresoc.v:47626$2859 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47831.5-47831.29" + attribute \src "libresoc.v:47627.5-47627.29" switch \initial - attribute \src "libresoc.v:47831.9-47831.17" + attribute \src "libresoc.v:47627.9-47627.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83346,7 +83142,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83362,24 +83158,24 @@ module \core sync always update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] end - attribute \src "libresoc.v:47859.3-47887.6" - process $proc$libresoc.v:47859$2860 + attribute \src "libresoc.v:47655.3-47683.6" + process $proc$libresoc.v:47655$2860 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47860.5-47860.29" + attribute \src "libresoc.v:47656.5-47656.29" switch \initial - attribute \src "libresoc.v:47860.9-47860.17" + attribute \src "libresoc.v:47656.9-47656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83391,7 +83187,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83407,24 +83203,24 @@ module \core sync always update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] end - attribute \src "libresoc.v:47888.3-47916.6" - process $proc$libresoc.v:47888$2861 + attribute \src "libresoc.v:47684.3-47712.6" + process $proc$libresoc.v:47684$2861 assign { } { } assign { } { } assign $0\fus_cu_issue_i$16[0:0]$2862 $1\fus_cu_issue_i$16[0:0]$2863 - attribute \src "libresoc.v:47889.5-47889.29" + attribute \src "libresoc.v:47685.5-47685.29" switch \initial - attribute \src "libresoc.v:47889.9-47889.17" + attribute \src "libresoc.v:47685.9-47685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$16[0:0]$2863 $2\fus_cu_issue_i$16[0:0]$2864 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83436,7 +83232,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$16[0:0]$2864 $3\fus_cu_issue_i$16[0:0]$2865 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83452,24 +83248,24 @@ module \core sync always update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2862 end - attribute \src "libresoc.v:47917.3-47945.6" - process $proc$libresoc.v:47917$2866 + attribute \src "libresoc.v:47713.3-47741.6" + process $proc$libresoc.v:47713$2866 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$18[2:0]$2867 $1\fus_cu_rdmaskn_i$18[2:0]$2868 - attribute \src "libresoc.v:47918.5-47918.29" + attribute \src "libresoc.v:47714.5-47714.29" switch \initial - attribute \src "libresoc.v:47918.9-47918.17" + attribute \src "libresoc.v:47714.9-47714.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$18[2:0]$2868 $2\fus_cu_rdmaskn_i$18[2:0]$2869 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83481,7 +83277,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 $3\fus_cu_rdmaskn_i$18[2:0]$2870 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83497,24 +83293,24 @@ module \core sync always update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[2:0]$2867 end - attribute \src "libresoc.v:47946.3-47974.6" - process $proc$libresoc.v:47946$2871 + attribute \src "libresoc.v:47742.3-47770.6" + process $proc$libresoc.v:47742$2871 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47947.5-47947.29" + attribute \src "libresoc.v:47743.5-47743.29" switch \initial - attribute \src "libresoc.v:47947.9-47947.17" + attribute \src "libresoc.v:47743.9-47743.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83526,7 +83322,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83542,24 +83338,24 @@ module \core sync always update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] end - attribute \src "libresoc.v:47975.3-48003.6" - process $proc$libresoc.v:47975$2872 + attribute \src "libresoc.v:47771.3-47799.6" + process $proc$libresoc.v:47771$2872 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__fn_unit[13:0] $1\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:47976.5-47976.29" + attribute \src "libresoc.v:47772.5-47772.29" switch \initial - attribute \src "libresoc.v:47976.9-47976.17" + attribute \src "libresoc.v:47772.9-47772.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__fn_unit[13:0] $2\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83571,7 +83367,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] $3\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83587,24 +83383,24 @@ module \core sync always update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[13:0] end - attribute \src "libresoc.v:48004.3-48032.6" - process $proc$libresoc.v:48004$2873 + attribute \src "libresoc.v:47800.3-47828.6" + process $proc$libresoc.v:47800$2873 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:48005.5-48005.29" + attribute \src "libresoc.v:47801.5-47801.29" switch \initial - attribute \src "libresoc.v:48005.9-48005.17" + attribute \src "libresoc.v:47801.9-47801.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83616,7 +83412,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83632,24 +83428,24 @@ module \core sync always update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] end - attribute \src "libresoc.v:48033.3-48061.6" - process $proc$libresoc.v:48033$2874 + attribute \src "libresoc.v:47829.3-47857.6" + process $proc$libresoc.v:47829$2874 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48034.5-48034.29" + attribute \src "libresoc.v:47830.5-47830.29" switch \initial - attribute \src "libresoc.v:48034.9-48034.17" + attribute \src "libresoc.v:47830.9-47830.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83661,7 +83457,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83677,24 +83473,24 @@ module \core sync always update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] end - attribute \src "libresoc.v:48062.3-48090.6" - process $proc$libresoc.v:48062$2875 + attribute \src "libresoc.v:47858.3-47886.6" + process $proc$libresoc.v:47858$2875 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:48063.5-48063.29" + attribute \src "libresoc.v:47859.5-47859.29" switch \initial - attribute \src "libresoc.v:48063.9-48063.17" + attribute \src "libresoc.v:47859.9-47859.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83706,7 +83502,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83722,24 +83518,24 @@ module \core sync always update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] end - attribute \src "libresoc.v:48091.3-48119.6" - process $proc$libresoc.v:48091$2876 + attribute \src "libresoc.v:47887.3-47915.6" + process $proc$libresoc.v:47887$2876 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48092.5-48092.29" + attribute \src "libresoc.v:47888.5-47888.29" switch \initial - attribute \src "libresoc.v:48092.9-48092.17" + attribute \src "libresoc.v:47888.9-47888.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83751,7 +83547,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83767,24 +83563,24 @@ module \core sync always update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] end - attribute \src "libresoc.v:48120.3-48148.6" - process $proc$libresoc.v:48120$2877 + attribute \src "libresoc.v:47916.3-47944.6" + process $proc$libresoc.v:47916$2877 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:48121.5-48121.29" + attribute \src "libresoc.v:47917.5-47917.29" switch \initial - attribute \src "libresoc.v:48121.9-48121.17" + attribute \src "libresoc.v:47917.9-47917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83796,7 +83592,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83812,24 +83608,24 @@ module \core sync always update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] end - attribute \src "libresoc.v:48149.3-48177.6" - process $proc$libresoc.v:48149$2878 + attribute \src "libresoc.v:47945.3-47973.6" + process $proc$libresoc.v:47945$2878 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48150.5-48150.29" + attribute \src "libresoc.v:47946.5-47946.29" switch \initial - attribute \src "libresoc.v:48150.9-48150.17" + attribute \src "libresoc.v:47946.9-47946.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83841,7 +83637,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83857,24 +83653,24 @@ module \core sync always update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] end - attribute \src "libresoc.v:48178.3-48206.6" - process $proc$libresoc.v:48178$2879 + attribute \src "libresoc.v:47974.3-48002.6" + process $proc$libresoc.v:47974$2879 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48179.5-48179.29" + attribute \src "libresoc.v:47975.5-47975.29" switch \initial - attribute \src "libresoc.v:48179.9-48179.17" + attribute \src "libresoc.v:47975.9-47975.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83886,7 +83682,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83902,24 +83698,24 @@ module \core sync always update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] end - attribute \src "libresoc.v:48207.3-48235.6" - process $proc$libresoc.v:48207$2880 + attribute \src "libresoc.v:48003.3-48031.6" + process $proc$libresoc.v:48003$2880 assign { } { } assign { } { } assign $0\fus_cu_issue_i$19[0:0]$2881 $1\fus_cu_issue_i$19[0:0]$2882 - attribute \src "libresoc.v:48208.5-48208.29" + attribute \src "libresoc.v:48004.5-48004.29" switch \initial - attribute \src "libresoc.v:48208.9-48208.17" + attribute \src "libresoc.v:48004.9-48004.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$19[0:0]$2882 $2\fus_cu_issue_i$19[0:0]$2883 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83931,7 +83727,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$19[0:0]$2883 $3\fus_cu_issue_i$19[0:0]$2884 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83947,24 +83743,24 @@ module \core sync always update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2881 end - attribute \src "libresoc.v:48236.3-48264.6" - process $proc$libresoc.v:48236$2885 + attribute \src "libresoc.v:48032.3-48060.6" + process $proc$libresoc.v:48032$2885 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$21[3:0]$2886 $1\fus_cu_rdmaskn_i$21[3:0]$2887 - attribute \src "libresoc.v:48237.5-48237.29" + attribute \src "libresoc.v:48033.5-48033.29" switch \initial - attribute \src "libresoc.v:48237.9-48237.17" + attribute \src "libresoc.v:48033.9-48033.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$21[3:0]$2887 $2\fus_cu_rdmaskn_i$21[3:0]$2888 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83976,7 +83772,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 $3\fus_cu_rdmaskn_i$21[3:0]$2889 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83992,24 +83788,24 @@ module \core sync always update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[3:0]$2886 end - attribute \src "libresoc.v:48265.3-48293.6" - process $proc$libresoc.v:48265$2890 + attribute \src "libresoc.v:48061.3-48089.6" + process $proc$libresoc.v:48061$2890 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48266.5-48266.29" + attribute \src "libresoc.v:48062.5-48062.29" switch \initial - attribute \src "libresoc.v:48266.9-48266.17" + attribute \src "libresoc.v:48062.9-48062.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84021,7 +83817,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84037,24 +83833,24 @@ module \core sync always update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] end - attribute \src "libresoc.v:48294.3-48322.6" - process $proc$libresoc.v:48294$2891 + attribute \src "libresoc.v:48090.3-48118.6" + process $proc$libresoc.v:48090$2891 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__fn_unit[13:0] $1\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48295.5-48295.29" + attribute \src "libresoc.v:48091.5-48091.29" switch \initial - attribute \src "libresoc.v:48295.9-48295.17" + attribute \src "libresoc.v:48091.9-48091.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__fn_unit[13:0] $2\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84066,7 +83862,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] $3\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84082,21 +83878,21 @@ module \core sync always update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[13:0] end - attribute \src "libresoc.v:48323.3-48352.6" - process $proc$libresoc.v:48323$2892 + attribute \src "libresoc.v:48119.3-48148.6" + process $proc$libresoc.v:48119$2892 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48324.5-48324.29" + attribute \src "libresoc.v:48120.5-48120.29" switch \initial - attribute \src "libresoc.v:48324.9-48324.17" + attribute \src "libresoc.v:48120.9-48120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84104,7 +83900,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84120,7 +83916,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84140,21 +83936,21 @@ module \core update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] end - attribute \src "libresoc.v:48353.3-48382.6" - process $proc$libresoc.v:48353$2893 + attribute \src "libresoc.v:48149.3-48178.6" + process $proc$libresoc.v:48149$2893 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48354.5-48354.29" + attribute \src "libresoc.v:48150.5-48150.29" switch \initial - attribute \src "libresoc.v:48354.9-48354.17" + attribute \src "libresoc.v:48150.9-48150.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84162,7 +83958,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84178,7 +83974,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84198,21 +83994,21 @@ module \core update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] end - attribute \src "libresoc.v:48383.3-48412.6" - process $proc$libresoc.v:48383$2894 + attribute \src "libresoc.v:48179.3-48208.6" + process $proc$libresoc.v:48179$2894 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:48384.5-48384.29" + attribute \src "libresoc.v:48180.5-48180.29" switch \initial - attribute \src "libresoc.v:48384.9-48384.17" + attribute \src "libresoc.v:48180.9-48180.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84220,7 +84016,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84236,7 +84032,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84256,24 +84052,24 @@ module \core update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] end - attribute \src "libresoc.v:48413.3-48441.6" - process $proc$libresoc.v:48413$2895 + attribute \src "libresoc.v:48209.3-48237.6" + process $proc$libresoc.v:48209$2895 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48414.5-48414.29" + attribute \src "libresoc.v:48210.5-48210.29" switch \initial - attribute \src "libresoc.v:48414.9-48414.17" + attribute \src "libresoc.v:48210.9-48210.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84285,7 +84081,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84301,24 +84097,24 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] end - attribute \src "libresoc.v:48442.3-48470.6" - process $proc$libresoc.v:48442$2896 + attribute \src "libresoc.v:48238.3-48266.6" + process $proc$libresoc.v:48238$2896 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:48443.5-48443.29" + attribute \src "libresoc.v:48239.5-48239.29" switch \initial - attribute \src "libresoc.v:48443.9-48443.17" + attribute \src "libresoc.v:48239.9-48239.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84330,7 +84126,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84346,24 +84142,24 @@ module \core sync always update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] end - attribute \src "libresoc.v:48471.3-48499.6" - process $proc$libresoc.v:48471$2897 + attribute \src "libresoc.v:48267.3-48295.6" + process $proc$libresoc.v:48267$2897 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48472.5-48472.29" + attribute \src "libresoc.v:48268.5-48268.29" switch \initial - attribute \src "libresoc.v:48472.9-48472.17" + attribute \src "libresoc.v:48268.9-48268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84375,7 +84171,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84391,24 +84187,24 @@ module \core sync always update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] end - attribute \src "libresoc.v:48500.3-48528.6" - process $proc$libresoc.v:48500$2898 + attribute \src "libresoc.v:48296.3-48324.6" + process $proc$libresoc.v:48296$2898 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:48501.5-48501.29" + attribute \src "libresoc.v:48297.5-48297.29" switch \initial - attribute \src "libresoc.v:48501.9-48501.17" + attribute \src "libresoc.v:48297.9-48297.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84420,7 +84216,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84436,24 +84232,24 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] end - attribute \src "libresoc.v:48529.3-48557.6" - process $proc$libresoc.v:48529$2899 + attribute \src "libresoc.v:48325.3-48353.6" + process $proc$libresoc.v:48325$2899 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48530.5-48530.29" + attribute \src "libresoc.v:48326.5-48326.29" switch \initial - attribute \src "libresoc.v:48530.9-48530.17" + attribute \src "libresoc.v:48326.9-48326.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84465,7 +84261,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84481,731 +84277,731 @@ module \core sync always update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] end - connect \$1001 $ternary$libresoc.v:42111$1506_Y - connect \$1003 $and$libresoc.v:42112$1507_Y - connect \$1006 $and$libresoc.v:42113$1508_Y - connect \$1010 $not$libresoc.v:42114$1509_Y - connect \$1012 $and$libresoc.v:42115$1510_Y - connect \$1019 $and$libresoc.v:42116$1511_Y - connect \$1022 $ternary$libresoc.v:42117$1512_Y - connect \$1024 $and$libresoc.v:42118$1513_Y - connect \$1027 $and$libresoc.v:42119$1514_Y - connect \$1031 $not$libresoc.v:42120$1515_Y - connect \$1033 $and$libresoc.v:42121$1516_Y - connect \$1037 $and$libresoc.v:42122$1517_Y - connect \$1040 $ternary$libresoc.v:42123$1518_Y - connect \$1042 $and$libresoc.v:42124$1519_Y - connect \$1045 $and$libresoc.v:42125$1520_Y - connect \$1049 $not$libresoc.v:42126$1521_Y - connect \$1051 $and$libresoc.v:42127$1522_Y - connect \$1059 $and$libresoc.v:42128$1523_Y - connect \$1062 $ternary$libresoc.v:42129$1524_Y - connect \$1064 $and$libresoc.v:42130$1525_Y - connect \$1067 $and$libresoc.v:42131$1526_Y - connect \$1071 $not$libresoc.v:42132$1527_Y - connect \$1073 $and$libresoc.v:42133$1528_Y - connect \$1079 $and$libresoc.v:42134$1529_Y - connect \$1082 $ternary$libresoc.v:42135$1530_Y - connect \$1084 $and$libresoc.v:42136$1531_Y - connect \$1087 $and$libresoc.v:42137$1532_Y - connect \$1091 $not$libresoc.v:42138$1533_Y - connect \$1093 $and$libresoc.v:42139$1534_Y - connect \$1099 $and$libresoc.v:42140$1535_Y - connect \$1102 $ternary$libresoc.v:42141$1536_Y - connect \$1104 $and$libresoc.v:42142$1537_Y - connect \$1107 $and$libresoc.v:42143$1538_Y - connect \$1111 $not$libresoc.v:42144$1539_Y - connect \$1113 $and$libresoc.v:42145$1540_Y - connect \$1118 $and$libresoc.v:42146$1541_Y - connect \$1121 $ternary$libresoc.v:42147$1542_Y - connect \$1123 $and$libresoc.v:42148$1543_Y - connect \$1126 $and$libresoc.v:42149$1544_Y - connect \$1130 $not$libresoc.v:42150$1545_Y - connect \$1132 $and$libresoc.v:42151$1546_Y - connect \$1136 $and$libresoc.v:42152$1547_Y - connect \$1139 $ternary$libresoc.v:42153$1548_Y - connect \$1141 $and$libresoc.v:42154$1549_Y - connect \$1144 $and$libresoc.v:42155$1550_Y - connect \$1147 $not$libresoc.v:42156$1551_Y - connect \$1149 $and$libresoc.v:42157$1552_Y - connect \$1152 $and$libresoc.v:42158$1553_Y - connect \$1155 $ternary$libresoc.v:42159$1554_Y - connect \$1158 $or$libresoc.v:42160$1555_Y - connect \$1160 $or$libresoc.v:42161$1556_Y - connect \$1162 $or$libresoc.v:42162$1557_Y - connect \$1164 $or$libresoc.v:42163$1558_Y - connect \$1166 $or$libresoc.v:42164$1559_Y - connect \$1168 $or$libresoc.v:42165$1560_Y - connect \$1170 $or$libresoc.v:42166$1561_Y - connect \$1172 $or$libresoc.v:42167$1562_Y - connect \$1174 $or$libresoc.v:42168$1563_Y - connect \$1177 $or$libresoc.v:42169$1564_Y - connect \$1179 $or$libresoc.v:42170$1565_Y - connect \$1181 $or$libresoc.v:42171$1566_Y - connect \$1183 $or$libresoc.v:42172$1567_Y - connect \$1185 $or$libresoc.v:42173$1568_Y - connect \$1187 $or$libresoc.v:42174$1569_Y - connect \$1189 $or$libresoc.v:42175$1570_Y - connect \$1191 $or$libresoc.v:42176$1571_Y - connect \$1193 $or$libresoc.v:42177$1572_Y - connect \$1195 $or$libresoc.v:42178$1573_Y - connect \$1197 $or$libresoc.v:42179$1574_Y - connect \$1199 $or$libresoc.v:42180$1575_Y - connect \$1201 $or$libresoc.v:42181$1576_Y - connect \$1203 $or$libresoc.v:42182$1577_Y - connect \$1205 $or$libresoc.v:42183$1578_Y - connect \$1207 $or$libresoc.v:42184$1579_Y - connect \$1209 $or$libresoc.v:42185$1580_Y - connect \$1211 $or$libresoc.v:42186$1581_Y - connect \$1213 $and$libresoc.v:42187$1582_Y - connect \$1215 $and$libresoc.v:42188$1583_Y - connect \$1218 $and$libresoc.v:42189$1584_Y - connect \$1221 $not$libresoc.v:42190$1585_Y - connect \$1223 $and$libresoc.v:42191$1586_Y - connect \$1226 $and$libresoc.v:42192$1587_Y - connect \$1229 $ternary$libresoc.v:42193$1588_Y - connect \$1231 $and$libresoc.v:42194$1589_Y - connect \$1233 $and$libresoc.v:42195$1590_Y - connect \$1235 $and$libresoc.v:42196$1591_Y - connect \$1237 $and$libresoc.v:42197$1592_Y - connect \$1239 $and$libresoc.v:42198$1593_Y - connect \$1241 $and$libresoc.v:42199$1594_Y - connect \$1243 $and$libresoc.v:42200$1595_Y - connect \$1246 $and$libresoc.v:42201$1596_Y - connect \$1249 $not$libresoc.v:42202$1597_Y - connect \$1251 $and$libresoc.v:42203$1598_Y - connect \$1254 $and$libresoc.v:42204$1599_Y - connect \$1257 $sub$libresoc.v:42205$1600_Y - connect \$1259 $sshl$libresoc.v:42206$1601_Y - connect \$1261 $ternary$libresoc.v:42207$1602_Y - connect \$1263 $and$libresoc.v:42208$1603_Y - connect \$1266 $and$libresoc.v:42209$1604_Y - connect \$1269 $not$libresoc.v:42210$1605_Y - connect \$1271 $and$libresoc.v:42211$1606_Y - connect \$1274 $and$libresoc.v:42212$1607_Y - connect \$1277 $sub$libresoc.v:42213$1608_Y - connect \$1279 $sshl$libresoc.v:42214$1609_Y - connect \$1281 $ternary$libresoc.v:42215$1610_Y - connect \$1283 $and$libresoc.v:42216$1611_Y - connect \$1286 $and$libresoc.v:42217$1612_Y - connect \$1289 $not$libresoc.v:42218$1613_Y - connect \$1291 $and$libresoc.v:42219$1614_Y - connect \$1294 $and$libresoc.v:42220$1615_Y - connect \$1297 $sub$libresoc.v:42221$1616_Y - connect \$1299 $sshl$libresoc.v:42222$1617_Y - connect \$1301 $ternary$libresoc.v:42223$1618_Y - connect \$1303 $and$libresoc.v:42224$1619_Y - connect \$1306 $and$libresoc.v:42225$1620_Y - connect \$1309 $not$libresoc.v:42226$1621_Y - connect \$1311 $and$libresoc.v:42227$1622_Y - connect \$1314 $and$libresoc.v:42228$1623_Y - connect \$1317 $sub$libresoc.v:42229$1624_Y - connect \$1319 $sshl$libresoc.v:42230$1625_Y - connect \$1321 $ternary$libresoc.v:42231$1626_Y - connect \$1323 $and$libresoc.v:42232$1627_Y - connect \$1326 $and$libresoc.v:42233$1628_Y - connect \$1329 $not$libresoc.v:42234$1629_Y - connect \$1331 $and$libresoc.v:42235$1630_Y - connect \$1334 $and$libresoc.v:42236$1631_Y - connect \$1337 $sub$libresoc.v:42237$1632_Y - connect \$1339 $sshl$libresoc.v:42238$1633_Y - connect \$1341 $ternary$libresoc.v:42239$1634_Y - connect \$1343 $and$libresoc.v:42240$1635_Y - connect \$1346 $and$libresoc.v:42241$1636_Y - connect \$1349 $not$libresoc.v:42242$1637_Y - connect \$1351 $and$libresoc.v:42243$1638_Y - connect \$1354 $and$libresoc.v:42244$1639_Y - connect \$1357 $sub$libresoc.v:42245$1640_Y - connect \$1359 $sshl$libresoc.v:42246$1641_Y - connect \$1361 $ternary$libresoc.v:42247$1642_Y - connect \$1363 $or$libresoc.v:42248$1643_Y - connect \$1365 $or$libresoc.v:42249$1644_Y - connect \$1367 $or$libresoc.v:42250$1645_Y - connect \$1369 $or$libresoc.v:42251$1646_Y - connect \$1371 $or$libresoc.v:42252$1647_Y - connect \$1374 $or$libresoc.v:42253$1648_Y - connect \$1376 $or$libresoc.v:42254$1649_Y - connect \$1378 $or$libresoc.v:42255$1650_Y - connect \$1380 $or$libresoc.v:42256$1651_Y - connect \$1382 $or$libresoc.v:42257$1652_Y - connect \$1384 $and$libresoc.v:42258$1653_Y - connect \$1386 $and$libresoc.v:42259$1654_Y - connect \$1388 $and$libresoc.v:42260$1655_Y - connect \$1390 $and$libresoc.v:42261$1656_Y - connect \$1393 $and$libresoc.v:42262$1657_Y - connect \$1396 $not$libresoc.v:42263$1658_Y - connect \$1398 $and$libresoc.v:42264$1659_Y - connect \$1401 $and$libresoc.v:42265$1660_Y - connect \$1404 $ternary$libresoc.v:42266$1661_Y - connect \$1406 $and$libresoc.v:42267$1662_Y - connect \$1409 $and$libresoc.v:42268$1663_Y - connect \$1412 $not$libresoc.v:42269$1664_Y - connect \$1414 $and$libresoc.v:42270$1665_Y - connect \$1417 $and$libresoc.v:42271$1666_Y - connect \$1420 $ternary$libresoc.v:42272$1667_Y - connect \$1422 $and$libresoc.v:42273$1668_Y - connect \$1425 $and$libresoc.v:42274$1669_Y - connect \$1428 $not$libresoc.v:42275$1670_Y - connect \$1430 $and$libresoc.v:42276$1671_Y - connect \$1433 $and$libresoc.v:42277$1672_Y - connect \$1436 $ternary$libresoc.v:42278$1673_Y - connect \$1438 $or$libresoc.v:42279$1674_Y - connect \$1440 $or$libresoc.v:42280$1675_Y - connect \$1443 $or$libresoc.v:42281$1676_Y - connect \$1445 $or$libresoc.v:42282$1677_Y - connect \$1442 $pos$libresoc.v:42283$1679_Y - connect \$1448 $and$libresoc.v:42284$1680_Y - connect \$1450 $and$libresoc.v:42285$1681_Y - connect \$1452 $and$libresoc.v:42286$1682_Y - connect \$1454 $and$libresoc.v:42287$1683_Y - connect \$1456 $and$libresoc.v:42288$1684_Y - connect \$1459 $and$libresoc.v:42289$1685_Y - connect \$1462 $not$libresoc.v:42290$1686_Y - connect \$1464 $and$libresoc.v:42291$1687_Y - connect \$1467 $and$libresoc.v:42292$1688_Y - connect \$1470 $ternary$libresoc.v:42293$1689_Y - connect \$1472 $and$libresoc.v:42294$1690_Y - connect \$1475 $and$libresoc.v:42295$1691_Y - connect \$1478 $not$libresoc.v:42296$1692_Y - connect \$1480 $and$libresoc.v:42297$1693_Y - connect \$1483 $and$libresoc.v:42298$1694_Y - connect \$1486 $ternary$libresoc.v:42299$1695_Y - connect \$1488 $and$libresoc.v:42300$1696_Y - connect \$1491 $and$libresoc.v:42301$1697_Y - connect \$1494 $not$libresoc.v:42302$1698_Y - connect \$1496 $and$libresoc.v:42303$1699_Y - connect \$1499 $and$libresoc.v:42304$1700_Y - connect \$1502 $ternary$libresoc.v:42305$1701_Y - connect \$1504 $and$libresoc.v:42306$1702_Y - connect \$1507 $and$libresoc.v:42307$1703_Y - connect \$1510 $not$libresoc.v:42308$1704_Y - connect \$1512 $and$libresoc.v:42309$1705_Y - connect \$1515 $and$libresoc.v:42310$1706_Y - connect \$1518 $ternary$libresoc.v:42311$1707_Y - connect \$1520 $or$libresoc.v:42312$1708_Y - connect \$1522 $or$libresoc.v:42313$1709_Y - connect \$1524 $or$libresoc.v:42314$1710_Y - connect \$1526 $or$libresoc.v:42315$1711_Y - connect \$1528 $or$libresoc.v:42316$1712_Y - connect \$1530 $or$libresoc.v:42317$1713_Y - connect \$1532 $and$libresoc.v:42318$1714_Y - connect \$1534 $and$libresoc.v:42319$1715_Y - connect \$1536 $and$libresoc.v:42320$1716_Y - connect \$1538 $and$libresoc.v:42321$1717_Y - connect \$1540 $and$libresoc.v:42322$1718_Y - connect \$1543 $and$libresoc.v:42323$1719_Y - connect \$1546 $not$libresoc.v:42324$1720_Y - connect \$1548 $and$libresoc.v:42325$1721_Y - connect \$1551 $and$libresoc.v:42326$1722_Y - connect \$1554 $ternary$libresoc.v:42327$1723_Y - connect \$1556 $and$libresoc.v:42328$1724_Y - connect \$1559 $and$libresoc.v:42329$1725_Y - connect \$1562 $not$libresoc.v:42330$1726_Y - connect \$1564 $and$libresoc.v:42331$1727_Y - connect \$1567 $and$libresoc.v:42332$1728_Y - connect \$1570 $ternary$libresoc.v:42333$1729_Y - connect \$1572 $and$libresoc.v:42334$1730_Y - connect \$1575 $and$libresoc.v:42335$1731_Y - connect \$1578 $not$libresoc.v:42336$1732_Y - connect \$1580 $and$libresoc.v:42337$1733_Y - connect \$1583 $and$libresoc.v:42338$1734_Y - connect \$1586 $ternary$libresoc.v:42339$1735_Y - connect \$1588 $and$libresoc.v:42340$1736_Y - connect \$1591 $and$libresoc.v:42341$1737_Y - connect \$1594 $not$libresoc.v:42342$1738_Y - connect \$1596 $and$libresoc.v:42343$1739_Y - connect \$1599 $and$libresoc.v:42344$1740_Y - connect \$1602 $ternary$libresoc.v:42345$1741_Y - connect \$1605 $or$libresoc.v:42346$1742_Y - connect \$1607 $or$libresoc.v:42347$1743_Y - connect \$1609 $or$libresoc.v:42348$1744_Y - connect \$1604 $pos$libresoc.v:42349$1746_Y - connect \$1613 $or$libresoc.v:42350$1747_Y - connect \$1615 $or$libresoc.v:42351$1748_Y - connect \$1617 $or$libresoc.v:42352$1749_Y - connect \$1612 $pos$libresoc.v:42353$1751_Y - connect \$1620 $and$libresoc.v:42354$1752_Y - connect \$1622 $and$libresoc.v:42355$1753_Y - connect \$1624 $and$libresoc.v:42356$1754_Y - connect \$1626 $and$libresoc.v:42357$1755_Y - connect \$1628 $and$libresoc.v:42358$1756_Y - connect \$1630 $and$libresoc.v:42359$1757_Y - connect \$1633 $and$libresoc.v:42360$1758_Y - connect \$1637 $not$libresoc.v:42361$1759_Y - connect \$1639 $and$libresoc.v:42362$1760_Y - connect \$1644 $and$libresoc.v:42363$1761_Y - connect \$1647 $ternary$libresoc.v:42364$1762_Y - connect \$1649 $and$libresoc.v:42365$1763_Y - connect \$1652 $and$libresoc.v:42366$1764_Y - connect \$1655 $not$libresoc.v:42367$1765_Y - connect \$1657 $and$libresoc.v:42368$1766_Y - connect \$1660 $and$libresoc.v:42369$1767_Y - connect \$1663 $ternary$libresoc.v:42370$1768_Y - connect \$1665 $and$libresoc.v:42371$1769_Y - connect \$1668 $and$libresoc.v:42372$1770_Y - connect \$1671 $not$libresoc.v:42373$1771_Y - connect \$1673 $and$libresoc.v:42374$1772_Y - connect \$1676 $and$libresoc.v:42375$1773_Y - connect \$1679 $ternary$libresoc.v:42376$1774_Y - connect \$1681 $and$libresoc.v:42377$1775_Y - connect \$1684 $and$libresoc.v:42378$1776_Y - connect \$1687 $not$libresoc.v:42379$1777_Y - connect \$1689 $and$libresoc.v:42380$1778_Y - connect \$1692 $and$libresoc.v:42381$1779_Y - connect \$1695 $ternary$libresoc.v:42382$1780_Y - connect \$1697 $and$libresoc.v:42383$1781_Y - connect \$1700 $and$libresoc.v:42384$1782_Y - connect \$1703 $not$libresoc.v:42385$1783_Y - connect \$1705 $and$libresoc.v:42386$1784_Y - connect \$1708 $and$libresoc.v:42387$1785_Y - connect \$1711 $ternary$libresoc.v:42388$1786_Y - connect \$1713 $or$libresoc.v:42389$1787_Y - connect \$1715 $or$libresoc.v:42390$1788_Y - connect \$1717 $or$libresoc.v:42391$1789_Y - connect \$1719 $or$libresoc.v:42392$1790_Y - connect \$1721 $or$libresoc.v:42393$1791_Y - connect \$1723 $or$libresoc.v:42394$1792_Y - connect \$1725 $or$libresoc.v:42395$1793_Y - connect \$1727 $or$libresoc.v:42396$1794_Y - connect \$1729 $or$libresoc.v:42397$1795_Y - connect \$1731 $or$libresoc.v:42398$1796_Y - connect \$1733 $or$libresoc.v:42399$1797_Y - connect \$1735 $or$libresoc.v:42400$1798_Y - connect \$1737 $and$libresoc.v:42401$1799_Y - connect \$1739 $and$libresoc.v:42402$1800_Y - connect \$1741 $and$libresoc.v:42403$1801_Y - connect \$1744 $and$libresoc.v:42404$1802_Y - connect \$1747 $not$libresoc.v:42405$1803_Y - connect \$1749 $and$libresoc.v:42406$1804_Y - connect \$1752 $and$libresoc.v:42407$1805_Y - connect \$1755 $ternary$libresoc.v:42408$1806_Y - connect \$1757 $and$libresoc.v:42409$1807_Y - connect \$1760 $and$libresoc.v:42410$1808_Y - connect \$1763 $not$libresoc.v:42411$1809_Y - connect \$1765 $and$libresoc.v:42412$1810_Y - connect \$1768 $and$libresoc.v:42413$1811_Y - connect \$1771 $ternary$libresoc.v:42414$1812_Y - connect \$1773 $or$libresoc.v:42415$1813_Y - connect \$1776 $or$libresoc.v:42416$1814_Y - connect \$1775 $pos$libresoc.v:42417$1816_Y - connect \$1779 $and$libresoc.v:42418$1817_Y - connect \$1781 $and$libresoc.v:42419$1818_Y - connect \$1784 $and$libresoc.v:42420$1819_Y - connect \$1787 $not$libresoc.v:42421$1820_Y - connect \$1789 $and$libresoc.v:42422$1821_Y - connect \$1792 $and$libresoc.v:42423$1822_Y - connect \$1795 $ternary$libresoc.v:42424$1823_Y - connect \$1797 $pos$libresoc.v:42425$1825_Y - connect \$1799 $and$libresoc.v:42426$1826_Y - connect \$1801 $and$libresoc.v:42427$1827_Y - connect \$1804 $and$libresoc.v:42428$1828_Y - connect \$1807 $not$libresoc.v:42429$1829_Y - connect \$1809 $and$libresoc.v:42430$1830_Y - connect \$1812 $and$libresoc.v:42431$1831_Y - connect \$1815 $ternary$libresoc.v:42432$1832_Y - connect \$182 $and$libresoc.v:42433$1833_Y - connect \$181 $reduce_or$libresoc.v:42434$1834_Y - connect \$186 $and$libresoc.v:42435$1835_Y - connect \$185 $reduce_or$libresoc.v:42436$1836_Y - connect \$190 $and$libresoc.v:42437$1837_Y - connect \$189 $reduce_or$libresoc.v:42438$1838_Y - connect \$194 $and$libresoc.v:42439$1839_Y - connect \$193 $reduce_or$libresoc.v:42440$1840_Y - connect \$198 $and$libresoc.v:42441$1841_Y - connect \$197 $reduce_or$libresoc.v:42442$1842_Y - connect \$202 $and$libresoc.v:42443$1843_Y - connect \$201 $reduce_or$libresoc.v:42444$1844_Y - connect \$206 $and$libresoc.v:42445$1845_Y - connect \$205 $reduce_or$libresoc.v:42446$1846_Y - connect \$210 $and$libresoc.v:42447$1847_Y - connect \$209 $reduce_or$libresoc.v:42448$1848_Y - connect \$214 $and$libresoc.v:42449$1849_Y - connect \$213 $reduce_or$libresoc.v:42450$1850_Y - connect \$218 $and$libresoc.v:42451$1851_Y - connect \$217 $reduce_or$libresoc.v:42452$1852_Y - connect \$221 $ne$libresoc.v:42453$1853_Y - connect \$224 $sub$libresoc.v:42454$1854_Y - connect \$226 $ne$libresoc.v:42455$1855_Y - connect \$229 $and$libresoc.v:42456$1856_Y - connect \$231 $and$libresoc.v:42457$1857_Y - connect \$233 $eq$libresoc.v:42458$1858_Y - connect \$235 $or$libresoc.v:42459$1859_Y - connect \$237 $and$libresoc.v:42460$1860_Y - connect \$239 $or$libresoc.v:42461$1861_Y - connect \$241 $eq$libresoc.v:42462$1862_Y - connect \$243 $and$libresoc.v:42463$1863_Y - connect \$245 $eq$libresoc.v:42464$1864_Y - connect \$247 $or$libresoc.v:42465$1865_Y - connect \$228 $not$libresoc.v:42466$1866_Y - connect \$250 $not$libresoc.v:42467$1867_Y - connect \$252 $not$libresoc.v:42468$1868_Y - connect \$254 $not$libresoc.v:42469$1869_Y - connect \$257 $and$libresoc.v:42470$1870_Y - connect \$259 $and$libresoc.v:42471$1871_Y - connect \$261 $eq$libresoc.v:42472$1872_Y - connect \$263 $or$libresoc.v:42473$1873_Y - connect \$265 $and$libresoc.v:42474$1874_Y - connect \$267 $or$libresoc.v:42475$1875_Y - connect \$256 $not$libresoc.v:42476$1876_Y - connect \$271 $and$libresoc.v:42477$1877_Y - connect \$273 $and$libresoc.v:42478$1878_Y - connect \$275 $eq$libresoc.v:42479$1879_Y - connect \$277 $or$libresoc.v:42480$1880_Y - connect \$279 $and$libresoc.v:42481$1881_Y - connect \$281 $or$libresoc.v:42482$1882_Y - connect \$283 $and$libresoc.v:42483$1883_Y - connect \$285 $and$libresoc.v:42484$1884_Y - connect \$287 $eq$libresoc.v:42485$1885_Y - connect \$289 $or$libresoc.v:42486$1886_Y - connect \$291 $eq$libresoc.v:42487$1887_Y - connect \$293 $and$libresoc.v:42488$1888_Y - connect \$295 $eq$libresoc.v:42489$1889_Y - connect \$297 $or$libresoc.v:42490$1890_Y - connect \$270 $not$libresoc.v:42491$1891_Y - connect \$301 $and$libresoc.v:42492$1892_Y - connect \$303 $and$libresoc.v:42493$1893_Y - connect \$305 $eq$libresoc.v:42494$1894_Y - connect \$307 $or$libresoc.v:42495$1895_Y - connect \$309 $and$libresoc.v:42496$1896_Y - connect \$311 $or$libresoc.v:42497$1897_Y - connect \$300 $not$libresoc.v:42498$1898_Y - connect \$315 $and$libresoc.v:42499$1899_Y - connect \$317 $and$libresoc.v:42500$1900_Y - connect \$319 $eq$libresoc.v:42501$1901_Y - connect \$321 $or$libresoc.v:42502$1902_Y - connect \$323 $and$libresoc.v:42503$1903_Y - connect \$325 $or$libresoc.v:42504$1904_Y - connect \$314 $not$libresoc.v:42505$1905_Y - connect \$329 $and$libresoc.v:42506$1906_Y - connect \$331 $and$libresoc.v:42507$1907_Y - connect \$333 $eq$libresoc.v:42508$1908_Y - connect \$335 $or$libresoc.v:42509$1909_Y - connect \$337 $and$libresoc.v:42510$1910_Y - connect \$339 $or$libresoc.v:42511$1911_Y - connect \$341 $eq$libresoc.v:42512$1912_Y - connect \$343 $and$libresoc.v:42513$1913_Y - connect \$345 $eq$libresoc.v:42514$1914_Y - connect \$347 $or$libresoc.v:42515$1915_Y - connect \$328 $not$libresoc.v:42516$1916_Y - connect \$350 $not$libresoc.v:42517$1917_Y - connect \$352 $and$libresoc.v:42518$1918_Y - connect \$354 $and$libresoc.v:42519$1919_Y - connect \$356 $not$libresoc.v:42520$1920_Y - connect \$358 $and$libresoc.v:42521$1921_Y - connect \$360 $and$libresoc.v:42522$1922_Y - connect \$362 $ternary$libresoc.v:42523$1923_Y - connect \$364 $and$libresoc.v:42524$1924_Y - connect \$366 $and$libresoc.v:42525$1925_Y - connect \$368 $not$libresoc.v:42526$1926_Y - connect \$370 $and$libresoc.v:42527$1927_Y - connect \$372 $and$libresoc.v:42528$1928_Y - connect \$374 $ternary$libresoc.v:42529$1929_Y - connect \$376 $and$libresoc.v:42530$1930_Y - connect \$378 $and$libresoc.v:42531$1931_Y - connect \$380 $not$libresoc.v:42532$1932_Y - connect \$382 $and$libresoc.v:42533$1933_Y - connect \$384 $and$libresoc.v:42534$1934_Y - connect \$386 $ternary$libresoc.v:42535$1935_Y - connect \$388 $and$libresoc.v:42536$1936_Y - connect \$390 $and$libresoc.v:42537$1937_Y - connect \$392 $not$libresoc.v:42538$1938_Y - connect \$394 $and$libresoc.v:42539$1939_Y - connect \$396 $and$libresoc.v:42540$1940_Y - connect \$398 $ternary$libresoc.v:42541$1941_Y - connect \$400 $and$libresoc.v:42542$1942_Y - connect \$402 $and$libresoc.v:42543$1943_Y - connect \$404 $not$libresoc.v:42544$1944_Y - connect \$406 $and$libresoc.v:42545$1945_Y - connect \$408 $and$libresoc.v:42546$1946_Y - connect \$410 $ternary$libresoc.v:42547$1947_Y - connect \$412 $and$libresoc.v:42548$1948_Y - connect \$414 $and$libresoc.v:42549$1949_Y - connect \$416 $not$libresoc.v:42550$1950_Y - connect \$418 $and$libresoc.v:42551$1951_Y - connect \$420 $and$libresoc.v:42552$1952_Y - connect \$422 $ternary$libresoc.v:42553$1953_Y - connect \$424 $and$libresoc.v:42554$1954_Y - connect \$426 $and$libresoc.v:42555$1955_Y - connect \$428 $not$libresoc.v:42556$1956_Y - connect \$430 $and$libresoc.v:42557$1957_Y - connect \$432 $and$libresoc.v:42558$1958_Y - connect \$434 $ternary$libresoc.v:42559$1959_Y - connect \$436 $and$libresoc.v:42560$1960_Y - connect \$438 $and$libresoc.v:42561$1961_Y - connect \$440 $not$libresoc.v:42562$1962_Y - connect \$442 $and$libresoc.v:42563$1963_Y - connect \$444 $and$libresoc.v:42564$1964_Y - connect \$446 $ternary$libresoc.v:42565$1965_Y - connect \$448 $and$libresoc.v:42566$1966_Y - connect \$450 $and$libresoc.v:42567$1967_Y - connect \$452 $not$libresoc.v:42568$1968_Y - connect \$454 $and$libresoc.v:42569$1969_Y - connect \$456 $and$libresoc.v:42570$1970_Y - connect \$458 $ternary$libresoc.v:42571$1971_Y - connect \$460 $and$libresoc.v:42572$1972_Y - connect \$462 $and$libresoc.v:42573$1973_Y - connect \$464 $not$libresoc.v:42574$1974_Y - connect \$466 $and$libresoc.v:42575$1975_Y - connect \$468 $and$libresoc.v:42576$1976_Y - connect \$470 $ternary$libresoc.v:42577$1977_Y - connect \$472 $and$libresoc.v:42578$1978_Y - connect \$474 $and$libresoc.v:42579$1979_Y - connect \$476 $not$libresoc.v:42580$1980_Y - connect \$478 $and$libresoc.v:42581$1981_Y - connect \$480 $and$libresoc.v:42582$1982_Y - connect \$482 $ternary$libresoc.v:42583$1983_Y - connect \$484 $and$libresoc.v:42584$1984_Y - connect \$486 $and$libresoc.v:42585$1985_Y - connect \$488 $not$libresoc.v:42586$1986_Y - connect \$490 $and$libresoc.v:42587$1987_Y - connect \$492 $and$libresoc.v:42588$1988_Y - connect \$494 $ternary$libresoc.v:42589$1989_Y - connect \$496 $and$libresoc.v:42590$1990_Y - connect \$498 $and$libresoc.v:42591$1991_Y - connect \$500 $not$libresoc.v:42592$1992_Y - connect \$502 $and$libresoc.v:42593$1993_Y - connect \$504 $and$libresoc.v:42594$1994_Y - connect \$506 $ternary$libresoc.v:42595$1995_Y - connect \$508 $and$libresoc.v:42596$1996_Y - connect \$510 $and$libresoc.v:42597$1997_Y - connect \$512 $not$libresoc.v:42598$1998_Y - connect \$514 $and$libresoc.v:42599$1999_Y - connect \$516 $and$libresoc.v:42600$2000_Y - connect \$518 $ternary$libresoc.v:42601$2001_Y - connect \$520 $and$libresoc.v:42602$2002_Y - connect \$522 $and$libresoc.v:42603$2003_Y - connect \$524 $not$libresoc.v:42604$2004_Y - connect \$526 $and$libresoc.v:42605$2005_Y - connect \$528 $and$libresoc.v:42606$2006_Y - connect \$530 $ternary$libresoc.v:42607$2007_Y - connect \$532 $and$libresoc.v:42608$2008_Y - connect \$534 $and$libresoc.v:42609$2009_Y - connect \$536 $not$libresoc.v:42610$2010_Y - connect \$538 $and$libresoc.v:42611$2011_Y - connect \$540 $and$libresoc.v:42612$2012_Y - connect \$542 $ternary$libresoc.v:42613$2013_Y - connect \$544 $and$libresoc.v:42614$2014_Y - connect \$546 $and$libresoc.v:42615$2015_Y - connect \$548 $not$libresoc.v:42616$2016_Y - connect \$550 $and$libresoc.v:42617$2017_Y - connect \$552 $and$libresoc.v:42618$2018_Y - connect \$554 $ternary$libresoc.v:42619$2019_Y - connect \$556 $and$libresoc.v:42620$2020_Y - connect \$558 $and$libresoc.v:42621$2021_Y - connect \$560 $not$libresoc.v:42622$2022_Y - connect \$562 $and$libresoc.v:42623$2023_Y - connect \$564 $and$libresoc.v:42624$2024_Y - connect \$566 $ternary$libresoc.v:42625$2025_Y - connect \$568 $and$libresoc.v:42626$2026_Y - connect \$570 $and$libresoc.v:42627$2027_Y - connect \$572 $not$libresoc.v:42628$2028_Y - connect \$574 $and$libresoc.v:42629$2029_Y - connect \$576 $and$libresoc.v:42630$2030_Y - connect \$578 $ternary$libresoc.v:42631$2031_Y - connect \$581 $or$libresoc.v:42632$2032_Y - connect \$583 $or$libresoc.v:42633$2033_Y - connect \$585 $or$libresoc.v:42634$2034_Y - connect \$587 $or$libresoc.v:42635$2035_Y - connect \$589 $or$libresoc.v:42636$2036_Y - connect \$591 $or$libresoc.v:42637$2037_Y - connect \$593 $or$libresoc.v:42638$2038_Y - connect \$595 $or$libresoc.v:42639$2039_Y - connect \$597 $or$libresoc.v:42640$2040_Y - connect \$599 $or$libresoc.v:42641$2041_Y - connect \$601 $or$libresoc.v:42642$2042_Y - connect \$603 $or$libresoc.v:42643$2043_Y - connect \$605 $or$libresoc.v:42644$2044_Y - connect \$607 $or$libresoc.v:42645$2045_Y - connect \$609 $or$libresoc.v:42646$2046_Y - connect \$611 $or$libresoc.v:42647$2047_Y - connect \$613 $or$libresoc.v:42648$2048_Y - connect \$615 $or$libresoc.v:42649$2049_Y - connect \$617 $reduce_or$libresoc.v:42650$2050_Y - connect \$619 $and$libresoc.v:42651$2051_Y - connect \$621 $and$libresoc.v:42652$2052_Y - connect \$623 $eq$libresoc.v:42653$2053_Y - connect \$625 $or$libresoc.v:42654$2054_Y - connect \$627 $and$libresoc.v:42655$2055_Y - connect \$629 $or$libresoc.v:42656$2056_Y - connect \$631 $and$libresoc.v:42657$2057_Y - connect \$633 $and$libresoc.v:42658$2058_Y - connect \$635 $not$libresoc.v:42659$2059_Y - connect \$637 $and$libresoc.v:42660$2060_Y - connect \$639 $and$libresoc.v:42661$2061_Y - connect \$641 $ternary$libresoc.v:42662$2062_Y - connect \$643 $and$libresoc.v:42663$2063_Y - connect \$645 $and$libresoc.v:42664$2064_Y - connect \$647 $not$libresoc.v:42665$2065_Y - connect \$649 $and$libresoc.v:42666$2066_Y - connect \$651 $and$libresoc.v:42667$2067_Y - connect \$653 $ternary$libresoc.v:42668$2068_Y - connect \$655 $and$libresoc.v:42669$2069_Y - connect \$657 $and$libresoc.v:42670$2070_Y - connect \$659 $not$libresoc.v:42671$2071_Y - connect \$661 $and$libresoc.v:42672$2072_Y - connect \$663 $and$libresoc.v:42673$2073_Y - connect \$665 $ternary$libresoc.v:42674$2074_Y - connect \$667 $and$libresoc.v:42675$2075_Y - connect \$669 $and$libresoc.v:42676$2076_Y - connect \$671 $not$libresoc.v:42677$2077_Y - connect \$673 $and$libresoc.v:42678$2078_Y - connect \$675 $and$libresoc.v:42679$2079_Y - connect \$677 $ternary$libresoc.v:42680$2080_Y - connect \$679 $and$libresoc.v:42681$2081_Y - connect \$681 $and$libresoc.v:42682$2082_Y - connect \$683 $not$libresoc.v:42683$2083_Y - connect \$685 $and$libresoc.v:42684$2084_Y - connect \$687 $and$libresoc.v:42685$2085_Y - connect \$689 $ternary$libresoc.v:42686$2086_Y - connect \$691 $and$libresoc.v:42687$2087_Y - connect \$693 $and$libresoc.v:42688$2088_Y - connect \$695 $not$libresoc.v:42689$2089_Y - connect \$697 $and$libresoc.v:42690$2090_Y - connect \$699 $and$libresoc.v:42691$2091_Y - connect \$701 $ternary$libresoc.v:42692$2092_Y - connect \$704 $or$libresoc.v:42693$2093_Y - connect \$706 $or$libresoc.v:42694$2094_Y - connect \$708 $or$libresoc.v:42695$2095_Y - connect \$710 $or$libresoc.v:42696$2096_Y - connect \$712 $or$libresoc.v:42697$2097_Y - connect \$703 $pos$libresoc.v:42698$2099_Y - connect \$715 $eq$libresoc.v:42699$2100_Y - connect \$717 $and$libresoc.v:42700$2101_Y - connect \$719 $eq$libresoc.v:42701$2102_Y - connect \$721 $or$libresoc.v:42702$2103_Y - connect \$723 $and$libresoc.v:42703$2104_Y - connect \$725 $and$libresoc.v:42704$2105_Y - connect \$727 $not$libresoc.v:42705$2106_Y - connect \$729 $and$libresoc.v:42706$2107_Y - connect \$731 $and$libresoc.v:42707$2108_Y - connect \$733 $ternary$libresoc.v:42708$2109_Y - connect \$735 $and$libresoc.v:42709$2110_Y - connect \$737 $and$libresoc.v:42710$2111_Y - connect \$739 $not$libresoc.v:42711$2112_Y - connect \$741 $and$libresoc.v:42712$2113_Y - connect \$743 $and$libresoc.v:42713$2114_Y - connect \$745 $ternary$libresoc.v:42714$2115_Y - connect \$747 $and$libresoc.v:42715$2116_Y - connect \$749 $and$libresoc.v:42716$2117_Y - connect \$751 $not$libresoc.v:42717$2118_Y - connect \$753 $and$libresoc.v:42718$2119_Y - connect \$755 $and$libresoc.v:42719$2120_Y - connect \$757 $ternary$libresoc.v:42720$2121_Y - connect \$760 $or$libresoc.v:42721$2122_Y - connect \$762 $or$libresoc.v:42722$2123_Y - connect \$759 $pos$libresoc.v:42723$2125_Y - connect \$765 $and$libresoc.v:42724$2126_Y - connect \$767 $and$libresoc.v:42725$2127_Y - connect \$769 $eq$libresoc.v:42726$2128_Y - connect \$771 $or$libresoc.v:42727$2129_Y - connect \$773 $and$libresoc.v:42728$2130_Y - connect \$775 $and$libresoc.v:42729$2131_Y - connect \$777 $not$libresoc.v:42730$2132_Y - connect \$779 $and$libresoc.v:42731$2133_Y - connect \$781 $and$libresoc.v:42732$2134_Y - connect \$783 $ternary$libresoc.v:42733$2135_Y - connect \$785 $and$libresoc.v:42734$2136_Y - connect \$787 $and$libresoc.v:42735$2137_Y - connect \$789 $not$libresoc.v:42736$2138_Y - connect \$791 $and$libresoc.v:42737$2139_Y - connect \$793 $and$libresoc.v:42738$2140_Y - connect \$795 $ternary$libresoc.v:42739$2141_Y - connect \$797 $and$libresoc.v:42740$2142_Y - connect \$799 $and$libresoc.v:42741$2143_Y - connect \$801 $not$libresoc.v:42742$2144_Y - connect \$803 $and$libresoc.v:42743$2145_Y - connect \$805 $and$libresoc.v:42744$2146_Y - connect \$807 $sub$libresoc.v:42745$2147_Y - connect \$809 $sshl$libresoc.v:42746$2148_Y - connect \$811 $ternary$libresoc.v:42747$2149_Y - connect \$813 $and$libresoc.v:42748$2150_Y - connect \$815 $and$libresoc.v:42749$2151_Y - connect \$817 $not$libresoc.v:42750$2152_Y - connect \$819 $and$libresoc.v:42751$2153_Y - connect \$821 $and$libresoc.v:42752$2154_Y - connect \$823 $sub$libresoc.v:42753$2155_Y - connect \$825 $sshl$libresoc.v:42754$2156_Y - connect \$827 $ternary$libresoc.v:42755$2157_Y - connect \$830 $or$libresoc.v:42756$2158_Y - connect \$832 $and$libresoc.v:42757$2159_Y - connect \$834 $and$libresoc.v:42758$2160_Y - connect \$836 $not$libresoc.v:42759$2161_Y - connect \$838 $and$libresoc.v:42760$2162_Y - connect \$840 $and$libresoc.v:42761$2163_Y - connect \$842 $sub$libresoc.v:42762$2164_Y - connect \$844 $sshl$libresoc.v:42763$2165_Y - connect \$846 $ternary$libresoc.v:42764$2166_Y - connect \$848 $and$libresoc.v:42765$2167_Y - connect \$850 $and$libresoc.v:42766$2168_Y - connect \$852 $not$libresoc.v:42767$2169_Y - connect \$854 $and$libresoc.v:42768$2170_Y - connect \$856 $and$libresoc.v:42769$2171_Y - connect \$858 $sub$libresoc.v:42770$2172_Y - connect \$860 $sshl$libresoc.v:42771$2173_Y - connect \$862 $ternary$libresoc.v:42772$2174_Y - connect \$864 $and$libresoc.v:42773$2175_Y - connect \$866 $and$libresoc.v:42774$2176_Y - connect \$868 $not$libresoc.v:42775$2177_Y - connect \$870 $and$libresoc.v:42776$2178_Y - connect \$872 $and$libresoc.v:42777$2179_Y - connect \$874 $ternary$libresoc.v:42778$2180_Y - connect \$876 $and$libresoc.v:42779$2181_Y - connect \$878 $and$libresoc.v:42780$2182_Y - connect \$880 $not$libresoc.v:42781$2183_Y - connect \$882 $and$libresoc.v:42782$2184_Y - connect \$884 $and$libresoc.v:42783$2185_Y - connect \$886 $ternary$libresoc.v:42784$2186_Y - connect \$888 $and$libresoc.v:42785$2187_Y - connect \$890 $and$libresoc.v:42786$2188_Y - connect \$892 $not$libresoc.v:42787$2189_Y - connect \$894 $and$libresoc.v:42788$2190_Y - connect \$896 $and$libresoc.v:42789$2191_Y - connect \$898 $ternary$libresoc.v:42790$2192_Y - connect \$900 $and$libresoc.v:42791$2193_Y - connect \$902 $and$libresoc.v:42792$2194_Y - connect \$904 $not$libresoc.v:42793$2195_Y - connect \$906 $and$libresoc.v:42794$2196_Y - connect \$908 $and$libresoc.v:42795$2197_Y - connect \$910 $ternary$libresoc.v:42796$2198_Y - connect \$912 $and$libresoc.v:42797$2199_Y - connect \$914 $and$libresoc.v:42798$2200_Y - connect \$916 $not$libresoc.v:42799$2201_Y - connect \$918 $and$libresoc.v:42800$2202_Y - connect \$920 $and$libresoc.v:42801$2203_Y - connect \$922 $ternary$libresoc.v:42802$2204_Y - connect \$924 $or$libresoc.v:42803$2205_Y - connect \$926 $or$libresoc.v:42804$2206_Y - connect \$928 $or$libresoc.v:42805$2207_Y - connect \$930 $or$libresoc.v:42806$2208_Y - connect \$932 $reduce_or$libresoc.v:42807$2209_Y - connect \$934 $and$libresoc.v:42808$2210_Y - connect \$936 $and$libresoc.v:42809$2211_Y - connect \$938 $not$libresoc.v:42810$2212_Y - connect \$940 $and$libresoc.v:42811$2213_Y - connect \$942 $and$libresoc.v:42812$2214_Y - connect \$944 $ternary$libresoc.v:42813$2215_Y - connect \$946 $reduce_or$libresoc.v:42814$2216_Y - connect \$948 $and$libresoc.v:42815$2217_Y - connect \$950 $and$libresoc.v:42816$2218_Y - connect \$952 $and$libresoc.v:42817$2219_Y - connect \$954 $and$libresoc.v:42818$2220_Y - connect \$956 $and$libresoc.v:42819$2221_Y - connect \$958 $and$libresoc.v:42820$2222_Y - connect \$960 $and$libresoc.v:42821$2223_Y - connect \$962 $and$libresoc.v:42822$2224_Y - connect \$964 $and$libresoc.v:42823$2225_Y - connect \$966 $and$libresoc.v:42824$2226_Y - connect \$968 $and$libresoc.v:42825$2227_Y - connect \$970 $and$libresoc.v:42826$2228_Y - connect \$972 $not$libresoc.v:42827$2229_Y - connect \$974 $and$libresoc.v:42828$2230_Y - connect \$980 $and$libresoc.v:42829$2231_Y - connect \$982 $ternary$libresoc.v:42830$2232_Y - connect \$984 $and$libresoc.v:42831$2233_Y - connect \$987 $and$libresoc.v:42832$2234_Y - connect \$991 $not$libresoc.v:42833$2235_Y - connect \$993 $and$libresoc.v:42834$2236_Y - connect \$998 $and$libresoc.v:42835$2237_Y + connect \$1001 $ternary$libresoc.v:41907$1506_Y + connect \$1003 $and$libresoc.v:41908$1507_Y + connect \$1006 $and$libresoc.v:41909$1508_Y + connect \$1010 $not$libresoc.v:41910$1509_Y + connect \$1012 $and$libresoc.v:41911$1510_Y + connect \$1019 $and$libresoc.v:41912$1511_Y + connect \$1022 $ternary$libresoc.v:41913$1512_Y + connect \$1024 $and$libresoc.v:41914$1513_Y + connect \$1027 $and$libresoc.v:41915$1514_Y + connect \$1031 $not$libresoc.v:41916$1515_Y + connect \$1033 $and$libresoc.v:41917$1516_Y + connect \$1037 $and$libresoc.v:41918$1517_Y + connect \$1040 $ternary$libresoc.v:41919$1518_Y + connect \$1042 $and$libresoc.v:41920$1519_Y + connect \$1045 $and$libresoc.v:41921$1520_Y + connect \$1049 $not$libresoc.v:41922$1521_Y + connect \$1051 $and$libresoc.v:41923$1522_Y + connect \$1059 $and$libresoc.v:41924$1523_Y + connect \$1062 $ternary$libresoc.v:41925$1524_Y + connect \$1064 $and$libresoc.v:41926$1525_Y + connect \$1067 $and$libresoc.v:41927$1526_Y + connect \$1071 $not$libresoc.v:41928$1527_Y + connect \$1073 $and$libresoc.v:41929$1528_Y + connect \$1079 $and$libresoc.v:41930$1529_Y + connect \$1082 $ternary$libresoc.v:41931$1530_Y + connect \$1084 $and$libresoc.v:41932$1531_Y + connect \$1087 $and$libresoc.v:41933$1532_Y + connect \$1091 $not$libresoc.v:41934$1533_Y + connect \$1093 $and$libresoc.v:41935$1534_Y + connect \$1099 $and$libresoc.v:41936$1535_Y + connect \$1102 $ternary$libresoc.v:41937$1536_Y + connect \$1104 $and$libresoc.v:41938$1537_Y + connect \$1107 $and$libresoc.v:41939$1538_Y + connect \$1111 $not$libresoc.v:41940$1539_Y + connect \$1113 $and$libresoc.v:41941$1540_Y + connect \$1118 $and$libresoc.v:41942$1541_Y + connect \$1121 $ternary$libresoc.v:41943$1542_Y + connect \$1123 $and$libresoc.v:41944$1543_Y + connect \$1126 $and$libresoc.v:41945$1544_Y + connect \$1130 $not$libresoc.v:41946$1545_Y + connect \$1132 $and$libresoc.v:41947$1546_Y + connect \$1136 $and$libresoc.v:41948$1547_Y + connect \$1139 $ternary$libresoc.v:41949$1548_Y + connect \$1141 $and$libresoc.v:41950$1549_Y + connect \$1144 $and$libresoc.v:41951$1550_Y + connect \$1147 $not$libresoc.v:41952$1551_Y + connect \$1149 $and$libresoc.v:41953$1552_Y + connect \$1152 $and$libresoc.v:41954$1553_Y + connect \$1155 $ternary$libresoc.v:41955$1554_Y + connect \$1158 $or$libresoc.v:41956$1555_Y + connect \$1160 $or$libresoc.v:41957$1556_Y + connect \$1162 $or$libresoc.v:41958$1557_Y + connect \$1164 $or$libresoc.v:41959$1558_Y + connect \$1166 $or$libresoc.v:41960$1559_Y + connect \$1168 $or$libresoc.v:41961$1560_Y + connect \$1170 $or$libresoc.v:41962$1561_Y + connect \$1172 $or$libresoc.v:41963$1562_Y + connect \$1174 $or$libresoc.v:41964$1563_Y + connect \$1177 $or$libresoc.v:41965$1564_Y + connect \$1179 $or$libresoc.v:41966$1565_Y + connect \$1181 $or$libresoc.v:41967$1566_Y + connect \$1183 $or$libresoc.v:41968$1567_Y + connect \$1185 $or$libresoc.v:41969$1568_Y + connect \$1187 $or$libresoc.v:41970$1569_Y + connect \$1189 $or$libresoc.v:41971$1570_Y + connect \$1191 $or$libresoc.v:41972$1571_Y + connect \$1193 $or$libresoc.v:41973$1572_Y + connect \$1195 $or$libresoc.v:41974$1573_Y + connect \$1197 $or$libresoc.v:41975$1574_Y + connect \$1199 $or$libresoc.v:41976$1575_Y + connect \$1201 $or$libresoc.v:41977$1576_Y + connect \$1203 $or$libresoc.v:41978$1577_Y + connect \$1205 $or$libresoc.v:41979$1578_Y + connect \$1207 $or$libresoc.v:41980$1579_Y + connect \$1209 $or$libresoc.v:41981$1580_Y + connect \$1211 $or$libresoc.v:41982$1581_Y + connect \$1213 $and$libresoc.v:41983$1582_Y + connect \$1215 $and$libresoc.v:41984$1583_Y + connect \$1218 $and$libresoc.v:41985$1584_Y + connect \$1221 $not$libresoc.v:41986$1585_Y + connect \$1223 $and$libresoc.v:41987$1586_Y + connect \$1226 $and$libresoc.v:41988$1587_Y + connect \$1229 $ternary$libresoc.v:41989$1588_Y + connect \$1231 $and$libresoc.v:41990$1589_Y + connect \$1233 $and$libresoc.v:41991$1590_Y + connect \$1235 $and$libresoc.v:41992$1591_Y + connect \$1237 $and$libresoc.v:41993$1592_Y + connect \$1239 $and$libresoc.v:41994$1593_Y + connect \$1241 $and$libresoc.v:41995$1594_Y + connect \$1243 $and$libresoc.v:41996$1595_Y + connect \$1246 $and$libresoc.v:41997$1596_Y + connect \$1249 $not$libresoc.v:41998$1597_Y + connect \$1251 $and$libresoc.v:41999$1598_Y + connect \$1254 $and$libresoc.v:42000$1599_Y + connect \$1257 $sub$libresoc.v:42001$1600_Y + connect \$1259 $sshl$libresoc.v:42002$1601_Y + connect \$1261 $ternary$libresoc.v:42003$1602_Y + connect \$1263 $and$libresoc.v:42004$1603_Y + connect \$1266 $and$libresoc.v:42005$1604_Y + connect \$1269 $not$libresoc.v:42006$1605_Y + connect \$1271 $and$libresoc.v:42007$1606_Y + connect \$1274 $and$libresoc.v:42008$1607_Y + connect \$1277 $sub$libresoc.v:42009$1608_Y + connect \$1279 $sshl$libresoc.v:42010$1609_Y + connect \$1281 $ternary$libresoc.v:42011$1610_Y + connect \$1283 $and$libresoc.v:42012$1611_Y + connect \$1286 $and$libresoc.v:42013$1612_Y + connect \$1289 $not$libresoc.v:42014$1613_Y + connect \$1291 $and$libresoc.v:42015$1614_Y + connect \$1294 $and$libresoc.v:42016$1615_Y + connect \$1297 $sub$libresoc.v:42017$1616_Y + connect \$1299 $sshl$libresoc.v:42018$1617_Y + connect \$1301 $ternary$libresoc.v:42019$1618_Y + connect \$1303 $and$libresoc.v:42020$1619_Y + connect \$1306 $and$libresoc.v:42021$1620_Y + connect \$1309 $not$libresoc.v:42022$1621_Y + connect \$1311 $and$libresoc.v:42023$1622_Y + connect \$1314 $and$libresoc.v:42024$1623_Y + connect \$1317 $sub$libresoc.v:42025$1624_Y + connect \$1319 $sshl$libresoc.v:42026$1625_Y + connect \$1321 $ternary$libresoc.v:42027$1626_Y + connect \$1323 $and$libresoc.v:42028$1627_Y + connect \$1326 $and$libresoc.v:42029$1628_Y + connect \$1329 $not$libresoc.v:42030$1629_Y + connect \$1331 $and$libresoc.v:42031$1630_Y + connect \$1334 $and$libresoc.v:42032$1631_Y + connect \$1337 $sub$libresoc.v:42033$1632_Y + connect \$1339 $sshl$libresoc.v:42034$1633_Y + connect \$1341 $ternary$libresoc.v:42035$1634_Y + connect \$1343 $and$libresoc.v:42036$1635_Y + connect \$1346 $and$libresoc.v:42037$1636_Y + connect \$1349 $not$libresoc.v:42038$1637_Y + connect \$1351 $and$libresoc.v:42039$1638_Y + connect \$1354 $and$libresoc.v:42040$1639_Y + connect \$1357 $sub$libresoc.v:42041$1640_Y + connect \$1359 $sshl$libresoc.v:42042$1641_Y + connect \$1361 $ternary$libresoc.v:42043$1642_Y + connect \$1363 $or$libresoc.v:42044$1643_Y + connect \$1365 $or$libresoc.v:42045$1644_Y + connect \$1367 $or$libresoc.v:42046$1645_Y + connect \$1369 $or$libresoc.v:42047$1646_Y + connect \$1371 $or$libresoc.v:42048$1647_Y + connect \$1374 $or$libresoc.v:42049$1648_Y + connect \$1376 $or$libresoc.v:42050$1649_Y + connect \$1378 $or$libresoc.v:42051$1650_Y + connect \$1380 $or$libresoc.v:42052$1651_Y + connect \$1382 $or$libresoc.v:42053$1652_Y + connect \$1384 $and$libresoc.v:42054$1653_Y + connect \$1386 $and$libresoc.v:42055$1654_Y + connect \$1388 $and$libresoc.v:42056$1655_Y + connect \$1390 $and$libresoc.v:42057$1656_Y + connect \$1393 $and$libresoc.v:42058$1657_Y + connect \$1396 $not$libresoc.v:42059$1658_Y + connect \$1398 $and$libresoc.v:42060$1659_Y + connect \$1401 $and$libresoc.v:42061$1660_Y + connect \$1404 $ternary$libresoc.v:42062$1661_Y + connect \$1406 $and$libresoc.v:42063$1662_Y + connect \$1409 $and$libresoc.v:42064$1663_Y + connect \$1412 $not$libresoc.v:42065$1664_Y + connect \$1414 $and$libresoc.v:42066$1665_Y + connect \$1417 $and$libresoc.v:42067$1666_Y + connect \$1420 $ternary$libresoc.v:42068$1667_Y + connect \$1422 $and$libresoc.v:42069$1668_Y + connect \$1425 $and$libresoc.v:42070$1669_Y + connect \$1428 $not$libresoc.v:42071$1670_Y + connect \$1430 $and$libresoc.v:42072$1671_Y + connect \$1433 $and$libresoc.v:42073$1672_Y + connect \$1436 $ternary$libresoc.v:42074$1673_Y + connect \$1438 $or$libresoc.v:42075$1674_Y + connect \$1440 $or$libresoc.v:42076$1675_Y + connect \$1443 $or$libresoc.v:42077$1676_Y + connect \$1445 $or$libresoc.v:42078$1677_Y + connect \$1442 $pos$libresoc.v:42079$1679_Y + connect \$1448 $and$libresoc.v:42080$1680_Y + connect \$1450 $and$libresoc.v:42081$1681_Y + connect \$1452 $and$libresoc.v:42082$1682_Y + connect \$1454 $and$libresoc.v:42083$1683_Y + connect \$1456 $and$libresoc.v:42084$1684_Y + connect \$1459 $and$libresoc.v:42085$1685_Y + connect \$1462 $not$libresoc.v:42086$1686_Y + connect \$1464 $and$libresoc.v:42087$1687_Y + connect \$1467 $and$libresoc.v:42088$1688_Y + connect \$1470 $ternary$libresoc.v:42089$1689_Y + connect \$1472 $and$libresoc.v:42090$1690_Y + connect \$1475 $and$libresoc.v:42091$1691_Y + connect \$1478 $not$libresoc.v:42092$1692_Y + connect \$1480 $and$libresoc.v:42093$1693_Y + connect \$1483 $and$libresoc.v:42094$1694_Y + connect \$1486 $ternary$libresoc.v:42095$1695_Y + connect \$1488 $and$libresoc.v:42096$1696_Y + connect \$1491 $and$libresoc.v:42097$1697_Y + connect \$1494 $not$libresoc.v:42098$1698_Y + connect \$1496 $and$libresoc.v:42099$1699_Y + connect \$1499 $and$libresoc.v:42100$1700_Y + connect \$1502 $ternary$libresoc.v:42101$1701_Y + connect \$1504 $and$libresoc.v:42102$1702_Y + connect \$1507 $and$libresoc.v:42103$1703_Y + connect \$1510 $not$libresoc.v:42104$1704_Y + connect \$1512 $and$libresoc.v:42105$1705_Y + connect \$1515 $and$libresoc.v:42106$1706_Y + connect \$1518 $ternary$libresoc.v:42107$1707_Y + connect \$1520 $or$libresoc.v:42108$1708_Y + connect \$1522 $or$libresoc.v:42109$1709_Y + connect \$1524 $or$libresoc.v:42110$1710_Y + connect \$1526 $or$libresoc.v:42111$1711_Y + connect \$1528 $or$libresoc.v:42112$1712_Y + connect \$1530 $or$libresoc.v:42113$1713_Y + connect \$1532 $and$libresoc.v:42114$1714_Y + connect \$1534 $and$libresoc.v:42115$1715_Y + connect \$1536 $and$libresoc.v:42116$1716_Y + connect \$1538 $and$libresoc.v:42117$1717_Y + connect \$1540 $and$libresoc.v:42118$1718_Y + connect \$1543 $and$libresoc.v:42119$1719_Y + connect \$1546 $not$libresoc.v:42120$1720_Y + connect \$1548 $and$libresoc.v:42121$1721_Y + connect \$1551 $and$libresoc.v:42122$1722_Y + connect \$1554 $ternary$libresoc.v:42123$1723_Y + connect \$1556 $and$libresoc.v:42124$1724_Y + connect \$1559 $and$libresoc.v:42125$1725_Y + connect \$1562 $not$libresoc.v:42126$1726_Y + connect \$1564 $and$libresoc.v:42127$1727_Y + connect \$1567 $and$libresoc.v:42128$1728_Y + connect \$1570 $ternary$libresoc.v:42129$1729_Y + connect \$1572 $and$libresoc.v:42130$1730_Y + connect \$1575 $and$libresoc.v:42131$1731_Y + connect \$1578 $not$libresoc.v:42132$1732_Y + connect \$1580 $and$libresoc.v:42133$1733_Y + connect \$1583 $and$libresoc.v:42134$1734_Y + connect \$1586 $ternary$libresoc.v:42135$1735_Y + connect \$1588 $and$libresoc.v:42136$1736_Y + connect \$1591 $and$libresoc.v:42137$1737_Y + connect \$1594 $not$libresoc.v:42138$1738_Y + connect \$1596 $and$libresoc.v:42139$1739_Y + connect \$1599 $and$libresoc.v:42140$1740_Y + connect \$1602 $ternary$libresoc.v:42141$1741_Y + connect \$1605 $or$libresoc.v:42142$1742_Y + connect \$1607 $or$libresoc.v:42143$1743_Y + connect \$1609 $or$libresoc.v:42144$1744_Y + connect \$1604 $pos$libresoc.v:42145$1746_Y + connect \$1613 $or$libresoc.v:42146$1747_Y + connect \$1615 $or$libresoc.v:42147$1748_Y + connect \$1617 $or$libresoc.v:42148$1749_Y + connect \$1612 $pos$libresoc.v:42149$1751_Y + connect \$1620 $and$libresoc.v:42150$1752_Y + connect \$1622 $and$libresoc.v:42151$1753_Y + connect \$1624 $and$libresoc.v:42152$1754_Y + connect \$1626 $and$libresoc.v:42153$1755_Y + connect \$1628 $and$libresoc.v:42154$1756_Y + connect \$1630 $and$libresoc.v:42155$1757_Y + connect \$1633 $and$libresoc.v:42156$1758_Y + connect \$1637 $not$libresoc.v:42157$1759_Y + connect \$1639 $and$libresoc.v:42158$1760_Y + connect \$1644 $and$libresoc.v:42159$1761_Y + connect \$1647 $ternary$libresoc.v:42160$1762_Y + connect \$1649 $and$libresoc.v:42161$1763_Y + connect \$1652 $and$libresoc.v:42162$1764_Y + connect \$1655 $not$libresoc.v:42163$1765_Y + connect \$1657 $and$libresoc.v:42164$1766_Y + connect \$1660 $and$libresoc.v:42165$1767_Y + connect \$1663 $ternary$libresoc.v:42166$1768_Y + connect \$1665 $and$libresoc.v:42167$1769_Y + connect \$1668 $and$libresoc.v:42168$1770_Y + connect \$1671 $not$libresoc.v:42169$1771_Y + connect \$1673 $and$libresoc.v:42170$1772_Y + connect \$1676 $and$libresoc.v:42171$1773_Y + connect \$1679 $ternary$libresoc.v:42172$1774_Y + connect \$1681 $and$libresoc.v:42173$1775_Y + connect \$1684 $and$libresoc.v:42174$1776_Y + connect \$1687 $not$libresoc.v:42175$1777_Y + connect \$1689 $and$libresoc.v:42176$1778_Y + connect \$1692 $and$libresoc.v:42177$1779_Y + connect \$1695 $ternary$libresoc.v:42178$1780_Y + connect \$1697 $and$libresoc.v:42179$1781_Y + connect \$1700 $and$libresoc.v:42180$1782_Y + connect \$1703 $not$libresoc.v:42181$1783_Y + connect \$1705 $and$libresoc.v:42182$1784_Y + connect \$1708 $and$libresoc.v:42183$1785_Y + connect \$1711 $ternary$libresoc.v:42184$1786_Y + connect \$1713 $or$libresoc.v:42185$1787_Y + connect \$1715 $or$libresoc.v:42186$1788_Y + connect \$1717 $or$libresoc.v:42187$1789_Y + connect \$1719 $or$libresoc.v:42188$1790_Y + connect \$1721 $or$libresoc.v:42189$1791_Y + connect \$1723 $or$libresoc.v:42190$1792_Y + connect \$1725 $or$libresoc.v:42191$1793_Y + connect \$1727 $or$libresoc.v:42192$1794_Y + connect \$1729 $or$libresoc.v:42193$1795_Y + connect \$1731 $or$libresoc.v:42194$1796_Y + connect \$1733 $or$libresoc.v:42195$1797_Y + connect \$1735 $or$libresoc.v:42196$1798_Y + connect \$1737 $and$libresoc.v:42197$1799_Y + connect \$1739 $and$libresoc.v:42198$1800_Y + connect \$1741 $and$libresoc.v:42199$1801_Y + connect \$1744 $and$libresoc.v:42200$1802_Y + connect \$1747 $not$libresoc.v:42201$1803_Y + connect \$1749 $and$libresoc.v:42202$1804_Y + connect \$1752 $and$libresoc.v:42203$1805_Y + connect \$1755 $ternary$libresoc.v:42204$1806_Y + connect \$1757 $and$libresoc.v:42205$1807_Y + connect \$1760 $and$libresoc.v:42206$1808_Y + connect \$1763 $not$libresoc.v:42207$1809_Y + connect \$1765 $and$libresoc.v:42208$1810_Y + connect \$1768 $and$libresoc.v:42209$1811_Y + connect \$1771 $ternary$libresoc.v:42210$1812_Y + connect \$1773 $or$libresoc.v:42211$1813_Y + connect \$1776 $or$libresoc.v:42212$1814_Y + connect \$1775 $pos$libresoc.v:42213$1816_Y + connect \$1779 $and$libresoc.v:42214$1817_Y + connect \$1781 $and$libresoc.v:42215$1818_Y + connect \$1784 $and$libresoc.v:42216$1819_Y + connect \$1787 $not$libresoc.v:42217$1820_Y + connect \$1789 $and$libresoc.v:42218$1821_Y + connect \$1792 $and$libresoc.v:42219$1822_Y + connect \$1795 $ternary$libresoc.v:42220$1823_Y + connect \$1797 $pos$libresoc.v:42221$1825_Y + connect \$1799 $and$libresoc.v:42222$1826_Y + connect \$1801 $and$libresoc.v:42223$1827_Y + connect \$1804 $and$libresoc.v:42224$1828_Y + connect \$1807 $not$libresoc.v:42225$1829_Y + connect \$1809 $and$libresoc.v:42226$1830_Y + connect \$1812 $and$libresoc.v:42227$1831_Y + connect \$1815 $ternary$libresoc.v:42228$1832_Y + connect \$182 $and$libresoc.v:42229$1833_Y + connect \$181 $reduce_or$libresoc.v:42230$1834_Y + connect \$186 $and$libresoc.v:42231$1835_Y + connect \$185 $reduce_or$libresoc.v:42232$1836_Y + connect \$190 $and$libresoc.v:42233$1837_Y + connect \$189 $reduce_or$libresoc.v:42234$1838_Y + connect \$194 $and$libresoc.v:42235$1839_Y + connect \$193 $reduce_or$libresoc.v:42236$1840_Y + connect \$198 $and$libresoc.v:42237$1841_Y + connect \$197 $reduce_or$libresoc.v:42238$1842_Y + connect \$202 $and$libresoc.v:42239$1843_Y + connect \$201 $reduce_or$libresoc.v:42240$1844_Y + connect \$206 $and$libresoc.v:42241$1845_Y + connect \$205 $reduce_or$libresoc.v:42242$1846_Y + connect \$210 $and$libresoc.v:42243$1847_Y + connect \$209 $reduce_or$libresoc.v:42244$1848_Y + connect \$214 $and$libresoc.v:42245$1849_Y + connect \$213 $reduce_or$libresoc.v:42246$1850_Y + connect \$218 $and$libresoc.v:42247$1851_Y + connect \$217 $reduce_or$libresoc.v:42248$1852_Y + connect \$221 $ne$libresoc.v:42249$1853_Y + connect \$224 $sub$libresoc.v:42250$1854_Y + connect \$226 $ne$libresoc.v:42251$1855_Y + connect \$229 $and$libresoc.v:42252$1856_Y + connect \$231 $and$libresoc.v:42253$1857_Y + connect \$233 $eq$libresoc.v:42254$1858_Y + connect \$235 $or$libresoc.v:42255$1859_Y + connect \$237 $and$libresoc.v:42256$1860_Y + connect \$239 $or$libresoc.v:42257$1861_Y + connect \$241 $eq$libresoc.v:42258$1862_Y + connect \$243 $and$libresoc.v:42259$1863_Y + connect \$245 $eq$libresoc.v:42260$1864_Y + connect \$247 $or$libresoc.v:42261$1865_Y + connect \$228 $not$libresoc.v:42262$1866_Y + connect \$250 $not$libresoc.v:42263$1867_Y + connect \$252 $not$libresoc.v:42264$1868_Y + connect \$254 $not$libresoc.v:42265$1869_Y + connect \$257 $and$libresoc.v:42266$1870_Y + connect \$259 $and$libresoc.v:42267$1871_Y + connect \$261 $eq$libresoc.v:42268$1872_Y + connect \$263 $or$libresoc.v:42269$1873_Y + connect \$265 $and$libresoc.v:42270$1874_Y + connect \$267 $or$libresoc.v:42271$1875_Y + connect \$256 $not$libresoc.v:42272$1876_Y + connect \$271 $and$libresoc.v:42273$1877_Y + connect \$273 $and$libresoc.v:42274$1878_Y + connect \$275 $eq$libresoc.v:42275$1879_Y + connect \$277 $or$libresoc.v:42276$1880_Y + connect \$279 $and$libresoc.v:42277$1881_Y + connect \$281 $or$libresoc.v:42278$1882_Y + connect \$283 $and$libresoc.v:42279$1883_Y + connect \$285 $and$libresoc.v:42280$1884_Y + connect \$287 $eq$libresoc.v:42281$1885_Y + connect \$289 $or$libresoc.v:42282$1886_Y + connect \$291 $eq$libresoc.v:42283$1887_Y + connect \$293 $and$libresoc.v:42284$1888_Y + connect \$295 $eq$libresoc.v:42285$1889_Y + connect \$297 $or$libresoc.v:42286$1890_Y + connect \$270 $not$libresoc.v:42287$1891_Y + connect \$301 $and$libresoc.v:42288$1892_Y + connect \$303 $and$libresoc.v:42289$1893_Y + connect \$305 $eq$libresoc.v:42290$1894_Y + connect \$307 $or$libresoc.v:42291$1895_Y + connect \$309 $and$libresoc.v:42292$1896_Y + connect \$311 $or$libresoc.v:42293$1897_Y + connect \$300 $not$libresoc.v:42294$1898_Y + connect \$315 $and$libresoc.v:42295$1899_Y + connect \$317 $and$libresoc.v:42296$1900_Y + connect \$319 $eq$libresoc.v:42297$1901_Y + connect \$321 $or$libresoc.v:42298$1902_Y + connect \$323 $and$libresoc.v:42299$1903_Y + connect \$325 $or$libresoc.v:42300$1904_Y + connect \$314 $not$libresoc.v:42301$1905_Y + connect \$329 $and$libresoc.v:42302$1906_Y + connect \$331 $and$libresoc.v:42303$1907_Y + connect \$333 $eq$libresoc.v:42304$1908_Y + connect \$335 $or$libresoc.v:42305$1909_Y + connect \$337 $and$libresoc.v:42306$1910_Y + connect \$339 $or$libresoc.v:42307$1911_Y + connect \$341 $eq$libresoc.v:42308$1912_Y + connect \$343 $and$libresoc.v:42309$1913_Y + connect \$345 $eq$libresoc.v:42310$1914_Y + connect \$347 $or$libresoc.v:42311$1915_Y + connect \$328 $not$libresoc.v:42312$1916_Y + connect \$350 $not$libresoc.v:42313$1917_Y + connect \$352 $and$libresoc.v:42314$1918_Y + connect \$354 $and$libresoc.v:42315$1919_Y + connect \$356 $not$libresoc.v:42316$1920_Y + connect \$358 $and$libresoc.v:42317$1921_Y + connect \$360 $and$libresoc.v:42318$1922_Y + connect \$362 $ternary$libresoc.v:42319$1923_Y + connect \$364 $and$libresoc.v:42320$1924_Y + connect \$366 $and$libresoc.v:42321$1925_Y + connect \$368 $not$libresoc.v:42322$1926_Y + connect \$370 $and$libresoc.v:42323$1927_Y + connect \$372 $and$libresoc.v:42324$1928_Y + connect \$374 $ternary$libresoc.v:42325$1929_Y + connect \$376 $and$libresoc.v:42326$1930_Y + connect \$378 $and$libresoc.v:42327$1931_Y + connect \$380 $not$libresoc.v:42328$1932_Y + connect \$382 $and$libresoc.v:42329$1933_Y + connect \$384 $and$libresoc.v:42330$1934_Y + connect \$386 $ternary$libresoc.v:42331$1935_Y + connect \$388 $and$libresoc.v:42332$1936_Y + connect \$390 $and$libresoc.v:42333$1937_Y + connect \$392 $not$libresoc.v:42334$1938_Y + connect \$394 $and$libresoc.v:42335$1939_Y + connect \$396 $and$libresoc.v:42336$1940_Y + connect \$398 $ternary$libresoc.v:42337$1941_Y + connect \$400 $and$libresoc.v:42338$1942_Y + connect \$402 $and$libresoc.v:42339$1943_Y + connect \$404 $not$libresoc.v:42340$1944_Y + connect \$406 $and$libresoc.v:42341$1945_Y + connect \$408 $and$libresoc.v:42342$1946_Y + connect \$410 $ternary$libresoc.v:42343$1947_Y + connect \$412 $and$libresoc.v:42344$1948_Y + connect \$414 $and$libresoc.v:42345$1949_Y + connect \$416 $not$libresoc.v:42346$1950_Y + connect \$418 $and$libresoc.v:42347$1951_Y + connect \$420 $and$libresoc.v:42348$1952_Y + connect \$422 $ternary$libresoc.v:42349$1953_Y + connect \$424 $and$libresoc.v:42350$1954_Y + connect \$426 $and$libresoc.v:42351$1955_Y + connect \$428 $not$libresoc.v:42352$1956_Y + connect \$430 $and$libresoc.v:42353$1957_Y + connect \$432 $and$libresoc.v:42354$1958_Y + connect \$434 $ternary$libresoc.v:42355$1959_Y + connect \$436 $and$libresoc.v:42356$1960_Y + connect \$438 $and$libresoc.v:42357$1961_Y + connect \$440 $not$libresoc.v:42358$1962_Y + connect \$442 $and$libresoc.v:42359$1963_Y + connect \$444 $and$libresoc.v:42360$1964_Y + connect \$446 $ternary$libresoc.v:42361$1965_Y + connect \$448 $and$libresoc.v:42362$1966_Y + connect \$450 $and$libresoc.v:42363$1967_Y + connect \$452 $not$libresoc.v:42364$1968_Y + connect \$454 $and$libresoc.v:42365$1969_Y + connect \$456 $and$libresoc.v:42366$1970_Y + connect \$458 $ternary$libresoc.v:42367$1971_Y + connect \$460 $and$libresoc.v:42368$1972_Y + connect \$462 $and$libresoc.v:42369$1973_Y + connect \$464 $not$libresoc.v:42370$1974_Y + connect \$466 $and$libresoc.v:42371$1975_Y + connect \$468 $and$libresoc.v:42372$1976_Y + connect \$470 $ternary$libresoc.v:42373$1977_Y + connect \$472 $and$libresoc.v:42374$1978_Y + connect \$474 $and$libresoc.v:42375$1979_Y + connect \$476 $not$libresoc.v:42376$1980_Y + connect \$478 $and$libresoc.v:42377$1981_Y + connect \$480 $and$libresoc.v:42378$1982_Y + connect \$482 $ternary$libresoc.v:42379$1983_Y + connect \$484 $and$libresoc.v:42380$1984_Y + connect \$486 $and$libresoc.v:42381$1985_Y + connect \$488 $not$libresoc.v:42382$1986_Y + connect \$490 $and$libresoc.v:42383$1987_Y + connect \$492 $and$libresoc.v:42384$1988_Y + connect \$494 $ternary$libresoc.v:42385$1989_Y + connect \$496 $and$libresoc.v:42386$1990_Y + connect \$498 $and$libresoc.v:42387$1991_Y + connect \$500 $not$libresoc.v:42388$1992_Y + connect \$502 $and$libresoc.v:42389$1993_Y + connect \$504 $and$libresoc.v:42390$1994_Y + connect \$506 $ternary$libresoc.v:42391$1995_Y + connect \$508 $and$libresoc.v:42392$1996_Y + connect \$510 $and$libresoc.v:42393$1997_Y + connect \$512 $not$libresoc.v:42394$1998_Y + connect \$514 $and$libresoc.v:42395$1999_Y + connect \$516 $and$libresoc.v:42396$2000_Y + connect \$518 $ternary$libresoc.v:42397$2001_Y + connect \$520 $and$libresoc.v:42398$2002_Y + connect \$522 $and$libresoc.v:42399$2003_Y + connect \$524 $not$libresoc.v:42400$2004_Y + connect \$526 $and$libresoc.v:42401$2005_Y + connect \$528 $and$libresoc.v:42402$2006_Y + connect \$530 $ternary$libresoc.v:42403$2007_Y + connect \$532 $and$libresoc.v:42404$2008_Y + connect \$534 $and$libresoc.v:42405$2009_Y + connect \$536 $not$libresoc.v:42406$2010_Y + connect \$538 $and$libresoc.v:42407$2011_Y + connect \$540 $and$libresoc.v:42408$2012_Y + connect \$542 $ternary$libresoc.v:42409$2013_Y + connect \$544 $and$libresoc.v:42410$2014_Y + connect \$546 $and$libresoc.v:42411$2015_Y + connect \$548 $not$libresoc.v:42412$2016_Y + connect \$550 $and$libresoc.v:42413$2017_Y + connect \$552 $and$libresoc.v:42414$2018_Y + connect \$554 $ternary$libresoc.v:42415$2019_Y + connect \$556 $and$libresoc.v:42416$2020_Y + connect \$558 $and$libresoc.v:42417$2021_Y + connect \$560 $not$libresoc.v:42418$2022_Y + connect \$562 $and$libresoc.v:42419$2023_Y + connect \$564 $and$libresoc.v:42420$2024_Y + connect \$566 $ternary$libresoc.v:42421$2025_Y + connect \$568 $and$libresoc.v:42422$2026_Y + connect \$570 $and$libresoc.v:42423$2027_Y + connect \$572 $not$libresoc.v:42424$2028_Y + connect \$574 $and$libresoc.v:42425$2029_Y + connect \$576 $and$libresoc.v:42426$2030_Y + connect \$578 $ternary$libresoc.v:42427$2031_Y + connect \$581 $or$libresoc.v:42428$2032_Y + connect \$583 $or$libresoc.v:42429$2033_Y + connect \$585 $or$libresoc.v:42430$2034_Y + connect \$587 $or$libresoc.v:42431$2035_Y + connect \$589 $or$libresoc.v:42432$2036_Y + connect \$591 $or$libresoc.v:42433$2037_Y + connect \$593 $or$libresoc.v:42434$2038_Y + connect \$595 $or$libresoc.v:42435$2039_Y + connect \$597 $or$libresoc.v:42436$2040_Y + connect \$599 $or$libresoc.v:42437$2041_Y + connect \$601 $or$libresoc.v:42438$2042_Y + connect \$603 $or$libresoc.v:42439$2043_Y + connect \$605 $or$libresoc.v:42440$2044_Y + connect \$607 $or$libresoc.v:42441$2045_Y + connect \$609 $or$libresoc.v:42442$2046_Y + connect \$611 $or$libresoc.v:42443$2047_Y + connect \$613 $or$libresoc.v:42444$2048_Y + connect \$615 $or$libresoc.v:42445$2049_Y + connect \$617 $reduce_or$libresoc.v:42446$2050_Y + connect \$619 $and$libresoc.v:42447$2051_Y + connect \$621 $and$libresoc.v:42448$2052_Y + connect \$623 $eq$libresoc.v:42449$2053_Y + connect \$625 $or$libresoc.v:42450$2054_Y + connect \$627 $and$libresoc.v:42451$2055_Y + connect \$629 $or$libresoc.v:42452$2056_Y + connect \$631 $and$libresoc.v:42453$2057_Y + connect \$633 $and$libresoc.v:42454$2058_Y + connect \$635 $not$libresoc.v:42455$2059_Y + connect \$637 $and$libresoc.v:42456$2060_Y + connect \$639 $and$libresoc.v:42457$2061_Y + connect \$641 $ternary$libresoc.v:42458$2062_Y + connect \$643 $and$libresoc.v:42459$2063_Y + connect \$645 $and$libresoc.v:42460$2064_Y + connect \$647 $not$libresoc.v:42461$2065_Y + connect \$649 $and$libresoc.v:42462$2066_Y + connect \$651 $and$libresoc.v:42463$2067_Y + connect \$653 $ternary$libresoc.v:42464$2068_Y + connect \$655 $and$libresoc.v:42465$2069_Y + connect \$657 $and$libresoc.v:42466$2070_Y + connect \$659 $not$libresoc.v:42467$2071_Y + connect \$661 $and$libresoc.v:42468$2072_Y + connect \$663 $and$libresoc.v:42469$2073_Y + connect \$665 $ternary$libresoc.v:42470$2074_Y + connect \$667 $and$libresoc.v:42471$2075_Y + connect \$669 $and$libresoc.v:42472$2076_Y + connect \$671 $not$libresoc.v:42473$2077_Y + connect \$673 $and$libresoc.v:42474$2078_Y + connect \$675 $and$libresoc.v:42475$2079_Y + connect \$677 $ternary$libresoc.v:42476$2080_Y + connect \$679 $and$libresoc.v:42477$2081_Y + connect \$681 $and$libresoc.v:42478$2082_Y + connect \$683 $not$libresoc.v:42479$2083_Y + connect \$685 $and$libresoc.v:42480$2084_Y + connect \$687 $and$libresoc.v:42481$2085_Y + connect \$689 $ternary$libresoc.v:42482$2086_Y + connect \$691 $and$libresoc.v:42483$2087_Y + connect \$693 $and$libresoc.v:42484$2088_Y + connect \$695 $not$libresoc.v:42485$2089_Y + connect \$697 $and$libresoc.v:42486$2090_Y + connect \$699 $and$libresoc.v:42487$2091_Y + connect \$701 $ternary$libresoc.v:42488$2092_Y + connect \$704 $or$libresoc.v:42489$2093_Y + connect \$706 $or$libresoc.v:42490$2094_Y + connect \$708 $or$libresoc.v:42491$2095_Y + connect \$710 $or$libresoc.v:42492$2096_Y + connect \$712 $or$libresoc.v:42493$2097_Y + connect \$703 $pos$libresoc.v:42494$2099_Y + connect \$715 $eq$libresoc.v:42495$2100_Y + connect \$717 $and$libresoc.v:42496$2101_Y + connect \$719 $eq$libresoc.v:42497$2102_Y + connect \$721 $or$libresoc.v:42498$2103_Y + connect \$723 $and$libresoc.v:42499$2104_Y + connect \$725 $and$libresoc.v:42500$2105_Y + connect \$727 $not$libresoc.v:42501$2106_Y + connect \$729 $and$libresoc.v:42502$2107_Y + connect \$731 $and$libresoc.v:42503$2108_Y + connect \$733 $ternary$libresoc.v:42504$2109_Y + connect \$735 $and$libresoc.v:42505$2110_Y + connect \$737 $and$libresoc.v:42506$2111_Y + connect \$739 $not$libresoc.v:42507$2112_Y + connect \$741 $and$libresoc.v:42508$2113_Y + connect \$743 $and$libresoc.v:42509$2114_Y + connect \$745 $ternary$libresoc.v:42510$2115_Y + connect \$747 $and$libresoc.v:42511$2116_Y + connect \$749 $and$libresoc.v:42512$2117_Y + connect \$751 $not$libresoc.v:42513$2118_Y + connect \$753 $and$libresoc.v:42514$2119_Y + connect \$755 $and$libresoc.v:42515$2120_Y + connect \$757 $ternary$libresoc.v:42516$2121_Y + connect \$760 $or$libresoc.v:42517$2122_Y + connect \$762 $or$libresoc.v:42518$2123_Y + connect \$759 $pos$libresoc.v:42519$2125_Y + connect \$765 $and$libresoc.v:42520$2126_Y + connect \$767 $and$libresoc.v:42521$2127_Y + connect \$769 $eq$libresoc.v:42522$2128_Y + connect \$771 $or$libresoc.v:42523$2129_Y + connect \$773 $and$libresoc.v:42524$2130_Y + connect \$775 $and$libresoc.v:42525$2131_Y + connect \$777 $not$libresoc.v:42526$2132_Y + connect \$779 $and$libresoc.v:42527$2133_Y + connect \$781 $and$libresoc.v:42528$2134_Y + connect \$783 $ternary$libresoc.v:42529$2135_Y + connect \$785 $and$libresoc.v:42530$2136_Y + connect \$787 $and$libresoc.v:42531$2137_Y + connect \$789 $not$libresoc.v:42532$2138_Y + connect \$791 $and$libresoc.v:42533$2139_Y + connect \$793 $and$libresoc.v:42534$2140_Y + connect \$795 $ternary$libresoc.v:42535$2141_Y + connect \$797 $and$libresoc.v:42536$2142_Y + connect \$799 $and$libresoc.v:42537$2143_Y + connect \$801 $not$libresoc.v:42538$2144_Y + connect \$803 $and$libresoc.v:42539$2145_Y + connect \$805 $and$libresoc.v:42540$2146_Y + connect \$807 $sub$libresoc.v:42541$2147_Y + connect \$809 $sshl$libresoc.v:42542$2148_Y + connect \$811 $ternary$libresoc.v:42543$2149_Y + connect \$813 $and$libresoc.v:42544$2150_Y + connect \$815 $and$libresoc.v:42545$2151_Y + connect \$817 $not$libresoc.v:42546$2152_Y + connect \$819 $and$libresoc.v:42547$2153_Y + connect \$821 $and$libresoc.v:42548$2154_Y + connect \$823 $sub$libresoc.v:42549$2155_Y + connect \$825 $sshl$libresoc.v:42550$2156_Y + connect \$827 $ternary$libresoc.v:42551$2157_Y + connect \$830 $or$libresoc.v:42552$2158_Y + connect \$832 $and$libresoc.v:42553$2159_Y + connect \$834 $and$libresoc.v:42554$2160_Y + connect \$836 $not$libresoc.v:42555$2161_Y + connect \$838 $and$libresoc.v:42556$2162_Y + connect \$840 $and$libresoc.v:42557$2163_Y + connect \$842 $sub$libresoc.v:42558$2164_Y + connect \$844 $sshl$libresoc.v:42559$2165_Y + connect \$846 $ternary$libresoc.v:42560$2166_Y + connect \$848 $and$libresoc.v:42561$2167_Y + connect \$850 $and$libresoc.v:42562$2168_Y + connect \$852 $not$libresoc.v:42563$2169_Y + connect \$854 $and$libresoc.v:42564$2170_Y + connect \$856 $and$libresoc.v:42565$2171_Y + connect \$858 $sub$libresoc.v:42566$2172_Y + connect \$860 $sshl$libresoc.v:42567$2173_Y + connect \$862 $ternary$libresoc.v:42568$2174_Y + connect \$864 $and$libresoc.v:42569$2175_Y + connect \$866 $and$libresoc.v:42570$2176_Y + connect \$868 $not$libresoc.v:42571$2177_Y + connect \$870 $and$libresoc.v:42572$2178_Y + connect \$872 $and$libresoc.v:42573$2179_Y + connect \$874 $ternary$libresoc.v:42574$2180_Y + connect \$876 $and$libresoc.v:42575$2181_Y + connect \$878 $and$libresoc.v:42576$2182_Y + connect \$880 $not$libresoc.v:42577$2183_Y + connect \$882 $and$libresoc.v:42578$2184_Y + connect \$884 $and$libresoc.v:42579$2185_Y + connect \$886 $ternary$libresoc.v:42580$2186_Y + connect \$888 $and$libresoc.v:42581$2187_Y + connect \$890 $and$libresoc.v:42582$2188_Y + connect \$892 $not$libresoc.v:42583$2189_Y + connect \$894 $and$libresoc.v:42584$2190_Y + connect \$896 $and$libresoc.v:42585$2191_Y + connect \$898 $ternary$libresoc.v:42586$2192_Y + connect \$900 $and$libresoc.v:42587$2193_Y + connect \$902 $and$libresoc.v:42588$2194_Y + connect \$904 $not$libresoc.v:42589$2195_Y + connect \$906 $and$libresoc.v:42590$2196_Y + connect \$908 $and$libresoc.v:42591$2197_Y + connect \$910 $ternary$libresoc.v:42592$2198_Y + connect \$912 $and$libresoc.v:42593$2199_Y + connect \$914 $and$libresoc.v:42594$2200_Y + connect \$916 $not$libresoc.v:42595$2201_Y + connect \$918 $and$libresoc.v:42596$2202_Y + connect \$920 $and$libresoc.v:42597$2203_Y + connect \$922 $ternary$libresoc.v:42598$2204_Y + connect \$924 $or$libresoc.v:42599$2205_Y + connect \$926 $or$libresoc.v:42600$2206_Y + connect \$928 $or$libresoc.v:42601$2207_Y + connect \$930 $or$libresoc.v:42602$2208_Y + connect \$932 $reduce_or$libresoc.v:42603$2209_Y + connect \$934 $and$libresoc.v:42604$2210_Y + connect \$936 $and$libresoc.v:42605$2211_Y + connect \$938 $not$libresoc.v:42606$2212_Y + connect \$940 $and$libresoc.v:42607$2213_Y + connect \$942 $and$libresoc.v:42608$2214_Y + connect \$944 $ternary$libresoc.v:42609$2215_Y + connect \$946 $reduce_or$libresoc.v:42610$2216_Y + connect \$948 $and$libresoc.v:42611$2217_Y + connect \$950 $and$libresoc.v:42612$2218_Y + connect \$952 $and$libresoc.v:42613$2219_Y + connect \$954 $and$libresoc.v:42614$2220_Y + connect \$956 $and$libresoc.v:42615$2221_Y + connect \$958 $and$libresoc.v:42616$2222_Y + connect \$960 $and$libresoc.v:42617$2223_Y + connect \$962 $and$libresoc.v:42618$2224_Y + connect \$964 $and$libresoc.v:42619$2225_Y + connect \$966 $and$libresoc.v:42620$2226_Y + connect \$968 $and$libresoc.v:42621$2227_Y + connect \$970 $and$libresoc.v:42622$2228_Y + connect \$972 $not$libresoc.v:42623$2229_Y + connect \$974 $and$libresoc.v:42624$2230_Y + connect \$980 $and$libresoc.v:42625$2231_Y + connect \$982 $ternary$libresoc.v:42626$2232_Y + connect \$984 $and$libresoc.v:42627$2233_Y + connect \$987 $and$libresoc.v:42628$2234_Y + connect \$991 $not$libresoc.v:42629$2235_Y + connect \$993 $and$libresoc.v:42630$2236_Y + connect \$998 $and$libresoc.v:42631$2237_Y connect \$223 \$224 connect \$580 \$615 connect \$829 \$830 @@ -85604,8 +85400,8 @@ module \core connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 connect \pick_XER_xer_so_alu0_0 \$637 connect \rdflag_XER_xer_so_0 \$629 - connect \int_src__ren \$617 - connect \int_src__addr \$615 [4:0] + connect \int_src1__ren \$617 + connect \int_src1__addr \$615 [4:0] connect \addr_en_INT_rabc_ldst0_18 \$578 connect \rp_INT_rabc_ldst0_18 \$576 connect \pick_INT_rabc_ldst0_18 \$574 @@ -85770,97 +85566,97 @@ module \core connect \dec_ALU_bigendian \bigendian_i connect \dec_ALU_raw_opcode_in \raw_insn_i end -attribute \src "libresoc.v:49125.1-49758.10" +attribute \src "libresoc.v:48921.1-49554.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr" attribute \generator "nMigen" module \cr - attribute \src "libresoc.v:49126.7-49126.20" + attribute \src "libresoc.v:48922.7-48922.20" wire $0\initial[0:0] - attribute \src "libresoc.v:49672.3-49680.6" + attribute \src "libresoc.v:49468.3-49476.6" wire width 8 $0\ren_delay$17$next[7:0]$3046 - attribute \src "libresoc.v:49508.3-49509.43" + attribute \src "libresoc.v:49304.3-49305.43" wire width 8 $0\ren_delay$17[7:0]$3043 - attribute \src "libresoc.v:49454.13-49454.35" + attribute \src "libresoc.v:49250.13-49250.35" wire width 8 $0\ren_delay$17[7:0]$3060 - attribute \src "libresoc.v:49691.3-49699.6" + attribute \src "libresoc.v:49487.3-49495.6" wire width 8 $0\ren_delay$34$next[7:0]$3050 - attribute \src "libresoc.v:49506.3-49507.43" + attribute \src "libresoc.v:49302.3-49303.43" wire width 8 $0\ren_delay$34[7:0]$3041 - attribute \src "libresoc.v:49458.13-49458.35" + attribute \src "libresoc.v:49254.13-49254.35" wire width 8 $0\ren_delay$34[7:0]$3062 - attribute \src "libresoc.v:49710.3-49718.6" + attribute \src "libresoc.v:49506.3-49514.6" wire width 8 $0\ren_delay$next[7:0]$3054 - attribute \src "libresoc.v:49510.3-49511.35" + attribute \src "libresoc.v:49306.3-49307.35" wire width 8 $0\ren_delay[7:0] - attribute \src "libresoc.v:49719.3-49728.6" + attribute \src "libresoc.v:49515.3-49524.6" wire width 4 $0\src1__data_o[3:0] - attribute \src "libresoc.v:49681.3-49690.6" + attribute \src "libresoc.v:49477.3-49486.6" wire width 4 $0\src2__data_o[3:0] - attribute \src "libresoc.v:49700.3-49709.6" + attribute \src "libresoc.v:49496.3-49505.6" wire width 4 $0\src3__data_o[3:0] - attribute \src "libresoc.v:49672.3-49680.6" + attribute \src "libresoc.v:49468.3-49476.6" wire width 8 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49691.3-49699.6" + attribute \src "libresoc.v:49487.3-49495.6" wire width 8 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49710.3-49718.6" + attribute \src "libresoc.v:49506.3-49514.6" wire width 8 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:49452.13-49452.30" + attribute \src "libresoc.v:49248.13-49248.30" wire width 8 $1\ren_delay[7:0] - attribute \src "libresoc.v:49719.3-49728.6" + attribute \src "libresoc.v:49515.3-49524.6" wire width 4 $1\src1__data_o[3:0] - attribute \src "libresoc.v:49681.3-49690.6" + attribute \src "libresoc.v:49477.3-49486.6" wire width 4 $1\src2__data_o[3:0] - attribute \src "libresoc.v:49700.3-49709.6" + attribute \src "libresoc.v:49496.3-49505.6" wire width 4 $1\src3__data_o[3:0] - attribute \src "libresoc.v:49482.17-49482.125" - wire width 4 $or$libresoc.v:49482$3016_Y - attribute \src "libresoc.v:49483.18-49483.126" - wire width 4 $or$libresoc.v:49483$3017_Y - attribute \src "libresoc.v:49484.18-49484.96" - wire width 4 $or$libresoc.v:49484$3018_Y - attribute \src "libresoc.v:49485.18-49485.96" - wire width 4 $or$libresoc.v:49485$3019_Y - attribute \src "libresoc.v:49488.18-49488.126" - wire width 4 $or$libresoc.v:49488$3022_Y - attribute \src "libresoc.v:49489.18-49489.126" - wire width 4 $or$libresoc.v:49489$3023_Y - attribute \src "libresoc.v:49490.18-49490.97" - wire width 4 $or$libresoc.v:49490$3024_Y - attribute \src "libresoc.v:49491.18-49491.126" - wire width 4 $or$libresoc.v:49491$3025_Y - attribute \src "libresoc.v:49492.18-49492.126" - wire width 4 $or$libresoc.v:49492$3026_Y - attribute \src "libresoc.v:49493.18-49493.97" - wire width 4 $or$libresoc.v:49493$3027_Y - attribute \src "libresoc.v:49494.18-49494.97" - wire width 4 $or$libresoc.v:49494$3028_Y - attribute \src "libresoc.v:49496.18-49496.126" - wire width 4 $or$libresoc.v:49496$3030_Y - attribute \src "libresoc.v:49497.17-49497.125" - wire width 4 $or$libresoc.v:49497$3031_Y - attribute \src "libresoc.v:49498.18-49498.126" - wire width 4 $or$libresoc.v:49498$3032_Y - attribute \src "libresoc.v:49499.18-49499.97" - wire width 4 $or$libresoc.v:49499$3033_Y - attribute \src "libresoc.v:49500.18-49500.126" - wire width 4 $or$libresoc.v:49500$3034_Y - attribute \src "libresoc.v:49501.18-49501.126" - wire width 4 $or$libresoc.v:49501$3035_Y - attribute \src "libresoc.v:49502.18-49502.97" - wire width 4 $or$libresoc.v:49502$3036_Y - attribute \src "libresoc.v:49503.18-49503.97" - wire width 4 $or$libresoc.v:49503$3037_Y - attribute \src "libresoc.v:49504.17-49504.125" - wire width 4 $or$libresoc.v:49504$3038_Y - attribute \src "libresoc.v:49505.17-49505.94" - wire width 4 $or$libresoc.v:49505$3039_Y - attribute \src "libresoc.v:49486.18-49486.100" - wire $reduce_or$libresoc.v:49486$3020_Y - attribute \src "libresoc.v:49487.17-49487.95" - wire $reduce_or$libresoc.v:49487$3021_Y - attribute \src "libresoc.v:49495.18-49495.100" - wire $reduce_or$libresoc.v:49495$3029_Y + attribute \src "libresoc.v:49278.17-49278.125" + wire width 4 $or$libresoc.v:49278$3016_Y + attribute \src "libresoc.v:49279.18-49279.126" + wire width 4 $or$libresoc.v:49279$3017_Y + attribute \src "libresoc.v:49280.18-49280.96" + wire width 4 $or$libresoc.v:49280$3018_Y + attribute \src "libresoc.v:49281.18-49281.96" + wire width 4 $or$libresoc.v:49281$3019_Y + attribute \src "libresoc.v:49284.18-49284.126" + wire width 4 $or$libresoc.v:49284$3022_Y + attribute \src "libresoc.v:49285.18-49285.126" + wire width 4 $or$libresoc.v:49285$3023_Y + attribute \src "libresoc.v:49286.18-49286.97" + wire width 4 $or$libresoc.v:49286$3024_Y + attribute \src "libresoc.v:49287.18-49287.126" + wire width 4 $or$libresoc.v:49287$3025_Y + attribute \src "libresoc.v:49288.18-49288.126" + wire width 4 $or$libresoc.v:49288$3026_Y + attribute \src "libresoc.v:49289.18-49289.97" + wire width 4 $or$libresoc.v:49289$3027_Y + attribute \src "libresoc.v:49290.18-49290.97" + wire width 4 $or$libresoc.v:49290$3028_Y + attribute \src "libresoc.v:49292.18-49292.126" + wire width 4 $or$libresoc.v:49292$3030_Y + attribute \src "libresoc.v:49293.17-49293.125" + wire width 4 $or$libresoc.v:49293$3031_Y + attribute \src "libresoc.v:49294.18-49294.126" + wire width 4 $or$libresoc.v:49294$3032_Y + attribute \src "libresoc.v:49295.18-49295.97" + wire width 4 $or$libresoc.v:49295$3033_Y + attribute \src "libresoc.v:49296.18-49296.126" + wire width 4 $or$libresoc.v:49296$3034_Y + attribute \src "libresoc.v:49297.18-49297.126" + wire width 4 $or$libresoc.v:49297$3035_Y + attribute \src "libresoc.v:49298.18-49298.97" + wire width 4 $or$libresoc.v:49298$3036_Y + attribute \src "libresoc.v:49299.18-49299.97" + wire width 4 $or$libresoc.v:49299$3037_Y + attribute \src "libresoc.v:49300.17-49300.125" + wire width 4 $or$libresoc.v:49300$3038_Y + attribute \src "libresoc.v:49301.17-49301.94" + wire width 4 $or$libresoc.v:49301$3039_Y + attribute \src "libresoc.v:49282.18-49282.100" + wire $reduce_or$libresoc.v:49282$3020_Y + attribute \src "libresoc.v:49283.17-49283.95" + wire $reduce_or$libresoc.v:49283$3021_Y + attribute \src "libresoc.v:49291.18-49291.100" + wire $reduce_or$libresoc.v:49291$3029_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -85909,9 +85705,9 @@ module \cr wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 14 \data_i @@ -85929,7 +85725,7 @@ module \cr wire width 32 input 12 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 13 \full_wr__wen - attribute \src "libresoc.v:49126.7-49126.15" + attribute \src "libresoc.v:48922.7-48922.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_dest10__data_i @@ -86216,7 +86012,7 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \wen$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49482$3016 + cell $or $or$libresoc.v:49278$3016 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86224,10 +86020,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src14__data_o connect \B \reg_5_src15__data_o - connect \Y $or$libresoc.v:49482$3016_Y + connect \Y $or$libresoc.v:49278$3016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49483$3017 + cell $or $or$libresoc.v:49279$3017 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86235,10 +86031,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src16__data_o connect \B \reg_7_src17__data_o - connect \Y $or$libresoc.v:49483$3017_Y + connect \Y $or$libresoc.v:49279$3017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49484$3018 + cell $or $or$libresoc.v:49280$3018 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86246,10 +86042,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:49484$3018_Y + connect \Y $or$libresoc.v:49280$3018_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49485$3019 + cell $or $or$libresoc.v:49281$3019 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86257,10 +86053,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$7 connect \B \$13 - connect \Y $or$libresoc.v:49485$3019_Y + connect \Y $or$libresoc.v:49281$3019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49488$3022 + cell $or $or$libresoc.v:49284$3022 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86268,10 +86064,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src20__data_o connect \B \reg_1_src21__data_o - connect \Y $or$libresoc.v:49488$3022_Y + connect \Y $or$libresoc.v:49284$3022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49489$3023 + cell $or $or$libresoc.v:49285$3023 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86279,10 +86075,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src22__data_o connect \B \reg_3_src23__data_o - connect \Y $or$libresoc.v:49489$3023_Y + connect \Y $or$libresoc.v:49285$3023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49490$3024 + cell $or $or$libresoc.v:49286$3024 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86290,10 +86086,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$20 connect \B \$22 - connect \Y $or$libresoc.v:49490$3024_Y + connect \Y $or$libresoc.v:49286$3024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49491$3025 + cell $or $or$libresoc.v:49287$3025 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86301,10 +86097,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src24__data_o connect \B \reg_5_src25__data_o - connect \Y $or$libresoc.v:49491$3025_Y + connect \Y $or$libresoc.v:49287$3025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49492$3026 + cell $or $or$libresoc.v:49288$3026 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86312,10 +86108,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src26__data_o connect \B \reg_7_src27__data_o - connect \Y $or$libresoc.v:49492$3026_Y + connect \Y $or$libresoc.v:49288$3026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49493$3027 + cell $or $or$libresoc.v:49289$3027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86323,10 +86119,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:49493$3027_Y + connect \Y $or$libresoc.v:49289$3027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49494$3028 + cell $or $or$libresoc.v:49290$3028 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86334,10 +86130,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$24 connect \B \$30 - connect \Y $or$libresoc.v:49494$3028_Y + connect \Y $or$libresoc.v:49290$3028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49496$3030 + cell $or $or$libresoc.v:49292$3030 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86345,10 +86141,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src30__data_o connect \B \reg_1_src31__data_o - connect \Y $or$libresoc.v:49496$3030_Y + connect \Y $or$libresoc.v:49292$3030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49497$3031 + cell $or $or$libresoc.v:49293$3031 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86356,10 +86152,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src10__data_o connect \B \reg_1_src11__data_o - connect \Y $or$libresoc.v:49497$3031_Y + connect \Y $or$libresoc.v:49293$3031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49498$3032 + cell $or $or$libresoc.v:49294$3032 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86367,10 +86163,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src32__data_o connect \B \reg_3_src33__data_o - connect \Y $or$libresoc.v:49498$3032_Y + connect \Y $or$libresoc.v:49294$3032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49499$3033 + cell $or $or$libresoc.v:49295$3033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86378,10 +86174,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:49499$3033_Y + connect \Y $or$libresoc.v:49295$3033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49500$3034 + cell $or $or$libresoc.v:49296$3034 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86389,10 +86185,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src34__data_o connect \B \reg_5_src35__data_o - connect \Y $or$libresoc.v:49500$3034_Y + connect \Y $or$libresoc.v:49296$3034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49501$3035 + cell $or $or$libresoc.v:49297$3035 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86400,10 +86196,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src36__data_o connect \B \reg_7_src37__data_o - connect \Y $or$libresoc.v:49501$3035_Y + connect \Y $or$libresoc.v:49297$3035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49502$3036 + cell $or $or$libresoc.v:49298$3036 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86411,10 +86207,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$43 connect \B \$45 - connect \Y $or$libresoc.v:49502$3036_Y + connect \Y $or$libresoc.v:49298$3036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49503$3037 + cell $or $or$libresoc.v:49299$3037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86422,10 +86218,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$41 connect \B \$47 - connect \Y $or$libresoc.v:49503$3037_Y + connect \Y $or$libresoc.v:49299$3037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49504$3038 + cell $or $or$libresoc.v:49300$3038 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86433,10 +86229,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src12__data_o connect \B \reg_3_src13__data_o - connect \Y $or$libresoc.v:49504$3038_Y + connect \Y $or$libresoc.v:49300$3038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49505$3039 + cell $or $or$libresoc.v:49301$3039 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86444,34 +86240,34 @@ module \cr parameter \Y_WIDTH 4 connect \A \$3 connect \B \$5 - connect \Y $or$libresoc.v:49505$3039_Y + connect \Y $or$libresoc.v:49301$3039_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49486$3020 + cell $reduce_or $reduce_or$libresoc.v:49282$3020 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$17 - connect \Y $reduce_or$libresoc.v:49486$3020_Y + connect \Y $reduce_or$libresoc.v:49282$3020_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49487$3021 + cell $reduce_or $reduce_or$libresoc.v:49283$3021 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:49487$3021_Y + connect \Y $reduce_or$libresoc.v:49283$3021_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49495$3029 + cell $reduce_or $reduce_or$libresoc.v:49291$3029 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$34 - connect \Y $reduce_or$libresoc.v:49495$3029_Y + connect \Y $reduce_or$libresoc.v:49291$3029_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:49512.9-49531.4" + attribute \src "libresoc.v:49308.9-49327.4" cell \reg_0 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86493,7 +86289,7 @@ module \cr connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49532.9-49551.4" + attribute \src "libresoc.v:49328.9-49347.4" cell \reg_1 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86515,7 +86311,7 @@ module \cr connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49552.9-49571.4" + attribute \src "libresoc.v:49348.9-49367.4" cell \reg_2 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86537,7 +86333,7 @@ module \cr connect \w2__wen \reg_2_w2__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49572.9-49591.4" + attribute \src "libresoc.v:49368.9-49387.4" cell \reg_3 \reg_3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86559,7 +86355,7 @@ module \cr connect \w3__wen \reg_3_w3__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49592.9-49611.4" + attribute \src "libresoc.v:49388.9-49407.4" cell \reg_4 \reg_4 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86581,7 +86377,7 @@ module \cr connect \w4__wen \reg_4_w4__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49612.9-49631.4" + attribute \src "libresoc.v:49408.9-49427.4" cell \reg_5 \reg_5 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86603,7 +86399,7 @@ module \cr connect \w5__wen \reg_5_w5__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49632.9-49651.4" + attribute \src "libresoc.v:49428.9-49447.4" cell \reg_6 \reg_6 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86625,7 +86421,7 @@ module \cr connect \w6__wen \reg_6_w6__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49652.9-49671.4" + attribute \src "libresoc.v:49448.9-49467.4" cell \reg_7 \reg_7 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86646,67 +86442,67 @@ module \cr connect \w7__data_i \reg_7_w7__data_i connect \w7__wen \reg_7_w7__wen end - attribute \src "libresoc.v:49126.7-49126.20" - process $proc$libresoc.v:49126$3057 + attribute \src "libresoc.v:48922.7-48922.20" + process $proc$libresoc.v:48922$3057 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49452.13-49452.30" - process $proc$libresoc.v:49452$3058 + attribute \src "libresoc.v:49248.13-49248.30" + process $proc$libresoc.v:49248$3058 assign { } { } assign $1\ren_delay[7:0] 8'00000000 sync always sync init update \ren_delay $1\ren_delay[7:0] end - attribute \src "libresoc.v:49454.13-49454.35" - process $proc$libresoc.v:49454$3059 + attribute \src "libresoc.v:49250.13-49250.35" + process $proc$libresoc.v:49250$3059 assign { } { } assign $0\ren_delay$17[7:0]$3060 8'00000000 sync always sync init update \ren_delay$17 $0\ren_delay$17[7:0]$3060 end - attribute \src "libresoc.v:49458.13-49458.35" - process $proc$libresoc.v:49458$3061 + attribute \src "libresoc.v:49254.13-49254.35" + process $proc$libresoc.v:49254$3061 assign { } { } assign $0\ren_delay$34[7:0]$3062 8'00000000 sync always sync init update \ren_delay$34 $0\ren_delay$34[7:0]$3062 end - attribute \src "libresoc.v:49506.3-49507.43" - process $proc$libresoc.v:49506$3040 + attribute \src "libresoc.v:49302.3-49303.43" + process $proc$libresoc.v:49302$3040 assign { } { } assign $0\ren_delay$34[7:0]$3041 \ren_delay$34$next sync posedge \coresync_clk update \ren_delay$34 $0\ren_delay$34[7:0]$3041 end - attribute \src "libresoc.v:49508.3-49509.43" - process $proc$libresoc.v:49508$3042 + attribute \src "libresoc.v:49304.3-49305.43" + process $proc$libresoc.v:49304$3042 assign { } { } assign $0\ren_delay$17[7:0]$3043 \ren_delay$17$next sync posedge \coresync_clk update \ren_delay$17 $0\ren_delay$17[7:0]$3043 end - attribute \src "libresoc.v:49510.3-49511.35" - process $proc$libresoc.v:49510$3044 + attribute \src "libresoc.v:49306.3-49307.35" + process $proc$libresoc.v:49306$3044 assign { } { } assign $0\ren_delay[7:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[7:0] end - attribute \src "libresoc.v:49672.3-49680.6" - process $proc$libresoc.v:49672$3045 + attribute \src "libresoc.v:49468.3-49476.6" + process $proc$libresoc.v:49468$3045 assign { } { } assign { } { } assign $0\ren_delay$17$next[7:0]$3046 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49673.5-49673.29" + attribute \src "libresoc.v:49469.5-49469.29" switch \initial - attribute \src "libresoc.v:49673.9-49673.17" + attribute \src "libresoc.v:49469.9-49469.17" case 1'1 case end @@ -86722,14 +86518,14 @@ module \cr sync always update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3046 end - attribute \src "libresoc.v:49681.3-49690.6" - process $proc$libresoc.v:49681$3048 + attribute \src "libresoc.v:49477.3-49486.6" + process $proc$libresoc.v:49477$3048 assign { } { } assign { } { } assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] - attribute \src "libresoc.v:49682.5-49682.29" + attribute \src "libresoc.v:49478.5-49478.29" switch \initial - attribute \src "libresoc.v:49682.9-49682.17" + attribute \src "libresoc.v:49478.9-49478.17" case 1'1 case end @@ -86745,14 +86541,14 @@ module \cr sync always update \src2__data_o $0\src2__data_o[3:0] end - attribute \src "libresoc.v:49691.3-49699.6" - process $proc$libresoc.v:49691$3049 + attribute \src "libresoc.v:49487.3-49495.6" + process $proc$libresoc.v:49487$3049 assign { } { } assign { } { } assign $0\ren_delay$34$next[7:0]$3050 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49692.5-49692.29" + attribute \src "libresoc.v:49488.5-49488.29" switch \initial - attribute \src "libresoc.v:49692.9-49692.17" + attribute \src "libresoc.v:49488.9-49488.17" case 1'1 case end @@ -86768,14 +86564,14 @@ module \cr sync always update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3050 end - attribute \src "libresoc.v:49700.3-49709.6" - process $proc$libresoc.v:49700$3052 + attribute \src "libresoc.v:49496.3-49505.6" + process $proc$libresoc.v:49496$3052 assign { } { } assign { } { } assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] - attribute \src "libresoc.v:49701.5-49701.29" + attribute \src "libresoc.v:49497.5-49497.29" switch \initial - attribute \src "libresoc.v:49701.9-49701.17" + attribute \src "libresoc.v:49497.9-49497.17" case 1'1 case end @@ -86791,14 +86587,14 @@ module \cr sync always update \src3__data_o $0\src3__data_o[3:0] end - attribute \src "libresoc.v:49710.3-49718.6" - process $proc$libresoc.v:49710$3053 + attribute \src "libresoc.v:49506.3-49514.6" + process $proc$libresoc.v:49506$3053 assign { } { } assign { } { } assign $0\ren_delay$next[7:0]$3054 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:49711.5-49711.29" + attribute \src "libresoc.v:49507.5-49507.29" switch \initial - attribute \src "libresoc.v:49711.9-49711.17" + attribute \src "libresoc.v:49507.9-49507.17" case 1'1 case end @@ -86814,14 +86610,14 @@ module \cr sync always update \ren_delay$next $0\ren_delay$next[7:0]$3054 end - attribute \src "libresoc.v:49719.3-49728.6" - process $proc$libresoc.v:49719$3056 + attribute \src "libresoc.v:49515.3-49524.6" + process $proc$libresoc.v:49515$3056 assign { } { } assign { } { } assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] - attribute \src "libresoc.v:49720.5-49720.29" + attribute \src "libresoc.v:49516.5-49516.29" switch \initial - attribute \src "libresoc.v:49720.9-49720.17" + attribute \src "libresoc.v:49516.9-49516.17" case 1'1 case end @@ -86837,30 +86633,30 @@ module \cr sync always update \src1__data_o $0\src1__data_o[3:0] end - connect \$9 $or$libresoc.v:49482$3016_Y - connect \$11 $or$libresoc.v:49483$3017_Y - connect \$13 $or$libresoc.v:49484$3018_Y - connect \$15 $or$libresoc.v:49485$3019_Y - connect \$18 $reduce_or$libresoc.v:49486$3020_Y - connect \$1 $reduce_or$libresoc.v:49487$3021_Y - connect \$20 $or$libresoc.v:49488$3022_Y - connect \$22 $or$libresoc.v:49489$3023_Y - connect \$24 $or$libresoc.v:49490$3024_Y - connect \$26 $or$libresoc.v:49491$3025_Y - connect \$28 $or$libresoc.v:49492$3026_Y - connect \$30 $or$libresoc.v:49493$3027_Y - connect \$32 $or$libresoc.v:49494$3028_Y - connect \$35 $reduce_or$libresoc.v:49495$3029_Y - connect \$37 $or$libresoc.v:49496$3030_Y - connect \$3 $or$libresoc.v:49497$3031_Y - connect \$39 $or$libresoc.v:49498$3032_Y - connect \$41 $or$libresoc.v:49499$3033_Y - connect \$43 $or$libresoc.v:49500$3034_Y - connect \$45 $or$libresoc.v:49501$3035_Y - connect \$47 $or$libresoc.v:49502$3036_Y - connect \$49 $or$libresoc.v:49503$3037_Y - connect \$5 $or$libresoc.v:49504$3038_Y - connect \$7 $or$libresoc.v:49505$3039_Y + connect \$9 $or$libresoc.v:49278$3016_Y + connect \$11 $or$libresoc.v:49279$3017_Y + connect \$13 $or$libresoc.v:49280$3018_Y + connect \$15 $or$libresoc.v:49281$3019_Y + connect \$18 $reduce_or$libresoc.v:49282$3020_Y + connect \$1 $reduce_or$libresoc.v:49283$3021_Y + connect \$20 $or$libresoc.v:49284$3022_Y + connect \$22 $or$libresoc.v:49285$3023_Y + connect \$24 $or$libresoc.v:49286$3024_Y + connect \$26 $or$libresoc.v:49287$3025_Y + connect \$28 $or$libresoc.v:49288$3026_Y + connect \$30 $or$libresoc.v:49289$3027_Y + connect \$32 $or$libresoc.v:49290$3028_Y + connect \$35 $reduce_or$libresoc.v:49291$3029_Y + connect \$37 $or$libresoc.v:49292$3030_Y + connect \$3 $or$libresoc.v:49293$3031_Y + connect \$39 $or$libresoc.v:49294$3032_Y + connect \$41 $or$libresoc.v:49295$3033_Y + connect \$43 $or$libresoc.v:49296$3034_Y + connect \$45 $or$libresoc.v:49297$3035_Y + connect \$47 $or$libresoc.v:49298$3036_Y + connect \$49 $or$libresoc.v:49299$3037_Y + connect \$5 $or$libresoc.v:49300$3038_Y + connect \$7 $or$libresoc.v:49301$3039_Y connect \wen$51 8'00000000 connect \data_i$52 4'0000 connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen @@ -86891,393 +86687,393 @@ module \cr connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:49762.1-50819.10" +attribute \src "libresoc.v:49558.1-50615.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" attribute \generator "nMigen" module \cr0 - attribute \src "libresoc.v:50420.3-50421.25" + attribute \src "libresoc.v:50216.3-50217.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:50593.3-50604.6" + attribute \src "libresoc.v:50389.3-50400.6" wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 - attribute \src "libresoc.v:50392.3-50393.61" + attribute \src "libresoc.v:50188.3-50189.61" wire width 14 $0\alu_cr0_cr_op__fn_unit[13:0] - attribute \src "libresoc.v:50593.3-50604.6" + attribute \src "libresoc.v:50389.3-50400.6" wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3183 - attribute \src "libresoc.v:50394.3-50395.55" + attribute \src "libresoc.v:50190.3-50191.55" wire width 32 $0\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50593.3-50604.6" + attribute \src "libresoc.v:50389.3-50400.6" wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 - attribute \src "libresoc.v:50390.3-50391.65" + attribute \src "libresoc.v:50186.3-50187.65" wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50418.3-50419.39" + attribute \src "libresoc.v:50214.3-50215.39" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:50740.3-50748.6" + attribute \src "libresoc.v:50536.3-50544.6" wire $0\alu_l_r_alu$next[0:0]$3234 - attribute \src "libresoc.v:50362.3-50363.39" + attribute \src "libresoc.v:50158.3-50159.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50731.3-50739.6" + attribute \src "libresoc.v:50527.3-50535.6" wire $0\alui_l_r_alui$next[0:0]$3231 - attribute \src "libresoc.v:50364.3-50365.43" + attribute \src "libresoc.v:50160.3-50161.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50605.3-50626.6" + attribute \src "libresoc.v:50401.3-50422.6" wire width 64 $0\data_r0__o$next[63:0]$3189 - attribute \src "libresoc.v:50386.3-50387.37" + attribute \src "libresoc.v:50182.3-50183.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:50605.3-50626.6" + attribute \src "libresoc.v:50401.3-50422.6" wire $0\data_r0__o_ok$next[0:0]$3190 - attribute \src "libresoc.v:50388.3-50389.43" + attribute \src "libresoc.v:50184.3-50185.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50627.3-50648.6" + attribute \src "libresoc.v:50423.3-50444.6" wire width 32 $0\data_r1__full_cr$next[31:0]$3197 - attribute \src "libresoc.v:50382.3-50383.49" + attribute \src "libresoc.v:50178.3-50179.49" wire width 32 $0\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50627.3-50648.6" + attribute \src "libresoc.v:50423.3-50444.6" wire $0\data_r1__full_cr_ok$next[0:0]$3198 - attribute \src "libresoc.v:50384.3-50385.55" + attribute \src "libresoc.v:50180.3-50181.55" wire $0\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50649.3-50670.6" + attribute \src "libresoc.v:50445.3-50466.6" wire width 4 $0\data_r2__cr_a$next[3:0]$3205 - attribute \src "libresoc.v:50378.3-50379.43" + attribute \src "libresoc.v:50174.3-50175.43" wire width 4 $0\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50649.3-50670.6" + attribute \src "libresoc.v:50445.3-50466.6" wire $0\data_r2__cr_a_ok$next[0:0]$3206 - attribute \src "libresoc.v:50380.3-50381.49" + attribute \src "libresoc.v:50176.3-50177.49" wire $0\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50749.3-50758.6" + attribute \src "libresoc.v:50545.3-50554.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:50759.3-50768.6" + attribute \src "libresoc.v:50555.3-50564.6" wire width 32 $0\dest2_o[31:0] - attribute \src "libresoc.v:50769.3-50778.6" + attribute \src "libresoc.v:50565.3-50574.6" wire width 4 $0\dest3_o[3:0] - attribute \src "libresoc.v:49763.7-49763.20" + attribute \src "libresoc.v:49559.7-49559.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50548.3-50556.6" + attribute \src "libresoc.v:50344.3-50352.6" wire $0\opc_l_r_opc$next[0:0]$3167 - attribute \src "libresoc.v:50404.3-50405.39" + attribute \src "libresoc.v:50200.3-50201.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50539.3-50547.6" + attribute \src "libresoc.v:50335.3-50343.6" wire $0\opc_l_s_opc$next[0:0]$3164 - attribute \src "libresoc.v:50406.3-50407.39" + attribute \src "libresoc.v:50202.3-50203.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50779.3-50787.6" + attribute \src "libresoc.v:50575.3-50583.6" wire width 3 $0\prev_wr_go$next[2:0]$3240 - attribute \src "libresoc.v:50416.3-50417.37" + attribute \src "libresoc.v:50212.3-50213.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:50493.3-50502.6" + attribute \src "libresoc.v:50289.3-50298.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:50584.3-50592.6" + attribute \src "libresoc.v:50380.3-50388.6" wire width 3 $0\req_l_r_req$next[2:0]$3179 - attribute \src "libresoc.v:50396.3-50397.39" + attribute \src "libresoc.v:50192.3-50193.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:50575.3-50583.6" + attribute \src "libresoc.v:50371.3-50379.6" wire width 3 $0\req_l_s_req$next[2:0]$3176 - attribute \src "libresoc.v:50398.3-50399.39" + attribute \src "libresoc.v:50194.3-50195.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:50512.3-50520.6" + attribute \src "libresoc.v:50308.3-50316.6" wire $0\rok_l_r_rdok$next[0:0]$3155 - attribute \src "libresoc.v:50412.3-50413.41" + attribute \src "libresoc.v:50208.3-50209.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50503.3-50511.6" + attribute \src "libresoc.v:50299.3-50307.6" wire $0\rok_l_s_rdok$next[0:0]$3152 - attribute \src "libresoc.v:50414.3-50415.41" + attribute \src "libresoc.v:50210.3-50211.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50530.3-50538.6" + attribute \src "libresoc.v:50326.3-50334.6" wire $0\rst_l_r_rst$next[0:0]$3161 - attribute \src "libresoc.v:50408.3-50409.39" + attribute \src "libresoc.v:50204.3-50205.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50521.3-50529.6" + attribute \src "libresoc.v:50317.3-50325.6" wire $0\rst_l_s_rst$next[0:0]$3158 - attribute \src "libresoc.v:50410.3-50411.39" + attribute \src "libresoc.v:50206.3-50207.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50566.3-50574.6" + attribute \src "libresoc.v:50362.3-50370.6" wire width 6 $0\src_l_r_src$next[5:0]$3173 - attribute \src "libresoc.v:50400.3-50401.39" + attribute \src "libresoc.v:50196.3-50197.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:50557.3-50565.6" + attribute \src "libresoc.v:50353.3-50361.6" wire width 6 $0\src_l_s_src$next[5:0]$3170 - attribute \src "libresoc.v:50402.3-50403.39" + attribute \src "libresoc.v:50198.3-50199.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:50671.3-50680.6" + attribute \src "libresoc.v:50467.3-50476.6" wire width 64 $0\src_r0$next[63:0]$3213 - attribute \src "libresoc.v:50376.3-50377.29" + attribute \src "libresoc.v:50172.3-50173.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:50681.3-50690.6" + attribute \src "libresoc.v:50477.3-50486.6" wire width 64 $0\src_r1$next[63:0]$3216 - attribute \src "libresoc.v:50374.3-50375.29" + attribute \src "libresoc.v:50170.3-50171.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:50691.3-50700.6" + attribute \src "libresoc.v:50487.3-50496.6" wire width 32 $0\src_r2$next[31:0]$3219 - attribute \src "libresoc.v:50372.3-50373.29" + attribute \src "libresoc.v:50168.3-50169.29" wire width 32 $0\src_r2[31:0] - attribute \src "libresoc.v:50701.3-50710.6" + attribute \src "libresoc.v:50497.3-50506.6" wire width 4 $0\src_r3$next[3:0]$3222 - attribute \src "libresoc.v:50370.3-50371.29" + attribute \src "libresoc.v:50166.3-50167.29" wire width 4 $0\src_r3[3:0] - attribute \src "libresoc.v:50711.3-50720.6" + attribute \src "libresoc.v:50507.3-50516.6" wire width 4 $0\src_r4$next[3:0]$3225 - attribute \src "libresoc.v:50368.3-50369.29" + attribute \src "libresoc.v:50164.3-50165.29" wire width 4 $0\src_r4[3:0] - attribute \src "libresoc.v:50721.3-50730.6" + attribute \src "libresoc.v:50517.3-50526.6" wire width 4 $0\src_r5$next[3:0]$3228 - attribute \src "libresoc.v:50366.3-50367.29" + attribute \src "libresoc.v:50162.3-50163.29" wire width 4 $0\src_r5[3:0] - attribute \src "libresoc.v:49881.7-49881.24" + attribute \src "libresoc.v:49677.7-49677.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:50593.3-50604.6" + attribute \src "libresoc.v:50389.3-50400.6" wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 - attribute \src "libresoc.v:49912.14-49912.47" + attribute \src "libresoc.v:49708.14-49708.47" wire width 14 $1\alu_cr0_cr_op__fn_unit[13:0] - attribute \src "libresoc.v:50593.3-50604.6" + attribute \src "libresoc.v:50389.3-50400.6" wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3186 - attribute \src "libresoc.v:49916.14-49916.41" + attribute \src "libresoc.v:49712.14-49712.41" wire width 32 $1\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50593.3-50604.6" + attribute \src "libresoc.v:50389.3-50400.6" wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:49995.13-49995.45" + attribute \src "libresoc.v:49791.13-49791.45" wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50019.7-50019.26" + attribute \src "libresoc.v:49815.7-49815.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:50740.3-50748.6" + attribute \src "libresoc.v:50536.3-50544.6" wire $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:50027.7-50027.25" + attribute \src "libresoc.v:49823.7-49823.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50731.3-50739.6" + attribute \src "libresoc.v:50527.3-50535.6" wire $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:50039.7-50039.27" + attribute \src "libresoc.v:49835.7-49835.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50605.3-50626.6" + attribute \src "libresoc.v:50401.3-50422.6" wire width 64 $1\data_r0__o$next[63:0]$3191 - attribute \src "libresoc.v:50073.14-50073.47" + attribute \src "libresoc.v:49869.14-49869.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:50605.3-50626.6" + attribute \src "libresoc.v:50401.3-50422.6" wire $1\data_r0__o_ok$next[0:0]$3192 - attribute \src "libresoc.v:50077.7-50077.27" + attribute \src "libresoc.v:49873.7-49873.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50627.3-50648.6" + attribute \src "libresoc.v:50423.3-50444.6" wire width 32 $1\data_r1__full_cr$next[31:0]$3199 - attribute \src "libresoc.v:50081.14-50081.38" + attribute \src "libresoc.v:49877.14-49877.38" wire width 32 $1\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50627.3-50648.6" + attribute \src "libresoc.v:50423.3-50444.6" wire $1\data_r1__full_cr_ok$next[0:0]$3200 - attribute \src "libresoc.v:50085.7-50085.33" + attribute \src "libresoc.v:49881.7-49881.33" wire $1\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50649.3-50670.6" + attribute \src "libresoc.v:50445.3-50466.6" wire width 4 $1\data_r2__cr_a$next[3:0]$3207 - attribute \src "libresoc.v:50089.13-50089.33" + attribute \src "libresoc.v:49885.13-49885.33" wire width 4 $1\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50649.3-50670.6" + attribute \src "libresoc.v:50445.3-50466.6" wire $1\data_r2__cr_a_ok$next[0:0]$3208 - attribute \src "libresoc.v:50093.7-50093.30" + attribute \src "libresoc.v:49889.7-49889.30" wire $1\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50749.3-50758.6" + attribute \src "libresoc.v:50545.3-50554.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:50759.3-50768.6" + attribute \src "libresoc.v:50555.3-50564.6" wire width 32 $1\dest2_o[31:0] - attribute \src "libresoc.v:50769.3-50778.6" + attribute \src "libresoc.v:50565.3-50574.6" wire width 4 $1\dest3_o[3:0] - attribute \src "libresoc.v:50548.3-50556.6" + attribute \src "libresoc.v:50344.3-50352.6" wire $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:50112.7-50112.25" + attribute \src "libresoc.v:49908.7-49908.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50539.3-50547.6" + attribute \src "libresoc.v:50335.3-50343.6" wire $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:50116.7-50116.25" + attribute \src "libresoc.v:49912.7-49912.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50779.3-50787.6" + attribute \src "libresoc.v:50575.3-50583.6" wire width 3 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:50216.13-50216.30" + attribute \src "libresoc.v:50012.13-50012.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:50493.3-50502.6" + attribute \src "libresoc.v:50289.3-50298.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:50584.3-50592.6" + attribute \src "libresoc.v:50380.3-50388.6" wire width 3 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:50224.13-50224.31" + attribute \src "libresoc.v:50020.13-50020.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:50575.3-50583.6" + attribute \src "libresoc.v:50371.3-50379.6" wire width 3 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:50228.13-50228.31" + attribute \src "libresoc.v:50024.13-50024.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:50512.3-50520.6" + attribute \src "libresoc.v:50308.3-50316.6" wire $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:50240.7-50240.26" + attribute \src "libresoc.v:50036.7-50036.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50503.3-50511.6" + attribute \src "libresoc.v:50299.3-50307.6" wire $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:50244.7-50244.26" + attribute \src "libresoc.v:50040.7-50040.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50530.3-50538.6" + attribute \src "libresoc.v:50326.3-50334.6" wire $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:50248.7-50248.25" + attribute \src "libresoc.v:50044.7-50044.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50521.3-50529.6" + attribute \src "libresoc.v:50317.3-50325.6" wire $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:50252.7-50252.25" + attribute \src "libresoc.v:50048.7-50048.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50566.3-50574.6" + attribute \src "libresoc.v:50362.3-50370.6" wire width 6 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:50272.13-50272.32" + attribute \src "libresoc.v:50068.13-50068.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:50557.3-50565.6" + attribute \src "libresoc.v:50353.3-50361.6" wire width 6 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:50276.13-50276.32" + attribute \src "libresoc.v:50072.13-50072.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:50671.3-50680.6" + attribute \src "libresoc.v:50467.3-50476.6" wire width 64 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:50280.14-50280.43" + attribute \src "libresoc.v:50076.14-50076.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:50681.3-50690.6" + attribute \src "libresoc.v:50477.3-50486.6" wire width 64 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:50284.14-50284.43" + attribute \src "libresoc.v:50080.14-50080.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:50691.3-50700.6" + attribute \src "libresoc.v:50487.3-50496.6" wire width 32 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:50288.14-50288.28" + attribute \src "libresoc.v:50084.14-50084.28" wire width 32 $1\src_r2[31:0] - attribute \src "libresoc.v:50701.3-50710.6" + attribute \src "libresoc.v:50497.3-50506.6" wire width 4 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:50292.13-50292.26" + attribute \src "libresoc.v:50088.13-50088.26" wire width 4 $1\src_r3[3:0] - attribute \src "libresoc.v:50711.3-50720.6" + attribute \src "libresoc.v:50507.3-50516.6" wire width 4 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:50296.13-50296.26" + attribute \src "libresoc.v:50092.13-50092.26" wire width 4 $1\src_r4[3:0] - attribute \src "libresoc.v:50721.3-50730.6" + attribute \src "libresoc.v:50517.3-50526.6" wire width 4 $1\src_r5$next[3:0]$3229 - attribute \src "libresoc.v:50300.13-50300.26" + attribute \src "libresoc.v:50096.13-50096.26" wire width 4 $1\src_r5[3:0] - attribute \src "libresoc.v:50605.3-50626.6" + attribute \src "libresoc.v:50401.3-50422.6" wire width 64 $2\data_r0__o$next[63:0]$3193 - attribute \src "libresoc.v:50605.3-50626.6" + attribute \src "libresoc.v:50401.3-50422.6" wire $2\data_r0__o_ok$next[0:0]$3194 - attribute \src "libresoc.v:50627.3-50648.6" + attribute \src "libresoc.v:50423.3-50444.6" wire width 32 $2\data_r1__full_cr$next[31:0]$3201 - attribute \src "libresoc.v:50627.3-50648.6" + attribute \src "libresoc.v:50423.3-50444.6" wire $2\data_r1__full_cr_ok$next[0:0]$3202 - attribute \src "libresoc.v:50649.3-50670.6" + attribute \src "libresoc.v:50445.3-50466.6" wire width 4 $2\data_r2__cr_a$next[3:0]$3209 - attribute \src "libresoc.v:50649.3-50670.6" + attribute \src "libresoc.v:50445.3-50466.6" wire $2\data_r2__cr_a_ok$next[0:0]$3210 - attribute \src "libresoc.v:50605.3-50626.6" + attribute \src "libresoc.v:50401.3-50422.6" wire $3\data_r0__o_ok$next[0:0]$3195 - attribute \src "libresoc.v:50627.3-50648.6" + attribute \src "libresoc.v:50423.3-50444.6" wire $3\data_r1__full_cr_ok$next[0:0]$3203 - attribute \src "libresoc.v:50649.3-50670.6" + attribute \src "libresoc.v:50445.3-50466.6" wire $3\data_r2__cr_a_ok$next[0:0]$3211 - attribute \src "libresoc.v:50306.18-50306.112" - wire width 6 $and$libresoc.v:50306$3064_Y - attribute \src "libresoc.v:50307.19-50307.125" - wire $and$libresoc.v:50307$3065_Y - attribute \src "libresoc.v:50308.19-50308.125" - wire $and$libresoc.v:50308$3066_Y - attribute \src "libresoc.v:50309.19-50309.125" - wire $and$libresoc.v:50309$3067_Y - attribute \src "libresoc.v:50310.19-50310.141" - wire width 3 $and$libresoc.v:50310$3068_Y - attribute \src "libresoc.v:50311.19-50311.121" - wire width 3 $and$libresoc.v:50311$3069_Y - attribute \src "libresoc.v:50312.19-50312.127" - wire $and$libresoc.v:50312$3070_Y - attribute \src "libresoc.v:50313.19-50313.127" - wire $and$libresoc.v:50313$3071_Y - attribute \src "libresoc.v:50314.19-50314.127" - wire $and$libresoc.v:50314$3072_Y - attribute \src "libresoc.v:50315.18-50315.110" - wire $and$libresoc.v:50315$3073_Y - attribute \src "libresoc.v:50317.18-50317.98" - wire $and$libresoc.v:50317$3075_Y - attribute \src "libresoc.v:50319.18-50319.100" - wire $and$libresoc.v:50319$3077_Y - attribute \src "libresoc.v:50320.18-50320.149" - wire width 3 $and$libresoc.v:50320$3078_Y - attribute \src "libresoc.v:50322.18-50322.119" - wire width 3 $and$libresoc.v:50322$3080_Y - attribute \src "libresoc.v:50325.18-50325.116" - wire $and$libresoc.v:50325$3083_Y - attribute \src "libresoc.v:50329.17-50329.123" - wire $and$libresoc.v:50329$3087_Y - attribute \src "libresoc.v:50331.18-50331.113" - wire $and$libresoc.v:50331$3089_Y - attribute \src "libresoc.v:50332.18-50332.125" - wire width 3 $and$libresoc.v:50332$3090_Y - attribute \src "libresoc.v:50334.18-50334.112" - wire $and$libresoc.v:50334$3092_Y - attribute \src "libresoc.v:50336.18-50336.125" - wire $and$libresoc.v:50336$3094_Y - attribute \src "libresoc.v:50337.18-50337.125" - wire $and$libresoc.v:50337$3095_Y - attribute \src "libresoc.v:50338.18-50338.117" - wire $and$libresoc.v:50338$3096_Y - attribute \src "libresoc.v:50343.18-50343.129" - wire $and$libresoc.v:50343$3101_Y - attribute \src "libresoc.v:50344.18-50344.124" - wire width 3 $and$libresoc.v:50344$3102_Y - attribute \src "libresoc.v:50347.18-50347.116" - wire $and$libresoc.v:50347$3105_Y - attribute \src "libresoc.v:50348.18-50348.122" - wire $and$libresoc.v:50348$3106_Y - attribute \src "libresoc.v:50349.18-50349.119" - wire $and$libresoc.v:50349$3107_Y - attribute \src "libresoc.v:50357.18-50357.133" - wire $and$libresoc.v:50357$3115_Y - attribute \src "libresoc.v:50358.18-50358.131" - wire $and$libresoc.v:50358$3116_Y - attribute \src "libresoc.v:50359.18-50359.182" - wire width 6 $and$libresoc.v:50359$3117_Y - attribute \src "libresoc.v:50360.18-50360.113" - wire width 6 $and$libresoc.v:50360$3118_Y - attribute \src "libresoc.v:50333.18-50333.113" - wire $eq$libresoc.v:50333$3091_Y - attribute \src "libresoc.v:50335.18-50335.119" - wire $eq$libresoc.v:50335$3093_Y - attribute \src "libresoc.v:50316.18-50316.97" - wire $not$libresoc.v:50316$3074_Y - attribute \src "libresoc.v:50318.18-50318.99" - wire $not$libresoc.v:50318$3076_Y - attribute \src "libresoc.v:50321.18-50321.113" - wire width 3 $not$libresoc.v:50321$3079_Y - attribute \src "libresoc.v:50324.18-50324.106" - wire $not$libresoc.v:50324$3082_Y - attribute \src "libresoc.v:50330.18-50330.119" - wire $not$libresoc.v:50330$3088_Y - attribute \src "libresoc.v:50345.17-50345.113" - wire width 6 $not$libresoc.v:50345$3103_Y - attribute \src "libresoc.v:50361.18-50361.114" - wire width 6 $not$libresoc.v:50361$3119_Y - attribute \src "libresoc.v:50328.18-50328.112" - wire $or$libresoc.v:50328$3086_Y - attribute \src "libresoc.v:50339.18-50339.122" - wire $or$libresoc.v:50339$3097_Y - attribute \src "libresoc.v:50340.18-50340.124" - wire $or$libresoc.v:50340$3098_Y - attribute \src "libresoc.v:50341.18-50341.155" - wire width 3 $or$libresoc.v:50341$3099_Y - attribute \src "libresoc.v:50342.18-50342.194" - wire width 6 $or$libresoc.v:50342$3100_Y - attribute \src "libresoc.v:50346.18-50346.120" - wire width 3 $or$libresoc.v:50346$3104_Y - attribute \src "libresoc.v:50356.17-50356.117" - wire width 6 $or$libresoc.v:50356$3114_Y - attribute \src "libresoc.v:50305.17-50305.104" - wire $reduce_and$libresoc.v:50305$3063_Y - attribute \src "libresoc.v:50323.18-50323.106" - wire $reduce_or$libresoc.v:50323$3081_Y - attribute \src "libresoc.v:50326.18-50326.113" - wire $reduce_or$libresoc.v:50326$3084_Y - attribute \src "libresoc.v:50327.18-50327.112" - wire $reduce_or$libresoc.v:50327$3085_Y - attribute \src "libresoc.v:50350.18-50350.118" - wire width 64 $ternary$libresoc.v:50350$3108_Y - attribute \src "libresoc.v:50351.18-50351.118" - wire width 64 $ternary$libresoc.v:50351$3109_Y - attribute \src "libresoc.v:50352.18-50352.118" - wire width 32 $ternary$libresoc.v:50352$3110_Y - attribute \src "libresoc.v:50353.18-50353.118" - wire width 4 $ternary$libresoc.v:50353$3111_Y - attribute \src "libresoc.v:50354.18-50354.118" - wire width 4 $ternary$libresoc.v:50354$3112_Y - attribute \src "libresoc.v:50355.18-50355.118" - wire width 4 $ternary$libresoc.v:50355$3113_Y + attribute \src "libresoc.v:50102.18-50102.112" + wire width 6 $and$libresoc.v:50102$3064_Y + attribute \src "libresoc.v:50103.19-50103.125" + wire $and$libresoc.v:50103$3065_Y + attribute \src "libresoc.v:50104.19-50104.125" + wire $and$libresoc.v:50104$3066_Y + attribute \src "libresoc.v:50105.19-50105.125" + wire $and$libresoc.v:50105$3067_Y + attribute \src "libresoc.v:50106.19-50106.141" + wire width 3 $and$libresoc.v:50106$3068_Y + attribute \src "libresoc.v:50107.19-50107.121" + wire width 3 $and$libresoc.v:50107$3069_Y + attribute \src "libresoc.v:50108.19-50108.127" + wire $and$libresoc.v:50108$3070_Y + attribute \src "libresoc.v:50109.19-50109.127" + wire $and$libresoc.v:50109$3071_Y + attribute \src "libresoc.v:50110.19-50110.127" + wire $and$libresoc.v:50110$3072_Y + attribute \src "libresoc.v:50111.18-50111.110" + wire $and$libresoc.v:50111$3073_Y + attribute \src "libresoc.v:50113.18-50113.98" + wire $and$libresoc.v:50113$3075_Y + attribute \src "libresoc.v:50115.18-50115.100" + wire $and$libresoc.v:50115$3077_Y + attribute \src "libresoc.v:50116.18-50116.149" + wire width 3 $and$libresoc.v:50116$3078_Y + attribute \src "libresoc.v:50118.18-50118.119" + wire width 3 $and$libresoc.v:50118$3080_Y + attribute \src "libresoc.v:50121.18-50121.116" + wire $and$libresoc.v:50121$3083_Y + attribute \src "libresoc.v:50125.17-50125.123" + wire $and$libresoc.v:50125$3087_Y + attribute \src "libresoc.v:50127.18-50127.113" + wire $and$libresoc.v:50127$3089_Y + attribute \src "libresoc.v:50128.18-50128.125" + wire width 3 $and$libresoc.v:50128$3090_Y + attribute \src "libresoc.v:50130.18-50130.112" + wire $and$libresoc.v:50130$3092_Y + attribute \src "libresoc.v:50132.18-50132.125" + wire $and$libresoc.v:50132$3094_Y + attribute \src "libresoc.v:50133.18-50133.125" + wire $and$libresoc.v:50133$3095_Y + attribute \src "libresoc.v:50134.18-50134.117" + wire $and$libresoc.v:50134$3096_Y + attribute \src "libresoc.v:50139.18-50139.129" + wire $and$libresoc.v:50139$3101_Y + attribute \src "libresoc.v:50140.18-50140.124" + wire width 3 $and$libresoc.v:50140$3102_Y + attribute \src "libresoc.v:50143.18-50143.116" + wire $and$libresoc.v:50143$3105_Y + attribute \src "libresoc.v:50144.18-50144.122" + wire $and$libresoc.v:50144$3106_Y + attribute \src "libresoc.v:50145.18-50145.119" + wire $and$libresoc.v:50145$3107_Y + attribute \src "libresoc.v:50153.18-50153.133" + wire $and$libresoc.v:50153$3115_Y + attribute \src "libresoc.v:50154.18-50154.131" + wire $and$libresoc.v:50154$3116_Y + attribute \src "libresoc.v:50155.18-50155.182" + wire width 6 $and$libresoc.v:50155$3117_Y + attribute \src "libresoc.v:50156.18-50156.113" + wire width 6 $and$libresoc.v:50156$3118_Y + attribute \src "libresoc.v:50129.18-50129.113" + wire $eq$libresoc.v:50129$3091_Y + attribute \src "libresoc.v:50131.18-50131.119" + wire $eq$libresoc.v:50131$3093_Y + attribute \src "libresoc.v:50112.18-50112.97" + wire $not$libresoc.v:50112$3074_Y + attribute \src "libresoc.v:50114.18-50114.99" + wire $not$libresoc.v:50114$3076_Y + attribute \src "libresoc.v:50117.18-50117.113" + wire width 3 $not$libresoc.v:50117$3079_Y + attribute \src "libresoc.v:50120.18-50120.106" + wire $not$libresoc.v:50120$3082_Y + attribute \src "libresoc.v:50126.18-50126.119" + wire $not$libresoc.v:50126$3088_Y + attribute \src "libresoc.v:50141.17-50141.113" + wire width 6 $not$libresoc.v:50141$3103_Y + attribute \src "libresoc.v:50157.18-50157.114" + wire width 6 $not$libresoc.v:50157$3119_Y + attribute \src "libresoc.v:50124.18-50124.112" + wire $or$libresoc.v:50124$3086_Y + attribute \src "libresoc.v:50135.18-50135.122" + wire $or$libresoc.v:50135$3097_Y + attribute \src "libresoc.v:50136.18-50136.124" + wire $or$libresoc.v:50136$3098_Y + attribute \src "libresoc.v:50137.18-50137.155" + wire width 3 $or$libresoc.v:50137$3099_Y + attribute \src "libresoc.v:50138.18-50138.194" + wire width 6 $or$libresoc.v:50138$3100_Y + attribute \src "libresoc.v:50142.18-50142.120" + wire width 3 $or$libresoc.v:50142$3104_Y + attribute \src "libresoc.v:50152.17-50152.117" + wire width 6 $or$libresoc.v:50152$3114_Y + attribute \src "libresoc.v:50101.17-50101.104" + wire $reduce_and$libresoc.v:50101$3063_Y + attribute \src "libresoc.v:50119.18-50119.106" + wire $reduce_or$libresoc.v:50119$3081_Y + attribute \src "libresoc.v:50122.18-50122.113" + wire $reduce_or$libresoc.v:50122$3084_Y + attribute \src "libresoc.v:50123.18-50123.112" + wire $reduce_or$libresoc.v:50123$3085_Y + attribute \src "libresoc.v:50146.18-50146.118" + wire width 64 $ternary$libresoc.v:50146$3108_Y + attribute \src "libresoc.v:50147.18-50147.118" + wire width 64 $ternary$libresoc.v:50147$3109_Y + attribute \src "libresoc.v:50148.18-50148.118" + wire width 32 $ternary$libresoc.v:50148$3110_Y + attribute \src "libresoc.v:50149.18-50149.118" + wire width 4 $ternary$libresoc.v:50149$3111_Y + attribute \src "libresoc.v:50150.18-50150.118" + wire width 4 $ternary$libresoc.v:50150$3112_Y + attribute \src "libresoc.v:50151.18-50151.118" + wire width 4 $ternary$libresoc.v:50151$3113_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -87558,9 +87354,9 @@ module \cr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 24 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 22 \cr_a_ok @@ -87618,7 +87414,7 @@ module \cr0 wire width 4 output 23 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 20 \full_cr_ok - attribute \src "libresoc.v:49763.7-49763.15" + attribute \src "libresoc.v:49559.7-49559.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 16 \o_ok @@ -87819,7 +87615,7 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50306$3064 + cell $and $and$libresoc.v:50102$3064 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87827,10 +87623,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:50306$3064_Y + connect \Y $and$libresoc.v:50102$3064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50307$3065 + cell $and $and$libresoc.v:50103$3065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87838,10 +87634,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50307$3065_Y + connect \Y $and$libresoc.v:50103$3065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50308$3066 + cell $and $and$libresoc.v:50104$3066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87849,10 +87645,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50308$3066_Y + connect \Y $and$libresoc.v:50104$3066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50309$3067 + cell $and $and$libresoc.v:50105$3067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87860,10 +87656,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50309$3067_Y + connect \Y $and$libresoc.v:50105$3067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50310$3068 + cell $and $and$libresoc.v:50106$3068 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87871,10 +87667,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:50310$3068_Y + connect \Y $and$libresoc.v:50106$3068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50311$3069 + cell $and $and$libresoc.v:50107$3069 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87882,10 +87678,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50311$3069_Y + connect \Y $and$libresoc.v:50107$3069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50312$3070 + cell $and $and$libresoc.v:50108$3070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87893,10 +87689,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50312$3070_Y + connect \Y $and$libresoc.v:50108$3070_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50313$3071 + cell $and $and$libresoc.v:50109$3071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87904,10 +87700,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50313$3071_Y + connect \Y $and$libresoc.v:50109$3071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50314$3072 + cell $and $and$libresoc.v:50110$3072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87915,10 +87711,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50314$3072_Y + connect \Y $and$libresoc.v:50110$3072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:50315$3073 + cell $and $and$libresoc.v:50111$3073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87926,10 +87722,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:50315$3073_Y + connect \Y $and$libresoc.v:50111$3073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50317$3075 + cell $and $and$libresoc.v:50113$3075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87937,10 +87733,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:50317$3075_Y + connect \Y $and$libresoc.v:50113$3075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50319$3077 + cell $and $and$libresoc.v:50115$3077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87948,10 +87744,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:50319$3077_Y + connect \Y $and$libresoc.v:50115$3077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:50320$3078 + cell $and $and$libresoc.v:50116$3078 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87959,10 +87755,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50320$3078_Y + connect \Y $and$libresoc.v:50116$3078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50322$3080 + cell $and $and$libresoc.v:50118$3080 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87970,10 +87766,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:50322$3080_Y + connect \Y $and$libresoc.v:50118$3080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50325$3083 + cell $and $and$libresoc.v:50121$3083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87981,10 +87777,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:50325$3083_Y + connect \Y $and$libresoc.v:50121$3083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:50329$3087 + cell $and $and$libresoc.v:50125$3087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87992,10 +87788,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:50329$3087_Y + connect \Y $and$libresoc.v:50125$3087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:50331$3089 + cell $and $and$libresoc.v:50127$3089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88003,10 +87799,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:50331$3089_Y + connect \Y $and$libresoc.v:50127$3089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50332$3090 + cell $and $and$libresoc.v:50128$3090 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88014,10 +87810,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50332$3090_Y + connect \Y $and$libresoc.v:50128$3090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50334$3092 + cell $and $and$libresoc.v:50130$3092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88025,10 +87821,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:50334$3092_Y + connect \Y $and$libresoc.v:50130$3092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50336$3094 + cell $and $and$libresoc.v:50132$3094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88036,10 +87832,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_cr0_n_ready_i - connect \Y $and$libresoc.v:50336$3094_Y + connect \Y $and$libresoc.v:50132$3094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50337$3095 + cell $and $and$libresoc.v:50133$3095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88047,10 +87843,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_cr0_n_valid_o - connect \Y $and$libresoc.v:50337$3095_Y + connect \Y $and$libresoc.v:50133$3095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50338$3096 + cell $and $and$libresoc.v:50134$3096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88058,10 +87854,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:50338$3096_Y + connect \Y $and$libresoc.v:50134$3096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:50343$3101 + cell $and $and$libresoc.v:50139$3101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88069,10 +87865,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:50343$3101_Y + connect \Y $and$libresoc.v:50139$3101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:50344$3102 + cell $and $and$libresoc.v:50140$3102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88080,10 +87876,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50344$3102_Y + connect \Y $and$libresoc.v:50140$3102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50347$3105 + cell $and $and$libresoc.v:50143$3105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88091,10 +87887,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50347$3105_Y + connect \Y $and$libresoc.v:50143$3105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50348$3106 + cell $and $and$libresoc.v:50144$3106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88102,10 +87898,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \full_cr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50348$3106_Y + connect \Y $and$libresoc.v:50144$3106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50349$3107 + cell $and $and$libresoc.v:50145$3107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88113,10 +87909,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50349$3107_Y + connect \Y $and$libresoc.v:50145$3107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:50357$3115 + cell $and $and$libresoc.v:50153$3115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88124,10 +87920,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:50357$3115_Y + connect \Y $and$libresoc.v:50153$3115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:50358$3116 + cell $and $and$libresoc.v:50154$3116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88135,10 +87931,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:50358$3116_Y + connect \Y $and$libresoc.v:50154$3116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50359$3117 + cell $and $and$libresoc.v:50155$3117 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88146,10 +87942,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50359$3117_Y + connect \Y $and$libresoc.v:50155$3117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50360$3118 + cell $and $and$libresoc.v:50156$3118 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88157,10 +87953,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$93 connect \B 6'111111 - connect \Y $and$libresoc.v:50360$3118_Y + connect \Y $and$libresoc.v:50156$3118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:50333$3091 + cell $eq $eq$libresoc.v:50129$3091 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88168,10 +87964,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:50333$3091_Y + connect \Y $eq$libresoc.v:50129$3091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:50335$3093 + cell $eq $eq$libresoc.v:50131$3093 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88179,66 +87975,66 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:50335$3093_Y + connect \Y $eq$libresoc.v:50131$3093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50316$3074 + cell $not $not$libresoc.v:50112$3074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:50316$3074_Y + connect \Y $not$libresoc.v:50112$3074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50318$3076 + cell $not $not$libresoc.v:50114$3076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:50318$3076_Y + connect \Y $not$libresoc.v:50114$3076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50321$3079 + cell $not $not$libresoc.v:50117$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:50321$3079_Y + connect \Y $not$libresoc.v:50117$3079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50324$3082 + cell $not $not$libresoc.v:50120$3082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:50324$3082_Y + connect \Y $not$libresoc.v:50120$3082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:50330$3088 + cell $not $not$libresoc.v:50126$3088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_ready_i - connect \Y $not$libresoc.v:50330$3088_Y + connect \Y $not$libresoc.v:50126$3088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:50345$3103 + cell $not $not$libresoc.v:50141$3103 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:50345$3103_Y + connect \Y $not$libresoc.v:50141$3103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:50361$3119 + cell $not $not$libresoc.v:50157$3119 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:50361$3119_Y + connect \Y $not$libresoc.v:50157$3119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:50328$3086 + cell $or $or$libresoc.v:50124$3086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88246,10 +88042,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:50328$3086_Y + connect \Y $or$libresoc.v:50124$3086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:50339$3097 + cell $or $or$libresoc.v:50135$3097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88257,10 +88053,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50339$3097_Y + connect \Y $or$libresoc.v:50135$3097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:50340$3098 + cell $or $or$libresoc.v:50136$3098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88268,10 +88064,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50340$3098_Y + connect \Y $or$libresoc.v:50136$3098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:50341$3099 + cell $or $or$libresoc.v:50137$3099 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88279,10 +88075,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50341$3099_Y + connect \Y $or$libresoc.v:50137$3099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:50342$3100 + cell $or $or$libresoc.v:50138$3100 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88290,10 +88086,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50342$3100_Y + connect \Y $or$libresoc.v:50138$3100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:50346$3104 + cell $or $or$libresoc.v:50142$3104 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88301,10 +88097,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:50346$3104_Y + connect \Y $or$libresoc.v:50142$3104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:50356$3114 + cell $or $or$libresoc.v:50152$3114 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88312,90 +88108,90 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:50356$3114_Y + connect \Y $or$libresoc.v:50152$3114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:50305$3063 + cell $reduce_and $reduce_and$libresoc.v:50101$3063 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:50305$3063_Y + connect \Y $reduce_and$libresoc.v:50101$3063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:50323$3081 + cell $reduce_or $reduce_or$libresoc.v:50119$3081 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:50323$3081_Y + connect \Y $reduce_or$libresoc.v:50119$3081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50326$3084 + cell $reduce_or $reduce_or$libresoc.v:50122$3084 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:50326$3084_Y + connect \Y $reduce_or$libresoc.v:50122$3084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50327$3085 + cell $reduce_or $reduce_or$libresoc.v:50123$3085 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:50327$3085_Y + connect \Y $reduce_or$libresoc.v:50123$3085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50350$3108 + cell $mux $ternary$libresoc.v:50146$3108 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:50350$3108_Y + connect \Y $ternary$libresoc.v:50146$3108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50351$3109 + cell $mux $ternary$libresoc.v:50147$3109 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:50351$3109_Y + connect \Y $ternary$libresoc.v:50147$3109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50352$3110 + cell $mux $ternary$libresoc.v:50148$3110 parameter \WIDTH 32 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:50352$3110_Y + connect \Y $ternary$libresoc.v:50148$3110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50353$3111 + cell $mux $ternary$libresoc.v:50149$3111 parameter \WIDTH 4 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:50353$3111_Y + connect \Y $ternary$libresoc.v:50149$3111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50354$3112 + cell $mux $ternary$libresoc.v:50150$3112 parameter \WIDTH 4 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:50354$3112_Y + connect \Y $ternary$libresoc.v:50150$3112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50355$3113 + cell $mux $ternary$libresoc.v:50151$3113 parameter \WIDTH 4 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:50355$3113_Y + connect \Y $ternary$libresoc.v:50151$3113_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:50422.11-50444.4" + attribute \src "libresoc.v:50218.11-50240.4" cell \alu_cr0 \alu_cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88420,7 +88216,7 @@ module \cr0 connect \rb \alu_cr0_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:50445.14-50451.4" + attribute \src "libresoc.v:50241.14-50247.4" cell \alu_l$16 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88429,7 +88225,7 @@ module \cr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:50452.15-50458.4" + attribute \src "libresoc.v:50248.15-50254.4" cell \alui_l$15 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88438,7 +88234,7 @@ module \cr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:50459.14-50465.4" + attribute \src "libresoc.v:50255.14-50261.4" cell \opc_l$11 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88447,7 +88243,7 @@ module \cr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:50466.14-50472.4" + attribute \src "libresoc.v:50262.14-50268.4" cell \req_l$12 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88456,7 +88252,7 @@ module \cr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:50473.14-50479.4" + attribute \src "libresoc.v:50269.14-50275.4" cell \rok_l$14 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88465,7 +88261,7 @@ module \cr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:50480.14-50485.4" + attribute \src "libresoc.v:50276.14-50281.4" cell \rst_l$13 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88473,7 +88269,7 @@ module \cr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:50486.14-50492.4" + attribute \src "libresoc.v:50282.14-50288.4" cell \src_l$10 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88481,472 +88277,472 @@ module \cr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:49763.7-49763.20" - process $proc$libresoc.v:49763$3242 + attribute \src "libresoc.v:49559.7-49559.20" + process $proc$libresoc.v:49559$3242 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49881.7-49881.24" - process $proc$libresoc.v:49881$3243 + attribute \src "libresoc.v:49677.7-49677.24" + process $proc$libresoc.v:49677$3243 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:49912.14-49912.47" - process $proc$libresoc.v:49912$3244 + attribute \src "libresoc.v:49708.14-49708.47" + process $proc$libresoc.v:49708$3244 assign { } { } assign $1\alu_cr0_cr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:49916.14-49916.41" - process $proc$libresoc.v:49916$3245 + attribute \src "libresoc.v:49712.14-49712.41" + process $proc$libresoc.v:49712$3245 assign { } { } assign $1\alu_cr0_cr_op__insn[31:0] 0 sync always sync init update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:49995.13-49995.45" - process $proc$libresoc.v:49995$3246 + attribute \src "libresoc.v:49791.13-49791.45" + process $proc$libresoc.v:49791$3246 assign { } { } assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50019.7-50019.26" - process $proc$libresoc.v:50019$3247 + attribute \src "libresoc.v:49815.7-49815.26" + process $proc$libresoc.v:49815$3247 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:50027.7-50027.25" - process $proc$libresoc.v:50027$3248 + attribute \src "libresoc.v:49823.7-49823.25" + process $proc$libresoc.v:49823$3248 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50039.7-50039.27" - process $proc$libresoc.v:50039$3249 + attribute \src "libresoc.v:49835.7-49835.27" + process $proc$libresoc.v:49835$3249 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50073.14-50073.47" - process $proc$libresoc.v:50073$3250 + attribute \src "libresoc.v:49869.14-49869.47" + process $proc$libresoc.v:49869$3250 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:50077.7-50077.27" - process $proc$libresoc.v:50077$3251 + attribute \src "libresoc.v:49873.7-49873.27" + process $proc$libresoc.v:49873$3251 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50081.14-50081.38" - process $proc$libresoc.v:50081$3252 + attribute \src "libresoc.v:49877.14-49877.38" + process $proc$libresoc.v:49877$3252 assign { } { } assign $1\data_r1__full_cr[31:0] 0 sync always sync init update \data_r1__full_cr $1\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50085.7-50085.33" - process $proc$libresoc.v:50085$3253 + attribute \src "libresoc.v:49881.7-49881.33" + process $proc$libresoc.v:49881$3253 assign { } { } assign $1\data_r1__full_cr_ok[0:0] 1'0 sync always sync init update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50089.13-50089.33" - process $proc$libresoc.v:50089$3254 + attribute \src "libresoc.v:49885.13-49885.33" + process $proc$libresoc.v:49885$3254 assign { } { } assign $1\data_r2__cr_a[3:0] 4'0000 sync always sync init update \data_r2__cr_a $1\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50093.7-50093.30" - process $proc$libresoc.v:50093$3255 + attribute \src "libresoc.v:49889.7-49889.30" + process $proc$libresoc.v:49889$3255 assign { } { } assign $1\data_r2__cr_a_ok[0:0] 1'0 sync always sync init update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50112.7-50112.25" - process $proc$libresoc.v:50112$3256 + attribute \src "libresoc.v:49908.7-49908.25" + process $proc$libresoc.v:49908$3256 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50116.7-50116.25" - process $proc$libresoc.v:50116$3257 + attribute \src "libresoc.v:49912.7-49912.25" + process $proc$libresoc.v:49912$3257 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50216.13-50216.30" - process $proc$libresoc.v:50216$3258 + attribute \src "libresoc.v:50012.13-50012.30" + process $proc$libresoc.v:50012$3258 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:50224.13-50224.31" - process $proc$libresoc.v:50224$3259 + attribute \src "libresoc.v:50020.13-50020.31" + process $proc$libresoc.v:50020$3259 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:50228.13-50228.31" - process $proc$libresoc.v:50228$3260 + attribute \src "libresoc.v:50024.13-50024.31" + process $proc$libresoc.v:50024$3260 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:50240.7-50240.26" - process $proc$libresoc.v:50240$3261 + attribute \src "libresoc.v:50036.7-50036.26" + process $proc$libresoc.v:50036$3261 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50244.7-50244.26" - process $proc$libresoc.v:50244$3262 + attribute \src "libresoc.v:50040.7-50040.26" + process $proc$libresoc.v:50040$3262 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50248.7-50248.25" - process $proc$libresoc.v:50248$3263 + attribute \src "libresoc.v:50044.7-50044.25" + process $proc$libresoc.v:50044$3263 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50252.7-50252.25" - process $proc$libresoc.v:50252$3264 + attribute \src "libresoc.v:50048.7-50048.25" + process $proc$libresoc.v:50048$3264 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50272.13-50272.32" - process $proc$libresoc.v:50272$3265 + attribute \src "libresoc.v:50068.13-50068.32" + process $proc$libresoc.v:50068$3265 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:50276.13-50276.32" - process $proc$libresoc.v:50276$3266 + attribute \src "libresoc.v:50072.13-50072.32" + process $proc$libresoc.v:50072$3266 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:50280.14-50280.43" - process $proc$libresoc.v:50280$3267 + attribute \src "libresoc.v:50076.14-50076.43" + process $proc$libresoc.v:50076$3267 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:50284.14-50284.43" - process $proc$libresoc.v:50284$3268 + attribute \src "libresoc.v:50080.14-50080.43" + process $proc$libresoc.v:50080$3268 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:50288.14-50288.28" - process $proc$libresoc.v:50288$3269 + attribute \src "libresoc.v:50084.14-50084.28" + process $proc$libresoc.v:50084$3269 assign { } { } assign $1\src_r2[31:0] 0 sync always sync init update \src_r2 $1\src_r2[31:0] end - attribute \src "libresoc.v:50292.13-50292.26" - process $proc$libresoc.v:50292$3270 + attribute \src "libresoc.v:50088.13-50088.26" + process $proc$libresoc.v:50088$3270 assign { } { } assign $1\src_r3[3:0] 4'0000 sync always sync init update \src_r3 $1\src_r3[3:0] end - attribute \src "libresoc.v:50296.13-50296.26" - process $proc$libresoc.v:50296$3271 + attribute \src "libresoc.v:50092.13-50092.26" + process $proc$libresoc.v:50092$3271 assign { } { } assign $1\src_r4[3:0] 4'0000 sync always sync init update \src_r4 $1\src_r4[3:0] end - attribute \src "libresoc.v:50300.13-50300.26" - process $proc$libresoc.v:50300$3272 + attribute \src "libresoc.v:50096.13-50096.26" + process $proc$libresoc.v:50096$3272 assign { } { } assign $1\src_r5[3:0] 4'0000 sync always sync init update \src_r5 $1\src_r5[3:0] end - attribute \src "libresoc.v:50362.3-50363.39" - process $proc$libresoc.v:50362$3120 + attribute \src "libresoc.v:50158.3-50159.39" + process $proc$libresoc.v:50158$3120 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50364.3-50365.43" - process $proc$libresoc.v:50364$3121 + attribute \src "libresoc.v:50160.3-50161.43" + process $proc$libresoc.v:50160$3121 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50366.3-50367.29" - process $proc$libresoc.v:50366$3122 + attribute \src "libresoc.v:50162.3-50163.29" + process $proc$libresoc.v:50162$3122 assign { } { } assign $0\src_r5[3:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[3:0] end - attribute \src "libresoc.v:50368.3-50369.29" - process $proc$libresoc.v:50368$3123 + attribute \src "libresoc.v:50164.3-50165.29" + process $proc$libresoc.v:50164$3123 assign { } { } assign $0\src_r4[3:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[3:0] end - attribute \src "libresoc.v:50370.3-50371.29" - process $proc$libresoc.v:50370$3124 + attribute \src "libresoc.v:50166.3-50167.29" + process $proc$libresoc.v:50166$3124 assign { } { } assign $0\src_r3[3:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[3:0] end - attribute \src "libresoc.v:50372.3-50373.29" - process $proc$libresoc.v:50372$3125 + attribute \src "libresoc.v:50168.3-50169.29" + process $proc$libresoc.v:50168$3125 assign { } { } assign $0\src_r2[31:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[31:0] end - attribute \src "libresoc.v:50374.3-50375.29" - process $proc$libresoc.v:50374$3126 + attribute \src "libresoc.v:50170.3-50171.29" + process $proc$libresoc.v:50170$3126 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:50376.3-50377.29" - process $proc$libresoc.v:50376$3127 + attribute \src "libresoc.v:50172.3-50173.29" + process $proc$libresoc.v:50172$3127 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:50378.3-50379.43" - process $proc$libresoc.v:50378$3128 + attribute \src "libresoc.v:50174.3-50175.43" + process $proc$libresoc.v:50174$3128 assign { } { } assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next sync posedge \coresync_clk update \data_r2__cr_a $0\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50380.3-50381.49" - process $proc$libresoc.v:50380$3129 + attribute \src "libresoc.v:50176.3-50177.49" + process $proc$libresoc.v:50176$3129 assign { } { } assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next sync posedge \coresync_clk update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50382.3-50383.49" - process $proc$libresoc.v:50382$3130 + attribute \src "libresoc.v:50178.3-50179.49" + process $proc$libresoc.v:50178$3130 assign { } { } assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next sync posedge \coresync_clk update \data_r1__full_cr $0\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50384.3-50385.55" - process $proc$libresoc.v:50384$3131 + attribute \src "libresoc.v:50180.3-50181.55" + process $proc$libresoc.v:50180$3131 assign { } { } assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next sync posedge \coresync_clk update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50386.3-50387.37" - process $proc$libresoc.v:50386$3132 + attribute \src "libresoc.v:50182.3-50183.37" + process $proc$libresoc.v:50182$3132 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:50388.3-50389.43" - process $proc$libresoc.v:50388$3133 + attribute \src "libresoc.v:50184.3-50185.43" + process $proc$libresoc.v:50184$3133 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50390.3-50391.65" - process $proc$libresoc.v:50390$3134 + attribute \src "libresoc.v:50186.3-50187.65" + process $proc$libresoc.v:50186$3134 assign { } { } assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50392.3-50393.61" - process $proc$libresoc.v:50392$3135 + attribute \src "libresoc.v:50188.3-50189.61" + process $proc$libresoc.v:50188$3135 assign { } { } assign $0\alu_cr0_cr_op__fn_unit[13:0] \alu_cr0_cr_op__fn_unit$next sync posedge \coresync_clk update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:50394.3-50395.55" - process $proc$libresoc.v:50394$3136 + attribute \src "libresoc.v:50190.3-50191.55" + process $proc$libresoc.v:50190$3136 assign { } { } assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:50396.3-50397.39" - process $proc$libresoc.v:50396$3137 + attribute \src "libresoc.v:50192.3-50193.39" + process $proc$libresoc.v:50192$3137 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:50398.3-50399.39" - process $proc$libresoc.v:50398$3138 + attribute \src "libresoc.v:50194.3-50195.39" + process $proc$libresoc.v:50194$3138 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:50400.3-50401.39" - process $proc$libresoc.v:50400$3139 + attribute \src "libresoc.v:50196.3-50197.39" + process $proc$libresoc.v:50196$3139 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:50402.3-50403.39" - process $proc$libresoc.v:50402$3140 + attribute \src "libresoc.v:50198.3-50199.39" + process $proc$libresoc.v:50198$3140 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:50404.3-50405.39" - process $proc$libresoc.v:50404$3141 + attribute \src "libresoc.v:50200.3-50201.39" + process $proc$libresoc.v:50200$3141 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50406.3-50407.39" - process $proc$libresoc.v:50406$3142 + attribute \src "libresoc.v:50202.3-50203.39" + process $proc$libresoc.v:50202$3142 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50408.3-50409.39" - process $proc$libresoc.v:50408$3143 + attribute \src "libresoc.v:50204.3-50205.39" + process $proc$libresoc.v:50204$3143 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50410.3-50411.39" - process $proc$libresoc.v:50410$3144 + attribute \src "libresoc.v:50206.3-50207.39" + process $proc$libresoc.v:50206$3144 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50412.3-50413.41" - process $proc$libresoc.v:50412$3145 + attribute \src "libresoc.v:50208.3-50209.41" + process $proc$libresoc.v:50208$3145 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50414.3-50415.41" - process $proc$libresoc.v:50414$3146 + attribute \src "libresoc.v:50210.3-50211.41" + process $proc$libresoc.v:50210$3146 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50416.3-50417.37" - process $proc$libresoc.v:50416$3147 + attribute \src "libresoc.v:50212.3-50213.37" + process $proc$libresoc.v:50212$3147 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:50418.3-50419.39" - process $proc$libresoc.v:50418$3148 + attribute \src "libresoc.v:50214.3-50215.39" + process $proc$libresoc.v:50214$3148 assign { } { } assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:50420.3-50421.25" - process $proc$libresoc.v:50420$3149 + attribute \src "libresoc.v:50216.3-50217.25" + process $proc$libresoc.v:50216$3149 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:50493.3-50502.6" - process $proc$libresoc.v:50493$3150 + attribute \src "libresoc.v:50289.3-50298.6" + process $proc$libresoc.v:50289$3150 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:50494.5-50494.29" + attribute \src "libresoc.v:50290.5-50290.29" switch \initial - attribute \src "libresoc.v:50494.9-50494.17" + attribute \src "libresoc.v:50290.9-50290.17" case 1'1 case end @@ -88962,14 +88758,14 @@ module \cr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:50503.3-50511.6" - process $proc$libresoc.v:50503$3151 + attribute \src "libresoc.v:50299.3-50307.6" + process $proc$libresoc.v:50299$3151 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$3152 $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:50504.5-50504.29" + attribute \src "libresoc.v:50300.5-50300.29" switch \initial - attribute \src "libresoc.v:50504.9-50504.17" + attribute \src "libresoc.v:50300.9-50300.17" case 1'1 case end @@ -88985,14 +88781,14 @@ module \cr0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3152 end - attribute \src "libresoc.v:50512.3-50520.6" - process $proc$libresoc.v:50512$3154 + attribute \src "libresoc.v:50308.3-50316.6" + process $proc$libresoc.v:50308$3154 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$3155 $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:50513.5-50513.29" + attribute \src "libresoc.v:50309.5-50309.29" switch \initial - attribute \src "libresoc.v:50513.9-50513.17" + attribute \src "libresoc.v:50309.9-50309.17" case 1'1 case end @@ -89008,14 +88804,14 @@ module \cr0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3155 end - attribute \src "libresoc.v:50521.3-50529.6" - process $proc$libresoc.v:50521$3157 + attribute \src "libresoc.v:50317.3-50325.6" + process $proc$libresoc.v:50317$3157 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$3158 $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:50522.5-50522.29" + attribute \src "libresoc.v:50318.5-50318.29" switch \initial - attribute \src "libresoc.v:50522.9-50522.17" + attribute \src "libresoc.v:50318.9-50318.17" case 1'1 case end @@ -89031,14 +88827,14 @@ module \cr0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3158 end - attribute \src "libresoc.v:50530.3-50538.6" - process $proc$libresoc.v:50530$3160 + attribute \src "libresoc.v:50326.3-50334.6" + process $proc$libresoc.v:50326$3160 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$3161 $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:50531.5-50531.29" + attribute \src "libresoc.v:50327.5-50327.29" switch \initial - attribute \src "libresoc.v:50531.9-50531.17" + attribute \src "libresoc.v:50327.9-50327.17" case 1'1 case end @@ -89054,14 +88850,14 @@ module \cr0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3161 end - attribute \src "libresoc.v:50539.3-50547.6" - process $proc$libresoc.v:50539$3163 + attribute \src "libresoc.v:50335.3-50343.6" + process $proc$libresoc.v:50335$3163 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$3164 $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:50540.5-50540.29" + attribute \src "libresoc.v:50336.5-50336.29" switch \initial - attribute \src "libresoc.v:50540.9-50540.17" + attribute \src "libresoc.v:50336.9-50336.17" case 1'1 case end @@ -89077,14 +88873,14 @@ module \cr0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3164 end - attribute \src "libresoc.v:50548.3-50556.6" - process $proc$libresoc.v:50548$3166 + attribute \src "libresoc.v:50344.3-50352.6" + process $proc$libresoc.v:50344$3166 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$3167 $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:50549.5-50549.29" + attribute \src "libresoc.v:50345.5-50345.29" switch \initial - attribute \src "libresoc.v:50549.9-50549.17" + attribute \src "libresoc.v:50345.9-50345.17" case 1'1 case end @@ -89100,14 +88896,14 @@ module \cr0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3167 end - attribute \src "libresoc.v:50557.3-50565.6" - process $proc$libresoc.v:50557$3169 + attribute \src "libresoc.v:50353.3-50361.6" + process $proc$libresoc.v:50353$3169 assign { } { } assign { } { } assign $0\src_l_s_src$next[5:0]$3170 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:50558.5-50558.29" + attribute \src "libresoc.v:50354.5-50354.29" switch \initial - attribute \src "libresoc.v:50558.9-50558.17" + attribute \src "libresoc.v:50354.9-50354.17" case 1'1 case end @@ -89123,14 +88919,14 @@ module \cr0 sync always update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3170 end - attribute \src "libresoc.v:50566.3-50574.6" - process $proc$libresoc.v:50566$3172 + attribute \src "libresoc.v:50362.3-50370.6" + process $proc$libresoc.v:50362$3172 assign { } { } assign { } { } assign $0\src_l_r_src$next[5:0]$3173 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:50567.5-50567.29" + attribute \src "libresoc.v:50363.5-50363.29" switch \initial - attribute \src "libresoc.v:50567.9-50567.17" + attribute \src "libresoc.v:50363.9-50363.17" case 1'1 case end @@ -89146,14 +88942,14 @@ module \cr0 sync always update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3173 end - attribute \src "libresoc.v:50575.3-50583.6" - process $proc$libresoc.v:50575$3175 + attribute \src "libresoc.v:50371.3-50379.6" + process $proc$libresoc.v:50371$3175 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$3176 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:50576.5-50576.29" + attribute \src "libresoc.v:50372.5-50372.29" switch \initial - attribute \src "libresoc.v:50576.9-50576.17" + attribute \src "libresoc.v:50372.9-50372.17" case 1'1 case end @@ -89169,14 +88965,14 @@ module \cr0 sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3176 end - attribute \src "libresoc.v:50584.3-50592.6" - process $proc$libresoc.v:50584$3178 + attribute \src "libresoc.v:50380.3-50388.6" + process $proc$libresoc.v:50380$3178 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$3179 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:50585.5-50585.29" + attribute \src "libresoc.v:50381.5-50381.29" switch \initial - attribute \src "libresoc.v:50585.9-50585.17" + attribute \src "libresoc.v:50381.9-50381.17" case 1'1 case end @@ -89192,8 +88988,8 @@ module \cr0 sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3179 end - attribute \src "libresoc.v:50593.3-50604.6" - process $proc$libresoc.v:50593$3181 + attribute \src "libresoc.v:50389.3-50400.6" + process $proc$libresoc.v:50389$3181 assign { } { } assign { } { } assign { } { } @@ -89203,9 +88999,9 @@ module \cr0 assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 assign $0\alu_cr0_cr_op__insn$next[31:0]$3183 $1\alu_cr0_cr_op__insn$next[31:0]$3186 assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:50594.5-50594.29" + attribute \src "libresoc.v:50390.5-50390.29" switch \initial - attribute \src "libresoc.v:50594.9-50594.17" + attribute \src "libresoc.v:50390.9-50390.17" case 1'1 case end @@ -89227,8 +89023,8 @@ module \cr0 update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3183 update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 end - attribute \src "libresoc.v:50605.3-50626.6" - process $proc$libresoc.v:50605$3188 + attribute \src "libresoc.v:50401.3-50422.6" + process $proc$libresoc.v:50401$3188 assign { } { } assign { } { } assign { } { } @@ -89238,9 +89034,9 @@ module \cr0 assign $0\data_r0__o$next[63:0]$3189 $2\data_r0__o$next[63:0]$3193 assign { } { } assign $0\data_r0__o_ok$next[0:0]$3190 $3\data_r0__o_ok$next[0:0]$3195 - attribute \src "libresoc.v:50606.5-50606.29" + attribute \src "libresoc.v:50402.5-50402.29" switch \initial - attribute \src "libresoc.v:50606.9-50606.17" + attribute \src "libresoc.v:50402.9-50402.17" case 1'1 case end @@ -89279,8 +89075,8 @@ module \cr0 update \data_r0__o$next $0\data_r0__o$next[63:0]$3189 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3190 end - attribute \src "libresoc.v:50627.3-50648.6" - process $proc$libresoc.v:50627$3196 + attribute \src "libresoc.v:50423.3-50444.6" + process $proc$libresoc.v:50423$3196 assign { } { } assign { } { } assign { } { } @@ -89290,9 +89086,9 @@ module \cr0 assign $0\data_r1__full_cr$next[31:0]$3197 $2\data_r1__full_cr$next[31:0]$3201 assign { } { } assign $0\data_r1__full_cr_ok$next[0:0]$3198 $3\data_r1__full_cr_ok$next[0:0]$3203 - attribute \src "libresoc.v:50628.5-50628.29" + attribute \src "libresoc.v:50424.5-50424.29" switch \initial - attribute \src "libresoc.v:50628.9-50628.17" + attribute \src "libresoc.v:50424.9-50424.17" case 1'1 case end @@ -89331,8 +89127,8 @@ module \cr0 update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3197 update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3198 end - attribute \src "libresoc.v:50649.3-50670.6" - process $proc$libresoc.v:50649$3204 + attribute \src "libresoc.v:50445.3-50466.6" + process $proc$libresoc.v:50445$3204 assign { } { } assign { } { } assign { } { } @@ -89342,9 +89138,9 @@ module \cr0 assign $0\data_r2__cr_a$next[3:0]$3205 $2\data_r2__cr_a$next[3:0]$3209 assign { } { } assign $0\data_r2__cr_a_ok$next[0:0]$3206 $3\data_r2__cr_a_ok$next[0:0]$3211 - attribute \src "libresoc.v:50650.5-50650.29" + attribute \src "libresoc.v:50446.5-50446.29" switch \initial - attribute \src "libresoc.v:50650.9-50650.17" + attribute \src "libresoc.v:50446.9-50446.17" case 1'1 case end @@ -89383,14 +89179,14 @@ module \cr0 update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3205 update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3206 end - attribute \src "libresoc.v:50671.3-50680.6" - process $proc$libresoc.v:50671$3212 + attribute \src "libresoc.v:50467.3-50476.6" + process $proc$libresoc.v:50467$3212 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$3213 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:50672.5-50672.29" + attribute \src "libresoc.v:50468.5-50468.29" switch \initial - attribute \src "libresoc.v:50672.9-50672.17" + attribute \src "libresoc.v:50468.9-50468.17" case 1'1 case end @@ -89406,14 +89202,14 @@ module \cr0 sync always update \src_r0$next $0\src_r0$next[63:0]$3213 end - attribute \src "libresoc.v:50681.3-50690.6" - process $proc$libresoc.v:50681$3215 + attribute \src "libresoc.v:50477.3-50486.6" + process $proc$libresoc.v:50477$3215 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$3216 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:50682.5-50682.29" + attribute \src "libresoc.v:50478.5-50478.29" switch \initial - attribute \src "libresoc.v:50682.9-50682.17" + attribute \src "libresoc.v:50478.9-50478.17" case 1'1 case end @@ -89429,14 +89225,14 @@ module \cr0 sync always update \src_r1$next $0\src_r1$next[63:0]$3216 end - attribute \src "libresoc.v:50691.3-50700.6" - process $proc$libresoc.v:50691$3218 + attribute \src "libresoc.v:50487.3-50496.6" + process $proc$libresoc.v:50487$3218 assign { } { } assign { } { } assign $0\src_r2$next[31:0]$3219 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:50692.5-50692.29" + attribute \src "libresoc.v:50488.5-50488.29" switch \initial - attribute \src "libresoc.v:50692.9-50692.17" + attribute \src "libresoc.v:50488.9-50488.17" case 1'1 case end @@ -89452,14 +89248,14 @@ module \cr0 sync always update \src_r2$next $0\src_r2$next[31:0]$3219 end - attribute \src "libresoc.v:50701.3-50710.6" - process $proc$libresoc.v:50701$3221 + attribute \src "libresoc.v:50497.3-50506.6" + process $proc$libresoc.v:50497$3221 assign { } { } assign { } { } assign $0\src_r3$next[3:0]$3222 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:50702.5-50702.29" + attribute \src "libresoc.v:50498.5-50498.29" switch \initial - attribute \src "libresoc.v:50702.9-50702.17" + attribute \src "libresoc.v:50498.9-50498.17" case 1'1 case end @@ -89475,14 +89271,14 @@ module \cr0 sync always update \src_r3$next $0\src_r3$next[3:0]$3222 end - attribute \src "libresoc.v:50711.3-50720.6" - process $proc$libresoc.v:50711$3224 + attribute \src "libresoc.v:50507.3-50516.6" + process $proc$libresoc.v:50507$3224 assign { } { } assign { } { } assign $0\src_r4$next[3:0]$3225 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:50712.5-50712.29" + attribute \src "libresoc.v:50508.5-50508.29" switch \initial - attribute \src "libresoc.v:50712.9-50712.17" + attribute \src "libresoc.v:50508.9-50508.17" case 1'1 case end @@ -89498,14 +89294,14 @@ module \cr0 sync always update \src_r4$next $0\src_r4$next[3:0]$3225 end - attribute \src "libresoc.v:50721.3-50730.6" - process $proc$libresoc.v:50721$3227 + attribute \src "libresoc.v:50517.3-50526.6" + process $proc$libresoc.v:50517$3227 assign { } { } assign { } { } assign $0\src_r5$next[3:0]$3228 $1\src_r5$next[3:0]$3229 - attribute \src "libresoc.v:50722.5-50722.29" + attribute \src "libresoc.v:50518.5-50518.29" switch \initial - attribute \src "libresoc.v:50722.9-50722.17" + attribute \src "libresoc.v:50518.9-50518.17" case 1'1 case end @@ -89521,14 +89317,14 @@ module \cr0 sync always update \src_r5$next $0\src_r5$next[3:0]$3228 end - attribute \src "libresoc.v:50731.3-50739.6" - process $proc$libresoc.v:50731$3230 + attribute \src "libresoc.v:50527.3-50535.6" + process $proc$libresoc.v:50527$3230 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$3231 $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:50732.5-50732.29" + attribute \src "libresoc.v:50528.5-50528.29" switch \initial - attribute \src "libresoc.v:50732.9-50732.17" + attribute \src "libresoc.v:50528.9-50528.17" case 1'1 case end @@ -89544,14 +89340,14 @@ module \cr0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3231 end - attribute \src "libresoc.v:50740.3-50748.6" - process $proc$libresoc.v:50740$3233 + attribute \src "libresoc.v:50536.3-50544.6" + process $proc$libresoc.v:50536$3233 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$3234 $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:50741.5-50741.29" + attribute \src "libresoc.v:50537.5-50537.29" switch \initial - attribute \src "libresoc.v:50741.9-50741.17" + attribute \src "libresoc.v:50537.9-50537.17" case 1'1 case end @@ -89567,14 +89363,14 @@ module \cr0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3234 end - attribute \src "libresoc.v:50749.3-50758.6" - process $proc$libresoc.v:50749$3236 + attribute \src "libresoc.v:50545.3-50554.6" + process $proc$libresoc.v:50545$3236 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:50750.5-50750.29" + attribute \src "libresoc.v:50546.5-50546.29" switch \initial - attribute \src "libresoc.v:50750.9-50750.17" + attribute \src "libresoc.v:50546.9-50546.17" case 1'1 case end @@ -89590,14 +89386,14 @@ module \cr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:50759.3-50768.6" - process $proc$libresoc.v:50759$3237 + attribute \src "libresoc.v:50555.3-50564.6" + process $proc$libresoc.v:50555$3237 assign { } { } assign { } { } assign $0\dest2_o[31:0] $1\dest2_o[31:0] - attribute \src "libresoc.v:50760.5-50760.29" + attribute \src "libresoc.v:50556.5-50556.29" switch \initial - attribute \src "libresoc.v:50760.9-50760.17" + attribute \src "libresoc.v:50556.9-50556.17" case 1'1 case end @@ -89613,14 +89409,14 @@ module \cr0 sync always update \dest2_o $0\dest2_o[31:0] end - attribute \src "libresoc.v:50769.3-50778.6" - process $proc$libresoc.v:50769$3238 + attribute \src "libresoc.v:50565.3-50574.6" + process $proc$libresoc.v:50565$3238 assign { } { } assign { } { } assign $0\dest3_o[3:0] $1\dest3_o[3:0] - attribute \src "libresoc.v:50770.5-50770.29" + attribute \src "libresoc.v:50566.5-50566.29" switch \initial - attribute \src "libresoc.v:50770.9-50770.17" + attribute \src "libresoc.v:50566.9-50566.17" case 1'1 case end @@ -89636,14 +89432,14 @@ module \cr0 sync always update \dest3_o $0\dest3_o[3:0] end - attribute \src "libresoc.v:50779.3-50787.6" - process $proc$libresoc.v:50779$3239 + attribute \src "libresoc.v:50575.3-50583.6" + process $proc$libresoc.v:50575$3239 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$3240 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:50780.5-50780.29" + attribute \src "libresoc.v:50576.5-50576.29" switch \initial - attribute \src "libresoc.v:50780.9-50780.17" + attribute \src "libresoc.v:50576.9-50576.17" case 1'1 case end @@ -89659,63 +89455,63 @@ module \cr0 sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3240 end - connect \$5 $reduce_and$libresoc.v:50305$3063_Y - connect \$99 $and$libresoc.v:50306$3064_Y - connect \$101 $and$libresoc.v:50307$3065_Y - connect \$103 $and$libresoc.v:50308$3066_Y - connect \$105 $and$libresoc.v:50309$3067_Y - connect \$107 $and$libresoc.v:50310$3068_Y - connect \$109 $and$libresoc.v:50311$3069_Y - connect \$111 $and$libresoc.v:50312$3070_Y - connect \$113 $and$libresoc.v:50313$3071_Y - connect \$115 $and$libresoc.v:50314$3072_Y - connect \$11 $and$libresoc.v:50315$3073_Y - connect \$13 $not$libresoc.v:50316$3074_Y - connect \$15 $and$libresoc.v:50317$3075_Y - connect \$17 $not$libresoc.v:50318$3076_Y - connect \$19 $and$libresoc.v:50319$3077_Y - connect \$21 $and$libresoc.v:50320$3078_Y - connect \$25 $not$libresoc.v:50321$3079_Y - connect \$27 $and$libresoc.v:50322$3080_Y - connect \$24 $reduce_or$libresoc.v:50323$3081_Y - connect \$23 $not$libresoc.v:50324$3082_Y - connect \$31 $and$libresoc.v:50325$3083_Y - connect \$33 $reduce_or$libresoc.v:50326$3084_Y - connect \$35 $reduce_or$libresoc.v:50327$3085_Y - connect \$37 $or$libresoc.v:50328$3086_Y - connect \$3 $and$libresoc.v:50329$3087_Y - connect \$39 $not$libresoc.v:50330$3088_Y - connect \$41 $and$libresoc.v:50331$3089_Y - connect \$43 $and$libresoc.v:50332$3090_Y - connect \$45 $eq$libresoc.v:50333$3091_Y - connect \$47 $and$libresoc.v:50334$3092_Y - connect \$49 $eq$libresoc.v:50335$3093_Y - connect \$51 $and$libresoc.v:50336$3094_Y - connect \$53 $and$libresoc.v:50337$3095_Y - connect \$55 $and$libresoc.v:50338$3096_Y - connect \$57 $or$libresoc.v:50339$3097_Y - connect \$59 $or$libresoc.v:50340$3098_Y - connect \$61 $or$libresoc.v:50341$3099_Y - connect \$63 $or$libresoc.v:50342$3100_Y - connect \$65 $and$libresoc.v:50343$3101_Y - connect \$67 $and$libresoc.v:50344$3102_Y - connect \$6 $not$libresoc.v:50345$3103_Y - connect \$69 $or$libresoc.v:50346$3104_Y - connect \$71 $and$libresoc.v:50347$3105_Y - connect \$73 $and$libresoc.v:50348$3106_Y - connect \$75 $and$libresoc.v:50349$3107_Y - connect \$77 $ternary$libresoc.v:50350$3108_Y - connect \$79 $ternary$libresoc.v:50351$3109_Y - connect \$81 $ternary$libresoc.v:50352$3110_Y - connect \$83 $ternary$libresoc.v:50353$3111_Y - connect \$85 $ternary$libresoc.v:50354$3112_Y - connect \$87 $ternary$libresoc.v:50355$3113_Y - connect \$8 $or$libresoc.v:50356$3114_Y - connect \$89 $and$libresoc.v:50357$3115_Y - connect \$91 $and$libresoc.v:50358$3116_Y - connect \$93 $and$libresoc.v:50359$3117_Y - connect \$95 $and$libresoc.v:50360$3118_Y - connect \$97 $not$libresoc.v:50361$3119_Y + connect \$5 $reduce_and$libresoc.v:50101$3063_Y + connect \$99 $and$libresoc.v:50102$3064_Y + connect \$101 $and$libresoc.v:50103$3065_Y + connect \$103 $and$libresoc.v:50104$3066_Y + connect \$105 $and$libresoc.v:50105$3067_Y + connect \$107 $and$libresoc.v:50106$3068_Y + connect \$109 $and$libresoc.v:50107$3069_Y + connect \$111 $and$libresoc.v:50108$3070_Y + connect \$113 $and$libresoc.v:50109$3071_Y + connect \$115 $and$libresoc.v:50110$3072_Y + connect \$11 $and$libresoc.v:50111$3073_Y + connect \$13 $not$libresoc.v:50112$3074_Y + connect \$15 $and$libresoc.v:50113$3075_Y + connect \$17 $not$libresoc.v:50114$3076_Y + connect \$19 $and$libresoc.v:50115$3077_Y + connect \$21 $and$libresoc.v:50116$3078_Y + connect \$25 $not$libresoc.v:50117$3079_Y + connect \$27 $and$libresoc.v:50118$3080_Y + connect \$24 $reduce_or$libresoc.v:50119$3081_Y + connect \$23 $not$libresoc.v:50120$3082_Y + connect \$31 $and$libresoc.v:50121$3083_Y + connect \$33 $reduce_or$libresoc.v:50122$3084_Y + connect \$35 $reduce_or$libresoc.v:50123$3085_Y + connect \$37 $or$libresoc.v:50124$3086_Y + connect \$3 $and$libresoc.v:50125$3087_Y + connect \$39 $not$libresoc.v:50126$3088_Y + connect \$41 $and$libresoc.v:50127$3089_Y + connect \$43 $and$libresoc.v:50128$3090_Y + connect \$45 $eq$libresoc.v:50129$3091_Y + connect \$47 $and$libresoc.v:50130$3092_Y + connect \$49 $eq$libresoc.v:50131$3093_Y + connect \$51 $and$libresoc.v:50132$3094_Y + connect \$53 $and$libresoc.v:50133$3095_Y + connect \$55 $and$libresoc.v:50134$3096_Y + connect \$57 $or$libresoc.v:50135$3097_Y + connect \$59 $or$libresoc.v:50136$3098_Y + connect \$61 $or$libresoc.v:50137$3099_Y + connect \$63 $or$libresoc.v:50138$3100_Y + connect \$65 $and$libresoc.v:50139$3101_Y + connect \$67 $and$libresoc.v:50140$3102_Y + connect \$6 $not$libresoc.v:50141$3103_Y + connect \$69 $or$libresoc.v:50142$3104_Y + connect \$71 $and$libresoc.v:50143$3105_Y + connect \$73 $and$libresoc.v:50144$3106_Y + connect \$75 $and$libresoc.v:50145$3107_Y + connect \$77 $ternary$libresoc.v:50146$3108_Y + connect \$79 $ternary$libresoc.v:50147$3109_Y + connect \$81 $ternary$libresoc.v:50148$3110_Y + connect \$83 $ternary$libresoc.v:50149$3111_Y + connect \$85 $ternary$libresoc.v:50150$3112_Y + connect \$87 $ternary$libresoc.v:50151$3113_Y + connect \$8 $or$libresoc.v:50152$3114_Y + connect \$89 $and$libresoc.v:50153$3115_Y + connect \$91 $and$libresoc.v:50154$3116_Y + connect \$93 $and$libresoc.v:50155$3117_Y + connect \$95 $and$libresoc.v:50156$3118_Y + connect \$97 $not$libresoc.v:50157$3119_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -89748,31 +89544,31 @@ module \cr0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:50823.1-50872.10" +attribute \src "libresoc.v:50619.1-50668.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" attribute \generator "nMigen" module \cyc_l - attribute \src "libresoc.v:50824.7-50824.20" + attribute \src "libresoc.v:50620.7-50620.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50860.3-50868.6" + attribute \src "libresoc.v:50656.3-50664.6" wire $0\q_int$next[0:0]$3280 - attribute \src "libresoc.v:50858.3-50859.27" + attribute \src "libresoc.v:50654.3-50655.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:50860.3-50868.6" + attribute \src "libresoc.v:50656.3-50664.6" wire $1\q_int$next[0:0]$3281 - attribute \src "libresoc.v:50842.7-50842.19" + attribute \src "libresoc.v:50638.7-50638.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:50855.17-50855.96" - wire $and$libresoc.v:50855$3275_Y - attribute \src "libresoc.v:50854.17-50854.92" - wire $not$libresoc.v:50854$3274_Y - attribute \src "libresoc.v:50857.17-50857.92" - wire $not$libresoc.v:50857$3277_Y - attribute \src "libresoc.v:50853.17-50853.98" - wire $or$libresoc.v:50853$3273_Y - attribute \src "libresoc.v:50856.17-50856.97" - wire $or$libresoc.v:50856$3276_Y + attribute \src "libresoc.v:50651.17-50651.96" + wire $and$libresoc.v:50651$3275_Y + attribute \src "libresoc.v:50650.17-50650.92" + wire $not$libresoc.v:50650$3274_Y + attribute \src "libresoc.v:50653.17-50653.92" + wire $not$libresoc.v:50653$3277_Y + attribute \src "libresoc.v:50649.17-50649.98" + wire $or$libresoc.v:50649$3273_Y + attribute \src "libresoc.v:50652.17-50652.97" + wire $or$libresoc.v:50652$3276_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -89783,11 +89579,11 @@ module \cyc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:50824.7-50824.15" + attribute \src "libresoc.v:50620.7-50620.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_cyc @@ -89804,7 +89600,7 @@ module \cyc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:50855$3275 + cell $and $and$libresoc.v:50651$3275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89812,26 +89608,26 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:50855$3275_Y + connect \Y $and$libresoc.v:50651$3275_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:50854$3274 + cell $not $not$libresoc.v:50650$3274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_cyc - connect \Y $not$libresoc.v:50854$3274_Y + connect \Y $not$libresoc.v:50650$3274_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:50857$3277 + cell $not $not$libresoc.v:50653$3277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_cyc - connect \Y $not$libresoc.v:50857$3277_Y + connect \Y $not$libresoc.v:50653$3277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:50853$3273 + cell $or $or$libresoc.v:50649$3273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89839,10 +89635,10 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_cyc connect \B \q_int - connect \Y $or$libresoc.v:50853$3273_Y + connect \Y $or$libresoc.v:50649$3273_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:50856$3276 + cell $or $or$libresoc.v:50652$3276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89850,39 +89646,39 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_cyc - connect \Y $or$libresoc.v:50856$3276_Y + connect \Y $or$libresoc.v:50652$3276_Y end - attribute \src "libresoc.v:50824.7-50824.20" - process $proc$libresoc.v:50824$3282 + attribute \src "libresoc.v:50620.7-50620.20" + process $proc$libresoc.v:50620$3282 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50842.7-50842.19" - process $proc$libresoc.v:50842$3283 + attribute \src "libresoc.v:50638.7-50638.19" + process $proc$libresoc.v:50638$3283 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:50858.3-50859.27" - process $proc$libresoc.v:50858$3278 + attribute \src "libresoc.v:50654.3-50655.27" + process $proc$libresoc.v:50654$3278 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:50860.3-50868.6" - process $proc$libresoc.v:50860$3279 + attribute \src "libresoc.v:50656.3-50664.6" + process $proc$libresoc.v:50656$3279 assign { } { } assign { } { } assign $0\q_int$next[0:0]$3280 $1\q_int$next[0:0]$3281 - attribute \src "libresoc.v:50861.5-50861.29" + attribute \src "libresoc.v:50657.5-50657.29" switch \initial - attribute \src "libresoc.v:50861.9-50861.17" + attribute \src "libresoc.v:50657.9-50657.17" case 1'1 case end @@ -89898,324 +89694,324 @@ module \cyc_l sync always update \q_int$next $0\q_int$next[0:0]$3280 end - connect \$9 $or$libresoc.v:50853$3273_Y - connect \$1 $not$libresoc.v:50854$3274_Y - connect \$3 $and$libresoc.v:50855$3275_Y - connect \$5 $or$libresoc.v:50856$3276_Y - connect \$7 $not$libresoc.v:50857$3277_Y + connect \$9 $or$libresoc.v:50649$3273_Y + connect \$1 $not$libresoc.v:50650$3274_Y + connect \$3 $and$libresoc.v:50651$3275_Y + connect \$5 $or$libresoc.v:50652$3276_Y + connect \$7 $not$libresoc.v:50653$3277_Y connect \qlq_cyc \$9 connect \qn_cyc \$7 connect \q_cyc \q_int end -attribute \src "libresoc.v:50876.1-51617.10" +attribute \src "libresoc.v:50672.1-51413.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dbg" attribute \generator "nMigen" module \dbg - attribute \src "libresoc.v:51421.3-51433.6" + attribute \src "libresoc.v:51217.3-51229.6" wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:51228.3-51237.6" + attribute \src "libresoc.v:51024.3-51033.6" wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:51434.3-51449.6" + attribute \src "libresoc.v:51230.3-51245.6" wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:51210.3-51227.6" + attribute \src "libresoc.v:51006.3-51023.6" wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:51450.3-51483.6" + attribute \src "libresoc.v:51246.3-51279.6" wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:51412.3-51420.6" + attribute \src "libresoc.v:51208.3-51216.6" wire $0\dmi_read_log_data$next[0:0]$3398 - attribute \src "libresoc.v:51188.3-51189.51" + attribute \src "libresoc.v:50984.3-50985.51" wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51403.3-51411.6" + attribute \src "libresoc.v:51199.3-51207.6" wire $0\dmi_read_log_data_1$next[0:0]$3395 - attribute \src "libresoc.v:51190.3-51191.55" + attribute \src "libresoc.v:50986.3-50987.55" wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51238.3-51246.6" + attribute \src "libresoc.v:51034.3-51042.6" wire $0\dmi_req_i_1$next[0:0]$3361 - attribute \src "libresoc.v:51200.3-51201.39" + attribute \src "libresoc.v:50996.3-50997.39" wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51574.3-51607.6" + attribute \src "libresoc.v:51370.3-51403.6" wire $0\do_dmi_log_rd$next[0:0]$3425 - attribute \src "libresoc.v:51202.3-51203.43" + attribute \src "libresoc.v:50998.3-50999.43" wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51544.3-51573.6" + attribute \src "libresoc.v:51340.3-51369.6" wire $0\do_icreset$next[0:0]$3418 - attribute \src "libresoc.v:51204.3-51205.37" + attribute \src "libresoc.v:51000.3-51001.37" wire $0\do_icreset[0:0] - attribute \src "libresoc.v:51514.3-51543.6" + attribute \src "libresoc.v:51310.3-51339.6" wire $0\do_reset$next[0:0]$3411 - attribute \src "libresoc.v:51206.3-51207.33" + attribute \src "libresoc.v:51002.3-51003.33" wire $0\do_reset[0:0] - attribute \src "libresoc.v:51484.3-51513.6" + attribute \src "libresoc.v:51280.3-51309.6" wire $0\do_step$next[0:0]$3404 - attribute \src "libresoc.v:51208.3-51209.31" + attribute \src "libresoc.v:51004.3-51005.31" wire $0\do_step[0:0] - attribute \src "libresoc.v:51341.3-51368.6" + attribute \src "libresoc.v:51137.3-51164.6" wire width 7 $0\gspr_index$next[6:0]$3383 - attribute \src "libresoc.v:51194.3-51195.37" + attribute \src "libresoc.v:50990.3-50991.37" wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:50877.7-50877.20" + attribute \src "libresoc.v:50673.7-50673.20" wire $0\initial[0:0] - attribute \src "libresoc.v:51369.3-51402.6" + attribute \src "libresoc.v:51165.3-51198.6" wire width 32 $0\log_dmi_addr$next[31:0]$3389 - attribute \src "libresoc.v:51192.3-51193.41" + attribute \src "libresoc.v:50988.3-50989.41" wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:51297.3-51340.6" + attribute \src "libresoc.v:51093.3-51136.6" wire $0\stopping$next[0:0]$3374 - attribute \src "libresoc.v:51196.3-51197.33" + attribute \src "libresoc.v:50992.3-50993.33" wire $0\stopping[0:0] - attribute \src "libresoc.v:51247.3-51296.6" + attribute \src "libresoc.v:51043.3-51092.6" wire $0\terminated$next[0:0]$3364 - attribute \src "libresoc.v:51198.3-51199.37" + attribute \src "libresoc.v:50994.3-50995.37" wire $0\terminated[0:0] - attribute \src "libresoc.v:51421.3-51433.6" + attribute \src "libresoc.v:51217.3-51229.6" wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:51228.3-51237.6" + attribute \src "libresoc.v:51024.3-51033.6" wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51434.3-51449.6" + attribute \src "libresoc.v:51230.3-51245.6" wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:51210.3-51227.6" + attribute \src "libresoc.v:51006.3-51023.6" wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51450.3-51483.6" + attribute \src "libresoc.v:51246.3-51279.6" wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:51412.3-51420.6" + attribute \src "libresoc.v:51208.3-51216.6" wire $1\dmi_read_log_data$next[0:0]$3399 - attribute \src "libresoc.v:51064.7-51064.31" + attribute \src "libresoc.v:50860.7-50860.31" wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51403.3-51411.6" + attribute \src "libresoc.v:51199.3-51207.6" wire $1\dmi_read_log_data_1$next[0:0]$3396 - attribute \src "libresoc.v:51068.7-51068.33" + attribute \src "libresoc.v:50864.7-50864.33" wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51238.3-51246.6" + attribute \src "libresoc.v:51034.3-51042.6" wire $1\dmi_req_i_1$next[0:0]$3362 - attribute \src "libresoc.v:51074.7-51074.25" + attribute \src "libresoc.v:50870.7-50870.25" wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51574.3-51607.6" + attribute \src "libresoc.v:51370.3-51403.6" wire $1\do_dmi_log_rd$next[0:0]$3426 - attribute \src "libresoc.v:51080.7-51080.27" + attribute \src "libresoc.v:50876.7-50876.27" wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51544.3-51573.6" + attribute \src "libresoc.v:51340.3-51369.6" wire $1\do_icreset$next[0:0]$3419 - attribute \src "libresoc.v:51084.7-51084.24" + attribute \src "libresoc.v:50880.7-50880.24" wire $1\do_icreset[0:0] - attribute \src "libresoc.v:51514.3-51543.6" + attribute \src "libresoc.v:51310.3-51339.6" wire $1\do_reset$next[0:0]$3412 - attribute \src "libresoc.v:51088.7-51088.22" + attribute \src "libresoc.v:50884.7-50884.22" wire $1\do_reset[0:0] - attribute \src "libresoc.v:51484.3-51513.6" + attribute \src "libresoc.v:51280.3-51309.6" wire $1\do_step$next[0:0]$3405 - attribute \src "libresoc.v:51092.7-51092.21" + attribute \src "libresoc.v:50888.7-50888.21" wire $1\do_step[0:0] - attribute \src "libresoc.v:51341.3-51368.6" + attribute \src "libresoc.v:51137.3-51164.6" wire width 7 $1\gspr_index$next[6:0]$3384 - attribute \src "libresoc.v:51096.13-51096.31" + attribute \src "libresoc.v:50892.13-50892.31" wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:51369.3-51402.6" + attribute \src "libresoc.v:51165.3-51198.6" wire width 32 $1\log_dmi_addr$next[31:0]$3390 - attribute \src "libresoc.v:51102.14-51102.34" + attribute \src "libresoc.v:50898.14-50898.34" wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:51297.3-51340.6" + attribute \src "libresoc.v:51093.3-51136.6" wire $1\stopping$next[0:0]$3375 - attribute \src "libresoc.v:51114.7-51114.22" + attribute \src "libresoc.v:50910.7-50910.22" wire $1\stopping[0:0] - attribute \src "libresoc.v:51247.3-51296.6" + attribute \src "libresoc.v:51043.3-51092.6" wire $1\terminated$next[0:0]$3365 - attribute \src "libresoc.v:51120.7-51120.24" + attribute \src "libresoc.v:50916.7-50916.24" wire $1\terminated[0:0] - attribute \src "libresoc.v:51574.3-51607.6" + attribute \src "libresoc.v:51370.3-51403.6" wire $2\do_dmi_log_rd$next[0:0]$3427 - attribute \src "libresoc.v:51544.3-51573.6" + attribute \src "libresoc.v:51340.3-51369.6" wire $2\do_icreset$next[0:0]$3420 - attribute \src "libresoc.v:51514.3-51543.6" + attribute \src "libresoc.v:51310.3-51339.6" wire $2\do_reset$next[0:0]$3413 - attribute \src "libresoc.v:51484.3-51513.6" + attribute \src "libresoc.v:51280.3-51309.6" wire $2\do_step$next[0:0]$3406 - attribute \src "libresoc.v:51341.3-51368.6" + attribute \src "libresoc.v:51137.3-51164.6" wire width 7 $2\gspr_index$next[6:0]$3385 - attribute \src "libresoc.v:51369.3-51402.6" + attribute \src "libresoc.v:51165.3-51198.6" wire width 32 $2\log_dmi_addr$next[31:0]$3391 - attribute \src "libresoc.v:51297.3-51340.6" + attribute \src "libresoc.v:51093.3-51136.6" wire $2\stopping$next[0:0]$3376 - attribute \src "libresoc.v:51247.3-51296.6" + attribute \src "libresoc.v:51043.3-51092.6" wire $2\terminated$next[0:0]$3366 - attribute \src "libresoc.v:51574.3-51607.6" + attribute \src "libresoc.v:51370.3-51403.6" wire $3\do_dmi_log_rd$next[0:0]$3428 - attribute \src "libresoc.v:51544.3-51573.6" + attribute \src "libresoc.v:51340.3-51369.6" wire $3\do_icreset$next[0:0]$3421 - attribute \src "libresoc.v:51514.3-51543.6" + attribute \src "libresoc.v:51310.3-51339.6" wire $3\do_reset$next[0:0]$3414 - attribute \src "libresoc.v:51484.3-51513.6" + attribute \src "libresoc.v:51280.3-51309.6" wire $3\do_step$next[0:0]$3407 - attribute \src "libresoc.v:51341.3-51368.6" + attribute \src "libresoc.v:51137.3-51164.6" wire width 7 $3\gspr_index$next[6:0]$3386 - attribute \src "libresoc.v:51369.3-51402.6" + attribute \src "libresoc.v:51165.3-51198.6" wire width 32 $3\log_dmi_addr$next[31:0]$3392 - attribute \src "libresoc.v:51297.3-51340.6" + attribute \src "libresoc.v:51093.3-51136.6" wire $3\stopping$next[0:0]$3377 - attribute \src "libresoc.v:51247.3-51296.6" + attribute \src "libresoc.v:51043.3-51092.6" wire $3\terminated$next[0:0]$3367 - attribute \src "libresoc.v:51574.3-51607.6" + attribute \src "libresoc.v:51370.3-51403.6" wire $4\do_dmi_log_rd$next[0:0]$3429 - attribute \src "libresoc.v:51544.3-51573.6" + attribute \src "libresoc.v:51340.3-51369.6" wire $4\do_icreset$next[0:0]$3422 - attribute \src "libresoc.v:51514.3-51543.6" + attribute \src "libresoc.v:51310.3-51339.6" wire $4\do_reset$next[0:0]$3415 - attribute \src "libresoc.v:51484.3-51513.6" + attribute \src "libresoc.v:51280.3-51309.6" wire $4\do_step$next[0:0]$3408 - attribute \src "libresoc.v:51341.3-51368.6" + attribute \src "libresoc.v:51137.3-51164.6" wire width 7 $4\gspr_index$next[6:0]$3387 - attribute \src "libresoc.v:51369.3-51402.6" + attribute \src "libresoc.v:51165.3-51198.6" wire width 32 $4\log_dmi_addr$next[31:0]$3393 - attribute \src "libresoc.v:51297.3-51340.6" + attribute \src "libresoc.v:51093.3-51136.6" wire $4\stopping$next[0:0]$3378 - attribute \src "libresoc.v:51247.3-51296.6" + attribute \src "libresoc.v:51043.3-51092.6" wire $4\terminated$next[0:0]$3368 - attribute \src "libresoc.v:51544.3-51573.6" + attribute \src "libresoc.v:51340.3-51369.6" wire $5\do_icreset$next[0:0]$3423 - attribute \src "libresoc.v:51514.3-51543.6" + attribute \src "libresoc.v:51310.3-51339.6" wire $5\do_reset$next[0:0]$3416 - attribute \src "libresoc.v:51484.3-51513.6" + attribute \src "libresoc.v:51280.3-51309.6" wire $5\do_step$next[0:0]$3409 - attribute \src "libresoc.v:51297.3-51340.6" + attribute \src "libresoc.v:51093.3-51136.6" wire $5\stopping$next[0:0]$3379 - attribute \src "libresoc.v:51247.3-51296.6" + attribute \src "libresoc.v:51043.3-51092.6" wire $5\terminated$next[0:0]$3369 - attribute \src "libresoc.v:51297.3-51340.6" + attribute \src "libresoc.v:51093.3-51136.6" wire $6\stopping$next[0:0]$3380 - attribute \src "libresoc.v:51247.3-51296.6" + attribute \src "libresoc.v:51043.3-51092.6" wire $6\terminated$next[0:0]$3370 - attribute \src "libresoc.v:51297.3-51340.6" + attribute \src "libresoc.v:51093.3-51136.6" wire $7\stopping$next[0:0]$3381 - attribute \src "libresoc.v:51247.3-51296.6" + attribute \src "libresoc.v:51043.3-51092.6" wire $7\terminated$next[0:0]$3371 - attribute \src "libresoc.v:51247.3-51296.6" + attribute \src "libresoc.v:51043.3-51092.6" wire $8\terminated$next[0:0]$3372 - attribute \src "libresoc.v:51135.19-51135.110" - wire width 3 $add$libresoc.v:51135$3294_Y - attribute \src "libresoc.v:51129.19-51129.103" - wire $and$libresoc.v:51129$3288_Y - attribute \src "libresoc.v:51131.19-51131.113" - wire $and$libresoc.v:51131$3290_Y - attribute \src "libresoc.v:51136.18-51136.110" - wire $and$libresoc.v:51136$3295_Y - attribute \src "libresoc.v:51138.19-51138.103" - wire $and$libresoc.v:51138$3297_Y - attribute \src "libresoc.v:51140.19-51140.102" - wire $and$libresoc.v:51140$3299_Y - attribute \src "libresoc.v:51146.18-51146.101" - wire $and$libresoc.v:51146$3305_Y - attribute \src "libresoc.v:51148.18-51148.111" - wire $and$libresoc.v:51148$3307_Y - attribute \src "libresoc.v:51153.18-51153.101" - wire $and$libresoc.v:51153$3312_Y - attribute \src "libresoc.v:51156.18-51156.111" - wire $and$libresoc.v:51156$3315_Y - attribute \src "libresoc.v:51161.18-51161.101" - wire $and$libresoc.v:51161$3320_Y - attribute \src "libresoc.v:51163.18-51163.111" - wire $and$libresoc.v:51163$3322_Y - attribute \src "libresoc.v:51169.18-51169.101" - wire $and$libresoc.v:51169$3328_Y - attribute \src "libresoc.v:51171.18-51171.111" - wire $and$libresoc.v:51171$3330_Y - attribute \src "libresoc.v:51176.18-51176.101" - wire $and$libresoc.v:51176$3335_Y - attribute \src "libresoc.v:51177.17-51177.99" - wire $and$libresoc.v:51177$3336_Y - attribute \src "libresoc.v:51179.18-51179.111" - wire $and$libresoc.v:51179$3338_Y - attribute \src "libresoc.v:51184.18-51184.101" - wire $and$libresoc.v:51184$3343_Y - attribute \src "libresoc.v:51186.18-51186.111" - wire $and$libresoc.v:51186$3345_Y - attribute \src "libresoc.v:51126.18-51126.103" - wire $eq$libresoc.v:51126$3285_Y - attribute \src "libresoc.v:51127.19-51127.104" - wire $eq$libresoc.v:51127$3286_Y - attribute \src "libresoc.v:51132.19-51132.104" - wire $eq$libresoc.v:51132$3291_Y - attribute \src "libresoc.v:51133.19-51133.104" - wire $eq$libresoc.v:51133$3292_Y - attribute \src "libresoc.v:51134.19-51134.104" - wire $eq$libresoc.v:51134$3293_Y - attribute \src "libresoc.v:51137.19-51137.104" - wire $eq$libresoc.v:51137$3296_Y - attribute \src "libresoc.v:51141.18-51141.103" - wire $eq$libresoc.v:51141$3300_Y - attribute \src "libresoc.v:51142.18-51142.103" - wire $eq$libresoc.v:51142$3301_Y - attribute \src "libresoc.v:51143.18-51143.103" - wire $eq$libresoc.v:51143$3302_Y - attribute \src "libresoc.v:51149.18-51149.103" - wire $eq$libresoc.v:51149$3308_Y - attribute \src "libresoc.v:51150.18-51150.103" - wire $eq$libresoc.v:51150$3309_Y - attribute \src "libresoc.v:51151.18-51151.103" - wire $eq$libresoc.v:51151$3310_Y - attribute \src "libresoc.v:51157.18-51157.103" - wire $eq$libresoc.v:51157$3316_Y - attribute \src "libresoc.v:51158.18-51158.103" - wire $eq$libresoc.v:51158$3317_Y - attribute \src "libresoc.v:51159.18-51159.103" - wire $eq$libresoc.v:51159$3318_Y - attribute \src "libresoc.v:51164.18-51164.103" - wire $eq$libresoc.v:51164$3323_Y - attribute \src "libresoc.v:51165.18-51165.103" - wire $eq$libresoc.v:51165$3324_Y - attribute \src "libresoc.v:51167.18-51167.103" - wire $eq$libresoc.v:51167$3326_Y - attribute \src "libresoc.v:51172.18-51172.103" - wire $eq$libresoc.v:51172$3331_Y - attribute \src "libresoc.v:51173.18-51173.103" - wire $eq$libresoc.v:51173$3332_Y - attribute \src "libresoc.v:51174.18-51174.103" - wire $eq$libresoc.v:51174$3333_Y - attribute \src "libresoc.v:51180.18-51180.103" - wire $eq$libresoc.v:51180$3339_Y - attribute \src "libresoc.v:51181.18-51181.103" - wire $eq$libresoc.v:51181$3340_Y - attribute \src "libresoc.v:51182.18-51182.103" - wire $eq$libresoc.v:51182$3341_Y - attribute \src "libresoc.v:51187.18-51187.103" - wire $eq$libresoc.v:51187$3346_Y - attribute \src "libresoc.v:51125.17-51125.103" - wire $not$libresoc.v:51125$3284_Y - attribute \src "libresoc.v:51128.19-51128.99" - wire $not$libresoc.v:51128$3287_Y - attribute \src "libresoc.v:51130.19-51130.105" - wire $not$libresoc.v:51130$3289_Y - attribute \src "libresoc.v:51139.19-51139.95" - wire $not$libresoc.v:51139$3298_Y - attribute \src "libresoc.v:51145.18-51145.98" - wire $not$libresoc.v:51145$3304_Y - attribute \src "libresoc.v:51147.18-51147.104" - wire $not$libresoc.v:51147$3306_Y - attribute \src "libresoc.v:51152.18-51152.98" - wire $not$libresoc.v:51152$3311_Y - attribute \src "libresoc.v:51154.18-51154.104" - wire $not$libresoc.v:51154$3313_Y - attribute \src "libresoc.v:51160.18-51160.98" - wire $not$libresoc.v:51160$3319_Y - attribute \src "libresoc.v:51162.18-51162.104" - wire $not$libresoc.v:51162$3321_Y - attribute \src "libresoc.v:51166.17-51166.97" - wire $not$libresoc.v:51166$3325_Y - attribute \src "libresoc.v:51168.18-51168.98" - wire $not$libresoc.v:51168$3327_Y - attribute \src "libresoc.v:51170.18-51170.104" - wire $not$libresoc.v:51170$3329_Y - attribute \src "libresoc.v:51175.18-51175.98" - wire $not$libresoc.v:51175$3334_Y - attribute \src "libresoc.v:51178.18-51178.104" - wire $not$libresoc.v:51178$3337_Y - attribute \src "libresoc.v:51183.18-51183.98" - wire $not$libresoc.v:51183$3342_Y - attribute \src "libresoc.v:51185.18-51185.104" - wire $not$libresoc.v:51185$3344_Y - attribute \src "libresoc.v:51144.17-51144.126" - wire width 64 $pos$libresoc.v:51144$3303_Y - attribute \src "libresoc.v:51155.17-51155.245" - wire width 64 $pos$libresoc.v:51155$3314_Y + attribute \src "libresoc.v:50931.19-50931.110" + wire width 3 $add$libresoc.v:50931$3294_Y + attribute \src "libresoc.v:50925.19-50925.103" + wire $and$libresoc.v:50925$3288_Y + attribute \src "libresoc.v:50927.19-50927.113" + wire $and$libresoc.v:50927$3290_Y + attribute \src "libresoc.v:50932.18-50932.110" + wire $and$libresoc.v:50932$3295_Y + attribute \src "libresoc.v:50934.19-50934.103" + wire $and$libresoc.v:50934$3297_Y + attribute \src "libresoc.v:50936.19-50936.102" + wire $and$libresoc.v:50936$3299_Y + attribute \src "libresoc.v:50942.18-50942.101" + wire $and$libresoc.v:50942$3305_Y + attribute \src "libresoc.v:50944.18-50944.111" + wire $and$libresoc.v:50944$3307_Y + attribute \src "libresoc.v:50949.18-50949.101" + wire $and$libresoc.v:50949$3312_Y + attribute \src "libresoc.v:50952.18-50952.111" + wire $and$libresoc.v:50952$3315_Y + attribute \src "libresoc.v:50957.18-50957.101" + wire $and$libresoc.v:50957$3320_Y + attribute \src "libresoc.v:50959.18-50959.111" + wire $and$libresoc.v:50959$3322_Y + attribute \src "libresoc.v:50965.18-50965.101" + wire $and$libresoc.v:50965$3328_Y + attribute \src "libresoc.v:50967.18-50967.111" + wire $and$libresoc.v:50967$3330_Y + attribute \src "libresoc.v:50972.18-50972.101" + wire $and$libresoc.v:50972$3335_Y + attribute \src "libresoc.v:50973.17-50973.99" + wire $and$libresoc.v:50973$3336_Y + attribute \src "libresoc.v:50975.18-50975.111" + wire $and$libresoc.v:50975$3338_Y + attribute \src "libresoc.v:50980.18-50980.101" + wire $and$libresoc.v:50980$3343_Y + attribute \src "libresoc.v:50982.18-50982.111" + wire $and$libresoc.v:50982$3345_Y + attribute \src "libresoc.v:50922.18-50922.103" + wire $eq$libresoc.v:50922$3285_Y + attribute \src "libresoc.v:50923.19-50923.104" + wire $eq$libresoc.v:50923$3286_Y + attribute \src "libresoc.v:50928.19-50928.104" + wire $eq$libresoc.v:50928$3291_Y + attribute \src "libresoc.v:50929.19-50929.104" + wire $eq$libresoc.v:50929$3292_Y + attribute \src "libresoc.v:50930.19-50930.104" + wire $eq$libresoc.v:50930$3293_Y + attribute \src "libresoc.v:50933.19-50933.104" + wire $eq$libresoc.v:50933$3296_Y + attribute \src "libresoc.v:50937.18-50937.103" + wire $eq$libresoc.v:50937$3300_Y + attribute \src "libresoc.v:50938.18-50938.103" + wire $eq$libresoc.v:50938$3301_Y + attribute \src "libresoc.v:50939.18-50939.103" + wire $eq$libresoc.v:50939$3302_Y + attribute \src "libresoc.v:50945.18-50945.103" + wire $eq$libresoc.v:50945$3308_Y + attribute \src "libresoc.v:50946.18-50946.103" + wire $eq$libresoc.v:50946$3309_Y + attribute \src "libresoc.v:50947.18-50947.103" + wire $eq$libresoc.v:50947$3310_Y + attribute \src "libresoc.v:50953.18-50953.103" + wire $eq$libresoc.v:50953$3316_Y + attribute \src "libresoc.v:50954.18-50954.103" + wire $eq$libresoc.v:50954$3317_Y + attribute \src "libresoc.v:50955.18-50955.103" + wire $eq$libresoc.v:50955$3318_Y + attribute \src "libresoc.v:50960.18-50960.103" + wire $eq$libresoc.v:50960$3323_Y + attribute \src "libresoc.v:50961.18-50961.103" + wire $eq$libresoc.v:50961$3324_Y + attribute \src "libresoc.v:50963.18-50963.103" + wire $eq$libresoc.v:50963$3326_Y + attribute \src "libresoc.v:50968.18-50968.103" + wire $eq$libresoc.v:50968$3331_Y + attribute \src "libresoc.v:50969.18-50969.103" + wire $eq$libresoc.v:50969$3332_Y + attribute \src "libresoc.v:50970.18-50970.103" + wire $eq$libresoc.v:50970$3333_Y + attribute \src "libresoc.v:50976.18-50976.103" + wire $eq$libresoc.v:50976$3339_Y + attribute \src "libresoc.v:50977.18-50977.103" + wire $eq$libresoc.v:50977$3340_Y + attribute \src "libresoc.v:50978.18-50978.103" + wire $eq$libresoc.v:50978$3341_Y + attribute \src "libresoc.v:50983.18-50983.103" + wire $eq$libresoc.v:50983$3346_Y + attribute \src "libresoc.v:50921.17-50921.103" + wire $not$libresoc.v:50921$3284_Y + attribute \src "libresoc.v:50924.19-50924.99" + wire $not$libresoc.v:50924$3287_Y + attribute \src "libresoc.v:50926.19-50926.105" + wire $not$libresoc.v:50926$3289_Y + attribute \src "libresoc.v:50935.19-50935.95" + wire $not$libresoc.v:50935$3298_Y + attribute \src "libresoc.v:50941.18-50941.98" + wire $not$libresoc.v:50941$3304_Y + attribute \src "libresoc.v:50943.18-50943.104" + wire $not$libresoc.v:50943$3306_Y + attribute \src "libresoc.v:50948.18-50948.98" + wire $not$libresoc.v:50948$3311_Y + attribute \src "libresoc.v:50950.18-50950.104" + wire $not$libresoc.v:50950$3313_Y + attribute \src "libresoc.v:50956.18-50956.98" + wire $not$libresoc.v:50956$3319_Y + attribute \src "libresoc.v:50958.18-50958.104" + wire $not$libresoc.v:50958$3321_Y + attribute \src "libresoc.v:50962.17-50962.97" + wire $not$libresoc.v:50962$3325_Y + attribute \src "libresoc.v:50964.18-50964.98" + wire $not$libresoc.v:50964$3327_Y + attribute \src "libresoc.v:50966.18-50966.104" + wire $not$libresoc.v:50966$3329_Y + attribute \src "libresoc.v:50971.18-50971.98" + wire $not$libresoc.v:50971$3334_Y + attribute \src "libresoc.v:50974.18-50974.104" + wire $not$libresoc.v:50974$3337_Y + attribute \src "libresoc.v:50979.18-50979.98" + wire $not$libresoc.v:50979$3342_Y + attribute \src "libresoc.v:50981.18-50981.104" + wire $not$libresoc.v:50981$3344_Y + attribute \src "libresoc.v:50940.17-50940.126" + wire width 64 $pos$libresoc.v:50940$3303_Y + attribute \src "libresoc.v:50951.17-50951.245" + wire width 64 $pos$libresoc.v:50951$3314_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" @@ -90344,7 +90140,7 @@ module \dbg wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 30 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 input 13 \core_dbg_core_dbg_dststep @@ -90363,7 +90159,7 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 10 \core_dbg_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" - wire output 8 \core_rst_o + wire output 7 \core_rst_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" wire output 18 \core_stop_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104" @@ -90389,13 +90185,13 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" wire output 27 \d_xer_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63" - wire output 6 \dmi_ack_o + wire output 5 \dmi_ack_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 4 input 2 \dmi_addr_i + wire width 4 input 1 \dmi_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 input 5 \dmi_din + wire width 64 input 4 \dmi_din attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire width 64 output 7 \dmi_dout + wire width 64 output 6 \dmi_dout attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" wire \dmi_read_log_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" @@ -90405,13 +90201,13 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" wire \dmi_read_log_data_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire input 3 \dmi_req_i + wire input 2 \dmi_req_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" wire \dmi_req_i_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" wire \dmi_req_i_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire input 4 \dmi_we_i + wire input 3 \dmi_we_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" wire \do_dmi_log_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" @@ -90434,7 +90230,7 @@ module \dbg wire width 7 \gspr_index$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100" wire \icache_rst_o - attribute \src "libresoc.v:50877.7-50877.15" + attribute \src "libresoc.v:50673.7-50673.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" wire width 32 \log_dmi_addr @@ -90444,8 +90240,8 @@ module \dbg wire width 64 \log_dmi_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" - wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" + wire input 8 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" wire width 64 \stat_reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" @@ -90461,7 +90257,7 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" wire \terminated_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" - cell $add $add$libresoc.v:51135$3294 + cell $add $add$libresoc.v:50931$3294 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -90469,10 +90265,10 @@ module \dbg parameter \Y_WIDTH 3 connect \A \log_dmi_addr [1:0] connect \B 1'1 - connect \Y $add$libresoc.v:51135$3294_Y + connect \Y $add$libresoc.v:50931$3294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51129$3288 + cell $and $and$libresoc.v:50925$3288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90480,10 +90276,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$103 - connect \Y $and$libresoc.v:51129$3288_Y + connect \Y $and$libresoc.v:50925$3288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51131$3290 + cell $and $and$libresoc.v:50927$3290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90491,10 +90287,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$107 - connect \Y $and$libresoc.v:51131$3290_Y + connect \Y $and$libresoc.v:50927$3290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51136$3295 + cell $and $and$libresoc.v:50932$3295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90502,10 +90298,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$9 - connect \Y $and$libresoc.v:51136$3295_Y + connect \Y $and$libresoc.v:50932$3295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $and $and$libresoc.v:51138$3297 + cell $and $and$libresoc.v:50934$3297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90513,10 +90309,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$120 - connect \Y $and$libresoc.v:51138$3297_Y + connect \Y $and$libresoc.v:50934$3297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $and $and$libresoc.v:51140$3299 + cell $and $and$libresoc.v:50936$3299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90524,10 +90320,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \stopping connect \B \$124 - connect \Y $and$libresoc.v:51140$3299_Y + connect \Y $and$libresoc.v:50936$3299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51146$3305 + cell $and $and$libresoc.v:50942$3305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90535,10 +90331,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$19 - connect \Y $and$libresoc.v:51146$3305_Y + connect \Y $and$libresoc.v:50942$3305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51148$3307 + cell $and $and$libresoc.v:50944$3307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90546,10 +90342,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$23 - connect \Y $and$libresoc.v:51148$3307_Y + connect \Y $and$libresoc.v:50944$3307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51153$3312 + cell $and $and$libresoc.v:50949$3312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90557,10 +90353,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$33 - connect \Y $and$libresoc.v:51153$3312_Y + connect \Y $and$libresoc.v:50949$3312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51156$3315 + cell $and $and$libresoc.v:50952$3315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90568,10 +90364,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$37 - connect \Y $and$libresoc.v:51156$3315_Y + connect \Y $and$libresoc.v:50952$3315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51161$3320 + cell $and $and$libresoc.v:50957$3320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90579,10 +90375,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$47 - connect \Y $and$libresoc.v:51161$3320_Y + connect \Y $and$libresoc.v:50957$3320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51163$3322 + cell $and $and$libresoc.v:50959$3322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90590,10 +90386,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$51 - connect \Y $and$libresoc.v:51163$3322_Y + connect \Y $and$libresoc.v:50959$3322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51169$3328 + cell $and $and$libresoc.v:50965$3328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90601,10 +90397,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$61 - connect \Y $and$libresoc.v:51169$3328_Y + connect \Y $and$libresoc.v:50965$3328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51171$3330 + cell $and $and$libresoc.v:50967$3330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90612,10 +90408,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$65 - connect \Y $and$libresoc.v:51171$3330_Y + connect \Y $and$libresoc.v:50967$3330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51176$3335 + cell $and $and$libresoc.v:50972$3335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90623,10 +90419,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$75 - connect \Y $and$libresoc.v:51176$3335_Y + connect \Y $and$libresoc.v:50972$3335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51177$3336 + cell $and $and$libresoc.v:50973$3336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90634,10 +90430,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$5 - connect \Y $and$libresoc.v:51177$3336_Y + connect \Y $and$libresoc.v:50973$3336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51179$3338 + cell $and $and$libresoc.v:50975$3338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90645,10 +90441,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$79 - connect \Y $and$libresoc.v:51179$3338_Y + connect \Y $and$libresoc.v:50975$3338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51184$3343 + cell $and $and$libresoc.v:50980$3343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90656,10 +90452,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$89 - connect \Y $and$libresoc.v:51184$3343_Y + connect \Y $and$libresoc.v:50980$3343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51186$3345 + cell $and $and$libresoc.v:50982$3345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90667,10 +90463,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$93 - connect \Y $and$libresoc.v:51186$3345_Y + connect \Y $and$libresoc.v:50982$3345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51126$3285 + cell $eq $eq$libresoc.v:50922$3285 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90678,10 +90474,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51126$3285_Y + connect \Y $eq$libresoc.v:50922$3285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51127$3286 + cell $eq $eq$libresoc.v:50923$3286 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90689,10 +90485,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51127$3286_Y + connect \Y $eq$libresoc.v:50923$3286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51132$3291 + cell $eq $eq$libresoc.v:50928$3291 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90700,10 +90496,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51132$3291_Y + connect \Y $eq$libresoc.v:50928$3291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51133$3292 + cell $eq $eq$libresoc.v:50929$3292 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90711,10 +90507,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51133$3292_Y + connect \Y $eq$libresoc.v:50929$3292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51134$3293 + cell $eq $eq$libresoc.v:50930$3293 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90722,10 +90518,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51134$3293_Y + connect \Y $eq$libresoc.v:50930$3293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $eq $eq$libresoc.v:51137$3296 + cell $eq $eq$libresoc.v:50933$3296 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90733,10 +90529,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'111 - connect \Y $eq$libresoc.v:51137$3296_Y + connect \Y $eq$libresoc.v:50933$3296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51141$3300 + cell $eq $eq$libresoc.v:50937$3300 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90744,10 +90540,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51141$3300_Y + connect \Y $eq$libresoc.v:50937$3300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51142$3301 + cell $eq $eq$libresoc.v:50938$3301 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90755,10 +90551,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51142$3301_Y + connect \Y $eq$libresoc.v:50938$3301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51143$3302 + cell $eq $eq$libresoc.v:50939$3302 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90766,10 +90562,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51143$3302_Y + connect \Y $eq$libresoc.v:50939$3302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51149$3308 + cell $eq $eq$libresoc.v:50945$3308 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90777,10 +90573,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51149$3308_Y + connect \Y $eq$libresoc.v:50945$3308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51150$3309 + cell $eq $eq$libresoc.v:50946$3309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90788,10 +90584,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51150$3309_Y + connect \Y $eq$libresoc.v:50946$3309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51151$3310 + cell $eq $eq$libresoc.v:50947$3310 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90799,10 +90595,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51151$3310_Y + connect \Y $eq$libresoc.v:50947$3310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51157$3316 + cell $eq $eq$libresoc.v:50953$3316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90810,10 +90606,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51157$3316_Y + connect \Y $eq$libresoc.v:50953$3316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51158$3317 + cell $eq $eq$libresoc.v:50954$3317 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90821,10 +90617,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51158$3317_Y + connect \Y $eq$libresoc.v:50954$3317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51159$3318 + cell $eq $eq$libresoc.v:50955$3318 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90832,10 +90628,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51159$3318_Y + connect \Y $eq$libresoc.v:50955$3318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51164$3323 + cell $eq $eq$libresoc.v:50960$3323 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90843,10 +90639,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51164$3323_Y + connect \Y $eq$libresoc.v:50960$3323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51165$3324 + cell $eq $eq$libresoc.v:50961$3324 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90854,10 +90650,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51165$3324_Y + connect \Y $eq$libresoc.v:50961$3324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51167$3326 + cell $eq $eq$libresoc.v:50963$3326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90865,10 +90661,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51167$3326_Y + connect \Y $eq$libresoc.v:50963$3326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51172$3331 + cell $eq $eq$libresoc.v:50968$3331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90876,10 +90672,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51172$3331_Y + connect \Y $eq$libresoc.v:50968$3331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51173$3332 + cell $eq $eq$libresoc.v:50969$3332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90887,10 +90683,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51173$3332_Y + connect \Y $eq$libresoc.v:50969$3332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51174$3333 + cell $eq $eq$libresoc.v:50970$3333 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90898,10 +90694,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51174$3333_Y + connect \Y $eq$libresoc.v:50970$3333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51180$3339 + cell $eq $eq$libresoc.v:50976$3339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90909,10 +90705,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51180$3339_Y + connect \Y $eq$libresoc.v:50976$3339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51181$3340 + cell $eq $eq$libresoc.v:50977$3340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90920,10 +90716,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51181$3340_Y + connect \Y $eq$libresoc.v:50977$3340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51182$3341 + cell $eq $eq$libresoc.v:50978$3341 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90931,10 +90727,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51182$3341_Y + connect \Y $eq$libresoc.v:50978$3341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51187$3346 + cell $eq $eq$libresoc.v:50983$3346 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90942,340 +90738,340 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51187$3346_Y + connect \Y $eq$libresoc.v:50983$3346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51125$3284 + cell $not $not$libresoc.v:50921$3284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51125$3284_Y + connect \Y $not$libresoc.v:50921$3284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51128$3287 + cell $not $not$libresoc.v:50924$3287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51128$3287_Y + connect \Y $not$libresoc.v:50924$3287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51130$3289 + cell $not $not$libresoc.v:50926$3289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51130$3289_Y + connect \Y $not$libresoc.v:50926$3289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $not $not$libresoc.v:51139$3298 + cell $not $not$libresoc.v:50935$3298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \do_step - connect \Y $not$libresoc.v:51139$3298_Y + connect \Y $not$libresoc.v:50935$3298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51145$3304 + cell $not $not$libresoc.v:50941$3304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51145$3304_Y + connect \Y $not$libresoc.v:50941$3304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51147$3306 + cell $not $not$libresoc.v:50943$3306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51147$3306_Y + connect \Y $not$libresoc.v:50943$3306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51152$3311 + cell $not $not$libresoc.v:50948$3311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51152$3311_Y + connect \Y $not$libresoc.v:50948$3311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51154$3313 + cell $not $not$libresoc.v:50950$3313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51154$3313_Y + connect \Y $not$libresoc.v:50950$3313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51160$3319 + cell $not $not$libresoc.v:50956$3319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51160$3319_Y + connect \Y $not$libresoc.v:50956$3319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51162$3321 + cell $not $not$libresoc.v:50958$3321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51162$3321_Y + connect \Y $not$libresoc.v:50958$3321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51166$3325 + cell $not $not$libresoc.v:50962$3325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51166$3325_Y + connect \Y $not$libresoc.v:50962$3325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51168$3327 + cell $not $not$libresoc.v:50964$3327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51168$3327_Y + connect \Y $not$libresoc.v:50964$3327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51170$3329 + cell $not $not$libresoc.v:50966$3329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51170$3329_Y + connect \Y $not$libresoc.v:50966$3329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51175$3334 + cell $not $not$libresoc.v:50971$3334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51175$3334_Y + connect \Y $not$libresoc.v:50971$3334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51178$3337 + cell $not $not$libresoc.v:50974$3337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51178$3337_Y + connect \Y $not$libresoc.v:50974$3337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51183$3342 + cell $not $not$libresoc.v:50979$3342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51183$3342_Y + connect \Y $not$libresoc.v:50979$3342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51185$3344 + cell $not $not$libresoc.v:50981$3344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51185$3344_Y + connect \Y $not$libresoc.v:50981$3344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $pos $pos$libresoc.v:51144$3303 + cell $pos $pos$libresoc.v:50940$3303 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$libresoc.v:51144$3303_Y + connect \Y $pos$libresoc.v:50940$3303_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:51155$3314 + cell $pos $pos$libresoc.v:50951$3314 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep } - connect \Y $pos$libresoc.v:51155$3314_Y + connect \Y $pos$libresoc.v:50951$3314_Y end - attribute \src "libresoc.v:50877.7-50877.20" - process $proc$libresoc.v:50877$3430 + attribute \src "libresoc.v:50673.7-50673.20" + process $proc$libresoc.v:50673$3430 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:51064.7-51064.31" - process $proc$libresoc.v:51064$3431 + attribute \src "libresoc.v:50860.7-50860.31" + process $proc$libresoc.v:50860$3431 assign { } { } assign $1\dmi_read_log_data[0:0] 1'0 sync always sync init update \dmi_read_log_data $1\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51068.7-51068.33" - process $proc$libresoc.v:51068$3432 + attribute \src "libresoc.v:50864.7-50864.33" + process $proc$libresoc.v:50864$3432 assign { } { } assign $1\dmi_read_log_data_1[0:0] 1'0 sync always sync init update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51074.7-51074.25" - process $proc$libresoc.v:51074$3433 + attribute \src "libresoc.v:50870.7-50870.25" + process $proc$libresoc.v:50870$3433 assign { } { } assign $1\dmi_req_i_1[0:0] 1'0 sync always sync init update \dmi_req_i_1 $1\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51080.7-51080.27" - process $proc$libresoc.v:51080$3434 + attribute \src "libresoc.v:50876.7-50876.27" + process $proc$libresoc.v:50876$3434 assign { } { } assign $1\do_dmi_log_rd[0:0] 1'0 sync always sync init update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51084.7-51084.24" - process $proc$libresoc.v:51084$3435 + attribute \src "libresoc.v:50880.7-50880.24" + process $proc$libresoc.v:50880$3435 assign { } { } assign $1\do_icreset[0:0] 1'0 sync always sync init update \do_icreset $1\do_icreset[0:0] end - attribute \src "libresoc.v:51088.7-51088.22" - process $proc$libresoc.v:51088$3436 + attribute \src "libresoc.v:50884.7-50884.22" + process $proc$libresoc.v:50884$3436 assign { } { } assign $1\do_reset[0:0] 1'0 sync always sync init update \do_reset $1\do_reset[0:0] end - attribute \src "libresoc.v:51092.7-51092.21" - process $proc$libresoc.v:51092$3437 + attribute \src "libresoc.v:50888.7-50888.21" + process $proc$libresoc.v:50888$3437 assign { } { } assign $1\do_step[0:0] 1'0 sync always sync init update \do_step $1\do_step[0:0] end - attribute \src "libresoc.v:51096.13-51096.31" - process $proc$libresoc.v:51096$3438 + attribute \src "libresoc.v:50892.13-50892.31" + process $proc$libresoc.v:50892$3438 assign { } { } assign $1\gspr_index[6:0] 7'0000000 sync always sync init update \gspr_index $1\gspr_index[6:0] end - attribute \src "libresoc.v:51102.14-51102.34" - process $proc$libresoc.v:51102$3439 + attribute \src "libresoc.v:50898.14-50898.34" + process $proc$libresoc.v:50898$3439 assign { } { } assign $1\log_dmi_addr[31:0] 0 sync always sync init update \log_dmi_addr $1\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51114.7-51114.22" - process $proc$libresoc.v:51114$3440 + attribute \src "libresoc.v:50910.7-50910.22" + process $proc$libresoc.v:50910$3440 assign { } { } assign $1\stopping[0:0] 1'0 sync always sync init update \stopping $1\stopping[0:0] end - attribute \src "libresoc.v:51120.7-51120.24" - process $proc$libresoc.v:51120$3441 + attribute \src "libresoc.v:50916.7-50916.24" + process $proc$libresoc.v:50916$3441 assign { } { } assign $1\terminated[0:0] 1'0 sync always sync init update \terminated $1\terminated[0:0] end - attribute \src "libresoc.v:51188.3-51189.51" - process $proc$libresoc.v:51188$3347 + attribute \src "libresoc.v:50984.3-50985.51" + process $proc$libresoc.v:50984$3347 assign { } { } assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next sync posedge \clk update \dmi_read_log_data $0\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51190.3-51191.55" - process $proc$libresoc.v:51190$3348 + attribute \src "libresoc.v:50986.3-50987.55" + process $proc$libresoc.v:50986$3348 assign { } { } assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next sync posedge \clk update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51192.3-51193.41" - process $proc$libresoc.v:51192$3349 + attribute \src "libresoc.v:50988.3-50989.41" + process $proc$libresoc.v:50988$3349 assign { } { } assign $0\log_dmi_addr[31:0] \log_dmi_addr$next sync posedge \clk update \log_dmi_addr $0\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51194.3-51195.37" - process $proc$libresoc.v:51194$3350 + attribute \src "libresoc.v:50990.3-50991.37" + process $proc$libresoc.v:50990$3350 assign { } { } assign $0\gspr_index[6:0] \gspr_index$next sync posedge \clk update \gspr_index $0\gspr_index[6:0] end - attribute \src "libresoc.v:51196.3-51197.33" - process $proc$libresoc.v:51196$3351 + attribute \src "libresoc.v:50992.3-50993.33" + process $proc$libresoc.v:50992$3351 assign { } { } assign $0\stopping[0:0] \stopping$next sync posedge \clk update \stopping $0\stopping[0:0] end - attribute \src "libresoc.v:51198.3-51199.37" - process $proc$libresoc.v:51198$3352 + attribute \src "libresoc.v:50994.3-50995.37" + process $proc$libresoc.v:50994$3352 assign { } { } assign $0\terminated[0:0] \terminated$next sync posedge \clk update \terminated $0\terminated[0:0] end - attribute \src "libresoc.v:51200.3-51201.39" - process $proc$libresoc.v:51200$3353 + attribute \src "libresoc.v:50996.3-50997.39" + process $proc$libresoc.v:50996$3353 assign { } { } assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next sync posedge \clk update \dmi_req_i_1 $0\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51202.3-51203.43" - process $proc$libresoc.v:51202$3354 + attribute \src "libresoc.v:50998.3-50999.43" + process $proc$libresoc.v:50998$3354 assign { } { } assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next sync posedge \clk update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51204.3-51205.37" - process $proc$libresoc.v:51204$3355 + attribute \src "libresoc.v:51000.3-51001.37" + process $proc$libresoc.v:51000$3355 assign { } { } assign $0\do_icreset[0:0] \do_icreset$next sync posedge \clk update \do_icreset $0\do_icreset[0:0] end - attribute \src "libresoc.v:51206.3-51207.33" - process $proc$libresoc.v:51206$3356 + attribute \src "libresoc.v:51002.3-51003.33" + process $proc$libresoc.v:51002$3356 assign { } { } assign $0\do_reset[0:0] \do_reset$next sync posedge \clk update \do_reset $0\do_reset[0:0] end - attribute \src "libresoc.v:51208.3-51209.31" - process $proc$libresoc.v:51208$3357 + attribute \src "libresoc.v:51004.3-51005.31" + process $proc$libresoc.v:51004$3357 assign { } { } assign $0\do_step[0:0] \do_step$next sync posedge \clk update \do_step $0\do_step[0:0] end - attribute \src "libresoc.v:51210.3-51227.6" - process $proc$libresoc.v:51210$3358 + attribute \src "libresoc.v:51006.3-51023.6" + process $proc$libresoc.v:51006$3358 assign { } { } assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51211.5-51211.29" + attribute \src "libresoc.v:51007.5-51007.29" switch \initial - attribute \src "libresoc.v:51211.9-51211.17" + attribute \src "libresoc.v:51007.9-51007.17" case 1'1 case end @@ -91301,14 +91097,14 @@ module \dbg sync always update \dmi_ack_o $0\dmi_ack_o[0:0] end - attribute \src "libresoc.v:51228.3-51237.6" - process $proc$libresoc.v:51228$3359 + attribute \src "libresoc.v:51024.3-51033.6" + process $proc$libresoc.v:51024$3359 assign { } { } assign { } { } assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51229.5-51229.29" + attribute \src "libresoc.v:51025.5-51025.29" switch \initial - attribute \src "libresoc.v:51229.9-51229.17" + attribute \src "libresoc.v:51025.9-51025.17" case 1'1 case end @@ -91324,14 +91120,14 @@ module \dbg sync always update \d_gpr_req $0\d_gpr_req[0:0] end - attribute \src "libresoc.v:51238.3-51246.6" - process $proc$libresoc.v:51238$3360 + attribute \src "libresoc.v:51034.3-51042.6" + process $proc$libresoc.v:51034$3360 assign { } { } assign { } { } assign $0\dmi_req_i_1$next[0:0]$3361 $1\dmi_req_i_1$next[0:0]$3362 - attribute \src "libresoc.v:51239.5-51239.29" + attribute \src "libresoc.v:51035.5-51035.29" switch \initial - attribute \src "libresoc.v:51239.9-51239.17" + attribute \src "libresoc.v:51035.9-51035.17" case 1'1 case end @@ -91347,16 +91143,16 @@ module \dbg sync always update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3361 end - attribute \src "libresoc.v:51247.3-51296.6" - process $proc$libresoc.v:51247$3363 + attribute \src "libresoc.v:51043.3-51092.6" + process $proc$libresoc.v:51043$3363 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\terminated$next[0:0]$3364 $8\terminated$next[0:0]$3372 - attribute \src "libresoc.v:51248.5-51248.29" + attribute \src "libresoc.v:51044.5-51044.29" switch \initial - attribute \src "libresoc.v:51248.9-51248.17" + attribute \src "libresoc.v:51044.9-51044.17" case 1'1 case end @@ -91437,16 +91233,16 @@ module \dbg sync always update \terminated$next $0\terminated$next[0:0]$3364 end - attribute \src "libresoc.v:51297.3-51340.6" - process $proc$libresoc.v:51297$3373 + attribute \src "libresoc.v:51093.3-51136.6" + process $proc$libresoc.v:51093$3373 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\stopping$next[0:0]$3374 $7\stopping$next[0:0]$3381 - attribute \src "libresoc.v:51298.5-51298.29" + attribute \src "libresoc.v:51094.5-51094.29" switch \initial - attribute \src "libresoc.v:51298.9-51298.17" + attribute \src "libresoc.v:51094.9-51094.17" case 1'1 case end @@ -91517,15 +91313,15 @@ module \dbg sync always update \stopping$next $0\stopping$next[0:0]$3374 end - attribute \src "libresoc.v:51341.3-51368.6" - process $proc$libresoc.v:51341$3382 + attribute \src "libresoc.v:51137.3-51164.6" + process $proc$libresoc.v:51137$3382 assign { } { } assign { } { } assign { } { } assign $0\gspr_index$next[6:0]$3383 $4\gspr_index$next[6:0]$3387 - attribute \src "libresoc.v:51342.5-51342.29" + attribute \src "libresoc.v:51138.5-51138.29" switch \initial - attribute \src "libresoc.v:51342.9-51342.17" + attribute \src "libresoc.v:51138.9-51138.17" case 1'1 case end @@ -91571,15 +91367,15 @@ module \dbg sync always update \gspr_index$next $0\gspr_index$next[6:0]$3383 end - attribute \src "libresoc.v:51369.3-51402.6" - process $proc$libresoc.v:51369$3388 + attribute \src "libresoc.v:51165.3-51198.6" + process $proc$libresoc.v:51165$3388 assign { } { } assign { } { } assign { } { } assign $0\log_dmi_addr$next[31:0]$3389 $4\log_dmi_addr$next[31:0]$3393 - attribute \src "libresoc.v:51370.5-51370.29" + attribute \src "libresoc.v:51166.5-51166.29" switch \initial - attribute \src "libresoc.v:51370.9-51370.17" + attribute \src "libresoc.v:51166.9-51166.17" case 1'1 case end @@ -91632,14 +91428,14 @@ module \dbg sync always update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3389 end - attribute \src "libresoc.v:51403.3-51411.6" - process $proc$libresoc.v:51403$3394 + attribute \src "libresoc.v:51199.3-51207.6" + process $proc$libresoc.v:51199$3394 assign { } { } assign { } { } assign $0\dmi_read_log_data_1$next[0:0]$3395 $1\dmi_read_log_data_1$next[0:0]$3396 - attribute \src "libresoc.v:51404.5-51404.29" + attribute \src "libresoc.v:51200.5-51200.29" switch \initial - attribute \src "libresoc.v:51404.9-51404.17" + attribute \src "libresoc.v:51200.9-51200.17" case 1'1 case end @@ -91655,14 +91451,14 @@ module \dbg sync always update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3395 end - attribute \src "libresoc.v:51412.3-51420.6" - process $proc$libresoc.v:51412$3397 + attribute \src "libresoc.v:51208.3-51216.6" + process $proc$libresoc.v:51208$3397 assign { } { } assign { } { } assign $0\dmi_read_log_data$next[0:0]$3398 $1\dmi_read_log_data$next[0:0]$3399 - attribute \src "libresoc.v:51413.5-51413.29" + attribute \src "libresoc.v:51209.5-51209.29" switch \initial - attribute \src "libresoc.v:51413.9-51413.17" + attribute \src "libresoc.v:51209.9-51209.17" case 1'1 case end @@ -91678,14 +91474,14 @@ module \dbg sync always update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3398 end - attribute \src "libresoc.v:51421.3-51433.6" - process $proc$libresoc.v:51421$3400 + attribute \src "libresoc.v:51217.3-51229.6" + process $proc$libresoc.v:51217$3400 assign { } { } assign { } { } assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:51422.5-51422.29" + attribute \src "libresoc.v:51218.5-51218.29" switch \initial - attribute \src "libresoc.v:51422.9-51422.17" + attribute \src "libresoc.v:51218.9-51218.17" case 1'1 case end @@ -91704,14 +91500,14 @@ module \dbg sync always update \d_cr_req $0\d_cr_req[0:0] end - attribute \src "libresoc.v:51434.3-51449.6" - process $proc$libresoc.v:51434$3401 + attribute \src "libresoc.v:51230.3-51245.6" + process $proc$libresoc.v:51230$3401 assign { } { } assign { } { } assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:51435.5-51435.29" + attribute \src "libresoc.v:51231.5-51231.29" switch \initial - attribute \src "libresoc.v:51435.9-51435.17" + attribute \src "libresoc.v:51231.9-51231.17" case 1'1 case end @@ -91733,14 +91529,14 @@ module \dbg sync always update \d_xer_req $0\d_xer_req[0:0] end - attribute \src "libresoc.v:51450.3-51483.6" - process $proc$libresoc.v:51450$3402 + attribute \src "libresoc.v:51246.3-51279.6" + process $proc$libresoc.v:51246$3402 assign { } { } assign { } { } assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:51451.5-51451.29" + attribute \src "libresoc.v:51247.5-51247.29" switch \initial - attribute \src "libresoc.v:51451.9-51451.17" + attribute \src "libresoc.v:51247.9-51247.17" case 1'1 case end @@ -91788,15 +91584,15 @@ module \dbg sync always update \dmi_dout $0\dmi_dout[63:0] end - attribute \src "libresoc.v:51484.3-51513.6" - process $proc$libresoc.v:51484$3403 + attribute \src "libresoc.v:51280.3-51309.6" + process $proc$libresoc.v:51280$3403 assign { } { } assign { } { } assign { } { } assign $0\do_step$next[0:0]$3404 $5\do_step$next[0:0]$3409 - attribute \src "libresoc.v:51485.5-51485.29" + attribute \src "libresoc.v:51281.5-51281.29" switch \initial - attribute \src "libresoc.v:51485.9-51485.17" + attribute \src "libresoc.v:51281.9-51281.17" case 1'1 case end @@ -91848,15 +91644,15 @@ module \dbg sync always update \do_step$next $0\do_step$next[0:0]$3404 end - attribute \src "libresoc.v:51514.3-51543.6" - process $proc$libresoc.v:51514$3410 + attribute \src "libresoc.v:51310.3-51339.6" + process $proc$libresoc.v:51310$3410 assign { } { } assign { } { } assign { } { } assign $0\do_reset$next[0:0]$3411 $5\do_reset$next[0:0]$3416 - attribute \src "libresoc.v:51515.5-51515.29" + attribute \src "libresoc.v:51311.5-51311.29" switch \initial - attribute \src "libresoc.v:51515.9-51515.17" + attribute \src "libresoc.v:51311.9-51311.17" case 1'1 case end @@ -91908,15 +91704,15 @@ module \dbg sync always update \do_reset$next $0\do_reset$next[0:0]$3411 end - attribute \src "libresoc.v:51544.3-51573.6" - process $proc$libresoc.v:51544$3417 + attribute \src "libresoc.v:51340.3-51369.6" + process $proc$libresoc.v:51340$3417 assign { } { } assign { } { } assign { } { } assign $0\do_icreset$next[0:0]$3418 $5\do_icreset$next[0:0]$3423 - attribute \src "libresoc.v:51545.5-51545.29" + attribute \src "libresoc.v:51341.5-51341.29" switch \initial - attribute \src "libresoc.v:51545.9-51545.17" + attribute \src "libresoc.v:51341.9-51341.17" case 1'1 case end @@ -91968,15 +91764,15 @@ module \dbg sync always update \do_icreset$next $0\do_icreset$next[0:0]$3418 end - attribute \src "libresoc.v:51574.3-51607.6" - process $proc$libresoc.v:51574$3424 + attribute \src "libresoc.v:51370.3-51403.6" + process $proc$libresoc.v:51370$3424 assign { } { } assign { } { } assign { } { } assign $0\do_dmi_log_rd$next[0:0]$3425 $4\do_dmi_log_rd$next[0:0]$3429 - attribute \src "libresoc.v:51575.5-51575.29" + attribute \src "libresoc.v:51371.5-51371.29" switch \initial - attribute \src "libresoc.v:51575.9-51575.17" + attribute \src "libresoc.v:51371.9-51371.17" case 1'1 case end @@ -92029,69 +91825,69 @@ module \dbg sync always update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3425 end - connect \$9 $not$libresoc.v:51125$3284_Y - connect \$99 $eq$libresoc.v:51126$3285_Y - connect \$101 $eq$libresoc.v:51127$3286_Y - connect \$103 $not$libresoc.v:51128$3287_Y - connect \$105 $and$libresoc.v:51129$3288_Y - connect \$107 $not$libresoc.v:51130$3289_Y - connect \$109 $and$libresoc.v:51131$3290_Y - connect \$111 $eq$libresoc.v:51132$3291_Y - connect \$113 $eq$libresoc.v:51133$3292_Y - connect \$115 $eq$libresoc.v:51134$3293_Y - connect \$118 $add$libresoc.v:51135$3294_Y - connect \$11 $and$libresoc.v:51136$3295_Y - connect \$120 $eq$libresoc.v:51137$3296_Y - connect \$122 $and$libresoc.v:51138$3297_Y - connect \$124 $not$libresoc.v:51139$3298_Y - connect \$126 $and$libresoc.v:51140$3299_Y - connect \$13 $eq$libresoc.v:51141$3300_Y - connect \$15 $eq$libresoc.v:51142$3301_Y - connect \$17 $eq$libresoc.v:51143$3302_Y - connect \$1 $pos$libresoc.v:51144$3303_Y - connect \$19 $not$libresoc.v:51145$3304_Y - connect \$21 $and$libresoc.v:51146$3305_Y - connect \$23 $not$libresoc.v:51147$3306_Y - connect \$25 $and$libresoc.v:51148$3307_Y - connect \$27 $eq$libresoc.v:51149$3308_Y - connect \$29 $eq$libresoc.v:51150$3309_Y - connect \$31 $eq$libresoc.v:51151$3310_Y - connect \$33 $not$libresoc.v:51152$3311_Y - connect \$35 $and$libresoc.v:51153$3312_Y - connect \$37 $not$libresoc.v:51154$3313_Y - connect \$3 $pos$libresoc.v:51155$3314_Y - connect \$39 $and$libresoc.v:51156$3315_Y - connect \$41 $eq$libresoc.v:51157$3316_Y - connect \$43 $eq$libresoc.v:51158$3317_Y - connect \$45 $eq$libresoc.v:51159$3318_Y - connect \$47 $not$libresoc.v:51160$3319_Y - connect \$49 $and$libresoc.v:51161$3320_Y - connect \$51 $not$libresoc.v:51162$3321_Y - connect \$53 $and$libresoc.v:51163$3322_Y - connect \$55 $eq$libresoc.v:51164$3323_Y - connect \$57 $eq$libresoc.v:51165$3324_Y - connect \$5 $not$libresoc.v:51166$3325_Y - connect \$59 $eq$libresoc.v:51167$3326_Y - connect \$61 $not$libresoc.v:51168$3327_Y - connect \$63 $and$libresoc.v:51169$3328_Y - connect \$65 $not$libresoc.v:51170$3329_Y - connect \$67 $and$libresoc.v:51171$3330_Y - connect \$69 $eq$libresoc.v:51172$3331_Y - connect \$71 $eq$libresoc.v:51173$3332_Y - connect \$73 $eq$libresoc.v:51174$3333_Y - connect \$75 $not$libresoc.v:51175$3334_Y - connect \$77 $and$libresoc.v:51176$3335_Y - connect \$7 $and$libresoc.v:51177$3336_Y - connect \$79 $not$libresoc.v:51178$3337_Y - connect \$81 $and$libresoc.v:51179$3338_Y - connect \$83 $eq$libresoc.v:51180$3339_Y - connect \$85 $eq$libresoc.v:51181$3340_Y - connect \$87 $eq$libresoc.v:51182$3341_Y - connect \$89 $not$libresoc.v:51183$3342_Y - connect \$91 $and$libresoc.v:51184$3343_Y - connect \$93 $not$libresoc.v:51185$3344_Y - connect \$95 $and$libresoc.v:51186$3345_Y - connect \$97 $eq$libresoc.v:51187$3346_Y + connect \$9 $not$libresoc.v:50921$3284_Y + connect \$99 $eq$libresoc.v:50922$3285_Y + connect \$101 $eq$libresoc.v:50923$3286_Y + connect \$103 $not$libresoc.v:50924$3287_Y + connect \$105 $and$libresoc.v:50925$3288_Y + connect \$107 $not$libresoc.v:50926$3289_Y + connect \$109 $and$libresoc.v:50927$3290_Y + connect \$111 $eq$libresoc.v:50928$3291_Y + connect \$113 $eq$libresoc.v:50929$3292_Y + connect \$115 $eq$libresoc.v:50930$3293_Y + connect \$118 $add$libresoc.v:50931$3294_Y + connect \$11 $and$libresoc.v:50932$3295_Y + connect \$120 $eq$libresoc.v:50933$3296_Y + connect \$122 $and$libresoc.v:50934$3297_Y + connect \$124 $not$libresoc.v:50935$3298_Y + connect \$126 $and$libresoc.v:50936$3299_Y + connect \$13 $eq$libresoc.v:50937$3300_Y + connect \$15 $eq$libresoc.v:50938$3301_Y + connect \$17 $eq$libresoc.v:50939$3302_Y + connect \$1 $pos$libresoc.v:50940$3303_Y + connect \$19 $not$libresoc.v:50941$3304_Y + connect \$21 $and$libresoc.v:50942$3305_Y + connect \$23 $not$libresoc.v:50943$3306_Y + connect \$25 $and$libresoc.v:50944$3307_Y + connect \$27 $eq$libresoc.v:50945$3308_Y + connect \$29 $eq$libresoc.v:50946$3309_Y + connect \$31 $eq$libresoc.v:50947$3310_Y + connect \$33 $not$libresoc.v:50948$3311_Y + connect \$35 $and$libresoc.v:50949$3312_Y + connect \$37 $not$libresoc.v:50950$3313_Y + connect \$3 $pos$libresoc.v:50951$3314_Y + connect \$39 $and$libresoc.v:50952$3315_Y + connect \$41 $eq$libresoc.v:50953$3316_Y + connect \$43 $eq$libresoc.v:50954$3317_Y + connect \$45 $eq$libresoc.v:50955$3318_Y + connect \$47 $not$libresoc.v:50956$3319_Y + connect \$49 $and$libresoc.v:50957$3320_Y + connect \$51 $not$libresoc.v:50958$3321_Y + connect \$53 $and$libresoc.v:50959$3322_Y + connect \$55 $eq$libresoc.v:50960$3323_Y + connect \$57 $eq$libresoc.v:50961$3324_Y + connect \$5 $not$libresoc.v:50962$3325_Y + connect \$59 $eq$libresoc.v:50963$3326_Y + connect \$61 $not$libresoc.v:50964$3327_Y + connect \$63 $and$libresoc.v:50965$3328_Y + connect \$65 $not$libresoc.v:50966$3329_Y + connect \$67 $and$libresoc.v:50967$3330_Y + connect \$69 $eq$libresoc.v:50968$3331_Y + connect \$71 $eq$libresoc.v:50969$3332_Y + connect \$73 $eq$libresoc.v:50970$3333_Y + connect \$75 $not$libresoc.v:50971$3334_Y + connect \$77 $and$libresoc.v:50972$3335_Y + connect \$7 $and$libresoc.v:50973$3336_Y + connect \$79 $not$libresoc.v:50974$3337_Y + connect \$81 $and$libresoc.v:50975$3338_Y + connect \$83 $eq$libresoc.v:50976$3339_Y + connect \$85 $eq$libresoc.v:50977$3340_Y + connect \$87 $eq$libresoc.v:50978$3341_Y + connect \$89 $not$libresoc.v:50979$3342_Y + connect \$91 $and$libresoc.v:50980$3343_Y + connect \$93 $not$libresoc.v:50981$3344_Y + connect \$95 $and$libresoc.v:50982$3345_Y + connect \$97 $eq$libresoc.v:50983$3346_Y connect \$117 \$118 connect \log_write_addr_o 0 connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -92102,71 +91898,71 @@ module \dbg connect \d_gpr_addr \gspr_index connect \stat_reg \$1 end -attribute \src "libresoc.v:51621.1-53671.10" +attribute \src "libresoc.v:51417.1-53467.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec" attribute \generator "nMigen" module \dec - attribute \src "libresoc.v:53232.3-53265.6" + attribute \src "libresoc.v:53028.3-53061.6" wire width 3 $0\ALU_cr_in[2:0] - attribute \src "libresoc.v:53266.3-53299.6" + attribute \src "libresoc.v:53062.3-53095.6" wire width 3 $0\ALU_cr_out[2:0] - attribute \src "libresoc.v:52892.3-52925.6" + attribute \src "libresoc.v:52688.3-52721.6" wire width 2 $0\ALU_cry_in[1:0] - attribute \src "libresoc.v:52994.3-53027.6" + attribute \src "libresoc.v:52790.3-52823.6" wire $0\ALU_cry_out[0:0] - attribute \src "libresoc.v:53096.3-53129.6" + attribute \src "libresoc.v:52892.3-52925.6" wire width 14 $0\ALU_function_unit[13:0] - attribute \src "libresoc.v:53164.3-53197.6" + attribute \src "libresoc.v:52960.3-52993.6" wire width 3 $0\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53198.3-53231.6" + attribute \src "libresoc.v:52994.3-53027.6" wire width 4 $0\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53130.3-53163.6" - wire width 7 $0\ALU_internal_op[6:0] attribute \src "libresoc.v:52926.3-52959.6" + wire width 7 $0\ALU_internal_op[6:0] + attribute \src "libresoc.v:52722.3-52755.6" wire $0\ALU_inv_a[0:0] - attribute \src "libresoc.v:52960.3-52993.6" + attribute \src "libresoc.v:52756.3-52789.6" wire $0\ALU_inv_out[0:0] - attribute \src "libresoc.v:53028.3-53061.6" + attribute \src "libresoc.v:52824.3-52857.6" wire $0\ALU_is_32b[0:0] - attribute \src "libresoc.v:53300.3-53333.6" + attribute \src "libresoc.v:53096.3-53129.6" wire width 4 $0\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52858.3-52891.6" + attribute \src "libresoc.v:52654.3-52687.6" wire width 2 $0\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53062.3-53095.6" + attribute \src "libresoc.v:52858.3-52891.6" wire $0\ALU_sgn[0:0] - attribute \src "libresoc.v:51622.7-51622.20" + attribute \src "libresoc.v:51418.7-51418.20" wire $0\initial[0:0] - attribute \src "libresoc.v:53232.3-53265.6" + attribute \src "libresoc.v:53028.3-53061.6" wire width 3 $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53266.3-53299.6" + attribute \src "libresoc.v:53062.3-53095.6" wire width 3 $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:52892.3-52925.6" + attribute \src "libresoc.v:52688.3-52721.6" wire width 2 $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:52994.3-53027.6" + attribute \src "libresoc.v:52790.3-52823.6" wire $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:53096.3-53129.6" + attribute \src "libresoc.v:52892.3-52925.6" wire width 14 $1\ALU_function_unit[13:0] - attribute \src "libresoc.v:53164.3-53197.6" + attribute \src "libresoc.v:52960.3-52993.6" wire width 3 $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53198.3-53231.6" + attribute \src "libresoc.v:52994.3-53027.6" wire width 4 $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53130.3-53163.6" - wire width 7 $1\ALU_internal_op[6:0] attribute \src "libresoc.v:52926.3-52959.6" + wire width 7 $1\ALU_internal_op[6:0] + attribute \src "libresoc.v:52722.3-52755.6" wire $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52960.3-52993.6" + attribute \src "libresoc.v:52756.3-52789.6" wire $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:53028.3-53061.6" + attribute \src "libresoc.v:52824.3-52857.6" wire $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53300.3-53333.6" + attribute \src "libresoc.v:53096.3-53129.6" wire width 4 $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52858.3-52891.6" + attribute \src "libresoc.v:52654.3-52687.6" wire width 2 $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53062.3-53095.6" + attribute \src "libresoc.v:52858.3-52891.6" wire $1\ALU_sgn[0:0] - attribute \src "libresoc.v:52823.17-52823.211" - wire width 32 $ternary$libresoc.v:52823$3442_Y + attribute \src "libresoc.v:52619.17-52619.211" + wire width 32 $ternary$libresoc.v:52619$3442_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -93348,7 +93144,7 @@ module \dec wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:51622.7-51622.15" + attribute \src "libresoc.v:51418.7-51418.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -93357,15 +93153,15 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:52823$3442 + cell $mux $ternary$libresoc.v:52619$3442 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:52823$3442_Y + connect \Y $ternary$libresoc.v:52619$3442_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:52824.13-52840.4" + attribute \src "libresoc.v:52620.13-52636.4" cell \ALU_dec19 \ALU_dec19 connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out @@ -93384,7 +93180,7 @@ module \dec connect \opcode_in \ALU_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:52841.13-52857.4" + attribute \src "libresoc.v:52637.13-52653.4" cell \ALU_dec31 \ALU_dec31 connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out @@ -93402,22 +93198,22 @@ module \dec connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn connect \opcode_in \ALU_dec31_opcode_in end - attribute \src "libresoc.v:51622.7-51622.20" - process $proc$libresoc.v:51622$3457 + attribute \src "libresoc.v:51418.7-51418.20" + process $proc$libresoc.v:51418$3457 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:52858.3-52891.6" - process $proc$libresoc.v:52858$3443 + attribute \src "libresoc.v:52654.3-52687.6" + process $proc$libresoc.v:52654$3443 assign { } { } assign { } { } assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52859.5-52859.29" + attribute \src "libresoc.v:52655.5-52655.29" switch \initial - attribute \src "libresoc.v:52859.9-52859.17" + attribute \src "libresoc.v:52655.9-52655.17" case 1'1 case end @@ -93465,14 +93261,14 @@ module \dec sync always update \ALU_rc_sel $0\ALU_rc_sel[1:0] end - attribute \src "libresoc.v:52892.3-52925.6" - process $proc$libresoc.v:52892$3444 + attribute \src "libresoc.v:52688.3-52721.6" + process $proc$libresoc.v:52688$3444 assign { } { } assign { } { } assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:52893.5-52893.29" + attribute \src "libresoc.v:52689.5-52689.29" switch \initial - attribute \src "libresoc.v:52893.9-52893.17" + attribute \src "libresoc.v:52689.9-52689.17" case 1'1 case end @@ -93520,14 +93316,14 @@ module \dec sync always update \ALU_cry_in $0\ALU_cry_in[1:0] end - attribute \src "libresoc.v:52926.3-52959.6" - process $proc$libresoc.v:52926$3445 + attribute \src "libresoc.v:52722.3-52755.6" + process $proc$libresoc.v:52722$3445 assign { } { } assign { } { } assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52927.5-52927.29" + attribute \src "libresoc.v:52723.5-52723.29" switch \initial - attribute \src "libresoc.v:52927.9-52927.17" + attribute \src "libresoc.v:52723.9-52723.17" case 1'1 case end @@ -93575,14 +93371,14 @@ module \dec sync always update \ALU_inv_a $0\ALU_inv_a[0:0] end - attribute \src "libresoc.v:52960.3-52993.6" - process $proc$libresoc.v:52960$3446 + attribute \src "libresoc.v:52756.3-52789.6" + process $proc$libresoc.v:52756$3446 assign { } { } assign { } { } assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:52961.5-52961.29" + attribute \src "libresoc.v:52757.5-52757.29" switch \initial - attribute \src "libresoc.v:52961.9-52961.17" + attribute \src "libresoc.v:52757.9-52757.17" case 1'1 case end @@ -93630,14 +93426,14 @@ module \dec sync always update \ALU_inv_out $0\ALU_inv_out[0:0] end - attribute \src "libresoc.v:52994.3-53027.6" - process $proc$libresoc.v:52994$3447 + attribute \src "libresoc.v:52790.3-52823.6" + process $proc$libresoc.v:52790$3447 assign { } { } assign { } { } assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:52995.5-52995.29" + attribute \src "libresoc.v:52791.5-52791.29" switch \initial - attribute \src "libresoc.v:52995.9-52995.17" + attribute \src "libresoc.v:52791.9-52791.17" case 1'1 case end @@ -93685,14 +93481,14 @@ module \dec sync always update \ALU_cry_out $0\ALU_cry_out[0:0] end - attribute \src "libresoc.v:53028.3-53061.6" - process $proc$libresoc.v:53028$3448 + attribute \src "libresoc.v:52824.3-52857.6" + process $proc$libresoc.v:52824$3448 assign { } { } assign { } { } assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53029.5-53029.29" + attribute \src "libresoc.v:52825.5-52825.29" switch \initial - attribute \src "libresoc.v:53029.9-53029.17" + attribute \src "libresoc.v:52825.9-52825.17" case 1'1 case end @@ -93740,14 +93536,14 @@ module \dec sync always update \ALU_is_32b $0\ALU_is_32b[0:0] end - attribute \src "libresoc.v:53062.3-53095.6" - process $proc$libresoc.v:53062$3449 + attribute \src "libresoc.v:52858.3-52891.6" + process $proc$libresoc.v:52858$3449 assign { } { } assign { } { } assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] - attribute \src "libresoc.v:53063.5-53063.29" + attribute \src "libresoc.v:52859.5-52859.29" switch \initial - attribute \src "libresoc.v:53063.9-53063.17" + attribute \src "libresoc.v:52859.9-52859.17" case 1'1 case end @@ -93795,14 +93591,14 @@ module \dec sync always update \ALU_sgn $0\ALU_sgn[0:0] end - attribute \src "libresoc.v:53096.3-53129.6" - process $proc$libresoc.v:53096$3450 + attribute \src "libresoc.v:52892.3-52925.6" + process $proc$libresoc.v:52892$3450 assign { } { } assign { } { } assign $0\ALU_function_unit[13:0] $1\ALU_function_unit[13:0] - attribute \src "libresoc.v:53097.5-53097.29" + attribute \src "libresoc.v:52893.5-52893.29" switch \initial - attribute \src "libresoc.v:53097.9-53097.17" + attribute \src "libresoc.v:52893.9-52893.17" case 1'1 case end @@ -93850,14 +93646,14 @@ module \dec sync always update \ALU_function_unit $0\ALU_function_unit[13:0] end - attribute \src "libresoc.v:53130.3-53163.6" - process $proc$libresoc.v:53130$3451 + attribute \src "libresoc.v:52926.3-52959.6" + process $proc$libresoc.v:52926$3451 assign { } { } assign { } { } assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:53131.5-53131.29" + attribute \src "libresoc.v:52927.5-52927.29" switch \initial - attribute \src "libresoc.v:53131.9-53131.17" + attribute \src "libresoc.v:52927.9-52927.17" case 1'1 case end @@ -93905,14 +93701,14 @@ module \dec sync always update \ALU_internal_op $0\ALU_internal_op[6:0] end - attribute \src "libresoc.v:53164.3-53197.6" - process $proc$libresoc.v:53164$3452 + attribute \src "libresoc.v:52960.3-52993.6" + process $proc$libresoc.v:52960$3452 assign { } { } assign { } { } assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53165.5-53165.29" + attribute \src "libresoc.v:52961.5-52961.29" switch \initial - attribute \src "libresoc.v:53165.9-53165.17" + attribute \src "libresoc.v:52961.9-52961.17" case 1'1 case end @@ -93960,14 +93756,14 @@ module \dec sync always update \ALU_in1_sel $0\ALU_in1_sel[2:0] end - attribute \src "libresoc.v:53198.3-53231.6" - process $proc$libresoc.v:53198$3453 + attribute \src "libresoc.v:52994.3-53027.6" + process $proc$libresoc.v:52994$3453 assign { } { } assign { } { } assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53199.5-53199.29" + attribute \src "libresoc.v:52995.5-52995.29" switch \initial - attribute \src "libresoc.v:53199.9-53199.17" + attribute \src "libresoc.v:52995.9-52995.17" case 1'1 case end @@ -94015,14 +93811,14 @@ module \dec sync always update \ALU_in2_sel $0\ALU_in2_sel[3:0] end - attribute \src "libresoc.v:53232.3-53265.6" - process $proc$libresoc.v:53232$3454 + attribute \src "libresoc.v:53028.3-53061.6" + process $proc$libresoc.v:53028$3454 assign { } { } assign { } { } assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53233.5-53233.29" + attribute \src "libresoc.v:53029.5-53029.29" switch \initial - attribute \src "libresoc.v:53233.9-53233.17" + attribute \src "libresoc.v:53029.9-53029.17" case 1'1 case end @@ -94070,14 +93866,14 @@ module \dec sync always update \ALU_cr_in $0\ALU_cr_in[2:0] end - attribute \src "libresoc.v:53266.3-53299.6" - process $proc$libresoc.v:53266$3455 + attribute \src "libresoc.v:53062.3-53095.6" + process $proc$libresoc.v:53062$3455 assign { } { } assign { } { } assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:53267.5-53267.29" + attribute \src "libresoc.v:53063.5-53063.29" switch \initial - attribute \src "libresoc.v:53267.9-53267.17" + attribute \src "libresoc.v:53063.9-53063.17" case 1'1 case end @@ -94125,14 +93921,14 @@ module \dec sync always update \ALU_cr_out $0\ALU_cr_out[2:0] end - attribute \src "libresoc.v:53300.3-53333.6" - process $proc$libresoc.v:53300$3456 + attribute \src "libresoc.v:53096.3-53129.6" + process $proc$libresoc.v:53096$3456 assign { } { } assign { } { } assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:53301.5-53301.29" + attribute \src "libresoc.v:53097.5-53097.29" switch \initial - attribute \src "libresoc.v:53301.9-53301.17" + attribute \src "libresoc.v:53097.9-53097.17" case 1'1 case end @@ -94180,7 +93976,7 @@ module \dec sync always update \ALU_ldst_len $0\ALU_ldst_len[3:0] end - connect \$1 $ternary$libresoc.v:52823$3442_Y + connect \$1 $ternary$libresoc.v:52619$3442_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -94519,35 +94315,35 @@ module \dec connect \ALU_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:53675.1-55140.10" +attribute \src "libresoc.v:53471.1-54936.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" attribute \generator "nMigen" module \dec$138 - attribute \src "libresoc.v:54764.3-54776.6" + attribute \src "libresoc.v:54560.3-54572.6" wire width 3 $0\CR_cr_in[2:0] - attribute \src "libresoc.v:54777.3-54789.6" + attribute \src "libresoc.v:54573.3-54585.6" wire width 3 $0\CR_cr_out[2:0] - attribute \src "libresoc.v:54738.3-54750.6" + attribute \src "libresoc.v:54534.3-54546.6" wire width 14 $0\CR_function_unit[13:0] - attribute \src "libresoc.v:54751.3-54763.6" + attribute \src "libresoc.v:54547.3-54559.6" wire width 7 $0\CR_internal_op[6:0] - attribute \src "libresoc.v:54790.3-54802.6" + attribute \src "libresoc.v:54586.3-54598.6" wire width 2 $0\CR_rc_sel[1:0] - attribute \src "libresoc.v:53676.7-53676.20" + attribute \src "libresoc.v:53472.7-53472.20" wire $0\initial[0:0] - attribute \src "libresoc.v:54764.3-54776.6" + attribute \src "libresoc.v:54560.3-54572.6" wire width 3 $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54777.3-54789.6" + attribute \src "libresoc.v:54573.3-54585.6" wire width 3 $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54738.3-54750.6" + attribute \src "libresoc.v:54534.3-54546.6" wire width 14 $1\CR_function_unit[13:0] - attribute \src "libresoc.v:54751.3-54763.6" + attribute \src "libresoc.v:54547.3-54559.6" wire width 7 $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54790.3-54802.6" + attribute \src "libresoc.v:54586.3-54598.6" wire width 2 $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54721.17-54721.211" - wire width 32 $ternary$libresoc.v:54721$3458_Y + attribute \src "libresoc.v:54517.17-54517.211" + wire width 32 $ternary$libresoc.v:54517$3458_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -95582,7 +95378,7 @@ module \dec$138 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:53676.7-53676.15" + attribute \src "libresoc.v:53472.7-53472.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -95591,15 +95387,15 @@ module \dec$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 10 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:54721$3458 + cell $mux $ternary$libresoc.v:54517$3458 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:54721$3458_Y + connect \Y $ternary$libresoc.v:54517$3458_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:54722.12-54729.4" + attribute \src "libresoc.v:54518.12-54525.4" cell \CR_dec19 \CR_dec19 connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out @@ -95609,7 +95405,7 @@ module \dec$138 connect \opcode_in \CR_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:54730.12-54737.4" + attribute \src "libresoc.v:54526.12-54533.4" cell \CR_dec31 \CR_dec31 connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out @@ -95618,22 +95414,22 @@ module \dec$138 connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel connect \opcode_in \CR_dec31_opcode_in end - attribute \src "libresoc.v:53676.7-53676.20" - process $proc$libresoc.v:53676$3464 + attribute \src "libresoc.v:53472.7-53472.20" + process $proc$libresoc.v:53472$3464 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:54738.3-54750.6" - process $proc$libresoc.v:54738$3459 + attribute \src "libresoc.v:54534.3-54546.6" + process $proc$libresoc.v:54534$3459 assign { } { } assign { } { } assign $0\CR_function_unit[13:0] $1\CR_function_unit[13:0] - attribute \src "libresoc.v:54739.5-54739.29" + attribute \src "libresoc.v:54535.5-54535.29" switch \initial - attribute \src "libresoc.v:54739.9-54739.17" + attribute \src "libresoc.v:54535.9-54535.17" case 1'1 case end @@ -95653,14 +95449,14 @@ module \dec$138 sync always update \CR_function_unit $0\CR_function_unit[13:0] end - attribute \src "libresoc.v:54751.3-54763.6" - process $proc$libresoc.v:54751$3460 + attribute \src "libresoc.v:54547.3-54559.6" + process $proc$libresoc.v:54547$3460 assign { } { } assign { } { } assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54752.5-54752.29" + attribute \src "libresoc.v:54548.5-54548.29" switch \initial - attribute \src "libresoc.v:54752.9-54752.17" + attribute \src "libresoc.v:54548.9-54548.17" case 1'1 case end @@ -95680,14 +95476,14 @@ module \dec$138 sync always update \CR_internal_op $0\CR_internal_op[6:0] end - attribute \src "libresoc.v:54764.3-54776.6" - process $proc$libresoc.v:54764$3461 + attribute \src "libresoc.v:54560.3-54572.6" + process $proc$libresoc.v:54560$3461 assign { } { } assign { } { } assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54765.5-54765.29" + attribute \src "libresoc.v:54561.5-54561.29" switch \initial - attribute \src "libresoc.v:54765.9-54765.17" + attribute \src "libresoc.v:54561.9-54561.17" case 1'1 case end @@ -95707,14 +95503,14 @@ module \dec$138 sync always update \CR_cr_in $0\CR_cr_in[2:0] end - attribute \src "libresoc.v:54777.3-54789.6" - process $proc$libresoc.v:54777$3462 + attribute \src "libresoc.v:54573.3-54585.6" + process $proc$libresoc.v:54573$3462 assign { } { } assign { } { } assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54778.5-54778.29" + attribute \src "libresoc.v:54574.5-54574.29" switch \initial - attribute \src "libresoc.v:54778.9-54778.17" + attribute \src "libresoc.v:54574.9-54574.17" case 1'1 case end @@ -95734,14 +95530,14 @@ module \dec$138 sync always update \CR_cr_out $0\CR_cr_out[2:0] end - attribute \src "libresoc.v:54790.3-54802.6" - process $proc$libresoc.v:54790$3463 + attribute \src "libresoc.v:54586.3-54598.6" + process $proc$libresoc.v:54586$3463 assign { } { } assign { } { } assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54791.5-54791.29" + attribute \src "libresoc.v:54587.5-54587.29" switch \initial - attribute \src "libresoc.v:54791.9-54791.17" + attribute \src "libresoc.v:54587.9-54587.17" case 1'1 case end @@ -95761,7 +95557,7 @@ module \dec$138 sync always update \CR_rc_sel $0\CR_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:54721$3458_Y + connect \$1 $ternary$libresoc.v:54517$3458_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -96100,47 +95896,47 @@ module \dec$138 connect \CR_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:55144.1-56589.10" +attribute \src "libresoc.v:54940.1-56385.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" attribute \generator "nMigen" module \dec$141 - attribute \src "libresoc.v:56173.3-56188.6" + attribute \src "libresoc.v:55969.3-55984.6" wire width 3 $0\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56189.3-56204.6" + attribute \src "libresoc.v:55985.3-56000.6" wire width 3 $0\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56125.3-56140.6" + attribute \src "libresoc.v:55921.3-55936.6" wire width 14 $0\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56157.3-56172.6" + attribute \src "libresoc.v:55953.3-55968.6" wire width 4 $0\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56141.3-56156.6" + attribute \src "libresoc.v:55937.3-55952.6" wire width 7 $0\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56221.3-56236.6" + attribute \src "libresoc.v:56017.3-56032.6" wire $0\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56237.3-56252.6" + attribute \src "libresoc.v:56033.3-56048.6" wire $0\BRANCH_lk[0:0] - attribute \src "libresoc.v:56205.3-56220.6" + attribute \src "libresoc.v:56001.3-56016.6" wire width 2 $0\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:55145.7-55145.20" + attribute \src "libresoc.v:54941.7-54941.20" wire $0\initial[0:0] - attribute \src "libresoc.v:56173.3-56188.6" + attribute \src "libresoc.v:55969.3-55984.6" wire width 3 $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56189.3-56204.6" + attribute \src "libresoc.v:55985.3-56000.6" wire width 3 $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56125.3-56140.6" + attribute \src "libresoc.v:55921.3-55936.6" wire width 14 $1\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56157.3-56172.6" + attribute \src "libresoc.v:55953.3-55968.6" wire width 4 $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56141.3-56156.6" + attribute \src "libresoc.v:55937.3-55952.6" wire width 7 $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56221.3-56236.6" + attribute \src "libresoc.v:56017.3-56032.6" wire $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56237.3-56252.6" + attribute \src "libresoc.v:56033.3-56048.6" wire $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56205.3-56220.6" + attribute \src "libresoc.v:56001.3-56016.6" wire width 2 $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56113.17-56113.211" - wire width 32 $ternary$libresoc.v:56113$3465_Y + attribute \src "libresoc.v:55909.17-55909.211" + wire width 32 $ternary$libresoc.v:55909$3465_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -97095,7 +96891,7 @@ module \dec$141 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:55145.7-55145.15" + attribute \src "libresoc.v:54941.7-54941.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -97104,15 +96900,15 @@ module \dec$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:56113$3465 + cell $mux $ternary$libresoc.v:55909$3465 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:56113$3465_Y + connect \Y $ternary$libresoc.v:55909$3465_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:56114.16-56124.4" + attribute \src "libresoc.v:55910.16-55920.4" cell \BRANCH_dec19 \BRANCH_dec19 connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out @@ -97124,22 +96920,22 @@ module \dec$141 connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel connect \opcode_in \BRANCH_dec19_opcode_in end - attribute \src "libresoc.v:55145.7-55145.20" - process $proc$libresoc.v:55145$3474 + attribute \src "libresoc.v:54941.7-54941.20" + process $proc$libresoc.v:54941$3474 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:56125.3-56140.6" - process $proc$libresoc.v:56125$3466 + attribute \src "libresoc.v:55921.3-55936.6" + process $proc$libresoc.v:55921$3466 assign { } { } assign { } { } assign $0\BRANCH_function_unit[13:0] $1\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56126.5-56126.29" + attribute \src "libresoc.v:55922.5-55922.29" switch \initial - attribute \src "libresoc.v:56126.9-56126.17" + attribute \src "libresoc.v:55922.9-55922.17" case 1'1 case end @@ -97163,14 +96959,14 @@ module \dec$141 sync always update \BRANCH_function_unit $0\BRANCH_function_unit[13:0] end - attribute \src "libresoc.v:56141.3-56156.6" - process $proc$libresoc.v:56141$3467 + attribute \src "libresoc.v:55937.3-55952.6" + process $proc$libresoc.v:55937$3467 assign { } { } assign { } { } assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56142.5-56142.29" + attribute \src "libresoc.v:55938.5-55938.29" switch \initial - attribute \src "libresoc.v:56142.9-56142.17" + attribute \src "libresoc.v:55938.9-55938.17" case 1'1 case end @@ -97194,14 +96990,14 @@ module \dec$141 sync always update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] end - attribute \src "libresoc.v:56157.3-56172.6" - process $proc$libresoc.v:56157$3468 + attribute \src "libresoc.v:55953.3-55968.6" + process $proc$libresoc.v:55953$3468 assign { } { } assign { } { } assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56158.5-56158.29" + attribute \src "libresoc.v:55954.5-55954.29" switch \initial - attribute \src "libresoc.v:56158.9-56158.17" + attribute \src "libresoc.v:55954.9-55954.17" case 1'1 case end @@ -97225,14 +97021,14 @@ module \dec$141 sync always update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] end - attribute \src "libresoc.v:56173.3-56188.6" - process $proc$libresoc.v:56173$3469 + attribute \src "libresoc.v:55969.3-55984.6" + process $proc$libresoc.v:55969$3469 assign { } { } assign { } { } assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56174.5-56174.29" + attribute \src "libresoc.v:55970.5-55970.29" switch \initial - attribute \src "libresoc.v:56174.9-56174.17" + attribute \src "libresoc.v:55970.9-55970.17" case 1'1 case end @@ -97256,14 +97052,14 @@ module \dec$141 sync always update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] end - attribute \src "libresoc.v:56189.3-56204.6" - process $proc$libresoc.v:56189$3470 + attribute \src "libresoc.v:55985.3-56000.6" + process $proc$libresoc.v:55985$3470 assign { } { } assign { } { } assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56190.5-56190.29" + attribute \src "libresoc.v:55986.5-55986.29" switch \initial - attribute \src "libresoc.v:56190.9-56190.17" + attribute \src "libresoc.v:55986.9-55986.17" case 1'1 case end @@ -97287,14 +97083,14 @@ module \dec$141 sync always update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] end - attribute \src "libresoc.v:56205.3-56220.6" - process $proc$libresoc.v:56205$3471 + attribute \src "libresoc.v:56001.3-56016.6" + process $proc$libresoc.v:56001$3471 assign { } { } assign { } { } assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56206.5-56206.29" + attribute \src "libresoc.v:56002.5-56002.29" switch \initial - attribute \src "libresoc.v:56206.9-56206.17" + attribute \src "libresoc.v:56002.9-56002.17" case 1'1 case end @@ -97318,14 +97114,14 @@ module \dec$141 sync always update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] end - attribute \src "libresoc.v:56221.3-56236.6" - process $proc$libresoc.v:56221$3472 + attribute \src "libresoc.v:56017.3-56032.6" + process $proc$libresoc.v:56017$3472 assign { } { } assign { } { } assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56222.5-56222.29" + attribute \src "libresoc.v:56018.5-56018.29" switch \initial - attribute \src "libresoc.v:56222.9-56222.17" + attribute \src "libresoc.v:56018.9-56018.17" case 1'1 case end @@ -97349,14 +97145,14 @@ module \dec$141 sync always update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] end - attribute \src "libresoc.v:56237.3-56252.6" - process $proc$libresoc.v:56237$3473 + attribute \src "libresoc.v:56033.3-56048.6" + process $proc$libresoc.v:56033$3473 assign { } { } assign { } { } assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56238.5-56238.29" + attribute \src "libresoc.v:56034.5-56034.29" switch \initial - attribute \src "libresoc.v:56238.9-56238.17" + attribute \src "libresoc.v:56034.9-56034.17" case 1'1 case end @@ -97380,7 +97176,7 @@ module \dec$141 sync always update \BRANCH_lk $0\BRANCH_lk[0:0] end - connect \$1 $ternary$libresoc.v:56113$3465_Y + connect \$1 $ternary$libresoc.v:55909$3465_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -97718,71 +97514,71 @@ module \dec$141 connect \BRANCH_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:56593.1-58370.10" +attribute \src "libresoc.v:56389.1-58166.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" attribute \generator "nMigen" module \dec$145 - attribute \src "libresoc.v:57922.3-57949.6" + attribute \src "libresoc.v:57718.3-57745.6" wire width 3 $0\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57950.3-57977.6" + attribute \src "libresoc.v:57746.3-57773.6" wire width 3 $0\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57642.3-57669.6" + attribute \src "libresoc.v:57438.3-57465.6" wire width 2 $0\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57726.3-57753.6" + attribute \src "libresoc.v:57522.3-57549.6" wire $0\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57810.3-57837.6" + attribute \src "libresoc.v:57606.3-57633.6" wire width 14 $0\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57866.3-57893.6" + attribute \src "libresoc.v:57662.3-57689.6" wire width 3 $0\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57894.3-57921.6" + attribute \src "libresoc.v:57690.3-57717.6" wire width 4 $0\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57838.3-57865.6" + attribute \src "libresoc.v:57634.3-57661.6" wire width 7 $0\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57670.3-57697.6" + attribute \src "libresoc.v:57466.3-57493.6" wire $0\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57698.3-57725.6" + attribute \src "libresoc.v:57494.3-57521.6" wire $0\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57754.3-57781.6" + attribute \src "libresoc.v:57550.3-57577.6" wire $0\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57978.3-58005.6" + attribute \src "libresoc.v:57774.3-57801.6" wire width 4 $0\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58006.3-58033.6" + attribute \src "libresoc.v:57802.3-57829.6" wire width 2 $0\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57782.3-57809.6" + attribute \src "libresoc.v:57578.3-57605.6" wire $0\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:56594.7-56594.20" + attribute \src "libresoc.v:56390.7-56390.20" wire $0\initial[0:0] - attribute \src "libresoc.v:57922.3-57949.6" + attribute \src "libresoc.v:57718.3-57745.6" wire width 3 $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57950.3-57977.6" + attribute \src "libresoc.v:57746.3-57773.6" wire width 3 $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57642.3-57669.6" + attribute \src "libresoc.v:57438.3-57465.6" wire width 2 $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57726.3-57753.6" + attribute \src "libresoc.v:57522.3-57549.6" wire $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57810.3-57837.6" + attribute \src "libresoc.v:57606.3-57633.6" wire width 14 $1\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57866.3-57893.6" + attribute \src "libresoc.v:57662.3-57689.6" wire width 3 $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57894.3-57921.6" + attribute \src "libresoc.v:57690.3-57717.6" wire width 4 $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57838.3-57865.6" + attribute \src "libresoc.v:57634.3-57661.6" wire width 7 $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57670.3-57697.6" + attribute \src "libresoc.v:57466.3-57493.6" wire $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57698.3-57725.6" + attribute \src "libresoc.v:57494.3-57521.6" wire $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57754.3-57781.6" + attribute \src "libresoc.v:57550.3-57577.6" wire $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57978.3-58005.6" + attribute \src "libresoc.v:57774.3-57801.6" wire width 4 $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58006.3-58033.6" + attribute \src "libresoc.v:57802.3-57829.6" wire width 2 $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57782.3-57809.6" + attribute \src "libresoc.v:57578.3-57605.6" wire $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57624.17-57624.211" - wire width 32 $ternary$libresoc.v:57624$3475_Y + attribute \src "libresoc.v:57420.17-57420.211" + wire width 32 $ternary$libresoc.v:57420$3475_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -98793,7 +98589,7 @@ module \dec$145 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:56594.7-56594.15" + attribute \src "libresoc.v:56390.7-56390.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -98802,15 +98598,15 @@ module \dec$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:57624$3475 + cell $mux $ternary$libresoc.v:57420$3475 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:57624$3475_Y + connect \Y $ternary$libresoc.v:57420$3475_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:57625.17-57641.4" + attribute \src "libresoc.v:57421.17-57437.4" cell \LOGICAL_dec31 \LOGICAL_dec31 connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out @@ -98828,22 +98624,22 @@ module \dec$145 connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn connect \opcode_in \LOGICAL_dec31_opcode_in end - attribute \src "libresoc.v:56594.7-56594.20" - process $proc$libresoc.v:56594$3490 + attribute \src "libresoc.v:56390.7-56390.20" + process $proc$libresoc.v:56390$3490 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:57642.3-57669.6" - process $proc$libresoc.v:57642$3476 + attribute \src "libresoc.v:57438.3-57465.6" + process $proc$libresoc.v:57438$3476 assign { } { } assign { } { } assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57643.5-57643.29" + attribute \src "libresoc.v:57439.5-57439.29" switch \initial - attribute \src "libresoc.v:57643.9-57643.17" + attribute \src "libresoc.v:57439.9-57439.17" case 1'1 case end @@ -98883,14 +98679,14 @@ module \dec$145 sync always update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] end - attribute \src "libresoc.v:57670.3-57697.6" - process $proc$libresoc.v:57670$3477 + attribute \src "libresoc.v:57466.3-57493.6" + process $proc$libresoc.v:57466$3477 assign { } { } assign { } { } assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57671.5-57671.29" + attribute \src "libresoc.v:57467.5-57467.29" switch \initial - attribute \src "libresoc.v:57671.9-57671.17" + attribute \src "libresoc.v:57467.9-57467.17" case 1'1 case end @@ -98930,14 +98726,14 @@ module \dec$145 sync always update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] end - attribute \src "libresoc.v:57698.3-57725.6" - process $proc$libresoc.v:57698$3478 + attribute \src "libresoc.v:57494.3-57521.6" + process $proc$libresoc.v:57494$3478 assign { } { } assign { } { } assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57699.5-57699.29" + attribute \src "libresoc.v:57495.5-57495.29" switch \initial - attribute \src "libresoc.v:57699.9-57699.17" + attribute \src "libresoc.v:57495.9-57495.17" case 1'1 case end @@ -98977,14 +98773,14 @@ module \dec$145 sync always update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] end - attribute \src "libresoc.v:57726.3-57753.6" - process $proc$libresoc.v:57726$3479 + attribute \src "libresoc.v:57522.3-57549.6" + process $proc$libresoc.v:57522$3479 assign { } { } assign { } { } assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57727.5-57727.29" + attribute \src "libresoc.v:57523.5-57523.29" switch \initial - attribute \src "libresoc.v:57727.9-57727.17" + attribute \src "libresoc.v:57523.9-57523.17" case 1'1 case end @@ -99024,14 +98820,14 @@ module \dec$145 sync always update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] end - attribute \src "libresoc.v:57754.3-57781.6" - process $proc$libresoc.v:57754$3480 + attribute \src "libresoc.v:57550.3-57577.6" + process $proc$libresoc.v:57550$3480 assign { } { } assign { } { } assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57755.5-57755.29" + attribute \src "libresoc.v:57551.5-57551.29" switch \initial - attribute \src "libresoc.v:57755.9-57755.17" + attribute \src "libresoc.v:57551.9-57551.17" case 1'1 case end @@ -99071,14 +98867,14 @@ module \dec$145 sync always update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] end - attribute \src "libresoc.v:57782.3-57809.6" - process $proc$libresoc.v:57782$3481 + attribute \src "libresoc.v:57578.3-57605.6" + process $proc$libresoc.v:57578$3481 assign { } { } assign { } { } assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57783.5-57783.29" + attribute \src "libresoc.v:57579.5-57579.29" switch \initial - attribute \src "libresoc.v:57783.9-57783.17" + attribute \src "libresoc.v:57579.9-57579.17" case 1'1 case end @@ -99118,14 +98914,14 @@ module \dec$145 sync always update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] end - attribute \src "libresoc.v:57810.3-57837.6" - process $proc$libresoc.v:57810$3482 + attribute \src "libresoc.v:57606.3-57633.6" + process $proc$libresoc.v:57606$3482 assign { } { } assign { } { } assign $0\LOGICAL_function_unit[13:0] $1\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57811.5-57811.29" + attribute \src "libresoc.v:57607.5-57607.29" switch \initial - attribute \src "libresoc.v:57811.9-57811.17" + attribute \src "libresoc.v:57607.9-57607.17" case 1'1 case end @@ -99165,14 +98961,14 @@ module \dec$145 sync always update \LOGICAL_function_unit $0\LOGICAL_function_unit[13:0] end - attribute \src "libresoc.v:57838.3-57865.6" - process $proc$libresoc.v:57838$3483 + attribute \src "libresoc.v:57634.3-57661.6" + process $proc$libresoc.v:57634$3483 assign { } { } assign { } { } assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57839.5-57839.29" + attribute \src "libresoc.v:57635.5-57635.29" switch \initial - attribute \src "libresoc.v:57839.9-57839.17" + attribute \src "libresoc.v:57635.9-57635.17" case 1'1 case end @@ -99212,14 +99008,14 @@ module \dec$145 sync always update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] end - attribute \src "libresoc.v:57866.3-57893.6" - process $proc$libresoc.v:57866$3484 + attribute \src "libresoc.v:57662.3-57689.6" + process $proc$libresoc.v:57662$3484 assign { } { } assign { } { } assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57867.5-57867.29" + attribute \src "libresoc.v:57663.5-57663.29" switch \initial - attribute \src "libresoc.v:57867.9-57867.17" + attribute \src "libresoc.v:57663.9-57663.17" case 1'1 case end @@ -99259,14 +99055,14 @@ module \dec$145 sync always update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] end - attribute \src "libresoc.v:57894.3-57921.6" - process $proc$libresoc.v:57894$3485 + attribute \src "libresoc.v:57690.3-57717.6" + process $proc$libresoc.v:57690$3485 assign { } { } assign { } { } assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57895.5-57895.29" + attribute \src "libresoc.v:57691.5-57691.29" switch \initial - attribute \src "libresoc.v:57895.9-57895.17" + attribute \src "libresoc.v:57691.9-57691.17" case 1'1 case end @@ -99306,14 +99102,14 @@ module \dec$145 sync always update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] end - attribute \src "libresoc.v:57922.3-57949.6" - process $proc$libresoc.v:57922$3486 + attribute \src "libresoc.v:57718.3-57745.6" + process $proc$libresoc.v:57718$3486 assign { } { } assign { } { } assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57923.5-57923.29" + attribute \src "libresoc.v:57719.5-57719.29" switch \initial - attribute \src "libresoc.v:57923.9-57923.17" + attribute \src "libresoc.v:57719.9-57719.17" case 1'1 case end @@ -99353,14 +99149,14 @@ module \dec$145 sync always update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] end - attribute \src "libresoc.v:57950.3-57977.6" - process $proc$libresoc.v:57950$3487 + attribute \src "libresoc.v:57746.3-57773.6" + process $proc$libresoc.v:57746$3487 assign { } { } assign { } { } assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57951.5-57951.29" + attribute \src "libresoc.v:57747.5-57747.29" switch \initial - attribute \src "libresoc.v:57951.9-57951.17" + attribute \src "libresoc.v:57747.9-57747.17" case 1'1 case end @@ -99400,14 +99196,14 @@ module \dec$145 sync always update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] end - attribute \src "libresoc.v:57978.3-58005.6" - process $proc$libresoc.v:57978$3488 + attribute \src "libresoc.v:57774.3-57801.6" + process $proc$libresoc.v:57774$3488 assign { } { } assign { } { } assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:57979.5-57979.29" + attribute \src "libresoc.v:57775.5-57775.29" switch \initial - attribute \src "libresoc.v:57979.9-57979.17" + attribute \src "libresoc.v:57775.9-57775.17" case 1'1 case end @@ -99447,14 +99243,14 @@ module \dec$145 sync always update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] end - attribute \src "libresoc.v:58006.3-58033.6" - process $proc$libresoc.v:58006$3489 + attribute \src "libresoc.v:57802.3-57829.6" + process $proc$libresoc.v:57802$3489 assign { } { } assign { } { } assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:58007.5-58007.29" + attribute \src "libresoc.v:57803.5-57803.29" switch \initial - attribute \src "libresoc.v:58007.9-58007.17" + attribute \src "libresoc.v:57803.9-57803.17" case 1'1 case end @@ -99494,7 +99290,7 @@ module \dec$145 sync always update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:57624$3475_Y + connect \$1 $ternary$libresoc.v:57420$3475_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -99832,39 +99628,39 @@ module \dec$145 connect \LOGICAL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:58374.1-59709.10" +attribute \src "libresoc.v:58170.1-59505.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" attribute \generator "nMigen" module \dec$150 - attribute \src "libresoc.v:59333.3-59342.6" + attribute \src "libresoc.v:59129.3-59138.6" wire width 3 $0\SPR_cr_in[2:0] - attribute \src "libresoc.v:59343.3-59352.6" + attribute \src "libresoc.v:59139.3-59148.6" wire width 3 $0\SPR_cr_out[2:0] - attribute \src "libresoc.v:59313.3-59322.6" + attribute \src "libresoc.v:59109.3-59118.6" wire width 14 $0\SPR_function_unit[13:0] - attribute \src "libresoc.v:59323.3-59332.6" + attribute \src "libresoc.v:59119.3-59128.6" wire width 7 $0\SPR_internal_op[6:0] - attribute \src "libresoc.v:59363.3-59372.6" + attribute \src "libresoc.v:59159.3-59168.6" wire $0\SPR_is_32b[0:0] - attribute \src "libresoc.v:59353.3-59362.6" + attribute \src "libresoc.v:59149.3-59158.6" wire width 2 $0\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58375.7-58375.20" + attribute \src "libresoc.v:58171.7-58171.20" wire $0\initial[0:0] - attribute \src "libresoc.v:59333.3-59342.6" + attribute \src "libresoc.v:59129.3-59138.6" wire width 3 $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59343.3-59352.6" + attribute \src "libresoc.v:59139.3-59148.6" wire width 3 $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59313.3-59322.6" + attribute \src "libresoc.v:59109.3-59118.6" wire width 14 $1\SPR_function_unit[13:0] - attribute \src "libresoc.v:59323.3-59332.6" + attribute \src "libresoc.v:59119.3-59128.6" wire width 7 $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59363.3-59372.6" + attribute \src "libresoc.v:59159.3-59168.6" wire $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59353.3-59362.6" + attribute \src "libresoc.v:59149.3-59158.6" wire width 2 $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59303.17-59303.211" - wire width 32 $ternary$libresoc.v:59303$3491_Y + attribute \src "libresoc.v:59099.17-59099.211" + wire width 32 $ternary$libresoc.v:59099$3491_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -100781,7 +100577,7 @@ module \dec$150 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:58375.7-58375.15" + attribute \src "libresoc.v:58171.7-58171.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -100790,15 +100586,15 @@ module \dec$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 11 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:59303$3491 + cell $mux $ternary$libresoc.v:59099$3491 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:59303$3491_Y + connect \Y $ternary$libresoc.v:59099$3491_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:59304.13-59312.4" + attribute \src "libresoc.v:59100.13-59108.4" cell \SPR_dec31 \SPR_dec31 connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out @@ -100808,22 +100604,22 @@ module \dec$150 connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel connect \opcode_in \SPR_dec31_opcode_in end - attribute \src "libresoc.v:58375.7-58375.20" - process $proc$libresoc.v:58375$3498 + attribute \src "libresoc.v:58171.7-58171.20" + process $proc$libresoc.v:58171$3498 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:59313.3-59322.6" - process $proc$libresoc.v:59313$3492 + attribute \src "libresoc.v:59109.3-59118.6" + process $proc$libresoc.v:59109$3492 assign { } { } assign { } { } assign $0\SPR_function_unit[13:0] $1\SPR_function_unit[13:0] - attribute \src "libresoc.v:59314.5-59314.29" + attribute \src "libresoc.v:59110.5-59110.29" switch \initial - attribute \src "libresoc.v:59314.9-59314.17" + attribute \src "libresoc.v:59110.9-59110.17" case 1'1 case end @@ -100839,14 +100635,14 @@ module \dec$150 sync always update \SPR_function_unit $0\SPR_function_unit[13:0] end - attribute \src "libresoc.v:59323.3-59332.6" - process $proc$libresoc.v:59323$3493 + attribute \src "libresoc.v:59119.3-59128.6" + process $proc$libresoc.v:59119$3493 assign { } { } assign { } { } assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59324.5-59324.29" + attribute \src "libresoc.v:59120.5-59120.29" switch \initial - attribute \src "libresoc.v:59324.9-59324.17" + attribute \src "libresoc.v:59120.9-59120.17" case 1'1 case end @@ -100862,14 +100658,14 @@ module \dec$150 sync always update \SPR_internal_op $0\SPR_internal_op[6:0] end - attribute \src "libresoc.v:59333.3-59342.6" - process $proc$libresoc.v:59333$3494 + attribute \src "libresoc.v:59129.3-59138.6" + process $proc$libresoc.v:59129$3494 assign { } { } assign { } { } assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59334.5-59334.29" + attribute \src "libresoc.v:59130.5-59130.29" switch \initial - attribute \src "libresoc.v:59334.9-59334.17" + attribute \src "libresoc.v:59130.9-59130.17" case 1'1 case end @@ -100885,14 +100681,14 @@ module \dec$150 sync always update \SPR_cr_in $0\SPR_cr_in[2:0] end - attribute \src "libresoc.v:59343.3-59352.6" - process $proc$libresoc.v:59343$3495 + attribute \src "libresoc.v:59139.3-59148.6" + process $proc$libresoc.v:59139$3495 assign { } { } assign { } { } assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59344.5-59344.29" + attribute \src "libresoc.v:59140.5-59140.29" switch \initial - attribute \src "libresoc.v:59344.9-59344.17" + attribute \src "libresoc.v:59140.9-59140.17" case 1'1 case end @@ -100908,14 +100704,14 @@ module \dec$150 sync always update \SPR_cr_out $0\SPR_cr_out[2:0] end - attribute \src "libresoc.v:59353.3-59362.6" - process $proc$libresoc.v:59353$3496 + attribute \src "libresoc.v:59149.3-59158.6" + process $proc$libresoc.v:59149$3496 assign { } { } assign { } { } assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59354.5-59354.29" + attribute \src "libresoc.v:59150.5-59150.29" switch \initial - attribute \src "libresoc.v:59354.9-59354.17" + attribute \src "libresoc.v:59150.9-59150.17" case 1'1 case end @@ -100931,14 +100727,14 @@ module \dec$150 sync always update \SPR_rc_sel $0\SPR_rc_sel[1:0] end - attribute \src "libresoc.v:59363.3-59372.6" - process $proc$libresoc.v:59363$3497 + attribute \src "libresoc.v:59159.3-59168.6" + process $proc$libresoc.v:59159$3497 assign { } { } assign { } { } assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59364.5-59364.29" + attribute \src "libresoc.v:59160.5-59160.29" switch \initial - attribute \src "libresoc.v:59364.9-59364.17" + attribute \src "libresoc.v:59160.9-59160.17" case 1'1 case end @@ -100954,7 +100750,7 @@ module \dec$150 sync always update \SPR_is_32b $0\SPR_is_32b[0:0] end - connect \$1 $ternary$libresoc.v:59303$3491_Y + connect \$1 $ternary$libresoc.v:59099$3491_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -101292,71 +101088,71 @@ module \dec$150 connect \SPR_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:59713.1-61238.10" +attribute \src "libresoc.v:59509.1-61034.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" attribute \generator "nMigen" module \dec$153 - attribute \src "libresoc.v:60862.3-60871.6" + attribute \src "libresoc.v:60658.3-60667.6" wire width 3 $0\DIV_cr_in[2:0] - attribute \src "libresoc.v:60872.3-60881.6" + attribute \src "libresoc.v:60668.3-60677.6" wire width 3 $0\DIV_cr_out[2:0] - attribute \src "libresoc.v:60762.3-60771.6" + attribute \src "libresoc.v:60558.3-60567.6" wire width 2 $0\DIV_cry_in[1:0] - attribute \src "libresoc.v:60792.3-60801.6" + attribute \src "libresoc.v:60588.3-60597.6" wire $0\DIV_cry_out[0:0] - attribute \src "libresoc.v:60822.3-60831.6" + attribute \src "libresoc.v:60618.3-60627.6" wire width 14 $0\DIV_function_unit[13:0] - attribute \src "libresoc.v:60842.3-60851.6" + attribute \src "libresoc.v:60638.3-60647.6" wire width 3 $0\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60852.3-60861.6" + attribute \src "libresoc.v:60648.3-60657.6" wire width 4 $0\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60832.3-60841.6" + attribute \src "libresoc.v:60628.3-60637.6" wire width 7 $0\DIV_internal_op[6:0] - attribute \src "libresoc.v:60772.3-60781.6" + attribute \src "libresoc.v:60568.3-60577.6" wire $0\DIV_inv_a[0:0] - attribute \src "libresoc.v:60782.3-60791.6" + attribute \src "libresoc.v:60578.3-60587.6" wire $0\DIV_inv_out[0:0] - attribute \src "libresoc.v:60802.3-60811.6" + attribute \src "libresoc.v:60598.3-60607.6" wire $0\DIV_is_32b[0:0] - attribute \src "libresoc.v:60882.3-60891.6" + attribute \src "libresoc.v:60678.3-60687.6" wire width 4 $0\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60892.3-60901.6" + attribute \src "libresoc.v:60688.3-60697.6" wire width 2 $0\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60812.3-60821.6" + attribute \src "libresoc.v:60608.3-60617.6" wire $0\DIV_sgn[0:0] - attribute \src "libresoc.v:59714.7-59714.20" + attribute \src "libresoc.v:59510.7-59510.20" wire $0\initial[0:0] - attribute \src "libresoc.v:60862.3-60871.6" + attribute \src "libresoc.v:60658.3-60667.6" wire width 3 $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60872.3-60881.6" + attribute \src "libresoc.v:60668.3-60677.6" wire width 3 $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60762.3-60771.6" + attribute \src "libresoc.v:60558.3-60567.6" wire width 2 $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60792.3-60801.6" + attribute \src "libresoc.v:60588.3-60597.6" wire $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60822.3-60831.6" + attribute \src "libresoc.v:60618.3-60627.6" wire width 14 $1\DIV_function_unit[13:0] - attribute \src "libresoc.v:60842.3-60851.6" + attribute \src "libresoc.v:60638.3-60647.6" wire width 3 $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60852.3-60861.6" + attribute \src "libresoc.v:60648.3-60657.6" wire width 4 $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60832.3-60841.6" + attribute \src "libresoc.v:60628.3-60637.6" wire width 7 $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60772.3-60781.6" + attribute \src "libresoc.v:60568.3-60577.6" wire $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60782.3-60791.6" + attribute \src "libresoc.v:60578.3-60587.6" wire $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60802.3-60811.6" + attribute \src "libresoc.v:60598.3-60607.6" wire $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60882.3-60891.6" + attribute \src "libresoc.v:60678.3-60687.6" wire width 4 $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60892.3-60901.6" + attribute \src "libresoc.v:60688.3-60697.6" wire width 2 $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60812.3-60821.6" + attribute \src "libresoc.v:60608.3-60617.6" wire $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60744.17-60744.211" - wire width 32 $ternary$libresoc.v:60744$3499_Y + attribute \src "libresoc.v:60540.17-60540.211" + wire width 32 $ternary$libresoc.v:60540$3499_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -102367,7 +102163,7 @@ module \dec$153 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:59714.7-59714.15" + attribute \src "libresoc.v:59510.7-59510.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -102376,15 +102172,15 @@ module \dec$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:60744$3499 + cell $mux $ternary$libresoc.v:60540$3499 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:60744$3499_Y + connect \Y $ternary$libresoc.v:60540$3499_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:60745.13-60761.4" + attribute \src "libresoc.v:60541.13-60557.4" cell \DIV_dec31 \DIV_dec31 connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out @@ -102402,22 +102198,22 @@ module \dec$153 connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn connect \opcode_in \DIV_dec31_opcode_in end - attribute \src "libresoc.v:59714.7-59714.20" - process $proc$libresoc.v:59714$3514 + attribute \src "libresoc.v:59510.7-59510.20" + process $proc$libresoc.v:59510$3514 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:60762.3-60771.6" - process $proc$libresoc.v:60762$3500 + attribute \src "libresoc.v:60558.3-60567.6" + process $proc$libresoc.v:60558$3500 assign { } { } assign { } { } assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60763.5-60763.29" + attribute \src "libresoc.v:60559.5-60559.29" switch \initial - attribute \src "libresoc.v:60763.9-60763.17" + attribute \src "libresoc.v:60559.9-60559.17" case 1'1 case end @@ -102433,14 +102229,14 @@ module \dec$153 sync always update \DIV_cry_in $0\DIV_cry_in[1:0] end - attribute \src "libresoc.v:60772.3-60781.6" - process $proc$libresoc.v:60772$3501 + attribute \src "libresoc.v:60568.3-60577.6" + process $proc$libresoc.v:60568$3501 assign { } { } assign { } { } assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60773.5-60773.29" + attribute \src "libresoc.v:60569.5-60569.29" switch \initial - attribute \src "libresoc.v:60773.9-60773.17" + attribute \src "libresoc.v:60569.9-60569.17" case 1'1 case end @@ -102456,14 +102252,14 @@ module \dec$153 sync always update \DIV_inv_a $0\DIV_inv_a[0:0] end - attribute \src "libresoc.v:60782.3-60791.6" - process $proc$libresoc.v:60782$3502 + attribute \src "libresoc.v:60578.3-60587.6" + process $proc$libresoc.v:60578$3502 assign { } { } assign { } { } assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60783.5-60783.29" + attribute \src "libresoc.v:60579.5-60579.29" switch \initial - attribute \src "libresoc.v:60783.9-60783.17" + attribute \src "libresoc.v:60579.9-60579.17" case 1'1 case end @@ -102479,14 +102275,14 @@ module \dec$153 sync always update \DIV_inv_out $0\DIV_inv_out[0:0] end - attribute \src "libresoc.v:60792.3-60801.6" - process $proc$libresoc.v:60792$3503 + attribute \src "libresoc.v:60588.3-60597.6" + process $proc$libresoc.v:60588$3503 assign { } { } assign { } { } assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60793.5-60793.29" + attribute \src "libresoc.v:60589.5-60589.29" switch \initial - attribute \src "libresoc.v:60793.9-60793.17" + attribute \src "libresoc.v:60589.9-60589.17" case 1'1 case end @@ -102502,14 +102298,14 @@ module \dec$153 sync always update \DIV_cry_out $0\DIV_cry_out[0:0] end - attribute \src "libresoc.v:60802.3-60811.6" - process $proc$libresoc.v:60802$3504 + attribute \src "libresoc.v:60598.3-60607.6" + process $proc$libresoc.v:60598$3504 assign { } { } assign { } { } assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60803.5-60803.29" + attribute \src "libresoc.v:60599.5-60599.29" switch \initial - attribute \src "libresoc.v:60803.9-60803.17" + attribute \src "libresoc.v:60599.9-60599.17" case 1'1 case end @@ -102525,14 +102321,14 @@ module \dec$153 sync always update \DIV_is_32b $0\DIV_is_32b[0:0] end - attribute \src "libresoc.v:60812.3-60821.6" - process $proc$libresoc.v:60812$3505 + attribute \src "libresoc.v:60608.3-60617.6" + process $proc$libresoc.v:60608$3505 assign { } { } assign { } { } assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60813.5-60813.29" + attribute \src "libresoc.v:60609.5-60609.29" switch \initial - attribute \src "libresoc.v:60813.9-60813.17" + attribute \src "libresoc.v:60609.9-60609.17" case 1'1 case end @@ -102548,14 +102344,14 @@ module \dec$153 sync always update \DIV_sgn $0\DIV_sgn[0:0] end - attribute \src "libresoc.v:60822.3-60831.6" - process $proc$libresoc.v:60822$3506 + attribute \src "libresoc.v:60618.3-60627.6" + process $proc$libresoc.v:60618$3506 assign { } { } assign { } { } assign $0\DIV_function_unit[13:0] $1\DIV_function_unit[13:0] - attribute \src "libresoc.v:60823.5-60823.29" + attribute \src "libresoc.v:60619.5-60619.29" switch \initial - attribute \src "libresoc.v:60823.9-60823.17" + attribute \src "libresoc.v:60619.9-60619.17" case 1'1 case end @@ -102571,14 +102367,14 @@ module \dec$153 sync always update \DIV_function_unit $0\DIV_function_unit[13:0] end - attribute \src "libresoc.v:60832.3-60841.6" - process $proc$libresoc.v:60832$3507 + attribute \src "libresoc.v:60628.3-60637.6" + process $proc$libresoc.v:60628$3507 assign { } { } assign { } { } assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60833.5-60833.29" + attribute \src "libresoc.v:60629.5-60629.29" switch \initial - attribute \src "libresoc.v:60833.9-60833.17" + attribute \src "libresoc.v:60629.9-60629.17" case 1'1 case end @@ -102594,14 +102390,14 @@ module \dec$153 sync always update \DIV_internal_op $0\DIV_internal_op[6:0] end - attribute \src "libresoc.v:60842.3-60851.6" - process $proc$libresoc.v:60842$3508 + attribute \src "libresoc.v:60638.3-60647.6" + process $proc$libresoc.v:60638$3508 assign { } { } assign { } { } assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60843.5-60843.29" + attribute \src "libresoc.v:60639.5-60639.29" switch \initial - attribute \src "libresoc.v:60843.9-60843.17" + attribute \src "libresoc.v:60639.9-60639.17" case 1'1 case end @@ -102617,14 +102413,14 @@ module \dec$153 sync always update \DIV_in1_sel $0\DIV_in1_sel[2:0] end - attribute \src "libresoc.v:60852.3-60861.6" - process $proc$libresoc.v:60852$3509 + attribute \src "libresoc.v:60648.3-60657.6" + process $proc$libresoc.v:60648$3509 assign { } { } assign { } { } assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60853.5-60853.29" + attribute \src "libresoc.v:60649.5-60649.29" switch \initial - attribute \src "libresoc.v:60853.9-60853.17" + attribute \src "libresoc.v:60649.9-60649.17" case 1'1 case end @@ -102640,14 +102436,14 @@ module \dec$153 sync always update \DIV_in2_sel $0\DIV_in2_sel[3:0] end - attribute \src "libresoc.v:60862.3-60871.6" - process $proc$libresoc.v:60862$3510 + attribute \src "libresoc.v:60658.3-60667.6" + process $proc$libresoc.v:60658$3510 assign { } { } assign { } { } assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60863.5-60863.29" + attribute \src "libresoc.v:60659.5-60659.29" switch \initial - attribute \src "libresoc.v:60863.9-60863.17" + attribute \src "libresoc.v:60659.9-60659.17" case 1'1 case end @@ -102663,14 +102459,14 @@ module \dec$153 sync always update \DIV_cr_in $0\DIV_cr_in[2:0] end - attribute \src "libresoc.v:60872.3-60881.6" - process $proc$libresoc.v:60872$3511 + attribute \src "libresoc.v:60668.3-60677.6" + process $proc$libresoc.v:60668$3511 assign { } { } assign { } { } assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60873.5-60873.29" + attribute \src "libresoc.v:60669.5-60669.29" switch \initial - attribute \src "libresoc.v:60873.9-60873.17" + attribute \src "libresoc.v:60669.9-60669.17" case 1'1 case end @@ -102686,14 +102482,14 @@ module \dec$153 sync always update \DIV_cr_out $0\DIV_cr_out[2:0] end - attribute \src "libresoc.v:60882.3-60891.6" - process $proc$libresoc.v:60882$3512 + attribute \src "libresoc.v:60678.3-60687.6" + process $proc$libresoc.v:60678$3512 assign { } { } assign { } { } assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60883.5-60883.29" + attribute \src "libresoc.v:60679.5-60679.29" switch \initial - attribute \src "libresoc.v:60883.9-60883.17" + attribute \src "libresoc.v:60679.9-60679.17" case 1'1 case end @@ -102709,14 +102505,14 @@ module \dec$153 sync always update \DIV_ldst_len $0\DIV_ldst_len[3:0] end - attribute \src "libresoc.v:60892.3-60901.6" - process $proc$libresoc.v:60892$3513 + attribute \src "libresoc.v:60688.3-60697.6" + process $proc$libresoc.v:60688$3513 assign { } { } assign { } { } assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60893.5-60893.29" + attribute \src "libresoc.v:60689.5-60689.29" switch \initial - attribute \src "libresoc.v:60893.9-60893.17" + attribute \src "libresoc.v:60689.9-60689.17" case 1'1 case end @@ -102732,7 +102528,7 @@ module \dec$153 sync always update \DIV_rc_sel $0\DIV_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:60744$3499_Y + connect \$1 $ternary$libresoc.v:60540$3499_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -103070,47 +102866,47 @@ module \dec$153 connect \DIV_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:61242.1-62663.10" +attribute \src "libresoc.v:61038.1-62459.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" attribute \generator "nMigen" module \dec$158 - attribute \src "libresoc.v:62262.3-62274.6" + attribute \src "libresoc.v:62058.3-62070.6" wire width 3 $0\MUL_cr_in[2:0] - attribute \src "libresoc.v:62275.3-62287.6" + attribute \src "libresoc.v:62071.3-62083.6" wire width 3 $0\MUL_cr_out[2:0] - attribute \src "libresoc.v:62223.3-62235.6" + attribute \src "libresoc.v:62019.3-62031.6" wire width 14 $0\MUL_function_unit[13:0] - attribute \src "libresoc.v:62249.3-62261.6" + attribute \src "libresoc.v:62045.3-62057.6" wire width 4 $0\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62236.3-62248.6" + attribute \src "libresoc.v:62032.3-62044.6" wire width 7 $0\MUL_internal_op[6:0] - attribute \src "libresoc.v:62301.3-62313.6" + attribute \src "libresoc.v:62097.3-62109.6" wire $0\MUL_is_32b[0:0] - attribute \src "libresoc.v:62288.3-62300.6" + attribute \src "libresoc.v:62084.3-62096.6" wire width 2 $0\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62314.3-62326.6" + attribute \src "libresoc.v:62110.3-62122.6" wire $0\MUL_sgn[0:0] - attribute \src "libresoc.v:61243.7-61243.20" + attribute \src "libresoc.v:61039.7-61039.20" wire $0\initial[0:0] - attribute \src "libresoc.v:62262.3-62274.6" + attribute \src "libresoc.v:62058.3-62070.6" wire width 3 $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62275.3-62287.6" + attribute \src "libresoc.v:62071.3-62083.6" wire width 3 $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62223.3-62235.6" + attribute \src "libresoc.v:62019.3-62031.6" wire width 14 $1\MUL_function_unit[13:0] - attribute \src "libresoc.v:62249.3-62261.6" + attribute \src "libresoc.v:62045.3-62057.6" wire width 4 $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62236.3-62248.6" + attribute \src "libresoc.v:62032.3-62044.6" wire width 7 $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62301.3-62313.6" + attribute \src "libresoc.v:62097.3-62109.6" wire $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62288.3-62300.6" + attribute \src "libresoc.v:62084.3-62096.6" wire width 2 $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62314.3-62326.6" + attribute \src "libresoc.v:62110.3-62122.6" wire $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62211.17-62211.211" - wire width 32 $ternary$libresoc.v:62211$3515_Y + attribute \src "libresoc.v:62007.17-62007.211" + wire width 32 $ternary$libresoc.v:62007$3515_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -104065,7 +103861,7 @@ module \dec$158 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:61243.7-61243.15" + attribute \src "libresoc.v:61039.7-61039.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -104074,15 +103870,15 @@ module \dec$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 20 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:62211$3515 + cell $mux $ternary$libresoc.v:62007$3515 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:62211$3515_Y + connect \Y $ternary$libresoc.v:62007$3515_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:62212.13-62222.4" + attribute \src "libresoc.v:62008.13-62018.4" cell \MUL_dec31 \MUL_dec31 connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out @@ -104094,22 +103890,22 @@ module \dec$158 connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn connect \opcode_in \MUL_dec31_opcode_in end - attribute \src "libresoc.v:61243.7-61243.20" - process $proc$libresoc.v:61243$3524 + attribute \src "libresoc.v:61039.7-61039.20" + process $proc$libresoc.v:61039$3524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:62223.3-62235.6" - process $proc$libresoc.v:62223$3516 + attribute \src "libresoc.v:62019.3-62031.6" + process $proc$libresoc.v:62019$3516 assign { } { } assign { } { } assign $0\MUL_function_unit[13:0] $1\MUL_function_unit[13:0] - attribute \src "libresoc.v:62224.5-62224.29" + attribute \src "libresoc.v:62020.5-62020.29" switch \initial - attribute \src "libresoc.v:62224.9-62224.17" + attribute \src "libresoc.v:62020.9-62020.17" case 1'1 case end @@ -104129,14 +103925,14 @@ module \dec$158 sync always update \MUL_function_unit $0\MUL_function_unit[13:0] end - attribute \src "libresoc.v:62236.3-62248.6" - process $proc$libresoc.v:62236$3517 + attribute \src "libresoc.v:62032.3-62044.6" + process $proc$libresoc.v:62032$3517 assign { } { } assign { } { } assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62237.5-62237.29" + attribute \src "libresoc.v:62033.5-62033.29" switch \initial - attribute \src "libresoc.v:62237.9-62237.17" + attribute \src "libresoc.v:62033.9-62033.17" case 1'1 case end @@ -104156,14 +103952,14 @@ module \dec$158 sync always update \MUL_internal_op $0\MUL_internal_op[6:0] end - attribute \src "libresoc.v:62249.3-62261.6" - process $proc$libresoc.v:62249$3518 + attribute \src "libresoc.v:62045.3-62057.6" + process $proc$libresoc.v:62045$3518 assign { } { } assign { } { } assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62250.5-62250.29" + attribute \src "libresoc.v:62046.5-62046.29" switch \initial - attribute \src "libresoc.v:62250.9-62250.17" + attribute \src "libresoc.v:62046.9-62046.17" case 1'1 case end @@ -104183,14 +103979,14 @@ module \dec$158 sync always update \MUL_in2_sel $0\MUL_in2_sel[3:0] end - attribute \src "libresoc.v:62262.3-62274.6" - process $proc$libresoc.v:62262$3519 + attribute \src "libresoc.v:62058.3-62070.6" + process $proc$libresoc.v:62058$3519 assign { } { } assign { } { } assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62263.5-62263.29" + attribute \src "libresoc.v:62059.5-62059.29" switch \initial - attribute \src "libresoc.v:62263.9-62263.17" + attribute \src "libresoc.v:62059.9-62059.17" case 1'1 case end @@ -104210,14 +104006,14 @@ module \dec$158 sync always update \MUL_cr_in $0\MUL_cr_in[2:0] end - attribute \src "libresoc.v:62275.3-62287.6" - process $proc$libresoc.v:62275$3520 + attribute \src "libresoc.v:62071.3-62083.6" + process $proc$libresoc.v:62071$3520 assign { } { } assign { } { } assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62276.5-62276.29" + attribute \src "libresoc.v:62072.5-62072.29" switch \initial - attribute \src "libresoc.v:62276.9-62276.17" + attribute \src "libresoc.v:62072.9-62072.17" case 1'1 case end @@ -104237,14 +104033,14 @@ module \dec$158 sync always update \MUL_cr_out $0\MUL_cr_out[2:0] end - attribute \src "libresoc.v:62288.3-62300.6" - process $proc$libresoc.v:62288$3521 + attribute \src "libresoc.v:62084.3-62096.6" + process $proc$libresoc.v:62084$3521 assign { } { } assign { } { } assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62289.5-62289.29" + attribute \src "libresoc.v:62085.5-62085.29" switch \initial - attribute \src "libresoc.v:62289.9-62289.17" + attribute \src "libresoc.v:62085.9-62085.17" case 1'1 case end @@ -104264,14 +104060,14 @@ module \dec$158 sync always update \MUL_rc_sel $0\MUL_rc_sel[1:0] end - attribute \src "libresoc.v:62301.3-62313.6" - process $proc$libresoc.v:62301$3522 + attribute \src "libresoc.v:62097.3-62109.6" + process $proc$libresoc.v:62097$3522 assign { } { } assign { } { } assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62302.5-62302.29" + attribute \src "libresoc.v:62098.5-62098.29" switch \initial - attribute \src "libresoc.v:62302.9-62302.17" + attribute \src "libresoc.v:62098.9-62098.17" case 1'1 case end @@ -104291,14 +104087,14 @@ module \dec$158 sync always update \MUL_is_32b $0\MUL_is_32b[0:0] end - attribute \src "libresoc.v:62314.3-62326.6" - process $proc$libresoc.v:62314$3523 + attribute \src "libresoc.v:62110.3-62122.6" + process $proc$libresoc.v:62110$3523 assign { } { } assign { } { } assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62315.5-62315.29" + attribute \src "libresoc.v:62111.5-62111.29" switch \initial - attribute \src "libresoc.v:62315.9-62315.17" + attribute \src "libresoc.v:62111.9-62111.17" case 1'1 case end @@ -104318,7 +104114,7 @@ module \dec$158 sync always update \MUL_sgn $0\MUL_sgn[0:0] end - connect \$1 $ternary$libresoc.v:62211$3515_Y + connect \$1 $ternary$libresoc.v:62007$3515_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -104656,59 +104452,59 @@ module \dec$158 connect \MUL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:62667.1-64421.10" +attribute \src "libresoc.v:62463.1-64217.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" attribute \generator "nMigen" module \dec$162 - attribute \src "libresoc.v:63996.3-64017.6" + attribute \src "libresoc.v:63792.3-63813.6" wire width 3 $0\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64018.3-64039.6" + attribute \src "libresoc.v:63814.3-63835.6" wire width 3 $0\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64062.3-64083.6" + attribute \src "libresoc.v:63858.3-63879.6" wire width 2 $0\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63864.3-63885.6" + attribute \src "libresoc.v:63660.3-63681.6" wire $0\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63930.3-63951.6" + attribute \src "libresoc.v:63726.3-63747.6" wire width 14 $0\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:63974.3-63995.6" + attribute \src "libresoc.v:63770.3-63791.6" wire width 4 $0\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63952.3-63973.6" + attribute \src "libresoc.v:63748.3-63769.6" wire width 7 $0\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63842.3-63863.6" + attribute \src "libresoc.v:63638.3-63659.6" wire $0\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63886.3-63907.6" + attribute \src "libresoc.v:63682.3-63703.6" wire $0\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64040.3-64061.6" + attribute \src "libresoc.v:63836.3-63857.6" wire width 2 $0\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63908.3-63929.6" + attribute \src "libresoc.v:63704.3-63725.6" wire $0\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:62668.7-62668.20" + attribute \src "libresoc.v:62464.7-62464.20" wire $0\initial[0:0] - attribute \src "libresoc.v:63996.3-64017.6" + attribute \src "libresoc.v:63792.3-63813.6" wire width 3 $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64018.3-64039.6" + attribute \src "libresoc.v:63814.3-63835.6" wire width 3 $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64062.3-64083.6" + attribute \src "libresoc.v:63858.3-63879.6" wire width 2 $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63864.3-63885.6" + attribute \src "libresoc.v:63660.3-63681.6" wire $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63930.3-63951.6" + attribute \src "libresoc.v:63726.3-63747.6" wire width 14 $1\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:63974.3-63995.6" + attribute \src "libresoc.v:63770.3-63791.6" wire width 4 $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63952.3-63973.6" + attribute \src "libresoc.v:63748.3-63769.6" wire width 7 $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63842.3-63863.6" + attribute \src "libresoc.v:63638.3-63659.6" wire $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63886.3-63907.6" + attribute \src "libresoc.v:63682.3-63703.6" wire $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64040.3-64061.6" + attribute \src "libresoc.v:63836.3-63857.6" wire width 2 $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63908.3-63929.6" + attribute \src "libresoc.v:63704.3-63725.6" wire $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63813.17-63813.211" - wire width 32 $ternary$libresoc.v:63813$3525_Y + attribute \src "libresoc.v:63609.17-63609.211" + wire width 32 $ternary$libresoc.v:63609$3525_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -105836,7 +105632,7 @@ module \dec$162 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:62668.7-62668.15" + attribute \src "libresoc.v:62464.7-62464.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -105845,15 +105641,15 @@ module \dec$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 24 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:63813$3525 + cell $mux $ternary$libresoc.v:63609$3525 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:63813$3525_Y + connect \Y $ternary$libresoc.v:63609$3525_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:63814.19-63827.4" + attribute \src "libresoc.v:63610.19-63623.4" cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out @@ -105869,7 +105665,7 @@ module \dec$162 connect \opcode_in \SHIFT_ROT_dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:63828.19-63841.4" + attribute \src "libresoc.v:63624.19-63637.4" cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out @@ -105884,22 +105680,22 @@ module \dec$162 connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn connect \opcode_in \SHIFT_ROT_dec31_opcode_in end - attribute \src "libresoc.v:62668.7-62668.20" - process $proc$libresoc.v:62668$3537 + attribute \src "libresoc.v:62464.7-62464.20" + process $proc$libresoc.v:62464$3537 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:63842.3-63863.6" - process $proc$libresoc.v:63842$3526 + attribute \src "libresoc.v:63638.3-63659.6" + process $proc$libresoc.v:63638$3526 assign { } { } assign { } { } assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63843.5-63843.29" + attribute \src "libresoc.v:63639.5-63639.29" switch \initial - attribute \src "libresoc.v:63843.9-63843.17" + attribute \src "libresoc.v:63639.9-63639.17" case 1'1 case end @@ -105931,14 +105727,14 @@ module \dec$162 sync always update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] end - attribute \src "libresoc.v:63864.3-63885.6" - process $proc$libresoc.v:63864$3527 + attribute \src "libresoc.v:63660.3-63681.6" + process $proc$libresoc.v:63660$3527 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63865.5-63865.29" + attribute \src "libresoc.v:63661.5-63661.29" switch \initial - attribute \src "libresoc.v:63865.9-63865.17" + attribute \src "libresoc.v:63661.9-63661.17" case 1'1 case end @@ -105970,14 +105766,14 @@ module \dec$162 sync always update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] end - attribute \src "libresoc.v:63886.3-63907.6" - process $proc$libresoc.v:63886$3528 + attribute \src "libresoc.v:63682.3-63703.6" + process $proc$libresoc.v:63682$3528 assign { } { } assign { } { } assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63887.5-63887.29" + attribute \src "libresoc.v:63683.5-63683.29" switch \initial - attribute \src "libresoc.v:63887.9-63887.17" + attribute \src "libresoc.v:63683.9-63683.17" case 1'1 case end @@ -106009,14 +105805,14 @@ module \dec$162 sync always update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] end - attribute \src "libresoc.v:63908.3-63929.6" - process $proc$libresoc.v:63908$3529 + attribute \src "libresoc.v:63704.3-63725.6" + process $proc$libresoc.v:63704$3529 assign { } { } assign { } { } assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63909.5-63909.29" + attribute \src "libresoc.v:63705.5-63705.29" switch \initial - attribute \src "libresoc.v:63909.9-63909.17" + attribute \src "libresoc.v:63705.9-63705.17" case 1'1 case end @@ -106048,14 +105844,14 @@ module \dec$162 sync always update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] end - attribute \src "libresoc.v:63930.3-63951.6" - process $proc$libresoc.v:63930$3530 + attribute \src "libresoc.v:63726.3-63747.6" + process $proc$libresoc.v:63726$3530 assign { } { } assign { } { } assign $0\SHIFT_ROT_function_unit[13:0] $1\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:63931.5-63931.29" + attribute \src "libresoc.v:63727.5-63727.29" switch \initial - attribute \src "libresoc.v:63931.9-63931.17" + attribute \src "libresoc.v:63727.9-63727.17" case 1'1 case end @@ -106087,14 +105883,14 @@ module \dec$162 sync always update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[13:0] end - attribute \src "libresoc.v:63952.3-63973.6" - process $proc$libresoc.v:63952$3531 + attribute \src "libresoc.v:63748.3-63769.6" + process $proc$libresoc.v:63748$3531 assign { } { } assign { } { } assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63953.5-63953.29" + attribute \src "libresoc.v:63749.5-63749.29" switch \initial - attribute \src "libresoc.v:63953.9-63953.17" + attribute \src "libresoc.v:63749.9-63749.17" case 1'1 case end @@ -106126,14 +105922,14 @@ module \dec$162 sync always update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] end - attribute \src "libresoc.v:63974.3-63995.6" - process $proc$libresoc.v:63974$3532 + attribute \src "libresoc.v:63770.3-63791.6" + process $proc$libresoc.v:63770$3532 assign { } { } assign { } { } assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63975.5-63975.29" + attribute \src "libresoc.v:63771.5-63771.29" switch \initial - attribute \src "libresoc.v:63975.9-63975.17" + attribute \src "libresoc.v:63771.9-63771.17" case 1'1 case end @@ -106165,14 +105961,14 @@ module \dec$162 sync always update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] end - attribute \src "libresoc.v:63996.3-64017.6" - process $proc$libresoc.v:63996$3533 + attribute \src "libresoc.v:63792.3-63813.6" + process $proc$libresoc.v:63792$3533 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:63997.5-63997.29" + attribute \src "libresoc.v:63793.5-63793.29" switch \initial - attribute \src "libresoc.v:63997.9-63997.17" + attribute \src "libresoc.v:63793.9-63793.17" case 1'1 case end @@ -106204,14 +106000,14 @@ module \dec$162 sync always update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] end - attribute \src "libresoc.v:64018.3-64039.6" - process $proc$libresoc.v:64018$3534 + attribute \src "libresoc.v:63814.3-63835.6" + process $proc$libresoc.v:63814$3534 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64019.5-64019.29" + attribute \src "libresoc.v:63815.5-63815.29" switch \initial - attribute \src "libresoc.v:64019.9-64019.17" + attribute \src "libresoc.v:63815.9-63815.17" case 1'1 case end @@ -106243,14 +106039,14 @@ module \dec$162 sync always update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] end - attribute \src "libresoc.v:64040.3-64061.6" - process $proc$libresoc.v:64040$3535 + attribute \src "libresoc.v:63836.3-63857.6" + process $proc$libresoc.v:63836$3535 assign { } { } assign { } { } assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:64041.5-64041.29" + attribute \src "libresoc.v:63837.5-63837.29" switch \initial - attribute \src "libresoc.v:64041.9-64041.17" + attribute \src "libresoc.v:63837.9-63837.17" case 1'1 case end @@ -106282,14 +106078,14 @@ module \dec$162 sync always update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] end - attribute \src "libresoc.v:64062.3-64083.6" - process $proc$libresoc.v:64062$3536 + attribute \src "libresoc.v:63858.3-63879.6" + process $proc$libresoc.v:63858$3536 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:64063.5-64063.29" + attribute \src "libresoc.v:63859.5-63859.29" switch \initial - attribute \src "libresoc.v:64063.9-64063.17" + attribute \src "libresoc.v:63859.9-63859.17" case 1'1 case end @@ -106321,7 +106117,7 @@ module \dec$162 sync always update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] end - connect \$1 $ternary$libresoc.v:63813$3525_Y + connect \$1 $ternary$libresoc.v:63609$3525_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -106660,67 +106456,67 @@ module \dec$162 connect \SHIFT_ROT_dec30_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:64425.1-66934.10" +attribute \src "libresoc.v:64221.1-66730.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" attribute \generator "nMigen" module \dec$166 - attribute \src "libresoc.v:66016.3-66073.6" + attribute \src "libresoc.v:65812.3-65869.6" wire $0\LDST_br[0:0] - attribute \src "libresoc.v:66480.3-66537.6" + attribute \src "libresoc.v:66276.3-66333.6" wire width 3 $0\LDST_cr_in[2:0] - attribute \src "libresoc.v:66538.3-66595.6" + attribute \src "libresoc.v:66334.3-66391.6" wire width 3 $0\LDST_cr_out[2:0] - attribute \src "libresoc.v:66248.3-66305.6" + attribute \src "libresoc.v:66044.3-66101.6" wire width 14 $0\LDST_function_unit[13:0] - attribute \src "libresoc.v:66364.3-66421.6" + attribute \src "libresoc.v:66160.3-66217.6" wire width 3 $0\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66422.3-66479.6" + attribute \src "libresoc.v:66218.3-66275.6" wire width 4 $0\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66306.3-66363.6" + attribute \src "libresoc.v:66102.3-66159.6" wire width 7 $0\LDST_internal_op[6:0] - attribute \src "libresoc.v:66132.3-66189.6" + attribute \src "libresoc.v:65928.3-65985.6" wire $0\LDST_is_32b[0:0] - attribute \src "libresoc.v:65842.3-65899.6" + attribute \src "libresoc.v:65638.3-65695.6" wire width 4 $0\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65958.3-66015.6" + attribute \src "libresoc.v:65754.3-65811.6" wire width 2 $0\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66190.3-66247.6" + attribute \src "libresoc.v:65986.3-66043.6" wire $0\LDST_sgn[0:0] - attribute \src "libresoc.v:66074.3-66131.6" + attribute \src "libresoc.v:65870.3-65927.6" wire $0\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65900.3-65957.6" + attribute \src "libresoc.v:65696.3-65753.6" wire width 2 $0\LDST_upd[1:0] - attribute \src "libresoc.v:64426.7-64426.20" + attribute \src "libresoc.v:64222.7-64222.20" wire $0\initial[0:0] - attribute \src "libresoc.v:66016.3-66073.6" + attribute \src "libresoc.v:65812.3-65869.6" wire $1\LDST_br[0:0] - attribute \src "libresoc.v:66480.3-66537.6" + attribute \src "libresoc.v:66276.3-66333.6" wire width 3 $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66538.3-66595.6" + attribute \src "libresoc.v:66334.3-66391.6" wire width 3 $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66248.3-66305.6" + attribute \src "libresoc.v:66044.3-66101.6" wire width 14 $1\LDST_function_unit[13:0] - attribute \src "libresoc.v:66364.3-66421.6" + attribute \src "libresoc.v:66160.3-66217.6" wire width 3 $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66422.3-66479.6" + attribute \src "libresoc.v:66218.3-66275.6" wire width 4 $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66306.3-66363.6" + attribute \src "libresoc.v:66102.3-66159.6" wire width 7 $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66132.3-66189.6" + attribute \src "libresoc.v:65928.3-65985.6" wire $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:65842.3-65899.6" + attribute \src "libresoc.v:65638.3-65695.6" wire width 4 $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65958.3-66015.6" + attribute \src "libresoc.v:65754.3-65811.6" wire width 2 $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66190.3-66247.6" + attribute \src "libresoc.v:65986.3-66043.6" wire $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66074.3-66131.6" + attribute \src "libresoc.v:65870.3-65927.6" wire $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65900.3-65957.6" + attribute \src "libresoc.v:65696.3-65753.6" wire width 2 $1\LDST_upd[1:0] - attribute \src "libresoc.v:65793.17-65793.211" - wire width 32 $ternary$libresoc.v:65793$3538_Y + attribute \src "libresoc.v:65589.17-65589.211" + wire width 32 $ternary$libresoc.v:65589$3538_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -108069,7 +107865,7 @@ module \dec$166 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:64426.7-64426.15" + attribute \src "libresoc.v:64222.7-64222.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -108078,15 +107874,15 @@ module \dec$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 26 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:65793$3538 + cell $mux $ternary$libresoc.v:65589$3538 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:65793$3538_Y + connect \Y $ternary$libresoc.v:65589$3538_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:65794.14-65809.4" + attribute \src "libresoc.v:65590.14-65605.4" cell \LDST_dec31 \LDST_dec31 connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in @@ -108104,7 +107900,7 @@ module \dec$166 connect \opcode_in \LDST_dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65810.14-65825.4" + attribute \src "libresoc.v:65606.14-65621.4" cell \LDST_dec58 \LDST_dec58 connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in @@ -108122,7 +107918,7 @@ module \dec$166 connect \opcode_in \LDST_dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65826.14-65841.4" + attribute \src "libresoc.v:65622.14-65637.4" cell \LDST_dec62 \LDST_dec62 connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in @@ -108139,22 +107935,22 @@ module \dec$166 connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd connect \opcode_in \LDST_dec62_opcode_in end - attribute \src "libresoc.v:64426.7-64426.20" - process $proc$libresoc.v:64426$3552 + attribute \src "libresoc.v:64222.7-64222.20" + process $proc$libresoc.v:64222$3552 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:65842.3-65899.6" - process $proc$libresoc.v:65842$3539 + attribute \src "libresoc.v:65638.3-65695.6" + process $proc$libresoc.v:65638$3539 assign { } { } assign { } { } assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65843.5-65843.29" + attribute \src "libresoc.v:65639.5-65639.29" switch \initial - attribute \src "libresoc.v:65843.9-65843.17" + attribute \src "libresoc.v:65639.9-65639.17" case 1'1 case end @@ -108234,14 +108030,14 @@ module \dec$166 sync always update \LDST_ldst_len $0\LDST_ldst_len[3:0] end - attribute \src "libresoc.v:65900.3-65957.6" - process $proc$libresoc.v:65900$3540 + attribute \src "libresoc.v:65696.3-65753.6" + process $proc$libresoc.v:65696$3540 assign { } { } assign { } { } assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] - attribute \src "libresoc.v:65901.5-65901.29" + attribute \src "libresoc.v:65697.5-65697.29" switch \initial - attribute \src "libresoc.v:65901.9-65901.17" + attribute \src "libresoc.v:65697.9-65697.17" case 1'1 case end @@ -108321,14 +108117,14 @@ module \dec$166 sync always update \LDST_upd $0\LDST_upd[1:0] end - attribute \src "libresoc.v:65958.3-66015.6" - process $proc$libresoc.v:65958$3541 + attribute \src "libresoc.v:65754.3-65811.6" + process $proc$libresoc.v:65754$3541 assign { } { } assign { } { } assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:65959.5-65959.29" + attribute \src "libresoc.v:65755.5-65755.29" switch \initial - attribute \src "libresoc.v:65959.9-65959.17" + attribute \src "libresoc.v:65755.9-65755.17" case 1'1 case end @@ -108408,14 +108204,14 @@ module \dec$166 sync always update \LDST_rc_sel $0\LDST_rc_sel[1:0] end - attribute \src "libresoc.v:66016.3-66073.6" - process $proc$libresoc.v:66016$3542 + attribute \src "libresoc.v:65812.3-65869.6" + process $proc$libresoc.v:65812$3542 assign { } { } assign { } { } assign $0\LDST_br[0:0] $1\LDST_br[0:0] - attribute \src "libresoc.v:66017.5-66017.29" + attribute \src "libresoc.v:65813.5-65813.29" switch \initial - attribute \src "libresoc.v:66017.9-66017.17" + attribute \src "libresoc.v:65813.9-65813.17" case 1'1 case end @@ -108495,14 +108291,14 @@ module \dec$166 sync always update \LDST_br $0\LDST_br[0:0] end - attribute \src "libresoc.v:66074.3-66131.6" - process $proc$libresoc.v:66074$3543 + attribute \src "libresoc.v:65870.3-65927.6" + process $proc$libresoc.v:65870$3543 assign { } { } assign { } { } assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:66075.5-66075.29" + attribute \src "libresoc.v:65871.5-65871.29" switch \initial - attribute \src "libresoc.v:66075.9-66075.17" + attribute \src "libresoc.v:65871.9-65871.17" case 1'1 case end @@ -108582,14 +108378,14 @@ module \dec$166 sync always update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] end - attribute \src "libresoc.v:66132.3-66189.6" - process $proc$libresoc.v:66132$3544 + attribute \src "libresoc.v:65928.3-65985.6" + process $proc$libresoc.v:65928$3544 assign { } { } assign { } { } assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:66133.5-66133.29" + attribute \src "libresoc.v:65929.5-65929.29" switch \initial - attribute \src "libresoc.v:66133.9-66133.17" + attribute \src "libresoc.v:65929.9-65929.17" case 1'1 case end @@ -108669,14 +108465,14 @@ module \dec$166 sync always update \LDST_is_32b $0\LDST_is_32b[0:0] end - attribute \src "libresoc.v:66190.3-66247.6" - process $proc$libresoc.v:66190$3545 + attribute \src "libresoc.v:65986.3-66043.6" + process $proc$libresoc.v:65986$3545 assign { } { } assign { } { } assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66191.5-66191.29" + attribute \src "libresoc.v:65987.5-65987.29" switch \initial - attribute \src "libresoc.v:66191.9-66191.17" + attribute \src "libresoc.v:65987.9-65987.17" case 1'1 case end @@ -108756,14 +108552,14 @@ module \dec$166 sync always update \LDST_sgn $0\LDST_sgn[0:0] end - attribute \src "libresoc.v:66248.3-66305.6" - process $proc$libresoc.v:66248$3546 + attribute \src "libresoc.v:66044.3-66101.6" + process $proc$libresoc.v:66044$3546 assign { } { } assign { } { } assign $0\LDST_function_unit[13:0] $1\LDST_function_unit[13:0] - attribute \src "libresoc.v:66249.5-66249.29" + attribute \src "libresoc.v:66045.5-66045.29" switch \initial - attribute \src "libresoc.v:66249.9-66249.17" + attribute \src "libresoc.v:66045.9-66045.17" case 1'1 case end @@ -108843,14 +108639,14 @@ module \dec$166 sync always update \LDST_function_unit $0\LDST_function_unit[13:0] end - attribute \src "libresoc.v:66306.3-66363.6" - process $proc$libresoc.v:66306$3547 + attribute \src "libresoc.v:66102.3-66159.6" + process $proc$libresoc.v:66102$3547 assign { } { } assign { } { } assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66307.5-66307.29" + attribute \src "libresoc.v:66103.5-66103.29" switch \initial - attribute \src "libresoc.v:66307.9-66307.17" + attribute \src "libresoc.v:66103.9-66103.17" case 1'1 case end @@ -108930,14 +108726,14 @@ module \dec$166 sync always update \LDST_internal_op $0\LDST_internal_op[6:0] end - attribute \src "libresoc.v:66364.3-66421.6" - process $proc$libresoc.v:66364$3548 + attribute \src "libresoc.v:66160.3-66217.6" + process $proc$libresoc.v:66160$3548 assign { } { } assign { } { } assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66365.5-66365.29" + attribute \src "libresoc.v:66161.5-66161.29" switch \initial - attribute \src "libresoc.v:66365.9-66365.17" + attribute \src "libresoc.v:66161.9-66161.17" case 1'1 case end @@ -109017,14 +108813,14 @@ module \dec$166 sync always update \LDST_in1_sel $0\LDST_in1_sel[2:0] end - attribute \src "libresoc.v:66422.3-66479.6" - process $proc$libresoc.v:66422$3549 + attribute \src "libresoc.v:66218.3-66275.6" + process $proc$libresoc.v:66218$3549 assign { } { } assign { } { } assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66423.5-66423.29" + attribute \src "libresoc.v:66219.5-66219.29" switch \initial - attribute \src "libresoc.v:66423.9-66423.17" + attribute \src "libresoc.v:66219.9-66219.17" case 1'1 case end @@ -109104,14 +108900,14 @@ module \dec$166 sync always update \LDST_in2_sel $0\LDST_in2_sel[3:0] end - attribute \src "libresoc.v:66480.3-66537.6" - process $proc$libresoc.v:66480$3550 + attribute \src "libresoc.v:66276.3-66333.6" + process $proc$libresoc.v:66276$3550 assign { } { } assign { } { } assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66481.5-66481.29" + attribute \src "libresoc.v:66277.5-66277.29" switch \initial - attribute \src "libresoc.v:66481.9-66481.17" + attribute \src "libresoc.v:66277.9-66277.17" case 1'1 case end @@ -109191,14 +108987,14 @@ module \dec$166 sync always update \LDST_cr_in $0\LDST_cr_in[2:0] end - attribute \src "libresoc.v:66538.3-66595.6" - process $proc$libresoc.v:66538$3551 + attribute \src "libresoc.v:66334.3-66391.6" + process $proc$libresoc.v:66334$3551 assign { } { } assign { } { } assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66539.5-66539.29" + attribute \src "libresoc.v:66335.5-66335.29" switch \initial - attribute \src "libresoc.v:66539.9-66539.17" + attribute \src "libresoc.v:66335.9-66335.17" case 1'1 case end @@ -109278,7 +109074,7 @@ module \dec$166 sync always update \LDST_cr_out $0\LDST_cr_out[2:0] end - connect \$1 $ternary$libresoc.v:65793$3538_Y + connect \$1 $ternary$libresoc.v:65589$3538_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -109618,213 +109414,213 @@ module \dec$166 connect \LDST_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:66938.1-75158.10" +attribute \src "libresoc.v:66734.1-74954.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" attribute \generator "nMigen" module \dec$171 - attribute \src "libresoc.v:70321.3-70465.6" + attribute \src "libresoc.v:70117.3-70261.6" wire width 2 $0\SV_Etype[1:0] - attribute \src "libresoc.v:70466.3-70610.6" + attribute \src "libresoc.v:70262.3-70406.6" wire width 2 $0\SV_Ptype[1:0] - attribute \src "libresoc.v:70176.3-70320.6" + attribute \src "libresoc.v:69972.3-70116.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:73511.3-73655.6" + attribute \src "libresoc.v:73307.3-73451.6" wire $0\br[0:0] - attribute \src "libresoc.v:71191.3-71335.6" + attribute \src "libresoc.v:70987.3-71131.6" wire width 3 $0\cr_in[2:0] - attribute \src "libresoc.v:71336.3-71480.6" + attribute \src "libresoc.v:71132.3-71276.6" wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:72931.3-73075.6" + attribute \src "libresoc.v:72727.3-72871.6" wire width 2 $0\cry_in[1:0] - attribute \src "libresoc.v:73366.3-73510.6" + attribute \src "libresoc.v:73162.3-73306.6" wire $0\cry_out[0:0] - attribute \src "libresoc.v:70031.3-70175.6" + attribute \src "libresoc.v:69827.3-69971.6" wire width 5 $0\form[4:0] - attribute \src "libresoc.v:74526.3-74670.6" + attribute \src "libresoc.v:74322.3-74466.6" wire width 14 $0\function_unit[13:0] - attribute \src "libresoc.v:70611.3-70755.6" + attribute \src "libresoc.v:70407.3-70551.6" wire width 3 $0\in1_sel[2:0] - attribute \src "libresoc.v:70756.3-70900.6" + attribute \src "libresoc.v:70552.3-70696.6" wire width 4 $0\in2_sel[3:0] - attribute \src "libresoc.v:70901.3-71045.6" + attribute \src "libresoc.v:70697.3-70841.6" wire width 2 $0\in3_sel[1:0] - attribute \src "libresoc.v:66939.7-66939.20" + attribute \src "libresoc.v:66735.7-66735.20" wire $0\initial[0:0] - attribute \src "libresoc.v:74671.3-74815.6" + attribute \src "libresoc.v:74467.3-74611.6" wire width 7 $0\internal_op[6:0] - attribute \src "libresoc.v:73076.3-73220.6" + attribute \src "libresoc.v:72872.3-73016.6" wire $0\inv_a[0:0] - attribute \src "libresoc.v:73221.3-73365.6" + attribute \src "libresoc.v:73017.3-73161.6" wire $0\inv_out[0:0] - attribute \src "libresoc.v:73946.3-74090.6" + attribute \src "libresoc.v:73742.3-73886.6" wire $0\is_32b[0:0] - attribute \src "libresoc.v:72496.3-72640.6" + attribute \src "libresoc.v:72292.3-72436.6" wire width 4 $0\ldst_len[3:0] - attribute \src "libresoc.v:74236.3-74380.6" + attribute \src "libresoc.v:74032.3-74176.6" wire $0\lk[0:0] - attribute \src "libresoc.v:71046.3-71190.6" + attribute \src "libresoc.v:70842.3-70986.6" wire width 3 $0\out_sel[2:0] - attribute \src "libresoc.v:72786.3-72930.6" + attribute \src "libresoc.v:72582.3-72726.6" wire width 2 $0\rc_sel[1:0] - attribute \src "libresoc.v:73801.3-73945.6" + attribute \src "libresoc.v:73597.3-73741.6" wire $0\rsrv[0:0] - attribute \src "libresoc.v:74381.3-74525.6" + attribute \src "libresoc.v:74177.3-74321.6" wire $0\sgl_pipe[0:0] - attribute \src "libresoc.v:74091.3-74235.6" + attribute \src "libresoc.v:73887.3-74031.6" wire $0\sgn[0:0] - attribute \src "libresoc.v:73656.3-73800.6" + attribute \src "libresoc.v:73452.3-73596.6" wire $0\sgn_ext[0:0] - attribute \src "libresoc.v:72206.3-72350.6" + attribute \src "libresoc.v:72002.3-72146.6" wire width 3 $0\sv_cr_in[2:0] - attribute \src "libresoc.v:72351.3-72495.6" + attribute \src "libresoc.v:72147.3-72291.6" wire width 3 $0\sv_cr_out[2:0] - attribute \src "libresoc.v:71481.3-71625.6" + attribute \src "libresoc.v:71277.3-71421.6" wire width 3 $0\sv_in1[2:0] - attribute \src "libresoc.v:71626.3-71770.6" + attribute \src "libresoc.v:71422.3-71566.6" wire width 3 $0\sv_in2[2:0] - attribute \src "libresoc.v:71771.3-71915.6" + attribute \src "libresoc.v:71567.3-71711.6" wire width 3 $0\sv_in3[2:0] - attribute \src "libresoc.v:72061.3-72205.6" + attribute \src "libresoc.v:71857.3-72001.6" wire width 3 $0\sv_out2[2:0] - attribute \src "libresoc.v:71916.3-72060.6" + attribute \src "libresoc.v:71712.3-71856.6" wire width 3 $0\sv_out[2:0] - attribute \src "libresoc.v:72641.3-72785.6" + attribute \src "libresoc.v:72437.3-72581.6" wire width 2 $0\upd[1:0] - attribute \src "libresoc.v:70321.3-70465.6" + attribute \src "libresoc.v:70117.3-70261.6" wire width 2 $1\SV_Etype[1:0] - attribute \src "libresoc.v:70466.3-70610.6" + attribute \src "libresoc.v:70262.3-70406.6" wire width 2 $1\SV_Ptype[1:0] - attribute \src "libresoc.v:70176.3-70320.6" + attribute \src "libresoc.v:69972.3-70116.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:73511.3-73655.6" + attribute \src "libresoc.v:73307.3-73451.6" wire $1\br[0:0] - attribute \src "libresoc.v:71191.3-71335.6" + attribute \src "libresoc.v:70987.3-71131.6" wire width 3 $1\cr_in[2:0] - attribute \src "libresoc.v:71336.3-71480.6" + attribute \src "libresoc.v:71132.3-71276.6" wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:72931.3-73075.6" + attribute \src "libresoc.v:72727.3-72871.6" wire width 2 $1\cry_in[1:0] - attribute \src "libresoc.v:73366.3-73510.6" + attribute \src "libresoc.v:73162.3-73306.6" wire $1\cry_out[0:0] - attribute \src "libresoc.v:70031.3-70175.6" + attribute \src "libresoc.v:69827.3-69971.6" wire width 5 $1\form[4:0] - attribute \src "libresoc.v:74526.3-74670.6" + attribute \src "libresoc.v:74322.3-74466.6" wire width 14 $1\function_unit[13:0] - attribute \src "libresoc.v:70611.3-70755.6" + attribute \src "libresoc.v:70407.3-70551.6" wire width 3 $1\in1_sel[2:0] - attribute \src "libresoc.v:70756.3-70900.6" + attribute \src "libresoc.v:70552.3-70696.6" wire width 4 $1\in2_sel[3:0] - attribute \src "libresoc.v:70901.3-71045.6" + attribute \src "libresoc.v:70697.3-70841.6" wire width 2 $1\in3_sel[1:0] - attribute \src "libresoc.v:74671.3-74815.6" + attribute \src "libresoc.v:74467.3-74611.6" wire width 7 $1\internal_op[6:0] - attribute \src "libresoc.v:73076.3-73220.6" + attribute \src "libresoc.v:72872.3-73016.6" wire $1\inv_a[0:0] - attribute \src "libresoc.v:73221.3-73365.6" + attribute \src "libresoc.v:73017.3-73161.6" wire $1\inv_out[0:0] - attribute \src "libresoc.v:73946.3-74090.6" + attribute \src "libresoc.v:73742.3-73886.6" wire $1\is_32b[0:0] - attribute \src "libresoc.v:72496.3-72640.6" + attribute \src "libresoc.v:72292.3-72436.6" wire width 4 $1\ldst_len[3:0] - attribute \src "libresoc.v:74236.3-74380.6" + attribute \src "libresoc.v:74032.3-74176.6" wire $1\lk[0:0] - attribute \src "libresoc.v:71046.3-71190.6" + attribute \src "libresoc.v:70842.3-70986.6" wire width 3 $1\out_sel[2:0] - attribute \src "libresoc.v:72786.3-72930.6" + attribute \src "libresoc.v:72582.3-72726.6" wire width 2 $1\rc_sel[1:0] - attribute \src "libresoc.v:73801.3-73945.6" + attribute \src "libresoc.v:73597.3-73741.6" wire $1\rsrv[0:0] - attribute \src "libresoc.v:74381.3-74525.6" + attribute \src "libresoc.v:74177.3-74321.6" wire $1\sgl_pipe[0:0] - attribute \src "libresoc.v:74091.3-74235.6" + attribute \src "libresoc.v:73887.3-74031.6" wire $1\sgn[0:0] - attribute \src "libresoc.v:73656.3-73800.6" + attribute \src "libresoc.v:73452.3-73596.6" wire $1\sgn_ext[0:0] - attribute \src "libresoc.v:72206.3-72350.6" + attribute \src "libresoc.v:72002.3-72146.6" wire width 3 $1\sv_cr_in[2:0] - attribute \src "libresoc.v:72351.3-72495.6" + attribute \src "libresoc.v:72147.3-72291.6" wire width 3 $1\sv_cr_out[2:0] - attribute \src "libresoc.v:71481.3-71625.6" + attribute \src "libresoc.v:71277.3-71421.6" wire width 3 $1\sv_in1[2:0] - attribute \src "libresoc.v:71626.3-71770.6" + attribute \src "libresoc.v:71422.3-71566.6" wire width 3 $1\sv_in2[2:0] - attribute \src "libresoc.v:71771.3-71915.6" + attribute \src "libresoc.v:71567.3-71711.6" wire width 3 $1\sv_in3[2:0] - attribute \src "libresoc.v:72061.3-72205.6" + attribute \src "libresoc.v:71857.3-72001.6" wire width 3 $1\sv_out2[2:0] - attribute \src "libresoc.v:71916.3-72060.6" + attribute \src "libresoc.v:71712.3-71856.6" wire width 3 $1\sv_out[2:0] - attribute \src "libresoc.v:72641.3-72785.6" + attribute \src "libresoc.v:72437.3-72581.6" wire width 2 $1\upd[1:0] - attribute \src "libresoc.v:70321.3-70465.6" + attribute \src "libresoc.v:70117.3-70261.6" wire width 2 $2\SV_Etype[1:0] - attribute \src "libresoc.v:70466.3-70610.6" + attribute \src "libresoc.v:70262.3-70406.6" wire width 2 $2\SV_Ptype[1:0] - attribute \src "libresoc.v:70176.3-70320.6" + attribute \src "libresoc.v:69972.3-70116.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:73511.3-73655.6" + attribute \src "libresoc.v:73307.3-73451.6" wire $2\br[0:0] - attribute \src "libresoc.v:71191.3-71335.6" + attribute \src "libresoc.v:70987.3-71131.6" wire width 3 $2\cr_in[2:0] - attribute \src "libresoc.v:71336.3-71480.6" + attribute \src "libresoc.v:71132.3-71276.6" wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:72931.3-73075.6" + attribute \src "libresoc.v:72727.3-72871.6" wire width 2 $2\cry_in[1:0] - attribute \src "libresoc.v:73366.3-73510.6" + attribute \src "libresoc.v:73162.3-73306.6" wire $2\cry_out[0:0] - attribute \src "libresoc.v:70031.3-70175.6" + attribute \src "libresoc.v:69827.3-69971.6" wire width 5 $2\form[4:0] - attribute \src "libresoc.v:74526.3-74670.6" + attribute \src "libresoc.v:74322.3-74466.6" wire width 14 $2\function_unit[13:0] - attribute \src "libresoc.v:70611.3-70755.6" + attribute \src "libresoc.v:70407.3-70551.6" wire width 3 $2\in1_sel[2:0] - attribute \src "libresoc.v:70756.3-70900.6" + attribute \src "libresoc.v:70552.3-70696.6" wire width 4 $2\in2_sel[3:0] - attribute \src "libresoc.v:70901.3-71045.6" + attribute \src "libresoc.v:70697.3-70841.6" wire width 2 $2\in3_sel[1:0] - attribute \src "libresoc.v:74671.3-74815.6" + attribute \src "libresoc.v:74467.3-74611.6" wire width 7 $2\internal_op[6:0] - attribute \src "libresoc.v:73076.3-73220.6" + attribute \src "libresoc.v:72872.3-73016.6" wire $2\inv_a[0:0] - attribute \src "libresoc.v:73221.3-73365.6" + attribute \src "libresoc.v:73017.3-73161.6" wire $2\inv_out[0:0] - attribute \src "libresoc.v:73946.3-74090.6" + attribute \src "libresoc.v:73742.3-73886.6" wire $2\is_32b[0:0] - attribute \src "libresoc.v:72496.3-72640.6" + attribute \src "libresoc.v:72292.3-72436.6" wire width 4 $2\ldst_len[3:0] - attribute \src "libresoc.v:74236.3-74380.6" + attribute \src "libresoc.v:74032.3-74176.6" wire $2\lk[0:0] - attribute \src "libresoc.v:71046.3-71190.6" + attribute \src "libresoc.v:70842.3-70986.6" wire width 3 $2\out_sel[2:0] - attribute \src "libresoc.v:72786.3-72930.6" + attribute \src "libresoc.v:72582.3-72726.6" wire width 2 $2\rc_sel[1:0] - attribute \src "libresoc.v:73801.3-73945.6" + attribute \src "libresoc.v:73597.3-73741.6" wire $2\rsrv[0:0] - attribute \src "libresoc.v:74381.3-74525.6" + attribute \src "libresoc.v:74177.3-74321.6" wire $2\sgl_pipe[0:0] - attribute \src "libresoc.v:74091.3-74235.6" + attribute \src "libresoc.v:73887.3-74031.6" wire $2\sgn[0:0] - attribute \src "libresoc.v:73656.3-73800.6" + attribute \src "libresoc.v:73452.3-73596.6" wire $2\sgn_ext[0:0] - attribute \src "libresoc.v:72206.3-72350.6" + attribute \src "libresoc.v:72002.3-72146.6" wire width 3 $2\sv_cr_in[2:0] - attribute \src "libresoc.v:72351.3-72495.6" + attribute \src "libresoc.v:72147.3-72291.6" wire width 3 $2\sv_cr_out[2:0] - attribute \src "libresoc.v:71481.3-71625.6" + attribute \src "libresoc.v:71277.3-71421.6" wire width 3 $2\sv_in1[2:0] - attribute \src "libresoc.v:71626.3-71770.6" + attribute \src "libresoc.v:71422.3-71566.6" wire width 3 $2\sv_in2[2:0] - attribute \src "libresoc.v:71771.3-71915.6" + attribute \src "libresoc.v:71567.3-71711.6" wire width 3 $2\sv_in3[2:0] - attribute \src "libresoc.v:72061.3-72205.6" + attribute \src "libresoc.v:71857.3-72001.6" wire width 3 $2\sv_out2[2:0] - attribute \src "libresoc.v:71916.3-72060.6" + attribute \src "libresoc.v:71712.3-71856.6" wire width 3 $2\sv_out[2:0] - attribute \src "libresoc.v:72641.3-72785.6" + attribute \src "libresoc.v:72437.3-72581.6" wire width 2 $2\upd[1:0] - attribute \src "libresoc.v:69814.17-69814.211" - wire width 32 $ternary$libresoc.v:69814$3553_Y + attribute \src "libresoc.v:69610.17-69610.211" + wire width 32 $ternary$libresoc.v:69610$3553_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -112490,7 +112286,7 @@ module \dec$171 attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 15 \in3_sel - attribute \src "libresoc.v:66939.7-66939.15" + attribute \src "libresoc.v:66735.7-66735.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -112688,15 +112484,15 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 18 \upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:69814$3553 + cell $mux $ternary$libresoc.v:69610$3553 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:69814$3553_Y + connect \Y $ternary$libresoc.v:69610$3553_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:69815.9-69850.4" + attribute \src "libresoc.v:69611.9-69646.4" cell \dec19 \dec19 connect \dec19_SV_Etype \dec19_dec19_SV_Etype connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype @@ -112734,7 +112530,7 @@ module \dec$171 connect \opcode_in \dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69851.9-69886.4" + attribute \src "libresoc.v:69647.9-69682.4" cell \dec22 \dec22 connect \dec22_SV_Etype \dec22_dec22_SV_Etype connect \dec22_SV_Ptype \dec22_dec22_SV_Ptype @@ -112772,7 +112568,7 @@ module \dec$171 connect \opcode_in \dec22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69887.9-69922.4" + attribute \src "libresoc.v:69683.9-69718.4" cell \dec30 \dec30 connect \dec30_SV_Etype \dec30_dec30_SV_Etype connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype @@ -112810,7 +112606,7 @@ module \dec$171 connect \opcode_in \dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69923.9-69958.4" + attribute \src "libresoc.v:69719.9-69754.4" cell \dec31 \dec31 connect \dec31_SV_Etype \dec31_dec31_SV_Etype connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype @@ -112848,7 +112644,7 @@ module \dec$171 connect \opcode_in \dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69959.9-69994.4" + attribute \src "libresoc.v:69755.9-69790.4" cell \dec58 \dec58 connect \dec58_SV_Etype \dec58_dec58_SV_Etype connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype @@ -112886,7 +112682,7 @@ module \dec$171 connect \opcode_in \dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69995.9-70030.4" + attribute \src "libresoc.v:69791.9-69826.4" cell \dec62 \dec62 connect \dec62_SV_Etype \dec62_dec62_SV_Etype connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype @@ -112923,23 +112719,23 @@ module \dec$171 connect \dec62_upd \dec62_dec62_upd connect \opcode_in \dec62_opcode_in end - attribute \src "libresoc.v:66939.7-66939.20" - process $proc$libresoc.v:66939$3587 + attribute \src "libresoc.v:66735.7-66735.20" + process $proc$libresoc.v:66735$3587 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:70031.3-70175.6" - process $proc$libresoc.v:70031$3554 + attribute \src "libresoc.v:69827.3-69971.6" + process $proc$libresoc.v:69827$3554 assign { } { } assign { } { } assign { } { } assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:70032.5-70032.29" + attribute \src "libresoc.v:69828.5-69828.29" switch \initial - attribute \src "libresoc.v:70032.9-70032.17" + attribute \src "libresoc.v:69828.9-69828.17" case 1'1 case end @@ -113136,15 +112932,15 @@ module \dec$171 sync always update \form $0\form[4:0] end - attribute \src "libresoc.v:70176.3-70320.6" - process $proc$libresoc.v:70176$3555 + attribute \src "libresoc.v:69972.3-70116.6" + process $proc$libresoc.v:69972$3555 assign { } { } assign { } { } assign { } { } assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:70177.5-70177.29" + attribute \src "libresoc.v:69973.5-69973.29" switch \initial - attribute \src "libresoc.v:70177.9-70177.17" + attribute \src "libresoc.v:69973.9-69973.17" case 1'1 case end @@ -113340,15 +113136,15 @@ module \dec$171 sync always update \asmcode $0\asmcode[7:0] end - attribute \src "libresoc.v:70321.3-70465.6" - process $proc$libresoc.v:70321$3556 + attribute \src "libresoc.v:70117.3-70261.6" + process $proc$libresoc.v:70117$3556 assign { } { } assign { } { } assign { } { } assign $0\SV_Etype[1:0] $2\SV_Etype[1:0] - attribute \src "libresoc.v:70322.5-70322.29" + attribute \src "libresoc.v:70118.5-70118.29" switch \initial - attribute \src "libresoc.v:70322.9-70322.17" + attribute \src "libresoc.v:70118.9-70118.17" case 1'1 case end @@ -113545,15 +113341,15 @@ module \dec$171 sync always update \SV_Etype $0\SV_Etype[1:0] end - attribute \src "libresoc.v:70466.3-70610.6" - process $proc$libresoc.v:70466$3557 + attribute \src "libresoc.v:70262.3-70406.6" + process $proc$libresoc.v:70262$3557 assign { } { } assign { } { } assign { } { } assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0] - attribute \src "libresoc.v:70467.5-70467.29" + attribute \src "libresoc.v:70263.5-70263.29" switch \initial - attribute \src "libresoc.v:70467.9-70467.17" + attribute \src "libresoc.v:70263.9-70263.17" case 1'1 case end @@ -113750,15 +113546,15 @@ module \dec$171 sync always update \SV_Ptype $0\SV_Ptype[1:0] end - attribute \src "libresoc.v:70611.3-70755.6" - process $proc$libresoc.v:70611$3558 + attribute \src "libresoc.v:70407.3-70551.6" + process $proc$libresoc.v:70407$3558 assign { } { } assign { } { } assign { } { } assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:70612.5-70612.29" + attribute \src "libresoc.v:70408.5-70408.29" switch \initial - attribute \src "libresoc.v:70612.9-70612.17" + attribute \src "libresoc.v:70408.9-70408.17" case 1'1 case end @@ -113955,15 +113751,15 @@ module \dec$171 sync always update \in1_sel $0\in1_sel[2:0] end - attribute \src "libresoc.v:70756.3-70900.6" - process $proc$libresoc.v:70756$3559 + attribute \src "libresoc.v:70552.3-70696.6" + process $proc$libresoc.v:70552$3559 assign { } { } assign { } { } assign { } { } assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:70757.5-70757.29" + attribute \src "libresoc.v:70553.5-70553.29" switch \initial - attribute \src "libresoc.v:70757.9-70757.17" + attribute \src "libresoc.v:70553.9-70553.17" case 1'1 case end @@ -114160,15 +113956,15 @@ module \dec$171 sync always update \in2_sel $0\in2_sel[3:0] end - attribute \src "libresoc.v:70901.3-71045.6" - process $proc$libresoc.v:70901$3560 + attribute \src "libresoc.v:70697.3-70841.6" + process $proc$libresoc.v:70697$3560 assign { } { } assign { } { } assign { } { } assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:70902.5-70902.29" + attribute \src "libresoc.v:70698.5-70698.29" switch \initial - attribute \src "libresoc.v:70902.9-70902.17" + attribute \src "libresoc.v:70698.9-70698.17" case 1'1 case end @@ -114365,15 +114161,15 @@ module \dec$171 sync always update \in3_sel $0\in3_sel[1:0] end - attribute \src "libresoc.v:71046.3-71190.6" - process $proc$libresoc.v:71046$3561 + attribute \src "libresoc.v:70842.3-70986.6" + process $proc$libresoc.v:70842$3561 assign { } { } assign { } { } assign { } { } assign $0\out_sel[2:0] $2\out_sel[2:0] - attribute \src "libresoc.v:71047.5-71047.29" + attribute \src "libresoc.v:70843.5-70843.29" switch \initial - attribute \src "libresoc.v:71047.9-71047.17" + attribute \src "libresoc.v:70843.9-70843.17" case 1'1 case end @@ -114570,15 +114366,15 @@ module \dec$171 sync always update \out_sel $0\out_sel[2:0] end - attribute \src "libresoc.v:71191.3-71335.6" - process $proc$libresoc.v:71191$3562 + attribute \src "libresoc.v:70987.3-71131.6" + process $proc$libresoc.v:70987$3562 assign { } { } assign { } { } assign { } { } assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:71192.5-71192.29" + attribute \src "libresoc.v:70988.5-70988.29" switch \initial - attribute \src "libresoc.v:71192.9-71192.17" + attribute \src "libresoc.v:70988.9-70988.17" case 1'1 case end @@ -114775,15 +114571,15 @@ module \dec$171 sync always update \cr_in $0\cr_in[2:0] end - attribute \src "libresoc.v:71336.3-71480.6" - process $proc$libresoc.v:71336$3563 + attribute \src "libresoc.v:71132.3-71276.6" + process $proc$libresoc.v:71132$3563 assign { } { } assign { } { } assign { } { } assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:71337.5-71337.29" + attribute \src "libresoc.v:71133.5-71133.29" switch \initial - attribute \src "libresoc.v:71337.9-71337.17" + attribute \src "libresoc.v:71133.9-71133.17" case 1'1 case end @@ -114980,15 +114776,15 @@ module \dec$171 sync always update \cr_out $0\cr_out[2:0] end - attribute \src "libresoc.v:71481.3-71625.6" - process $proc$libresoc.v:71481$3564 + attribute \src "libresoc.v:71277.3-71421.6" + process $proc$libresoc.v:71277$3564 assign { } { } assign { } { } assign { } { } assign $0\sv_in1[2:0] $2\sv_in1[2:0] - attribute \src "libresoc.v:71482.5-71482.29" + attribute \src "libresoc.v:71278.5-71278.29" switch \initial - attribute \src "libresoc.v:71482.9-71482.17" + attribute \src "libresoc.v:71278.9-71278.17" case 1'1 case end @@ -115185,15 +114981,15 @@ module \dec$171 sync always update \sv_in1 $0\sv_in1[2:0] end - attribute \src "libresoc.v:71626.3-71770.6" - process $proc$libresoc.v:71626$3565 + attribute \src "libresoc.v:71422.3-71566.6" + process $proc$libresoc.v:71422$3565 assign { } { } assign { } { } assign { } { } assign $0\sv_in2[2:0] $2\sv_in2[2:0] - attribute \src "libresoc.v:71627.5-71627.29" + attribute \src "libresoc.v:71423.5-71423.29" switch \initial - attribute \src "libresoc.v:71627.9-71627.17" + attribute \src "libresoc.v:71423.9-71423.17" case 1'1 case end @@ -115390,15 +115186,15 @@ module \dec$171 sync always update \sv_in2 $0\sv_in2[2:0] end - attribute \src "libresoc.v:71771.3-71915.6" - process $proc$libresoc.v:71771$3566 + attribute \src "libresoc.v:71567.3-71711.6" + process $proc$libresoc.v:71567$3566 assign { } { } assign { } { } assign { } { } assign $0\sv_in3[2:0] $2\sv_in3[2:0] - attribute \src "libresoc.v:71772.5-71772.29" + attribute \src "libresoc.v:71568.5-71568.29" switch \initial - attribute \src "libresoc.v:71772.9-71772.17" + attribute \src "libresoc.v:71568.9-71568.17" case 1'1 case end @@ -115595,15 +115391,15 @@ module \dec$171 sync always update \sv_in3 $0\sv_in3[2:0] end - attribute \src "libresoc.v:71916.3-72060.6" - process $proc$libresoc.v:71916$3567 + attribute \src "libresoc.v:71712.3-71856.6" + process $proc$libresoc.v:71712$3567 assign { } { } assign { } { } assign { } { } assign $0\sv_out[2:0] $2\sv_out[2:0] - attribute \src "libresoc.v:71917.5-71917.29" + attribute \src "libresoc.v:71713.5-71713.29" switch \initial - attribute \src "libresoc.v:71917.9-71917.17" + attribute \src "libresoc.v:71713.9-71713.17" case 1'1 case end @@ -115800,15 +115596,15 @@ module \dec$171 sync always update \sv_out $0\sv_out[2:0] end - attribute \src "libresoc.v:72061.3-72205.6" - process $proc$libresoc.v:72061$3568 + attribute \src "libresoc.v:71857.3-72001.6" + process $proc$libresoc.v:71857$3568 assign { } { } assign { } { } assign { } { } assign $0\sv_out2[2:0] $2\sv_out2[2:0] - attribute \src "libresoc.v:72062.5-72062.29" + attribute \src "libresoc.v:71858.5-71858.29" switch \initial - attribute \src "libresoc.v:72062.9-72062.17" + attribute \src "libresoc.v:71858.9-71858.17" case 1'1 case end @@ -116005,15 +115801,15 @@ module \dec$171 sync always update \sv_out2 $0\sv_out2[2:0] end - attribute \src "libresoc.v:72206.3-72350.6" - process $proc$libresoc.v:72206$3569 + attribute \src "libresoc.v:72002.3-72146.6" + process $proc$libresoc.v:72002$3569 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0] - attribute \src "libresoc.v:72207.5-72207.29" + attribute \src "libresoc.v:72003.5-72003.29" switch \initial - attribute \src "libresoc.v:72207.9-72207.17" + attribute \src "libresoc.v:72003.9-72003.17" case 1'1 case end @@ -116210,15 +116006,15 @@ module \dec$171 sync always update \sv_cr_in $0\sv_cr_in[2:0] end - attribute \src "libresoc.v:72351.3-72495.6" - process $proc$libresoc.v:72351$3570 + attribute \src "libresoc.v:72147.3-72291.6" + process $proc$libresoc.v:72147$3570 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0] - attribute \src "libresoc.v:72352.5-72352.29" + attribute \src "libresoc.v:72148.5-72148.29" switch \initial - attribute \src "libresoc.v:72352.9-72352.17" + attribute \src "libresoc.v:72148.9-72148.17" case 1'1 case end @@ -116415,15 +116211,15 @@ module \dec$171 sync always update \sv_cr_out $0\sv_cr_out[2:0] end - attribute \src "libresoc.v:72496.3-72640.6" - process $proc$libresoc.v:72496$3571 + attribute \src "libresoc.v:72292.3-72436.6" + process $proc$libresoc.v:72292$3571 assign { } { } assign { } { } assign { } { } assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:72497.5-72497.29" + attribute \src "libresoc.v:72293.5-72293.29" switch \initial - attribute \src "libresoc.v:72497.9-72497.17" + attribute \src "libresoc.v:72293.9-72293.17" case 1'1 case end @@ -116620,15 +116416,15 @@ module \dec$171 sync always update \ldst_len $0\ldst_len[3:0] end - attribute \src "libresoc.v:72641.3-72785.6" - process $proc$libresoc.v:72641$3572 + attribute \src "libresoc.v:72437.3-72581.6" + process $proc$libresoc.v:72437$3572 assign { } { } assign { } { } assign { } { } assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:72642.5-72642.29" + attribute \src "libresoc.v:72438.5-72438.29" switch \initial - attribute \src "libresoc.v:72642.9-72642.17" + attribute \src "libresoc.v:72438.9-72438.17" case 1'1 case end @@ -116825,15 +116621,15 @@ module \dec$171 sync always update \upd $0\upd[1:0] end - attribute \src "libresoc.v:72786.3-72930.6" - process $proc$libresoc.v:72786$3573 + attribute \src "libresoc.v:72582.3-72726.6" + process $proc$libresoc.v:72582$3573 assign { } { } assign { } { } assign { } { } assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:72787.5-72787.29" + attribute \src "libresoc.v:72583.5-72583.29" switch \initial - attribute \src "libresoc.v:72787.9-72787.17" + attribute \src "libresoc.v:72583.9-72583.17" case 1'1 case end @@ -117030,15 +116826,15 @@ module \dec$171 sync always update \rc_sel $0\rc_sel[1:0] end - attribute \src "libresoc.v:72931.3-73075.6" - process $proc$libresoc.v:72931$3574 + attribute \src "libresoc.v:72727.3-72871.6" + process $proc$libresoc.v:72727$3574 assign { } { } assign { } { } assign { } { } assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:72932.5-72932.29" + attribute \src "libresoc.v:72728.5-72728.29" switch \initial - attribute \src "libresoc.v:72932.9-72932.17" + attribute \src "libresoc.v:72728.9-72728.17" case 1'1 case end @@ -117235,15 +117031,15 @@ module \dec$171 sync always update \cry_in $0\cry_in[1:0] end - attribute \src "libresoc.v:73076.3-73220.6" - process $proc$libresoc.v:73076$3575 + attribute \src "libresoc.v:72872.3-73016.6" + process $proc$libresoc.v:72872$3575 assign { } { } assign { } { } assign { } { } assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:73077.5-73077.29" + attribute \src "libresoc.v:72873.5-72873.29" switch \initial - attribute \src "libresoc.v:73077.9-73077.17" + attribute \src "libresoc.v:72873.9-72873.17" case 1'1 case end @@ -117440,15 +117236,15 @@ module \dec$171 sync always update \inv_a $0\inv_a[0:0] end - attribute \src "libresoc.v:73221.3-73365.6" - process $proc$libresoc.v:73221$3576 + attribute \src "libresoc.v:73017.3-73161.6" + process $proc$libresoc.v:73017$3576 assign { } { } assign { } { } assign { } { } assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:73222.5-73222.29" + attribute \src "libresoc.v:73018.5-73018.29" switch \initial - attribute \src "libresoc.v:73222.9-73222.17" + attribute \src "libresoc.v:73018.9-73018.17" case 1'1 case end @@ -117645,15 +117441,15 @@ module \dec$171 sync always update \inv_out $0\inv_out[0:0] end - attribute \src "libresoc.v:73366.3-73510.6" - process $proc$libresoc.v:73366$3577 + attribute \src "libresoc.v:73162.3-73306.6" + process $proc$libresoc.v:73162$3577 assign { } { } assign { } { } assign { } { } assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:73367.5-73367.29" + attribute \src "libresoc.v:73163.5-73163.29" switch \initial - attribute \src "libresoc.v:73367.9-73367.17" + attribute \src "libresoc.v:73163.9-73163.17" case 1'1 case end @@ -117850,15 +117646,15 @@ module \dec$171 sync always update \cry_out $0\cry_out[0:0] end - attribute \src "libresoc.v:73511.3-73655.6" - process $proc$libresoc.v:73511$3578 + attribute \src "libresoc.v:73307.3-73451.6" + process $proc$libresoc.v:73307$3578 assign { } { } assign { } { } assign { } { } assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:73512.5-73512.29" + attribute \src "libresoc.v:73308.5-73308.29" switch \initial - attribute \src "libresoc.v:73512.9-73512.17" + attribute \src "libresoc.v:73308.9-73308.17" case 1'1 case end @@ -118055,15 +117851,15 @@ module \dec$171 sync always update \br $0\br[0:0] end - attribute \src "libresoc.v:73656.3-73800.6" - process $proc$libresoc.v:73656$3579 + attribute \src "libresoc.v:73452.3-73596.6" + process $proc$libresoc.v:73452$3579 assign { } { } assign { } { } assign { } { } assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:73657.5-73657.29" + attribute \src "libresoc.v:73453.5-73453.29" switch \initial - attribute \src "libresoc.v:73657.9-73657.17" + attribute \src "libresoc.v:73453.9-73453.17" case 1'1 case end @@ -118260,15 +118056,15 @@ module \dec$171 sync always update \sgn_ext $0\sgn_ext[0:0] end - attribute \src "libresoc.v:73801.3-73945.6" - process $proc$libresoc.v:73801$3580 + attribute \src "libresoc.v:73597.3-73741.6" + process $proc$libresoc.v:73597$3580 assign { } { } assign { } { } assign { } { } assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:73802.5-73802.29" + attribute \src "libresoc.v:73598.5-73598.29" switch \initial - attribute \src "libresoc.v:73802.9-73802.17" + attribute \src "libresoc.v:73598.9-73598.17" case 1'1 case end @@ -118465,15 +118261,15 @@ module \dec$171 sync always update \rsrv $0\rsrv[0:0] end - attribute \src "libresoc.v:73946.3-74090.6" - process $proc$libresoc.v:73946$3581 + attribute \src "libresoc.v:73742.3-73886.6" + process $proc$libresoc.v:73742$3581 assign { } { } assign { } { } assign { } { } assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:73947.5-73947.29" + attribute \src "libresoc.v:73743.5-73743.29" switch \initial - attribute \src "libresoc.v:73947.9-73947.17" + attribute \src "libresoc.v:73743.9-73743.17" case 1'1 case end @@ -118670,15 +118466,15 @@ module \dec$171 sync always update \is_32b $0\is_32b[0:0] end - attribute \src "libresoc.v:74091.3-74235.6" - process $proc$libresoc.v:74091$3582 + attribute \src "libresoc.v:73887.3-74031.6" + process $proc$libresoc.v:73887$3582 assign { } { } assign { } { } assign { } { } assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:74092.5-74092.29" + attribute \src "libresoc.v:73888.5-73888.29" switch \initial - attribute \src "libresoc.v:74092.9-74092.17" + attribute \src "libresoc.v:73888.9-73888.17" case 1'1 case end @@ -118875,15 +118671,15 @@ module \dec$171 sync always update \sgn $0\sgn[0:0] end - attribute \src "libresoc.v:74236.3-74380.6" - process $proc$libresoc.v:74236$3583 + attribute \src "libresoc.v:74032.3-74176.6" + process $proc$libresoc.v:74032$3583 assign { } { } assign { } { } assign { } { } assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:74237.5-74237.29" + attribute \src "libresoc.v:74033.5-74033.29" switch \initial - attribute \src "libresoc.v:74237.9-74237.17" + attribute \src "libresoc.v:74033.9-74033.17" case 1'1 case end @@ -119080,15 +118876,15 @@ module \dec$171 sync always update \lk $0\lk[0:0] end - attribute \src "libresoc.v:74381.3-74525.6" - process $proc$libresoc.v:74381$3584 + attribute \src "libresoc.v:74177.3-74321.6" + process $proc$libresoc.v:74177$3584 assign { } { } assign { } { } assign { } { } assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:74382.5-74382.29" + attribute \src "libresoc.v:74178.5-74178.29" switch \initial - attribute \src "libresoc.v:74382.9-74382.17" + attribute \src "libresoc.v:74178.9-74178.17" case 1'1 case end @@ -119285,15 +119081,15 @@ module \dec$171 sync always update \sgl_pipe $0\sgl_pipe[0:0] end - attribute \src "libresoc.v:74526.3-74670.6" - process $proc$libresoc.v:74526$3585 + attribute \src "libresoc.v:74322.3-74466.6" + process $proc$libresoc.v:74322$3585 assign { } { } assign { } { } assign { } { } assign $0\function_unit[13:0] $2\function_unit[13:0] - attribute \src "libresoc.v:74527.5-74527.29" + attribute \src "libresoc.v:74323.5-74323.29" switch \initial - attribute \src "libresoc.v:74527.9-74527.17" + attribute \src "libresoc.v:74323.9-74323.17" case 1'1 case end @@ -119490,15 +119286,15 @@ module \dec$171 sync always update \function_unit $0\function_unit[13:0] end - attribute \src "libresoc.v:74671.3-74815.6" - process $proc$libresoc.v:74671$3586 + attribute \src "libresoc.v:74467.3-74611.6" + process $proc$libresoc.v:74467$3586 assign { } { } assign { } { } assign { } { } assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:74672.5-74672.29" + attribute \src "libresoc.v:74468.5-74468.29" switch \initial - attribute \src "libresoc.v:74672.9-74672.17" + attribute \src "libresoc.v:74468.9-74468.17" case 1'1 case end @@ -119695,7 +119491,7 @@ module \dec$171 sync always update \internal_op $0\internal_op[6:0] end - connect \$2 $ternary$libresoc.v:69814$3553_Y + connect \$2 $ternary$libresoc.v:69610$3553_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -120039,144 +119835,144 @@ module \dec$171 connect \dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:75162.1-77228.10" +attribute \src "libresoc.v:74958.1-77024.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" attribute \generator "nMigen" module \dec19 - attribute \src "libresoc.v:76915.3-76966.6" + attribute \src "libresoc.v:76711.3-76762.6" wire width 2 $0\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76967.3-77018.6" + attribute \src "libresoc.v:76763.3-76814.6" wire width 2 $0\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76291.3-76342.6" + attribute \src "libresoc.v:76087.3-76138.6" wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:76499.3-76550.6" + attribute \src "libresoc.v:76295.3-76346.6" wire $0\dec19_br[0:0] - attribute \src "libresoc.v:75563.3-75614.6" + attribute \src "libresoc.v:75359.3-75410.6" wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:75615.3-75666.6" + attribute \src "libresoc.v:75411.3-75462.6" wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:76239.3-76290.6" + attribute \src "libresoc.v:76035.3-76086.6" wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:76447.3-76498.6" + attribute \src "libresoc.v:76243.3-76294.6" wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:76655.3-76706.6" + attribute \src "libresoc.v:76451.3-76502.6" wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:75511.3-75562.6" + attribute \src "libresoc.v:75307.3-75358.6" wire width 14 $0\dec19_function_unit[13:0] - attribute \src "libresoc.v:77019.3-77070.6" + attribute \src "libresoc.v:76815.3-76866.6" wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:77071.3-77122.6" + attribute \src "libresoc.v:76867.3-76918.6" wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:77123.3-77174.6" + attribute \src "libresoc.v:76919.3-76970.6" wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:76083.3-76134.6" + attribute \src "libresoc.v:75879.3-75930.6" wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:76343.3-76394.6" + attribute \src "libresoc.v:76139.3-76190.6" wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:76395.3-76446.6" + attribute \src "libresoc.v:76191.3-76242.6" wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:76707.3-76758.6" + attribute \src "libresoc.v:76503.3-76554.6" wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:76031.3-76082.6" + attribute \src "libresoc.v:75827.3-75878.6" wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76811.3-76862.6" + attribute \src "libresoc.v:76607.3-76658.6" wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:77175.3-77226.6" + attribute \src "libresoc.v:76971.3-77022.6" wire width 3 $0\dec19_out_sel[2:0] - attribute \src "libresoc.v:76187.3-76238.6" + attribute \src "libresoc.v:75983.3-76034.6" wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76603.3-76654.6" + attribute \src "libresoc.v:76399.3-76450.6" wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:76863.3-76914.6" + attribute \src "libresoc.v:76659.3-76710.6" wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76759.3-76810.6" + attribute \src "libresoc.v:76555.3-76606.6" wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:76551.3-76602.6" + attribute \src "libresoc.v:76347.3-76398.6" wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:75927.3-75978.6" + attribute \src "libresoc.v:75723.3-75774.6" wire width 3 $0\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75979.3-76030.6" + attribute \src "libresoc.v:75775.3-75826.6" wire width 3 $0\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75667.3-75718.6" + attribute \src "libresoc.v:75463.3-75514.6" wire width 3 $0\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75719.3-75770.6" + attribute \src "libresoc.v:75515.3-75566.6" wire width 3 $0\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75771.3-75822.6" + attribute \src "libresoc.v:75567.3-75618.6" wire width 3 $0\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75875.3-75926.6" + attribute \src "libresoc.v:75671.3-75722.6" wire width 3 $0\dec19_sv_out2[2:0] - attribute \src "libresoc.v:75823.3-75874.6" + attribute \src "libresoc.v:75619.3-75670.6" wire width 3 $0\dec19_sv_out[2:0] - attribute \src "libresoc.v:76135.3-76186.6" + attribute \src "libresoc.v:75931.3-75982.6" wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:75163.7-75163.20" + attribute \src "libresoc.v:74959.7-74959.20" wire $0\initial[0:0] - attribute \src "libresoc.v:76915.3-76966.6" + attribute \src "libresoc.v:76711.3-76762.6" wire width 2 $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76967.3-77018.6" + attribute \src "libresoc.v:76763.3-76814.6" wire width 2 $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76291.3-76342.6" + attribute \src "libresoc.v:76087.3-76138.6" wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:76499.3-76550.6" + attribute \src "libresoc.v:76295.3-76346.6" wire $1\dec19_br[0:0] - attribute \src "libresoc.v:75563.3-75614.6" + attribute \src "libresoc.v:75359.3-75410.6" wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:75615.3-75666.6" + attribute \src "libresoc.v:75411.3-75462.6" wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:76239.3-76290.6" + attribute \src "libresoc.v:76035.3-76086.6" wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:76447.3-76498.6" + attribute \src "libresoc.v:76243.3-76294.6" wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:76655.3-76706.6" + attribute \src "libresoc.v:76451.3-76502.6" wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:75511.3-75562.6" + attribute \src "libresoc.v:75307.3-75358.6" wire width 14 $1\dec19_function_unit[13:0] - attribute \src "libresoc.v:77019.3-77070.6" + attribute \src "libresoc.v:76815.3-76866.6" wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:77071.3-77122.6" + attribute \src "libresoc.v:76867.3-76918.6" wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:77123.3-77174.6" + attribute \src "libresoc.v:76919.3-76970.6" wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:76083.3-76134.6" + attribute \src "libresoc.v:75879.3-75930.6" wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:76343.3-76394.6" + attribute \src "libresoc.v:76139.3-76190.6" wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:76395.3-76446.6" + attribute \src "libresoc.v:76191.3-76242.6" wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:76707.3-76758.6" + attribute \src "libresoc.v:76503.3-76554.6" wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:76031.3-76082.6" + attribute \src "libresoc.v:75827.3-75878.6" wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76811.3-76862.6" + attribute \src "libresoc.v:76607.3-76658.6" wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:77175.3-77226.6" + attribute \src "libresoc.v:76971.3-77022.6" wire width 3 $1\dec19_out_sel[2:0] - attribute \src "libresoc.v:76187.3-76238.6" + attribute \src "libresoc.v:75983.3-76034.6" wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76603.3-76654.6" + attribute \src "libresoc.v:76399.3-76450.6" wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:76863.3-76914.6" + attribute \src "libresoc.v:76659.3-76710.6" wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76759.3-76810.6" + attribute \src "libresoc.v:76555.3-76606.6" wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:76551.3-76602.6" + attribute \src "libresoc.v:76347.3-76398.6" wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:75927.3-75978.6" + attribute \src "libresoc.v:75723.3-75774.6" wire width 3 $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75979.3-76030.6" + attribute \src "libresoc.v:75775.3-75826.6" wire width 3 $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75667.3-75718.6" + attribute \src "libresoc.v:75463.3-75514.6" wire width 3 $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75719.3-75770.6" + attribute \src "libresoc.v:75515.3-75566.6" wire width 3 $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75771.3-75822.6" + attribute \src "libresoc.v:75567.3-75618.6" wire width 3 $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75875.3-75926.6" + attribute \src "libresoc.v:75671.3-75722.6" wire width 3 $1\dec19_sv_out2[2:0] - attribute \src "libresoc.v:75823.3-75874.6" + attribute \src "libresoc.v:75619.3-75670.6" wire width 3 $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:76135.3-76186.6" + attribute \src "libresoc.v:75931.3-75982.6" wire width 2 $1\dec19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -120488,28 +120284,28 @@ module \dec19 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec19_upd - attribute \src "libresoc.v:75163.7-75163.15" + attribute \src "libresoc.v:74959.7-74959.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch - attribute \src "libresoc.v:75163.7-75163.20" - process $proc$libresoc.v:75163$3621 + attribute \src "libresoc.v:74959.7-74959.20" + process $proc$libresoc.v:74959$3621 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:75511.3-75562.6" - process $proc$libresoc.v:75511$3588 + attribute \src "libresoc.v:75307.3-75358.6" + process $proc$libresoc.v:75307$3588 assign { } { } assign { } { } assign $0\dec19_function_unit[13:0] $1\dec19_function_unit[13:0] - attribute \src "libresoc.v:75512.5-75512.29" + attribute \src "libresoc.v:75308.5-75308.29" switch \initial - attribute \src "libresoc.v:75512.9-75512.17" + attribute \src "libresoc.v:75308.9-75308.17" case 1'1 case end @@ -120581,14 +120377,14 @@ module \dec19 sync always update \dec19_function_unit $0\dec19_function_unit[13:0] end - attribute \src "libresoc.v:75563.3-75614.6" - process $proc$libresoc.v:75563$3589 + attribute \src "libresoc.v:75359.3-75410.6" + process $proc$libresoc.v:75359$3589 assign { } { } assign { } { } assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:75564.5-75564.29" + attribute \src "libresoc.v:75360.5-75360.29" switch \initial - attribute \src "libresoc.v:75564.9-75564.17" + attribute \src "libresoc.v:75360.9-75360.17" case 1'1 case end @@ -120660,14 +120456,14 @@ module \dec19 sync always update \dec19_cr_in $0\dec19_cr_in[2:0] end - attribute \src "libresoc.v:75615.3-75666.6" - process $proc$libresoc.v:75615$3590 + attribute \src "libresoc.v:75411.3-75462.6" + process $proc$libresoc.v:75411$3590 assign { } { } assign { } { } assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:75616.5-75616.29" + attribute \src "libresoc.v:75412.5-75412.29" switch \initial - attribute \src "libresoc.v:75616.9-75616.17" + attribute \src "libresoc.v:75412.9-75412.17" case 1'1 case end @@ -120739,14 +120535,14 @@ module \dec19 sync always update \dec19_cr_out $0\dec19_cr_out[2:0] end - attribute \src "libresoc.v:75667.3-75718.6" - process $proc$libresoc.v:75667$3591 + attribute \src "libresoc.v:75463.3-75514.6" + process $proc$libresoc.v:75463$3591 assign { } { } assign { } { } assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75668.5-75668.29" + attribute \src "libresoc.v:75464.5-75464.29" switch \initial - attribute \src "libresoc.v:75668.9-75668.17" + attribute \src "libresoc.v:75464.9-75464.17" case 1'1 case end @@ -120818,14 +120614,14 @@ module \dec19 sync always update \dec19_sv_in1 $0\dec19_sv_in1[2:0] end - attribute \src "libresoc.v:75719.3-75770.6" - process $proc$libresoc.v:75719$3592 + attribute \src "libresoc.v:75515.3-75566.6" + process $proc$libresoc.v:75515$3592 assign { } { } assign { } { } assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75720.5-75720.29" + attribute \src "libresoc.v:75516.5-75516.29" switch \initial - attribute \src "libresoc.v:75720.9-75720.17" + attribute \src "libresoc.v:75516.9-75516.17" case 1'1 case end @@ -120897,14 +120693,14 @@ module \dec19 sync always update \dec19_sv_in2 $0\dec19_sv_in2[2:0] end - attribute \src "libresoc.v:75771.3-75822.6" - process $proc$libresoc.v:75771$3593 + attribute \src "libresoc.v:75567.3-75618.6" + process $proc$libresoc.v:75567$3593 assign { } { } assign { } { } assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75772.5-75772.29" + attribute \src "libresoc.v:75568.5-75568.29" switch \initial - attribute \src "libresoc.v:75772.9-75772.17" + attribute \src "libresoc.v:75568.9-75568.17" case 1'1 case end @@ -120976,14 +120772,14 @@ module \dec19 sync always update \dec19_sv_in3 $0\dec19_sv_in3[2:0] end - attribute \src "libresoc.v:75823.3-75874.6" - process $proc$libresoc.v:75823$3594 + attribute \src "libresoc.v:75619.3-75670.6" + process $proc$libresoc.v:75619$3594 assign { } { } assign { } { } assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:75824.5-75824.29" + attribute \src "libresoc.v:75620.5-75620.29" switch \initial - attribute \src "libresoc.v:75824.9-75824.17" + attribute \src "libresoc.v:75620.9-75620.17" case 1'1 case end @@ -121055,14 +120851,14 @@ module \dec19 sync always update \dec19_sv_out $0\dec19_sv_out[2:0] end - attribute \src "libresoc.v:75875.3-75926.6" - process $proc$libresoc.v:75875$3595 + attribute \src "libresoc.v:75671.3-75722.6" + process $proc$libresoc.v:75671$3595 assign { } { } assign { } { } assign $0\dec19_sv_out2[2:0] $1\dec19_sv_out2[2:0] - attribute \src "libresoc.v:75876.5-75876.29" + attribute \src "libresoc.v:75672.5-75672.29" switch \initial - attribute \src "libresoc.v:75876.9-75876.17" + attribute \src "libresoc.v:75672.9-75672.17" case 1'1 case end @@ -121134,14 +120930,14 @@ module \dec19 sync always update \dec19_sv_out2 $0\dec19_sv_out2[2:0] end - attribute \src "libresoc.v:75927.3-75978.6" - process $proc$libresoc.v:75927$3596 + attribute \src "libresoc.v:75723.3-75774.6" + process $proc$libresoc.v:75723$3596 assign { } { } assign { } { } assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75928.5-75928.29" + attribute \src "libresoc.v:75724.5-75724.29" switch \initial - attribute \src "libresoc.v:75928.9-75928.17" + attribute \src "libresoc.v:75724.9-75724.17" case 1'1 case end @@ -121213,14 +121009,14 @@ module \dec19 sync always update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0] end - attribute \src "libresoc.v:75979.3-76030.6" - process $proc$libresoc.v:75979$3597 + attribute \src "libresoc.v:75775.3-75826.6" + process $proc$libresoc.v:75775$3597 assign { } { } assign { } { } assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75980.5-75980.29" + attribute \src "libresoc.v:75776.5-75776.29" switch \initial - attribute \src "libresoc.v:75980.9-75980.17" + attribute \src "libresoc.v:75776.9-75776.17" case 1'1 case end @@ -121292,14 +121088,14 @@ module \dec19 sync always update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0] end - attribute \src "libresoc.v:76031.3-76082.6" - process $proc$libresoc.v:76031$3598 + attribute \src "libresoc.v:75827.3-75878.6" + process $proc$libresoc.v:75827$3598 assign { } { } assign { } { } assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76032.5-76032.29" + attribute \src "libresoc.v:75828.5-75828.29" switch \initial - attribute \src "libresoc.v:76032.9-76032.17" + attribute \src "libresoc.v:75828.9-75828.17" case 1'1 case end @@ -121371,14 +121167,14 @@ module \dec19 sync always update \dec19_ldst_len $0\dec19_ldst_len[3:0] end - attribute \src "libresoc.v:76083.3-76134.6" - process $proc$libresoc.v:76083$3599 + attribute \src "libresoc.v:75879.3-75930.6" + process $proc$libresoc.v:75879$3599 assign { } { } assign { } { } assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:76084.5-76084.29" + attribute \src "libresoc.v:75880.5-75880.29" switch \initial - attribute \src "libresoc.v:76084.9-76084.17" + attribute \src "libresoc.v:75880.9-75880.17" case 1'1 case end @@ -121450,14 +121246,14 @@ module \dec19 sync always update \dec19_internal_op $0\dec19_internal_op[6:0] end - attribute \src "libresoc.v:76135.3-76186.6" - process $proc$libresoc.v:76135$3600 + attribute \src "libresoc.v:75931.3-75982.6" + process $proc$libresoc.v:75931$3600 assign { } { } assign { } { } assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:76136.5-76136.29" + attribute \src "libresoc.v:75932.5-75932.29" switch \initial - attribute \src "libresoc.v:76136.9-76136.17" + attribute \src "libresoc.v:75932.9-75932.17" case 1'1 case end @@ -121529,14 +121325,14 @@ module \dec19 sync always update \dec19_upd $0\dec19_upd[1:0] end - attribute \src "libresoc.v:76187.3-76238.6" - process $proc$libresoc.v:76187$3601 + attribute \src "libresoc.v:75983.3-76034.6" + process $proc$libresoc.v:75983$3601 assign { } { } assign { } { } assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76188.5-76188.29" + attribute \src "libresoc.v:75984.5-75984.29" switch \initial - attribute \src "libresoc.v:76188.9-76188.17" + attribute \src "libresoc.v:75984.9-75984.17" case 1'1 case end @@ -121608,14 +121404,14 @@ module \dec19 sync always update \dec19_rc_sel $0\dec19_rc_sel[1:0] end - attribute \src "libresoc.v:76239.3-76290.6" - process $proc$libresoc.v:76239$3602 + attribute \src "libresoc.v:76035.3-76086.6" + process $proc$libresoc.v:76035$3602 assign { } { } assign { } { } assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:76240.5-76240.29" + attribute \src "libresoc.v:76036.5-76036.29" switch \initial - attribute \src "libresoc.v:76240.9-76240.17" + attribute \src "libresoc.v:76036.9-76036.17" case 1'1 case end @@ -121687,14 +121483,14 @@ module \dec19 sync always update \dec19_cry_in $0\dec19_cry_in[1:0] end - attribute \src "libresoc.v:76291.3-76342.6" - process $proc$libresoc.v:76291$3603 + attribute \src "libresoc.v:76087.3-76138.6" + process $proc$libresoc.v:76087$3603 assign { } { } assign { } { } assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:76292.5-76292.29" + attribute \src "libresoc.v:76088.5-76088.29" switch \initial - attribute \src "libresoc.v:76292.9-76292.17" + attribute \src "libresoc.v:76088.9-76088.17" case 1'1 case end @@ -121766,14 +121562,14 @@ module \dec19 sync always update \dec19_asmcode $0\dec19_asmcode[7:0] end - attribute \src "libresoc.v:76343.3-76394.6" - process $proc$libresoc.v:76343$3604 + attribute \src "libresoc.v:76139.3-76190.6" + process $proc$libresoc.v:76139$3604 assign { } { } assign { } { } assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:76344.5-76344.29" + attribute \src "libresoc.v:76140.5-76140.29" switch \initial - attribute \src "libresoc.v:76344.9-76344.17" + attribute \src "libresoc.v:76140.9-76140.17" case 1'1 case end @@ -121845,14 +121641,14 @@ module \dec19 sync always update \dec19_inv_a $0\dec19_inv_a[0:0] end - attribute \src "libresoc.v:76395.3-76446.6" - process $proc$libresoc.v:76395$3605 + attribute \src "libresoc.v:76191.3-76242.6" + process $proc$libresoc.v:76191$3605 assign { } { } assign { } { } assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:76396.5-76396.29" + attribute \src "libresoc.v:76192.5-76192.29" switch \initial - attribute \src "libresoc.v:76396.9-76396.17" + attribute \src "libresoc.v:76192.9-76192.17" case 1'1 case end @@ -121924,14 +121720,14 @@ module \dec19 sync always update \dec19_inv_out $0\dec19_inv_out[0:0] end - attribute \src "libresoc.v:76447.3-76498.6" - process $proc$libresoc.v:76447$3606 + attribute \src "libresoc.v:76243.3-76294.6" + process $proc$libresoc.v:76243$3606 assign { } { } assign { } { } assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:76448.5-76448.29" + attribute \src "libresoc.v:76244.5-76244.29" switch \initial - attribute \src "libresoc.v:76448.9-76448.17" + attribute \src "libresoc.v:76244.9-76244.17" case 1'1 case end @@ -122003,14 +121799,14 @@ module \dec19 sync always update \dec19_cry_out $0\dec19_cry_out[0:0] end - attribute \src "libresoc.v:76499.3-76550.6" - process $proc$libresoc.v:76499$3607 + attribute \src "libresoc.v:76295.3-76346.6" + process $proc$libresoc.v:76295$3607 assign { } { } assign { } { } assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:76500.5-76500.29" + attribute \src "libresoc.v:76296.5-76296.29" switch \initial - attribute \src "libresoc.v:76500.9-76500.17" + attribute \src "libresoc.v:76296.9-76296.17" case 1'1 case end @@ -122082,14 +121878,14 @@ module \dec19 sync always update \dec19_br $0\dec19_br[0:0] end - attribute \src "libresoc.v:76551.3-76602.6" - process $proc$libresoc.v:76551$3608 + attribute \src "libresoc.v:76347.3-76398.6" + process $proc$libresoc.v:76347$3608 assign { } { } assign { } { } assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:76552.5-76552.29" + attribute \src "libresoc.v:76348.5-76348.29" switch \initial - attribute \src "libresoc.v:76552.9-76552.17" + attribute \src "libresoc.v:76348.9-76348.17" case 1'1 case end @@ -122161,14 +121957,14 @@ module \dec19 sync always update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] end - attribute \src "libresoc.v:76603.3-76654.6" - process $proc$libresoc.v:76603$3609 + attribute \src "libresoc.v:76399.3-76450.6" + process $proc$libresoc.v:76399$3609 assign { } { } assign { } { } assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:76604.5-76604.29" + attribute \src "libresoc.v:76400.5-76400.29" switch \initial - attribute \src "libresoc.v:76604.9-76604.17" + attribute \src "libresoc.v:76400.9-76400.17" case 1'1 case end @@ -122240,14 +122036,14 @@ module \dec19 sync always update \dec19_rsrv $0\dec19_rsrv[0:0] end - attribute \src "libresoc.v:76655.3-76706.6" - process $proc$libresoc.v:76655$3610 + attribute \src "libresoc.v:76451.3-76502.6" + process $proc$libresoc.v:76451$3610 assign { } { } assign { } { } assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:76656.5-76656.29" + attribute \src "libresoc.v:76452.5-76452.29" switch \initial - attribute \src "libresoc.v:76656.9-76656.17" + attribute \src "libresoc.v:76452.9-76452.17" case 1'1 case end @@ -122319,14 +122115,14 @@ module \dec19 sync always update \dec19_form $0\dec19_form[4:0] end - attribute \src "libresoc.v:76707.3-76758.6" - process $proc$libresoc.v:76707$3611 + attribute \src "libresoc.v:76503.3-76554.6" + process $proc$libresoc.v:76503$3611 assign { } { } assign { } { } assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:76708.5-76708.29" + attribute \src "libresoc.v:76504.5-76504.29" switch \initial - attribute \src "libresoc.v:76708.9-76708.17" + attribute \src "libresoc.v:76504.9-76504.17" case 1'1 case end @@ -122398,14 +122194,14 @@ module \dec19 sync always update \dec19_is_32b $0\dec19_is_32b[0:0] end - attribute \src "libresoc.v:76759.3-76810.6" - process $proc$libresoc.v:76759$3612 + attribute \src "libresoc.v:76555.3-76606.6" + process $proc$libresoc.v:76555$3612 assign { } { } assign { } { } assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:76760.5-76760.29" + attribute \src "libresoc.v:76556.5-76556.29" switch \initial - attribute \src "libresoc.v:76760.9-76760.17" + attribute \src "libresoc.v:76556.9-76556.17" case 1'1 case end @@ -122477,14 +122273,14 @@ module \dec19 sync always update \dec19_sgn $0\dec19_sgn[0:0] end - attribute \src "libresoc.v:76811.3-76862.6" - process $proc$libresoc.v:76811$3613 + attribute \src "libresoc.v:76607.3-76658.6" + process $proc$libresoc.v:76607$3613 assign { } { } assign { } { } assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:76812.5-76812.29" + attribute \src "libresoc.v:76608.5-76608.29" switch \initial - attribute \src "libresoc.v:76812.9-76812.17" + attribute \src "libresoc.v:76608.9-76608.17" case 1'1 case end @@ -122556,14 +122352,14 @@ module \dec19 sync always update \dec19_lk $0\dec19_lk[0:0] end - attribute \src "libresoc.v:76863.3-76914.6" - process $proc$libresoc.v:76863$3614 + attribute \src "libresoc.v:76659.3-76710.6" + process $proc$libresoc.v:76659$3614 assign { } { } assign { } { } assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76864.5-76864.29" + attribute \src "libresoc.v:76660.5-76660.29" switch \initial - attribute \src "libresoc.v:76864.9-76864.17" + attribute \src "libresoc.v:76660.9-76660.17" case 1'1 case end @@ -122635,14 +122431,14 @@ module \dec19 sync always update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end - attribute \src "libresoc.v:76915.3-76966.6" - process $proc$libresoc.v:76915$3615 + attribute \src "libresoc.v:76711.3-76762.6" + process $proc$libresoc.v:76711$3615 assign { } { } assign { } { } assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76916.5-76916.29" + attribute \src "libresoc.v:76712.5-76712.29" switch \initial - attribute \src "libresoc.v:76916.9-76916.17" + attribute \src "libresoc.v:76712.9-76712.17" case 1'1 case end @@ -122714,14 +122510,14 @@ module \dec19 sync always update \dec19_SV_Etype $0\dec19_SV_Etype[1:0] end - attribute \src "libresoc.v:76967.3-77018.6" - process $proc$libresoc.v:76967$3616 + attribute \src "libresoc.v:76763.3-76814.6" + process $proc$libresoc.v:76763$3616 assign { } { } assign { } { } assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76968.5-76968.29" + attribute \src "libresoc.v:76764.5-76764.29" switch \initial - attribute \src "libresoc.v:76968.9-76968.17" + attribute \src "libresoc.v:76764.9-76764.17" case 1'1 case end @@ -122793,14 +122589,14 @@ module \dec19 sync always update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0] end - attribute \src "libresoc.v:77019.3-77070.6" - process $proc$libresoc.v:77019$3617 + attribute \src "libresoc.v:76815.3-76866.6" + process $proc$libresoc.v:76815$3617 assign { } { } assign { } { } assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:77020.5-77020.29" + attribute \src "libresoc.v:76816.5-76816.29" switch \initial - attribute \src "libresoc.v:77020.9-77020.17" + attribute \src "libresoc.v:76816.9-76816.17" case 1'1 case end @@ -122872,14 +122668,14 @@ module \dec19 sync always update \dec19_in1_sel $0\dec19_in1_sel[2:0] end - attribute \src "libresoc.v:77071.3-77122.6" - process $proc$libresoc.v:77071$3618 + attribute \src "libresoc.v:76867.3-76918.6" + process $proc$libresoc.v:76867$3618 assign { } { } assign { } { } assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:77072.5-77072.29" + attribute \src "libresoc.v:76868.5-76868.29" switch \initial - attribute \src "libresoc.v:77072.9-77072.17" + attribute \src "libresoc.v:76868.9-76868.17" case 1'1 case end @@ -122951,14 +122747,14 @@ module \dec19 sync always update \dec19_in2_sel $0\dec19_in2_sel[3:0] end - attribute \src "libresoc.v:77123.3-77174.6" - process $proc$libresoc.v:77123$3619 + attribute \src "libresoc.v:76919.3-76970.6" + process $proc$libresoc.v:76919$3619 assign { } { } assign { } { } assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:77124.5-77124.29" + attribute \src "libresoc.v:76920.5-76920.29" switch \initial - attribute \src "libresoc.v:77124.9-77124.17" + attribute \src "libresoc.v:76920.9-76920.17" case 1'1 case end @@ -123030,14 +122826,14 @@ module \dec19 sync always update \dec19_in3_sel $0\dec19_in3_sel[1:0] end - attribute \src "libresoc.v:77175.3-77226.6" - process $proc$libresoc.v:77175$3620 + attribute \src "libresoc.v:76971.3-77022.6" + process $proc$libresoc.v:76971$3620 assign { } { } assign { } { } assign $0\dec19_out_sel[2:0] $1\dec19_out_sel[2:0] - attribute \src "libresoc.v:77176.5-77176.29" + attribute \src "libresoc.v:76972.5-76972.29" switch \initial - attribute \src "libresoc.v:77176.9-77176.17" + attribute \src "libresoc.v:76972.9-76972.17" case 1'1 case end @@ -123111,755 +122907,755 @@ module \dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:77232.1-79453.10" +attribute \src "libresoc.v:77028.1-79249.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2" attribute \generator "nMigen" module \dec2 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\cr_in1[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\cr_in2$1[6:0]$3682 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\cr_in2[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_in2_ok$2[0:0]$3683 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\cr_out[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\ea[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\ea_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$3[0:0]$3685 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$4[0:0]$3686 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$5[0:0]$3687 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$6[0:0]$3688 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$7[0:0]$3689 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$8[0:0]$3690 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$9[0:0]$3691 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal[0:0]$3684 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $0\fn_unit[13:0] - attribute \src "libresoc.v:77233.7-77233.20" + attribute \src "libresoc.v:77029.7-77029.20" wire $0\initial[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:79192.3-79215.6" + attribute \src "libresoc.v:78988.3-79011.6" wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\lk[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\oe[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\rc[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\reg1[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\reg2[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\reg3[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\rego[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\rego_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\spro_ok[0:0] - attribute \src "libresoc.v:79118.3-79132.6" + attribute \src "libresoc.v:78914.3-78928.6" wire width 14 $0\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:79143.3-79155.6" + attribute \src "libresoc.v:78939.3-78951.6" wire width 7 $0\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:79133.3-79142.6" + attribute \src "libresoc.v:78929.3-78938.6" wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:79182.3-79191.6" + attribute \src "libresoc.v:78978.3-78987.6" wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:79156.3-79171.6" + attribute \src "libresoc.v:78952.3-78967.6" wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:79172.3-79181.6" + attribute \src "libresoc.v:78968.3-78977.6" wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\traptype[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\xer_out[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\cr_in1[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\cr_in2$1[6:0]$3692 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\cr_in2[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_in2_ok$2[0:0]$3693 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\cr_out[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\ea[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\ea_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$3[0:0]$3695 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$4[0:0]$3696 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$5[0:0]$3697 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$6[0:0]$3698 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$7[0:0]$3699 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$8[0:0]$3700 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$9[0:0]$3701 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal[0:0]$3694 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $1\fn_unit[13:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:79192.3-79215.6" + attribute \src "libresoc.v:78988.3-79011.6" wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\lk[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\oe[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\rc[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\rc_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\reg1[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\reg2[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\reg3[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\rego[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\rego_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\spro_ok[0:0] - attribute \src "libresoc.v:79118.3-79132.6" + attribute \src "libresoc.v:78914.3-78928.6" wire width 14 $1\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:79143.3-79155.6" + attribute \src "libresoc.v:78939.3-78951.6" wire width 7 $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:79133.3-79142.6" + attribute \src "libresoc.v:78929.3-78938.6" wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:79182.3-79191.6" + attribute \src "libresoc.v:78978.3-78987.6" wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:79156.3-79171.6" + attribute \src "libresoc.v:78952.3-78967.6" wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:79172.3-79181.6" + attribute \src "libresoc.v:78968.3-78977.6" wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\traptype[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\xer_out[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $2\cia[63:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\cr_in1[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_in1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\cr_in2$1[6:0]$3702 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\cr_in2[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_in2_ok$2[0:0]$3703 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_in2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\cr_out[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_out_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\cr_rd[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_rd_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\cr_wr[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_wr_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\ea[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\ea_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$3[0:0]$3705 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$4[0:0]$3706 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$5[0:0]$3707 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$6[0:0]$3708 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$7[0:0]$3709 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$8[0:0]$3710 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$9[0:0]$3711 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal[0:0]$3704 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fast1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fast2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fasto1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\fasto1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fasto2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\fasto2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $2\fn_unit[13:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $2\input_carry[1:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $2\insn[31:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\insn_type[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\is_32bit[0:0] - attribute \src "libresoc.v:79192.3-79215.6" + attribute \src "libresoc.v:78988.3-79011.6" wire $2\is_priv_insn[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\lk[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\oe[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\oe_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\rc[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\rc_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\reg1[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\reg1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\reg2[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\reg2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\reg3[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\reg3_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\rego[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\rego_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $2\spr1[9:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $2\spro[9:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\spro_ok[0:0] - attribute \src "libresoc.v:79156.3-79171.6" + attribute \src "libresoc.v:78952.3-78967.6" wire width 3 $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $2\trapaddr[12:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\traptype[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\xer_in[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\xer_out[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\asmcode[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $3\cia[63:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\cr_in1[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_in1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\cr_in2$1[6:0]$3712 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\cr_in2[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_in2_ok$2[0:0]$3713 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_in2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\cr_out[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_out_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\cr_rd[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_rd_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\cr_wr[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_wr_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\ea[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\ea_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$3[0:0]$3715 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$4[0:0]$3716 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$5[0:0]$3717 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$6[0:0]$3718 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$7[0:0]$3719 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$8[0:0]$3720 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$9[0:0]$3721 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal[0:0]$3714 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fast1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\fast1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fast2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\fast2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fasto1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\fasto1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fasto2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\fasto2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $3\fn_unit[13:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $3\input_carry[1:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $3\insn[31:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\insn_type[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\is_32bit[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\lk[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $3\msr[63:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\oe[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\oe_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\rc[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\rc_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\reg1[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\reg1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\reg2[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\reg2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\reg3[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\reg3_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\rego[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\rego_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $3\spr1[9:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\spr1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $3\spro[9:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\spro_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $3\trapaddr[12:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\traptype[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\xer_in[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\xer_out[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $4\asmcode[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $4\cia[63:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\cr_in1[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_in1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\cr_in2$1[6:0]$3722 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\cr_in2[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_in2_ok$2[0:0]$3723 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_in2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\cr_out[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_out_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $4\cr_rd[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_rd_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $4\cr_wr[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_wr_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\ea[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\ea_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$3[0:0]$3725 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$4[0:0]$3726 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$5[0:0]$3727 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$6[0:0]$3728 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$7[0:0]$3729 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$8[0:0]$3730 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$9[0:0]$3731 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal[0:0]$3724 - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\fast1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\fast1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\fast2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\fast2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\fasto1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\fasto1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\fasto2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\fasto2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $4\fn_unit[13:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $4\input_carry[1:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $4\insn[31:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\insn_type[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\is_32bit[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\lk[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $4\msr[63:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\oe[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\oe_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\rc[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\rc_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\reg1[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\reg1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\reg2[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\reg2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\reg3[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\reg3_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\rego[6:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\rego_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $4\spr1[9:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\spr1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $4\spro[9:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\spro_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $4\trapaddr[12:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $4\traptype[7:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\xer_in[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\xer_out[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $5\fast1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $5\fast1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $5\fast2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $5\fast2_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $5\fasto1[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $5\fasto1_ok[0:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $5\fasto2[2:0] - attribute \src "libresoc.v:79216.3-79373.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $5\fasto2_ok[0:0] - attribute \src "libresoc.v:78939.19-78939.122" - wire $and$libresoc.v:78939$3632_Y - attribute \src "libresoc.v:78940.19-78940.125" - wire $and$libresoc.v:78940$3633_Y - attribute \src "libresoc.v:78941.19-78941.126" - wire $and$libresoc.v:78941$3634_Y - attribute \src "libresoc.v:78948.18-78948.114" - wire $and$libresoc.v:78948$3641_Y - attribute \src "libresoc.v:78949.18-78949.116" - wire $and$libresoc.v:78949$3642_Y - attribute \src "libresoc.v:78951.18-78951.114" - wire $and$libresoc.v:78951$3644_Y - attribute \src "libresoc.v:78953.18-78953.110" - wire $and$libresoc.v:78953$3646_Y - attribute \src "libresoc.v:78965.18-78965.114" - wire $and$libresoc.v:78965$3658_Y - attribute \src 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attribute \src "libresoc.v:78950.18-78950.127" - wire $eq$libresoc.v:78950$3643_Y - attribute \src "libresoc.v:78954.18-78954.122" - wire $eq$libresoc.v:78954$3647_Y - attribute \src "libresoc.v:78955.18-78955.122" - wire $eq$libresoc.v:78955$3648_Y - attribute \src "libresoc.v:78957.18-78957.110" - wire $eq$libresoc.v:78957$3650_Y - attribute \src "libresoc.v:78958.18-78958.110" - wire $eq$libresoc.v:78958$3651_Y - attribute \src "libresoc.v:78960.18-78960.112" - wire $eq$libresoc.v:78960$3653_Y - attribute \src "libresoc.v:78962.18-78962.110" - wire $eq$libresoc.v:78962$3655_Y - attribute \src "libresoc.v:78964.18-78964.127" - wire $eq$libresoc.v:78964$3657_Y - attribute \src "libresoc.v:78967.18-78967.127" - wire $eq$libresoc.v:78967$3660_Y - attribute \src "libresoc.v:78932.19-78932.124" - wire width 7 $extend$libresoc.v:78932$3622_Y - attribute \src "libresoc.v:78933.19-78933.124" - wire width 7 $extend$libresoc.v:78933$3624_Y - attribute \src "libresoc.v:78934.19-78934.123" - wire width 7 $extend$libresoc.v:78934$3626_Y - attribute \src "libresoc.v:78971.18-78971.111" - wire width 7 $extend$libresoc.v:78971$3664_Y - attribute \src "libresoc.v:78972.18-78972.111" - wire width 7 $extend$libresoc.v:78972$3666_Y - attribute \src "libresoc.v:78973.18-78973.111" - wire width 7 $extend$libresoc.v:78973$3668_Y - attribute \src "libresoc.v:78974.18-78974.113" - wire width 7 $extend$libresoc.v:78974$3670_Y - attribute \src "libresoc.v:78975.18-78975.121" - wire width 7 $extend$libresoc.v:78975$3672_Y - attribute \src "libresoc.v:78952.18-78952.110" - wire $not$libresoc.v:78952$3645_Y - attribute \src "libresoc.v:78969.18-78969.110" - wire $not$libresoc.v:78969$3662_Y - attribute \src "libresoc.v:78945.18-78945.111" - wire $or$libresoc.v:78945$3638_Y - attribute \src "libresoc.v:78956.18-78956.110" - wire $or$libresoc.v:78956$3649_Y - attribute \src "libresoc.v:78959.18-78959.110" - wire $or$libresoc.v:78959$3652_Y - attribute \src "libresoc.v:78961.18-78961.110" - wire $or$libresoc.v:78961$3654_Y - attribute \src "libresoc.v:78963.18-78963.110" - wire $or$libresoc.v:78963$3656_Y - attribute \src "libresoc.v:78932.19-78932.124" - wire width 7 $pos$libresoc.v:78932$3623_Y - attribute \src "libresoc.v:78933.19-78933.124" - wire width 7 $pos$libresoc.v:78933$3625_Y - attribute \src "libresoc.v:78934.19-78934.123" - wire width 7 $pos$libresoc.v:78934$3627_Y - attribute \src "libresoc.v:78971.18-78971.111" - wire width 7 $pos$libresoc.v:78971$3665_Y - attribute \src "libresoc.v:78972.18-78972.111" - wire width 7 $pos$libresoc.v:78972$3667_Y - attribute \src "libresoc.v:78973.18-78973.111" - wire width 7 $pos$libresoc.v:78973$3669_Y - attribute \src "libresoc.v:78974.18-78974.113" - wire width 7 $pos$libresoc.v:78974$3671_Y - attribute \src "libresoc.v:78975.18-78975.121" - wire width 7 $pos$libresoc.v:78975$3673_Y + attribute \src "libresoc.v:78735.19-78735.122" + wire $and$libresoc.v:78735$3632_Y + attribute \src "libresoc.v:78736.19-78736.125" + wire $and$libresoc.v:78736$3633_Y + attribute \src "libresoc.v:78737.19-78737.126" + wire $and$libresoc.v:78737$3634_Y + attribute \src "libresoc.v:78744.18-78744.114" + wire $and$libresoc.v:78744$3641_Y + attribute \src "libresoc.v:78745.18-78745.116" + wire $and$libresoc.v:78745$3642_Y + attribute \src "libresoc.v:78747.18-78747.114" + wire $and$libresoc.v:78747$3644_Y + attribute \src "libresoc.v:78749.18-78749.110" + wire $and$libresoc.v:78749$3646_Y + attribute \src "libresoc.v:78761.18-78761.114" + wire $and$libresoc.v:78761$3658_Y + attribute \src "libresoc.v:78762.18-78762.116" + wire $and$libresoc.v:78762$3659_Y + attribute \src "libresoc.v:78764.18-78764.114" + wire $and$libresoc.v:78764$3661_Y + attribute \src "libresoc.v:78766.18-78766.110" + wire $and$libresoc.v:78766$3663_Y + attribute \src "libresoc.v:78731.19-78731.124" + wire $eq$libresoc.v:78731$3628_Y + attribute \src "libresoc.v:78732.19-78732.124" + wire $eq$libresoc.v:78732$3629_Y + attribute \src "libresoc.v:78733.19-78733.124" + wire $eq$libresoc.v:78733$3630_Y + attribute \src "libresoc.v:78734.19-78734.124" + wire $eq$libresoc.v:78734$3631_Y + attribute \src "libresoc.v:78738.19-78738.124" + wire $eq$libresoc.v:78738$3635_Y + attribute \src "libresoc.v:78739.18-78739.117" + wire $eq$libresoc.v:78739$3636_Y + attribute \src "libresoc.v:78740.18-78740.117" + wire $eq$libresoc.v:78740$3637_Y + attribute \src "libresoc.v:78742.18-78742.117" + wire $eq$libresoc.v:78742$3639_Y + attribute \src "libresoc.v:78743.18-78743.127" + wire $eq$libresoc.v:78743$3640_Y + attribute \src "libresoc.v:78746.18-78746.127" + wire $eq$libresoc.v:78746$3643_Y + attribute \src "libresoc.v:78750.18-78750.122" + wire $eq$libresoc.v:78750$3647_Y + attribute \src "libresoc.v:78751.18-78751.122" + wire $eq$libresoc.v:78751$3648_Y + attribute \src "libresoc.v:78753.18-78753.110" + wire $eq$libresoc.v:78753$3650_Y + attribute \src "libresoc.v:78754.18-78754.110" + wire $eq$libresoc.v:78754$3651_Y + attribute \src "libresoc.v:78756.18-78756.112" + wire $eq$libresoc.v:78756$3653_Y + attribute \src "libresoc.v:78758.18-78758.110" + wire $eq$libresoc.v:78758$3655_Y + attribute \src "libresoc.v:78760.18-78760.127" + wire $eq$libresoc.v:78760$3657_Y + attribute \src "libresoc.v:78763.18-78763.127" + wire $eq$libresoc.v:78763$3660_Y + attribute \src "libresoc.v:78728.19-78728.124" + wire width 7 $extend$libresoc.v:78728$3622_Y + attribute \src "libresoc.v:78729.19-78729.124" + wire width 7 $extend$libresoc.v:78729$3624_Y + attribute \src "libresoc.v:78730.19-78730.123" + wire width 7 $extend$libresoc.v:78730$3626_Y + attribute \src "libresoc.v:78767.18-78767.111" + wire width 7 $extend$libresoc.v:78767$3664_Y + attribute \src "libresoc.v:78768.18-78768.111" + wire width 7 $extend$libresoc.v:78768$3666_Y + attribute \src "libresoc.v:78769.18-78769.111" + wire width 7 $extend$libresoc.v:78769$3668_Y + attribute \src "libresoc.v:78770.18-78770.113" + wire width 7 $extend$libresoc.v:78770$3670_Y + attribute \src "libresoc.v:78771.18-78771.121" + wire width 7 $extend$libresoc.v:78771$3672_Y + attribute \src "libresoc.v:78748.18-78748.110" + wire $not$libresoc.v:78748$3645_Y + attribute \src "libresoc.v:78765.18-78765.110" + wire $not$libresoc.v:78765$3662_Y + attribute \src "libresoc.v:78741.18-78741.111" + wire $or$libresoc.v:78741$3638_Y + attribute \src "libresoc.v:78752.18-78752.110" + wire $or$libresoc.v:78752$3649_Y + attribute \src "libresoc.v:78755.18-78755.110" + wire $or$libresoc.v:78755$3652_Y + attribute \src "libresoc.v:78757.18-78757.110" + wire $or$libresoc.v:78757$3654_Y + attribute \src "libresoc.v:78759.18-78759.110" + wire $or$libresoc.v:78759$3656_Y + attribute \src "libresoc.v:78728.19-78728.124" + wire width 7 $pos$libresoc.v:78728$3623_Y + attribute \src "libresoc.v:78729.19-78729.124" + wire width 7 $pos$libresoc.v:78729$3625_Y + attribute \src "libresoc.v:78730.19-78730.123" + wire width 7 $pos$libresoc.v:78730$3627_Y + attribute \src "libresoc.v:78767.18-78767.111" + wire width 7 $pos$libresoc.v:78767$3665_Y + attribute \src "libresoc.v:78768.18-78768.111" + wire width 7 $pos$libresoc.v:78768$3667_Y + attribute \src "libresoc.v:78769.18-78769.111" + wire width 7 $pos$libresoc.v:78769$3669_Y + attribute \src "libresoc.v:78770.18-78770.113" + wire width 7 $pos$libresoc.v:78770$3671_Y + attribute \src "libresoc.v:78771.18-78771.121" + wire width 7 $pos$libresoc.v:78771$3673_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" @@ -124664,7 +124460,7 @@ module \dec2 wire width 14 output 42 \fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1246" wire \illeg_ok - attribute \src "libresoc.v:77233.7-77233.15" + attribute \src "libresoc.v:77029.7-77029.15" wire \initial attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" @@ -125502,7 +125298,7 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire output 21 \xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" - cell $and $and$libresoc.v:78939$3632 + cell $and $and$libresoc.v:78735$3632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125510,10 +125306,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_eint connect \B \cur_msr [15] - connect \Y $and$libresoc.v:78939$3632_Y + connect \Y $and$libresoc.v:78735$3632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" - cell $and $and$libresoc.v:78940$3633 + cell $and $and$libresoc.v:78736$3633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125521,10 +125317,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_dec [63] connect \B \cur_msr [15] - connect \Y $and$libresoc.v:78940$3633_Y + connect \Y $and$libresoc.v:78736$3633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" - cell $and $and$libresoc.v:78941$3634 + cell $and $and$libresoc.v:78737$3634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125532,10 +125328,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_priv_insn connect \B \cur_msr [14] - connect \Y $and$libresoc.v:78941$3634_Y + connect \Y $and$libresoc.v:78737$3634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:78948$3641 + cell $and $and$libresoc.v:78744$3641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125543,10 +125339,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$37 - connect \Y $and$libresoc.v:78948$3641_Y + connect \Y $and$libresoc.v:78744$3641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:78949$3642 + cell $and $and$libresoc.v:78745$3642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125554,10 +125350,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$39 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:78949$3642_Y + connect \Y $and$libresoc.v:78745$3642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:78951$3644 + cell $and $and$libresoc.v:78747$3644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125565,10 +125361,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$43 - connect \Y $and$libresoc.v:78951$3644_Y + connect \Y $and$libresoc.v:78747$3644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:78953$3646 + cell $and $and$libresoc.v:78749$3646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125576,10 +125372,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:78953$3646_Y + connect \Y $and$libresoc.v:78749$3646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:78965$3658 + cell $and $and$libresoc.v:78761$3658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125587,10 +125383,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$71 - connect \Y $and$libresoc.v:78965$3658_Y + connect \Y $and$libresoc.v:78761$3658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:78966$3659 + cell $and $and$libresoc.v:78762$3659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125598,10 +125394,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$73 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:78966$3659_Y + connect \Y $and$libresoc.v:78762$3659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:78968$3661 + cell $and $and$libresoc.v:78764$3661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125609,10 +125405,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$77 - connect \Y $and$libresoc.v:78968$3661_Y + connect \Y $and$libresoc.v:78764$3661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:78970$3663 + cell $and $and$libresoc.v:78766$3663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125620,10 +125416,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:78970$3663_Y + connect \Y $and$libresoc.v:78766$3663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" - cell $eq $eq$libresoc.v:78935$3628 + cell $eq $eq$libresoc.v:78731$3628 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125631,10 +125427,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:78935$3628_Y + connect \Y $eq$libresoc.v:78731$3628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" - cell $eq $eq$libresoc.v:78936$3629 + cell $eq $eq$libresoc.v:78732$3629 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125642,10 +125438,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0001010 - connect \Y $eq$libresoc.v:78936$3629_Y + connect \Y $eq$libresoc.v:78732$3629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" - cell $eq $eq$libresoc.v:78937$3630 + cell $eq $eq$libresoc.v:78733$3630 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125653,10 +125449,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:78937$3630_Y + connect \Y $eq$libresoc.v:78733$3630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" - cell $eq $eq$libresoc.v:78938$3631 + cell $eq $eq$libresoc.v:78734$3631 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125664,10 +125460,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0111111 - connect \Y $eq$libresoc.v:78938$3631_Y + connect \Y $eq$libresoc.v:78734$3631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" - cell $eq $eq$libresoc.v:78942$3635 + cell $eq $eq$libresoc.v:78738$3635 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125675,10 +125471,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0000000 - connect \Y $eq$libresoc.v:78942$3635_Y + connect \Y $eq$libresoc.v:78738$3635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" - cell $eq $eq$libresoc.v:78943$3636 + cell $eq $eq$libresoc.v:78739$3636 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125686,10 +125482,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'0111111 - connect \Y $eq$libresoc.v:78943$3636_Y + connect \Y $eq$libresoc.v:78739$3636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" - cell $eq $eq$libresoc.v:78944$3637 + cell $eq $eq$libresoc.v:78740$3637 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125697,10 +125493,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1001001 - connect \Y $eq$libresoc.v:78944$3637_Y + connect \Y $eq$libresoc.v:78740$3637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" - cell $eq $eq$libresoc.v:78946$3639 + cell $eq $eq$libresoc.v:78742$3639 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125708,10 +125504,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1000110 - connect \Y $eq$libresoc.v:78946$3639_Y + connect \Y $eq$libresoc.v:78742$3639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:78947$3640 + cell $eq $eq$libresoc.v:78743$3640 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125719,10 +125515,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:78947$3640_Y + connect \Y $eq$libresoc.v:78743$3640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:78950$3643 + cell $eq $eq$libresoc.v:78746$3643 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125730,10 +125526,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:78950$3643_Y + connect \Y $eq$libresoc.v:78746$3643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" - cell $eq $eq$libresoc.v:78954$3647 + cell $eq $eq$libresoc.v:78750$3647 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125741,10 +125537,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:78954$3647_Y + connect \Y $eq$libresoc.v:78750$3647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $eq $eq$libresoc.v:78955$3648 + cell $eq $eq$libresoc.v:78751$3648 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125752,10 +125548,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:78955$3648_Y + connect \Y $eq$libresoc.v:78751$3648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:78957$3650 + cell $eq $eq$libresoc.v:78753$3650 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125763,10 +125559,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:78957$3650_Y + connect \Y $eq$libresoc.v:78753$3650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:78958$3651 + cell $eq $eq$libresoc.v:78754$3651 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125774,10 +125570,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:78958$3651_Y + connect \Y $eq$libresoc.v:78754$3651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:78960$3653 + cell $eq $eq$libresoc.v:78756$3653 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125785,10 +125581,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:78960$3653_Y + connect \Y $eq$libresoc.v:78756$3653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $eq $eq$libresoc.v:78962$3655 + cell $eq $eq$libresoc.v:78758$3655 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125796,10 +125592,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:78962$3655_Y + connect \Y $eq$libresoc.v:78758$3655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:78964$3657 + cell $eq $eq$libresoc.v:78760$3657 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125807,10 +125603,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:78964$3657_Y + connect \Y $eq$libresoc.v:78760$3657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:78967$3660 + cell $eq $eq$libresoc.v:78763$3660 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125818,90 +125614,90 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:78967$3660_Y + connect \Y $eq$libresoc.v:78763$3660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:78932$3622 + cell $pos $extend$libresoc.v:78728$3622 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_b - connect \Y $extend$libresoc.v:78932$3622_Y + connect \Y $extend$libresoc.v:78728$3622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:78933$3624 + cell $pos $extend$libresoc.v:78729$3624 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_o - connect \Y $extend$libresoc.v:78933$3624_Y + connect \Y $extend$libresoc.v:78729$3624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:78934$3626 + cell $pos $extend$libresoc.v:78730$3626 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_out_cr_bitfield - connect \Y $extend$libresoc.v:78934$3626_Y + connect \Y $extend$libresoc.v:78730$3626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:78971$3664 + cell $pos $extend$libresoc.v:78767$3664 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_a_reg_a - connect \Y $extend$libresoc.v:78971$3664_Y + connect \Y $extend$libresoc.v:78767$3664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:78972$3666 + cell $pos $extend$libresoc.v:78768$3666 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_c_reg_c - connect \Y $extend$libresoc.v:78972$3666_Y + connect \Y $extend$libresoc.v:78768$3666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:78973$3668 + cell $pos $extend$libresoc.v:78769$3668 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o_reg_o - connect \Y $extend$libresoc.v:78973$3668_Y + connect \Y $extend$libresoc.v:78769$3668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:78974$3670 + cell $pos $extend$libresoc.v:78770$3670 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o2_reg_o2 - connect \Y $extend$libresoc.v:78974$3670_Y + connect \Y $extend$libresoc.v:78770$3670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:78975$3672 + cell $pos $extend$libresoc.v:78771$3672 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield - connect \Y $extend$libresoc.v:78975$3672_Y + connect \Y $extend$libresoc.v:78771$3672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:78952$3645 + cell $not $not$libresoc.v:78748$3645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:78952$3645_Y + connect \Y $not$libresoc.v:78748$3645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:78969$3662 + cell $not $not$libresoc.v:78765$3662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:78969$3662_Y + connect \Y $not$libresoc.v:78765$3662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" - cell $or $or$libresoc.v:78945$3638 + cell $or $or$libresoc.v:78741$3638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125909,10 +125705,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$28 connect \B \$30 - connect \Y $or$libresoc.v:78945$3638_Y + connect \Y $or$libresoc.v:78741$3638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $or $or$libresoc.v:78956$3649 + cell $or $or$libresoc.v:78752$3649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125920,10 +125716,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:78956$3649_Y + connect \Y $or$libresoc.v:78752$3649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:78959$3652 + cell $or $or$libresoc.v:78755$3652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125931,10 +125727,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$57 connect \B \$59 - connect \Y $or$libresoc.v:78959$3652_Y + connect \Y $or$libresoc.v:78755$3652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:78961$3654 + cell $or $or$libresoc.v:78757$3654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125942,10 +125738,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$61 connect \B \$63 - connect \Y $or$libresoc.v:78961$3654_Y + connect \Y $or$libresoc.v:78757$3654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $or $or$libresoc.v:78963$3656 + cell $or $or$libresoc.v:78759$3656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125953,74 +125749,74 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$65 connect \B \$67 - connect \Y $or$libresoc.v:78963$3656_Y + connect \Y $or$libresoc.v:78759$3656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:78932$3623 + cell $pos $pos$libresoc.v:78728$3623 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78932$3622_Y - connect \Y $pos$libresoc.v:78932$3623_Y + connect \A $extend$libresoc.v:78728$3622_Y + connect \Y $pos$libresoc.v:78728$3623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:78933$3625 + cell $pos $pos$libresoc.v:78729$3625 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78933$3624_Y - connect \Y $pos$libresoc.v:78933$3625_Y + connect \A $extend$libresoc.v:78729$3624_Y + connect \Y $pos$libresoc.v:78729$3625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:78934$3627 + cell $pos $pos$libresoc.v:78730$3627 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78934$3626_Y - connect \Y $pos$libresoc.v:78934$3627_Y + connect \A $extend$libresoc.v:78730$3626_Y + connect \Y $pos$libresoc.v:78730$3627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:78971$3665 + cell $pos $pos$libresoc.v:78767$3665 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78971$3664_Y - connect \Y $pos$libresoc.v:78971$3665_Y + connect \A $extend$libresoc.v:78767$3664_Y + connect \Y $pos$libresoc.v:78767$3665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:78972$3667 + cell $pos $pos$libresoc.v:78768$3667 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78972$3666_Y - connect \Y $pos$libresoc.v:78972$3667_Y + connect \A $extend$libresoc.v:78768$3666_Y + connect \Y $pos$libresoc.v:78768$3667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:78973$3669 + cell $pos $pos$libresoc.v:78769$3669 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78973$3668_Y - connect \Y $pos$libresoc.v:78973$3669_Y + connect \A $extend$libresoc.v:78769$3668_Y + connect \Y $pos$libresoc.v:78769$3669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:78974$3671 + cell $pos $pos$libresoc.v:78770$3671 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78974$3670_Y - connect \Y $pos$libresoc.v:78974$3671_Y + connect \A $extend$libresoc.v:78770$3670_Y + connect \Y $pos$libresoc.v:78770$3671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:78975$3673 + cell $pos $pos$libresoc.v:78771$3673 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78975$3672_Y - connect \Y $pos$libresoc.v:78975$3673_Y + connect \A $extend$libresoc.v:78771$3672_Y + connect \Y $pos$libresoc.v:78771$3673_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:78976.13-79013.4" + attribute \src "libresoc.v:78772.13-78809.4" cell \dec$171 \dec connect \BA \dec_BA connect \BB \dec_BB @@ -126060,7 +125856,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:79014.9-79029.4" + attribute \src "libresoc.v:78810.9-78825.4" cell \dec_a \dec_a connect \BO \dec_BO connect \RA \dec_RA @@ -126078,7 +125874,7 @@ module \dec2 connect \sv_nz \dec_a_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:79030.9-79040.4" + attribute \src "libresoc.v:78826.9-78836.4" cell \dec_b \dec_b connect \RB \dec_RB connect \RS \dec_RS @@ -126091,7 +125887,7 @@ module \dec2 connect \sel_in \dec_b_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79041.9-79047.4" + attribute \src "libresoc.v:78837.9-78843.4" cell \dec_c \dec_c connect \RB \dec_RB connect \RS \dec_RS @@ -126100,7 +125896,7 @@ module \dec2 connect \sel_in \dec_c_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79048.13-79067.4" + attribute \src "libresoc.v:78844.13-78863.4" cell \dec_cr_in \dec_cr_in$10 connect \BA \dec_BA connect \BB \dec_BB @@ -126122,7 +125918,7 @@ module \dec2 connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79068.14-79080.4" + attribute \src "libresoc.v:78864.14-78876.4" cell \dec_cr_out \dec_cr_out$11 connect \FXM \dec_FXM connect \XL_BT \dec_XL_BT @@ -126137,7 +125933,7 @@ module \dec2 connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79081.9-79094.4" + attribute \src "libresoc.v:78877.9-78890.4" cell \dec_o \dec_o connect \BO \dec_BO connect \RA \dec_RA @@ -126153,7 +125949,7 @@ module \dec2 connect \spr_o_ok \dec_o_spr_o_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:79095.10-79104.4" + attribute \src "libresoc.v:78891.10-78900.4" cell \dec_o2 \dec_o2 connect \RA \dec_RA connect \fast_o2 \dec_o2_fast_o2 @@ -126165,7 +125961,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:79105.16-79111.4" + attribute \src "libresoc.v:78901.16-78907.4" cell \dec_oe$173 \dec_oe connect \OE \dec_OE connect \internal_op \dec_internal_op @@ -126174,28 +125970,28 @@ module \dec2 connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79112.16-79117.4" + attribute \src "libresoc.v:78908.16-78913.4" cell \dec_rc$172 \dec_rc connect \Rc \dec_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:77233.7-77233.20" - process $proc$libresoc.v:77233$3732 + attribute \src "libresoc.v:77029.7-77029.20" + process $proc$libresoc.v:77029$3732 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:79118.3-79132.6" - process $proc$libresoc.v:79118$3674 + attribute \src "libresoc.v:78914.3-78928.6" + process $proc$libresoc.v:78914$3674 assign { } { } assign $0\tmp_tmp_fn_unit[13:0] $1\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:79119.5-79119.29" + attribute \src "libresoc.v:78915.5-78915.29" switch \initial - attribute \src "libresoc.v:79119.9-79119.17" + attribute \src "libresoc.v:78915.9-78915.17" case 1'1 case end @@ -126217,14 +126013,14 @@ module \dec2 sync always update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[13:0] end - attribute \src "libresoc.v:79133.3-79142.6" - process $proc$libresoc.v:79133$3675 + attribute \src "libresoc.v:78929.3-78938.6" + process $proc$libresoc.v:78929$3675 assign { } { } assign { } { } assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:79134.5-79134.29" + attribute \src "libresoc.v:78930.5-78930.29" switch \initial - attribute \src "libresoc.v:79134.9-79134.17" + attribute \src "libresoc.v:78930.9-78930.17" case 1'1 case end @@ -126240,14 +126036,14 @@ module \dec2 sync always update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end - attribute \src "libresoc.v:79143.3-79155.6" - process $proc$libresoc.v:79143$3676 + attribute \src "libresoc.v:78939.3-78951.6" + process $proc$libresoc.v:78939$3676 assign { } { } assign { } { } assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:79144.5-79144.29" + attribute \src "libresoc.v:78940.5-78940.29" switch \initial - attribute \src "libresoc.v:79144.9-79144.17" + attribute \src "libresoc.v:78940.9-78940.17" case 1'1 case end @@ -126267,15 +126063,15 @@ module \dec2 sync always update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0] end - attribute \src "libresoc.v:79156.3-79171.6" - process $proc$libresoc.v:79156$3677 + attribute \src "libresoc.v:78952.3-78967.6" + process $proc$libresoc.v:78952$3677 assign { } { } assign { } { } assign { } { } assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:79157.5-79157.29" + attribute \src "libresoc.v:78953.5-78953.29" switch \initial - attribute \src "libresoc.v:79157.9-79157.17" + attribute \src "libresoc.v:78953.9-78953.17" case 1'1 case end @@ -126300,14 +126096,14 @@ module \dec2 sync always update \tmp_xer_in $0\tmp_xer_in[2:0] end - attribute \src "libresoc.v:79172.3-79181.6" - process $proc$libresoc.v:79172$3678 + attribute \src "libresoc.v:78968.3-78977.6" + process $proc$libresoc.v:78968$3678 assign { } { } assign { } { } assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:79173.5-79173.29" + attribute \src "libresoc.v:78969.5-78969.29" switch \initial - attribute \src "libresoc.v:79173.9-79173.17" + attribute \src "libresoc.v:78969.9-78969.17" case 1'1 case end @@ -126323,14 +126119,14 @@ module \dec2 sync always update \tmp_xer_out $0\tmp_xer_out[0:0] end - attribute \src "libresoc.v:79182.3-79191.6" - process $proc$libresoc.v:79182$3679 + attribute \src "libresoc.v:78978.3-78987.6" + process $proc$libresoc.v:78978$3679 assign { } { } assign { } { } assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:79183.5-79183.29" + attribute \src "libresoc.v:78979.5-78979.29" switch \initial - attribute \src "libresoc.v:79183.9-79183.17" + attribute \src "libresoc.v:78979.9-78979.17" case 1'1 case end @@ -126346,14 +126142,14 @@ module \dec2 sync always update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] end - attribute \src "libresoc.v:79192.3-79215.6" - process $proc$libresoc.v:79192$3680 + attribute \src "libresoc.v:78988.3-79011.6" + process $proc$libresoc.v:78988$3680 assign { } { } assign { } { } assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:79193.5-79193.29" + attribute \src "libresoc.v:78989.5-78989.29" switch \initial - attribute \src "libresoc.v:79193.9-79193.17" + attribute \src "libresoc.v:78989.9-78989.17" case 1'1 case end @@ -126386,8 +126182,8 @@ module \dec2 sync always update \is_priv_insn $0\is_priv_insn[0:0] end - attribute \src "libresoc.v:79216.3-79373.6" - process $proc$libresoc.v:79216$3681 + attribute \src "libresoc.v:79012.3-79169.6" + process $proc$libresoc.v:79012$3681 assign { } { } assign { } { } assign { } { } @@ -126515,9 +126311,9 @@ module \dec2 assign $0\fast2[2:0] $5\fast2[2:0] assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:79217.5-79217.29" + attribute \src "libresoc.v:79013.5-79013.29" switch \initial - attribute \src "libresoc.v:79217.9-79217.17" + attribute \src "libresoc.v:79013.9-79013.17" case 1'1 case end @@ -127674,50 +127470,50 @@ module \dec2 update \xer_in $0\xer_in[2:0] update \xer_out $0\xer_out[0:0] end - connect \$100 $pos$libresoc.v:78932$3623_Y - connect \$102 $pos$libresoc.v:78933$3625_Y - connect \$104 $pos$libresoc.v:78934$3627_Y - connect \$106 $eq$libresoc.v:78935$3628_Y - connect \$108 $eq$libresoc.v:78936$3629_Y - connect \$110 $eq$libresoc.v:78937$3630_Y - connect \$112 $eq$libresoc.v:78938$3631_Y - connect \$114 $and$libresoc.v:78939$3632_Y - connect \$116 $and$libresoc.v:78940$3633_Y - connect \$118 $and$libresoc.v:78941$3634_Y - connect \$120 $eq$libresoc.v:78942$3635_Y - connect \$28 $eq$libresoc.v:78943$3636_Y - connect \$30 $eq$libresoc.v:78944$3637_Y - connect \$32 $or$libresoc.v:78945$3638_Y - connect \$34 $eq$libresoc.v:78946$3639_Y - connect \$37 $eq$libresoc.v:78947$3640_Y - connect \$39 $and$libresoc.v:78948$3641_Y - connect \$41 $and$libresoc.v:78949$3642_Y - connect \$43 $eq$libresoc.v:78950$3643_Y - connect \$45 $and$libresoc.v:78951$3644_Y - connect \$47 $not$libresoc.v:78952$3645_Y - connect \$49 $and$libresoc.v:78953$3646_Y - connect \$51 $eq$libresoc.v:78954$3647_Y - connect \$53 $eq$libresoc.v:78955$3648_Y - connect \$55 $or$libresoc.v:78956$3649_Y - connect \$57 $eq$libresoc.v:78957$3650_Y - connect \$59 $eq$libresoc.v:78958$3651_Y - connect \$61 $or$libresoc.v:78959$3652_Y - connect \$63 $eq$libresoc.v:78960$3653_Y - connect \$65 $or$libresoc.v:78961$3654_Y - connect \$67 $eq$libresoc.v:78962$3655_Y - connect \$69 $or$libresoc.v:78963$3656_Y - connect \$71 $eq$libresoc.v:78964$3657_Y - connect \$73 $and$libresoc.v:78965$3658_Y - connect \$75 $and$libresoc.v:78966$3659_Y - connect \$77 $eq$libresoc.v:78967$3660_Y - connect \$79 $and$libresoc.v:78968$3661_Y - connect \$81 $not$libresoc.v:78969$3662_Y - connect \$83 $and$libresoc.v:78970$3663_Y - connect \$90 $pos$libresoc.v:78971$3665_Y - connect \$92 $pos$libresoc.v:78972$3667_Y - connect \$94 $pos$libresoc.v:78973$3669_Y - connect \$96 $pos$libresoc.v:78974$3671_Y - connect \$98 $pos$libresoc.v:78975$3673_Y + connect \$100 $pos$libresoc.v:78728$3623_Y + connect \$102 $pos$libresoc.v:78729$3625_Y + connect \$104 $pos$libresoc.v:78730$3627_Y + connect \$106 $eq$libresoc.v:78731$3628_Y + connect \$108 $eq$libresoc.v:78732$3629_Y + connect \$110 $eq$libresoc.v:78733$3630_Y + connect \$112 $eq$libresoc.v:78734$3631_Y + connect \$114 $and$libresoc.v:78735$3632_Y + connect \$116 $and$libresoc.v:78736$3633_Y + connect \$118 $and$libresoc.v:78737$3634_Y + connect \$120 $eq$libresoc.v:78738$3635_Y + connect \$28 $eq$libresoc.v:78739$3636_Y + connect \$30 $eq$libresoc.v:78740$3637_Y + connect \$32 $or$libresoc.v:78741$3638_Y + connect \$34 $eq$libresoc.v:78742$3639_Y + connect \$37 $eq$libresoc.v:78743$3640_Y + connect \$39 $and$libresoc.v:78744$3641_Y + connect \$41 $and$libresoc.v:78745$3642_Y + connect \$43 $eq$libresoc.v:78746$3643_Y + connect \$45 $and$libresoc.v:78747$3644_Y + connect \$47 $not$libresoc.v:78748$3645_Y + connect \$49 $and$libresoc.v:78749$3646_Y + connect \$51 $eq$libresoc.v:78750$3647_Y + connect \$53 $eq$libresoc.v:78751$3648_Y + connect \$55 $or$libresoc.v:78752$3649_Y + connect \$57 $eq$libresoc.v:78753$3650_Y + connect \$59 $eq$libresoc.v:78754$3651_Y + connect \$61 $or$libresoc.v:78755$3652_Y + connect \$63 $eq$libresoc.v:78756$3653_Y + connect \$65 $or$libresoc.v:78757$3654_Y + connect \$67 $eq$libresoc.v:78758$3655_Y + connect \$69 $or$libresoc.v:78759$3656_Y + connect \$71 $eq$libresoc.v:78760$3657_Y + connect \$73 $and$libresoc.v:78761$3658_Y + connect \$75 $and$libresoc.v:78762$3659_Y + connect \$77 $eq$libresoc.v:78763$3660_Y + connect \$79 $and$libresoc.v:78764$3661_Y + connect \$81 $not$libresoc.v:78765$3662_Y + connect \$83 $and$libresoc.v:78766$3663_Y + connect \$90 $pos$libresoc.v:78767$3665_Y + connect \$92 $pos$libresoc.v:78768$3667_Y + connect \$94 $pos$libresoc.v:78769$3669_Y + connect \$96 $pos$libresoc.v:78770$3671_Y + connect \$98 $pos$libresoc.v:78771$3673_Y connect \dec2_exc_$signal 1'0 connect \dec2_exc_$signal$12 1'0 connect \dec2_exc_$signal$13 1'0 @@ -127798,144 +127594,144 @@ module \dec2 connect \insn_in$36 \dec_opcode_in connect \insn_in \dec_opcode_in end -attribute \src "libresoc.v:79457.1-80137.10" +attribute \src "libresoc.v:79253.1-79933.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec22" attribute \generator "nMigen" module \dec22 - attribute \src "libresoc.v:80076.3-80085.6" + attribute \src "libresoc.v:79872.3-79881.6" wire width 2 $0\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:80086.3-80095.6" + attribute \src "libresoc.v:79882.3-79891.6" wire width 2 $0\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:79956.3-79965.6" + attribute \src "libresoc.v:79752.3-79761.6" wire width 8 $0\dec22_asmcode[7:0] - attribute \src "libresoc.v:79996.3-80005.6" + attribute \src "libresoc.v:79792.3-79801.6" wire $0\dec22_br[0:0] - attribute \src "libresoc.v:79816.3-79825.6" + attribute \src "libresoc.v:79612.3-79621.6" wire width 3 $0\dec22_cr_in[2:0] - attribute \src "libresoc.v:79826.3-79835.6" + attribute \src "libresoc.v:79622.3-79631.6" wire width 3 $0\dec22_cr_out[2:0] - attribute \src "libresoc.v:79946.3-79955.6" + attribute \src "libresoc.v:79742.3-79751.6" wire width 2 $0\dec22_cry_in[1:0] - attribute \src "libresoc.v:79986.3-79995.6" + attribute \src "libresoc.v:79782.3-79791.6" wire $0\dec22_cry_out[0:0] - attribute \src "libresoc.v:80026.3-80035.6" + attribute \src "libresoc.v:79822.3-79831.6" wire width 5 $0\dec22_form[4:0] - attribute \src "libresoc.v:79806.3-79815.6" + attribute \src "libresoc.v:79602.3-79611.6" wire width 14 $0\dec22_function_unit[13:0] - attribute \src "libresoc.v:80096.3-80105.6" + attribute \src "libresoc.v:79892.3-79901.6" wire width 3 $0\dec22_in1_sel[2:0] - attribute \src "libresoc.v:80106.3-80115.6" + attribute \src "libresoc.v:79902.3-79911.6" wire width 4 $0\dec22_in2_sel[3:0] - attribute \src "libresoc.v:80116.3-80125.6" + attribute \src "libresoc.v:79912.3-79921.6" wire width 2 $0\dec22_in3_sel[1:0] - attribute \src "libresoc.v:79916.3-79925.6" + attribute \src "libresoc.v:79712.3-79721.6" wire width 7 $0\dec22_internal_op[6:0] - attribute \src "libresoc.v:79966.3-79975.6" + attribute \src "libresoc.v:79762.3-79771.6" wire $0\dec22_inv_a[0:0] - attribute \src "libresoc.v:79976.3-79985.6" + attribute \src "libresoc.v:79772.3-79781.6" wire $0\dec22_inv_out[0:0] - attribute \src "libresoc.v:80036.3-80045.6" + attribute \src "libresoc.v:79832.3-79841.6" wire $0\dec22_is_32b[0:0] - attribute \src "libresoc.v:79906.3-79915.6" + attribute \src "libresoc.v:79702.3-79711.6" wire width 4 $0\dec22_ldst_len[3:0] - attribute \src "libresoc.v:80056.3-80065.6" + attribute \src "libresoc.v:79852.3-79861.6" wire $0\dec22_lk[0:0] - attribute \src "libresoc.v:80126.3-80135.6" + attribute \src "libresoc.v:79922.3-79931.6" wire width 3 $0\dec22_out_sel[2:0] - attribute \src "libresoc.v:79936.3-79945.6" + attribute \src "libresoc.v:79732.3-79741.6" wire width 2 $0\dec22_rc_sel[1:0] - attribute \src "libresoc.v:80016.3-80025.6" + attribute \src "libresoc.v:79812.3-79821.6" wire $0\dec22_rsrv[0:0] - attribute \src "libresoc.v:80066.3-80075.6" + attribute \src "libresoc.v:79862.3-79871.6" wire $0\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:80046.3-80055.6" + attribute \src "libresoc.v:79842.3-79851.6" wire $0\dec22_sgn[0:0] - attribute \src "libresoc.v:80006.3-80015.6" + attribute \src "libresoc.v:79802.3-79811.6" wire $0\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79886.3-79895.6" + attribute \src "libresoc.v:79682.3-79691.6" wire width 3 $0\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:79896.3-79905.6" + attribute \src "libresoc.v:79692.3-79701.6" wire width 3 $0\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79836.3-79845.6" + attribute \src "libresoc.v:79632.3-79641.6" wire width 3 $0\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79846.3-79855.6" + attribute \src "libresoc.v:79642.3-79651.6" wire width 3 $0\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79856.3-79865.6" + attribute \src "libresoc.v:79652.3-79661.6" wire width 3 $0\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79876.3-79885.6" + attribute \src "libresoc.v:79672.3-79681.6" wire width 3 $0\dec22_sv_out2[2:0] - attribute \src "libresoc.v:79866.3-79875.6" + attribute \src "libresoc.v:79662.3-79671.6" wire width 3 $0\dec22_sv_out[2:0] - attribute \src "libresoc.v:79926.3-79935.6" + attribute \src "libresoc.v:79722.3-79731.6" wire width 2 $0\dec22_upd[1:0] - attribute \src "libresoc.v:79458.7-79458.20" + attribute \src "libresoc.v:79254.7-79254.20" wire $0\initial[0:0] - attribute \src "libresoc.v:80076.3-80085.6" + attribute \src "libresoc.v:79872.3-79881.6" wire width 2 $1\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:80086.3-80095.6" + attribute \src "libresoc.v:79882.3-79891.6" wire width 2 $1\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:79956.3-79965.6" + attribute \src "libresoc.v:79752.3-79761.6" wire width 8 $1\dec22_asmcode[7:0] - attribute \src "libresoc.v:79996.3-80005.6" + attribute \src "libresoc.v:79792.3-79801.6" wire $1\dec22_br[0:0] - attribute \src "libresoc.v:79816.3-79825.6" + attribute \src "libresoc.v:79612.3-79621.6" wire width 3 $1\dec22_cr_in[2:0] - attribute \src "libresoc.v:79826.3-79835.6" + attribute \src "libresoc.v:79622.3-79631.6" wire width 3 $1\dec22_cr_out[2:0] - attribute \src "libresoc.v:79946.3-79955.6" + attribute \src "libresoc.v:79742.3-79751.6" wire width 2 $1\dec22_cry_in[1:0] - attribute \src "libresoc.v:79986.3-79995.6" + attribute \src "libresoc.v:79782.3-79791.6" wire $1\dec22_cry_out[0:0] - attribute \src "libresoc.v:80026.3-80035.6" + attribute \src "libresoc.v:79822.3-79831.6" wire width 5 $1\dec22_form[4:0] - attribute \src "libresoc.v:79806.3-79815.6" + attribute \src "libresoc.v:79602.3-79611.6" wire width 14 $1\dec22_function_unit[13:0] - attribute \src "libresoc.v:80096.3-80105.6" + attribute \src "libresoc.v:79892.3-79901.6" wire width 3 $1\dec22_in1_sel[2:0] - attribute \src "libresoc.v:80106.3-80115.6" + attribute \src "libresoc.v:79902.3-79911.6" wire width 4 $1\dec22_in2_sel[3:0] - attribute \src "libresoc.v:80116.3-80125.6" + attribute \src "libresoc.v:79912.3-79921.6" wire width 2 $1\dec22_in3_sel[1:0] - attribute \src "libresoc.v:79916.3-79925.6" + attribute \src "libresoc.v:79712.3-79721.6" wire width 7 $1\dec22_internal_op[6:0] - attribute \src "libresoc.v:79966.3-79975.6" + attribute \src "libresoc.v:79762.3-79771.6" wire $1\dec22_inv_a[0:0] - attribute \src "libresoc.v:79976.3-79985.6" + attribute \src "libresoc.v:79772.3-79781.6" wire $1\dec22_inv_out[0:0] - attribute \src "libresoc.v:80036.3-80045.6" + attribute \src "libresoc.v:79832.3-79841.6" wire $1\dec22_is_32b[0:0] - attribute \src "libresoc.v:79906.3-79915.6" + attribute \src "libresoc.v:79702.3-79711.6" wire width 4 $1\dec22_ldst_len[3:0] - attribute \src "libresoc.v:80056.3-80065.6" + attribute \src "libresoc.v:79852.3-79861.6" wire $1\dec22_lk[0:0] - attribute \src "libresoc.v:80126.3-80135.6" + attribute \src "libresoc.v:79922.3-79931.6" wire width 3 $1\dec22_out_sel[2:0] - attribute \src "libresoc.v:79936.3-79945.6" + attribute \src "libresoc.v:79732.3-79741.6" wire width 2 $1\dec22_rc_sel[1:0] - attribute \src "libresoc.v:80016.3-80025.6" + attribute \src "libresoc.v:79812.3-79821.6" wire $1\dec22_rsrv[0:0] - attribute \src "libresoc.v:80066.3-80075.6" + attribute \src "libresoc.v:79862.3-79871.6" wire $1\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:80046.3-80055.6" + attribute \src "libresoc.v:79842.3-79851.6" wire $1\dec22_sgn[0:0] - attribute \src "libresoc.v:80006.3-80015.6" + attribute \src "libresoc.v:79802.3-79811.6" wire $1\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79886.3-79895.6" + attribute \src "libresoc.v:79682.3-79691.6" wire width 3 $1\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:79896.3-79905.6" + attribute \src "libresoc.v:79692.3-79701.6" wire width 3 $1\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79836.3-79845.6" + attribute \src "libresoc.v:79632.3-79641.6" wire width 3 $1\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79846.3-79855.6" + attribute \src "libresoc.v:79642.3-79651.6" wire width 3 $1\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79856.3-79865.6" + attribute \src "libresoc.v:79652.3-79661.6" wire width 3 $1\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79876.3-79885.6" + attribute \src "libresoc.v:79672.3-79681.6" wire width 3 $1\dec22_sv_out2[2:0] - attribute \src "libresoc.v:79866.3-79875.6" + attribute \src "libresoc.v:79662.3-79671.6" wire width 3 $1\dec22_sv_out[2:0] - attribute \src "libresoc.v:79926.3-79935.6" + attribute \src "libresoc.v:79722.3-79731.6" wire width 2 $1\dec22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -128247,28 +128043,28 @@ module \dec22 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec22_upd - attribute \src "libresoc.v:79458.7-79458.15" + attribute \src "libresoc.v:79254.7-79254.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch - attribute \src "libresoc.v:79458.7-79458.20" - process $proc$libresoc.v:79458$3766 + attribute \src "libresoc.v:79254.7-79254.20" + process $proc$libresoc.v:79254$3766 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:79806.3-79815.6" - process $proc$libresoc.v:79806$3733 + attribute \src "libresoc.v:79602.3-79611.6" + process $proc$libresoc.v:79602$3733 assign { } { } assign { } { } assign $0\dec22_function_unit[13:0] $1\dec22_function_unit[13:0] - attribute \src "libresoc.v:79807.5-79807.29" + attribute \src "libresoc.v:79603.5-79603.29" switch \initial - attribute \src "libresoc.v:79807.9-79807.17" + attribute \src "libresoc.v:79603.9-79603.17" case 1'1 case end @@ -128284,14 +128080,14 @@ module \dec22 sync always update \dec22_function_unit $0\dec22_function_unit[13:0] end - attribute \src "libresoc.v:79816.3-79825.6" - process $proc$libresoc.v:79816$3734 + attribute \src "libresoc.v:79612.3-79621.6" + process $proc$libresoc.v:79612$3734 assign { } { } assign { } { } assign $0\dec22_cr_in[2:0] $1\dec22_cr_in[2:0] - attribute \src "libresoc.v:79817.5-79817.29" + attribute \src "libresoc.v:79613.5-79613.29" switch \initial - attribute \src "libresoc.v:79817.9-79817.17" + attribute \src "libresoc.v:79613.9-79613.17" case 1'1 case end @@ -128307,14 +128103,14 @@ module \dec22 sync always update \dec22_cr_in $0\dec22_cr_in[2:0] end - attribute \src "libresoc.v:79826.3-79835.6" - process $proc$libresoc.v:79826$3735 + attribute \src "libresoc.v:79622.3-79631.6" + process $proc$libresoc.v:79622$3735 assign { } { } assign { } { } assign $0\dec22_cr_out[2:0] $1\dec22_cr_out[2:0] - attribute \src "libresoc.v:79827.5-79827.29" + attribute \src "libresoc.v:79623.5-79623.29" switch \initial - attribute \src "libresoc.v:79827.9-79827.17" + attribute \src "libresoc.v:79623.9-79623.17" case 1'1 case end @@ -128330,14 +128126,14 @@ module \dec22 sync always update \dec22_cr_out $0\dec22_cr_out[2:0] end - attribute \src "libresoc.v:79836.3-79845.6" - process $proc$libresoc.v:79836$3736 + attribute \src "libresoc.v:79632.3-79641.6" + process $proc$libresoc.v:79632$3736 assign { } { } assign { } { } assign $0\dec22_sv_in1[2:0] $1\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79837.5-79837.29" + attribute \src "libresoc.v:79633.5-79633.29" switch \initial - attribute \src "libresoc.v:79837.9-79837.17" + attribute \src "libresoc.v:79633.9-79633.17" case 1'1 case end @@ -128353,14 +128149,14 @@ module \dec22 sync always update \dec22_sv_in1 $0\dec22_sv_in1[2:0] end - attribute \src "libresoc.v:79846.3-79855.6" - process $proc$libresoc.v:79846$3737 + attribute \src "libresoc.v:79642.3-79651.6" + process $proc$libresoc.v:79642$3737 assign { } { } assign { } { } assign $0\dec22_sv_in2[2:0] $1\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79847.5-79847.29" + attribute \src "libresoc.v:79643.5-79643.29" switch \initial - attribute \src "libresoc.v:79847.9-79847.17" + attribute \src "libresoc.v:79643.9-79643.17" case 1'1 case end @@ -128376,14 +128172,14 @@ module \dec22 sync always update \dec22_sv_in2 $0\dec22_sv_in2[2:0] end - attribute \src "libresoc.v:79856.3-79865.6" - process $proc$libresoc.v:79856$3738 + attribute \src "libresoc.v:79652.3-79661.6" + process $proc$libresoc.v:79652$3738 assign { } { } assign { } { } assign $0\dec22_sv_in3[2:0] $1\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79857.5-79857.29" + attribute \src "libresoc.v:79653.5-79653.29" switch \initial - attribute \src "libresoc.v:79857.9-79857.17" + attribute \src "libresoc.v:79653.9-79653.17" case 1'1 case end @@ -128399,14 +128195,14 @@ module \dec22 sync always update \dec22_sv_in3 $0\dec22_sv_in3[2:0] end - attribute \src "libresoc.v:79866.3-79875.6" - process $proc$libresoc.v:79866$3739 + attribute \src "libresoc.v:79662.3-79671.6" + process $proc$libresoc.v:79662$3739 assign { } { } assign { } { } assign $0\dec22_sv_out[2:0] $1\dec22_sv_out[2:0] - attribute \src "libresoc.v:79867.5-79867.29" + attribute \src "libresoc.v:79663.5-79663.29" switch \initial - attribute \src "libresoc.v:79867.9-79867.17" + attribute \src "libresoc.v:79663.9-79663.17" case 1'1 case end @@ -128422,14 +128218,14 @@ module \dec22 sync always update \dec22_sv_out $0\dec22_sv_out[2:0] end - attribute \src "libresoc.v:79876.3-79885.6" - process $proc$libresoc.v:79876$3740 + attribute \src "libresoc.v:79672.3-79681.6" + process $proc$libresoc.v:79672$3740 assign { } { } assign { } { } assign $0\dec22_sv_out2[2:0] $1\dec22_sv_out2[2:0] - attribute \src "libresoc.v:79877.5-79877.29" + attribute \src "libresoc.v:79673.5-79673.29" switch \initial - attribute \src "libresoc.v:79877.9-79877.17" + attribute \src "libresoc.v:79673.9-79673.17" case 1'1 case end @@ -128445,14 +128241,14 @@ module \dec22 sync always update \dec22_sv_out2 $0\dec22_sv_out2[2:0] end - attribute \src "libresoc.v:79886.3-79895.6" - process $proc$libresoc.v:79886$3741 + attribute \src "libresoc.v:79682.3-79691.6" + process $proc$libresoc.v:79682$3741 assign { } { } assign { } { } assign $0\dec22_sv_cr_in[2:0] $1\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:79887.5-79887.29" + attribute \src "libresoc.v:79683.5-79683.29" switch \initial - attribute \src "libresoc.v:79887.9-79887.17" + attribute \src "libresoc.v:79683.9-79683.17" case 1'1 case end @@ -128468,14 +128264,14 @@ module \dec22 sync always update \dec22_sv_cr_in $0\dec22_sv_cr_in[2:0] end - attribute \src "libresoc.v:79896.3-79905.6" - process $proc$libresoc.v:79896$3742 + attribute \src "libresoc.v:79692.3-79701.6" + process $proc$libresoc.v:79692$3742 assign { } { } assign { } { } assign $0\dec22_sv_cr_out[2:0] $1\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79897.5-79897.29" + attribute \src "libresoc.v:79693.5-79693.29" switch \initial - attribute \src "libresoc.v:79897.9-79897.17" + attribute \src "libresoc.v:79693.9-79693.17" case 1'1 case end @@ -128491,14 +128287,14 @@ module \dec22 sync always update \dec22_sv_cr_out $0\dec22_sv_cr_out[2:0] end - attribute \src "libresoc.v:79906.3-79915.6" - process $proc$libresoc.v:79906$3743 + attribute \src "libresoc.v:79702.3-79711.6" + process $proc$libresoc.v:79702$3743 assign { } { } assign { } { } assign $0\dec22_ldst_len[3:0] $1\dec22_ldst_len[3:0] - attribute \src "libresoc.v:79907.5-79907.29" + attribute \src "libresoc.v:79703.5-79703.29" switch \initial - attribute \src "libresoc.v:79907.9-79907.17" + attribute \src "libresoc.v:79703.9-79703.17" case 1'1 case end @@ -128514,14 +128310,14 @@ module \dec22 sync always update \dec22_ldst_len $0\dec22_ldst_len[3:0] end - attribute \src "libresoc.v:79916.3-79925.6" - process $proc$libresoc.v:79916$3744 + attribute \src "libresoc.v:79712.3-79721.6" + process $proc$libresoc.v:79712$3744 assign { } { } assign { } { } assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0] - attribute \src "libresoc.v:79917.5-79917.29" + attribute \src "libresoc.v:79713.5-79713.29" switch \initial - attribute \src "libresoc.v:79917.9-79917.17" + attribute \src "libresoc.v:79713.9-79713.17" case 1'1 case end @@ -128537,14 +128333,14 @@ module \dec22 sync always update \dec22_internal_op $0\dec22_internal_op[6:0] end - attribute \src "libresoc.v:79926.3-79935.6" - process $proc$libresoc.v:79926$3745 + attribute \src "libresoc.v:79722.3-79731.6" + process $proc$libresoc.v:79722$3745 assign { } { } assign { } { } assign $0\dec22_upd[1:0] $1\dec22_upd[1:0] - attribute \src "libresoc.v:79927.5-79927.29" + attribute \src "libresoc.v:79723.5-79723.29" switch \initial - attribute \src "libresoc.v:79927.9-79927.17" + attribute \src "libresoc.v:79723.9-79723.17" case 1'1 case end @@ -128560,14 +128356,14 @@ module \dec22 sync always update \dec22_upd $0\dec22_upd[1:0] end - attribute \src "libresoc.v:79936.3-79945.6" - process $proc$libresoc.v:79936$3746 + attribute \src "libresoc.v:79732.3-79741.6" + process $proc$libresoc.v:79732$3746 assign { } { } assign { } { } assign $0\dec22_rc_sel[1:0] $1\dec22_rc_sel[1:0] - attribute \src "libresoc.v:79937.5-79937.29" + attribute \src "libresoc.v:79733.5-79733.29" switch \initial - attribute \src "libresoc.v:79937.9-79937.17" + attribute \src "libresoc.v:79733.9-79733.17" case 1'1 case end @@ -128583,14 +128379,14 @@ module \dec22 sync always update \dec22_rc_sel $0\dec22_rc_sel[1:0] end - attribute \src "libresoc.v:79946.3-79955.6" - process $proc$libresoc.v:79946$3747 + attribute \src "libresoc.v:79742.3-79751.6" + process $proc$libresoc.v:79742$3747 assign { } { } assign { } { } assign $0\dec22_cry_in[1:0] $1\dec22_cry_in[1:0] - attribute \src "libresoc.v:79947.5-79947.29" + attribute \src "libresoc.v:79743.5-79743.29" switch \initial - attribute \src "libresoc.v:79947.9-79947.17" + attribute \src "libresoc.v:79743.9-79743.17" case 1'1 case end @@ -128606,14 +128402,14 @@ module \dec22 sync always update \dec22_cry_in $0\dec22_cry_in[1:0] end - attribute \src "libresoc.v:79956.3-79965.6" - process $proc$libresoc.v:79956$3748 + attribute \src "libresoc.v:79752.3-79761.6" + process $proc$libresoc.v:79752$3748 assign { } { } assign { } { } assign $0\dec22_asmcode[7:0] $1\dec22_asmcode[7:0] - attribute \src "libresoc.v:79957.5-79957.29" + attribute \src "libresoc.v:79753.5-79753.29" switch \initial - attribute \src "libresoc.v:79957.9-79957.17" + attribute \src "libresoc.v:79753.9-79753.17" case 1'1 case end @@ -128629,14 +128425,14 @@ module \dec22 sync always update \dec22_asmcode $0\dec22_asmcode[7:0] end - attribute \src "libresoc.v:79966.3-79975.6" - process $proc$libresoc.v:79966$3749 + attribute \src "libresoc.v:79762.3-79771.6" + process $proc$libresoc.v:79762$3749 assign { } { } assign { } { } assign $0\dec22_inv_a[0:0] $1\dec22_inv_a[0:0] - attribute \src "libresoc.v:79967.5-79967.29" + attribute \src "libresoc.v:79763.5-79763.29" switch \initial - attribute \src "libresoc.v:79967.9-79967.17" + attribute \src "libresoc.v:79763.9-79763.17" case 1'1 case end @@ -128652,14 +128448,14 @@ module \dec22 sync always update \dec22_inv_a $0\dec22_inv_a[0:0] end - attribute \src "libresoc.v:79976.3-79985.6" - process $proc$libresoc.v:79976$3750 + attribute \src "libresoc.v:79772.3-79781.6" + process $proc$libresoc.v:79772$3750 assign { } { } assign { } { } assign $0\dec22_inv_out[0:0] $1\dec22_inv_out[0:0] - attribute \src "libresoc.v:79977.5-79977.29" + attribute \src "libresoc.v:79773.5-79773.29" switch \initial - attribute \src "libresoc.v:79977.9-79977.17" + attribute \src "libresoc.v:79773.9-79773.17" case 1'1 case end @@ -128675,14 +128471,14 @@ module \dec22 sync always update \dec22_inv_out $0\dec22_inv_out[0:0] end - attribute \src "libresoc.v:79986.3-79995.6" - process $proc$libresoc.v:79986$3751 + attribute \src "libresoc.v:79782.3-79791.6" + process $proc$libresoc.v:79782$3751 assign { } { } assign { } { } assign $0\dec22_cry_out[0:0] $1\dec22_cry_out[0:0] - attribute \src "libresoc.v:79987.5-79987.29" + attribute \src "libresoc.v:79783.5-79783.29" switch \initial - attribute \src "libresoc.v:79987.9-79987.17" + attribute \src "libresoc.v:79783.9-79783.17" case 1'1 case end @@ -128698,14 +128494,14 @@ module \dec22 sync always update \dec22_cry_out $0\dec22_cry_out[0:0] end - attribute \src "libresoc.v:79996.3-80005.6" - process $proc$libresoc.v:79996$3752 + attribute \src "libresoc.v:79792.3-79801.6" + process $proc$libresoc.v:79792$3752 assign { } { } assign { } { } assign $0\dec22_br[0:0] $1\dec22_br[0:0] - attribute \src "libresoc.v:79997.5-79997.29" + attribute \src "libresoc.v:79793.5-79793.29" switch \initial - attribute \src "libresoc.v:79997.9-79997.17" + attribute \src "libresoc.v:79793.9-79793.17" case 1'1 case end @@ -128721,14 +128517,14 @@ module \dec22 sync always update \dec22_br $0\dec22_br[0:0] end - attribute \src "libresoc.v:80006.3-80015.6" - process $proc$libresoc.v:80006$3753 + attribute \src "libresoc.v:79802.3-79811.6" + process $proc$libresoc.v:79802$3753 assign { } { } assign { } { } assign $0\dec22_sgn_ext[0:0] $1\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:80007.5-80007.29" + attribute \src "libresoc.v:79803.5-79803.29" switch \initial - attribute \src "libresoc.v:80007.9-80007.17" + attribute \src "libresoc.v:79803.9-79803.17" case 1'1 case end @@ -128744,14 +128540,14 @@ module \dec22 sync always update \dec22_sgn_ext $0\dec22_sgn_ext[0:0] end - attribute \src "libresoc.v:80016.3-80025.6" - process $proc$libresoc.v:80016$3754 + attribute \src "libresoc.v:79812.3-79821.6" + process $proc$libresoc.v:79812$3754 assign { } { } assign { } { } assign $0\dec22_rsrv[0:0] $1\dec22_rsrv[0:0] - attribute \src "libresoc.v:80017.5-80017.29" + attribute \src "libresoc.v:79813.5-79813.29" switch \initial - attribute \src "libresoc.v:80017.9-80017.17" + attribute \src "libresoc.v:79813.9-79813.17" case 1'1 case end @@ -128767,14 +128563,14 @@ module \dec22 sync always update \dec22_rsrv $0\dec22_rsrv[0:0] end - attribute \src "libresoc.v:80026.3-80035.6" - process $proc$libresoc.v:80026$3755 + attribute \src "libresoc.v:79822.3-79831.6" + process $proc$libresoc.v:79822$3755 assign { } { } assign { } { } assign $0\dec22_form[4:0] $1\dec22_form[4:0] - attribute \src "libresoc.v:80027.5-80027.29" + attribute \src "libresoc.v:79823.5-79823.29" switch \initial - attribute \src "libresoc.v:80027.9-80027.17" + attribute \src "libresoc.v:79823.9-79823.17" case 1'1 case end @@ -128790,14 +128586,14 @@ module \dec22 sync always update \dec22_form $0\dec22_form[4:0] end - attribute \src "libresoc.v:80036.3-80045.6" - process $proc$libresoc.v:80036$3756 + attribute \src "libresoc.v:79832.3-79841.6" + process $proc$libresoc.v:79832$3756 assign { } { } assign { } { } assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0] - attribute \src "libresoc.v:80037.5-80037.29" + attribute \src "libresoc.v:79833.5-79833.29" switch \initial - attribute \src "libresoc.v:80037.9-80037.17" + attribute \src "libresoc.v:79833.9-79833.17" case 1'1 case end @@ -128813,14 +128609,14 @@ module \dec22 sync always update \dec22_is_32b $0\dec22_is_32b[0:0] end - attribute \src "libresoc.v:80046.3-80055.6" - process $proc$libresoc.v:80046$3757 + attribute \src "libresoc.v:79842.3-79851.6" + process $proc$libresoc.v:79842$3757 assign { } { } assign { } { } assign $0\dec22_sgn[0:0] $1\dec22_sgn[0:0] - attribute \src "libresoc.v:80047.5-80047.29" + attribute \src "libresoc.v:79843.5-79843.29" switch \initial - attribute \src "libresoc.v:80047.9-80047.17" + attribute \src "libresoc.v:79843.9-79843.17" case 1'1 case end @@ -128836,14 +128632,14 @@ module \dec22 sync always update \dec22_sgn $0\dec22_sgn[0:0] end - attribute \src "libresoc.v:80056.3-80065.6" - process $proc$libresoc.v:80056$3758 + attribute \src "libresoc.v:79852.3-79861.6" + process $proc$libresoc.v:79852$3758 assign { } { } assign { } { } assign $0\dec22_lk[0:0] $1\dec22_lk[0:0] - attribute \src "libresoc.v:80057.5-80057.29" + attribute \src "libresoc.v:79853.5-79853.29" switch \initial - attribute \src "libresoc.v:80057.9-80057.17" + attribute \src "libresoc.v:79853.9-79853.17" case 1'1 case end @@ -128859,14 +128655,14 @@ module \dec22 sync always update \dec22_lk $0\dec22_lk[0:0] end - attribute \src "libresoc.v:80066.3-80075.6" - process $proc$libresoc.v:80066$3759 + attribute \src "libresoc.v:79862.3-79871.6" + process $proc$libresoc.v:79862$3759 assign { } { } assign { } { } assign $0\dec22_sgl_pipe[0:0] $1\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:80067.5-80067.29" + attribute \src "libresoc.v:79863.5-79863.29" switch \initial - attribute \src "libresoc.v:80067.9-80067.17" + attribute \src "libresoc.v:79863.9-79863.17" case 1'1 case end @@ -128882,14 +128678,14 @@ module \dec22 sync always update \dec22_sgl_pipe $0\dec22_sgl_pipe[0:0] end - attribute \src "libresoc.v:80076.3-80085.6" - process $proc$libresoc.v:80076$3760 + attribute \src "libresoc.v:79872.3-79881.6" + process $proc$libresoc.v:79872$3760 assign { } { } assign { } { } assign $0\dec22_SV_Etype[1:0] $1\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:80077.5-80077.29" + attribute \src "libresoc.v:79873.5-79873.29" switch \initial - attribute \src "libresoc.v:80077.9-80077.17" + attribute \src "libresoc.v:79873.9-79873.17" case 1'1 case end @@ -128905,14 +128701,14 @@ module \dec22 sync always update \dec22_SV_Etype $0\dec22_SV_Etype[1:0] end - attribute \src "libresoc.v:80086.3-80095.6" - process $proc$libresoc.v:80086$3761 + attribute \src "libresoc.v:79882.3-79891.6" + process $proc$libresoc.v:79882$3761 assign { } { } assign { } { } assign $0\dec22_SV_Ptype[1:0] $1\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:80087.5-80087.29" + attribute \src "libresoc.v:79883.5-79883.29" switch \initial - attribute \src "libresoc.v:80087.9-80087.17" + attribute \src "libresoc.v:79883.9-79883.17" case 1'1 case end @@ -128928,14 +128724,14 @@ module \dec22 sync always update \dec22_SV_Ptype $0\dec22_SV_Ptype[1:0] end - attribute \src "libresoc.v:80096.3-80105.6" - process $proc$libresoc.v:80096$3762 + attribute \src "libresoc.v:79892.3-79901.6" + process $proc$libresoc.v:79892$3762 assign { } { } assign { } { } assign $0\dec22_in1_sel[2:0] $1\dec22_in1_sel[2:0] - attribute \src "libresoc.v:80097.5-80097.29" + attribute \src "libresoc.v:79893.5-79893.29" switch \initial - attribute \src "libresoc.v:80097.9-80097.17" + attribute \src "libresoc.v:79893.9-79893.17" case 1'1 case end @@ -128951,14 +128747,14 @@ module \dec22 sync always update \dec22_in1_sel $0\dec22_in1_sel[2:0] end - attribute \src "libresoc.v:80106.3-80115.6" - process $proc$libresoc.v:80106$3763 + attribute \src "libresoc.v:79902.3-79911.6" + process $proc$libresoc.v:79902$3763 assign { } { } assign { } { } assign $0\dec22_in2_sel[3:0] $1\dec22_in2_sel[3:0] - attribute \src "libresoc.v:80107.5-80107.29" + attribute \src "libresoc.v:79903.5-79903.29" switch \initial - attribute \src "libresoc.v:80107.9-80107.17" + attribute \src "libresoc.v:79903.9-79903.17" case 1'1 case end @@ -128974,14 +128770,14 @@ module \dec22 sync always update \dec22_in2_sel $0\dec22_in2_sel[3:0] end - attribute \src "libresoc.v:80116.3-80125.6" - process $proc$libresoc.v:80116$3764 + attribute \src "libresoc.v:79912.3-79921.6" + process $proc$libresoc.v:79912$3764 assign { } { } assign { } { } assign $0\dec22_in3_sel[1:0] $1\dec22_in3_sel[1:0] - attribute \src "libresoc.v:80117.5-80117.29" + attribute \src "libresoc.v:79913.5-79913.29" switch \initial - attribute \src "libresoc.v:80117.9-80117.17" + attribute \src "libresoc.v:79913.9-79913.17" case 1'1 case end @@ -128997,14 +128793,14 @@ module \dec22 sync always update \dec22_in3_sel $0\dec22_in3_sel[1:0] end - attribute \src "libresoc.v:80126.3-80135.6" - process $proc$libresoc.v:80126$3765 + attribute \src "libresoc.v:79922.3-79931.6" + process $proc$libresoc.v:79922$3765 assign { } { } assign { } { } assign $0\dec22_out_sel[2:0] $1\dec22_out_sel[2:0] - attribute \src "libresoc.v:80127.5-80127.29" + attribute \src "libresoc.v:79923.5-79923.29" switch \initial - attribute \src "libresoc.v:80127.9-80127.17" + attribute \src "libresoc.v:79923.9-79923.17" case 1'1 case end @@ -129022,144 +128818,144 @@ module \dec22 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:80141.1-81712.10" +attribute \src "libresoc.v:79937.1-81508.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" attribute \generator "nMigen" module \dec30 - attribute \src "libresoc.v:81489.3-81525.6" + attribute \src "libresoc.v:81285.3-81321.6" wire width 2 $0\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81526.3-81562.6" + attribute \src "libresoc.v:81322.3-81358.6" wire width 2 $0\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:81045.3-81081.6" + attribute \src "libresoc.v:80841.3-80877.6" wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:81193.3-81229.6" + attribute \src "libresoc.v:80989.3-81025.6" wire $0\dec30_br[0:0] - attribute \src "libresoc.v:80527.3-80563.6" + attribute \src "libresoc.v:80323.3-80359.6" wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:80564.3-80600.6" + attribute \src "libresoc.v:80360.3-80396.6" wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:81008.3-81044.6" + attribute \src "libresoc.v:80804.3-80840.6" wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:81156.3-81192.6" + attribute \src "libresoc.v:80952.3-80988.6" wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:81304.3-81340.6" + attribute \src "libresoc.v:81100.3-81136.6" wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:80490.3-80526.6" + attribute \src "libresoc.v:80286.3-80322.6" wire width 14 $0\dec30_function_unit[13:0] - attribute \src "libresoc.v:81563.3-81599.6" + attribute \src "libresoc.v:81359.3-81395.6" wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81600.3-81636.6" + attribute \src "libresoc.v:81396.3-81432.6" wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81637.3-81673.6" + attribute \src "libresoc.v:81433.3-81469.6" wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:80897.3-80933.6" + attribute \src "libresoc.v:80693.3-80729.6" wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:81082.3-81118.6" + attribute \src "libresoc.v:80878.3-80914.6" wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:81119.3-81155.6" + attribute \src "libresoc.v:80915.3-80951.6" wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:81341.3-81377.6" + attribute \src "libresoc.v:81137.3-81173.6" wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:80860.3-80896.6" + attribute \src "libresoc.v:80656.3-80692.6" wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:81415.3-81451.6" + attribute \src "libresoc.v:81211.3-81247.6" wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:81674.3-81710.6" + attribute \src "libresoc.v:81470.3-81506.6" wire width 3 $0\dec30_out_sel[2:0] - attribute \src "libresoc.v:80971.3-81007.6" + attribute \src "libresoc.v:80767.3-80803.6" wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:81267.3-81303.6" + attribute \src "libresoc.v:81063.3-81099.6" wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:81452.3-81488.6" + attribute \src "libresoc.v:81248.3-81284.6" wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81378.3-81414.6" + attribute \src "libresoc.v:81174.3-81210.6" wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:81230.3-81266.6" + attribute \src "libresoc.v:81026.3-81062.6" wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80786.3-80822.6" + attribute \src "libresoc.v:80582.3-80618.6" wire width 3 $0\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80823.3-80859.6" + attribute \src "libresoc.v:80619.3-80655.6" wire width 3 $0\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80601.3-80637.6" + attribute \src "libresoc.v:80397.3-80433.6" wire width 3 $0\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80638.3-80674.6" + attribute \src "libresoc.v:80434.3-80470.6" wire width 3 $0\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80675.3-80711.6" + attribute \src "libresoc.v:80471.3-80507.6" wire width 3 $0\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80749.3-80785.6" + attribute \src "libresoc.v:80545.3-80581.6" wire width 3 $0\dec30_sv_out2[2:0] - attribute \src "libresoc.v:80712.3-80748.6" + attribute \src "libresoc.v:80508.3-80544.6" wire width 3 $0\dec30_sv_out[2:0] - attribute \src "libresoc.v:80934.3-80970.6" + attribute \src "libresoc.v:80730.3-80766.6" wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:80142.7-80142.20" + attribute \src "libresoc.v:79938.7-79938.20" wire $0\initial[0:0] - attribute \src "libresoc.v:81489.3-81525.6" + attribute \src "libresoc.v:81285.3-81321.6" wire width 2 $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81526.3-81562.6" + attribute \src "libresoc.v:81322.3-81358.6" wire width 2 $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:81045.3-81081.6" + attribute \src "libresoc.v:80841.3-80877.6" wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:81193.3-81229.6" + attribute \src "libresoc.v:80989.3-81025.6" wire $1\dec30_br[0:0] - attribute \src "libresoc.v:80527.3-80563.6" + attribute \src "libresoc.v:80323.3-80359.6" wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:80564.3-80600.6" + attribute \src "libresoc.v:80360.3-80396.6" wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:81008.3-81044.6" + attribute \src "libresoc.v:80804.3-80840.6" wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:81156.3-81192.6" + attribute \src "libresoc.v:80952.3-80988.6" wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:81304.3-81340.6" + attribute \src "libresoc.v:81100.3-81136.6" wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:80490.3-80526.6" + attribute \src "libresoc.v:80286.3-80322.6" wire width 14 $1\dec30_function_unit[13:0] - attribute \src "libresoc.v:81563.3-81599.6" + attribute \src "libresoc.v:81359.3-81395.6" wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81600.3-81636.6" + attribute \src "libresoc.v:81396.3-81432.6" wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81637.3-81673.6" + attribute \src "libresoc.v:81433.3-81469.6" wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:80897.3-80933.6" + attribute \src "libresoc.v:80693.3-80729.6" wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:81082.3-81118.6" + attribute \src "libresoc.v:80878.3-80914.6" wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:81119.3-81155.6" + attribute \src "libresoc.v:80915.3-80951.6" wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:81341.3-81377.6" + attribute \src "libresoc.v:81137.3-81173.6" wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:80860.3-80896.6" + attribute \src "libresoc.v:80656.3-80692.6" wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:81415.3-81451.6" + attribute \src "libresoc.v:81211.3-81247.6" wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:81674.3-81710.6" + attribute \src "libresoc.v:81470.3-81506.6" wire width 3 $1\dec30_out_sel[2:0] - attribute \src "libresoc.v:80971.3-81007.6" + attribute \src "libresoc.v:80767.3-80803.6" wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:81267.3-81303.6" + attribute \src "libresoc.v:81063.3-81099.6" wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:81452.3-81488.6" + attribute \src "libresoc.v:81248.3-81284.6" wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81378.3-81414.6" + attribute \src "libresoc.v:81174.3-81210.6" wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:81230.3-81266.6" + attribute \src "libresoc.v:81026.3-81062.6" wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80786.3-80822.6" + attribute \src "libresoc.v:80582.3-80618.6" wire width 3 $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80823.3-80859.6" + attribute \src "libresoc.v:80619.3-80655.6" wire width 3 $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80601.3-80637.6" + attribute \src "libresoc.v:80397.3-80433.6" wire width 3 $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80638.3-80674.6" + attribute \src "libresoc.v:80434.3-80470.6" wire width 3 $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80675.3-80711.6" + attribute \src "libresoc.v:80471.3-80507.6" wire width 3 $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80749.3-80785.6" + attribute \src "libresoc.v:80545.3-80581.6" wire width 3 $1\dec30_sv_out2[2:0] - attribute \src "libresoc.v:80712.3-80748.6" + attribute \src "libresoc.v:80508.3-80544.6" wire width 3 $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:80934.3-80970.6" + attribute \src "libresoc.v:80730.3-80766.6" wire width 2 $1\dec30_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -129471,28 +129267,28 @@ module \dec30 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec30_upd - attribute \src "libresoc.v:80142.7-80142.15" + attribute \src "libresoc.v:79938.7-79938.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch - attribute \src "libresoc.v:80142.7-80142.20" - process $proc$libresoc.v:80142$3800 + attribute \src "libresoc.v:79938.7-79938.20" + process $proc$libresoc.v:79938$3800 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:80490.3-80526.6" - process $proc$libresoc.v:80490$3767 + attribute \src "libresoc.v:80286.3-80322.6" + process $proc$libresoc.v:80286$3767 assign { } { } assign { } { } assign $0\dec30_function_unit[13:0] $1\dec30_function_unit[13:0] - attribute \src "libresoc.v:80491.5-80491.29" + attribute \src "libresoc.v:80287.5-80287.29" switch \initial - attribute \src "libresoc.v:80491.9-80491.17" + attribute \src "libresoc.v:80287.9-80287.17" case 1'1 case end @@ -129544,14 +129340,14 @@ module \dec30 sync always update \dec30_function_unit $0\dec30_function_unit[13:0] end - attribute \src "libresoc.v:80527.3-80563.6" - process $proc$libresoc.v:80527$3768 + attribute \src "libresoc.v:80323.3-80359.6" + process $proc$libresoc.v:80323$3768 assign { } { } assign { } { } assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:80528.5-80528.29" + attribute \src "libresoc.v:80324.5-80324.29" switch \initial - attribute \src "libresoc.v:80528.9-80528.17" + attribute \src "libresoc.v:80324.9-80324.17" case 1'1 case end @@ -129603,14 +129399,14 @@ module \dec30 sync always update \dec30_cr_in $0\dec30_cr_in[2:0] end - attribute \src "libresoc.v:80564.3-80600.6" - process $proc$libresoc.v:80564$3769 + attribute \src "libresoc.v:80360.3-80396.6" + process $proc$libresoc.v:80360$3769 assign { } { } assign { } { } assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:80565.5-80565.29" + attribute \src "libresoc.v:80361.5-80361.29" switch \initial - attribute \src "libresoc.v:80565.9-80565.17" + attribute \src "libresoc.v:80361.9-80361.17" case 1'1 case end @@ -129662,14 +129458,14 @@ module \dec30 sync always update \dec30_cr_out $0\dec30_cr_out[2:0] end - attribute \src "libresoc.v:80601.3-80637.6" - process $proc$libresoc.v:80601$3770 + attribute \src "libresoc.v:80397.3-80433.6" + process $proc$libresoc.v:80397$3770 assign { } { } assign { } { } assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80602.5-80602.29" + attribute \src "libresoc.v:80398.5-80398.29" switch \initial - attribute \src "libresoc.v:80602.9-80602.17" + attribute \src "libresoc.v:80398.9-80398.17" case 1'1 case end @@ -129721,14 +129517,14 @@ module \dec30 sync always update \dec30_sv_in1 $0\dec30_sv_in1[2:0] end - attribute \src "libresoc.v:80638.3-80674.6" - process $proc$libresoc.v:80638$3771 + attribute \src "libresoc.v:80434.3-80470.6" + process $proc$libresoc.v:80434$3771 assign { } { } assign { } { } assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80639.5-80639.29" + attribute \src "libresoc.v:80435.5-80435.29" switch \initial - attribute \src "libresoc.v:80639.9-80639.17" + attribute \src "libresoc.v:80435.9-80435.17" case 1'1 case end @@ -129780,14 +129576,14 @@ module \dec30 sync always update \dec30_sv_in2 $0\dec30_sv_in2[2:0] end - attribute \src "libresoc.v:80675.3-80711.6" - process $proc$libresoc.v:80675$3772 + attribute \src "libresoc.v:80471.3-80507.6" + process $proc$libresoc.v:80471$3772 assign { } { } assign { } { } assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80676.5-80676.29" + attribute \src "libresoc.v:80472.5-80472.29" switch \initial - attribute \src "libresoc.v:80676.9-80676.17" + attribute \src "libresoc.v:80472.9-80472.17" case 1'1 case end @@ -129839,14 +129635,14 @@ module \dec30 sync always update \dec30_sv_in3 $0\dec30_sv_in3[2:0] end - attribute \src "libresoc.v:80712.3-80748.6" - process $proc$libresoc.v:80712$3773 + attribute \src "libresoc.v:80508.3-80544.6" + process $proc$libresoc.v:80508$3773 assign { } { } assign { } { } assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:80713.5-80713.29" + attribute \src "libresoc.v:80509.5-80509.29" switch \initial - attribute \src "libresoc.v:80713.9-80713.17" + attribute \src "libresoc.v:80509.9-80509.17" case 1'1 case end @@ -129898,14 +129694,14 @@ module \dec30 sync always update \dec30_sv_out $0\dec30_sv_out[2:0] end - attribute \src "libresoc.v:80749.3-80785.6" - process $proc$libresoc.v:80749$3774 + attribute \src "libresoc.v:80545.3-80581.6" + process $proc$libresoc.v:80545$3774 assign { } { } assign { } { } assign $0\dec30_sv_out2[2:0] $1\dec30_sv_out2[2:0] - attribute \src "libresoc.v:80750.5-80750.29" + attribute \src "libresoc.v:80546.5-80546.29" switch \initial - attribute \src "libresoc.v:80750.9-80750.17" + attribute \src "libresoc.v:80546.9-80546.17" case 1'1 case end @@ -129957,14 +129753,14 @@ module \dec30 sync always update \dec30_sv_out2 $0\dec30_sv_out2[2:0] end - attribute \src "libresoc.v:80786.3-80822.6" - process $proc$libresoc.v:80786$3775 + attribute \src "libresoc.v:80582.3-80618.6" + process $proc$libresoc.v:80582$3775 assign { } { } assign { } { } assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80787.5-80787.29" + attribute \src "libresoc.v:80583.5-80583.29" switch \initial - attribute \src "libresoc.v:80787.9-80787.17" + attribute \src "libresoc.v:80583.9-80583.17" case 1'1 case end @@ -130016,14 +129812,14 @@ module \dec30 sync always update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0] end - attribute \src "libresoc.v:80823.3-80859.6" - process $proc$libresoc.v:80823$3776 + attribute \src "libresoc.v:80619.3-80655.6" + process $proc$libresoc.v:80619$3776 assign { } { } assign { } { } assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80824.5-80824.29" + attribute \src "libresoc.v:80620.5-80620.29" switch \initial - attribute \src "libresoc.v:80824.9-80824.17" + attribute \src "libresoc.v:80620.9-80620.17" case 1'1 case end @@ -130075,14 +129871,14 @@ module \dec30 sync always update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0] end - attribute \src "libresoc.v:80860.3-80896.6" - process $proc$libresoc.v:80860$3777 + attribute \src "libresoc.v:80656.3-80692.6" + process $proc$libresoc.v:80656$3777 assign { } { } assign { } { } assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:80861.5-80861.29" + attribute \src "libresoc.v:80657.5-80657.29" switch \initial - attribute \src "libresoc.v:80861.9-80861.17" + attribute \src "libresoc.v:80657.9-80657.17" case 1'1 case end @@ -130134,14 +129930,14 @@ module \dec30 sync always update \dec30_ldst_len $0\dec30_ldst_len[3:0] end - attribute \src "libresoc.v:80897.3-80933.6" - process $proc$libresoc.v:80897$3778 + attribute \src "libresoc.v:80693.3-80729.6" + process $proc$libresoc.v:80693$3778 assign { } { } assign { } { } assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:80898.5-80898.29" + attribute \src "libresoc.v:80694.5-80694.29" switch \initial - attribute \src "libresoc.v:80898.9-80898.17" + attribute \src "libresoc.v:80694.9-80694.17" case 1'1 case end @@ -130193,14 +129989,14 @@ module \dec30 sync always update \dec30_internal_op $0\dec30_internal_op[6:0] end - attribute \src "libresoc.v:80934.3-80970.6" - process $proc$libresoc.v:80934$3779 + attribute \src "libresoc.v:80730.3-80766.6" + process $proc$libresoc.v:80730$3779 assign { } { } assign { } { } assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:80935.5-80935.29" + attribute \src "libresoc.v:80731.5-80731.29" switch \initial - attribute \src "libresoc.v:80935.9-80935.17" + attribute \src "libresoc.v:80731.9-80731.17" case 1'1 case end @@ -130252,14 +130048,14 @@ module \dec30 sync always update \dec30_upd $0\dec30_upd[1:0] end - attribute \src "libresoc.v:80971.3-81007.6" - process $proc$libresoc.v:80971$3780 + attribute \src "libresoc.v:80767.3-80803.6" + process $proc$libresoc.v:80767$3780 assign { } { } assign { } { } assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:80972.5-80972.29" + attribute \src "libresoc.v:80768.5-80768.29" switch \initial - attribute \src "libresoc.v:80972.9-80972.17" + attribute \src "libresoc.v:80768.9-80768.17" case 1'1 case end @@ -130311,14 +130107,14 @@ module \dec30 sync always update \dec30_rc_sel $0\dec30_rc_sel[1:0] end - attribute \src "libresoc.v:81008.3-81044.6" - process $proc$libresoc.v:81008$3781 + attribute \src "libresoc.v:80804.3-80840.6" + process $proc$libresoc.v:80804$3781 assign { } { } assign { } { } assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:81009.5-81009.29" + attribute \src "libresoc.v:80805.5-80805.29" switch \initial - attribute \src "libresoc.v:81009.9-81009.17" + attribute \src "libresoc.v:80805.9-80805.17" case 1'1 case end @@ -130370,14 +130166,14 @@ module \dec30 sync always update \dec30_cry_in $0\dec30_cry_in[1:0] end - attribute \src "libresoc.v:81045.3-81081.6" - process $proc$libresoc.v:81045$3782 + attribute \src "libresoc.v:80841.3-80877.6" + process $proc$libresoc.v:80841$3782 assign { } { } assign { } { } assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:81046.5-81046.29" + attribute \src "libresoc.v:80842.5-80842.29" switch \initial - attribute \src "libresoc.v:81046.9-81046.17" + attribute \src "libresoc.v:80842.9-80842.17" case 1'1 case end @@ -130429,14 +130225,14 @@ module \dec30 sync always update \dec30_asmcode $0\dec30_asmcode[7:0] end - attribute \src "libresoc.v:81082.3-81118.6" - process $proc$libresoc.v:81082$3783 + attribute \src "libresoc.v:80878.3-80914.6" + process $proc$libresoc.v:80878$3783 assign { } { } assign { } { } assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:81083.5-81083.29" + attribute \src "libresoc.v:80879.5-80879.29" switch \initial - attribute \src "libresoc.v:81083.9-81083.17" + attribute \src "libresoc.v:80879.9-80879.17" case 1'1 case end @@ -130488,14 +130284,14 @@ module \dec30 sync always update \dec30_inv_a $0\dec30_inv_a[0:0] end - attribute \src "libresoc.v:81119.3-81155.6" - process $proc$libresoc.v:81119$3784 + attribute \src "libresoc.v:80915.3-80951.6" + process $proc$libresoc.v:80915$3784 assign { } { } assign { } { } assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:81120.5-81120.29" + attribute \src "libresoc.v:80916.5-80916.29" switch \initial - attribute \src "libresoc.v:81120.9-81120.17" + attribute \src "libresoc.v:80916.9-80916.17" case 1'1 case end @@ -130547,14 +130343,14 @@ module \dec30 sync always update \dec30_inv_out $0\dec30_inv_out[0:0] end - attribute \src "libresoc.v:81156.3-81192.6" - process $proc$libresoc.v:81156$3785 + attribute \src "libresoc.v:80952.3-80988.6" + process $proc$libresoc.v:80952$3785 assign { } { } assign { } { } assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:81157.5-81157.29" + attribute \src "libresoc.v:80953.5-80953.29" switch \initial - attribute \src "libresoc.v:81157.9-81157.17" + attribute \src "libresoc.v:80953.9-80953.17" case 1'1 case end @@ -130606,14 +130402,14 @@ module \dec30 sync always update \dec30_cry_out $0\dec30_cry_out[0:0] end - attribute \src "libresoc.v:81193.3-81229.6" - process $proc$libresoc.v:81193$3786 + attribute \src "libresoc.v:80989.3-81025.6" + process $proc$libresoc.v:80989$3786 assign { } { } assign { } { } assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:81194.5-81194.29" + attribute \src "libresoc.v:80990.5-80990.29" switch \initial - attribute \src "libresoc.v:81194.9-81194.17" + attribute \src "libresoc.v:80990.9-80990.17" case 1'1 case end @@ -130665,14 +130461,14 @@ module \dec30 sync always update \dec30_br $0\dec30_br[0:0] end - attribute \src "libresoc.v:81230.3-81266.6" - process $proc$libresoc.v:81230$3787 + attribute \src "libresoc.v:81026.3-81062.6" + process $proc$libresoc.v:81026$3787 assign { } { } assign { } { } assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:81231.5-81231.29" + attribute \src "libresoc.v:81027.5-81027.29" switch \initial - attribute \src "libresoc.v:81231.9-81231.17" + attribute \src "libresoc.v:81027.9-81027.17" case 1'1 case end @@ -130724,14 +130520,14 @@ module \dec30 sync always update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end - attribute \src "libresoc.v:81267.3-81303.6" - process $proc$libresoc.v:81267$3788 + attribute \src "libresoc.v:81063.3-81099.6" + process $proc$libresoc.v:81063$3788 assign { } { } assign { } { } assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:81268.5-81268.29" + attribute \src "libresoc.v:81064.5-81064.29" switch \initial - attribute \src "libresoc.v:81268.9-81268.17" + attribute \src "libresoc.v:81064.9-81064.17" case 1'1 case end @@ -130783,14 +130579,14 @@ module \dec30 sync always update \dec30_rsrv $0\dec30_rsrv[0:0] end - attribute \src "libresoc.v:81304.3-81340.6" - process $proc$libresoc.v:81304$3789 + attribute \src "libresoc.v:81100.3-81136.6" + process $proc$libresoc.v:81100$3789 assign { } { } assign { } { } assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:81305.5-81305.29" + attribute \src "libresoc.v:81101.5-81101.29" switch \initial - attribute \src "libresoc.v:81305.9-81305.17" + attribute \src "libresoc.v:81101.9-81101.17" case 1'1 case end @@ -130842,14 +130638,14 @@ module \dec30 sync always update \dec30_form $0\dec30_form[4:0] end - attribute \src "libresoc.v:81341.3-81377.6" - process $proc$libresoc.v:81341$3790 + attribute \src "libresoc.v:81137.3-81173.6" + process $proc$libresoc.v:81137$3790 assign { } { } assign { } { } assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:81342.5-81342.29" + attribute \src "libresoc.v:81138.5-81138.29" switch \initial - attribute \src "libresoc.v:81342.9-81342.17" + attribute \src "libresoc.v:81138.9-81138.17" case 1'1 case end @@ -130901,14 +130697,14 @@ module \dec30 sync always update \dec30_is_32b $0\dec30_is_32b[0:0] end - attribute \src "libresoc.v:81378.3-81414.6" - process $proc$libresoc.v:81378$3791 + attribute \src "libresoc.v:81174.3-81210.6" + process $proc$libresoc.v:81174$3791 assign { } { } assign { } { } assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:81379.5-81379.29" + attribute \src "libresoc.v:81175.5-81175.29" switch \initial - attribute \src "libresoc.v:81379.9-81379.17" + attribute \src "libresoc.v:81175.9-81175.17" case 1'1 case end @@ -130960,14 +130756,14 @@ module \dec30 sync always update \dec30_sgn $0\dec30_sgn[0:0] end - attribute \src "libresoc.v:81415.3-81451.6" - process $proc$libresoc.v:81415$3792 + attribute \src "libresoc.v:81211.3-81247.6" + process $proc$libresoc.v:81211$3792 assign { } { } assign { } { } assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:81416.5-81416.29" + attribute \src "libresoc.v:81212.5-81212.29" switch \initial - attribute \src "libresoc.v:81416.9-81416.17" + attribute \src "libresoc.v:81212.9-81212.17" case 1'1 case end @@ -131019,14 +130815,14 @@ module \dec30 sync always update \dec30_lk $0\dec30_lk[0:0] end - attribute \src "libresoc.v:81452.3-81488.6" - process $proc$libresoc.v:81452$3793 + attribute \src "libresoc.v:81248.3-81284.6" + process $proc$libresoc.v:81248$3793 assign { } { } assign { } { } assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81453.5-81453.29" + attribute \src "libresoc.v:81249.5-81249.29" switch \initial - attribute \src "libresoc.v:81453.9-81453.17" + attribute \src "libresoc.v:81249.9-81249.17" case 1'1 case end @@ -131078,14 +130874,14 @@ module \dec30 sync always update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] end - attribute \src "libresoc.v:81489.3-81525.6" - process $proc$libresoc.v:81489$3794 + attribute \src "libresoc.v:81285.3-81321.6" + process $proc$libresoc.v:81285$3794 assign { } { } assign { } { } assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81490.5-81490.29" + attribute \src "libresoc.v:81286.5-81286.29" switch \initial - attribute \src "libresoc.v:81490.9-81490.17" + attribute \src "libresoc.v:81286.9-81286.17" case 1'1 case end @@ -131137,14 +130933,14 @@ module \dec30 sync always update \dec30_SV_Etype $0\dec30_SV_Etype[1:0] end - attribute \src "libresoc.v:81526.3-81562.6" - process $proc$libresoc.v:81526$3795 + attribute \src "libresoc.v:81322.3-81358.6" + process $proc$libresoc.v:81322$3795 assign { } { } assign { } { } assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:81527.5-81527.29" + attribute \src "libresoc.v:81323.5-81323.29" switch \initial - attribute \src "libresoc.v:81527.9-81527.17" + attribute \src "libresoc.v:81323.9-81323.17" case 1'1 case end @@ -131196,14 +130992,14 @@ module \dec30 sync always update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0] end - attribute \src "libresoc.v:81563.3-81599.6" - process $proc$libresoc.v:81563$3796 + attribute \src "libresoc.v:81359.3-81395.6" + process $proc$libresoc.v:81359$3796 assign { } { } assign { } { } assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81564.5-81564.29" + attribute \src "libresoc.v:81360.5-81360.29" switch \initial - attribute \src "libresoc.v:81564.9-81564.17" + attribute \src "libresoc.v:81360.9-81360.17" case 1'1 case end @@ -131255,14 +131051,14 @@ module \dec30 sync always update \dec30_in1_sel $0\dec30_in1_sel[2:0] end - attribute \src "libresoc.v:81600.3-81636.6" - process $proc$libresoc.v:81600$3797 + attribute \src "libresoc.v:81396.3-81432.6" + process $proc$libresoc.v:81396$3797 assign { } { } assign { } { } assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81601.5-81601.29" + attribute \src "libresoc.v:81397.5-81397.29" switch \initial - attribute \src "libresoc.v:81601.9-81601.17" + attribute \src "libresoc.v:81397.9-81397.17" case 1'1 case end @@ -131314,14 +131110,14 @@ module \dec30 sync always update \dec30_in2_sel $0\dec30_in2_sel[3:0] end - attribute \src "libresoc.v:81637.3-81673.6" - process $proc$libresoc.v:81637$3798 + attribute \src "libresoc.v:81433.3-81469.6" + process $proc$libresoc.v:81433$3798 assign { } { } assign { } { } assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:81638.5-81638.29" + attribute \src "libresoc.v:81434.5-81434.29" switch \initial - attribute \src "libresoc.v:81638.9-81638.17" + attribute \src "libresoc.v:81434.9-81434.17" case 1'1 case end @@ -131373,14 +131169,14 @@ module \dec30 sync always update \dec30_in3_sel $0\dec30_in3_sel[1:0] end - attribute \src "libresoc.v:81674.3-81710.6" - process $proc$libresoc.v:81674$3799 + attribute \src "libresoc.v:81470.3-81506.6" + process $proc$libresoc.v:81470$3799 assign { } { } assign { } { } assign $0\dec30_out_sel[2:0] $1\dec30_out_sel[2:0] - attribute \src "libresoc.v:81675.5-81675.29" + attribute \src "libresoc.v:81471.5-81471.29" switch \initial - attribute \src "libresoc.v:81675.9-81675.17" + attribute \src "libresoc.v:81471.9-81471.17" case 1'1 case end @@ -131434,144 +131230,144 @@ module \dec30 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:81716.1-90364.10" +attribute \src "libresoc.v:81512.1-90160.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" attribute \generator "nMigen" module \dec31 - attribute \src "libresoc.v:88575.3-88635.6" + attribute \src "libresoc.v:88371.3-88431.6" wire width 2 $0\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88636.3-88696.6" + attribute \src "libresoc.v:88432.3-88492.6" wire width 2 $0\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:88514.3-88574.6" + attribute \src "libresoc.v:88310.3-88370.6" wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:89917.3-89977.6" + attribute \src "libresoc.v:89713.3-89773.6" wire $0\dec31_br[0:0] - attribute \src "libresoc.v:88941.3-89001.6" + attribute \src "libresoc.v:88737.3-88797.6" wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:89002.3-89062.6" + attribute \src "libresoc.v:88798.3-88858.6" wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:89673.3-89733.6" + attribute \src "libresoc.v:89469.3-89529.6" wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:89856.3-89916.6" + attribute \src "libresoc.v:89652.3-89712.6" wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:88453.3-88513.6" + attribute \src "libresoc.v:88249.3-88309.6" wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:88331.3-88391.6" + attribute \src "libresoc.v:88127.3-88187.6" wire width 14 $0\dec31_function_unit[13:0] - attribute \src "libresoc.v:88697.3-88757.6" + attribute \src "libresoc.v:88493.3-88553.6" wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88758.3-88818.6" + attribute \src "libresoc.v:88554.3-88614.6" wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88819.3-88879.6" + attribute \src "libresoc.v:88615.3-88675.6" wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:88392.3-88452.6" + attribute \src "libresoc.v:88188.3-88248.6" wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:89734.3-89794.6" + attribute \src "libresoc.v:89530.3-89590.6" wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:89795.3-89855.6" + attribute \src "libresoc.v:89591.3-89651.6" wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:90100.3-90160.6" + attribute \src "libresoc.v:89896.3-89956.6" wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:89490.3-89550.6" + attribute \src "libresoc.v:89286.3-89346.6" wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:90222.3-90282.6" + attribute \src "libresoc.v:90018.3-90078.6" wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:88880.3-88940.6" + attribute \src "libresoc.v:88676.3-88736.6" wire width 3 $0\dec31_out_sel[2:0] - attribute \src "libresoc.v:89612.3-89672.6" + attribute \src "libresoc.v:89408.3-89468.6" wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:90039.3-90099.6" + attribute \src "libresoc.v:89835.3-89895.6" wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:90283.3-90343.6" + attribute \src "libresoc.v:90079.3-90139.6" wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:90161.3-90221.6" + attribute \src "libresoc.v:89957.3-90017.6" wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:89978.3-90038.6" + attribute \src "libresoc.v:89774.3-89834.6" wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:89368.3-89428.6" + attribute \src "libresoc.v:89164.3-89224.6" wire width 3 $0\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:89429.3-89489.6" + attribute \src "libresoc.v:89225.3-89285.6" wire width 3 $0\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:89063.3-89123.6" + attribute \src "libresoc.v:88859.3-88919.6" wire width 3 $0\dec31_sv_in1[2:0] - attribute \src "libresoc.v:89124.3-89184.6" + attribute \src "libresoc.v:88920.3-88980.6" wire width 3 $0\dec31_sv_in2[2:0] - attribute \src "libresoc.v:89185.3-89245.6" + attribute \src "libresoc.v:88981.3-89041.6" wire width 3 $0\dec31_sv_in3[2:0] - attribute \src "libresoc.v:89307.3-89367.6" + attribute \src "libresoc.v:89103.3-89163.6" wire width 3 $0\dec31_sv_out2[2:0] - attribute \src "libresoc.v:89246.3-89306.6" + attribute \src "libresoc.v:89042.3-89102.6" wire width 3 $0\dec31_sv_out[2:0] - attribute \src "libresoc.v:89551.3-89611.6" + attribute \src "libresoc.v:89347.3-89407.6" wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:81717.7-81717.20" + attribute \src "libresoc.v:81513.7-81513.20" wire $0\initial[0:0] - attribute \src "libresoc.v:88575.3-88635.6" + attribute \src "libresoc.v:88371.3-88431.6" wire width 2 $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88636.3-88696.6" + attribute \src "libresoc.v:88432.3-88492.6" wire width 2 $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:88514.3-88574.6" + attribute \src "libresoc.v:88310.3-88370.6" wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:89917.3-89977.6" + attribute \src "libresoc.v:89713.3-89773.6" wire $1\dec31_br[0:0] - attribute \src "libresoc.v:88941.3-89001.6" + attribute \src "libresoc.v:88737.3-88797.6" wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:89002.3-89062.6" + attribute \src "libresoc.v:88798.3-88858.6" wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:89673.3-89733.6" + attribute \src "libresoc.v:89469.3-89529.6" wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:89856.3-89916.6" + attribute \src "libresoc.v:89652.3-89712.6" wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:88453.3-88513.6" + attribute \src "libresoc.v:88249.3-88309.6" wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:88331.3-88391.6" + attribute \src "libresoc.v:88127.3-88187.6" wire width 14 $1\dec31_function_unit[13:0] - attribute \src "libresoc.v:88697.3-88757.6" + attribute \src "libresoc.v:88493.3-88553.6" wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88758.3-88818.6" + attribute \src "libresoc.v:88554.3-88614.6" wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88819.3-88879.6" + attribute \src "libresoc.v:88615.3-88675.6" wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:88392.3-88452.6" + attribute \src "libresoc.v:88188.3-88248.6" wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:89734.3-89794.6" + attribute \src "libresoc.v:89530.3-89590.6" wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:89795.3-89855.6" + attribute \src "libresoc.v:89591.3-89651.6" wire $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:90100.3-90160.6" + attribute \src "libresoc.v:89896.3-89956.6" wire $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:89490.3-89550.6" + attribute \src "libresoc.v:89286.3-89346.6" wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:90222.3-90282.6" + attribute \src "libresoc.v:90018.3-90078.6" wire $1\dec31_lk[0:0] - attribute \src "libresoc.v:88880.3-88940.6" + attribute \src "libresoc.v:88676.3-88736.6" wire width 3 $1\dec31_out_sel[2:0] - attribute \src "libresoc.v:89612.3-89672.6" + attribute \src "libresoc.v:89408.3-89468.6" wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:90039.3-90099.6" + attribute \src "libresoc.v:89835.3-89895.6" wire $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:90283.3-90343.6" + attribute \src "libresoc.v:90079.3-90139.6" wire $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:90161.3-90221.6" + attribute \src "libresoc.v:89957.3-90017.6" wire $1\dec31_sgn[0:0] - attribute \src "libresoc.v:89978.3-90038.6" + attribute \src "libresoc.v:89774.3-89834.6" wire $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:89368.3-89428.6" + attribute \src "libresoc.v:89164.3-89224.6" wire width 3 $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:89429.3-89489.6" + attribute \src "libresoc.v:89225.3-89285.6" wire width 3 $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:89063.3-89123.6" + attribute \src "libresoc.v:88859.3-88919.6" wire width 3 $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:89124.3-89184.6" + attribute \src "libresoc.v:88920.3-88980.6" wire width 3 $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:89185.3-89245.6" + attribute \src "libresoc.v:88981.3-89041.6" wire width 3 $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:89307.3-89367.6" + attribute \src "libresoc.v:89103.3-89163.6" wire width 3 $1\dec31_sv_out2[2:0] - attribute \src "libresoc.v:89246.3-89306.6" + attribute \src "libresoc.v:89042.3-89102.6" wire width 3 $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:89551.3-89611.6" + attribute \src "libresoc.v:89347.3-89407.6" wire width 2 $1\dec31_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -137499,7 +137295,7 @@ module \dec31 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_upd - attribute \src "libresoc.v:81717.7-81717.15" + attribute \src "libresoc.v:81513.7-81513.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in @@ -137508,7 +137304,7 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:87683.18-87718.4" + attribute \src "libresoc.v:87479.18-87514.4" cell \dec31_dec_sub0 \dec31_dec_sub0 connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype @@ -137546,7 +137342,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87719.19-87754.4" + attribute \src "libresoc.v:87515.19-87550.4" cell \dec31_dec_sub10 \dec31_dec_sub10 connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype @@ -137584,7 +137380,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87755.19-87790.4" + attribute \src "libresoc.v:87551.19-87586.4" cell \dec31_dec_sub11 \dec31_dec_sub11 connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype @@ -137622,7 +137418,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87791.19-87826.4" + attribute \src "libresoc.v:87587.19-87622.4" cell \dec31_dec_sub15 \dec31_dec_sub15 connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype @@ -137660,7 +137456,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87827.19-87862.4" + attribute \src "libresoc.v:87623.19-87658.4" cell \dec31_dec_sub16 \dec31_dec_sub16 connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype @@ -137698,7 +137494,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87863.19-87898.4" + attribute \src "libresoc.v:87659.19-87694.4" cell \dec31_dec_sub18 \dec31_dec_sub18 connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype @@ -137736,7 +137532,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub18_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87899.19-87934.4" + attribute \src "libresoc.v:87695.19-87730.4" cell \dec31_dec_sub19 \dec31_dec_sub19 connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype @@ -137774,7 +137570,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87935.19-87970.4" + attribute \src "libresoc.v:87731.19-87766.4" cell \dec31_dec_sub20 \dec31_dec_sub20 connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype @@ -137812,7 +137608,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87971.19-88006.4" + attribute \src "libresoc.v:87767.19-87802.4" cell \dec31_dec_sub21 \dec31_dec_sub21 connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype @@ -137850,7 +137646,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88007.19-88042.4" + attribute \src "libresoc.v:87803.19-87838.4" cell \dec31_dec_sub22 \dec31_dec_sub22 connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype @@ -137888,7 +137684,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88043.19-88078.4" + attribute \src "libresoc.v:87839.19-87874.4" cell \dec31_dec_sub23 \dec31_dec_sub23 connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype @@ -137926,7 +137722,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub23_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88079.19-88114.4" + attribute \src "libresoc.v:87875.19-87910.4" cell \dec31_dec_sub24 \dec31_dec_sub24 connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype @@ -137964,7 +137760,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88115.19-88150.4" + attribute \src "libresoc.v:87911.19-87946.4" cell \dec31_dec_sub26 \dec31_dec_sub26 connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype @@ -138002,7 +137798,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88151.19-88186.4" + attribute \src "libresoc.v:87947.19-87982.4" cell \dec31_dec_sub27 \dec31_dec_sub27 connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype @@ -138040,7 +137836,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub27_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88187.19-88222.4" + attribute \src "libresoc.v:87983.19-88018.4" cell \dec31_dec_sub28 \dec31_dec_sub28 connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype @@ -138078,7 +137874,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub28_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88223.18-88258.4" + attribute \src "libresoc.v:88019.18-88054.4" cell \dec31_dec_sub4 \dec31_dec_sub4 connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype @@ -138116,7 +137912,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub4_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88259.18-88294.4" + attribute \src "libresoc.v:88055.18-88090.4" cell \dec31_dec_sub8 \dec31_dec_sub8 connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype @@ -138154,7 +137950,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub8_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88295.18-88330.4" + attribute \src "libresoc.v:88091.18-88126.4" cell \dec31_dec_sub9 \dec31_dec_sub9 connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype @@ -138191,22 +137987,22 @@ module \dec31 connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd connect \opcode_in \dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:81717.7-81717.20" - process $proc$libresoc.v:81717$3834 + attribute \src "libresoc.v:81513.7-81513.20" + process $proc$libresoc.v:81513$3834 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:88331.3-88391.6" - process $proc$libresoc.v:88331$3801 + attribute \src "libresoc.v:88127.3-88187.6" + process $proc$libresoc.v:88127$3801 assign { } { } assign { } { } assign $0\dec31_function_unit[13:0] $1\dec31_function_unit[13:0] - attribute \src "libresoc.v:88332.5-88332.29" + attribute \src "libresoc.v:88128.5-88128.29" switch \initial - attribute \src "libresoc.v:88332.9-88332.17" + attribute \src "libresoc.v:88128.9-88128.17" case 1'1 case end @@ -138290,14 +138086,14 @@ module \dec31 sync always update \dec31_function_unit $0\dec31_function_unit[13:0] end - attribute \src "libresoc.v:88392.3-88452.6" - process $proc$libresoc.v:88392$3802 + attribute \src "libresoc.v:88188.3-88248.6" + process $proc$libresoc.v:88188$3802 assign { } { } assign { } { } assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:88393.5-88393.29" + attribute \src "libresoc.v:88189.5-88189.29" switch \initial - attribute \src "libresoc.v:88393.9-88393.17" + attribute \src "libresoc.v:88189.9-88189.17" case 1'1 case end @@ -138381,14 +138177,14 @@ module \dec31 sync always update \dec31_internal_op $0\dec31_internal_op[6:0] end - attribute \src "libresoc.v:88453.3-88513.6" - process $proc$libresoc.v:88453$3803 + attribute \src "libresoc.v:88249.3-88309.6" + process $proc$libresoc.v:88249$3803 assign { } { } assign { } { } assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:88454.5-88454.29" + attribute \src "libresoc.v:88250.5-88250.29" switch \initial - attribute \src "libresoc.v:88454.9-88454.17" + attribute \src "libresoc.v:88250.9-88250.17" case 1'1 case end @@ -138472,14 +138268,14 @@ module \dec31 sync always update \dec31_form $0\dec31_form[4:0] end - attribute \src "libresoc.v:88514.3-88574.6" - process $proc$libresoc.v:88514$3804 + attribute \src "libresoc.v:88310.3-88370.6" + process $proc$libresoc.v:88310$3804 assign { } { } assign { } { } assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:88515.5-88515.29" + attribute \src "libresoc.v:88311.5-88311.29" switch \initial - attribute \src "libresoc.v:88515.9-88515.17" + attribute \src "libresoc.v:88311.9-88311.17" case 1'1 case end @@ -138563,14 +138359,14 @@ module \dec31 sync always update \dec31_asmcode $0\dec31_asmcode[7:0] end - attribute \src "libresoc.v:88575.3-88635.6" - process $proc$libresoc.v:88575$3805 + attribute \src "libresoc.v:88371.3-88431.6" + process $proc$libresoc.v:88371$3805 assign { } { } assign { } { } assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88576.5-88576.29" + attribute \src "libresoc.v:88372.5-88372.29" switch \initial - attribute \src "libresoc.v:88576.9-88576.17" + attribute \src "libresoc.v:88372.9-88372.17" case 1'1 case end @@ -138654,14 +138450,14 @@ module \dec31 sync always update \dec31_SV_Etype $0\dec31_SV_Etype[1:0] end - attribute \src "libresoc.v:88636.3-88696.6" - process $proc$libresoc.v:88636$3806 + attribute \src "libresoc.v:88432.3-88492.6" + process $proc$libresoc.v:88432$3806 assign { } { } assign { } { } assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:88637.5-88637.29" + attribute \src "libresoc.v:88433.5-88433.29" switch \initial - attribute \src "libresoc.v:88637.9-88637.17" + attribute \src "libresoc.v:88433.9-88433.17" case 1'1 case end @@ -138745,14 +138541,14 @@ module \dec31 sync always update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0] end - attribute \src "libresoc.v:88697.3-88757.6" - process $proc$libresoc.v:88697$3807 + attribute \src "libresoc.v:88493.3-88553.6" + process $proc$libresoc.v:88493$3807 assign { } { } assign { } { } assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88698.5-88698.29" + attribute \src "libresoc.v:88494.5-88494.29" switch \initial - attribute \src "libresoc.v:88698.9-88698.17" + attribute \src "libresoc.v:88494.9-88494.17" case 1'1 case end @@ -138836,14 +138632,14 @@ module \dec31 sync always update \dec31_in1_sel $0\dec31_in1_sel[2:0] end - attribute \src "libresoc.v:88758.3-88818.6" - process $proc$libresoc.v:88758$3808 + attribute \src "libresoc.v:88554.3-88614.6" + process $proc$libresoc.v:88554$3808 assign { } { } assign { } { } assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88759.5-88759.29" + attribute \src "libresoc.v:88555.5-88555.29" switch \initial - attribute \src "libresoc.v:88759.9-88759.17" + attribute \src "libresoc.v:88555.9-88555.17" case 1'1 case end @@ -138927,14 +138723,14 @@ module \dec31 sync always update \dec31_in2_sel $0\dec31_in2_sel[3:0] end - attribute \src "libresoc.v:88819.3-88879.6" - process $proc$libresoc.v:88819$3809 + attribute \src "libresoc.v:88615.3-88675.6" + process $proc$libresoc.v:88615$3809 assign { } { } assign { } { } assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:88820.5-88820.29" + attribute \src "libresoc.v:88616.5-88616.29" switch \initial - attribute \src "libresoc.v:88820.9-88820.17" + attribute \src "libresoc.v:88616.9-88616.17" case 1'1 case end @@ -139018,14 +138814,14 @@ module \dec31 sync always update \dec31_in3_sel $0\dec31_in3_sel[1:0] end - attribute \src "libresoc.v:88880.3-88940.6" - process $proc$libresoc.v:88880$3810 + attribute \src "libresoc.v:88676.3-88736.6" + process $proc$libresoc.v:88676$3810 assign { } { } assign { } { } assign $0\dec31_out_sel[2:0] $1\dec31_out_sel[2:0] - attribute \src "libresoc.v:88881.5-88881.29" + attribute \src "libresoc.v:88677.5-88677.29" switch \initial - attribute \src "libresoc.v:88881.9-88881.17" + attribute \src "libresoc.v:88677.9-88677.17" case 1'1 case end @@ -139109,14 +138905,14 @@ module \dec31 sync always update \dec31_out_sel $0\dec31_out_sel[2:0] end - attribute \src "libresoc.v:88941.3-89001.6" - process $proc$libresoc.v:88941$3811 + attribute \src "libresoc.v:88737.3-88797.6" + process $proc$libresoc.v:88737$3811 assign { } { } assign { } { } assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:88942.5-88942.29" + attribute \src "libresoc.v:88738.5-88738.29" switch \initial - attribute \src "libresoc.v:88942.9-88942.17" + attribute \src "libresoc.v:88738.9-88738.17" case 1'1 case end @@ -139200,14 +138996,14 @@ module \dec31 sync always update \dec31_cr_in $0\dec31_cr_in[2:0] end - attribute \src "libresoc.v:89002.3-89062.6" - process $proc$libresoc.v:89002$3812 + attribute \src "libresoc.v:88798.3-88858.6" + process $proc$libresoc.v:88798$3812 assign { } { } assign { } { } assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:89003.5-89003.29" + attribute \src "libresoc.v:88799.5-88799.29" switch \initial - attribute \src "libresoc.v:89003.9-89003.17" + attribute \src "libresoc.v:88799.9-88799.17" case 1'1 case end @@ -139291,14 +139087,14 @@ module \dec31 sync always update \dec31_cr_out $0\dec31_cr_out[2:0] end - attribute \src "libresoc.v:89063.3-89123.6" - process $proc$libresoc.v:89063$3813 + attribute \src "libresoc.v:88859.3-88919.6" + process $proc$libresoc.v:88859$3813 assign { } { } assign { } { } assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:89064.5-89064.29" + attribute \src "libresoc.v:88860.5-88860.29" switch \initial - attribute \src "libresoc.v:89064.9-89064.17" + attribute \src "libresoc.v:88860.9-88860.17" case 1'1 case end @@ -139382,14 +139178,14 @@ module \dec31 sync always update \dec31_sv_in1 $0\dec31_sv_in1[2:0] end - attribute \src "libresoc.v:89124.3-89184.6" - process $proc$libresoc.v:89124$3814 + attribute \src "libresoc.v:88920.3-88980.6" + process $proc$libresoc.v:88920$3814 assign { } { } assign { } { } assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:89125.5-89125.29" + attribute \src "libresoc.v:88921.5-88921.29" switch \initial - attribute \src "libresoc.v:89125.9-89125.17" + attribute \src "libresoc.v:88921.9-88921.17" case 1'1 case end @@ -139473,14 +139269,14 @@ module \dec31 sync always update \dec31_sv_in2 $0\dec31_sv_in2[2:0] end - attribute \src "libresoc.v:89185.3-89245.6" - process $proc$libresoc.v:89185$3815 + attribute \src "libresoc.v:88981.3-89041.6" + process $proc$libresoc.v:88981$3815 assign { } { } assign { } { } assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:89186.5-89186.29" + attribute \src "libresoc.v:88982.5-88982.29" switch \initial - attribute \src "libresoc.v:89186.9-89186.17" + attribute \src "libresoc.v:88982.9-88982.17" case 1'1 case end @@ -139564,14 +139360,14 @@ module \dec31 sync always update \dec31_sv_in3 $0\dec31_sv_in3[2:0] end - attribute \src "libresoc.v:89246.3-89306.6" - process $proc$libresoc.v:89246$3816 + attribute \src "libresoc.v:89042.3-89102.6" + process $proc$libresoc.v:89042$3816 assign { } { } assign { } { } assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:89247.5-89247.29" + attribute \src "libresoc.v:89043.5-89043.29" switch \initial - attribute \src "libresoc.v:89247.9-89247.17" + attribute \src "libresoc.v:89043.9-89043.17" case 1'1 case end @@ -139655,14 +139451,14 @@ module \dec31 sync always update \dec31_sv_out $0\dec31_sv_out[2:0] end - attribute \src "libresoc.v:89307.3-89367.6" - process $proc$libresoc.v:89307$3817 + attribute \src "libresoc.v:89103.3-89163.6" + process $proc$libresoc.v:89103$3817 assign { } { } assign { } { } assign $0\dec31_sv_out2[2:0] $1\dec31_sv_out2[2:0] - attribute \src "libresoc.v:89308.5-89308.29" + attribute \src "libresoc.v:89104.5-89104.29" switch \initial - attribute \src "libresoc.v:89308.9-89308.17" + attribute \src "libresoc.v:89104.9-89104.17" case 1'1 case end @@ -139746,14 +139542,14 @@ module \dec31 sync always update \dec31_sv_out2 $0\dec31_sv_out2[2:0] end - attribute \src "libresoc.v:89368.3-89428.6" - process $proc$libresoc.v:89368$3818 + attribute \src "libresoc.v:89164.3-89224.6" + process $proc$libresoc.v:89164$3818 assign { } { } assign { } { } assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:89369.5-89369.29" + attribute \src "libresoc.v:89165.5-89165.29" switch \initial - attribute \src "libresoc.v:89369.9-89369.17" + attribute \src "libresoc.v:89165.9-89165.17" case 1'1 case end @@ -139837,14 +139633,14 @@ module \dec31 sync always update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0] end - attribute \src "libresoc.v:89429.3-89489.6" - process $proc$libresoc.v:89429$3819 + attribute \src "libresoc.v:89225.3-89285.6" + process $proc$libresoc.v:89225$3819 assign { } { } assign { } { } assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:89430.5-89430.29" + attribute \src "libresoc.v:89226.5-89226.29" switch \initial - attribute \src "libresoc.v:89430.9-89430.17" + attribute \src "libresoc.v:89226.9-89226.17" case 1'1 case end @@ -139928,14 +139724,14 @@ module \dec31 sync always update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0] end - attribute \src "libresoc.v:89490.3-89550.6" - process $proc$libresoc.v:89490$3820 + attribute \src "libresoc.v:89286.3-89346.6" + process $proc$libresoc.v:89286$3820 assign { } { } assign { } { } assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:89491.5-89491.29" + attribute \src "libresoc.v:89287.5-89287.29" switch \initial - attribute \src "libresoc.v:89491.9-89491.17" + attribute \src "libresoc.v:89287.9-89287.17" case 1'1 case end @@ -140019,14 +139815,14 @@ module \dec31 sync always update \dec31_ldst_len $0\dec31_ldst_len[3:0] end - attribute \src "libresoc.v:89551.3-89611.6" - process $proc$libresoc.v:89551$3821 + attribute \src "libresoc.v:89347.3-89407.6" + process $proc$libresoc.v:89347$3821 assign { } { } assign { } { } assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:89552.5-89552.29" + attribute \src "libresoc.v:89348.5-89348.29" switch \initial - attribute \src "libresoc.v:89552.9-89552.17" + attribute \src "libresoc.v:89348.9-89348.17" case 1'1 case end @@ -140110,14 +139906,14 @@ module \dec31 sync always update \dec31_upd $0\dec31_upd[1:0] end - attribute \src "libresoc.v:89612.3-89672.6" - process $proc$libresoc.v:89612$3822 + attribute \src "libresoc.v:89408.3-89468.6" + process $proc$libresoc.v:89408$3822 assign { } { } assign { } { } assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:89613.5-89613.29" + attribute \src "libresoc.v:89409.5-89409.29" switch \initial - attribute \src "libresoc.v:89613.9-89613.17" + attribute \src "libresoc.v:89409.9-89409.17" case 1'1 case end @@ -140201,14 +139997,14 @@ module \dec31 sync always update \dec31_rc_sel $0\dec31_rc_sel[1:0] end - attribute \src "libresoc.v:89673.3-89733.6" - process $proc$libresoc.v:89673$3823 + attribute \src "libresoc.v:89469.3-89529.6" + process $proc$libresoc.v:89469$3823 assign { } { } assign { } { } assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:89674.5-89674.29" + attribute \src "libresoc.v:89470.5-89470.29" switch \initial - attribute \src "libresoc.v:89674.9-89674.17" + attribute \src "libresoc.v:89470.9-89470.17" case 1'1 case end @@ -140292,14 +140088,14 @@ module \dec31 sync always update \dec31_cry_in $0\dec31_cry_in[1:0] end - attribute \src "libresoc.v:89734.3-89794.6" - process $proc$libresoc.v:89734$3824 + attribute \src "libresoc.v:89530.3-89590.6" + process $proc$libresoc.v:89530$3824 assign { } { } assign { } { } assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:89735.5-89735.29" + attribute \src "libresoc.v:89531.5-89531.29" switch \initial - attribute \src "libresoc.v:89735.9-89735.17" + attribute \src "libresoc.v:89531.9-89531.17" case 1'1 case end @@ -140383,14 +140179,14 @@ module \dec31 sync always update \dec31_inv_a $0\dec31_inv_a[0:0] end - attribute \src "libresoc.v:89795.3-89855.6" - process $proc$libresoc.v:89795$3825 + attribute \src "libresoc.v:89591.3-89651.6" + process $proc$libresoc.v:89591$3825 assign { } { } assign { } { } assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:89796.5-89796.29" + attribute \src "libresoc.v:89592.5-89592.29" switch \initial - attribute \src "libresoc.v:89796.9-89796.17" + attribute \src "libresoc.v:89592.9-89592.17" case 1'1 case end @@ -140474,14 +140270,14 @@ module \dec31 sync always update \dec31_inv_out $0\dec31_inv_out[0:0] end - attribute \src "libresoc.v:89856.3-89916.6" - process $proc$libresoc.v:89856$3826 + attribute \src "libresoc.v:89652.3-89712.6" + process $proc$libresoc.v:89652$3826 assign { } { } assign { } { } assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:89857.5-89857.29" + attribute \src "libresoc.v:89653.5-89653.29" switch \initial - attribute \src "libresoc.v:89857.9-89857.17" + attribute \src "libresoc.v:89653.9-89653.17" case 1'1 case end @@ -140565,14 +140361,14 @@ module \dec31 sync always update \dec31_cry_out $0\dec31_cry_out[0:0] end - attribute \src "libresoc.v:89917.3-89977.6" - process $proc$libresoc.v:89917$3827 + attribute \src "libresoc.v:89713.3-89773.6" + process $proc$libresoc.v:89713$3827 assign { } { } assign { } { } assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:89918.5-89918.29" + attribute \src "libresoc.v:89714.5-89714.29" switch \initial - attribute \src "libresoc.v:89918.9-89918.17" + attribute \src "libresoc.v:89714.9-89714.17" case 1'1 case end @@ -140656,14 +140452,14 @@ module \dec31 sync always update \dec31_br $0\dec31_br[0:0] end - attribute \src "libresoc.v:89978.3-90038.6" - process $proc$libresoc.v:89978$3828 + attribute \src "libresoc.v:89774.3-89834.6" + process $proc$libresoc.v:89774$3828 assign { } { } assign { } { } assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:89979.5-89979.29" + attribute \src "libresoc.v:89775.5-89775.29" switch \initial - attribute \src "libresoc.v:89979.9-89979.17" + attribute \src "libresoc.v:89775.9-89775.17" case 1'1 case end @@ -140747,14 +140543,14 @@ module \dec31 sync always update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end - attribute \src "libresoc.v:90039.3-90099.6" - process $proc$libresoc.v:90039$3829 + attribute \src "libresoc.v:89835.3-89895.6" + process $proc$libresoc.v:89835$3829 assign { } { } assign { } { } assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:90040.5-90040.29" + attribute \src "libresoc.v:89836.5-89836.29" switch \initial - attribute \src "libresoc.v:90040.9-90040.17" + attribute \src "libresoc.v:89836.9-89836.17" case 1'1 case end @@ -140838,14 +140634,14 @@ module \dec31 sync always update \dec31_rsrv $0\dec31_rsrv[0:0] end - attribute \src "libresoc.v:90100.3-90160.6" - process $proc$libresoc.v:90100$3830 + attribute \src "libresoc.v:89896.3-89956.6" + process $proc$libresoc.v:89896$3830 assign { } { } assign { } { } assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:90101.5-90101.29" + attribute \src "libresoc.v:89897.5-89897.29" switch \initial - attribute \src "libresoc.v:90101.9-90101.17" + attribute \src "libresoc.v:89897.9-89897.17" case 1'1 case end @@ -140929,14 +140725,14 @@ module \dec31 sync always update \dec31_is_32b $0\dec31_is_32b[0:0] end - attribute \src "libresoc.v:90161.3-90221.6" - process $proc$libresoc.v:90161$3831 + attribute \src "libresoc.v:89957.3-90017.6" + process $proc$libresoc.v:89957$3831 assign { } { } assign { } { } assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:90162.5-90162.29" + attribute \src "libresoc.v:89958.5-89958.29" switch \initial - attribute \src "libresoc.v:90162.9-90162.17" + attribute \src "libresoc.v:89958.9-89958.17" case 1'1 case end @@ -141020,14 +140816,14 @@ module \dec31 sync always update \dec31_sgn $0\dec31_sgn[0:0] end - attribute \src "libresoc.v:90222.3-90282.6" - process $proc$libresoc.v:90222$3832 + attribute \src "libresoc.v:90018.3-90078.6" + process $proc$libresoc.v:90018$3832 assign { } { } assign { } { } assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:90223.5-90223.29" + attribute \src "libresoc.v:90019.5-90019.29" switch \initial - attribute \src "libresoc.v:90223.9-90223.17" + attribute \src "libresoc.v:90019.9-90019.17" case 1'1 case end @@ -141111,14 +140907,14 @@ module \dec31 sync always update \dec31_lk $0\dec31_lk[0:0] end - attribute \src "libresoc.v:90283.3-90343.6" - process $proc$libresoc.v:90283$3833 + attribute \src "libresoc.v:90079.3-90139.6" + process $proc$libresoc.v:90079$3833 assign { } { } assign { } { } assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:90284.5-90284.29" + attribute \src "libresoc.v:90080.5-90080.29" switch \initial - attribute \src "libresoc.v:90284.9-90284.17" + attribute \src "libresoc.v:90080.9-90080.17" case 1'1 case end @@ -141223,144 +141019,144 @@ module \dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:90368.1-91345.10" +attribute \src "libresoc.v:90164.1-91141.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" attribute \generator "nMigen" module \dec31_dec_sub0 - attribute \src "libresoc.v:91230.3-91248.6" + attribute \src "libresoc.v:91026.3-91044.6" wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:91249.3-91267.6" + attribute \src "libresoc.v:91045.3-91063.6" wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:91002.3-91020.6" + attribute \src "libresoc.v:90798.3-90816.6" wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:91078.3-91096.6" + attribute \src "libresoc.v:90874.3-90892.6" wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90736.3-90754.6" + attribute \src "libresoc.v:90532.3-90550.6" wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90755.3-90773.6" + attribute \src "libresoc.v:90551.3-90569.6" wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:90983.3-91001.6" + attribute \src "libresoc.v:90779.3-90797.6" wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:91059.3-91077.6" + attribute \src "libresoc.v:90855.3-90873.6" wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:91135.3-91153.6" + attribute \src "libresoc.v:90931.3-90949.6" wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90717.3-90735.6" + attribute \src "libresoc.v:90513.3-90531.6" wire width 14 $0\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:91268.3-91286.6" + attribute \src "libresoc.v:91064.3-91082.6" wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:91287.3-91305.6" + attribute \src "libresoc.v:91083.3-91101.6" wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:91306.3-91324.6" + attribute \src "libresoc.v:91102.3-91120.6" wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:90926.3-90944.6" + attribute \src "libresoc.v:90722.3-90740.6" wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:91021.3-91039.6" + attribute \src "libresoc.v:90817.3-90835.6" wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:91040.3-91058.6" + attribute \src "libresoc.v:90836.3-90854.6" wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:91154.3-91172.6" + attribute \src "libresoc.v:90950.3-90968.6" wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:90907.3-90925.6" + attribute \src "libresoc.v:90703.3-90721.6" wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:91192.3-91210.6" + attribute \src "libresoc.v:90988.3-91006.6" wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:91325.3-91343.6" + attribute \src "libresoc.v:91121.3-91139.6" wire width 3 $0\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:90964.3-90982.6" + attribute \src "libresoc.v:90760.3-90778.6" wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:91116.3-91134.6" + attribute \src "libresoc.v:90912.3-90930.6" wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:91211.3-91229.6" + attribute \src "libresoc.v:91007.3-91025.6" wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:91173.3-91191.6" + attribute \src "libresoc.v:90969.3-90987.6" wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:91097.3-91115.6" + attribute \src "libresoc.v:90893.3-90911.6" wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90869.3-90887.6" + attribute \src "libresoc.v:90665.3-90683.6" wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90888.3-90906.6" + attribute \src "libresoc.v:90684.3-90702.6" wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90774.3-90792.6" + attribute \src "libresoc.v:90570.3-90588.6" wire width 3 $0\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90793.3-90811.6" + attribute \src "libresoc.v:90589.3-90607.6" wire width 3 $0\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90812.3-90830.6" + attribute \src "libresoc.v:90608.3-90626.6" wire width 3 $0\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90850.3-90868.6" + attribute \src "libresoc.v:90646.3-90664.6" wire width 3 $0\dec31_dec_sub0_sv_out2[2:0] - attribute \src "libresoc.v:90831.3-90849.6" + attribute \src "libresoc.v:90627.3-90645.6" wire width 3 $0\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:90945.3-90963.6" + attribute \src "libresoc.v:90741.3-90759.6" wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:90369.7-90369.20" + attribute \src "libresoc.v:90165.7-90165.20" wire $0\initial[0:0] - attribute \src "libresoc.v:91230.3-91248.6" + attribute \src "libresoc.v:91026.3-91044.6" wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:91249.3-91267.6" + attribute \src "libresoc.v:91045.3-91063.6" wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:91002.3-91020.6" + attribute \src "libresoc.v:90798.3-90816.6" wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:91078.3-91096.6" + attribute \src "libresoc.v:90874.3-90892.6" wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90736.3-90754.6" + attribute \src "libresoc.v:90532.3-90550.6" wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90755.3-90773.6" + attribute \src "libresoc.v:90551.3-90569.6" wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:90983.3-91001.6" + attribute \src "libresoc.v:90779.3-90797.6" wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:91059.3-91077.6" + attribute \src "libresoc.v:90855.3-90873.6" wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:91135.3-91153.6" + attribute \src "libresoc.v:90931.3-90949.6" wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90717.3-90735.6" + attribute \src "libresoc.v:90513.3-90531.6" wire width 14 $1\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:91268.3-91286.6" + attribute \src "libresoc.v:91064.3-91082.6" wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:91287.3-91305.6" + attribute \src "libresoc.v:91083.3-91101.6" wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:91306.3-91324.6" + attribute \src "libresoc.v:91102.3-91120.6" wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:90926.3-90944.6" + attribute \src "libresoc.v:90722.3-90740.6" wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:91021.3-91039.6" + attribute \src "libresoc.v:90817.3-90835.6" wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:91040.3-91058.6" + attribute \src "libresoc.v:90836.3-90854.6" wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:91154.3-91172.6" + attribute \src "libresoc.v:90950.3-90968.6" wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:90907.3-90925.6" + attribute \src "libresoc.v:90703.3-90721.6" wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:91192.3-91210.6" + attribute \src "libresoc.v:90988.3-91006.6" wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:91325.3-91343.6" + attribute \src "libresoc.v:91121.3-91139.6" wire width 3 $1\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:90964.3-90982.6" + attribute \src "libresoc.v:90760.3-90778.6" wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:91116.3-91134.6" + attribute \src "libresoc.v:90912.3-90930.6" wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:91211.3-91229.6" + attribute \src "libresoc.v:91007.3-91025.6" wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:91173.3-91191.6" + attribute \src "libresoc.v:90969.3-90987.6" wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:91097.3-91115.6" + attribute \src "libresoc.v:90893.3-90911.6" wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90869.3-90887.6" + attribute \src "libresoc.v:90665.3-90683.6" wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90888.3-90906.6" + attribute \src "libresoc.v:90684.3-90702.6" wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90774.3-90792.6" + attribute \src "libresoc.v:90570.3-90588.6" wire width 3 $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90793.3-90811.6" + attribute \src "libresoc.v:90589.3-90607.6" wire width 3 $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90812.3-90830.6" + attribute \src "libresoc.v:90608.3-90626.6" wire width 3 $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90850.3-90868.6" + attribute \src "libresoc.v:90646.3-90664.6" wire width 3 $1\dec31_dec_sub0_sv_out2[2:0] - attribute \src "libresoc.v:90831.3-90849.6" + attribute \src "libresoc.v:90627.3-90645.6" wire width 3 $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:90945.3-90963.6" + attribute \src "libresoc.v:90741.3-90759.6" wire width 2 $1\dec31_dec_sub0_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -141672,28 +141468,28 @@ module \dec31_dec_sub0 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub0_upd - attribute \src "libresoc.v:90369.7-90369.15" + attribute \src "libresoc.v:90165.7-90165.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:90369.7-90369.20" - process $proc$libresoc.v:90369$3868 + attribute \src "libresoc.v:90165.7-90165.20" + process $proc$libresoc.v:90165$3868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:90717.3-90735.6" - process $proc$libresoc.v:90717$3835 + attribute \src "libresoc.v:90513.3-90531.6" + process $proc$libresoc.v:90513$3835 assign { } { } assign { } { } assign $0\dec31_dec_sub0_function_unit[13:0] $1\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:90718.5-90718.29" + attribute \src "libresoc.v:90514.5-90514.29" switch \initial - attribute \src "libresoc.v:90718.9-90718.17" + attribute \src "libresoc.v:90514.9-90514.17" case 1'1 case end @@ -141721,14 +141517,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[13:0] end - attribute \src "libresoc.v:90736.3-90754.6" - process $proc$libresoc.v:90736$3836 + attribute \src "libresoc.v:90532.3-90550.6" + process $proc$libresoc.v:90532$3836 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90737.5-90737.29" + attribute \src "libresoc.v:90533.5-90533.29" switch \initial - attribute \src "libresoc.v:90737.9-90737.17" + attribute \src "libresoc.v:90533.9-90533.17" case 1'1 case end @@ -141756,14 +141552,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:90755.3-90773.6" - process $proc$libresoc.v:90755$3837 + attribute \src "libresoc.v:90551.3-90569.6" + process $proc$libresoc.v:90551$3837 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:90756.5-90756.29" + attribute \src "libresoc.v:90552.5-90552.29" switch \initial - attribute \src "libresoc.v:90756.9-90756.17" + attribute \src "libresoc.v:90552.9-90552.17" case 1'1 case end @@ -141791,14 +141587,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] end - attribute \src "libresoc.v:90774.3-90792.6" - process $proc$libresoc.v:90774$3838 + attribute \src "libresoc.v:90570.3-90588.6" + process $proc$libresoc.v:90570$3838 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90775.5-90775.29" + attribute \src "libresoc.v:90571.5-90571.29" switch \initial - attribute \src "libresoc.v:90775.9-90775.17" + attribute \src "libresoc.v:90571.9-90571.17" case 1'1 case end @@ -141826,14 +141622,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0] end - attribute \src "libresoc.v:90793.3-90811.6" - process $proc$libresoc.v:90793$3839 + attribute \src "libresoc.v:90589.3-90607.6" + process $proc$libresoc.v:90589$3839 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90794.5-90794.29" + attribute \src "libresoc.v:90590.5-90590.29" switch \initial - attribute \src "libresoc.v:90794.9-90794.17" + attribute \src "libresoc.v:90590.9-90590.17" case 1'1 case end @@ -141861,14 +141657,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0] end - attribute \src "libresoc.v:90812.3-90830.6" - process $proc$libresoc.v:90812$3840 + attribute \src "libresoc.v:90608.3-90626.6" + process $proc$libresoc.v:90608$3840 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90813.5-90813.29" + attribute \src "libresoc.v:90609.5-90609.29" switch \initial - attribute \src "libresoc.v:90813.9-90813.17" + attribute \src "libresoc.v:90609.9-90609.17" case 1'1 case end @@ -141896,14 +141692,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0] end - attribute \src "libresoc.v:90831.3-90849.6" - process $proc$libresoc.v:90831$3841 + attribute \src "libresoc.v:90627.3-90645.6" + process $proc$libresoc.v:90627$3841 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:90832.5-90832.29" + attribute \src "libresoc.v:90628.5-90628.29" switch \initial - attribute \src "libresoc.v:90832.9-90832.17" + attribute \src "libresoc.v:90628.9-90628.17" case 1'1 case end @@ -141931,14 +141727,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0] end - attribute \src "libresoc.v:90850.3-90868.6" - process $proc$libresoc.v:90850$3842 + attribute \src "libresoc.v:90646.3-90664.6" + process $proc$libresoc.v:90646$3842 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out2[2:0] $1\dec31_dec_sub0_sv_out2[2:0] - attribute \src "libresoc.v:90851.5-90851.29" + attribute \src "libresoc.v:90647.5-90647.29" switch \initial - attribute \src "libresoc.v:90851.9-90851.17" + attribute \src "libresoc.v:90647.9-90647.17" case 1'1 case end @@ -141966,14 +141762,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_out2 $0\dec31_dec_sub0_sv_out2[2:0] end - attribute \src "libresoc.v:90869.3-90887.6" - process $proc$libresoc.v:90869$3843 + attribute \src "libresoc.v:90665.3-90683.6" + process $proc$libresoc.v:90665$3843 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90870.5-90870.29" + attribute \src "libresoc.v:90666.5-90666.29" switch \initial - attribute \src "libresoc.v:90870.9-90870.17" + attribute \src "libresoc.v:90666.9-90666.17" case 1'1 case end @@ -142001,14 +141797,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0] end - attribute \src "libresoc.v:90888.3-90906.6" - process $proc$libresoc.v:90888$3844 + attribute \src "libresoc.v:90684.3-90702.6" + process $proc$libresoc.v:90684$3844 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90889.5-90889.29" + attribute \src "libresoc.v:90685.5-90685.29" switch \initial - attribute \src "libresoc.v:90889.9-90889.17" + attribute \src "libresoc.v:90685.9-90685.17" case 1'1 case end @@ -142036,14 +141832,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0] end - attribute \src "libresoc.v:90907.3-90925.6" - process $proc$libresoc.v:90907$3845 + attribute \src "libresoc.v:90703.3-90721.6" + process $proc$libresoc.v:90703$3845 assign { } { } assign { } { } assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:90908.5-90908.29" + attribute \src "libresoc.v:90704.5-90704.29" switch \initial - attribute \src "libresoc.v:90908.9-90908.17" + attribute \src "libresoc.v:90704.9-90704.17" case 1'1 case end @@ -142071,14 +141867,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end - attribute \src "libresoc.v:90926.3-90944.6" - process $proc$libresoc.v:90926$3846 + attribute \src "libresoc.v:90722.3-90740.6" + process $proc$libresoc.v:90722$3846 assign { } { } assign { } { } assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:90927.5-90927.29" + attribute \src "libresoc.v:90723.5-90723.29" switch \initial - attribute \src "libresoc.v:90927.9-90927.17" + attribute \src "libresoc.v:90723.9-90723.17" case 1'1 case end @@ -142106,14 +141902,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:90945.3-90963.6" - process $proc$libresoc.v:90945$3847 + attribute \src "libresoc.v:90741.3-90759.6" + process $proc$libresoc.v:90741$3847 assign { } { } assign { } { } assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:90946.5-90946.29" + attribute \src "libresoc.v:90742.5-90742.29" switch \initial - attribute \src "libresoc.v:90946.9-90946.17" + attribute \src "libresoc.v:90742.9-90742.17" case 1'1 case end @@ -142141,14 +141937,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end - attribute \src "libresoc.v:90964.3-90982.6" - process $proc$libresoc.v:90964$3848 + attribute \src "libresoc.v:90760.3-90778.6" + process $proc$libresoc.v:90760$3848 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:90965.5-90965.29" + attribute \src "libresoc.v:90761.5-90761.29" switch \initial - attribute \src "libresoc.v:90965.9-90965.17" + attribute \src "libresoc.v:90761.9-90761.17" case 1'1 case end @@ -142176,14 +141972,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end - attribute \src "libresoc.v:90983.3-91001.6" - process $proc$libresoc.v:90983$3849 + attribute \src "libresoc.v:90779.3-90797.6" + process $proc$libresoc.v:90779$3849 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:90984.5-90984.29" + attribute \src "libresoc.v:90780.5-90780.29" switch \initial - attribute \src "libresoc.v:90984.9-90984.17" + attribute \src "libresoc.v:90780.9-90780.17" case 1'1 case end @@ -142211,14 +142007,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] end - attribute \src "libresoc.v:91002.3-91020.6" - process $proc$libresoc.v:91002$3850 + attribute \src "libresoc.v:90798.3-90816.6" + process $proc$libresoc.v:90798$3850 assign { } { } assign { } { } assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:91003.5-91003.29" + attribute \src "libresoc.v:90799.5-90799.29" switch \initial - attribute \src "libresoc.v:91003.9-91003.17" + attribute \src "libresoc.v:90799.9-90799.17" case 1'1 case end @@ -142246,14 +142042,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] end - attribute \src "libresoc.v:91021.3-91039.6" - process $proc$libresoc.v:91021$3851 + attribute \src "libresoc.v:90817.3-90835.6" + process $proc$libresoc.v:90817$3851 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:91022.5-91022.29" + attribute \src "libresoc.v:90818.5-90818.29" switch \initial - attribute \src "libresoc.v:91022.9-91022.17" + attribute \src "libresoc.v:90818.9-90818.17" case 1'1 case end @@ -142281,14 +142077,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] end - attribute \src "libresoc.v:91040.3-91058.6" - process $proc$libresoc.v:91040$3852 + attribute \src "libresoc.v:90836.3-90854.6" + process $proc$libresoc.v:90836$3852 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:91041.5-91041.29" + attribute \src "libresoc.v:90837.5-90837.29" switch \initial - attribute \src "libresoc.v:91041.9-91041.17" + attribute \src "libresoc.v:90837.9-90837.17" case 1'1 case end @@ -142316,14 +142112,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] end - attribute \src "libresoc.v:91059.3-91077.6" - process $proc$libresoc.v:91059$3853 + attribute \src "libresoc.v:90855.3-90873.6" + process $proc$libresoc.v:90855$3853 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:91060.5-91060.29" + attribute \src "libresoc.v:90856.5-90856.29" switch \initial - attribute \src "libresoc.v:91060.9-91060.17" + attribute \src "libresoc.v:90856.9-90856.17" case 1'1 case end @@ -142351,14 +142147,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] end - attribute \src "libresoc.v:91078.3-91096.6" - process $proc$libresoc.v:91078$3854 + attribute \src "libresoc.v:90874.3-90892.6" + process $proc$libresoc.v:90874$3854 assign { } { } assign { } { } assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:91079.5-91079.29" + attribute \src "libresoc.v:90875.5-90875.29" switch \initial - attribute \src "libresoc.v:91079.9-91079.17" + attribute \src "libresoc.v:90875.9-90875.17" case 1'1 case end @@ -142386,14 +142182,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] end - attribute \src "libresoc.v:91097.3-91115.6" - process $proc$libresoc.v:91097$3855 + attribute \src "libresoc.v:90893.3-90911.6" + process $proc$libresoc.v:90893$3855 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:91098.5-91098.29" + attribute \src "libresoc.v:90894.5-90894.29" switch \initial - attribute \src "libresoc.v:91098.9-91098.17" + attribute \src "libresoc.v:90894.9-90894.17" case 1'1 case end @@ -142421,14 +142217,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] end - attribute \src "libresoc.v:91116.3-91134.6" - process $proc$libresoc.v:91116$3856 + attribute \src "libresoc.v:90912.3-90930.6" + process $proc$libresoc.v:90912$3856 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:91117.5-91117.29" + attribute \src "libresoc.v:90913.5-90913.29" switch \initial - attribute \src "libresoc.v:91117.9-91117.17" + attribute \src "libresoc.v:90913.9-90913.17" case 1'1 case end @@ -142456,14 +142252,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] end - attribute \src "libresoc.v:91135.3-91153.6" - process $proc$libresoc.v:91135$3857 + attribute \src "libresoc.v:90931.3-90949.6" + process $proc$libresoc.v:90931$3857 assign { } { } assign { } { } assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:91136.5-91136.29" + attribute \src "libresoc.v:90932.5-90932.29" switch \initial - attribute \src "libresoc.v:91136.9-91136.17" + attribute \src "libresoc.v:90932.9-90932.17" case 1'1 case end @@ -142491,14 +142287,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] end - attribute \src "libresoc.v:91154.3-91172.6" - process $proc$libresoc.v:91154$3858 + attribute \src "libresoc.v:90950.3-90968.6" + process $proc$libresoc.v:90950$3858 assign { } { } assign { } { } assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:91155.5-91155.29" + attribute \src "libresoc.v:90951.5-90951.29" switch \initial - attribute \src "libresoc.v:91155.9-91155.17" + attribute \src "libresoc.v:90951.9-90951.17" case 1'1 case end @@ -142526,14 +142322,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] end - attribute \src "libresoc.v:91173.3-91191.6" - process $proc$libresoc.v:91173$3859 + attribute \src "libresoc.v:90969.3-90987.6" + process $proc$libresoc.v:90969$3859 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:91174.5-91174.29" + attribute \src "libresoc.v:90970.5-90970.29" switch \initial - attribute \src "libresoc.v:91174.9-91174.17" + attribute \src "libresoc.v:90970.9-90970.17" case 1'1 case end @@ -142561,14 +142357,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] end - attribute \src "libresoc.v:91192.3-91210.6" - process $proc$libresoc.v:91192$3860 + attribute \src "libresoc.v:90988.3-91006.6" + process $proc$libresoc.v:90988$3860 assign { } { } assign { } { } assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:91193.5-91193.29" + attribute \src "libresoc.v:90989.5-90989.29" switch \initial - attribute \src "libresoc.v:91193.9-91193.17" + attribute \src "libresoc.v:90989.9-90989.17" case 1'1 case end @@ -142596,14 +142392,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] end - attribute \src "libresoc.v:91211.3-91229.6" - process $proc$libresoc.v:91211$3861 + attribute \src "libresoc.v:91007.3-91025.6" + process $proc$libresoc.v:91007$3861 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:91212.5-91212.29" + attribute \src "libresoc.v:91008.5-91008.29" switch \initial - attribute \src "libresoc.v:91212.9-91212.17" + attribute \src "libresoc.v:91008.9-91008.17" case 1'1 case end @@ -142631,14 +142427,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] end - attribute \src "libresoc.v:91230.3-91248.6" - process $proc$libresoc.v:91230$3862 + attribute \src "libresoc.v:91026.3-91044.6" + process $proc$libresoc.v:91026$3862 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:91231.5-91231.29" + attribute \src "libresoc.v:91027.5-91027.29" switch \initial - attribute \src "libresoc.v:91231.9-91231.17" + attribute \src "libresoc.v:91027.9-91027.17" case 1'1 case end @@ -142666,14 +142462,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0] end - attribute \src "libresoc.v:91249.3-91267.6" - process $proc$libresoc.v:91249$3863 + attribute \src "libresoc.v:91045.3-91063.6" + process $proc$libresoc.v:91045$3863 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:91250.5-91250.29" + attribute \src "libresoc.v:91046.5-91046.29" switch \initial - attribute \src "libresoc.v:91250.9-91250.17" + attribute \src "libresoc.v:91046.9-91046.17" case 1'1 case end @@ -142701,14 +142497,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0] end - attribute \src "libresoc.v:91268.3-91286.6" - process $proc$libresoc.v:91268$3864 + attribute \src "libresoc.v:91064.3-91082.6" + process $proc$libresoc.v:91064$3864 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:91269.5-91269.29" + attribute \src "libresoc.v:91065.5-91065.29" switch \initial - attribute \src "libresoc.v:91269.9-91269.17" + attribute \src "libresoc.v:91065.9-91065.17" case 1'1 case end @@ -142736,14 +142532,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] end - attribute \src "libresoc.v:91287.3-91305.6" - process $proc$libresoc.v:91287$3865 + attribute \src "libresoc.v:91083.3-91101.6" + process $proc$libresoc.v:91083$3865 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:91288.5-91288.29" + attribute \src "libresoc.v:91084.5-91084.29" switch \initial - attribute \src "libresoc.v:91288.9-91288.17" + attribute \src "libresoc.v:91084.9-91084.17" case 1'1 case end @@ -142771,14 +142567,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] end - attribute \src "libresoc.v:91306.3-91324.6" - process $proc$libresoc.v:91306$3866 + attribute \src "libresoc.v:91102.3-91120.6" + process $proc$libresoc.v:91102$3866 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:91307.5-91307.29" + attribute \src "libresoc.v:91103.5-91103.29" switch \initial - attribute \src "libresoc.v:91307.9-91307.17" + attribute \src "libresoc.v:91103.9-91103.17" case 1'1 case end @@ -142806,14 +142602,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] end - attribute \src "libresoc.v:91325.3-91343.6" - process $proc$libresoc.v:91325$3867 + attribute \src "libresoc.v:91121.3-91139.6" + process $proc$libresoc.v:91121$3867 assign { } { } assign { } { } assign $0\dec31_dec_sub0_out_sel[2:0] $1\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:91326.5-91326.29" + attribute \src "libresoc.v:91122.5-91122.29" switch \initial - attribute \src "libresoc.v:91326.9-91326.17" + attribute \src "libresoc.v:91122.9-91122.17" case 1'1 case end @@ -142843,144 +142639,144 @@ module \dec31_dec_sub0 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:91349.1-92920.10" +attribute \src "libresoc.v:91145.1-92716.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" module \dec31_dec_sub10 - attribute \src "libresoc.v:92697.3-92733.6" + attribute \src "libresoc.v:92493.3-92529.6" wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92734.3-92770.6" + attribute \src "libresoc.v:92530.3-92566.6" wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:92253.3-92289.6" + attribute \src "libresoc.v:92049.3-92085.6" wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:92401.3-92437.6" + attribute \src "libresoc.v:92197.3-92233.6" wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91735.3-91771.6" + attribute \src "libresoc.v:91531.3-91567.6" wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91772.3-91808.6" + attribute \src "libresoc.v:91568.3-91604.6" wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:92216.3-92252.6" + attribute \src "libresoc.v:92012.3-92048.6" wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:92364.3-92400.6" + attribute \src "libresoc.v:92160.3-92196.6" wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:92512.3-92548.6" + attribute \src "libresoc.v:92308.3-92344.6" wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91698.3-91734.6" + attribute \src "libresoc.v:91494.3-91530.6" wire width 14 $0\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:92771.3-92807.6" + attribute \src "libresoc.v:92567.3-92603.6" wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92808.3-92844.6" + attribute \src "libresoc.v:92604.3-92640.6" wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92845.3-92881.6" + attribute \src "libresoc.v:92641.3-92677.6" wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:92105.3-92141.6" + attribute \src "libresoc.v:91901.3-91937.6" wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:92290.3-92326.6" + attribute \src "libresoc.v:92086.3-92122.6" wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:92327.3-92363.6" + attribute \src "libresoc.v:92123.3-92159.6" wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:92549.3-92585.6" + attribute \src "libresoc.v:92345.3-92381.6" wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:92068.3-92104.6" + attribute \src "libresoc.v:91864.3-91900.6" wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:92623.3-92659.6" + attribute \src "libresoc.v:92419.3-92455.6" wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92882.3-92918.6" + attribute \src "libresoc.v:92678.3-92714.6" wire width 3 $0\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:92179.3-92215.6" + attribute \src "libresoc.v:91975.3-92011.6" wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:92475.3-92511.6" + attribute \src "libresoc.v:92271.3-92307.6" wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:92660.3-92696.6" + attribute \src "libresoc.v:92456.3-92492.6" wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:92586.3-92622.6" + attribute \src "libresoc.v:92382.3-92418.6" wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:92438.3-92474.6" + attribute \src "libresoc.v:92234.3-92270.6" wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:91994.3-92030.6" + attribute \src "libresoc.v:91790.3-91826.6" wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:92031.3-92067.6" + attribute \src "libresoc.v:91827.3-91863.6" wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91809.3-91845.6" + attribute \src "libresoc.v:91605.3-91641.6" wire width 3 $0\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91846.3-91882.6" + attribute \src "libresoc.v:91642.3-91678.6" wire width 3 $0\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91883.3-91919.6" + attribute \src "libresoc.v:91679.3-91715.6" wire width 3 $0\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:91957.3-91993.6" + attribute \src "libresoc.v:91753.3-91789.6" wire width 3 $0\dec31_dec_sub10_sv_out2[2:0] - attribute \src "libresoc.v:91920.3-91956.6" + attribute \src "libresoc.v:91716.3-91752.6" wire width 3 $0\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:92142.3-92178.6" + attribute \src "libresoc.v:91938.3-91974.6" wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:91350.7-91350.20" + attribute \src "libresoc.v:91146.7-91146.20" wire $0\initial[0:0] - attribute \src "libresoc.v:92697.3-92733.6" + attribute \src "libresoc.v:92493.3-92529.6" wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92734.3-92770.6" + attribute \src "libresoc.v:92530.3-92566.6" wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:92253.3-92289.6" + attribute \src "libresoc.v:92049.3-92085.6" wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:92401.3-92437.6" + attribute \src "libresoc.v:92197.3-92233.6" wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91735.3-91771.6" + attribute \src "libresoc.v:91531.3-91567.6" wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91772.3-91808.6" + attribute \src "libresoc.v:91568.3-91604.6" wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:92216.3-92252.6" + attribute \src "libresoc.v:92012.3-92048.6" wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:92364.3-92400.6" + attribute \src "libresoc.v:92160.3-92196.6" wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:92512.3-92548.6" + attribute \src "libresoc.v:92308.3-92344.6" wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91698.3-91734.6" + attribute \src "libresoc.v:91494.3-91530.6" wire width 14 $1\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:92771.3-92807.6" + attribute \src "libresoc.v:92567.3-92603.6" wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92808.3-92844.6" + attribute \src "libresoc.v:92604.3-92640.6" wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92845.3-92881.6" + attribute \src "libresoc.v:92641.3-92677.6" wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:92105.3-92141.6" + attribute \src "libresoc.v:91901.3-91937.6" wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:92290.3-92326.6" + attribute \src "libresoc.v:92086.3-92122.6" wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:92327.3-92363.6" + attribute \src "libresoc.v:92123.3-92159.6" wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:92549.3-92585.6" + attribute \src "libresoc.v:92345.3-92381.6" wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:92068.3-92104.6" + attribute \src "libresoc.v:91864.3-91900.6" wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:92623.3-92659.6" + attribute \src "libresoc.v:92419.3-92455.6" wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92882.3-92918.6" + attribute \src "libresoc.v:92678.3-92714.6" wire width 3 $1\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:92179.3-92215.6" + attribute \src "libresoc.v:91975.3-92011.6" wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:92475.3-92511.6" + attribute \src "libresoc.v:92271.3-92307.6" wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:92660.3-92696.6" + attribute \src "libresoc.v:92456.3-92492.6" wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:92586.3-92622.6" + attribute \src "libresoc.v:92382.3-92418.6" wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:92438.3-92474.6" + attribute \src "libresoc.v:92234.3-92270.6" wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:91994.3-92030.6" + attribute \src "libresoc.v:91790.3-91826.6" wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:92031.3-92067.6" + attribute \src "libresoc.v:91827.3-91863.6" wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91809.3-91845.6" + attribute \src "libresoc.v:91605.3-91641.6" wire width 3 $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91846.3-91882.6" + attribute \src "libresoc.v:91642.3-91678.6" wire width 3 $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91883.3-91919.6" + attribute \src "libresoc.v:91679.3-91715.6" wire width 3 $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:91957.3-91993.6" + attribute \src "libresoc.v:91753.3-91789.6" wire width 3 $1\dec31_dec_sub10_sv_out2[2:0] - attribute \src "libresoc.v:91920.3-91956.6" + attribute \src "libresoc.v:91716.3-91752.6" wire width 3 $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:92142.3-92178.6" + attribute \src "libresoc.v:91938.3-91974.6" wire width 2 $1\dec31_dec_sub10_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -143292,28 +143088,28 @@ module \dec31_dec_sub10 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub10_upd - attribute \src "libresoc.v:91350.7-91350.15" + attribute \src "libresoc.v:91146.7-91146.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:91350.7-91350.20" - process $proc$libresoc.v:91350$3902 + attribute \src "libresoc.v:91146.7-91146.20" + process $proc$libresoc.v:91146$3902 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:91698.3-91734.6" - process $proc$libresoc.v:91698$3869 + attribute \src "libresoc.v:91494.3-91530.6" + process $proc$libresoc.v:91494$3869 assign { } { } assign { } { } assign $0\dec31_dec_sub10_function_unit[13:0] $1\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:91699.5-91699.29" + attribute \src "libresoc.v:91495.5-91495.29" switch \initial - attribute \src "libresoc.v:91699.9-91699.17" + attribute \src "libresoc.v:91495.9-91495.17" case 1'1 case end @@ -143365,14 +143161,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[13:0] end - attribute \src "libresoc.v:91735.3-91771.6" - process $proc$libresoc.v:91735$3870 + attribute \src "libresoc.v:91531.3-91567.6" + process $proc$libresoc.v:91531$3870 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91736.5-91736.29" + attribute \src "libresoc.v:91532.5-91532.29" switch \initial - attribute \src "libresoc.v:91736.9-91736.17" + attribute \src "libresoc.v:91532.9-91532.17" case 1'1 case end @@ -143424,14 +143220,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end - attribute \src "libresoc.v:91772.3-91808.6" - process $proc$libresoc.v:91772$3871 + attribute \src "libresoc.v:91568.3-91604.6" + process $proc$libresoc.v:91568$3871 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:91773.5-91773.29" + attribute \src "libresoc.v:91569.5-91569.29" switch \initial - attribute \src "libresoc.v:91773.9-91773.17" + attribute \src "libresoc.v:91569.9-91569.17" case 1'1 case end @@ -143483,14 +143279,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] end - attribute \src "libresoc.v:91809.3-91845.6" - process $proc$libresoc.v:91809$3872 + attribute \src "libresoc.v:91605.3-91641.6" + process $proc$libresoc.v:91605$3872 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91810.5-91810.29" + attribute \src "libresoc.v:91606.5-91606.29" switch \initial - attribute \src "libresoc.v:91810.9-91810.17" + attribute \src "libresoc.v:91606.9-91606.17" case 1'1 case end @@ -143542,14 +143338,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0] end - attribute \src "libresoc.v:91846.3-91882.6" - process $proc$libresoc.v:91846$3873 + attribute \src "libresoc.v:91642.3-91678.6" + process $proc$libresoc.v:91642$3873 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91847.5-91847.29" + attribute \src "libresoc.v:91643.5-91643.29" switch \initial - attribute \src "libresoc.v:91847.9-91847.17" + attribute \src "libresoc.v:91643.9-91643.17" case 1'1 case end @@ -143601,14 +143397,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0] end - attribute \src "libresoc.v:91883.3-91919.6" - process $proc$libresoc.v:91883$3874 + attribute \src "libresoc.v:91679.3-91715.6" + process $proc$libresoc.v:91679$3874 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:91884.5-91884.29" + attribute \src "libresoc.v:91680.5-91680.29" switch \initial - attribute \src "libresoc.v:91884.9-91884.17" + attribute \src "libresoc.v:91680.9-91680.17" case 1'1 case end @@ -143660,14 +143456,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0] end - attribute \src "libresoc.v:91920.3-91956.6" - process $proc$libresoc.v:91920$3875 + attribute \src "libresoc.v:91716.3-91752.6" + process $proc$libresoc.v:91716$3875 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:91921.5-91921.29" + attribute \src "libresoc.v:91717.5-91717.29" switch \initial - attribute \src "libresoc.v:91921.9-91921.17" + attribute \src "libresoc.v:91717.9-91717.17" case 1'1 case end @@ -143719,14 +143515,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0] end - attribute \src "libresoc.v:91957.3-91993.6" - process $proc$libresoc.v:91957$3876 + attribute \src "libresoc.v:91753.3-91789.6" + process $proc$libresoc.v:91753$3876 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out2[2:0] $1\dec31_dec_sub10_sv_out2[2:0] - attribute \src "libresoc.v:91958.5-91958.29" + attribute \src "libresoc.v:91754.5-91754.29" switch \initial - attribute \src "libresoc.v:91958.9-91958.17" + attribute \src "libresoc.v:91754.9-91754.17" case 1'1 case end @@ -143778,14 +143574,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_out2 $0\dec31_dec_sub10_sv_out2[2:0] end - attribute \src "libresoc.v:91994.3-92030.6" - process $proc$libresoc.v:91994$3877 + attribute \src "libresoc.v:91790.3-91826.6" + process $proc$libresoc.v:91790$3877 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:91995.5-91995.29" + attribute \src "libresoc.v:91791.5-91791.29" switch \initial - attribute \src "libresoc.v:91995.9-91995.17" + attribute \src "libresoc.v:91791.9-91791.17" case 1'1 case end @@ -143837,14 +143633,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0] end - attribute \src "libresoc.v:92031.3-92067.6" - process $proc$libresoc.v:92031$3878 + attribute \src "libresoc.v:91827.3-91863.6" + process $proc$libresoc.v:91827$3878 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:92032.5-92032.29" + attribute \src "libresoc.v:91828.5-91828.29" switch \initial - attribute \src "libresoc.v:92032.9-92032.17" + attribute \src "libresoc.v:91828.9-91828.17" case 1'1 case end @@ -143896,14 +143692,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0] end - attribute \src "libresoc.v:92068.3-92104.6" - process $proc$libresoc.v:92068$3879 + attribute \src "libresoc.v:91864.3-91900.6" + process $proc$libresoc.v:91864$3879 assign { } { } assign { } { } assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:92069.5-92069.29" + attribute \src "libresoc.v:91865.5-91865.29" switch \initial - attribute \src "libresoc.v:92069.9-92069.17" + attribute \src "libresoc.v:91865.9-91865.17" case 1'1 case end @@ -143955,14 +143751,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "libresoc.v:92105.3-92141.6" - process $proc$libresoc.v:92105$3880 + attribute \src "libresoc.v:91901.3-91937.6" + process $proc$libresoc.v:91901$3880 assign { } { } assign { } { } assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:92106.5-92106.29" + attribute \src "libresoc.v:91902.5-91902.29" switch \initial - attribute \src "libresoc.v:92106.9-92106.17" + attribute \src "libresoc.v:91902.9-91902.17" case 1'1 case end @@ -144014,14 +143810,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end - attribute \src "libresoc.v:92142.3-92178.6" - process $proc$libresoc.v:92142$3881 + attribute \src "libresoc.v:91938.3-91974.6" + process $proc$libresoc.v:91938$3881 assign { } { } assign { } { } assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:92143.5-92143.29" + attribute \src "libresoc.v:91939.5-91939.29" switch \initial - attribute \src "libresoc.v:92143.9-92143.17" + attribute \src "libresoc.v:91939.9-91939.17" case 1'1 case end @@ -144073,14 +143869,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "libresoc.v:92179.3-92215.6" - process $proc$libresoc.v:92179$3882 + attribute \src "libresoc.v:91975.3-92011.6" + process $proc$libresoc.v:91975$3882 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:92180.5-92180.29" + attribute \src "libresoc.v:91976.5-91976.29" switch \initial - attribute \src "libresoc.v:92180.9-92180.17" + attribute \src "libresoc.v:91976.9-91976.17" case 1'1 case end @@ -144132,14 +143928,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end - attribute \src "libresoc.v:92216.3-92252.6" - process $proc$libresoc.v:92216$3883 + attribute \src "libresoc.v:92012.3-92048.6" + process $proc$libresoc.v:92012$3883 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:92217.5-92217.29" + attribute \src "libresoc.v:92013.5-92013.29" switch \initial - attribute \src "libresoc.v:92217.9-92217.17" + attribute \src "libresoc.v:92013.9-92013.17" case 1'1 case end @@ -144191,14 +143987,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end - attribute \src "libresoc.v:92253.3-92289.6" - process $proc$libresoc.v:92253$3884 + attribute \src "libresoc.v:92049.3-92085.6" + process $proc$libresoc.v:92049$3884 assign { } { } assign { } { } assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:92254.5-92254.29" + attribute \src "libresoc.v:92050.5-92050.29" switch \initial - attribute \src "libresoc.v:92254.9-92254.17" + attribute \src "libresoc.v:92050.9-92050.17" case 1'1 case end @@ -144250,14 +144046,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end - attribute \src "libresoc.v:92290.3-92326.6" - process $proc$libresoc.v:92290$3885 + attribute \src "libresoc.v:92086.3-92122.6" + process $proc$libresoc.v:92086$3885 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:92291.5-92291.29" + attribute \src "libresoc.v:92087.5-92087.29" switch \initial - attribute \src "libresoc.v:92291.9-92291.17" + attribute \src "libresoc.v:92087.9-92087.17" case 1'1 case end @@ -144309,14 +144105,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] end - attribute \src "libresoc.v:92327.3-92363.6" - process $proc$libresoc.v:92327$3886 + attribute \src "libresoc.v:92123.3-92159.6" + process $proc$libresoc.v:92123$3886 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:92328.5-92328.29" + attribute \src "libresoc.v:92124.5-92124.29" switch \initial - attribute \src "libresoc.v:92328.9-92328.17" + attribute \src "libresoc.v:92124.9-92124.17" case 1'1 case end @@ -144368,14 +144164,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] end - attribute \src "libresoc.v:92364.3-92400.6" - process $proc$libresoc.v:92364$3887 + attribute \src "libresoc.v:92160.3-92196.6" + process $proc$libresoc.v:92160$3887 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:92365.5-92365.29" + attribute \src "libresoc.v:92161.5-92161.29" switch \initial - attribute \src "libresoc.v:92365.9-92365.17" + attribute \src "libresoc.v:92161.9-92161.17" case 1'1 case end @@ -144427,14 +144223,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] end - attribute \src "libresoc.v:92401.3-92437.6" - process $proc$libresoc.v:92401$3888 + attribute \src "libresoc.v:92197.3-92233.6" + process $proc$libresoc.v:92197$3888 assign { } { } assign { } { } assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:92402.5-92402.29" + attribute \src "libresoc.v:92198.5-92198.29" switch \initial - attribute \src "libresoc.v:92402.9-92402.17" + attribute \src "libresoc.v:92198.9-92198.17" case 1'1 case end @@ -144486,14 +144282,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] end - attribute \src "libresoc.v:92438.3-92474.6" - process $proc$libresoc.v:92438$3889 + attribute \src "libresoc.v:92234.3-92270.6" + process $proc$libresoc.v:92234$3889 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:92439.5-92439.29" + attribute \src "libresoc.v:92235.5-92235.29" switch \initial - attribute \src "libresoc.v:92439.9-92439.17" + attribute \src "libresoc.v:92235.9-92235.17" case 1'1 case end @@ -144545,14 +144341,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] end - attribute \src "libresoc.v:92475.3-92511.6" - process $proc$libresoc.v:92475$3890 + attribute \src "libresoc.v:92271.3-92307.6" + process $proc$libresoc.v:92271$3890 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:92476.5-92476.29" + attribute \src "libresoc.v:92272.5-92272.29" switch \initial - attribute \src "libresoc.v:92476.9-92476.17" + attribute \src "libresoc.v:92272.9-92272.17" case 1'1 case end @@ -144604,14 +144400,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end - attribute \src "libresoc.v:92512.3-92548.6" - process $proc$libresoc.v:92512$3891 + attribute \src "libresoc.v:92308.3-92344.6" + process $proc$libresoc.v:92308$3891 assign { } { } assign { } { } assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:92513.5-92513.29" + attribute \src "libresoc.v:92309.5-92309.29" switch \initial - attribute \src "libresoc.v:92513.9-92513.17" + attribute \src "libresoc.v:92309.9-92309.17" case 1'1 case end @@ -144663,14 +144459,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "libresoc.v:92549.3-92585.6" - process $proc$libresoc.v:92549$3892 + attribute \src "libresoc.v:92345.3-92381.6" + process $proc$libresoc.v:92345$3892 assign { } { } assign { } { } assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:92550.5-92550.29" + attribute \src "libresoc.v:92346.5-92346.29" switch \initial - attribute \src "libresoc.v:92550.9-92550.17" + attribute \src "libresoc.v:92346.9-92346.17" case 1'1 case end @@ -144722,14 +144518,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end - attribute \src "libresoc.v:92586.3-92622.6" - process $proc$libresoc.v:92586$3893 + attribute \src "libresoc.v:92382.3-92418.6" + process $proc$libresoc.v:92382$3893 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:92587.5-92587.29" + attribute \src "libresoc.v:92383.5-92383.29" switch \initial - attribute \src "libresoc.v:92587.9-92587.17" + attribute \src "libresoc.v:92383.9-92383.17" case 1'1 case end @@ -144781,14 +144577,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "libresoc.v:92623.3-92659.6" - process $proc$libresoc.v:92623$3894 + attribute \src "libresoc.v:92419.3-92455.6" + process $proc$libresoc.v:92419$3894 assign { } { } assign { } { } assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92624.5-92624.29" + attribute \src "libresoc.v:92420.5-92420.29" switch \initial - attribute \src "libresoc.v:92624.9-92624.17" + attribute \src "libresoc.v:92420.9-92420.17" case 1'1 case end @@ -144840,14 +144636,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "libresoc.v:92660.3-92696.6" - process $proc$libresoc.v:92660$3895 + attribute \src "libresoc.v:92456.3-92492.6" + process $proc$libresoc.v:92456$3895 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:92661.5-92661.29" + attribute \src "libresoc.v:92457.5-92457.29" switch \initial - attribute \src "libresoc.v:92661.9-92661.17" + attribute \src "libresoc.v:92457.9-92457.17" case 1'1 case end @@ -144899,14 +144695,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "libresoc.v:92697.3-92733.6" - process $proc$libresoc.v:92697$3896 + attribute \src "libresoc.v:92493.3-92529.6" + process $proc$libresoc.v:92493$3896 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92698.5-92698.29" + attribute \src "libresoc.v:92494.5-92494.29" switch \initial - attribute \src "libresoc.v:92698.9-92698.17" + attribute \src "libresoc.v:92494.9-92494.17" case 1'1 case end @@ -144958,14 +144754,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0] end - attribute \src "libresoc.v:92734.3-92770.6" - process $proc$libresoc.v:92734$3897 + attribute \src "libresoc.v:92530.3-92566.6" + process $proc$libresoc.v:92530$3897 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:92735.5-92735.29" + attribute \src "libresoc.v:92531.5-92531.29" switch \initial - attribute \src "libresoc.v:92735.9-92735.17" + attribute \src "libresoc.v:92531.9-92531.17" case 1'1 case end @@ -145017,14 +144813,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0] end - attribute \src "libresoc.v:92771.3-92807.6" - process $proc$libresoc.v:92771$3898 + attribute \src "libresoc.v:92567.3-92603.6" + process $proc$libresoc.v:92567$3898 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92772.5-92772.29" + attribute \src "libresoc.v:92568.5-92568.29" switch \initial - attribute \src "libresoc.v:92772.9-92772.17" + attribute \src "libresoc.v:92568.9-92568.17" case 1'1 case end @@ -145076,14 +144872,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "libresoc.v:92808.3-92844.6" - process $proc$libresoc.v:92808$3899 + attribute \src "libresoc.v:92604.3-92640.6" + process $proc$libresoc.v:92604$3899 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92809.5-92809.29" + attribute \src "libresoc.v:92605.5-92605.29" switch \initial - attribute \src "libresoc.v:92809.9-92809.17" + attribute \src "libresoc.v:92605.9-92605.17" case 1'1 case end @@ -145135,14 +144931,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "libresoc.v:92845.3-92881.6" - process $proc$libresoc.v:92845$3900 + attribute \src "libresoc.v:92641.3-92677.6" + process $proc$libresoc.v:92641$3900 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:92846.5-92846.29" + attribute \src "libresoc.v:92642.5-92642.29" switch \initial - attribute \src "libresoc.v:92846.9-92846.17" + attribute \src "libresoc.v:92642.9-92642.17" case 1'1 case end @@ -145194,14 +144990,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "libresoc.v:92882.3-92918.6" - process $proc$libresoc.v:92882$3901 + attribute \src "libresoc.v:92678.3-92714.6" + process $proc$libresoc.v:92678$3901 assign { } { } assign { } { } assign $0\dec31_dec_sub10_out_sel[2:0] $1\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:92883.5-92883.29" + attribute \src "libresoc.v:92679.5-92679.29" switch \initial - attribute \src "libresoc.v:92883.9-92883.17" + attribute \src "libresoc.v:92679.9-92679.17" case 1'1 case end @@ -145255,144 +145051,144 @@ module \dec31_dec_sub10 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:92924.1-95089.10" +attribute \src "libresoc.v:92720.1-94885.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" module \dec31_dec_sub11 - attribute \src "libresoc.v:94758.3-94812.6" + attribute \src "libresoc.v:94554.3-94608.6" wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94813.3-94867.6" + attribute \src "libresoc.v:94609.3-94663.6" wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:94098.3-94152.6" + attribute \src "libresoc.v:93894.3-93948.6" wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:94318.3-94372.6" + attribute \src "libresoc.v:94114.3-94168.6" wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:93328.3-93382.6" + attribute \src "libresoc.v:93124.3-93178.6" wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:93383.3-93437.6" + attribute \src "libresoc.v:93179.3-93233.6" wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:94043.3-94097.6" + attribute \src "libresoc.v:93839.3-93893.6" wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:94263.3-94317.6" + attribute \src "libresoc.v:94059.3-94113.6" wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:94483.3-94537.6" + attribute \src "libresoc.v:94279.3-94333.6" wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:93273.3-93327.6" + attribute \src "libresoc.v:93069.3-93123.6" wire width 14 $0\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:94868.3-94922.6" + attribute \src "libresoc.v:94664.3-94718.6" wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:94923.3-94977.6" + attribute \src "libresoc.v:94719.3-94773.6" wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:94978.3-95032.6" + attribute \src "libresoc.v:94774.3-94828.6" wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:93878.3-93932.6" + attribute \src "libresoc.v:93674.3-93728.6" wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:94153.3-94207.6" + attribute \src "libresoc.v:93949.3-94003.6" wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:94208.3-94262.6" + attribute \src "libresoc.v:94004.3-94058.6" wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:94538.3-94592.6" + attribute \src "libresoc.v:94334.3-94388.6" wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93823.3-93877.6" + attribute \src "libresoc.v:93619.3-93673.6" wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:94648.3-94702.6" + attribute \src "libresoc.v:94444.3-94498.6" wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:95033.3-95087.6" + attribute \src "libresoc.v:94829.3-94883.6" wire width 3 $0\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:93988.3-94042.6" + attribute \src "libresoc.v:93784.3-93838.6" wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:94428.3-94482.6" + attribute \src "libresoc.v:94224.3-94278.6" wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:94703.3-94757.6" + attribute \src "libresoc.v:94499.3-94553.6" wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:94593.3-94647.6" + attribute \src "libresoc.v:94389.3-94443.6" wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:94373.3-94427.6" + attribute \src "libresoc.v:94169.3-94223.6" wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:93713.3-93767.6" + attribute \src "libresoc.v:93509.3-93563.6" wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93768.3-93822.6" + attribute \src "libresoc.v:93564.3-93618.6" wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:93438.3-93492.6" + attribute \src "libresoc.v:93234.3-93288.6" wire width 3 $0\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:93493.3-93547.6" + attribute \src "libresoc.v:93289.3-93343.6" wire width 3 $0\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:93548.3-93602.6" + attribute \src "libresoc.v:93344.3-93398.6" wire width 3 $0\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:93658.3-93712.6" + attribute \src "libresoc.v:93454.3-93508.6" wire width 3 $0\dec31_dec_sub11_sv_out2[2:0] - attribute \src "libresoc.v:93603.3-93657.6" + attribute \src "libresoc.v:93399.3-93453.6" wire width 3 $0\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:93933.3-93987.6" + attribute \src "libresoc.v:93729.3-93783.6" wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:92925.7-92925.20" + attribute \src "libresoc.v:92721.7-92721.20" wire $0\initial[0:0] - attribute \src "libresoc.v:94758.3-94812.6" + attribute \src "libresoc.v:94554.3-94608.6" wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94813.3-94867.6" + attribute \src "libresoc.v:94609.3-94663.6" wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:94098.3-94152.6" + attribute \src "libresoc.v:93894.3-93948.6" wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:94318.3-94372.6" + attribute \src "libresoc.v:94114.3-94168.6" wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:93328.3-93382.6" + attribute \src "libresoc.v:93124.3-93178.6" wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:93383.3-93437.6" + attribute \src "libresoc.v:93179.3-93233.6" wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:94043.3-94097.6" + attribute \src "libresoc.v:93839.3-93893.6" wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:94263.3-94317.6" + attribute \src "libresoc.v:94059.3-94113.6" wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:94483.3-94537.6" + attribute \src "libresoc.v:94279.3-94333.6" wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:93273.3-93327.6" + attribute \src "libresoc.v:93069.3-93123.6" wire width 14 $1\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:94868.3-94922.6" + attribute \src "libresoc.v:94664.3-94718.6" wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:94923.3-94977.6" + attribute \src "libresoc.v:94719.3-94773.6" wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:94978.3-95032.6" + attribute \src "libresoc.v:94774.3-94828.6" wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:93878.3-93932.6" + attribute \src "libresoc.v:93674.3-93728.6" wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:94153.3-94207.6" + attribute \src "libresoc.v:93949.3-94003.6" wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:94208.3-94262.6" + attribute \src "libresoc.v:94004.3-94058.6" wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:94538.3-94592.6" + attribute \src "libresoc.v:94334.3-94388.6" wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93823.3-93877.6" + attribute \src "libresoc.v:93619.3-93673.6" wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:94648.3-94702.6" + attribute \src "libresoc.v:94444.3-94498.6" wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:95033.3-95087.6" + attribute \src "libresoc.v:94829.3-94883.6" wire width 3 $1\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:93988.3-94042.6" + attribute \src "libresoc.v:93784.3-93838.6" wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:94428.3-94482.6" + attribute \src "libresoc.v:94224.3-94278.6" wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:94703.3-94757.6" + attribute \src "libresoc.v:94499.3-94553.6" wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:94593.3-94647.6" + attribute \src "libresoc.v:94389.3-94443.6" wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:94373.3-94427.6" + attribute \src "libresoc.v:94169.3-94223.6" wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:93713.3-93767.6" + attribute \src "libresoc.v:93509.3-93563.6" wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93768.3-93822.6" + attribute \src "libresoc.v:93564.3-93618.6" wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:93438.3-93492.6" + attribute \src "libresoc.v:93234.3-93288.6" wire width 3 $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:93493.3-93547.6" + attribute \src "libresoc.v:93289.3-93343.6" wire width 3 $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:93548.3-93602.6" + attribute \src "libresoc.v:93344.3-93398.6" wire width 3 $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:93658.3-93712.6" + attribute \src "libresoc.v:93454.3-93508.6" wire width 3 $1\dec31_dec_sub11_sv_out2[2:0] - attribute \src "libresoc.v:93603.3-93657.6" + attribute \src "libresoc.v:93399.3-93453.6" wire width 3 $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:93933.3-93987.6" + attribute \src "libresoc.v:93729.3-93783.6" wire width 2 $1\dec31_dec_sub11_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -145704,28 +145500,28 @@ module \dec31_dec_sub11 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub11_upd - attribute \src "libresoc.v:92925.7-92925.15" + attribute \src "libresoc.v:92721.7-92721.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:92925.7-92925.20" - process $proc$libresoc.v:92925$3936 + attribute \src "libresoc.v:92721.7-92721.20" + process $proc$libresoc.v:92721$3936 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:93273.3-93327.6" - process $proc$libresoc.v:93273$3903 + attribute \src "libresoc.v:93069.3-93123.6" + process $proc$libresoc.v:93069$3903 assign { } { } assign { } { } assign $0\dec31_dec_sub11_function_unit[13:0] $1\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:93274.5-93274.29" + attribute \src "libresoc.v:93070.5-93070.29" switch \initial - attribute \src "libresoc.v:93274.9-93274.17" + attribute \src "libresoc.v:93070.9-93070.17" case 1'1 case end @@ -145801,14 +145597,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[13:0] end - attribute \src "libresoc.v:93328.3-93382.6" - process $proc$libresoc.v:93328$3904 + attribute \src "libresoc.v:93124.3-93178.6" + process $proc$libresoc.v:93124$3904 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:93329.5-93329.29" + attribute \src "libresoc.v:93125.5-93125.29" switch \initial - attribute \src "libresoc.v:93329.9-93329.17" + attribute \src "libresoc.v:93125.9-93125.17" case 1'1 case end @@ -145884,14 +145680,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:93383.3-93437.6" - process $proc$libresoc.v:93383$3905 + attribute \src "libresoc.v:93179.3-93233.6" + process $proc$libresoc.v:93179$3905 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:93384.5-93384.29" + attribute \src "libresoc.v:93180.5-93180.29" switch \initial - attribute \src "libresoc.v:93384.9-93384.17" + attribute \src "libresoc.v:93180.9-93180.17" case 1'1 case end @@ -145967,14 +145763,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:93438.3-93492.6" - process $proc$libresoc.v:93438$3906 + attribute \src "libresoc.v:93234.3-93288.6" + process $proc$libresoc.v:93234$3906 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:93439.5-93439.29" + attribute \src "libresoc.v:93235.5-93235.29" switch \initial - attribute \src "libresoc.v:93439.9-93439.17" + attribute \src "libresoc.v:93235.9-93235.17" case 1'1 case end @@ -146050,14 +145846,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0] end - attribute \src "libresoc.v:93493.3-93547.6" - process $proc$libresoc.v:93493$3907 + attribute \src "libresoc.v:93289.3-93343.6" + process $proc$libresoc.v:93289$3907 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:93494.5-93494.29" + attribute \src "libresoc.v:93290.5-93290.29" switch \initial - attribute \src "libresoc.v:93494.9-93494.17" + attribute \src "libresoc.v:93290.9-93290.17" case 1'1 case end @@ -146133,14 +145929,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0] end - attribute \src "libresoc.v:93548.3-93602.6" - process $proc$libresoc.v:93548$3908 + attribute \src "libresoc.v:93344.3-93398.6" + process $proc$libresoc.v:93344$3908 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:93549.5-93549.29" + attribute \src "libresoc.v:93345.5-93345.29" switch \initial - attribute \src "libresoc.v:93549.9-93549.17" + attribute \src "libresoc.v:93345.9-93345.17" case 1'1 case end @@ -146216,14 +146012,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0] end - attribute \src "libresoc.v:93603.3-93657.6" - process $proc$libresoc.v:93603$3909 + attribute \src "libresoc.v:93399.3-93453.6" + process $proc$libresoc.v:93399$3909 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:93604.5-93604.29" + attribute \src "libresoc.v:93400.5-93400.29" switch \initial - attribute \src "libresoc.v:93604.9-93604.17" + attribute \src "libresoc.v:93400.9-93400.17" case 1'1 case end @@ -146299,14 +146095,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0] end - attribute \src "libresoc.v:93658.3-93712.6" - process $proc$libresoc.v:93658$3910 + attribute \src "libresoc.v:93454.3-93508.6" + process $proc$libresoc.v:93454$3910 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out2[2:0] $1\dec31_dec_sub11_sv_out2[2:0] - attribute \src "libresoc.v:93659.5-93659.29" + attribute \src "libresoc.v:93455.5-93455.29" switch \initial - attribute \src "libresoc.v:93659.9-93659.17" + attribute \src "libresoc.v:93455.9-93455.17" case 1'1 case end @@ -146382,14 +146178,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_out2 $0\dec31_dec_sub11_sv_out2[2:0] end - attribute \src "libresoc.v:93713.3-93767.6" - process $proc$libresoc.v:93713$3911 + attribute \src "libresoc.v:93509.3-93563.6" + process $proc$libresoc.v:93509$3911 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93714.5-93714.29" + attribute \src "libresoc.v:93510.5-93510.29" switch \initial - attribute \src "libresoc.v:93714.9-93714.17" + attribute \src "libresoc.v:93510.9-93510.17" case 1'1 case end @@ -146465,14 +146261,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0] end - attribute \src "libresoc.v:93768.3-93822.6" - process $proc$libresoc.v:93768$3912 + attribute \src "libresoc.v:93564.3-93618.6" + process $proc$libresoc.v:93564$3912 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:93769.5-93769.29" + attribute \src "libresoc.v:93565.5-93565.29" switch \initial - attribute \src "libresoc.v:93769.9-93769.17" + attribute \src "libresoc.v:93565.9-93565.17" case 1'1 case end @@ -146548,14 +146344,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0] end - attribute \src "libresoc.v:93823.3-93877.6" - process $proc$libresoc.v:93823$3913 + attribute \src "libresoc.v:93619.3-93673.6" + process $proc$libresoc.v:93619$3913 assign { } { } assign { } { } assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:93824.5-93824.29" + attribute \src "libresoc.v:93620.5-93620.29" switch \initial - attribute \src "libresoc.v:93824.9-93824.17" + attribute \src "libresoc.v:93620.9-93620.17" case 1'1 case end @@ -146631,14 +146427,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \src "libresoc.v:93878.3-93932.6" - process $proc$libresoc.v:93878$3914 + attribute \src "libresoc.v:93674.3-93728.6" + process $proc$libresoc.v:93674$3914 assign { } { } assign { } { } assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:93879.5-93879.29" + attribute \src "libresoc.v:93675.5-93675.29" switch \initial - attribute \src "libresoc.v:93879.9-93879.17" + attribute \src "libresoc.v:93675.9-93675.17" case 1'1 case end @@ -146714,14 +146510,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:93933.3-93987.6" - process $proc$libresoc.v:93933$3915 + attribute \src "libresoc.v:93729.3-93783.6" + process $proc$libresoc.v:93729$3915 assign { } { } assign { } { } assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:93934.5-93934.29" + attribute \src "libresoc.v:93730.5-93730.29" switch \initial - attribute \src "libresoc.v:93934.9-93934.17" + attribute \src "libresoc.v:93730.9-93730.17" case 1'1 case end @@ -146797,14 +146593,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \src "libresoc.v:93988.3-94042.6" - process $proc$libresoc.v:93988$3916 + attribute \src "libresoc.v:93784.3-93838.6" + process $proc$libresoc.v:93784$3916 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:93989.5-93989.29" + attribute \src "libresoc.v:93785.5-93785.29" switch \initial - attribute \src "libresoc.v:93989.9-93989.17" + attribute \src "libresoc.v:93785.9-93785.17" case 1'1 case end @@ -146880,14 +146676,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:94043.3-94097.6" - process $proc$libresoc.v:94043$3917 + attribute \src "libresoc.v:93839.3-93893.6" + process $proc$libresoc.v:93839$3917 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:94044.5-94044.29" + attribute \src "libresoc.v:93840.5-93840.29" switch \initial - attribute \src "libresoc.v:94044.9-94044.17" + attribute \src "libresoc.v:93840.9-93840.17" case 1'1 case end @@ -146963,14 +146759,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \src "libresoc.v:94098.3-94152.6" - process $proc$libresoc.v:94098$3918 + attribute \src "libresoc.v:93894.3-93948.6" + process $proc$libresoc.v:93894$3918 assign { } { } assign { } { } assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:94099.5-94099.29" + attribute \src "libresoc.v:93895.5-93895.29" switch \initial - attribute \src "libresoc.v:94099.9-94099.17" + attribute \src "libresoc.v:93895.9-93895.17" case 1'1 case end @@ -147046,14 +146842,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \src "libresoc.v:94153.3-94207.6" - process $proc$libresoc.v:94153$3919 + attribute \src "libresoc.v:93949.3-94003.6" + process $proc$libresoc.v:93949$3919 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:94154.5-94154.29" + attribute \src "libresoc.v:93950.5-93950.29" switch \initial - attribute \src "libresoc.v:94154.9-94154.17" + attribute \src "libresoc.v:93950.9-93950.17" case 1'1 case end @@ -147129,14 +146925,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "libresoc.v:94208.3-94262.6" - process $proc$libresoc.v:94208$3920 + attribute \src "libresoc.v:94004.3-94058.6" + process $proc$libresoc.v:94004$3920 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:94209.5-94209.29" + attribute \src "libresoc.v:94005.5-94005.29" switch \initial - attribute \src "libresoc.v:94209.9-94209.17" + attribute \src "libresoc.v:94005.9-94005.17" case 1'1 case end @@ -147212,14 +147008,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end - attribute \src "libresoc.v:94263.3-94317.6" - process $proc$libresoc.v:94263$3921 + attribute \src "libresoc.v:94059.3-94113.6" + process $proc$libresoc.v:94059$3921 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:94264.5-94264.29" + attribute \src "libresoc.v:94060.5-94060.29" switch \initial - attribute \src "libresoc.v:94264.9-94264.17" + attribute \src "libresoc.v:94060.9-94060.17" case 1'1 case end @@ -147295,14 +147091,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end - attribute \src "libresoc.v:94318.3-94372.6" - process $proc$libresoc.v:94318$3922 + attribute \src "libresoc.v:94114.3-94168.6" + process $proc$libresoc.v:94114$3922 assign { } { } assign { } { } assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:94319.5-94319.29" + attribute \src "libresoc.v:94115.5-94115.29" switch \initial - attribute \src "libresoc.v:94319.9-94319.17" + attribute \src "libresoc.v:94115.9-94115.17" case 1'1 case end @@ -147378,14 +147174,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end - attribute \src "libresoc.v:94373.3-94427.6" - process $proc$libresoc.v:94373$3923 + attribute \src "libresoc.v:94169.3-94223.6" + process $proc$libresoc.v:94169$3923 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:94374.5-94374.29" + attribute \src "libresoc.v:94170.5-94170.29" switch \initial - attribute \src "libresoc.v:94374.9-94374.17" + attribute \src "libresoc.v:94170.9-94170.17" case 1'1 case end @@ -147461,14 +147257,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end - attribute \src "libresoc.v:94428.3-94482.6" - process $proc$libresoc.v:94428$3924 + attribute \src "libresoc.v:94224.3-94278.6" + process $proc$libresoc.v:94224$3924 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:94429.5-94429.29" + attribute \src "libresoc.v:94225.5-94225.29" switch \initial - attribute \src "libresoc.v:94429.9-94429.17" + attribute \src "libresoc.v:94225.9-94225.17" case 1'1 case end @@ -147544,14 +147340,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end - attribute \src "libresoc.v:94483.3-94537.6" - process $proc$libresoc.v:94483$3925 + attribute \src "libresoc.v:94279.3-94333.6" + process $proc$libresoc.v:94279$3925 assign { } { } assign { } { } assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:94484.5-94484.29" + attribute \src "libresoc.v:94280.5-94280.29" switch \initial - attribute \src "libresoc.v:94484.9-94484.17" + attribute \src "libresoc.v:94280.9-94280.17" case 1'1 case end @@ -147627,14 +147423,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "libresoc.v:94538.3-94592.6" - process $proc$libresoc.v:94538$3926 + attribute \src "libresoc.v:94334.3-94388.6" + process $proc$libresoc.v:94334$3926 assign { } { } assign { } { } assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:94539.5-94539.29" + attribute \src "libresoc.v:94335.5-94335.29" switch \initial - attribute \src "libresoc.v:94539.9-94539.17" + attribute \src "libresoc.v:94335.9-94335.17" case 1'1 case end @@ -147710,14 +147506,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:94593.3-94647.6" - process $proc$libresoc.v:94593$3927 + attribute \src "libresoc.v:94389.3-94443.6" + process $proc$libresoc.v:94389$3927 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:94594.5-94594.29" + attribute \src "libresoc.v:94390.5-94390.29" switch \initial - attribute \src "libresoc.v:94594.9-94594.17" + attribute \src "libresoc.v:94390.9-94390.17" case 1'1 case end @@ -147793,14 +147589,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "libresoc.v:94648.3-94702.6" - process $proc$libresoc.v:94648$3928 + attribute \src "libresoc.v:94444.3-94498.6" + process $proc$libresoc.v:94444$3928 assign { } { } assign { } { } assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:94649.5-94649.29" + attribute \src "libresoc.v:94445.5-94445.29" switch \initial - attribute \src "libresoc.v:94649.9-94649.17" + attribute \src "libresoc.v:94445.9-94445.17" case 1'1 case end @@ -147876,14 +147672,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "libresoc.v:94703.3-94757.6" - process $proc$libresoc.v:94703$3929 + attribute \src "libresoc.v:94499.3-94553.6" + process $proc$libresoc.v:94499$3929 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:94704.5-94704.29" + attribute \src "libresoc.v:94500.5-94500.29" switch \initial - attribute \src "libresoc.v:94704.9-94704.17" + attribute \src "libresoc.v:94500.9-94500.17" case 1'1 case end @@ -147959,14 +147755,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "libresoc.v:94758.3-94812.6" - process $proc$libresoc.v:94758$3930 + attribute \src "libresoc.v:94554.3-94608.6" + process $proc$libresoc.v:94554$3930 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94759.5-94759.29" + attribute \src "libresoc.v:94555.5-94555.29" switch \initial - attribute \src "libresoc.v:94759.9-94759.17" + attribute \src "libresoc.v:94555.9-94555.17" case 1'1 case end @@ -148042,14 +147838,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0] end - attribute \src "libresoc.v:94813.3-94867.6" - process $proc$libresoc.v:94813$3931 + attribute \src "libresoc.v:94609.3-94663.6" + process $proc$libresoc.v:94609$3931 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:94814.5-94814.29" + attribute \src "libresoc.v:94610.5-94610.29" switch \initial - attribute \src "libresoc.v:94814.9-94814.17" + attribute \src "libresoc.v:94610.9-94610.17" case 1'1 case end @@ -148125,14 +147921,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0] end - attribute \src "libresoc.v:94868.3-94922.6" - process $proc$libresoc.v:94868$3932 + attribute \src "libresoc.v:94664.3-94718.6" + process $proc$libresoc.v:94664$3932 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:94869.5-94869.29" + attribute \src "libresoc.v:94665.5-94665.29" switch \initial - attribute \src "libresoc.v:94869.9-94869.17" + attribute \src "libresoc.v:94665.9-94665.17" case 1'1 case end @@ -148208,14 +148004,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end - attribute \src "libresoc.v:94923.3-94977.6" - process $proc$libresoc.v:94923$3933 + attribute \src "libresoc.v:94719.3-94773.6" + process $proc$libresoc.v:94719$3933 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:94924.5-94924.29" + attribute \src "libresoc.v:94720.5-94720.29" switch \initial - attribute \src "libresoc.v:94924.9-94924.17" + attribute \src "libresoc.v:94720.9-94720.17" case 1'1 case end @@ -148291,14 +148087,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:94978.3-95032.6" - process $proc$libresoc.v:94978$3934 + attribute \src "libresoc.v:94774.3-94828.6" + process $proc$libresoc.v:94774$3934 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:94979.5-94979.29" + attribute \src "libresoc.v:94775.5-94775.29" switch \initial - attribute \src "libresoc.v:94979.9-94979.17" + attribute \src "libresoc.v:94775.9-94775.17" case 1'1 case end @@ -148374,14 +148170,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end - attribute \src "libresoc.v:95033.3-95087.6" - process $proc$libresoc.v:95033$3935 + attribute \src "libresoc.v:94829.3-94883.6" + process $proc$libresoc.v:94829$3935 assign { } { } assign { } { } assign $0\dec31_dec_sub11_out_sel[2:0] $1\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:95034.5-95034.29" + attribute \src "libresoc.v:94830.5-94830.29" switch \initial - attribute \src "libresoc.v:95034.9-95034.17" + attribute \src "libresoc.v:94830.9-94830.17" case 1'1 case end @@ -148459,144 +148255,144 @@ module \dec31_dec_sub11 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:95093.1-98842.10" +attribute \src "libresoc.v:94889.1-98638.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" module \dec31_dec_sub15 - attribute \src "libresoc.v:98223.3-98325.6" + attribute \src "libresoc.v:98019.3-98121.6" wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:98326.3-98428.6" + attribute \src "libresoc.v:98122.3-98224.6" wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:96987.3-97089.6" + attribute \src "libresoc.v:96783.3-96885.6" wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:97399.3-97501.6" + attribute \src "libresoc.v:97195.3-97297.6" wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:95545.3-95647.6" + attribute \src "libresoc.v:95341.3-95443.6" wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:95648.3-95750.6" + attribute \src "libresoc.v:95444.3-95546.6" wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:96884.3-96986.6" + attribute \src "libresoc.v:96680.3-96782.6" wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:97296.3-97398.6" + attribute \src "libresoc.v:97092.3-97194.6" wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:97708.3-97810.6" + attribute \src "libresoc.v:97504.3-97606.6" wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:95442.3-95544.6" + attribute \src "libresoc.v:95238.3-95340.6" wire width 14 $0\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:98429.3-98531.6" + attribute \src "libresoc.v:98225.3-98327.6" wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:98532.3-98634.6" + attribute \src "libresoc.v:98328.3-98430.6" wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:98635.3-98737.6" + attribute \src "libresoc.v:98431.3-98533.6" wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:96575.3-96677.6" + attribute \src "libresoc.v:96371.3-96473.6" wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:97090.3-97192.6" + attribute \src "libresoc.v:96886.3-96988.6" wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:97193.3-97295.6" + attribute \src "libresoc.v:96989.3-97091.6" wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:97811.3-97913.6" + attribute \src "libresoc.v:97607.3-97709.6" wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:96472.3-96574.6" + attribute \src "libresoc.v:96268.3-96370.6" wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:98017.3-98119.6" + attribute \src "libresoc.v:97813.3-97915.6" wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:98738.3-98840.6" + attribute \src "libresoc.v:98534.3-98636.6" wire width 3 $0\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:96781.3-96883.6" + attribute \src "libresoc.v:96577.3-96679.6" wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:97605.3-97707.6" + attribute \src "libresoc.v:97401.3-97503.6" wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:98120.3-98222.6" + attribute \src "libresoc.v:97916.3-98018.6" wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:97914.3-98016.6" + attribute \src "libresoc.v:97710.3-97812.6" wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:97502.3-97604.6" + attribute \src "libresoc.v:97298.3-97400.6" wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:96266.3-96368.6" + attribute \src "libresoc.v:96062.3-96164.6" wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:96369.3-96471.6" + attribute \src "libresoc.v:96165.3-96267.6" wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95751.3-95853.6" + attribute \src "libresoc.v:95547.3-95649.6" wire width 3 $0\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95854.3-95956.6" + attribute \src "libresoc.v:95650.3-95752.6" wire width 3 $0\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:95957.3-96059.6" + attribute \src "libresoc.v:95753.3-95855.6" wire width 3 $0\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:96163.3-96265.6" + attribute \src "libresoc.v:95959.3-96061.6" wire width 3 $0\dec31_dec_sub15_sv_out2[2:0] - attribute \src "libresoc.v:96060.3-96162.6" + attribute \src "libresoc.v:95856.3-95958.6" wire width 3 $0\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:96678.3-96780.6" + attribute \src "libresoc.v:96474.3-96576.6" wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:95094.7-95094.20" + attribute \src "libresoc.v:94890.7-94890.20" wire $0\initial[0:0] - attribute \src "libresoc.v:98223.3-98325.6" + attribute \src "libresoc.v:98019.3-98121.6" wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:98326.3-98428.6" + attribute \src "libresoc.v:98122.3-98224.6" wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:96987.3-97089.6" + attribute \src "libresoc.v:96783.3-96885.6" wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:97399.3-97501.6" + attribute \src "libresoc.v:97195.3-97297.6" wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:95545.3-95647.6" + attribute \src "libresoc.v:95341.3-95443.6" wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:95648.3-95750.6" + attribute \src "libresoc.v:95444.3-95546.6" wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:96884.3-96986.6" + attribute \src "libresoc.v:96680.3-96782.6" wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:97296.3-97398.6" + attribute \src "libresoc.v:97092.3-97194.6" wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:97708.3-97810.6" + attribute \src "libresoc.v:97504.3-97606.6" wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:95442.3-95544.6" + attribute \src "libresoc.v:95238.3-95340.6" wire width 14 $1\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:98429.3-98531.6" + attribute \src "libresoc.v:98225.3-98327.6" wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:98532.3-98634.6" + attribute \src "libresoc.v:98328.3-98430.6" wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:98635.3-98737.6" + attribute \src "libresoc.v:98431.3-98533.6" wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:96575.3-96677.6" + attribute \src "libresoc.v:96371.3-96473.6" wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:97090.3-97192.6" + attribute \src "libresoc.v:96886.3-96988.6" wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:97193.3-97295.6" + attribute \src "libresoc.v:96989.3-97091.6" wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:97811.3-97913.6" + attribute \src "libresoc.v:97607.3-97709.6" wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:96472.3-96574.6" + attribute \src "libresoc.v:96268.3-96370.6" wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:98017.3-98119.6" + attribute \src "libresoc.v:97813.3-97915.6" wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:98738.3-98840.6" + attribute \src "libresoc.v:98534.3-98636.6" wire width 3 $1\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:96781.3-96883.6" + attribute \src "libresoc.v:96577.3-96679.6" wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:97605.3-97707.6" + attribute \src "libresoc.v:97401.3-97503.6" wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:98120.3-98222.6" + attribute \src "libresoc.v:97916.3-98018.6" wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:97914.3-98016.6" + attribute \src "libresoc.v:97710.3-97812.6" wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:97502.3-97604.6" + attribute \src "libresoc.v:97298.3-97400.6" wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:96266.3-96368.6" + attribute \src "libresoc.v:96062.3-96164.6" wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:96369.3-96471.6" + attribute \src "libresoc.v:96165.3-96267.6" wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95751.3-95853.6" + attribute \src "libresoc.v:95547.3-95649.6" wire width 3 $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95854.3-95956.6" + attribute \src "libresoc.v:95650.3-95752.6" wire width 3 $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:95957.3-96059.6" + attribute \src "libresoc.v:95753.3-95855.6" wire width 3 $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:96163.3-96265.6" + attribute \src "libresoc.v:95959.3-96061.6" wire width 3 $1\dec31_dec_sub15_sv_out2[2:0] - attribute \src "libresoc.v:96060.3-96162.6" + attribute \src "libresoc.v:95856.3-95958.6" wire width 3 $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:96678.3-96780.6" + attribute \src "libresoc.v:96474.3-96576.6" wire width 2 $1\dec31_dec_sub15_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -148908,28 +148704,28 @@ module \dec31_dec_sub15 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub15_upd - attribute \src "libresoc.v:95094.7-95094.15" + attribute \src "libresoc.v:94890.7-94890.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:95094.7-95094.20" - process $proc$libresoc.v:95094$3970 + attribute \src "libresoc.v:94890.7-94890.20" + process $proc$libresoc.v:94890$3970 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:95442.3-95544.6" - process $proc$libresoc.v:95442$3937 + attribute \src "libresoc.v:95238.3-95340.6" + process $proc$libresoc.v:95238$3937 assign { } { } assign { } { } assign $0\dec31_dec_sub15_function_unit[13:0] $1\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:95443.5-95443.29" + attribute \src "libresoc.v:95239.5-95239.29" switch \initial - attribute \src "libresoc.v:95443.9-95443.17" + attribute \src "libresoc.v:95239.9-95239.17" case 1'1 case end @@ -149069,14 +148865,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[13:0] end - attribute \src "libresoc.v:95545.3-95647.6" - process $proc$libresoc.v:95545$3938 + attribute \src "libresoc.v:95341.3-95443.6" + process $proc$libresoc.v:95341$3938 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:95546.5-95546.29" + attribute \src "libresoc.v:95342.5-95342.29" switch \initial - attribute \src "libresoc.v:95546.9-95546.17" + attribute \src "libresoc.v:95342.9-95342.17" case 1'1 case end @@ -149216,14 +149012,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:95648.3-95750.6" - process $proc$libresoc.v:95648$3939 + attribute \src "libresoc.v:95444.3-95546.6" + process $proc$libresoc.v:95444$3939 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:95649.5-95649.29" + attribute \src "libresoc.v:95445.5-95445.29" switch \initial - attribute \src "libresoc.v:95649.9-95649.17" + attribute \src "libresoc.v:95445.9-95445.17" case 1'1 case end @@ -149363,14 +149159,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] end - attribute \src "libresoc.v:95751.3-95853.6" - process $proc$libresoc.v:95751$3940 + attribute \src "libresoc.v:95547.3-95649.6" + process $proc$libresoc.v:95547$3940 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95752.5-95752.29" + attribute \src "libresoc.v:95548.5-95548.29" switch \initial - attribute \src "libresoc.v:95752.9-95752.17" + attribute \src "libresoc.v:95548.9-95548.17" case 1'1 case end @@ -149510,14 +149306,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0] end - attribute \src "libresoc.v:95854.3-95956.6" - process $proc$libresoc.v:95854$3941 + attribute \src "libresoc.v:95650.3-95752.6" + process $proc$libresoc.v:95650$3941 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:95855.5-95855.29" + attribute \src "libresoc.v:95651.5-95651.29" switch \initial - attribute \src "libresoc.v:95855.9-95855.17" + attribute \src "libresoc.v:95651.9-95651.17" case 1'1 case end @@ -149657,14 +149453,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0] end - attribute \src "libresoc.v:95957.3-96059.6" - process $proc$libresoc.v:95957$3942 + attribute \src "libresoc.v:95753.3-95855.6" + process $proc$libresoc.v:95753$3942 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:95958.5-95958.29" + attribute \src "libresoc.v:95754.5-95754.29" switch \initial - attribute \src "libresoc.v:95958.9-95958.17" + attribute \src "libresoc.v:95754.9-95754.17" case 1'1 case end @@ -149804,14 +149600,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0] end - attribute \src "libresoc.v:96060.3-96162.6" - process $proc$libresoc.v:96060$3943 + attribute \src "libresoc.v:95856.3-95958.6" + process $proc$libresoc.v:95856$3943 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:96061.5-96061.29" + attribute \src "libresoc.v:95857.5-95857.29" switch \initial - attribute \src "libresoc.v:96061.9-96061.17" + attribute \src "libresoc.v:95857.9-95857.17" case 1'1 case end @@ -149951,14 +149747,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0] end - attribute \src "libresoc.v:96163.3-96265.6" - process $proc$libresoc.v:96163$3944 + attribute \src "libresoc.v:95959.3-96061.6" + process $proc$libresoc.v:95959$3944 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out2[2:0] $1\dec31_dec_sub15_sv_out2[2:0] - attribute \src "libresoc.v:96164.5-96164.29" + attribute \src "libresoc.v:95960.5-95960.29" switch \initial - attribute \src "libresoc.v:96164.9-96164.17" + attribute \src "libresoc.v:95960.9-95960.17" case 1'1 case end @@ -150098,14 +149894,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_out2 $0\dec31_dec_sub15_sv_out2[2:0] end - attribute \src "libresoc.v:96266.3-96368.6" - process $proc$libresoc.v:96266$3945 + attribute \src "libresoc.v:96062.3-96164.6" + process $proc$libresoc.v:96062$3945 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:96267.5-96267.29" + attribute \src "libresoc.v:96063.5-96063.29" switch \initial - attribute \src "libresoc.v:96267.9-96267.17" + attribute \src "libresoc.v:96063.9-96063.17" case 1'1 case end @@ -150245,14 +150041,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0] end - attribute \src "libresoc.v:96369.3-96471.6" - process $proc$libresoc.v:96369$3946 + attribute \src "libresoc.v:96165.3-96267.6" + process $proc$libresoc.v:96165$3946 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:96370.5-96370.29" + attribute \src "libresoc.v:96166.5-96166.29" switch \initial - attribute \src "libresoc.v:96370.9-96370.17" + attribute \src "libresoc.v:96166.9-96166.17" case 1'1 case end @@ -150392,14 +150188,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0] end - attribute \src "libresoc.v:96472.3-96574.6" - process $proc$libresoc.v:96472$3947 + attribute \src "libresoc.v:96268.3-96370.6" + process $proc$libresoc.v:96268$3947 assign { } { } assign { } { } assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:96473.5-96473.29" + attribute \src "libresoc.v:96269.5-96269.29" switch \initial - attribute \src "libresoc.v:96473.9-96473.17" + attribute \src "libresoc.v:96269.9-96269.17" case 1'1 case end @@ -150539,14 +150335,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "libresoc.v:96575.3-96677.6" - process $proc$libresoc.v:96575$3948 + attribute \src "libresoc.v:96371.3-96473.6" + process $proc$libresoc.v:96371$3948 assign { } { } assign { } { } assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:96576.5-96576.29" + attribute \src "libresoc.v:96372.5-96372.29" switch \initial - attribute \src "libresoc.v:96576.9-96576.17" + attribute \src "libresoc.v:96372.9-96372.17" case 1'1 case end @@ -150686,14 +150482,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "libresoc.v:96678.3-96780.6" - process $proc$libresoc.v:96678$3949 + attribute \src "libresoc.v:96474.3-96576.6" + process $proc$libresoc.v:96474$3949 assign { } { } assign { } { } assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:96679.5-96679.29" + attribute \src "libresoc.v:96475.5-96475.29" switch \initial - attribute \src "libresoc.v:96679.9-96679.17" + attribute \src "libresoc.v:96475.9-96475.17" case 1'1 case end @@ -150833,14 +150629,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "libresoc.v:96781.3-96883.6" - process $proc$libresoc.v:96781$3950 + attribute \src "libresoc.v:96577.3-96679.6" + process $proc$libresoc.v:96577$3950 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:96782.5-96782.29" + attribute \src "libresoc.v:96578.5-96578.29" switch \initial - attribute \src "libresoc.v:96782.9-96782.17" + attribute \src "libresoc.v:96578.9-96578.17" case 1'1 case end @@ -150980,14 +150776,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end - attribute \src "libresoc.v:96884.3-96986.6" - process $proc$libresoc.v:96884$3951 + attribute \src "libresoc.v:96680.3-96782.6" + process $proc$libresoc.v:96680$3951 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:96885.5-96885.29" + attribute \src "libresoc.v:96681.5-96681.29" switch \initial - attribute \src "libresoc.v:96885.9-96885.17" + attribute \src "libresoc.v:96681.9-96681.17" case 1'1 case end @@ -151127,14 +150923,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "libresoc.v:96987.3-97089.6" - process $proc$libresoc.v:96987$3952 + attribute \src "libresoc.v:96783.3-96885.6" + process $proc$libresoc.v:96783$3952 assign { } { } assign { } { } assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:96988.5-96988.29" + attribute \src "libresoc.v:96784.5-96784.29" switch \initial - attribute \src "libresoc.v:96988.9-96988.17" + attribute \src "libresoc.v:96784.9-96784.17" case 1'1 case end @@ -151274,14 +151070,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "libresoc.v:97090.3-97192.6" - process $proc$libresoc.v:97090$3953 + attribute \src "libresoc.v:96886.3-96988.6" + process $proc$libresoc.v:96886$3953 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:97091.5-97091.29" + attribute \src "libresoc.v:96887.5-96887.29" switch \initial - attribute \src "libresoc.v:97091.9-97091.17" + attribute \src "libresoc.v:96887.9-96887.17" case 1'1 case end @@ -151421,14 +151217,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "libresoc.v:97193.3-97295.6" - process $proc$libresoc.v:97193$3954 + attribute \src "libresoc.v:96989.3-97091.6" + process $proc$libresoc.v:96989$3954 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:97194.5-97194.29" + attribute \src "libresoc.v:96990.5-96990.29" switch \initial - attribute \src "libresoc.v:97194.9-97194.17" + attribute \src "libresoc.v:96990.9-96990.17" case 1'1 case end @@ -151568,14 +151364,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "libresoc.v:97296.3-97398.6" - process $proc$libresoc.v:97296$3955 + attribute \src "libresoc.v:97092.3-97194.6" + process $proc$libresoc.v:97092$3955 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:97297.5-97297.29" + attribute \src "libresoc.v:97093.5-97093.29" switch \initial - attribute \src "libresoc.v:97297.9-97297.17" + attribute \src "libresoc.v:97093.9-97093.17" case 1'1 case end @@ -151715,14 +151511,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "libresoc.v:97399.3-97501.6" - process $proc$libresoc.v:97399$3956 + attribute \src "libresoc.v:97195.3-97297.6" + process $proc$libresoc.v:97195$3956 assign { } { } assign { } { } assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:97400.5-97400.29" + attribute \src "libresoc.v:97196.5-97196.29" switch \initial - attribute \src "libresoc.v:97400.9-97400.17" + attribute \src "libresoc.v:97196.9-97196.17" case 1'1 case end @@ -151862,14 +151658,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "libresoc.v:97502.3-97604.6" - process $proc$libresoc.v:97502$3957 + attribute \src "libresoc.v:97298.3-97400.6" + process $proc$libresoc.v:97298$3957 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:97503.5-97503.29" + attribute \src "libresoc.v:97299.5-97299.29" switch \initial - attribute \src "libresoc.v:97503.9-97503.17" + attribute \src "libresoc.v:97299.9-97299.17" case 1'1 case end @@ -152009,14 +151805,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "libresoc.v:97605.3-97707.6" - process $proc$libresoc.v:97605$3958 + attribute \src "libresoc.v:97401.3-97503.6" + process $proc$libresoc.v:97401$3958 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:97606.5-97606.29" + attribute \src "libresoc.v:97402.5-97402.29" switch \initial - attribute \src "libresoc.v:97606.9-97606.17" + attribute \src "libresoc.v:97402.9-97402.17" case 1'1 case end @@ -152156,14 +151952,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "libresoc.v:97708.3-97810.6" - process $proc$libresoc.v:97708$3959 + attribute \src "libresoc.v:97504.3-97606.6" + process $proc$libresoc.v:97504$3959 assign { } { } assign { } { } assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:97709.5-97709.29" + attribute \src "libresoc.v:97505.5-97505.29" switch \initial - attribute \src "libresoc.v:97709.9-97709.17" + attribute \src "libresoc.v:97505.9-97505.17" case 1'1 case end @@ -152303,14 +152099,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "libresoc.v:97811.3-97913.6" - process $proc$libresoc.v:97811$3960 + attribute \src "libresoc.v:97607.3-97709.6" + process $proc$libresoc.v:97607$3960 assign { } { } assign { } { } assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:97812.5-97812.29" + attribute \src "libresoc.v:97608.5-97608.29" switch \initial - attribute \src "libresoc.v:97812.9-97812.17" + attribute \src "libresoc.v:97608.9-97608.17" case 1'1 case end @@ -152450,14 +152246,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "libresoc.v:97914.3-98016.6" - process $proc$libresoc.v:97914$3961 + attribute \src "libresoc.v:97710.3-97812.6" + process $proc$libresoc.v:97710$3961 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:97915.5-97915.29" + attribute \src "libresoc.v:97711.5-97711.29" switch \initial - attribute \src "libresoc.v:97915.9-97915.17" + attribute \src "libresoc.v:97711.9-97711.17" case 1'1 case end @@ -152597,14 +152393,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - attribute \src "libresoc.v:98017.3-98119.6" - process $proc$libresoc.v:98017$3962 + attribute \src "libresoc.v:97813.3-97915.6" + process $proc$libresoc.v:97813$3962 assign { } { } assign { } { } assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:98018.5-98018.29" + attribute \src "libresoc.v:97814.5-97814.29" switch \initial - attribute \src "libresoc.v:98018.9-98018.17" + attribute \src "libresoc.v:97814.9-97814.17" case 1'1 case end @@ -152744,14 +152540,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "libresoc.v:98120.3-98222.6" - process $proc$libresoc.v:98120$3963 + attribute \src "libresoc.v:97916.3-98018.6" + process $proc$libresoc.v:97916$3963 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:98121.5-98121.29" + attribute \src "libresoc.v:97917.5-97917.29" switch \initial - attribute \src "libresoc.v:98121.9-98121.17" + attribute \src "libresoc.v:97917.9-97917.17" case 1'1 case end @@ -152891,14 +152687,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "libresoc.v:98223.3-98325.6" - process $proc$libresoc.v:98223$3964 + attribute \src "libresoc.v:98019.3-98121.6" + process $proc$libresoc.v:98019$3964 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:98224.5-98224.29" + attribute \src "libresoc.v:98020.5-98020.29" switch \initial - attribute \src "libresoc.v:98224.9-98224.17" + attribute \src "libresoc.v:98020.9-98020.17" case 1'1 case end @@ -153038,14 +152834,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0] end - attribute \src "libresoc.v:98326.3-98428.6" - process $proc$libresoc.v:98326$3965 + attribute \src "libresoc.v:98122.3-98224.6" + process $proc$libresoc.v:98122$3965 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:98327.5-98327.29" + attribute \src "libresoc.v:98123.5-98123.29" switch \initial - attribute \src "libresoc.v:98327.9-98327.17" + attribute \src "libresoc.v:98123.9-98123.17" case 1'1 case end @@ -153185,14 +152981,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0] end - attribute \src "libresoc.v:98429.3-98531.6" - process $proc$libresoc.v:98429$3966 + attribute \src "libresoc.v:98225.3-98327.6" + process $proc$libresoc.v:98225$3966 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:98430.5-98430.29" + attribute \src "libresoc.v:98226.5-98226.29" switch \initial - attribute \src "libresoc.v:98430.9-98430.17" + attribute \src "libresoc.v:98226.9-98226.17" case 1'1 case end @@ -153332,14 +153128,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "libresoc.v:98532.3-98634.6" - process $proc$libresoc.v:98532$3967 + attribute \src "libresoc.v:98328.3-98430.6" + process $proc$libresoc.v:98328$3967 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:98533.5-98533.29" + attribute \src "libresoc.v:98329.5-98329.29" switch \initial - attribute \src "libresoc.v:98533.9-98533.17" + attribute \src "libresoc.v:98329.9-98329.17" case 1'1 case end @@ -153479,14 +153275,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "libresoc.v:98635.3-98737.6" - process $proc$libresoc.v:98635$3968 + attribute \src "libresoc.v:98431.3-98533.6" + process $proc$libresoc.v:98431$3968 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:98636.5-98636.29" + attribute \src "libresoc.v:98432.5-98432.29" switch \initial - attribute \src "libresoc.v:98636.9-98636.17" + attribute \src "libresoc.v:98432.9-98432.17" case 1'1 case end @@ -153626,14 +153422,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end - attribute \src "libresoc.v:98738.3-98840.6" - process $proc$libresoc.v:98738$3969 + attribute \src "libresoc.v:98534.3-98636.6" + process $proc$libresoc.v:98534$3969 assign { } { } assign { } { } assign $0\dec31_dec_sub15_out_sel[2:0] $1\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:98739.5-98739.29" + attribute \src "libresoc.v:98535.5-98535.29" switch \initial - attribute \src "libresoc.v:98739.9-98739.17" + attribute \src "libresoc.v:98535.9-98535.17" case 1'1 case end @@ -153775,144 +153571,144 @@ module \dec31_dec_sub15 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98846.1-99526.10" +attribute \src "libresoc.v:98642.1-99322.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" attribute \generator "nMigen" module \dec31_dec_sub16 - attribute \src "libresoc.v:99465.3-99474.6" + attribute \src "libresoc.v:99261.3-99270.6" wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:99475.3-99484.6" + attribute \src "libresoc.v:99271.3-99280.6" wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:99345.3-99354.6" + attribute \src "libresoc.v:99141.3-99150.6" wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:99385.3-99394.6" + attribute \src "libresoc.v:99181.3-99190.6" wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:99205.3-99214.6" + attribute \src "libresoc.v:99001.3-99010.6" wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:99215.3-99224.6" + attribute \src "libresoc.v:99011.3-99020.6" wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:99335.3-99344.6" + attribute \src "libresoc.v:99131.3-99140.6" wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:99375.3-99384.6" + attribute \src "libresoc.v:99171.3-99180.6" wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:99415.3-99424.6" + attribute \src "libresoc.v:99211.3-99220.6" wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:99195.3-99204.6" + attribute \src "libresoc.v:98991.3-99000.6" wire width 14 $0\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:99485.3-99494.6" + attribute \src "libresoc.v:99281.3-99290.6" wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:99495.3-99504.6" + attribute \src "libresoc.v:99291.3-99300.6" wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:99505.3-99514.6" + attribute \src "libresoc.v:99301.3-99310.6" wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:99305.3-99314.6" + attribute \src "libresoc.v:99101.3-99110.6" wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:99355.3-99364.6" + attribute \src "libresoc.v:99151.3-99160.6" wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:99365.3-99374.6" + attribute \src "libresoc.v:99161.3-99170.6" wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:99425.3-99434.6" + attribute \src "libresoc.v:99221.3-99230.6" wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:99295.3-99304.6" + attribute \src "libresoc.v:99091.3-99100.6" wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:99445.3-99454.6" + attribute \src "libresoc.v:99241.3-99250.6" wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:99515.3-99524.6" + attribute \src "libresoc.v:99311.3-99320.6" wire width 3 $0\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:99325.3-99334.6" + attribute \src "libresoc.v:99121.3-99130.6" wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:99405.3-99414.6" + attribute \src "libresoc.v:99201.3-99210.6" wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:99455.3-99464.6" + attribute \src "libresoc.v:99251.3-99260.6" wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:99435.3-99444.6" + attribute \src "libresoc.v:99231.3-99240.6" wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:99395.3-99404.6" + attribute \src "libresoc.v:99191.3-99200.6" wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:99275.3-99284.6" + attribute \src "libresoc.v:99071.3-99080.6" wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:99285.3-99294.6" + attribute \src "libresoc.v:99081.3-99090.6" wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:99225.3-99234.6" + attribute \src "libresoc.v:99021.3-99030.6" wire width 3 $0\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:99235.3-99244.6" + attribute \src "libresoc.v:99031.3-99040.6" wire width 3 $0\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:99245.3-99254.6" + attribute \src "libresoc.v:99041.3-99050.6" wire width 3 $0\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:99265.3-99274.6" + attribute \src "libresoc.v:99061.3-99070.6" wire width 3 $0\dec31_dec_sub16_sv_out2[2:0] - attribute \src "libresoc.v:99255.3-99264.6" + attribute \src "libresoc.v:99051.3-99060.6" wire width 3 $0\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:99315.3-99324.6" + attribute \src "libresoc.v:99111.3-99120.6" wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:98847.7-98847.20" + attribute \src "libresoc.v:98643.7-98643.20" wire $0\initial[0:0] - attribute \src "libresoc.v:99465.3-99474.6" + attribute \src "libresoc.v:99261.3-99270.6" wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:99475.3-99484.6" + attribute \src "libresoc.v:99271.3-99280.6" wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:99345.3-99354.6" + attribute \src "libresoc.v:99141.3-99150.6" wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:99385.3-99394.6" + attribute \src "libresoc.v:99181.3-99190.6" wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:99205.3-99214.6" + attribute \src "libresoc.v:99001.3-99010.6" wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:99215.3-99224.6" + attribute \src "libresoc.v:99011.3-99020.6" wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:99335.3-99344.6" + attribute \src "libresoc.v:99131.3-99140.6" wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:99375.3-99384.6" + attribute \src "libresoc.v:99171.3-99180.6" wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:99415.3-99424.6" + attribute \src "libresoc.v:99211.3-99220.6" wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:99195.3-99204.6" + attribute \src "libresoc.v:98991.3-99000.6" wire width 14 $1\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:99485.3-99494.6" + attribute \src "libresoc.v:99281.3-99290.6" wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:99495.3-99504.6" + attribute \src "libresoc.v:99291.3-99300.6" wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:99505.3-99514.6" + attribute \src "libresoc.v:99301.3-99310.6" wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:99305.3-99314.6" + attribute \src "libresoc.v:99101.3-99110.6" wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:99355.3-99364.6" + attribute \src "libresoc.v:99151.3-99160.6" wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:99365.3-99374.6" + attribute \src "libresoc.v:99161.3-99170.6" wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:99425.3-99434.6" + attribute \src "libresoc.v:99221.3-99230.6" wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:99295.3-99304.6" + attribute \src "libresoc.v:99091.3-99100.6" wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:99445.3-99454.6" + attribute \src "libresoc.v:99241.3-99250.6" wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:99515.3-99524.6" + attribute \src "libresoc.v:99311.3-99320.6" wire width 3 $1\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:99325.3-99334.6" + attribute \src "libresoc.v:99121.3-99130.6" wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:99405.3-99414.6" + attribute \src "libresoc.v:99201.3-99210.6" wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:99455.3-99464.6" + attribute \src "libresoc.v:99251.3-99260.6" wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:99435.3-99444.6" + attribute \src "libresoc.v:99231.3-99240.6" wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:99395.3-99404.6" + attribute \src "libresoc.v:99191.3-99200.6" wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:99275.3-99284.6" + attribute \src "libresoc.v:99071.3-99080.6" wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:99285.3-99294.6" + attribute \src "libresoc.v:99081.3-99090.6" wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:99225.3-99234.6" + attribute \src "libresoc.v:99021.3-99030.6" wire width 3 $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:99235.3-99244.6" + attribute \src "libresoc.v:99031.3-99040.6" wire width 3 $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:99245.3-99254.6" + attribute \src "libresoc.v:99041.3-99050.6" wire width 3 $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:99265.3-99274.6" + attribute \src "libresoc.v:99061.3-99070.6" wire width 3 $1\dec31_dec_sub16_sv_out2[2:0] - attribute \src "libresoc.v:99255.3-99264.6" + attribute \src "libresoc.v:99051.3-99060.6" wire width 3 $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:99315.3-99324.6" + attribute \src "libresoc.v:99111.3-99120.6" wire width 2 $1\dec31_dec_sub16_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -154224,28 +154020,28 @@ module \dec31_dec_sub16 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub16_upd - attribute \src "libresoc.v:98847.7-98847.15" + attribute \src "libresoc.v:98643.7-98643.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:98847.7-98847.20" - process $proc$libresoc.v:98847$4004 + attribute \src "libresoc.v:98643.7-98643.20" + process $proc$libresoc.v:98643$4004 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:99195.3-99204.6" - process $proc$libresoc.v:99195$3971 + attribute \src "libresoc.v:98991.3-99000.6" + process $proc$libresoc.v:98991$3971 assign { } { } assign { } { } assign $0\dec31_dec_sub16_function_unit[13:0] $1\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:99196.5-99196.29" + attribute \src "libresoc.v:98992.5-98992.29" switch \initial - attribute \src "libresoc.v:99196.9-99196.17" + attribute \src "libresoc.v:98992.9-98992.17" case 1'1 case end @@ -154261,14 +154057,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[13:0] end - attribute \src "libresoc.v:99205.3-99214.6" - process $proc$libresoc.v:99205$3972 + attribute \src "libresoc.v:99001.3-99010.6" + process $proc$libresoc.v:99001$3972 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:99206.5-99206.29" + attribute \src "libresoc.v:99002.5-99002.29" switch \initial - attribute \src "libresoc.v:99206.9-99206.17" + attribute \src "libresoc.v:99002.9-99002.17" case 1'1 case end @@ -154284,14 +154080,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] end - attribute \src "libresoc.v:99215.3-99224.6" - process $proc$libresoc.v:99215$3973 + attribute \src "libresoc.v:99011.3-99020.6" + process $proc$libresoc.v:99011$3973 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:99216.5-99216.29" + attribute \src "libresoc.v:99012.5-99012.29" switch \initial - attribute \src "libresoc.v:99216.9-99216.17" + attribute \src "libresoc.v:99012.9-99012.17" case 1'1 case end @@ -154307,14 +154103,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] end - attribute \src "libresoc.v:99225.3-99234.6" - process $proc$libresoc.v:99225$3974 + attribute \src "libresoc.v:99021.3-99030.6" + process $proc$libresoc.v:99021$3974 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:99226.5-99226.29" + attribute \src "libresoc.v:99022.5-99022.29" switch \initial - attribute \src "libresoc.v:99226.9-99226.17" + attribute \src "libresoc.v:99022.9-99022.17" case 1'1 case end @@ -154330,14 +154126,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0] end - attribute \src "libresoc.v:99235.3-99244.6" - process $proc$libresoc.v:99235$3975 + attribute \src "libresoc.v:99031.3-99040.6" + process $proc$libresoc.v:99031$3975 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:99236.5-99236.29" + attribute \src "libresoc.v:99032.5-99032.29" switch \initial - attribute \src "libresoc.v:99236.9-99236.17" + attribute \src "libresoc.v:99032.9-99032.17" case 1'1 case end @@ -154353,14 +154149,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0] end - attribute \src "libresoc.v:99245.3-99254.6" - process $proc$libresoc.v:99245$3976 + attribute \src "libresoc.v:99041.3-99050.6" + process $proc$libresoc.v:99041$3976 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:99246.5-99246.29" + attribute \src "libresoc.v:99042.5-99042.29" switch \initial - attribute \src "libresoc.v:99246.9-99246.17" + attribute \src "libresoc.v:99042.9-99042.17" case 1'1 case end @@ -154376,14 +154172,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0] end - attribute \src "libresoc.v:99255.3-99264.6" - process $proc$libresoc.v:99255$3977 + attribute \src "libresoc.v:99051.3-99060.6" + process $proc$libresoc.v:99051$3977 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:99256.5-99256.29" + attribute \src "libresoc.v:99052.5-99052.29" switch \initial - attribute \src "libresoc.v:99256.9-99256.17" + attribute \src "libresoc.v:99052.9-99052.17" case 1'1 case end @@ -154399,14 +154195,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0] end - attribute \src "libresoc.v:99265.3-99274.6" - process $proc$libresoc.v:99265$3978 + attribute \src "libresoc.v:99061.3-99070.6" + process $proc$libresoc.v:99061$3978 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out2[2:0] $1\dec31_dec_sub16_sv_out2[2:0] - attribute \src "libresoc.v:99266.5-99266.29" + attribute \src "libresoc.v:99062.5-99062.29" switch \initial - attribute \src "libresoc.v:99266.9-99266.17" + attribute \src "libresoc.v:99062.9-99062.17" case 1'1 case end @@ -154422,14 +154218,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_out2 $0\dec31_dec_sub16_sv_out2[2:0] end - attribute \src "libresoc.v:99275.3-99284.6" - process $proc$libresoc.v:99275$3979 + attribute \src "libresoc.v:99071.3-99080.6" + process $proc$libresoc.v:99071$3979 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:99276.5-99276.29" + attribute \src "libresoc.v:99072.5-99072.29" switch \initial - attribute \src "libresoc.v:99276.9-99276.17" + attribute \src "libresoc.v:99072.9-99072.17" case 1'1 case end @@ -154445,14 +154241,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0] end - attribute \src "libresoc.v:99285.3-99294.6" - process $proc$libresoc.v:99285$3980 + attribute \src "libresoc.v:99081.3-99090.6" + process $proc$libresoc.v:99081$3980 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:99286.5-99286.29" + attribute \src "libresoc.v:99082.5-99082.29" switch \initial - attribute \src "libresoc.v:99286.9-99286.17" + attribute \src "libresoc.v:99082.9-99082.17" case 1'1 case end @@ -154468,14 +154264,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0] end - attribute \src "libresoc.v:99295.3-99304.6" - process $proc$libresoc.v:99295$3981 + attribute \src "libresoc.v:99091.3-99100.6" + process $proc$libresoc.v:99091$3981 assign { } { } assign { } { } assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:99296.5-99296.29" + attribute \src "libresoc.v:99092.5-99092.29" switch \initial - attribute \src "libresoc.v:99296.9-99296.17" + attribute \src "libresoc.v:99092.9-99092.17" case 1'1 case end @@ -154491,14 +154287,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] end - attribute \src "libresoc.v:99305.3-99314.6" - process $proc$libresoc.v:99305$3982 + attribute \src "libresoc.v:99101.3-99110.6" + process $proc$libresoc.v:99101$3982 assign { } { } assign { } { } assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:99306.5-99306.29" + attribute \src "libresoc.v:99102.5-99102.29" switch \initial - attribute \src "libresoc.v:99306.9-99306.17" + attribute \src "libresoc.v:99102.9-99102.17" case 1'1 case end @@ -154514,14 +154310,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] end - attribute \src "libresoc.v:99315.3-99324.6" - process $proc$libresoc.v:99315$3983 + attribute \src "libresoc.v:99111.3-99120.6" + process $proc$libresoc.v:99111$3983 assign { } { } assign { } { } assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:99316.5-99316.29" + attribute \src "libresoc.v:99112.5-99112.29" switch \initial - attribute \src "libresoc.v:99316.9-99316.17" + attribute \src "libresoc.v:99112.9-99112.17" case 1'1 case end @@ -154537,14 +154333,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] end - attribute \src "libresoc.v:99325.3-99334.6" - process $proc$libresoc.v:99325$3984 + attribute \src "libresoc.v:99121.3-99130.6" + process $proc$libresoc.v:99121$3984 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:99326.5-99326.29" + attribute \src "libresoc.v:99122.5-99122.29" switch \initial - attribute \src "libresoc.v:99326.9-99326.17" + attribute \src "libresoc.v:99122.9-99122.17" case 1'1 case end @@ -154560,14 +154356,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] end - attribute \src "libresoc.v:99335.3-99344.6" - process $proc$libresoc.v:99335$3985 + attribute \src "libresoc.v:99131.3-99140.6" + process $proc$libresoc.v:99131$3985 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:99336.5-99336.29" + attribute \src "libresoc.v:99132.5-99132.29" switch \initial - attribute \src "libresoc.v:99336.9-99336.17" + attribute \src "libresoc.v:99132.9-99132.17" case 1'1 case end @@ -154583,14 +154379,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] end - attribute \src "libresoc.v:99345.3-99354.6" - process $proc$libresoc.v:99345$3986 + attribute \src "libresoc.v:99141.3-99150.6" + process $proc$libresoc.v:99141$3986 assign { } { } assign { } { } assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:99346.5-99346.29" + attribute \src "libresoc.v:99142.5-99142.29" switch \initial - attribute \src "libresoc.v:99346.9-99346.17" + attribute \src "libresoc.v:99142.9-99142.17" case 1'1 case end @@ -154606,14 +154402,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] end - attribute \src "libresoc.v:99355.3-99364.6" - process $proc$libresoc.v:99355$3987 + attribute \src "libresoc.v:99151.3-99160.6" + process $proc$libresoc.v:99151$3987 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:99356.5-99356.29" + attribute \src "libresoc.v:99152.5-99152.29" switch \initial - attribute \src "libresoc.v:99356.9-99356.17" + attribute \src "libresoc.v:99152.9-99152.17" case 1'1 case end @@ -154629,14 +154425,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] end - attribute \src "libresoc.v:99365.3-99374.6" - process $proc$libresoc.v:99365$3988 + attribute \src "libresoc.v:99161.3-99170.6" + process $proc$libresoc.v:99161$3988 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:99366.5-99366.29" + attribute \src "libresoc.v:99162.5-99162.29" switch \initial - attribute \src "libresoc.v:99366.9-99366.17" + attribute \src "libresoc.v:99162.9-99162.17" case 1'1 case end @@ -154652,14 +154448,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] end - attribute \src "libresoc.v:99375.3-99384.6" - process $proc$libresoc.v:99375$3989 + attribute \src "libresoc.v:99171.3-99180.6" + process $proc$libresoc.v:99171$3989 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:99376.5-99376.29" + attribute \src "libresoc.v:99172.5-99172.29" switch \initial - attribute \src "libresoc.v:99376.9-99376.17" + attribute \src "libresoc.v:99172.9-99172.17" case 1'1 case end @@ -154675,14 +154471,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] end - attribute \src "libresoc.v:99385.3-99394.6" - process $proc$libresoc.v:99385$3990 + attribute \src "libresoc.v:99181.3-99190.6" + process $proc$libresoc.v:99181$3990 assign { } { } assign { } { } assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:99386.5-99386.29" + attribute \src "libresoc.v:99182.5-99182.29" switch \initial - attribute \src "libresoc.v:99386.9-99386.17" + attribute \src "libresoc.v:99182.9-99182.17" case 1'1 case end @@ -154698,14 +154494,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] end - attribute \src "libresoc.v:99395.3-99404.6" - process $proc$libresoc.v:99395$3991 + attribute \src "libresoc.v:99191.3-99200.6" + process $proc$libresoc.v:99191$3991 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:99396.5-99396.29" + attribute \src "libresoc.v:99192.5-99192.29" switch \initial - attribute \src "libresoc.v:99396.9-99396.17" + attribute \src "libresoc.v:99192.9-99192.17" case 1'1 case end @@ -154721,14 +154517,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] end - attribute \src "libresoc.v:99405.3-99414.6" - process $proc$libresoc.v:99405$3992 + attribute \src "libresoc.v:99201.3-99210.6" + process $proc$libresoc.v:99201$3992 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:99406.5-99406.29" + attribute \src "libresoc.v:99202.5-99202.29" switch \initial - attribute \src "libresoc.v:99406.9-99406.17" + attribute \src "libresoc.v:99202.9-99202.17" case 1'1 case end @@ -154744,14 +154540,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] end - attribute \src "libresoc.v:99415.3-99424.6" - process $proc$libresoc.v:99415$3993 + attribute \src "libresoc.v:99211.3-99220.6" + process $proc$libresoc.v:99211$3993 assign { } { } assign { } { } assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:99416.5-99416.29" + attribute \src "libresoc.v:99212.5-99212.29" switch \initial - attribute \src "libresoc.v:99416.9-99416.17" + attribute \src "libresoc.v:99212.9-99212.17" case 1'1 case end @@ -154767,14 +154563,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] end - attribute \src "libresoc.v:99425.3-99434.6" - process $proc$libresoc.v:99425$3994 + attribute \src "libresoc.v:99221.3-99230.6" + process $proc$libresoc.v:99221$3994 assign { } { } assign { } { } assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:99426.5-99426.29" + attribute \src "libresoc.v:99222.5-99222.29" switch \initial - attribute \src "libresoc.v:99426.9-99426.17" + attribute \src "libresoc.v:99222.9-99222.17" case 1'1 case end @@ -154790,14 +154586,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] end - attribute \src "libresoc.v:99435.3-99444.6" - process $proc$libresoc.v:99435$3995 + attribute \src "libresoc.v:99231.3-99240.6" + process $proc$libresoc.v:99231$3995 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:99436.5-99436.29" + attribute \src "libresoc.v:99232.5-99232.29" switch \initial - attribute \src "libresoc.v:99436.9-99436.17" + attribute \src "libresoc.v:99232.9-99232.17" case 1'1 case end @@ -154813,14 +154609,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] end - attribute \src "libresoc.v:99445.3-99454.6" - process $proc$libresoc.v:99445$3996 + attribute \src "libresoc.v:99241.3-99250.6" + process $proc$libresoc.v:99241$3996 assign { } { } assign { } { } assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:99446.5-99446.29" + attribute \src "libresoc.v:99242.5-99242.29" switch \initial - attribute \src "libresoc.v:99446.9-99446.17" + attribute \src "libresoc.v:99242.9-99242.17" case 1'1 case end @@ -154836,14 +154632,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] end - attribute \src "libresoc.v:99455.3-99464.6" - process $proc$libresoc.v:99455$3997 + attribute \src "libresoc.v:99251.3-99260.6" + process $proc$libresoc.v:99251$3997 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:99456.5-99456.29" + attribute \src "libresoc.v:99252.5-99252.29" switch \initial - attribute \src "libresoc.v:99456.9-99456.17" + attribute \src "libresoc.v:99252.9-99252.17" case 1'1 case end @@ -154859,14 +154655,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] end - attribute \src "libresoc.v:99465.3-99474.6" - process $proc$libresoc.v:99465$3998 + attribute \src "libresoc.v:99261.3-99270.6" + process $proc$libresoc.v:99261$3998 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:99466.5-99466.29" + attribute \src "libresoc.v:99262.5-99262.29" switch \initial - attribute \src "libresoc.v:99466.9-99466.17" + attribute \src "libresoc.v:99262.9-99262.17" case 1'1 case end @@ -154882,14 +154678,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0] end - attribute \src "libresoc.v:99475.3-99484.6" - process $proc$libresoc.v:99475$3999 + attribute \src "libresoc.v:99271.3-99280.6" + process $proc$libresoc.v:99271$3999 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:99476.5-99476.29" + attribute \src "libresoc.v:99272.5-99272.29" switch \initial - attribute \src "libresoc.v:99476.9-99476.17" + attribute \src "libresoc.v:99272.9-99272.17" case 1'1 case end @@ -154905,14 +154701,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0] end - attribute \src "libresoc.v:99485.3-99494.6" - process $proc$libresoc.v:99485$4000 + attribute \src "libresoc.v:99281.3-99290.6" + process $proc$libresoc.v:99281$4000 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:99486.5-99486.29" + attribute \src "libresoc.v:99282.5-99282.29" switch \initial - attribute \src "libresoc.v:99486.9-99486.17" + attribute \src "libresoc.v:99282.9-99282.17" case 1'1 case end @@ -154928,14 +154724,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] end - attribute \src "libresoc.v:99495.3-99504.6" - process $proc$libresoc.v:99495$4001 + attribute \src "libresoc.v:99291.3-99300.6" + process $proc$libresoc.v:99291$4001 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:99496.5-99496.29" + attribute \src "libresoc.v:99292.5-99292.29" switch \initial - attribute \src "libresoc.v:99496.9-99496.17" + attribute \src "libresoc.v:99292.9-99292.17" case 1'1 case end @@ -154951,14 +154747,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] end - attribute \src "libresoc.v:99505.3-99514.6" - process $proc$libresoc.v:99505$4002 + attribute \src "libresoc.v:99301.3-99310.6" + process $proc$libresoc.v:99301$4002 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:99506.5-99506.29" + attribute \src "libresoc.v:99302.5-99302.29" switch \initial - attribute \src "libresoc.v:99506.9-99506.17" + attribute \src "libresoc.v:99302.9-99302.17" case 1'1 case end @@ -154974,14 +154770,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] end - attribute \src "libresoc.v:99515.3-99524.6" - process $proc$libresoc.v:99515$4003 + attribute \src "libresoc.v:99311.3-99320.6" + process $proc$libresoc.v:99311$4003 assign { } { } assign { } { } assign $0\dec31_dec_sub16_out_sel[2:0] $1\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:99516.5-99516.29" + attribute \src "libresoc.v:99312.5-99312.29" switch \initial - attribute \src "libresoc.v:99516.9-99516.17" + attribute \src "libresoc.v:99312.9-99312.17" case 1'1 case end @@ -154999,144 +154795,144 @@ module \dec31_dec_sub16 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:99530.1-100606.10" +attribute \src "libresoc.v:99326.1-100402.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" attribute \generator "nMigen" module \dec31_dec_sub18 - attribute \src "libresoc.v:100473.3-100494.6" + attribute \src "libresoc.v:100269.3-100290.6" wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:100495.3-100516.6" + attribute \src "libresoc.v:100291.3-100312.6" wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:100209.3-100230.6" + attribute \src "libresoc.v:100005.3-100026.6" wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:100297.3-100318.6" + attribute \src "libresoc.v:100093.3-100114.6" wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:99901.3-99922.6" + attribute \src "libresoc.v:99697.3-99718.6" wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:99923.3-99944.6" + attribute \src "libresoc.v:99719.3-99740.6" wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:100187.3-100208.6" + attribute \src "libresoc.v:99983.3-100004.6" wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:100275.3-100296.6" + attribute \src "libresoc.v:100071.3-100092.6" wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:100363.3-100384.6" + attribute \src "libresoc.v:100159.3-100180.6" wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99879.3-99900.6" + attribute \src "libresoc.v:99675.3-99696.6" wire width 14 $0\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:100517.3-100538.6" + attribute \src "libresoc.v:100313.3-100334.6" wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:100539.3-100560.6" + attribute \src "libresoc.v:100335.3-100356.6" wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:100561.3-100582.6" + attribute \src "libresoc.v:100357.3-100378.6" wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:100121.3-100142.6" + attribute \src "libresoc.v:99917.3-99938.6" wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:100231.3-100252.6" + attribute \src "libresoc.v:100027.3-100048.6" wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:100253.3-100274.6" + attribute \src "libresoc.v:100049.3-100070.6" wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:100385.3-100406.6" + attribute \src "libresoc.v:100181.3-100202.6" wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:100099.3-100120.6" + attribute \src "libresoc.v:99895.3-99916.6" wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:100429.3-100450.6" + attribute \src "libresoc.v:100225.3-100246.6" wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:100583.3-100604.6" + attribute \src "libresoc.v:100379.3-100400.6" wire width 3 $0\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:100165.3-100186.6" + attribute \src "libresoc.v:99961.3-99982.6" wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:100341.3-100362.6" + attribute \src "libresoc.v:100137.3-100158.6" wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:100451.3-100472.6" + attribute \src "libresoc.v:100247.3-100268.6" wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:100407.3-100428.6" + attribute \src "libresoc.v:100203.3-100224.6" wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:100319.3-100340.6" + attribute \src "libresoc.v:100115.3-100136.6" wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:100055.3-100076.6" + attribute \src "libresoc.v:99851.3-99872.6" wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:100077.3-100098.6" + attribute \src "libresoc.v:99873.3-99894.6" wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:99945.3-99966.6" + attribute \src "libresoc.v:99741.3-99762.6" wire width 3 $0\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:99967.3-99988.6" + attribute \src "libresoc.v:99763.3-99784.6" wire width 3 $0\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:99989.3-100010.6" + attribute \src "libresoc.v:99785.3-99806.6" wire width 3 $0\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:100033.3-100054.6" + attribute \src "libresoc.v:99829.3-99850.6" wire width 3 $0\dec31_dec_sub18_sv_out2[2:0] - attribute \src "libresoc.v:100011.3-100032.6" + attribute \src "libresoc.v:99807.3-99828.6" wire width 3 $0\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:100143.3-100164.6" + attribute \src "libresoc.v:99939.3-99960.6" wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:99531.7-99531.20" + attribute \src "libresoc.v:99327.7-99327.20" wire $0\initial[0:0] - attribute \src "libresoc.v:100473.3-100494.6" + attribute \src "libresoc.v:100269.3-100290.6" wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:100495.3-100516.6" + attribute \src "libresoc.v:100291.3-100312.6" wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:100209.3-100230.6" + attribute \src "libresoc.v:100005.3-100026.6" wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:100297.3-100318.6" + attribute \src "libresoc.v:100093.3-100114.6" wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:99901.3-99922.6" + attribute \src "libresoc.v:99697.3-99718.6" wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:99923.3-99944.6" + attribute \src "libresoc.v:99719.3-99740.6" wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:100187.3-100208.6" + attribute \src "libresoc.v:99983.3-100004.6" wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:100275.3-100296.6" + attribute \src "libresoc.v:100071.3-100092.6" wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:100363.3-100384.6" + attribute \src "libresoc.v:100159.3-100180.6" wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99879.3-99900.6" + attribute \src "libresoc.v:99675.3-99696.6" wire width 14 $1\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:100517.3-100538.6" + attribute \src "libresoc.v:100313.3-100334.6" wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:100539.3-100560.6" + attribute \src "libresoc.v:100335.3-100356.6" wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:100561.3-100582.6" + attribute \src "libresoc.v:100357.3-100378.6" wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:100121.3-100142.6" + attribute \src "libresoc.v:99917.3-99938.6" wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:100231.3-100252.6" + attribute \src "libresoc.v:100027.3-100048.6" wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:100253.3-100274.6" + attribute \src "libresoc.v:100049.3-100070.6" wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:100385.3-100406.6" + attribute \src "libresoc.v:100181.3-100202.6" wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:100099.3-100120.6" + attribute \src "libresoc.v:99895.3-99916.6" wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:100429.3-100450.6" + attribute \src "libresoc.v:100225.3-100246.6" wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:100583.3-100604.6" + attribute \src "libresoc.v:100379.3-100400.6" wire width 3 $1\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:100165.3-100186.6" + attribute \src "libresoc.v:99961.3-99982.6" wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:100341.3-100362.6" + attribute \src "libresoc.v:100137.3-100158.6" wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:100451.3-100472.6" + attribute \src "libresoc.v:100247.3-100268.6" wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:100407.3-100428.6" + attribute \src "libresoc.v:100203.3-100224.6" wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:100319.3-100340.6" + attribute \src "libresoc.v:100115.3-100136.6" wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:100055.3-100076.6" + attribute \src "libresoc.v:99851.3-99872.6" wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:100077.3-100098.6" + attribute \src "libresoc.v:99873.3-99894.6" wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:99945.3-99966.6" + attribute \src "libresoc.v:99741.3-99762.6" wire width 3 $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:99967.3-99988.6" + attribute \src "libresoc.v:99763.3-99784.6" wire width 3 $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:99989.3-100010.6" + attribute \src "libresoc.v:99785.3-99806.6" wire width 3 $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:100033.3-100054.6" + attribute \src "libresoc.v:99829.3-99850.6" wire width 3 $1\dec31_dec_sub18_sv_out2[2:0] - attribute \src "libresoc.v:100011.3-100032.6" + attribute \src "libresoc.v:99807.3-99828.6" wire width 3 $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:100143.3-100164.6" + attribute \src "libresoc.v:99939.3-99960.6" wire width 2 $1\dec31_dec_sub18_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -155448,371 +155244,20 @@ module \dec31_dec_sub18 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub18_upd - attribute \src "libresoc.v:99531.7-99531.15" + attribute \src "libresoc.v:99327.7-99327.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:100011.3-100032.6" - process $proc$libresoc.v:100011$4011 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:100012.5-100012.29" - switch \initial - attribute \src "libresoc.v:100012.9-100012.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - case - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] - end - attribute \src "libresoc.v:100033.3-100054.6" - process $proc$libresoc.v:100033$4012 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sv_out2[2:0] $1\dec31_dec_sub18_sv_out2[2:0] - attribute \src "libresoc.v:100034.5-100034.29" - switch \initial - attribute \src "libresoc.v:100034.9-100034.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - case - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_sv_out2 $0\dec31_dec_sub18_sv_out2[2:0] - end - attribute \src "libresoc.v:100055.3-100076.6" - process $proc$libresoc.v:100055$4013 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:100056.5-100056.29" - switch \initial - attribute \src "libresoc.v:100056.9-100056.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] - end - attribute \src "libresoc.v:100077.3-100098.6" - process $proc$libresoc.v:100077$4014 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:100078.5-100078.29" - switch \initial - attribute \src "libresoc.v:100078.9-100078.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] - end - attribute \src "libresoc.v:100099.3-100120.6" - process $proc$libresoc.v:100099$4015 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:100100.5-100100.29" - switch \initial - attribute \src "libresoc.v:100100.9-100100.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] - end - attribute \src "libresoc.v:100121.3-100142.6" - process $proc$libresoc.v:100121$4016 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:100122.5-100122.29" - switch \initial - attribute \src "libresoc.v:100122.9-100122.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - case - assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] - end - attribute \src "libresoc.v:100143.3-100164.6" - process $proc$libresoc.v:100143$4017 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:100144.5-100144.29" - switch \initial - attribute \src "libresoc.v:100144.9-100144.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] - end - attribute \src "libresoc.v:100165.3-100186.6" - process $proc$libresoc.v:100165$4018 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:100166.5-100166.29" - switch \initial - attribute \src "libresoc.v:100166.9-100166.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] - end - attribute \src "libresoc.v:100187.3-100208.6" - process $proc$libresoc.v:100187$4019 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:100188.5-100188.29" - switch \initial - attribute \src "libresoc.v:100188.9-100188.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] - end - attribute \src "libresoc.v:100209.3-100230.6" - process $proc$libresoc.v:100209$4020 + attribute \src "libresoc.v:100005.3-100026.6" + process $proc$libresoc.v:100005$4020 assign { } { } assign { } { } assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:100210.5-100210.29" + attribute \src "libresoc.v:100006.5-100006.29" switch \initial - attribute \src "libresoc.v:100210.9-100210.17" + attribute \src "libresoc.v:100006.9-100006.17" case 1'1 case end @@ -155844,14 +155289,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] end - attribute \src "libresoc.v:100231.3-100252.6" - process $proc$libresoc.v:100231$4021 + attribute \src "libresoc.v:100027.3-100048.6" + process $proc$libresoc.v:100027$4021 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:100232.5-100232.29" + attribute \src "libresoc.v:100028.5-100028.29" switch \initial - attribute \src "libresoc.v:100232.9-100232.17" + attribute \src "libresoc.v:100028.9-100028.17" case 1'1 case end @@ -155883,14 +155328,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] end - attribute \src "libresoc.v:100253.3-100274.6" - process $proc$libresoc.v:100253$4022 + attribute \src "libresoc.v:100049.3-100070.6" + process $proc$libresoc.v:100049$4022 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:100254.5-100254.29" + attribute \src "libresoc.v:100050.5-100050.29" switch \initial - attribute \src "libresoc.v:100254.9-100254.17" + attribute \src "libresoc.v:100050.9-100050.17" case 1'1 case end @@ -155922,14 +155367,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] end - attribute \src "libresoc.v:100275.3-100296.6" - process $proc$libresoc.v:100275$4023 + attribute \src "libresoc.v:100071.3-100092.6" + process $proc$libresoc.v:100071$4023 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:100276.5-100276.29" + attribute \src "libresoc.v:100072.5-100072.29" switch \initial - attribute \src "libresoc.v:100276.9-100276.17" + attribute \src "libresoc.v:100072.9-100072.17" case 1'1 case end @@ -155961,14 +155406,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] end - attribute \src "libresoc.v:100297.3-100318.6" - process $proc$libresoc.v:100297$4024 + attribute \src "libresoc.v:100093.3-100114.6" + process $proc$libresoc.v:100093$4024 assign { } { } assign { } { } assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:100298.5-100298.29" + attribute \src "libresoc.v:100094.5-100094.29" switch \initial - attribute \src "libresoc.v:100298.9-100298.17" + attribute \src "libresoc.v:100094.9-100094.17" case 1'1 case end @@ -156000,14 +155445,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] end - attribute \src "libresoc.v:100319.3-100340.6" - process $proc$libresoc.v:100319$4025 + attribute \src "libresoc.v:100115.3-100136.6" + process $proc$libresoc.v:100115$4025 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:100320.5-100320.29" + attribute \src "libresoc.v:100116.5-100116.29" switch \initial - attribute \src "libresoc.v:100320.9-100320.17" + attribute \src "libresoc.v:100116.9-100116.17" case 1'1 case end @@ -156039,14 +155484,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] end - attribute \src "libresoc.v:100341.3-100362.6" - process $proc$libresoc.v:100341$4026 + attribute \src "libresoc.v:100137.3-100158.6" + process $proc$libresoc.v:100137$4026 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:100342.5-100342.29" + attribute \src "libresoc.v:100138.5-100138.29" switch \initial - attribute \src "libresoc.v:100342.9-100342.17" + attribute \src "libresoc.v:100138.9-100138.17" case 1'1 case end @@ -156078,14 +155523,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] end - attribute \src "libresoc.v:100363.3-100384.6" - process $proc$libresoc.v:100363$4027 + attribute \src "libresoc.v:100159.3-100180.6" + process $proc$libresoc.v:100159$4027 assign { } { } assign { } { } assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:100364.5-100364.29" + attribute \src "libresoc.v:100160.5-100160.29" switch \initial - attribute \src "libresoc.v:100364.9-100364.17" + attribute \src "libresoc.v:100160.9-100160.17" case 1'1 case end @@ -156117,14 +155562,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] end - attribute \src "libresoc.v:100385.3-100406.6" - process $proc$libresoc.v:100385$4028 + attribute \src "libresoc.v:100181.3-100202.6" + process $proc$libresoc.v:100181$4028 assign { } { } assign { } { } assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:100386.5-100386.29" + attribute \src "libresoc.v:100182.5-100182.29" switch \initial - attribute \src "libresoc.v:100386.9-100386.17" + attribute \src "libresoc.v:100182.9-100182.17" case 1'1 case end @@ -156156,14 +155601,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] end - attribute \src "libresoc.v:100407.3-100428.6" - process $proc$libresoc.v:100407$4029 + attribute \src "libresoc.v:100203.3-100224.6" + process $proc$libresoc.v:100203$4029 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:100408.5-100408.29" + attribute \src "libresoc.v:100204.5-100204.29" switch \initial - attribute \src "libresoc.v:100408.9-100408.17" + attribute \src "libresoc.v:100204.9-100204.17" case 1'1 case end @@ -156195,14 +155640,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] end - attribute \src "libresoc.v:100429.3-100450.6" - process $proc$libresoc.v:100429$4030 + attribute \src "libresoc.v:100225.3-100246.6" + process $proc$libresoc.v:100225$4030 assign { } { } assign { } { } assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:100430.5-100430.29" + attribute \src "libresoc.v:100226.5-100226.29" switch \initial - attribute \src "libresoc.v:100430.9-100430.17" + attribute \src "libresoc.v:100226.9-100226.17" case 1'1 case end @@ -156234,14 +155679,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] end - attribute \src "libresoc.v:100451.3-100472.6" - process $proc$libresoc.v:100451$4031 + attribute \src "libresoc.v:100247.3-100268.6" + process $proc$libresoc.v:100247$4031 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:100452.5-100452.29" + attribute \src "libresoc.v:100248.5-100248.29" switch \initial - attribute \src "libresoc.v:100452.9-100452.17" + attribute \src "libresoc.v:100248.9-100248.17" case 1'1 case end @@ -156273,14 +155718,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] end - attribute \src "libresoc.v:100473.3-100494.6" - process $proc$libresoc.v:100473$4032 + attribute \src "libresoc.v:100269.3-100290.6" + process $proc$libresoc.v:100269$4032 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:100474.5-100474.29" + attribute \src "libresoc.v:100270.5-100270.29" switch \initial - attribute \src "libresoc.v:100474.9-100474.17" + attribute \src "libresoc.v:100270.9-100270.17" case 1'1 case end @@ -156312,14 +155757,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0] end - attribute \src "libresoc.v:100495.3-100516.6" - process $proc$libresoc.v:100495$4033 + attribute \src "libresoc.v:100291.3-100312.6" + process $proc$libresoc.v:100291$4033 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:100496.5-100496.29" + attribute \src "libresoc.v:100292.5-100292.29" switch \initial - attribute \src "libresoc.v:100496.9-100496.17" + attribute \src "libresoc.v:100292.9-100292.17" case 1'1 case end @@ -156351,14 +155796,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0] end - attribute \src "libresoc.v:100517.3-100538.6" - process $proc$libresoc.v:100517$4034 + attribute \src "libresoc.v:100313.3-100334.6" + process $proc$libresoc.v:100313$4034 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:100518.5-100518.29" + attribute \src "libresoc.v:100314.5-100314.29" switch \initial - attribute \src "libresoc.v:100518.9-100518.17" + attribute \src "libresoc.v:100314.9-100314.17" case 1'1 case end @@ -156390,14 +155835,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] end - attribute \src "libresoc.v:100539.3-100560.6" - process $proc$libresoc.v:100539$4035 + attribute \src "libresoc.v:100335.3-100356.6" + process $proc$libresoc.v:100335$4035 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:100540.5-100540.29" + attribute \src "libresoc.v:100336.5-100336.29" switch \initial - attribute \src "libresoc.v:100540.9-100540.17" + attribute \src "libresoc.v:100336.9-100336.17" case 1'1 case end @@ -156429,14 +155874,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] end - attribute \src "libresoc.v:100561.3-100582.6" - process $proc$libresoc.v:100561$4036 + attribute \src "libresoc.v:100357.3-100378.6" + process $proc$libresoc.v:100357$4036 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:100562.5-100562.29" + attribute \src "libresoc.v:100358.5-100358.29" switch \initial - attribute \src "libresoc.v:100562.9-100562.17" + attribute \src "libresoc.v:100358.9-100358.17" case 1'1 case end @@ -156468,14 +155913,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] end - attribute \src "libresoc.v:100583.3-100604.6" - process $proc$libresoc.v:100583$4037 + attribute \src "libresoc.v:100379.3-100400.6" + process $proc$libresoc.v:100379$4037 assign { } { } assign { } { } assign $0\dec31_dec_sub18_out_sel[2:0] $1\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:100584.5-100584.29" + attribute \src "libresoc.v:100380.5-100380.29" switch \initial - attribute \src "libresoc.v:100584.9-100584.17" + attribute \src "libresoc.v:100380.9-100380.17" case 1'1 case end @@ -156507,22 +155952,22 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[2:0] end - attribute \src "libresoc.v:99531.7-99531.20" - process $proc$libresoc.v:99531$4038 + attribute \src "libresoc.v:99327.7-99327.20" + process $proc$libresoc.v:99327$4038 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:99879.3-99900.6" - process $proc$libresoc.v:99879$4005 + attribute \src "libresoc.v:99675.3-99696.6" + process $proc$libresoc.v:99675$4005 assign { } { } assign { } { } assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:99880.5-99880.29" + attribute \src "libresoc.v:99676.5-99676.29" switch \initial - attribute \src "libresoc.v:99880.9-99880.17" + attribute \src "libresoc.v:99676.9-99676.17" case 1'1 case end @@ -156554,14 +155999,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] end - attribute \src "libresoc.v:99901.3-99922.6" - process $proc$libresoc.v:99901$4006 + attribute \src "libresoc.v:99697.3-99718.6" + process $proc$libresoc.v:99697$4006 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:99902.5-99902.29" + attribute \src "libresoc.v:99698.5-99698.29" switch \initial - attribute \src "libresoc.v:99902.9-99902.17" + attribute \src "libresoc.v:99698.9-99698.17" case 1'1 case end @@ -156593,14 +156038,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] end - attribute \src "libresoc.v:99923.3-99944.6" - process $proc$libresoc.v:99923$4007 + attribute \src "libresoc.v:99719.3-99740.6" + process $proc$libresoc.v:99719$4007 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:99924.5-99924.29" + attribute \src "libresoc.v:99720.5-99720.29" switch \initial - attribute \src "libresoc.v:99924.9-99924.17" + attribute \src "libresoc.v:99720.9-99720.17" case 1'1 case end @@ -156632,14 +156077,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] end - attribute \src "libresoc.v:99945.3-99966.6" - process $proc$libresoc.v:99945$4008 + attribute \src "libresoc.v:99741.3-99762.6" + process $proc$libresoc.v:99741$4008 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:99946.5-99946.29" + attribute \src "libresoc.v:99742.5-99742.29" switch \initial - attribute \src "libresoc.v:99946.9-99946.17" + attribute \src "libresoc.v:99742.9-99742.17" case 1'1 case end @@ -156671,14 +156116,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] end - attribute \src "libresoc.v:99967.3-99988.6" - process $proc$libresoc.v:99967$4009 + attribute \src "libresoc.v:99763.3-99784.6" + process $proc$libresoc.v:99763$4009 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:99968.5-99968.29" + attribute \src "libresoc.v:99764.5-99764.29" switch \initial - attribute \src "libresoc.v:99968.9-99968.17" + attribute \src "libresoc.v:99764.9-99764.17" case 1'1 case end @@ -156710,14 +156155,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] end - attribute \src "libresoc.v:99989.3-100010.6" - process $proc$libresoc.v:99989$4010 + attribute \src "libresoc.v:99785.3-99806.6" + process $proc$libresoc.v:99785$4010 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:99990.5-99990.29" + attribute \src "libresoc.v:99786.5-99786.29" switch \initial - attribute \src "libresoc.v:99990.9-99990.17" + attribute \src "libresoc.v:99786.9-99786.17" case 1'1 case end @@ -156749,146 +156194,497 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] end + attribute \src "libresoc.v:99807.3-99828.6" + process $proc$libresoc.v:99807$4011 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] + attribute \src "libresoc.v:99808.5-99808.29" + switch \initial + attribute \src "libresoc.v:99808.9-99808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] + end + attribute \src "libresoc.v:99829.3-99850.6" + process $proc$libresoc.v:99829$4012 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_out2[2:0] $1\dec31_dec_sub18_sv_out2[2:0] + attribute \src "libresoc.v:99830.5-99830.29" + switch \initial + attribute \src "libresoc.v:99830.9-99830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_out2 $0\dec31_dec_sub18_sv_out2[2:0] + end + attribute \src "libresoc.v:99851.3-99872.6" + process $proc$libresoc.v:99851$4013 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] + attribute \src "libresoc.v:99852.5-99852.29" + switch \initial + attribute \src "libresoc.v:99852.9-99852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] + end + attribute \src "libresoc.v:99873.3-99894.6" + process $proc$libresoc.v:99873$4014 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] + attribute \src "libresoc.v:99874.5-99874.29" + switch \initial + attribute \src "libresoc.v:99874.9-99874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] + end + attribute \src "libresoc.v:99895.3-99916.6" + process $proc$libresoc.v:99895$4015 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:99896.5-99896.29" + switch \initial + attribute \src "libresoc.v:99896.9-99896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] + end + attribute \src "libresoc.v:99917.3-99938.6" + process $proc$libresoc.v:99917$4016 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:99918.5-99918.29" + switch \initial + attribute \src "libresoc.v:99918.9-99918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + case + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + end + attribute \src "libresoc.v:99939.3-99960.6" + process $proc$libresoc.v:99939$4017 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:99940.5-99940.29" + switch \initial + attribute \src "libresoc.v:99940.9-99940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + end + attribute \src "libresoc.v:99961.3-99982.6" + process $proc$libresoc.v:99961$4018 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:99962.5-99962.29" + switch \initial + attribute \src "libresoc.v:99962.9-99962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] + end + attribute \src "libresoc.v:99983.3-100004.6" + process $proc$libresoc.v:99983$4019 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:99984.5-99984.29" + switch \initial + attribute \src "libresoc.v:99984.9-99984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] + end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:100610.1-101587.10" +attribute \src "libresoc.v:100406.1-101383.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" attribute \generator "nMigen" module \dec31_dec_sub19 - attribute \src "libresoc.v:101472.3-101490.6" + attribute \src "libresoc.v:101268.3-101286.6" wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:101491.3-101509.6" + attribute \src "libresoc.v:101287.3-101305.6" wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:101244.3-101262.6" + attribute \src "libresoc.v:101040.3-101058.6" wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:101320.3-101338.6" + attribute \src "libresoc.v:101116.3-101134.6" wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:100978.3-100996.6" + attribute \src "libresoc.v:100774.3-100792.6" wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:100997.3-101015.6" + attribute \src "libresoc.v:100793.3-100811.6" wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:101225.3-101243.6" + attribute \src "libresoc.v:101021.3-101039.6" wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:101301.3-101319.6" + attribute \src "libresoc.v:101097.3-101115.6" wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:101377.3-101395.6" + attribute \src "libresoc.v:101173.3-101191.6" wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:100959.3-100977.6" + attribute \src "libresoc.v:100755.3-100773.6" wire width 14 $0\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:101510.3-101528.6" + attribute \src "libresoc.v:101306.3-101324.6" wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:101529.3-101547.6" + attribute \src "libresoc.v:101325.3-101343.6" wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:101548.3-101566.6" + attribute \src "libresoc.v:101344.3-101362.6" wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:101168.3-101186.6" + attribute \src "libresoc.v:100964.3-100982.6" wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:101263.3-101281.6" + attribute \src "libresoc.v:101059.3-101077.6" wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:101282.3-101300.6" + attribute \src "libresoc.v:101078.3-101096.6" wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:101396.3-101414.6" + attribute \src "libresoc.v:101192.3-101210.6" wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:101149.3-101167.6" + attribute \src "libresoc.v:100945.3-100963.6" wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:101434.3-101452.6" + attribute \src "libresoc.v:101230.3-101248.6" wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:101567.3-101585.6" + attribute \src "libresoc.v:101363.3-101381.6" wire width 3 $0\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:101206.3-101224.6" + attribute \src "libresoc.v:101002.3-101020.6" wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:101358.3-101376.6" + attribute \src "libresoc.v:101154.3-101172.6" wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:101453.3-101471.6" + attribute \src "libresoc.v:101249.3-101267.6" wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:101415.3-101433.6" + attribute \src "libresoc.v:101211.3-101229.6" wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:101339.3-101357.6" + attribute \src "libresoc.v:101135.3-101153.6" wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:101111.3-101129.6" + attribute \src "libresoc.v:100907.3-100925.6" wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:101130.3-101148.6" + attribute \src "libresoc.v:100926.3-100944.6" wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:101016.3-101034.6" + attribute \src "libresoc.v:100812.3-100830.6" wire width 3 $0\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:101035.3-101053.6" + attribute \src "libresoc.v:100831.3-100849.6" wire width 3 $0\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:101054.3-101072.6" + attribute \src "libresoc.v:100850.3-100868.6" wire width 3 $0\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:101092.3-101110.6" + attribute \src "libresoc.v:100888.3-100906.6" wire width 3 $0\dec31_dec_sub19_sv_out2[2:0] - attribute \src "libresoc.v:101073.3-101091.6" + attribute \src "libresoc.v:100869.3-100887.6" wire width 3 $0\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:101187.3-101205.6" + attribute \src "libresoc.v:100983.3-101001.6" wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:100611.7-100611.20" + attribute \src "libresoc.v:100407.7-100407.20" wire $0\initial[0:0] - attribute \src "libresoc.v:101472.3-101490.6" + attribute \src "libresoc.v:101268.3-101286.6" wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:101491.3-101509.6" + attribute \src "libresoc.v:101287.3-101305.6" wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:101244.3-101262.6" + attribute \src "libresoc.v:101040.3-101058.6" wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:101320.3-101338.6" + attribute \src "libresoc.v:101116.3-101134.6" wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:100978.3-100996.6" + attribute \src "libresoc.v:100774.3-100792.6" wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:100997.3-101015.6" + attribute \src "libresoc.v:100793.3-100811.6" wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:101225.3-101243.6" + attribute \src "libresoc.v:101021.3-101039.6" wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:101301.3-101319.6" + attribute \src "libresoc.v:101097.3-101115.6" wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:101377.3-101395.6" + attribute \src "libresoc.v:101173.3-101191.6" wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:100959.3-100977.6" + attribute \src "libresoc.v:100755.3-100773.6" wire width 14 $1\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:101510.3-101528.6" + attribute \src "libresoc.v:101306.3-101324.6" wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:101529.3-101547.6" + attribute \src "libresoc.v:101325.3-101343.6" wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:101548.3-101566.6" + attribute \src "libresoc.v:101344.3-101362.6" wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:101168.3-101186.6" + attribute \src "libresoc.v:100964.3-100982.6" wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:101263.3-101281.6" + attribute \src "libresoc.v:101059.3-101077.6" wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:101282.3-101300.6" + attribute \src "libresoc.v:101078.3-101096.6" wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:101396.3-101414.6" + attribute \src "libresoc.v:101192.3-101210.6" wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:101149.3-101167.6" + attribute \src "libresoc.v:100945.3-100963.6" wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:101434.3-101452.6" + attribute \src "libresoc.v:101230.3-101248.6" wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:101567.3-101585.6" + attribute \src "libresoc.v:101363.3-101381.6" wire width 3 $1\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:101206.3-101224.6" + attribute \src "libresoc.v:101002.3-101020.6" wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:101358.3-101376.6" + attribute \src "libresoc.v:101154.3-101172.6" wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:101453.3-101471.6" + attribute \src "libresoc.v:101249.3-101267.6" wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:101415.3-101433.6" + attribute \src "libresoc.v:101211.3-101229.6" wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:101339.3-101357.6" + attribute \src "libresoc.v:101135.3-101153.6" wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:101111.3-101129.6" + attribute \src "libresoc.v:100907.3-100925.6" wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:101130.3-101148.6" + attribute \src "libresoc.v:100926.3-100944.6" wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:101016.3-101034.6" + attribute \src "libresoc.v:100812.3-100830.6" wire width 3 $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:101035.3-101053.6" + attribute \src "libresoc.v:100831.3-100849.6" wire width 3 $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:101054.3-101072.6" + attribute \src "libresoc.v:100850.3-100868.6" wire width 3 $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:101092.3-101110.6" + attribute \src "libresoc.v:100888.3-100906.6" wire width 3 $1\dec31_dec_sub19_sv_out2[2:0] - attribute \src "libresoc.v:101073.3-101091.6" + attribute \src "libresoc.v:100869.3-100887.6" wire width 3 $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:101187.3-101205.6" + attribute \src "libresoc.v:100983.3-101001.6" wire width 2 $1\dec31_dec_sub19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -157200,28 +156996,28 @@ module \dec31_dec_sub19 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub19_upd - attribute \src "libresoc.v:100611.7-100611.15" + attribute \src "libresoc.v:100407.7-100407.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:100611.7-100611.20" - process $proc$libresoc.v:100611$4072 + attribute \src "libresoc.v:100407.7-100407.20" + process $proc$libresoc.v:100407$4072 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:100959.3-100977.6" - process $proc$libresoc.v:100959$4039 + attribute \src "libresoc.v:100755.3-100773.6" + process $proc$libresoc.v:100755$4039 assign { } { } assign { } { } assign $0\dec31_dec_sub19_function_unit[13:0] $1\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:100960.5-100960.29" + attribute \src "libresoc.v:100756.5-100756.29" switch \initial - attribute \src "libresoc.v:100960.9-100960.17" + attribute \src "libresoc.v:100756.9-100756.17" case 1'1 case end @@ -157249,14 +157045,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[13:0] end - attribute \src "libresoc.v:100978.3-100996.6" - process $proc$libresoc.v:100978$4040 + attribute \src "libresoc.v:100774.3-100792.6" + process $proc$libresoc.v:100774$4040 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:100979.5-100979.29" + attribute \src "libresoc.v:100775.5-100775.29" switch \initial - attribute \src "libresoc.v:100979.9-100979.17" + attribute \src "libresoc.v:100775.9-100775.17" case 1'1 case end @@ -157284,14 +157080,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:100997.3-101015.6" - process $proc$libresoc.v:100997$4041 + attribute \src "libresoc.v:100793.3-100811.6" + process $proc$libresoc.v:100793$4041 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:100998.5-100998.29" + attribute \src "libresoc.v:100794.5-100794.29" switch \initial - attribute \src "libresoc.v:100998.9-100998.17" + attribute \src "libresoc.v:100794.9-100794.17" case 1'1 case end @@ -157319,14 +157115,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:101016.3-101034.6" - process $proc$libresoc.v:101016$4042 + attribute \src "libresoc.v:100812.3-100830.6" + process $proc$libresoc.v:100812$4042 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:101017.5-101017.29" + attribute \src "libresoc.v:100813.5-100813.29" switch \initial - attribute \src "libresoc.v:101017.9-101017.17" + attribute \src "libresoc.v:100813.9-100813.17" case 1'1 case end @@ -157354,14 +157150,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] end - attribute \src "libresoc.v:101035.3-101053.6" - process $proc$libresoc.v:101035$4043 + attribute \src "libresoc.v:100831.3-100849.6" + process $proc$libresoc.v:100831$4043 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:101036.5-101036.29" + attribute \src "libresoc.v:100832.5-100832.29" switch \initial - attribute \src "libresoc.v:101036.9-101036.17" + attribute \src "libresoc.v:100832.9-100832.17" case 1'1 case end @@ -157389,14 +157185,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] end - attribute \src "libresoc.v:101054.3-101072.6" - process $proc$libresoc.v:101054$4044 + attribute \src "libresoc.v:100850.3-100868.6" + process $proc$libresoc.v:100850$4044 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:101055.5-101055.29" + attribute \src "libresoc.v:100851.5-100851.29" switch \initial - attribute \src "libresoc.v:101055.9-101055.17" + attribute \src "libresoc.v:100851.9-100851.17" case 1'1 case end @@ -157424,14 +157220,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] end - attribute \src "libresoc.v:101073.3-101091.6" - process $proc$libresoc.v:101073$4045 + attribute \src "libresoc.v:100869.3-100887.6" + process $proc$libresoc.v:100869$4045 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:101074.5-101074.29" + attribute \src "libresoc.v:100870.5-100870.29" switch \initial - attribute \src "libresoc.v:101074.9-101074.17" + attribute \src "libresoc.v:100870.9-100870.17" case 1'1 case end @@ -157459,14 +157255,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] end - attribute \src "libresoc.v:101092.3-101110.6" - process $proc$libresoc.v:101092$4046 + attribute \src "libresoc.v:100888.3-100906.6" + process $proc$libresoc.v:100888$4046 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_out2[2:0] $1\dec31_dec_sub19_sv_out2[2:0] - attribute \src "libresoc.v:101093.5-101093.29" + attribute \src "libresoc.v:100889.5-100889.29" switch \initial - attribute \src "libresoc.v:101093.9-101093.17" + attribute \src "libresoc.v:100889.9-100889.17" case 1'1 case end @@ -157494,14 +157290,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_out2 $0\dec31_dec_sub19_sv_out2[2:0] end - attribute \src "libresoc.v:101111.3-101129.6" - process $proc$libresoc.v:101111$4047 + attribute \src "libresoc.v:100907.3-100925.6" + process $proc$libresoc.v:100907$4047 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:101112.5-101112.29" + attribute \src "libresoc.v:100908.5-100908.29" switch \initial - attribute \src "libresoc.v:101112.9-101112.17" + attribute \src "libresoc.v:100908.9-100908.17" case 1'1 case end @@ -157529,14 +157325,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] end - attribute \src "libresoc.v:101130.3-101148.6" - process $proc$libresoc.v:101130$4048 + attribute \src "libresoc.v:100926.3-100944.6" + process $proc$libresoc.v:100926$4048 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:101131.5-101131.29" + attribute \src "libresoc.v:100927.5-100927.29" switch \initial - attribute \src "libresoc.v:101131.9-101131.17" + attribute \src "libresoc.v:100927.9-100927.17" case 1'1 case end @@ -157564,14 +157360,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0] end - attribute \src "libresoc.v:101149.3-101167.6" - process $proc$libresoc.v:101149$4049 + attribute \src "libresoc.v:100945.3-100963.6" + process $proc$libresoc.v:100945$4049 assign { } { } assign { } { } assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:101150.5-101150.29" + attribute \src "libresoc.v:100946.5-100946.29" switch \initial - attribute \src "libresoc.v:101150.9-101150.17" + attribute \src "libresoc.v:100946.9-100946.17" case 1'1 case end @@ -157599,14 +157395,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] end - attribute \src "libresoc.v:101168.3-101186.6" - process $proc$libresoc.v:101168$4050 + attribute \src "libresoc.v:100964.3-100982.6" + process $proc$libresoc.v:100964$4050 assign { } { } assign { } { } assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:101169.5-101169.29" + attribute \src "libresoc.v:100965.5-100965.29" switch \initial - attribute \src "libresoc.v:101169.9-101169.17" + attribute \src "libresoc.v:100965.9-100965.17" case 1'1 case end @@ -157634,14 +157430,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:101187.3-101205.6" - process $proc$libresoc.v:101187$4051 + attribute \src "libresoc.v:100983.3-101001.6" + process $proc$libresoc.v:100983$4051 assign { } { } assign { } { } assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:101188.5-101188.29" + attribute \src "libresoc.v:100984.5-100984.29" switch \initial - attribute \src "libresoc.v:101188.9-101188.17" + attribute \src "libresoc.v:100984.9-100984.17" case 1'1 case end @@ -157669,14 +157465,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] end - attribute \src "libresoc.v:101206.3-101224.6" - process $proc$libresoc.v:101206$4052 + attribute \src "libresoc.v:101002.3-101020.6" + process $proc$libresoc.v:101002$4052 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:101207.5-101207.29" + attribute \src "libresoc.v:101003.5-101003.29" switch \initial - attribute \src "libresoc.v:101207.9-101207.17" + attribute \src "libresoc.v:101003.9-101003.17" case 1'1 case end @@ -157704,14 +157500,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] end - attribute \src "libresoc.v:101225.3-101243.6" - process $proc$libresoc.v:101225$4053 + attribute \src "libresoc.v:101021.3-101039.6" + process $proc$libresoc.v:101021$4053 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:101226.5-101226.29" + attribute \src "libresoc.v:101022.5-101022.29" switch \initial - attribute \src "libresoc.v:101226.9-101226.17" + attribute \src "libresoc.v:101022.9-101022.17" case 1'1 case end @@ -157739,14 +157535,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] end - attribute \src "libresoc.v:101244.3-101262.6" - process $proc$libresoc.v:101244$4054 + attribute \src "libresoc.v:101040.3-101058.6" + process $proc$libresoc.v:101040$4054 assign { } { } assign { } { } assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:101245.5-101245.29" + attribute \src "libresoc.v:101041.5-101041.29" switch \initial - attribute \src "libresoc.v:101245.9-101245.17" + attribute \src "libresoc.v:101041.9-101041.17" case 1'1 case end @@ -157774,14 +157570,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] end - attribute \src "libresoc.v:101263.3-101281.6" - process $proc$libresoc.v:101263$4055 + attribute \src "libresoc.v:101059.3-101077.6" + process $proc$libresoc.v:101059$4055 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:101264.5-101264.29" + attribute \src "libresoc.v:101060.5-101060.29" switch \initial - attribute \src "libresoc.v:101264.9-101264.17" + attribute \src "libresoc.v:101060.9-101060.17" case 1'1 case end @@ -157809,14 +157605,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] end - attribute \src "libresoc.v:101282.3-101300.6" - process $proc$libresoc.v:101282$4056 + attribute \src "libresoc.v:101078.3-101096.6" + process $proc$libresoc.v:101078$4056 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:101283.5-101283.29" + attribute \src "libresoc.v:101079.5-101079.29" switch \initial - attribute \src "libresoc.v:101283.9-101283.17" + attribute \src "libresoc.v:101079.9-101079.17" case 1'1 case end @@ -157844,14 +157640,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] end - attribute \src "libresoc.v:101301.3-101319.6" - process $proc$libresoc.v:101301$4057 + attribute \src "libresoc.v:101097.3-101115.6" + process $proc$libresoc.v:101097$4057 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:101302.5-101302.29" + attribute \src "libresoc.v:101098.5-101098.29" switch \initial - attribute \src "libresoc.v:101302.9-101302.17" + attribute \src "libresoc.v:101098.9-101098.17" case 1'1 case end @@ -157879,14 +157675,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] end - attribute \src "libresoc.v:101320.3-101338.6" - process $proc$libresoc.v:101320$4058 + attribute \src "libresoc.v:101116.3-101134.6" + process $proc$libresoc.v:101116$4058 assign { } { } assign { } { } assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:101321.5-101321.29" + attribute \src "libresoc.v:101117.5-101117.29" switch \initial - attribute \src "libresoc.v:101321.9-101321.17" + attribute \src "libresoc.v:101117.9-101117.17" case 1'1 case end @@ -157914,14 +157710,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] end - attribute \src "libresoc.v:101339.3-101357.6" - process $proc$libresoc.v:101339$4059 + attribute \src "libresoc.v:101135.3-101153.6" + process $proc$libresoc.v:101135$4059 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:101340.5-101340.29" + attribute \src "libresoc.v:101136.5-101136.29" switch \initial - attribute \src "libresoc.v:101340.9-101340.17" + attribute \src "libresoc.v:101136.9-101136.17" case 1'1 case end @@ -157949,14 +157745,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] end - attribute \src "libresoc.v:101358.3-101376.6" - process $proc$libresoc.v:101358$4060 + attribute \src "libresoc.v:101154.3-101172.6" + process $proc$libresoc.v:101154$4060 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:101359.5-101359.29" + attribute \src "libresoc.v:101155.5-101155.29" switch \initial - attribute \src "libresoc.v:101359.9-101359.17" + attribute \src "libresoc.v:101155.9-101155.17" case 1'1 case end @@ -157984,14 +157780,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] end - attribute \src "libresoc.v:101377.3-101395.6" - process $proc$libresoc.v:101377$4061 + attribute \src "libresoc.v:101173.3-101191.6" + process $proc$libresoc.v:101173$4061 assign { } { } assign { } { } assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:101378.5-101378.29" + attribute \src "libresoc.v:101174.5-101174.29" switch \initial - attribute \src "libresoc.v:101378.9-101378.17" + attribute \src "libresoc.v:101174.9-101174.17" case 1'1 case end @@ -158019,14 +157815,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] end - attribute \src "libresoc.v:101396.3-101414.6" - process $proc$libresoc.v:101396$4062 + attribute \src "libresoc.v:101192.3-101210.6" + process $proc$libresoc.v:101192$4062 assign { } { } assign { } { } assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:101397.5-101397.29" + attribute \src "libresoc.v:101193.5-101193.29" switch \initial - attribute \src "libresoc.v:101397.9-101397.17" + attribute \src "libresoc.v:101193.9-101193.17" case 1'1 case end @@ -158054,14 +157850,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] end - attribute \src "libresoc.v:101415.3-101433.6" - process $proc$libresoc.v:101415$4063 + attribute \src "libresoc.v:101211.3-101229.6" + process $proc$libresoc.v:101211$4063 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:101416.5-101416.29" + attribute \src "libresoc.v:101212.5-101212.29" switch \initial - attribute \src "libresoc.v:101416.9-101416.17" + attribute \src "libresoc.v:101212.9-101212.17" case 1'1 case end @@ -158089,14 +157885,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] end - attribute \src "libresoc.v:101434.3-101452.6" - process $proc$libresoc.v:101434$4064 + attribute \src "libresoc.v:101230.3-101248.6" + process $proc$libresoc.v:101230$4064 assign { } { } assign { } { } assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:101435.5-101435.29" + attribute \src "libresoc.v:101231.5-101231.29" switch \initial - attribute \src "libresoc.v:101435.9-101435.17" + attribute \src "libresoc.v:101231.9-101231.17" case 1'1 case end @@ -158124,14 +157920,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] end - attribute \src "libresoc.v:101453.3-101471.6" - process $proc$libresoc.v:101453$4065 + attribute \src "libresoc.v:101249.3-101267.6" + process $proc$libresoc.v:101249$4065 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:101454.5-101454.29" + attribute \src "libresoc.v:101250.5-101250.29" switch \initial - attribute \src "libresoc.v:101454.9-101454.17" + attribute \src "libresoc.v:101250.9-101250.17" case 1'1 case end @@ -158159,14 +157955,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] end - attribute \src "libresoc.v:101472.3-101490.6" - process $proc$libresoc.v:101472$4066 + attribute \src "libresoc.v:101268.3-101286.6" + process $proc$libresoc.v:101268$4066 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:101473.5-101473.29" + attribute \src "libresoc.v:101269.5-101269.29" switch \initial - attribute \src "libresoc.v:101473.9-101473.17" + attribute \src "libresoc.v:101269.9-101269.17" case 1'1 case end @@ -158194,14 +157990,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0] end - attribute \src "libresoc.v:101491.3-101509.6" - process $proc$libresoc.v:101491$4067 + attribute \src "libresoc.v:101287.3-101305.6" + process $proc$libresoc.v:101287$4067 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:101492.5-101492.29" + attribute \src "libresoc.v:101288.5-101288.29" switch \initial - attribute \src "libresoc.v:101492.9-101492.17" + attribute \src "libresoc.v:101288.9-101288.17" case 1'1 case end @@ -158229,14 +158025,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0] end - attribute \src "libresoc.v:101510.3-101528.6" - process $proc$libresoc.v:101510$4068 + attribute \src "libresoc.v:101306.3-101324.6" + process $proc$libresoc.v:101306$4068 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:101511.5-101511.29" + attribute \src "libresoc.v:101307.5-101307.29" switch \initial - attribute \src "libresoc.v:101511.9-101511.17" + attribute \src "libresoc.v:101307.9-101307.17" case 1'1 case end @@ -158264,14 +158060,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] end - attribute \src "libresoc.v:101529.3-101547.6" - process $proc$libresoc.v:101529$4069 + attribute \src "libresoc.v:101325.3-101343.6" + process $proc$libresoc.v:101325$4069 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:101530.5-101530.29" + attribute \src "libresoc.v:101326.5-101326.29" switch \initial - attribute \src "libresoc.v:101530.9-101530.17" + attribute \src "libresoc.v:101326.9-101326.17" case 1'1 case end @@ -158299,14 +158095,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] end - attribute \src "libresoc.v:101548.3-101566.6" - process $proc$libresoc.v:101548$4070 + attribute \src "libresoc.v:101344.3-101362.6" + process $proc$libresoc.v:101344$4070 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:101549.5-101549.29" + attribute \src "libresoc.v:101345.5-101345.29" switch \initial - attribute \src "libresoc.v:101549.9-101549.17" + attribute \src "libresoc.v:101345.9-101345.17" case 1'1 case end @@ -158334,14 +158130,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] end - attribute \src "libresoc.v:101567.3-101585.6" - process $proc$libresoc.v:101567$4071 + attribute \src "libresoc.v:101363.3-101381.6" + process $proc$libresoc.v:101363$4071 assign { } { } assign { } { } assign $0\dec31_dec_sub19_out_sel[2:0] $1\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:101568.5-101568.29" + attribute \src "libresoc.v:101364.5-101364.29" switch \initial - attribute \src "libresoc.v:101568.9-101568.17" + attribute \src "libresoc.v:101364.9-101364.17" case 1'1 case end @@ -158371,144 +158167,144 @@ module \dec31_dec_sub19 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:101591.1-102766.10" +attribute \src "libresoc.v:101387.1-102562.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" attribute \generator "nMigen" module \dec31_dec_sub20 - attribute \src "libresoc.v:102615.3-102639.6" + attribute \src "libresoc.v:102411.3-102435.6" wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:102640.3-102664.6" + attribute \src "libresoc.v:102436.3-102460.6" wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:102315.3-102339.6" + attribute \src "libresoc.v:102111.3-102135.6" wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:102415.3-102439.6" + attribute \src "libresoc.v:102211.3-102235.6" wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:101965.3-101989.6" + attribute \src "libresoc.v:101761.3-101785.6" wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:101990.3-102014.6" + attribute \src "libresoc.v:101786.3-101810.6" wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:102290.3-102314.6" + attribute \src "libresoc.v:102086.3-102110.6" wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:102390.3-102414.6" + attribute \src "libresoc.v:102186.3-102210.6" wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:102490.3-102514.6" + attribute \src "libresoc.v:102286.3-102310.6" wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:101940.3-101964.6" + attribute \src "libresoc.v:101736.3-101760.6" wire width 14 $0\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:102665.3-102689.6" + attribute \src "libresoc.v:102461.3-102485.6" wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:102690.3-102714.6" + attribute \src "libresoc.v:102486.3-102510.6" wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:102715.3-102739.6" + attribute \src "libresoc.v:102511.3-102535.6" wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:102215.3-102239.6" + attribute \src "libresoc.v:102011.3-102035.6" wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:102340.3-102364.6" + attribute \src "libresoc.v:102136.3-102160.6" wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:102365.3-102389.6" + attribute \src "libresoc.v:102161.3-102185.6" wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:102515.3-102539.6" + attribute \src "libresoc.v:102311.3-102335.6" wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:102190.3-102214.6" + attribute \src "libresoc.v:101986.3-102010.6" wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:102565.3-102589.6" + attribute \src "libresoc.v:102361.3-102385.6" wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:102740.3-102764.6" + attribute \src "libresoc.v:102536.3-102560.6" wire width 3 $0\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:102265.3-102289.6" + attribute \src "libresoc.v:102061.3-102085.6" wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:102465.3-102489.6" + attribute \src "libresoc.v:102261.3-102285.6" wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:102590.3-102614.6" + attribute \src "libresoc.v:102386.3-102410.6" wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:102540.3-102564.6" + attribute \src "libresoc.v:102336.3-102360.6" wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:102440.3-102464.6" + attribute \src "libresoc.v:102236.3-102260.6" wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:102140.3-102164.6" + attribute \src "libresoc.v:101936.3-101960.6" wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:102165.3-102189.6" + attribute \src "libresoc.v:101961.3-101985.6" wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:102015.3-102039.6" + attribute \src "libresoc.v:101811.3-101835.6" wire width 3 $0\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:102040.3-102064.6" + attribute \src "libresoc.v:101836.3-101860.6" wire width 3 $0\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:102065.3-102089.6" + attribute \src "libresoc.v:101861.3-101885.6" wire width 3 $0\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:102115.3-102139.6" + attribute \src "libresoc.v:101911.3-101935.6" wire width 3 $0\dec31_dec_sub20_sv_out2[2:0] - attribute \src "libresoc.v:102090.3-102114.6" + attribute \src "libresoc.v:101886.3-101910.6" wire width 3 $0\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:102240.3-102264.6" + attribute \src "libresoc.v:102036.3-102060.6" wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:101592.7-101592.20" + attribute \src "libresoc.v:101388.7-101388.20" wire $0\initial[0:0] - attribute \src "libresoc.v:102615.3-102639.6" + attribute \src "libresoc.v:102411.3-102435.6" wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:102640.3-102664.6" + attribute \src "libresoc.v:102436.3-102460.6" wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:102315.3-102339.6" + attribute \src "libresoc.v:102111.3-102135.6" wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:102415.3-102439.6" + attribute \src "libresoc.v:102211.3-102235.6" wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:101965.3-101989.6" + attribute \src "libresoc.v:101761.3-101785.6" wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:101990.3-102014.6" + attribute \src "libresoc.v:101786.3-101810.6" wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:102290.3-102314.6" + attribute \src "libresoc.v:102086.3-102110.6" wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:102390.3-102414.6" + attribute \src "libresoc.v:102186.3-102210.6" wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:102490.3-102514.6" + attribute \src "libresoc.v:102286.3-102310.6" wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:101940.3-101964.6" + attribute \src "libresoc.v:101736.3-101760.6" wire width 14 $1\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:102665.3-102689.6" + attribute \src "libresoc.v:102461.3-102485.6" wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:102690.3-102714.6" + attribute \src "libresoc.v:102486.3-102510.6" wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:102715.3-102739.6" + attribute \src "libresoc.v:102511.3-102535.6" wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:102215.3-102239.6" + attribute \src "libresoc.v:102011.3-102035.6" wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:102340.3-102364.6" + attribute \src "libresoc.v:102136.3-102160.6" wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:102365.3-102389.6" + attribute \src "libresoc.v:102161.3-102185.6" wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:102515.3-102539.6" + attribute \src "libresoc.v:102311.3-102335.6" wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:102190.3-102214.6" + attribute \src "libresoc.v:101986.3-102010.6" wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:102565.3-102589.6" + attribute \src "libresoc.v:102361.3-102385.6" wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:102740.3-102764.6" + attribute \src "libresoc.v:102536.3-102560.6" wire width 3 $1\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:102265.3-102289.6" + attribute \src "libresoc.v:102061.3-102085.6" wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:102465.3-102489.6" + attribute \src "libresoc.v:102261.3-102285.6" wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:102590.3-102614.6" + attribute \src "libresoc.v:102386.3-102410.6" wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:102540.3-102564.6" + attribute \src "libresoc.v:102336.3-102360.6" wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:102440.3-102464.6" + attribute \src "libresoc.v:102236.3-102260.6" wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:102140.3-102164.6" + attribute \src "libresoc.v:101936.3-101960.6" wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:102165.3-102189.6" + attribute \src "libresoc.v:101961.3-101985.6" wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:102015.3-102039.6" + attribute \src "libresoc.v:101811.3-101835.6" wire width 3 $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:102040.3-102064.6" + attribute \src "libresoc.v:101836.3-101860.6" wire width 3 $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:102065.3-102089.6" + attribute \src "libresoc.v:101861.3-101885.6" wire width 3 $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:102115.3-102139.6" + attribute \src "libresoc.v:101911.3-101935.6" wire width 3 $1\dec31_dec_sub20_sv_out2[2:0] - attribute \src "libresoc.v:102090.3-102114.6" + attribute \src "libresoc.v:101886.3-101910.6" wire width 3 $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:102240.3-102264.6" + attribute \src "libresoc.v:102036.3-102060.6" wire width 2 $1\dec31_dec_sub20_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -158820,28 +158616,28 @@ module \dec31_dec_sub20 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub20_upd - attribute \src "libresoc.v:101592.7-101592.15" + attribute \src "libresoc.v:101388.7-101388.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:101592.7-101592.20" - process $proc$libresoc.v:101592$4106 + attribute \src "libresoc.v:101388.7-101388.20" + process $proc$libresoc.v:101388$4106 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:101940.3-101964.6" - process $proc$libresoc.v:101940$4073 + attribute \src "libresoc.v:101736.3-101760.6" + process $proc$libresoc.v:101736$4073 assign { } { } assign { } { } assign $0\dec31_dec_sub20_function_unit[13:0] $1\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:101941.5-101941.29" + attribute \src "libresoc.v:101737.5-101737.29" switch \initial - attribute \src "libresoc.v:101941.9-101941.17" + attribute \src "libresoc.v:101737.9-101737.17" case 1'1 case end @@ -158877,14 +158673,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[13:0] end - attribute \src "libresoc.v:101965.3-101989.6" - process $proc$libresoc.v:101965$4074 + attribute \src "libresoc.v:101761.3-101785.6" + process $proc$libresoc.v:101761$4074 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:101966.5-101966.29" + attribute \src "libresoc.v:101762.5-101762.29" switch \initial - attribute \src "libresoc.v:101966.9-101966.17" + attribute \src "libresoc.v:101762.9-101762.17" case 1'1 case end @@ -158920,14 +158716,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] end - attribute \src "libresoc.v:101990.3-102014.6" - process $proc$libresoc.v:101990$4075 + attribute \src "libresoc.v:101786.3-101810.6" + process $proc$libresoc.v:101786$4075 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:101991.5-101991.29" + attribute \src "libresoc.v:101787.5-101787.29" switch \initial - attribute \src "libresoc.v:101991.9-101991.17" + attribute \src "libresoc.v:101787.9-101787.17" case 1'1 case end @@ -158963,14 +158759,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] end - attribute \src "libresoc.v:102015.3-102039.6" - process $proc$libresoc.v:102015$4076 + attribute \src "libresoc.v:101811.3-101835.6" + process $proc$libresoc.v:101811$4076 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:102016.5-102016.29" + attribute \src "libresoc.v:101812.5-101812.29" switch \initial - attribute \src "libresoc.v:102016.9-102016.17" + attribute \src "libresoc.v:101812.9-101812.17" case 1'1 case end @@ -159006,14 +158802,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0] end - attribute \src "libresoc.v:102040.3-102064.6" - process $proc$libresoc.v:102040$4077 + attribute \src "libresoc.v:101836.3-101860.6" + process $proc$libresoc.v:101836$4077 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:102041.5-102041.29" + attribute \src "libresoc.v:101837.5-101837.29" switch \initial - attribute \src "libresoc.v:102041.9-102041.17" + attribute \src "libresoc.v:101837.9-101837.17" case 1'1 case end @@ -159049,14 +158845,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0] end - attribute \src "libresoc.v:102065.3-102089.6" - process $proc$libresoc.v:102065$4078 + attribute \src "libresoc.v:101861.3-101885.6" + process $proc$libresoc.v:101861$4078 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:102066.5-102066.29" + attribute \src "libresoc.v:101862.5-101862.29" switch \initial - attribute \src "libresoc.v:102066.9-102066.17" + attribute \src "libresoc.v:101862.9-101862.17" case 1'1 case end @@ -159092,14 +158888,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0] end - attribute \src "libresoc.v:102090.3-102114.6" - process $proc$libresoc.v:102090$4079 + attribute \src "libresoc.v:101886.3-101910.6" + process $proc$libresoc.v:101886$4079 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:102091.5-102091.29" + attribute \src "libresoc.v:101887.5-101887.29" switch \initial - attribute \src "libresoc.v:102091.9-102091.17" + attribute \src "libresoc.v:101887.9-101887.17" case 1'1 case end @@ -159135,14 +158931,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0] end - attribute \src "libresoc.v:102115.3-102139.6" - process $proc$libresoc.v:102115$4080 + attribute \src "libresoc.v:101911.3-101935.6" + process $proc$libresoc.v:101911$4080 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out2[2:0] $1\dec31_dec_sub20_sv_out2[2:0] - attribute \src "libresoc.v:102116.5-102116.29" + attribute \src "libresoc.v:101912.5-101912.29" switch \initial - attribute \src "libresoc.v:102116.9-102116.17" + attribute \src "libresoc.v:101912.9-101912.17" case 1'1 case end @@ -159178,14 +158974,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_out2 $0\dec31_dec_sub20_sv_out2[2:0] end - attribute \src "libresoc.v:102140.3-102164.6" - process $proc$libresoc.v:102140$4081 + attribute \src "libresoc.v:101936.3-101960.6" + process $proc$libresoc.v:101936$4081 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:102141.5-102141.29" + attribute \src "libresoc.v:101937.5-101937.29" switch \initial - attribute \src "libresoc.v:102141.9-102141.17" + attribute \src "libresoc.v:101937.9-101937.17" case 1'1 case end @@ -159221,14 +159017,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0] end - attribute \src "libresoc.v:102165.3-102189.6" - process $proc$libresoc.v:102165$4082 + attribute \src "libresoc.v:101961.3-101985.6" + process $proc$libresoc.v:101961$4082 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:102166.5-102166.29" + attribute \src "libresoc.v:101962.5-101962.29" switch \initial - attribute \src "libresoc.v:102166.9-102166.17" + attribute \src "libresoc.v:101962.9-101962.17" case 1'1 case end @@ -159264,14 +159060,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0] end - attribute \src "libresoc.v:102190.3-102214.6" - process $proc$libresoc.v:102190$4083 + attribute \src "libresoc.v:101986.3-102010.6" + process $proc$libresoc.v:101986$4083 assign { } { } assign { } { } assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:102191.5-102191.29" + attribute \src "libresoc.v:101987.5-101987.29" switch \initial - attribute \src "libresoc.v:102191.9-102191.17" + attribute \src "libresoc.v:101987.9-101987.17" case 1'1 case end @@ -159307,14 +159103,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] end - attribute \src "libresoc.v:102215.3-102239.6" - process $proc$libresoc.v:102215$4084 + attribute \src "libresoc.v:102011.3-102035.6" + process $proc$libresoc.v:102011$4084 assign { } { } assign { } { } assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:102216.5-102216.29" + attribute \src "libresoc.v:102012.5-102012.29" switch \initial - attribute \src "libresoc.v:102216.9-102216.17" + attribute \src "libresoc.v:102012.9-102012.17" case 1'1 case end @@ -159350,14 +159146,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] end - attribute \src "libresoc.v:102240.3-102264.6" - process $proc$libresoc.v:102240$4085 + attribute \src "libresoc.v:102036.3-102060.6" + process $proc$libresoc.v:102036$4085 assign { } { } assign { } { } assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:102241.5-102241.29" + attribute \src "libresoc.v:102037.5-102037.29" switch \initial - attribute \src "libresoc.v:102241.9-102241.17" + attribute \src "libresoc.v:102037.9-102037.17" case 1'1 case end @@ -159393,14 +159189,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] end - attribute \src "libresoc.v:102265.3-102289.6" - process $proc$libresoc.v:102265$4086 + attribute \src "libresoc.v:102061.3-102085.6" + process $proc$libresoc.v:102061$4086 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:102266.5-102266.29" + attribute \src "libresoc.v:102062.5-102062.29" switch \initial - attribute \src "libresoc.v:102266.9-102266.17" + attribute \src "libresoc.v:102062.9-102062.17" case 1'1 case end @@ -159436,14 +159232,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] end - attribute \src "libresoc.v:102290.3-102314.6" - process $proc$libresoc.v:102290$4087 + attribute \src "libresoc.v:102086.3-102110.6" + process $proc$libresoc.v:102086$4087 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:102291.5-102291.29" + attribute \src "libresoc.v:102087.5-102087.29" switch \initial - attribute \src "libresoc.v:102291.9-102291.17" + attribute \src "libresoc.v:102087.9-102087.17" case 1'1 case end @@ -159479,14 +159275,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] end - attribute \src "libresoc.v:102315.3-102339.6" - process $proc$libresoc.v:102315$4088 + attribute \src "libresoc.v:102111.3-102135.6" + process $proc$libresoc.v:102111$4088 assign { } { } assign { } { } assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:102316.5-102316.29" + attribute \src "libresoc.v:102112.5-102112.29" switch \initial - attribute \src "libresoc.v:102316.9-102316.17" + attribute \src "libresoc.v:102112.9-102112.17" case 1'1 case end @@ -159522,14 +159318,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] end - attribute \src "libresoc.v:102340.3-102364.6" - process $proc$libresoc.v:102340$4089 + attribute \src "libresoc.v:102136.3-102160.6" + process $proc$libresoc.v:102136$4089 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:102341.5-102341.29" + attribute \src "libresoc.v:102137.5-102137.29" switch \initial - attribute \src "libresoc.v:102341.9-102341.17" + attribute \src "libresoc.v:102137.9-102137.17" case 1'1 case end @@ -159565,14 +159361,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] end - attribute \src "libresoc.v:102365.3-102389.6" - process $proc$libresoc.v:102365$4090 + attribute \src "libresoc.v:102161.3-102185.6" + process $proc$libresoc.v:102161$4090 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:102366.5-102366.29" + attribute \src "libresoc.v:102162.5-102162.29" switch \initial - attribute \src "libresoc.v:102366.9-102366.17" + attribute \src "libresoc.v:102162.9-102162.17" case 1'1 case end @@ -159608,14 +159404,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] end - attribute \src "libresoc.v:102390.3-102414.6" - process $proc$libresoc.v:102390$4091 + attribute \src "libresoc.v:102186.3-102210.6" + process $proc$libresoc.v:102186$4091 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:102391.5-102391.29" + attribute \src "libresoc.v:102187.5-102187.29" switch \initial - attribute \src "libresoc.v:102391.9-102391.17" + attribute \src "libresoc.v:102187.9-102187.17" case 1'1 case end @@ -159651,14 +159447,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] end - attribute \src "libresoc.v:102415.3-102439.6" - process $proc$libresoc.v:102415$4092 + attribute \src "libresoc.v:102211.3-102235.6" + process $proc$libresoc.v:102211$4092 assign { } { } assign { } { } assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:102416.5-102416.29" + attribute \src "libresoc.v:102212.5-102212.29" switch \initial - attribute \src "libresoc.v:102416.9-102416.17" + attribute \src "libresoc.v:102212.9-102212.17" case 1'1 case end @@ -159694,14 +159490,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] end - attribute \src "libresoc.v:102440.3-102464.6" - process $proc$libresoc.v:102440$4093 + attribute \src "libresoc.v:102236.3-102260.6" + process $proc$libresoc.v:102236$4093 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:102441.5-102441.29" + attribute \src "libresoc.v:102237.5-102237.29" switch \initial - attribute \src "libresoc.v:102441.9-102441.17" + attribute \src "libresoc.v:102237.9-102237.17" case 1'1 case end @@ -159737,14 +159533,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] end - attribute \src "libresoc.v:102465.3-102489.6" - process $proc$libresoc.v:102465$4094 + attribute \src "libresoc.v:102261.3-102285.6" + process $proc$libresoc.v:102261$4094 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:102466.5-102466.29" + attribute \src "libresoc.v:102262.5-102262.29" switch \initial - attribute \src "libresoc.v:102466.9-102466.17" + attribute \src "libresoc.v:102262.9-102262.17" case 1'1 case end @@ -159780,14 +159576,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] end - attribute \src "libresoc.v:102490.3-102514.6" - process $proc$libresoc.v:102490$4095 + attribute \src "libresoc.v:102286.3-102310.6" + process $proc$libresoc.v:102286$4095 assign { } { } assign { } { } assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:102491.5-102491.29" + attribute \src "libresoc.v:102287.5-102287.29" switch \initial - attribute \src "libresoc.v:102491.9-102491.17" + attribute \src "libresoc.v:102287.9-102287.17" case 1'1 case end @@ -159823,14 +159619,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] end - attribute \src "libresoc.v:102515.3-102539.6" - process $proc$libresoc.v:102515$4096 + attribute \src "libresoc.v:102311.3-102335.6" + process $proc$libresoc.v:102311$4096 assign { } { } assign { } { } assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:102516.5-102516.29" + attribute \src "libresoc.v:102312.5-102312.29" switch \initial - attribute \src "libresoc.v:102516.9-102516.17" + attribute \src "libresoc.v:102312.9-102312.17" case 1'1 case end @@ -159866,14 +159662,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] end - attribute \src "libresoc.v:102540.3-102564.6" - process $proc$libresoc.v:102540$4097 + attribute \src "libresoc.v:102336.3-102360.6" + process $proc$libresoc.v:102336$4097 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:102541.5-102541.29" + attribute \src "libresoc.v:102337.5-102337.29" switch \initial - attribute \src "libresoc.v:102541.9-102541.17" + attribute \src "libresoc.v:102337.9-102337.17" case 1'1 case end @@ -159909,14 +159705,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] end - attribute \src "libresoc.v:102565.3-102589.6" - process $proc$libresoc.v:102565$4098 + attribute \src "libresoc.v:102361.3-102385.6" + process $proc$libresoc.v:102361$4098 assign { } { } assign { } { } assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:102566.5-102566.29" + attribute \src "libresoc.v:102362.5-102362.29" switch \initial - attribute \src "libresoc.v:102566.9-102566.17" + attribute \src "libresoc.v:102362.9-102362.17" case 1'1 case end @@ -159952,14 +159748,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] end - attribute \src "libresoc.v:102590.3-102614.6" - process $proc$libresoc.v:102590$4099 + attribute \src "libresoc.v:102386.3-102410.6" + process $proc$libresoc.v:102386$4099 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:102591.5-102591.29" + attribute \src "libresoc.v:102387.5-102387.29" switch \initial - attribute \src "libresoc.v:102591.9-102591.17" + attribute \src "libresoc.v:102387.9-102387.17" case 1'1 case end @@ -159995,14 +159791,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] end - attribute \src "libresoc.v:102615.3-102639.6" - process $proc$libresoc.v:102615$4100 + attribute \src "libresoc.v:102411.3-102435.6" + process $proc$libresoc.v:102411$4100 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:102616.5-102616.29" + attribute \src "libresoc.v:102412.5-102412.29" switch \initial - attribute \src "libresoc.v:102616.9-102616.17" + attribute \src "libresoc.v:102412.9-102412.17" case 1'1 case end @@ -160038,14 +159834,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] end - attribute \src "libresoc.v:102640.3-102664.6" - process $proc$libresoc.v:102640$4101 + attribute \src "libresoc.v:102436.3-102460.6" + process $proc$libresoc.v:102436$4101 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:102641.5-102641.29" + attribute \src "libresoc.v:102437.5-102437.29" switch \initial - attribute \src "libresoc.v:102641.9-102641.17" + attribute \src "libresoc.v:102437.9-102437.17" case 1'1 case end @@ -160081,14 +159877,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] end - attribute \src "libresoc.v:102665.3-102689.6" - process $proc$libresoc.v:102665$4102 + attribute \src "libresoc.v:102461.3-102485.6" + process $proc$libresoc.v:102461$4102 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:102666.5-102666.29" + attribute \src "libresoc.v:102462.5-102462.29" switch \initial - attribute \src "libresoc.v:102666.9-102666.17" + attribute \src "libresoc.v:102462.9-102462.17" case 1'1 case end @@ -160124,14 +159920,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] end - attribute \src "libresoc.v:102690.3-102714.6" - process $proc$libresoc.v:102690$4103 + attribute \src "libresoc.v:102486.3-102510.6" + process $proc$libresoc.v:102486$4103 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:102691.5-102691.29" + attribute \src "libresoc.v:102487.5-102487.29" switch \initial - attribute \src "libresoc.v:102691.9-102691.17" + attribute \src "libresoc.v:102487.9-102487.17" case 1'1 case end @@ -160167,14 +159963,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] end - attribute \src "libresoc.v:102715.3-102739.6" - process $proc$libresoc.v:102715$4104 + attribute \src "libresoc.v:102511.3-102535.6" + process $proc$libresoc.v:102511$4104 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:102716.5-102716.29" + attribute \src "libresoc.v:102512.5-102512.29" switch \initial - attribute \src "libresoc.v:102716.9-102716.17" + attribute \src "libresoc.v:102512.9-102512.17" case 1'1 case end @@ -160210,14 +160006,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] end - attribute \src "libresoc.v:102740.3-102764.6" - process $proc$libresoc.v:102740$4105 + attribute \src "libresoc.v:102536.3-102560.6" + process $proc$libresoc.v:102536$4105 assign { } { } assign { } { } assign $0\dec31_dec_sub20_out_sel[2:0] $1\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:102741.5-102741.29" + attribute \src "libresoc.v:102537.5-102537.29" switch \initial - attribute \src "libresoc.v:102741.9-102741.17" + attribute \src "libresoc.v:102537.9-102537.17" case 1'1 case end @@ -160255,144 +160051,144 @@ module \dec31_dec_sub20 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:102770.1-104731.10" +attribute \src "libresoc.v:102566.1-104527.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" attribute \generator "nMigen" module \dec31_dec_sub21 - attribute \src "libresoc.v:104436.3-104484.6" + attribute \src "libresoc.v:104232.3-104280.6" wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:104485.3-104533.6" + attribute \src "libresoc.v:104281.3-104329.6" wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:104393.3-104435.6" + attribute \src "libresoc.v:104189.3-104231.6" wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:104001.3-104049.6" + attribute \src "libresoc.v:103797.3-103845.6" wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:103168.3-103216.6" + attribute \src "libresoc.v:102964.3-103012.6" wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:103217.3-103265.6" + attribute \src "libresoc.v:103013.3-103061.6" wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:103805.3-103853.6" + attribute \src "libresoc.v:103601.3-103649.6" wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:103952.3-104000.6" + attribute \src "libresoc.v:103748.3-103796.6" wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:104197.3-104245.6" + attribute \src "libresoc.v:103993.3-104041.6" wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:103119.3-103167.6" + attribute \src "libresoc.v:102915.3-102963.6" wire width 14 $0\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:104534.3-104582.6" + attribute \src "libresoc.v:104330.3-104378.6" wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:104583.3-104631.6" + attribute \src "libresoc.v:104379.3-104427.6" wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:104632.3-104680.6" + attribute \src "libresoc.v:104428.3-104476.6" wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:103658.3-103706.6" + attribute \src "libresoc.v:103454.3-103502.6" wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:103854.3-103902.6" + attribute \src "libresoc.v:103650.3-103698.6" wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:103903.3-103951.6" + attribute \src "libresoc.v:103699.3-103747.6" wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:104148.3-104196.6" + attribute \src "libresoc.v:103944.3-103992.6" wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:103609.3-103657.6" + attribute \src "libresoc.v:103405.3-103453.6" wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:104295.3-104343.6" + attribute \src "libresoc.v:104091.3-104139.6" wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:104681.3-104729.6" + attribute \src "libresoc.v:104477.3-104525.6" wire width 3 $0\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:103756.3-103804.6" + attribute \src "libresoc.v:103552.3-103600.6" wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:104099.3-104147.6" + attribute \src "libresoc.v:103895.3-103943.6" wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:104344.3-104392.6" + attribute \src "libresoc.v:104140.3-104188.6" wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:104246.3-104294.6" + attribute \src "libresoc.v:104042.3-104090.6" wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:104050.3-104098.6" + attribute \src "libresoc.v:103846.3-103894.6" wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:103511.3-103559.6" + attribute \src "libresoc.v:103307.3-103355.6" wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:103560.3-103608.6" + attribute \src "libresoc.v:103356.3-103404.6" wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:103266.3-103314.6" + attribute \src "libresoc.v:103062.3-103110.6" wire width 3 $0\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:103315.3-103363.6" + attribute \src "libresoc.v:103111.3-103159.6" wire width 3 $0\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:103364.3-103412.6" + attribute \src "libresoc.v:103160.3-103208.6" wire width 3 $0\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:103462.3-103510.6" + attribute \src "libresoc.v:103258.3-103306.6" wire width 3 $0\dec31_dec_sub21_sv_out2[2:0] - attribute \src "libresoc.v:103413.3-103461.6" + attribute \src "libresoc.v:103209.3-103257.6" wire width 3 $0\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:103707.3-103755.6" + attribute \src "libresoc.v:103503.3-103551.6" wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:102771.7-102771.20" + attribute \src "libresoc.v:102567.7-102567.20" wire $0\initial[0:0] - attribute \src "libresoc.v:104436.3-104484.6" + attribute \src "libresoc.v:104232.3-104280.6" wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:104485.3-104533.6" + attribute \src "libresoc.v:104281.3-104329.6" wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:104393.3-104435.6" + attribute \src "libresoc.v:104189.3-104231.6" wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:104001.3-104049.6" + attribute \src "libresoc.v:103797.3-103845.6" wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:103168.3-103216.6" + attribute \src "libresoc.v:102964.3-103012.6" wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:103217.3-103265.6" + attribute \src "libresoc.v:103013.3-103061.6" wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:103805.3-103853.6" + attribute \src "libresoc.v:103601.3-103649.6" wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:103952.3-104000.6" + attribute \src "libresoc.v:103748.3-103796.6" wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:104197.3-104245.6" + attribute \src "libresoc.v:103993.3-104041.6" wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:103119.3-103167.6" + attribute \src "libresoc.v:102915.3-102963.6" wire width 14 $1\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:104534.3-104582.6" + attribute \src "libresoc.v:104330.3-104378.6" wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:104583.3-104631.6" + attribute \src "libresoc.v:104379.3-104427.6" wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:104632.3-104680.6" + attribute \src "libresoc.v:104428.3-104476.6" wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:103658.3-103706.6" + attribute \src "libresoc.v:103454.3-103502.6" wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:103854.3-103902.6" + attribute \src "libresoc.v:103650.3-103698.6" wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:103903.3-103951.6" + attribute \src "libresoc.v:103699.3-103747.6" wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:104148.3-104196.6" + attribute \src "libresoc.v:103944.3-103992.6" wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:103609.3-103657.6" + attribute \src "libresoc.v:103405.3-103453.6" wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:104295.3-104343.6" + attribute \src "libresoc.v:104091.3-104139.6" wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:104681.3-104729.6" + attribute \src "libresoc.v:104477.3-104525.6" wire width 3 $1\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:103756.3-103804.6" + attribute \src "libresoc.v:103552.3-103600.6" wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:104099.3-104147.6" + attribute \src "libresoc.v:103895.3-103943.6" wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:104344.3-104392.6" + attribute \src "libresoc.v:104140.3-104188.6" wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:104246.3-104294.6" + attribute \src "libresoc.v:104042.3-104090.6" wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:104050.3-104098.6" + attribute \src "libresoc.v:103846.3-103894.6" wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:103511.3-103559.6" + attribute \src "libresoc.v:103307.3-103355.6" wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:103560.3-103608.6" + attribute \src "libresoc.v:103356.3-103404.6" wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:103266.3-103314.6" + attribute \src "libresoc.v:103062.3-103110.6" wire width 3 $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:103315.3-103363.6" + attribute \src "libresoc.v:103111.3-103159.6" wire width 3 $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:103364.3-103412.6" + attribute \src "libresoc.v:103160.3-103208.6" wire width 3 $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:103462.3-103510.6" + attribute \src "libresoc.v:103258.3-103306.6" wire width 3 $1\dec31_dec_sub21_sv_out2[2:0] - attribute \src "libresoc.v:103413.3-103461.6" + attribute \src "libresoc.v:103209.3-103257.6" wire width 3 $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:103707.3-103755.6" + attribute \src "libresoc.v:103503.3-103551.6" wire width 2 $1\dec31_dec_sub21_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -160704,28 +160500,28 @@ module \dec31_dec_sub21 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub21_upd - attribute \src "libresoc.v:102771.7-102771.15" + attribute \src "libresoc.v:102567.7-102567.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:102771.7-102771.20" - process $proc$libresoc.v:102771$4140 + attribute \src "libresoc.v:102567.7-102567.20" + process $proc$libresoc.v:102567$4140 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:103119.3-103167.6" - process $proc$libresoc.v:103119$4107 + attribute \src "libresoc.v:102915.3-102963.6" + process $proc$libresoc.v:102915$4107 assign { } { } assign { } { } assign $0\dec31_dec_sub21_function_unit[13:0] $1\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:103120.5-103120.29" + attribute \src "libresoc.v:102916.5-102916.29" switch \initial - attribute \src "libresoc.v:103120.9-103120.17" + attribute \src "libresoc.v:102916.9-102916.17" case 1'1 case end @@ -160793,14 +160589,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[13:0] end - attribute \src "libresoc.v:103168.3-103216.6" - process $proc$libresoc.v:103168$4108 + attribute \src "libresoc.v:102964.3-103012.6" + process $proc$libresoc.v:102964$4108 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:103169.5-103169.29" + attribute \src "libresoc.v:102965.5-102965.29" switch \initial - attribute \src "libresoc.v:103169.9-103169.17" + attribute \src "libresoc.v:102965.9-102965.17" case 1'1 case end @@ -160868,14 +160664,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:103217.3-103265.6" - process $proc$libresoc.v:103217$4109 + attribute \src "libresoc.v:103013.3-103061.6" + process $proc$libresoc.v:103013$4109 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:103218.5-103218.29" + attribute \src "libresoc.v:103014.5-103014.29" switch \initial - attribute \src "libresoc.v:103218.9-103218.17" + attribute \src "libresoc.v:103014.9-103014.17" case 1'1 case end @@ -160943,14 +160739,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] end - attribute \src "libresoc.v:103266.3-103314.6" - process $proc$libresoc.v:103266$4110 + attribute \src "libresoc.v:103062.3-103110.6" + process $proc$libresoc.v:103062$4110 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:103267.5-103267.29" + attribute \src "libresoc.v:103063.5-103063.29" switch \initial - attribute \src "libresoc.v:103267.9-103267.17" + attribute \src "libresoc.v:103063.9-103063.17" case 1'1 case end @@ -161018,14 +160814,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0] end - attribute \src "libresoc.v:103315.3-103363.6" - process $proc$libresoc.v:103315$4111 + attribute \src "libresoc.v:103111.3-103159.6" + process $proc$libresoc.v:103111$4111 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:103316.5-103316.29" + attribute \src "libresoc.v:103112.5-103112.29" switch \initial - attribute \src "libresoc.v:103316.9-103316.17" + attribute \src "libresoc.v:103112.9-103112.17" case 1'1 case end @@ -161093,14 +160889,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0] end - attribute \src "libresoc.v:103364.3-103412.6" - process $proc$libresoc.v:103364$4112 + attribute \src "libresoc.v:103160.3-103208.6" + process $proc$libresoc.v:103160$4112 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:103365.5-103365.29" + attribute \src "libresoc.v:103161.5-103161.29" switch \initial - attribute \src "libresoc.v:103365.9-103365.17" + attribute \src "libresoc.v:103161.9-103161.17" case 1'1 case end @@ -161168,14 +160964,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0] end - attribute \src "libresoc.v:103413.3-103461.6" - process $proc$libresoc.v:103413$4113 + attribute \src "libresoc.v:103209.3-103257.6" + process $proc$libresoc.v:103209$4113 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:103414.5-103414.29" + attribute \src "libresoc.v:103210.5-103210.29" switch \initial - attribute \src "libresoc.v:103414.9-103414.17" + attribute \src "libresoc.v:103210.9-103210.17" case 1'1 case end @@ -161243,14 +161039,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0] end - attribute \src "libresoc.v:103462.3-103510.6" - process $proc$libresoc.v:103462$4114 + attribute \src "libresoc.v:103258.3-103306.6" + process $proc$libresoc.v:103258$4114 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out2[2:0] $1\dec31_dec_sub21_sv_out2[2:0] - attribute \src "libresoc.v:103463.5-103463.29" + attribute \src "libresoc.v:103259.5-103259.29" switch \initial - attribute \src "libresoc.v:103463.9-103463.17" + attribute \src "libresoc.v:103259.9-103259.17" case 1'1 case end @@ -161318,14 +161114,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_out2 $0\dec31_dec_sub21_sv_out2[2:0] end - attribute \src "libresoc.v:103511.3-103559.6" - process $proc$libresoc.v:103511$4115 + attribute \src "libresoc.v:103307.3-103355.6" + process $proc$libresoc.v:103307$4115 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:103512.5-103512.29" + attribute \src "libresoc.v:103308.5-103308.29" switch \initial - attribute \src "libresoc.v:103512.9-103512.17" + attribute \src "libresoc.v:103308.9-103308.17" case 1'1 case end @@ -161393,14 +161189,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0] end - attribute \src "libresoc.v:103560.3-103608.6" - process $proc$libresoc.v:103560$4116 + attribute \src "libresoc.v:103356.3-103404.6" + process $proc$libresoc.v:103356$4116 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:103561.5-103561.29" + attribute \src "libresoc.v:103357.5-103357.29" switch \initial - attribute \src "libresoc.v:103561.9-103561.17" + attribute \src "libresoc.v:103357.9-103357.17" case 1'1 case end @@ -161468,14 +161264,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0] end - attribute \src "libresoc.v:103609.3-103657.6" - process $proc$libresoc.v:103609$4117 + attribute \src "libresoc.v:103405.3-103453.6" + process $proc$libresoc.v:103405$4117 assign { } { } assign { } { } assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:103610.5-103610.29" + attribute \src "libresoc.v:103406.5-103406.29" switch \initial - attribute \src "libresoc.v:103610.9-103610.17" + attribute \src "libresoc.v:103406.9-103406.17" case 1'1 case end @@ -161543,14 +161339,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:103658.3-103706.6" - process $proc$libresoc.v:103658$4118 + attribute \src "libresoc.v:103454.3-103502.6" + process $proc$libresoc.v:103454$4118 assign { } { } assign { } { } assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:103659.5-103659.29" + attribute \src "libresoc.v:103455.5-103455.29" switch \initial - attribute \src "libresoc.v:103659.9-103659.17" + attribute \src "libresoc.v:103455.9-103455.17" case 1'1 case end @@ -161618,14 +161414,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] end - attribute \src "libresoc.v:103707.3-103755.6" - process $proc$libresoc.v:103707$4119 + attribute \src "libresoc.v:103503.3-103551.6" + process $proc$libresoc.v:103503$4119 assign { } { } assign { } { } assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:103708.5-103708.29" + attribute \src "libresoc.v:103504.5-103504.29" switch \initial - attribute \src "libresoc.v:103708.9-103708.17" + attribute \src "libresoc.v:103504.9-103504.17" case 1'1 case end @@ -161693,14 +161489,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:103756.3-103804.6" - process $proc$libresoc.v:103756$4120 + attribute \src "libresoc.v:103552.3-103600.6" + process $proc$libresoc.v:103552$4120 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:103757.5-103757.29" + attribute \src "libresoc.v:103553.5-103553.29" switch \initial - attribute \src "libresoc.v:103757.9-103757.17" + attribute \src "libresoc.v:103553.9-103553.17" case 1'1 case end @@ -161768,14 +161564,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end - attribute \src "libresoc.v:103805.3-103853.6" - process $proc$libresoc.v:103805$4121 + attribute \src "libresoc.v:103601.3-103649.6" + process $proc$libresoc.v:103601$4121 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:103806.5-103806.29" + attribute \src "libresoc.v:103602.5-103602.29" switch \initial - attribute \src "libresoc.v:103806.9-103806.17" + attribute \src "libresoc.v:103602.9-103602.17" case 1'1 case end @@ -161843,14 +161639,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end - attribute \src "libresoc.v:103854.3-103902.6" - process $proc$libresoc.v:103854$4122 + attribute \src "libresoc.v:103650.3-103698.6" + process $proc$libresoc.v:103650$4122 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:103855.5-103855.29" + attribute \src "libresoc.v:103651.5-103651.29" switch \initial - attribute \src "libresoc.v:103855.9-103855.17" + attribute \src "libresoc.v:103651.9-103651.17" case 1'1 case end @@ -161918,14 +161714,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end - attribute \src "libresoc.v:103903.3-103951.6" - process $proc$libresoc.v:103903$4123 + attribute \src "libresoc.v:103699.3-103747.6" + process $proc$libresoc.v:103699$4123 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:103904.5-103904.29" + attribute \src "libresoc.v:103700.5-103700.29" switch \initial - attribute \src "libresoc.v:103904.9-103904.17" + attribute \src "libresoc.v:103700.9-103700.17" case 1'1 case end @@ -161993,14 +161789,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end - attribute \src "libresoc.v:103952.3-104000.6" - process $proc$libresoc.v:103952$4124 + attribute \src "libresoc.v:103748.3-103796.6" + process $proc$libresoc.v:103748$4124 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:103953.5-103953.29" + attribute \src "libresoc.v:103749.5-103749.29" switch \initial - attribute \src "libresoc.v:103953.9-103953.17" + attribute \src "libresoc.v:103749.9-103749.17" case 1'1 case end @@ -162068,14 +161864,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end - attribute \src "libresoc.v:104001.3-104049.6" - process $proc$libresoc.v:104001$4125 + attribute \src "libresoc.v:103797.3-103845.6" + process $proc$libresoc.v:103797$4125 assign { } { } assign { } { } assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:104002.5-104002.29" + attribute \src "libresoc.v:103798.5-103798.29" switch \initial - attribute \src "libresoc.v:104002.9-104002.17" + attribute \src "libresoc.v:103798.9-103798.17" case 1'1 case end @@ -162143,14 +161939,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:104050.3-104098.6" - process $proc$libresoc.v:104050$4126 + attribute \src "libresoc.v:103846.3-103894.6" + process $proc$libresoc.v:103846$4126 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:104051.5-104051.29" + attribute \src "libresoc.v:103847.5-103847.29" switch \initial - attribute \src "libresoc.v:104051.9-104051.17" + attribute \src "libresoc.v:103847.9-103847.17" case 1'1 case end @@ -162218,14 +162014,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:104099.3-104147.6" - process $proc$libresoc.v:104099$4127 + attribute \src "libresoc.v:103895.3-103943.6" + process $proc$libresoc.v:103895$4127 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:104100.5-104100.29" + attribute \src "libresoc.v:103896.5-103896.29" switch \initial - attribute \src "libresoc.v:104100.9-104100.17" + attribute \src "libresoc.v:103896.9-103896.17" case 1'1 case end @@ -162293,14 +162089,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end - attribute \src "libresoc.v:104148.3-104196.6" - process $proc$libresoc.v:104148$4128 + attribute \src "libresoc.v:103944.3-103992.6" + process $proc$libresoc.v:103944$4128 assign { } { } assign { } { } assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:104149.5-104149.29" + attribute \src "libresoc.v:103945.5-103945.29" switch \initial - attribute \src "libresoc.v:104149.9-104149.17" + attribute \src "libresoc.v:103945.9-103945.17" case 1'1 case end @@ -162368,14 +162164,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:104197.3-104245.6" - process $proc$libresoc.v:104197$4129 + attribute \src "libresoc.v:103993.3-104041.6" + process $proc$libresoc.v:103993$4129 assign { } { } assign { } { } assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:104198.5-104198.29" + attribute \src "libresoc.v:103994.5-103994.29" switch \initial - attribute \src "libresoc.v:104198.9-104198.17" + attribute \src "libresoc.v:103994.9-103994.17" case 1'1 case end @@ -162443,14 +162239,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end - attribute \src "libresoc.v:104246.3-104294.6" - process $proc$libresoc.v:104246$4130 + attribute \src "libresoc.v:104042.3-104090.6" + process $proc$libresoc.v:104042$4130 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:104247.5-104247.29" + attribute \src "libresoc.v:104043.5-104043.29" switch \initial - attribute \src "libresoc.v:104247.9-104247.17" + attribute \src "libresoc.v:104043.9-104043.17" case 1'1 case end @@ -162518,14 +162314,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:104295.3-104343.6" - process $proc$libresoc.v:104295$4131 + attribute \src "libresoc.v:104091.3-104139.6" + process $proc$libresoc.v:104091$4131 assign { } { } assign { } { } assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:104296.5-104296.29" + attribute \src "libresoc.v:104092.5-104092.29" switch \initial - attribute \src "libresoc.v:104296.9-104296.17" + attribute \src "libresoc.v:104092.9-104092.17" case 1'1 case end @@ -162593,14 +162389,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] end - attribute \src "libresoc.v:104344.3-104392.6" - process $proc$libresoc.v:104344$4132 + attribute \src "libresoc.v:104140.3-104188.6" + process $proc$libresoc.v:104140$4132 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:104345.5-104345.29" + attribute \src "libresoc.v:104141.5-104141.29" switch \initial - attribute \src "libresoc.v:104345.9-104345.17" + attribute \src "libresoc.v:104141.9-104141.17" case 1'1 case end @@ -162668,14 +162464,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] end - attribute \src "libresoc.v:104393.3-104435.6" - process $proc$libresoc.v:104393$4133 + attribute \src "libresoc.v:104189.3-104231.6" + process $proc$libresoc.v:104189$4133 assign { } { } assign { } { } assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:104394.5-104394.29" + attribute \src "libresoc.v:104190.5-104190.29" switch \initial - attribute \src "libresoc.v:104394.9-104394.17" + attribute \src "libresoc.v:104190.9-104190.17" case 1'1 case end @@ -162731,14 +162527,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] end - attribute \src "libresoc.v:104436.3-104484.6" - process $proc$libresoc.v:104436$4134 + attribute \src "libresoc.v:104232.3-104280.6" + process $proc$libresoc.v:104232$4134 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:104437.5-104437.29" + attribute \src "libresoc.v:104233.5-104233.29" switch \initial - attribute \src "libresoc.v:104437.9-104437.17" + attribute \src "libresoc.v:104233.9-104233.17" case 1'1 case end @@ -162806,14 +162602,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0] end - attribute \src "libresoc.v:104485.3-104533.6" - process $proc$libresoc.v:104485$4135 + attribute \src "libresoc.v:104281.3-104329.6" + process $proc$libresoc.v:104281$4135 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:104486.5-104486.29" + attribute \src "libresoc.v:104282.5-104282.29" switch \initial - attribute \src "libresoc.v:104486.9-104486.17" + attribute \src "libresoc.v:104282.9-104282.17" case 1'1 case end @@ -162881,14 +162677,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0] end - attribute \src "libresoc.v:104534.3-104582.6" - process $proc$libresoc.v:104534$4136 + attribute \src "libresoc.v:104330.3-104378.6" + process $proc$libresoc.v:104330$4136 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:104535.5-104535.29" + attribute \src "libresoc.v:104331.5-104331.29" switch \initial - attribute \src "libresoc.v:104535.9-104535.17" + attribute \src "libresoc.v:104331.9-104331.17" case 1'1 case end @@ -162956,14 +162752,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] end - attribute \src "libresoc.v:104583.3-104631.6" - process $proc$libresoc.v:104583$4137 + attribute \src "libresoc.v:104379.3-104427.6" + process $proc$libresoc.v:104379$4137 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:104584.5-104584.29" + attribute \src "libresoc.v:104380.5-104380.29" switch \initial - attribute \src "libresoc.v:104584.9-104584.17" + attribute \src "libresoc.v:104380.9-104380.17" case 1'1 case end @@ -163031,14 +162827,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] end - attribute \src "libresoc.v:104632.3-104680.6" - process $proc$libresoc.v:104632$4138 + attribute \src "libresoc.v:104428.3-104476.6" + process $proc$libresoc.v:104428$4138 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:104633.5-104633.29" + attribute \src "libresoc.v:104429.5-104429.29" switch \initial - attribute \src "libresoc.v:104633.9-104633.17" + attribute \src "libresoc.v:104429.9-104429.17" case 1'1 case end @@ -163106,14 +162902,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] end - attribute \src "libresoc.v:104681.3-104729.6" - process $proc$libresoc.v:104681$4139 + attribute \src "libresoc.v:104477.3-104525.6" + process $proc$libresoc.v:104477$4139 assign { } { } assign { } { } assign $0\dec31_dec_sub21_out_sel[2:0] $1\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:104682.5-104682.29" + attribute \src "libresoc.v:104478.5-104478.29" switch \initial - attribute \src "libresoc.v:104682.9-104682.17" + attribute \src "libresoc.v:104478.9-104478.17" case 1'1 case end @@ -163183,144 +162979,144 @@ module \dec31_dec_sub21 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:104735.1-106900.10" +attribute \src "libresoc.v:104531.1-106696.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" attribute \generator "nMigen" module \dec31_dec_sub22 - attribute \src "libresoc.v:106569.3-106623.6" + attribute \src "libresoc.v:106365.3-106419.6" wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:106624.3-106678.6" + attribute \src "libresoc.v:106420.3-106474.6" wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:105909.3-105963.6" + attribute \src "libresoc.v:105705.3-105759.6" wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:106129.3-106183.6" + attribute \src "libresoc.v:105925.3-105979.6" wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:105139.3-105193.6" + attribute \src "libresoc.v:104935.3-104989.6" wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:105194.3-105248.6" + attribute \src "libresoc.v:104990.3-105044.6" wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:105854.3-105908.6" + attribute \src "libresoc.v:105650.3-105704.6" wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:106074.3-106128.6" + attribute \src "libresoc.v:105870.3-105924.6" wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:106294.3-106348.6" + attribute \src "libresoc.v:106090.3-106144.6" wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:105084.3-105138.6" + attribute \src "libresoc.v:104880.3-104934.6" wire width 14 $0\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:106679.3-106733.6" + attribute \src "libresoc.v:106475.3-106529.6" wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:106734.3-106788.6" + attribute \src "libresoc.v:106530.3-106584.6" wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:106789.3-106843.6" + attribute \src "libresoc.v:106585.3-106639.6" wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:105689.3-105743.6" + attribute \src "libresoc.v:105485.3-105539.6" wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:105964.3-106018.6" + attribute \src "libresoc.v:105760.3-105814.6" wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:106019.3-106073.6" + attribute \src "libresoc.v:105815.3-105869.6" wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:106349.3-106403.6" + attribute \src "libresoc.v:106145.3-106199.6" wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:105634.3-105688.6" + attribute \src "libresoc.v:105430.3-105484.6" wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:106459.3-106513.6" + attribute \src "libresoc.v:106255.3-106309.6" wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:106844.3-106898.6" + attribute \src "libresoc.v:106640.3-106694.6" wire width 3 $0\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:105799.3-105853.6" + attribute \src "libresoc.v:105595.3-105649.6" wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:106239.3-106293.6" + attribute \src "libresoc.v:106035.3-106089.6" wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:106514.3-106568.6" + attribute \src "libresoc.v:106310.3-106364.6" wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:106404.3-106458.6" + attribute \src "libresoc.v:106200.3-106254.6" wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:106184.3-106238.6" + attribute \src "libresoc.v:105980.3-106034.6" wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:105524.3-105578.6" + attribute \src "libresoc.v:105320.3-105374.6" wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:105579.3-105633.6" + attribute \src "libresoc.v:105375.3-105429.6" wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:105249.3-105303.6" + attribute \src "libresoc.v:105045.3-105099.6" wire width 3 $0\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:105304.3-105358.6" + attribute \src "libresoc.v:105100.3-105154.6" wire width 3 $0\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:105359.3-105413.6" + attribute \src "libresoc.v:105155.3-105209.6" wire width 3 $0\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:105469.3-105523.6" + attribute \src "libresoc.v:105265.3-105319.6" wire width 3 $0\dec31_dec_sub22_sv_out2[2:0] - attribute \src "libresoc.v:105414.3-105468.6" + attribute \src "libresoc.v:105210.3-105264.6" wire width 3 $0\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:105744.3-105798.6" + attribute \src "libresoc.v:105540.3-105594.6" wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:104736.7-104736.20" + attribute \src "libresoc.v:104532.7-104532.20" wire $0\initial[0:0] - attribute \src "libresoc.v:106569.3-106623.6" + attribute \src "libresoc.v:106365.3-106419.6" wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:106624.3-106678.6" + attribute \src "libresoc.v:106420.3-106474.6" wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:105909.3-105963.6" + attribute \src "libresoc.v:105705.3-105759.6" wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:106129.3-106183.6" + attribute \src "libresoc.v:105925.3-105979.6" wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:105139.3-105193.6" + attribute \src "libresoc.v:104935.3-104989.6" wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:105194.3-105248.6" + attribute \src "libresoc.v:104990.3-105044.6" wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:105854.3-105908.6" + attribute \src "libresoc.v:105650.3-105704.6" wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:106074.3-106128.6" + attribute \src "libresoc.v:105870.3-105924.6" wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:106294.3-106348.6" + attribute \src "libresoc.v:106090.3-106144.6" wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:105084.3-105138.6" + attribute \src "libresoc.v:104880.3-104934.6" wire width 14 $1\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:106679.3-106733.6" + attribute \src "libresoc.v:106475.3-106529.6" wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:106734.3-106788.6" + attribute \src "libresoc.v:106530.3-106584.6" wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:106789.3-106843.6" + attribute \src "libresoc.v:106585.3-106639.6" wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:105689.3-105743.6" + attribute \src "libresoc.v:105485.3-105539.6" wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:105964.3-106018.6" + attribute \src "libresoc.v:105760.3-105814.6" wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:106019.3-106073.6" + attribute \src "libresoc.v:105815.3-105869.6" wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:106349.3-106403.6" + attribute \src "libresoc.v:106145.3-106199.6" wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:105634.3-105688.6" + attribute \src "libresoc.v:105430.3-105484.6" wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:106459.3-106513.6" + attribute \src "libresoc.v:106255.3-106309.6" wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:106844.3-106898.6" + attribute \src "libresoc.v:106640.3-106694.6" wire width 3 $1\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:105799.3-105853.6" + attribute \src "libresoc.v:105595.3-105649.6" wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:106239.3-106293.6" + attribute \src "libresoc.v:106035.3-106089.6" wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:106514.3-106568.6" + attribute \src "libresoc.v:106310.3-106364.6" wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:106404.3-106458.6" + attribute \src "libresoc.v:106200.3-106254.6" wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:106184.3-106238.6" + attribute \src "libresoc.v:105980.3-106034.6" wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:105524.3-105578.6" + attribute \src "libresoc.v:105320.3-105374.6" wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:105579.3-105633.6" + attribute \src "libresoc.v:105375.3-105429.6" wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:105249.3-105303.6" + attribute \src "libresoc.v:105045.3-105099.6" wire width 3 $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:105304.3-105358.6" + attribute \src "libresoc.v:105100.3-105154.6" wire width 3 $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:105359.3-105413.6" + attribute \src "libresoc.v:105155.3-105209.6" wire width 3 $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:105469.3-105523.6" + attribute \src "libresoc.v:105265.3-105319.6" wire width 3 $1\dec31_dec_sub22_sv_out2[2:0] - attribute \src "libresoc.v:105414.3-105468.6" + attribute \src "libresoc.v:105210.3-105264.6" wire width 3 $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:105744.3-105798.6" + attribute \src "libresoc.v:105540.3-105594.6" wire width 2 $1\dec31_dec_sub22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -163632,28 +163428,28 @@ module \dec31_dec_sub22 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub22_upd - attribute \src "libresoc.v:104736.7-104736.15" + attribute \src "libresoc.v:104532.7-104532.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:104736.7-104736.20" - process $proc$libresoc.v:104736$4174 + attribute \src "libresoc.v:104532.7-104532.20" + process $proc$libresoc.v:104532$4174 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:105084.3-105138.6" - process $proc$libresoc.v:105084$4141 + attribute \src "libresoc.v:104880.3-104934.6" + process $proc$libresoc.v:104880$4141 assign { } { } assign { } { } assign $0\dec31_dec_sub22_function_unit[13:0] $1\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:105085.5-105085.29" + attribute \src "libresoc.v:104881.5-104881.29" switch \initial - attribute \src "libresoc.v:105085.9-105085.17" + attribute \src "libresoc.v:104881.9-104881.17" case 1'1 case end @@ -163729,14 +163525,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[13:0] end - attribute \src "libresoc.v:105139.3-105193.6" - process $proc$libresoc.v:105139$4142 + attribute \src "libresoc.v:104935.3-104989.6" + process $proc$libresoc.v:104935$4142 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:105140.5-105140.29" + attribute \src "libresoc.v:104936.5-104936.29" switch \initial - attribute \src "libresoc.v:105140.9-105140.17" + attribute \src "libresoc.v:104936.9-104936.17" case 1'1 case end @@ -163812,14 +163608,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:105194.3-105248.6" - process $proc$libresoc.v:105194$4143 + attribute \src "libresoc.v:104990.3-105044.6" + process $proc$libresoc.v:104990$4143 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:105195.5-105195.29" + attribute \src "libresoc.v:104991.5-104991.29" switch \initial - attribute \src "libresoc.v:105195.9-105195.17" + attribute \src "libresoc.v:104991.9-104991.17" case 1'1 case end @@ -163895,14 +163691,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:105249.3-105303.6" - process $proc$libresoc.v:105249$4144 + attribute \src "libresoc.v:105045.3-105099.6" + process $proc$libresoc.v:105045$4144 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:105250.5-105250.29" + attribute \src "libresoc.v:105046.5-105046.29" switch \initial - attribute \src "libresoc.v:105250.9-105250.17" + attribute \src "libresoc.v:105046.9-105046.17" case 1'1 case end @@ -163978,14 +163774,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0] end - attribute \src "libresoc.v:105304.3-105358.6" - process $proc$libresoc.v:105304$4145 + attribute \src "libresoc.v:105100.3-105154.6" + process $proc$libresoc.v:105100$4145 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:105305.5-105305.29" + attribute \src "libresoc.v:105101.5-105101.29" switch \initial - attribute \src "libresoc.v:105305.9-105305.17" + attribute \src "libresoc.v:105101.9-105101.17" case 1'1 case end @@ -164061,14 +163857,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0] end - attribute \src "libresoc.v:105359.3-105413.6" - process $proc$libresoc.v:105359$4146 + attribute \src "libresoc.v:105155.3-105209.6" + process $proc$libresoc.v:105155$4146 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:105360.5-105360.29" + attribute \src "libresoc.v:105156.5-105156.29" switch \initial - attribute \src "libresoc.v:105360.9-105360.17" + attribute \src "libresoc.v:105156.9-105156.17" case 1'1 case end @@ -164144,14 +163940,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0] end - attribute \src "libresoc.v:105414.3-105468.6" - process $proc$libresoc.v:105414$4147 + attribute \src "libresoc.v:105210.3-105264.6" + process $proc$libresoc.v:105210$4147 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:105415.5-105415.29" + attribute \src "libresoc.v:105211.5-105211.29" switch \initial - attribute \src "libresoc.v:105415.9-105415.17" + attribute \src "libresoc.v:105211.9-105211.17" case 1'1 case end @@ -164227,14 +164023,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0] end - attribute \src "libresoc.v:105469.3-105523.6" - process $proc$libresoc.v:105469$4148 + attribute \src "libresoc.v:105265.3-105319.6" + process $proc$libresoc.v:105265$4148 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out2[2:0] $1\dec31_dec_sub22_sv_out2[2:0] - attribute \src "libresoc.v:105470.5-105470.29" + attribute \src "libresoc.v:105266.5-105266.29" switch \initial - attribute \src "libresoc.v:105470.9-105470.17" + attribute \src "libresoc.v:105266.9-105266.17" case 1'1 case end @@ -164310,14 +164106,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_out2 $0\dec31_dec_sub22_sv_out2[2:0] end - attribute \src "libresoc.v:105524.3-105578.6" - process $proc$libresoc.v:105524$4149 + attribute \src "libresoc.v:105320.3-105374.6" + process $proc$libresoc.v:105320$4149 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:105525.5-105525.29" + attribute \src "libresoc.v:105321.5-105321.29" switch \initial - attribute \src "libresoc.v:105525.9-105525.17" + attribute \src "libresoc.v:105321.9-105321.17" case 1'1 case end @@ -164393,14 +164189,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0] end - attribute \src "libresoc.v:105579.3-105633.6" - process $proc$libresoc.v:105579$4150 + attribute \src "libresoc.v:105375.3-105429.6" + process $proc$libresoc.v:105375$4150 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:105580.5-105580.29" + attribute \src "libresoc.v:105376.5-105376.29" switch \initial - attribute \src "libresoc.v:105580.9-105580.17" + attribute \src "libresoc.v:105376.9-105376.17" case 1'1 case end @@ -164476,14 +164272,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0] end - attribute \src "libresoc.v:105634.3-105688.6" - process $proc$libresoc.v:105634$4151 + attribute \src "libresoc.v:105430.3-105484.6" + process $proc$libresoc.v:105430$4151 assign { } { } assign { } { } assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:105635.5-105635.29" + attribute \src "libresoc.v:105431.5-105431.29" switch \initial - attribute \src "libresoc.v:105635.9-105635.17" + attribute \src "libresoc.v:105431.9-105431.17" case 1'1 case end @@ -164559,14 +164355,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:105689.3-105743.6" - process $proc$libresoc.v:105689$4152 + attribute \src "libresoc.v:105485.3-105539.6" + process $proc$libresoc.v:105485$4152 assign { } { } assign { } { } assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:105690.5-105690.29" + attribute \src "libresoc.v:105486.5-105486.29" switch \initial - attribute \src "libresoc.v:105690.9-105690.17" + attribute \src "libresoc.v:105486.9-105486.17" case 1'1 case end @@ -164642,14 +164438,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:105744.3-105798.6" - process $proc$libresoc.v:105744$4153 + attribute \src "libresoc.v:105540.3-105594.6" + process $proc$libresoc.v:105540$4153 assign { } { } assign { } { } assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:105745.5-105745.29" + attribute \src "libresoc.v:105541.5-105541.29" switch \initial - attribute \src "libresoc.v:105745.9-105745.17" + attribute \src "libresoc.v:105541.9-105541.17" case 1'1 case end @@ -164725,14 +164521,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:105799.3-105853.6" - process $proc$libresoc.v:105799$4154 + attribute \src "libresoc.v:105595.3-105649.6" + process $proc$libresoc.v:105595$4154 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:105800.5-105800.29" + attribute \src "libresoc.v:105596.5-105596.29" switch \initial - attribute \src "libresoc.v:105800.9-105800.17" + attribute \src "libresoc.v:105596.9-105596.17" case 1'1 case end @@ -164808,14 +164604,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:105854.3-105908.6" - process $proc$libresoc.v:105854$4155 + attribute \src "libresoc.v:105650.3-105704.6" + process $proc$libresoc.v:105650$4155 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:105855.5-105855.29" + attribute \src "libresoc.v:105651.5-105651.29" switch \initial - attribute \src "libresoc.v:105855.9-105855.17" + attribute \src "libresoc.v:105651.9-105651.17" case 1'1 case end @@ -164891,14 +164687,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end - attribute \src "libresoc.v:105909.3-105963.6" - process $proc$libresoc.v:105909$4156 + attribute \src "libresoc.v:105705.3-105759.6" + process $proc$libresoc.v:105705$4156 assign { } { } assign { } { } assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:105910.5-105910.29" + attribute \src "libresoc.v:105706.5-105706.29" switch \initial - attribute \src "libresoc.v:105910.9-105910.17" + attribute \src "libresoc.v:105706.9-105706.17" case 1'1 case end @@ -164974,14 +164770,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end - attribute \src "libresoc.v:105964.3-106018.6" - process $proc$libresoc.v:105964$4157 + attribute \src "libresoc.v:105760.3-105814.6" + process $proc$libresoc.v:105760$4157 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:105965.5-105965.29" + attribute \src "libresoc.v:105761.5-105761.29" switch \initial - attribute \src "libresoc.v:105965.9-105965.17" + attribute \src "libresoc.v:105761.9-105761.17" case 1'1 case end @@ -165057,14 +164853,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:106019.3-106073.6" - process $proc$libresoc.v:106019$4158 + attribute \src "libresoc.v:105815.3-105869.6" + process $proc$libresoc.v:105815$4158 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:106020.5-106020.29" + attribute \src "libresoc.v:105816.5-105816.29" switch \initial - attribute \src "libresoc.v:106020.9-106020.17" + attribute \src "libresoc.v:105816.9-105816.17" case 1'1 case end @@ -165140,14 +164936,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:106074.3-106128.6" - process $proc$libresoc.v:106074$4159 + attribute \src "libresoc.v:105870.3-105924.6" + process $proc$libresoc.v:105870$4159 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:106075.5-106075.29" + attribute \src "libresoc.v:105871.5-105871.29" switch \initial - attribute \src "libresoc.v:106075.9-106075.17" + attribute \src "libresoc.v:105871.9-105871.17" case 1'1 case end @@ -165223,14 +165019,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:106129.3-106183.6" - process $proc$libresoc.v:106129$4160 + attribute \src "libresoc.v:105925.3-105979.6" + process $proc$libresoc.v:105925$4160 assign { } { } assign { } { } assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:106130.5-106130.29" + attribute \src "libresoc.v:105926.5-105926.29" switch \initial - attribute \src "libresoc.v:106130.9-106130.17" + attribute \src "libresoc.v:105926.9-105926.17" case 1'1 case end @@ -165306,14 +165102,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:106184.3-106238.6" - process $proc$libresoc.v:106184$4161 + attribute \src "libresoc.v:105980.3-106034.6" + process $proc$libresoc.v:105980$4161 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:106185.5-106185.29" + attribute \src "libresoc.v:105981.5-105981.29" switch \initial - attribute \src "libresoc.v:106185.9-106185.17" + attribute \src "libresoc.v:105981.9-105981.17" case 1'1 case end @@ -165389,14 +165185,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:106239.3-106293.6" - process $proc$libresoc.v:106239$4162 + attribute \src "libresoc.v:106035.3-106089.6" + process $proc$libresoc.v:106035$4162 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:106240.5-106240.29" + attribute \src "libresoc.v:106036.5-106036.29" switch \initial - attribute \src "libresoc.v:106240.9-106240.17" + attribute \src "libresoc.v:106036.9-106036.17" case 1'1 case end @@ -165472,14 +165268,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end - attribute \src "libresoc.v:106294.3-106348.6" - process $proc$libresoc.v:106294$4163 + attribute \src "libresoc.v:106090.3-106144.6" + process $proc$libresoc.v:106090$4163 assign { } { } assign { } { } assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:106295.5-106295.29" + attribute \src "libresoc.v:106091.5-106091.29" switch \initial - attribute \src "libresoc.v:106295.9-106295.17" + attribute \src "libresoc.v:106091.9-106091.17" case 1'1 case end @@ -165555,14 +165351,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end - attribute \src "libresoc.v:106349.3-106403.6" - process $proc$libresoc.v:106349$4164 + attribute \src "libresoc.v:106145.3-106199.6" + process $proc$libresoc.v:106145$4164 assign { } { } assign { } { } assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:106350.5-106350.29" + attribute \src "libresoc.v:106146.5-106146.29" switch \initial - attribute \src "libresoc.v:106350.9-106350.17" + attribute \src "libresoc.v:106146.9-106146.17" case 1'1 case end @@ -165638,14 +165434,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:106404.3-106458.6" - process $proc$libresoc.v:106404$4165 + attribute \src "libresoc.v:106200.3-106254.6" + process $proc$libresoc.v:106200$4165 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:106405.5-106405.29" + attribute \src "libresoc.v:106201.5-106201.29" switch \initial - attribute \src "libresoc.v:106405.9-106405.17" + attribute \src "libresoc.v:106201.9-106201.17" case 1'1 case end @@ -165721,14 +165517,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:106459.3-106513.6" - process $proc$libresoc.v:106459$4166 + attribute \src "libresoc.v:106255.3-106309.6" + process $proc$libresoc.v:106255$4166 assign { } { } assign { } { } assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:106460.5-106460.29" + attribute \src "libresoc.v:106256.5-106256.29" switch \initial - attribute \src "libresoc.v:106460.9-106460.17" + attribute \src "libresoc.v:106256.9-106256.17" case 1'1 case end @@ -165804,14 +165600,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end - attribute \src "libresoc.v:106514.3-106568.6" - process $proc$libresoc.v:106514$4167 + attribute \src "libresoc.v:106310.3-106364.6" + process $proc$libresoc.v:106310$4167 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:106515.5-106515.29" + attribute \src "libresoc.v:106311.5-106311.29" switch \initial - attribute \src "libresoc.v:106515.9-106515.17" + attribute \src "libresoc.v:106311.9-106311.17" case 1'1 case end @@ -165887,14 +165683,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end - attribute \src "libresoc.v:106569.3-106623.6" - process $proc$libresoc.v:106569$4168 + attribute \src "libresoc.v:106365.3-106419.6" + process $proc$libresoc.v:106365$4168 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:106570.5-106570.29" + attribute \src "libresoc.v:106366.5-106366.29" switch \initial - attribute \src "libresoc.v:106570.9-106570.17" + attribute \src "libresoc.v:106366.9-106366.17" case 1'1 case end @@ -165970,14 +165766,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0] end - attribute \src "libresoc.v:106624.3-106678.6" - process $proc$libresoc.v:106624$4169 + attribute \src "libresoc.v:106420.3-106474.6" + process $proc$libresoc.v:106420$4169 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:106625.5-106625.29" + attribute \src "libresoc.v:106421.5-106421.29" switch \initial - attribute \src "libresoc.v:106625.9-106625.17" + attribute \src "libresoc.v:106421.9-106421.17" case 1'1 case end @@ -166053,14 +165849,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0] end - attribute \src "libresoc.v:106679.3-106733.6" - process $proc$libresoc.v:106679$4170 + attribute \src "libresoc.v:106475.3-106529.6" + process $proc$libresoc.v:106475$4170 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:106680.5-106680.29" + attribute \src "libresoc.v:106476.5-106476.29" switch \initial - attribute \src "libresoc.v:106680.9-106680.17" + attribute \src "libresoc.v:106476.9-106476.17" case 1'1 case end @@ -166136,14 +165932,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:106734.3-106788.6" - process $proc$libresoc.v:106734$4171 + attribute \src "libresoc.v:106530.3-106584.6" + process $proc$libresoc.v:106530$4171 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:106735.5-106735.29" + attribute \src "libresoc.v:106531.5-106531.29" switch \initial - attribute \src "libresoc.v:106735.9-106735.17" + attribute \src "libresoc.v:106531.9-106531.17" case 1'1 case end @@ -166219,14 +166015,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:106789.3-106843.6" - process $proc$libresoc.v:106789$4172 + attribute \src "libresoc.v:106585.3-106639.6" + process $proc$libresoc.v:106585$4172 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:106790.5-106790.29" + attribute \src "libresoc.v:106586.5-106586.29" switch \initial - attribute \src "libresoc.v:106790.9-106790.17" + attribute \src "libresoc.v:106586.9-106586.17" case 1'1 case end @@ -166302,14 +166098,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end - attribute \src "libresoc.v:106844.3-106898.6" - process $proc$libresoc.v:106844$4173 + attribute \src "libresoc.v:106640.3-106694.6" + process $proc$libresoc.v:106640$4173 assign { } { } assign { } { } assign $0\dec31_dec_sub22_out_sel[2:0] $1\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:106845.5-106845.29" + attribute \src "libresoc.v:106641.5-106641.29" switch \initial - attribute \src "libresoc.v:106845.9-106845.17" + attribute \src "libresoc.v:106641.9-106641.17" case 1'1 case end @@ -166387,144 +166183,144 @@ module \dec31_dec_sub22 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:106904.1-108871.10" +attribute \src "libresoc.v:106700.1-108667.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" attribute \generator "nMigen" module \dec31_dec_sub23 - attribute \src "libresoc.v:108576.3-108624.6" + attribute \src "libresoc.v:108372.3-108420.6" wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:108625.3-108673.6" + attribute \src "libresoc.v:108421.3-108469.6" wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:107988.3-108036.6" + attribute \src "libresoc.v:107784.3-107832.6" wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:108184.3-108232.6" + attribute \src "libresoc.v:107980.3-108028.6" wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:107302.3-107350.6" + attribute \src "libresoc.v:107098.3-107146.6" wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:107351.3-107399.6" + attribute \src "libresoc.v:107147.3-107195.6" wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:107939.3-107987.6" + attribute \src "libresoc.v:107735.3-107783.6" wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:108135.3-108183.6" + attribute \src "libresoc.v:107931.3-107979.6" wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:108331.3-108379.6" + attribute \src "libresoc.v:108127.3-108175.6" wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:107253.3-107301.6" + attribute \src "libresoc.v:107049.3-107097.6" wire width 14 $0\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:108674.3-108722.6" + attribute \src "libresoc.v:108470.3-108518.6" wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:108723.3-108771.6" + attribute \src "libresoc.v:108519.3-108567.6" wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:108772.3-108820.6" + attribute \src "libresoc.v:108568.3-108616.6" wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:107792.3-107840.6" + attribute \src "libresoc.v:107588.3-107636.6" wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:108037.3-108085.6" + attribute \src "libresoc.v:107833.3-107881.6" wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:108086.3-108134.6" + attribute \src "libresoc.v:107882.3-107930.6" wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:108380.3-108428.6" + attribute \src "libresoc.v:108176.3-108224.6" wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:107743.3-107791.6" + attribute \src "libresoc.v:107539.3-107587.6" wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:108478.3-108526.6" + attribute \src "libresoc.v:108274.3-108322.6" wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:108821.3-108869.6" + attribute \src "libresoc.v:108617.3-108665.6" wire width 3 $0\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:107890.3-107938.6" + attribute \src "libresoc.v:107686.3-107734.6" wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:108282.3-108330.6" + attribute \src "libresoc.v:108078.3-108126.6" wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:108527.3-108575.6" + attribute \src "libresoc.v:108323.3-108371.6" wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:108429.3-108477.6" + attribute \src "libresoc.v:108225.3-108273.6" wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:108233.3-108281.6" + attribute \src "libresoc.v:108029.3-108077.6" wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:107645.3-107693.6" + attribute \src "libresoc.v:107441.3-107489.6" wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:107694.3-107742.6" + attribute \src "libresoc.v:107490.3-107538.6" wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:107400.3-107448.6" + attribute \src "libresoc.v:107196.3-107244.6" wire width 3 $0\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:107449.3-107497.6" + attribute \src "libresoc.v:107245.3-107293.6" wire width 3 $0\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:107498.3-107546.6" + attribute \src "libresoc.v:107294.3-107342.6" wire width 3 $0\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:107596.3-107644.6" + attribute \src "libresoc.v:107392.3-107440.6" wire width 3 $0\dec31_dec_sub23_sv_out2[2:0] - attribute \src "libresoc.v:107547.3-107595.6" + attribute \src "libresoc.v:107343.3-107391.6" wire width 3 $0\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:107841.3-107889.6" + attribute \src "libresoc.v:107637.3-107685.6" wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:106905.7-106905.20" + attribute \src "libresoc.v:106701.7-106701.20" wire $0\initial[0:0] - attribute \src "libresoc.v:108576.3-108624.6" + attribute \src "libresoc.v:108372.3-108420.6" wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:108625.3-108673.6" + attribute \src "libresoc.v:108421.3-108469.6" wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:107988.3-108036.6" + attribute \src "libresoc.v:107784.3-107832.6" wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:108184.3-108232.6" + attribute \src "libresoc.v:107980.3-108028.6" wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:107302.3-107350.6" + attribute \src "libresoc.v:107098.3-107146.6" wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:107351.3-107399.6" + attribute \src "libresoc.v:107147.3-107195.6" wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:107939.3-107987.6" + attribute \src "libresoc.v:107735.3-107783.6" wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:108135.3-108183.6" + attribute \src "libresoc.v:107931.3-107979.6" wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:108331.3-108379.6" + attribute \src "libresoc.v:108127.3-108175.6" wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:107253.3-107301.6" + attribute \src "libresoc.v:107049.3-107097.6" wire width 14 $1\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:108674.3-108722.6" + attribute \src "libresoc.v:108470.3-108518.6" wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:108723.3-108771.6" + attribute \src "libresoc.v:108519.3-108567.6" wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:108772.3-108820.6" + attribute \src "libresoc.v:108568.3-108616.6" wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:107792.3-107840.6" + attribute \src "libresoc.v:107588.3-107636.6" wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:108037.3-108085.6" + attribute \src "libresoc.v:107833.3-107881.6" wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:108086.3-108134.6" + attribute \src "libresoc.v:107882.3-107930.6" wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:108380.3-108428.6" + attribute \src "libresoc.v:108176.3-108224.6" wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:107743.3-107791.6" + attribute \src "libresoc.v:107539.3-107587.6" wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:108478.3-108526.6" + attribute \src "libresoc.v:108274.3-108322.6" wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:108821.3-108869.6" + attribute \src "libresoc.v:108617.3-108665.6" wire width 3 $1\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:107890.3-107938.6" + attribute \src "libresoc.v:107686.3-107734.6" wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:108282.3-108330.6" + attribute \src "libresoc.v:108078.3-108126.6" wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:108527.3-108575.6" + attribute \src "libresoc.v:108323.3-108371.6" wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:108429.3-108477.6" + attribute \src "libresoc.v:108225.3-108273.6" wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:108233.3-108281.6" + attribute \src "libresoc.v:108029.3-108077.6" wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:107645.3-107693.6" + attribute \src "libresoc.v:107441.3-107489.6" wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:107694.3-107742.6" + attribute \src "libresoc.v:107490.3-107538.6" wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:107400.3-107448.6" + attribute \src "libresoc.v:107196.3-107244.6" wire width 3 $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:107449.3-107497.6" + attribute \src "libresoc.v:107245.3-107293.6" wire width 3 $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:107498.3-107546.6" + attribute \src "libresoc.v:107294.3-107342.6" wire width 3 $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:107596.3-107644.6" + attribute \src "libresoc.v:107392.3-107440.6" wire width 3 $1\dec31_dec_sub23_sv_out2[2:0] - attribute \src "libresoc.v:107547.3-107595.6" + attribute \src "libresoc.v:107343.3-107391.6" wire width 3 $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:107841.3-107889.6" + attribute \src "libresoc.v:107637.3-107685.6" wire width 2 $1\dec31_dec_sub23_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -166836,28 +166632,28 @@ module \dec31_dec_sub23 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub23_upd - attribute \src "libresoc.v:106905.7-106905.15" + attribute \src "libresoc.v:106701.7-106701.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:106905.7-106905.20" - process $proc$libresoc.v:106905$4208 + attribute \src "libresoc.v:106701.7-106701.20" + process $proc$libresoc.v:106701$4208 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:107253.3-107301.6" - process $proc$libresoc.v:107253$4175 + attribute \src "libresoc.v:107049.3-107097.6" + process $proc$libresoc.v:107049$4175 assign { } { } assign { } { } assign $0\dec31_dec_sub23_function_unit[13:0] $1\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:107254.5-107254.29" + attribute \src "libresoc.v:107050.5-107050.29" switch \initial - attribute \src "libresoc.v:107254.9-107254.17" + attribute \src "libresoc.v:107050.9-107050.17" case 1'1 case end @@ -166925,14 +166721,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[13:0] end - attribute \src "libresoc.v:107302.3-107350.6" - process $proc$libresoc.v:107302$4176 + attribute \src "libresoc.v:107098.3-107146.6" + process $proc$libresoc.v:107098$4176 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:107303.5-107303.29" + attribute \src "libresoc.v:107099.5-107099.29" switch \initial - attribute \src "libresoc.v:107303.9-107303.17" + attribute \src "libresoc.v:107099.9-107099.17" case 1'1 case end @@ -167000,14 +166796,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:107351.3-107399.6" - process $proc$libresoc.v:107351$4177 + attribute \src "libresoc.v:107147.3-107195.6" + process $proc$libresoc.v:107147$4177 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:107352.5-107352.29" + attribute \src "libresoc.v:107148.5-107148.29" switch \initial - attribute \src "libresoc.v:107352.9-107352.17" + attribute \src "libresoc.v:107148.9-107148.17" case 1'1 case end @@ -167075,14 +166871,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] end - attribute \src "libresoc.v:107400.3-107448.6" - process $proc$libresoc.v:107400$4178 + attribute \src "libresoc.v:107196.3-107244.6" + process $proc$libresoc.v:107196$4178 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:107401.5-107401.29" + attribute \src "libresoc.v:107197.5-107197.29" switch \initial - attribute \src "libresoc.v:107401.9-107401.17" + attribute \src "libresoc.v:107197.9-107197.17" case 1'1 case end @@ -167150,14 +166946,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0] end - attribute \src "libresoc.v:107449.3-107497.6" - process $proc$libresoc.v:107449$4179 + attribute \src "libresoc.v:107245.3-107293.6" + process $proc$libresoc.v:107245$4179 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:107450.5-107450.29" + attribute \src "libresoc.v:107246.5-107246.29" switch \initial - attribute \src "libresoc.v:107450.9-107450.17" + attribute \src "libresoc.v:107246.9-107246.17" case 1'1 case end @@ -167225,14 +167021,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0] end - attribute \src "libresoc.v:107498.3-107546.6" - process $proc$libresoc.v:107498$4180 + attribute \src "libresoc.v:107294.3-107342.6" + process $proc$libresoc.v:107294$4180 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:107499.5-107499.29" + attribute \src "libresoc.v:107295.5-107295.29" switch \initial - attribute \src "libresoc.v:107499.9-107499.17" + attribute \src "libresoc.v:107295.9-107295.17" case 1'1 case end @@ -167300,14 +167096,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0] end - attribute \src "libresoc.v:107547.3-107595.6" - process $proc$libresoc.v:107547$4181 + attribute \src "libresoc.v:107343.3-107391.6" + process $proc$libresoc.v:107343$4181 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:107548.5-107548.29" + attribute \src "libresoc.v:107344.5-107344.29" switch \initial - attribute \src "libresoc.v:107548.9-107548.17" + attribute \src "libresoc.v:107344.9-107344.17" case 1'1 case end @@ -167375,14 +167171,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0] end - attribute \src "libresoc.v:107596.3-107644.6" - process $proc$libresoc.v:107596$4182 + attribute \src "libresoc.v:107392.3-107440.6" + process $proc$libresoc.v:107392$4182 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out2[2:0] $1\dec31_dec_sub23_sv_out2[2:0] - attribute \src "libresoc.v:107597.5-107597.29" + attribute \src "libresoc.v:107393.5-107393.29" switch \initial - attribute \src "libresoc.v:107597.9-107597.17" + attribute \src "libresoc.v:107393.9-107393.17" case 1'1 case end @@ -167450,14 +167246,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_out2 $0\dec31_dec_sub23_sv_out2[2:0] end - attribute \src "libresoc.v:107645.3-107693.6" - process $proc$libresoc.v:107645$4183 + attribute \src "libresoc.v:107441.3-107489.6" + process $proc$libresoc.v:107441$4183 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:107646.5-107646.29" + attribute \src "libresoc.v:107442.5-107442.29" switch \initial - attribute \src "libresoc.v:107646.9-107646.17" + attribute \src "libresoc.v:107442.9-107442.17" case 1'1 case end @@ -167525,14 +167321,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0] end - attribute \src "libresoc.v:107694.3-107742.6" - process $proc$libresoc.v:107694$4184 + attribute \src "libresoc.v:107490.3-107538.6" + process $proc$libresoc.v:107490$4184 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:107695.5-107695.29" + attribute \src "libresoc.v:107491.5-107491.29" switch \initial - attribute \src "libresoc.v:107695.9-107695.17" + attribute \src "libresoc.v:107491.9-107491.17" case 1'1 case end @@ -167600,14 +167396,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0] end - attribute \src "libresoc.v:107743.3-107791.6" - process $proc$libresoc.v:107743$4185 + attribute \src "libresoc.v:107539.3-107587.6" + process $proc$libresoc.v:107539$4185 assign { } { } assign { } { } assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:107744.5-107744.29" + attribute \src "libresoc.v:107540.5-107540.29" switch \initial - attribute \src "libresoc.v:107744.9-107744.17" + attribute \src "libresoc.v:107540.9-107540.17" case 1'1 case end @@ -167675,14 +167471,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:107792.3-107840.6" - process $proc$libresoc.v:107792$4186 + attribute \src "libresoc.v:107588.3-107636.6" + process $proc$libresoc.v:107588$4186 assign { } { } assign { } { } assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:107793.5-107793.29" + attribute \src "libresoc.v:107589.5-107589.29" switch \initial - attribute \src "libresoc.v:107793.9-107793.17" + attribute \src "libresoc.v:107589.9-107589.17" case 1'1 case end @@ -167750,14 +167546,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:107841.3-107889.6" - process $proc$libresoc.v:107841$4187 + attribute \src "libresoc.v:107637.3-107685.6" + process $proc$libresoc.v:107637$4187 assign { } { } assign { } { } assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:107842.5-107842.29" + attribute \src "libresoc.v:107638.5-107638.29" switch \initial - attribute \src "libresoc.v:107842.9-107842.17" + attribute \src "libresoc.v:107638.9-107638.17" case 1'1 case end @@ -167825,14 +167621,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:107890.3-107938.6" - process $proc$libresoc.v:107890$4188 + attribute \src "libresoc.v:107686.3-107734.6" + process $proc$libresoc.v:107686$4188 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:107891.5-107891.29" + attribute \src "libresoc.v:107687.5-107687.29" switch \initial - attribute \src "libresoc.v:107891.9-107891.17" + attribute \src "libresoc.v:107687.9-107687.17" case 1'1 case end @@ -167900,14 +167696,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end - attribute \src "libresoc.v:107939.3-107987.6" - process $proc$libresoc.v:107939$4189 + attribute \src "libresoc.v:107735.3-107783.6" + process $proc$libresoc.v:107735$4189 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:107940.5-107940.29" + attribute \src "libresoc.v:107736.5-107736.29" switch \initial - attribute \src "libresoc.v:107940.9-107940.17" + attribute \src "libresoc.v:107736.9-107736.17" case 1'1 case end @@ -167975,14 +167771,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "libresoc.v:107988.3-108036.6" - process $proc$libresoc.v:107988$4190 + attribute \src "libresoc.v:107784.3-107832.6" + process $proc$libresoc.v:107784$4190 assign { } { } assign { } { } assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:107989.5-107989.29" + attribute \src "libresoc.v:107785.5-107785.29" switch \initial - attribute \src "libresoc.v:107989.9-107989.17" + attribute \src "libresoc.v:107785.9-107785.17" case 1'1 case end @@ -168050,14 +167846,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end - attribute \src "libresoc.v:108037.3-108085.6" - process $proc$libresoc.v:108037$4191 + attribute \src "libresoc.v:107833.3-107881.6" + process $proc$libresoc.v:107833$4191 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:108038.5-108038.29" + attribute \src "libresoc.v:107834.5-107834.29" switch \initial - attribute \src "libresoc.v:108038.9-108038.17" + attribute \src "libresoc.v:107834.9-107834.17" case 1'1 case end @@ -168125,14 +167921,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end - attribute \src "libresoc.v:108086.3-108134.6" - process $proc$libresoc.v:108086$4192 + attribute \src "libresoc.v:107882.3-107930.6" + process $proc$libresoc.v:107882$4192 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:108087.5-108087.29" + attribute \src "libresoc.v:107883.5-107883.29" switch \initial - attribute \src "libresoc.v:108087.9-108087.17" + attribute \src "libresoc.v:107883.9-107883.17" case 1'1 case end @@ -168200,14 +167996,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "libresoc.v:108135.3-108183.6" - process $proc$libresoc.v:108135$4193 + attribute \src "libresoc.v:107931.3-107979.6" + process $proc$libresoc.v:107931$4193 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:108136.5-108136.29" + attribute \src "libresoc.v:107932.5-107932.29" switch \initial - attribute \src "libresoc.v:108136.9-108136.17" + attribute \src "libresoc.v:107932.9-107932.17" case 1'1 case end @@ -168275,14 +168071,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end - attribute \src "libresoc.v:108184.3-108232.6" - process $proc$libresoc.v:108184$4194 + attribute \src "libresoc.v:107980.3-108028.6" + process $proc$libresoc.v:107980$4194 assign { } { } assign { } { } assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:108185.5-108185.29" + attribute \src "libresoc.v:107981.5-107981.29" switch \initial - attribute \src "libresoc.v:108185.9-108185.17" + attribute \src "libresoc.v:107981.9-107981.17" case 1'1 case end @@ -168350,14 +168146,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] end - attribute \src "libresoc.v:108233.3-108281.6" - process $proc$libresoc.v:108233$4195 + attribute \src "libresoc.v:108029.3-108077.6" + process $proc$libresoc.v:108029$4195 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:108234.5-108234.29" + attribute \src "libresoc.v:108030.5-108030.29" switch \initial - attribute \src "libresoc.v:108234.9-108234.17" + attribute \src "libresoc.v:108030.9-108030.17" case 1'1 case end @@ -168425,14 +168221,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:108282.3-108330.6" - process $proc$libresoc.v:108282$4196 + attribute \src "libresoc.v:108078.3-108126.6" + process $proc$libresoc.v:108078$4196 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:108283.5-108283.29" + attribute \src "libresoc.v:108079.5-108079.29" switch \initial - attribute \src "libresoc.v:108283.9-108283.17" + attribute \src "libresoc.v:108079.9-108079.17" case 1'1 case end @@ -168500,14 +168296,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] end - attribute \src "libresoc.v:108331.3-108379.6" - process $proc$libresoc.v:108331$4197 + attribute \src "libresoc.v:108127.3-108175.6" + process $proc$libresoc.v:108127$4197 assign { } { } assign { } { } assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:108332.5-108332.29" + attribute \src "libresoc.v:108128.5-108128.29" switch \initial - attribute \src "libresoc.v:108332.9-108332.17" + attribute \src "libresoc.v:108128.9-108128.17" case 1'1 case end @@ -168575,14 +168371,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] end - attribute \src "libresoc.v:108380.3-108428.6" - process $proc$libresoc.v:108380$4198 + attribute \src "libresoc.v:108176.3-108224.6" + process $proc$libresoc.v:108176$4198 assign { } { } assign { } { } assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:108381.5-108381.29" + attribute \src "libresoc.v:108177.5-108177.29" switch \initial - attribute \src "libresoc.v:108381.9-108381.17" + attribute \src "libresoc.v:108177.9-108177.17" case 1'1 case end @@ -168650,14 +168446,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:108429.3-108477.6" - process $proc$libresoc.v:108429$4199 + attribute \src "libresoc.v:108225.3-108273.6" + process $proc$libresoc.v:108225$4199 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:108430.5-108430.29" + attribute \src "libresoc.v:108226.5-108226.29" switch \initial - attribute \src "libresoc.v:108430.9-108430.17" + attribute \src "libresoc.v:108226.9-108226.17" case 1'1 case end @@ -168725,14 +168521,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:108478.3-108526.6" - process $proc$libresoc.v:108478$4200 + attribute \src "libresoc.v:108274.3-108322.6" + process $proc$libresoc.v:108274$4200 assign { } { } assign { } { } assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:108479.5-108479.29" + attribute \src "libresoc.v:108275.5-108275.29" switch \initial - attribute \src "libresoc.v:108479.9-108479.17" + attribute \src "libresoc.v:108275.9-108275.17" case 1'1 case end @@ -168800,14 +168596,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] end - attribute \src "libresoc.v:108527.3-108575.6" - process $proc$libresoc.v:108527$4201 + attribute \src "libresoc.v:108323.3-108371.6" + process $proc$libresoc.v:108323$4201 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:108528.5-108528.29" + attribute \src "libresoc.v:108324.5-108324.29" switch \initial - attribute \src "libresoc.v:108528.9-108528.17" + attribute \src "libresoc.v:108324.9-108324.17" case 1'1 case end @@ -168875,14 +168671,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "libresoc.v:108576.3-108624.6" - process $proc$libresoc.v:108576$4202 + attribute \src "libresoc.v:108372.3-108420.6" + process $proc$libresoc.v:108372$4202 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:108577.5-108577.29" + attribute \src "libresoc.v:108373.5-108373.29" switch \initial - attribute \src "libresoc.v:108577.9-108577.17" + attribute \src "libresoc.v:108373.9-108373.17" case 1'1 case end @@ -168950,14 +168746,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0] end - attribute \src "libresoc.v:108625.3-108673.6" - process $proc$libresoc.v:108625$4203 + attribute \src "libresoc.v:108421.3-108469.6" + process $proc$libresoc.v:108421$4203 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:108626.5-108626.29" + attribute \src "libresoc.v:108422.5-108422.29" switch \initial - attribute \src "libresoc.v:108626.9-108626.17" + attribute \src "libresoc.v:108422.9-108422.17" case 1'1 case end @@ -169025,14 +168821,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0] end - attribute \src "libresoc.v:108674.3-108722.6" - process $proc$libresoc.v:108674$4204 + attribute \src "libresoc.v:108470.3-108518.6" + process $proc$libresoc.v:108470$4204 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:108675.5-108675.29" + attribute \src "libresoc.v:108471.5-108471.29" switch \initial - attribute \src "libresoc.v:108675.9-108675.17" + attribute \src "libresoc.v:108471.9-108471.17" case 1'1 case end @@ -169100,14 +168896,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:108723.3-108771.6" - process $proc$libresoc.v:108723$4205 + attribute \src "libresoc.v:108519.3-108567.6" + process $proc$libresoc.v:108519$4205 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:108724.5-108724.29" + attribute \src "libresoc.v:108520.5-108520.29" switch \initial - attribute \src "libresoc.v:108724.9-108724.17" + attribute \src "libresoc.v:108520.9-108520.17" case 1'1 case end @@ -169175,14 +168971,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:108772.3-108820.6" - process $proc$libresoc.v:108772$4206 + attribute \src "libresoc.v:108568.3-108616.6" + process $proc$libresoc.v:108568$4206 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:108773.5-108773.29" + attribute \src "libresoc.v:108569.5-108569.29" switch \initial - attribute \src "libresoc.v:108773.9-108773.17" + attribute \src "libresoc.v:108569.9-108569.17" case 1'1 case end @@ -169250,14 +169046,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] end - attribute \src "libresoc.v:108821.3-108869.6" - process $proc$libresoc.v:108821$4207 + attribute \src "libresoc.v:108617.3-108665.6" + process $proc$libresoc.v:108617$4207 assign { } { } assign { } { } assign $0\dec31_dec_sub23_out_sel[2:0] $1\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:108822.5-108822.29" + attribute \src "libresoc.v:108618.5-108618.29" switch \initial - attribute \src "libresoc.v:108822.9-108822.17" + attribute \src "libresoc.v:108618.9-108618.17" case 1'1 case end @@ -169327,144 +169123,144 @@ module \dec31_dec_sub23 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:108875.1-109852.10" +attribute \src "libresoc.v:108671.1-109648.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" attribute \generator "nMigen" module \dec31_dec_sub24 - attribute \src "libresoc.v:109737.3-109755.6" + attribute \src "libresoc.v:109533.3-109551.6" wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:109756.3-109774.6" + attribute \src "libresoc.v:109552.3-109570.6" wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:109509.3-109527.6" + attribute \src "libresoc.v:109305.3-109323.6" wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:109585.3-109603.6" + attribute \src "libresoc.v:109381.3-109399.6" wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:109243.3-109261.6" + attribute \src "libresoc.v:109039.3-109057.6" wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:109262.3-109280.6" + attribute \src "libresoc.v:109058.3-109076.6" wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:109490.3-109508.6" + attribute \src "libresoc.v:109286.3-109304.6" wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:109566.3-109584.6" + attribute \src "libresoc.v:109362.3-109380.6" wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:109642.3-109660.6" + attribute \src "libresoc.v:109438.3-109456.6" wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:109224.3-109242.6" + attribute \src "libresoc.v:109020.3-109038.6" wire width 14 $0\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:109775.3-109793.6" + attribute \src "libresoc.v:109571.3-109589.6" wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:109794.3-109812.6" + attribute \src "libresoc.v:109590.3-109608.6" wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:109813.3-109831.6" + attribute \src "libresoc.v:109609.3-109627.6" wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:109433.3-109451.6" + attribute \src "libresoc.v:109229.3-109247.6" wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:109528.3-109546.6" + attribute \src "libresoc.v:109324.3-109342.6" wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:109547.3-109565.6" + attribute \src "libresoc.v:109343.3-109361.6" wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:109661.3-109679.6" + attribute \src "libresoc.v:109457.3-109475.6" wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:109414.3-109432.6" + attribute \src "libresoc.v:109210.3-109228.6" wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:109699.3-109717.6" + attribute \src "libresoc.v:109495.3-109513.6" wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:109832.3-109850.6" + attribute \src "libresoc.v:109628.3-109646.6" wire width 3 $0\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:109471.3-109489.6" + attribute \src "libresoc.v:109267.3-109285.6" wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:109623.3-109641.6" + attribute \src "libresoc.v:109419.3-109437.6" wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:109718.3-109736.6" + attribute \src "libresoc.v:109514.3-109532.6" wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:109680.3-109698.6" + attribute \src "libresoc.v:109476.3-109494.6" wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:109604.3-109622.6" + attribute \src "libresoc.v:109400.3-109418.6" wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:109376.3-109394.6" + attribute \src "libresoc.v:109172.3-109190.6" wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:109395.3-109413.6" + attribute \src "libresoc.v:109191.3-109209.6" wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:109281.3-109299.6" + attribute \src "libresoc.v:109077.3-109095.6" wire width 3 $0\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:109300.3-109318.6" + attribute \src "libresoc.v:109096.3-109114.6" wire width 3 $0\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:109319.3-109337.6" + attribute \src "libresoc.v:109115.3-109133.6" wire width 3 $0\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:109357.3-109375.6" + attribute \src "libresoc.v:109153.3-109171.6" wire width 3 $0\dec31_dec_sub24_sv_out2[2:0] - attribute \src "libresoc.v:109338.3-109356.6" + attribute \src "libresoc.v:109134.3-109152.6" wire width 3 $0\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:109452.3-109470.6" + attribute \src "libresoc.v:109248.3-109266.6" wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:108876.7-108876.20" + attribute \src "libresoc.v:108672.7-108672.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109737.3-109755.6" + attribute \src "libresoc.v:109533.3-109551.6" wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:109756.3-109774.6" + attribute \src "libresoc.v:109552.3-109570.6" wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:109509.3-109527.6" + attribute \src "libresoc.v:109305.3-109323.6" wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:109585.3-109603.6" + attribute \src "libresoc.v:109381.3-109399.6" wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:109243.3-109261.6" + attribute \src "libresoc.v:109039.3-109057.6" wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:109262.3-109280.6" + attribute \src "libresoc.v:109058.3-109076.6" wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:109490.3-109508.6" + attribute \src "libresoc.v:109286.3-109304.6" wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:109566.3-109584.6" + attribute \src "libresoc.v:109362.3-109380.6" wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:109642.3-109660.6" + attribute \src "libresoc.v:109438.3-109456.6" wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:109224.3-109242.6" + attribute \src "libresoc.v:109020.3-109038.6" wire width 14 $1\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:109775.3-109793.6" + attribute \src "libresoc.v:109571.3-109589.6" wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:109794.3-109812.6" + attribute \src "libresoc.v:109590.3-109608.6" wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:109813.3-109831.6" + attribute \src "libresoc.v:109609.3-109627.6" wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:109433.3-109451.6" + attribute \src "libresoc.v:109229.3-109247.6" wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:109528.3-109546.6" + attribute \src "libresoc.v:109324.3-109342.6" wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:109547.3-109565.6" + attribute \src "libresoc.v:109343.3-109361.6" wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:109661.3-109679.6" + attribute \src "libresoc.v:109457.3-109475.6" wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:109414.3-109432.6" + attribute \src "libresoc.v:109210.3-109228.6" wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:109699.3-109717.6" + attribute \src "libresoc.v:109495.3-109513.6" wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:109832.3-109850.6" + attribute \src "libresoc.v:109628.3-109646.6" wire width 3 $1\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:109471.3-109489.6" + attribute \src "libresoc.v:109267.3-109285.6" wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:109623.3-109641.6" + attribute \src "libresoc.v:109419.3-109437.6" wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:109718.3-109736.6" + attribute \src "libresoc.v:109514.3-109532.6" wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:109680.3-109698.6" + attribute \src "libresoc.v:109476.3-109494.6" wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:109604.3-109622.6" + attribute \src "libresoc.v:109400.3-109418.6" wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:109376.3-109394.6" + attribute \src "libresoc.v:109172.3-109190.6" wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:109395.3-109413.6" + attribute \src "libresoc.v:109191.3-109209.6" wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:109281.3-109299.6" + attribute \src "libresoc.v:109077.3-109095.6" wire width 3 $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:109300.3-109318.6" + attribute \src "libresoc.v:109096.3-109114.6" wire width 3 $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:109319.3-109337.6" + attribute \src "libresoc.v:109115.3-109133.6" wire width 3 $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:109357.3-109375.6" + attribute \src "libresoc.v:109153.3-109171.6" wire width 3 $1\dec31_dec_sub24_sv_out2[2:0] - attribute \src "libresoc.v:109338.3-109356.6" + attribute \src "libresoc.v:109134.3-109152.6" wire width 3 $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:109452.3-109470.6" + attribute \src "libresoc.v:109248.3-109266.6" wire width 2 $1\dec31_dec_sub24_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -169776,28 +169572,28 @@ module \dec31_dec_sub24 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub24_upd - attribute \src "libresoc.v:108876.7-108876.15" + attribute \src "libresoc.v:108672.7-108672.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:108876.7-108876.20" - process $proc$libresoc.v:108876$4242 + attribute \src "libresoc.v:108672.7-108672.20" + process $proc$libresoc.v:108672$4242 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109224.3-109242.6" - process $proc$libresoc.v:109224$4209 + attribute \src "libresoc.v:109020.3-109038.6" + process $proc$libresoc.v:109020$4209 assign { } { } assign { } { } assign $0\dec31_dec_sub24_function_unit[13:0] $1\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:109225.5-109225.29" + attribute \src "libresoc.v:109021.5-109021.29" switch \initial - attribute \src "libresoc.v:109225.9-109225.17" + attribute \src "libresoc.v:109021.9-109021.17" case 1'1 case end @@ -169825,14 +169621,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[13:0] end - attribute \src "libresoc.v:109243.3-109261.6" - process $proc$libresoc.v:109243$4210 + attribute \src "libresoc.v:109039.3-109057.6" + process $proc$libresoc.v:109039$4210 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:109244.5-109244.29" + attribute \src "libresoc.v:109040.5-109040.29" switch \initial - attribute \src "libresoc.v:109244.9-109244.17" + attribute \src "libresoc.v:109040.9-109040.17" case 1'1 case end @@ -169860,14 +169656,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:109262.3-109280.6" - process $proc$libresoc.v:109262$4211 + attribute \src "libresoc.v:109058.3-109076.6" + process $proc$libresoc.v:109058$4211 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:109263.5-109263.29" + attribute \src "libresoc.v:109059.5-109059.29" switch \initial - attribute \src "libresoc.v:109263.9-109263.17" + attribute \src "libresoc.v:109059.9-109059.17" case 1'1 case end @@ -169895,14 +169691,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] end - attribute \src "libresoc.v:109281.3-109299.6" - process $proc$libresoc.v:109281$4212 + attribute \src "libresoc.v:109077.3-109095.6" + process $proc$libresoc.v:109077$4212 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:109282.5-109282.29" + attribute \src "libresoc.v:109078.5-109078.29" switch \initial - attribute \src "libresoc.v:109282.9-109282.17" + attribute \src "libresoc.v:109078.9-109078.17" case 1'1 case end @@ -169930,14 +169726,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0] end - attribute \src "libresoc.v:109300.3-109318.6" - process $proc$libresoc.v:109300$4213 + attribute \src "libresoc.v:109096.3-109114.6" + process $proc$libresoc.v:109096$4213 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:109301.5-109301.29" + attribute \src "libresoc.v:109097.5-109097.29" switch \initial - attribute \src "libresoc.v:109301.9-109301.17" + attribute \src "libresoc.v:109097.9-109097.17" case 1'1 case end @@ -169965,14 +169761,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0] end - attribute \src "libresoc.v:109319.3-109337.6" - process $proc$libresoc.v:109319$4214 + attribute \src "libresoc.v:109115.3-109133.6" + process $proc$libresoc.v:109115$4214 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:109320.5-109320.29" + attribute \src "libresoc.v:109116.5-109116.29" switch \initial - attribute \src "libresoc.v:109320.9-109320.17" + attribute \src "libresoc.v:109116.9-109116.17" case 1'1 case end @@ -170000,14 +169796,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0] end - attribute \src "libresoc.v:109338.3-109356.6" - process $proc$libresoc.v:109338$4215 + attribute \src "libresoc.v:109134.3-109152.6" + process $proc$libresoc.v:109134$4215 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:109339.5-109339.29" + attribute \src "libresoc.v:109135.5-109135.29" switch \initial - attribute \src "libresoc.v:109339.9-109339.17" + attribute \src "libresoc.v:109135.9-109135.17" case 1'1 case end @@ -170035,14 +169831,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0] end - attribute \src "libresoc.v:109357.3-109375.6" - process $proc$libresoc.v:109357$4216 + attribute \src "libresoc.v:109153.3-109171.6" + process $proc$libresoc.v:109153$4216 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out2[2:0] $1\dec31_dec_sub24_sv_out2[2:0] - attribute \src "libresoc.v:109358.5-109358.29" + attribute \src "libresoc.v:109154.5-109154.29" switch \initial - attribute \src "libresoc.v:109358.9-109358.17" + attribute \src "libresoc.v:109154.9-109154.17" case 1'1 case end @@ -170070,14 +169866,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_out2 $0\dec31_dec_sub24_sv_out2[2:0] end - attribute \src "libresoc.v:109376.3-109394.6" - process $proc$libresoc.v:109376$4217 + attribute \src "libresoc.v:109172.3-109190.6" + process $proc$libresoc.v:109172$4217 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:109377.5-109377.29" + attribute \src "libresoc.v:109173.5-109173.29" switch \initial - attribute \src "libresoc.v:109377.9-109377.17" + attribute \src "libresoc.v:109173.9-109173.17" case 1'1 case end @@ -170105,14 +169901,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0] end - attribute \src "libresoc.v:109395.3-109413.6" - process $proc$libresoc.v:109395$4218 + attribute \src "libresoc.v:109191.3-109209.6" + process $proc$libresoc.v:109191$4218 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:109396.5-109396.29" + attribute \src "libresoc.v:109192.5-109192.29" switch \initial - attribute \src "libresoc.v:109396.9-109396.17" + attribute \src "libresoc.v:109192.9-109192.17" case 1'1 case end @@ -170140,14 +169936,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0] end - attribute \src "libresoc.v:109414.3-109432.6" - process $proc$libresoc.v:109414$4219 + attribute \src "libresoc.v:109210.3-109228.6" + process $proc$libresoc.v:109210$4219 assign { } { } assign { } { } assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:109415.5-109415.29" + attribute \src "libresoc.v:109211.5-109211.29" switch \initial - attribute \src "libresoc.v:109415.9-109415.17" + attribute \src "libresoc.v:109211.9-109211.17" case 1'1 case end @@ -170175,14 +169971,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end - attribute \src "libresoc.v:109433.3-109451.6" - process $proc$libresoc.v:109433$4220 + attribute \src "libresoc.v:109229.3-109247.6" + process $proc$libresoc.v:109229$4220 assign { } { } assign { } { } assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:109434.5-109434.29" + attribute \src "libresoc.v:109230.5-109230.29" switch \initial - attribute \src "libresoc.v:109434.9-109434.17" + attribute \src "libresoc.v:109230.9-109230.17" case 1'1 case end @@ -170210,14 +170006,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:109452.3-109470.6" - process $proc$libresoc.v:109452$4221 + attribute \src "libresoc.v:109248.3-109266.6" + process $proc$libresoc.v:109248$4221 assign { } { } assign { } { } assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:109453.5-109453.29" + attribute \src "libresoc.v:109249.5-109249.29" switch \initial - attribute \src "libresoc.v:109453.9-109453.17" + attribute \src "libresoc.v:109249.9-109249.17" case 1'1 case end @@ -170245,14 +170041,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end - attribute \src "libresoc.v:109471.3-109489.6" - process $proc$libresoc.v:109471$4222 + attribute \src "libresoc.v:109267.3-109285.6" + process $proc$libresoc.v:109267$4222 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:109472.5-109472.29" + attribute \src "libresoc.v:109268.5-109268.29" switch \initial - attribute \src "libresoc.v:109472.9-109472.17" + attribute \src "libresoc.v:109268.9-109268.17" case 1'1 case end @@ -170280,14 +170076,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:109490.3-109508.6" - process $proc$libresoc.v:109490$4223 + attribute \src "libresoc.v:109286.3-109304.6" + process $proc$libresoc.v:109286$4223 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:109491.5-109491.29" + attribute \src "libresoc.v:109287.5-109287.29" switch \initial - attribute \src "libresoc.v:109491.9-109491.17" + attribute \src "libresoc.v:109287.9-109287.17" case 1'1 case end @@ -170315,14 +170111,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:109509.3-109527.6" - process $proc$libresoc.v:109509$4224 + attribute \src "libresoc.v:109305.3-109323.6" + process $proc$libresoc.v:109305$4224 assign { } { } assign { } { } assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:109510.5-109510.29" + attribute \src "libresoc.v:109306.5-109306.29" switch \initial - attribute \src "libresoc.v:109510.9-109510.17" + attribute \src "libresoc.v:109306.9-109306.17" case 1'1 case end @@ -170350,14 +170146,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "libresoc.v:109528.3-109546.6" - process $proc$libresoc.v:109528$4225 + attribute \src "libresoc.v:109324.3-109342.6" + process $proc$libresoc.v:109324$4225 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:109529.5-109529.29" + attribute \src "libresoc.v:109325.5-109325.29" switch \initial - attribute \src "libresoc.v:109529.9-109529.17" + attribute \src "libresoc.v:109325.9-109325.17" case 1'1 case end @@ -170385,14 +170181,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:109547.3-109565.6" - process $proc$libresoc.v:109547$4226 + attribute \src "libresoc.v:109343.3-109361.6" + process $proc$libresoc.v:109343$4226 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:109548.5-109548.29" + attribute \src "libresoc.v:109344.5-109344.29" switch \initial - attribute \src "libresoc.v:109548.9-109548.17" + attribute \src "libresoc.v:109344.9-109344.17" case 1'1 case end @@ -170420,14 +170216,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] end - attribute \src "libresoc.v:109566.3-109584.6" - process $proc$libresoc.v:109566$4227 + attribute \src "libresoc.v:109362.3-109380.6" + process $proc$libresoc.v:109362$4227 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:109567.5-109567.29" + attribute \src "libresoc.v:109363.5-109363.29" switch \initial - attribute \src "libresoc.v:109567.9-109567.17" + attribute \src "libresoc.v:109363.9-109363.17" case 1'1 case end @@ -170455,14 +170251,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end - attribute \src "libresoc.v:109585.3-109603.6" - process $proc$libresoc.v:109585$4228 + attribute \src "libresoc.v:109381.3-109399.6" + process $proc$libresoc.v:109381$4228 assign { } { } assign { } { } assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:109586.5-109586.29" + attribute \src "libresoc.v:109382.5-109382.29" switch \initial - attribute \src "libresoc.v:109586.9-109586.17" + attribute \src "libresoc.v:109382.9-109382.17" case 1'1 case end @@ -170490,14 +170286,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] end - attribute \src "libresoc.v:109604.3-109622.6" - process $proc$libresoc.v:109604$4229 + attribute \src "libresoc.v:109400.3-109418.6" + process $proc$libresoc.v:109400$4229 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:109605.5-109605.29" + attribute \src "libresoc.v:109401.5-109401.29" switch \initial - attribute \src "libresoc.v:109605.9-109605.17" + attribute \src "libresoc.v:109401.9-109401.17" case 1'1 case end @@ -170525,14 +170321,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end - attribute \src "libresoc.v:109623.3-109641.6" - process $proc$libresoc.v:109623$4230 + attribute \src "libresoc.v:109419.3-109437.6" + process $proc$libresoc.v:109419$4230 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:109624.5-109624.29" + attribute \src "libresoc.v:109420.5-109420.29" switch \initial - attribute \src "libresoc.v:109624.9-109624.17" + attribute \src "libresoc.v:109420.9-109420.17" case 1'1 case end @@ -170560,14 +170356,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] end - attribute \src "libresoc.v:109642.3-109660.6" - process $proc$libresoc.v:109642$4231 + attribute \src "libresoc.v:109438.3-109456.6" + process $proc$libresoc.v:109438$4231 assign { } { } assign { } { } assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:109643.5-109643.29" + attribute \src "libresoc.v:109439.5-109439.29" switch \initial - attribute \src "libresoc.v:109643.9-109643.17" + attribute \src "libresoc.v:109439.9-109439.17" case 1'1 case end @@ -170595,14 +170391,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] end - attribute \src "libresoc.v:109661.3-109679.6" - process $proc$libresoc.v:109661$4232 + attribute \src "libresoc.v:109457.3-109475.6" + process $proc$libresoc.v:109457$4232 assign { } { } assign { } { } assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:109662.5-109662.29" + attribute \src "libresoc.v:109458.5-109458.29" switch \initial - attribute \src "libresoc.v:109662.9-109662.17" + attribute \src "libresoc.v:109458.9-109458.17" case 1'1 case end @@ -170630,14 +170426,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:109680.3-109698.6" - process $proc$libresoc.v:109680$4233 + attribute \src "libresoc.v:109476.3-109494.6" + process $proc$libresoc.v:109476$4233 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:109681.5-109681.29" + attribute \src "libresoc.v:109477.5-109477.29" switch \initial - attribute \src "libresoc.v:109681.9-109681.17" + attribute \src "libresoc.v:109477.9-109477.17" case 1'1 case end @@ -170665,14 +170461,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:109699.3-109717.6" - process $proc$libresoc.v:109699$4234 + attribute \src "libresoc.v:109495.3-109513.6" + process $proc$libresoc.v:109495$4234 assign { } { } assign { } { } assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:109700.5-109700.29" + attribute \src "libresoc.v:109496.5-109496.29" switch \initial - attribute \src "libresoc.v:109700.9-109700.17" + attribute \src "libresoc.v:109496.9-109496.17" case 1'1 case end @@ -170700,14 +170496,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] end - attribute \src "libresoc.v:109718.3-109736.6" - process $proc$libresoc.v:109718$4235 + attribute \src "libresoc.v:109514.3-109532.6" + process $proc$libresoc.v:109514$4235 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:109719.5-109719.29" + attribute \src "libresoc.v:109515.5-109515.29" switch \initial - attribute \src "libresoc.v:109719.9-109719.17" + attribute \src "libresoc.v:109515.9-109515.17" case 1'1 case end @@ -170735,14 +170531,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "libresoc.v:109737.3-109755.6" - process $proc$libresoc.v:109737$4236 + attribute \src "libresoc.v:109533.3-109551.6" + process $proc$libresoc.v:109533$4236 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:109738.5-109738.29" + attribute \src "libresoc.v:109534.5-109534.29" switch \initial - attribute \src "libresoc.v:109738.9-109738.17" + attribute \src "libresoc.v:109534.9-109534.17" case 1'1 case end @@ -170770,14 +170566,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0] end - attribute \src "libresoc.v:109756.3-109774.6" - process $proc$libresoc.v:109756$4237 + attribute \src "libresoc.v:109552.3-109570.6" + process $proc$libresoc.v:109552$4237 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:109757.5-109757.29" + attribute \src "libresoc.v:109553.5-109553.29" switch \initial - attribute \src "libresoc.v:109757.9-109757.17" + attribute \src "libresoc.v:109553.9-109553.17" case 1'1 case end @@ -170805,14 +170601,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0] end - attribute \src "libresoc.v:109775.3-109793.6" - process $proc$libresoc.v:109775$4238 + attribute \src "libresoc.v:109571.3-109589.6" + process $proc$libresoc.v:109571$4238 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:109776.5-109776.29" + attribute \src "libresoc.v:109572.5-109572.29" switch \initial - attribute \src "libresoc.v:109776.9-109776.17" + attribute \src "libresoc.v:109572.9-109572.17" case 1'1 case end @@ -170840,14 +170636,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] end - attribute \src "libresoc.v:109794.3-109812.6" - process $proc$libresoc.v:109794$4239 + attribute \src "libresoc.v:109590.3-109608.6" + process $proc$libresoc.v:109590$4239 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:109795.5-109795.29" + attribute \src "libresoc.v:109591.5-109591.29" switch \initial - attribute \src "libresoc.v:109795.9-109795.17" + attribute \src "libresoc.v:109591.9-109591.17" case 1'1 case end @@ -170875,14 +170671,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:109813.3-109831.6" - process $proc$libresoc.v:109813$4240 + attribute \src "libresoc.v:109609.3-109627.6" + process $proc$libresoc.v:109609$4240 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:109814.5-109814.29" + attribute \src "libresoc.v:109610.5-109610.29" switch \initial - attribute \src "libresoc.v:109814.9-109814.17" + attribute \src "libresoc.v:109610.9-109610.17" case 1'1 case end @@ -170910,14 +170706,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] end - attribute \src "libresoc.v:109832.3-109850.6" - process $proc$libresoc.v:109832$4241 + attribute \src "libresoc.v:109628.3-109646.6" + process $proc$libresoc.v:109628$4241 assign { } { } assign { } { } assign $0\dec31_dec_sub24_out_sel[2:0] $1\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:109833.5-109833.29" + attribute \src "libresoc.v:109629.5-109629.29" switch \initial - attribute \src "libresoc.v:109833.9-109833.17" + attribute \src "libresoc.v:109629.9-109629.17" case 1'1 case end @@ -170947,144 +170743,144 @@ module \dec31_dec_sub24 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:109856.1-111922.10" +attribute \src "libresoc.v:109652.1-111718.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" attribute \generator "nMigen" module \dec31_dec_sub26 - attribute \src "libresoc.v:111609.3-111660.6" + attribute \src "libresoc.v:111405.3-111456.6" wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:111661.3-111712.6" + attribute \src "libresoc.v:111457.3-111508.6" wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:110985.3-111036.6" + attribute \src "libresoc.v:110781.3-110832.6" wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:111193.3-111244.6" + attribute \src "libresoc.v:110989.3-111040.6" wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:110257.3-110308.6" + attribute \src "libresoc.v:110053.3-110104.6" wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:110309.3-110360.6" + attribute \src "libresoc.v:110105.3-110156.6" wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:110933.3-110984.6" + attribute \src "libresoc.v:110729.3-110780.6" wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:111141.3-111192.6" + attribute \src "libresoc.v:110937.3-110988.6" wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:111349.3-111400.6" + attribute \src "libresoc.v:111145.3-111196.6" wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:110205.3-110256.6" + attribute \src "libresoc.v:110001.3-110052.6" wire width 14 $0\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:111713.3-111764.6" + attribute \src "libresoc.v:111509.3-111560.6" wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:111765.3-111816.6" + attribute \src "libresoc.v:111561.3-111612.6" wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:111817.3-111868.6" + attribute \src "libresoc.v:111613.3-111664.6" wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:110777.3-110828.6" + attribute \src "libresoc.v:110573.3-110624.6" wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:111037.3-111088.6" + attribute \src "libresoc.v:110833.3-110884.6" wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:111089.3-111140.6" + attribute \src "libresoc.v:110885.3-110936.6" wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:111401.3-111452.6" + attribute \src "libresoc.v:111197.3-111248.6" wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:110725.3-110776.6" + attribute \src "libresoc.v:110521.3-110572.6" wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:111505.3-111556.6" + attribute \src "libresoc.v:111301.3-111352.6" wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:111869.3-111920.6" + attribute \src "libresoc.v:111665.3-111716.6" wire width 3 $0\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:110881.3-110932.6" + attribute \src "libresoc.v:110677.3-110728.6" wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:111297.3-111348.6" + attribute \src "libresoc.v:111093.3-111144.6" wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:111557.3-111608.6" + attribute \src "libresoc.v:111353.3-111404.6" wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:111453.3-111504.6" + attribute \src "libresoc.v:111249.3-111300.6" wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:111245.3-111296.6" + attribute \src "libresoc.v:111041.3-111092.6" wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:110621.3-110672.6" + attribute \src "libresoc.v:110417.3-110468.6" wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:110673.3-110724.6" + attribute \src "libresoc.v:110469.3-110520.6" wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:110361.3-110412.6" + attribute \src "libresoc.v:110157.3-110208.6" wire width 3 $0\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:110413.3-110464.6" + attribute \src "libresoc.v:110209.3-110260.6" wire width 3 $0\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:110465.3-110516.6" + attribute \src "libresoc.v:110261.3-110312.6" wire width 3 $0\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:110569.3-110620.6" + attribute \src "libresoc.v:110365.3-110416.6" wire width 3 $0\dec31_dec_sub26_sv_out2[2:0] - attribute \src "libresoc.v:110517.3-110568.6" + attribute \src "libresoc.v:110313.3-110364.6" wire width 3 $0\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:110829.3-110880.6" + attribute \src "libresoc.v:110625.3-110676.6" wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:109857.7-109857.20" + attribute \src "libresoc.v:109653.7-109653.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111609.3-111660.6" + attribute \src "libresoc.v:111405.3-111456.6" wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:111661.3-111712.6" + attribute \src "libresoc.v:111457.3-111508.6" wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:110985.3-111036.6" + attribute \src "libresoc.v:110781.3-110832.6" wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:111193.3-111244.6" + attribute \src "libresoc.v:110989.3-111040.6" wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:110257.3-110308.6" + attribute \src "libresoc.v:110053.3-110104.6" wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:110309.3-110360.6" + attribute \src "libresoc.v:110105.3-110156.6" wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:110933.3-110984.6" + attribute \src "libresoc.v:110729.3-110780.6" wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:111141.3-111192.6" + attribute \src "libresoc.v:110937.3-110988.6" wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:111349.3-111400.6" + attribute \src "libresoc.v:111145.3-111196.6" wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:110205.3-110256.6" + attribute \src "libresoc.v:110001.3-110052.6" wire width 14 $1\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:111713.3-111764.6" + attribute \src "libresoc.v:111509.3-111560.6" wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:111765.3-111816.6" + attribute \src "libresoc.v:111561.3-111612.6" wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:111817.3-111868.6" + attribute \src "libresoc.v:111613.3-111664.6" wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:110777.3-110828.6" + attribute \src "libresoc.v:110573.3-110624.6" wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:111037.3-111088.6" + attribute \src "libresoc.v:110833.3-110884.6" wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:111089.3-111140.6" + attribute \src "libresoc.v:110885.3-110936.6" wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:111401.3-111452.6" + attribute \src "libresoc.v:111197.3-111248.6" wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:110725.3-110776.6" + attribute \src "libresoc.v:110521.3-110572.6" wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:111505.3-111556.6" + attribute \src "libresoc.v:111301.3-111352.6" wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:111869.3-111920.6" + attribute \src "libresoc.v:111665.3-111716.6" wire width 3 $1\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:110881.3-110932.6" + attribute \src "libresoc.v:110677.3-110728.6" wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:111297.3-111348.6" + attribute \src "libresoc.v:111093.3-111144.6" wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:111557.3-111608.6" + attribute \src "libresoc.v:111353.3-111404.6" wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:111453.3-111504.6" + attribute \src "libresoc.v:111249.3-111300.6" wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:111245.3-111296.6" + attribute \src "libresoc.v:111041.3-111092.6" wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:110621.3-110672.6" + attribute \src "libresoc.v:110417.3-110468.6" wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:110673.3-110724.6" + attribute \src "libresoc.v:110469.3-110520.6" wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:110361.3-110412.6" + attribute \src "libresoc.v:110157.3-110208.6" wire width 3 $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:110413.3-110464.6" + attribute \src "libresoc.v:110209.3-110260.6" wire width 3 $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:110465.3-110516.6" + attribute \src "libresoc.v:110261.3-110312.6" wire width 3 $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:110569.3-110620.6" + attribute \src "libresoc.v:110365.3-110416.6" wire width 3 $1\dec31_dec_sub26_sv_out2[2:0] - attribute \src "libresoc.v:110517.3-110568.6" + attribute \src "libresoc.v:110313.3-110364.6" wire width 3 $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:110829.3-110880.6" + attribute \src "libresoc.v:110625.3-110676.6" wire width 2 $1\dec31_dec_sub26_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -171396,28 +171192,28 @@ module \dec31_dec_sub26 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub26_upd - attribute \src "libresoc.v:109857.7-109857.15" + attribute \src "libresoc.v:109653.7-109653.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:109857.7-109857.20" - process $proc$libresoc.v:109857$4276 + attribute \src "libresoc.v:109653.7-109653.20" + process $proc$libresoc.v:109653$4276 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:110205.3-110256.6" - process $proc$libresoc.v:110205$4243 + attribute \src "libresoc.v:110001.3-110052.6" + process $proc$libresoc.v:110001$4243 assign { } { } assign { } { } assign $0\dec31_dec_sub26_function_unit[13:0] $1\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:110206.5-110206.29" + attribute \src "libresoc.v:110002.5-110002.29" switch \initial - attribute \src "libresoc.v:110206.9-110206.17" + attribute \src "libresoc.v:110002.9-110002.17" case 1'1 case end @@ -171489,14 +171285,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:110257.3-110308.6" - process $proc$libresoc.v:110257$4244 + attribute \src "libresoc.v:110053.3-110104.6" + process $proc$libresoc.v:110053$4244 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:110258.5-110258.29" + attribute \src "libresoc.v:110054.5-110054.29" switch \initial - attribute \src "libresoc.v:110258.9-110258.17" + attribute \src "libresoc.v:110054.9-110054.17" case 1'1 case end @@ -171568,14 +171364,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:110309.3-110360.6" - process $proc$libresoc.v:110309$4245 + attribute \src "libresoc.v:110105.3-110156.6" + process $proc$libresoc.v:110105$4245 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:110310.5-110310.29" + attribute \src "libresoc.v:110106.5-110106.29" switch \initial - attribute \src "libresoc.v:110310.9-110310.17" + attribute \src "libresoc.v:110106.9-110106.17" case 1'1 case end @@ -171647,14 +171443,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:110361.3-110412.6" - process $proc$libresoc.v:110361$4246 + attribute \src "libresoc.v:110157.3-110208.6" + process $proc$libresoc.v:110157$4246 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:110362.5-110362.29" + attribute \src "libresoc.v:110158.5-110158.29" switch \initial - attribute \src "libresoc.v:110362.9-110362.17" + attribute \src "libresoc.v:110158.9-110158.17" case 1'1 case end @@ -171726,14 +171522,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0] end - attribute \src "libresoc.v:110413.3-110464.6" - process $proc$libresoc.v:110413$4247 + attribute \src "libresoc.v:110209.3-110260.6" + process $proc$libresoc.v:110209$4247 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:110414.5-110414.29" + attribute \src "libresoc.v:110210.5-110210.29" switch \initial - attribute \src "libresoc.v:110414.9-110414.17" + attribute \src "libresoc.v:110210.9-110210.17" case 1'1 case end @@ -171805,14 +171601,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0] end - attribute \src "libresoc.v:110465.3-110516.6" - process $proc$libresoc.v:110465$4248 + attribute \src "libresoc.v:110261.3-110312.6" + process $proc$libresoc.v:110261$4248 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:110466.5-110466.29" + attribute \src "libresoc.v:110262.5-110262.29" switch \initial - attribute \src "libresoc.v:110466.9-110466.17" + attribute \src "libresoc.v:110262.9-110262.17" case 1'1 case end @@ -171884,14 +171680,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0] end - attribute \src "libresoc.v:110517.3-110568.6" - process $proc$libresoc.v:110517$4249 + attribute \src "libresoc.v:110313.3-110364.6" + process $proc$libresoc.v:110313$4249 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:110518.5-110518.29" + attribute \src "libresoc.v:110314.5-110314.29" switch \initial - attribute \src "libresoc.v:110518.9-110518.17" + attribute \src "libresoc.v:110314.9-110314.17" case 1'1 case end @@ -171963,14 +171759,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0] end - attribute \src "libresoc.v:110569.3-110620.6" - process $proc$libresoc.v:110569$4250 + attribute \src "libresoc.v:110365.3-110416.6" + process $proc$libresoc.v:110365$4250 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out2[2:0] $1\dec31_dec_sub26_sv_out2[2:0] - attribute \src "libresoc.v:110570.5-110570.29" + attribute \src "libresoc.v:110366.5-110366.29" switch \initial - attribute \src "libresoc.v:110570.9-110570.17" + attribute \src "libresoc.v:110366.9-110366.17" case 1'1 case end @@ -172042,14 +171838,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_out2 $0\dec31_dec_sub26_sv_out2[2:0] end - attribute \src "libresoc.v:110621.3-110672.6" - process $proc$libresoc.v:110621$4251 + attribute \src "libresoc.v:110417.3-110468.6" + process $proc$libresoc.v:110417$4251 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:110622.5-110622.29" + attribute \src "libresoc.v:110418.5-110418.29" switch \initial - attribute \src "libresoc.v:110622.9-110622.17" + attribute \src "libresoc.v:110418.9-110418.17" case 1'1 case end @@ -172121,14 +171917,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0] end - attribute \src "libresoc.v:110673.3-110724.6" - process $proc$libresoc.v:110673$4252 + attribute \src "libresoc.v:110469.3-110520.6" + process $proc$libresoc.v:110469$4252 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:110674.5-110674.29" + attribute \src "libresoc.v:110470.5-110470.29" switch \initial - attribute \src "libresoc.v:110674.9-110674.17" + attribute \src "libresoc.v:110470.9-110470.17" case 1'1 case end @@ -172200,14 +171996,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0] end - attribute \src "libresoc.v:110725.3-110776.6" - process $proc$libresoc.v:110725$4253 + attribute \src "libresoc.v:110521.3-110572.6" + process $proc$libresoc.v:110521$4253 assign { } { } assign { } { } assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:110726.5-110726.29" + attribute \src "libresoc.v:110522.5-110522.29" switch \initial - attribute \src "libresoc.v:110726.9-110726.17" + attribute \src "libresoc.v:110522.9-110522.17" case 1'1 case end @@ -172279,14 +172075,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:110777.3-110828.6" - process $proc$libresoc.v:110777$4254 + attribute \src "libresoc.v:110573.3-110624.6" + process $proc$libresoc.v:110573$4254 assign { } { } assign { } { } assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:110778.5-110778.29" + attribute \src "libresoc.v:110574.5-110574.29" switch \initial - attribute \src "libresoc.v:110778.9-110778.17" + attribute \src "libresoc.v:110574.9-110574.17" case 1'1 case end @@ -172358,14 +172154,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:110829.3-110880.6" - process $proc$libresoc.v:110829$4255 + attribute \src "libresoc.v:110625.3-110676.6" + process $proc$libresoc.v:110625$4255 assign { } { } assign { } { } assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:110830.5-110830.29" + attribute \src "libresoc.v:110626.5-110626.29" switch \initial - attribute \src "libresoc.v:110830.9-110830.17" + attribute \src "libresoc.v:110626.9-110626.17" case 1'1 case end @@ -172437,14 +172233,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end - attribute \src "libresoc.v:110881.3-110932.6" - process $proc$libresoc.v:110881$4256 + attribute \src "libresoc.v:110677.3-110728.6" + process $proc$libresoc.v:110677$4256 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:110882.5-110882.29" + attribute \src "libresoc.v:110678.5-110678.29" switch \initial - attribute \src "libresoc.v:110882.9-110882.17" + attribute \src "libresoc.v:110678.9-110678.17" case 1'1 case end @@ -172516,14 +172312,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:110933.3-110984.6" - process $proc$libresoc.v:110933$4257 + attribute \src "libresoc.v:110729.3-110780.6" + process $proc$libresoc.v:110729$4257 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:110934.5-110934.29" + attribute \src "libresoc.v:110730.5-110730.29" switch \initial - attribute \src "libresoc.v:110934.9-110934.17" + attribute \src "libresoc.v:110730.9-110730.17" case 1'1 case end @@ -172595,14 +172391,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:110985.3-111036.6" - process $proc$libresoc.v:110985$4258 + attribute \src "libresoc.v:110781.3-110832.6" + process $proc$libresoc.v:110781$4258 assign { } { } assign { } { } assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:110986.5-110986.29" + attribute \src "libresoc.v:110782.5-110782.29" switch \initial - attribute \src "libresoc.v:110986.9-110986.17" + attribute \src "libresoc.v:110782.9-110782.17" case 1'1 case end @@ -172674,14 +172470,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end - attribute \src "libresoc.v:111037.3-111088.6" - process $proc$libresoc.v:111037$4259 + attribute \src "libresoc.v:110833.3-110884.6" + process $proc$libresoc.v:110833$4259 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:111038.5-111038.29" + attribute \src "libresoc.v:110834.5-110834.29" switch \initial - attribute \src "libresoc.v:111038.9-111038.17" + attribute \src "libresoc.v:110834.9-110834.17" case 1'1 case end @@ -172753,14 +172549,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:111089.3-111140.6" - process $proc$libresoc.v:111089$4260 + attribute \src "libresoc.v:110885.3-110936.6" + process $proc$libresoc.v:110885$4260 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:111090.5-111090.29" + attribute \src "libresoc.v:110886.5-110886.29" switch \initial - attribute \src "libresoc.v:111090.9-111090.17" + attribute \src "libresoc.v:110886.9-110886.17" case 1'1 case end @@ -172832,14 +172628,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:111141.3-111192.6" - process $proc$libresoc.v:111141$4261 + attribute \src "libresoc.v:110937.3-110988.6" + process $proc$libresoc.v:110937$4261 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:111142.5-111142.29" + attribute \src "libresoc.v:110938.5-110938.29" switch \initial - attribute \src "libresoc.v:111142.9-111142.17" + attribute \src "libresoc.v:110938.9-110938.17" case 1'1 case end @@ -172911,14 +172707,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:111193.3-111244.6" - process $proc$libresoc.v:111193$4262 + attribute \src "libresoc.v:110989.3-111040.6" + process $proc$libresoc.v:110989$4262 assign { } { } assign { } { } assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:111194.5-111194.29" + attribute \src "libresoc.v:110990.5-110990.29" switch \initial - attribute \src "libresoc.v:111194.9-111194.17" + attribute \src "libresoc.v:110990.9-110990.17" case 1'1 case end @@ -172990,14 +172786,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "libresoc.v:111245.3-111296.6" - process $proc$libresoc.v:111245$4263 + attribute \src "libresoc.v:111041.3-111092.6" + process $proc$libresoc.v:111041$4263 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:111246.5-111246.29" + attribute \src "libresoc.v:111042.5-111042.29" switch \initial - attribute \src "libresoc.v:111246.9-111246.17" + attribute \src "libresoc.v:111042.9-111042.17" case 1'1 case end @@ -173069,14 +172865,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end - attribute \src "libresoc.v:111297.3-111348.6" - process $proc$libresoc.v:111297$4264 + attribute \src "libresoc.v:111093.3-111144.6" + process $proc$libresoc.v:111093$4264 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:111298.5-111298.29" + attribute \src "libresoc.v:111094.5-111094.29" switch \initial - attribute \src "libresoc.v:111298.9-111298.17" + attribute \src "libresoc.v:111094.9-111094.17" case 1'1 case end @@ -173148,14 +172944,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "libresoc.v:111349.3-111400.6" - process $proc$libresoc.v:111349$4265 + attribute \src "libresoc.v:111145.3-111196.6" + process $proc$libresoc.v:111145$4265 assign { } { } assign { } { } assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:111350.5-111350.29" + attribute \src "libresoc.v:111146.5-111146.29" switch \initial - attribute \src "libresoc.v:111350.9-111350.17" + attribute \src "libresoc.v:111146.9-111146.17" case 1'1 case end @@ -173227,14 +173023,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end - attribute \src "libresoc.v:111401.3-111452.6" - process $proc$libresoc.v:111401$4266 + attribute \src "libresoc.v:111197.3-111248.6" + process $proc$libresoc.v:111197$4266 assign { } { } assign { } { } assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:111402.5-111402.29" + attribute \src "libresoc.v:111198.5-111198.29" switch \initial - attribute \src "libresoc.v:111402.9-111402.17" + attribute \src "libresoc.v:111198.9-111198.17" case 1'1 case end @@ -173306,14 +173102,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:111453.3-111504.6" - process $proc$libresoc.v:111453$4267 + attribute \src "libresoc.v:111249.3-111300.6" + process $proc$libresoc.v:111249$4267 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:111454.5-111454.29" + attribute \src "libresoc.v:111250.5-111250.29" switch \initial - attribute \src "libresoc.v:111454.9-111454.17" + attribute \src "libresoc.v:111250.9-111250.17" case 1'1 case end @@ -173385,14 +173181,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:111505.3-111556.6" - process $proc$libresoc.v:111505$4268 + attribute \src "libresoc.v:111301.3-111352.6" + process $proc$libresoc.v:111301$4268 assign { } { } assign { } { } assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:111506.5-111506.29" + attribute \src "libresoc.v:111302.5-111302.29" switch \initial - attribute \src "libresoc.v:111506.9-111506.17" + attribute \src "libresoc.v:111302.9-111302.17" case 1'1 case end @@ -173464,14 +173260,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - attribute \src "libresoc.v:111557.3-111608.6" - process $proc$libresoc.v:111557$4269 + attribute \src "libresoc.v:111353.3-111404.6" + process $proc$libresoc.v:111353$4269 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:111558.5-111558.29" + attribute \src "libresoc.v:111354.5-111354.29" switch \initial - attribute \src "libresoc.v:111558.9-111558.17" + attribute \src "libresoc.v:111354.9-111354.17" case 1'1 case end @@ -173543,14 +173339,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] end - attribute \src "libresoc.v:111609.3-111660.6" - process $proc$libresoc.v:111609$4270 + attribute \src "libresoc.v:111405.3-111456.6" + process $proc$libresoc.v:111405$4270 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:111610.5-111610.29" + attribute \src "libresoc.v:111406.5-111406.29" switch \initial - attribute \src "libresoc.v:111610.9-111610.17" + attribute \src "libresoc.v:111406.9-111406.17" case 1'1 case end @@ -173622,14 +173418,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0] end - attribute \src "libresoc.v:111661.3-111712.6" - process $proc$libresoc.v:111661$4271 + attribute \src "libresoc.v:111457.3-111508.6" + process $proc$libresoc.v:111457$4271 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:111662.5-111662.29" + attribute \src "libresoc.v:111458.5-111458.29" switch \initial - attribute \src "libresoc.v:111662.9-111662.17" + attribute \src "libresoc.v:111458.9-111458.17" case 1'1 case end @@ -173701,14 +173497,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0] end - attribute \src "libresoc.v:111713.3-111764.6" - process $proc$libresoc.v:111713$4272 + attribute \src "libresoc.v:111509.3-111560.6" + process $proc$libresoc.v:111509$4272 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:111714.5-111714.29" + attribute \src "libresoc.v:111510.5-111510.29" switch \initial - attribute \src "libresoc.v:111714.9-111714.17" + attribute \src "libresoc.v:111510.9-111510.17" case 1'1 case end @@ -173780,14 +173576,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:111765.3-111816.6" - process $proc$libresoc.v:111765$4273 + attribute \src "libresoc.v:111561.3-111612.6" + process $proc$libresoc.v:111561$4273 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:111766.5-111766.29" + attribute \src "libresoc.v:111562.5-111562.29" switch \initial - attribute \src "libresoc.v:111766.9-111766.17" + attribute \src "libresoc.v:111562.9-111562.17" case 1'1 case end @@ -173859,14 +173655,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:111817.3-111868.6" - process $proc$libresoc.v:111817$4274 + attribute \src "libresoc.v:111613.3-111664.6" + process $proc$libresoc.v:111613$4274 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:111818.5-111818.29" + attribute \src "libresoc.v:111614.5-111614.29" switch \initial - attribute \src "libresoc.v:111818.9-111818.17" + attribute \src "libresoc.v:111614.9-111614.17" case 1'1 case end @@ -173938,14 +173734,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] end - attribute \src "libresoc.v:111869.3-111920.6" - process $proc$libresoc.v:111869$4275 + attribute \src "libresoc.v:111665.3-111716.6" + process $proc$libresoc.v:111665$4275 assign { } { } assign { } { } assign $0\dec31_dec_sub26_out_sel[2:0] $1\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:111870.5-111870.29" + attribute \src "libresoc.v:111666.5-111666.29" switch \initial - attribute \src "libresoc.v:111870.9-111870.17" + attribute \src "libresoc.v:111666.9-111666.17" case 1'1 case end @@ -174019,144 +173815,144 @@ module \dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:111926.1-112903.10" +attribute \src "libresoc.v:111722.1-112699.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" attribute \generator "nMigen" module \dec31_dec_sub27 - attribute \src "libresoc.v:112788.3-112806.6" + attribute \src "libresoc.v:112584.3-112602.6" wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:112807.3-112825.6" + attribute \src "libresoc.v:112603.3-112621.6" wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:112560.3-112578.6" + attribute \src "libresoc.v:112356.3-112374.6" wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:112636.3-112654.6" + attribute \src "libresoc.v:112432.3-112450.6" wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:112294.3-112312.6" + attribute \src "libresoc.v:112090.3-112108.6" wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:112313.3-112331.6" + attribute \src "libresoc.v:112109.3-112127.6" wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:112541.3-112559.6" + attribute \src "libresoc.v:112337.3-112355.6" wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:112617.3-112635.6" + attribute \src "libresoc.v:112413.3-112431.6" wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:112693.3-112711.6" + attribute \src "libresoc.v:112489.3-112507.6" wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:112275.3-112293.6" + attribute \src "libresoc.v:112071.3-112089.6" wire width 14 $0\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:112826.3-112844.6" + attribute \src "libresoc.v:112622.3-112640.6" wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:112845.3-112863.6" + attribute \src "libresoc.v:112641.3-112659.6" wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:112864.3-112882.6" + attribute \src "libresoc.v:112660.3-112678.6" wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:112484.3-112502.6" + attribute \src "libresoc.v:112280.3-112298.6" wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:112579.3-112597.6" + attribute \src "libresoc.v:112375.3-112393.6" wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:112598.3-112616.6" + attribute \src "libresoc.v:112394.3-112412.6" wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:112712.3-112730.6" + attribute \src "libresoc.v:112508.3-112526.6" wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:112465.3-112483.6" + attribute \src "libresoc.v:112261.3-112279.6" wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:112750.3-112768.6" + attribute \src "libresoc.v:112546.3-112564.6" wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:112883.3-112901.6" + attribute \src "libresoc.v:112679.3-112697.6" wire width 3 $0\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:112522.3-112540.6" + attribute \src "libresoc.v:112318.3-112336.6" wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:112674.3-112692.6" + attribute \src "libresoc.v:112470.3-112488.6" wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:112769.3-112787.6" + attribute \src "libresoc.v:112565.3-112583.6" wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:112731.3-112749.6" + attribute \src "libresoc.v:112527.3-112545.6" wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:112655.3-112673.6" + attribute \src "libresoc.v:112451.3-112469.6" wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:112427.3-112445.6" + attribute \src "libresoc.v:112223.3-112241.6" wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:112446.3-112464.6" + attribute \src "libresoc.v:112242.3-112260.6" wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:112332.3-112350.6" + attribute \src "libresoc.v:112128.3-112146.6" wire width 3 $0\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:112351.3-112369.6" + attribute \src "libresoc.v:112147.3-112165.6" wire width 3 $0\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:112370.3-112388.6" + attribute \src "libresoc.v:112166.3-112184.6" wire width 3 $0\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:112408.3-112426.6" + attribute \src "libresoc.v:112204.3-112222.6" wire width 3 $0\dec31_dec_sub27_sv_out2[2:0] - attribute \src "libresoc.v:112389.3-112407.6" + attribute \src "libresoc.v:112185.3-112203.6" wire width 3 $0\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:112503.3-112521.6" + attribute \src "libresoc.v:112299.3-112317.6" wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:111927.7-111927.20" + attribute \src "libresoc.v:111723.7-111723.20" wire $0\initial[0:0] - attribute \src "libresoc.v:112788.3-112806.6" + attribute \src "libresoc.v:112584.3-112602.6" wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:112807.3-112825.6" + attribute \src "libresoc.v:112603.3-112621.6" wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:112560.3-112578.6" + attribute \src "libresoc.v:112356.3-112374.6" wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:112636.3-112654.6" + attribute \src "libresoc.v:112432.3-112450.6" wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:112294.3-112312.6" + attribute \src "libresoc.v:112090.3-112108.6" wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:112313.3-112331.6" + attribute \src "libresoc.v:112109.3-112127.6" wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:112541.3-112559.6" + attribute \src "libresoc.v:112337.3-112355.6" wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:112617.3-112635.6" + attribute \src "libresoc.v:112413.3-112431.6" wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:112693.3-112711.6" + attribute \src "libresoc.v:112489.3-112507.6" wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:112275.3-112293.6" + attribute \src "libresoc.v:112071.3-112089.6" wire width 14 $1\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:112826.3-112844.6" + attribute \src "libresoc.v:112622.3-112640.6" wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:112845.3-112863.6" + attribute \src "libresoc.v:112641.3-112659.6" wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:112864.3-112882.6" + attribute \src "libresoc.v:112660.3-112678.6" wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:112484.3-112502.6" + attribute \src "libresoc.v:112280.3-112298.6" wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:112579.3-112597.6" + attribute \src "libresoc.v:112375.3-112393.6" wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:112598.3-112616.6" + attribute \src "libresoc.v:112394.3-112412.6" wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:112712.3-112730.6" + attribute \src "libresoc.v:112508.3-112526.6" wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:112465.3-112483.6" + attribute \src "libresoc.v:112261.3-112279.6" wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:112750.3-112768.6" + attribute \src "libresoc.v:112546.3-112564.6" wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:112883.3-112901.6" + attribute \src "libresoc.v:112679.3-112697.6" wire width 3 $1\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:112522.3-112540.6" + attribute \src "libresoc.v:112318.3-112336.6" wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:112674.3-112692.6" + attribute \src "libresoc.v:112470.3-112488.6" wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:112769.3-112787.6" + attribute \src "libresoc.v:112565.3-112583.6" wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:112731.3-112749.6" + attribute \src "libresoc.v:112527.3-112545.6" wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:112655.3-112673.6" + attribute \src "libresoc.v:112451.3-112469.6" wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:112427.3-112445.6" + attribute \src "libresoc.v:112223.3-112241.6" wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:112446.3-112464.6" + attribute \src "libresoc.v:112242.3-112260.6" wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:112332.3-112350.6" + attribute \src "libresoc.v:112128.3-112146.6" wire width 3 $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:112351.3-112369.6" + attribute \src "libresoc.v:112147.3-112165.6" wire width 3 $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:112370.3-112388.6" + attribute \src "libresoc.v:112166.3-112184.6" wire width 3 $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:112408.3-112426.6" + attribute \src "libresoc.v:112204.3-112222.6" wire width 3 $1\dec31_dec_sub27_sv_out2[2:0] - attribute \src "libresoc.v:112389.3-112407.6" + attribute \src "libresoc.v:112185.3-112203.6" wire width 3 $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:112503.3-112521.6" + attribute \src "libresoc.v:112299.3-112317.6" wire width 2 $1\dec31_dec_sub27_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -174468,28 +174264,28 @@ module \dec31_dec_sub27 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub27_upd - attribute \src "libresoc.v:111927.7-111927.15" + attribute \src "libresoc.v:111723.7-111723.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:111927.7-111927.20" - process $proc$libresoc.v:111927$4310 + attribute \src "libresoc.v:111723.7-111723.20" + process $proc$libresoc.v:111723$4310 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:112275.3-112293.6" - process $proc$libresoc.v:112275$4277 + attribute \src "libresoc.v:112071.3-112089.6" + process $proc$libresoc.v:112071$4277 assign { } { } assign { } { } assign $0\dec31_dec_sub27_function_unit[13:0] $1\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:112276.5-112276.29" + attribute \src "libresoc.v:112072.5-112072.29" switch \initial - attribute \src "libresoc.v:112276.9-112276.17" + attribute \src "libresoc.v:112072.9-112072.17" case 1'1 case end @@ -174517,14 +174313,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[13:0] end - attribute \src "libresoc.v:112294.3-112312.6" - process $proc$libresoc.v:112294$4278 + attribute \src "libresoc.v:112090.3-112108.6" + process $proc$libresoc.v:112090$4278 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:112295.5-112295.29" + attribute \src "libresoc.v:112091.5-112091.29" switch \initial - attribute \src "libresoc.v:112295.9-112295.17" + attribute \src "libresoc.v:112091.9-112091.17" case 1'1 case end @@ -174552,14 +174348,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:112313.3-112331.6" - process $proc$libresoc.v:112313$4279 + attribute \src "libresoc.v:112109.3-112127.6" + process $proc$libresoc.v:112109$4279 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:112314.5-112314.29" + attribute \src "libresoc.v:112110.5-112110.29" switch \initial - attribute \src "libresoc.v:112314.9-112314.17" + attribute \src "libresoc.v:112110.9-112110.17" case 1'1 case end @@ -174587,14 +174383,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] end - attribute \src "libresoc.v:112332.3-112350.6" - process $proc$libresoc.v:112332$4280 + attribute \src "libresoc.v:112128.3-112146.6" + process $proc$libresoc.v:112128$4280 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:112333.5-112333.29" + attribute \src "libresoc.v:112129.5-112129.29" switch \initial - attribute \src "libresoc.v:112333.9-112333.17" + attribute \src "libresoc.v:112129.9-112129.17" case 1'1 case end @@ -174622,14 +174418,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0] end - attribute \src "libresoc.v:112351.3-112369.6" - process $proc$libresoc.v:112351$4281 + attribute \src "libresoc.v:112147.3-112165.6" + process $proc$libresoc.v:112147$4281 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:112352.5-112352.29" + attribute \src "libresoc.v:112148.5-112148.29" switch \initial - attribute \src "libresoc.v:112352.9-112352.17" + attribute \src "libresoc.v:112148.9-112148.17" case 1'1 case end @@ -174657,14 +174453,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0] end - attribute \src "libresoc.v:112370.3-112388.6" - process $proc$libresoc.v:112370$4282 + attribute \src "libresoc.v:112166.3-112184.6" + process $proc$libresoc.v:112166$4282 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:112371.5-112371.29" + attribute \src "libresoc.v:112167.5-112167.29" switch \initial - attribute \src "libresoc.v:112371.9-112371.17" + attribute \src "libresoc.v:112167.9-112167.17" case 1'1 case end @@ -174692,14 +174488,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0] end - attribute \src "libresoc.v:112389.3-112407.6" - process $proc$libresoc.v:112389$4283 + attribute \src "libresoc.v:112185.3-112203.6" + process $proc$libresoc.v:112185$4283 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:112390.5-112390.29" + attribute \src "libresoc.v:112186.5-112186.29" switch \initial - attribute \src "libresoc.v:112390.9-112390.17" + attribute \src "libresoc.v:112186.9-112186.17" case 1'1 case end @@ -174727,14 +174523,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0] end - attribute \src "libresoc.v:112408.3-112426.6" - process $proc$libresoc.v:112408$4284 + attribute \src "libresoc.v:112204.3-112222.6" + process $proc$libresoc.v:112204$4284 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out2[2:0] $1\dec31_dec_sub27_sv_out2[2:0] - attribute \src "libresoc.v:112409.5-112409.29" + attribute \src "libresoc.v:112205.5-112205.29" switch \initial - attribute \src "libresoc.v:112409.9-112409.17" + attribute \src "libresoc.v:112205.9-112205.17" case 1'1 case end @@ -174762,14 +174558,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_out2 $0\dec31_dec_sub27_sv_out2[2:0] end - attribute \src "libresoc.v:112427.3-112445.6" - process $proc$libresoc.v:112427$4285 + attribute \src "libresoc.v:112223.3-112241.6" + process $proc$libresoc.v:112223$4285 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:112428.5-112428.29" + attribute \src "libresoc.v:112224.5-112224.29" switch \initial - attribute \src "libresoc.v:112428.9-112428.17" + attribute \src "libresoc.v:112224.9-112224.17" case 1'1 case end @@ -174797,14 +174593,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0] end - attribute \src "libresoc.v:112446.3-112464.6" - process $proc$libresoc.v:112446$4286 + attribute \src "libresoc.v:112242.3-112260.6" + process $proc$libresoc.v:112242$4286 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:112447.5-112447.29" + attribute \src "libresoc.v:112243.5-112243.29" switch \initial - attribute \src "libresoc.v:112447.9-112447.17" + attribute \src "libresoc.v:112243.9-112243.17" case 1'1 case end @@ -174832,14 +174628,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0] end - attribute \src "libresoc.v:112465.3-112483.6" - process $proc$libresoc.v:112465$4287 + attribute \src "libresoc.v:112261.3-112279.6" + process $proc$libresoc.v:112261$4287 assign { } { } assign { } { } assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:112466.5-112466.29" + attribute \src "libresoc.v:112262.5-112262.29" switch \initial - attribute \src "libresoc.v:112466.9-112466.17" + attribute \src "libresoc.v:112262.9-112262.17" case 1'1 case end @@ -174867,14 +174663,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "libresoc.v:112484.3-112502.6" - process $proc$libresoc.v:112484$4288 + attribute \src "libresoc.v:112280.3-112298.6" + process $proc$libresoc.v:112280$4288 assign { } { } assign { } { } assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:112485.5-112485.29" + attribute \src "libresoc.v:112281.5-112281.29" switch \initial - attribute \src "libresoc.v:112485.9-112485.17" + attribute \src "libresoc.v:112281.9-112281.17" case 1'1 case end @@ -174902,14 +174698,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:112503.3-112521.6" - process $proc$libresoc.v:112503$4289 + attribute \src "libresoc.v:112299.3-112317.6" + process $proc$libresoc.v:112299$4289 assign { } { } assign { } { } assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:112504.5-112504.29" + attribute \src "libresoc.v:112300.5-112300.29" switch \initial - attribute \src "libresoc.v:112504.9-112504.17" + attribute \src "libresoc.v:112300.9-112300.17" case 1'1 case end @@ -174937,14 +174733,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end - attribute \src "libresoc.v:112522.3-112540.6" - process $proc$libresoc.v:112522$4290 + attribute \src "libresoc.v:112318.3-112336.6" + process $proc$libresoc.v:112318$4290 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:112523.5-112523.29" + attribute \src "libresoc.v:112319.5-112319.29" switch \initial - attribute \src "libresoc.v:112523.9-112523.17" + attribute \src "libresoc.v:112319.9-112319.17" case 1'1 case end @@ -174972,14 +174768,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:112541.3-112559.6" - process $proc$libresoc.v:112541$4291 + attribute \src "libresoc.v:112337.3-112355.6" + process $proc$libresoc.v:112337$4291 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:112542.5-112542.29" + attribute \src "libresoc.v:112338.5-112338.29" switch \initial - attribute \src "libresoc.v:112542.9-112542.17" + attribute \src "libresoc.v:112338.9-112338.17" case 1'1 case end @@ -175007,14 +174803,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:112560.3-112578.6" - process $proc$libresoc.v:112560$4292 + attribute \src "libresoc.v:112356.3-112374.6" + process $proc$libresoc.v:112356$4292 assign { } { } assign { } { } assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:112561.5-112561.29" + attribute \src "libresoc.v:112357.5-112357.29" switch \initial - attribute \src "libresoc.v:112561.9-112561.17" + attribute \src "libresoc.v:112357.9-112357.17" case 1'1 case end @@ -175042,14 +174838,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end - attribute \src "libresoc.v:112579.3-112597.6" - process $proc$libresoc.v:112579$4293 + attribute \src "libresoc.v:112375.3-112393.6" + process $proc$libresoc.v:112375$4293 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:112580.5-112580.29" + attribute \src "libresoc.v:112376.5-112376.29" switch \initial - attribute \src "libresoc.v:112580.9-112580.17" + attribute \src "libresoc.v:112376.9-112376.17" case 1'1 case end @@ -175077,14 +174873,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:112598.3-112616.6" - process $proc$libresoc.v:112598$4294 + attribute \src "libresoc.v:112394.3-112412.6" + process $proc$libresoc.v:112394$4294 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:112599.5-112599.29" + attribute \src "libresoc.v:112395.5-112395.29" switch \initial - attribute \src "libresoc.v:112599.9-112599.17" + attribute \src "libresoc.v:112395.9-112395.17" case 1'1 case end @@ -175112,14 +174908,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end - attribute \src "libresoc.v:112617.3-112635.6" - process $proc$libresoc.v:112617$4295 + attribute \src "libresoc.v:112413.3-112431.6" + process $proc$libresoc.v:112413$4295 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:112618.5-112618.29" + attribute \src "libresoc.v:112414.5-112414.29" switch \initial - attribute \src "libresoc.v:112618.9-112618.17" + attribute \src "libresoc.v:112414.9-112414.17" case 1'1 case end @@ -175147,14 +174943,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end - attribute \src "libresoc.v:112636.3-112654.6" - process $proc$libresoc.v:112636$4296 + attribute \src "libresoc.v:112432.3-112450.6" + process $proc$libresoc.v:112432$4296 assign { } { } assign { } { } assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:112637.5-112637.29" + attribute \src "libresoc.v:112433.5-112433.29" switch \initial - attribute \src "libresoc.v:112637.9-112637.17" + attribute \src "libresoc.v:112433.9-112433.17" case 1'1 case end @@ -175182,14 +174978,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end - attribute \src "libresoc.v:112655.3-112673.6" - process $proc$libresoc.v:112655$4297 + attribute \src "libresoc.v:112451.3-112469.6" + process $proc$libresoc.v:112451$4297 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:112656.5-112656.29" + attribute \src "libresoc.v:112452.5-112452.29" switch \initial - attribute \src "libresoc.v:112656.9-112656.17" + attribute \src "libresoc.v:112452.9-112452.17" case 1'1 case end @@ -175217,14 +175013,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] end - attribute \src "libresoc.v:112674.3-112692.6" - process $proc$libresoc.v:112674$4298 + attribute \src "libresoc.v:112470.3-112488.6" + process $proc$libresoc.v:112470$4298 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:112675.5-112675.29" + attribute \src "libresoc.v:112471.5-112471.29" switch \initial - attribute \src "libresoc.v:112675.9-112675.17" + attribute \src "libresoc.v:112471.9-112471.17" case 1'1 case end @@ -175252,14 +175048,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "libresoc.v:112693.3-112711.6" - process $proc$libresoc.v:112693$4299 + attribute \src "libresoc.v:112489.3-112507.6" + process $proc$libresoc.v:112489$4299 assign { } { } assign { } { } assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:112694.5-112694.29" + attribute \src "libresoc.v:112490.5-112490.29" switch \initial - attribute \src "libresoc.v:112694.9-112694.17" + attribute \src "libresoc.v:112490.9-112490.17" case 1'1 case end @@ -175287,14 +175083,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end - attribute \src "libresoc.v:112712.3-112730.6" - process $proc$libresoc.v:112712$4300 + attribute \src "libresoc.v:112508.3-112526.6" + process $proc$libresoc.v:112508$4300 assign { } { } assign { } { } assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:112713.5-112713.29" + attribute \src "libresoc.v:112509.5-112509.29" switch \initial - attribute \src "libresoc.v:112713.9-112713.17" + attribute \src "libresoc.v:112509.9-112509.17" case 1'1 case end @@ -175322,14 +175118,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:112731.3-112749.6" - process $proc$libresoc.v:112731$4301 + attribute \src "libresoc.v:112527.3-112545.6" + process $proc$libresoc.v:112527$4301 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:112732.5-112732.29" + attribute \src "libresoc.v:112528.5-112528.29" switch \initial - attribute \src "libresoc.v:112732.9-112732.17" + attribute \src "libresoc.v:112528.9-112528.17" case 1'1 case end @@ -175357,14 +175153,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:112750.3-112768.6" - process $proc$libresoc.v:112750$4302 + attribute \src "libresoc.v:112546.3-112564.6" + process $proc$libresoc.v:112546$4302 assign { } { } assign { } { } assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:112751.5-112751.29" + attribute \src "libresoc.v:112547.5-112547.29" switch \initial - attribute \src "libresoc.v:112751.9-112751.17" + attribute \src "libresoc.v:112547.9-112547.17" case 1'1 case end @@ -175392,14 +175188,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] end - attribute \src "libresoc.v:112769.3-112787.6" - process $proc$libresoc.v:112769$4303 + attribute \src "libresoc.v:112565.3-112583.6" + process $proc$libresoc.v:112565$4303 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:112770.5-112770.29" + attribute \src "libresoc.v:112566.5-112566.29" switch \initial - attribute \src "libresoc.v:112770.9-112770.17" + attribute \src "libresoc.v:112566.9-112566.17" case 1'1 case end @@ -175427,14 +175223,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] end - attribute \src "libresoc.v:112788.3-112806.6" - process $proc$libresoc.v:112788$4304 + attribute \src "libresoc.v:112584.3-112602.6" + process $proc$libresoc.v:112584$4304 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:112789.5-112789.29" + attribute \src "libresoc.v:112585.5-112585.29" switch \initial - attribute \src "libresoc.v:112789.9-112789.17" + attribute \src "libresoc.v:112585.9-112585.17" case 1'1 case end @@ -175462,14 +175258,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0] end - attribute \src "libresoc.v:112807.3-112825.6" - process $proc$libresoc.v:112807$4305 + attribute \src "libresoc.v:112603.3-112621.6" + process $proc$libresoc.v:112603$4305 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:112808.5-112808.29" + attribute \src "libresoc.v:112604.5-112604.29" switch \initial - attribute \src "libresoc.v:112808.9-112808.17" + attribute \src "libresoc.v:112604.9-112604.17" case 1'1 case end @@ -175497,14 +175293,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0] end - attribute \src "libresoc.v:112826.3-112844.6" - process $proc$libresoc.v:112826$4306 + attribute \src "libresoc.v:112622.3-112640.6" + process $proc$libresoc.v:112622$4306 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:112827.5-112827.29" + attribute \src "libresoc.v:112623.5-112623.29" switch \initial - attribute \src "libresoc.v:112827.9-112827.17" + attribute \src "libresoc.v:112623.9-112623.17" case 1'1 case end @@ -175532,14 +175328,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] end - attribute \src "libresoc.v:112845.3-112863.6" - process $proc$libresoc.v:112845$4307 + attribute \src "libresoc.v:112641.3-112659.6" + process $proc$libresoc.v:112641$4307 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:112846.5-112846.29" + attribute \src "libresoc.v:112642.5-112642.29" switch \initial - attribute \src "libresoc.v:112846.9-112846.17" + attribute \src "libresoc.v:112642.9-112642.17" case 1'1 case end @@ -175567,14 +175363,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:112864.3-112882.6" - process $proc$libresoc.v:112864$4308 + attribute \src "libresoc.v:112660.3-112678.6" + process $proc$libresoc.v:112660$4308 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:112865.5-112865.29" + attribute \src "libresoc.v:112661.5-112661.29" switch \initial - attribute \src "libresoc.v:112865.9-112865.17" + attribute \src "libresoc.v:112661.9-112661.17" case 1'1 case end @@ -175602,14 +175398,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] end - attribute \src "libresoc.v:112883.3-112901.6" - process $proc$libresoc.v:112883$4309 + attribute \src "libresoc.v:112679.3-112697.6" + process $proc$libresoc.v:112679$4309 assign { } { } assign { } { } assign $0\dec31_dec_sub27_out_sel[2:0] $1\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:112884.5-112884.29" + attribute \src "libresoc.v:112680.5-112680.29" switch \initial - attribute \src "libresoc.v:112884.9-112884.17" + attribute \src "libresoc.v:112680.9-112680.17" case 1'1 case end @@ -175639,144 +175435,144 @@ module \dec31_dec_sub27 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:112907.1-114478.10" +attribute \src "libresoc.v:112703.1-114274.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" attribute \generator "nMigen" module \dec31_dec_sub28 - attribute \src "libresoc.v:114255.3-114291.6" + attribute \src "libresoc.v:114051.3-114087.6" wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:114292.3-114328.6" + attribute \src "libresoc.v:114088.3-114124.6" wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:113811.3-113847.6" + attribute \src "libresoc.v:113607.3-113643.6" wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:113959.3-113995.6" + attribute \src "libresoc.v:113755.3-113791.6" wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:113293.3-113329.6" + attribute \src "libresoc.v:113089.3-113125.6" wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:113330.3-113366.6" + attribute \src "libresoc.v:113126.3-113162.6" wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:113774.3-113810.6" + attribute \src "libresoc.v:113570.3-113606.6" wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:113922.3-113958.6" + attribute \src "libresoc.v:113718.3-113754.6" wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:114070.3-114106.6" + attribute \src "libresoc.v:113866.3-113902.6" wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:113256.3-113292.6" + attribute \src "libresoc.v:113052.3-113088.6" wire width 14 $0\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:114329.3-114365.6" + attribute \src "libresoc.v:114125.3-114161.6" wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:114366.3-114402.6" + attribute \src "libresoc.v:114162.3-114198.6" wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:114403.3-114439.6" + attribute \src "libresoc.v:114199.3-114235.6" wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:113663.3-113699.6" + attribute \src "libresoc.v:113459.3-113495.6" wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:113848.3-113884.6" + attribute \src "libresoc.v:113644.3-113680.6" wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:113885.3-113921.6" + attribute \src "libresoc.v:113681.3-113717.6" wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:114107.3-114143.6" + attribute \src "libresoc.v:113903.3-113939.6" wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:113626.3-113662.6" + attribute \src "libresoc.v:113422.3-113458.6" wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:114181.3-114217.6" + attribute \src "libresoc.v:113977.3-114013.6" wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:114440.3-114476.6" + attribute \src "libresoc.v:114236.3-114272.6" wire width 3 $0\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:113737.3-113773.6" + attribute \src "libresoc.v:113533.3-113569.6" wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:114033.3-114069.6" + attribute \src "libresoc.v:113829.3-113865.6" wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:114218.3-114254.6" + attribute \src "libresoc.v:114014.3-114050.6" wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:114144.3-114180.6" + attribute \src "libresoc.v:113940.3-113976.6" wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:113996.3-114032.6" + attribute \src "libresoc.v:113792.3-113828.6" wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:113552.3-113588.6" + attribute \src "libresoc.v:113348.3-113384.6" wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:113589.3-113625.6" + attribute \src "libresoc.v:113385.3-113421.6" wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:113367.3-113403.6" + attribute \src "libresoc.v:113163.3-113199.6" wire width 3 $0\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:113404.3-113440.6" + attribute \src "libresoc.v:113200.3-113236.6" wire width 3 $0\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:113441.3-113477.6" + attribute \src "libresoc.v:113237.3-113273.6" wire width 3 $0\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:113515.3-113551.6" + attribute \src "libresoc.v:113311.3-113347.6" wire width 3 $0\dec31_dec_sub28_sv_out2[2:0] - attribute \src "libresoc.v:113478.3-113514.6" + attribute \src "libresoc.v:113274.3-113310.6" wire width 3 $0\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:113700.3-113736.6" + attribute \src "libresoc.v:113496.3-113532.6" wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:112908.7-112908.20" + attribute \src "libresoc.v:112704.7-112704.20" wire $0\initial[0:0] - attribute \src "libresoc.v:114255.3-114291.6" + attribute \src "libresoc.v:114051.3-114087.6" wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:114292.3-114328.6" + attribute \src "libresoc.v:114088.3-114124.6" wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:113811.3-113847.6" + attribute \src "libresoc.v:113607.3-113643.6" wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:113959.3-113995.6" + attribute \src "libresoc.v:113755.3-113791.6" wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:113293.3-113329.6" + attribute \src "libresoc.v:113089.3-113125.6" wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:113330.3-113366.6" + attribute \src "libresoc.v:113126.3-113162.6" wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:113774.3-113810.6" + attribute \src "libresoc.v:113570.3-113606.6" wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:113922.3-113958.6" + attribute \src "libresoc.v:113718.3-113754.6" wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:114070.3-114106.6" + attribute \src "libresoc.v:113866.3-113902.6" wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:113256.3-113292.6" + attribute \src "libresoc.v:113052.3-113088.6" wire width 14 $1\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:114329.3-114365.6" + attribute \src "libresoc.v:114125.3-114161.6" wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:114366.3-114402.6" + attribute \src "libresoc.v:114162.3-114198.6" wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:114403.3-114439.6" + attribute \src "libresoc.v:114199.3-114235.6" wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:113663.3-113699.6" + attribute \src "libresoc.v:113459.3-113495.6" wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:113848.3-113884.6" + attribute \src "libresoc.v:113644.3-113680.6" wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:113885.3-113921.6" + attribute \src "libresoc.v:113681.3-113717.6" wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:114107.3-114143.6" + attribute \src "libresoc.v:113903.3-113939.6" wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:113626.3-113662.6" + attribute \src "libresoc.v:113422.3-113458.6" wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:114181.3-114217.6" + attribute \src "libresoc.v:113977.3-114013.6" wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:114440.3-114476.6" + attribute \src "libresoc.v:114236.3-114272.6" wire width 3 $1\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:113737.3-113773.6" + attribute \src "libresoc.v:113533.3-113569.6" wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:114033.3-114069.6" + attribute \src "libresoc.v:113829.3-113865.6" wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:114218.3-114254.6" + attribute \src "libresoc.v:114014.3-114050.6" wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:114144.3-114180.6" + attribute \src "libresoc.v:113940.3-113976.6" wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:113996.3-114032.6" + attribute \src "libresoc.v:113792.3-113828.6" wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:113552.3-113588.6" + attribute \src "libresoc.v:113348.3-113384.6" wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:113589.3-113625.6" + attribute \src "libresoc.v:113385.3-113421.6" wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:113367.3-113403.6" + attribute \src "libresoc.v:113163.3-113199.6" wire width 3 $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:113404.3-113440.6" + attribute \src "libresoc.v:113200.3-113236.6" wire width 3 $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:113441.3-113477.6" + attribute \src "libresoc.v:113237.3-113273.6" wire width 3 $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:113515.3-113551.6" + attribute \src "libresoc.v:113311.3-113347.6" wire width 3 $1\dec31_dec_sub28_sv_out2[2:0] - attribute \src "libresoc.v:113478.3-113514.6" + attribute \src "libresoc.v:113274.3-113310.6" wire width 3 $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:113700.3-113736.6" + attribute \src "libresoc.v:113496.3-113532.6" wire width 2 $1\dec31_dec_sub28_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -176088,28 +175884,28 @@ module \dec31_dec_sub28 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub28_upd - attribute \src "libresoc.v:112908.7-112908.15" + attribute \src "libresoc.v:112704.7-112704.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:112908.7-112908.20" - process $proc$libresoc.v:112908$4344 + attribute \src "libresoc.v:112704.7-112704.20" + process $proc$libresoc.v:112704$4344 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:113256.3-113292.6" - process $proc$libresoc.v:113256$4311 + attribute \src "libresoc.v:113052.3-113088.6" + process $proc$libresoc.v:113052$4311 assign { } { } assign { } { } assign $0\dec31_dec_sub28_function_unit[13:0] $1\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:113257.5-113257.29" + attribute \src "libresoc.v:113053.5-113053.29" switch \initial - attribute \src "libresoc.v:113257.9-113257.17" + attribute \src "libresoc.v:113053.9-113053.17" case 1'1 case end @@ -176161,14 +175957,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[13:0] end - attribute \src "libresoc.v:113293.3-113329.6" - process $proc$libresoc.v:113293$4312 + attribute \src "libresoc.v:113089.3-113125.6" + process $proc$libresoc.v:113089$4312 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:113294.5-113294.29" + attribute \src "libresoc.v:113090.5-113090.29" switch \initial - attribute \src "libresoc.v:113294.9-113294.17" + attribute \src "libresoc.v:113090.9-113090.17" case 1'1 case end @@ -176220,14 +176016,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:113330.3-113366.6" - process $proc$libresoc.v:113330$4313 + attribute \src "libresoc.v:113126.3-113162.6" + process $proc$libresoc.v:113126$4313 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:113331.5-113331.29" + attribute \src "libresoc.v:113127.5-113127.29" switch \initial - attribute \src "libresoc.v:113331.9-113331.17" + attribute \src "libresoc.v:113127.9-113127.17" case 1'1 case end @@ -176279,14 +176075,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end - attribute \src "libresoc.v:113367.3-113403.6" - process $proc$libresoc.v:113367$4314 + attribute \src "libresoc.v:113163.3-113199.6" + process $proc$libresoc.v:113163$4314 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:113368.5-113368.29" + attribute \src "libresoc.v:113164.5-113164.29" switch \initial - attribute \src "libresoc.v:113368.9-113368.17" + attribute \src "libresoc.v:113164.9-113164.17" case 1'1 case end @@ -176338,14 +176134,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0] end - attribute \src "libresoc.v:113404.3-113440.6" - process $proc$libresoc.v:113404$4315 + attribute \src "libresoc.v:113200.3-113236.6" + process $proc$libresoc.v:113200$4315 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:113405.5-113405.29" + attribute \src "libresoc.v:113201.5-113201.29" switch \initial - attribute \src "libresoc.v:113405.9-113405.17" + attribute \src "libresoc.v:113201.9-113201.17" case 1'1 case end @@ -176397,14 +176193,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0] end - attribute \src "libresoc.v:113441.3-113477.6" - process $proc$libresoc.v:113441$4316 + attribute \src "libresoc.v:113237.3-113273.6" + process $proc$libresoc.v:113237$4316 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:113442.5-113442.29" + attribute \src "libresoc.v:113238.5-113238.29" switch \initial - attribute \src "libresoc.v:113442.9-113442.17" + attribute \src "libresoc.v:113238.9-113238.17" case 1'1 case end @@ -176456,14 +176252,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0] end - attribute \src "libresoc.v:113478.3-113514.6" - process $proc$libresoc.v:113478$4317 + attribute \src "libresoc.v:113274.3-113310.6" + process $proc$libresoc.v:113274$4317 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:113479.5-113479.29" + attribute \src "libresoc.v:113275.5-113275.29" switch \initial - attribute \src "libresoc.v:113479.9-113479.17" + attribute \src "libresoc.v:113275.9-113275.17" case 1'1 case end @@ -176515,14 +176311,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0] end - attribute \src "libresoc.v:113515.3-113551.6" - process $proc$libresoc.v:113515$4318 + attribute \src "libresoc.v:113311.3-113347.6" + process $proc$libresoc.v:113311$4318 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out2[2:0] $1\dec31_dec_sub28_sv_out2[2:0] - attribute \src "libresoc.v:113516.5-113516.29" + attribute \src "libresoc.v:113312.5-113312.29" switch \initial - attribute \src "libresoc.v:113516.9-113516.17" + attribute \src "libresoc.v:113312.9-113312.17" case 1'1 case end @@ -176574,14 +176370,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_out2 $0\dec31_dec_sub28_sv_out2[2:0] end - attribute \src "libresoc.v:113552.3-113588.6" - process $proc$libresoc.v:113552$4319 + attribute \src "libresoc.v:113348.3-113384.6" + process $proc$libresoc.v:113348$4319 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:113553.5-113553.29" + attribute \src "libresoc.v:113349.5-113349.29" switch \initial - attribute \src "libresoc.v:113553.9-113553.17" + attribute \src "libresoc.v:113349.9-113349.17" case 1'1 case end @@ -176633,14 +176429,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0] end - attribute \src "libresoc.v:113589.3-113625.6" - process $proc$libresoc.v:113589$4320 + attribute \src "libresoc.v:113385.3-113421.6" + process $proc$libresoc.v:113385$4320 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:113590.5-113590.29" + attribute \src "libresoc.v:113386.5-113386.29" switch \initial - attribute \src "libresoc.v:113590.9-113590.17" + attribute \src "libresoc.v:113386.9-113386.17" case 1'1 case end @@ -176692,14 +176488,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0] end - attribute \src "libresoc.v:113626.3-113662.6" - process $proc$libresoc.v:113626$4321 + attribute \src "libresoc.v:113422.3-113458.6" + process $proc$libresoc.v:113422$4321 assign { } { } assign { } { } assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:113627.5-113627.29" + attribute \src "libresoc.v:113423.5-113423.29" switch \initial - attribute \src "libresoc.v:113627.9-113627.17" + attribute \src "libresoc.v:113423.9-113423.17" case 1'1 case end @@ -176751,14 +176547,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] end - attribute \src "libresoc.v:113663.3-113699.6" - process $proc$libresoc.v:113663$4322 + attribute \src "libresoc.v:113459.3-113495.6" + process $proc$libresoc.v:113459$4322 assign { } { } assign { } { } assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:113664.5-113664.29" + attribute \src "libresoc.v:113460.5-113460.29" switch \initial - attribute \src "libresoc.v:113664.9-113664.17" + attribute \src "libresoc.v:113460.9-113460.17" case 1'1 case end @@ -176810,14 +176606,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:113700.3-113736.6" - process $proc$libresoc.v:113700$4323 + attribute \src "libresoc.v:113496.3-113532.6" + process $proc$libresoc.v:113496$4323 assign { } { } assign { } { } assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:113701.5-113701.29" + attribute \src "libresoc.v:113497.5-113497.29" switch \initial - attribute \src "libresoc.v:113701.9-113701.17" + attribute \src "libresoc.v:113497.9-113497.17" case 1'1 case end @@ -176869,14 +176665,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end - attribute \src "libresoc.v:113737.3-113773.6" - process $proc$libresoc.v:113737$4324 + attribute \src "libresoc.v:113533.3-113569.6" + process $proc$libresoc.v:113533$4324 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:113738.5-113738.29" + attribute \src "libresoc.v:113534.5-113534.29" switch \initial - attribute \src "libresoc.v:113738.9-113738.17" + attribute \src "libresoc.v:113534.9-113534.17" case 1'1 case end @@ -176928,14 +176724,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:113774.3-113810.6" - process $proc$libresoc.v:113774$4325 + attribute \src "libresoc.v:113570.3-113606.6" + process $proc$libresoc.v:113570$4325 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:113775.5-113775.29" + attribute \src "libresoc.v:113571.5-113571.29" switch \initial - attribute \src "libresoc.v:113775.9-113775.17" + attribute \src "libresoc.v:113571.9-113571.17" case 1'1 case end @@ -176987,14 +176783,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "libresoc.v:113811.3-113847.6" - process $proc$libresoc.v:113811$4326 + attribute \src "libresoc.v:113607.3-113643.6" + process $proc$libresoc.v:113607$4326 assign { } { } assign { } { } assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:113812.5-113812.29" + attribute \src "libresoc.v:113608.5-113608.29" switch \initial - attribute \src "libresoc.v:113812.9-113812.17" + attribute \src "libresoc.v:113608.9-113608.17" case 1'1 case end @@ -177046,14 +176842,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "libresoc.v:113848.3-113884.6" - process $proc$libresoc.v:113848$4327 + attribute \src "libresoc.v:113644.3-113680.6" + process $proc$libresoc.v:113644$4327 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:113849.5-113849.29" + attribute \src "libresoc.v:113645.5-113645.29" switch \initial - attribute \src "libresoc.v:113849.9-113849.17" + attribute \src "libresoc.v:113645.9-113645.17" case 1'1 case end @@ -177105,14 +176901,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:113885.3-113921.6" - process $proc$libresoc.v:113885$4328 + attribute \src "libresoc.v:113681.3-113717.6" + process $proc$libresoc.v:113681$4328 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:113886.5-113886.29" + attribute \src "libresoc.v:113682.5-113682.29" switch \initial - attribute \src "libresoc.v:113886.9-113886.17" + attribute \src "libresoc.v:113682.9-113682.17" case 1'1 case end @@ -177164,14 +176960,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:113922.3-113958.6" - process $proc$libresoc.v:113922$4329 + attribute \src "libresoc.v:113718.3-113754.6" + process $proc$libresoc.v:113718$4329 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:113923.5-113923.29" + attribute \src "libresoc.v:113719.5-113719.29" switch \initial - attribute \src "libresoc.v:113923.9-113923.17" + attribute \src "libresoc.v:113719.9-113719.17" case 1'1 case end @@ -177223,14 +177019,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:113959.3-113995.6" - process $proc$libresoc.v:113959$4330 + attribute \src "libresoc.v:113755.3-113791.6" + process $proc$libresoc.v:113755$4330 assign { } { } assign { } { } assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:113960.5-113960.29" + attribute \src "libresoc.v:113756.5-113756.29" switch \initial - attribute \src "libresoc.v:113960.9-113960.17" + attribute \src "libresoc.v:113756.9-113756.17" case 1'1 case end @@ -177282,14 +177078,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end - attribute \src "libresoc.v:113996.3-114032.6" - process $proc$libresoc.v:113996$4331 + attribute \src "libresoc.v:113792.3-113828.6" + process $proc$libresoc.v:113792$4331 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:113997.5-113997.29" + attribute \src "libresoc.v:113793.5-113793.29" switch \initial - attribute \src "libresoc.v:113997.9-113997.17" + attribute \src "libresoc.v:113793.9-113793.17" case 1'1 case end @@ -177341,14 +177137,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "libresoc.v:114033.3-114069.6" - process $proc$libresoc.v:114033$4332 + attribute \src "libresoc.v:113829.3-113865.6" + process $proc$libresoc.v:113829$4332 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:114034.5-114034.29" + attribute \src "libresoc.v:113830.5-113830.29" switch \initial - attribute \src "libresoc.v:114034.9-114034.17" + attribute \src "libresoc.v:113830.9-113830.17" case 1'1 case end @@ -177400,14 +177196,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end - attribute \src "libresoc.v:114070.3-114106.6" - process $proc$libresoc.v:114070$4333 + attribute \src "libresoc.v:113866.3-113902.6" + process $proc$libresoc.v:113866$4333 assign { } { } assign { } { } assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:114071.5-114071.29" + attribute \src "libresoc.v:113867.5-113867.29" switch \initial - attribute \src "libresoc.v:114071.9-114071.17" + attribute \src "libresoc.v:113867.9-113867.17" case 1'1 case end @@ -177459,14 +177255,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end - attribute \src "libresoc.v:114107.3-114143.6" - process $proc$libresoc.v:114107$4334 + attribute \src "libresoc.v:113903.3-113939.6" + process $proc$libresoc.v:113903$4334 assign { } { } assign { } { } assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:114108.5-114108.29" + attribute \src "libresoc.v:113904.5-113904.29" switch \initial - attribute \src "libresoc.v:114108.9-114108.17" + attribute \src "libresoc.v:113904.9-113904.17" case 1'1 case end @@ -177518,14 +177314,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:114144.3-114180.6" - process $proc$libresoc.v:114144$4335 + attribute \src "libresoc.v:113940.3-113976.6" + process $proc$libresoc.v:113940$4335 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:114145.5-114145.29" + attribute \src "libresoc.v:113941.5-113941.29" switch \initial - attribute \src "libresoc.v:114145.9-114145.17" + attribute \src "libresoc.v:113941.9-113941.17" case 1'1 case end @@ -177577,14 +177373,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:114181.3-114217.6" - process $proc$libresoc.v:114181$4336 + attribute \src "libresoc.v:113977.3-114013.6" + process $proc$libresoc.v:113977$4336 assign { } { } assign { } { } assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:114182.5-114182.29" + attribute \src "libresoc.v:113978.5-113978.29" switch \initial - attribute \src "libresoc.v:114182.9-114182.17" + attribute \src "libresoc.v:113978.9-113978.17" case 1'1 case end @@ -177636,14 +177432,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end - attribute \src "libresoc.v:114218.3-114254.6" - process $proc$libresoc.v:114218$4337 + attribute \src "libresoc.v:114014.3-114050.6" + process $proc$libresoc.v:114014$4337 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:114219.5-114219.29" + attribute \src "libresoc.v:114015.5-114015.29" switch \initial - attribute \src "libresoc.v:114219.9-114219.17" + attribute \src "libresoc.v:114015.9-114015.17" case 1'1 case end @@ -177695,14 +177491,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "libresoc.v:114255.3-114291.6" - process $proc$libresoc.v:114255$4338 + attribute \src "libresoc.v:114051.3-114087.6" + process $proc$libresoc.v:114051$4338 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:114256.5-114256.29" + attribute \src "libresoc.v:114052.5-114052.29" switch \initial - attribute \src "libresoc.v:114256.9-114256.17" + attribute \src "libresoc.v:114052.9-114052.17" case 1'1 case end @@ -177754,14 +177550,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0] end - attribute \src "libresoc.v:114292.3-114328.6" - process $proc$libresoc.v:114292$4339 + attribute \src "libresoc.v:114088.3-114124.6" + process $proc$libresoc.v:114088$4339 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:114293.5-114293.29" + attribute \src "libresoc.v:114089.5-114089.29" switch \initial - attribute \src "libresoc.v:114293.9-114293.17" + attribute \src "libresoc.v:114089.9-114089.17" case 1'1 case end @@ -177813,14 +177609,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0] end - attribute \src "libresoc.v:114329.3-114365.6" - process $proc$libresoc.v:114329$4340 + attribute \src "libresoc.v:114125.3-114161.6" + process $proc$libresoc.v:114125$4340 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:114330.5-114330.29" + attribute \src "libresoc.v:114126.5-114126.29" switch \initial - attribute \src "libresoc.v:114330.9-114330.17" + attribute \src "libresoc.v:114126.9-114126.17" case 1'1 case end @@ -177872,14 +177668,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:114366.3-114402.6" - process $proc$libresoc.v:114366$4341 + attribute \src "libresoc.v:114162.3-114198.6" + process $proc$libresoc.v:114162$4341 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:114367.5-114367.29" + attribute \src "libresoc.v:114163.5-114163.29" switch \initial - attribute \src "libresoc.v:114367.9-114367.17" + attribute \src "libresoc.v:114163.9-114163.17" case 1'1 case end @@ -177931,14 +177727,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:114403.3-114439.6" - process $proc$libresoc.v:114403$4342 + attribute \src "libresoc.v:114199.3-114235.6" + process $proc$libresoc.v:114199$4342 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:114404.5-114404.29" + attribute \src "libresoc.v:114200.5-114200.29" switch \initial - attribute \src "libresoc.v:114404.9-114404.17" + attribute \src "libresoc.v:114200.9-114200.17" case 1'1 case end @@ -177990,14 +177786,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end - attribute \src "libresoc.v:114440.3-114476.6" - process $proc$libresoc.v:114440$4343 + attribute \src "libresoc.v:114236.3-114272.6" + process $proc$libresoc.v:114236$4343 assign { } { } assign { } { } assign $0\dec31_dec_sub28_out_sel[2:0] $1\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:114441.5-114441.29" + attribute \src "libresoc.v:114237.5-114237.29" switch \initial - attribute \src "libresoc.v:114441.9-114441.17" + attribute \src "libresoc.v:114237.9-114237.17" case 1'1 case end @@ -178051,144 +177847,144 @@ module \dec31_dec_sub28 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:114482.1-115261.10" +attribute \src "libresoc.v:114278.1-115057.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" module \dec31_dec_sub4 - attribute \src "libresoc.v:115182.3-115194.6" + attribute \src "libresoc.v:114978.3-114990.6" wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:115195.3-115207.6" + attribute \src "libresoc.v:114991.3-115003.6" wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:115026.3-115038.6" + attribute \src "libresoc.v:114822.3-114834.6" wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:115078.3-115090.6" + attribute \src "libresoc.v:114874.3-114886.6" wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:114844.3-114856.6" + attribute \src "libresoc.v:114640.3-114652.6" wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:114857.3-114869.6" + attribute \src "libresoc.v:114653.3-114665.6" wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:115013.3-115025.6" + attribute \src "libresoc.v:114809.3-114821.6" wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:115065.3-115077.6" + attribute \src "libresoc.v:114861.3-114873.6" wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:115117.3-115129.6" + attribute \src "libresoc.v:114913.3-114925.6" wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:114831.3-114843.6" + attribute \src "libresoc.v:114627.3-114639.6" wire width 14 $0\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:115208.3-115220.6" + attribute \src "libresoc.v:115004.3-115016.6" wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:115221.3-115233.6" + attribute \src "libresoc.v:115017.3-115029.6" wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:115234.3-115246.6" + attribute \src "libresoc.v:115030.3-115042.6" wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:114974.3-114986.6" + attribute \src "libresoc.v:114770.3-114782.6" wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:115039.3-115051.6" + attribute \src "libresoc.v:114835.3-114847.6" wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:115052.3-115064.6" + attribute \src "libresoc.v:114848.3-114860.6" wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:115130.3-115142.6" + attribute \src "libresoc.v:114926.3-114938.6" wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:114961.3-114973.6" + attribute \src "libresoc.v:114757.3-114769.6" wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:115156.3-115168.6" + attribute \src "libresoc.v:114952.3-114964.6" wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:115247.3-115259.6" + attribute \src "libresoc.v:115043.3-115055.6" wire width 3 $0\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:115000.3-115012.6" + attribute \src "libresoc.v:114796.3-114808.6" wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:115104.3-115116.6" + attribute \src "libresoc.v:114900.3-114912.6" wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:115169.3-115181.6" + attribute \src "libresoc.v:114965.3-114977.6" wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:115143.3-115155.6" + attribute \src "libresoc.v:114939.3-114951.6" wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:115091.3-115103.6" + attribute \src "libresoc.v:114887.3-114899.6" wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:114935.3-114947.6" + attribute \src "libresoc.v:114731.3-114743.6" wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:114948.3-114960.6" + attribute \src "libresoc.v:114744.3-114756.6" wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:114870.3-114882.6" + attribute \src "libresoc.v:114666.3-114678.6" wire width 3 $0\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:114883.3-114895.6" + attribute \src "libresoc.v:114679.3-114691.6" wire width 3 $0\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:114896.3-114908.6" + attribute \src "libresoc.v:114692.3-114704.6" wire width 3 $0\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:114922.3-114934.6" + attribute \src "libresoc.v:114718.3-114730.6" wire width 3 $0\dec31_dec_sub4_sv_out2[2:0] - attribute \src "libresoc.v:114909.3-114921.6" + attribute \src "libresoc.v:114705.3-114717.6" wire width 3 $0\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:114987.3-114999.6" + attribute \src "libresoc.v:114783.3-114795.6" wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:114483.7-114483.20" + attribute \src "libresoc.v:114279.7-114279.20" wire $0\initial[0:0] - attribute \src "libresoc.v:115182.3-115194.6" + attribute \src "libresoc.v:114978.3-114990.6" wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:115195.3-115207.6" + attribute \src "libresoc.v:114991.3-115003.6" wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:115026.3-115038.6" + attribute \src "libresoc.v:114822.3-114834.6" wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:115078.3-115090.6" + attribute \src "libresoc.v:114874.3-114886.6" wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:114844.3-114856.6" + attribute \src "libresoc.v:114640.3-114652.6" wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:114857.3-114869.6" + attribute \src "libresoc.v:114653.3-114665.6" wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:115013.3-115025.6" + attribute \src "libresoc.v:114809.3-114821.6" wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:115065.3-115077.6" + attribute \src "libresoc.v:114861.3-114873.6" wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:115117.3-115129.6" + attribute \src "libresoc.v:114913.3-114925.6" wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:114831.3-114843.6" + attribute \src "libresoc.v:114627.3-114639.6" wire width 14 $1\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:115208.3-115220.6" + attribute \src "libresoc.v:115004.3-115016.6" wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:115221.3-115233.6" + attribute \src "libresoc.v:115017.3-115029.6" wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:115234.3-115246.6" + attribute \src "libresoc.v:115030.3-115042.6" wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:114974.3-114986.6" + attribute \src "libresoc.v:114770.3-114782.6" wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:115039.3-115051.6" + attribute \src "libresoc.v:114835.3-114847.6" wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:115052.3-115064.6" + attribute \src "libresoc.v:114848.3-114860.6" wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:115130.3-115142.6" + attribute \src "libresoc.v:114926.3-114938.6" wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:114961.3-114973.6" + attribute \src "libresoc.v:114757.3-114769.6" wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:115156.3-115168.6" + attribute \src "libresoc.v:114952.3-114964.6" wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:115247.3-115259.6" + attribute \src "libresoc.v:115043.3-115055.6" wire width 3 $1\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:115000.3-115012.6" + attribute \src "libresoc.v:114796.3-114808.6" wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:115104.3-115116.6" + attribute \src "libresoc.v:114900.3-114912.6" wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:115169.3-115181.6" + attribute \src "libresoc.v:114965.3-114977.6" wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:115143.3-115155.6" + attribute \src "libresoc.v:114939.3-114951.6" wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:115091.3-115103.6" + attribute \src "libresoc.v:114887.3-114899.6" wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:114935.3-114947.6" + attribute \src "libresoc.v:114731.3-114743.6" wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:114948.3-114960.6" + attribute \src "libresoc.v:114744.3-114756.6" wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:114870.3-114882.6" + attribute \src "libresoc.v:114666.3-114678.6" wire width 3 $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:114883.3-114895.6" + attribute \src "libresoc.v:114679.3-114691.6" wire width 3 $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:114896.3-114908.6" + attribute \src "libresoc.v:114692.3-114704.6" wire width 3 $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:114922.3-114934.6" + attribute \src "libresoc.v:114718.3-114730.6" wire width 3 $1\dec31_dec_sub4_sv_out2[2:0] - attribute \src "libresoc.v:114909.3-114921.6" + attribute \src "libresoc.v:114705.3-114717.6" wire width 3 $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:114987.3-114999.6" + attribute \src "libresoc.v:114783.3-114795.6" wire width 2 $1\dec31_dec_sub4_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -178500,28 +178296,28 @@ module \dec31_dec_sub4 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub4_upd - attribute \src "libresoc.v:114483.7-114483.15" + attribute \src "libresoc.v:114279.7-114279.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:114483.7-114483.20" - process $proc$libresoc.v:114483$4378 + attribute \src "libresoc.v:114279.7-114279.20" + process $proc$libresoc.v:114279$4378 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114831.3-114843.6" - process $proc$libresoc.v:114831$4345 + attribute \src "libresoc.v:114627.3-114639.6" + process $proc$libresoc.v:114627$4345 assign { } { } assign { } { } assign $0\dec31_dec_sub4_function_unit[13:0] $1\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:114832.5-114832.29" + attribute \src "libresoc.v:114628.5-114628.29" switch \initial - attribute \src "libresoc.v:114832.9-114832.17" + attribute \src "libresoc.v:114628.9-114628.17" case 1'1 case end @@ -178541,14 +178337,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[13:0] end - attribute \src "libresoc.v:114844.3-114856.6" - process $proc$libresoc.v:114844$4346 + attribute \src "libresoc.v:114640.3-114652.6" + process $proc$libresoc.v:114640$4346 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:114845.5-114845.29" + attribute \src "libresoc.v:114641.5-114641.29" switch \initial - attribute \src "libresoc.v:114845.9-114845.17" + attribute \src "libresoc.v:114641.9-114641.17" case 1'1 case end @@ -178568,14 +178364,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end - attribute \src "libresoc.v:114857.3-114869.6" - process $proc$libresoc.v:114857$4347 + attribute \src "libresoc.v:114653.3-114665.6" + process $proc$libresoc.v:114653$4347 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:114858.5-114858.29" + attribute \src "libresoc.v:114654.5-114654.29" switch \initial - attribute \src "libresoc.v:114858.9-114858.17" + attribute \src "libresoc.v:114654.9-114654.17" case 1'1 case end @@ -178595,14 +178391,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] end - attribute \src "libresoc.v:114870.3-114882.6" - process $proc$libresoc.v:114870$4348 + attribute \src "libresoc.v:114666.3-114678.6" + process $proc$libresoc.v:114666$4348 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:114871.5-114871.29" + attribute \src "libresoc.v:114667.5-114667.29" switch \initial - attribute \src "libresoc.v:114871.9-114871.17" + attribute \src "libresoc.v:114667.9-114667.17" case 1'1 case end @@ -178622,14 +178418,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0] end - attribute \src "libresoc.v:114883.3-114895.6" - process $proc$libresoc.v:114883$4349 + attribute \src "libresoc.v:114679.3-114691.6" + process $proc$libresoc.v:114679$4349 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:114884.5-114884.29" + attribute \src "libresoc.v:114680.5-114680.29" switch \initial - attribute \src "libresoc.v:114884.9-114884.17" + attribute \src "libresoc.v:114680.9-114680.17" case 1'1 case end @@ -178649,14 +178445,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0] end - attribute \src "libresoc.v:114896.3-114908.6" - process $proc$libresoc.v:114896$4350 + attribute \src "libresoc.v:114692.3-114704.6" + process $proc$libresoc.v:114692$4350 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:114897.5-114897.29" + attribute \src "libresoc.v:114693.5-114693.29" switch \initial - attribute \src "libresoc.v:114897.9-114897.17" + attribute \src "libresoc.v:114693.9-114693.17" case 1'1 case end @@ -178676,14 +178472,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0] end - attribute \src "libresoc.v:114909.3-114921.6" - process $proc$libresoc.v:114909$4351 + attribute \src "libresoc.v:114705.3-114717.6" + process $proc$libresoc.v:114705$4351 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:114910.5-114910.29" + attribute \src "libresoc.v:114706.5-114706.29" switch \initial - attribute \src "libresoc.v:114910.9-114910.17" + attribute \src "libresoc.v:114706.9-114706.17" case 1'1 case end @@ -178703,14 +178499,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0] end - attribute \src "libresoc.v:114922.3-114934.6" - process $proc$libresoc.v:114922$4352 + attribute \src "libresoc.v:114718.3-114730.6" + process $proc$libresoc.v:114718$4352 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out2[2:0] $1\dec31_dec_sub4_sv_out2[2:0] - attribute \src "libresoc.v:114923.5-114923.29" + attribute \src "libresoc.v:114719.5-114719.29" switch \initial - attribute \src "libresoc.v:114923.9-114923.17" + attribute \src "libresoc.v:114719.9-114719.17" case 1'1 case end @@ -178730,14 +178526,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_out2 $0\dec31_dec_sub4_sv_out2[2:0] end - attribute \src "libresoc.v:114935.3-114947.6" - process $proc$libresoc.v:114935$4353 + attribute \src "libresoc.v:114731.3-114743.6" + process $proc$libresoc.v:114731$4353 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:114936.5-114936.29" + attribute \src "libresoc.v:114732.5-114732.29" switch \initial - attribute \src "libresoc.v:114936.9-114936.17" + attribute \src "libresoc.v:114732.9-114732.17" case 1'1 case end @@ -178757,14 +178553,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0] end - attribute \src "libresoc.v:114948.3-114960.6" - process $proc$libresoc.v:114948$4354 + attribute \src "libresoc.v:114744.3-114756.6" + process $proc$libresoc.v:114744$4354 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:114949.5-114949.29" + attribute \src "libresoc.v:114745.5-114745.29" switch \initial - attribute \src "libresoc.v:114949.9-114949.17" + attribute \src "libresoc.v:114745.9-114745.17" case 1'1 case end @@ -178784,14 +178580,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0] end - attribute \src "libresoc.v:114961.3-114973.6" - process $proc$libresoc.v:114961$4355 + attribute \src "libresoc.v:114757.3-114769.6" + process $proc$libresoc.v:114757$4355 assign { } { } assign { } { } assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:114962.5-114962.29" + attribute \src "libresoc.v:114758.5-114758.29" switch \initial - attribute \src "libresoc.v:114962.9-114962.17" + attribute \src "libresoc.v:114758.9-114758.17" case 1'1 case end @@ -178811,14 +178607,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end - attribute \src "libresoc.v:114974.3-114986.6" - process $proc$libresoc.v:114974$4356 + attribute \src "libresoc.v:114770.3-114782.6" + process $proc$libresoc.v:114770$4356 assign { } { } assign { } { } assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:114975.5-114975.29" + attribute \src "libresoc.v:114771.5-114771.29" switch \initial - attribute \src "libresoc.v:114975.9-114975.17" + attribute \src "libresoc.v:114771.9-114771.17" case 1'1 case end @@ -178838,14 +178634,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] end - attribute \src "libresoc.v:114987.3-114999.6" - process $proc$libresoc.v:114987$4357 + attribute \src "libresoc.v:114783.3-114795.6" + process $proc$libresoc.v:114783$4357 assign { } { } assign { } { } assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:114988.5-114988.29" + attribute \src "libresoc.v:114784.5-114784.29" switch \initial - attribute \src "libresoc.v:114988.9-114988.17" + attribute \src "libresoc.v:114784.9-114784.17" case 1'1 case end @@ -178865,14 +178661,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] end - attribute \src "libresoc.v:115000.3-115012.6" - process $proc$libresoc.v:115000$4358 + attribute \src "libresoc.v:114796.3-114808.6" + process $proc$libresoc.v:114796$4358 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:115001.5-115001.29" + attribute \src "libresoc.v:114797.5-114797.29" switch \initial - attribute \src "libresoc.v:115001.9-115001.17" + attribute \src "libresoc.v:114797.9-114797.17" case 1'1 case end @@ -178892,14 +178688,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] end - attribute \src "libresoc.v:115013.3-115025.6" - process $proc$libresoc.v:115013$4359 + attribute \src "libresoc.v:114809.3-114821.6" + process $proc$libresoc.v:114809$4359 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:115014.5-115014.29" + attribute \src "libresoc.v:114810.5-114810.29" switch \initial - attribute \src "libresoc.v:115014.9-115014.17" + attribute \src "libresoc.v:114810.9-114810.17" case 1'1 case end @@ -178919,14 +178715,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end - attribute \src "libresoc.v:115026.3-115038.6" - process $proc$libresoc.v:115026$4360 + attribute \src "libresoc.v:114822.3-114834.6" + process $proc$libresoc.v:114822$4360 assign { } { } assign { } { } assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:115027.5-115027.29" + attribute \src "libresoc.v:114823.5-114823.29" switch \initial - attribute \src "libresoc.v:115027.9-115027.17" + attribute \src "libresoc.v:114823.9-114823.17" case 1'1 case end @@ -178946,14 +178742,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] end - attribute \src "libresoc.v:115039.3-115051.6" - process $proc$libresoc.v:115039$4361 + attribute \src "libresoc.v:114835.3-114847.6" + process $proc$libresoc.v:114835$4361 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:115040.5-115040.29" + attribute \src "libresoc.v:114836.5-114836.29" switch \initial - attribute \src "libresoc.v:115040.9-115040.17" + attribute \src "libresoc.v:114836.9-114836.17" case 1'1 case end @@ -178973,14 +178769,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] end - attribute \src "libresoc.v:115052.3-115064.6" - process $proc$libresoc.v:115052$4362 + attribute \src "libresoc.v:114848.3-114860.6" + process $proc$libresoc.v:114848$4362 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:115053.5-115053.29" + attribute \src "libresoc.v:114849.5-114849.29" switch \initial - attribute \src "libresoc.v:115053.9-115053.17" + attribute \src "libresoc.v:114849.9-114849.17" case 1'1 case end @@ -179000,14 +178796,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] end - attribute \src "libresoc.v:115065.3-115077.6" - process $proc$libresoc.v:115065$4363 + attribute \src "libresoc.v:114861.3-114873.6" + process $proc$libresoc.v:114861$4363 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:115066.5-115066.29" + attribute \src "libresoc.v:114862.5-114862.29" switch \initial - attribute \src "libresoc.v:115066.9-115066.17" + attribute \src "libresoc.v:114862.9-114862.17" case 1'1 case end @@ -179027,14 +178823,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] end - attribute \src "libresoc.v:115078.3-115090.6" - process $proc$libresoc.v:115078$4364 + attribute \src "libresoc.v:114874.3-114886.6" + process $proc$libresoc.v:114874$4364 assign { } { } assign { } { } assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:115079.5-115079.29" + attribute \src "libresoc.v:114875.5-114875.29" switch \initial - attribute \src "libresoc.v:115079.9-115079.17" + attribute \src "libresoc.v:114875.9-114875.17" case 1'1 case end @@ -179054,14 +178850,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] end - attribute \src "libresoc.v:115091.3-115103.6" - process $proc$libresoc.v:115091$4365 + attribute \src "libresoc.v:114887.3-114899.6" + process $proc$libresoc.v:114887$4365 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:115092.5-115092.29" + attribute \src "libresoc.v:114888.5-114888.29" switch \initial - attribute \src "libresoc.v:115092.9-115092.17" + attribute \src "libresoc.v:114888.9-114888.17" case 1'1 case end @@ -179081,14 +178877,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] end - attribute \src "libresoc.v:115104.3-115116.6" - process $proc$libresoc.v:115104$4366 + attribute \src "libresoc.v:114900.3-114912.6" + process $proc$libresoc.v:114900$4366 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:115105.5-115105.29" + attribute \src "libresoc.v:114901.5-114901.29" switch \initial - attribute \src "libresoc.v:115105.9-115105.17" + attribute \src "libresoc.v:114901.9-114901.17" case 1'1 case end @@ -179108,14 +178904,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] end - attribute \src "libresoc.v:115117.3-115129.6" - process $proc$libresoc.v:115117$4367 + attribute \src "libresoc.v:114913.3-114925.6" + process $proc$libresoc.v:114913$4367 assign { } { } assign { } { } assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:115118.5-115118.29" + attribute \src "libresoc.v:114914.5-114914.29" switch \initial - attribute \src "libresoc.v:115118.9-115118.17" + attribute \src "libresoc.v:114914.9-114914.17" case 1'1 case end @@ -179135,14 +178931,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] end - attribute \src "libresoc.v:115130.3-115142.6" - process $proc$libresoc.v:115130$4368 + attribute \src "libresoc.v:114926.3-114938.6" + process $proc$libresoc.v:114926$4368 assign { } { } assign { } { } assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:115131.5-115131.29" + attribute \src "libresoc.v:114927.5-114927.29" switch \initial - attribute \src "libresoc.v:115131.9-115131.17" + attribute \src "libresoc.v:114927.9-114927.17" case 1'1 case end @@ -179162,14 +178958,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end - attribute \src "libresoc.v:115143.3-115155.6" - process $proc$libresoc.v:115143$4369 + attribute \src "libresoc.v:114939.3-114951.6" + process $proc$libresoc.v:114939$4369 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:115144.5-115144.29" + attribute \src "libresoc.v:114940.5-114940.29" switch \initial - attribute \src "libresoc.v:115144.9-115144.17" + attribute \src "libresoc.v:114940.9-114940.17" case 1'1 case end @@ -179189,14 +178985,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] end - attribute \src "libresoc.v:115156.3-115168.6" - process $proc$libresoc.v:115156$4370 + attribute \src "libresoc.v:114952.3-114964.6" + process $proc$libresoc.v:114952$4370 assign { } { } assign { } { } assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:115157.5-115157.29" + attribute \src "libresoc.v:114953.5-114953.29" switch \initial - attribute \src "libresoc.v:115157.9-115157.17" + attribute \src "libresoc.v:114953.9-114953.17" case 1'1 case end @@ -179216,14 +179012,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] end - attribute \src "libresoc.v:115169.3-115181.6" - process $proc$libresoc.v:115169$4371 + attribute \src "libresoc.v:114965.3-114977.6" + process $proc$libresoc.v:114965$4371 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:115170.5-115170.29" + attribute \src "libresoc.v:114966.5-114966.29" switch \initial - attribute \src "libresoc.v:115170.9-115170.17" + attribute \src "libresoc.v:114966.9-114966.17" case 1'1 case end @@ -179243,14 +179039,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] end - attribute \src "libresoc.v:115182.3-115194.6" - process $proc$libresoc.v:115182$4372 + attribute \src "libresoc.v:114978.3-114990.6" + process $proc$libresoc.v:114978$4372 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:115183.5-115183.29" + attribute \src "libresoc.v:114979.5-114979.29" switch \initial - attribute \src "libresoc.v:115183.9-115183.17" + attribute \src "libresoc.v:114979.9-114979.17" case 1'1 case end @@ -179270,14 +179066,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0] end - attribute \src "libresoc.v:115195.3-115207.6" - process $proc$libresoc.v:115195$4373 + attribute \src "libresoc.v:114991.3-115003.6" + process $proc$libresoc.v:114991$4373 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:115196.5-115196.29" + attribute \src "libresoc.v:114992.5-114992.29" switch \initial - attribute \src "libresoc.v:115196.9-115196.17" + attribute \src "libresoc.v:114992.9-114992.17" case 1'1 case end @@ -179297,14 +179093,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0] end - attribute \src "libresoc.v:115208.3-115220.6" - process $proc$libresoc.v:115208$4374 + attribute \src "libresoc.v:115004.3-115016.6" + process $proc$libresoc.v:115004$4374 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:115209.5-115209.29" + attribute \src "libresoc.v:115005.5-115005.29" switch \initial - attribute \src "libresoc.v:115209.9-115209.17" + attribute \src "libresoc.v:115005.9-115005.17" case 1'1 case end @@ -179324,14 +179120,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] end - attribute \src "libresoc.v:115221.3-115233.6" - process $proc$libresoc.v:115221$4375 + attribute \src "libresoc.v:115017.3-115029.6" + process $proc$libresoc.v:115017$4375 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:115222.5-115222.29" + attribute \src "libresoc.v:115018.5-115018.29" switch \initial - attribute \src "libresoc.v:115222.9-115222.17" + attribute \src "libresoc.v:115018.9-115018.17" case 1'1 case end @@ -179351,14 +179147,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end - attribute \src "libresoc.v:115234.3-115246.6" - process $proc$libresoc.v:115234$4376 + attribute \src "libresoc.v:115030.3-115042.6" + process $proc$libresoc.v:115030$4376 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:115235.5-115235.29" + attribute \src "libresoc.v:115031.5-115031.29" switch \initial - attribute \src "libresoc.v:115235.9-115235.17" + attribute \src "libresoc.v:115031.9-115031.17" case 1'1 case end @@ -179378,14 +179174,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] end - attribute \src "libresoc.v:115247.3-115259.6" - process $proc$libresoc.v:115247$4377 + attribute \src "libresoc.v:115043.3-115055.6" + process $proc$libresoc.v:115043$4377 assign { } { } assign { } { } assign $0\dec31_dec_sub4_out_sel[2:0] $1\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:115248.5-115248.29" + attribute \src "libresoc.v:115044.5-115044.29" switch \initial - attribute \src "libresoc.v:115248.9-115248.17" + attribute \src "libresoc.v:115044.9-115044.17" case 1'1 case end @@ -179407,144 +179203,144 @@ module \dec31_dec_sub4 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:115265.1-117034.10" +attribute \src "libresoc.v:115061.1-116830.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" attribute \generator "nMigen" module \dec31_dec_sub8 - attribute \src "libresoc.v:116775.3-116817.6" + attribute \src "libresoc.v:116571.3-116613.6" wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:116818.3-116860.6" + attribute \src "libresoc.v:116614.3-116656.6" wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:116259.3-116301.6" + attribute \src "libresoc.v:116055.3-116097.6" wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:116431.3-116473.6" + attribute \src "libresoc.v:116227.3-116269.6" wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:115657.3-115699.6" + attribute \src "libresoc.v:115453.3-115495.6" wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:115700.3-115742.6" + attribute \src "libresoc.v:115496.3-115538.6" wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:116216.3-116258.6" + attribute \src "libresoc.v:116012.3-116054.6" wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:116388.3-116430.6" + attribute \src "libresoc.v:116184.3-116226.6" wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:116560.3-116602.6" + attribute \src "libresoc.v:116356.3-116398.6" wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:115614.3-115656.6" + attribute \src "libresoc.v:115410.3-115452.6" wire width 14 $0\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:116861.3-116903.6" + attribute \src "libresoc.v:116657.3-116699.6" wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:116904.3-116946.6" + attribute \src "libresoc.v:116700.3-116742.6" wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:116947.3-116989.6" + attribute \src "libresoc.v:116743.3-116785.6" wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:116087.3-116129.6" + attribute \src "libresoc.v:115883.3-115925.6" wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:116302.3-116344.6" + attribute \src "libresoc.v:116098.3-116140.6" wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:116345.3-116387.6" + attribute \src "libresoc.v:116141.3-116183.6" wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:116603.3-116645.6" + attribute \src "libresoc.v:116399.3-116441.6" wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:116044.3-116086.6" + attribute \src "libresoc.v:115840.3-115882.6" wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:116689.3-116731.6" + attribute \src "libresoc.v:116485.3-116527.6" wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:116990.3-117032.6" + attribute \src "libresoc.v:116786.3-116828.6" wire width 3 $0\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:116173.3-116215.6" + attribute \src "libresoc.v:115969.3-116011.6" wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:116517.3-116559.6" + attribute \src "libresoc.v:116313.3-116355.6" wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:116732.3-116774.6" + attribute \src "libresoc.v:116528.3-116570.6" wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:116646.3-116688.6" + attribute \src "libresoc.v:116442.3-116484.6" wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:116474.3-116516.6" + attribute \src "libresoc.v:116270.3-116312.6" wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:115958.3-116000.6" + attribute \src "libresoc.v:115754.3-115796.6" wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:116001.3-116043.6" + attribute \src "libresoc.v:115797.3-115839.6" wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:115743.3-115785.6" + attribute \src "libresoc.v:115539.3-115581.6" wire width 3 $0\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:115786.3-115828.6" + attribute \src "libresoc.v:115582.3-115624.6" wire width 3 $0\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:115829.3-115871.6" + attribute \src "libresoc.v:115625.3-115667.6" wire width 3 $0\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:115915.3-115957.6" + attribute \src "libresoc.v:115711.3-115753.6" wire width 3 $0\dec31_dec_sub8_sv_out2[2:0] - attribute \src "libresoc.v:115872.3-115914.6" + attribute \src "libresoc.v:115668.3-115710.6" wire width 3 $0\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:116130.3-116172.6" + attribute \src "libresoc.v:115926.3-115968.6" wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:115266.7-115266.20" + attribute \src "libresoc.v:115062.7-115062.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116775.3-116817.6" + attribute \src "libresoc.v:116571.3-116613.6" wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:116818.3-116860.6" + attribute \src "libresoc.v:116614.3-116656.6" wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:116259.3-116301.6" + attribute \src "libresoc.v:116055.3-116097.6" wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:116431.3-116473.6" + attribute \src "libresoc.v:116227.3-116269.6" wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:115657.3-115699.6" + attribute \src "libresoc.v:115453.3-115495.6" wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:115700.3-115742.6" + attribute \src "libresoc.v:115496.3-115538.6" wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:116216.3-116258.6" + attribute \src "libresoc.v:116012.3-116054.6" wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:116388.3-116430.6" + attribute \src "libresoc.v:116184.3-116226.6" wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:116560.3-116602.6" + attribute \src "libresoc.v:116356.3-116398.6" wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:115614.3-115656.6" + attribute \src "libresoc.v:115410.3-115452.6" wire width 14 $1\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:116861.3-116903.6" + attribute \src "libresoc.v:116657.3-116699.6" wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:116904.3-116946.6" + attribute \src "libresoc.v:116700.3-116742.6" wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:116947.3-116989.6" + attribute \src "libresoc.v:116743.3-116785.6" wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:116087.3-116129.6" + attribute \src "libresoc.v:115883.3-115925.6" wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:116302.3-116344.6" + attribute \src "libresoc.v:116098.3-116140.6" wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:116345.3-116387.6" + attribute \src "libresoc.v:116141.3-116183.6" wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:116603.3-116645.6" + attribute \src "libresoc.v:116399.3-116441.6" wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:116044.3-116086.6" + attribute \src "libresoc.v:115840.3-115882.6" wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:116689.3-116731.6" + attribute \src "libresoc.v:116485.3-116527.6" wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:116990.3-117032.6" + attribute \src "libresoc.v:116786.3-116828.6" wire width 3 $1\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:116173.3-116215.6" + attribute \src "libresoc.v:115969.3-116011.6" wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:116517.3-116559.6" + attribute \src "libresoc.v:116313.3-116355.6" wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:116732.3-116774.6" + attribute \src "libresoc.v:116528.3-116570.6" wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:116646.3-116688.6" + attribute \src "libresoc.v:116442.3-116484.6" wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:116474.3-116516.6" + attribute \src "libresoc.v:116270.3-116312.6" wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:115958.3-116000.6" + attribute \src "libresoc.v:115754.3-115796.6" wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:116001.3-116043.6" + attribute \src "libresoc.v:115797.3-115839.6" wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:115743.3-115785.6" + attribute \src "libresoc.v:115539.3-115581.6" wire width 3 $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:115786.3-115828.6" + attribute \src "libresoc.v:115582.3-115624.6" wire width 3 $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:115829.3-115871.6" + attribute \src "libresoc.v:115625.3-115667.6" wire width 3 $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:115915.3-115957.6" + attribute \src "libresoc.v:115711.3-115753.6" wire width 3 $1\dec31_dec_sub8_sv_out2[2:0] - attribute \src "libresoc.v:115872.3-115914.6" + attribute \src "libresoc.v:115668.3-115710.6" wire width 3 $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:116130.3-116172.6" + attribute \src "libresoc.v:115926.3-115968.6" wire width 2 $1\dec31_dec_sub8_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -179856,28 +179652,28 @@ module \dec31_dec_sub8 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub8_upd - attribute \src "libresoc.v:115266.7-115266.15" + attribute \src "libresoc.v:115062.7-115062.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:115266.7-115266.20" - process $proc$libresoc.v:115266$4412 + attribute \src "libresoc.v:115062.7-115062.20" + process $proc$libresoc.v:115062$4412 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115614.3-115656.6" - process $proc$libresoc.v:115614$4379 + attribute \src "libresoc.v:115410.3-115452.6" + process $proc$libresoc.v:115410$4379 assign { } { } assign { } { } assign $0\dec31_dec_sub8_function_unit[13:0] $1\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:115615.5-115615.29" + attribute \src "libresoc.v:115411.5-115411.29" switch \initial - attribute \src "libresoc.v:115615.9-115615.17" + attribute \src "libresoc.v:115411.9-115411.17" case 1'1 case end @@ -179937,14 +179733,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[13:0] end - attribute \src "libresoc.v:115657.3-115699.6" - process $proc$libresoc.v:115657$4380 + attribute \src "libresoc.v:115453.3-115495.6" + process $proc$libresoc.v:115453$4380 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:115658.5-115658.29" + attribute \src "libresoc.v:115454.5-115454.29" switch \initial - attribute \src "libresoc.v:115658.9-115658.17" + attribute \src "libresoc.v:115454.9-115454.17" case 1'1 case end @@ -180004,14 +179800,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:115700.3-115742.6" - process $proc$libresoc.v:115700$4381 + attribute \src "libresoc.v:115496.3-115538.6" + process $proc$libresoc.v:115496$4381 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:115701.5-115701.29" + attribute \src "libresoc.v:115497.5-115497.29" switch \initial - attribute \src "libresoc.v:115701.9-115701.17" + attribute \src "libresoc.v:115497.9-115497.17" case 1'1 case end @@ -180071,14 +179867,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end - attribute \src "libresoc.v:115743.3-115785.6" - process $proc$libresoc.v:115743$4382 + attribute \src "libresoc.v:115539.3-115581.6" + process $proc$libresoc.v:115539$4382 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:115744.5-115744.29" + attribute \src "libresoc.v:115540.5-115540.29" switch \initial - attribute \src "libresoc.v:115744.9-115744.17" + attribute \src "libresoc.v:115540.9-115540.17" case 1'1 case end @@ -180138,14 +179934,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0] end - attribute \src "libresoc.v:115786.3-115828.6" - process $proc$libresoc.v:115786$4383 + attribute \src "libresoc.v:115582.3-115624.6" + process $proc$libresoc.v:115582$4383 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:115787.5-115787.29" + attribute \src "libresoc.v:115583.5-115583.29" switch \initial - attribute \src "libresoc.v:115787.9-115787.17" + attribute \src "libresoc.v:115583.9-115583.17" case 1'1 case end @@ -180205,14 +180001,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0] end - attribute \src "libresoc.v:115829.3-115871.6" - process $proc$libresoc.v:115829$4384 + attribute \src "libresoc.v:115625.3-115667.6" + process $proc$libresoc.v:115625$4384 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:115830.5-115830.29" + attribute \src "libresoc.v:115626.5-115626.29" switch \initial - attribute \src "libresoc.v:115830.9-115830.17" + attribute \src "libresoc.v:115626.9-115626.17" case 1'1 case end @@ -180272,14 +180068,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0] end - attribute \src "libresoc.v:115872.3-115914.6" - process $proc$libresoc.v:115872$4385 + attribute \src "libresoc.v:115668.3-115710.6" + process $proc$libresoc.v:115668$4385 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:115873.5-115873.29" + attribute \src "libresoc.v:115669.5-115669.29" switch \initial - attribute \src "libresoc.v:115873.9-115873.17" + attribute \src "libresoc.v:115669.9-115669.17" case 1'1 case end @@ -180339,14 +180135,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0] end - attribute \src "libresoc.v:115915.3-115957.6" - process $proc$libresoc.v:115915$4386 + attribute \src "libresoc.v:115711.3-115753.6" + process $proc$libresoc.v:115711$4386 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out2[2:0] $1\dec31_dec_sub8_sv_out2[2:0] - attribute \src "libresoc.v:115916.5-115916.29" + attribute \src "libresoc.v:115712.5-115712.29" switch \initial - attribute \src "libresoc.v:115916.9-115916.17" + attribute \src "libresoc.v:115712.9-115712.17" case 1'1 case end @@ -180406,14 +180202,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_out2 $0\dec31_dec_sub8_sv_out2[2:0] end - attribute \src "libresoc.v:115958.3-116000.6" - process $proc$libresoc.v:115958$4387 + attribute \src "libresoc.v:115754.3-115796.6" + process $proc$libresoc.v:115754$4387 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:115959.5-115959.29" + attribute \src "libresoc.v:115755.5-115755.29" switch \initial - attribute \src "libresoc.v:115959.9-115959.17" + attribute \src "libresoc.v:115755.9-115755.17" case 1'1 case end @@ -180473,14 +180269,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0] end - attribute \src "libresoc.v:116001.3-116043.6" - process $proc$libresoc.v:116001$4388 + attribute \src "libresoc.v:115797.3-115839.6" + process $proc$libresoc.v:115797$4388 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:116002.5-116002.29" + attribute \src "libresoc.v:115798.5-115798.29" switch \initial - attribute \src "libresoc.v:116002.9-116002.17" + attribute \src "libresoc.v:115798.9-115798.17" case 1'1 case end @@ -180540,14 +180336,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0] end - attribute \src "libresoc.v:116044.3-116086.6" - process $proc$libresoc.v:116044$4389 + attribute \src "libresoc.v:115840.3-115882.6" + process $proc$libresoc.v:115840$4389 assign { } { } assign { } { } assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:116045.5-116045.29" + attribute \src "libresoc.v:115841.5-115841.29" switch \initial - attribute \src "libresoc.v:116045.9-116045.17" + attribute \src "libresoc.v:115841.9-115841.17" case 1'1 case end @@ -180607,14 +180403,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:116087.3-116129.6" - process $proc$libresoc.v:116087$4390 + attribute \src "libresoc.v:115883.3-115925.6" + process $proc$libresoc.v:115883$4390 assign { } { } assign { } { } assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:116088.5-116088.29" + attribute \src "libresoc.v:115884.5-115884.29" switch \initial - attribute \src "libresoc.v:116088.9-116088.17" + attribute \src "libresoc.v:115884.9-115884.17" case 1'1 case end @@ -180674,14 +180470,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:116130.3-116172.6" - process $proc$libresoc.v:116130$4391 + attribute \src "libresoc.v:115926.3-115968.6" + process $proc$libresoc.v:115926$4391 assign { } { } assign { } { } assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:116131.5-116131.29" + attribute \src "libresoc.v:115927.5-115927.29" switch \initial - attribute \src "libresoc.v:116131.9-116131.17" + attribute \src "libresoc.v:115927.9-115927.17" case 1'1 case end @@ -180741,14 +180537,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end - attribute \src "libresoc.v:116173.3-116215.6" - process $proc$libresoc.v:116173$4392 + attribute \src "libresoc.v:115969.3-116011.6" + process $proc$libresoc.v:115969$4392 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:116174.5-116174.29" + attribute \src "libresoc.v:115970.5-115970.29" switch \initial - attribute \src "libresoc.v:116174.9-116174.17" + attribute \src "libresoc.v:115970.9-115970.17" case 1'1 case end @@ -180808,14 +180604,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:116216.3-116258.6" - process $proc$libresoc.v:116216$4393 + attribute \src "libresoc.v:116012.3-116054.6" + process $proc$libresoc.v:116012$4393 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:116217.5-116217.29" + attribute \src "libresoc.v:116013.5-116013.29" switch \initial - attribute \src "libresoc.v:116217.9-116217.17" + attribute \src "libresoc.v:116013.9-116013.17" case 1'1 case end @@ -180875,14 +180671,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end - attribute \src "libresoc.v:116259.3-116301.6" - process $proc$libresoc.v:116259$4394 + attribute \src "libresoc.v:116055.3-116097.6" + process $proc$libresoc.v:116055$4394 assign { } { } assign { } { } assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:116260.5-116260.29" + attribute \src "libresoc.v:116056.5-116056.29" switch \initial - attribute \src "libresoc.v:116260.9-116260.17" + attribute \src "libresoc.v:116056.9-116056.17" case 1'1 case end @@ -180942,14 +180738,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end - attribute \src "libresoc.v:116302.3-116344.6" - process $proc$libresoc.v:116302$4395 + attribute \src "libresoc.v:116098.3-116140.6" + process $proc$libresoc.v:116098$4395 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:116303.5-116303.29" + attribute \src "libresoc.v:116099.5-116099.29" switch \initial - attribute \src "libresoc.v:116303.9-116303.17" + attribute \src "libresoc.v:116099.9-116099.17" case 1'1 case end @@ -181009,14 +180805,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] end - attribute \src "libresoc.v:116345.3-116387.6" - process $proc$libresoc.v:116345$4396 + attribute \src "libresoc.v:116141.3-116183.6" + process $proc$libresoc.v:116141$4396 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:116346.5-116346.29" + attribute \src "libresoc.v:116142.5-116142.29" switch \initial - attribute \src "libresoc.v:116346.9-116346.17" + attribute \src "libresoc.v:116142.9-116142.17" case 1'1 case end @@ -181076,14 +180872,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:116388.3-116430.6" - process $proc$libresoc.v:116388$4397 + attribute \src "libresoc.v:116184.3-116226.6" + process $proc$libresoc.v:116184$4397 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:116389.5-116389.29" + attribute \src "libresoc.v:116185.5-116185.29" switch \initial - attribute \src "libresoc.v:116389.9-116389.17" + attribute \src "libresoc.v:116185.9-116185.17" case 1'1 case end @@ -181143,14 +180939,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] end - attribute \src "libresoc.v:116431.3-116473.6" - process $proc$libresoc.v:116431$4398 + attribute \src "libresoc.v:116227.3-116269.6" + process $proc$libresoc.v:116227$4398 assign { } { } assign { } { } assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:116432.5-116432.29" + attribute \src "libresoc.v:116228.5-116228.29" switch \initial - attribute \src "libresoc.v:116432.9-116432.17" + attribute \src "libresoc.v:116228.9-116228.17" case 1'1 case end @@ -181210,14 +181006,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end - attribute \src "libresoc.v:116474.3-116516.6" - process $proc$libresoc.v:116474$4399 + attribute \src "libresoc.v:116270.3-116312.6" + process $proc$libresoc.v:116270$4399 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:116475.5-116475.29" + attribute \src "libresoc.v:116271.5-116271.29" switch \initial - attribute \src "libresoc.v:116475.9-116475.17" + attribute \src "libresoc.v:116271.9-116271.17" case 1'1 case end @@ -181277,14 +181073,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] end - attribute \src "libresoc.v:116517.3-116559.6" - process $proc$libresoc.v:116517$4400 + attribute \src "libresoc.v:116313.3-116355.6" + process $proc$libresoc.v:116313$4400 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:116518.5-116518.29" + attribute \src "libresoc.v:116314.5-116314.29" switch \initial - attribute \src "libresoc.v:116518.9-116518.17" + attribute \src "libresoc.v:116314.9-116314.17" case 1'1 case end @@ -181344,14 +181140,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end - attribute \src "libresoc.v:116560.3-116602.6" - process $proc$libresoc.v:116560$4401 + attribute \src "libresoc.v:116356.3-116398.6" + process $proc$libresoc.v:116356$4401 assign { } { } assign { } { } assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:116561.5-116561.29" + attribute \src "libresoc.v:116357.5-116357.29" switch \initial - attribute \src "libresoc.v:116561.9-116561.17" + attribute \src "libresoc.v:116357.9-116357.17" case 1'1 case end @@ -181411,14 +181207,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end - attribute \src "libresoc.v:116603.3-116645.6" - process $proc$libresoc.v:116603$4402 + attribute \src "libresoc.v:116399.3-116441.6" + process $proc$libresoc.v:116399$4402 assign { } { } assign { } { } assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:116604.5-116604.29" + attribute \src "libresoc.v:116400.5-116400.29" switch \initial - attribute \src "libresoc.v:116604.9-116604.17" + attribute \src "libresoc.v:116400.9-116400.17" case 1'1 case end @@ -181478,14 +181274,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] end - attribute \src "libresoc.v:116646.3-116688.6" - process $proc$libresoc.v:116646$4403 + attribute \src "libresoc.v:116442.3-116484.6" + process $proc$libresoc.v:116442$4403 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:116647.5-116647.29" + attribute \src "libresoc.v:116443.5-116443.29" switch \initial - attribute \src "libresoc.v:116647.9-116647.17" + attribute \src "libresoc.v:116443.9-116443.17" case 1'1 case end @@ -181545,14 +181341,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:116689.3-116731.6" - process $proc$libresoc.v:116689$4404 + attribute \src "libresoc.v:116485.3-116527.6" + process $proc$libresoc.v:116485$4404 assign { } { } assign { } { } assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:116690.5-116690.29" + attribute \src "libresoc.v:116486.5-116486.29" switch \initial - attribute \src "libresoc.v:116690.9-116690.17" + attribute \src "libresoc.v:116486.9-116486.17" case 1'1 case end @@ -181612,14 +181408,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] end - attribute \src "libresoc.v:116732.3-116774.6" - process $proc$libresoc.v:116732$4405 + attribute \src "libresoc.v:116528.3-116570.6" + process $proc$libresoc.v:116528$4405 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:116733.5-116733.29" + attribute \src "libresoc.v:116529.5-116529.29" switch \initial - attribute \src "libresoc.v:116733.9-116733.17" + attribute \src "libresoc.v:116529.9-116529.17" case 1'1 case end @@ -181679,14 +181475,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end - attribute \src "libresoc.v:116775.3-116817.6" - process $proc$libresoc.v:116775$4406 + attribute \src "libresoc.v:116571.3-116613.6" + process $proc$libresoc.v:116571$4406 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:116776.5-116776.29" + attribute \src "libresoc.v:116572.5-116572.29" switch \initial - attribute \src "libresoc.v:116776.9-116776.17" + attribute \src "libresoc.v:116572.9-116572.17" case 1'1 case end @@ -181746,14 +181542,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0] end - attribute \src "libresoc.v:116818.3-116860.6" - process $proc$libresoc.v:116818$4407 + attribute \src "libresoc.v:116614.3-116656.6" + process $proc$libresoc.v:116614$4407 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:116819.5-116819.29" + attribute \src "libresoc.v:116615.5-116615.29" switch \initial - attribute \src "libresoc.v:116819.9-116819.17" + attribute \src "libresoc.v:116615.9-116615.17" case 1'1 case end @@ -181813,14 +181609,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0] end - attribute \src "libresoc.v:116861.3-116903.6" - process $proc$libresoc.v:116861$4408 + attribute \src "libresoc.v:116657.3-116699.6" + process $proc$libresoc.v:116657$4408 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:116862.5-116862.29" + attribute \src "libresoc.v:116658.5-116658.29" switch \initial - attribute \src "libresoc.v:116862.9-116862.17" + attribute \src "libresoc.v:116658.9-116658.17" case 1'1 case end @@ -181880,14 +181676,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:116904.3-116946.6" - process $proc$libresoc.v:116904$4409 + attribute \src "libresoc.v:116700.3-116742.6" + process $proc$libresoc.v:116700$4409 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:116905.5-116905.29" + attribute \src "libresoc.v:116701.5-116701.29" switch \initial - attribute \src "libresoc.v:116905.9-116905.17" + attribute \src "libresoc.v:116701.9-116701.17" case 1'1 case end @@ -181947,14 +181743,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:116947.3-116989.6" - process $proc$libresoc.v:116947$4410 + attribute \src "libresoc.v:116743.3-116785.6" + process $proc$libresoc.v:116743$4410 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:116948.5-116948.29" + attribute \src "libresoc.v:116744.5-116744.29" switch \initial - attribute \src "libresoc.v:116948.9-116948.17" + attribute \src "libresoc.v:116744.9-116744.17" case 1'1 case end @@ -182014,14 +181810,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end - attribute \src "libresoc.v:116990.3-117032.6" - process $proc$libresoc.v:116990$4411 + attribute \src "libresoc.v:116786.3-116828.6" + process $proc$libresoc.v:116786$4411 assign { } { } assign { } { } assign $0\dec31_dec_sub8_out_sel[2:0] $1\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:116991.5-116991.29" + attribute \src "libresoc.v:116787.5-116787.29" switch \initial - attribute \src "libresoc.v:116991.9-116991.17" + attribute \src "libresoc.v:116787.9-116787.17" case 1'1 case end @@ -182083,144 +181879,144 @@ module \dec31_dec_sub8 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:117038.1-119203.10" +attribute \src "libresoc.v:116834.1-118999.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" attribute \generator "nMigen" module \dec31_dec_sub9 - attribute \src "libresoc.v:118872.3-118926.6" + attribute \src "libresoc.v:118668.3-118722.6" wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:118927.3-118981.6" + attribute \src "libresoc.v:118723.3-118777.6" wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:118212.3-118266.6" + attribute \src "libresoc.v:118008.3-118062.6" wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:118432.3-118486.6" + attribute \src "libresoc.v:118228.3-118282.6" wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:117442.3-117496.6" + attribute \src "libresoc.v:117238.3-117292.6" wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:117497.3-117551.6" + attribute \src "libresoc.v:117293.3-117347.6" wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:118157.3-118211.6" + attribute \src "libresoc.v:117953.3-118007.6" wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:118377.3-118431.6" + attribute \src "libresoc.v:118173.3-118227.6" wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:118597.3-118651.6" + attribute \src "libresoc.v:118393.3-118447.6" wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:117387.3-117441.6" + attribute \src "libresoc.v:117183.3-117237.6" wire width 14 $0\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:118982.3-119036.6" + attribute \src "libresoc.v:118778.3-118832.6" wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:119037.3-119091.6" + attribute \src "libresoc.v:118833.3-118887.6" wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:119092.3-119146.6" + attribute \src "libresoc.v:118888.3-118942.6" wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:117992.3-118046.6" + attribute \src "libresoc.v:117788.3-117842.6" wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:118267.3-118321.6" + attribute \src "libresoc.v:118063.3-118117.6" wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:118322.3-118376.6" + attribute \src "libresoc.v:118118.3-118172.6" wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:118652.3-118706.6" + attribute \src "libresoc.v:118448.3-118502.6" wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:117937.3-117991.6" + attribute \src "libresoc.v:117733.3-117787.6" wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:118762.3-118816.6" + attribute \src "libresoc.v:118558.3-118612.6" wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:119147.3-119201.6" + attribute \src "libresoc.v:118943.3-118997.6" wire width 3 $0\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:118102.3-118156.6" + attribute \src "libresoc.v:117898.3-117952.6" wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:118542.3-118596.6" + attribute \src "libresoc.v:118338.3-118392.6" wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:118817.3-118871.6" + attribute \src "libresoc.v:118613.3-118667.6" wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:118707.3-118761.6" + attribute \src "libresoc.v:118503.3-118557.6" wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:118487.3-118541.6" + attribute \src "libresoc.v:118283.3-118337.6" wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:117827.3-117881.6" + attribute \src "libresoc.v:117623.3-117677.6" wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:117882.3-117936.6" + attribute \src "libresoc.v:117678.3-117732.6" wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:117552.3-117606.6" + attribute \src "libresoc.v:117348.3-117402.6" wire width 3 $0\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:117607.3-117661.6" + attribute \src "libresoc.v:117403.3-117457.6" wire width 3 $0\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:117662.3-117716.6" + attribute \src "libresoc.v:117458.3-117512.6" wire width 3 $0\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:117772.3-117826.6" + attribute \src "libresoc.v:117568.3-117622.6" wire width 3 $0\dec31_dec_sub9_sv_out2[2:0] - attribute \src "libresoc.v:117717.3-117771.6" + attribute \src "libresoc.v:117513.3-117567.6" wire width 3 $0\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:118047.3-118101.6" + attribute \src "libresoc.v:117843.3-117897.6" wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:117039.7-117039.20" + attribute \src "libresoc.v:116835.7-116835.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118872.3-118926.6" + attribute \src "libresoc.v:118668.3-118722.6" wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:118927.3-118981.6" + attribute \src "libresoc.v:118723.3-118777.6" wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:118212.3-118266.6" + attribute \src "libresoc.v:118008.3-118062.6" wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:118432.3-118486.6" + attribute \src "libresoc.v:118228.3-118282.6" wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:117442.3-117496.6" + attribute \src "libresoc.v:117238.3-117292.6" wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:117497.3-117551.6" + attribute \src "libresoc.v:117293.3-117347.6" wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:118157.3-118211.6" + attribute \src "libresoc.v:117953.3-118007.6" wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:118377.3-118431.6" + attribute \src "libresoc.v:118173.3-118227.6" wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:118597.3-118651.6" + attribute \src "libresoc.v:118393.3-118447.6" wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:117387.3-117441.6" + attribute \src "libresoc.v:117183.3-117237.6" wire width 14 $1\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:118982.3-119036.6" + attribute \src "libresoc.v:118778.3-118832.6" wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:119037.3-119091.6" + attribute \src "libresoc.v:118833.3-118887.6" wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:119092.3-119146.6" + attribute \src "libresoc.v:118888.3-118942.6" wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:117992.3-118046.6" + attribute \src "libresoc.v:117788.3-117842.6" wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:118267.3-118321.6" + attribute \src "libresoc.v:118063.3-118117.6" wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:118322.3-118376.6" + attribute \src "libresoc.v:118118.3-118172.6" wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:118652.3-118706.6" + attribute \src "libresoc.v:118448.3-118502.6" wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:117937.3-117991.6" + attribute \src "libresoc.v:117733.3-117787.6" wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:118762.3-118816.6" + attribute \src "libresoc.v:118558.3-118612.6" wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:119147.3-119201.6" + attribute \src "libresoc.v:118943.3-118997.6" wire width 3 $1\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:118102.3-118156.6" + attribute \src "libresoc.v:117898.3-117952.6" wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:118542.3-118596.6" + attribute \src "libresoc.v:118338.3-118392.6" wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:118817.3-118871.6" + attribute \src "libresoc.v:118613.3-118667.6" wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:118707.3-118761.6" + attribute \src "libresoc.v:118503.3-118557.6" wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:118487.3-118541.6" + attribute \src "libresoc.v:118283.3-118337.6" wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:117827.3-117881.6" + attribute \src "libresoc.v:117623.3-117677.6" wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:117882.3-117936.6" + attribute \src "libresoc.v:117678.3-117732.6" wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:117552.3-117606.6" + attribute \src "libresoc.v:117348.3-117402.6" wire width 3 $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:117607.3-117661.6" + attribute \src "libresoc.v:117403.3-117457.6" wire width 3 $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:117662.3-117716.6" + attribute \src "libresoc.v:117458.3-117512.6" wire width 3 $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:117772.3-117826.6" + attribute \src "libresoc.v:117568.3-117622.6" wire width 3 $1\dec31_dec_sub9_sv_out2[2:0] - attribute \src "libresoc.v:117717.3-117771.6" + attribute \src "libresoc.v:117513.3-117567.6" wire width 3 $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:118047.3-118101.6" + attribute \src "libresoc.v:117843.3-117897.6" wire width 2 $1\dec31_dec_sub9_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -182532,28 +182328,28 @@ module \dec31_dec_sub9 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub9_upd - attribute \src "libresoc.v:117039.7-117039.15" + attribute \src "libresoc.v:116835.7-116835.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:117039.7-117039.20" - process $proc$libresoc.v:117039$4446 + attribute \src "libresoc.v:116835.7-116835.20" + process $proc$libresoc.v:116835$4446 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:117387.3-117441.6" - process $proc$libresoc.v:117387$4413 + attribute \src "libresoc.v:117183.3-117237.6" + process $proc$libresoc.v:117183$4413 assign { } { } assign { } { } assign $0\dec31_dec_sub9_function_unit[13:0] $1\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:117388.5-117388.29" + attribute \src "libresoc.v:117184.5-117184.29" switch \initial - attribute \src "libresoc.v:117388.9-117388.17" + attribute \src "libresoc.v:117184.9-117184.17" case 1'1 case end @@ -182629,14 +182425,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[13:0] end - attribute \src "libresoc.v:117442.3-117496.6" - process $proc$libresoc.v:117442$4414 + attribute \src "libresoc.v:117238.3-117292.6" + process $proc$libresoc.v:117238$4414 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:117443.5-117443.29" + attribute \src "libresoc.v:117239.5-117239.29" switch \initial - attribute \src "libresoc.v:117443.9-117443.17" + attribute \src "libresoc.v:117239.9-117239.17" case 1'1 case end @@ -182712,14 +182508,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:117497.3-117551.6" - process $proc$libresoc.v:117497$4415 + attribute \src "libresoc.v:117293.3-117347.6" + process $proc$libresoc.v:117293$4415 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:117498.5-117498.29" + attribute \src "libresoc.v:117294.5-117294.29" switch \initial - attribute \src "libresoc.v:117498.9-117498.17" + attribute \src "libresoc.v:117294.9-117294.17" case 1'1 case end @@ -182795,14 +182591,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:117552.3-117606.6" - process $proc$libresoc.v:117552$4416 + attribute \src "libresoc.v:117348.3-117402.6" + process $proc$libresoc.v:117348$4416 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:117553.5-117553.29" + attribute \src "libresoc.v:117349.5-117349.29" switch \initial - attribute \src "libresoc.v:117553.9-117553.17" + attribute \src "libresoc.v:117349.9-117349.17" case 1'1 case end @@ -182878,14 +182674,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0] end - attribute \src "libresoc.v:117607.3-117661.6" - process $proc$libresoc.v:117607$4417 + attribute \src "libresoc.v:117403.3-117457.6" + process $proc$libresoc.v:117403$4417 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:117608.5-117608.29" + attribute \src "libresoc.v:117404.5-117404.29" switch \initial - attribute \src "libresoc.v:117608.9-117608.17" + attribute \src "libresoc.v:117404.9-117404.17" case 1'1 case end @@ -182961,14 +182757,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0] end - attribute \src "libresoc.v:117662.3-117716.6" - process $proc$libresoc.v:117662$4418 + attribute \src "libresoc.v:117458.3-117512.6" + process $proc$libresoc.v:117458$4418 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:117663.5-117663.29" + attribute \src "libresoc.v:117459.5-117459.29" switch \initial - attribute \src "libresoc.v:117663.9-117663.17" + attribute \src "libresoc.v:117459.9-117459.17" case 1'1 case end @@ -183044,14 +182840,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0] end - attribute \src "libresoc.v:117717.3-117771.6" - process $proc$libresoc.v:117717$4419 + attribute \src "libresoc.v:117513.3-117567.6" + process $proc$libresoc.v:117513$4419 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:117718.5-117718.29" + attribute \src "libresoc.v:117514.5-117514.29" switch \initial - attribute \src "libresoc.v:117718.9-117718.17" + attribute \src "libresoc.v:117514.9-117514.17" case 1'1 case end @@ -183127,14 +182923,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0] end - attribute \src "libresoc.v:117772.3-117826.6" - process $proc$libresoc.v:117772$4420 + attribute \src "libresoc.v:117568.3-117622.6" + process $proc$libresoc.v:117568$4420 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out2[2:0] $1\dec31_dec_sub9_sv_out2[2:0] - attribute \src "libresoc.v:117773.5-117773.29" + attribute \src "libresoc.v:117569.5-117569.29" switch \initial - attribute \src "libresoc.v:117773.9-117773.17" + attribute \src "libresoc.v:117569.9-117569.17" case 1'1 case end @@ -183210,14 +183006,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_out2 $0\dec31_dec_sub9_sv_out2[2:0] end - attribute \src "libresoc.v:117827.3-117881.6" - process $proc$libresoc.v:117827$4421 + attribute \src "libresoc.v:117623.3-117677.6" + process $proc$libresoc.v:117623$4421 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:117828.5-117828.29" + attribute \src "libresoc.v:117624.5-117624.29" switch \initial - attribute \src "libresoc.v:117828.9-117828.17" + attribute \src "libresoc.v:117624.9-117624.17" case 1'1 case end @@ -183293,14 +183089,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0] end - attribute \src "libresoc.v:117882.3-117936.6" - process $proc$libresoc.v:117882$4422 + attribute \src "libresoc.v:117678.3-117732.6" + process $proc$libresoc.v:117678$4422 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:117883.5-117883.29" + attribute \src "libresoc.v:117679.5-117679.29" switch \initial - attribute \src "libresoc.v:117883.9-117883.17" + attribute \src "libresoc.v:117679.9-117679.17" case 1'1 case end @@ -183376,14 +183172,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0] end - attribute \src "libresoc.v:117937.3-117991.6" - process $proc$libresoc.v:117937$4423 + attribute \src "libresoc.v:117733.3-117787.6" + process $proc$libresoc.v:117733$4423 assign { } { } assign { } { } assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:117938.5-117938.29" + attribute \src "libresoc.v:117734.5-117734.29" switch \initial - attribute \src "libresoc.v:117938.9-117938.17" + attribute \src "libresoc.v:117734.9-117734.17" case 1'1 case end @@ -183459,14 +183255,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:117992.3-118046.6" - process $proc$libresoc.v:117992$4424 + attribute \src "libresoc.v:117788.3-117842.6" + process $proc$libresoc.v:117788$4424 assign { } { } assign { } { } assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:117993.5-117993.29" + attribute \src "libresoc.v:117789.5-117789.29" switch \initial - attribute \src "libresoc.v:117993.9-117993.17" + attribute \src "libresoc.v:117789.9-117789.17" case 1'1 case end @@ -183542,14 +183338,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:118047.3-118101.6" - process $proc$libresoc.v:118047$4425 + attribute \src "libresoc.v:117843.3-117897.6" + process $proc$libresoc.v:117843$4425 assign { } { } assign { } { } assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:118048.5-118048.29" + attribute \src "libresoc.v:117844.5-117844.29" switch \initial - attribute \src "libresoc.v:118048.9-118048.17" + attribute \src "libresoc.v:117844.9-117844.17" case 1'1 case end @@ -183625,14 +183421,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "libresoc.v:118102.3-118156.6" - process $proc$libresoc.v:118102$4426 + attribute \src "libresoc.v:117898.3-117952.6" + process $proc$libresoc.v:117898$4426 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:118103.5-118103.29" + attribute \src "libresoc.v:117899.5-117899.29" switch \initial - attribute \src "libresoc.v:118103.9-118103.17" + attribute \src "libresoc.v:117899.9-117899.17" case 1'1 case end @@ -183708,14 +183504,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:118157.3-118211.6" - process $proc$libresoc.v:118157$4427 + attribute \src "libresoc.v:117953.3-118007.6" + process $proc$libresoc.v:117953$4427 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:118158.5-118158.29" + attribute \src "libresoc.v:117954.5-117954.29" switch \initial - attribute \src "libresoc.v:118158.9-118158.17" + attribute \src "libresoc.v:117954.9-117954.17" case 1'1 case end @@ -183791,14 +183587,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "libresoc.v:118212.3-118266.6" - process $proc$libresoc.v:118212$4428 + attribute \src "libresoc.v:118008.3-118062.6" + process $proc$libresoc.v:118008$4428 assign { } { } assign { } { } assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:118213.5-118213.29" + attribute \src "libresoc.v:118009.5-118009.29" switch \initial - attribute \src "libresoc.v:118213.9-118213.17" + attribute \src "libresoc.v:118009.9-118009.17" case 1'1 case end @@ -183874,14 +183670,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "libresoc.v:118267.3-118321.6" - process $proc$libresoc.v:118267$4429 + attribute \src "libresoc.v:118063.3-118117.6" + process $proc$libresoc.v:118063$4429 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:118268.5-118268.29" + attribute \src "libresoc.v:118064.5-118064.29" switch \initial - attribute \src "libresoc.v:118268.9-118268.17" + attribute \src "libresoc.v:118064.9-118064.17" case 1'1 case end @@ -183957,14 +183753,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:118322.3-118376.6" - process $proc$libresoc.v:118322$4430 + attribute \src "libresoc.v:118118.3-118172.6" + process $proc$libresoc.v:118118$4430 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:118323.5-118323.29" + attribute \src "libresoc.v:118119.5-118119.29" switch \initial - attribute \src "libresoc.v:118323.9-118323.17" + attribute \src "libresoc.v:118119.9-118119.17" case 1'1 case end @@ -184040,14 +183836,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:118377.3-118431.6" - process $proc$libresoc.v:118377$4431 + attribute \src "libresoc.v:118173.3-118227.6" + process $proc$libresoc.v:118173$4431 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:118378.5-118378.29" + attribute \src "libresoc.v:118174.5-118174.29" switch \initial - attribute \src "libresoc.v:118378.9-118378.17" + attribute \src "libresoc.v:118174.9-118174.17" case 1'1 case end @@ -184123,14 +183919,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:118432.3-118486.6" - process $proc$libresoc.v:118432$4432 + attribute \src "libresoc.v:118228.3-118282.6" + process $proc$libresoc.v:118228$4432 assign { } { } assign { } { } assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:118433.5-118433.29" + attribute \src "libresoc.v:118229.5-118229.29" switch \initial - attribute \src "libresoc.v:118433.9-118433.17" + attribute \src "libresoc.v:118229.9-118229.17" case 1'1 case end @@ -184206,14 +184002,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - attribute \src "libresoc.v:118487.3-118541.6" - process $proc$libresoc.v:118487$4433 + attribute \src "libresoc.v:118283.3-118337.6" + process $proc$libresoc.v:118283$4433 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:118488.5-118488.29" + attribute \src "libresoc.v:118284.5-118284.29" switch \initial - attribute \src "libresoc.v:118488.9-118488.17" + attribute \src "libresoc.v:118284.9-118284.17" case 1'1 case end @@ -184289,14 +184085,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \src "libresoc.v:118542.3-118596.6" - process $proc$libresoc.v:118542$4434 + attribute \src "libresoc.v:118338.3-118392.6" + process $proc$libresoc.v:118338$4434 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:118543.5-118543.29" + attribute \src "libresoc.v:118339.5-118339.29" switch \initial - attribute \src "libresoc.v:118543.9-118543.17" + attribute \src "libresoc.v:118339.9-118339.17" case 1'1 case end @@ -184372,14 +184168,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \src "libresoc.v:118597.3-118651.6" - process $proc$libresoc.v:118597$4435 + attribute \src "libresoc.v:118393.3-118447.6" + process $proc$libresoc.v:118393$4435 assign { } { } assign { } { } assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:118598.5-118598.29" + attribute \src "libresoc.v:118394.5-118394.29" switch \initial - attribute \src "libresoc.v:118598.9-118598.17" + attribute \src "libresoc.v:118394.9-118394.17" case 1'1 case end @@ -184455,14 +184251,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \src "libresoc.v:118652.3-118706.6" - process $proc$libresoc.v:118652$4436 + attribute \src "libresoc.v:118448.3-118502.6" + process $proc$libresoc.v:118448$4436 assign { } { } assign { } { } assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:118653.5-118653.29" + attribute \src "libresoc.v:118449.5-118449.29" switch \initial - attribute \src "libresoc.v:118653.9-118653.17" + attribute \src "libresoc.v:118449.9-118449.17" case 1'1 case end @@ -184538,14 +184334,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:118707.3-118761.6" - process $proc$libresoc.v:118707$4437 + attribute \src "libresoc.v:118503.3-118557.6" + process $proc$libresoc.v:118503$4437 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:118708.5-118708.29" + attribute \src "libresoc.v:118504.5-118504.29" switch \initial - attribute \src "libresoc.v:118708.9-118708.17" + attribute \src "libresoc.v:118504.9-118504.17" case 1'1 case end @@ -184621,14 +184417,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:118762.3-118816.6" - process $proc$libresoc.v:118762$4438 + attribute \src "libresoc.v:118558.3-118612.6" + process $proc$libresoc.v:118558$4438 assign { } { } assign { } { } assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:118763.5-118763.29" + attribute \src "libresoc.v:118559.5-118559.29" switch \initial - attribute \src "libresoc.v:118763.9-118763.17" + attribute \src "libresoc.v:118559.9-118559.17" case 1'1 case end @@ -184704,14 +184500,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \src "libresoc.v:118817.3-118871.6" - process $proc$libresoc.v:118817$4439 + attribute \src "libresoc.v:118613.3-118667.6" + process $proc$libresoc.v:118613$4439 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:118818.5-118818.29" + attribute \src "libresoc.v:118614.5-118614.29" switch \initial - attribute \src "libresoc.v:118818.9-118818.17" + attribute \src "libresoc.v:118614.9-118614.17" case 1'1 case end @@ -184787,14 +184583,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - attribute \src "libresoc.v:118872.3-118926.6" - process $proc$libresoc.v:118872$4440 + attribute \src "libresoc.v:118668.3-118722.6" + process $proc$libresoc.v:118668$4440 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:118873.5-118873.29" + attribute \src "libresoc.v:118669.5-118669.29" switch \initial - attribute \src "libresoc.v:118873.9-118873.17" + attribute \src "libresoc.v:118669.9-118669.17" case 1'1 case end @@ -184870,14 +184666,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0] end - attribute \src "libresoc.v:118927.3-118981.6" - process $proc$libresoc.v:118927$4441 + attribute \src "libresoc.v:118723.3-118777.6" + process $proc$libresoc.v:118723$4441 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:118928.5-118928.29" + attribute \src "libresoc.v:118724.5-118724.29" switch \initial - attribute \src "libresoc.v:118928.9-118928.17" + attribute \src "libresoc.v:118724.9-118724.17" case 1'1 case end @@ -184953,14 +184749,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0] end - attribute \src "libresoc.v:118982.3-119036.6" - process $proc$libresoc.v:118982$4442 + attribute \src "libresoc.v:118778.3-118832.6" + process $proc$libresoc.v:118778$4442 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:118983.5-118983.29" + attribute \src "libresoc.v:118779.5-118779.29" switch \initial - attribute \src "libresoc.v:118983.9-118983.17" + attribute \src "libresoc.v:118779.9-118779.17" case 1'1 case end @@ -185036,14 +184832,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:119037.3-119091.6" - process $proc$libresoc.v:119037$4443 + attribute \src "libresoc.v:118833.3-118887.6" + process $proc$libresoc.v:118833$4443 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:119038.5-119038.29" + attribute \src "libresoc.v:118834.5-118834.29" switch \initial - attribute \src "libresoc.v:119038.9-119038.17" + attribute \src "libresoc.v:118834.9-118834.17" case 1'1 case end @@ -185119,14 +184915,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:119092.3-119146.6" - process $proc$libresoc.v:119092$4444 + attribute \src "libresoc.v:118888.3-118942.6" + process $proc$libresoc.v:118888$4444 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:119093.5-119093.29" + attribute \src "libresoc.v:118889.5-118889.29" switch \initial - attribute \src "libresoc.v:119093.9-119093.17" + attribute \src "libresoc.v:118889.9-118889.17" case 1'1 case end @@ -185202,14 +184998,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end - attribute \src "libresoc.v:119147.3-119201.6" - process $proc$libresoc.v:119147$4445 + attribute \src "libresoc.v:118943.3-118997.6" + process $proc$libresoc.v:118943$4445 assign { } { } assign { } { } assign $0\dec31_dec_sub9_out_sel[2:0] $1\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:119148.5-119148.29" + attribute \src "libresoc.v:118944.5-118944.29" switch \initial - attribute \src "libresoc.v:119148.9-119148.17" + attribute \src "libresoc.v:118944.9-118944.17" case 1'1 case end @@ -185287,144 +185083,144 @@ module \dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:119207.1-120085.10" +attribute \src "libresoc.v:119003.1-119881.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" attribute \generator "nMigen" module \dec58 - attribute \src "libresoc.v:119988.3-120003.6" + attribute \src "libresoc.v:119784.3-119799.6" wire width 2 $0\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:120004.3-120019.6" + attribute \src "libresoc.v:119800.3-119815.6" wire width 2 $0\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:119796.3-119811.6" + attribute \src "libresoc.v:119592.3-119607.6" wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:119860.3-119875.6" + attribute \src "libresoc.v:119656.3-119671.6" wire $0\dec58_br[0:0] - attribute \src "libresoc.v:119572.3-119587.6" + attribute \src "libresoc.v:119368.3-119383.6" wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:119588.3-119603.6" + attribute \src "libresoc.v:119384.3-119399.6" wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:119780.3-119795.6" + attribute \src "libresoc.v:119576.3-119591.6" wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:119844.3-119859.6" + attribute \src "libresoc.v:119640.3-119655.6" wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:119908.3-119923.6" + attribute \src "libresoc.v:119704.3-119719.6" wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:119556.3-119571.6" + attribute \src "libresoc.v:119352.3-119367.6" wire width 14 $0\dec58_function_unit[13:0] - attribute \src "libresoc.v:120020.3-120035.6" + attribute \src "libresoc.v:119816.3-119831.6" wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:120036.3-120051.6" + attribute \src "libresoc.v:119832.3-119847.6" wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:120052.3-120067.6" + attribute \src "libresoc.v:119848.3-119863.6" wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:119732.3-119747.6" + attribute \src "libresoc.v:119528.3-119543.6" wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:119812.3-119827.6" + attribute \src "libresoc.v:119608.3-119623.6" wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:119828.3-119843.6" + attribute \src "libresoc.v:119624.3-119639.6" wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:119924.3-119939.6" + attribute \src "libresoc.v:119720.3-119735.6" wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:119716.3-119731.6" + attribute \src "libresoc.v:119512.3-119527.6" wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:119956.3-119971.6" + attribute \src "libresoc.v:119752.3-119767.6" wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:120068.3-120083.6" + attribute \src "libresoc.v:119864.3-119879.6" wire width 3 $0\dec58_out_sel[2:0] - attribute \src "libresoc.v:119764.3-119779.6" + attribute \src "libresoc.v:119560.3-119575.6" wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:119892.3-119907.6" + attribute \src "libresoc.v:119688.3-119703.6" wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:119972.3-119987.6" + attribute \src "libresoc.v:119768.3-119783.6" wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:119940.3-119955.6" + attribute \src "libresoc.v:119736.3-119751.6" wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:119876.3-119891.6" + attribute \src "libresoc.v:119672.3-119687.6" wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:119684.3-119699.6" + attribute \src "libresoc.v:119480.3-119495.6" wire width 3 $0\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:119700.3-119715.6" + attribute \src "libresoc.v:119496.3-119511.6" wire width 3 $0\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:119604.3-119619.6" + attribute \src "libresoc.v:119400.3-119415.6" wire width 3 $0\dec58_sv_in1[2:0] - attribute \src "libresoc.v:119620.3-119635.6" + attribute \src "libresoc.v:119416.3-119431.6" wire width 3 $0\dec58_sv_in2[2:0] - attribute \src "libresoc.v:119636.3-119651.6" + attribute \src "libresoc.v:119432.3-119447.6" wire width 3 $0\dec58_sv_in3[2:0] - attribute \src "libresoc.v:119668.3-119683.6" + attribute \src "libresoc.v:119464.3-119479.6" wire width 3 $0\dec58_sv_out2[2:0] - attribute \src "libresoc.v:119652.3-119667.6" + attribute \src "libresoc.v:119448.3-119463.6" wire width 3 $0\dec58_sv_out[2:0] - attribute \src "libresoc.v:119748.3-119763.6" + attribute \src "libresoc.v:119544.3-119559.6" wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:119208.7-119208.20" + attribute \src "libresoc.v:119004.7-119004.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119988.3-120003.6" + attribute \src "libresoc.v:119784.3-119799.6" wire width 2 $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:120004.3-120019.6" + attribute \src "libresoc.v:119800.3-119815.6" wire width 2 $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:119796.3-119811.6" + attribute \src "libresoc.v:119592.3-119607.6" wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:119860.3-119875.6" + attribute \src "libresoc.v:119656.3-119671.6" wire $1\dec58_br[0:0] - attribute \src "libresoc.v:119572.3-119587.6" + attribute \src "libresoc.v:119368.3-119383.6" wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:119588.3-119603.6" + attribute \src "libresoc.v:119384.3-119399.6" wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:119780.3-119795.6" + attribute \src "libresoc.v:119576.3-119591.6" wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:119844.3-119859.6" + attribute \src "libresoc.v:119640.3-119655.6" wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:119908.3-119923.6" + attribute \src "libresoc.v:119704.3-119719.6" wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:119556.3-119571.6" + attribute \src "libresoc.v:119352.3-119367.6" wire width 14 $1\dec58_function_unit[13:0] - attribute \src "libresoc.v:120020.3-120035.6" + attribute \src "libresoc.v:119816.3-119831.6" wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:120036.3-120051.6" + attribute \src "libresoc.v:119832.3-119847.6" wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:120052.3-120067.6" + attribute \src "libresoc.v:119848.3-119863.6" wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:119732.3-119747.6" + attribute \src "libresoc.v:119528.3-119543.6" wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:119812.3-119827.6" + attribute \src "libresoc.v:119608.3-119623.6" wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:119828.3-119843.6" + attribute \src "libresoc.v:119624.3-119639.6" wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:119924.3-119939.6" + attribute \src "libresoc.v:119720.3-119735.6" wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:119716.3-119731.6" + attribute \src "libresoc.v:119512.3-119527.6" wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:119956.3-119971.6" + attribute \src "libresoc.v:119752.3-119767.6" wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:120068.3-120083.6" + attribute \src "libresoc.v:119864.3-119879.6" wire width 3 $1\dec58_out_sel[2:0] - attribute \src "libresoc.v:119764.3-119779.6" + attribute \src "libresoc.v:119560.3-119575.6" wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:119892.3-119907.6" + attribute \src "libresoc.v:119688.3-119703.6" wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:119972.3-119987.6" + attribute \src "libresoc.v:119768.3-119783.6" wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:119940.3-119955.6" + attribute \src "libresoc.v:119736.3-119751.6" wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:119876.3-119891.6" + attribute \src "libresoc.v:119672.3-119687.6" wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:119684.3-119699.6" + attribute \src "libresoc.v:119480.3-119495.6" wire width 3 $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:119700.3-119715.6" + attribute \src "libresoc.v:119496.3-119511.6" wire width 3 $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:119604.3-119619.6" + attribute \src "libresoc.v:119400.3-119415.6" wire width 3 $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:119620.3-119635.6" + attribute \src "libresoc.v:119416.3-119431.6" wire width 3 $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:119636.3-119651.6" + attribute \src "libresoc.v:119432.3-119447.6" wire width 3 $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:119668.3-119683.6" + attribute \src "libresoc.v:119464.3-119479.6" wire width 3 $1\dec58_sv_out2[2:0] - attribute \src "libresoc.v:119652.3-119667.6" + attribute \src "libresoc.v:119448.3-119463.6" wire width 3 $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:119748.3-119763.6" + attribute \src "libresoc.v:119544.3-119559.6" wire width 2 $1\dec58_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -185736,28 +185532,28 @@ module \dec58 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec58_upd - attribute \src "libresoc.v:119208.7-119208.15" + attribute \src "libresoc.v:119004.7-119004.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch - attribute \src "libresoc.v:119208.7-119208.20" - process $proc$libresoc.v:119208$4480 + attribute \src "libresoc.v:119004.7-119004.20" + process $proc$libresoc.v:119004$4480 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119556.3-119571.6" - process $proc$libresoc.v:119556$4447 + attribute \src "libresoc.v:119352.3-119367.6" + process $proc$libresoc.v:119352$4447 assign { } { } assign { } { } assign $0\dec58_function_unit[13:0] $1\dec58_function_unit[13:0] - attribute \src "libresoc.v:119557.5-119557.29" + attribute \src "libresoc.v:119353.5-119353.29" switch \initial - attribute \src "libresoc.v:119557.9-119557.17" + attribute \src "libresoc.v:119353.9-119353.17" case 1'1 case end @@ -185781,14 +185577,14 @@ module \dec58 sync always update \dec58_function_unit $0\dec58_function_unit[13:0] end - attribute \src "libresoc.v:119572.3-119587.6" - process $proc$libresoc.v:119572$4448 + attribute \src "libresoc.v:119368.3-119383.6" + process $proc$libresoc.v:119368$4448 assign { } { } assign { } { } assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:119573.5-119573.29" + attribute \src "libresoc.v:119369.5-119369.29" switch \initial - attribute \src "libresoc.v:119573.9-119573.17" + attribute \src "libresoc.v:119369.9-119369.17" case 1'1 case end @@ -185812,14 +185608,14 @@ module \dec58 sync always update \dec58_cr_in $0\dec58_cr_in[2:0] end - attribute \src "libresoc.v:119588.3-119603.6" - process $proc$libresoc.v:119588$4449 + attribute \src "libresoc.v:119384.3-119399.6" + process $proc$libresoc.v:119384$4449 assign { } { } assign { } { } assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:119589.5-119589.29" + attribute \src "libresoc.v:119385.5-119385.29" switch \initial - attribute \src "libresoc.v:119589.9-119589.17" + attribute \src "libresoc.v:119385.9-119385.17" case 1'1 case end @@ -185843,14 +185639,14 @@ module \dec58 sync always update \dec58_cr_out $0\dec58_cr_out[2:0] end - attribute \src "libresoc.v:119604.3-119619.6" - process $proc$libresoc.v:119604$4450 + attribute \src "libresoc.v:119400.3-119415.6" + process $proc$libresoc.v:119400$4450 assign { } { } assign { } { } assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:119605.5-119605.29" + attribute \src "libresoc.v:119401.5-119401.29" switch \initial - attribute \src "libresoc.v:119605.9-119605.17" + attribute \src "libresoc.v:119401.9-119401.17" case 1'1 case end @@ -185874,14 +185670,14 @@ module \dec58 sync always update \dec58_sv_in1 $0\dec58_sv_in1[2:0] end - attribute \src "libresoc.v:119620.3-119635.6" - process $proc$libresoc.v:119620$4451 + attribute \src "libresoc.v:119416.3-119431.6" + process $proc$libresoc.v:119416$4451 assign { } { } assign { } { } assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:119621.5-119621.29" + attribute \src "libresoc.v:119417.5-119417.29" switch \initial - attribute \src "libresoc.v:119621.9-119621.17" + attribute \src "libresoc.v:119417.9-119417.17" case 1'1 case end @@ -185905,14 +185701,14 @@ module \dec58 sync always update \dec58_sv_in2 $0\dec58_sv_in2[2:0] end - attribute \src "libresoc.v:119636.3-119651.6" - process $proc$libresoc.v:119636$4452 + attribute \src "libresoc.v:119432.3-119447.6" + process $proc$libresoc.v:119432$4452 assign { } { } assign { } { } assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:119637.5-119637.29" + attribute \src "libresoc.v:119433.5-119433.29" switch \initial - attribute \src "libresoc.v:119637.9-119637.17" + attribute \src "libresoc.v:119433.9-119433.17" case 1'1 case end @@ -185936,14 +185732,14 @@ module \dec58 sync always update \dec58_sv_in3 $0\dec58_sv_in3[2:0] end - attribute \src "libresoc.v:119652.3-119667.6" - process $proc$libresoc.v:119652$4453 + attribute \src "libresoc.v:119448.3-119463.6" + process $proc$libresoc.v:119448$4453 assign { } { } assign { } { } assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:119653.5-119653.29" + attribute \src "libresoc.v:119449.5-119449.29" switch \initial - attribute \src "libresoc.v:119653.9-119653.17" + attribute \src "libresoc.v:119449.9-119449.17" case 1'1 case end @@ -185967,14 +185763,14 @@ module \dec58 sync always update \dec58_sv_out $0\dec58_sv_out[2:0] end - attribute \src "libresoc.v:119668.3-119683.6" - process $proc$libresoc.v:119668$4454 + attribute \src "libresoc.v:119464.3-119479.6" + process $proc$libresoc.v:119464$4454 assign { } { } assign { } { } assign $0\dec58_sv_out2[2:0] $1\dec58_sv_out2[2:0] - attribute \src "libresoc.v:119669.5-119669.29" + attribute \src "libresoc.v:119465.5-119465.29" switch \initial - attribute \src "libresoc.v:119669.9-119669.17" + attribute \src "libresoc.v:119465.9-119465.17" case 1'1 case end @@ -185998,14 +185794,14 @@ module \dec58 sync always update \dec58_sv_out2 $0\dec58_sv_out2[2:0] end - attribute \src "libresoc.v:119684.3-119699.6" - process $proc$libresoc.v:119684$4455 + attribute \src "libresoc.v:119480.3-119495.6" + process $proc$libresoc.v:119480$4455 assign { } { } assign { } { } assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:119685.5-119685.29" + attribute \src "libresoc.v:119481.5-119481.29" switch \initial - attribute \src "libresoc.v:119685.9-119685.17" + attribute \src "libresoc.v:119481.9-119481.17" case 1'1 case end @@ -186029,14 +185825,14 @@ module \dec58 sync always update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0] end - attribute \src "libresoc.v:119700.3-119715.6" - process $proc$libresoc.v:119700$4456 + attribute \src "libresoc.v:119496.3-119511.6" + process $proc$libresoc.v:119496$4456 assign { } { } assign { } { } assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:119701.5-119701.29" + attribute \src "libresoc.v:119497.5-119497.29" switch \initial - attribute \src "libresoc.v:119701.9-119701.17" + attribute \src "libresoc.v:119497.9-119497.17" case 1'1 case end @@ -186060,14 +185856,14 @@ module \dec58 sync always update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0] end - attribute \src "libresoc.v:119716.3-119731.6" - process $proc$libresoc.v:119716$4457 + attribute \src "libresoc.v:119512.3-119527.6" + process $proc$libresoc.v:119512$4457 assign { } { } assign { } { } assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:119717.5-119717.29" + attribute \src "libresoc.v:119513.5-119513.29" switch \initial - attribute \src "libresoc.v:119717.9-119717.17" + attribute \src "libresoc.v:119513.9-119513.17" case 1'1 case end @@ -186091,14 +185887,14 @@ module \dec58 sync always update \dec58_ldst_len $0\dec58_ldst_len[3:0] end - attribute \src "libresoc.v:119732.3-119747.6" - process $proc$libresoc.v:119732$4458 + attribute \src "libresoc.v:119528.3-119543.6" + process $proc$libresoc.v:119528$4458 assign { } { } assign { } { } assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:119733.5-119733.29" + attribute \src "libresoc.v:119529.5-119529.29" switch \initial - attribute \src "libresoc.v:119733.9-119733.17" + attribute \src "libresoc.v:119529.9-119529.17" case 1'1 case end @@ -186122,14 +185918,14 @@ module \dec58 sync always update \dec58_internal_op $0\dec58_internal_op[6:0] end - attribute \src "libresoc.v:119748.3-119763.6" - process $proc$libresoc.v:119748$4459 + attribute \src "libresoc.v:119544.3-119559.6" + process $proc$libresoc.v:119544$4459 assign { } { } assign { } { } assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:119749.5-119749.29" + attribute \src "libresoc.v:119545.5-119545.29" switch \initial - attribute \src "libresoc.v:119749.9-119749.17" + attribute \src "libresoc.v:119545.9-119545.17" case 1'1 case end @@ -186153,14 +185949,14 @@ module \dec58 sync always update \dec58_upd $0\dec58_upd[1:0] end - attribute \src "libresoc.v:119764.3-119779.6" - process $proc$libresoc.v:119764$4460 + attribute \src "libresoc.v:119560.3-119575.6" + process $proc$libresoc.v:119560$4460 assign { } { } assign { } { } assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:119765.5-119765.29" + attribute \src "libresoc.v:119561.5-119561.29" switch \initial - attribute \src "libresoc.v:119765.9-119765.17" + attribute \src "libresoc.v:119561.9-119561.17" case 1'1 case end @@ -186184,14 +185980,14 @@ module \dec58 sync always update \dec58_rc_sel $0\dec58_rc_sel[1:0] end - attribute \src "libresoc.v:119780.3-119795.6" - process $proc$libresoc.v:119780$4461 + attribute \src "libresoc.v:119576.3-119591.6" + process $proc$libresoc.v:119576$4461 assign { } { } assign { } { } assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:119781.5-119781.29" + attribute \src "libresoc.v:119577.5-119577.29" switch \initial - attribute \src "libresoc.v:119781.9-119781.17" + attribute \src "libresoc.v:119577.9-119577.17" case 1'1 case end @@ -186215,14 +186011,14 @@ module \dec58 sync always update \dec58_cry_in $0\dec58_cry_in[1:0] end - attribute \src "libresoc.v:119796.3-119811.6" - process $proc$libresoc.v:119796$4462 + attribute \src "libresoc.v:119592.3-119607.6" + process $proc$libresoc.v:119592$4462 assign { } { } assign { } { } assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:119797.5-119797.29" + attribute \src "libresoc.v:119593.5-119593.29" switch \initial - attribute \src "libresoc.v:119797.9-119797.17" + attribute \src "libresoc.v:119593.9-119593.17" case 1'1 case end @@ -186246,14 +186042,14 @@ module \dec58 sync always update \dec58_asmcode $0\dec58_asmcode[7:0] end - attribute \src "libresoc.v:119812.3-119827.6" - process $proc$libresoc.v:119812$4463 + attribute \src "libresoc.v:119608.3-119623.6" + process $proc$libresoc.v:119608$4463 assign { } { } assign { } { } assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:119813.5-119813.29" + attribute \src "libresoc.v:119609.5-119609.29" switch \initial - attribute \src "libresoc.v:119813.9-119813.17" + attribute \src "libresoc.v:119609.9-119609.17" case 1'1 case end @@ -186277,14 +186073,14 @@ module \dec58 sync always update \dec58_inv_a $0\dec58_inv_a[0:0] end - attribute \src "libresoc.v:119828.3-119843.6" - process $proc$libresoc.v:119828$4464 + attribute \src "libresoc.v:119624.3-119639.6" + process $proc$libresoc.v:119624$4464 assign { } { } assign { } { } assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:119829.5-119829.29" + attribute \src "libresoc.v:119625.5-119625.29" switch \initial - attribute \src "libresoc.v:119829.9-119829.17" + attribute \src "libresoc.v:119625.9-119625.17" case 1'1 case end @@ -186308,14 +186104,14 @@ module \dec58 sync always update \dec58_inv_out $0\dec58_inv_out[0:0] end - attribute \src "libresoc.v:119844.3-119859.6" - process $proc$libresoc.v:119844$4465 + attribute \src "libresoc.v:119640.3-119655.6" + process $proc$libresoc.v:119640$4465 assign { } { } assign { } { } assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:119845.5-119845.29" + attribute \src "libresoc.v:119641.5-119641.29" switch \initial - attribute \src "libresoc.v:119845.9-119845.17" + attribute \src "libresoc.v:119641.9-119641.17" case 1'1 case end @@ -186339,14 +186135,14 @@ module \dec58 sync always update \dec58_cry_out $0\dec58_cry_out[0:0] end - attribute \src "libresoc.v:119860.3-119875.6" - process $proc$libresoc.v:119860$4466 + attribute \src "libresoc.v:119656.3-119671.6" + process $proc$libresoc.v:119656$4466 assign { } { } assign { } { } assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:119861.5-119861.29" + attribute \src "libresoc.v:119657.5-119657.29" switch \initial - attribute \src "libresoc.v:119861.9-119861.17" + attribute \src "libresoc.v:119657.9-119657.17" case 1'1 case end @@ -186370,14 +186166,14 @@ module \dec58 sync always update \dec58_br $0\dec58_br[0:0] end - attribute \src "libresoc.v:119876.3-119891.6" - process $proc$libresoc.v:119876$4467 + attribute \src "libresoc.v:119672.3-119687.6" + process $proc$libresoc.v:119672$4467 assign { } { } assign { } { } assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:119877.5-119877.29" + attribute \src "libresoc.v:119673.5-119673.29" switch \initial - attribute \src "libresoc.v:119877.9-119877.17" + attribute \src "libresoc.v:119673.9-119673.17" case 1'1 case end @@ -186401,14 +186197,14 @@ module \dec58 sync always update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] end - attribute \src "libresoc.v:119892.3-119907.6" - process $proc$libresoc.v:119892$4468 + attribute \src "libresoc.v:119688.3-119703.6" + process $proc$libresoc.v:119688$4468 assign { } { } assign { } { } assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:119893.5-119893.29" + attribute \src "libresoc.v:119689.5-119689.29" switch \initial - attribute \src "libresoc.v:119893.9-119893.17" + attribute \src "libresoc.v:119689.9-119689.17" case 1'1 case end @@ -186432,14 +186228,14 @@ module \dec58 sync always update \dec58_rsrv $0\dec58_rsrv[0:0] end - attribute \src "libresoc.v:119908.3-119923.6" - process $proc$libresoc.v:119908$4469 + attribute \src "libresoc.v:119704.3-119719.6" + process $proc$libresoc.v:119704$4469 assign { } { } assign { } { } assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:119909.5-119909.29" + attribute \src "libresoc.v:119705.5-119705.29" switch \initial - attribute \src "libresoc.v:119909.9-119909.17" + attribute \src "libresoc.v:119705.9-119705.17" case 1'1 case end @@ -186463,14 +186259,14 @@ module \dec58 sync always update \dec58_form $0\dec58_form[4:0] end - attribute \src "libresoc.v:119924.3-119939.6" - process $proc$libresoc.v:119924$4470 + attribute \src "libresoc.v:119720.3-119735.6" + process $proc$libresoc.v:119720$4470 assign { } { } assign { } { } assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:119925.5-119925.29" + attribute \src "libresoc.v:119721.5-119721.29" switch \initial - attribute \src "libresoc.v:119925.9-119925.17" + attribute \src "libresoc.v:119721.9-119721.17" case 1'1 case end @@ -186494,14 +186290,14 @@ module \dec58 sync always update \dec58_is_32b $0\dec58_is_32b[0:0] end - attribute \src "libresoc.v:119940.3-119955.6" - process $proc$libresoc.v:119940$4471 + attribute \src "libresoc.v:119736.3-119751.6" + process $proc$libresoc.v:119736$4471 assign { } { } assign { } { } assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:119941.5-119941.29" + attribute \src "libresoc.v:119737.5-119737.29" switch \initial - attribute \src "libresoc.v:119941.9-119941.17" + attribute \src "libresoc.v:119737.9-119737.17" case 1'1 case end @@ -186525,14 +186321,14 @@ module \dec58 sync always update \dec58_sgn $0\dec58_sgn[0:0] end - attribute \src "libresoc.v:119956.3-119971.6" - process $proc$libresoc.v:119956$4472 + attribute \src "libresoc.v:119752.3-119767.6" + process $proc$libresoc.v:119752$4472 assign { } { } assign { } { } assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:119957.5-119957.29" + attribute \src "libresoc.v:119753.5-119753.29" switch \initial - attribute \src "libresoc.v:119957.9-119957.17" + attribute \src "libresoc.v:119753.9-119753.17" case 1'1 case end @@ -186556,14 +186352,14 @@ module \dec58 sync always update \dec58_lk $0\dec58_lk[0:0] end - attribute \src "libresoc.v:119972.3-119987.6" - process $proc$libresoc.v:119972$4473 + attribute \src "libresoc.v:119768.3-119783.6" + process $proc$libresoc.v:119768$4473 assign { } { } assign { } { } assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:119973.5-119973.29" + attribute \src "libresoc.v:119769.5-119769.29" switch \initial - attribute \src "libresoc.v:119973.9-119973.17" + attribute \src "libresoc.v:119769.9-119769.17" case 1'1 case end @@ -186587,14 +186383,14 @@ module \dec58 sync always update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] end - attribute \src "libresoc.v:119988.3-120003.6" - process $proc$libresoc.v:119988$4474 + attribute \src "libresoc.v:119784.3-119799.6" + process $proc$libresoc.v:119784$4474 assign { } { } assign { } { } assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:119989.5-119989.29" + attribute \src "libresoc.v:119785.5-119785.29" switch \initial - attribute \src "libresoc.v:119989.9-119989.17" + attribute \src "libresoc.v:119785.9-119785.17" case 1'1 case end @@ -186618,14 +186414,14 @@ module \dec58 sync always update \dec58_SV_Etype $0\dec58_SV_Etype[1:0] end - attribute \src "libresoc.v:120004.3-120019.6" - process $proc$libresoc.v:120004$4475 + attribute \src "libresoc.v:119800.3-119815.6" + process $proc$libresoc.v:119800$4475 assign { } { } assign { } { } assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:120005.5-120005.29" + attribute \src "libresoc.v:119801.5-119801.29" switch \initial - attribute \src "libresoc.v:120005.9-120005.17" + attribute \src "libresoc.v:119801.9-119801.17" case 1'1 case end @@ -186649,14 +186445,14 @@ module \dec58 sync always update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0] end - attribute \src "libresoc.v:120020.3-120035.6" - process $proc$libresoc.v:120020$4476 + attribute \src "libresoc.v:119816.3-119831.6" + process $proc$libresoc.v:119816$4476 assign { } { } assign { } { } assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:120021.5-120021.29" + attribute \src "libresoc.v:119817.5-119817.29" switch \initial - attribute \src "libresoc.v:120021.9-120021.17" + attribute \src "libresoc.v:119817.9-119817.17" case 1'1 case end @@ -186680,14 +186476,14 @@ module \dec58 sync always update \dec58_in1_sel $0\dec58_in1_sel[2:0] end - attribute \src "libresoc.v:120036.3-120051.6" - process $proc$libresoc.v:120036$4477 + attribute \src "libresoc.v:119832.3-119847.6" + process $proc$libresoc.v:119832$4477 assign { } { } assign { } { } assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:120037.5-120037.29" + attribute \src "libresoc.v:119833.5-119833.29" switch \initial - attribute \src "libresoc.v:120037.9-120037.17" + attribute \src "libresoc.v:119833.9-119833.17" case 1'1 case end @@ -186711,14 +186507,14 @@ module \dec58 sync always update \dec58_in2_sel $0\dec58_in2_sel[3:0] end - attribute \src "libresoc.v:120052.3-120067.6" - process $proc$libresoc.v:120052$4478 + attribute \src "libresoc.v:119848.3-119863.6" + process $proc$libresoc.v:119848$4478 assign { } { } assign { } { } assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:120053.5-120053.29" + attribute \src "libresoc.v:119849.5-119849.29" switch \initial - attribute \src "libresoc.v:120053.9-120053.17" + attribute \src "libresoc.v:119849.9-119849.17" case 1'1 case end @@ -186742,14 +186538,14 @@ module \dec58 sync always update \dec58_in3_sel $0\dec58_in3_sel[1:0] end - attribute \src "libresoc.v:120068.3-120083.6" - process $proc$libresoc.v:120068$4479 + attribute \src "libresoc.v:119864.3-119879.6" + process $proc$libresoc.v:119864$4479 assign { } { } assign { } { } assign $0\dec58_out_sel[2:0] $1\dec58_out_sel[2:0] - attribute \src "libresoc.v:120069.5-120069.29" + attribute \src "libresoc.v:119865.5-119865.29" switch \initial - attribute \src "libresoc.v:120069.9-120069.17" + attribute \src "libresoc.v:119865.9-119865.17" case 1'1 case end @@ -186775,144 +186571,144 @@ module \dec58 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:120089.1-120868.10" +attribute \src "libresoc.v:119885.1-120664.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" attribute \generator "nMigen" module \dec62 - attribute \src "libresoc.v:120789.3-120801.6" + attribute \src "libresoc.v:120585.3-120597.6" wire width 2 $0\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:120802.3-120814.6" + attribute \src "libresoc.v:120598.3-120610.6" wire width 2 $0\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:120633.3-120645.6" + attribute \src "libresoc.v:120429.3-120441.6" wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:120685.3-120697.6" + attribute \src "libresoc.v:120481.3-120493.6" wire $0\dec62_br[0:0] - attribute \src "libresoc.v:120451.3-120463.6" + attribute \src "libresoc.v:120247.3-120259.6" wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:120464.3-120476.6" + attribute \src "libresoc.v:120260.3-120272.6" wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:120620.3-120632.6" + attribute \src "libresoc.v:120416.3-120428.6" wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:120672.3-120684.6" + attribute \src "libresoc.v:120468.3-120480.6" wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:120724.3-120736.6" + attribute \src "libresoc.v:120520.3-120532.6" wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:120438.3-120450.6" + attribute \src "libresoc.v:120234.3-120246.6" wire width 14 $0\dec62_function_unit[13:0] - attribute \src "libresoc.v:120815.3-120827.6" + attribute \src "libresoc.v:120611.3-120623.6" wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:120828.3-120840.6" + attribute \src "libresoc.v:120624.3-120636.6" wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:120841.3-120853.6" + attribute \src "libresoc.v:120637.3-120649.6" wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:120581.3-120593.6" + attribute \src "libresoc.v:120377.3-120389.6" wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:120646.3-120658.6" + attribute \src "libresoc.v:120442.3-120454.6" wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:120659.3-120671.6" + attribute \src "libresoc.v:120455.3-120467.6" wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:120737.3-120749.6" + attribute \src "libresoc.v:120533.3-120545.6" wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:120568.3-120580.6" + attribute \src "libresoc.v:120364.3-120376.6" wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:120763.3-120775.6" + attribute \src "libresoc.v:120559.3-120571.6" wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:120854.3-120866.6" + attribute \src "libresoc.v:120650.3-120662.6" wire width 3 $0\dec62_out_sel[2:0] - attribute \src "libresoc.v:120607.3-120619.6" + attribute \src "libresoc.v:120403.3-120415.6" wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:120711.3-120723.6" + attribute \src "libresoc.v:120507.3-120519.6" wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:120776.3-120788.6" + attribute \src "libresoc.v:120572.3-120584.6" wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:120750.3-120762.6" + attribute \src "libresoc.v:120546.3-120558.6" wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:120698.3-120710.6" + attribute \src "libresoc.v:120494.3-120506.6" wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:120542.3-120554.6" + attribute \src "libresoc.v:120338.3-120350.6" wire width 3 $0\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:120555.3-120567.6" + attribute \src "libresoc.v:120351.3-120363.6" wire width 3 $0\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:120477.3-120489.6" + attribute \src "libresoc.v:120273.3-120285.6" wire width 3 $0\dec62_sv_in1[2:0] - attribute \src "libresoc.v:120490.3-120502.6" + attribute \src "libresoc.v:120286.3-120298.6" wire width 3 $0\dec62_sv_in2[2:0] - attribute \src "libresoc.v:120503.3-120515.6" + attribute \src "libresoc.v:120299.3-120311.6" wire width 3 $0\dec62_sv_in3[2:0] - attribute \src "libresoc.v:120529.3-120541.6" + attribute \src "libresoc.v:120325.3-120337.6" wire width 3 $0\dec62_sv_out2[2:0] - attribute \src "libresoc.v:120516.3-120528.6" + attribute \src "libresoc.v:120312.3-120324.6" wire width 3 $0\dec62_sv_out[2:0] - attribute \src "libresoc.v:120594.3-120606.6" + attribute \src "libresoc.v:120390.3-120402.6" wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:120090.7-120090.20" + attribute \src "libresoc.v:119886.7-119886.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120789.3-120801.6" + attribute \src "libresoc.v:120585.3-120597.6" wire width 2 $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:120802.3-120814.6" + attribute \src "libresoc.v:120598.3-120610.6" wire width 2 $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:120633.3-120645.6" + attribute \src "libresoc.v:120429.3-120441.6" wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:120685.3-120697.6" + attribute \src "libresoc.v:120481.3-120493.6" wire $1\dec62_br[0:0] - attribute \src "libresoc.v:120451.3-120463.6" + attribute \src "libresoc.v:120247.3-120259.6" wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:120464.3-120476.6" + attribute \src "libresoc.v:120260.3-120272.6" wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:120620.3-120632.6" + attribute \src "libresoc.v:120416.3-120428.6" wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:120672.3-120684.6" + attribute \src "libresoc.v:120468.3-120480.6" wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:120724.3-120736.6" + attribute \src "libresoc.v:120520.3-120532.6" wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:120438.3-120450.6" + attribute \src "libresoc.v:120234.3-120246.6" wire width 14 $1\dec62_function_unit[13:0] - attribute \src "libresoc.v:120815.3-120827.6" + attribute \src "libresoc.v:120611.3-120623.6" wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:120828.3-120840.6" + attribute \src "libresoc.v:120624.3-120636.6" wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:120841.3-120853.6" + attribute \src "libresoc.v:120637.3-120649.6" wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:120581.3-120593.6" + attribute \src "libresoc.v:120377.3-120389.6" wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:120646.3-120658.6" + attribute \src "libresoc.v:120442.3-120454.6" wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:120659.3-120671.6" + attribute \src "libresoc.v:120455.3-120467.6" wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:120737.3-120749.6" + attribute \src "libresoc.v:120533.3-120545.6" wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:120568.3-120580.6" + attribute \src "libresoc.v:120364.3-120376.6" wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:120763.3-120775.6" + attribute \src "libresoc.v:120559.3-120571.6" wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:120854.3-120866.6" + attribute \src "libresoc.v:120650.3-120662.6" wire width 3 $1\dec62_out_sel[2:0] - attribute \src "libresoc.v:120607.3-120619.6" + attribute \src "libresoc.v:120403.3-120415.6" wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:120711.3-120723.6" + attribute \src "libresoc.v:120507.3-120519.6" wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:120776.3-120788.6" + attribute \src "libresoc.v:120572.3-120584.6" wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:120750.3-120762.6" + attribute \src "libresoc.v:120546.3-120558.6" wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:120698.3-120710.6" + attribute \src "libresoc.v:120494.3-120506.6" wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:120542.3-120554.6" + attribute \src "libresoc.v:120338.3-120350.6" wire width 3 $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:120555.3-120567.6" + attribute \src "libresoc.v:120351.3-120363.6" wire width 3 $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:120477.3-120489.6" + attribute \src "libresoc.v:120273.3-120285.6" wire width 3 $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:120490.3-120502.6" + attribute \src "libresoc.v:120286.3-120298.6" wire width 3 $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:120503.3-120515.6" + attribute \src "libresoc.v:120299.3-120311.6" wire width 3 $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:120529.3-120541.6" + attribute \src "libresoc.v:120325.3-120337.6" wire width 3 $1\dec62_sv_out2[2:0] - attribute \src "libresoc.v:120516.3-120528.6" + attribute \src "libresoc.v:120312.3-120324.6" wire width 3 $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:120594.3-120606.6" + attribute \src "libresoc.v:120390.3-120402.6" wire width 2 $1\dec62_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -187224,28 +187020,28 @@ module \dec62 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec62_upd - attribute \src "libresoc.v:120090.7-120090.15" + attribute \src "libresoc.v:119886.7-119886.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch - attribute \src "libresoc.v:120090.7-120090.20" - process $proc$libresoc.v:120090$4514 + attribute \src "libresoc.v:119886.7-119886.20" + process $proc$libresoc.v:119886$4514 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120438.3-120450.6" - process $proc$libresoc.v:120438$4481 + attribute \src "libresoc.v:120234.3-120246.6" + process $proc$libresoc.v:120234$4481 assign { } { } assign { } { } assign $0\dec62_function_unit[13:0] $1\dec62_function_unit[13:0] - attribute \src "libresoc.v:120439.5-120439.29" + attribute \src "libresoc.v:120235.5-120235.29" switch \initial - attribute \src "libresoc.v:120439.9-120439.17" + attribute \src "libresoc.v:120235.9-120235.17" case 1'1 case end @@ -187265,14 +187061,14 @@ module \dec62 sync always update \dec62_function_unit $0\dec62_function_unit[13:0] end - attribute \src "libresoc.v:120451.3-120463.6" - process $proc$libresoc.v:120451$4482 + attribute \src "libresoc.v:120247.3-120259.6" + process $proc$libresoc.v:120247$4482 assign { } { } assign { } { } assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:120452.5-120452.29" + attribute \src "libresoc.v:120248.5-120248.29" switch \initial - attribute \src "libresoc.v:120452.9-120452.17" + attribute \src "libresoc.v:120248.9-120248.17" case 1'1 case end @@ -187292,14 +187088,14 @@ module \dec62 sync always update \dec62_cr_in $0\dec62_cr_in[2:0] end - attribute \src "libresoc.v:120464.3-120476.6" - process $proc$libresoc.v:120464$4483 + attribute \src "libresoc.v:120260.3-120272.6" + process $proc$libresoc.v:120260$4483 assign { } { } assign { } { } assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:120465.5-120465.29" + attribute \src "libresoc.v:120261.5-120261.29" switch \initial - attribute \src "libresoc.v:120465.9-120465.17" + attribute \src "libresoc.v:120261.9-120261.17" case 1'1 case end @@ -187319,14 +187115,14 @@ module \dec62 sync always update \dec62_cr_out $0\dec62_cr_out[2:0] end - attribute \src "libresoc.v:120477.3-120489.6" - process $proc$libresoc.v:120477$4484 + attribute \src "libresoc.v:120273.3-120285.6" + process $proc$libresoc.v:120273$4484 assign { } { } assign { } { } assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:120478.5-120478.29" + attribute \src "libresoc.v:120274.5-120274.29" switch \initial - attribute \src "libresoc.v:120478.9-120478.17" + attribute \src "libresoc.v:120274.9-120274.17" case 1'1 case end @@ -187346,14 +187142,14 @@ module \dec62 sync always update \dec62_sv_in1 $0\dec62_sv_in1[2:0] end - attribute \src "libresoc.v:120490.3-120502.6" - process $proc$libresoc.v:120490$4485 + attribute \src "libresoc.v:120286.3-120298.6" + process $proc$libresoc.v:120286$4485 assign { } { } assign { } { } assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:120491.5-120491.29" + attribute \src "libresoc.v:120287.5-120287.29" switch \initial - attribute \src "libresoc.v:120491.9-120491.17" + attribute \src "libresoc.v:120287.9-120287.17" case 1'1 case end @@ -187373,14 +187169,14 @@ module \dec62 sync always update \dec62_sv_in2 $0\dec62_sv_in2[2:0] end - attribute \src "libresoc.v:120503.3-120515.6" - process $proc$libresoc.v:120503$4486 + attribute \src "libresoc.v:120299.3-120311.6" + process $proc$libresoc.v:120299$4486 assign { } { } assign { } { } assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:120504.5-120504.29" + attribute \src "libresoc.v:120300.5-120300.29" switch \initial - attribute \src "libresoc.v:120504.9-120504.17" + attribute \src "libresoc.v:120300.9-120300.17" case 1'1 case end @@ -187400,14 +187196,14 @@ module \dec62 sync always update \dec62_sv_in3 $0\dec62_sv_in3[2:0] end - attribute \src "libresoc.v:120516.3-120528.6" - process $proc$libresoc.v:120516$4487 + attribute \src "libresoc.v:120312.3-120324.6" + process $proc$libresoc.v:120312$4487 assign { } { } assign { } { } assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:120517.5-120517.29" + attribute \src "libresoc.v:120313.5-120313.29" switch \initial - attribute \src "libresoc.v:120517.9-120517.17" + attribute \src "libresoc.v:120313.9-120313.17" case 1'1 case end @@ -187427,14 +187223,14 @@ module \dec62 sync always update \dec62_sv_out $0\dec62_sv_out[2:0] end - attribute \src "libresoc.v:120529.3-120541.6" - process $proc$libresoc.v:120529$4488 + attribute \src "libresoc.v:120325.3-120337.6" + process $proc$libresoc.v:120325$4488 assign { } { } assign { } { } assign $0\dec62_sv_out2[2:0] $1\dec62_sv_out2[2:0] - attribute \src "libresoc.v:120530.5-120530.29" + attribute \src "libresoc.v:120326.5-120326.29" switch \initial - attribute \src "libresoc.v:120530.9-120530.17" + attribute \src "libresoc.v:120326.9-120326.17" case 1'1 case end @@ -187454,14 +187250,14 @@ module \dec62 sync always update \dec62_sv_out2 $0\dec62_sv_out2[2:0] end - attribute \src "libresoc.v:120542.3-120554.6" - process $proc$libresoc.v:120542$4489 + attribute \src "libresoc.v:120338.3-120350.6" + process $proc$libresoc.v:120338$4489 assign { } { } assign { } { } assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:120543.5-120543.29" + attribute \src "libresoc.v:120339.5-120339.29" switch \initial - attribute \src "libresoc.v:120543.9-120543.17" + attribute \src "libresoc.v:120339.9-120339.17" case 1'1 case end @@ -187481,14 +187277,14 @@ module \dec62 sync always update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0] end - attribute \src "libresoc.v:120555.3-120567.6" - process $proc$libresoc.v:120555$4490 + attribute \src "libresoc.v:120351.3-120363.6" + process $proc$libresoc.v:120351$4490 assign { } { } assign { } { } assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:120556.5-120556.29" + attribute \src "libresoc.v:120352.5-120352.29" switch \initial - attribute \src "libresoc.v:120556.9-120556.17" + attribute \src "libresoc.v:120352.9-120352.17" case 1'1 case end @@ -187508,14 +187304,14 @@ module \dec62 sync always update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0] end - attribute \src "libresoc.v:120568.3-120580.6" - process $proc$libresoc.v:120568$4491 + attribute \src "libresoc.v:120364.3-120376.6" + process $proc$libresoc.v:120364$4491 assign { } { } assign { } { } assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:120569.5-120569.29" + attribute \src "libresoc.v:120365.5-120365.29" switch \initial - attribute \src "libresoc.v:120569.9-120569.17" + attribute \src "libresoc.v:120365.9-120365.17" case 1'1 case end @@ -187535,14 +187331,14 @@ module \dec62 sync always update \dec62_ldst_len $0\dec62_ldst_len[3:0] end - attribute \src "libresoc.v:120581.3-120593.6" - process $proc$libresoc.v:120581$4492 + attribute \src "libresoc.v:120377.3-120389.6" + process $proc$libresoc.v:120377$4492 assign { } { } assign { } { } assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:120582.5-120582.29" + attribute \src "libresoc.v:120378.5-120378.29" switch \initial - attribute \src "libresoc.v:120582.9-120582.17" + attribute \src "libresoc.v:120378.9-120378.17" case 1'1 case end @@ -187562,14 +187358,14 @@ module \dec62 sync always update \dec62_internal_op $0\dec62_internal_op[6:0] end - attribute \src "libresoc.v:120594.3-120606.6" - process $proc$libresoc.v:120594$4493 + attribute \src "libresoc.v:120390.3-120402.6" + process $proc$libresoc.v:120390$4493 assign { } { } assign { } { } assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:120595.5-120595.29" + attribute \src "libresoc.v:120391.5-120391.29" switch \initial - attribute \src "libresoc.v:120595.9-120595.17" + attribute \src "libresoc.v:120391.9-120391.17" case 1'1 case end @@ -187589,14 +187385,14 @@ module \dec62 sync always update \dec62_upd $0\dec62_upd[1:0] end - attribute \src "libresoc.v:120607.3-120619.6" - process $proc$libresoc.v:120607$4494 + attribute \src "libresoc.v:120403.3-120415.6" + process $proc$libresoc.v:120403$4494 assign { } { } assign { } { } assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:120608.5-120608.29" + attribute \src "libresoc.v:120404.5-120404.29" switch \initial - attribute \src "libresoc.v:120608.9-120608.17" + attribute \src "libresoc.v:120404.9-120404.17" case 1'1 case end @@ -187616,14 +187412,14 @@ module \dec62 sync always update \dec62_rc_sel $0\dec62_rc_sel[1:0] end - attribute \src "libresoc.v:120620.3-120632.6" - process $proc$libresoc.v:120620$4495 + attribute \src "libresoc.v:120416.3-120428.6" + process $proc$libresoc.v:120416$4495 assign { } { } assign { } { } assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:120621.5-120621.29" + attribute \src "libresoc.v:120417.5-120417.29" switch \initial - attribute \src "libresoc.v:120621.9-120621.17" + attribute \src "libresoc.v:120417.9-120417.17" case 1'1 case end @@ -187643,14 +187439,14 @@ module \dec62 sync always update \dec62_cry_in $0\dec62_cry_in[1:0] end - attribute \src "libresoc.v:120633.3-120645.6" - process $proc$libresoc.v:120633$4496 + attribute \src "libresoc.v:120429.3-120441.6" + process $proc$libresoc.v:120429$4496 assign { } { } assign { } { } assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:120634.5-120634.29" + attribute \src "libresoc.v:120430.5-120430.29" switch \initial - attribute \src "libresoc.v:120634.9-120634.17" + attribute \src "libresoc.v:120430.9-120430.17" case 1'1 case end @@ -187670,14 +187466,14 @@ module \dec62 sync always update \dec62_asmcode $0\dec62_asmcode[7:0] end - attribute \src "libresoc.v:120646.3-120658.6" - process $proc$libresoc.v:120646$4497 + attribute \src "libresoc.v:120442.3-120454.6" + process $proc$libresoc.v:120442$4497 assign { } { } assign { } { } assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:120647.5-120647.29" + attribute \src "libresoc.v:120443.5-120443.29" switch \initial - attribute \src "libresoc.v:120647.9-120647.17" + attribute \src "libresoc.v:120443.9-120443.17" case 1'1 case end @@ -187697,14 +187493,14 @@ module \dec62 sync always update \dec62_inv_a $0\dec62_inv_a[0:0] end - attribute \src "libresoc.v:120659.3-120671.6" - process $proc$libresoc.v:120659$4498 + attribute \src "libresoc.v:120455.3-120467.6" + process $proc$libresoc.v:120455$4498 assign { } { } assign { } { } assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:120660.5-120660.29" + attribute \src "libresoc.v:120456.5-120456.29" switch \initial - attribute \src "libresoc.v:120660.9-120660.17" + attribute \src "libresoc.v:120456.9-120456.17" case 1'1 case end @@ -187724,14 +187520,14 @@ module \dec62 sync always update \dec62_inv_out $0\dec62_inv_out[0:0] end - attribute \src "libresoc.v:120672.3-120684.6" - process $proc$libresoc.v:120672$4499 + attribute \src "libresoc.v:120468.3-120480.6" + process $proc$libresoc.v:120468$4499 assign { } { } assign { } { } assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:120673.5-120673.29" + attribute \src "libresoc.v:120469.5-120469.29" switch \initial - attribute \src "libresoc.v:120673.9-120673.17" + attribute \src "libresoc.v:120469.9-120469.17" case 1'1 case end @@ -187751,14 +187547,14 @@ module \dec62 sync always update \dec62_cry_out $0\dec62_cry_out[0:0] end - attribute \src "libresoc.v:120685.3-120697.6" - process $proc$libresoc.v:120685$4500 + attribute \src "libresoc.v:120481.3-120493.6" + process $proc$libresoc.v:120481$4500 assign { } { } assign { } { } assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:120686.5-120686.29" + attribute \src "libresoc.v:120482.5-120482.29" switch \initial - attribute \src "libresoc.v:120686.9-120686.17" + attribute \src "libresoc.v:120482.9-120482.17" case 1'1 case end @@ -187778,14 +187574,14 @@ module \dec62 sync always update \dec62_br $0\dec62_br[0:0] end - attribute \src "libresoc.v:120698.3-120710.6" - process $proc$libresoc.v:120698$4501 + attribute \src "libresoc.v:120494.3-120506.6" + process $proc$libresoc.v:120494$4501 assign { } { } assign { } { } assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:120699.5-120699.29" + attribute \src "libresoc.v:120495.5-120495.29" switch \initial - attribute \src "libresoc.v:120699.9-120699.17" + attribute \src "libresoc.v:120495.9-120495.17" case 1'1 case end @@ -187805,14 +187601,14 @@ module \dec62 sync always update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] end - attribute \src "libresoc.v:120711.3-120723.6" - process $proc$libresoc.v:120711$4502 + attribute \src "libresoc.v:120507.3-120519.6" + process $proc$libresoc.v:120507$4502 assign { } { } assign { } { } assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:120712.5-120712.29" + attribute \src "libresoc.v:120508.5-120508.29" switch \initial - attribute \src "libresoc.v:120712.9-120712.17" + attribute \src "libresoc.v:120508.9-120508.17" case 1'1 case end @@ -187832,14 +187628,14 @@ module \dec62 sync always update \dec62_rsrv $0\dec62_rsrv[0:0] end - attribute \src "libresoc.v:120724.3-120736.6" - process $proc$libresoc.v:120724$4503 + attribute \src "libresoc.v:120520.3-120532.6" + process $proc$libresoc.v:120520$4503 assign { } { } assign { } { } assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:120725.5-120725.29" + attribute \src "libresoc.v:120521.5-120521.29" switch \initial - attribute \src "libresoc.v:120725.9-120725.17" + attribute \src "libresoc.v:120521.9-120521.17" case 1'1 case end @@ -187859,14 +187655,14 @@ module \dec62 sync always update \dec62_form $0\dec62_form[4:0] end - attribute \src "libresoc.v:120737.3-120749.6" - process $proc$libresoc.v:120737$4504 + attribute \src "libresoc.v:120533.3-120545.6" + process $proc$libresoc.v:120533$4504 assign { } { } assign { } { } assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:120738.5-120738.29" + attribute \src "libresoc.v:120534.5-120534.29" switch \initial - attribute \src "libresoc.v:120738.9-120738.17" + attribute \src "libresoc.v:120534.9-120534.17" case 1'1 case end @@ -187886,14 +187682,14 @@ module \dec62 sync always update \dec62_is_32b $0\dec62_is_32b[0:0] end - attribute \src "libresoc.v:120750.3-120762.6" - process $proc$libresoc.v:120750$4505 + attribute \src "libresoc.v:120546.3-120558.6" + process $proc$libresoc.v:120546$4505 assign { } { } assign { } { } assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:120751.5-120751.29" + attribute \src "libresoc.v:120547.5-120547.29" switch \initial - attribute \src "libresoc.v:120751.9-120751.17" + attribute \src "libresoc.v:120547.9-120547.17" case 1'1 case end @@ -187913,14 +187709,14 @@ module \dec62 sync always update \dec62_sgn $0\dec62_sgn[0:0] end - attribute \src "libresoc.v:120763.3-120775.6" - process $proc$libresoc.v:120763$4506 + attribute \src "libresoc.v:120559.3-120571.6" + process $proc$libresoc.v:120559$4506 assign { } { } assign { } { } assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:120764.5-120764.29" + attribute \src "libresoc.v:120560.5-120560.29" switch \initial - attribute \src "libresoc.v:120764.9-120764.17" + attribute \src "libresoc.v:120560.9-120560.17" case 1'1 case end @@ -187940,14 +187736,14 @@ module \dec62 sync always update \dec62_lk $0\dec62_lk[0:0] end - attribute \src "libresoc.v:120776.3-120788.6" - process $proc$libresoc.v:120776$4507 + attribute \src "libresoc.v:120572.3-120584.6" + process $proc$libresoc.v:120572$4507 assign { } { } assign { } { } assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:120777.5-120777.29" + attribute \src "libresoc.v:120573.5-120573.29" switch \initial - attribute \src "libresoc.v:120777.9-120777.17" + attribute \src "libresoc.v:120573.9-120573.17" case 1'1 case end @@ -187967,14 +187763,14 @@ module \dec62 sync always update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] end - attribute \src "libresoc.v:120789.3-120801.6" - process $proc$libresoc.v:120789$4508 + attribute \src "libresoc.v:120585.3-120597.6" + process $proc$libresoc.v:120585$4508 assign { } { } assign { } { } assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:120790.5-120790.29" + attribute \src "libresoc.v:120586.5-120586.29" switch \initial - attribute \src "libresoc.v:120790.9-120790.17" + attribute \src "libresoc.v:120586.9-120586.17" case 1'1 case end @@ -187994,14 +187790,14 @@ module \dec62 sync always update \dec62_SV_Etype $0\dec62_SV_Etype[1:0] end - attribute \src "libresoc.v:120802.3-120814.6" - process $proc$libresoc.v:120802$4509 + attribute \src "libresoc.v:120598.3-120610.6" + process $proc$libresoc.v:120598$4509 assign { } { } assign { } { } assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:120803.5-120803.29" + attribute \src "libresoc.v:120599.5-120599.29" switch \initial - attribute \src "libresoc.v:120803.9-120803.17" + attribute \src "libresoc.v:120599.9-120599.17" case 1'1 case end @@ -188021,14 +187817,14 @@ module \dec62 sync always update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0] end - attribute \src "libresoc.v:120815.3-120827.6" - process $proc$libresoc.v:120815$4510 + attribute \src "libresoc.v:120611.3-120623.6" + process $proc$libresoc.v:120611$4510 assign { } { } assign { } { } assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:120816.5-120816.29" + attribute \src "libresoc.v:120612.5-120612.29" switch \initial - attribute \src "libresoc.v:120816.9-120816.17" + attribute \src "libresoc.v:120612.9-120612.17" case 1'1 case end @@ -188048,14 +187844,14 @@ module \dec62 sync always update \dec62_in1_sel $0\dec62_in1_sel[2:0] end - attribute \src "libresoc.v:120828.3-120840.6" - process $proc$libresoc.v:120828$4511 + attribute \src "libresoc.v:120624.3-120636.6" + process $proc$libresoc.v:120624$4511 assign { } { } assign { } { } assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:120829.5-120829.29" + attribute \src "libresoc.v:120625.5-120625.29" switch \initial - attribute \src "libresoc.v:120829.9-120829.17" + attribute \src "libresoc.v:120625.9-120625.17" case 1'1 case end @@ -188075,14 +187871,14 @@ module \dec62 sync always update \dec62_in2_sel $0\dec62_in2_sel[3:0] end - attribute \src "libresoc.v:120841.3-120853.6" - process $proc$libresoc.v:120841$4512 + attribute \src "libresoc.v:120637.3-120649.6" + process $proc$libresoc.v:120637$4512 assign { } { } assign { } { } assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:120842.5-120842.29" + attribute \src "libresoc.v:120638.5-120638.29" switch \initial - attribute \src "libresoc.v:120842.9-120842.17" + attribute \src "libresoc.v:120638.9-120638.17" case 1'1 case end @@ -188102,14 +187898,14 @@ module \dec62 sync always update \dec62_in3_sel $0\dec62_in3_sel[1:0] end - attribute \src "libresoc.v:120854.3-120866.6" - process $proc$libresoc.v:120854$4513 + attribute \src "libresoc.v:120650.3-120662.6" + process $proc$libresoc.v:120650$4513 assign { } { } assign { } { } assign $0\dec62_out_sel[2:0] $1\dec62_out_sel[2:0] - attribute \src "libresoc.v:120855.5-120855.29" + attribute \src "libresoc.v:120651.5-120651.29" switch \initial - attribute \src "libresoc.v:120855.9-120855.17" + attribute \src "libresoc.v:120651.9-120651.17" case 1'1 case end @@ -188131,73 +187927,73 @@ module \dec62 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:120872.1-121455.10" +attribute \src "libresoc.v:120668.1-121251.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" attribute \generator "nMigen" module \dec_ALU - attribute \src "libresoc.v:121418.3-121432.6" + attribute \src "libresoc.v:121214.3-121228.6" wire width 14 $0\ALU__fn_unit[13:0] - attribute \src "libresoc.v:121405.3-121417.6" + attribute \src "libresoc.v:121201.3-121213.6" wire width 7 $0\ALU__insn_type[6:0] - attribute \src "libresoc.v:121390.3-121404.6" + attribute \src "libresoc.v:121186.3-121200.6" wire $0\ALU__write_cr0[0:0] - attribute \src "libresoc.v:120873.7-120873.20" + attribute \src "libresoc.v:120669.7-120669.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121418.3-121432.6" + attribute \src "libresoc.v:121214.3-121228.6" wire width 14 $1\ALU__fn_unit[13:0] - attribute \src "libresoc.v:121405.3-121417.6" + attribute \src "libresoc.v:121201.3-121213.6" wire width 7 $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:121390.3-121404.6" + attribute \src "libresoc.v:121186.3-121200.6" wire $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:121306.18-121306.113" - wire $and$libresoc.v:121306$4515_Y - attribute \src "libresoc.v:121308.18-121308.110" - wire $and$libresoc.v:121308$4517_Y - attribute \src "libresoc.v:121321.18-121321.114" - wire $and$libresoc.v:121321$4530_Y - attribute \src "libresoc.v:121322.18-121322.116" - wire $and$libresoc.v:121322$4531_Y - attribute \src "libresoc.v:121324.18-121324.114" - wire $and$libresoc.v:121324$4533_Y - attribute \src "libresoc.v:121326.18-121326.110" - wire $and$libresoc.v:121326$4535_Y - attribute \src "libresoc.v:121327.17-121327.112" - wire $and$libresoc.v:121327$4536_Y - attribute \src "libresoc.v:121328.17-121328.114" - wire $and$libresoc.v:121328$4537_Y - attribute \src "libresoc.v:121309.18-121309.126" - wire $eq$libresoc.v:121309$4518_Y - attribute \src "libresoc.v:121310.18-121310.126" - wire $eq$libresoc.v:121310$4519_Y - attribute \src "libresoc.v:121312.18-121312.110" - wire $eq$libresoc.v:121312$4521_Y - attribute \src "libresoc.v:121313.18-121313.110" - wire $eq$libresoc.v:121313$4522_Y - attribute \src "libresoc.v:121315.18-121315.112" - wire $eq$libresoc.v:121315$4524_Y - attribute \src "libresoc.v:121316.17-121316.130" - wire $eq$libresoc.v:121316$4525_Y - attribute \src "libresoc.v:121318.18-121318.110" - wire $eq$libresoc.v:121318$4527_Y - attribute \src "libresoc.v:121320.18-121320.131" - wire $eq$libresoc.v:121320$4529_Y - attribute \src "libresoc.v:121323.18-121323.131" - wire $eq$libresoc.v:121323$4532_Y - attribute \src "libresoc.v:121329.17-121329.130" - wire $eq$libresoc.v:121329$4538_Y - attribute \src "libresoc.v:121307.18-121307.110" - wire $not$libresoc.v:121307$4516_Y - attribute \src "libresoc.v:121325.18-121325.110" - wire $not$libresoc.v:121325$4534_Y - attribute \src "libresoc.v:121311.18-121311.110" - wire $or$libresoc.v:121311$4520_Y - attribute \src "libresoc.v:121314.18-121314.110" - wire $or$libresoc.v:121314$4523_Y - attribute \src "libresoc.v:121317.18-121317.110" - wire $or$libresoc.v:121317$4526_Y - attribute \src "libresoc.v:121319.18-121319.110" - wire $or$libresoc.v:121319$4528_Y + attribute \src "libresoc.v:121102.18-121102.113" + wire $and$libresoc.v:121102$4515_Y + attribute \src "libresoc.v:121104.18-121104.110" + wire $and$libresoc.v:121104$4517_Y + attribute \src "libresoc.v:121117.18-121117.114" + wire $and$libresoc.v:121117$4530_Y + attribute \src "libresoc.v:121118.18-121118.116" + wire $and$libresoc.v:121118$4531_Y + attribute \src "libresoc.v:121120.18-121120.114" + wire $and$libresoc.v:121120$4533_Y + attribute \src "libresoc.v:121122.18-121122.110" + wire $and$libresoc.v:121122$4535_Y + attribute \src "libresoc.v:121123.17-121123.112" + wire $and$libresoc.v:121123$4536_Y + attribute \src "libresoc.v:121124.17-121124.114" + wire $and$libresoc.v:121124$4537_Y + attribute \src "libresoc.v:121105.18-121105.126" + wire $eq$libresoc.v:121105$4518_Y + attribute \src "libresoc.v:121106.18-121106.126" + wire $eq$libresoc.v:121106$4519_Y + attribute \src "libresoc.v:121108.18-121108.110" + wire $eq$libresoc.v:121108$4521_Y + attribute \src "libresoc.v:121109.18-121109.110" + wire $eq$libresoc.v:121109$4522_Y + attribute \src "libresoc.v:121111.18-121111.112" + wire $eq$libresoc.v:121111$4524_Y + attribute \src "libresoc.v:121112.17-121112.130" + wire $eq$libresoc.v:121112$4525_Y + attribute \src "libresoc.v:121114.18-121114.110" + wire $eq$libresoc.v:121114$4527_Y + attribute \src "libresoc.v:121116.18-121116.131" + wire $eq$libresoc.v:121116$4529_Y + attribute \src "libresoc.v:121119.18-121119.131" + wire $eq$libresoc.v:121119$4532_Y + attribute \src "libresoc.v:121125.17-121125.130" + wire $eq$libresoc.v:121125$4538_Y + attribute \src "libresoc.v:121103.18-121103.110" + wire $not$libresoc.v:121103$4516_Y + attribute \src "libresoc.v:121121.18-121121.110" + wire $not$libresoc.v:121121$4534_Y + attribute \src "libresoc.v:121107.18-121107.110" + wire $or$libresoc.v:121107$4520_Y + attribute \src "libresoc.v:121110.18-121110.110" + wire $or$libresoc.v:121110$4523_Y + attribute \src "libresoc.v:121113.18-121113.110" + wire $or$libresoc.v:121113$4526_Y + attribute \src "libresoc.v:121115.18-121115.110" + wire $or$libresoc.v:121115$4528_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" @@ -188613,7 +188409,7 @@ module \dec_ALU attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:120873.7-120873.15" + attribute \src "libresoc.v:120669.7-120669.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in @@ -188630,7 +188426,7 @@ module \dec_ALU attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:121306$4515 + cell $and $and$libresoc.v:121102$4515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188638,10 +188434,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121306$4515_Y + connect \Y $and$libresoc.v:121102$4515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:121308$4517 + cell $and $and$libresoc.v:121104$4517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188649,10 +188445,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121308$4517_Y + connect \Y $and$libresoc.v:121104$4517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:121321$4530 + cell $and $and$libresoc.v:121117$4530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188660,10 +188456,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121321$4530_Y + connect \Y $and$libresoc.v:121117$4530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:121322$4531 + cell $and $and$libresoc.v:121118$4531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188671,10 +188467,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121322$4531_Y + connect \Y $and$libresoc.v:121118$4531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:121324$4533 + cell $and $and$libresoc.v:121120$4533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188682,10 +188478,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121324$4533_Y + connect \Y $and$libresoc.v:121120$4533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:121326$4535 + cell $and $and$libresoc.v:121122$4535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188693,10 +188489,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121326$4535_Y + connect \Y $and$libresoc.v:121122$4535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:121327$4536 + cell $and $and$libresoc.v:121123$4536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188704,10 +188500,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121327$4536_Y + connect \Y $and$libresoc.v:121123$4536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:121328$4537 + cell $and $and$libresoc.v:121124$4537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188715,10 +188511,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121328$4537_Y + connect \Y $and$libresoc.v:121124$4537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" - cell $eq $eq$libresoc.v:121309$4518 + cell $eq $eq$libresoc.v:121105$4518 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188726,10 +188522,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121309$4518_Y + connect \Y $eq$libresoc.v:121105$4518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $eq $eq$libresoc.v:121310$4519 + cell $eq $eq$libresoc.v:121106$4519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188737,10 +188533,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121310$4519_Y + connect \Y $eq$libresoc.v:121106$4519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:121312$4521 + cell $eq $eq$libresoc.v:121108$4521 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188748,10 +188544,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121312$4521_Y + connect \Y $eq$libresoc.v:121108$4521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:121313$4522 + cell $eq $eq$libresoc.v:121109$4522 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188759,10 +188555,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121313$4522_Y + connect \Y $eq$libresoc.v:121109$4522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:121315$4524 + cell $eq $eq$libresoc.v:121111$4524 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188770,10 +188566,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121315$4524_Y + connect \Y $eq$libresoc.v:121111$4524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:121316$4525 + cell $eq $eq$libresoc.v:121112$4525 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188781,10 +188577,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121316$4525_Y + connect \Y $eq$libresoc.v:121112$4525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $eq $eq$libresoc.v:121318$4527 + cell $eq $eq$libresoc.v:121114$4527 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188792,10 +188588,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121318$4527_Y + connect \Y $eq$libresoc.v:121114$4527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:121320$4529 + cell $eq $eq$libresoc.v:121116$4529 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188803,10 +188599,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121320$4529_Y + connect \Y $eq$libresoc.v:121116$4529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:121323$4532 + cell $eq $eq$libresoc.v:121119$4532 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188814,10 +188610,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121323$4532_Y + connect \Y $eq$libresoc.v:121119$4532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:121329$4538 + cell $eq $eq$libresoc.v:121125$4538 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188825,26 +188621,26 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121329$4538_Y + connect \Y $eq$libresoc.v:121125$4538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:121307$4516 + cell $not $not$libresoc.v:121103$4516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121307$4516_Y + connect \Y $not$libresoc.v:121103$4516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:121325$4534 + cell $not $not$libresoc.v:121121$4534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121325$4534_Y + connect \Y $not$libresoc.v:121121$4534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $or $or$libresoc.v:121311$4520 + cell $or $or$libresoc.v:121107$4520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188852,10 +188648,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121311$4520_Y + connect \Y $or$libresoc.v:121107$4520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:121314$4523 + cell $or $or$libresoc.v:121110$4523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188863,10 +188659,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121314$4523_Y + connect \Y $or$libresoc.v:121110$4523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:121317$4526 + cell $or $or$libresoc.v:121113$4526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188874,10 +188670,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121317$4526_Y + connect \Y $or$libresoc.v:121113$4526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $or $or$libresoc.v:121319$4528 + cell $or $or$libresoc.v:121115$4528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188885,10 +188681,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121319$4528_Y + connect \Y $or$libresoc.v:121115$4528_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121330.7-121358.4" + attribute \src "libresoc.v:121126.7-121154.4" cell \dec \dec connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -188919,7 +188715,7 @@ module \dec_ALU connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121359.10-121364.4" + attribute \src "libresoc.v:121155.10-121160.4" cell \dec_ai \dec_ai connect \ALU_RA \dec_ALU_RA connect \immz_out \dec_ai_immz_out @@ -188927,7 +188723,7 @@ module \dec_ALU connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:121365.10-121376.4" + attribute \src "libresoc.v:121161.10-121172.4" cell \dec_bi \dec_bi connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -188941,7 +188737,7 @@ module \dec_ALU connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121377.10-121383.4" + attribute \src "libresoc.v:121173.10-121179.4" cell \dec_oe \dec_oe connect \ALU_OE \dec_ALU_OE connect \ALU_internal_op \dec_ALU_internal_op @@ -188950,29 +188746,29 @@ module \dec_ALU connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121384.10-121389.4" + attribute \src "libresoc.v:121180.10-121185.4" cell \dec_rc \dec_rc connect \ALU_Rc \dec_ALU_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:120873.7-120873.20" - process $proc$libresoc.v:120873$4542 + attribute \src "libresoc.v:120669.7-120669.20" + process $proc$libresoc.v:120669$4542 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121390.3-121404.6" - process $proc$libresoc.v:121390$4539 + attribute \src "libresoc.v:121186.3-121200.6" + process $proc$libresoc.v:121186$4539 assign { } { } assign { } { } assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:121391.5-121391.29" + attribute \src "libresoc.v:121187.5-121187.29" switch \initial - attribute \src "libresoc.v:121391.9-121391.17" + attribute \src "libresoc.v:121187.9-121187.17" case 1'1 case end @@ -188992,14 +188788,14 @@ module \dec_ALU sync always update \ALU__write_cr0 $0\ALU__write_cr0[0:0] end - attribute \src "libresoc.v:121405.3-121417.6" - process $proc$libresoc.v:121405$4540 + attribute \src "libresoc.v:121201.3-121213.6" + process $proc$libresoc.v:121201$4540 assign { } { } assign { } { } assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:121406.5-121406.29" + attribute \src "libresoc.v:121202.5-121202.29" switch \initial - attribute \src "libresoc.v:121406.9-121406.17" + attribute \src "libresoc.v:121202.9-121202.17" case 1'1 case end @@ -189019,13 +188815,13 @@ module \dec_ALU sync always update \ALU__insn_type $0\ALU__insn_type[6:0] end - attribute \src "libresoc.v:121418.3-121432.6" - process $proc$libresoc.v:121418$4541 + attribute \src "libresoc.v:121214.3-121228.6" + process $proc$libresoc.v:121214$4541 assign { } { } assign $0\ALU__fn_unit[13:0] $1\ALU__fn_unit[13:0] - attribute \src "libresoc.v:121419.5-121419.29" + attribute \src "libresoc.v:121215.5-121215.29" switch \initial - attribute \src "libresoc.v:121419.9-121419.17" + attribute \src "libresoc.v:121215.9-121215.17" case 1'1 case end @@ -189047,30 +188843,30 @@ module \dec_ALU sync always update \ALU__fn_unit $0\ALU__fn_unit[13:0] end - connect \$10 $and$libresoc.v:121306$4515_Y - connect \$12 $not$libresoc.v:121307$4516_Y - connect \$14 $and$libresoc.v:121308$4517_Y - connect \$16 $eq$libresoc.v:121309$4518_Y - connect \$18 $eq$libresoc.v:121310$4519_Y - connect \$20 $or$libresoc.v:121311$4520_Y - connect \$22 $eq$libresoc.v:121312$4521_Y - connect \$24 $eq$libresoc.v:121313$4522_Y - connect \$26 $or$libresoc.v:121314$4523_Y - connect \$28 $eq$libresoc.v:121315$4524_Y - connect \$2 $eq$libresoc.v:121316$4525_Y - connect \$30 $or$libresoc.v:121317$4526_Y - connect \$32 $eq$libresoc.v:121318$4527_Y - connect \$34 $or$libresoc.v:121319$4528_Y - connect \$36 $eq$libresoc.v:121320$4529_Y - connect \$38 $and$libresoc.v:121321$4530_Y - connect \$40 $and$libresoc.v:121322$4531_Y - connect \$42 $eq$libresoc.v:121323$4532_Y - connect \$44 $and$libresoc.v:121324$4533_Y - connect \$46 $not$libresoc.v:121325$4534_Y - connect \$48 $and$libresoc.v:121326$4535_Y - connect \$4 $and$libresoc.v:121327$4536_Y - connect \$6 $and$libresoc.v:121328$4537_Y - connect \$8 $eq$libresoc.v:121329$4538_Y + connect \$10 $and$libresoc.v:121102$4515_Y + connect \$12 $not$libresoc.v:121103$4516_Y + connect \$14 $and$libresoc.v:121104$4517_Y + connect \$16 $eq$libresoc.v:121105$4518_Y + connect \$18 $eq$libresoc.v:121106$4519_Y + connect \$20 $or$libresoc.v:121107$4520_Y + connect \$22 $eq$libresoc.v:121108$4521_Y + connect \$24 $eq$libresoc.v:121109$4522_Y + connect \$26 $or$libresoc.v:121110$4523_Y + connect \$28 $eq$libresoc.v:121111$4524_Y + connect \$2 $eq$libresoc.v:121112$4525_Y + connect \$30 $or$libresoc.v:121113$4526_Y + connect \$32 $eq$libresoc.v:121114$4527_Y + connect \$34 $or$libresoc.v:121115$4528_Y + connect \$36 $eq$libresoc.v:121116$4529_Y + connect \$38 $and$libresoc.v:121117$4530_Y + connect \$40 $and$libresoc.v:121118$4531_Y + connect \$42 $eq$libresoc.v:121119$4532_Y + connect \$44 $and$libresoc.v:121120$4533_Y + connect \$46 $not$libresoc.v:121121$4534_Y + connect \$48 $and$libresoc.v:121122$4535_Y + connect \$4 $and$libresoc.v:121123$4536_Y + connect \$6 $and$libresoc.v:121124$4537_Y + connect \$8 $eq$libresoc.v:121125$4538_Y connect \ALU__is_signed \dec_ALU_sgn connect \ALU__is_32bit \dec_ALU_is_32b connect \ALU__output_carry \dec_ALU_cry_out @@ -189094,73 +188890,73 @@ module \dec_ALU connect \insn_in \dec_opcode_in connect \ALU__insn \dec_opcode_in end -attribute \src "libresoc.v:121459.1-121939.10" +attribute \src "libresoc.v:121255.1-121735.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" attribute \generator "nMigen" module \dec_BRANCH - attribute \src "libresoc.v:121889.3-121903.6" + attribute \src "libresoc.v:121685.3-121699.6" wire width 14 $0\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:121914.3-121926.6" + attribute \src "libresoc.v:121710.3-121722.6" wire width 7 $0\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:121904.3-121913.6" + attribute \src "libresoc.v:121700.3-121709.6" wire $0\BRANCH__lk[0:0] - attribute \src "libresoc.v:121460.7-121460.20" + attribute \src "libresoc.v:121256.7-121256.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121889.3-121903.6" + attribute \src "libresoc.v:121685.3-121699.6" wire width 14 $1\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:121914.3-121926.6" + attribute \src "libresoc.v:121710.3-121722.6" wire width 7 $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:121904.3-121913.6" + attribute \src "libresoc.v:121700.3-121709.6" wire $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:121821.18-121821.113" - wire $and$libresoc.v:121821$4543_Y - attribute \src "libresoc.v:121823.18-121823.110" - wire $and$libresoc.v:121823$4545_Y - attribute \src "libresoc.v:121836.18-121836.114" - wire $and$libresoc.v:121836$4558_Y - attribute \src "libresoc.v:121837.18-121837.116" - wire $and$libresoc.v:121837$4559_Y - attribute \src "libresoc.v:121839.18-121839.114" - wire $and$libresoc.v:121839$4561_Y - attribute \src "libresoc.v:121841.18-121841.110" - wire $and$libresoc.v:121841$4563_Y - attribute \src "libresoc.v:121842.17-121842.112" - wire $and$libresoc.v:121842$4564_Y - attribute \src "libresoc.v:121843.17-121843.114" - wire $and$libresoc.v:121843$4565_Y - attribute \src "libresoc.v:121824.18-121824.129" - wire $eq$libresoc.v:121824$4546_Y - attribute \src "libresoc.v:121825.18-121825.129" - wire $eq$libresoc.v:121825$4547_Y - attribute \src "libresoc.v:121827.18-121827.110" - wire $eq$libresoc.v:121827$4549_Y - attribute \src "libresoc.v:121828.18-121828.110" - wire $eq$libresoc.v:121828$4550_Y - attribute \src "libresoc.v:121830.18-121830.112" - wire $eq$libresoc.v:121830$4552_Y - attribute \src "libresoc.v:121831.17-121831.133" - wire $eq$libresoc.v:121831$4553_Y - attribute \src "libresoc.v:121833.18-121833.110" - wire $eq$libresoc.v:121833$4555_Y - attribute \src "libresoc.v:121835.18-121835.134" - wire $eq$libresoc.v:121835$4557_Y - attribute \src "libresoc.v:121838.18-121838.134" - wire $eq$libresoc.v:121838$4560_Y - attribute \src "libresoc.v:121844.17-121844.133" - wire $eq$libresoc.v:121844$4566_Y - attribute \src "libresoc.v:121822.18-121822.110" - wire $not$libresoc.v:121822$4544_Y - attribute \src "libresoc.v:121840.18-121840.110" - wire $not$libresoc.v:121840$4562_Y - attribute \src "libresoc.v:121826.18-121826.110" - wire $or$libresoc.v:121826$4548_Y - attribute \src "libresoc.v:121829.18-121829.110" - wire $or$libresoc.v:121829$4551_Y - attribute \src "libresoc.v:121832.18-121832.110" - wire $or$libresoc.v:121832$4554_Y - attribute \src "libresoc.v:121834.18-121834.110" - wire $or$libresoc.v:121834$4556_Y + attribute \src "libresoc.v:121617.18-121617.113" + wire $and$libresoc.v:121617$4543_Y + attribute \src "libresoc.v:121619.18-121619.110" + wire $and$libresoc.v:121619$4545_Y + attribute \src "libresoc.v:121632.18-121632.114" + wire $and$libresoc.v:121632$4558_Y + attribute \src "libresoc.v:121633.18-121633.116" + wire $and$libresoc.v:121633$4559_Y + attribute \src "libresoc.v:121635.18-121635.114" + wire $and$libresoc.v:121635$4561_Y + attribute \src "libresoc.v:121637.18-121637.110" + wire $and$libresoc.v:121637$4563_Y + attribute \src "libresoc.v:121638.17-121638.112" + wire $and$libresoc.v:121638$4564_Y + attribute \src "libresoc.v:121639.17-121639.114" + wire $and$libresoc.v:121639$4565_Y + attribute \src "libresoc.v:121620.18-121620.129" + wire $eq$libresoc.v:121620$4546_Y + attribute \src "libresoc.v:121621.18-121621.129" + wire $eq$libresoc.v:121621$4547_Y + attribute \src "libresoc.v:121623.18-121623.110" + wire $eq$libresoc.v:121623$4549_Y + attribute \src "libresoc.v:121624.18-121624.110" + wire $eq$libresoc.v:121624$4550_Y + attribute \src "libresoc.v:121626.18-121626.112" + wire $eq$libresoc.v:121626$4552_Y + attribute \src "libresoc.v:121627.17-121627.133" + wire $eq$libresoc.v:121627$4553_Y + attribute \src "libresoc.v:121629.18-121629.110" + wire $eq$libresoc.v:121629$4555_Y + attribute \src "libresoc.v:121631.18-121631.134" + wire $eq$libresoc.v:121631$4557_Y + attribute \src "libresoc.v:121634.18-121634.134" + wire $eq$libresoc.v:121634$4560_Y + attribute \src "libresoc.v:121640.17-121640.133" + wire $eq$libresoc.v:121640$4566_Y + attribute \src "libresoc.v:121618.18-121618.110" + wire $not$libresoc.v:121618$4544_Y + attribute \src "libresoc.v:121636.18-121636.110" + wire $not$libresoc.v:121636$4562_Y + attribute \src "libresoc.v:121622.18-121622.110" + wire $or$libresoc.v:121622$4548_Y + attribute \src "libresoc.v:121625.18-121625.110" + wire $or$libresoc.v:121625$4551_Y + attribute \src "libresoc.v:121628.18-121628.110" + wire $or$libresoc.v:121628$4554_Y + attribute \src "libresoc.v:121630.18-121630.110" + wire $or$libresoc.v:121630$4556_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" @@ -189506,7 +189302,7 @@ module \dec_BRANCH attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121460.7-121460.15" + attribute \src "libresoc.v:121256.7-121256.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in @@ -189521,7 +189317,7 @@ module \dec_BRANCH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:121821$4543 + cell $and $and$libresoc.v:121617$4543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189529,10 +189325,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121821$4543_Y + connect \Y $and$libresoc.v:121617$4543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:121823$4545 + cell $and $and$libresoc.v:121619$4545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189540,10 +189336,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121823$4545_Y + connect \Y $and$libresoc.v:121619$4545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:121836$4558 + cell $and $and$libresoc.v:121632$4558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189551,10 +189347,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121836$4558_Y + connect \Y $and$libresoc.v:121632$4558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:121837$4559 + cell $and $and$libresoc.v:121633$4559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189562,10 +189358,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121837$4559_Y + connect \Y $and$libresoc.v:121633$4559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:121839$4561 + cell $and $and$libresoc.v:121635$4561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189573,10 +189369,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121839$4561_Y + connect \Y $and$libresoc.v:121635$4561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:121841$4563 + cell $and $and$libresoc.v:121637$4563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189584,10 +189380,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121841$4563_Y + connect \Y $and$libresoc.v:121637$4563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:121842$4564 + cell $and $and$libresoc.v:121638$4564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189595,10 +189391,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121842$4564_Y + connect \Y $and$libresoc.v:121638$4564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:121843$4565 + cell $and $and$libresoc.v:121639$4565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189606,10 +189402,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121843$4565_Y + connect \Y $and$libresoc.v:121639$4565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" - cell $eq $eq$libresoc.v:121824$4546 + cell $eq $eq$libresoc.v:121620$4546 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189617,10 +189413,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121824$4546_Y + connect \Y $eq$libresoc.v:121620$4546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $eq $eq$libresoc.v:121825$4547 + cell $eq $eq$libresoc.v:121621$4547 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189628,10 +189424,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121825$4547_Y + connect \Y $eq$libresoc.v:121621$4547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:121827$4549 + cell $eq $eq$libresoc.v:121623$4549 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189639,10 +189435,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121827$4549_Y + connect \Y $eq$libresoc.v:121623$4549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:121828$4550 + cell $eq $eq$libresoc.v:121624$4550 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189650,10 +189446,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121828$4550_Y + connect \Y $eq$libresoc.v:121624$4550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:121830$4552 + cell $eq $eq$libresoc.v:121626$4552 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189661,10 +189457,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121830$4552_Y + connect \Y $eq$libresoc.v:121626$4552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:121831$4553 + cell $eq $eq$libresoc.v:121627$4553 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189672,10 +189468,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121831$4553_Y + connect \Y $eq$libresoc.v:121627$4553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $eq $eq$libresoc.v:121833$4555 + cell $eq $eq$libresoc.v:121629$4555 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189683,10 +189479,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121833$4555_Y + connect \Y $eq$libresoc.v:121629$4555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:121835$4557 + cell $eq $eq$libresoc.v:121631$4557 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189694,10 +189490,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121835$4557_Y + connect \Y $eq$libresoc.v:121631$4557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:121838$4560 + cell $eq $eq$libresoc.v:121634$4560 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189705,10 +189501,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121838$4560_Y + connect \Y $eq$libresoc.v:121634$4560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:121844$4566 + cell $eq $eq$libresoc.v:121640$4566 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189716,26 +189512,26 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121844$4566_Y + connect \Y $eq$libresoc.v:121640$4566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:121822$4544 + cell $not $not$libresoc.v:121618$4544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121822$4544_Y + connect \Y $not$libresoc.v:121618$4544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:121840$4562 + cell $not $not$libresoc.v:121636$4562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121840$4562_Y + connect \Y $not$libresoc.v:121636$4562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $or $or$libresoc.v:121826$4548 + cell $or $or$libresoc.v:121622$4548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189743,10 +189539,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121826$4548_Y + connect \Y $or$libresoc.v:121622$4548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:121829$4551 + cell $or $or$libresoc.v:121625$4551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189754,10 +189550,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121829$4551_Y + connect \Y $or$libresoc.v:121625$4551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:121832$4554 + cell $or $or$libresoc.v:121628$4554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189765,10 +189561,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121832$4554_Y + connect \Y $or$libresoc.v:121628$4554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $or $or$libresoc.v:121834$4556 + cell $or $or$libresoc.v:121630$4556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189776,10 +189572,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121834$4556_Y + connect \Y $or$libresoc.v:121630$4556_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121845.13-121867.4" + attribute \src "libresoc.v:121641.13-121663.4" cell \dec$141 \dec connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -189804,7 +189600,7 @@ module \dec_BRANCH connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121868.16-121879.4" + attribute \src "libresoc.v:121664.16-121675.4" cell \dec_bi$144 \dec_bi connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -189818,33 +189614,33 @@ module \dec_BRANCH connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121880.16-121884.4" + attribute \src "libresoc.v:121676.16-121680.4" cell \dec_oe$143 \dec_oe connect \BRANCH_OE \dec_BRANCH_OE connect \BRANCH_internal_op \dec_BRANCH_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121885.16-121888.4" + attribute \src "libresoc.v:121681.16-121684.4" cell \dec_rc$142 \dec_rc connect \BRANCH_Rc \dec_BRANCH_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121460.7-121460.20" - process $proc$libresoc.v:121460$4570 + attribute \src "libresoc.v:121256.7-121256.20" + process $proc$libresoc.v:121256$4570 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121889.3-121903.6" - process $proc$libresoc.v:121889$4567 + attribute \src "libresoc.v:121685.3-121699.6" + process $proc$libresoc.v:121685$4567 assign { } { } assign $0\BRANCH__fn_unit[13:0] $1\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:121890.5-121890.29" + attribute \src "libresoc.v:121686.5-121686.29" switch \initial - attribute \src "libresoc.v:121890.9-121890.17" + attribute \src "libresoc.v:121686.9-121686.17" case 1'1 case end @@ -189866,14 +189662,14 @@ module \dec_BRANCH sync always update \BRANCH__fn_unit $0\BRANCH__fn_unit[13:0] end - attribute \src "libresoc.v:121904.3-121913.6" - process $proc$libresoc.v:121904$4568 + attribute \src "libresoc.v:121700.3-121709.6" + process $proc$libresoc.v:121700$4568 assign { } { } assign { } { } assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:121905.5-121905.29" + attribute \src "libresoc.v:121701.5-121701.29" switch \initial - attribute \src "libresoc.v:121905.9-121905.17" + attribute \src "libresoc.v:121701.9-121701.17" case 1'1 case end @@ -189889,14 +189685,14 @@ module \dec_BRANCH sync always update \BRANCH__lk $0\BRANCH__lk[0:0] end - attribute \src "libresoc.v:121914.3-121926.6" - process $proc$libresoc.v:121914$4569 + attribute \src "libresoc.v:121710.3-121722.6" + process $proc$libresoc.v:121710$4569 assign { } { } assign { } { } assign $0\BRANCH__insn_type[6:0] $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:121915.5-121915.29" + attribute \src "libresoc.v:121711.5-121711.29" switch \initial - attribute \src "libresoc.v:121915.9-121915.17" + attribute \src "libresoc.v:121711.9-121711.17" case 1'1 case end @@ -189916,30 +189712,30 @@ module \dec_BRANCH sync always update \BRANCH__insn_type $0\BRANCH__insn_type[6:0] end - connect \$10 $and$libresoc.v:121821$4543_Y - connect \$12 $not$libresoc.v:121822$4544_Y - connect \$14 $and$libresoc.v:121823$4545_Y - connect \$16 $eq$libresoc.v:121824$4546_Y - connect \$18 $eq$libresoc.v:121825$4547_Y - connect \$20 $or$libresoc.v:121826$4548_Y - connect \$22 $eq$libresoc.v:121827$4549_Y - connect \$24 $eq$libresoc.v:121828$4550_Y - connect \$26 $or$libresoc.v:121829$4551_Y - connect \$28 $eq$libresoc.v:121830$4552_Y - connect \$2 $eq$libresoc.v:121831$4553_Y - connect \$30 $or$libresoc.v:121832$4554_Y - connect \$32 $eq$libresoc.v:121833$4555_Y - connect \$34 $or$libresoc.v:121834$4556_Y - connect \$36 $eq$libresoc.v:121835$4557_Y - connect \$38 $and$libresoc.v:121836$4558_Y - connect \$40 $and$libresoc.v:121837$4559_Y - connect \$42 $eq$libresoc.v:121838$4560_Y - connect \$44 $and$libresoc.v:121839$4561_Y - connect \$46 $not$libresoc.v:121840$4562_Y - connect \$48 $and$libresoc.v:121841$4563_Y - connect \$4 $and$libresoc.v:121842$4564_Y - connect \$6 $and$libresoc.v:121843$4565_Y - connect \$8 $eq$libresoc.v:121844$4566_Y + connect \$10 $and$libresoc.v:121617$4543_Y + connect \$12 $not$libresoc.v:121618$4544_Y + connect \$14 $and$libresoc.v:121619$4545_Y + connect \$16 $eq$libresoc.v:121620$4546_Y + connect \$18 $eq$libresoc.v:121621$4547_Y + connect \$20 $or$libresoc.v:121622$4548_Y + connect \$22 $eq$libresoc.v:121623$4549_Y + connect \$24 $eq$libresoc.v:121624$4550_Y + connect \$26 $or$libresoc.v:121625$4551_Y + connect \$28 $eq$libresoc.v:121626$4552_Y + connect \$2 $eq$libresoc.v:121627$4553_Y + connect \$30 $or$libresoc.v:121628$4554_Y + connect \$32 $eq$libresoc.v:121629$4555_Y + connect \$34 $or$libresoc.v:121630$4556_Y + connect \$36 $eq$libresoc.v:121631$4557_Y + connect \$38 $and$libresoc.v:121632$4558_Y + connect \$40 $and$libresoc.v:121633$4559_Y + connect \$42 $eq$libresoc.v:121634$4560_Y + connect \$44 $and$libresoc.v:121635$4561_Y + connect \$46 $not$libresoc.v:121636$4562_Y + connect \$48 $and$libresoc.v:121637$4563_Y + connect \$4 $and$libresoc.v:121638$4564_Y + connect \$6 $and$libresoc.v:121639$4565_Y + connect \$8 $eq$libresoc.v:121640$4566_Y connect \BRANCH__is_32bit \dec_BRANCH_is_32b connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_BRANCH_in2_sel @@ -189953,69 +189749,69 @@ module \dec_BRANCH connect \insn_in \dec_opcode_in connect \BRANCH__insn \dec_opcode_in end -attribute \src "libresoc.v:121943.1-122315.10" +attribute \src "libresoc.v:121739.1-122111.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" attribute \generator "nMigen" module \dec_CR - attribute \src "libresoc.v:122292.3-122306.6" + attribute \src "libresoc.v:122088.3-122102.6" wire width 14 $0\CR__fn_unit[13:0] - attribute \src "libresoc.v:122279.3-122291.6" + attribute \src "libresoc.v:122075.3-122087.6" wire width 7 $0\CR__insn_type[6:0] - attribute \src "libresoc.v:121944.7-121944.20" + attribute \src "libresoc.v:121740.7-121740.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122292.3-122306.6" + attribute \src "libresoc.v:122088.3-122102.6" wire width 14 $1\CR__fn_unit[13:0] - attribute \src "libresoc.v:122279.3-122291.6" + attribute \src "libresoc.v:122075.3-122087.6" wire width 7 $1\CR__insn_type[6:0] - attribute \src "libresoc.v:122234.18-122234.113" - wire $and$libresoc.v:122234$4571_Y - attribute \src "libresoc.v:122236.18-122236.110" - wire $and$libresoc.v:122236$4573_Y - attribute \src "libresoc.v:122249.18-122249.114" - wire $and$libresoc.v:122249$4586_Y - attribute \src "libresoc.v:122250.18-122250.116" - wire $and$libresoc.v:122250$4587_Y - attribute \src "libresoc.v:122252.18-122252.114" - wire $and$libresoc.v:122252$4589_Y - attribute \src "libresoc.v:122254.18-122254.110" - wire $and$libresoc.v:122254$4591_Y - attribute \src "libresoc.v:122255.17-122255.112" - wire $and$libresoc.v:122255$4592_Y - attribute \src "libresoc.v:122256.17-122256.114" - wire $and$libresoc.v:122256$4593_Y - attribute \src "libresoc.v:122237.18-122237.125" - wire $eq$libresoc.v:122237$4574_Y - attribute \src "libresoc.v:122238.18-122238.125" - wire $eq$libresoc.v:122238$4575_Y - attribute \src "libresoc.v:122240.18-122240.110" - wire $eq$libresoc.v:122240$4577_Y - attribute \src "libresoc.v:122241.18-122241.110" - wire $eq$libresoc.v:122241$4578_Y - attribute \src "libresoc.v:122243.18-122243.112" - wire $eq$libresoc.v:122243$4580_Y - attribute \src "libresoc.v:122244.17-122244.129" - wire $eq$libresoc.v:122244$4581_Y - attribute \src "libresoc.v:122246.18-122246.110" - wire $eq$libresoc.v:122246$4583_Y - attribute \src "libresoc.v:122248.18-122248.130" - wire $eq$libresoc.v:122248$4585_Y - attribute \src "libresoc.v:122251.18-122251.130" - wire $eq$libresoc.v:122251$4588_Y - attribute \src "libresoc.v:122257.17-122257.129" - wire $eq$libresoc.v:122257$4594_Y - attribute \src "libresoc.v:122235.18-122235.110" - wire $not$libresoc.v:122235$4572_Y - attribute \src "libresoc.v:122253.18-122253.110" - wire $not$libresoc.v:122253$4590_Y - attribute \src "libresoc.v:122239.18-122239.110" - wire $or$libresoc.v:122239$4576_Y - attribute \src "libresoc.v:122242.18-122242.110" - wire $or$libresoc.v:122242$4579_Y - attribute \src "libresoc.v:122245.18-122245.110" - wire $or$libresoc.v:122245$4582_Y - attribute \src "libresoc.v:122247.18-122247.110" - wire $or$libresoc.v:122247$4584_Y + attribute \src "libresoc.v:122030.18-122030.113" + wire $and$libresoc.v:122030$4571_Y + attribute \src "libresoc.v:122032.18-122032.110" + wire $and$libresoc.v:122032$4573_Y + attribute \src "libresoc.v:122045.18-122045.114" + wire $and$libresoc.v:122045$4586_Y + attribute \src "libresoc.v:122046.18-122046.116" + wire $and$libresoc.v:122046$4587_Y + attribute \src "libresoc.v:122048.18-122048.114" + wire $and$libresoc.v:122048$4589_Y + attribute \src "libresoc.v:122050.18-122050.110" + wire $and$libresoc.v:122050$4591_Y + attribute \src "libresoc.v:122051.17-122051.112" + wire $and$libresoc.v:122051$4592_Y + attribute \src "libresoc.v:122052.17-122052.114" + wire $and$libresoc.v:122052$4593_Y + attribute \src "libresoc.v:122033.18-122033.125" + wire $eq$libresoc.v:122033$4574_Y + attribute \src "libresoc.v:122034.18-122034.125" + wire $eq$libresoc.v:122034$4575_Y + attribute \src "libresoc.v:122036.18-122036.110" + wire $eq$libresoc.v:122036$4577_Y + attribute \src "libresoc.v:122037.18-122037.110" + wire $eq$libresoc.v:122037$4578_Y + attribute \src "libresoc.v:122039.18-122039.112" + wire $eq$libresoc.v:122039$4580_Y + attribute \src "libresoc.v:122040.17-122040.129" + wire $eq$libresoc.v:122040$4581_Y + attribute \src "libresoc.v:122042.18-122042.110" + wire $eq$libresoc.v:122042$4583_Y + attribute \src "libresoc.v:122044.18-122044.130" + wire $eq$libresoc.v:122044$4585_Y + attribute \src "libresoc.v:122047.18-122047.130" + wire $eq$libresoc.v:122047$4588_Y + attribute \src "libresoc.v:122053.17-122053.129" + wire $eq$libresoc.v:122053$4594_Y + attribute \src "libresoc.v:122031.18-122031.110" + wire $not$libresoc.v:122031$4572_Y + attribute \src "libresoc.v:122049.18-122049.110" + wire $not$libresoc.v:122049$4590_Y + attribute \src "libresoc.v:122035.18-122035.110" + wire $or$libresoc.v:122035$4576_Y + attribute \src "libresoc.v:122038.18-122038.110" + wire $or$libresoc.v:122038$4579_Y + attribute \src "libresoc.v:122041.18-122041.110" + wire $or$libresoc.v:122041$4582_Y + attribute \src "libresoc.v:122043.18-122043.110" + wire $or$libresoc.v:122043$4584_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" @@ -190291,7 +190087,7 @@ module \dec_CR attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121944.7-121944.15" + attribute \src "libresoc.v:121740.7-121740.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in @@ -190306,7 +190102,7 @@ module \dec_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:122234$4571 + cell $and $and$libresoc.v:122030$4571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190314,10 +190110,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:122234$4571_Y + connect \Y $and$libresoc.v:122030$4571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:122236$4573 + cell $and $and$libresoc.v:122032$4573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190325,10 +190121,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:122236$4573_Y + connect \Y $and$libresoc.v:122032$4573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:122249$4586 + cell $and $and$libresoc.v:122045$4586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190336,10 +190132,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:122249$4586_Y + connect \Y $and$libresoc.v:122045$4586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:122250$4587 + cell $and $and$libresoc.v:122046$4587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190347,10 +190143,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122250$4587_Y + connect \Y $and$libresoc.v:122046$4587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:122252$4589 + cell $and $and$libresoc.v:122048$4589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190358,10 +190154,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:122252$4589_Y + connect \Y $and$libresoc.v:122048$4589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:122254$4591 + cell $and $and$libresoc.v:122050$4591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190369,10 +190165,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:122254$4591_Y + connect \Y $and$libresoc.v:122050$4591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:122255$4592 + cell $and $and$libresoc.v:122051$4592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190380,10 +190176,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:122255$4592_Y + connect \Y $and$libresoc.v:122051$4592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:122256$4593 + cell $and $and$libresoc.v:122052$4593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190391,10 +190187,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122256$4593_Y + connect \Y $and$libresoc.v:122052$4593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" - cell $eq $eq$libresoc.v:122237$4574 + cell $eq $eq$libresoc.v:122033$4574 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190402,10 +190198,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122237$4574_Y + connect \Y $eq$libresoc.v:122033$4574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $eq $eq$libresoc.v:122238$4575 + cell $eq $eq$libresoc.v:122034$4575 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190413,10 +190209,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122238$4575_Y + connect \Y $eq$libresoc.v:122034$4575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:122240$4577 + cell $eq $eq$libresoc.v:122036$4577 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190424,10 +190220,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:122240$4577_Y + connect \Y $eq$libresoc.v:122036$4577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:122241$4578 + cell $eq $eq$libresoc.v:122037$4578 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190435,10 +190231,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:122241$4578_Y + connect \Y $eq$libresoc.v:122037$4578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:122243$4580 + cell $eq $eq$libresoc.v:122039$4580 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190446,10 +190242,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122243$4580_Y + connect \Y $eq$libresoc.v:122039$4580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:122244$4581 + cell $eq $eq$libresoc.v:122040$4581 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190457,10 +190253,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122244$4581_Y + connect \Y $eq$libresoc.v:122040$4581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $eq $eq$libresoc.v:122246$4583 + cell $eq $eq$libresoc.v:122042$4583 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190468,10 +190264,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:122246$4583_Y + connect \Y $eq$libresoc.v:122042$4583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:122248$4585 + cell $eq $eq$libresoc.v:122044$4585 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190479,10 +190275,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122248$4585_Y + connect \Y $eq$libresoc.v:122044$4585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:122251$4588 + cell $eq $eq$libresoc.v:122047$4588 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190490,10 +190286,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122251$4588_Y + connect \Y $eq$libresoc.v:122047$4588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:122257$4594 + cell $eq $eq$libresoc.v:122053$4594 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190501,26 +190297,26 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122257$4594_Y + connect \Y $eq$libresoc.v:122053$4594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:122235$4572 + cell $not $not$libresoc.v:122031$4572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122235$4572_Y + connect \Y $not$libresoc.v:122031$4572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:122253$4590 + cell $not $not$libresoc.v:122049$4590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122253$4590_Y + connect \Y $not$libresoc.v:122049$4590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $or $or$libresoc.v:122239$4576 + cell $or $or$libresoc.v:122035$4576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190528,10 +190324,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:122239$4576_Y + connect \Y $or$libresoc.v:122035$4576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:122242$4579 + cell $or $or$libresoc.v:122038$4579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190539,10 +190335,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:122242$4579_Y + connect \Y $or$libresoc.v:122038$4579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:122245$4582 + cell $or $or$libresoc.v:122041$4582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190550,10 +190346,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:122245$4582_Y + connect \Y $or$libresoc.v:122041$4582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $or $or$libresoc.v:122247$4584 + cell $or $or$libresoc.v:122043$4584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190561,10 +190357,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:122247$4584_Y + connect \Y $or$libresoc.v:122043$4584_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122258.13-122269.4" + attribute \src "libresoc.v:122054.13-122065.4" cell \dec$138 \dec connect \CR_OE \dec_CR_OE connect \CR_Rc \dec_CR_Rc @@ -190578,34 +190374,34 @@ module \dec_CR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122270.16-122274.4" + attribute \src "libresoc.v:122066.16-122070.4" cell \dec_oe$140 \dec_oe connect \CR_OE \dec_CR_OE connect \CR_internal_op \dec_CR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122275.16-122278.4" + attribute \src "libresoc.v:122071.16-122074.4" cell \dec_rc$139 \dec_rc connect \CR_Rc \dec_CR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121944.7-121944.20" - process $proc$libresoc.v:121944$4597 + attribute \src "libresoc.v:121740.7-121740.20" + process $proc$libresoc.v:121740$4597 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122279.3-122291.6" - process $proc$libresoc.v:122279$4595 + attribute \src "libresoc.v:122075.3-122087.6" + process $proc$libresoc.v:122075$4595 assign { } { } assign { } { } assign $0\CR__insn_type[6:0] $1\CR__insn_type[6:0] - attribute \src "libresoc.v:122280.5-122280.29" + attribute \src "libresoc.v:122076.5-122076.29" switch \initial - attribute \src "libresoc.v:122280.9-122280.17" + attribute \src "libresoc.v:122076.9-122076.17" case 1'1 case end @@ -190625,13 +190421,13 @@ module \dec_CR sync always update \CR__insn_type $0\CR__insn_type[6:0] end - attribute \src "libresoc.v:122292.3-122306.6" - process $proc$libresoc.v:122292$4596 + attribute \src "libresoc.v:122088.3-122102.6" + process $proc$libresoc.v:122088$4596 assign { } { } assign $0\CR__fn_unit[13:0] $1\CR__fn_unit[13:0] - attribute \src "libresoc.v:122293.5-122293.29" + attribute \src "libresoc.v:122089.5-122089.29" switch \initial - attribute \src "libresoc.v:122293.9-122293.17" + attribute \src "libresoc.v:122089.9-122089.17" case 1'1 case end @@ -190653,30 +190449,30 @@ module \dec_CR sync always update \CR__fn_unit $0\CR__fn_unit[13:0] end - connect \$10 $and$libresoc.v:122234$4571_Y - connect \$12 $not$libresoc.v:122235$4572_Y - connect \$14 $and$libresoc.v:122236$4573_Y - connect \$16 $eq$libresoc.v:122237$4574_Y - connect \$18 $eq$libresoc.v:122238$4575_Y - connect \$20 $or$libresoc.v:122239$4576_Y - connect \$22 $eq$libresoc.v:122240$4577_Y - connect \$24 $eq$libresoc.v:122241$4578_Y - connect \$26 $or$libresoc.v:122242$4579_Y - connect \$28 $eq$libresoc.v:122243$4580_Y - connect \$2 $eq$libresoc.v:122244$4581_Y - connect \$30 $or$libresoc.v:122245$4582_Y - connect \$32 $eq$libresoc.v:122246$4583_Y - connect \$34 $or$libresoc.v:122247$4584_Y - connect \$36 $eq$libresoc.v:122248$4585_Y - connect \$38 $and$libresoc.v:122249$4586_Y - connect \$40 $and$libresoc.v:122250$4587_Y - connect \$42 $eq$libresoc.v:122251$4588_Y - connect \$44 $and$libresoc.v:122252$4589_Y - connect \$46 $not$libresoc.v:122253$4590_Y - connect \$48 $and$libresoc.v:122254$4591_Y - connect \$4 $and$libresoc.v:122255$4592_Y - connect \$6 $and$libresoc.v:122256$4593_Y - connect \$8 $eq$libresoc.v:122257$4594_Y + connect \$10 $and$libresoc.v:122030$4571_Y + connect \$12 $not$libresoc.v:122031$4572_Y + connect \$14 $and$libresoc.v:122032$4573_Y + connect \$16 $eq$libresoc.v:122033$4574_Y + connect \$18 $eq$libresoc.v:122034$4575_Y + connect \$20 $or$libresoc.v:122035$4576_Y + connect \$22 $eq$libresoc.v:122036$4577_Y + connect \$24 $eq$libresoc.v:122037$4578_Y + connect \$26 $or$libresoc.v:122038$4579_Y + connect \$28 $eq$libresoc.v:122039$4580_Y + connect \$2 $eq$libresoc.v:122040$4581_Y + connect \$30 $or$libresoc.v:122041$4582_Y + connect \$32 $eq$libresoc.v:122042$4583_Y + connect \$34 $or$libresoc.v:122043$4584_Y + connect \$36 $eq$libresoc.v:122044$4585_Y + connect \$38 $and$libresoc.v:122045$4586_Y + connect \$40 $and$libresoc.v:122046$4587_Y + connect \$42 $eq$libresoc.v:122047$4588_Y + connect \$44 $and$libresoc.v:122048$4589_Y + connect \$46 $not$libresoc.v:122049$4590_Y + connect \$48 $and$libresoc.v:122050$4591_Y + connect \$4 $and$libresoc.v:122051$4592_Y + connect \$6 $and$libresoc.v:122052$4593_Y + connect \$8 $eq$libresoc.v:122053$4594_Y connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_CR_SPR [4:0] \dec_CR_SPR [9:5] } @@ -190686,73 +190482,73 @@ module \dec_CR connect \insn_in \dec_opcode_in connect \CR__insn \dec_opcode_in end -attribute \src "libresoc.v:122319.1-122902.10" +attribute \src "libresoc.v:122115.1-122698.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV" attribute \generator "nMigen" module \dec_DIV - attribute \src "libresoc.v:122865.3-122879.6" + attribute \src "libresoc.v:122661.3-122675.6" wire width 14 $0\DIV__fn_unit[13:0] - attribute \src "libresoc.v:122852.3-122864.6" + attribute \src "libresoc.v:122648.3-122660.6" wire width 7 $0\DIV__insn_type[6:0] - attribute \src "libresoc.v:122837.3-122851.6" + attribute \src "libresoc.v:122633.3-122647.6" wire $0\DIV__write_cr0[0:0] - attribute \src "libresoc.v:122320.7-122320.20" + attribute \src "libresoc.v:122116.7-122116.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122865.3-122879.6" + attribute \src "libresoc.v:122661.3-122675.6" wire width 14 $1\DIV__fn_unit[13:0] - attribute \src "libresoc.v:122852.3-122864.6" + attribute \src "libresoc.v:122648.3-122660.6" wire width 7 $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:122837.3-122851.6" + attribute \src "libresoc.v:122633.3-122647.6" wire $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:122753.18-122753.113" - wire $and$libresoc.v:122753$4598_Y - attribute \src "libresoc.v:122755.18-122755.110" - wire $and$libresoc.v:122755$4600_Y - attribute \src "libresoc.v:122768.18-122768.114" - wire $and$libresoc.v:122768$4613_Y - attribute \src "libresoc.v:122769.18-122769.116" - wire $and$libresoc.v:122769$4614_Y - attribute \src "libresoc.v:122771.18-122771.114" - wire $and$libresoc.v:122771$4616_Y - attribute \src "libresoc.v:122773.18-122773.110" - wire $and$libresoc.v:122773$4618_Y - attribute \src "libresoc.v:122774.17-122774.112" - wire $and$libresoc.v:122774$4619_Y - attribute \src "libresoc.v:122775.17-122775.114" - wire $and$libresoc.v:122775$4620_Y - attribute \src "libresoc.v:122756.18-122756.126" - wire $eq$libresoc.v:122756$4601_Y - attribute \src "libresoc.v:122757.18-122757.126" - wire $eq$libresoc.v:122757$4602_Y - attribute \src "libresoc.v:122759.18-122759.110" - wire $eq$libresoc.v:122759$4604_Y - attribute \src "libresoc.v:122760.18-122760.110" - wire $eq$libresoc.v:122760$4605_Y - attribute \src "libresoc.v:122762.18-122762.112" - wire $eq$libresoc.v:122762$4607_Y - attribute \src "libresoc.v:122763.17-122763.130" - wire $eq$libresoc.v:122763$4608_Y - attribute \src "libresoc.v:122765.18-122765.110" - wire $eq$libresoc.v:122765$4610_Y - attribute \src "libresoc.v:122767.18-122767.131" - wire $eq$libresoc.v:122767$4612_Y - attribute \src "libresoc.v:122770.18-122770.131" - wire $eq$libresoc.v:122770$4615_Y - attribute \src "libresoc.v:122776.17-122776.130" - wire $eq$libresoc.v:122776$4621_Y - attribute \src "libresoc.v:122754.18-122754.110" - wire $not$libresoc.v:122754$4599_Y - attribute \src "libresoc.v:122772.18-122772.110" - wire $not$libresoc.v:122772$4617_Y - attribute \src "libresoc.v:122758.18-122758.110" - wire $or$libresoc.v:122758$4603_Y - attribute \src "libresoc.v:122761.18-122761.110" - wire $or$libresoc.v:122761$4606_Y - attribute \src "libresoc.v:122764.18-122764.110" - wire $or$libresoc.v:122764$4609_Y - attribute \src "libresoc.v:122766.18-122766.110" - wire $or$libresoc.v:122766$4611_Y + attribute \src "libresoc.v:122549.18-122549.113" + wire $and$libresoc.v:122549$4598_Y + attribute \src "libresoc.v:122551.18-122551.110" + wire $and$libresoc.v:122551$4600_Y + attribute \src "libresoc.v:122564.18-122564.114" + wire $and$libresoc.v:122564$4613_Y + attribute \src "libresoc.v:122565.18-122565.116" + wire $and$libresoc.v:122565$4614_Y + attribute \src "libresoc.v:122567.18-122567.114" + wire $and$libresoc.v:122567$4616_Y + attribute \src "libresoc.v:122569.18-122569.110" + wire $and$libresoc.v:122569$4618_Y + attribute \src "libresoc.v:122570.17-122570.112" + wire $and$libresoc.v:122570$4619_Y + attribute \src "libresoc.v:122571.17-122571.114" + wire $and$libresoc.v:122571$4620_Y + attribute \src "libresoc.v:122552.18-122552.126" + wire $eq$libresoc.v:122552$4601_Y + attribute \src "libresoc.v:122553.18-122553.126" + wire $eq$libresoc.v:122553$4602_Y + attribute \src "libresoc.v:122555.18-122555.110" + wire $eq$libresoc.v:122555$4604_Y + attribute \src "libresoc.v:122556.18-122556.110" + wire $eq$libresoc.v:122556$4605_Y + attribute \src "libresoc.v:122558.18-122558.112" + wire $eq$libresoc.v:122558$4607_Y + attribute \src "libresoc.v:122559.17-122559.130" + wire $eq$libresoc.v:122559$4608_Y + attribute \src "libresoc.v:122561.18-122561.110" + wire $eq$libresoc.v:122561$4610_Y + attribute \src "libresoc.v:122563.18-122563.131" + wire $eq$libresoc.v:122563$4612_Y + attribute \src "libresoc.v:122566.18-122566.131" + wire $eq$libresoc.v:122566$4615_Y + attribute \src "libresoc.v:122572.17-122572.130" + wire $eq$libresoc.v:122572$4621_Y + attribute \src "libresoc.v:122550.18-122550.110" + wire $not$libresoc.v:122550$4599_Y + attribute \src "libresoc.v:122568.18-122568.110" + wire $not$libresoc.v:122568$4617_Y + attribute \src "libresoc.v:122554.18-122554.110" + wire $or$libresoc.v:122554$4603_Y + attribute \src "libresoc.v:122557.18-122557.110" + wire $or$libresoc.v:122557$4606_Y + attribute \src "libresoc.v:122560.18-122560.110" + wire $or$libresoc.v:122560$4609_Y + attribute \src "libresoc.v:122562.18-122562.110" + wire $or$libresoc.v:122562$4611_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" @@ -191168,7 +190964,7 @@ module \dec_DIV attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:122320.7-122320.15" + attribute \src "libresoc.v:122116.7-122116.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in @@ -191185,7 +190981,7 @@ module \dec_DIV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:122753$4598 + cell $and $and$libresoc.v:122549$4598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191193,10 +190989,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:122753$4598_Y + connect \Y $and$libresoc.v:122549$4598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:122755$4600 + cell $and $and$libresoc.v:122551$4600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191204,10 +191000,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:122755$4600_Y + connect \Y $and$libresoc.v:122551$4600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:122768$4613 + cell $and $and$libresoc.v:122564$4613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191215,10 +191011,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:122768$4613_Y + connect \Y $and$libresoc.v:122564$4613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:122769$4614 + cell $and $and$libresoc.v:122565$4614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191226,10 +191022,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122769$4614_Y + connect \Y $and$libresoc.v:122565$4614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:122771$4616 + cell $and $and$libresoc.v:122567$4616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191237,10 +191033,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:122771$4616_Y + connect \Y $and$libresoc.v:122567$4616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:122773$4618 + cell $and $and$libresoc.v:122569$4618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191248,10 +191044,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:122773$4618_Y + connect \Y $and$libresoc.v:122569$4618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:122774$4619 + cell $and $and$libresoc.v:122570$4619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191259,10 +191055,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:122774$4619_Y + connect \Y $and$libresoc.v:122570$4619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:122775$4620 + cell $and $and$libresoc.v:122571$4620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191270,10 +191066,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122775$4620_Y + connect \Y $and$libresoc.v:122571$4620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" - cell $eq $eq$libresoc.v:122756$4601 + cell $eq $eq$libresoc.v:122552$4601 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191281,10 +191077,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122756$4601_Y + connect \Y $eq$libresoc.v:122552$4601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $eq $eq$libresoc.v:122757$4602 + cell $eq $eq$libresoc.v:122553$4602 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191292,10 +191088,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122757$4602_Y + connect \Y $eq$libresoc.v:122553$4602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:122759$4604 + cell $eq $eq$libresoc.v:122555$4604 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191303,10 +191099,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:122759$4604_Y + connect \Y $eq$libresoc.v:122555$4604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:122760$4605 + cell $eq $eq$libresoc.v:122556$4605 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191314,10 +191110,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:122760$4605_Y + connect \Y $eq$libresoc.v:122556$4605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:122762$4607 + cell $eq $eq$libresoc.v:122558$4607 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191325,10 +191121,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122762$4607_Y + connect \Y $eq$libresoc.v:122558$4607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:122763$4608 + cell $eq $eq$libresoc.v:122559$4608 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191336,10 +191132,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122763$4608_Y + connect \Y $eq$libresoc.v:122559$4608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $eq $eq$libresoc.v:122765$4610 + cell $eq $eq$libresoc.v:122561$4610 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191347,10 +191143,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:122765$4610_Y + connect \Y $eq$libresoc.v:122561$4610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:122767$4612 + cell $eq $eq$libresoc.v:122563$4612 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191358,10 +191154,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122767$4612_Y + connect \Y $eq$libresoc.v:122563$4612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:122770$4615 + cell $eq $eq$libresoc.v:122566$4615 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191369,10 +191165,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122770$4615_Y + connect \Y $eq$libresoc.v:122566$4615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:122776$4621 + cell $eq $eq$libresoc.v:122572$4621 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191380,26 +191176,26 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122776$4621_Y + connect \Y $eq$libresoc.v:122572$4621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:122754$4599 + cell $not $not$libresoc.v:122550$4599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122754$4599_Y + connect \Y $not$libresoc.v:122550$4599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:122772$4617 + cell $not $not$libresoc.v:122568$4617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122772$4617_Y + connect \Y $not$libresoc.v:122568$4617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $or $or$libresoc.v:122758$4603 + cell $or $or$libresoc.v:122554$4603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191407,10 +191203,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:122758$4603_Y + connect \Y $or$libresoc.v:122554$4603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:122761$4606 + cell $or $or$libresoc.v:122557$4606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191418,10 +191214,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:122761$4606_Y + connect \Y $or$libresoc.v:122557$4606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:122764$4609 + cell $or $or$libresoc.v:122560$4609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191429,10 +191225,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:122764$4609_Y + connect \Y $or$libresoc.v:122560$4609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $or $or$libresoc.v:122766$4611 + cell $or $or$libresoc.v:122562$4611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191440,10 +191236,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:122766$4611_Y + connect \Y $or$libresoc.v:122562$4611_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122777.13-122805.4" + attribute \src "libresoc.v:122573.13-122601.4" cell \dec$153 \dec connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -191474,7 +191270,7 @@ module \dec_DIV connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122806.16-122811.4" + attribute \src "libresoc.v:122602.16-122607.4" cell \dec_ai$156 \dec_ai connect \DIV_RA \dec_DIV_RA connect \immz_out \dec_ai_immz_out @@ -191482,7 +191278,7 @@ module \dec_DIV connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:122812.16-122823.4" + attribute \src "libresoc.v:122608.16-122619.4" cell \dec_bi$157 \dec_bi connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -191496,7 +191292,7 @@ module \dec_DIV connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122824.16-122830.4" + attribute \src "libresoc.v:122620.16-122626.4" cell \dec_oe$155 \dec_oe connect \DIV_OE \dec_DIV_OE connect \DIV_internal_op \dec_DIV_internal_op @@ -191505,29 +191301,29 @@ module \dec_DIV connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122831.16-122836.4" + attribute \src "libresoc.v:122627.16-122632.4" cell \dec_rc$154 \dec_rc connect \DIV_Rc \dec_DIV_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:122320.7-122320.20" - process $proc$libresoc.v:122320$4625 + attribute \src "libresoc.v:122116.7-122116.20" + process $proc$libresoc.v:122116$4625 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122837.3-122851.6" - process $proc$libresoc.v:122837$4622 + attribute \src "libresoc.v:122633.3-122647.6" + process $proc$libresoc.v:122633$4622 assign { } { } assign { } { } assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:122838.5-122838.29" + attribute \src "libresoc.v:122634.5-122634.29" switch \initial - attribute \src "libresoc.v:122838.9-122838.17" + attribute \src "libresoc.v:122634.9-122634.17" case 1'1 case end @@ -191547,14 +191343,14 @@ module \dec_DIV sync always update \DIV__write_cr0 $0\DIV__write_cr0[0:0] end - attribute \src "libresoc.v:122852.3-122864.6" - process $proc$libresoc.v:122852$4623 + attribute \src "libresoc.v:122648.3-122660.6" + process $proc$libresoc.v:122648$4623 assign { } { } assign { } { } assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:122853.5-122853.29" + attribute \src "libresoc.v:122649.5-122649.29" switch \initial - attribute \src "libresoc.v:122853.9-122853.17" + attribute \src "libresoc.v:122649.9-122649.17" case 1'1 case end @@ -191574,13 +191370,13 @@ module \dec_DIV sync always update \DIV__insn_type $0\DIV__insn_type[6:0] end - attribute \src "libresoc.v:122865.3-122879.6" - process $proc$libresoc.v:122865$4624 + attribute \src "libresoc.v:122661.3-122675.6" + process $proc$libresoc.v:122661$4624 assign { } { } assign $0\DIV__fn_unit[13:0] $1\DIV__fn_unit[13:0] - attribute \src "libresoc.v:122866.5-122866.29" + attribute \src "libresoc.v:122662.5-122662.29" switch \initial - attribute \src "libresoc.v:122866.9-122866.17" + attribute \src "libresoc.v:122662.9-122662.17" case 1'1 case end @@ -191602,30 +191398,30 @@ module \dec_DIV sync always update \DIV__fn_unit $0\DIV__fn_unit[13:0] end - connect \$10 $and$libresoc.v:122753$4598_Y - connect \$12 $not$libresoc.v:122754$4599_Y - connect \$14 $and$libresoc.v:122755$4600_Y - connect \$16 $eq$libresoc.v:122756$4601_Y - connect \$18 $eq$libresoc.v:122757$4602_Y - connect \$20 $or$libresoc.v:122758$4603_Y - connect \$22 $eq$libresoc.v:122759$4604_Y - connect \$24 $eq$libresoc.v:122760$4605_Y - connect \$26 $or$libresoc.v:122761$4606_Y - connect \$28 $eq$libresoc.v:122762$4607_Y - connect \$2 $eq$libresoc.v:122763$4608_Y - connect \$30 $or$libresoc.v:122764$4609_Y - connect \$32 $eq$libresoc.v:122765$4610_Y - connect \$34 $or$libresoc.v:122766$4611_Y - connect \$36 $eq$libresoc.v:122767$4612_Y - connect \$38 $and$libresoc.v:122768$4613_Y - connect \$40 $and$libresoc.v:122769$4614_Y - connect \$42 $eq$libresoc.v:122770$4615_Y - connect \$44 $and$libresoc.v:122771$4616_Y - connect \$46 $not$libresoc.v:122772$4617_Y - connect \$48 $and$libresoc.v:122773$4618_Y - connect \$4 $and$libresoc.v:122774$4619_Y - connect \$6 $and$libresoc.v:122775$4620_Y - connect \$8 $eq$libresoc.v:122776$4621_Y + connect \$10 $and$libresoc.v:122549$4598_Y + connect \$12 $not$libresoc.v:122550$4599_Y + connect \$14 $and$libresoc.v:122551$4600_Y + connect \$16 $eq$libresoc.v:122552$4601_Y + connect \$18 $eq$libresoc.v:122553$4602_Y + connect \$20 $or$libresoc.v:122554$4603_Y + connect \$22 $eq$libresoc.v:122555$4604_Y + connect \$24 $eq$libresoc.v:122556$4605_Y + connect \$26 $or$libresoc.v:122557$4606_Y + connect \$28 $eq$libresoc.v:122558$4607_Y + connect \$2 $eq$libresoc.v:122559$4608_Y + connect \$30 $or$libresoc.v:122560$4609_Y + connect \$32 $eq$libresoc.v:122561$4610_Y + connect \$34 $or$libresoc.v:122562$4611_Y + connect \$36 $eq$libresoc.v:122563$4612_Y + connect \$38 $and$libresoc.v:122564$4613_Y + connect \$40 $and$libresoc.v:122565$4614_Y + connect \$42 $eq$libresoc.v:122566$4615_Y + connect \$44 $and$libresoc.v:122567$4616_Y + connect \$46 $not$libresoc.v:122568$4617_Y + connect \$48 $and$libresoc.v:122569$4618_Y + connect \$4 $and$libresoc.v:122570$4619_Y + connect \$6 $and$libresoc.v:122571$4620_Y + connect \$8 $eq$libresoc.v:122572$4621_Y connect \DIV__is_signed \dec_DIV_sgn connect \DIV__is_32bit \dec_DIV_is_32b connect \DIV__output_carry \dec_DIV_cry_out @@ -191649,69 +191445,69 @@ module \dec_DIV connect \insn_in \dec_opcode_in connect \DIV__insn \dec_opcode_in end -attribute \src "libresoc.v:122906.1-123467.10" +attribute \src "libresoc.v:122702.1-123263.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" attribute \generator "nMigen" module \dec_LDST - attribute \src "libresoc.v:123431.3-123445.6" + attribute \src "libresoc.v:123227.3-123241.6" wire width 14 $0\LDST__fn_unit[13:0] - attribute \src "libresoc.v:123418.3-123430.6" + attribute \src "libresoc.v:123214.3-123226.6" wire width 7 $0\LDST__insn_type[6:0] - attribute \src "libresoc.v:122907.7-122907.20" + attribute \src "libresoc.v:122703.7-122703.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123431.3-123445.6" + attribute \src "libresoc.v:123227.3-123241.6" wire width 14 $1\LDST__fn_unit[13:0] - attribute \src "libresoc.v:123418.3-123430.6" + attribute \src "libresoc.v:123214.3-123226.6" wire width 7 $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:123335.18-123335.113" - wire $and$libresoc.v:123335$4626_Y - attribute \src "libresoc.v:123337.18-123337.110" - wire $and$libresoc.v:123337$4628_Y - attribute \src "libresoc.v:123350.18-123350.114" - wire $and$libresoc.v:123350$4641_Y - attribute \src "libresoc.v:123351.18-123351.116" - wire $and$libresoc.v:123351$4642_Y - attribute \src "libresoc.v:123353.18-123353.114" - wire $and$libresoc.v:123353$4644_Y - attribute \src "libresoc.v:123355.18-123355.110" - wire $and$libresoc.v:123355$4646_Y - attribute \src "libresoc.v:123356.17-123356.112" - wire $and$libresoc.v:123356$4647_Y - attribute \src "libresoc.v:123357.17-123357.114" - wire $and$libresoc.v:123357$4648_Y - attribute \src "libresoc.v:123338.18-123338.127" - wire $eq$libresoc.v:123338$4629_Y - attribute \src "libresoc.v:123339.18-123339.127" - wire $eq$libresoc.v:123339$4630_Y - attribute \src "libresoc.v:123341.18-123341.110" - wire $eq$libresoc.v:123341$4632_Y - attribute \src "libresoc.v:123342.18-123342.110" - wire $eq$libresoc.v:123342$4633_Y - attribute \src "libresoc.v:123344.18-123344.112" - wire $eq$libresoc.v:123344$4635_Y - attribute \src "libresoc.v:123345.17-123345.131" - wire $eq$libresoc.v:123345$4636_Y - attribute \src "libresoc.v:123347.18-123347.110" - wire $eq$libresoc.v:123347$4638_Y - attribute \src "libresoc.v:123349.18-123349.132" - wire $eq$libresoc.v:123349$4640_Y - attribute \src "libresoc.v:123352.18-123352.132" - wire $eq$libresoc.v:123352$4643_Y - attribute \src "libresoc.v:123358.17-123358.131" - wire $eq$libresoc.v:123358$4649_Y - attribute \src "libresoc.v:123336.18-123336.110" - wire $not$libresoc.v:123336$4627_Y - attribute \src "libresoc.v:123354.18-123354.110" - wire $not$libresoc.v:123354$4645_Y - attribute \src "libresoc.v:123340.18-123340.110" - wire $or$libresoc.v:123340$4631_Y - attribute \src "libresoc.v:123343.18-123343.110" - wire $or$libresoc.v:123343$4634_Y - attribute \src "libresoc.v:123346.18-123346.110" - wire $or$libresoc.v:123346$4637_Y - attribute \src "libresoc.v:123348.18-123348.110" - wire $or$libresoc.v:123348$4639_Y + attribute \src "libresoc.v:123131.18-123131.113" + wire $and$libresoc.v:123131$4626_Y + attribute \src "libresoc.v:123133.18-123133.110" + wire $and$libresoc.v:123133$4628_Y + attribute \src "libresoc.v:123146.18-123146.114" + wire $and$libresoc.v:123146$4641_Y + attribute \src "libresoc.v:123147.18-123147.116" + wire $and$libresoc.v:123147$4642_Y + attribute \src "libresoc.v:123149.18-123149.114" + wire $and$libresoc.v:123149$4644_Y + attribute \src "libresoc.v:123151.18-123151.110" + wire $and$libresoc.v:123151$4646_Y + attribute \src "libresoc.v:123152.17-123152.112" + wire $and$libresoc.v:123152$4647_Y + attribute \src "libresoc.v:123153.17-123153.114" + wire $and$libresoc.v:123153$4648_Y + attribute \src "libresoc.v:123134.18-123134.127" + wire $eq$libresoc.v:123134$4629_Y + attribute \src "libresoc.v:123135.18-123135.127" + wire $eq$libresoc.v:123135$4630_Y + attribute \src "libresoc.v:123137.18-123137.110" + wire $eq$libresoc.v:123137$4632_Y + attribute \src "libresoc.v:123138.18-123138.110" + wire $eq$libresoc.v:123138$4633_Y + attribute \src "libresoc.v:123140.18-123140.112" + wire $eq$libresoc.v:123140$4635_Y + attribute \src "libresoc.v:123141.17-123141.131" + wire $eq$libresoc.v:123141$4636_Y + attribute \src "libresoc.v:123143.18-123143.110" + wire $eq$libresoc.v:123143$4638_Y + attribute \src "libresoc.v:123145.18-123145.132" + wire $eq$libresoc.v:123145$4640_Y + attribute \src "libresoc.v:123148.18-123148.132" + wire $eq$libresoc.v:123148$4643_Y + attribute \src "libresoc.v:123154.17-123154.131" + wire $eq$libresoc.v:123154$4649_Y + attribute \src "libresoc.v:123132.18-123132.110" + wire $not$libresoc.v:123132$4627_Y + attribute \src "libresoc.v:123150.18-123150.110" + wire $not$libresoc.v:123150$4645_Y + attribute \src "libresoc.v:123136.18-123136.110" + wire $or$libresoc.v:123136$4631_Y + attribute \src "libresoc.v:123139.18-123139.110" + wire $or$libresoc.v:123139$4634_Y + attribute \src "libresoc.v:123142.18-123142.110" + wire $or$libresoc.v:123142$4637_Y + attribute \src "libresoc.v:123144.18-123144.110" + wire $or$libresoc.v:123144$4639_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" @@ -192123,7 +191919,7 @@ module \dec_LDST attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:122907.7-122907.15" + attribute \src "libresoc.v:122703.7-122703.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in @@ -192140,7 +191936,7 @@ module \dec_LDST attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:123335$4626 + cell $and $and$libresoc.v:123131$4626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192148,10 +191944,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:123335$4626_Y + connect \Y $and$libresoc.v:123131$4626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:123337$4628 + cell $and $and$libresoc.v:123133$4628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192159,10 +191955,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:123337$4628_Y + connect \Y $and$libresoc.v:123133$4628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:123350$4641 + cell $and $and$libresoc.v:123146$4641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192170,10 +191966,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:123350$4641_Y + connect \Y $and$libresoc.v:123146$4641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:123351$4642 + cell $and $and$libresoc.v:123147$4642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192181,10 +191977,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123351$4642_Y + connect \Y $and$libresoc.v:123147$4642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:123353$4644 + cell $and $and$libresoc.v:123149$4644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192192,10 +191988,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:123353$4644_Y + connect \Y $and$libresoc.v:123149$4644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:123355$4646 + cell $and $and$libresoc.v:123151$4646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192203,10 +191999,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:123355$4646_Y + connect \Y $and$libresoc.v:123151$4646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:123356$4647 + cell $and $and$libresoc.v:123152$4647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192214,10 +192010,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:123356$4647_Y + connect \Y $and$libresoc.v:123152$4647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:123357$4648 + cell $and $and$libresoc.v:123153$4648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192225,10 +192021,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123357$4648_Y + connect \Y $and$libresoc.v:123153$4648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" - cell $eq $eq$libresoc.v:123338$4629 + cell $eq $eq$libresoc.v:123134$4629 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192236,10 +192032,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:123338$4629_Y + connect \Y $eq$libresoc.v:123134$4629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $eq $eq$libresoc.v:123339$4630 + cell $eq $eq$libresoc.v:123135$4630 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192247,10 +192043,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:123339$4630_Y + connect \Y $eq$libresoc.v:123135$4630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:123341$4632 + cell $eq $eq$libresoc.v:123137$4632 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192258,10 +192054,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:123341$4632_Y + connect \Y $eq$libresoc.v:123137$4632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:123342$4633 + cell $eq $eq$libresoc.v:123138$4633 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192269,10 +192065,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:123342$4633_Y + connect \Y $eq$libresoc.v:123138$4633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:123344$4635 + cell $eq $eq$libresoc.v:123140$4635 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192280,10 +192076,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:123344$4635_Y + connect \Y $eq$libresoc.v:123140$4635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:123345$4636 + cell $eq $eq$libresoc.v:123141$4636 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192291,10 +192087,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123345$4636_Y + connect \Y $eq$libresoc.v:123141$4636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $eq $eq$libresoc.v:123347$4638 + cell $eq $eq$libresoc.v:123143$4638 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192302,10 +192098,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:123347$4638_Y + connect \Y $eq$libresoc.v:123143$4638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:123349$4640 + cell $eq $eq$libresoc.v:123145$4640 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192313,10 +192109,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123349$4640_Y + connect \Y $eq$libresoc.v:123145$4640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:123352$4643 + cell $eq $eq$libresoc.v:123148$4643 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192324,10 +192120,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123352$4643_Y + connect \Y $eq$libresoc.v:123148$4643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:123358$4649 + cell $eq $eq$libresoc.v:123154$4649 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192335,26 +192131,26 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123358$4649_Y + connect \Y $eq$libresoc.v:123154$4649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:123336$4627 + cell $not $not$libresoc.v:123132$4627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123336$4627_Y + connect \Y $not$libresoc.v:123132$4627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:123354$4645 + cell $not $not$libresoc.v:123150$4645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123354$4645_Y + connect \Y $not$libresoc.v:123150$4645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $or $or$libresoc.v:123340$4631 + cell $or $or$libresoc.v:123136$4631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192362,10 +192158,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:123340$4631_Y + connect \Y $or$libresoc.v:123136$4631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:123343$4634 + cell $or $or$libresoc.v:123139$4634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192373,10 +192169,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:123343$4634_Y + connect \Y $or$libresoc.v:123139$4634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:123346$4637 + cell $or $or$libresoc.v:123142$4637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192384,10 +192180,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:123346$4637_Y + connect \Y $or$libresoc.v:123142$4637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $or $or$libresoc.v:123348$4639 + cell $or $or$libresoc.v:123144$4639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192395,10 +192191,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:123348$4639_Y + connect \Y $or$libresoc.v:123144$4639_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:123359.13-123386.4" + attribute \src "libresoc.v:123155.13-123182.4" cell \dec$166 \dec connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -192428,7 +192224,7 @@ module \dec_LDST connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123387.16-123392.4" + attribute \src "libresoc.v:123183.16-123188.4" cell \dec_ai$169 \dec_ai connect \LDST_RA \dec_LDST_RA connect \immz_out \dec_ai_immz_out @@ -192436,7 +192232,7 @@ module \dec_LDST connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:123393.16-123404.4" + attribute \src "libresoc.v:123189.16-123200.4" cell \dec_bi$170 \dec_bi connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -192450,7 +192246,7 @@ module \dec_LDST connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123405.16-123411.4" + attribute \src "libresoc.v:123201.16-123207.4" cell \dec_oe$168 \dec_oe connect \LDST_OE \dec_LDST_OE connect \LDST_internal_op \dec_LDST_internal_op @@ -192459,29 +192255,29 @@ module \dec_LDST connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123412.16-123417.4" + attribute \src "libresoc.v:123208.16-123213.4" cell \dec_rc$167 \dec_rc connect \LDST_Rc \dec_LDST_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:122907.7-122907.20" - process $proc$libresoc.v:122907$4652 + attribute \src "libresoc.v:122703.7-122703.20" + process $proc$libresoc.v:122703$4652 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123418.3-123430.6" - process $proc$libresoc.v:123418$4650 + attribute \src "libresoc.v:123214.3-123226.6" + process $proc$libresoc.v:123214$4650 assign { } { } assign { } { } assign $0\LDST__insn_type[6:0] $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:123419.5-123419.29" + attribute \src "libresoc.v:123215.5-123215.29" switch \initial - attribute \src "libresoc.v:123419.9-123419.17" + attribute \src "libresoc.v:123215.9-123215.17" case 1'1 case end @@ -192501,13 +192297,13 @@ module \dec_LDST sync always update \LDST__insn_type $0\LDST__insn_type[6:0] end - attribute \src "libresoc.v:123431.3-123445.6" - process $proc$libresoc.v:123431$4651 + attribute \src "libresoc.v:123227.3-123241.6" + process $proc$libresoc.v:123227$4651 assign { } { } assign $0\LDST__fn_unit[13:0] $1\LDST__fn_unit[13:0] - attribute \src "libresoc.v:123432.5-123432.29" + attribute \src "libresoc.v:123228.5-123228.29" switch \initial - attribute \src "libresoc.v:123432.9-123432.17" + attribute \src "libresoc.v:123228.9-123228.17" case 1'1 case end @@ -192529,30 +192325,30 @@ module \dec_LDST sync always update \LDST__fn_unit $0\LDST__fn_unit[13:0] end - connect \$10 $and$libresoc.v:123335$4626_Y - connect \$12 $not$libresoc.v:123336$4627_Y - connect \$14 $and$libresoc.v:123337$4628_Y - connect \$16 $eq$libresoc.v:123338$4629_Y - connect \$18 $eq$libresoc.v:123339$4630_Y - connect \$20 $or$libresoc.v:123340$4631_Y - connect \$22 $eq$libresoc.v:123341$4632_Y - connect \$24 $eq$libresoc.v:123342$4633_Y - connect \$26 $or$libresoc.v:123343$4634_Y - connect \$28 $eq$libresoc.v:123344$4635_Y - connect \$2 $eq$libresoc.v:123345$4636_Y - connect \$30 $or$libresoc.v:123346$4637_Y - connect \$32 $eq$libresoc.v:123347$4638_Y - connect \$34 $or$libresoc.v:123348$4639_Y - connect \$36 $eq$libresoc.v:123349$4640_Y - connect \$38 $and$libresoc.v:123350$4641_Y - connect \$40 $and$libresoc.v:123351$4642_Y - connect \$42 $eq$libresoc.v:123352$4643_Y - connect \$44 $and$libresoc.v:123353$4644_Y - connect \$46 $not$libresoc.v:123354$4645_Y - connect \$48 $and$libresoc.v:123355$4646_Y - connect \$4 $and$libresoc.v:123356$4647_Y - connect \$6 $and$libresoc.v:123357$4648_Y - connect \$8 $eq$libresoc.v:123358$4649_Y + connect \$10 $and$libresoc.v:123131$4626_Y + connect \$12 $not$libresoc.v:123132$4627_Y + connect \$14 $and$libresoc.v:123133$4628_Y + connect \$16 $eq$libresoc.v:123134$4629_Y + connect \$18 $eq$libresoc.v:123135$4630_Y + connect \$20 $or$libresoc.v:123136$4631_Y + connect \$22 $eq$libresoc.v:123137$4632_Y + connect \$24 $eq$libresoc.v:123138$4633_Y + connect \$26 $or$libresoc.v:123139$4634_Y + connect \$28 $eq$libresoc.v:123140$4635_Y + connect \$2 $eq$libresoc.v:123141$4636_Y + connect \$30 $or$libresoc.v:123142$4637_Y + connect \$32 $eq$libresoc.v:123143$4638_Y + connect \$34 $or$libresoc.v:123144$4639_Y + connect \$36 $eq$libresoc.v:123145$4640_Y + connect \$38 $and$libresoc.v:123146$4641_Y + connect \$40 $and$libresoc.v:123147$4642_Y + connect \$42 $eq$libresoc.v:123148$4643_Y + connect \$44 $and$libresoc.v:123149$4644_Y + connect \$46 $not$libresoc.v:123150$4645_Y + connect \$48 $and$libresoc.v:123151$4646_Y + connect \$4 $and$libresoc.v:123152$4647_Y + connect \$6 $and$libresoc.v:123153$4648_Y + connect \$8 $eq$libresoc.v:123154$4649_Y connect \LDST__ldst_mode \dec_LDST_upd connect \LDST__sign_extend \dec_LDST_sgn_ext connect \LDST__byte_reverse \dec_LDST_br @@ -192575,73 +192371,73 @@ module \dec_LDST connect \insn_in \dec_opcode_in connect \LDST__insn \dec_opcode_in end -attribute \src "libresoc.v:123471.1-124054.10" +attribute \src "libresoc.v:123267.1-123850.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" attribute \generator "nMigen" module \dec_LOGICAL - attribute \src "libresoc.v:124017.3-124031.6" + attribute \src "libresoc.v:123813.3-123827.6" wire width 14 $0\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:124004.3-124016.6" + attribute \src "libresoc.v:123800.3-123812.6" wire width 7 $0\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:123989.3-124003.6" + attribute \src "libresoc.v:123785.3-123799.6" wire $0\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:123472.7-123472.20" + attribute \src "libresoc.v:123268.7-123268.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124017.3-124031.6" + attribute \src "libresoc.v:123813.3-123827.6" wire width 14 $1\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:124004.3-124016.6" + attribute \src "libresoc.v:123800.3-123812.6" wire width 7 $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:123989.3-124003.6" + attribute \src "libresoc.v:123785.3-123799.6" wire $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:123905.18-123905.113" - wire $and$libresoc.v:123905$4653_Y - attribute \src "libresoc.v:123907.18-123907.110" - wire $and$libresoc.v:123907$4655_Y - attribute \src "libresoc.v:123920.18-123920.114" - wire $and$libresoc.v:123920$4668_Y - attribute \src "libresoc.v:123921.18-123921.116" - wire $and$libresoc.v:123921$4669_Y - attribute \src "libresoc.v:123923.18-123923.114" - wire $and$libresoc.v:123923$4671_Y - attribute \src "libresoc.v:123925.18-123925.110" - wire $and$libresoc.v:123925$4673_Y - attribute \src "libresoc.v:123926.17-123926.112" - wire $and$libresoc.v:123926$4674_Y - attribute \src "libresoc.v:123927.17-123927.114" - wire $and$libresoc.v:123927$4675_Y - attribute \src "libresoc.v:123908.18-123908.130" - wire $eq$libresoc.v:123908$4656_Y - attribute \src "libresoc.v:123909.18-123909.130" - wire $eq$libresoc.v:123909$4657_Y - attribute \src "libresoc.v:123911.18-123911.110" - wire $eq$libresoc.v:123911$4659_Y - attribute \src "libresoc.v:123912.18-123912.110" - wire $eq$libresoc.v:123912$4660_Y - attribute \src "libresoc.v:123914.18-123914.112" - wire $eq$libresoc.v:123914$4662_Y - attribute \src "libresoc.v:123915.17-123915.134" - wire $eq$libresoc.v:123915$4663_Y - attribute \src "libresoc.v:123917.18-123917.110" - wire $eq$libresoc.v:123917$4665_Y - attribute \src "libresoc.v:123919.18-123919.135" - wire $eq$libresoc.v:123919$4667_Y - attribute \src "libresoc.v:123922.18-123922.135" - wire $eq$libresoc.v:123922$4670_Y - attribute \src "libresoc.v:123928.17-123928.134" - wire $eq$libresoc.v:123928$4676_Y - attribute \src "libresoc.v:123906.18-123906.110" - wire $not$libresoc.v:123906$4654_Y - attribute \src "libresoc.v:123924.18-123924.110" - wire $not$libresoc.v:123924$4672_Y - attribute \src "libresoc.v:123910.18-123910.110" - wire $or$libresoc.v:123910$4658_Y - attribute \src "libresoc.v:123913.18-123913.110" - wire $or$libresoc.v:123913$4661_Y - attribute \src "libresoc.v:123916.18-123916.110" - wire $or$libresoc.v:123916$4664_Y - attribute \src "libresoc.v:123918.18-123918.110" - wire $or$libresoc.v:123918$4666_Y + attribute \src "libresoc.v:123701.18-123701.113" + wire $and$libresoc.v:123701$4653_Y + attribute \src "libresoc.v:123703.18-123703.110" + wire $and$libresoc.v:123703$4655_Y + attribute \src "libresoc.v:123716.18-123716.114" + wire $and$libresoc.v:123716$4668_Y + attribute \src "libresoc.v:123717.18-123717.116" + wire $and$libresoc.v:123717$4669_Y + attribute \src "libresoc.v:123719.18-123719.114" + wire $and$libresoc.v:123719$4671_Y + attribute \src "libresoc.v:123721.18-123721.110" + wire $and$libresoc.v:123721$4673_Y + attribute \src "libresoc.v:123722.17-123722.112" + wire $and$libresoc.v:123722$4674_Y + attribute \src "libresoc.v:123723.17-123723.114" + wire $and$libresoc.v:123723$4675_Y + attribute \src "libresoc.v:123704.18-123704.130" + wire $eq$libresoc.v:123704$4656_Y + attribute \src "libresoc.v:123705.18-123705.130" + wire $eq$libresoc.v:123705$4657_Y + attribute \src "libresoc.v:123707.18-123707.110" + wire $eq$libresoc.v:123707$4659_Y + attribute \src "libresoc.v:123708.18-123708.110" + wire $eq$libresoc.v:123708$4660_Y + attribute \src "libresoc.v:123710.18-123710.112" + wire $eq$libresoc.v:123710$4662_Y + attribute \src "libresoc.v:123711.17-123711.134" + wire $eq$libresoc.v:123711$4663_Y + attribute \src "libresoc.v:123713.18-123713.110" + wire $eq$libresoc.v:123713$4665_Y + attribute \src "libresoc.v:123715.18-123715.135" + wire $eq$libresoc.v:123715$4667_Y + attribute \src "libresoc.v:123718.18-123718.135" + wire $eq$libresoc.v:123718$4670_Y + attribute \src "libresoc.v:123724.17-123724.134" + wire $eq$libresoc.v:123724$4676_Y + attribute \src "libresoc.v:123702.18-123702.110" + wire $not$libresoc.v:123702$4654_Y + attribute \src "libresoc.v:123720.18-123720.110" + wire $not$libresoc.v:123720$4672_Y + attribute \src "libresoc.v:123706.18-123706.110" + wire $or$libresoc.v:123706$4658_Y + attribute \src "libresoc.v:123709.18-123709.110" + wire $or$libresoc.v:123709$4661_Y + attribute \src "libresoc.v:123712.18-123712.110" + wire $or$libresoc.v:123712$4664_Y + attribute \src "libresoc.v:123714.18-123714.110" + wire $or$libresoc.v:123714$4666_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" @@ -193057,7 +192853,7 @@ module \dec_LOGICAL attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:123472.7-123472.15" + attribute \src "libresoc.v:123268.7-123268.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in @@ -193074,7 +192870,7 @@ module \dec_LOGICAL attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:123905$4653 + cell $and $and$libresoc.v:123701$4653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193082,10 +192878,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:123905$4653_Y + connect \Y $and$libresoc.v:123701$4653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:123907$4655 + cell $and $and$libresoc.v:123703$4655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193093,10 +192889,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:123907$4655_Y + connect \Y $and$libresoc.v:123703$4655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:123920$4668 + cell $and $and$libresoc.v:123716$4668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193104,10 +192900,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:123920$4668_Y + connect \Y $and$libresoc.v:123716$4668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:123921$4669 + cell $and $and$libresoc.v:123717$4669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193115,10 +192911,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123921$4669_Y + connect \Y $and$libresoc.v:123717$4669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:123923$4671 + cell $and $and$libresoc.v:123719$4671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193126,10 +192922,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:123923$4671_Y + connect \Y $and$libresoc.v:123719$4671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:123925$4673 + cell $and $and$libresoc.v:123721$4673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193137,10 +192933,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:123925$4673_Y + connect \Y $and$libresoc.v:123721$4673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:123926$4674 + cell $and $and$libresoc.v:123722$4674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193148,10 +192944,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:123926$4674_Y + connect \Y $and$libresoc.v:123722$4674_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:123927$4675 + cell $and $and$libresoc.v:123723$4675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193159,10 +192955,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123927$4675_Y + connect \Y $and$libresoc.v:123723$4675_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" - cell $eq $eq$libresoc.v:123908$4656 + cell $eq $eq$libresoc.v:123704$4656 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193170,10 +192966,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:123908$4656_Y + connect \Y $eq$libresoc.v:123704$4656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $eq $eq$libresoc.v:123909$4657 + cell $eq $eq$libresoc.v:123705$4657 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193181,10 +192977,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:123909$4657_Y + connect \Y $eq$libresoc.v:123705$4657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:123911$4659 + cell $eq $eq$libresoc.v:123707$4659 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193192,10 +192988,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:123911$4659_Y + connect \Y $eq$libresoc.v:123707$4659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:123912$4660 + cell $eq $eq$libresoc.v:123708$4660 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193203,10 +192999,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:123912$4660_Y + connect \Y $eq$libresoc.v:123708$4660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:123914$4662 + cell $eq $eq$libresoc.v:123710$4662 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193214,10 +193010,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:123914$4662_Y + connect \Y $eq$libresoc.v:123710$4662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:123915$4663 + cell $eq $eq$libresoc.v:123711$4663 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193225,10 +193021,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123915$4663_Y + connect \Y $eq$libresoc.v:123711$4663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $eq $eq$libresoc.v:123917$4665 + cell $eq $eq$libresoc.v:123713$4665 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193236,10 +193032,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:123917$4665_Y + connect \Y $eq$libresoc.v:123713$4665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:123919$4667 + cell $eq $eq$libresoc.v:123715$4667 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193247,10 +193043,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123919$4667_Y + connect \Y $eq$libresoc.v:123715$4667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:123922$4670 + cell $eq $eq$libresoc.v:123718$4670 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193258,10 +193054,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123922$4670_Y + connect \Y $eq$libresoc.v:123718$4670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:123928$4676 + cell $eq $eq$libresoc.v:123724$4676 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193269,26 +193065,26 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123928$4676_Y + connect \Y $eq$libresoc.v:123724$4676_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:123906$4654 + cell $not $not$libresoc.v:123702$4654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123906$4654_Y + connect \Y $not$libresoc.v:123702$4654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:123924$4672 + cell $not $not$libresoc.v:123720$4672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123924$4672_Y + connect \Y $not$libresoc.v:123720$4672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $or $or$libresoc.v:123910$4658 + cell $or $or$libresoc.v:123706$4658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193296,10 +193092,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:123910$4658_Y + connect \Y $or$libresoc.v:123706$4658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:123913$4661 + cell $or $or$libresoc.v:123709$4661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193307,10 +193103,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:123913$4661_Y + connect \Y $or$libresoc.v:123709$4661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:123916$4664 + cell $or $or$libresoc.v:123712$4664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193318,10 +193114,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:123916$4664_Y + connect \Y $or$libresoc.v:123712$4664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $or $or$libresoc.v:123918$4666 + cell $or $or$libresoc.v:123714$4666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193329,10 +193125,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:123918$4666_Y + connect \Y $or$libresoc.v:123714$4666_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:123929.13-123957.4" + attribute \src "libresoc.v:123725.13-123753.4" cell \dec$145 \dec connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -193363,7 +193159,7 @@ module \dec_LOGICAL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123958.16-123963.4" + attribute \src "libresoc.v:123754.16-123759.4" cell \dec_ai$148 \dec_ai connect \LOGICAL_RA \dec_LOGICAL_RA connect \immz_out \dec_ai_immz_out @@ -193371,7 +193167,7 @@ module \dec_LOGICAL connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:123964.16-123975.4" + attribute \src "libresoc.v:123760.16-123771.4" cell \dec_bi$149 \dec_bi connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -193385,7 +193181,7 @@ module \dec_LOGICAL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123976.16-123982.4" + attribute \src "libresoc.v:123772.16-123778.4" cell \dec_oe$147 \dec_oe connect \LOGICAL_OE \dec_LOGICAL_OE connect \LOGICAL_internal_op \dec_LOGICAL_internal_op @@ -193394,29 +193190,29 @@ module \dec_LOGICAL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123983.16-123988.4" + attribute \src "libresoc.v:123779.16-123784.4" cell \dec_rc$146 \dec_rc connect \LOGICAL_Rc \dec_LOGICAL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:123472.7-123472.20" - process $proc$libresoc.v:123472$4680 + attribute \src "libresoc.v:123268.7-123268.20" + process $proc$libresoc.v:123268$4680 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123989.3-124003.6" - process $proc$libresoc.v:123989$4677 + attribute \src "libresoc.v:123785.3-123799.6" + process $proc$libresoc.v:123785$4677 assign { } { } assign { } { } assign $0\LOGICAL__write_cr0[0:0] $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:123990.5-123990.29" + attribute \src "libresoc.v:123786.5-123786.29" switch \initial - attribute \src "libresoc.v:123990.9-123990.17" + attribute \src "libresoc.v:123786.9-123786.17" case 1'1 case end @@ -193436,14 +193232,14 @@ module \dec_LOGICAL sync always update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0] end - attribute \src "libresoc.v:124004.3-124016.6" - process $proc$libresoc.v:124004$4678 + attribute \src "libresoc.v:123800.3-123812.6" + process $proc$libresoc.v:123800$4678 assign { } { } assign { } { } assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:124005.5-124005.29" + attribute \src "libresoc.v:123801.5-123801.29" switch \initial - attribute \src "libresoc.v:124005.9-124005.17" + attribute \src "libresoc.v:123801.9-123801.17" case 1'1 case end @@ -193463,13 +193259,13 @@ module \dec_LOGICAL sync always update \LOGICAL__insn_type $0\LOGICAL__insn_type[6:0] end - attribute \src "libresoc.v:124017.3-124031.6" - process $proc$libresoc.v:124017$4679 + attribute \src "libresoc.v:123813.3-123827.6" + process $proc$libresoc.v:123813$4679 assign { } { } assign $0\LOGICAL__fn_unit[13:0] $1\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:124018.5-124018.29" + attribute \src "libresoc.v:123814.5-123814.29" switch \initial - attribute \src "libresoc.v:124018.9-124018.17" + attribute \src "libresoc.v:123814.9-123814.17" case 1'1 case end @@ -193491,30 +193287,30 @@ module \dec_LOGICAL sync always update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[13:0] end - connect \$10 $and$libresoc.v:123905$4653_Y - connect \$12 $not$libresoc.v:123906$4654_Y - connect \$14 $and$libresoc.v:123907$4655_Y - connect \$16 $eq$libresoc.v:123908$4656_Y - connect \$18 $eq$libresoc.v:123909$4657_Y - connect \$20 $or$libresoc.v:123910$4658_Y - connect \$22 $eq$libresoc.v:123911$4659_Y - connect \$24 $eq$libresoc.v:123912$4660_Y - connect \$26 $or$libresoc.v:123913$4661_Y - connect \$28 $eq$libresoc.v:123914$4662_Y - connect \$2 $eq$libresoc.v:123915$4663_Y - connect \$30 $or$libresoc.v:123916$4664_Y - connect \$32 $eq$libresoc.v:123917$4665_Y - connect \$34 $or$libresoc.v:123918$4666_Y - connect \$36 $eq$libresoc.v:123919$4667_Y - connect \$38 $and$libresoc.v:123920$4668_Y - connect \$40 $and$libresoc.v:123921$4669_Y - connect \$42 $eq$libresoc.v:123922$4670_Y - connect \$44 $and$libresoc.v:123923$4671_Y - connect \$46 $not$libresoc.v:123924$4672_Y - connect \$48 $and$libresoc.v:123925$4673_Y - connect \$4 $and$libresoc.v:123926$4674_Y - connect \$6 $and$libresoc.v:123927$4675_Y - connect \$8 $eq$libresoc.v:123928$4676_Y + connect \$10 $and$libresoc.v:123701$4653_Y + connect \$12 $not$libresoc.v:123702$4654_Y + connect \$14 $and$libresoc.v:123703$4655_Y + connect \$16 $eq$libresoc.v:123704$4656_Y + connect \$18 $eq$libresoc.v:123705$4657_Y + connect \$20 $or$libresoc.v:123706$4658_Y + connect \$22 $eq$libresoc.v:123707$4659_Y + connect \$24 $eq$libresoc.v:123708$4660_Y + connect \$26 $or$libresoc.v:123709$4661_Y + connect \$28 $eq$libresoc.v:123710$4662_Y + connect \$2 $eq$libresoc.v:123711$4663_Y + connect \$30 $or$libresoc.v:123712$4664_Y + connect \$32 $eq$libresoc.v:123713$4665_Y + connect \$34 $or$libresoc.v:123714$4666_Y + connect \$36 $eq$libresoc.v:123715$4667_Y + connect \$38 $and$libresoc.v:123716$4668_Y + connect \$40 $and$libresoc.v:123717$4669_Y + connect \$42 $eq$libresoc.v:123718$4670_Y + connect \$44 $and$libresoc.v:123719$4671_Y + connect \$46 $not$libresoc.v:123720$4672_Y + connect \$48 $and$libresoc.v:123721$4673_Y + connect \$4 $and$libresoc.v:123722$4674_Y + connect \$6 $and$libresoc.v:123723$4675_Y + connect \$8 $eq$libresoc.v:123724$4676_Y connect \LOGICAL__is_signed \dec_LOGICAL_sgn connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b connect \LOGICAL__output_carry \dec_LOGICAL_cry_out @@ -193538,73 +193334,73 @@ module \dec_LOGICAL connect \insn_in \dec_opcode_in connect \LOGICAL__insn \dec_opcode_in end -attribute \src "libresoc.v:124058.1-124560.10" +attribute \src "libresoc.v:123854.1-124356.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" attribute \generator "nMigen" module \dec_MUL - attribute \src "libresoc.v:124531.3-124545.6" + attribute \src "libresoc.v:124327.3-124341.6" wire width 14 $0\MUL__fn_unit[13:0] - attribute \src "libresoc.v:124518.3-124530.6" + attribute \src "libresoc.v:124314.3-124326.6" wire width 7 $0\MUL__insn_type[6:0] - attribute \src "libresoc.v:124503.3-124517.6" + attribute \src "libresoc.v:124299.3-124313.6" wire $0\MUL__write_cr0[0:0] - attribute \src "libresoc.v:124059.7-124059.20" + attribute \src "libresoc.v:123855.7-123855.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124531.3-124545.6" + attribute \src "libresoc.v:124327.3-124341.6" wire width 14 $1\MUL__fn_unit[13:0] - attribute \src "libresoc.v:124518.3-124530.6" + attribute \src "libresoc.v:124314.3-124326.6" wire width 7 $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:124503.3-124517.6" + attribute \src "libresoc.v:124299.3-124313.6" wire $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:124432.18-124432.113" - wire $and$libresoc.v:124432$4681_Y - attribute \src "libresoc.v:124434.18-124434.110" - wire $and$libresoc.v:124434$4683_Y - attribute \src "libresoc.v:124447.18-124447.114" - wire $and$libresoc.v:124447$4696_Y - attribute \src "libresoc.v:124448.18-124448.116" - wire $and$libresoc.v:124448$4697_Y - attribute \src "libresoc.v:124450.18-124450.114" - wire $and$libresoc.v:124450$4699_Y - attribute \src "libresoc.v:124452.18-124452.110" - wire $and$libresoc.v:124452$4701_Y - attribute \src "libresoc.v:124453.17-124453.112" - wire $and$libresoc.v:124453$4702_Y - attribute \src "libresoc.v:124454.17-124454.114" - wire $and$libresoc.v:124454$4703_Y - attribute \src "libresoc.v:124435.18-124435.126" - wire $eq$libresoc.v:124435$4684_Y - attribute \src "libresoc.v:124436.18-124436.126" - wire $eq$libresoc.v:124436$4685_Y - attribute \src "libresoc.v:124438.18-124438.110" - wire $eq$libresoc.v:124438$4687_Y - attribute \src "libresoc.v:124439.18-124439.110" - wire $eq$libresoc.v:124439$4688_Y - attribute \src "libresoc.v:124441.18-124441.112" - wire $eq$libresoc.v:124441$4690_Y - attribute \src "libresoc.v:124442.17-124442.130" - wire $eq$libresoc.v:124442$4691_Y - attribute \src "libresoc.v:124444.18-124444.110" - wire $eq$libresoc.v:124444$4693_Y - attribute \src "libresoc.v:124446.18-124446.131" - wire $eq$libresoc.v:124446$4695_Y - attribute \src "libresoc.v:124449.18-124449.131" - wire $eq$libresoc.v:124449$4698_Y - attribute \src "libresoc.v:124455.17-124455.130" - wire $eq$libresoc.v:124455$4704_Y - attribute \src "libresoc.v:124433.18-124433.110" - wire $not$libresoc.v:124433$4682_Y - attribute \src "libresoc.v:124451.18-124451.110" - wire $not$libresoc.v:124451$4700_Y - attribute \src "libresoc.v:124437.18-124437.110" - wire $or$libresoc.v:124437$4686_Y - attribute \src "libresoc.v:124440.18-124440.110" - wire $or$libresoc.v:124440$4689_Y - attribute \src "libresoc.v:124443.18-124443.110" - wire $or$libresoc.v:124443$4692_Y - attribute \src "libresoc.v:124445.18-124445.110" - wire $or$libresoc.v:124445$4694_Y + attribute \src "libresoc.v:124228.18-124228.113" + wire $and$libresoc.v:124228$4681_Y + attribute \src "libresoc.v:124230.18-124230.110" + wire $and$libresoc.v:124230$4683_Y + attribute \src "libresoc.v:124243.18-124243.114" + wire $and$libresoc.v:124243$4696_Y + attribute \src "libresoc.v:124244.18-124244.116" + wire $and$libresoc.v:124244$4697_Y + attribute \src "libresoc.v:124246.18-124246.114" + wire $and$libresoc.v:124246$4699_Y + attribute \src "libresoc.v:124248.18-124248.110" + wire $and$libresoc.v:124248$4701_Y + attribute \src "libresoc.v:124249.17-124249.112" + wire $and$libresoc.v:124249$4702_Y + attribute \src "libresoc.v:124250.17-124250.114" + wire $and$libresoc.v:124250$4703_Y + attribute \src "libresoc.v:124231.18-124231.126" + wire $eq$libresoc.v:124231$4684_Y + attribute \src "libresoc.v:124232.18-124232.126" + wire $eq$libresoc.v:124232$4685_Y + attribute \src "libresoc.v:124234.18-124234.110" + wire $eq$libresoc.v:124234$4687_Y + attribute \src "libresoc.v:124235.18-124235.110" + wire $eq$libresoc.v:124235$4688_Y + attribute \src "libresoc.v:124237.18-124237.112" + wire $eq$libresoc.v:124237$4690_Y + attribute \src "libresoc.v:124238.17-124238.130" + wire $eq$libresoc.v:124238$4691_Y + attribute \src "libresoc.v:124240.18-124240.110" + wire $eq$libresoc.v:124240$4693_Y + attribute \src "libresoc.v:124242.18-124242.131" + wire $eq$libresoc.v:124242$4695_Y + attribute \src "libresoc.v:124245.18-124245.131" + wire $eq$libresoc.v:124245$4698_Y + attribute \src "libresoc.v:124251.17-124251.130" + wire $eq$libresoc.v:124251$4704_Y + attribute \src "libresoc.v:124229.18-124229.110" + wire $not$libresoc.v:124229$4682_Y + attribute \src "libresoc.v:124247.18-124247.110" + wire $not$libresoc.v:124247$4700_Y + attribute \src "libresoc.v:124233.18-124233.110" + wire $or$libresoc.v:124233$4686_Y + attribute \src "libresoc.v:124236.18-124236.110" + wire $or$libresoc.v:124236$4689_Y + attribute \src "libresoc.v:124239.18-124239.110" + wire $or$libresoc.v:124239$4692_Y + attribute \src "libresoc.v:124241.18-124241.110" + wire $or$libresoc.v:124241$4694_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" @@ -193962,7 +193758,7 @@ module \dec_MUL attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:124059.7-124059.15" + attribute \src "libresoc.v:123855.7-123855.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in @@ -193977,7 +193773,7 @@ module \dec_MUL attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:124432$4681 + cell $and $and$libresoc.v:124228$4681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193985,10 +193781,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:124432$4681_Y + connect \Y $and$libresoc.v:124228$4681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:124434$4683 + cell $and $and$libresoc.v:124230$4683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193996,10 +193792,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:124434$4683_Y + connect \Y $and$libresoc.v:124230$4683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:124447$4696 + cell $and $and$libresoc.v:124243$4696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194007,10 +193803,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:124447$4696_Y + connect \Y $and$libresoc.v:124243$4696_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:124448$4697 + cell $and $and$libresoc.v:124244$4697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194018,10 +193814,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124448$4697_Y + connect \Y $and$libresoc.v:124244$4697_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:124450$4699 + cell $and $and$libresoc.v:124246$4699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194029,10 +193825,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:124450$4699_Y + connect \Y $and$libresoc.v:124246$4699_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:124452$4701 + cell $and $and$libresoc.v:124248$4701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194040,10 +193836,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:124452$4701_Y + connect \Y $and$libresoc.v:124248$4701_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:124453$4702 + cell $and $and$libresoc.v:124249$4702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194051,10 +193847,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:124453$4702_Y + connect \Y $and$libresoc.v:124249$4702_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:124454$4703 + cell $and $and$libresoc.v:124250$4703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194062,10 +193858,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124454$4703_Y + connect \Y $and$libresoc.v:124250$4703_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" - cell $eq $eq$libresoc.v:124435$4684 + cell $eq $eq$libresoc.v:124231$4684 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -194073,10 +193869,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:124435$4684_Y + connect \Y $eq$libresoc.v:124231$4684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $eq $eq$libresoc.v:124436$4685 + cell $eq $eq$libresoc.v:124232$4685 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -194084,10 +193880,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:124436$4685_Y + connect \Y $eq$libresoc.v:124232$4685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:124438$4687 + cell $eq $eq$libresoc.v:124234$4687 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194095,10 +193891,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:124438$4687_Y + connect \Y $eq$libresoc.v:124234$4687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:124439$4688 + cell $eq $eq$libresoc.v:124235$4688 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194106,10 +193902,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:124439$4688_Y + connect \Y $eq$libresoc.v:124235$4688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:124441$4690 + cell $eq $eq$libresoc.v:124237$4690 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194117,10 +193913,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:124441$4690_Y + connect \Y $eq$libresoc.v:124237$4690_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:124442$4691 + cell $eq $eq$libresoc.v:124238$4691 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194128,10 +193924,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124442$4691_Y + connect \Y $eq$libresoc.v:124238$4691_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $eq $eq$libresoc.v:124444$4693 + cell $eq $eq$libresoc.v:124240$4693 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194139,10 +193935,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:124444$4693_Y + connect \Y $eq$libresoc.v:124240$4693_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:124446$4695 + cell $eq $eq$libresoc.v:124242$4695 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194150,10 +193946,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124446$4695_Y + connect \Y $eq$libresoc.v:124242$4695_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:124449$4698 + cell $eq $eq$libresoc.v:124245$4698 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194161,10 +193957,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124449$4698_Y + connect \Y $eq$libresoc.v:124245$4698_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:124455$4704 + cell $eq $eq$libresoc.v:124251$4704 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194172,26 +193968,26 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124455$4704_Y + connect \Y $eq$libresoc.v:124251$4704_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:124433$4682 + cell $not $not$libresoc.v:124229$4682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124433$4682_Y + connect \Y $not$libresoc.v:124229$4682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:124451$4700 + cell $not $not$libresoc.v:124247$4700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124451$4700_Y + connect \Y $not$libresoc.v:124247$4700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $or $or$libresoc.v:124437$4686 + cell $or $or$libresoc.v:124233$4686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194199,10 +193995,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:124437$4686_Y + connect \Y $or$libresoc.v:124233$4686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:124440$4689 + cell $or $or$libresoc.v:124236$4689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194210,10 +194006,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:124440$4689_Y + connect \Y $or$libresoc.v:124236$4689_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:124443$4692 + cell $or $or$libresoc.v:124239$4692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194221,10 +194017,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:124443$4692_Y + connect \Y $or$libresoc.v:124239$4692_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $or $or$libresoc.v:124445$4694 + cell $or $or$libresoc.v:124241$4694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194232,10 +194028,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:124445$4694_Y + connect \Y $or$libresoc.v:124241$4694_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:124456.13-124477.4" + attribute \src "libresoc.v:124252.13-124273.4" cell \dec$158 \dec connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -194259,7 +194055,7 @@ module \dec_MUL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124478.16-124489.4" + attribute \src "libresoc.v:124274.16-124285.4" cell \dec_bi$161 \dec_bi connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -194273,7 +194069,7 @@ module \dec_MUL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124490.16-124496.4" + attribute \src "libresoc.v:124286.16-124292.4" cell \dec_oe$160 \dec_oe connect \MUL_OE \dec_MUL_OE connect \MUL_internal_op \dec_MUL_internal_op @@ -194282,29 +194078,29 @@ module \dec_MUL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124497.16-124502.4" + attribute \src "libresoc.v:124293.16-124298.4" cell \dec_rc$159 \dec_rc connect \MUL_Rc \dec_MUL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:124059.7-124059.20" - process $proc$libresoc.v:124059$4708 + attribute \src "libresoc.v:123855.7-123855.20" + process $proc$libresoc.v:123855$4708 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124503.3-124517.6" - process $proc$libresoc.v:124503$4705 + attribute \src "libresoc.v:124299.3-124313.6" + process $proc$libresoc.v:124299$4705 assign { } { } assign { } { } assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:124504.5-124504.29" + attribute \src "libresoc.v:124300.5-124300.29" switch \initial - attribute \src "libresoc.v:124504.9-124504.17" + attribute \src "libresoc.v:124300.9-124300.17" case 1'1 case end @@ -194324,14 +194120,14 @@ module \dec_MUL sync always update \MUL__write_cr0 $0\MUL__write_cr0[0:0] end - attribute \src "libresoc.v:124518.3-124530.6" - process $proc$libresoc.v:124518$4706 + attribute \src "libresoc.v:124314.3-124326.6" + process $proc$libresoc.v:124314$4706 assign { } { } assign { } { } assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:124519.5-124519.29" + attribute \src "libresoc.v:124315.5-124315.29" switch \initial - attribute \src "libresoc.v:124519.9-124519.17" + attribute \src "libresoc.v:124315.9-124315.17" case 1'1 case end @@ -194351,13 +194147,13 @@ module \dec_MUL sync always update \MUL__insn_type $0\MUL__insn_type[6:0] end - attribute \src "libresoc.v:124531.3-124545.6" - process $proc$libresoc.v:124531$4707 + attribute \src "libresoc.v:124327.3-124341.6" + process $proc$libresoc.v:124327$4707 assign { } { } assign $0\MUL__fn_unit[13:0] $1\MUL__fn_unit[13:0] - attribute \src "libresoc.v:124532.5-124532.29" + attribute \src "libresoc.v:124328.5-124328.29" switch \initial - attribute \src "libresoc.v:124532.9-124532.17" + attribute \src "libresoc.v:124328.9-124328.17" case 1'1 case end @@ -194379,30 +194175,30 @@ module \dec_MUL sync always update \MUL__fn_unit $0\MUL__fn_unit[13:0] end - connect \$10 $and$libresoc.v:124432$4681_Y - connect \$12 $not$libresoc.v:124433$4682_Y - connect \$14 $and$libresoc.v:124434$4683_Y - connect \$16 $eq$libresoc.v:124435$4684_Y - connect \$18 $eq$libresoc.v:124436$4685_Y - connect \$20 $or$libresoc.v:124437$4686_Y - connect \$22 $eq$libresoc.v:124438$4687_Y - connect \$24 $eq$libresoc.v:124439$4688_Y - connect \$26 $or$libresoc.v:124440$4689_Y - connect \$28 $eq$libresoc.v:124441$4690_Y - connect \$2 $eq$libresoc.v:124442$4691_Y - connect \$30 $or$libresoc.v:124443$4692_Y - connect \$32 $eq$libresoc.v:124444$4693_Y - connect \$34 $or$libresoc.v:124445$4694_Y - connect \$36 $eq$libresoc.v:124446$4695_Y - connect \$38 $and$libresoc.v:124447$4696_Y - connect \$40 $and$libresoc.v:124448$4697_Y - connect \$42 $eq$libresoc.v:124449$4698_Y - connect \$44 $and$libresoc.v:124450$4699_Y - connect \$46 $not$libresoc.v:124451$4700_Y - connect \$48 $and$libresoc.v:124452$4701_Y - connect \$4 $and$libresoc.v:124453$4702_Y - connect \$6 $and$libresoc.v:124454$4703_Y - connect \$8 $eq$libresoc.v:124455$4704_Y + connect \$10 $and$libresoc.v:124228$4681_Y + connect \$12 $not$libresoc.v:124229$4682_Y + connect \$14 $and$libresoc.v:124230$4683_Y + connect \$16 $eq$libresoc.v:124231$4684_Y + connect \$18 $eq$libresoc.v:124232$4685_Y + connect \$20 $or$libresoc.v:124233$4686_Y + connect \$22 $eq$libresoc.v:124234$4687_Y + connect \$24 $eq$libresoc.v:124235$4688_Y + connect \$26 $or$libresoc.v:124236$4689_Y + connect \$28 $eq$libresoc.v:124237$4690_Y + connect \$2 $eq$libresoc.v:124238$4691_Y + connect \$30 $or$libresoc.v:124239$4692_Y + connect \$32 $eq$libresoc.v:124240$4693_Y + connect \$34 $or$libresoc.v:124241$4694_Y + connect \$36 $eq$libresoc.v:124242$4695_Y + connect \$38 $and$libresoc.v:124243$4696_Y + connect \$40 $and$libresoc.v:124244$4697_Y + connect \$42 $eq$libresoc.v:124245$4698_Y + connect \$44 $and$libresoc.v:124246$4699_Y + connect \$46 $not$libresoc.v:124247$4700_Y + connect \$48 $and$libresoc.v:124248$4701_Y + connect \$4 $and$libresoc.v:124249$4702_Y + connect \$6 $and$libresoc.v:124250$4703_Y + connect \$8 $eq$libresoc.v:124251$4704_Y connect \MUL__is_signed \dec_MUL_sgn connect \MUL__is_32bit \dec_MUL_is_32b connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } @@ -194418,73 +194214,73 @@ module \dec_MUL connect \insn_in \dec_opcode_in connect \MUL__insn \dec_opcode_in end -attribute \src "libresoc.v:124564.1-125110.10" +attribute \src "libresoc.v:124360.1-124906.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" attribute \generator "nMigen" module \dec_SHIFT_ROT - attribute \src "libresoc.v:125076.3-125090.6" + attribute \src "libresoc.v:124872.3-124886.6" wire width 14 $0\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:125063.3-125075.6" + attribute \src "libresoc.v:124859.3-124871.6" wire width 7 $0\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:125048.3-125062.6" + attribute \src "libresoc.v:124844.3-124858.6" wire $0\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:124565.7-124565.20" + attribute \src "libresoc.v:124361.7-124361.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125076.3-125090.6" + attribute \src "libresoc.v:124872.3-124886.6" wire width 14 $1\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:125063.3-125075.6" + attribute \src "libresoc.v:124859.3-124871.6" wire width 7 $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:125048.3-125062.6" + attribute \src "libresoc.v:124844.3-124858.6" wire $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:124973.18-124973.113" - wire $and$libresoc.v:124973$4709_Y - attribute \src "libresoc.v:124975.18-124975.110" - wire $and$libresoc.v:124975$4711_Y - attribute \src "libresoc.v:124988.18-124988.114" - wire $and$libresoc.v:124988$4724_Y - attribute \src "libresoc.v:124989.18-124989.116" - wire $and$libresoc.v:124989$4725_Y - attribute \src "libresoc.v:124991.18-124991.114" - wire $and$libresoc.v:124991$4727_Y - attribute \src "libresoc.v:124993.18-124993.110" - wire $and$libresoc.v:124993$4729_Y - attribute \src "libresoc.v:124994.17-124994.112" - wire $and$libresoc.v:124994$4730_Y - attribute \src "libresoc.v:124995.17-124995.114" - wire $and$libresoc.v:124995$4731_Y - attribute \src "libresoc.v:124976.18-124976.132" - wire $eq$libresoc.v:124976$4712_Y - attribute \src "libresoc.v:124977.18-124977.132" - wire $eq$libresoc.v:124977$4713_Y - attribute \src "libresoc.v:124979.18-124979.110" - wire $eq$libresoc.v:124979$4715_Y - attribute \src "libresoc.v:124980.18-124980.110" - wire $eq$libresoc.v:124980$4716_Y - attribute \src "libresoc.v:124982.18-124982.112" - wire $eq$libresoc.v:124982$4718_Y - attribute \src "libresoc.v:124983.17-124983.136" - wire $eq$libresoc.v:124983$4719_Y - attribute \src "libresoc.v:124985.18-124985.110" - wire $eq$libresoc.v:124985$4721_Y - attribute \src "libresoc.v:124987.18-124987.137" - wire $eq$libresoc.v:124987$4723_Y - attribute \src "libresoc.v:124990.18-124990.137" - wire $eq$libresoc.v:124990$4726_Y - attribute \src "libresoc.v:124996.17-124996.136" - wire $eq$libresoc.v:124996$4732_Y - attribute \src "libresoc.v:124974.18-124974.110" - wire $not$libresoc.v:124974$4710_Y - attribute \src "libresoc.v:124992.18-124992.110" - wire $not$libresoc.v:124992$4728_Y - attribute \src "libresoc.v:124978.18-124978.110" - wire $or$libresoc.v:124978$4714_Y - attribute \src "libresoc.v:124981.18-124981.110" - wire $or$libresoc.v:124981$4717_Y - attribute \src "libresoc.v:124984.18-124984.110" - wire $or$libresoc.v:124984$4720_Y - attribute \src "libresoc.v:124986.18-124986.110" - wire $or$libresoc.v:124986$4722_Y + attribute \src "libresoc.v:124769.18-124769.113" + wire $and$libresoc.v:124769$4709_Y + attribute \src "libresoc.v:124771.18-124771.110" + wire $and$libresoc.v:124771$4711_Y + attribute \src "libresoc.v:124784.18-124784.114" + wire $and$libresoc.v:124784$4724_Y + attribute \src "libresoc.v:124785.18-124785.116" + wire $and$libresoc.v:124785$4725_Y + attribute \src "libresoc.v:124787.18-124787.114" + wire $and$libresoc.v:124787$4727_Y + attribute \src "libresoc.v:124789.18-124789.110" + wire $and$libresoc.v:124789$4729_Y + attribute \src "libresoc.v:124790.17-124790.112" + wire $and$libresoc.v:124790$4730_Y + attribute \src "libresoc.v:124791.17-124791.114" + wire $and$libresoc.v:124791$4731_Y + attribute \src "libresoc.v:124772.18-124772.132" + wire $eq$libresoc.v:124772$4712_Y + attribute \src "libresoc.v:124773.18-124773.132" + wire $eq$libresoc.v:124773$4713_Y + attribute \src "libresoc.v:124775.18-124775.110" + wire $eq$libresoc.v:124775$4715_Y + attribute \src "libresoc.v:124776.18-124776.110" + wire $eq$libresoc.v:124776$4716_Y + attribute \src "libresoc.v:124778.18-124778.112" + wire $eq$libresoc.v:124778$4718_Y + attribute \src "libresoc.v:124779.17-124779.136" + wire $eq$libresoc.v:124779$4719_Y + attribute \src "libresoc.v:124781.18-124781.110" + wire $eq$libresoc.v:124781$4721_Y + attribute \src "libresoc.v:124783.18-124783.137" + wire $eq$libresoc.v:124783$4723_Y + attribute \src "libresoc.v:124786.18-124786.137" + wire $eq$libresoc.v:124786$4726_Y + attribute \src "libresoc.v:124792.17-124792.136" + wire $eq$libresoc.v:124792$4732_Y + attribute \src "libresoc.v:124770.18-124770.110" + wire $not$libresoc.v:124770$4710_Y + attribute \src "libresoc.v:124788.18-124788.110" + wire $not$libresoc.v:124788$4728_Y + attribute \src "libresoc.v:124774.18-124774.110" + wire $or$libresoc.v:124774$4714_Y + attribute \src "libresoc.v:124777.18-124777.110" + wire $or$libresoc.v:124777$4717_Y + attribute \src "libresoc.v:124780.18-124780.110" + wire $or$libresoc.v:124780$4720_Y + attribute \src "libresoc.v:124782.18-124782.110" + wire $or$libresoc.v:124782$4722_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" @@ -194877,7 +194673,7 @@ module \dec_SHIFT_ROT attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:124565.7-124565.15" + attribute \src "libresoc.v:124361.7-124361.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in @@ -194892,7 +194688,7 @@ module \dec_SHIFT_ROT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:124973$4709 + cell $and $and$libresoc.v:124769$4709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194900,10 +194696,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:124973$4709_Y + connect \Y $and$libresoc.v:124769$4709_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:124975$4711 + cell $and $and$libresoc.v:124771$4711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194911,10 +194707,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:124975$4711_Y + connect \Y $and$libresoc.v:124771$4711_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:124988$4724 + cell $and $and$libresoc.v:124784$4724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194922,10 +194718,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:124988$4724_Y + connect \Y $and$libresoc.v:124784$4724_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:124989$4725 + cell $and $and$libresoc.v:124785$4725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194933,10 +194729,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124989$4725_Y + connect \Y $and$libresoc.v:124785$4725_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:124991$4727 + cell $and $and$libresoc.v:124787$4727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194944,10 +194740,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:124991$4727_Y + connect \Y $and$libresoc.v:124787$4727_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:124993$4729 + cell $and $and$libresoc.v:124789$4729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194955,10 +194751,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:124993$4729_Y + connect \Y $and$libresoc.v:124789$4729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:124994$4730 + cell $and $and$libresoc.v:124790$4730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194966,10 +194762,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:124994$4730_Y + connect \Y $and$libresoc.v:124790$4730_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:124995$4731 + cell $and $and$libresoc.v:124791$4731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194977,10 +194773,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124995$4731_Y + connect \Y $and$libresoc.v:124791$4731_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" - cell $eq $eq$libresoc.v:124976$4712 + cell $eq $eq$libresoc.v:124772$4712 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -194988,10 +194784,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:124976$4712_Y + connect \Y $eq$libresoc.v:124772$4712_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $eq $eq$libresoc.v:124977$4713 + cell $eq $eq$libresoc.v:124773$4713 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -194999,10 +194795,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:124977$4713_Y + connect \Y $eq$libresoc.v:124773$4713_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:124979$4715 + cell $eq $eq$libresoc.v:124775$4715 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195010,10 +194806,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:124979$4715_Y + connect \Y $eq$libresoc.v:124775$4715_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:124980$4716 + cell $eq $eq$libresoc.v:124776$4716 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195021,10 +194817,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:124980$4716_Y + connect \Y $eq$libresoc.v:124776$4716_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:124982$4718 + cell $eq $eq$libresoc.v:124778$4718 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195032,10 +194828,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:124982$4718_Y + connect \Y $eq$libresoc.v:124778$4718_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:124983$4719 + cell $eq $eq$libresoc.v:124779$4719 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195043,10 +194839,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124983$4719_Y + connect \Y $eq$libresoc.v:124779$4719_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $eq $eq$libresoc.v:124985$4721 + cell $eq $eq$libresoc.v:124781$4721 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195054,10 +194850,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:124985$4721_Y + connect \Y $eq$libresoc.v:124781$4721_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:124987$4723 + cell $eq $eq$libresoc.v:124783$4723 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195065,10 +194861,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124987$4723_Y + connect \Y $eq$libresoc.v:124783$4723_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:124990$4726 + cell $eq $eq$libresoc.v:124786$4726 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195076,10 +194872,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124990$4726_Y + connect \Y $eq$libresoc.v:124786$4726_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:124996$4732 + cell $eq $eq$libresoc.v:124792$4732 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195087,26 +194883,26 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124996$4732_Y + connect \Y $eq$libresoc.v:124792$4732_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:124974$4710 + cell $not $not$libresoc.v:124770$4710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124974$4710_Y + connect \Y $not$libresoc.v:124770$4710_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:124992$4728 + cell $not $not$libresoc.v:124788$4728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124992$4728_Y + connect \Y $not$libresoc.v:124788$4728_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $or $or$libresoc.v:124978$4714 + cell $or $or$libresoc.v:124774$4714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195114,10 +194910,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:124978$4714_Y + connect \Y $or$libresoc.v:124774$4714_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:124981$4717 + cell $or $or$libresoc.v:124777$4717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195125,10 +194921,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:124981$4717_Y + connect \Y $or$libresoc.v:124777$4717_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:124984$4720 + cell $or $or$libresoc.v:124780$4720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195136,10 +194932,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:124984$4720_Y + connect \Y $or$libresoc.v:124780$4720_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $or $or$libresoc.v:124986$4722 + cell $or $or$libresoc.v:124782$4722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195147,10 +194943,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:124986$4722_Y + connect \Y $or$libresoc.v:124782$4722_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:124997.13-125022.4" + attribute \src "libresoc.v:124793.13-124818.4" cell \dec$162 \dec connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -195178,7 +194974,7 @@ module \dec_SHIFT_ROT connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125023.16-125034.4" + attribute \src "libresoc.v:124819.16-124830.4" cell \dec_bi$165 \dec_bi connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -195192,7 +194988,7 @@ module \dec_SHIFT_ROT connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125035.16-125041.4" + attribute \src "libresoc.v:124831.16-124837.4" cell \dec_oe$164 \dec_oe connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op @@ -195201,29 +194997,29 @@ module \dec_SHIFT_ROT connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125042.16-125047.4" + attribute \src "libresoc.v:124838.16-124843.4" cell \dec_rc$163 \dec_rc connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:124565.7-124565.20" - process $proc$libresoc.v:124565$4736 + attribute \src "libresoc.v:124361.7-124361.20" + process $proc$libresoc.v:124361$4736 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125048.3-125062.6" - process $proc$libresoc.v:125048$4733 + attribute \src "libresoc.v:124844.3-124858.6" + process $proc$libresoc.v:124844$4733 assign { } { } assign { } { } assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:125049.5-125049.29" + attribute \src "libresoc.v:124845.5-124845.29" switch \initial - attribute \src "libresoc.v:125049.9-125049.17" + attribute \src "libresoc.v:124845.9-124845.17" case 1'1 case end @@ -195243,14 +195039,14 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0] end - attribute \src "libresoc.v:125063.3-125075.6" - process $proc$libresoc.v:125063$4734 + attribute \src "libresoc.v:124859.3-124871.6" + process $proc$libresoc.v:124859$4734 assign { } { } assign { } { } assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:125064.5-125064.29" + attribute \src "libresoc.v:124860.5-124860.29" switch \initial - attribute \src "libresoc.v:125064.9-125064.17" + attribute \src "libresoc.v:124860.9-124860.17" case 1'1 case end @@ -195270,13 +195066,13 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0] end - attribute \src "libresoc.v:125076.3-125090.6" - process $proc$libresoc.v:125076$4735 + attribute \src "libresoc.v:124872.3-124886.6" + process $proc$libresoc.v:124872$4735 assign { } { } assign $0\SHIFT_ROT__fn_unit[13:0] $1\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:125077.5-125077.29" + attribute \src "libresoc.v:124873.5-124873.29" switch \initial - attribute \src "libresoc.v:125077.9-125077.17" + attribute \src "libresoc.v:124873.9-124873.17" case 1'1 case end @@ -195298,30 +195094,30 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[13:0] end - connect \$10 $and$libresoc.v:124973$4709_Y - connect \$12 $not$libresoc.v:124974$4710_Y - connect \$14 $and$libresoc.v:124975$4711_Y - connect \$16 $eq$libresoc.v:124976$4712_Y - connect \$18 $eq$libresoc.v:124977$4713_Y - connect \$20 $or$libresoc.v:124978$4714_Y - connect \$22 $eq$libresoc.v:124979$4715_Y - connect \$24 $eq$libresoc.v:124980$4716_Y - connect \$26 $or$libresoc.v:124981$4717_Y - connect \$28 $eq$libresoc.v:124982$4718_Y - connect \$2 $eq$libresoc.v:124983$4719_Y - connect \$30 $or$libresoc.v:124984$4720_Y - connect \$32 $eq$libresoc.v:124985$4721_Y - connect \$34 $or$libresoc.v:124986$4722_Y - connect \$36 $eq$libresoc.v:124987$4723_Y - connect \$38 $and$libresoc.v:124988$4724_Y - connect \$40 $and$libresoc.v:124989$4725_Y - connect \$42 $eq$libresoc.v:124990$4726_Y - connect \$44 $and$libresoc.v:124991$4727_Y - connect \$46 $not$libresoc.v:124992$4728_Y - connect \$48 $and$libresoc.v:124993$4729_Y - connect \$4 $and$libresoc.v:124994$4730_Y - connect \$6 $and$libresoc.v:124995$4731_Y - connect \$8 $eq$libresoc.v:124996$4732_Y + connect \$10 $and$libresoc.v:124769$4709_Y + connect \$12 $not$libresoc.v:124770$4710_Y + connect \$14 $and$libresoc.v:124771$4711_Y + connect \$16 $eq$libresoc.v:124772$4712_Y + connect \$18 $eq$libresoc.v:124773$4713_Y + connect \$20 $or$libresoc.v:124774$4714_Y + connect \$22 $eq$libresoc.v:124775$4715_Y + connect \$24 $eq$libresoc.v:124776$4716_Y + connect \$26 $or$libresoc.v:124777$4717_Y + connect \$28 $eq$libresoc.v:124778$4718_Y + connect \$2 $eq$libresoc.v:124779$4719_Y + connect \$30 $or$libresoc.v:124780$4720_Y + connect \$32 $eq$libresoc.v:124781$4721_Y + connect \$34 $or$libresoc.v:124782$4722_Y + connect \$36 $eq$libresoc.v:124783$4723_Y + connect \$38 $and$libresoc.v:124784$4724_Y + connect \$40 $and$libresoc.v:124785$4725_Y + connect \$42 $eq$libresoc.v:124786$4726_Y + connect \$44 $and$libresoc.v:124787$4727_Y + connect \$46 $not$libresoc.v:124788$4728_Y + connect \$48 $and$libresoc.v:124789$4729_Y + connect \$4 $and$libresoc.v:124790$4730_Y + connect \$6 $and$libresoc.v:124791$4731_Y + connect \$8 $eq$libresoc.v:124792$4732_Y connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out @@ -195342,69 +195138,69 @@ module \dec_SHIFT_ROT connect \insn_in \dec_opcode_in connect \SHIFT_ROT__insn \dec_opcode_in end -attribute \src "libresoc.v:125114.1-125492.10" +attribute \src "libresoc.v:124910.1-125288.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" attribute \generator "nMigen" module \dec_SPR - attribute \src "libresoc.v:125468.3-125482.6" + attribute \src "libresoc.v:125264.3-125278.6" wire width 14 $0\SPR__fn_unit[13:0] - attribute \src "libresoc.v:125455.3-125467.6" + attribute \src "libresoc.v:125251.3-125263.6" wire width 7 $0\SPR__insn_type[6:0] - attribute \src "libresoc.v:125115.7-125115.20" + attribute \src "libresoc.v:124911.7-124911.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125468.3-125482.6" + attribute \src "libresoc.v:125264.3-125278.6" wire width 14 $1\SPR__fn_unit[13:0] - attribute \src "libresoc.v:125455.3-125467.6" + attribute \src "libresoc.v:125251.3-125263.6" wire width 7 $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:125409.18-125409.113" - wire $and$libresoc.v:125409$4737_Y - attribute \src "libresoc.v:125411.18-125411.110" - wire $and$libresoc.v:125411$4739_Y - attribute \src "libresoc.v:125424.18-125424.114" - wire $and$libresoc.v:125424$4752_Y - attribute \src "libresoc.v:125425.18-125425.116" - wire $and$libresoc.v:125425$4753_Y - attribute \src "libresoc.v:125427.18-125427.114" - wire $and$libresoc.v:125427$4755_Y - attribute \src "libresoc.v:125429.18-125429.110" - wire $and$libresoc.v:125429$4757_Y - attribute \src "libresoc.v:125430.17-125430.112" - wire $and$libresoc.v:125430$4758_Y - attribute \src "libresoc.v:125431.17-125431.114" - wire $and$libresoc.v:125431$4759_Y - attribute \src "libresoc.v:125412.18-125412.126" - wire $eq$libresoc.v:125412$4740_Y - attribute \src "libresoc.v:125413.18-125413.126" - wire $eq$libresoc.v:125413$4741_Y - attribute \src "libresoc.v:125415.18-125415.110" - wire $eq$libresoc.v:125415$4743_Y - attribute \src "libresoc.v:125416.18-125416.110" - wire $eq$libresoc.v:125416$4744_Y - attribute \src "libresoc.v:125418.18-125418.112" - wire $eq$libresoc.v:125418$4746_Y - attribute \src "libresoc.v:125419.17-125419.130" - wire $eq$libresoc.v:125419$4747_Y - attribute \src "libresoc.v:125421.18-125421.110" - wire $eq$libresoc.v:125421$4749_Y - attribute \src "libresoc.v:125423.18-125423.131" - wire $eq$libresoc.v:125423$4751_Y - attribute \src "libresoc.v:125426.18-125426.131" - wire $eq$libresoc.v:125426$4754_Y - attribute \src "libresoc.v:125432.17-125432.130" - wire $eq$libresoc.v:125432$4760_Y - attribute \src "libresoc.v:125410.18-125410.110" - wire $not$libresoc.v:125410$4738_Y - attribute \src "libresoc.v:125428.18-125428.110" - wire $not$libresoc.v:125428$4756_Y - attribute \src "libresoc.v:125414.18-125414.110" - wire $or$libresoc.v:125414$4742_Y - attribute \src "libresoc.v:125417.18-125417.110" - wire $or$libresoc.v:125417$4745_Y - attribute \src "libresoc.v:125420.18-125420.110" - wire $or$libresoc.v:125420$4748_Y - attribute \src "libresoc.v:125422.18-125422.110" - wire $or$libresoc.v:125422$4750_Y + attribute \src "libresoc.v:125205.18-125205.113" + wire $and$libresoc.v:125205$4737_Y + attribute \src "libresoc.v:125207.18-125207.110" + wire $and$libresoc.v:125207$4739_Y + attribute \src "libresoc.v:125220.18-125220.114" + wire $and$libresoc.v:125220$4752_Y + attribute \src "libresoc.v:125221.18-125221.116" + wire $and$libresoc.v:125221$4753_Y + attribute \src "libresoc.v:125223.18-125223.114" + wire $and$libresoc.v:125223$4755_Y + attribute \src "libresoc.v:125225.18-125225.110" + wire $and$libresoc.v:125225$4757_Y + attribute \src "libresoc.v:125226.17-125226.112" + wire $and$libresoc.v:125226$4758_Y + attribute \src "libresoc.v:125227.17-125227.114" + wire $and$libresoc.v:125227$4759_Y + attribute \src "libresoc.v:125208.18-125208.126" + wire $eq$libresoc.v:125208$4740_Y + attribute \src "libresoc.v:125209.18-125209.126" + wire $eq$libresoc.v:125209$4741_Y + attribute \src "libresoc.v:125211.18-125211.110" + wire $eq$libresoc.v:125211$4743_Y + attribute \src "libresoc.v:125212.18-125212.110" + wire $eq$libresoc.v:125212$4744_Y + attribute \src "libresoc.v:125214.18-125214.112" + wire $eq$libresoc.v:125214$4746_Y + attribute \src "libresoc.v:125215.17-125215.130" + wire $eq$libresoc.v:125215$4747_Y + attribute \src "libresoc.v:125217.18-125217.110" + wire $eq$libresoc.v:125217$4749_Y + attribute \src "libresoc.v:125219.18-125219.131" + wire $eq$libresoc.v:125219$4751_Y + attribute \src "libresoc.v:125222.18-125222.131" + wire $eq$libresoc.v:125222$4754_Y + attribute \src "libresoc.v:125228.17-125228.130" + wire $eq$libresoc.v:125228$4760_Y + attribute \src "libresoc.v:125206.18-125206.110" + wire $not$libresoc.v:125206$4738_Y + attribute \src "libresoc.v:125224.18-125224.110" + wire $not$libresoc.v:125224$4756_Y + attribute \src "libresoc.v:125210.18-125210.110" + wire $or$libresoc.v:125210$4742_Y + attribute \src "libresoc.v:125213.18-125213.110" + wire $or$libresoc.v:125213$4745_Y + attribute \src "libresoc.v:125216.18-125216.110" + wire $or$libresoc.v:125216$4748_Y + attribute \src "libresoc.v:125218.18-125218.110" + wire $or$libresoc.v:125218$4750_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" @@ -195684,7 +195480,7 @@ module \dec_SPR attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:125115.7-125115.15" + attribute \src "libresoc.v:124911.7-124911.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in @@ -195699,7 +195495,7 @@ module \dec_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:125409$4737 + cell $and $and$libresoc.v:125205$4737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195707,10 +195503,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:125409$4737_Y + connect \Y $and$libresoc.v:125205$4737_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:125411$4739 + cell $and $and$libresoc.v:125207$4739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195718,10 +195514,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:125411$4739_Y + connect \Y $and$libresoc.v:125207$4739_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:125424$4752 + cell $and $and$libresoc.v:125220$4752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195729,10 +195525,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:125424$4752_Y + connect \Y $and$libresoc.v:125220$4752_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:125425$4753 + cell $and $and$libresoc.v:125221$4753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195740,10 +195536,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:125425$4753_Y + connect \Y $and$libresoc.v:125221$4753_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:125427$4755 + cell $and $and$libresoc.v:125223$4755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195751,10 +195547,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:125427$4755_Y + connect \Y $and$libresoc.v:125223$4755_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $and $and$libresoc.v:125429$4757 + cell $and $and$libresoc.v:125225$4757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195762,10 +195558,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:125429$4757_Y + connect \Y $and$libresoc.v:125225$4757_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:125430$4758 + cell $and $and$libresoc.v:125226$4758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195773,10 +195569,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:125430$4758_Y + connect \Y $and$libresoc.v:125226$4758_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $and $and$libresoc.v:125431$4759 + cell $and $and$libresoc.v:125227$4759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195784,10 +195580,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:125431$4759_Y + connect \Y $and$libresoc.v:125227$4759_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" - cell $eq $eq$libresoc.v:125412$4740 + cell $eq $eq$libresoc.v:125208$4740 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -195795,10 +195591,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:125412$4740_Y + connect \Y $eq$libresoc.v:125208$4740_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $eq $eq$libresoc.v:125413$4741 + cell $eq $eq$libresoc.v:125209$4741 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -195806,10 +195602,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:125413$4741_Y + connect \Y $eq$libresoc.v:125209$4741_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:125415$4743 + cell $eq $eq$libresoc.v:125211$4743 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195817,10 +195613,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:125415$4743_Y + connect \Y $eq$libresoc.v:125211$4743_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:125416$4744 + cell $eq $eq$libresoc.v:125212$4744 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195828,10 +195624,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:125416$4744_Y + connect \Y $eq$libresoc.v:125212$4744_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $eq $eq$libresoc.v:125418$4746 + cell $eq $eq$libresoc.v:125214$4746 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195839,10 +195635,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:125418$4746_Y + connect \Y $eq$libresoc.v:125214$4746_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:125419$4747 + cell $eq $eq$libresoc.v:125215$4747 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195850,10 +195646,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:125419$4747_Y + connect \Y $eq$libresoc.v:125215$4747_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $eq $eq$libresoc.v:125421$4749 + cell $eq $eq$libresoc.v:125217$4749 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195861,10 +195657,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:125421$4749_Y + connect \Y $eq$libresoc.v:125217$4749_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" - cell $eq $eq$libresoc.v:125423$4751 + cell $eq $eq$libresoc.v:125219$4751 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195872,10 +195668,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:125423$4751_Y + connect \Y $eq$libresoc.v:125219$4751_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:125426$4754 + cell $eq $eq$libresoc.v:125222$4754 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195883,10 +195679,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:125426$4754_Y + connect \Y $eq$libresoc.v:125222$4754_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $eq $eq$libresoc.v:125432$4760 + cell $eq $eq$libresoc.v:125228$4760 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195894,26 +195690,26 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:125432$4760_Y + connect \Y $eq$libresoc.v:125228$4760_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:125410$4738 + cell $not $not$libresoc.v:125206$4738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:125410$4738_Y + connect \Y $not$libresoc.v:125206$4738_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" - cell $not $not$libresoc.v:125428$4756 + cell $not $not$libresoc.v:125224$4756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:125428$4756_Y + connect \Y $not$libresoc.v:125224$4756_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" - cell $or $or$libresoc.v:125414$4742 + cell $or $or$libresoc.v:125210$4742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195921,10 +195717,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:125414$4742_Y + connect \Y $or$libresoc.v:125210$4742_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:125417$4745 + cell $or $or$libresoc.v:125213$4745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195932,10 +195728,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:125417$4745_Y + connect \Y $or$libresoc.v:125213$4745_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" - cell $or $or$libresoc.v:125420$4748 + cell $or $or$libresoc.v:125216$4748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195943,10 +195739,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:125420$4748_Y + connect \Y $or$libresoc.v:125216$4748_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" - cell $or $or$libresoc.v:125422$4750 + cell $or $or$libresoc.v:125218$4750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195954,10 +195750,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:125422$4750_Y + connect \Y $or$libresoc.v:125218$4750_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:125433.13-125445.4" + attribute \src "libresoc.v:125229.13-125241.4" cell \dec$150 \dec connect \SPR_OE \dec_SPR_OE connect \SPR_Rc \dec_SPR_Rc @@ -195972,34 +195768,34 @@ module \dec_SPR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125446.16-125450.4" + attribute \src "libresoc.v:125242.16-125246.4" cell \dec_oe$152 \dec_oe connect \SPR_OE \dec_SPR_OE connect \SPR_internal_op \dec_SPR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125451.16-125454.4" + attribute \src "libresoc.v:125247.16-125250.4" cell \dec_rc$151 \dec_rc connect \SPR_Rc \dec_SPR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:125115.7-125115.20" - process $proc$libresoc.v:125115$4763 + attribute \src "libresoc.v:124911.7-124911.20" + process $proc$libresoc.v:124911$4763 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125455.3-125467.6" - process $proc$libresoc.v:125455$4761 + attribute \src "libresoc.v:125251.3-125263.6" + process $proc$libresoc.v:125251$4761 assign { } { } assign { } { } assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:125456.5-125456.29" + attribute \src "libresoc.v:125252.5-125252.29" switch \initial - attribute \src "libresoc.v:125456.9-125456.17" + attribute \src "libresoc.v:125252.9-125252.17" case 1'1 case end @@ -196019,13 +195815,13 @@ module \dec_SPR sync always update \SPR__insn_type $0\SPR__insn_type[6:0] end - attribute \src "libresoc.v:125468.3-125482.6" - process $proc$libresoc.v:125468$4762 + attribute \src "libresoc.v:125264.3-125278.6" + process $proc$libresoc.v:125264$4762 assign { } { } assign $0\SPR__fn_unit[13:0] $1\SPR__fn_unit[13:0] - attribute \src "libresoc.v:125469.5-125469.29" + attribute \src "libresoc.v:125265.5-125265.29" switch \initial - attribute \src "libresoc.v:125469.9-125469.17" + attribute \src "libresoc.v:125265.9-125265.17" case 1'1 case end @@ -196047,30 +195843,30 @@ module \dec_SPR sync always update \SPR__fn_unit $0\SPR__fn_unit[13:0] end - connect \$10 $and$libresoc.v:125409$4737_Y - connect \$12 $not$libresoc.v:125410$4738_Y - connect \$14 $and$libresoc.v:125411$4739_Y - connect \$16 $eq$libresoc.v:125412$4740_Y - connect \$18 $eq$libresoc.v:125413$4741_Y - connect \$20 $or$libresoc.v:125414$4742_Y - connect \$22 $eq$libresoc.v:125415$4743_Y - connect \$24 $eq$libresoc.v:125416$4744_Y - connect \$26 $or$libresoc.v:125417$4745_Y - connect \$28 $eq$libresoc.v:125418$4746_Y - connect \$2 $eq$libresoc.v:125419$4747_Y - connect \$30 $or$libresoc.v:125420$4748_Y - connect \$32 $eq$libresoc.v:125421$4749_Y - connect \$34 $or$libresoc.v:125422$4750_Y - connect \$36 $eq$libresoc.v:125423$4751_Y - connect \$38 $and$libresoc.v:125424$4752_Y - connect \$40 $and$libresoc.v:125425$4753_Y - connect \$42 $eq$libresoc.v:125426$4754_Y - connect \$44 $and$libresoc.v:125427$4755_Y - connect \$46 $not$libresoc.v:125428$4756_Y - connect \$48 $and$libresoc.v:125429$4757_Y - connect \$4 $and$libresoc.v:125430$4758_Y - connect \$6 $and$libresoc.v:125431$4759_Y - connect \$8 $eq$libresoc.v:125432$4760_Y + connect \$10 $and$libresoc.v:125205$4737_Y + connect \$12 $not$libresoc.v:125206$4738_Y + connect \$14 $and$libresoc.v:125207$4739_Y + connect \$16 $eq$libresoc.v:125208$4740_Y + connect \$18 $eq$libresoc.v:125209$4741_Y + connect \$20 $or$libresoc.v:125210$4742_Y + connect \$22 $eq$libresoc.v:125211$4743_Y + connect \$24 $eq$libresoc.v:125212$4744_Y + connect \$26 $or$libresoc.v:125213$4745_Y + connect \$28 $eq$libresoc.v:125214$4746_Y + connect \$2 $eq$libresoc.v:125215$4747_Y + connect \$30 $or$libresoc.v:125216$4748_Y + connect \$32 $eq$libresoc.v:125217$4749_Y + connect \$34 $or$libresoc.v:125218$4750_Y + connect \$36 $eq$libresoc.v:125219$4751_Y + connect \$38 $and$libresoc.v:125220$4752_Y + connect \$40 $and$libresoc.v:125221$4753_Y + connect \$42 $eq$libresoc.v:125222$4754_Y + connect \$44 $and$libresoc.v:125223$4755_Y + connect \$46 $not$libresoc.v:125224$4756_Y + connect \$48 $and$libresoc.v:125225$4757_Y + connect \$4 $and$libresoc.v:125226$4758_Y + connect \$6 $and$libresoc.v:125227$4759_Y + connect \$8 $eq$libresoc.v:125228$4760_Y connect \SPR__is_32bit \dec_SPR_is_32b connect \is_mmu_spr \$34 connect \is_spr_mv \$20 @@ -196081,95 +195877,95 @@ module \dec_SPR connect \insn_in \dec_opcode_in connect \SPR__insn \dec_opcode_in end -attribute \src "libresoc.v:125496.1-126049.10" +attribute \src "libresoc.v:125292.1-125845.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" attribute \generator "nMigen" module \dec_a - attribute \src "libresoc.v:125953.3-125988.6" + attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $0\fast_a[2:0] - attribute \src "libresoc.v:125953.3-125988.6" + attribute \src "libresoc.v:125749.3-125784.6" wire $0\fast_a_ok[0:0] - attribute \src "libresoc.v:125497.7-125497.20" + attribute \src "libresoc.v:125293.7-125293.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125921.3-125936.6" + attribute \src "libresoc.v:125717.3-125732.6" wire width 5 $0\reg_a[4:0] - attribute \src "libresoc.v:125937.3-125952.6" + attribute \src "libresoc.v:125733.3-125748.6" wire $0\reg_a_ok[0:0] - attribute \src "libresoc.v:125989.3-126007.6" + attribute \src "libresoc.v:125785.3-125803.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:126027.3-126046.6" + attribute \src "libresoc.v:125823.3-125842.6" wire width 10 $0\spr_a[9:0] - attribute \src "libresoc.v:126027.3-126046.6" + attribute \src "libresoc.v:125823.3-125842.6" wire $0\spr_a_ok[0:0] - attribute \src "libresoc.v:126008.3-126026.6" + attribute \src "libresoc.v:125804.3-125822.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:125953.3-125988.6" + attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $1\fast_a[2:0] - attribute \src "libresoc.v:125953.3-125988.6" + attribute \src "libresoc.v:125749.3-125784.6" wire $1\fast_a_ok[0:0] - attribute \src "libresoc.v:125921.3-125936.6" + attribute \src "libresoc.v:125717.3-125732.6" wire width 5 $1\reg_a[4:0] - attribute \src "libresoc.v:125937.3-125952.6" + attribute \src "libresoc.v:125733.3-125748.6" wire $1\reg_a_ok[0:0] - attribute \src "libresoc.v:125989.3-126007.6" + attribute \src "libresoc.v:125785.3-125803.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:126027.3-126046.6" + attribute \src "libresoc.v:125823.3-125842.6" wire width 10 $1\spr_a[9:0] - attribute \src "libresoc.v:126027.3-126046.6" + attribute \src "libresoc.v:125823.3-125842.6" wire $1\spr_a_ok[0:0] - attribute \src "libresoc.v:126008.3-126026.6" + attribute \src "libresoc.v:125804.3-125822.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:125953.3-125988.6" + attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $2\fast_a[2:0] - attribute \src "libresoc.v:125953.3-125988.6" + attribute \src "libresoc.v:125749.3-125784.6" wire $2\fast_a_ok[0:0] - attribute \src "libresoc.v:125921.3-125936.6" + attribute \src "libresoc.v:125717.3-125732.6" wire width 5 $2\reg_a[4:0] - attribute \src "libresoc.v:125937.3-125952.6" + attribute \src "libresoc.v:125733.3-125748.6" wire $2\reg_a_ok[0:0] - attribute \src "libresoc.v:125953.3-125988.6" + attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $3\fast_a[2:0] - attribute \src "libresoc.v:125953.3-125988.6" + attribute \src "libresoc.v:125749.3-125784.6" wire $3\fast_a_ok[0:0] - attribute \src "libresoc.v:125896.18-125896.108" - wire $and$libresoc.v:125896$4765_Y - attribute \src "libresoc.v:125905.18-125905.110" - wire $and$libresoc.v:125905$4774_Y - attribute \src "libresoc.v:125910.18-125910.113" - wire $and$libresoc.v:125910$4779_Y - attribute \src "libresoc.v:125898.18-125898.112" - wire $eq$libresoc.v:125898$4767_Y - attribute \src "libresoc.v:125899.18-125899.112" - wire $eq$libresoc.v:125899$4768_Y - attribute \src "libresoc.v:125900.17-125900.111" - wire $eq$libresoc.v:125900$4769_Y - attribute \src "libresoc.v:125901.18-125901.112" - wire $eq$libresoc.v:125901$4770_Y - attribute \src "libresoc.v:125907.18-125907.112" - wire $eq$libresoc.v:125907$4776_Y - attribute \src "libresoc.v:125911.17-125911.111" - wire $eq$libresoc.v:125911$4780_Y - attribute \src "libresoc.v:125902.18-125902.109" - wire $ne$libresoc.v:125902$4771_Y - attribute \src "libresoc.v:125903.18-125903.111" - wire $ne$libresoc.v:125903$4772_Y - attribute \src "libresoc.v:125912.17-125912.108" - wire $ne$libresoc.v:125912$4781_Y - attribute \src "libresoc.v:125913.17-125913.110" - wire $ne$libresoc.v:125913$4782_Y - attribute \src "libresoc.v:125908.18-125908.105" - wire $not$libresoc.v:125908$4777_Y - attribute \src "libresoc.v:125909.18-125909.108" - wire $not$libresoc.v:125909$4778_Y - attribute \src "libresoc.v:125895.17-125895.107" - wire $or$libresoc.v:125895$4764_Y - attribute \src "libresoc.v:125897.18-125897.109" - wire $or$libresoc.v:125897$4766_Y - attribute \src "libresoc.v:125904.18-125904.110" - wire $or$libresoc.v:125904$4773_Y - attribute \src "libresoc.v:125906.18-125906.110" - wire $or$libresoc.v:125906$4775_Y + attribute \src "libresoc.v:125692.18-125692.108" + wire $and$libresoc.v:125692$4765_Y + attribute \src "libresoc.v:125701.18-125701.110" + wire $and$libresoc.v:125701$4774_Y + attribute \src "libresoc.v:125706.18-125706.113" + wire $and$libresoc.v:125706$4779_Y + attribute \src "libresoc.v:125694.18-125694.112" + wire $eq$libresoc.v:125694$4767_Y + attribute \src "libresoc.v:125695.18-125695.112" + wire $eq$libresoc.v:125695$4768_Y + attribute \src "libresoc.v:125696.17-125696.111" + wire $eq$libresoc.v:125696$4769_Y + attribute \src "libresoc.v:125697.18-125697.112" + wire $eq$libresoc.v:125697$4770_Y + attribute \src "libresoc.v:125703.18-125703.112" + wire $eq$libresoc.v:125703$4776_Y + attribute \src "libresoc.v:125707.17-125707.111" + wire $eq$libresoc.v:125707$4780_Y + attribute \src "libresoc.v:125698.18-125698.109" + wire $ne$libresoc.v:125698$4771_Y + attribute \src "libresoc.v:125699.18-125699.111" + wire $ne$libresoc.v:125699$4772_Y + attribute \src "libresoc.v:125708.17-125708.108" + wire $ne$libresoc.v:125708$4781_Y + attribute \src "libresoc.v:125709.17-125709.110" + wire $ne$libresoc.v:125709$4782_Y + attribute \src "libresoc.v:125704.18-125704.105" + wire $not$libresoc.v:125704$4777_Y + attribute \src "libresoc.v:125705.18-125705.108" + wire $not$libresoc.v:125705$4778_Y + attribute \src "libresoc.v:125691.17-125691.107" + wire $or$libresoc.v:125691$4764_Y + attribute \src "libresoc.v:125693.18-125693.109" + wire $or$libresoc.v:125693$4766_Y + attribute \src "libresoc.v:125700.18-125700.110" + wire $or$libresoc.v:125700$4773_Y + attribute \src "libresoc.v:125702.18-125702.110" + wire $or$libresoc.v:125702$4775_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" @@ -196222,7 +196018,7 @@ module \dec_a wire width 3 output 8 \fast_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 9 \fast_a_ok - attribute \src "libresoc.v:125497.7-125497.15" + attribute \src "libresoc.v:125293.7-125293.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -196564,7 +196360,7 @@ module \dec_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" wire input 2 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $and $and$libresoc.v:125896$4765 + cell $and $and$libresoc.v:125692$4765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196572,10 +196368,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$3 connect \B \$9 - connect \Y $and$libresoc.v:125896$4765_Y + connect \Y $and$libresoc.v:125692$4765_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $and $and$libresoc.v:125905$4774 + cell $and $and$libresoc.v:125701$4774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196583,10 +196379,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$19 connect \B \$25 - connect \Y $and$libresoc.v:125905$4774_Y + connect \Y $and$libresoc.v:125701$4774_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" - cell $and $and$libresoc.v:125910$4779 + cell $and $and$libresoc.v:125706$4779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196594,10 +196390,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \XL_XO [9] connect \B \$35 - connect \Y $and$libresoc.v:125910$4779_Y + connect \Y $and$libresoc.v:125706$4779_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - cell $eq $eq$libresoc.v:125898$4767 + cell $eq $eq$libresoc.v:125694$4767 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196605,10 +196401,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:125898$4767_Y + connect \Y $eq$libresoc.v:125694$4767_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" - cell $eq $eq$libresoc.v:125899$4768 + cell $eq $eq$libresoc.v:125695$4768 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196616,10 +196412,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:125899$4768_Y + connect \Y $eq$libresoc.v:125695$4768_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" - cell $eq $eq$libresoc.v:125900$4769 + cell $eq $eq$libresoc.v:125696$4769 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196627,10 +196423,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:125900$4769_Y + connect \Y $eq$libresoc.v:125696$4769_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" - cell $eq $eq$libresoc.v:125901$4770 + cell $eq $eq$libresoc.v:125697$4770 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196638,10 +196434,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:125901$4770_Y + connect \Y $eq$libresoc.v:125697$4770_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - cell $eq $eq$libresoc.v:125907$4776 + cell $eq $eq$libresoc.v:125703$4776 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196649,10 +196445,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:125907$4776_Y + connect \Y $eq$libresoc.v:125703$4776_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" - cell $eq $eq$libresoc.v:125911$4780 + cell $eq $eq$libresoc.v:125707$4780 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196660,10 +196456,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:125911$4780_Y + connect \Y $eq$libresoc.v:125707$4780_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $ne $ne$libresoc.v:125902$4771 + cell $ne $ne$libresoc.v:125698$4771 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -196671,10 +196467,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:125902$4771_Y + connect \Y $ne$libresoc.v:125698$4771_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $ne $ne$libresoc.v:125903$4772 + cell $ne $ne$libresoc.v:125699$4772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196682,10 +196478,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $ne$libresoc.v:125903$4772_Y + connect \Y $ne$libresoc.v:125699$4772_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $ne $ne$libresoc.v:125912$4781 + cell $ne $ne$libresoc.v:125708$4781 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -196693,10 +196489,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:125912$4781_Y + connect \Y $ne$libresoc.v:125708$4781_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $ne $ne$libresoc.v:125913$4782 + cell $ne $ne$libresoc.v:125709$4782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196704,26 +196500,26 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $ne$libresoc.v:125913$4782_Y + connect \Y $ne$libresoc.v:125709$4782_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - cell $not $not$libresoc.v:125908$4777 + cell $not $not$libresoc.v:125704$4777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:125908$4777_Y + connect \Y $not$libresoc.v:125704$4777_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" - cell $not $not$libresoc.v:125909$4778 + cell $not $not$libresoc.v:125705$4778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [5] - connect \Y $not$libresoc.v:125909$4778_Y + connect \Y $not$libresoc.v:125705$4778_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $or $or$libresoc.v:125895$4764 + cell $or $or$libresoc.v:125691$4764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196731,10 +196527,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:125895$4764_Y + connect \Y $or$libresoc.v:125691$4764_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $or $or$libresoc.v:125897$4766 + cell $or $or$libresoc.v:125693$4766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196742,10 +196538,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$1 connect \B \$11 - connect \Y $or$libresoc.v:125897$4766_Y + connect \Y $or$libresoc.v:125693$4766_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $or $or$libresoc.v:125904$4773 + cell $or $or$libresoc.v:125700$4773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196753,10 +196549,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$21 connect \B \$23 - connect \Y $or$libresoc.v:125904$4773_Y + connect \Y $or$libresoc.v:125700$4773_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $or $or$libresoc.v:125906$4775 + cell $or $or$libresoc.v:125702$4775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196764,10 +196560,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$17 connect \B \$27 - connect \Y $or$libresoc.v:125906$4775_Y + connect \Y $or$libresoc.v:125702$4775_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:125914.10-125920.4" + attribute \src "libresoc.v:125710.10-125716.4" cell \sprmap \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -196775,23 +196571,23 @@ module \dec_a connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:125497.7-125497.20" - process $proc$libresoc.v:125497$4789 + attribute \src "libresoc.v:125293.7-125293.20" + process $proc$libresoc.v:125293$4789 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125921.3-125936.6" - process $proc$libresoc.v:125921$4783 + attribute \src "libresoc.v:125717.3-125732.6" + process $proc$libresoc.v:125717$4783 assign { } { } assign { } { } assign { } { } assign $0\reg_a[4:0] $2\reg_a[4:0] - attribute \src "libresoc.v:125922.5-125922.29" + attribute \src "libresoc.v:125718.5-125718.29" switch \initial - attribute \src "libresoc.v:125922.9-125922.17" + attribute \src "libresoc.v:125718.9-125718.17" case 1'1 case end @@ -196816,15 +196612,15 @@ module \dec_a sync always update \reg_a $0\reg_a[4:0] end - attribute \src "libresoc.v:125937.3-125952.6" - process $proc$libresoc.v:125937$4784 + attribute \src "libresoc.v:125733.3-125748.6" + process $proc$libresoc.v:125733$4784 assign { } { } assign { } { } assign { } { } assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] - attribute \src "libresoc.v:125938.5-125938.29" + attribute \src "libresoc.v:125734.5-125734.29" switch \initial - attribute \src "libresoc.v:125938.9-125938.17" + attribute \src "libresoc.v:125734.9-125734.17" case 1'1 case end @@ -196849,17 +196645,17 @@ module \dec_a sync always update \reg_a_ok $0\reg_a_ok[0:0] end - attribute \src "libresoc.v:125953.3-125988.6" - process $proc$libresoc.v:125953$4785 + attribute \src "libresoc.v:125749.3-125784.6" + process $proc$libresoc.v:125749$4785 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast_a[2:0] $1\fast_a[2:0] assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "libresoc.v:125954.5-125954.29" + attribute \src "libresoc.v:125750.5-125750.29" switch \initial - attribute \src "libresoc.v:125954.9-125954.17" + attribute \src "libresoc.v:125750.9-125750.17" case 1'1 case end @@ -196914,14 +196710,14 @@ module \dec_a update \fast_a $0\fast_a[2:0] update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "libresoc.v:125989.3-126007.6" - process $proc$libresoc.v:125989$4786 + attribute \src "libresoc.v:125785.3-125803.6" + process $proc$libresoc.v:125785$4786 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:125990.5-125990.29" + attribute \src "libresoc.v:125786.5-125786.29" switch \initial - attribute \src "libresoc.v:125990.9-125990.17" + attribute \src "libresoc.v:125786.9-125786.17" case 1'1 case end @@ -196943,14 +196739,14 @@ module \dec_a sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:126008.3-126026.6" - process $proc$libresoc.v:126008$4787 + attribute \src "libresoc.v:125804.3-125822.6" + process $proc$libresoc.v:125804$4787 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:126009.5-126009.29" + attribute \src "libresoc.v:125805.5-125805.29" switch \initial - attribute \src "libresoc.v:126009.9-126009.17" + attribute \src "libresoc.v:125805.9-125805.17" case 1'1 case end @@ -196972,17 +196768,17 @@ module \dec_a sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:126027.3-126046.6" - process $proc$libresoc.v:126027$4788 + attribute \src "libresoc.v:125823.3-125842.6" + process $proc$libresoc.v:125823$4788 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_a[9:0] $1\spr_a[9:0] assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "libresoc.v:126028.5-126028.29" + attribute \src "libresoc.v:125824.5-125824.29" switch \initial - attribute \src "libresoc.v:126028.9-126028.17" + attribute \src "libresoc.v:125824.9-125824.17" case 1'1 case end @@ -197009,49 +196805,49 @@ module \dec_a update \spr_a $0\spr_a[9:0] update \spr_a_ok $0\spr_a_ok[0:0] end - connect \$9 $or$libresoc.v:125895$4764_Y - connect \$11 $and$libresoc.v:125896$4765_Y - connect \$13 $or$libresoc.v:125897$4766_Y - connect \$15 $eq$libresoc.v:125898$4767_Y - connect \$17 $eq$libresoc.v:125899$4768_Y - connect \$1 $eq$libresoc.v:125900$4769_Y - connect \$19 $eq$libresoc.v:125901$4770_Y - connect \$21 $ne$libresoc.v:125902$4771_Y - connect \$23 $ne$libresoc.v:125903$4772_Y - connect \$25 $or$libresoc.v:125904$4773_Y - connect \$27 $and$libresoc.v:125905$4774_Y - connect \$29 $or$libresoc.v:125906$4775_Y - connect \$31 $eq$libresoc.v:125907$4776_Y - connect \$33 $not$libresoc.v:125908$4777_Y - connect \$35 $not$libresoc.v:125909$4778_Y - connect \$37 $and$libresoc.v:125910$4779_Y - connect \$3 $eq$libresoc.v:125911$4780_Y - connect \$5 $ne$libresoc.v:125912$4781_Y - connect \$7 $ne$libresoc.v:125913$4782_Y + connect \$9 $or$libresoc.v:125691$4764_Y + connect \$11 $and$libresoc.v:125692$4765_Y + connect \$13 $or$libresoc.v:125693$4766_Y + connect \$15 $eq$libresoc.v:125694$4767_Y + connect \$17 $eq$libresoc.v:125695$4768_Y + connect \$1 $eq$libresoc.v:125696$4769_Y + connect \$19 $eq$libresoc.v:125697$4770_Y + connect \$21 $ne$libresoc.v:125698$4771_Y + connect \$23 $ne$libresoc.v:125699$4772_Y + connect \$25 $or$libresoc.v:125700$4773_Y + connect \$27 $and$libresoc.v:125701$4774_Y + connect \$29 $or$libresoc.v:125702$4775_Y + connect \$31 $eq$libresoc.v:125703$4776_Y + connect \$33 $not$libresoc.v:125704$4777_Y + connect \$35 $not$libresoc.v:125705$4778_Y + connect \$37 $and$libresoc.v:125706$4779_Y + connect \$3 $eq$libresoc.v:125707$4780_Y + connect \$5 $ne$libresoc.v:125708$4781_Y + connect \$7 $ne$libresoc.v:125709$4782_Y connect \rs \RS connect \ra \RA end -attribute \src "libresoc.v:126053.1-126098.10" +attribute \src "libresoc.v:125849.1-125894.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai" attribute \generator "nMigen" module \dec_ai - attribute \src "libresoc.v:126087.3-126096.6" + attribute \src "libresoc.v:125883.3-125892.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126054.7-126054.20" + attribute \src "libresoc.v:125850.7-125850.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126087.3-126096.6" + attribute \src "libresoc.v:125883.3-125892.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126082.17-126082.107" - wire $and$libresoc.v:126082$4790_Y - attribute \src "libresoc.v:126085.17-126085.107" - wire $and$libresoc.v:126085$4793_Y - attribute \src "libresoc.v:126083.17-126083.111" - wire $eq$libresoc.v:126083$4791_Y - attribute \src "libresoc.v:126084.17-126084.108" - wire $eq$libresoc.v:126084$4792_Y - attribute \src "libresoc.v:126086.17-126086.110" - wire $eq$libresoc.v:126086$4794_Y + attribute \src "libresoc.v:125878.17-125878.107" + wire $and$libresoc.v:125878$4790_Y + attribute \src "libresoc.v:125881.17-125881.107" + wire $and$libresoc.v:125881$4793_Y + attribute \src "libresoc.v:125879.17-125879.111" + wire $eq$libresoc.v:125879$4791_Y + attribute \src "libresoc.v:125880.17-125880.108" + wire $eq$libresoc.v:125880$4792_Y + attribute \src "libresoc.v:125882.17-125882.110" + wire $eq$libresoc.v:125882$4794_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" @@ -197066,7 +196862,7 @@ module \dec_ai wire width 5 input 3 \ALU_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out - attribute \src "libresoc.v:126054.7-126054.15" + attribute \src "libresoc.v:125850.7-125850.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra @@ -197081,7 +196877,7 @@ module \dec_ai attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - cell $and $and$libresoc.v:126082$4790 + cell $and $and$libresoc.v:125878$4790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197089,10 +196885,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126082$4790_Y + connect \Y $and$libresoc.v:125878$4790_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $and $and$libresoc.v:126085$4793 + cell $and $and$libresoc.v:125881$4793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197100,10 +196896,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126085$4793_Y + connect \Y $and$libresoc.v:125881$4793_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $eq $eq$libresoc.v:126083$4791 + cell $eq $eq$libresoc.v:125879$4791 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197111,10 +196907,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126083$4791_Y + connect \Y $eq$libresoc.v:125879$4791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $eq $eq$libresoc.v:126084$4792 + cell $eq $eq$libresoc.v:125880$4792 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197122,10 +196918,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126084$4792_Y + connect \Y $eq$libresoc.v:125880$4792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - cell $eq $eq$libresoc.v:126086$4794 + cell $eq $eq$libresoc.v:125882$4794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197133,24 +196929,24 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126086$4794_Y + connect \Y $eq$libresoc.v:125882$4794_Y end - attribute \src "libresoc.v:126054.7-126054.20" - process $proc$libresoc.v:126054$4796 + attribute \src "libresoc.v:125850.7-125850.20" + process $proc$libresoc.v:125850$4796 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126087.3-126096.6" - process $proc$libresoc.v:126087$4795 + attribute \src "libresoc.v:125883.3-125892.6" + process $proc$libresoc.v:125883$4795 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126088.5-126088.29" + attribute \src "libresoc.v:125884.5-125884.29" switch \initial - attribute \src "libresoc.v:126088.9-126088.17" + attribute \src "libresoc.v:125884.9-125884.17" case 1'1 case end @@ -197166,34 +196962,34 @@ module \dec_ai sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126082$4790_Y - connect \$1 $eq$libresoc.v:126083$4791_Y - connect \$3 $eq$libresoc.v:126084$4792_Y - connect \$5 $and$libresoc.v:126085$4793_Y - connect \$7 $eq$libresoc.v:126086$4794_Y + connect \$9 $and$libresoc.v:125878$4790_Y + connect \$1 $eq$libresoc.v:125879$4791_Y + connect \$3 $eq$libresoc.v:125880$4792_Y + connect \$5 $and$libresoc.v:125881$4793_Y + connect \$7 $eq$libresoc.v:125882$4794_Y connect \ra \ALU_RA end -attribute \src "libresoc.v:126102.1-126147.10" +attribute \src "libresoc.v:125898.1-125943.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" attribute \generator "nMigen" module \dec_ai$148 - attribute \src "libresoc.v:126136.3-126145.6" + attribute \src "libresoc.v:125932.3-125941.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126103.7-126103.20" + attribute \src "libresoc.v:125899.7-125899.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126136.3-126145.6" + attribute \src "libresoc.v:125932.3-125941.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126131.17-126131.107" - wire $and$libresoc.v:126131$4797_Y - attribute \src "libresoc.v:126134.17-126134.107" - wire $and$libresoc.v:126134$4800_Y - attribute \src "libresoc.v:126132.17-126132.111" - wire $eq$libresoc.v:126132$4798_Y - attribute \src "libresoc.v:126133.17-126133.108" - wire $eq$libresoc.v:126133$4799_Y - attribute \src "libresoc.v:126135.17-126135.110" - wire $eq$libresoc.v:126135$4801_Y + attribute \src "libresoc.v:125927.17-125927.107" + wire $and$libresoc.v:125927$4797_Y + attribute \src "libresoc.v:125930.17-125930.107" + wire $and$libresoc.v:125930$4800_Y + attribute \src "libresoc.v:125928.17-125928.111" + wire $eq$libresoc.v:125928$4798_Y + attribute \src "libresoc.v:125929.17-125929.108" + wire $eq$libresoc.v:125929$4799_Y + attribute \src "libresoc.v:125931.17-125931.110" + wire $eq$libresoc.v:125931$4801_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" @@ -197208,7 +197004,7 @@ module \dec_ai$148 wire width 5 input 3 \LOGICAL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out - attribute \src "libresoc.v:126103.7-126103.15" + attribute \src "libresoc.v:125899.7-125899.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra @@ -197223,7 +197019,7 @@ module \dec_ai$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - cell $and $and$libresoc.v:126131$4797 + cell $and $and$libresoc.v:125927$4797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197231,10 +197027,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126131$4797_Y + connect \Y $and$libresoc.v:125927$4797_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $and $and$libresoc.v:126134$4800 + cell $and $and$libresoc.v:125930$4800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197242,10 +197038,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126134$4800_Y + connect \Y $and$libresoc.v:125930$4800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $eq $eq$libresoc.v:126132$4798 + cell $eq $eq$libresoc.v:125928$4798 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197253,10 +197049,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126132$4798_Y + connect \Y $eq$libresoc.v:125928$4798_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $eq $eq$libresoc.v:126133$4799 + cell $eq $eq$libresoc.v:125929$4799 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197264,10 +197060,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126133$4799_Y + connect \Y $eq$libresoc.v:125929$4799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - cell $eq $eq$libresoc.v:126135$4801 + cell $eq $eq$libresoc.v:125931$4801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197275,24 +197071,24 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126135$4801_Y + connect \Y $eq$libresoc.v:125931$4801_Y end - attribute \src "libresoc.v:126103.7-126103.20" - process $proc$libresoc.v:126103$4803 + attribute \src "libresoc.v:125899.7-125899.20" + process $proc$libresoc.v:125899$4803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126136.3-126145.6" - process $proc$libresoc.v:126136$4802 + attribute \src "libresoc.v:125932.3-125941.6" + process $proc$libresoc.v:125932$4802 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126137.5-126137.29" + attribute \src "libresoc.v:125933.5-125933.29" switch \initial - attribute \src "libresoc.v:126137.9-126137.17" + attribute \src "libresoc.v:125933.9-125933.17" case 1'1 case end @@ -197308,34 +197104,34 @@ module \dec_ai$148 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126131$4797_Y - connect \$1 $eq$libresoc.v:126132$4798_Y - connect \$3 $eq$libresoc.v:126133$4799_Y - connect \$5 $and$libresoc.v:126134$4800_Y - connect \$7 $eq$libresoc.v:126135$4801_Y + connect \$9 $and$libresoc.v:125927$4797_Y + connect \$1 $eq$libresoc.v:125928$4798_Y + connect \$3 $eq$libresoc.v:125929$4799_Y + connect \$5 $and$libresoc.v:125930$4800_Y + connect \$7 $eq$libresoc.v:125931$4801_Y connect \ra \LOGICAL_RA end -attribute \src "libresoc.v:126151.1-126196.10" +attribute \src "libresoc.v:125947.1-125992.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai" attribute \generator "nMigen" module \dec_ai$156 - attribute \src "libresoc.v:126185.3-126194.6" + attribute \src "libresoc.v:125981.3-125990.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126152.7-126152.20" + attribute \src "libresoc.v:125948.7-125948.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126185.3-126194.6" + attribute \src "libresoc.v:125981.3-125990.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126180.17-126180.107" - wire $and$libresoc.v:126180$4804_Y - attribute \src "libresoc.v:126183.17-126183.107" - wire $and$libresoc.v:126183$4807_Y - attribute \src "libresoc.v:126181.17-126181.111" - wire $eq$libresoc.v:126181$4805_Y - attribute \src "libresoc.v:126182.17-126182.108" - wire $eq$libresoc.v:126182$4806_Y - attribute \src "libresoc.v:126184.17-126184.110" - wire $eq$libresoc.v:126184$4808_Y + attribute \src "libresoc.v:125976.17-125976.107" + wire $and$libresoc.v:125976$4804_Y + attribute \src "libresoc.v:125979.17-125979.107" + wire $and$libresoc.v:125979$4807_Y + attribute \src "libresoc.v:125977.17-125977.111" + wire $eq$libresoc.v:125977$4805_Y + attribute \src "libresoc.v:125978.17-125978.108" + wire $eq$libresoc.v:125978$4806_Y + attribute \src "libresoc.v:125980.17-125980.110" + wire $eq$libresoc.v:125980$4808_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" @@ -197350,7 +197146,7 @@ module \dec_ai$156 wire width 5 input 3 \DIV_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out - attribute \src "libresoc.v:126152.7-126152.15" + attribute \src "libresoc.v:125948.7-125948.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra @@ -197365,7 +197161,7 @@ module \dec_ai$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - cell $and $and$libresoc.v:126180$4804 + cell $and $and$libresoc.v:125976$4804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197373,10 +197169,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126180$4804_Y + connect \Y $and$libresoc.v:125976$4804_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $and $and$libresoc.v:126183$4807 + cell $and $and$libresoc.v:125979$4807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197384,10 +197180,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126183$4807_Y + connect \Y $and$libresoc.v:125979$4807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $eq $eq$libresoc.v:126181$4805 + cell $eq $eq$libresoc.v:125977$4805 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197395,10 +197191,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126181$4805_Y + connect \Y $eq$libresoc.v:125977$4805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $eq $eq$libresoc.v:126182$4806 + cell $eq $eq$libresoc.v:125978$4806 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197406,10 +197202,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126182$4806_Y + connect \Y $eq$libresoc.v:125978$4806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - cell $eq $eq$libresoc.v:126184$4808 + cell $eq $eq$libresoc.v:125980$4808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197417,24 +197213,24 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126184$4808_Y + connect \Y $eq$libresoc.v:125980$4808_Y end - attribute \src "libresoc.v:126152.7-126152.20" - process $proc$libresoc.v:126152$4810 + attribute \src "libresoc.v:125948.7-125948.20" + process $proc$libresoc.v:125948$4810 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126185.3-126194.6" - process $proc$libresoc.v:126185$4809 + attribute \src "libresoc.v:125981.3-125990.6" + process $proc$libresoc.v:125981$4809 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126186.5-126186.29" + attribute \src "libresoc.v:125982.5-125982.29" switch \initial - attribute \src "libresoc.v:126186.9-126186.17" + attribute \src "libresoc.v:125982.9-125982.17" case 1'1 case end @@ -197450,34 +197246,34 @@ module \dec_ai$156 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126180$4804_Y - connect \$1 $eq$libresoc.v:126181$4805_Y - connect \$3 $eq$libresoc.v:126182$4806_Y - connect \$5 $and$libresoc.v:126183$4807_Y - connect \$7 $eq$libresoc.v:126184$4808_Y + connect \$9 $and$libresoc.v:125976$4804_Y + connect \$1 $eq$libresoc.v:125977$4805_Y + connect \$3 $eq$libresoc.v:125978$4806_Y + connect \$5 $and$libresoc.v:125979$4807_Y + connect \$7 $eq$libresoc.v:125980$4808_Y connect \ra \DIV_RA end -attribute \src "libresoc.v:126200.1-126245.10" +attribute \src "libresoc.v:125996.1-126041.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai" attribute \generator "nMigen" module \dec_ai$169 - attribute \src "libresoc.v:126234.3-126243.6" + attribute \src "libresoc.v:126030.3-126039.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126201.7-126201.20" + attribute \src "libresoc.v:125997.7-125997.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126234.3-126243.6" + attribute \src "libresoc.v:126030.3-126039.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126229.17-126229.107" - wire $and$libresoc.v:126229$4811_Y - attribute \src "libresoc.v:126232.17-126232.107" - wire $and$libresoc.v:126232$4814_Y - attribute \src "libresoc.v:126230.17-126230.111" - wire $eq$libresoc.v:126230$4812_Y - attribute \src "libresoc.v:126231.17-126231.108" - wire $eq$libresoc.v:126231$4813_Y - attribute \src "libresoc.v:126233.17-126233.110" - wire $eq$libresoc.v:126233$4815_Y + attribute \src "libresoc.v:126025.17-126025.107" + wire $and$libresoc.v:126025$4811_Y + attribute \src "libresoc.v:126028.17-126028.107" + wire $and$libresoc.v:126028$4814_Y + attribute \src "libresoc.v:126026.17-126026.111" + wire $eq$libresoc.v:126026$4812_Y + attribute \src "libresoc.v:126027.17-126027.108" + wire $eq$libresoc.v:126027$4813_Y + attribute \src "libresoc.v:126029.17-126029.110" + wire $eq$libresoc.v:126029$4815_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" @@ -197492,7 +197288,7 @@ module \dec_ai$169 wire width 5 input 3 \LDST_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out - attribute \src "libresoc.v:126201.7-126201.15" + attribute \src "libresoc.v:125997.7-125997.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra @@ -197507,7 +197303,7 @@ module \dec_ai$169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - cell $and $and$libresoc.v:126229$4811 + cell $and $and$libresoc.v:126025$4811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197515,10 +197311,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126229$4811_Y + connect \Y $and$libresoc.v:126025$4811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $and $and$libresoc.v:126232$4814 + cell $and $and$libresoc.v:126028$4814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197526,10 +197322,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126232$4814_Y + connect \Y $and$libresoc.v:126028$4814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $eq $eq$libresoc.v:126230$4812 + cell $eq $eq$libresoc.v:126026$4812 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197537,10 +197333,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126230$4812_Y + connect \Y $eq$libresoc.v:126026$4812_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" - cell $eq $eq$libresoc.v:126231$4813 + cell $eq $eq$libresoc.v:126027$4813 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197548,10 +197344,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126231$4813_Y + connect \Y $eq$libresoc.v:126027$4813_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - cell $eq $eq$libresoc.v:126233$4815 + cell $eq $eq$libresoc.v:126029$4815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197559,24 +197355,24 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126233$4815_Y + connect \Y $eq$libresoc.v:126029$4815_Y end - attribute \src "libresoc.v:126201.7-126201.20" - process $proc$libresoc.v:126201$4817 + attribute \src "libresoc.v:125997.7-125997.20" + process $proc$libresoc.v:125997$4817 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126234.3-126243.6" - process $proc$libresoc.v:126234$4816 + attribute \src "libresoc.v:126030.3-126039.6" + process $proc$libresoc.v:126030$4816 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126235.5-126235.29" + attribute \src "libresoc.v:126031.5-126031.29" switch \initial - attribute \src "libresoc.v:126235.9-126235.17" + attribute \src "libresoc.v:126031.9-126031.17" case 1'1 case end @@ -197592,56 +197388,56 @@ module \dec_ai$169 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126229$4811_Y - connect \$1 $eq$libresoc.v:126230$4812_Y - connect \$3 $eq$libresoc.v:126231$4813_Y - connect \$5 $and$libresoc.v:126232$4814_Y - connect \$7 $eq$libresoc.v:126233$4815_Y + connect \$9 $and$libresoc.v:126025$4811_Y + connect \$1 $eq$libresoc.v:126026$4812_Y + connect \$3 $eq$libresoc.v:126027$4813_Y + connect \$5 $and$libresoc.v:126028$4814_Y + connect \$7 $eq$libresoc.v:126029$4815_Y connect \ra \LDST_RA end -attribute \src "libresoc.v:126249.1-126447.10" +attribute \src "libresoc.v:126045.1-126243.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" attribute \generator "nMigen" module \dec_b - attribute \src "libresoc.v:126411.3-126428.6" + attribute \src "libresoc.v:126207.3-126224.6" wire width 3 $0\fast_b[2:0] - attribute \src "libresoc.v:126429.3-126446.6" + attribute \src "libresoc.v:126225.3-126242.6" wire $0\fast_b_ok[0:0] - attribute \src "libresoc.v:126250.7-126250.20" + attribute \src "libresoc.v:126046.7-126046.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126381.3-126395.6" + attribute \src "libresoc.v:126177.3-126191.6" wire width 7 $0\reg_b[6:0] - attribute \src "libresoc.v:126396.3-126410.6" + attribute \src "libresoc.v:126192.3-126206.6" wire $0\reg_b_ok[0:0] - attribute \src "libresoc.v:126411.3-126428.6" + attribute \src "libresoc.v:126207.3-126224.6" wire width 3 $1\fast_b[2:0] - attribute \src "libresoc.v:126429.3-126446.6" + attribute \src "libresoc.v:126225.3-126242.6" wire $1\fast_b_ok[0:0] - attribute \src "libresoc.v:126381.3-126395.6" + attribute \src "libresoc.v:126177.3-126191.6" wire width 7 $1\reg_b[6:0] - attribute \src "libresoc.v:126396.3-126410.6" + attribute \src "libresoc.v:126192.3-126206.6" wire $1\reg_b_ok[0:0] - attribute \src "libresoc.v:126411.3-126428.6" + attribute \src "libresoc.v:126207.3-126224.6" wire width 3 $2\fast_b[2:0] - attribute \src "libresoc.v:126429.3-126446.6" + attribute \src "libresoc.v:126225.3-126242.6" wire $2\fast_b_ok[0:0] - attribute \src "libresoc.v:126375.17-126375.117" - wire $eq$libresoc.v:126375$4818_Y - attribute \src "libresoc.v:126379.17-126379.117" - wire $eq$libresoc.v:126379$4824_Y - attribute \src "libresoc.v:126377.17-126377.100" - wire width 7 $extend$libresoc.v:126377$4820_Y - attribute \src "libresoc.v:126378.17-126378.100" - wire width 7 $extend$libresoc.v:126378$4822_Y - attribute \src "libresoc.v:126376.18-126376.108" - wire $not$libresoc.v:126376$4819_Y - attribute \src "libresoc.v:126380.17-126380.107" - wire $not$libresoc.v:126380$4825_Y - attribute \src "libresoc.v:126377.17-126377.100" - wire width 7 $pos$libresoc.v:126377$4821_Y - attribute \src "libresoc.v:126378.17-126378.100" - wire width 7 $pos$libresoc.v:126378$4823_Y + attribute \src "libresoc.v:126171.17-126171.117" + wire $eq$libresoc.v:126171$4818_Y + attribute \src "libresoc.v:126175.17-126175.117" + wire $eq$libresoc.v:126175$4824_Y + attribute \src "libresoc.v:126173.17-126173.100" + wire width 7 $extend$libresoc.v:126173$4820_Y + attribute \src "libresoc.v:126174.17-126174.100" + wire width 7 $extend$libresoc.v:126174$4822_Y + attribute \src "libresoc.v:126172.18-126172.108" + wire $not$libresoc.v:126172$4819_Y + attribute \src "libresoc.v:126176.17-126176.107" + wire $not$libresoc.v:126176$4825_Y + attribute \src "libresoc.v:126173.17-126173.100" + wire width 7 $pos$libresoc.v:126173$4821_Y + attribute \src "libresoc.v:126174.17-126174.100" + wire width 7 $pos$libresoc.v:126174$4823_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" @@ -197664,7 +197460,7 @@ module \dec_b wire width 3 output 4 \fast_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \fast_b_ok - attribute \src "libresoc.v:126250.7-126250.15" + attribute \src "libresoc.v:126046.7-126046.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -197765,7 +197561,7 @@ module \dec_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" wire width 4 input 1 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - cell $eq $eq$libresoc.v:126375$4818 + cell $eq $eq$libresoc.v:126171$4818 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -197773,10 +197569,10 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:126375$4818_Y + connect \Y $eq$libresoc.v:126171$4818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - cell $eq $eq$libresoc.v:126379$4824 + cell $eq $eq$libresoc.v:126175$4824 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -197784,72 +197580,72 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:126379$4824_Y + connect \Y $eq$libresoc.v:126175$4824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126377$4820 + cell $pos $extend$libresoc.v:126173$4820 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RB - connect \Y $extend$libresoc.v:126377$4820_Y + connect \Y $extend$libresoc.v:126173$4820_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126378$4822 + cell $pos $extend$libresoc.v:126174$4822 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RS - connect \Y $extend$libresoc.v:126378$4822_Y + connect \Y $extend$libresoc.v:126174$4822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" - cell $not $not$libresoc.v:126376$4819 + cell $not $not$libresoc.v:126172$4819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:126376$4819_Y + connect \Y $not$libresoc.v:126172$4819_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" - cell $not $not$libresoc.v:126380$4825 + cell $not $not$libresoc.v:126176$4825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:126380$4825_Y + connect \Y $not$libresoc.v:126176$4825_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126377$4821 + cell $pos $pos$libresoc.v:126173$4821 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:126377$4820_Y - connect \Y $pos$libresoc.v:126377$4821_Y + connect \A $extend$libresoc.v:126173$4820_Y + connect \Y $pos$libresoc.v:126173$4821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126378$4823 + cell $pos $pos$libresoc.v:126174$4823 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:126378$4822_Y - connect \Y $pos$libresoc.v:126378$4823_Y + connect \A $extend$libresoc.v:126174$4822_Y + connect \Y $pos$libresoc.v:126174$4823_Y end - attribute \src "libresoc.v:126250.7-126250.20" - process $proc$libresoc.v:126250$4830 + attribute \src "libresoc.v:126046.7-126046.20" + process $proc$libresoc.v:126046$4830 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126381.3-126395.6" - process $proc$libresoc.v:126381$4826 + attribute \src "libresoc.v:126177.3-126191.6" + process $proc$libresoc.v:126177$4826 assign { } { } assign { } { } assign $0\reg_b[6:0] $1\reg_b[6:0] - attribute \src "libresoc.v:126382.5-126382.29" + attribute \src "libresoc.v:126178.5-126178.29" switch \initial - attribute \src "libresoc.v:126382.9-126382.17" + attribute \src "libresoc.v:126178.9-126178.17" case 1'1 case end @@ -197869,14 +197665,14 @@ module \dec_b sync always update \reg_b $0\reg_b[6:0] end - attribute \src "libresoc.v:126396.3-126410.6" - process $proc$libresoc.v:126396$4827 + attribute \src "libresoc.v:126192.3-126206.6" + process $proc$libresoc.v:126192$4827 assign { } { } assign { } { } assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] - attribute \src "libresoc.v:126397.5-126397.29" + attribute \src "libresoc.v:126193.5-126193.29" switch \initial - attribute \src "libresoc.v:126397.9-126397.17" + attribute \src "libresoc.v:126193.9-126193.17" case 1'1 case end @@ -197896,14 +197692,14 @@ module \dec_b sync always update \reg_b_ok $0\reg_b_ok[0:0] end - attribute \src "libresoc.v:126411.3-126428.6" - process $proc$libresoc.v:126411$4828 + attribute \src "libresoc.v:126207.3-126224.6" + process $proc$libresoc.v:126207$4828 assign { } { } assign { } { } assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "libresoc.v:126412.5-126412.29" + attribute \src "libresoc.v:126208.5-126208.29" switch \initial - attribute \src "libresoc.v:126412.9-126412.17" + attribute \src "libresoc.v:126208.9-126208.17" case 1'1 case end @@ -197932,14 +197728,14 @@ module \dec_b sync always update \fast_b $0\fast_b[2:0] end - attribute \src "libresoc.v:126429.3-126446.6" - process $proc$libresoc.v:126429$4829 + attribute \src "libresoc.v:126225.3-126242.6" + process $proc$libresoc.v:126225$4829 assign { } { } assign { } { } assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:126430.5-126430.29" + attribute \src "libresoc.v:126226.5-126226.29" switch \initial - attribute \src "libresoc.v:126430.9-126430.17" + attribute \src "libresoc.v:126226.9-126226.17" case 1'1 case end @@ -197968,78 +197764,78 @@ module \dec_b sync always update \fast_b_ok $0\fast_b_ok[0:0] end - connect \$9 $eq$libresoc.v:126375$4818_Y - connect \$11 $not$libresoc.v:126376$4819_Y - connect \$1 $pos$libresoc.v:126377$4821_Y - connect \$3 $pos$libresoc.v:126378$4823_Y - connect \$5 $eq$libresoc.v:126379$4824_Y - connect \$7 $not$libresoc.v:126380$4825_Y + connect \$9 $eq$libresoc.v:126171$4818_Y + connect \$11 $not$libresoc.v:126172$4819_Y + connect \$1 $pos$libresoc.v:126173$4821_Y + connect \$3 $pos$libresoc.v:126174$4823_Y + connect \$5 $eq$libresoc.v:126175$4824_Y + connect \$7 $not$libresoc.v:126176$4825_Y end -attribute \src "libresoc.v:126451.1-126788.10" +attribute \src "libresoc.v:126247.1-126584.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" attribute \generator "nMigen" module \dec_bi - attribute \src "libresoc.v:126718.3-126748.6" + attribute \src "libresoc.v:126514.3-126544.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:126749.3-126783.6" + attribute \src "libresoc.v:126545.3-126579.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126540.3-126586.6" + attribute \src "libresoc.v:126336.3-126382.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126587.3-126633.6" + attribute \src "libresoc.v:126383.3-126429.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:126452.7-126452.20" + attribute \src "libresoc.v:126248.7-126248.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126691.3-126717.6" + attribute \src "libresoc.v:126487.3-126513.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126634.3-126648.6" + attribute \src "libresoc.v:126430.3-126444.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126649.3-126667.6" + attribute \src "libresoc.v:126445.3-126463.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:126668.3-126690.6" + attribute \src "libresoc.v:126464.3-126486.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:126718.3-126748.6" + attribute \src "libresoc.v:126514.3-126544.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:126749.3-126783.6" + attribute \src "libresoc.v:126545.3-126579.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126540.3-126586.6" + attribute \src "libresoc.v:126336.3-126382.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126587.3-126633.6" + attribute \src "libresoc.v:126383.3-126429.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126691.3-126717.6" + attribute \src "libresoc.v:126487.3-126513.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126634.3-126648.6" + attribute \src "libresoc.v:126430.3-126444.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126649.3-126667.6" + attribute \src "libresoc.v:126445.3-126463.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:126668.3-126690.6" + attribute \src "libresoc.v:126464.3-126486.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126530.17-126530.104" - wire width 64 $extend$libresoc.v:126530$4831_Y - attribute \src "libresoc.v:126531.18-126531.107" - wire width 64 $extend$libresoc.v:126531$4833_Y - attribute \src "libresoc.v:126534.17-126534.104" - wire width 64 $extend$libresoc.v:126534$4837_Y - attribute \src "libresoc.v:126538.17-126538.102" - wire width 64 $extend$libresoc.v:126538$4842_Y - attribute \src "libresoc.v:126530.17-126530.104" - wire width 64 $pos$libresoc.v:126530$4832_Y - attribute \src "libresoc.v:126531.18-126531.107" - wire width 64 $pos$libresoc.v:126531$4834_Y - attribute \src "libresoc.v:126534.17-126534.104" - wire width 64 $pos$libresoc.v:126534$4838_Y - attribute \src "libresoc.v:126538.17-126538.102" - wire width 64 $pos$libresoc.v:126538$4843_Y - attribute \src "libresoc.v:126532.18-126532.114" - wire width 47 $sshl$libresoc.v:126532$4835_Y - attribute \src "libresoc.v:126533.18-126533.113" - wire width 27 $sshl$libresoc.v:126533$4836_Y - attribute \src "libresoc.v:126535.18-126535.113" - wire width 17 $sshl$libresoc.v:126535$4839_Y - attribute \src "libresoc.v:126536.18-126536.113" - wire width 17 $sshl$libresoc.v:126536$4840_Y - attribute \src "libresoc.v:126537.17-126537.109" - wire width 47 $sshl$libresoc.v:126537$4841_Y + attribute \src "libresoc.v:126326.17-126326.104" + wire width 64 $extend$libresoc.v:126326$4831_Y + attribute \src "libresoc.v:126327.18-126327.107" + wire width 64 $extend$libresoc.v:126327$4833_Y + attribute \src "libresoc.v:126330.17-126330.104" + wire width 64 $extend$libresoc.v:126330$4837_Y + attribute \src "libresoc.v:126334.17-126334.102" + wire width 64 $extend$libresoc.v:126334$4842_Y + attribute \src "libresoc.v:126326.17-126326.104" + wire width 64 $pos$libresoc.v:126326$4832_Y + attribute \src "libresoc.v:126327.18-126327.107" + wire width 64 $pos$libresoc.v:126327$4834_Y + attribute \src "libresoc.v:126330.17-126330.104" + wire width 64 $pos$libresoc.v:126330$4838_Y + attribute \src "libresoc.v:126334.17-126334.102" + wire width 64 $pos$libresoc.v:126334$4843_Y + attribute \src "libresoc.v:126328.18-126328.114" + wire width 47 $sshl$libresoc.v:126328$4835_Y + attribute \src "libresoc.v:126329.18-126329.113" + wire width 27 $sshl$libresoc.v:126329$4836_Y + attribute \src "libresoc.v:126331.18-126331.113" + wire width 17 $sshl$libresoc.v:126331$4839_Y + attribute \src "libresoc.v:126332.18-126332.113" + wire width 17 $sshl$libresoc.v:126332$4840_Y + attribute \src "libresoc.v:126333.17-126333.109" + wire width 47 $sshl$libresoc.v:126333$4841_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -198090,7 +197886,7 @@ module \dec_bi wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:126452.7-126452.15" + attribute \src "libresoc.v:126248.7-126248.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li @@ -198118,71 +197914,71 @@ module \dec_bi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126530$4831 + cell $pos $extend$libresoc.v:126326$4831 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \ALU_sh - connect \Y $extend$libresoc.v:126530$4831_Y + connect \Y $extend$libresoc.v:126326$4831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126531$4833 + cell $pos $extend$libresoc.v:126327$4833 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \ALU_SH32 - connect \Y $extend$libresoc.v:126531$4833_Y + connect \Y $extend$libresoc.v:126327$4833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126534$4837 + cell $pos $extend$libresoc.v:126330$4837 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \ALU_UI - connect \Y $extend$libresoc.v:126534$4837_Y + connect \Y $extend$libresoc.v:126330$4837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $extend$libresoc.v:126538$4842 + cell $pos $extend$libresoc.v:126334$4842 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126538$4842_Y + connect \Y $extend$libresoc.v:126334$4842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126530$4832 + cell $pos $pos$libresoc.v:126326$4832 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126530$4831_Y - connect \Y $pos$libresoc.v:126530$4832_Y + connect \A $extend$libresoc.v:126326$4831_Y + connect \Y $pos$libresoc.v:126326$4832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126531$4834 + cell $pos $pos$libresoc.v:126327$4834 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126531$4833_Y - connect \Y $pos$libresoc.v:126531$4834_Y + connect \A $extend$libresoc.v:126327$4833_Y + connect \Y $pos$libresoc.v:126327$4834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126534$4838 + cell $pos $pos$libresoc.v:126330$4838 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126534$4837_Y - connect \Y $pos$libresoc.v:126534$4838_Y + connect \A $extend$libresoc.v:126330$4837_Y + connect \Y $pos$libresoc.v:126330$4838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $pos$libresoc.v:126538$4843 + cell $pos $pos$libresoc.v:126334$4843 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126538$4842_Y - connect \Y $pos$libresoc.v:126538$4843_Y + connect \A $extend$libresoc.v:126334$4842_Y + connect \Y $pos$libresoc.v:126334$4843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - cell $sshl $sshl$libresoc.v:126532$4835 + cell $sshl $sshl$libresoc.v:126328$4835 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198190,10 +197986,10 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ALU_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126532$4835_Y + connect \Y $sshl$libresoc.v:126328$4835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" - cell $sshl $sshl$libresoc.v:126533$4836 + cell $sshl $sshl$libresoc.v:126329$4836 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -198201,10 +197997,10 @@ module \dec_bi parameter \Y_WIDTH 27 connect \A \ALU_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126533$4836_Y + connect \Y $sshl$libresoc.v:126329$4836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" - cell $sshl $sshl$libresoc.v:126535$4839 + cell $sshl $sshl$libresoc.v:126331$4839 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198212,10 +198008,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126535$4839_Y + connect \Y $sshl$libresoc.v:126331$4839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - cell $sshl $sshl$libresoc.v:126536$4840 + cell $sshl $sshl$libresoc.v:126332$4840 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198223,10 +198019,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126536$4840_Y + connect \Y $sshl$libresoc.v:126332$4840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $sshl $sshl$libresoc.v:126537$4841 + cell $sshl $sshl$libresoc.v:126333$4841 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198234,24 +198030,24 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126537$4841_Y + connect \Y $sshl$libresoc.v:126333$4841_Y end - attribute \src "libresoc.v:126452.7-126452.20" - process $proc$libresoc.v:126452$4852 + attribute \src "libresoc.v:126248.7-126248.20" + process $proc$libresoc.v:126248$4852 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126540.3-126586.6" - process $proc$libresoc.v:126540$4844 + attribute \src "libresoc.v:126336.3-126382.6" + process $proc$libresoc.v:126336$4844 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126541.5-126541.29" + attribute \src "libresoc.v:126337.5-126337.29" switch \initial - attribute \src "libresoc.v:126541.9-126541.17" + attribute \src "libresoc.v:126337.9-126337.17" case 1'1 case end @@ -198303,14 +198099,14 @@ module \dec_bi sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126587.3-126633.6" - process $proc$libresoc.v:126587$4845 + attribute \src "libresoc.v:126383.3-126429.6" + process $proc$libresoc.v:126383$4845 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126588.5-126588.29" + attribute \src "libresoc.v:126384.5-126384.29" switch \initial - attribute \src "libresoc.v:126588.9-126588.17" + attribute \src "libresoc.v:126384.9-126384.17" case 1'1 case end @@ -198362,14 +198158,14 @@ module \dec_bi sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126634.3-126648.6" - process $proc$libresoc.v:126634$4846 + attribute \src "libresoc.v:126430.3-126444.6" + process $proc$libresoc.v:126430$4846 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126635.5-126635.29" + attribute \src "libresoc.v:126431.5-126431.29" switch \initial - attribute \src "libresoc.v:126635.9-126635.17" + attribute \src "libresoc.v:126431.9-126431.17" case 1'1 case end @@ -198388,14 +198184,14 @@ module \dec_bi sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126649.3-126667.6" - process $proc$libresoc.v:126649$4847 + attribute \src "libresoc.v:126445.3-126463.6" + process $proc$libresoc.v:126445$4847 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126650.5-126650.29" + attribute \src "libresoc.v:126446.5-126446.29" switch \initial - attribute \src "libresoc.v:126650.9-126650.17" + attribute \src "libresoc.v:126446.9-126446.17" case 1'1 case end @@ -198417,14 +198213,14 @@ module \dec_bi sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:126668.3-126690.6" - process $proc$libresoc.v:126668$4848 + attribute \src "libresoc.v:126464.3-126486.6" + process $proc$libresoc.v:126464$4848 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:126669.5-126669.29" + attribute \src "libresoc.v:126465.5-126465.29" switch \initial - attribute \src "libresoc.v:126669.9-126669.17" + attribute \src "libresoc.v:126465.9-126465.17" case 1'1 case end @@ -198449,14 +198245,14 @@ module \dec_bi sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:126691.3-126717.6" - process $proc$libresoc.v:126691$4849 + attribute \src "libresoc.v:126487.3-126513.6" + process $proc$libresoc.v:126487$4849 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:126692.5-126692.29" + attribute \src "libresoc.v:126488.5-126488.29" switch \initial - attribute \src "libresoc.v:126692.9-126692.17" + attribute \src "libresoc.v:126488.9-126488.17" case 1'1 case end @@ -198484,14 +198280,14 @@ module \dec_bi sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:126718.3-126748.6" - process $proc$libresoc.v:126718$4850 + attribute \src "libresoc.v:126514.3-126544.6" + process $proc$libresoc.v:126514$4850 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:126719.5-126719.29" + attribute \src "libresoc.v:126515.5-126515.29" switch \initial - attribute \src "libresoc.v:126719.9-126719.17" + attribute \src "libresoc.v:126515.9-126515.17" case 1'1 case end @@ -198522,14 +198318,14 @@ module \dec_bi sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:126749.3-126783.6" - process $proc$libresoc.v:126749$4851 + attribute \src "libresoc.v:126545.3-126579.6" + process $proc$libresoc.v:126545$4851 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:126750.5-126750.29" + attribute \src "libresoc.v:126546.5-126546.29" switch \initial - attribute \src "libresoc.v:126750.9-126750.17" + attribute \src "libresoc.v:126546.9-126546.17" case 1'1 case end @@ -198563,86 +198359,86 @@ module \dec_bi sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126530$4832_Y - connect \$11 $pos$libresoc.v:126531$4834_Y - connect \$14 $sshl$libresoc.v:126532$4835_Y - connect \$17 $sshl$libresoc.v:126533$4836_Y - connect \$1 $pos$libresoc.v:126534$4838_Y - connect \$20 $sshl$libresoc.v:126535$4839_Y - connect \$23 $sshl$libresoc.v:126536$4840_Y - connect \$4 $sshl$libresoc.v:126537$4841_Y - connect \$3 $pos$libresoc.v:126538$4843_Y + connect \$9 $pos$libresoc.v:126326$4832_Y + connect \$11 $pos$libresoc.v:126327$4834_Y + connect \$14 $sshl$libresoc.v:126328$4835_Y + connect \$17 $sshl$libresoc.v:126329$4836_Y + connect \$1 $pos$libresoc.v:126330$4838_Y + connect \$20 $sshl$libresoc.v:126331$4839_Y + connect \$23 $sshl$libresoc.v:126332$4840_Y + connect \$4 $sshl$libresoc.v:126333$4841_Y + connect \$3 $pos$libresoc.v:126334$4843_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:126792.1-127129.10" +attribute \src "libresoc.v:126588.1-126925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" attribute \generator "nMigen" module \dec_bi$144 - attribute \src "libresoc.v:127059.3-127089.6" + attribute \src "libresoc.v:126855.3-126885.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:127090.3-127124.6" + attribute \src "libresoc.v:126886.3-126920.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126881.3-126927.6" + attribute \src "libresoc.v:126677.3-126723.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126928.3-126974.6" + attribute \src "libresoc.v:126724.3-126770.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:126793.7-126793.20" + attribute \src "libresoc.v:126589.7-126589.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127032.3-127058.6" + attribute \src "libresoc.v:126828.3-126854.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126975.3-126989.6" + attribute \src "libresoc.v:126771.3-126785.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126990.3-127008.6" + attribute \src "libresoc.v:126786.3-126804.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:127009.3-127031.6" + attribute \src "libresoc.v:126805.3-126827.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:127059.3-127089.6" + attribute \src "libresoc.v:126855.3-126885.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:127090.3-127124.6" + attribute \src "libresoc.v:126886.3-126920.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126881.3-126927.6" + attribute \src "libresoc.v:126677.3-126723.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126928.3-126974.6" + attribute \src "libresoc.v:126724.3-126770.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127032.3-127058.6" + attribute \src "libresoc.v:126828.3-126854.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126975.3-126989.6" + attribute \src "libresoc.v:126771.3-126785.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126990.3-127008.6" + attribute \src "libresoc.v:126786.3-126804.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:127009.3-127031.6" + attribute \src "libresoc.v:126805.3-126827.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126871.17-126871.107" - wire width 64 $extend$libresoc.v:126871$4853_Y - attribute \src "libresoc.v:126872.18-126872.110" - wire width 64 $extend$libresoc.v:126872$4855_Y - attribute \src "libresoc.v:126875.17-126875.107" - wire width 64 $extend$libresoc.v:126875$4859_Y - attribute \src "libresoc.v:126879.17-126879.102" - wire width 64 $extend$libresoc.v:126879$4864_Y - attribute \src "libresoc.v:126871.17-126871.107" - wire width 64 $pos$libresoc.v:126871$4854_Y - attribute \src "libresoc.v:126872.18-126872.110" - wire width 64 $pos$libresoc.v:126872$4856_Y - attribute \src "libresoc.v:126875.17-126875.107" - wire width 64 $pos$libresoc.v:126875$4860_Y - attribute \src "libresoc.v:126879.17-126879.102" - wire width 64 $pos$libresoc.v:126879$4865_Y - attribute \src "libresoc.v:126873.18-126873.117" - wire width 47 $sshl$libresoc.v:126873$4857_Y - attribute \src "libresoc.v:126874.18-126874.116" - wire width 27 $sshl$libresoc.v:126874$4858_Y - attribute \src "libresoc.v:126876.18-126876.116" - wire width 17 $sshl$libresoc.v:126876$4861_Y - attribute \src "libresoc.v:126877.18-126877.116" - wire width 17 $sshl$libresoc.v:126877$4862_Y - attribute \src "libresoc.v:126878.17-126878.109" - wire width 47 $sshl$libresoc.v:126878$4863_Y + attribute \src "libresoc.v:126667.17-126667.107" + wire width 64 $extend$libresoc.v:126667$4853_Y + attribute \src "libresoc.v:126668.18-126668.110" + wire width 64 $extend$libresoc.v:126668$4855_Y + attribute \src "libresoc.v:126671.17-126671.107" + wire width 64 $extend$libresoc.v:126671$4859_Y + attribute \src "libresoc.v:126675.17-126675.102" + wire width 64 $extend$libresoc.v:126675$4864_Y + attribute \src "libresoc.v:126667.17-126667.107" + wire width 64 $pos$libresoc.v:126667$4854_Y + attribute \src "libresoc.v:126668.18-126668.110" + wire width 64 $pos$libresoc.v:126668$4856_Y + attribute \src "libresoc.v:126671.17-126671.107" + wire width 64 $pos$libresoc.v:126671$4860_Y + attribute \src "libresoc.v:126675.17-126675.102" + wire width 64 $pos$libresoc.v:126675$4865_Y + attribute \src "libresoc.v:126669.18-126669.117" + wire width 47 $sshl$libresoc.v:126669$4857_Y + attribute \src "libresoc.v:126670.18-126670.116" + wire width 27 $sshl$libresoc.v:126670$4858_Y + attribute \src "libresoc.v:126672.18-126672.116" + wire width 17 $sshl$libresoc.v:126672$4861_Y + attribute \src "libresoc.v:126673.18-126673.116" + wire width 17 $sshl$libresoc.v:126673$4862_Y + attribute \src "libresoc.v:126674.17-126674.109" + wire width 47 $sshl$libresoc.v:126674$4863_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -198693,7 +198489,7 @@ module \dec_bi$144 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:126793.7-126793.15" + attribute \src "libresoc.v:126589.7-126589.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li @@ -198721,71 +198517,71 @@ module \dec_bi$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126871$4853 + cell $pos $extend$libresoc.v:126667$4853 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \BRANCH_sh - connect \Y $extend$libresoc.v:126871$4853_Y + connect \Y $extend$libresoc.v:126667$4853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126872$4855 + cell $pos $extend$libresoc.v:126668$4855 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \BRANCH_SH32 - connect \Y $extend$libresoc.v:126872$4855_Y + connect \Y $extend$libresoc.v:126668$4855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126875$4859 + cell $pos $extend$libresoc.v:126671$4859 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \BRANCH_UI - connect \Y $extend$libresoc.v:126875$4859_Y + connect \Y $extend$libresoc.v:126671$4859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $extend$libresoc.v:126879$4864 + cell $pos $extend$libresoc.v:126675$4864 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126879$4864_Y + connect \Y $extend$libresoc.v:126675$4864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126871$4854 + cell $pos $pos$libresoc.v:126667$4854 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126871$4853_Y - connect \Y $pos$libresoc.v:126871$4854_Y + connect \A $extend$libresoc.v:126667$4853_Y + connect \Y $pos$libresoc.v:126667$4854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126872$4856 + cell $pos $pos$libresoc.v:126668$4856 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126872$4855_Y - connect \Y $pos$libresoc.v:126872$4856_Y + connect \A $extend$libresoc.v:126668$4855_Y + connect \Y $pos$libresoc.v:126668$4856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126875$4860 + cell $pos $pos$libresoc.v:126671$4860 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126875$4859_Y - connect \Y $pos$libresoc.v:126875$4860_Y + connect \A $extend$libresoc.v:126671$4859_Y + connect \Y $pos$libresoc.v:126671$4860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $pos$libresoc.v:126879$4865 + cell $pos $pos$libresoc.v:126675$4865 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126879$4864_Y - connect \Y $pos$libresoc.v:126879$4865_Y + connect \A $extend$libresoc.v:126675$4864_Y + connect \Y $pos$libresoc.v:126675$4865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - cell $sshl $sshl$libresoc.v:126873$4857 + cell $sshl $sshl$libresoc.v:126669$4857 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198793,10 +198589,10 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \BRANCH_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126873$4857_Y + connect \Y $sshl$libresoc.v:126669$4857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" - cell $sshl $sshl$libresoc.v:126874$4858 + cell $sshl $sshl$libresoc.v:126670$4858 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -198804,10 +198600,10 @@ module \dec_bi$144 parameter \Y_WIDTH 27 connect \A \BRANCH_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126874$4858_Y + connect \Y $sshl$libresoc.v:126670$4858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" - cell $sshl $sshl$libresoc.v:126876$4861 + cell $sshl $sshl$libresoc.v:126672$4861 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198815,10 +198611,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126876$4861_Y + connect \Y $sshl$libresoc.v:126672$4861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - cell $sshl $sshl$libresoc.v:126877$4862 + cell $sshl $sshl$libresoc.v:126673$4862 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198826,10 +198622,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126877$4862_Y + connect \Y $sshl$libresoc.v:126673$4862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $sshl $sshl$libresoc.v:126878$4863 + cell $sshl $sshl$libresoc.v:126674$4863 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198837,24 +198633,24 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126878$4863_Y + connect \Y $sshl$libresoc.v:126674$4863_Y end - attribute \src "libresoc.v:126793.7-126793.20" - process $proc$libresoc.v:126793$4874 + attribute \src "libresoc.v:126589.7-126589.20" + process $proc$libresoc.v:126589$4874 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126881.3-126927.6" - process $proc$libresoc.v:126881$4866 + attribute \src "libresoc.v:126677.3-126723.6" + process $proc$libresoc.v:126677$4866 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126882.5-126882.29" + attribute \src "libresoc.v:126678.5-126678.29" switch \initial - attribute \src "libresoc.v:126882.9-126882.17" + attribute \src "libresoc.v:126678.9-126678.17" case 1'1 case end @@ -198906,14 +198702,14 @@ module \dec_bi$144 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126928.3-126974.6" - process $proc$libresoc.v:126928$4867 + attribute \src "libresoc.v:126724.3-126770.6" + process $proc$libresoc.v:126724$4867 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126929.5-126929.29" + attribute \src "libresoc.v:126725.5-126725.29" switch \initial - attribute \src "libresoc.v:126929.9-126929.17" + attribute \src "libresoc.v:126725.9-126725.17" case 1'1 case end @@ -198965,14 +198761,14 @@ module \dec_bi$144 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126975.3-126989.6" - process $proc$libresoc.v:126975$4868 + attribute \src "libresoc.v:126771.3-126785.6" + process $proc$libresoc.v:126771$4868 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126976.5-126976.29" + attribute \src "libresoc.v:126772.5-126772.29" switch \initial - attribute \src "libresoc.v:126976.9-126976.17" + attribute \src "libresoc.v:126772.9-126772.17" case 1'1 case end @@ -198991,14 +198787,14 @@ module \dec_bi$144 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126990.3-127008.6" - process $proc$libresoc.v:126990$4869 + attribute \src "libresoc.v:126786.3-126804.6" + process $proc$libresoc.v:126786$4869 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126991.5-126991.29" + attribute \src "libresoc.v:126787.5-126787.29" switch \initial - attribute \src "libresoc.v:126991.9-126991.17" + attribute \src "libresoc.v:126787.9-126787.17" case 1'1 case end @@ -199020,14 +198816,14 @@ module \dec_bi$144 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:127009.3-127031.6" - process $proc$libresoc.v:127009$4870 + attribute \src "libresoc.v:126805.3-126827.6" + process $proc$libresoc.v:126805$4870 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:127010.5-127010.29" + attribute \src "libresoc.v:126806.5-126806.29" switch \initial - attribute \src "libresoc.v:127010.9-127010.17" + attribute \src "libresoc.v:126806.9-126806.17" case 1'1 case end @@ -199052,14 +198848,14 @@ module \dec_bi$144 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:127032.3-127058.6" - process $proc$libresoc.v:127032$4871 + attribute \src "libresoc.v:126828.3-126854.6" + process $proc$libresoc.v:126828$4871 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:127033.5-127033.29" + attribute \src "libresoc.v:126829.5-126829.29" switch \initial - attribute \src "libresoc.v:127033.9-127033.17" + attribute \src "libresoc.v:126829.9-126829.17" case 1'1 case end @@ -199087,14 +198883,14 @@ module \dec_bi$144 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:127059.3-127089.6" - process $proc$libresoc.v:127059$4872 + attribute \src "libresoc.v:126855.3-126885.6" + process $proc$libresoc.v:126855$4872 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:127060.5-127060.29" + attribute \src "libresoc.v:126856.5-126856.29" switch \initial - attribute \src "libresoc.v:127060.9-127060.17" + attribute \src "libresoc.v:126856.9-126856.17" case 1'1 case end @@ -199125,14 +198921,14 @@ module \dec_bi$144 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:127090.3-127124.6" - process $proc$libresoc.v:127090$4873 + attribute \src "libresoc.v:126886.3-126920.6" + process $proc$libresoc.v:126886$4873 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:127091.5-127091.29" + attribute \src "libresoc.v:126887.5-126887.29" switch \initial - attribute \src "libresoc.v:127091.9-127091.17" + attribute \src "libresoc.v:126887.9-126887.17" case 1'1 case end @@ -199166,86 +198962,86 @@ module \dec_bi$144 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126871$4854_Y - connect \$11 $pos$libresoc.v:126872$4856_Y - connect \$14 $sshl$libresoc.v:126873$4857_Y - connect \$17 $sshl$libresoc.v:126874$4858_Y - connect \$1 $pos$libresoc.v:126875$4860_Y - connect \$20 $sshl$libresoc.v:126876$4861_Y - connect \$23 $sshl$libresoc.v:126877$4862_Y - connect \$4 $sshl$libresoc.v:126878$4863_Y - connect \$3 $pos$libresoc.v:126879$4865_Y + connect \$9 $pos$libresoc.v:126667$4854_Y + connect \$11 $pos$libresoc.v:126668$4856_Y + connect \$14 $sshl$libresoc.v:126669$4857_Y + connect \$17 $sshl$libresoc.v:126670$4858_Y + connect \$1 $pos$libresoc.v:126671$4860_Y + connect \$20 $sshl$libresoc.v:126672$4861_Y + connect \$23 $sshl$libresoc.v:126673$4862_Y + connect \$4 $sshl$libresoc.v:126674$4863_Y + connect \$3 $pos$libresoc.v:126675$4865_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:127133.1-127470.10" +attribute \src "libresoc.v:126929.1-127266.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" attribute \generator "nMigen" module \dec_bi$149 - attribute \src "libresoc.v:127400.3-127430.6" + attribute \src "libresoc.v:127196.3-127226.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:127431.3-127465.6" + attribute \src "libresoc.v:127227.3-127261.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:127222.3-127268.6" + attribute \src "libresoc.v:127018.3-127064.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:127269.3-127315.6" + attribute \src "libresoc.v:127065.3-127111.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:127134.7-127134.20" + attribute \src "libresoc.v:126930.7-126930.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127373.3-127399.6" + attribute \src "libresoc.v:127169.3-127195.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:127316.3-127330.6" + attribute \src "libresoc.v:127112.3-127126.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:127331.3-127349.6" + attribute \src "libresoc.v:127127.3-127145.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:127350.3-127372.6" + attribute \src "libresoc.v:127146.3-127168.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:127400.3-127430.6" + attribute \src "libresoc.v:127196.3-127226.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:127431.3-127465.6" + attribute \src "libresoc.v:127227.3-127261.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:127222.3-127268.6" + attribute \src "libresoc.v:127018.3-127064.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:127269.3-127315.6" + attribute \src "libresoc.v:127065.3-127111.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127373.3-127399.6" + attribute \src "libresoc.v:127169.3-127195.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:127316.3-127330.6" + attribute \src "libresoc.v:127112.3-127126.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:127331.3-127349.6" + attribute \src "libresoc.v:127127.3-127145.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:127350.3-127372.6" + attribute \src "libresoc.v:127146.3-127168.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:127212.17-127212.108" - wire width 64 $extend$libresoc.v:127212$4875_Y - attribute \src "libresoc.v:127213.18-127213.111" - wire width 64 $extend$libresoc.v:127213$4877_Y - attribute \src "libresoc.v:127216.17-127216.108" - wire width 64 $extend$libresoc.v:127216$4881_Y - attribute \src "libresoc.v:127220.17-127220.102" - wire width 64 $extend$libresoc.v:127220$4886_Y - attribute \src "libresoc.v:127212.17-127212.108" - wire width 64 $pos$libresoc.v:127212$4876_Y - attribute \src "libresoc.v:127213.18-127213.111" - wire width 64 $pos$libresoc.v:127213$4878_Y - attribute \src "libresoc.v:127216.17-127216.108" - wire width 64 $pos$libresoc.v:127216$4882_Y - attribute \src "libresoc.v:127220.17-127220.102" - wire width 64 $pos$libresoc.v:127220$4887_Y - attribute \src "libresoc.v:127214.18-127214.118" - wire width 47 $sshl$libresoc.v:127214$4879_Y - attribute \src "libresoc.v:127215.18-127215.117" - wire width 27 $sshl$libresoc.v:127215$4880_Y - attribute \src "libresoc.v:127217.18-127217.117" - wire width 17 $sshl$libresoc.v:127217$4883_Y - attribute \src "libresoc.v:127218.18-127218.117" - wire width 17 $sshl$libresoc.v:127218$4884_Y - attribute \src "libresoc.v:127219.17-127219.109" - wire width 47 $sshl$libresoc.v:127219$4885_Y + attribute \src "libresoc.v:127008.17-127008.108" + wire width 64 $extend$libresoc.v:127008$4875_Y + attribute \src "libresoc.v:127009.18-127009.111" + wire width 64 $extend$libresoc.v:127009$4877_Y + attribute \src "libresoc.v:127012.17-127012.108" + wire width 64 $extend$libresoc.v:127012$4881_Y + attribute \src "libresoc.v:127016.17-127016.102" + wire width 64 $extend$libresoc.v:127016$4886_Y + attribute \src "libresoc.v:127008.17-127008.108" + wire width 64 $pos$libresoc.v:127008$4876_Y + attribute \src "libresoc.v:127009.18-127009.111" + wire width 64 $pos$libresoc.v:127009$4878_Y + attribute \src "libresoc.v:127012.17-127012.108" + wire width 64 $pos$libresoc.v:127012$4882_Y + attribute \src "libresoc.v:127016.17-127016.102" + wire width 64 $pos$libresoc.v:127016$4887_Y + attribute \src "libresoc.v:127010.18-127010.118" + wire width 47 $sshl$libresoc.v:127010$4879_Y + attribute \src "libresoc.v:127011.18-127011.117" + wire width 27 $sshl$libresoc.v:127011$4880_Y + attribute \src "libresoc.v:127013.18-127013.117" + wire width 17 $sshl$libresoc.v:127013$4883_Y + attribute \src "libresoc.v:127014.18-127014.117" + wire width 17 $sshl$libresoc.v:127014$4884_Y + attribute \src "libresoc.v:127015.17-127015.109" + wire width 47 $sshl$libresoc.v:127015$4885_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -199296,7 +199092,7 @@ module \dec_bi$149 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:127134.7-127134.15" + attribute \src "libresoc.v:126930.7-126930.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li @@ -199324,71 +199120,71 @@ module \dec_bi$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127212$4875 + cell $pos $extend$libresoc.v:127008$4875 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LOGICAL_sh - connect \Y $extend$libresoc.v:127212$4875_Y + connect \Y $extend$libresoc.v:127008$4875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127213$4877 + cell $pos $extend$libresoc.v:127009$4877 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LOGICAL_SH32 - connect \Y $extend$libresoc.v:127213$4877_Y + connect \Y $extend$libresoc.v:127009$4877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127216$4881 + cell $pos $extend$libresoc.v:127012$4881 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LOGICAL_UI - connect \Y $extend$libresoc.v:127216$4881_Y + connect \Y $extend$libresoc.v:127012$4881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $extend$libresoc.v:127220$4886 + cell $pos $extend$libresoc.v:127016$4886 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:127220$4886_Y + connect \Y $extend$libresoc.v:127016$4886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127212$4876 + cell $pos $pos$libresoc.v:127008$4876 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127212$4875_Y - connect \Y $pos$libresoc.v:127212$4876_Y + connect \A $extend$libresoc.v:127008$4875_Y + connect \Y $pos$libresoc.v:127008$4876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127213$4878 + cell $pos $pos$libresoc.v:127009$4878 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127213$4877_Y - connect \Y $pos$libresoc.v:127213$4878_Y + connect \A $extend$libresoc.v:127009$4877_Y + connect \Y $pos$libresoc.v:127009$4878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127216$4882 + cell $pos $pos$libresoc.v:127012$4882 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127216$4881_Y - connect \Y $pos$libresoc.v:127216$4882_Y + connect \A $extend$libresoc.v:127012$4881_Y + connect \Y $pos$libresoc.v:127012$4882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $pos$libresoc.v:127220$4887 + cell $pos $pos$libresoc.v:127016$4887 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127220$4886_Y - connect \Y $pos$libresoc.v:127220$4887_Y + connect \A $extend$libresoc.v:127016$4886_Y + connect \Y $pos$libresoc.v:127016$4887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - cell $sshl $sshl$libresoc.v:127214$4879 + cell $sshl $sshl$libresoc.v:127010$4879 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199396,10 +199192,10 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \LOGICAL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:127214$4879_Y + connect \Y $sshl$libresoc.v:127010$4879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" - cell $sshl $sshl$libresoc.v:127215$4880 + cell $sshl $sshl$libresoc.v:127011$4880 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -199407,10 +199203,10 @@ module \dec_bi$149 parameter \Y_WIDTH 27 connect \A \LOGICAL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:127215$4880_Y + connect \Y $sshl$libresoc.v:127011$4880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" - cell $sshl $sshl$libresoc.v:127217$4883 + cell $sshl $sshl$libresoc.v:127013$4883 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199418,10 +199214,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:127217$4883_Y + connect \Y $sshl$libresoc.v:127013$4883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - cell $sshl $sshl$libresoc.v:127218$4884 + cell $sshl $sshl$libresoc.v:127014$4884 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199429,10 +199225,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:127218$4884_Y + connect \Y $sshl$libresoc.v:127014$4884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $sshl $sshl$libresoc.v:127219$4885 + cell $sshl $sshl$libresoc.v:127015$4885 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199440,24 +199236,24 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:127219$4885_Y + connect \Y $sshl$libresoc.v:127015$4885_Y end - attribute \src "libresoc.v:127134.7-127134.20" - process $proc$libresoc.v:127134$4896 + attribute \src "libresoc.v:126930.7-126930.20" + process $proc$libresoc.v:126930$4896 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127222.3-127268.6" - process $proc$libresoc.v:127222$4888 + attribute \src "libresoc.v:127018.3-127064.6" + process $proc$libresoc.v:127018$4888 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:127223.5-127223.29" + attribute \src "libresoc.v:127019.5-127019.29" switch \initial - attribute \src "libresoc.v:127223.9-127223.17" + attribute \src "libresoc.v:127019.9-127019.17" case 1'1 case end @@ -199509,14 +199305,14 @@ module \dec_bi$149 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:127269.3-127315.6" - process $proc$libresoc.v:127269$4889 + attribute \src "libresoc.v:127065.3-127111.6" + process $proc$libresoc.v:127065$4889 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127270.5-127270.29" + attribute \src "libresoc.v:127066.5-127066.29" switch \initial - attribute \src "libresoc.v:127270.9-127270.17" + attribute \src "libresoc.v:127066.9-127066.17" case 1'1 case end @@ -199568,14 +199364,14 @@ module \dec_bi$149 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:127316.3-127330.6" - process $proc$libresoc.v:127316$4890 + attribute \src "libresoc.v:127112.3-127126.6" + process $proc$libresoc.v:127112$4890 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:127317.5-127317.29" + attribute \src "libresoc.v:127113.5-127113.29" switch \initial - attribute \src "libresoc.v:127317.9-127317.17" + attribute \src "libresoc.v:127113.9-127113.17" case 1'1 case end @@ -199594,14 +199390,14 @@ module \dec_bi$149 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:127331.3-127349.6" - process $proc$libresoc.v:127331$4891 + attribute \src "libresoc.v:127127.3-127145.6" + process $proc$libresoc.v:127127$4891 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:127332.5-127332.29" + attribute \src "libresoc.v:127128.5-127128.29" switch \initial - attribute \src "libresoc.v:127332.9-127332.17" + attribute \src "libresoc.v:127128.9-127128.17" case 1'1 case end @@ -199623,14 +199419,14 @@ module \dec_bi$149 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:127350.3-127372.6" - process $proc$libresoc.v:127350$4892 + attribute \src "libresoc.v:127146.3-127168.6" + process $proc$libresoc.v:127146$4892 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:127351.5-127351.29" + attribute \src "libresoc.v:127147.5-127147.29" switch \initial - attribute \src "libresoc.v:127351.9-127351.17" + attribute \src "libresoc.v:127147.9-127147.17" case 1'1 case end @@ -199655,14 +199451,14 @@ module \dec_bi$149 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:127373.3-127399.6" - process $proc$libresoc.v:127373$4893 + attribute \src "libresoc.v:127169.3-127195.6" + process $proc$libresoc.v:127169$4893 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:127374.5-127374.29" + attribute \src "libresoc.v:127170.5-127170.29" switch \initial - attribute \src "libresoc.v:127374.9-127374.17" + attribute \src "libresoc.v:127170.9-127170.17" case 1'1 case end @@ -199690,14 +199486,14 @@ module \dec_bi$149 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:127400.3-127430.6" - process $proc$libresoc.v:127400$4894 + attribute \src "libresoc.v:127196.3-127226.6" + process $proc$libresoc.v:127196$4894 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:127401.5-127401.29" + attribute \src "libresoc.v:127197.5-127197.29" switch \initial - attribute \src "libresoc.v:127401.9-127401.17" + attribute \src "libresoc.v:127197.9-127197.17" case 1'1 case end @@ -199728,14 +199524,14 @@ module \dec_bi$149 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:127431.3-127465.6" - process $proc$libresoc.v:127431$4895 + attribute \src "libresoc.v:127227.3-127261.6" + process $proc$libresoc.v:127227$4895 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:127432.5-127432.29" + attribute \src "libresoc.v:127228.5-127228.29" switch \initial - attribute \src "libresoc.v:127432.9-127432.17" + attribute \src "libresoc.v:127228.9-127228.17" case 1'1 case end @@ -199769,86 +199565,86 @@ module \dec_bi$149 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:127212$4876_Y - connect \$11 $pos$libresoc.v:127213$4878_Y - connect \$14 $sshl$libresoc.v:127214$4879_Y - connect \$17 $sshl$libresoc.v:127215$4880_Y - connect \$1 $pos$libresoc.v:127216$4882_Y - connect \$20 $sshl$libresoc.v:127217$4883_Y - connect \$23 $sshl$libresoc.v:127218$4884_Y - connect \$4 $sshl$libresoc.v:127219$4885_Y - connect \$3 $pos$libresoc.v:127220$4887_Y + connect \$9 $pos$libresoc.v:127008$4876_Y + connect \$11 $pos$libresoc.v:127009$4878_Y + connect \$14 $sshl$libresoc.v:127010$4879_Y + connect \$17 $sshl$libresoc.v:127011$4880_Y + connect \$1 $pos$libresoc.v:127012$4882_Y + connect \$20 $sshl$libresoc.v:127013$4883_Y + connect \$23 $sshl$libresoc.v:127014$4884_Y + connect \$4 $sshl$libresoc.v:127015$4885_Y + connect \$3 $pos$libresoc.v:127016$4887_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:127474.1-127811.10" +attribute \src "libresoc.v:127270.1-127607.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" attribute \generator "nMigen" module \dec_bi$157 - attribute \src "libresoc.v:127741.3-127771.6" + attribute \src "libresoc.v:127537.3-127567.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:127772.3-127806.6" + attribute \src "libresoc.v:127568.3-127602.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:127563.3-127609.6" + attribute \src "libresoc.v:127359.3-127405.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:127610.3-127656.6" + attribute \src "libresoc.v:127406.3-127452.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:127475.7-127475.20" + attribute \src "libresoc.v:127271.7-127271.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127714.3-127740.6" + attribute \src "libresoc.v:127510.3-127536.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:127657.3-127671.6" + attribute \src "libresoc.v:127453.3-127467.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:127672.3-127690.6" + attribute \src "libresoc.v:127468.3-127486.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:127691.3-127713.6" + attribute \src "libresoc.v:127487.3-127509.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:127741.3-127771.6" + attribute \src "libresoc.v:127537.3-127567.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:127772.3-127806.6" + attribute \src "libresoc.v:127568.3-127602.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:127563.3-127609.6" + attribute \src "libresoc.v:127359.3-127405.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:127610.3-127656.6" + attribute \src "libresoc.v:127406.3-127452.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127714.3-127740.6" + attribute \src "libresoc.v:127510.3-127536.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:127657.3-127671.6" + attribute \src "libresoc.v:127453.3-127467.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:127672.3-127690.6" + attribute \src "libresoc.v:127468.3-127486.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:127691.3-127713.6" + attribute \src "libresoc.v:127487.3-127509.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:127553.17-127553.104" - wire width 64 $extend$libresoc.v:127553$4897_Y - attribute \src "libresoc.v:127554.18-127554.107" - wire width 64 $extend$libresoc.v:127554$4899_Y - attribute \src "libresoc.v:127557.17-127557.104" - wire width 64 $extend$libresoc.v:127557$4903_Y - attribute \src "libresoc.v:127561.17-127561.102" - wire width 64 $extend$libresoc.v:127561$4908_Y - attribute \src "libresoc.v:127553.17-127553.104" - wire width 64 $pos$libresoc.v:127553$4898_Y - attribute \src "libresoc.v:127554.18-127554.107" - wire width 64 $pos$libresoc.v:127554$4900_Y - attribute \src "libresoc.v:127557.17-127557.104" - wire width 64 $pos$libresoc.v:127557$4904_Y - attribute \src "libresoc.v:127561.17-127561.102" - wire width 64 $pos$libresoc.v:127561$4909_Y - attribute \src "libresoc.v:127555.18-127555.114" - wire width 47 $sshl$libresoc.v:127555$4901_Y - attribute \src "libresoc.v:127556.18-127556.113" - wire width 27 $sshl$libresoc.v:127556$4902_Y - attribute \src "libresoc.v:127558.18-127558.113" - wire width 17 $sshl$libresoc.v:127558$4905_Y - attribute \src "libresoc.v:127559.18-127559.113" - wire width 17 $sshl$libresoc.v:127559$4906_Y - attribute \src "libresoc.v:127560.17-127560.109" - wire width 47 $sshl$libresoc.v:127560$4907_Y + attribute \src "libresoc.v:127349.17-127349.104" + wire width 64 $extend$libresoc.v:127349$4897_Y + attribute \src "libresoc.v:127350.18-127350.107" + wire width 64 $extend$libresoc.v:127350$4899_Y + attribute \src "libresoc.v:127353.17-127353.104" + wire width 64 $extend$libresoc.v:127353$4903_Y + attribute \src "libresoc.v:127357.17-127357.102" + wire width 64 $extend$libresoc.v:127357$4908_Y + attribute \src "libresoc.v:127349.17-127349.104" + wire width 64 $pos$libresoc.v:127349$4898_Y + attribute \src "libresoc.v:127350.18-127350.107" + wire width 64 $pos$libresoc.v:127350$4900_Y + attribute \src "libresoc.v:127353.17-127353.104" + wire width 64 $pos$libresoc.v:127353$4904_Y + attribute \src "libresoc.v:127357.17-127357.102" + wire width 64 $pos$libresoc.v:127357$4909_Y + attribute \src "libresoc.v:127351.18-127351.114" + wire width 47 $sshl$libresoc.v:127351$4901_Y + attribute \src "libresoc.v:127352.18-127352.113" + wire width 27 $sshl$libresoc.v:127352$4902_Y + attribute \src "libresoc.v:127354.18-127354.113" + wire width 17 $sshl$libresoc.v:127354$4905_Y + attribute \src "libresoc.v:127355.18-127355.113" + wire width 17 $sshl$libresoc.v:127355$4906_Y + attribute \src "libresoc.v:127356.17-127356.109" + wire width 47 $sshl$libresoc.v:127356$4907_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -199899,7 +199695,7 @@ module \dec_bi$157 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:127475.7-127475.15" + attribute \src "libresoc.v:127271.7-127271.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li @@ -199927,71 +199723,71 @@ module \dec_bi$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127553$4897 + cell $pos $extend$libresoc.v:127349$4897 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \DIV_sh - connect \Y $extend$libresoc.v:127553$4897_Y + connect \Y $extend$libresoc.v:127349$4897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127554$4899 + cell $pos $extend$libresoc.v:127350$4899 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \DIV_SH32 - connect \Y $extend$libresoc.v:127554$4899_Y + connect \Y $extend$libresoc.v:127350$4899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127557$4903 + cell $pos $extend$libresoc.v:127353$4903 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \DIV_UI - connect \Y $extend$libresoc.v:127557$4903_Y + connect \Y $extend$libresoc.v:127353$4903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $extend$libresoc.v:127561$4908 + cell $pos $extend$libresoc.v:127357$4908 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:127561$4908_Y + connect \Y $extend$libresoc.v:127357$4908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127553$4898 + cell $pos $pos$libresoc.v:127349$4898 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127553$4897_Y - connect \Y $pos$libresoc.v:127553$4898_Y + connect \A $extend$libresoc.v:127349$4897_Y + connect \Y $pos$libresoc.v:127349$4898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127554$4900 + cell $pos $pos$libresoc.v:127350$4900 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127554$4899_Y - connect \Y $pos$libresoc.v:127554$4900_Y + connect \A $extend$libresoc.v:127350$4899_Y + connect \Y $pos$libresoc.v:127350$4900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127557$4904 + cell $pos $pos$libresoc.v:127353$4904 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127557$4903_Y - connect \Y $pos$libresoc.v:127557$4904_Y + connect \A $extend$libresoc.v:127353$4903_Y + connect \Y $pos$libresoc.v:127353$4904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $pos$libresoc.v:127561$4909 + cell $pos $pos$libresoc.v:127357$4909 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127561$4908_Y - connect \Y $pos$libresoc.v:127561$4909_Y + connect \A $extend$libresoc.v:127357$4908_Y + connect \Y $pos$libresoc.v:127357$4909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - cell $sshl $sshl$libresoc.v:127555$4901 + cell $sshl $sshl$libresoc.v:127351$4901 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199999,10 +199795,10 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \DIV_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:127555$4901_Y + connect \Y $sshl$libresoc.v:127351$4901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" - cell $sshl $sshl$libresoc.v:127556$4902 + cell $sshl $sshl$libresoc.v:127352$4902 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -200010,10 +199806,10 @@ module \dec_bi$157 parameter \Y_WIDTH 27 connect \A \DIV_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:127556$4902_Y + connect \Y $sshl$libresoc.v:127352$4902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" - cell $sshl $sshl$libresoc.v:127558$4905 + cell $sshl $sshl$libresoc.v:127354$4905 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200021,10 +199817,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:127558$4905_Y + connect \Y $sshl$libresoc.v:127354$4905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - cell $sshl $sshl$libresoc.v:127559$4906 + cell $sshl $sshl$libresoc.v:127355$4906 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200032,10 +199828,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:127559$4906_Y + connect \Y $sshl$libresoc.v:127355$4906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $sshl $sshl$libresoc.v:127560$4907 + cell $sshl $sshl$libresoc.v:127356$4907 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -200043,24 +199839,24 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:127560$4907_Y + connect \Y $sshl$libresoc.v:127356$4907_Y end - attribute \src "libresoc.v:127475.7-127475.20" - process $proc$libresoc.v:127475$4918 + attribute \src "libresoc.v:127271.7-127271.20" + process $proc$libresoc.v:127271$4918 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127563.3-127609.6" - process $proc$libresoc.v:127563$4910 + attribute \src "libresoc.v:127359.3-127405.6" + process $proc$libresoc.v:127359$4910 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:127564.5-127564.29" + attribute \src "libresoc.v:127360.5-127360.29" switch \initial - attribute \src "libresoc.v:127564.9-127564.17" + attribute \src "libresoc.v:127360.9-127360.17" case 1'1 case end @@ -200112,14 +199908,14 @@ module \dec_bi$157 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:127610.3-127656.6" - process $proc$libresoc.v:127610$4911 + attribute \src "libresoc.v:127406.3-127452.6" + process $proc$libresoc.v:127406$4911 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127611.5-127611.29" + attribute \src "libresoc.v:127407.5-127407.29" switch \initial - attribute \src "libresoc.v:127611.9-127611.17" + attribute \src "libresoc.v:127407.9-127407.17" case 1'1 case end @@ -200171,14 +199967,14 @@ module \dec_bi$157 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:127657.3-127671.6" - process $proc$libresoc.v:127657$4912 + attribute \src "libresoc.v:127453.3-127467.6" + process $proc$libresoc.v:127453$4912 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:127658.5-127658.29" + attribute \src "libresoc.v:127454.5-127454.29" switch \initial - attribute \src "libresoc.v:127658.9-127658.17" + attribute \src "libresoc.v:127454.9-127454.17" case 1'1 case end @@ -200197,14 +199993,14 @@ module \dec_bi$157 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:127672.3-127690.6" - process $proc$libresoc.v:127672$4913 + attribute \src "libresoc.v:127468.3-127486.6" + process $proc$libresoc.v:127468$4913 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:127673.5-127673.29" + attribute \src "libresoc.v:127469.5-127469.29" switch \initial - attribute \src "libresoc.v:127673.9-127673.17" + attribute \src "libresoc.v:127469.9-127469.17" case 1'1 case end @@ -200226,14 +200022,14 @@ module \dec_bi$157 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:127691.3-127713.6" - process $proc$libresoc.v:127691$4914 + attribute \src "libresoc.v:127487.3-127509.6" + process $proc$libresoc.v:127487$4914 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:127692.5-127692.29" + attribute \src "libresoc.v:127488.5-127488.29" switch \initial - attribute \src "libresoc.v:127692.9-127692.17" + attribute \src "libresoc.v:127488.9-127488.17" case 1'1 case end @@ -200258,14 +200054,14 @@ module \dec_bi$157 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:127714.3-127740.6" - process $proc$libresoc.v:127714$4915 + attribute \src "libresoc.v:127510.3-127536.6" + process $proc$libresoc.v:127510$4915 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:127715.5-127715.29" + attribute \src "libresoc.v:127511.5-127511.29" switch \initial - attribute \src "libresoc.v:127715.9-127715.17" + attribute \src "libresoc.v:127511.9-127511.17" case 1'1 case end @@ -200293,14 +200089,14 @@ module \dec_bi$157 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:127741.3-127771.6" - process $proc$libresoc.v:127741$4916 + attribute \src "libresoc.v:127537.3-127567.6" + process $proc$libresoc.v:127537$4916 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:127742.5-127742.29" + attribute \src "libresoc.v:127538.5-127538.29" switch \initial - attribute \src "libresoc.v:127742.9-127742.17" + attribute \src "libresoc.v:127538.9-127538.17" case 1'1 case end @@ -200331,14 +200127,14 @@ module \dec_bi$157 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:127772.3-127806.6" - process $proc$libresoc.v:127772$4917 + attribute \src "libresoc.v:127568.3-127602.6" + process $proc$libresoc.v:127568$4917 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:127773.5-127773.29" + attribute \src "libresoc.v:127569.5-127569.29" switch \initial - attribute \src "libresoc.v:127773.9-127773.17" + attribute \src "libresoc.v:127569.9-127569.17" case 1'1 case end @@ -200372,86 +200168,86 @@ module \dec_bi$157 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:127553$4898_Y - connect \$11 $pos$libresoc.v:127554$4900_Y - connect \$14 $sshl$libresoc.v:127555$4901_Y - connect \$17 $sshl$libresoc.v:127556$4902_Y - connect \$1 $pos$libresoc.v:127557$4904_Y - connect \$20 $sshl$libresoc.v:127558$4905_Y - connect \$23 $sshl$libresoc.v:127559$4906_Y - connect \$4 $sshl$libresoc.v:127560$4907_Y - connect \$3 $pos$libresoc.v:127561$4909_Y + connect \$9 $pos$libresoc.v:127349$4898_Y + connect \$11 $pos$libresoc.v:127350$4900_Y + connect \$14 $sshl$libresoc.v:127351$4901_Y + connect \$17 $sshl$libresoc.v:127352$4902_Y + connect \$1 $pos$libresoc.v:127353$4904_Y + connect \$20 $sshl$libresoc.v:127354$4905_Y + connect \$23 $sshl$libresoc.v:127355$4906_Y + connect \$4 $sshl$libresoc.v:127356$4907_Y + connect \$3 $pos$libresoc.v:127357$4909_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:127815.1-128152.10" +attribute \src "libresoc.v:127611.1-127948.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" attribute \generator "nMigen" module \dec_bi$161 - attribute \src "libresoc.v:128082.3-128112.6" + attribute \src "libresoc.v:127878.3-127908.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:128113.3-128147.6" + attribute \src "libresoc.v:127909.3-127943.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:127904.3-127950.6" + attribute \src "libresoc.v:127700.3-127746.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:127951.3-127997.6" + attribute \src "libresoc.v:127747.3-127793.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:127816.7-127816.20" + attribute \src "libresoc.v:127612.7-127612.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128055.3-128081.6" + attribute \src "libresoc.v:127851.3-127877.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:127998.3-128012.6" + attribute \src "libresoc.v:127794.3-127808.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:128013.3-128031.6" + attribute \src "libresoc.v:127809.3-127827.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:128032.3-128054.6" + attribute \src "libresoc.v:127828.3-127850.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:128082.3-128112.6" + attribute \src "libresoc.v:127878.3-127908.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:128113.3-128147.6" + attribute \src "libresoc.v:127909.3-127943.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:127904.3-127950.6" + attribute \src "libresoc.v:127700.3-127746.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:127951.3-127997.6" + attribute \src "libresoc.v:127747.3-127793.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:128055.3-128081.6" + attribute \src "libresoc.v:127851.3-127877.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:127998.3-128012.6" + attribute \src "libresoc.v:127794.3-127808.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:128013.3-128031.6" + attribute \src "libresoc.v:127809.3-127827.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:128032.3-128054.6" + attribute \src "libresoc.v:127828.3-127850.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:127894.17-127894.104" - wire width 64 $extend$libresoc.v:127894$4919_Y - attribute \src "libresoc.v:127895.18-127895.107" - wire width 64 $extend$libresoc.v:127895$4921_Y - attribute \src "libresoc.v:127898.17-127898.104" - wire width 64 $extend$libresoc.v:127898$4925_Y - attribute \src "libresoc.v:127902.17-127902.102" - wire width 64 $extend$libresoc.v:127902$4930_Y - attribute \src "libresoc.v:127894.17-127894.104" - wire width 64 $pos$libresoc.v:127894$4920_Y - attribute \src "libresoc.v:127895.18-127895.107" - wire width 64 $pos$libresoc.v:127895$4922_Y - attribute \src "libresoc.v:127898.17-127898.104" - wire width 64 $pos$libresoc.v:127898$4926_Y - attribute \src "libresoc.v:127902.17-127902.102" - wire width 64 $pos$libresoc.v:127902$4931_Y - attribute \src "libresoc.v:127896.18-127896.114" - wire width 47 $sshl$libresoc.v:127896$4923_Y - attribute \src "libresoc.v:127897.18-127897.113" - wire width 27 $sshl$libresoc.v:127897$4924_Y - attribute \src "libresoc.v:127899.18-127899.113" - wire width 17 $sshl$libresoc.v:127899$4927_Y - attribute \src "libresoc.v:127900.18-127900.113" - wire width 17 $sshl$libresoc.v:127900$4928_Y - attribute \src "libresoc.v:127901.17-127901.109" - wire width 47 $sshl$libresoc.v:127901$4929_Y + attribute \src "libresoc.v:127690.17-127690.104" + wire width 64 $extend$libresoc.v:127690$4919_Y + attribute \src "libresoc.v:127691.18-127691.107" + wire width 64 $extend$libresoc.v:127691$4921_Y + attribute \src "libresoc.v:127694.17-127694.104" + wire width 64 $extend$libresoc.v:127694$4925_Y + attribute \src "libresoc.v:127698.17-127698.102" + wire width 64 $extend$libresoc.v:127698$4930_Y + attribute \src "libresoc.v:127690.17-127690.104" + wire width 64 $pos$libresoc.v:127690$4920_Y + attribute \src "libresoc.v:127691.18-127691.107" + wire width 64 $pos$libresoc.v:127691$4922_Y + attribute \src "libresoc.v:127694.17-127694.104" + wire width 64 $pos$libresoc.v:127694$4926_Y + attribute \src "libresoc.v:127698.17-127698.102" + wire width 64 $pos$libresoc.v:127698$4931_Y + attribute \src "libresoc.v:127692.18-127692.114" + wire width 47 $sshl$libresoc.v:127692$4923_Y + attribute \src "libresoc.v:127693.18-127693.113" + wire width 27 $sshl$libresoc.v:127693$4924_Y + attribute \src "libresoc.v:127695.18-127695.113" + wire width 17 $sshl$libresoc.v:127695$4927_Y + attribute \src "libresoc.v:127696.18-127696.113" + wire width 17 $sshl$libresoc.v:127696$4928_Y + attribute \src "libresoc.v:127697.17-127697.109" + wire width 47 $sshl$libresoc.v:127697$4929_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -200502,7 +200298,7 @@ module \dec_bi$161 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:127816.7-127816.15" + attribute \src "libresoc.v:127612.7-127612.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li @@ -200530,71 +200326,71 @@ module \dec_bi$161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127894$4919 + cell $pos $extend$libresoc.v:127690$4919 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \MUL_sh - connect \Y $extend$libresoc.v:127894$4919_Y + connect \Y $extend$libresoc.v:127690$4919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127895$4921 + cell $pos $extend$libresoc.v:127691$4921 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \MUL_SH32 - connect \Y $extend$libresoc.v:127895$4921_Y + connect \Y $extend$libresoc.v:127691$4921_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127898$4925 + cell $pos $extend$libresoc.v:127694$4925 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \MUL_UI - connect \Y $extend$libresoc.v:127898$4925_Y + connect \Y $extend$libresoc.v:127694$4925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $extend$libresoc.v:127902$4930 + cell $pos $extend$libresoc.v:127698$4930 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:127902$4930_Y + connect \Y $extend$libresoc.v:127698$4930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127894$4920 + cell $pos $pos$libresoc.v:127690$4920 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127894$4919_Y - connect \Y $pos$libresoc.v:127894$4920_Y + connect \A $extend$libresoc.v:127690$4919_Y + connect \Y $pos$libresoc.v:127690$4920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127895$4922 + cell $pos $pos$libresoc.v:127691$4922 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127895$4921_Y - connect \Y $pos$libresoc.v:127895$4922_Y + connect \A $extend$libresoc.v:127691$4921_Y + connect \Y $pos$libresoc.v:127691$4922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127898$4926 + cell $pos $pos$libresoc.v:127694$4926 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127898$4925_Y - connect \Y $pos$libresoc.v:127898$4926_Y + connect \A $extend$libresoc.v:127694$4925_Y + connect \Y $pos$libresoc.v:127694$4926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $pos$libresoc.v:127902$4931 + cell $pos $pos$libresoc.v:127698$4931 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127902$4930_Y - connect \Y $pos$libresoc.v:127902$4931_Y + connect \A $extend$libresoc.v:127698$4930_Y + connect \Y $pos$libresoc.v:127698$4931_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - cell $sshl $sshl$libresoc.v:127896$4923 + cell $sshl $sshl$libresoc.v:127692$4923 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -200602,10 +200398,10 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \MUL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:127896$4923_Y + connect \Y $sshl$libresoc.v:127692$4923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" - cell $sshl $sshl$libresoc.v:127897$4924 + cell $sshl $sshl$libresoc.v:127693$4924 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -200613,10 +200409,10 @@ module \dec_bi$161 parameter \Y_WIDTH 27 connect \A \MUL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:127897$4924_Y + connect \Y $sshl$libresoc.v:127693$4924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" - cell $sshl $sshl$libresoc.v:127899$4927 + cell $sshl $sshl$libresoc.v:127695$4927 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200624,10 +200420,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:127899$4927_Y + connect \Y $sshl$libresoc.v:127695$4927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - cell $sshl $sshl$libresoc.v:127900$4928 + cell $sshl $sshl$libresoc.v:127696$4928 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200635,10 +200431,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:127900$4928_Y + connect \Y $sshl$libresoc.v:127696$4928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $sshl $sshl$libresoc.v:127901$4929 + cell $sshl $sshl$libresoc.v:127697$4929 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -200646,24 +200442,24 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:127901$4929_Y + connect \Y $sshl$libresoc.v:127697$4929_Y end - attribute \src "libresoc.v:127816.7-127816.20" - process $proc$libresoc.v:127816$4940 + attribute \src "libresoc.v:127612.7-127612.20" + process $proc$libresoc.v:127612$4940 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127904.3-127950.6" - process $proc$libresoc.v:127904$4932 + attribute \src "libresoc.v:127700.3-127746.6" + process $proc$libresoc.v:127700$4932 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:127905.5-127905.29" + attribute \src "libresoc.v:127701.5-127701.29" switch \initial - attribute \src "libresoc.v:127905.9-127905.17" + attribute \src "libresoc.v:127701.9-127701.17" case 1'1 case end @@ -200715,14 +200511,14 @@ module \dec_bi$161 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:127951.3-127997.6" - process $proc$libresoc.v:127951$4933 + attribute \src "libresoc.v:127747.3-127793.6" + process $proc$libresoc.v:127747$4933 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127952.5-127952.29" + attribute \src "libresoc.v:127748.5-127748.29" switch \initial - attribute \src "libresoc.v:127952.9-127952.17" + attribute \src "libresoc.v:127748.9-127748.17" case 1'1 case end @@ -200774,14 +200570,14 @@ module \dec_bi$161 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:127998.3-128012.6" - process $proc$libresoc.v:127998$4934 + attribute \src "libresoc.v:127794.3-127808.6" + process $proc$libresoc.v:127794$4934 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:127999.5-127999.29" + attribute \src "libresoc.v:127795.5-127795.29" switch \initial - attribute \src "libresoc.v:127999.9-127999.17" + attribute \src "libresoc.v:127795.9-127795.17" case 1'1 case end @@ -200800,14 +200596,14 @@ module \dec_bi$161 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:128013.3-128031.6" - process $proc$libresoc.v:128013$4935 + attribute \src "libresoc.v:127809.3-127827.6" + process $proc$libresoc.v:127809$4935 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:128014.5-128014.29" + attribute \src "libresoc.v:127810.5-127810.29" switch \initial - attribute \src "libresoc.v:128014.9-128014.17" + attribute \src "libresoc.v:127810.9-127810.17" case 1'1 case end @@ -200829,14 +200625,14 @@ module \dec_bi$161 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:128032.3-128054.6" - process $proc$libresoc.v:128032$4936 + attribute \src "libresoc.v:127828.3-127850.6" + process $proc$libresoc.v:127828$4936 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:128033.5-128033.29" + attribute \src "libresoc.v:127829.5-127829.29" switch \initial - attribute \src "libresoc.v:128033.9-128033.17" + attribute \src "libresoc.v:127829.9-127829.17" case 1'1 case end @@ -200861,14 +200657,14 @@ module \dec_bi$161 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:128055.3-128081.6" - process $proc$libresoc.v:128055$4937 + attribute \src "libresoc.v:127851.3-127877.6" + process $proc$libresoc.v:127851$4937 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:128056.5-128056.29" + attribute \src "libresoc.v:127852.5-127852.29" switch \initial - attribute \src "libresoc.v:128056.9-128056.17" + attribute \src "libresoc.v:127852.9-127852.17" case 1'1 case end @@ -200896,14 +200692,14 @@ module \dec_bi$161 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:128082.3-128112.6" - process $proc$libresoc.v:128082$4938 + attribute \src "libresoc.v:127878.3-127908.6" + process $proc$libresoc.v:127878$4938 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:128083.5-128083.29" + attribute \src "libresoc.v:127879.5-127879.29" switch \initial - attribute \src "libresoc.v:128083.9-128083.17" + attribute \src "libresoc.v:127879.9-127879.17" case 1'1 case end @@ -200934,14 +200730,14 @@ module \dec_bi$161 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:128113.3-128147.6" - process $proc$libresoc.v:128113$4939 + attribute \src "libresoc.v:127909.3-127943.6" + process $proc$libresoc.v:127909$4939 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:128114.5-128114.29" + attribute \src "libresoc.v:127910.5-127910.29" switch \initial - attribute \src "libresoc.v:128114.9-128114.17" + attribute \src "libresoc.v:127910.9-127910.17" case 1'1 case end @@ -200975,86 +200771,86 @@ module \dec_bi$161 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:127894$4920_Y - connect \$11 $pos$libresoc.v:127895$4922_Y - connect \$14 $sshl$libresoc.v:127896$4923_Y - connect \$17 $sshl$libresoc.v:127897$4924_Y - connect \$1 $pos$libresoc.v:127898$4926_Y - connect \$20 $sshl$libresoc.v:127899$4927_Y - connect \$23 $sshl$libresoc.v:127900$4928_Y - connect \$4 $sshl$libresoc.v:127901$4929_Y - connect \$3 $pos$libresoc.v:127902$4931_Y + connect \$9 $pos$libresoc.v:127690$4920_Y + connect \$11 $pos$libresoc.v:127691$4922_Y + connect \$14 $sshl$libresoc.v:127692$4923_Y + connect \$17 $sshl$libresoc.v:127693$4924_Y + connect \$1 $pos$libresoc.v:127694$4926_Y + connect \$20 $sshl$libresoc.v:127695$4927_Y + connect \$23 $sshl$libresoc.v:127696$4928_Y + connect \$4 $sshl$libresoc.v:127697$4929_Y + connect \$3 $pos$libresoc.v:127698$4931_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:128156.1-128493.10" +attribute \src "libresoc.v:127952.1-128289.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" attribute \generator "nMigen" module \dec_bi$165 - attribute \src "libresoc.v:128423.3-128453.6" + attribute \src "libresoc.v:128219.3-128249.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:128454.3-128488.6" + attribute \src "libresoc.v:128250.3-128284.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:128245.3-128291.6" + attribute \src "libresoc.v:128041.3-128087.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:128292.3-128338.6" + attribute \src "libresoc.v:128088.3-128134.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:128157.7-128157.20" + attribute \src "libresoc.v:127953.7-127953.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128396.3-128422.6" + attribute \src "libresoc.v:128192.3-128218.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:128339.3-128353.6" + attribute \src "libresoc.v:128135.3-128149.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:128354.3-128372.6" + attribute \src "libresoc.v:128150.3-128168.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:128373.3-128395.6" + attribute \src "libresoc.v:128169.3-128191.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:128423.3-128453.6" + attribute \src "libresoc.v:128219.3-128249.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:128454.3-128488.6" + attribute \src "libresoc.v:128250.3-128284.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:128245.3-128291.6" + attribute \src "libresoc.v:128041.3-128087.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:128292.3-128338.6" + attribute \src "libresoc.v:128088.3-128134.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:128396.3-128422.6" + attribute \src "libresoc.v:128192.3-128218.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:128339.3-128353.6" + attribute \src "libresoc.v:128135.3-128149.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:128354.3-128372.6" + attribute \src "libresoc.v:128150.3-128168.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:128373.3-128395.6" + attribute \src "libresoc.v:128169.3-128191.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:128235.17-128235.110" - wire width 64 $extend$libresoc.v:128235$4941_Y - attribute \src "libresoc.v:128236.18-128236.113" - wire width 64 $extend$libresoc.v:128236$4943_Y - attribute \src "libresoc.v:128239.17-128239.110" - wire width 64 $extend$libresoc.v:128239$4947_Y - attribute \src "libresoc.v:128243.17-128243.102" - wire width 64 $extend$libresoc.v:128243$4952_Y - attribute \src "libresoc.v:128235.17-128235.110" - wire width 64 $pos$libresoc.v:128235$4942_Y - attribute \src "libresoc.v:128236.18-128236.113" - wire width 64 $pos$libresoc.v:128236$4944_Y - attribute \src "libresoc.v:128239.17-128239.110" - wire width 64 $pos$libresoc.v:128239$4948_Y - attribute \src "libresoc.v:128243.17-128243.102" - wire width 64 $pos$libresoc.v:128243$4953_Y - attribute \src "libresoc.v:128237.18-128237.120" - wire width 47 $sshl$libresoc.v:128237$4945_Y - attribute \src "libresoc.v:128238.18-128238.119" - wire width 27 $sshl$libresoc.v:128238$4946_Y - attribute \src "libresoc.v:128240.18-128240.119" - wire width 17 $sshl$libresoc.v:128240$4949_Y - attribute \src "libresoc.v:128241.18-128241.119" - wire width 17 $sshl$libresoc.v:128241$4950_Y - attribute \src "libresoc.v:128242.17-128242.109" - wire width 47 $sshl$libresoc.v:128242$4951_Y + attribute \src "libresoc.v:128031.17-128031.110" + wire width 64 $extend$libresoc.v:128031$4941_Y + attribute \src "libresoc.v:128032.18-128032.113" + wire width 64 $extend$libresoc.v:128032$4943_Y + attribute \src "libresoc.v:128035.17-128035.110" + wire width 64 $extend$libresoc.v:128035$4947_Y + attribute \src "libresoc.v:128039.17-128039.102" + wire width 64 $extend$libresoc.v:128039$4952_Y + attribute \src "libresoc.v:128031.17-128031.110" + wire width 64 $pos$libresoc.v:128031$4942_Y + attribute \src "libresoc.v:128032.18-128032.113" + wire width 64 $pos$libresoc.v:128032$4944_Y + attribute \src "libresoc.v:128035.17-128035.110" + wire width 64 $pos$libresoc.v:128035$4948_Y + attribute \src "libresoc.v:128039.17-128039.102" + wire width 64 $pos$libresoc.v:128039$4953_Y + attribute \src "libresoc.v:128033.18-128033.120" + wire width 47 $sshl$libresoc.v:128033$4945_Y + attribute \src "libresoc.v:128034.18-128034.119" + wire width 27 $sshl$libresoc.v:128034$4946_Y + attribute \src "libresoc.v:128036.18-128036.119" + wire width 17 $sshl$libresoc.v:128036$4949_Y + attribute \src "libresoc.v:128037.18-128037.119" + wire width 17 $sshl$libresoc.v:128037$4950_Y + attribute \src "libresoc.v:128038.17-128038.109" + wire width 47 $sshl$libresoc.v:128038$4951_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -201105,7 +200901,7 @@ module \dec_bi$165 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:128157.7-128157.15" + attribute \src "libresoc.v:127953.7-127953.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li @@ -201133,71 +200929,71 @@ module \dec_bi$165 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128235$4941 + cell $pos $extend$libresoc.v:128031$4941 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_sh - connect \Y $extend$libresoc.v:128235$4941_Y + connect \Y $extend$libresoc.v:128031$4941_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128236$4943 + cell $pos $extend$libresoc.v:128032$4943 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_SH32 - connect \Y $extend$libresoc.v:128236$4943_Y + connect \Y $extend$libresoc.v:128032$4943_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128239$4947 + cell $pos $extend$libresoc.v:128035$4947 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_UI - connect \Y $extend$libresoc.v:128239$4947_Y + connect \Y $extend$libresoc.v:128035$4947_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $extend$libresoc.v:128243$4952 + cell $pos $extend$libresoc.v:128039$4952 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:128243$4952_Y + connect \Y $extend$libresoc.v:128039$4952_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128235$4942 + cell $pos $pos$libresoc.v:128031$4942 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128235$4941_Y - connect \Y $pos$libresoc.v:128235$4942_Y + connect \A $extend$libresoc.v:128031$4941_Y + connect \Y $pos$libresoc.v:128031$4942_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128236$4944 + cell $pos $pos$libresoc.v:128032$4944 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128236$4943_Y - connect \Y $pos$libresoc.v:128236$4944_Y + connect \A $extend$libresoc.v:128032$4943_Y + connect \Y $pos$libresoc.v:128032$4944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128239$4948 + cell $pos $pos$libresoc.v:128035$4948 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128239$4947_Y - connect \Y $pos$libresoc.v:128239$4948_Y + connect \A $extend$libresoc.v:128035$4947_Y + connect \Y $pos$libresoc.v:128035$4948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $pos$libresoc.v:128243$4953 + cell $pos $pos$libresoc.v:128039$4953 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128243$4952_Y - connect \Y $pos$libresoc.v:128243$4953_Y + connect \A $extend$libresoc.v:128039$4952_Y + connect \Y $pos$libresoc.v:128039$4953_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - cell $sshl $sshl$libresoc.v:128237$4945 + cell $sshl $sshl$libresoc.v:128033$4945 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201205,10 +201001,10 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \SHIFT_ROT_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:128237$4945_Y + connect \Y $sshl$libresoc.v:128033$4945_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" - cell $sshl $sshl$libresoc.v:128238$4946 + cell $sshl $sshl$libresoc.v:128034$4946 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -201216,10 +201012,10 @@ module \dec_bi$165 parameter \Y_WIDTH 27 connect \A \SHIFT_ROT_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:128238$4946_Y + connect \Y $sshl$libresoc.v:128034$4946_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" - cell $sshl $sshl$libresoc.v:128240$4949 + cell $sshl $sshl$libresoc.v:128036$4949 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201227,10 +201023,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:128240$4949_Y + connect \Y $sshl$libresoc.v:128036$4949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - cell $sshl $sshl$libresoc.v:128241$4950 + cell $sshl $sshl$libresoc.v:128037$4950 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201238,10 +201034,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:128241$4950_Y + connect \Y $sshl$libresoc.v:128037$4950_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $sshl $sshl$libresoc.v:128242$4951 + cell $sshl $sshl$libresoc.v:128038$4951 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201249,24 +201045,24 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:128242$4951_Y + connect \Y $sshl$libresoc.v:128038$4951_Y end - attribute \src "libresoc.v:128157.7-128157.20" - process $proc$libresoc.v:128157$4962 + attribute \src "libresoc.v:127953.7-127953.20" + process $proc$libresoc.v:127953$4962 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128245.3-128291.6" - process $proc$libresoc.v:128245$4954 + attribute \src "libresoc.v:128041.3-128087.6" + process $proc$libresoc.v:128041$4954 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:128246.5-128246.29" + attribute \src "libresoc.v:128042.5-128042.29" switch \initial - attribute \src "libresoc.v:128246.9-128246.17" + attribute \src "libresoc.v:128042.9-128042.17" case 1'1 case end @@ -201318,14 +201114,14 @@ module \dec_bi$165 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:128292.3-128338.6" - process $proc$libresoc.v:128292$4955 + attribute \src "libresoc.v:128088.3-128134.6" + process $proc$libresoc.v:128088$4955 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:128293.5-128293.29" + attribute \src "libresoc.v:128089.5-128089.29" switch \initial - attribute \src "libresoc.v:128293.9-128293.17" + attribute \src "libresoc.v:128089.9-128089.17" case 1'1 case end @@ -201377,14 +201173,14 @@ module \dec_bi$165 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:128339.3-128353.6" - process $proc$libresoc.v:128339$4956 + attribute \src "libresoc.v:128135.3-128149.6" + process $proc$libresoc.v:128135$4956 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:128340.5-128340.29" + attribute \src "libresoc.v:128136.5-128136.29" switch \initial - attribute \src "libresoc.v:128340.9-128340.17" + attribute \src "libresoc.v:128136.9-128136.17" case 1'1 case end @@ -201403,14 +201199,14 @@ module \dec_bi$165 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:128354.3-128372.6" - process $proc$libresoc.v:128354$4957 + attribute \src "libresoc.v:128150.3-128168.6" + process $proc$libresoc.v:128150$4957 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:128355.5-128355.29" + attribute \src "libresoc.v:128151.5-128151.29" switch \initial - attribute \src "libresoc.v:128355.9-128355.17" + attribute \src "libresoc.v:128151.9-128151.17" case 1'1 case end @@ -201432,14 +201228,14 @@ module \dec_bi$165 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:128373.3-128395.6" - process $proc$libresoc.v:128373$4958 + attribute \src "libresoc.v:128169.3-128191.6" + process $proc$libresoc.v:128169$4958 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:128374.5-128374.29" + attribute \src "libresoc.v:128170.5-128170.29" switch \initial - attribute \src "libresoc.v:128374.9-128374.17" + attribute \src "libresoc.v:128170.9-128170.17" case 1'1 case end @@ -201464,14 +201260,14 @@ module \dec_bi$165 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:128396.3-128422.6" - process $proc$libresoc.v:128396$4959 + attribute \src "libresoc.v:128192.3-128218.6" + process $proc$libresoc.v:128192$4959 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:128397.5-128397.29" + attribute \src "libresoc.v:128193.5-128193.29" switch \initial - attribute \src "libresoc.v:128397.9-128397.17" + attribute \src "libresoc.v:128193.9-128193.17" case 1'1 case end @@ -201499,14 +201295,14 @@ module \dec_bi$165 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:128423.3-128453.6" - process $proc$libresoc.v:128423$4960 + attribute \src "libresoc.v:128219.3-128249.6" + process $proc$libresoc.v:128219$4960 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:128424.5-128424.29" + attribute \src "libresoc.v:128220.5-128220.29" switch \initial - attribute \src "libresoc.v:128424.9-128424.17" + attribute \src "libresoc.v:128220.9-128220.17" case 1'1 case end @@ -201537,14 +201333,14 @@ module \dec_bi$165 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:128454.3-128488.6" - process $proc$libresoc.v:128454$4961 + attribute \src "libresoc.v:128250.3-128284.6" + process $proc$libresoc.v:128250$4961 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:128455.5-128455.29" + attribute \src "libresoc.v:128251.5-128251.29" switch \initial - attribute \src "libresoc.v:128455.9-128455.17" + attribute \src "libresoc.v:128251.9-128251.17" case 1'1 case end @@ -201578,86 +201374,86 @@ module \dec_bi$165 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:128235$4942_Y - connect \$11 $pos$libresoc.v:128236$4944_Y - connect \$14 $sshl$libresoc.v:128237$4945_Y - connect \$17 $sshl$libresoc.v:128238$4946_Y - connect \$1 $pos$libresoc.v:128239$4948_Y - connect \$20 $sshl$libresoc.v:128240$4949_Y - connect \$23 $sshl$libresoc.v:128241$4950_Y - connect \$4 $sshl$libresoc.v:128242$4951_Y - connect \$3 $pos$libresoc.v:128243$4953_Y + connect \$9 $pos$libresoc.v:128031$4942_Y + connect \$11 $pos$libresoc.v:128032$4944_Y + connect \$14 $sshl$libresoc.v:128033$4945_Y + connect \$17 $sshl$libresoc.v:128034$4946_Y + connect \$1 $pos$libresoc.v:128035$4948_Y + connect \$20 $sshl$libresoc.v:128036$4949_Y + connect \$23 $sshl$libresoc.v:128037$4950_Y + connect \$4 $sshl$libresoc.v:128038$4951_Y + connect \$3 $pos$libresoc.v:128039$4953_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:128497.1-128834.10" +attribute \src "libresoc.v:128293.1-128630.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi" attribute \generator "nMigen" module \dec_bi$170 - attribute \src "libresoc.v:128764.3-128794.6" + attribute \src "libresoc.v:128560.3-128590.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:128795.3-128829.6" + attribute \src "libresoc.v:128591.3-128625.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:128586.3-128632.6" + attribute \src "libresoc.v:128382.3-128428.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:128633.3-128679.6" + attribute \src "libresoc.v:128429.3-128475.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:128498.7-128498.20" + attribute \src "libresoc.v:128294.7-128294.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128737.3-128763.6" + attribute \src "libresoc.v:128533.3-128559.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:128680.3-128694.6" + attribute \src "libresoc.v:128476.3-128490.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:128695.3-128713.6" + attribute \src "libresoc.v:128491.3-128509.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:128714.3-128736.6" + attribute \src "libresoc.v:128510.3-128532.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:128764.3-128794.6" + attribute \src "libresoc.v:128560.3-128590.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:128795.3-128829.6" + attribute \src "libresoc.v:128591.3-128625.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:128586.3-128632.6" + attribute \src "libresoc.v:128382.3-128428.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:128633.3-128679.6" + attribute \src "libresoc.v:128429.3-128475.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:128737.3-128763.6" + attribute \src "libresoc.v:128533.3-128559.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:128680.3-128694.6" + attribute \src "libresoc.v:128476.3-128490.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:128695.3-128713.6" + attribute \src "libresoc.v:128491.3-128509.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:128714.3-128736.6" + attribute \src "libresoc.v:128510.3-128532.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:128576.17-128576.105" - wire width 64 $extend$libresoc.v:128576$4963_Y - attribute \src "libresoc.v:128577.18-128577.108" - wire width 64 $extend$libresoc.v:128577$4965_Y - attribute \src "libresoc.v:128580.17-128580.105" - wire width 64 $extend$libresoc.v:128580$4969_Y - attribute \src "libresoc.v:128584.17-128584.102" - wire width 64 $extend$libresoc.v:128584$4974_Y - attribute \src "libresoc.v:128576.17-128576.105" - wire width 64 $pos$libresoc.v:128576$4964_Y - attribute \src "libresoc.v:128577.18-128577.108" - wire width 64 $pos$libresoc.v:128577$4966_Y - attribute \src "libresoc.v:128580.17-128580.105" - wire width 64 $pos$libresoc.v:128580$4970_Y - attribute \src "libresoc.v:128584.17-128584.102" - wire width 64 $pos$libresoc.v:128584$4975_Y - attribute \src "libresoc.v:128578.18-128578.115" - wire width 47 $sshl$libresoc.v:128578$4967_Y - attribute \src "libresoc.v:128579.18-128579.114" - wire width 27 $sshl$libresoc.v:128579$4968_Y - attribute \src "libresoc.v:128581.18-128581.114" - wire width 17 $sshl$libresoc.v:128581$4971_Y - attribute \src "libresoc.v:128582.18-128582.114" - wire width 17 $sshl$libresoc.v:128582$4972_Y - attribute \src "libresoc.v:128583.17-128583.109" - wire width 47 $sshl$libresoc.v:128583$4973_Y + attribute \src "libresoc.v:128372.17-128372.105" + wire width 64 $extend$libresoc.v:128372$4963_Y + attribute \src "libresoc.v:128373.18-128373.108" + wire width 64 $extend$libresoc.v:128373$4965_Y + attribute \src "libresoc.v:128376.17-128376.105" + wire width 64 $extend$libresoc.v:128376$4969_Y + attribute \src "libresoc.v:128380.17-128380.102" + wire width 64 $extend$libresoc.v:128380$4974_Y + attribute \src "libresoc.v:128372.17-128372.105" + wire width 64 $pos$libresoc.v:128372$4964_Y + attribute \src "libresoc.v:128373.18-128373.108" + wire width 64 $pos$libresoc.v:128373$4966_Y + attribute \src "libresoc.v:128376.17-128376.105" + wire width 64 $pos$libresoc.v:128376$4970_Y + attribute \src "libresoc.v:128380.17-128380.102" + wire width 64 $pos$libresoc.v:128380$4975_Y + attribute \src "libresoc.v:128374.18-128374.115" + wire width 47 $sshl$libresoc.v:128374$4967_Y + attribute \src "libresoc.v:128375.18-128375.114" + wire width 27 $sshl$libresoc.v:128375$4968_Y + attribute \src "libresoc.v:128377.18-128377.114" + wire width 17 $sshl$libresoc.v:128377$4971_Y + attribute \src "libresoc.v:128378.18-128378.114" + wire width 17 $sshl$libresoc.v:128378$4972_Y + attribute \src "libresoc.v:128379.17-128379.109" + wire width 47 $sshl$libresoc.v:128379$4973_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -201708,7 +201504,7 @@ module \dec_bi$170 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:128498.7-128498.15" + attribute \src "libresoc.v:128294.7-128294.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li @@ -201736,71 +201532,71 @@ module \dec_bi$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128576$4963 + cell $pos $extend$libresoc.v:128372$4963 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LDST_sh - connect \Y $extend$libresoc.v:128576$4963_Y + connect \Y $extend$libresoc.v:128372$4963_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128577$4965 + cell $pos $extend$libresoc.v:128373$4965 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LDST_SH32 - connect \Y $extend$libresoc.v:128577$4965_Y + connect \Y $extend$libresoc.v:128373$4965_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128580$4969 + cell $pos $extend$libresoc.v:128376$4969 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LDST_UI - connect \Y $extend$libresoc.v:128580$4969_Y + connect \Y $extend$libresoc.v:128376$4969_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $extend$libresoc.v:128584$4974 + cell $pos $extend$libresoc.v:128380$4974 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:128584$4974_Y + connect \Y $extend$libresoc.v:128380$4974_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128576$4964 + cell $pos $pos$libresoc.v:128372$4964 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128576$4963_Y - connect \Y $pos$libresoc.v:128576$4964_Y + connect \A $extend$libresoc.v:128372$4963_Y + connect \Y $pos$libresoc.v:128372$4964_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128577$4966 + cell $pos $pos$libresoc.v:128373$4966 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128577$4965_Y - connect \Y $pos$libresoc.v:128577$4966_Y + connect \A $extend$libresoc.v:128373$4965_Y + connect \Y $pos$libresoc.v:128373$4966_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128580$4970 + cell $pos $pos$libresoc.v:128376$4970 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128580$4969_Y - connect \Y $pos$libresoc.v:128580$4970_Y + connect \A $extend$libresoc.v:128376$4969_Y + connect \Y $pos$libresoc.v:128376$4970_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $pos $pos$libresoc.v:128584$4975 + cell $pos $pos$libresoc.v:128380$4975 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128584$4974_Y - connect \Y $pos$libresoc.v:128584$4975_Y + connect \A $extend$libresoc.v:128380$4974_Y + connect \Y $pos$libresoc.v:128380$4975_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - cell $sshl $sshl$libresoc.v:128578$4967 + cell $sshl $sshl$libresoc.v:128374$4967 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201808,10 +201604,10 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \LDST_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:128578$4967_Y + connect \Y $sshl$libresoc.v:128374$4967_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" - cell $sshl $sshl$libresoc.v:128579$4968 + cell $sshl $sshl$libresoc.v:128375$4968 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -201819,10 +201615,10 @@ module \dec_bi$170 parameter \Y_WIDTH 27 connect \A \LDST_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:128579$4968_Y + connect \Y $sshl$libresoc.v:128375$4968_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" - cell $sshl $sshl$libresoc.v:128581$4971 + cell $sshl $sshl$libresoc.v:128377$4971 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201830,10 +201626,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:128581$4971_Y + connect \Y $sshl$libresoc.v:128377$4971_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - cell $sshl $sshl$libresoc.v:128582$4972 + cell $sshl $sshl$libresoc.v:128378$4972 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201841,10 +201637,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:128582$4972_Y + connect \Y $sshl$libresoc.v:128378$4972_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" - cell $sshl $sshl$libresoc.v:128583$4973 + cell $sshl $sshl$libresoc.v:128379$4973 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201852,24 +201648,24 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:128583$4973_Y + connect \Y $sshl$libresoc.v:128379$4973_Y end - attribute \src "libresoc.v:128498.7-128498.20" - process $proc$libresoc.v:128498$4984 + attribute \src "libresoc.v:128294.7-128294.20" + process $proc$libresoc.v:128294$4984 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128586.3-128632.6" - process $proc$libresoc.v:128586$4976 + attribute \src "libresoc.v:128382.3-128428.6" + process $proc$libresoc.v:128382$4976 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:128587.5-128587.29" + attribute \src "libresoc.v:128383.5-128383.29" switch \initial - attribute \src "libresoc.v:128587.9-128587.17" + attribute \src "libresoc.v:128383.9-128383.17" case 1'1 case end @@ -201921,14 +201717,14 @@ module \dec_bi$170 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:128633.3-128679.6" - process $proc$libresoc.v:128633$4977 + attribute \src "libresoc.v:128429.3-128475.6" + process $proc$libresoc.v:128429$4977 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:128634.5-128634.29" + attribute \src "libresoc.v:128430.5-128430.29" switch \initial - attribute \src "libresoc.v:128634.9-128634.17" + attribute \src "libresoc.v:128430.9-128430.17" case 1'1 case end @@ -201980,14 +201776,14 @@ module \dec_bi$170 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:128680.3-128694.6" - process $proc$libresoc.v:128680$4978 + attribute \src "libresoc.v:128476.3-128490.6" + process $proc$libresoc.v:128476$4978 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:128681.5-128681.29" + attribute \src "libresoc.v:128477.5-128477.29" switch \initial - attribute \src "libresoc.v:128681.9-128681.17" + attribute \src "libresoc.v:128477.9-128477.17" case 1'1 case end @@ -202006,14 +201802,14 @@ module \dec_bi$170 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:128695.3-128713.6" - process $proc$libresoc.v:128695$4979 + attribute \src "libresoc.v:128491.3-128509.6" + process $proc$libresoc.v:128491$4979 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:128696.5-128696.29" + attribute \src "libresoc.v:128492.5-128492.29" switch \initial - attribute \src "libresoc.v:128696.9-128696.17" + attribute \src "libresoc.v:128492.9-128492.17" case 1'1 case end @@ -202035,14 +201831,14 @@ module \dec_bi$170 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:128714.3-128736.6" - process $proc$libresoc.v:128714$4980 + attribute \src "libresoc.v:128510.3-128532.6" + process $proc$libresoc.v:128510$4980 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:128715.5-128715.29" + attribute \src "libresoc.v:128511.5-128511.29" switch \initial - attribute \src "libresoc.v:128715.9-128715.17" + attribute \src "libresoc.v:128511.9-128511.17" case 1'1 case end @@ -202067,14 +201863,14 @@ module \dec_bi$170 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:128737.3-128763.6" - process $proc$libresoc.v:128737$4981 + attribute \src "libresoc.v:128533.3-128559.6" + process $proc$libresoc.v:128533$4981 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:128738.5-128738.29" + attribute \src "libresoc.v:128534.5-128534.29" switch \initial - attribute \src "libresoc.v:128738.9-128738.17" + attribute \src "libresoc.v:128534.9-128534.17" case 1'1 case end @@ -202102,14 +201898,14 @@ module \dec_bi$170 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:128764.3-128794.6" - process $proc$libresoc.v:128764$4982 + attribute \src "libresoc.v:128560.3-128590.6" + process $proc$libresoc.v:128560$4982 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:128765.5-128765.29" + attribute \src "libresoc.v:128561.5-128561.29" switch \initial - attribute \src "libresoc.v:128765.9-128765.17" + attribute \src "libresoc.v:128561.9-128561.17" case 1'1 case end @@ -202140,14 +201936,14 @@ module \dec_bi$170 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:128795.3-128829.6" - process $proc$libresoc.v:128795$4983 + attribute \src "libresoc.v:128591.3-128625.6" + process $proc$libresoc.v:128591$4983 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:128796.5-128796.29" + attribute \src "libresoc.v:128592.5-128592.29" switch \initial - attribute \src "libresoc.v:128796.9-128796.17" + attribute \src "libresoc.v:128592.9-128592.17" case 1'1 case end @@ -202181,41 +201977,41 @@ module \dec_bi$170 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:128576$4964_Y - connect \$11 $pos$libresoc.v:128577$4966_Y - connect \$14 $sshl$libresoc.v:128578$4967_Y - connect \$17 $sshl$libresoc.v:128579$4968_Y - connect \$1 $pos$libresoc.v:128580$4970_Y - connect \$20 $sshl$libresoc.v:128581$4971_Y - connect \$23 $sshl$libresoc.v:128582$4972_Y - connect \$4 $sshl$libresoc.v:128583$4973_Y - connect \$3 $pos$libresoc.v:128584$4975_Y + connect \$9 $pos$libresoc.v:128372$4964_Y + connect \$11 $pos$libresoc.v:128373$4966_Y + connect \$14 $sshl$libresoc.v:128374$4967_Y + connect \$17 $sshl$libresoc.v:128375$4968_Y + connect \$1 $pos$libresoc.v:128376$4970_Y + connect \$20 $sshl$libresoc.v:128377$4971_Y + connect \$23 $sshl$libresoc.v:128378$4972_Y + connect \$4 $sshl$libresoc.v:128379$4973_Y + connect \$3 $pos$libresoc.v:128380$4975_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:128838.1-128886.10" +attribute \src "libresoc.v:128634.1-128682.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" attribute \generator "nMigen" module \dec_c - attribute \src "libresoc.v:128839.7-128839.20" + attribute \src "libresoc.v:128635.7-128635.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128856.3-128870.6" + attribute \src "libresoc.v:128652.3-128666.6" wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:128871.3-128885.6" + attribute \src "libresoc.v:128667.3-128681.6" wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:128856.3-128870.6" + attribute \src "libresoc.v:128652.3-128666.6" wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:128871.3-128885.6" + attribute \src "libresoc.v:128667.3-128681.6" wire $1\reg_c_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 4 \RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \RS - attribute \src "libresoc.v:128839.7-128839.15" + attribute \src "libresoc.v:128635.7-128635.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 output 1 \reg_c @@ -202227,22 +202023,22 @@ module \dec_c attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:128839.7-128839.20" - process $proc$libresoc.v:128839$4987 + attribute \src "libresoc.v:128635.7-128635.20" + process $proc$libresoc.v:128635$4987 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128856.3-128870.6" - process $proc$libresoc.v:128856$4985 + attribute \src "libresoc.v:128652.3-128666.6" + process $proc$libresoc.v:128652$4985 assign { } { } assign { } { } assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:128857.5-128857.29" + attribute \src "libresoc.v:128653.5-128653.29" switch \initial - attribute \src "libresoc.v:128857.9-128857.17" + attribute \src "libresoc.v:128653.9-128653.17" case 1'1 case end @@ -202262,14 +202058,14 @@ module \dec_c sync always update \reg_c $0\reg_c[4:0] end - attribute \src "libresoc.v:128871.3-128885.6" - process $proc$libresoc.v:128871$4986 + attribute \src "libresoc.v:128667.3-128681.6" + process $proc$libresoc.v:128667$4986 assign { } { } assign { } { } assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:128872.5-128872.29" + attribute \src "libresoc.v:128668.5-128668.29" switch \initial - attribute \src "libresoc.v:128872.9-128872.17" + attribute \src "libresoc.v:128668.9-128668.17" case 1'1 case end @@ -202290,69 +202086,69 @@ module \dec_c update \reg_c_ok $0\reg_c_ok[0:0] end end -attribute \src "libresoc.v:128890.1-129426.10" +attribute \src "libresoc.v:128686.1-129222.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" attribute \generator "nMigen" module \dec_cr_in - attribute \src "libresoc.v:129246.3-129280.6" + attribute \src "libresoc.v:129042.3-129076.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:129281.3-129311.6" + attribute \src "libresoc.v:129077.3-129107.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:129079.3-129109.6" + attribute \src "libresoc.v:128875.3-128905.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:129312.3-129342.6" + attribute \src "libresoc.v:129108.3-129138.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:129157.3-129187.6" + attribute \src "libresoc.v:128953.3-128983.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:129044.3-129078.6" + attribute \src "libresoc.v:128840.3-128874.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129110.3-129156.6" + attribute \src "libresoc.v:128906.3-128952.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:129188.3-129226.6" + attribute \src "libresoc.v:128984.3-129022.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128891.7-128891.20" + attribute \src "libresoc.v:128687.7-128687.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129343.3-129381.6" + attribute \src "libresoc.v:129139.3-129177.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:129382.3-129425.6" + attribute \src "libresoc.v:129178.3-129221.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:129227.3-129245.6" + attribute \src "libresoc.v:129023.3-129041.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:129246.3-129280.6" + attribute \src "libresoc.v:129042.3-129076.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129281.3-129311.6" + attribute \src "libresoc.v:129077.3-129107.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:129079.3-129109.6" + attribute \src "libresoc.v:128875.3-128905.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:129312.3-129342.6" + attribute \src "libresoc.v:129108.3-129138.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:129157.3-129187.6" + attribute \src "libresoc.v:128953.3-128983.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:129044.3-129078.6" + attribute \src "libresoc.v:128840.3-128874.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129110.3-129156.6" + attribute \src "libresoc.v:128906.3-128952.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:129188.3-129226.6" + attribute \src "libresoc.v:128984.3-129022.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129343.3-129381.6" + attribute \src "libresoc.v:129139.3-129177.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:129382.3-129425.6" + attribute \src "libresoc.v:129178.3-129221.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:129227.3-129245.6" + attribute \src "libresoc.v:129023.3-129041.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:129110.3-129156.6" + attribute \src "libresoc.v:128906.3-128952.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:129382.3-129425.6" + attribute \src "libresoc.v:129178.3-129221.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:129037.17-129037.112" - wire $and$libresoc.v:129037$4989_Y - attribute \src "libresoc.v:129039.17-129039.112" - wire $and$libresoc.v:129039$4991_Y - attribute \src "libresoc.v:129036.17-129036.117" - wire $eq$libresoc.v:129036$4988_Y - attribute \src "libresoc.v:129038.17-129038.117" - wire $eq$libresoc.v:129038$4990_Y + attribute \src "libresoc.v:128833.17-128833.112" + wire $and$libresoc.v:128833$4989_Y + attribute \src "libresoc.v:128835.17-128835.112" + wire $and$libresoc.v:128835$4991_Y + attribute \src "libresoc.v:128832.17-128832.117" + wire $eq$libresoc.v:128832$4988_Y + attribute \src "libresoc.v:128834.17-128834.117" + wire $eq$libresoc.v:128834$4990_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" @@ -202391,7 +202187,7 @@ module \dec_cr_in wire width 8 output 3 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \cr_fxm_ok - attribute \src "libresoc.v:128891.7-128891.15" + attribute \src "libresoc.v:128687.7-128687.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" wire width 32 input 1 \insn_in @@ -202492,7 +202288,7 @@ module \dec_cr_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" wire width 2 \sv_override attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" - cell $and $and$libresoc.v:129037$4989 + cell $and $and$libresoc.v:128833$4989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202500,10 +202296,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:129037$4989_Y + connect \Y $and$libresoc.v:128833$4989_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" - cell $and $and$libresoc.v:129039$4991 + cell $and $and$libresoc.v:128835$4991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202511,10 +202307,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:129039$4991_Y + connect \Y $and$libresoc.v:128835$4991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" - cell $eq $eq$libresoc.v:129036$4988 + cell $eq $eq$libresoc.v:128832$4988 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -202522,10 +202318,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:129036$4988_Y + connect \Y $eq$libresoc.v:128832$4988_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" - cell $eq $eq$libresoc.v:129038$4990 + cell $eq $eq$libresoc.v:128834$4990 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -202533,30 +202329,30 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:129038$4990_Y + connect \Y $eq$libresoc.v:128834$4990_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:129040.9-129043.4" + attribute \src "libresoc.v:128836.9-128839.4" cell \ppick \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:128891.7-128891.20" - process $proc$libresoc.v:128891$5003 + attribute \src "libresoc.v:128687.7-128687.20" + process $proc$libresoc.v:128687$5003 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129044.3-129078.6" - process $proc$libresoc.v:129044$4992 + attribute \src "libresoc.v:128840.3-128874.6" + process $proc$libresoc.v:128840$4992 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129045.5-129045.29" + attribute \src "libresoc.v:128841.5-128841.29" switch \initial - attribute \src "libresoc.v:129045.9-129045.17" + attribute \src "libresoc.v:128841.9-128841.17" case 1'1 case end @@ -202595,14 +202391,14 @@ module \dec_cr_in sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:129079.3-129109.6" - process $proc$libresoc.v:129079$4993 + attribute \src "libresoc.v:128875.3-128905.6" + process $proc$libresoc.v:128875$4993 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:129080.5-129080.29" + attribute \src "libresoc.v:128876.5-128876.29" switch \initial - attribute \src "libresoc.v:129080.9-129080.17" + attribute \src "libresoc.v:128876.9-128876.17" case 1'1 case end @@ -202633,14 +202429,14 @@ module \dec_cr_in sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:129110.3-129156.6" - process $proc$libresoc.v:129110$4994 + attribute \src "libresoc.v:128906.3-128952.6" + process $proc$libresoc.v:128906$4994 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:129111.5-129111.29" + attribute \src "libresoc.v:128907.5-128907.29" switch \initial - attribute \src "libresoc.v:129111.9-129111.17" + attribute \src "libresoc.v:128907.9-128907.17" case 1'1 case end @@ -202688,14 +202484,14 @@ module \dec_cr_in sync always update \cr_fxm $0\cr_fxm[7:0] end - attribute \src "libresoc.v:129157.3-129187.6" - process $proc$libresoc.v:129157$4995 + attribute \src "libresoc.v:128953.3-128983.6" + process $proc$libresoc.v:128953$4995 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:129158.5-129158.29" + attribute \src "libresoc.v:128954.5-128954.29" switch \initial - attribute \src "libresoc.v:129158.9-129158.17" + attribute \src "libresoc.v:128954.9-128954.17" case 1'1 case end @@ -202726,14 +202522,14 @@ module \dec_cr_in sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:129188.3-129226.6" - process $proc$libresoc.v:129188$4996 + attribute \src "libresoc.v:128984.3-129022.6" + process $proc$libresoc.v:128984$4996 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129189.5-129189.29" + attribute \src "libresoc.v:128985.5-128985.29" switch \initial - attribute \src "libresoc.v:129189.9-129189.17" + attribute \src "libresoc.v:128985.9-128985.17" case 1'1 case end @@ -202770,14 +202566,14 @@ module \dec_cr_in sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:129227.3-129245.6" - process $proc$libresoc.v:129227$4997 + attribute \src "libresoc.v:129023.3-129041.6" + process $proc$libresoc.v:129023$4997 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:129228.5-129228.29" + attribute \src "libresoc.v:129024.5-129024.29" switch \initial - attribute \src "libresoc.v:129228.9-129228.17" + attribute \src "libresoc.v:129024.9-129024.17" case 1'1 case end @@ -202800,14 +202596,14 @@ module \dec_cr_in sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:129246.3-129280.6" - process $proc$libresoc.v:129246$4998 + attribute \src "libresoc.v:129042.3-129076.6" + process $proc$libresoc.v:129042$4998 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129247.5-129247.29" + attribute \src "libresoc.v:129043.5-129043.29" switch \initial - attribute \src "libresoc.v:129247.9-129247.17" + attribute \src "libresoc.v:129043.9-129043.17" case 1'1 case end @@ -202846,14 +202642,14 @@ module \dec_cr_in sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:129281.3-129311.6" - process $proc$libresoc.v:129281$4999 + attribute \src "libresoc.v:129077.3-129107.6" + process $proc$libresoc.v:129077$4999 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:129282.5-129282.29" + attribute \src "libresoc.v:129078.5-129078.29" switch \initial - attribute \src "libresoc.v:129282.9-129282.17" + attribute \src "libresoc.v:129078.9-129078.17" case 1'1 case end @@ -202884,14 +202680,14 @@ module \dec_cr_in sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:129312.3-129342.6" - process $proc$libresoc.v:129312$5000 + attribute \src "libresoc.v:129108.3-129138.6" + process $proc$libresoc.v:129108$5000 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:129313.5-129313.29" + attribute \src "libresoc.v:129109.5-129109.29" switch \initial - attribute \src "libresoc.v:129313.9-129313.17" + attribute \src "libresoc.v:129109.9-129109.17" case 1'1 case end @@ -202922,14 +202718,14 @@ module \dec_cr_in sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:129343.3-129381.6" - process $proc$libresoc.v:129343$5001 + attribute \src "libresoc.v:129139.3-129177.6" + process $proc$libresoc.v:129139$5001 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:129344.5-129344.29" + attribute \src "libresoc.v:129140.5-129140.29" switch \initial - attribute \src "libresoc.v:129344.9-129344.17" + attribute \src "libresoc.v:129140.9-129140.17" case 1'1 case end @@ -202966,14 +202762,14 @@ module \dec_cr_in sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:129382.3-129425.6" - process $proc$libresoc.v:129382$5002 + attribute \src "libresoc.v:129178.3-129221.6" + process $proc$libresoc.v:129178$5002 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:129383.5-129383.29" + attribute \src "libresoc.v:129179.5-129179.29" switch \initial - attribute \src "libresoc.v:129383.9-129383.17" + attribute \src "libresoc.v:129179.9-129179.17" case 1'1 case end @@ -203019,60 +202815,60 @@ module \dec_cr_in sync always update \ppick_i $0\ppick_i[7:0] end - connect \$1 $eq$libresoc.v:129036$4988_Y - connect \$3 $and$libresoc.v:129037$4989_Y - connect \$5 $eq$libresoc.v:129038$4990_Y - connect \$7 $and$libresoc.v:129039$4991_Y + connect \$1 $eq$libresoc.v:128832$4988_Y + connect \$3 $and$libresoc.v:128833$4989_Y + connect \$5 $eq$libresoc.v:128834$4990_Y + connect \$7 $and$libresoc.v:128835$4991_Y end -attribute \src "libresoc.v:129430.1-129792.10" +attribute \src "libresoc.v:129226.1-129588.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" attribute \generator "nMigen" module \dec_cr_out - attribute \src "libresoc.v:129638.3-129664.6" + attribute \src "libresoc.v:129434.3-129460.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:129561.3-129587.6" + attribute \src "libresoc.v:129357.3-129383.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129737.3-129791.6" + attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:129588.3-129618.6" + attribute \src "libresoc.v:129384.3-129414.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129431.7-129431.20" + attribute \src "libresoc.v:129227.7-129227.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129665.3-129695.6" + attribute \src "libresoc.v:129461.3-129491.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:129696.3-129736.6" + attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:129619.3-129637.6" + attribute \src "libresoc.v:129415.3-129433.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:129638.3-129664.6" + attribute \src "libresoc.v:129434.3-129460.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129561.3-129587.6" + attribute \src "libresoc.v:129357.3-129383.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129737.3-129791.6" + attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:129588.3-129618.6" + attribute \src "libresoc.v:129384.3-129414.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129665.3-129695.6" + attribute \src "libresoc.v:129461.3-129491.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:129696.3-129736.6" + attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:129619.3-129637.6" + attribute \src "libresoc.v:129415.3-129433.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:129737.3-129791.6" + attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:129696.3-129736.6" + attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:129737.3-129791.6" + attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:129696.3-129736.6" + attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:129737.3-129791.6" + attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:129554.17-129554.117" - wire $eq$libresoc.v:129554$5004_Y - attribute \src "libresoc.v:129555.17-129555.117" - wire $eq$libresoc.v:129555$5005_Y + attribute \src "libresoc.v:129350.17-129350.117" + wire $eq$libresoc.v:129350$5004_Y + attribute \src "libresoc.v:129351.17-129351.117" + wire $eq$libresoc.v:129351$5005_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" @@ -203091,7 +202887,7 @@ module \dec_cr_out wire width 8 output 4 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \cr_fxm_ok - attribute \src "libresoc.v:129431.7-129431.15" + attribute \src "libresoc.v:129227.7-129227.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" wire width 32 input 1 \insn_in @@ -203194,7 +202990,7 @@ module \dec_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:621" wire width 2 \sv_override attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" - cell $eq $eq$libresoc.v:129554$5004 + cell $eq $eq$libresoc.v:129350$5004 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -203202,10 +202998,10 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:129554$5004_Y + connect \Y $eq$libresoc.v:129350$5004_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" - cell $eq $eq$libresoc.v:129555$5005 + cell $eq $eq$libresoc.v:129351$5005 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -203213,31 +203009,31 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:129555$5005_Y + connect \Y $eq$libresoc.v:129351$5005_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:129556.15-129560.4" + attribute \src "libresoc.v:129352.15-129356.4" cell \ppick$175 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:129431.7-129431.20" - process $proc$libresoc.v:129431$5013 + attribute \src "libresoc.v:129227.7-129227.20" + process $proc$libresoc.v:129227$5013 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129561.3-129587.6" - process $proc$libresoc.v:129561$5006 + attribute \src "libresoc.v:129357.3-129383.6" + process $proc$libresoc.v:129357$5006 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129562.5-129562.29" + attribute \src "libresoc.v:129358.5-129358.29" switch \initial - attribute \src "libresoc.v:129562.9-129562.17" + attribute \src "libresoc.v:129358.9-129358.17" case 1'1 case end @@ -203268,14 +203064,14 @@ module \dec_cr_out sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:129588.3-129618.6" - process $proc$libresoc.v:129588$5007 + attribute \src "libresoc.v:129384.3-129414.6" + process $proc$libresoc.v:129384$5007 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129589.5-129589.29" + attribute \src "libresoc.v:129385.5-129385.29" switch \initial - attribute \src "libresoc.v:129589.9-129589.17" + attribute \src "libresoc.v:129385.9-129385.17" case 1'1 case end @@ -203306,14 +203102,14 @@ module \dec_cr_out sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:129619.3-129637.6" - process $proc$libresoc.v:129619$5008 + attribute \src "libresoc.v:129415.3-129433.6" + process $proc$libresoc.v:129415$5008 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:129620.5-129620.29" + attribute \src "libresoc.v:129416.5-129416.29" switch \initial - attribute \src "libresoc.v:129620.9-129620.17" + attribute \src "libresoc.v:129416.9-129416.17" case 1'1 case end @@ -203336,14 +203132,14 @@ module \dec_cr_out sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:129638.3-129664.6" - process $proc$libresoc.v:129638$5009 + attribute \src "libresoc.v:129434.3-129460.6" + process $proc$libresoc.v:129434$5009 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129639.5-129639.29" + attribute \src "libresoc.v:129435.5-129435.29" switch \initial - attribute \src "libresoc.v:129639.9-129639.17" + attribute \src "libresoc.v:129435.9-129435.17" case 1'1 case end @@ -203374,14 +203170,14 @@ module \dec_cr_out sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:129665.3-129695.6" - process $proc$libresoc.v:129665$5010 + attribute \src "libresoc.v:129461.3-129491.6" + process $proc$libresoc.v:129461$5010 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:129666.5-129666.29" + attribute \src "libresoc.v:129462.5-129462.29" switch \initial - attribute \src "libresoc.v:129666.9-129666.17" + attribute \src "libresoc.v:129462.9-129462.17" case 1'1 case end @@ -203412,14 +203208,14 @@ module \dec_cr_out sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:129696.3-129736.6" - process $proc$libresoc.v:129696$5011 + attribute \src "libresoc.v:129492.3-129532.6" + process $proc$libresoc.v:129492$5011 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:129697.5-129697.29" + attribute \src "libresoc.v:129493.5-129493.29" switch \initial - attribute \src "libresoc.v:129697.9-129697.17" + attribute \src "libresoc.v:129493.9-129493.17" case 1'1 case end @@ -203468,14 +203264,14 @@ module \dec_cr_out sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:129737.3-129791.6" - process $proc$libresoc.v:129737$5012 + attribute \src "libresoc.v:129533.3-129587.6" + process $proc$libresoc.v:129533$5012 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:129738.5-129738.29" + attribute \src "libresoc.v:129534.5-129534.29" switch \initial - attribute \src "libresoc.v:129738.9-129738.17" + attribute \src "libresoc.v:129534.9-129534.17" case 1'1 case end @@ -203539,74 +203335,74 @@ module \dec_cr_out sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:129554$5004_Y - connect \$3 $eq$libresoc.v:129555$5005_Y + connect \$1 $eq$libresoc.v:129350$5004_Y + connect \$3 $eq$libresoc.v:129351$5005_Y end -attribute \src "libresoc.v:129796.1-130313.10" +attribute \src "libresoc.v:129592.1-130109.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" attribute \generator "nMigen" module \dec_o - attribute \src "libresoc.v:130266.3-130312.6" + attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:130266.3-130312.6" + attribute \src "libresoc.v:130062.3-130108.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:129797.7-129797.20" + attribute \src "libresoc.v:129593.7-129593.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130168.3-130182.6" + attribute \src "libresoc.v:129964.3-129978.6" wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:130183.3-130197.6" + attribute \src "libresoc.v:129979.3-129993.6" wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:130198.3-130216.6" + attribute \src "libresoc.v:129994.3-130012.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:130241.3-130265.6" + attribute \src "libresoc.v:130037.3-130061.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:130241.3-130265.6" + attribute \src "libresoc.v:130037.3-130061.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:130217.3-130240.6" + attribute \src "libresoc.v:130013.3-130036.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:130266.3-130312.6" + attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:130266.3-130312.6" + attribute \src "libresoc.v:130062.3-130108.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:130168.3-130182.6" + attribute \src "libresoc.v:129964.3-129978.6" wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:130183.3-130197.6" + attribute \src "libresoc.v:129979.3-129993.6" wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:130198.3-130216.6" + attribute \src "libresoc.v:129994.3-130012.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:130241.3-130265.6" + attribute \src "libresoc.v:130037.3-130061.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:130241.3-130265.6" + attribute \src "libresoc.v:130037.3-130061.6" wire $1\spr_o_ok[0:0] - attribute \src "libresoc.v:130217.3-130240.6" + attribute \src "libresoc.v:130013.3-130036.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:130266.3-130312.6" + attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:130266.3-130312.6" + attribute \src "libresoc.v:130062.3-130108.6" wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:130241.3-130265.6" + attribute \src "libresoc.v:130037.3-130061.6" wire width 10 $2\spr_o[9:0] - attribute \src "libresoc.v:130241.3-130265.6" + attribute \src "libresoc.v:130037.3-130061.6" wire $2\spr_o_ok[0:0] - attribute \src "libresoc.v:130217.3-130240.6" + attribute \src "libresoc.v:130013.3-130036.6" wire width 10 $2\sprmap_spr_i[9:0] - attribute \src "libresoc.v:130266.3-130312.6" + attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $3\fast_o[2:0] - attribute \src "libresoc.v:130266.3-130312.6" + attribute \src "libresoc.v:130062.3-130108.6" wire $3\fast_o_ok[0:0] - attribute \src "libresoc.v:130266.3-130312.6" + attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $4\fast_o[2:0] - attribute \src "libresoc.v:130266.3-130312.6" + attribute \src "libresoc.v:130062.3-130108.6" wire $4\fast_o_ok[0:0] - attribute \src "libresoc.v:130157.17-130157.117" - wire $eq$libresoc.v:130157$5014_Y - attribute \src "libresoc.v:130158.17-130158.117" - wire $eq$libresoc.v:130158$5015_Y - attribute \src "libresoc.v:130159.17-130159.117" - wire $eq$libresoc.v:130159$5016_Y - attribute \src "libresoc.v:130160.17-130160.104" - wire $not$libresoc.v:130160$5017_Y + attribute \src "libresoc.v:129953.17-129953.117" + wire $eq$libresoc.v:129953$5014_Y + attribute \src "libresoc.v:129954.17-129954.117" + wire $eq$libresoc.v:129954$5015_Y + attribute \src "libresoc.v:129955.17-129955.117" + wire $eq$libresoc.v:129955$5016_Y + attribute \src "libresoc.v:129956.17-129956.104" + wire $not$libresoc.v:129956$5017_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" @@ -203627,7 +203423,7 @@ module \dec_o wire width 3 output 7 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 8 \fast_o_ok - attribute \src "libresoc.v:129797.7-129797.15" + attribute \src "libresoc.v:129593.7-129593.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203963,7 +203759,7 @@ module \dec_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \sprmap_spr_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" - cell $eq $eq$libresoc.v:130157$5014 + cell $eq $eq$libresoc.v:129953$5014 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -203971,10 +203767,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:130157$5014_Y + connect \Y $eq$libresoc.v:129953$5014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" - cell $eq $eq$libresoc.v:130158$5015 + cell $eq $eq$libresoc.v:129954$5015 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -203982,10 +203778,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:130158$5015_Y + connect \Y $eq$libresoc.v:129954$5015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" - cell $eq $eq$libresoc.v:130159$5016 + cell $eq $eq$libresoc.v:129955$5016 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -203993,18 +203789,18 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:130159$5016_Y + connect \Y $eq$libresoc.v:129955$5016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" - cell $not $not$libresoc.v:130160$5017 + cell $not $not$libresoc.v:129956$5017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:130160$5017_Y + connect \Y $not$libresoc.v:129956$5017_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:130161.16-130167.4" + attribute \src "libresoc.v:129957.16-129963.4" cell \sprmap$174 \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -204012,22 +203808,22 @@ module \dec_o connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:129797.7-129797.20" - process $proc$libresoc.v:129797$5024 + attribute \src "libresoc.v:129593.7-129593.20" + process $proc$libresoc.v:129593$5024 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130168.3-130182.6" - process $proc$libresoc.v:130168$5018 + attribute \src "libresoc.v:129964.3-129978.6" + process $proc$libresoc.v:129964$5018 assign { } { } assign { } { } assign $0\reg_o[4:0] $1\reg_o[4:0] - attribute \src "libresoc.v:130169.5-130169.29" + attribute \src "libresoc.v:129965.5-129965.29" switch \initial - attribute \src "libresoc.v:130169.9-130169.17" + attribute \src "libresoc.v:129965.9-129965.17" case 1'1 case end @@ -204047,14 +203843,14 @@ module \dec_o sync always update \reg_o $0\reg_o[4:0] end - attribute \src "libresoc.v:130183.3-130197.6" - process $proc$libresoc.v:130183$5019 + attribute \src "libresoc.v:129979.3-129993.6" + process $proc$libresoc.v:129979$5019 assign { } { } assign { } { } assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:130184.5-130184.29" + attribute \src "libresoc.v:129980.5-129980.29" switch \initial - attribute \src "libresoc.v:130184.9-130184.17" + attribute \src "libresoc.v:129980.9-129980.17" case 1'1 case end @@ -204074,14 +203870,14 @@ module \dec_o sync always update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:130198.3-130216.6" - process $proc$libresoc.v:130198$5020 + attribute \src "libresoc.v:129994.3-130012.6" + process $proc$libresoc.v:129994$5020 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:130199.5-130199.29" + attribute \src "libresoc.v:129995.5-129995.29" switch \initial - attribute \src "libresoc.v:130199.9-130199.17" + attribute \src "libresoc.v:129995.9-129995.17" case 1'1 case end @@ -204103,14 +203899,14 @@ module \dec_o sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:130217.3-130240.6" - process $proc$libresoc.v:130217$5021 + attribute \src "libresoc.v:130013.3-130036.6" + process $proc$libresoc.v:130013$5021 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:130218.5-130218.29" + attribute \src "libresoc.v:130014.5-130014.29" switch \initial - attribute \src "libresoc.v:130218.9-130218.17" + attribute \src "libresoc.v:130014.9-130014.17" case 1'1 case end @@ -204141,17 +203937,17 @@ module \dec_o sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:130241.3-130265.6" - process $proc$libresoc.v:130241$5022 + attribute \src "libresoc.v:130037.3-130061.6" + process $proc$libresoc.v:130037$5022 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:130242.5-130242.29" + attribute \src "libresoc.v:130038.5-130038.29" switch \initial - attribute \src "libresoc.v:130242.9-130242.17" + attribute \src "libresoc.v:130038.9-130038.17" case 1'1 case end @@ -204190,8 +203986,8 @@ module \dec_o update \spr_o $0\spr_o[9:0] update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:130266.3-130312.6" - process $proc$libresoc.v:130266$5023 + attribute \src "libresoc.v:130062.3-130108.6" + process $proc$libresoc.v:130062$5023 assign { } { } assign { } { } assign { } { } @@ -204200,9 +203996,9 @@ module \dec_o assign { } { } assign $0\fast_o[2:0] $3\fast_o[2:0] assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:130267.5-130267.29" + attribute \src "libresoc.v:130063.5-130063.29" switch \initial - attribute \src "libresoc.v:130267.9-130267.17" + attribute \src "libresoc.v:130063.9-130063.17" case 1'1 case end @@ -204271,42 +204067,42 @@ module \dec_o update \fast_o $0\fast_o[2:0] update \fast_o_ok $0\fast_o_ok[0:0] end - connect \$1 $eq$libresoc.v:130157$5014_Y - connect \$3 $eq$libresoc.v:130158$5015_Y - connect \$5 $eq$libresoc.v:130159$5016_Y - connect \$7 $not$libresoc.v:130160$5017_Y + connect \$1 $eq$libresoc.v:129953$5014_Y + connect \$3 $eq$libresoc.v:129954$5015_Y + connect \$5 $eq$libresoc.v:129955$5016_Y + connect \$7 $not$libresoc.v:129956$5017_Y end -attribute \src "libresoc.v:130317.1-130485.10" +attribute \src "libresoc.v:130113.1-130281.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" attribute \generator "nMigen" module \dec_o2 - attribute \src "libresoc.v:130445.3-130464.6" + attribute \src "libresoc.v:130241.3-130260.6" wire width 3 $0\fast_o2[2:0] - attribute \src "libresoc.v:130465.3-130484.6" + attribute \src "libresoc.v:130261.3-130280.6" wire $0\fast_o2_ok[0:0] - attribute \src "libresoc.v:130318.7-130318.20" + attribute \src "libresoc.v:130114.7-130114.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130425.3-130434.6" + attribute \src "libresoc.v:130221.3-130230.6" wire width 5 $0\reg_o2[4:0] - attribute \src "libresoc.v:130435.3-130444.6" + attribute \src "libresoc.v:130231.3-130240.6" wire $0\reg_o2_ok[0:0] - attribute \src "libresoc.v:130445.3-130464.6" + attribute \src "libresoc.v:130241.3-130260.6" wire width 3 $1\fast_o2[2:0] - attribute \src "libresoc.v:130465.3-130484.6" + attribute \src "libresoc.v:130261.3-130280.6" wire $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:130425.3-130434.6" + attribute \src "libresoc.v:130221.3-130230.6" wire width 5 $1\reg_o2[4:0] - attribute \src "libresoc.v:130435.3-130444.6" + attribute \src "libresoc.v:130231.3-130240.6" wire $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:130445.3-130464.6" + attribute \src "libresoc.v:130241.3-130260.6" wire width 3 $2\fast_o2[2:0] - attribute \src "libresoc.v:130465.3-130484.6" + attribute \src "libresoc.v:130261.3-130280.6" wire $2\fast_o2_ok[0:0] - attribute \src "libresoc.v:130423.17-130423.108" - wire $eq$libresoc.v:130423$5025_Y - attribute \src "libresoc.v:130424.17-130424.108" - wire $eq$libresoc.v:130424$5026_Y + attribute \src "libresoc.v:130219.17-130219.108" + wire $eq$libresoc.v:130219$5025_Y + attribute \src "libresoc.v:130220.17-130220.108" + wire $eq$libresoc.v:130220$5026_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" @@ -204317,7 +204113,7 @@ module \dec_o2 wire width 3 output 4 \fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \fast_o2_ok - attribute \src "libresoc.v:130318.7-130318.15" + attribute \src "libresoc.v:130114.7-130114.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -204410,7 +204206,7 @@ module \dec_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 input 6 \upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" - cell $eq $eq$libresoc.v:130423$5025 + cell $eq $eq$libresoc.v:130219$5025 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -204418,10 +204214,10 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:130423$5025_Y + connect \Y $eq$libresoc.v:130219$5025_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" - cell $eq $eq$libresoc.v:130424$5026 + cell $eq $eq$libresoc.v:130220$5026 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -204429,24 +204225,24 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:130424$5026_Y + connect \Y $eq$libresoc.v:130220$5026_Y end - attribute \src "libresoc.v:130318.7-130318.20" - process $proc$libresoc.v:130318$5031 + attribute \src "libresoc.v:130114.7-130114.20" + process $proc$libresoc.v:130114$5031 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130425.3-130434.6" - process $proc$libresoc.v:130425$5027 + attribute \src "libresoc.v:130221.3-130230.6" + process $proc$libresoc.v:130221$5027 assign { } { } assign { } { } assign $0\reg_o2[4:0] $1\reg_o2[4:0] - attribute \src "libresoc.v:130426.5-130426.29" + attribute \src "libresoc.v:130222.5-130222.29" switch \initial - attribute \src "libresoc.v:130426.9-130426.17" + attribute \src "libresoc.v:130222.9-130222.17" case 1'1 case end @@ -204462,14 +204258,14 @@ module \dec_o2 sync always update \reg_o2 $0\reg_o2[4:0] end - attribute \src "libresoc.v:130435.3-130444.6" - process $proc$libresoc.v:130435$5028 + attribute \src "libresoc.v:130231.3-130240.6" + process $proc$libresoc.v:130231$5028 assign { } { } assign { } { } assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:130436.5-130436.29" + attribute \src "libresoc.v:130232.5-130232.29" switch \initial - attribute \src "libresoc.v:130436.9-130436.17" + attribute \src "libresoc.v:130232.9-130232.17" case 1'1 case end @@ -204485,14 +204281,14 @@ module \dec_o2 sync always update \reg_o2_ok $0\reg_o2_ok[0:0] end - attribute \src "libresoc.v:130445.3-130464.6" - process $proc$libresoc.v:130445$5029 + attribute \src "libresoc.v:130241.3-130260.6" + process $proc$libresoc.v:130241$5029 assign { } { } assign { } { } assign $0\fast_o2[2:0] $1\fast_o2[2:0] - attribute \src "libresoc.v:130446.5-130446.29" + attribute \src "libresoc.v:130242.5-130242.29" switch \initial - attribute \src "libresoc.v:130446.9-130446.17" + attribute \src "libresoc.v:130242.9-130242.17" case 1'1 case end @@ -204521,14 +204317,14 @@ module \dec_o2 sync always update \fast_o2 $0\fast_o2[2:0] end - attribute \src "libresoc.v:130465.3-130484.6" - process $proc$libresoc.v:130465$5030 + attribute \src "libresoc.v:130261.3-130280.6" + process $proc$libresoc.v:130261$5030 assign { } { } assign { } { } assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:130466.5-130466.29" + attribute \src "libresoc.v:130262.5-130262.29" switch \initial - attribute \src "libresoc.v:130466.9-130466.17" + attribute \src "libresoc.v:130262.9-130262.17" case 1'1 case end @@ -204557,27 +204353,27 @@ module \dec_o2 sync always update \fast_o2_ok $0\fast_o2_ok[0:0] end - connect \$1 $eq$libresoc.v:130423$5025_Y - connect \$3 $eq$libresoc.v:130424$5026_Y + connect \$1 $eq$libresoc.v:130219$5025_Y + connect \$3 $eq$libresoc.v:130220$5026_Y end -attribute \src "libresoc.v:130489.1-130624.10" +attribute \src "libresoc.v:130285.1-130420.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" attribute \generator "nMigen" module \dec_oe - attribute \src "libresoc.v:130490.7-130490.20" + attribute \src "libresoc.v:130286.7-130286.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130582.3-130602.6" + attribute \src "libresoc.v:130378.3-130398.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130603.3-130623.6" + attribute \src "libresoc.v:130399.3-130419.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130582.3-130602.6" + attribute \src "libresoc.v:130378.3-130398.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130603.3-130623.6" + attribute \src "libresoc.v:130399.3-130419.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130582.3-130602.6" + attribute \src "libresoc.v:130378.3-130398.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130603.3-130623.6" + attribute \src "libresoc.v:130399.3-130419.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \ALU_OE @@ -204658,7 +204454,7 @@ module \dec_oe attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \ALU_internal_op - attribute \src "libresoc.v:130490.7-130490.15" + attribute \src "libresoc.v:130286.7-130286.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe @@ -204670,22 +204466,22 @@ module \dec_oe attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130490.7-130490.20" - process $proc$libresoc.v:130490$5034 + attribute \src "libresoc.v:130286.7-130286.20" + process $proc$libresoc.v:130286$5034 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130582.3-130602.6" - process $proc$libresoc.v:130582$5032 + attribute \src "libresoc.v:130378.3-130398.6" + process $proc$libresoc.v:130378$5032 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130583.5-130583.29" + attribute \src "libresoc.v:130379.5-130379.29" switch \initial - attribute \src "libresoc.v:130583.9-130583.17" + attribute \src "libresoc.v:130379.9-130379.17" case 1'1 case end @@ -204711,14 +204507,14 @@ module \dec_oe sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130603.3-130623.6" - process $proc$libresoc.v:130603$5033 + attribute \src "libresoc.v:130399.3-130419.6" + process $proc$libresoc.v:130399$5033 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130604.5-130604.29" + attribute \src "libresoc.v:130400.5-130400.29" switch \initial - attribute \src "libresoc.v:130604.9-130604.17" + attribute \src "libresoc.v:130400.9-130400.17" case 1'1 case end @@ -204745,24 +204541,24 @@ module \dec_oe update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130628.1-130761.10" +attribute \src "libresoc.v:130424.1-130557.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" attribute \generator "nMigen" module \dec_oe$140 - attribute \src "libresoc.v:130629.7-130629.20" + attribute \src "libresoc.v:130425.7-130425.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130719.3-130739.6" + attribute \src "libresoc.v:130515.3-130535.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130740.3-130760.6" + attribute \src "libresoc.v:130536.3-130556.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130719.3-130739.6" + attribute \src "libresoc.v:130515.3-130535.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130740.3-130760.6" + attribute \src "libresoc.v:130536.3-130556.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130719.3-130739.6" + attribute \src "libresoc.v:130515.3-130535.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130740.3-130760.6" + attribute \src "libresoc.v:130536.3-130556.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \CR_OE @@ -204843,7 +204639,7 @@ module \dec_oe$140 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \CR_internal_op - attribute \src "libresoc.v:130629.7-130629.15" + attribute \src "libresoc.v:130425.7-130425.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe @@ -204855,22 +204651,22 @@ module \dec_oe$140 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:130629.7-130629.20" - process $proc$libresoc.v:130629$5037 + attribute \src "libresoc.v:130425.7-130425.20" + process $proc$libresoc.v:130425$5037 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130719.3-130739.6" - process $proc$libresoc.v:130719$5035 + attribute \src "libresoc.v:130515.3-130535.6" + process $proc$libresoc.v:130515$5035 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130720.5-130720.29" + attribute \src "libresoc.v:130516.5-130516.29" switch \initial - attribute \src "libresoc.v:130720.9-130720.17" + attribute \src "libresoc.v:130516.9-130516.17" case 1'1 case end @@ -204896,14 +204692,14 @@ module \dec_oe$140 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130740.3-130760.6" - process $proc$libresoc.v:130740$5036 + attribute \src "libresoc.v:130536.3-130556.6" + process $proc$libresoc.v:130536$5036 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130741.5-130741.29" + attribute \src "libresoc.v:130537.5-130537.29" switch \initial - attribute \src "libresoc.v:130741.9-130741.17" + attribute \src "libresoc.v:130537.9-130537.17" case 1'1 case end @@ -204930,24 +204726,24 @@ module \dec_oe$140 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130765.1-130898.10" +attribute \src "libresoc.v:130561.1-130694.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" attribute \generator "nMigen" module \dec_oe$143 - attribute \src "libresoc.v:130766.7-130766.20" + attribute \src "libresoc.v:130562.7-130562.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130856.3-130876.6" + attribute \src "libresoc.v:130652.3-130672.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130877.3-130897.6" + attribute \src "libresoc.v:130673.3-130693.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130856.3-130876.6" + attribute \src "libresoc.v:130652.3-130672.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130877.3-130897.6" + attribute \src "libresoc.v:130673.3-130693.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130856.3-130876.6" + attribute \src "libresoc.v:130652.3-130672.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130877.3-130897.6" + attribute \src "libresoc.v:130673.3-130693.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \BRANCH_OE @@ -205028,7 +204824,7 @@ module \dec_oe$143 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \BRANCH_internal_op - attribute \src "libresoc.v:130766.7-130766.15" + attribute \src "libresoc.v:130562.7-130562.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe @@ -205040,22 +204836,22 @@ module \dec_oe$143 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:130766.7-130766.20" - process $proc$libresoc.v:130766$5040 + attribute \src "libresoc.v:130562.7-130562.20" + process $proc$libresoc.v:130562$5040 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130856.3-130876.6" - process $proc$libresoc.v:130856$5038 + attribute \src "libresoc.v:130652.3-130672.6" + process $proc$libresoc.v:130652$5038 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130857.5-130857.29" + attribute \src "libresoc.v:130653.5-130653.29" switch \initial - attribute \src "libresoc.v:130857.9-130857.17" + attribute \src "libresoc.v:130653.9-130653.17" case 1'1 case end @@ -205081,14 +204877,14 @@ module \dec_oe$143 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130877.3-130897.6" - process $proc$libresoc.v:130877$5039 + attribute \src "libresoc.v:130673.3-130693.6" + process $proc$libresoc.v:130673$5039 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130878.5-130878.29" + attribute \src "libresoc.v:130674.5-130674.29" switch \initial - attribute \src "libresoc.v:130878.9-130878.17" + attribute \src "libresoc.v:130674.9-130674.17" case 1'1 case end @@ -205115,24 +204911,24 @@ module \dec_oe$143 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130902.1-131037.10" +attribute \src "libresoc.v:130698.1-130833.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" attribute \generator "nMigen" module \dec_oe$147 - attribute \src "libresoc.v:130903.7-130903.20" + attribute \src "libresoc.v:130699.7-130699.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130995.3-131015.6" + attribute \src "libresoc.v:130791.3-130811.6" wire $0\oe[0:0] - attribute \src "libresoc.v:131016.3-131036.6" + attribute \src "libresoc.v:130812.3-130832.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130995.3-131015.6" + attribute \src "libresoc.v:130791.3-130811.6" wire $1\oe[0:0] - attribute \src "libresoc.v:131016.3-131036.6" + attribute \src "libresoc.v:130812.3-130832.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130995.3-131015.6" + attribute \src "libresoc.v:130791.3-130811.6" wire $2\oe[0:0] - attribute \src "libresoc.v:131016.3-131036.6" + attribute \src "libresoc.v:130812.3-130832.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LOGICAL_OE @@ -205213,7 +205009,7 @@ module \dec_oe$147 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LOGICAL_internal_op - attribute \src "libresoc.v:130903.7-130903.15" + attribute \src "libresoc.v:130699.7-130699.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe @@ -205225,22 +205021,22 @@ module \dec_oe$147 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130903.7-130903.20" - process $proc$libresoc.v:130903$5043 + attribute \src "libresoc.v:130699.7-130699.20" + process $proc$libresoc.v:130699$5043 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130995.3-131015.6" - process $proc$libresoc.v:130995$5041 + attribute \src "libresoc.v:130791.3-130811.6" + process $proc$libresoc.v:130791$5041 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130996.5-130996.29" + attribute \src "libresoc.v:130792.5-130792.29" switch \initial - attribute \src "libresoc.v:130996.9-130996.17" + attribute \src "libresoc.v:130792.9-130792.17" case 1'1 case end @@ -205266,14 +205062,14 @@ module \dec_oe$147 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:131016.3-131036.6" - process $proc$libresoc.v:131016$5042 + attribute \src "libresoc.v:130812.3-130832.6" + process $proc$libresoc.v:130812$5042 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:131017.5-131017.29" + attribute \src "libresoc.v:130813.5-130813.29" switch \initial - attribute \src "libresoc.v:131017.9-131017.17" + attribute \src "libresoc.v:130813.9-130813.17" case 1'1 case end @@ -205300,24 +205096,24 @@ module \dec_oe$147 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:131041.1-131174.10" +attribute \src "libresoc.v:130837.1-130970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" attribute \generator "nMigen" module \dec_oe$152 - attribute \src "libresoc.v:131042.7-131042.20" + attribute \src "libresoc.v:130838.7-130838.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131132.3-131152.6" + attribute \src "libresoc.v:130928.3-130948.6" wire $0\oe[0:0] - attribute \src "libresoc.v:131153.3-131173.6" + attribute \src "libresoc.v:130949.3-130969.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:131132.3-131152.6" + attribute \src "libresoc.v:130928.3-130948.6" wire $1\oe[0:0] - attribute \src "libresoc.v:131153.3-131173.6" + attribute \src "libresoc.v:130949.3-130969.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:131132.3-131152.6" + attribute \src "libresoc.v:130928.3-130948.6" wire $2\oe[0:0] - attribute \src "libresoc.v:131153.3-131173.6" + attribute \src "libresoc.v:130949.3-130969.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \SPR_OE @@ -205398,7 +205194,7 @@ module \dec_oe$152 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SPR_internal_op - attribute \src "libresoc.v:131042.7-131042.15" + attribute \src "libresoc.v:130838.7-130838.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe @@ -205410,22 +205206,22 @@ module \dec_oe$152 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:131042.7-131042.20" - process $proc$libresoc.v:131042$5046 + attribute \src "libresoc.v:130838.7-130838.20" + process $proc$libresoc.v:130838$5046 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131132.3-131152.6" - process $proc$libresoc.v:131132$5044 + attribute \src "libresoc.v:130928.3-130948.6" + process $proc$libresoc.v:130928$5044 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:131133.5-131133.29" + attribute \src "libresoc.v:130929.5-130929.29" switch \initial - attribute \src "libresoc.v:131133.9-131133.17" + attribute \src "libresoc.v:130929.9-130929.17" case 1'1 case end @@ -205451,14 +205247,14 @@ module \dec_oe$152 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:131153.3-131173.6" - process $proc$libresoc.v:131153$5045 + attribute \src "libresoc.v:130949.3-130969.6" + process $proc$libresoc.v:130949$5045 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:131154.5-131154.29" + attribute \src "libresoc.v:130950.5-130950.29" switch \initial - attribute \src "libresoc.v:131154.9-131154.17" + attribute \src "libresoc.v:130950.9-130950.17" case 1'1 case end @@ -205485,24 +205281,24 @@ module \dec_oe$152 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:131178.1-131313.10" +attribute \src "libresoc.v:130974.1-131109.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" attribute \generator "nMigen" module \dec_oe$155 - attribute \src "libresoc.v:131179.7-131179.20" + attribute \src "libresoc.v:130975.7-130975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131271.3-131291.6" + attribute \src "libresoc.v:131067.3-131087.6" wire $0\oe[0:0] - attribute \src "libresoc.v:131292.3-131312.6" + attribute \src "libresoc.v:131088.3-131108.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:131271.3-131291.6" + attribute \src "libresoc.v:131067.3-131087.6" wire $1\oe[0:0] - attribute \src "libresoc.v:131292.3-131312.6" + attribute \src "libresoc.v:131088.3-131108.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:131271.3-131291.6" + attribute \src "libresoc.v:131067.3-131087.6" wire $2\oe[0:0] - attribute \src "libresoc.v:131292.3-131312.6" + attribute \src "libresoc.v:131088.3-131108.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \DIV_OE @@ -205583,7 +205379,7 @@ module \dec_oe$155 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \DIV_internal_op - attribute \src "libresoc.v:131179.7-131179.15" + attribute \src "libresoc.v:130975.7-130975.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe @@ -205595,22 +205391,22 @@ module \dec_oe$155 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:131179.7-131179.20" - process $proc$libresoc.v:131179$5049 + attribute \src "libresoc.v:130975.7-130975.20" + process $proc$libresoc.v:130975$5049 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131271.3-131291.6" - process $proc$libresoc.v:131271$5047 + attribute \src "libresoc.v:131067.3-131087.6" + process $proc$libresoc.v:131067$5047 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:131272.5-131272.29" + attribute \src "libresoc.v:131068.5-131068.29" switch \initial - attribute \src "libresoc.v:131272.9-131272.17" + attribute \src "libresoc.v:131068.9-131068.17" case 1'1 case end @@ -205636,14 +205432,14 @@ module \dec_oe$155 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:131292.3-131312.6" - process $proc$libresoc.v:131292$5048 + attribute \src "libresoc.v:131088.3-131108.6" + process $proc$libresoc.v:131088$5048 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:131293.5-131293.29" + attribute \src "libresoc.v:131089.5-131089.29" switch \initial - attribute \src "libresoc.v:131293.9-131293.17" + attribute \src "libresoc.v:131089.9-131089.17" case 1'1 case end @@ -205670,24 +205466,24 @@ module \dec_oe$155 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:131317.1-131452.10" +attribute \src "libresoc.v:131113.1-131248.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" attribute \generator "nMigen" module \dec_oe$160 - attribute \src "libresoc.v:131318.7-131318.20" + attribute \src "libresoc.v:131114.7-131114.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131410.3-131430.6" + attribute \src "libresoc.v:131206.3-131226.6" wire $0\oe[0:0] - attribute \src "libresoc.v:131431.3-131451.6" + attribute \src "libresoc.v:131227.3-131247.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:131410.3-131430.6" + attribute \src "libresoc.v:131206.3-131226.6" wire $1\oe[0:0] - attribute \src "libresoc.v:131431.3-131451.6" + attribute \src "libresoc.v:131227.3-131247.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:131410.3-131430.6" + attribute \src "libresoc.v:131206.3-131226.6" wire $2\oe[0:0] - attribute \src "libresoc.v:131431.3-131451.6" + attribute \src "libresoc.v:131227.3-131247.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \MUL_OE @@ -205768,7 +205564,7 @@ module \dec_oe$160 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \MUL_internal_op - attribute \src "libresoc.v:131318.7-131318.15" + attribute \src "libresoc.v:131114.7-131114.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe @@ -205780,22 +205576,22 @@ module \dec_oe$160 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:131318.7-131318.20" - process $proc$libresoc.v:131318$5052 + attribute \src "libresoc.v:131114.7-131114.20" + process $proc$libresoc.v:131114$5052 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131410.3-131430.6" - process $proc$libresoc.v:131410$5050 + attribute \src "libresoc.v:131206.3-131226.6" + process $proc$libresoc.v:131206$5050 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:131411.5-131411.29" + attribute \src "libresoc.v:131207.5-131207.29" switch \initial - attribute \src "libresoc.v:131411.9-131411.17" + attribute \src "libresoc.v:131207.9-131207.17" case 1'1 case end @@ -205821,14 +205617,14 @@ module \dec_oe$160 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:131431.3-131451.6" - process $proc$libresoc.v:131431$5051 + attribute \src "libresoc.v:131227.3-131247.6" + process $proc$libresoc.v:131227$5051 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:131432.5-131432.29" + attribute \src "libresoc.v:131228.5-131228.29" switch \initial - attribute \src "libresoc.v:131432.9-131432.17" + attribute \src "libresoc.v:131228.9-131228.17" case 1'1 case end @@ -205855,24 +205651,24 @@ module \dec_oe$160 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:131456.1-131591.10" +attribute \src "libresoc.v:131252.1-131387.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" attribute \generator "nMigen" module \dec_oe$164 - attribute \src "libresoc.v:131457.7-131457.20" + attribute \src "libresoc.v:131253.7-131253.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131549.3-131569.6" + attribute \src "libresoc.v:131345.3-131365.6" wire $0\oe[0:0] - attribute \src "libresoc.v:131570.3-131590.6" + attribute \src "libresoc.v:131366.3-131386.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:131549.3-131569.6" + attribute \src "libresoc.v:131345.3-131365.6" wire $1\oe[0:0] - attribute \src "libresoc.v:131570.3-131590.6" + attribute \src "libresoc.v:131366.3-131386.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:131549.3-131569.6" + attribute \src "libresoc.v:131345.3-131365.6" wire $2\oe[0:0] - attribute \src "libresoc.v:131570.3-131590.6" + attribute \src "libresoc.v:131366.3-131386.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \SHIFT_ROT_OE @@ -205953,7 +205749,7 @@ module \dec_oe$164 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "libresoc.v:131457.7-131457.15" + attribute \src "libresoc.v:131253.7-131253.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe @@ -205965,22 +205761,22 @@ module \dec_oe$164 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:131457.7-131457.20" - process $proc$libresoc.v:131457$5055 + attribute \src "libresoc.v:131253.7-131253.20" + process $proc$libresoc.v:131253$5055 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131549.3-131569.6" - process $proc$libresoc.v:131549$5053 + attribute \src "libresoc.v:131345.3-131365.6" + process $proc$libresoc.v:131345$5053 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:131550.5-131550.29" + attribute \src "libresoc.v:131346.5-131346.29" switch \initial - attribute \src "libresoc.v:131550.9-131550.17" + attribute \src "libresoc.v:131346.9-131346.17" case 1'1 case end @@ -206006,14 +205802,14 @@ module \dec_oe$164 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:131570.3-131590.6" - process $proc$libresoc.v:131570$5054 + attribute \src "libresoc.v:131366.3-131386.6" + process $proc$libresoc.v:131366$5054 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:131571.5-131571.29" + attribute \src "libresoc.v:131367.5-131367.29" switch \initial - attribute \src "libresoc.v:131571.9-131571.17" + attribute \src "libresoc.v:131367.9-131367.17" case 1'1 case end @@ -206040,24 +205836,24 @@ module \dec_oe$164 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:131595.1-131730.10" +attribute \src "libresoc.v:131391.1-131526.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" attribute \generator "nMigen" module \dec_oe$168 - attribute \src "libresoc.v:131596.7-131596.20" + attribute \src "libresoc.v:131392.7-131392.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131688.3-131708.6" + attribute \src "libresoc.v:131484.3-131504.6" wire $0\oe[0:0] - attribute \src "libresoc.v:131709.3-131729.6" + attribute \src "libresoc.v:131505.3-131525.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:131688.3-131708.6" + attribute \src "libresoc.v:131484.3-131504.6" wire $1\oe[0:0] - attribute \src "libresoc.v:131709.3-131729.6" + attribute \src "libresoc.v:131505.3-131525.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:131688.3-131708.6" + attribute \src "libresoc.v:131484.3-131504.6" wire $2\oe[0:0] - attribute \src "libresoc.v:131709.3-131729.6" + attribute \src "libresoc.v:131505.3-131525.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LDST_OE @@ -206138,7 +205934,7 @@ module \dec_oe$168 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LDST_internal_op - attribute \src "libresoc.v:131596.7-131596.15" + attribute \src "libresoc.v:131392.7-131392.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe @@ -206150,22 +205946,22 @@ module \dec_oe$168 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:131596.7-131596.20" - process $proc$libresoc.v:131596$5058 + attribute \src "libresoc.v:131392.7-131392.20" + process $proc$libresoc.v:131392$5058 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131688.3-131708.6" - process $proc$libresoc.v:131688$5056 + attribute \src "libresoc.v:131484.3-131504.6" + process $proc$libresoc.v:131484$5056 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:131689.5-131689.29" + attribute \src "libresoc.v:131485.5-131485.29" switch \initial - attribute \src "libresoc.v:131689.9-131689.17" + attribute \src "libresoc.v:131485.9-131485.17" case 1'1 case end @@ -206191,14 +205987,14 @@ module \dec_oe$168 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:131709.3-131729.6" - process $proc$libresoc.v:131709$5057 + attribute \src "libresoc.v:131505.3-131525.6" + process $proc$libresoc.v:131505$5057 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:131710.5-131710.29" + attribute \src "libresoc.v:131506.5-131506.29" switch \initial - attribute \src "libresoc.v:131710.9-131710.17" + attribute \src "libresoc.v:131506.9-131506.17" case 1'1 case end @@ -206225,28 +206021,28 @@ module \dec_oe$168 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:131734.1-131869.10" +attribute \src "libresoc.v:131530.1-131665.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" attribute \generator "nMigen" module \dec_oe$173 - attribute \src "libresoc.v:131735.7-131735.20" + attribute \src "libresoc.v:131531.7-131531.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131827.3-131847.6" + attribute \src "libresoc.v:131623.3-131643.6" wire $0\oe[0:0] - attribute \src "libresoc.v:131848.3-131868.6" + attribute \src "libresoc.v:131644.3-131664.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:131827.3-131847.6" + attribute \src "libresoc.v:131623.3-131643.6" wire $1\oe[0:0] - attribute \src "libresoc.v:131848.3-131868.6" + attribute \src "libresoc.v:131644.3-131664.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:131827.3-131847.6" + attribute \src "libresoc.v:131623.3-131643.6" wire $2\oe[0:0] - attribute \src "libresoc.v:131848.3-131868.6" + attribute \src "libresoc.v:131644.3-131664.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \OE - attribute \src "libresoc.v:131735.7-131735.15" + attribute \src "libresoc.v:131531.7-131531.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -206335,22 +206131,22 @@ module \dec_oe$173 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:131735.7-131735.20" - process $proc$libresoc.v:131735$5061 + attribute \src "libresoc.v:131531.7-131531.20" + process $proc$libresoc.v:131531$5061 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131827.3-131847.6" - process $proc$libresoc.v:131827$5059 + attribute \src "libresoc.v:131623.3-131643.6" + process $proc$libresoc.v:131623$5059 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:131828.5-131828.29" + attribute \src "libresoc.v:131624.5-131624.29" switch \initial - attribute \src "libresoc.v:131828.9-131828.17" + attribute \src "libresoc.v:131624.9-131624.17" case 1'1 case end @@ -206376,14 +206172,14 @@ module \dec_oe$173 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:131848.3-131868.6" - process $proc$libresoc.v:131848$5060 + attribute \src "libresoc.v:131644.3-131664.6" + process $proc$libresoc.v:131644$5060 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:131849.5-131849.29" + attribute \src "libresoc.v:131645.5-131645.29" switch \initial - attribute \src "libresoc.v:131849.9-131849.17" + attribute \src "libresoc.v:131645.9-131645.17" case 1'1 case end @@ -206410,24 +206206,24 @@ module \dec_oe$173 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:131873.1-131927.10" +attribute \src "libresoc.v:131669.1-131723.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" attribute \generator "nMigen" module \dec_rc - attribute \src "libresoc.v:131874.7-131874.20" + attribute \src "libresoc.v:131670.7-131670.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131889.3-131907.6" + attribute \src "libresoc.v:131685.3-131703.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131908.3-131926.6" + attribute \src "libresoc.v:131704.3-131722.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131889.3-131907.6" + attribute \src "libresoc.v:131685.3-131703.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131908.3-131926.6" + attribute \src "libresoc.v:131704.3-131722.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \ALU_Rc - attribute \src "libresoc.v:131874.7-131874.15" + attribute \src "libresoc.v:131670.7-131670.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc @@ -206439,22 +206235,22 @@ module \dec_rc attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131874.7-131874.20" - process $proc$libresoc.v:131874$5064 + attribute \src "libresoc.v:131670.7-131670.20" + process $proc$libresoc.v:131670$5064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131889.3-131907.6" - process $proc$libresoc.v:131889$5062 + attribute \src "libresoc.v:131685.3-131703.6" + process $proc$libresoc.v:131685$5062 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131890.5-131890.29" + attribute \src "libresoc.v:131686.5-131686.29" switch \initial - attribute \src "libresoc.v:131890.9-131890.17" + attribute \src "libresoc.v:131686.9-131686.17" case 1'1 case end @@ -206478,14 +206274,14 @@ module \dec_rc sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131908.3-131926.6" - process $proc$libresoc.v:131908$5063 + attribute \src "libresoc.v:131704.3-131722.6" + process $proc$libresoc.v:131704$5063 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131909.5-131909.29" + attribute \src "libresoc.v:131705.5-131705.29" switch \initial - attribute \src "libresoc.v:131909.9-131909.17" + attribute \src "libresoc.v:131705.9-131705.17" case 1'1 case end @@ -206510,24 +206306,24 @@ module \dec_rc update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131931.1-131983.10" +attribute \src "libresoc.v:131727.1-131779.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" attribute \generator "nMigen" module \dec_rc$139 - attribute \src "libresoc.v:131932.7-131932.20" + attribute \src "libresoc.v:131728.7-131728.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131945.3-131963.6" + attribute \src "libresoc.v:131741.3-131759.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131964.3-131982.6" + attribute \src "libresoc.v:131760.3-131778.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131945.3-131963.6" + attribute \src "libresoc.v:131741.3-131759.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131964.3-131982.6" + attribute \src "libresoc.v:131760.3-131778.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \CR_Rc - attribute \src "libresoc.v:131932.7-131932.15" + attribute \src "libresoc.v:131728.7-131728.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc @@ -206539,22 +206335,22 @@ module \dec_rc$139 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:131932.7-131932.20" - process $proc$libresoc.v:131932$5067 + attribute \src "libresoc.v:131728.7-131728.20" + process $proc$libresoc.v:131728$5067 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131945.3-131963.6" - process $proc$libresoc.v:131945$5065 + attribute \src "libresoc.v:131741.3-131759.6" + process $proc$libresoc.v:131741$5065 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131946.5-131946.29" + attribute \src "libresoc.v:131742.5-131742.29" switch \initial - attribute \src "libresoc.v:131946.9-131946.17" + attribute \src "libresoc.v:131742.9-131742.17" case 1'1 case end @@ -206578,14 +206374,14 @@ module \dec_rc$139 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131964.3-131982.6" - process $proc$libresoc.v:131964$5066 + attribute \src "libresoc.v:131760.3-131778.6" + process $proc$libresoc.v:131760$5066 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131965.5-131965.29" + attribute \src "libresoc.v:131761.5-131761.29" switch \initial - attribute \src "libresoc.v:131965.9-131965.17" + attribute \src "libresoc.v:131761.9-131761.17" case 1'1 case end @@ -206610,24 +206406,24 @@ module \dec_rc$139 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131987.1-132039.10" +attribute \src "libresoc.v:131783.1-131835.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" attribute \generator "nMigen" module \dec_rc$142 - attribute \src "libresoc.v:131988.7-131988.20" + attribute \src "libresoc.v:131784.7-131784.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132001.3-132019.6" + attribute \src "libresoc.v:131797.3-131815.6" wire $0\rc[0:0] - attribute \src "libresoc.v:132020.3-132038.6" + attribute \src "libresoc.v:131816.3-131834.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:132001.3-132019.6" + attribute \src "libresoc.v:131797.3-131815.6" wire $1\rc[0:0] - attribute \src "libresoc.v:132020.3-132038.6" + attribute \src "libresoc.v:131816.3-131834.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \BRANCH_Rc - attribute \src "libresoc.v:131988.7-131988.15" + attribute \src "libresoc.v:131784.7-131784.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc @@ -206639,22 +206435,22 @@ module \dec_rc$142 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:131988.7-131988.20" - process $proc$libresoc.v:131988$5070 + attribute \src "libresoc.v:131784.7-131784.20" + process $proc$libresoc.v:131784$5070 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132001.3-132019.6" - process $proc$libresoc.v:132001$5068 + attribute \src "libresoc.v:131797.3-131815.6" + process $proc$libresoc.v:131797$5068 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:132002.5-132002.29" + attribute \src "libresoc.v:131798.5-131798.29" switch \initial - attribute \src "libresoc.v:132002.9-132002.17" + attribute \src "libresoc.v:131798.9-131798.17" case 1'1 case end @@ -206678,14 +206474,14 @@ module \dec_rc$142 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:132020.3-132038.6" - process $proc$libresoc.v:132020$5069 + attribute \src "libresoc.v:131816.3-131834.6" + process $proc$libresoc.v:131816$5069 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:132021.5-132021.29" + attribute \src "libresoc.v:131817.5-131817.29" switch \initial - attribute \src "libresoc.v:132021.9-132021.17" + attribute \src "libresoc.v:131817.9-131817.17" case 1'1 case end @@ -206710,24 +206506,24 @@ module \dec_rc$142 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:132043.1-132097.10" +attribute \src "libresoc.v:131839.1-131893.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" attribute \generator "nMigen" module \dec_rc$146 - attribute \src "libresoc.v:132044.7-132044.20" + attribute \src "libresoc.v:131840.7-131840.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132059.3-132077.6" + attribute \src "libresoc.v:131855.3-131873.6" wire $0\rc[0:0] - attribute \src "libresoc.v:132078.3-132096.6" + attribute \src "libresoc.v:131874.3-131892.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:132059.3-132077.6" + attribute \src "libresoc.v:131855.3-131873.6" wire $1\rc[0:0] - attribute \src "libresoc.v:132078.3-132096.6" + attribute \src "libresoc.v:131874.3-131892.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LOGICAL_Rc - attribute \src "libresoc.v:132044.7-132044.15" + attribute \src "libresoc.v:131840.7-131840.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc @@ -206739,22 +206535,22 @@ module \dec_rc$146 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:132044.7-132044.20" - process $proc$libresoc.v:132044$5073 + attribute \src "libresoc.v:131840.7-131840.20" + process $proc$libresoc.v:131840$5073 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132059.3-132077.6" - process $proc$libresoc.v:132059$5071 + attribute \src "libresoc.v:131855.3-131873.6" + process $proc$libresoc.v:131855$5071 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:132060.5-132060.29" + attribute \src "libresoc.v:131856.5-131856.29" switch \initial - attribute \src "libresoc.v:132060.9-132060.17" + attribute \src "libresoc.v:131856.9-131856.17" case 1'1 case end @@ -206778,14 +206574,14 @@ module \dec_rc$146 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:132078.3-132096.6" - process $proc$libresoc.v:132078$5072 + attribute \src "libresoc.v:131874.3-131892.6" + process $proc$libresoc.v:131874$5072 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:132079.5-132079.29" + attribute \src "libresoc.v:131875.5-131875.29" switch \initial - attribute \src "libresoc.v:132079.9-132079.17" + attribute \src "libresoc.v:131875.9-131875.17" case 1'1 case end @@ -206810,24 +206606,24 @@ module \dec_rc$146 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:132101.1-132153.10" +attribute \src "libresoc.v:131897.1-131949.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" attribute \generator "nMigen" module \dec_rc$151 - attribute \src "libresoc.v:132102.7-132102.20" + attribute \src "libresoc.v:131898.7-131898.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132115.3-132133.6" + attribute \src "libresoc.v:131911.3-131929.6" wire $0\rc[0:0] - attribute \src "libresoc.v:132134.3-132152.6" + attribute \src "libresoc.v:131930.3-131948.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:132115.3-132133.6" + attribute \src "libresoc.v:131911.3-131929.6" wire $1\rc[0:0] - attribute \src "libresoc.v:132134.3-132152.6" + attribute \src "libresoc.v:131930.3-131948.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \SPR_Rc - attribute \src "libresoc.v:132102.7-132102.15" + attribute \src "libresoc.v:131898.7-131898.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc @@ -206839,22 +206635,22 @@ module \dec_rc$151 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:132102.7-132102.20" - process $proc$libresoc.v:132102$5076 + attribute \src "libresoc.v:131898.7-131898.20" + process $proc$libresoc.v:131898$5076 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132115.3-132133.6" - process $proc$libresoc.v:132115$5074 + attribute \src "libresoc.v:131911.3-131929.6" + process $proc$libresoc.v:131911$5074 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:132116.5-132116.29" + attribute \src "libresoc.v:131912.5-131912.29" switch \initial - attribute \src "libresoc.v:132116.9-132116.17" + attribute \src "libresoc.v:131912.9-131912.17" case 1'1 case end @@ -206878,14 +206674,14 @@ module \dec_rc$151 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:132134.3-132152.6" - process $proc$libresoc.v:132134$5075 + attribute \src "libresoc.v:131930.3-131948.6" + process $proc$libresoc.v:131930$5075 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:132135.5-132135.29" + attribute \src "libresoc.v:131931.5-131931.29" switch \initial - attribute \src "libresoc.v:132135.9-132135.17" + attribute \src "libresoc.v:131931.9-131931.17" case 1'1 case end @@ -206910,24 +206706,24 @@ module \dec_rc$151 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:132157.1-132211.10" +attribute \src "libresoc.v:131953.1-132007.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" attribute \generator "nMigen" module \dec_rc$154 - attribute \src "libresoc.v:132158.7-132158.20" + attribute \src "libresoc.v:131954.7-131954.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132173.3-132191.6" + attribute \src "libresoc.v:131969.3-131987.6" wire $0\rc[0:0] - attribute \src "libresoc.v:132192.3-132210.6" + attribute \src "libresoc.v:131988.3-132006.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:132173.3-132191.6" + attribute \src "libresoc.v:131969.3-131987.6" wire $1\rc[0:0] - attribute \src "libresoc.v:132192.3-132210.6" + attribute \src "libresoc.v:131988.3-132006.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \DIV_Rc - attribute \src "libresoc.v:132158.7-132158.15" + attribute \src "libresoc.v:131954.7-131954.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc @@ -206939,22 +206735,22 @@ module \dec_rc$154 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:132158.7-132158.20" - process $proc$libresoc.v:132158$5079 + attribute \src "libresoc.v:131954.7-131954.20" + process $proc$libresoc.v:131954$5079 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132173.3-132191.6" - process $proc$libresoc.v:132173$5077 + attribute \src "libresoc.v:131969.3-131987.6" + process $proc$libresoc.v:131969$5077 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:132174.5-132174.29" + attribute \src "libresoc.v:131970.5-131970.29" switch \initial - attribute \src "libresoc.v:132174.9-132174.17" + attribute \src "libresoc.v:131970.9-131970.17" case 1'1 case end @@ -206978,14 +206774,14 @@ module \dec_rc$154 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:132192.3-132210.6" - process $proc$libresoc.v:132192$5078 + attribute \src "libresoc.v:131988.3-132006.6" + process $proc$libresoc.v:131988$5078 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:132193.5-132193.29" + attribute \src "libresoc.v:131989.5-131989.29" switch \initial - attribute \src "libresoc.v:132193.9-132193.17" + attribute \src "libresoc.v:131989.9-131989.17" case 1'1 case end @@ -207010,24 +206806,24 @@ module \dec_rc$154 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:132215.1-132269.10" +attribute \src "libresoc.v:132011.1-132065.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" attribute \generator "nMigen" module \dec_rc$159 - attribute \src "libresoc.v:132216.7-132216.20" + attribute \src "libresoc.v:132012.7-132012.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132231.3-132249.6" + attribute \src "libresoc.v:132027.3-132045.6" wire $0\rc[0:0] - attribute \src "libresoc.v:132250.3-132268.6" + attribute \src "libresoc.v:132046.3-132064.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:132231.3-132249.6" + attribute \src "libresoc.v:132027.3-132045.6" wire $1\rc[0:0] - attribute \src "libresoc.v:132250.3-132268.6" + attribute \src "libresoc.v:132046.3-132064.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \MUL_Rc - attribute \src "libresoc.v:132216.7-132216.15" + attribute \src "libresoc.v:132012.7-132012.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc @@ -207039,22 +206835,22 @@ module \dec_rc$159 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:132216.7-132216.20" - process $proc$libresoc.v:132216$5082 + attribute \src "libresoc.v:132012.7-132012.20" + process $proc$libresoc.v:132012$5082 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132231.3-132249.6" - process $proc$libresoc.v:132231$5080 + attribute \src "libresoc.v:132027.3-132045.6" + process $proc$libresoc.v:132027$5080 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:132232.5-132232.29" + attribute \src "libresoc.v:132028.5-132028.29" switch \initial - attribute \src "libresoc.v:132232.9-132232.17" + attribute \src "libresoc.v:132028.9-132028.17" case 1'1 case end @@ -207078,14 +206874,14 @@ module \dec_rc$159 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:132250.3-132268.6" - process $proc$libresoc.v:132250$5081 + attribute \src "libresoc.v:132046.3-132064.6" + process $proc$libresoc.v:132046$5081 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:132251.5-132251.29" + attribute \src "libresoc.v:132047.5-132047.29" switch \initial - attribute \src "libresoc.v:132251.9-132251.17" + attribute \src "libresoc.v:132047.9-132047.17" case 1'1 case end @@ -207110,24 +206906,24 @@ module \dec_rc$159 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:132273.1-132327.10" +attribute \src "libresoc.v:132069.1-132123.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" attribute \generator "nMigen" module \dec_rc$163 - attribute \src "libresoc.v:132274.7-132274.20" + attribute \src "libresoc.v:132070.7-132070.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132289.3-132307.6" + attribute \src "libresoc.v:132085.3-132103.6" wire $0\rc[0:0] - attribute \src "libresoc.v:132308.3-132326.6" + attribute \src "libresoc.v:132104.3-132122.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:132289.3-132307.6" + attribute \src "libresoc.v:132085.3-132103.6" wire $1\rc[0:0] - attribute \src "libresoc.v:132308.3-132326.6" + attribute \src "libresoc.v:132104.3-132122.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \SHIFT_ROT_Rc - attribute \src "libresoc.v:132274.7-132274.15" + attribute \src "libresoc.v:132070.7-132070.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc @@ -207139,22 +206935,22 @@ module \dec_rc$163 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:132274.7-132274.20" - process $proc$libresoc.v:132274$5085 + attribute \src "libresoc.v:132070.7-132070.20" + process $proc$libresoc.v:132070$5085 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132289.3-132307.6" - process $proc$libresoc.v:132289$5083 + attribute \src "libresoc.v:132085.3-132103.6" + process $proc$libresoc.v:132085$5083 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:132290.5-132290.29" + attribute \src "libresoc.v:132086.5-132086.29" switch \initial - attribute \src "libresoc.v:132290.9-132290.17" + attribute \src "libresoc.v:132086.9-132086.17" case 1'1 case end @@ -207178,14 +206974,14 @@ module \dec_rc$163 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:132308.3-132326.6" - process $proc$libresoc.v:132308$5084 + attribute \src "libresoc.v:132104.3-132122.6" + process $proc$libresoc.v:132104$5084 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:132309.5-132309.29" + attribute \src "libresoc.v:132105.5-132105.29" switch \initial - attribute \src "libresoc.v:132309.9-132309.17" + attribute \src "libresoc.v:132105.9-132105.17" case 1'1 case end @@ -207210,24 +207006,24 @@ module \dec_rc$163 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:132331.1-132385.10" +attribute \src "libresoc.v:132127.1-132181.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" attribute \generator "nMigen" module \dec_rc$167 - attribute \src "libresoc.v:132332.7-132332.20" + attribute \src "libresoc.v:132128.7-132128.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132347.3-132365.6" + attribute \src "libresoc.v:132143.3-132161.6" wire $0\rc[0:0] - attribute \src "libresoc.v:132366.3-132384.6" + attribute \src "libresoc.v:132162.3-132180.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:132347.3-132365.6" + attribute \src "libresoc.v:132143.3-132161.6" wire $1\rc[0:0] - attribute \src "libresoc.v:132366.3-132384.6" + attribute \src "libresoc.v:132162.3-132180.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LDST_Rc - attribute \src "libresoc.v:132332.7-132332.15" + attribute \src "libresoc.v:132128.7-132128.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc @@ -207239,22 +207035,22 @@ module \dec_rc$167 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:132332.7-132332.20" - process $proc$libresoc.v:132332$5088 + attribute \src "libresoc.v:132128.7-132128.20" + process $proc$libresoc.v:132128$5088 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132347.3-132365.6" - process $proc$libresoc.v:132347$5086 + attribute \src "libresoc.v:132143.3-132161.6" + process $proc$libresoc.v:132143$5086 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:132348.5-132348.29" + attribute \src "libresoc.v:132144.5-132144.29" switch \initial - attribute \src "libresoc.v:132348.9-132348.17" + attribute \src "libresoc.v:132144.9-132144.17" case 1'1 case end @@ -207278,14 +207074,14 @@ module \dec_rc$167 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:132366.3-132384.6" - process $proc$libresoc.v:132366$5087 + attribute \src "libresoc.v:132162.3-132180.6" + process $proc$libresoc.v:132162$5087 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:132367.5-132367.29" + attribute \src "libresoc.v:132163.5-132163.29" switch \initial - attribute \src "libresoc.v:132367.9-132367.17" + attribute \src "libresoc.v:132163.9-132163.17" case 1'1 case end @@ -207310,24 +207106,24 @@ module \dec_rc$167 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:132389.1-132443.10" +attribute \src "libresoc.v:132185.1-132239.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" attribute \generator "nMigen" module \dec_rc$172 - attribute \src "libresoc.v:132390.7-132390.20" + attribute \src "libresoc.v:132186.7-132186.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132405.3-132423.6" + attribute \src "libresoc.v:132201.3-132219.6" wire $0\rc[0:0] - attribute \src "libresoc.v:132424.3-132442.6" + attribute \src "libresoc.v:132220.3-132238.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:132405.3-132423.6" + attribute \src "libresoc.v:132201.3-132219.6" wire $1\rc[0:0] - attribute \src "libresoc.v:132424.3-132442.6" + attribute \src "libresoc.v:132220.3-132238.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \Rc - attribute \src "libresoc.v:132390.7-132390.15" + attribute \src "libresoc.v:132186.7-132186.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc @@ -207339,22 +207135,22 @@ module \dec_rc$172 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:132390.7-132390.20" - process $proc$libresoc.v:132390$5091 + attribute \src "libresoc.v:132186.7-132186.20" + process $proc$libresoc.v:132186$5091 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132405.3-132423.6" - process $proc$libresoc.v:132405$5089 + attribute \src "libresoc.v:132201.3-132219.6" + process $proc$libresoc.v:132201$5089 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:132406.5-132406.29" + attribute \src "libresoc.v:132202.5-132202.29" switch \initial - attribute \src "libresoc.v:132406.9-132406.17" + attribute \src "libresoc.v:132202.9-132202.17" case 1'1 case end @@ -207378,14 +207174,14 @@ module \dec_rc$172 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:132424.3-132442.6" - process $proc$libresoc.v:132424$5090 + attribute \src "libresoc.v:132220.3-132238.6" + process $proc$libresoc.v:132220$5090 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:132425.5-132425.29" + attribute \src "libresoc.v:132221.5-132221.29" switch \initial - attribute \src "libresoc.v:132425.9-132425.17" + attribute \src "libresoc.v:132221.9-132221.17" case 1'1 case end @@ -207410,539 +207206,539 @@ module \dec_rc$172 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:132447.1-133691.10" +attribute \src "libresoc.v:132243.1-133487.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" attribute \generator "nMigen" module \div0 - attribute \src "libresoc.v:133248.3-133249.25" + attribute \src "libresoc.v:133044.3-133045.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5231 - attribute \src "libresoc.v:133220.3-133221.75" + attribute \src "libresoc.v:133016.3-133017.75" wire width 4 $0\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5232 - attribute \src "libresoc.v:133190.3-133191.73" + attribute \src "libresoc.v:132986.3-132987.73" wire width 14 $0\alu_div0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5233 - attribute \src "libresoc.v:133192.3-133193.87" + attribute \src "libresoc.v:132988.3-132989.87" wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5234 - attribute \src "libresoc.v:133194.3-133195.83" + attribute \src "libresoc.v:132990.3-132991.83" wire $0\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5235 - attribute \src "libresoc.v:133208.3-133209.81" + attribute \src "libresoc.v:133004.3-133005.81" wire width 2 $0\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5236 - attribute \src "libresoc.v:133222.3-133223.67" + attribute \src "libresoc.v:133018.3-133019.67" wire width 32 $0\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5237 - attribute \src "libresoc.v:133188.3-133189.77" + attribute \src "libresoc.v:132984.3-132985.77" wire width 7 $0\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__invert_in$next[0:0]$5238 - attribute \src "libresoc.v:133204.3-133205.77" + attribute \src "libresoc.v:133000.3-133001.77" wire $0\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__invert_out$next[0:0]$5239 - attribute \src "libresoc.v:133210.3-133211.79" + attribute \src "libresoc.v:133006.3-133007.79" wire $0\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5240 - attribute \src "libresoc.v:133216.3-133217.75" + attribute \src "libresoc.v:133012.3-133013.75" wire $0\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__is_signed$next[0:0]$5241 - attribute \src "libresoc.v:133218.3-133219.77" + attribute \src "libresoc.v:133014.3-133015.77" wire $0\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5242 - attribute \src "libresoc.v:133200.3-133201.71" + attribute \src "libresoc.v:132996.3-132997.71" wire $0\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5243 - attribute \src "libresoc.v:133202.3-133203.71" + attribute \src "libresoc.v:132998.3-132999.71" wire $0\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__output_carry$next[0:0]$5244 - attribute \src "libresoc.v:133214.3-133215.83" + attribute \src "libresoc.v:133010.3-133011.83" wire $0\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5245 - attribute \src "libresoc.v:133198.3-133199.71" + attribute \src "libresoc.v:132994.3-132995.71" wire $0\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5246 - attribute \src "libresoc.v:133196.3-133197.71" + attribute \src "libresoc.v:132992.3-132993.71" wire $0\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5247 - attribute \src "libresoc.v:133212.3-133213.77" + attribute \src "libresoc.v:133008.3-133009.77" wire $0\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__zero_a$next[0:0]$5248 - attribute \src "libresoc.v:133206.3-133207.71" + attribute \src "libresoc.v:133002.3-133003.71" wire $0\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:133246.3-133247.40" + attribute \src "libresoc.v:133042.3-133043.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:133601.3-133609.6" + attribute \src "libresoc.v:133397.3-133405.6" wire $0\alu_l_r_alu$next[0:0]$5318 - attribute \src "libresoc.v:133162.3-133163.39" + attribute \src "libresoc.v:132958.3-132959.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:133592.3-133600.6" + attribute \src "libresoc.v:133388.3-133396.6" wire $0\alui_l_r_alui$next[0:0]$5315 - attribute \src "libresoc.v:133164.3-133165.43" + attribute \src "libresoc.v:132960.3-132961.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:133474.3-133495.6" + attribute \src "libresoc.v:133270.3-133291.6" wire width 64 $0\data_r0__o$next[63:0]$5274 - attribute \src "libresoc.v:133184.3-133185.37" + attribute \src "libresoc.v:132980.3-132981.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:133474.3-133495.6" + attribute \src "libresoc.v:133270.3-133291.6" wire $0\data_r0__o_ok$next[0:0]$5275 - attribute \src "libresoc.v:133186.3-133187.43" + attribute \src "libresoc.v:132982.3-132983.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:133496.3-133517.6" + attribute \src "libresoc.v:133292.3-133313.6" wire width 4 $0\data_r1__cr_a$next[3:0]$5282 - attribute \src "libresoc.v:133180.3-133181.43" + attribute \src "libresoc.v:132976.3-132977.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:133496.3-133517.6" + attribute \src "libresoc.v:133292.3-133313.6" wire $0\data_r1__cr_a_ok$next[0:0]$5283 - attribute \src "libresoc.v:133182.3-133183.49" + attribute \src "libresoc.v:132978.3-132979.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:133518.3-133539.6" + attribute \src "libresoc.v:133314.3-133335.6" wire width 2 $0\data_r2__xer_ov$next[1:0]$5290 - attribute \src "libresoc.v:133176.3-133177.47" + attribute \src "libresoc.v:132972.3-132973.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:133518.3-133539.6" + attribute \src "libresoc.v:133314.3-133335.6" wire $0\data_r2__xer_ov_ok$next[0:0]$5291 - attribute \src "libresoc.v:133178.3-133179.53" + attribute \src "libresoc.v:132974.3-132975.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:133540.3-133561.6" + attribute \src "libresoc.v:133336.3-133357.6" wire $0\data_r3__xer_so$next[0:0]$5298 - attribute \src "libresoc.v:133172.3-133173.47" + attribute \src "libresoc.v:132968.3-132969.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:133540.3-133561.6" + attribute \src "libresoc.v:133336.3-133357.6" wire $0\data_r3__xer_so_ok$next[0:0]$5299 - attribute \src "libresoc.v:133174.3-133175.53" + attribute \src "libresoc.v:132970.3-132971.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:133610.3-133619.6" + attribute \src "libresoc.v:133406.3-133415.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:133620.3-133629.6" + attribute \src "libresoc.v:133416.3-133425.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:133630.3-133639.6" + attribute \src "libresoc.v:133426.3-133435.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:133640.3-133649.6" + attribute \src "libresoc.v:133436.3-133445.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:132448.7-132448.20" + attribute \src "libresoc.v:132244.7-132244.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133390.3-133398.6" + attribute \src "libresoc.v:133186.3-133194.6" wire $0\opc_l_r_opc$next[0:0]$5216 - attribute \src "libresoc.v:133232.3-133233.39" + attribute \src "libresoc.v:133028.3-133029.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:133381.3-133389.6" + attribute \src "libresoc.v:133177.3-133185.6" wire $0\opc_l_s_opc$next[0:0]$5213 - attribute \src "libresoc.v:133234.3-133235.39" + attribute \src "libresoc.v:133030.3-133031.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:133650.3-133658.6" + attribute \src "libresoc.v:133446.3-133454.6" wire width 4 $0\prev_wr_go$next[3:0]$5325 - attribute \src "libresoc.v:133244.3-133245.37" + attribute \src "libresoc.v:133040.3-133041.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:133335.3-133344.6" + attribute \src "libresoc.v:133131.3-133140.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:133426.3-133434.6" + attribute \src "libresoc.v:133222.3-133230.6" wire width 4 $0\req_l_r_req$next[3:0]$5228 - attribute \src "libresoc.v:133224.3-133225.39" + attribute \src "libresoc.v:133020.3-133021.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:133417.3-133425.6" + attribute \src "libresoc.v:133213.3-133221.6" wire width 4 $0\req_l_s_req$next[3:0]$5225 - attribute \src "libresoc.v:133226.3-133227.39" + attribute \src "libresoc.v:133022.3-133023.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:133354.3-133362.6" + attribute \src "libresoc.v:133150.3-133158.6" wire $0\rok_l_r_rdok$next[0:0]$5204 - attribute \src "libresoc.v:133240.3-133241.41" + attribute \src "libresoc.v:133036.3-133037.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:133345.3-133353.6" + attribute \src "libresoc.v:133141.3-133149.6" wire $0\rok_l_s_rdok$next[0:0]$5201 - attribute \src "libresoc.v:133242.3-133243.41" + attribute \src "libresoc.v:133038.3-133039.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:133372.3-133380.6" + attribute \src "libresoc.v:133168.3-133176.6" wire $0\rst_l_r_rst$next[0:0]$5210 - attribute \src "libresoc.v:133236.3-133237.39" + attribute \src "libresoc.v:133032.3-133033.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:133363.3-133371.6" + attribute \src "libresoc.v:133159.3-133167.6" wire $0\rst_l_s_rst$next[0:0]$5207 - attribute \src "libresoc.v:133238.3-133239.39" + attribute \src "libresoc.v:133034.3-133035.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:133408.3-133416.6" + attribute \src "libresoc.v:133204.3-133212.6" wire width 3 $0\src_l_r_src$next[2:0]$5222 - attribute \src "libresoc.v:133228.3-133229.39" + attribute \src "libresoc.v:133024.3-133025.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:133399.3-133407.6" + attribute \src "libresoc.v:133195.3-133203.6" wire width 3 $0\src_l_s_src$next[2:0]$5219 - attribute \src "libresoc.v:133230.3-133231.39" + attribute \src "libresoc.v:133026.3-133027.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:133562.3-133571.6" + attribute \src "libresoc.v:133358.3-133367.6" wire width 64 $0\src_r0$next[63:0]$5306 - attribute \src "libresoc.v:133170.3-133171.29" + attribute \src "libresoc.v:132966.3-132967.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:133572.3-133581.6" + attribute \src "libresoc.v:133368.3-133377.6" wire width 64 $0\src_r1$next[63:0]$5309 - attribute \src "libresoc.v:133168.3-133169.29" + attribute \src "libresoc.v:132964.3-132965.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:133582.3-133591.6" + attribute \src "libresoc.v:133378.3-133387.6" wire $0\src_r2$next[0:0]$5312 - attribute \src "libresoc.v:133166.3-133167.29" + attribute \src "libresoc.v:132962.3-132963.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:132578.7-132578.24" + attribute \src "libresoc.v:132374.7-132374.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5249 - attribute \src "libresoc.v:132588.13-132588.49" + attribute \src "libresoc.v:132384.13-132384.49" wire width 4 $1\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5250 - attribute \src "libresoc.v:132607.14-132607.53" + attribute \src "libresoc.v:132403.14-132403.53" wire width 14 $1\alu_div0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251 - attribute \src "libresoc.v:132611.14-132611.72" + attribute \src "libresoc.v:132407.14-132407.72" wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252 - attribute \src "libresoc.v:132615.7-132615.47" + attribute \src "libresoc.v:132411.7-132411.47" wire $1\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5253 - attribute \src "libresoc.v:132623.13-132623.52" + attribute \src "libresoc.v:132419.13-132419.52" wire width 2 $1\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5254 - attribute \src "libresoc.v:132627.14-132627.47" + attribute \src "libresoc.v:132423.14-132423.47" wire width 32 $1\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5255 - attribute \src "libresoc.v:132706.13-132706.51" + attribute \src "libresoc.v:132502.13-132502.51" wire width 7 $1\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__invert_in$next[0:0]$5256 - attribute \src "libresoc.v:132710.7-132710.44" + attribute \src "libresoc.v:132506.7-132506.44" wire $1\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__invert_out$next[0:0]$5257 - attribute \src "libresoc.v:132714.7-132714.45" + attribute \src "libresoc.v:132510.7-132510.45" wire $1\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5258 - attribute \src "libresoc.v:132718.7-132718.43" + attribute \src "libresoc.v:132514.7-132514.43" wire $1\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__is_signed$next[0:0]$5259 - attribute \src "libresoc.v:132722.7-132722.44" + attribute \src "libresoc.v:132518.7-132518.44" wire $1\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5260 - attribute \src "libresoc.v:132726.7-132726.41" + attribute \src "libresoc.v:132522.7-132522.41" wire $1\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5261 - attribute \src "libresoc.v:132730.7-132730.41" + attribute \src "libresoc.v:132526.7-132526.41" wire $1\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__output_carry$next[0:0]$5262 - attribute \src "libresoc.v:132734.7-132734.47" + attribute \src "libresoc.v:132530.7-132530.47" wire $1\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5263 - attribute \src "libresoc.v:132738.7-132738.41" + attribute \src "libresoc.v:132534.7-132534.41" wire $1\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5264 - attribute \src "libresoc.v:132742.7-132742.41" + attribute \src "libresoc.v:132538.7-132538.41" wire $1\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5265 - attribute \src "libresoc.v:132746.7-132746.44" + attribute \src "libresoc.v:132542.7-132542.44" wire $1\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__zero_a$next[0:0]$5266 - attribute \src "libresoc.v:132750.7-132750.41" + attribute \src "libresoc.v:132546.7-132546.41" wire $1\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:132776.7-132776.26" + attribute \src "libresoc.v:132572.7-132572.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:133601.3-133609.6" + attribute \src "libresoc.v:133397.3-133405.6" wire $1\alu_l_r_alu$next[0:0]$5319 - attribute \src "libresoc.v:132784.7-132784.25" + attribute \src "libresoc.v:132580.7-132580.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:133592.3-133600.6" + attribute \src "libresoc.v:133388.3-133396.6" wire $1\alui_l_r_alui$next[0:0]$5316 - attribute \src "libresoc.v:132796.7-132796.27" + attribute \src "libresoc.v:132592.7-132592.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:133474.3-133495.6" + attribute \src "libresoc.v:133270.3-133291.6" wire width 64 $1\data_r0__o$next[63:0]$5276 - attribute \src "libresoc.v:132830.14-132830.47" + attribute \src "libresoc.v:132626.14-132626.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:133474.3-133495.6" + attribute \src "libresoc.v:133270.3-133291.6" wire $1\data_r0__o_ok$next[0:0]$5277 - attribute \src "libresoc.v:132834.7-132834.27" + attribute \src "libresoc.v:132630.7-132630.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:133496.3-133517.6" + attribute \src "libresoc.v:133292.3-133313.6" wire width 4 $1\data_r1__cr_a$next[3:0]$5284 - attribute \src "libresoc.v:132838.13-132838.33" + attribute \src "libresoc.v:132634.13-132634.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:133496.3-133517.6" + attribute \src "libresoc.v:133292.3-133313.6" wire $1\data_r1__cr_a_ok$next[0:0]$5285 - attribute \src "libresoc.v:132842.7-132842.30" + attribute \src "libresoc.v:132638.7-132638.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:133518.3-133539.6" + attribute \src "libresoc.v:133314.3-133335.6" wire width 2 $1\data_r2__xer_ov$next[1:0]$5292 - attribute \src "libresoc.v:132846.13-132846.35" + attribute \src "libresoc.v:132642.13-132642.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:133518.3-133539.6" + attribute \src "libresoc.v:133314.3-133335.6" wire $1\data_r2__xer_ov_ok$next[0:0]$5293 - attribute \src "libresoc.v:132850.7-132850.32" + attribute \src "libresoc.v:132646.7-132646.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:133540.3-133561.6" + attribute \src "libresoc.v:133336.3-133357.6" wire $1\data_r3__xer_so$next[0:0]$5300 - attribute \src "libresoc.v:132854.7-132854.29" + attribute \src "libresoc.v:132650.7-132650.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:133540.3-133561.6" + attribute \src "libresoc.v:133336.3-133357.6" wire $1\data_r3__xer_so_ok$next[0:0]$5301 - attribute \src "libresoc.v:132858.7-132858.32" + attribute \src "libresoc.v:132654.7-132654.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:133610.3-133619.6" + attribute \src "libresoc.v:133406.3-133415.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:133620.3-133629.6" + attribute \src "libresoc.v:133416.3-133425.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:133630.3-133639.6" + attribute \src "libresoc.v:133426.3-133435.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:133640.3-133649.6" + attribute \src "libresoc.v:133436.3-133445.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:133390.3-133398.6" + attribute \src "libresoc.v:133186.3-133194.6" wire $1\opc_l_r_opc$next[0:0]$5217 - attribute \src "libresoc.v:132878.7-132878.25" + attribute \src "libresoc.v:132674.7-132674.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:133381.3-133389.6" + attribute \src "libresoc.v:133177.3-133185.6" wire $1\opc_l_s_opc$next[0:0]$5214 - attribute \src "libresoc.v:132882.7-132882.25" + attribute \src "libresoc.v:132678.7-132678.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:133650.3-133658.6" + attribute \src "libresoc.v:133446.3-133454.6" wire width 4 $1\prev_wr_go$next[3:0]$5326 - attribute \src "libresoc.v:133016.13-133016.30" + attribute \src "libresoc.v:132812.13-132812.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:133335.3-133344.6" + attribute \src "libresoc.v:133131.3-133140.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:133426.3-133434.6" + attribute \src "libresoc.v:133222.3-133230.6" wire width 4 $1\req_l_r_req$next[3:0]$5229 - attribute \src "libresoc.v:133024.13-133024.31" + attribute \src "libresoc.v:132820.13-132820.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:133417.3-133425.6" + attribute \src "libresoc.v:133213.3-133221.6" wire width 4 $1\req_l_s_req$next[3:0]$5226 - attribute \src "libresoc.v:133028.13-133028.31" + attribute \src "libresoc.v:132824.13-132824.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:133354.3-133362.6" + attribute \src "libresoc.v:133150.3-133158.6" wire $1\rok_l_r_rdok$next[0:0]$5205 - attribute \src "libresoc.v:133040.7-133040.26" + attribute \src "libresoc.v:132836.7-132836.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:133345.3-133353.6" + attribute \src "libresoc.v:133141.3-133149.6" wire $1\rok_l_s_rdok$next[0:0]$5202 - attribute \src "libresoc.v:133044.7-133044.26" + attribute \src "libresoc.v:132840.7-132840.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:133372.3-133380.6" + attribute \src "libresoc.v:133168.3-133176.6" wire $1\rst_l_r_rst$next[0:0]$5211 - attribute \src "libresoc.v:133048.7-133048.25" + attribute \src "libresoc.v:132844.7-132844.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:133363.3-133371.6" + attribute \src "libresoc.v:133159.3-133167.6" wire $1\rst_l_s_rst$next[0:0]$5208 - attribute \src "libresoc.v:133052.7-133052.25" + attribute \src "libresoc.v:132848.7-132848.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:133408.3-133416.6" + attribute \src "libresoc.v:133204.3-133212.6" wire width 3 $1\src_l_r_src$next[2:0]$5223 - attribute \src "libresoc.v:133066.13-133066.31" + attribute \src "libresoc.v:132862.13-132862.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:133399.3-133407.6" + attribute \src "libresoc.v:133195.3-133203.6" wire width 3 $1\src_l_s_src$next[2:0]$5220 - attribute \src "libresoc.v:133070.13-133070.31" + attribute \src "libresoc.v:132866.13-132866.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:133562.3-133571.6" + attribute \src "libresoc.v:133358.3-133367.6" wire width 64 $1\src_r0$next[63:0]$5307 - attribute \src "libresoc.v:133078.14-133078.43" + attribute \src "libresoc.v:132874.14-132874.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:133572.3-133581.6" + attribute \src "libresoc.v:133368.3-133377.6" wire width 64 $1\src_r1$next[63:0]$5310 - attribute \src "libresoc.v:133082.14-133082.43" + attribute \src "libresoc.v:132878.14-132878.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:133582.3-133591.6" + attribute \src "libresoc.v:133378.3-133387.6" wire $1\src_r2$next[0:0]$5313 - attribute \src "libresoc.v:133086.7-133086.20" + attribute \src "libresoc.v:132882.7-132882.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267 - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5269 - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 - attribute \src "libresoc.v:133435.3-133473.6" + attribute \src "libresoc.v:133231.3-133269.6" wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 - attribute \src "libresoc.v:133474.3-133495.6" + attribute \src "libresoc.v:133270.3-133291.6" wire width 64 $2\data_r0__o$next[63:0]$5278 - attribute \src "libresoc.v:133474.3-133495.6" + attribute \src "libresoc.v:133270.3-133291.6" wire $2\data_r0__o_ok$next[0:0]$5279 - attribute \src "libresoc.v:133496.3-133517.6" + attribute \src "libresoc.v:133292.3-133313.6" wire width 4 $2\data_r1__cr_a$next[3:0]$5286 - attribute \src "libresoc.v:133496.3-133517.6" + attribute \src "libresoc.v:133292.3-133313.6" wire $2\data_r1__cr_a_ok$next[0:0]$5287 - attribute \src "libresoc.v:133518.3-133539.6" + attribute \src "libresoc.v:133314.3-133335.6" wire width 2 $2\data_r2__xer_ov$next[1:0]$5294 - attribute \src "libresoc.v:133518.3-133539.6" + attribute \src "libresoc.v:133314.3-133335.6" wire $2\data_r2__xer_ov_ok$next[0:0]$5295 - attribute \src "libresoc.v:133540.3-133561.6" + attribute \src "libresoc.v:133336.3-133357.6" wire $2\data_r3__xer_so$next[0:0]$5302 - attribute \src "libresoc.v:133540.3-133561.6" + attribute \src "libresoc.v:133336.3-133357.6" wire $2\data_r3__xer_so_ok$next[0:0]$5303 - attribute \src "libresoc.v:133474.3-133495.6" + attribute \src "libresoc.v:133270.3-133291.6" wire $3\data_r0__o_ok$next[0:0]$5280 - attribute \src "libresoc.v:133496.3-133517.6" + attribute \src "libresoc.v:133292.3-133313.6" wire $3\data_r1__cr_a_ok$next[0:0]$5288 - attribute \src "libresoc.v:133518.3-133539.6" + attribute \src "libresoc.v:133314.3-133335.6" wire $3\data_r2__xer_ov_ok$next[0:0]$5296 - attribute \src "libresoc.v:133540.3-133561.6" + attribute \src "libresoc.v:133336.3-133357.6" wire $3\data_r3__xer_so_ok$next[0:0]$5304 - attribute \src "libresoc.v:133101.19-133101.133" - wire width 3 $and$libresoc.v:133101$5094_Y - attribute \src "libresoc.v:133103.19-133103.115" - wire width 3 $and$libresoc.v:133103$5096_Y - attribute \src "libresoc.v:133104.18-133104.110" - wire $and$libresoc.v:133104$5097_Y - attribute \src "libresoc.v:133105.19-133105.125" - wire $and$libresoc.v:133105$5098_Y - attribute \src "libresoc.v:133106.19-133106.125" - wire $and$libresoc.v:133106$5099_Y - attribute \src "libresoc.v:133107.19-133107.125" - wire $and$libresoc.v:133107$5100_Y - attribute \src "libresoc.v:133108.19-133108.125" - wire $and$libresoc.v:133108$5101_Y - attribute \src "libresoc.v:133109.19-133109.149" - wire width 4 $and$libresoc.v:133109$5102_Y - attribute \src "libresoc.v:133110.19-133110.121" - wire width 4 $and$libresoc.v:133110$5103_Y - attribute \src "libresoc.v:133111.19-133111.127" - wire $and$libresoc.v:133111$5104_Y - attribute \src "libresoc.v:133112.19-133112.127" - wire $and$libresoc.v:133112$5105_Y - attribute \src "libresoc.v:133113.19-133113.127" - wire $and$libresoc.v:133113$5106_Y - attribute \src "libresoc.v:133114.19-133114.127" - wire $and$libresoc.v:133114$5107_Y - attribute \src "libresoc.v:133116.18-133116.98" - wire $and$libresoc.v:133116$5109_Y - attribute \src "libresoc.v:133118.18-133118.100" - wire $and$libresoc.v:133118$5111_Y - attribute \src "libresoc.v:133119.18-133119.160" - wire width 4 $and$libresoc.v:133119$5112_Y - attribute \src "libresoc.v:133121.18-133121.119" - wire width 4 $and$libresoc.v:133121$5114_Y - attribute \src "libresoc.v:133124.17-133124.123" - wire $and$libresoc.v:133124$5117_Y - attribute \src "libresoc.v:133125.18-133125.116" - wire $and$libresoc.v:133125$5118_Y - attribute \src "libresoc.v:133130.18-133130.113" - wire $and$libresoc.v:133130$5123_Y - attribute \src "libresoc.v:133131.18-133131.125" - wire width 4 $and$libresoc.v:133131$5124_Y - attribute \src "libresoc.v:133133.18-133133.112" - wire $and$libresoc.v:133133$5126_Y - attribute \src "libresoc.v:133135.18-133135.126" - wire $and$libresoc.v:133135$5128_Y - attribute \src "libresoc.v:133136.18-133136.126" - wire $and$libresoc.v:133136$5129_Y - attribute \src "libresoc.v:133137.18-133137.117" - wire $and$libresoc.v:133137$5130_Y - attribute \src "libresoc.v:133143.18-133143.130" - wire $and$libresoc.v:133143$5136_Y - attribute \src "libresoc.v:133144.18-133144.124" - wire width 4 $and$libresoc.v:133144$5137_Y - attribute \src "libresoc.v:133146.18-133146.116" - wire $and$libresoc.v:133146$5139_Y - attribute \src "libresoc.v:133147.18-133147.119" - wire $and$libresoc.v:133147$5140_Y - attribute \src "libresoc.v:133148.18-133148.121" - wire $and$libresoc.v:133148$5141_Y - attribute \src "libresoc.v:133149.18-133149.121" - wire $and$libresoc.v:133149$5142_Y - attribute \src "libresoc.v:133159.18-133159.134" - wire $and$libresoc.v:133159$5152_Y - attribute \src "libresoc.v:133160.18-133160.132" - wire $and$libresoc.v:133160$5153_Y - attribute \src "libresoc.v:133161.18-133161.149" - wire width 3 $and$libresoc.v:133161$5154_Y - attribute \src "libresoc.v:133132.18-133132.113" - wire $eq$libresoc.v:133132$5125_Y - attribute \src "libresoc.v:133134.18-133134.119" - wire $eq$libresoc.v:133134$5127_Y - attribute \src "libresoc.v:133099.19-133099.130" - wire $not$libresoc.v:133099$5092_Y - attribute \src "libresoc.v:133100.19-133100.136" - wire $not$libresoc.v:133100$5093_Y - attribute \src "libresoc.v:133102.19-133102.115" - wire width 3 $not$libresoc.v:133102$5095_Y - attribute \src "libresoc.v:133115.18-133115.97" - wire $not$libresoc.v:133115$5108_Y - attribute \src "libresoc.v:133117.18-133117.99" - wire $not$libresoc.v:133117$5110_Y - attribute \src "libresoc.v:133120.18-133120.113" - wire width 4 $not$libresoc.v:133120$5113_Y - attribute \src "libresoc.v:133123.18-133123.106" - wire $not$libresoc.v:133123$5116_Y - attribute \src "libresoc.v:133129.18-133129.120" - wire $not$libresoc.v:133129$5122_Y - attribute \src "libresoc.v:133140.17-133140.113" - wire width 3 $not$libresoc.v:133140$5133_Y - attribute \src "libresoc.v:133128.18-133128.112" - wire $or$libresoc.v:133128$5121_Y - attribute \src "libresoc.v:133138.18-133138.122" - wire $or$libresoc.v:133138$5131_Y - attribute \src "libresoc.v:133139.18-133139.124" - wire $or$libresoc.v:133139$5132_Y - attribute \src "libresoc.v:133141.18-133141.168" - wire width 4 $or$libresoc.v:133141$5134_Y - attribute \src "libresoc.v:133142.18-133142.155" - wire width 3 $or$libresoc.v:133142$5135_Y - attribute \src "libresoc.v:133145.18-133145.120" - wire width 4 $or$libresoc.v:133145$5138_Y - attribute \src "libresoc.v:133151.17-133151.117" - wire width 3 $or$libresoc.v:133151$5144_Y - attribute \src "libresoc.v:133156.17-133156.104" - wire $reduce_and$libresoc.v:133156$5149_Y - attribute \src "libresoc.v:133122.18-133122.106" - wire $reduce_or$libresoc.v:133122$5115_Y - attribute \src "libresoc.v:133126.18-133126.113" - wire $reduce_or$libresoc.v:133126$5119_Y - attribute \src "libresoc.v:133127.18-133127.112" - wire $reduce_or$libresoc.v:133127$5120_Y - attribute \src "libresoc.v:133150.18-133150.158" - wire $ternary$libresoc.v:133150$5143_Y - attribute \src "libresoc.v:133152.18-133152.159" - wire width 64 $ternary$libresoc.v:133152$5145_Y - attribute \src "libresoc.v:133153.18-133153.164" - wire $ternary$libresoc.v:133153$5146_Y - attribute \src "libresoc.v:133154.18-133154.180" - wire width 64 $ternary$libresoc.v:133154$5147_Y - attribute \src "libresoc.v:133155.18-133155.115" - wire width 64 $ternary$libresoc.v:133155$5148_Y - attribute \src "libresoc.v:133157.18-133157.125" - wire width 64 $ternary$libresoc.v:133157$5150_Y - attribute \src "libresoc.v:133158.18-133158.118" - wire $ternary$libresoc.v:133158$5151_Y + attribute \src "libresoc.v:132897.19-132897.133" + wire width 3 $and$libresoc.v:132897$5094_Y + attribute \src "libresoc.v:132899.19-132899.115" + wire width 3 $and$libresoc.v:132899$5096_Y + attribute \src "libresoc.v:132900.18-132900.110" + wire $and$libresoc.v:132900$5097_Y + attribute \src "libresoc.v:132901.19-132901.125" + wire $and$libresoc.v:132901$5098_Y + attribute \src "libresoc.v:132902.19-132902.125" + wire $and$libresoc.v:132902$5099_Y + attribute \src "libresoc.v:132903.19-132903.125" + wire $and$libresoc.v:132903$5100_Y + attribute \src "libresoc.v:132904.19-132904.125" + wire $and$libresoc.v:132904$5101_Y + attribute \src "libresoc.v:132905.19-132905.149" + wire width 4 $and$libresoc.v:132905$5102_Y + attribute \src "libresoc.v:132906.19-132906.121" + wire width 4 $and$libresoc.v:132906$5103_Y + attribute \src "libresoc.v:132907.19-132907.127" + wire $and$libresoc.v:132907$5104_Y + attribute \src "libresoc.v:132908.19-132908.127" + wire $and$libresoc.v:132908$5105_Y + attribute \src "libresoc.v:132909.19-132909.127" + wire $and$libresoc.v:132909$5106_Y + attribute \src "libresoc.v:132910.19-132910.127" + wire $and$libresoc.v:132910$5107_Y + attribute \src "libresoc.v:132912.18-132912.98" + wire $and$libresoc.v:132912$5109_Y + attribute \src "libresoc.v:132914.18-132914.100" + wire $and$libresoc.v:132914$5111_Y + attribute \src "libresoc.v:132915.18-132915.160" + wire width 4 $and$libresoc.v:132915$5112_Y + attribute \src "libresoc.v:132917.18-132917.119" + wire width 4 $and$libresoc.v:132917$5114_Y + attribute \src "libresoc.v:132920.17-132920.123" + wire $and$libresoc.v:132920$5117_Y + attribute \src "libresoc.v:132921.18-132921.116" + wire $and$libresoc.v:132921$5118_Y + attribute \src "libresoc.v:132926.18-132926.113" + wire $and$libresoc.v:132926$5123_Y + attribute \src "libresoc.v:132927.18-132927.125" + wire width 4 $and$libresoc.v:132927$5124_Y + attribute \src "libresoc.v:132929.18-132929.112" + wire $and$libresoc.v:132929$5126_Y + attribute \src "libresoc.v:132931.18-132931.126" + wire $and$libresoc.v:132931$5128_Y + attribute \src "libresoc.v:132932.18-132932.126" + wire $and$libresoc.v:132932$5129_Y + attribute \src "libresoc.v:132933.18-132933.117" + wire $and$libresoc.v:132933$5130_Y + attribute \src "libresoc.v:132939.18-132939.130" + wire $and$libresoc.v:132939$5136_Y + attribute \src "libresoc.v:132940.18-132940.124" + wire width 4 $and$libresoc.v:132940$5137_Y + attribute \src "libresoc.v:132942.18-132942.116" + wire $and$libresoc.v:132942$5139_Y + attribute \src "libresoc.v:132943.18-132943.119" + wire $and$libresoc.v:132943$5140_Y + attribute \src "libresoc.v:132944.18-132944.121" + wire $and$libresoc.v:132944$5141_Y + attribute \src "libresoc.v:132945.18-132945.121" + wire $and$libresoc.v:132945$5142_Y + attribute \src "libresoc.v:132955.18-132955.134" + wire $and$libresoc.v:132955$5152_Y + attribute \src "libresoc.v:132956.18-132956.132" + wire $and$libresoc.v:132956$5153_Y + attribute \src "libresoc.v:132957.18-132957.149" + wire width 3 $and$libresoc.v:132957$5154_Y + attribute \src "libresoc.v:132928.18-132928.113" + wire $eq$libresoc.v:132928$5125_Y + attribute \src "libresoc.v:132930.18-132930.119" + wire $eq$libresoc.v:132930$5127_Y + attribute \src "libresoc.v:132895.19-132895.130" + wire $not$libresoc.v:132895$5092_Y + attribute \src "libresoc.v:132896.19-132896.136" + wire $not$libresoc.v:132896$5093_Y + attribute \src "libresoc.v:132898.19-132898.115" + wire width 3 $not$libresoc.v:132898$5095_Y + attribute \src "libresoc.v:132911.18-132911.97" + wire $not$libresoc.v:132911$5108_Y + attribute \src "libresoc.v:132913.18-132913.99" + wire $not$libresoc.v:132913$5110_Y + attribute \src "libresoc.v:132916.18-132916.113" + wire width 4 $not$libresoc.v:132916$5113_Y + attribute \src "libresoc.v:132919.18-132919.106" + wire $not$libresoc.v:132919$5116_Y + attribute \src "libresoc.v:132925.18-132925.120" + wire $not$libresoc.v:132925$5122_Y + attribute \src "libresoc.v:132936.17-132936.113" + wire width 3 $not$libresoc.v:132936$5133_Y + attribute \src "libresoc.v:132924.18-132924.112" + wire $or$libresoc.v:132924$5121_Y + attribute \src "libresoc.v:132934.18-132934.122" + wire $or$libresoc.v:132934$5131_Y + attribute \src "libresoc.v:132935.18-132935.124" + wire $or$libresoc.v:132935$5132_Y + attribute \src "libresoc.v:132937.18-132937.168" + wire width 4 $or$libresoc.v:132937$5134_Y + attribute \src "libresoc.v:132938.18-132938.155" + wire width 3 $or$libresoc.v:132938$5135_Y + attribute \src "libresoc.v:132941.18-132941.120" + wire width 4 $or$libresoc.v:132941$5138_Y + attribute \src "libresoc.v:132947.17-132947.117" + wire width 3 $or$libresoc.v:132947$5144_Y + attribute \src "libresoc.v:132952.17-132952.104" + wire $reduce_and$libresoc.v:132952$5149_Y + attribute \src "libresoc.v:132918.18-132918.106" + wire $reduce_or$libresoc.v:132918$5115_Y + attribute \src "libresoc.v:132922.18-132922.113" + wire $reduce_or$libresoc.v:132922$5119_Y + attribute \src "libresoc.v:132923.18-132923.112" + wire $reduce_or$libresoc.v:132923$5120_Y + attribute \src "libresoc.v:132946.18-132946.158" + wire $ternary$libresoc.v:132946$5143_Y + attribute \src "libresoc.v:132948.18-132948.159" + wire width 64 $ternary$libresoc.v:132948$5145_Y + attribute \src "libresoc.v:132949.18-132949.164" + wire $ternary$libresoc.v:132949$5146_Y + attribute \src "libresoc.v:132950.18-132950.180" + wire width 64 $ternary$libresoc.v:132950$5147_Y + attribute \src "libresoc.v:132951.18-132951.115" + wire width 64 $ternary$libresoc.v:132951$5148_Y + attribute \src "libresoc.v:132953.18-132953.125" + wire width 64 $ternary$libresoc.v:132953$5150_Y + attribute \src "libresoc.v:132954.18-132954.118" + wire $ternary$libresoc.v:132954$5151_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" @@ -208295,9 +208091,9 @@ module \div0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \cr_a_ok @@ -208363,7 +208159,7 @@ module \div0 wire width 2 output 35 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 37 \dest4_o - attribute \src "libresoc.v:132448.7-132448.15" + attribute \src "libresoc.v:132244.7-132244.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \o_ok @@ -208592,7 +208388,7 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 36 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:133101$5094 + cell $and $and$libresoc.v:132897$5094 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208600,10 +208396,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$98 connect \B { 1'1 \$102 \$100 } - connect \Y $and$libresoc.v:133101$5094_Y + connect \Y $and$libresoc.v:132897$5094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:133103$5096 + cell $and $and$libresoc.v:132899$5096 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208611,10 +208407,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:133103$5096_Y + connect \Y $and$libresoc.v:132899$5096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:133104$5097 + cell $and $and$libresoc.v:132900$5097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208622,10 +208418,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:133104$5097_Y + connect \Y $and$libresoc.v:132900$5097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:133105$5098 + cell $and $and$libresoc.v:132901$5098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208633,10 +208429,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:133105$5098_Y + connect \Y $and$libresoc.v:132901$5098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:133106$5099 + cell $and $and$libresoc.v:132902$5099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208644,10 +208440,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:133106$5099_Y + connect \Y $and$libresoc.v:132902$5099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:133107$5100 + cell $and $and$libresoc.v:132903$5100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208655,10 +208451,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:133107$5100_Y + connect \Y $and$libresoc.v:132903$5100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:133108$5101 + cell $and $and$libresoc.v:132904$5101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208666,10 +208462,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:133108$5101_Y + connect \Y $and$libresoc.v:132904$5101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:133109$5102 + cell $and $and$libresoc.v:132905$5102 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208677,10 +208473,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 } - connect \Y $and$libresoc.v:133109$5102_Y + connect \Y $and$libresoc.v:132905$5102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:133110$5103 + cell $and $and$libresoc.v:132906$5103 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208688,10 +208484,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \$118 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:133110$5103_Y + connect \Y $and$libresoc.v:132906$5103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:133111$5104 + cell $and $and$libresoc.v:132907$5104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208699,10 +208495,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:133111$5104_Y + connect \Y $and$libresoc.v:132907$5104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:133112$5105 + cell $and $and$libresoc.v:132908$5105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208710,10 +208506,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:133112$5105_Y + connect \Y $and$libresoc.v:132908$5105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:133113$5106 + cell $and $and$libresoc.v:132909$5106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208721,10 +208517,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:133113$5106_Y + connect \Y $and$libresoc.v:132909$5106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:133114$5107 + cell $and $and$libresoc.v:132910$5107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208732,10 +208528,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:133114$5107_Y + connect \Y $and$libresoc.v:132910$5107_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:133116$5109 + cell $and $and$libresoc.v:132912$5109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208743,10 +208539,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:133116$5109_Y + connect \Y $and$libresoc.v:132912$5109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:133118$5111 + cell $and $and$libresoc.v:132914$5111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208754,10 +208550,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:133118$5111_Y + connect \Y $and$libresoc.v:132914$5111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:133119$5112 + cell $and $and$libresoc.v:132915$5112 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208765,10 +208561,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:133119$5112_Y + connect \Y $and$libresoc.v:132915$5112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:133121$5114 + cell $and $and$libresoc.v:132917$5114 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208776,10 +208572,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:133121$5114_Y + connect \Y $and$libresoc.v:132917$5114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:133124$5117 + cell $and $and$libresoc.v:132920$5117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208787,10 +208583,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:133124$5117_Y + connect \Y $and$libresoc.v:132920$5117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:133125$5118 + cell $and $and$libresoc.v:132921$5118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208798,10 +208594,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:133125$5118_Y + connect \Y $and$libresoc.v:132921$5118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:133130$5123 + cell $and $and$libresoc.v:132926$5123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208809,10 +208605,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:133130$5123_Y + connect \Y $and$libresoc.v:132926$5123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:133131$5124 + cell $and $and$libresoc.v:132927$5124 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208820,10 +208616,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:133131$5124_Y + connect \Y $and$libresoc.v:132927$5124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:133133$5126 + cell $and $and$libresoc.v:132929$5126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208831,10 +208627,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:133133$5126_Y + connect \Y $and$libresoc.v:132929$5126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:133135$5128 + cell $and $and$libresoc.v:132931$5128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208842,10 +208638,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_div0_n_ready_i - connect \Y $and$libresoc.v:133135$5128_Y + connect \Y $and$libresoc.v:132931$5128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:133136$5129 + cell $and $and$libresoc.v:132932$5129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208853,10 +208649,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_div0_n_valid_o - connect \Y $and$libresoc.v:133136$5129_Y + connect \Y $and$libresoc.v:132932$5129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:133137$5130 + cell $and $and$libresoc.v:132933$5130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208864,10 +208660,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:133137$5130_Y + connect \Y $and$libresoc.v:132933$5130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:133143$5136 + cell $and $and$libresoc.v:132939$5136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208875,10 +208671,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:133143$5136_Y + connect \Y $and$libresoc.v:132939$5136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:133144$5137 + cell $and $and$libresoc.v:132940$5137 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208886,10 +208682,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:133144$5137_Y + connect \Y $and$libresoc.v:132940$5137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:133146$5139 + cell $and $and$libresoc.v:132942$5139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208897,10 +208693,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:133146$5139_Y + connect \Y $and$libresoc.v:132942$5139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:133147$5140 + cell $and $and$libresoc.v:132943$5140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208908,10 +208704,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:133147$5140_Y + connect \Y $and$libresoc.v:132943$5140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:133148$5141 + cell $and $and$libresoc.v:132944$5141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208919,10 +208715,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:133148$5141_Y + connect \Y $and$libresoc.v:132944$5141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:133149$5142 + cell $and $and$libresoc.v:132945$5142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208930,10 +208726,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:133149$5142_Y + connect \Y $and$libresoc.v:132945$5142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:133159$5152 + cell $and $and$libresoc.v:132955$5152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208941,10 +208737,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:133159$5152_Y + connect \Y $and$libresoc.v:132955$5152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:133160$5153 + cell $and $and$libresoc.v:132956$5153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208952,10 +208748,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:133160$5153_Y + connect \Y $and$libresoc.v:132956$5153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:133161$5154 + cell $and $and$libresoc.v:132957$5154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208963,10 +208759,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:133161$5154_Y + connect \Y $and$libresoc.v:132957$5154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:133132$5125 + cell $eq $eq$libresoc.v:132928$5125 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208974,10 +208770,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:133132$5125_Y + connect \Y $eq$libresoc.v:132928$5125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:133134$5127 + cell $eq $eq$libresoc.v:132930$5127 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208985,82 +208781,82 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:133134$5127_Y + connect \Y $eq$libresoc.v:132930$5127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:133099$5092 + cell $not $not$libresoc.v:132895$5092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__zero_a - connect \Y $not$libresoc.v:133099$5092_Y + connect \Y $not$libresoc.v:132895$5092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:133100$5093 + cell $not $not$libresoc.v:132896$5093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:133100$5093_Y + connect \Y $not$libresoc.v:132896$5093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:133102$5095 + cell $not $not$libresoc.v:132898$5095 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:133102$5095_Y + connect \Y $not$libresoc.v:132898$5095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:133115$5108 + cell $not $not$libresoc.v:132911$5108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:133115$5108_Y + connect \Y $not$libresoc.v:132911$5108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:133117$5110 + cell $not $not$libresoc.v:132913$5110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:133117$5110_Y + connect \Y $not$libresoc.v:132913$5110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:133120$5113 + cell $not $not$libresoc.v:132916$5113 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:133120$5113_Y + connect \Y $not$libresoc.v:132916$5113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:133123$5116 + cell $not $not$libresoc.v:132919$5116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:133123$5116_Y + connect \Y $not$libresoc.v:132919$5116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:133129$5122 + cell $not $not$libresoc.v:132925$5122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_n_ready_i - connect \Y $not$libresoc.v:133129$5122_Y + connect \Y $not$libresoc.v:132925$5122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:133140$5133 + cell $not $not$libresoc.v:132936$5133 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:133140$5133_Y + connect \Y $not$libresoc.v:132936$5133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:133128$5121 + cell $or $or$libresoc.v:132924$5121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209068,10 +208864,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:133128$5121_Y + connect \Y $or$libresoc.v:132924$5121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:133138$5131 + cell $or $or$libresoc.v:132934$5131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209079,10 +208875,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:133138$5131_Y + connect \Y $or$libresoc.v:132934$5131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:133139$5132 + cell $or $or$libresoc.v:132935$5132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209090,10 +208886,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:133139$5132_Y + connect \Y $or$libresoc.v:132935$5132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:133141$5134 + cell $or $or$libresoc.v:132937$5134 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -209101,10 +208897,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:133141$5134_Y + connect \Y $or$libresoc.v:132937$5134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:133142$5135 + cell $or $or$libresoc.v:132938$5135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -209112,10 +208908,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:133142$5135_Y + connect \Y $or$libresoc.v:132938$5135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:133145$5138 + cell $or $or$libresoc.v:132941$5138 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -209123,10 +208919,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:133145$5138_Y + connect \Y $or$libresoc.v:132941$5138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:133151$5144 + cell $or $or$libresoc.v:132947$5144 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -209134,98 +208930,98 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:133151$5144_Y + connect \Y $or$libresoc.v:132947$5144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:133156$5149 + cell $reduce_and $reduce_and$libresoc.v:132952$5149 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:133156$5149_Y + connect \Y $reduce_and$libresoc.v:132952$5149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:133122$5115 + cell $reduce_or $reduce_or$libresoc.v:132918$5115 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:133122$5115_Y + connect \Y $reduce_or$libresoc.v:132918$5115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:133126$5119 + cell $reduce_or $reduce_or$libresoc.v:132922$5119 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:133126$5119_Y + connect \Y $reduce_or$libresoc.v:132922$5119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:133127$5120 + cell $reduce_or $reduce_or$libresoc.v:132923$5120 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:133127$5120_Y + connect \Y $reduce_or$libresoc.v:132923$5120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:133150$5143 + cell $mux $ternary$libresoc.v:132946$5143 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:133150$5143_Y + connect \Y $ternary$libresoc.v:132946$5143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:133152$5145 + cell $mux $ternary$libresoc.v:132948$5145 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:133152$5145_Y + connect \Y $ternary$libresoc.v:132948$5145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:133153$5146 + cell $mux $ternary$libresoc.v:132949$5146 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:133153$5146_Y + connect \Y $ternary$libresoc.v:132949$5146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:133154$5147 + cell $mux $ternary$libresoc.v:132950$5147 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_div0_logical_op__imm_data__data connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:133154$5147_Y + connect \Y $ternary$libresoc.v:132950$5147_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:133155$5148 + cell $mux $ternary$libresoc.v:132951$5148 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:133155$5148_Y + connect \Y $ternary$libresoc.v:132951$5148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:133157$5150 + cell $mux $ternary$libresoc.v:132953$5150 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$85 connect \S \src_sel$82 - connect \Y $ternary$libresoc.v:133157$5150_Y + connect \Y $ternary$libresoc.v:132953$5150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:133158$5151 + cell $mux $ternary$libresoc.v:132954$5151 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:133158$5151_Y + connect \Y $ternary$libresoc.v:132954$5151_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:133250.12-133286.4" + attribute \src "libresoc.v:133046.12-133082.4" cell \alu_div0 \alu_div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209264,7 +209060,7 @@ module \div0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:133287.14-133293.4" + attribute \src "libresoc.v:133083.14-133089.4" cell \alu_l$90 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209273,7 +209069,7 @@ module \div0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:133294.15-133300.4" + attribute \src "libresoc.v:133090.15-133096.4" cell \alui_l$89 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209282,7 +209078,7 @@ module \div0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:133301.14-133307.4" + attribute \src "libresoc.v:133097.14-133103.4" cell \opc_l$85 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209291,7 +209087,7 @@ module \div0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:133308.14-133314.4" + attribute \src "libresoc.v:133104.14-133110.4" cell \req_l$86 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209300,7 +209096,7 @@ module \div0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:133315.14-133321.4" + attribute \src "libresoc.v:133111.14-133117.4" cell \rok_l$88 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209309,7 +209105,7 @@ module \div0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:133322.14-133327.4" + attribute \src "libresoc.v:133118.14-133123.4" cell \rst_l$87 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209317,7 +209113,7 @@ module \div0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:133328.14-133334.4" + attribute \src "libresoc.v:133124.14-133130.4" cell \src_l$84 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -209325,682 +209121,682 @@ module \div0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:132448.7-132448.20" - process $proc$libresoc.v:132448$5327 + attribute \src "libresoc.v:132244.7-132244.20" + process $proc$libresoc.v:132244$5327 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132578.7-132578.24" - process $proc$libresoc.v:132578$5328 + attribute \src "libresoc.v:132374.7-132374.24" + process $proc$libresoc.v:132374$5328 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:132588.13-132588.49" - process $proc$libresoc.v:132588$5329 + attribute \src "libresoc.v:132384.13-132384.49" + process $proc$libresoc.v:132384$5329 assign { } { } assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:132607.14-132607.53" - process $proc$libresoc.v:132607$5330 + attribute \src "libresoc.v:132403.14-132403.53" + process $proc$libresoc.v:132403$5330 assign { } { } assign $1\alu_div0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:132611.14-132611.72" - process $proc$libresoc.v:132611$5331 + attribute \src "libresoc.v:132407.14-132407.72" + process $proc$libresoc.v:132407$5331 assign { } { } assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:132615.7-132615.47" - process $proc$libresoc.v:132615$5332 + attribute \src "libresoc.v:132411.7-132411.47" + process $proc$libresoc.v:132411$5332 assign { } { } assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:132623.13-132623.52" - process $proc$libresoc.v:132623$5333 + attribute \src "libresoc.v:132419.13-132419.52" + process $proc$libresoc.v:132419$5333 assign { } { } assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:132627.14-132627.47" - process $proc$libresoc.v:132627$5334 + attribute \src "libresoc.v:132423.14-132423.47" + process $proc$libresoc.v:132423$5334 assign { } { } assign $1\alu_div0_logical_op__insn[31:0] 0 sync always sync init update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:132706.13-132706.51" - process $proc$libresoc.v:132706$5335 + attribute \src "libresoc.v:132502.13-132502.51" + process $proc$libresoc.v:132502$5335 assign { } { } assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:132710.7-132710.44" - process $proc$libresoc.v:132710$5336 + attribute \src "libresoc.v:132506.7-132506.44" + process $proc$libresoc.v:132506$5336 assign { } { } assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:132714.7-132714.45" - process $proc$libresoc.v:132714$5337 + attribute \src "libresoc.v:132510.7-132510.45" + process $proc$libresoc.v:132510$5337 assign { } { } assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:132718.7-132718.43" - process $proc$libresoc.v:132718$5338 + attribute \src "libresoc.v:132514.7-132514.43" + process $proc$libresoc.v:132514$5338 assign { } { } assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:132722.7-132722.44" - process $proc$libresoc.v:132722$5339 + attribute \src "libresoc.v:132518.7-132518.44" + process $proc$libresoc.v:132518$5339 assign { } { } assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:132726.7-132726.41" - process $proc$libresoc.v:132726$5340 + attribute \src "libresoc.v:132522.7-132522.41" + process $proc$libresoc.v:132522$5340 assign { } { } assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:132730.7-132730.41" - process $proc$libresoc.v:132730$5341 + attribute \src "libresoc.v:132526.7-132526.41" + process $proc$libresoc.v:132526$5341 assign { } { } assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:132734.7-132734.47" - process $proc$libresoc.v:132734$5342 + attribute \src "libresoc.v:132530.7-132530.47" + process $proc$libresoc.v:132530$5342 assign { } { } assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:132738.7-132738.41" - process $proc$libresoc.v:132738$5343 + attribute \src "libresoc.v:132534.7-132534.41" + process $proc$libresoc.v:132534$5343 assign { } { } assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:132742.7-132742.41" - process $proc$libresoc.v:132742$5344 + attribute \src "libresoc.v:132538.7-132538.41" + process $proc$libresoc.v:132538$5344 assign { } { } assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:132746.7-132746.44" - process $proc$libresoc.v:132746$5345 + attribute \src "libresoc.v:132542.7-132542.44" + process $proc$libresoc.v:132542$5345 assign { } { } assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:132750.7-132750.41" - process $proc$libresoc.v:132750$5346 + attribute \src "libresoc.v:132546.7-132546.41" + process $proc$libresoc.v:132546$5346 assign { } { } assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:132776.7-132776.26" - process $proc$libresoc.v:132776$5347 + attribute \src "libresoc.v:132572.7-132572.26" + process $proc$libresoc.v:132572$5347 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:132784.7-132784.25" - process $proc$libresoc.v:132784$5348 + attribute \src "libresoc.v:132580.7-132580.25" + process $proc$libresoc.v:132580$5348 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:132796.7-132796.27" - process $proc$libresoc.v:132796$5349 + attribute \src "libresoc.v:132592.7-132592.27" + process $proc$libresoc.v:132592$5349 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:132830.14-132830.47" - process $proc$libresoc.v:132830$5350 + attribute \src "libresoc.v:132626.14-132626.47" + process $proc$libresoc.v:132626$5350 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:132834.7-132834.27" - process $proc$libresoc.v:132834$5351 + attribute \src "libresoc.v:132630.7-132630.27" + process $proc$libresoc.v:132630$5351 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:132838.13-132838.33" - process $proc$libresoc.v:132838$5352 + attribute \src "libresoc.v:132634.13-132634.33" + process $proc$libresoc.v:132634$5352 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:132842.7-132842.30" - process $proc$libresoc.v:132842$5353 + attribute \src "libresoc.v:132638.7-132638.30" + process $proc$libresoc.v:132638$5353 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:132846.13-132846.35" - process $proc$libresoc.v:132846$5354 + attribute \src "libresoc.v:132642.13-132642.35" + process $proc$libresoc.v:132642$5354 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:132850.7-132850.32" - process $proc$libresoc.v:132850$5355 + attribute \src "libresoc.v:132646.7-132646.32" + process $proc$libresoc.v:132646$5355 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:132854.7-132854.29" - process $proc$libresoc.v:132854$5356 + attribute \src "libresoc.v:132650.7-132650.29" + process $proc$libresoc.v:132650$5356 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:132858.7-132858.32" - process $proc$libresoc.v:132858$5357 + attribute \src "libresoc.v:132654.7-132654.32" + process $proc$libresoc.v:132654$5357 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:132878.7-132878.25" - process $proc$libresoc.v:132878$5358 + attribute \src "libresoc.v:132674.7-132674.25" + process $proc$libresoc.v:132674$5358 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:132882.7-132882.25" - process $proc$libresoc.v:132882$5359 + attribute \src "libresoc.v:132678.7-132678.25" + process $proc$libresoc.v:132678$5359 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:133016.13-133016.30" - process $proc$libresoc.v:133016$5360 + attribute \src "libresoc.v:132812.13-132812.30" + process $proc$libresoc.v:132812$5360 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:133024.13-133024.31" - process $proc$libresoc.v:133024$5361 + attribute \src "libresoc.v:132820.13-132820.31" + process $proc$libresoc.v:132820$5361 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:133028.13-133028.31" - process $proc$libresoc.v:133028$5362 + attribute \src "libresoc.v:132824.13-132824.31" + process $proc$libresoc.v:132824$5362 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:133040.7-133040.26" - process $proc$libresoc.v:133040$5363 + attribute \src "libresoc.v:132836.7-132836.26" + process $proc$libresoc.v:132836$5363 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:133044.7-133044.26" - process $proc$libresoc.v:133044$5364 + attribute \src "libresoc.v:132840.7-132840.26" + process $proc$libresoc.v:132840$5364 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:133048.7-133048.25" - process $proc$libresoc.v:133048$5365 + attribute \src "libresoc.v:132844.7-132844.25" + process $proc$libresoc.v:132844$5365 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:133052.7-133052.25" - process $proc$libresoc.v:133052$5366 + attribute \src "libresoc.v:132848.7-132848.25" + process $proc$libresoc.v:132848$5366 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:133066.13-133066.31" - process $proc$libresoc.v:133066$5367 + attribute \src "libresoc.v:132862.13-132862.31" + process $proc$libresoc.v:132862$5367 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:133070.13-133070.31" - process $proc$libresoc.v:133070$5368 + attribute \src "libresoc.v:132866.13-132866.31" + process $proc$libresoc.v:132866$5368 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:133078.14-133078.43" - process $proc$libresoc.v:133078$5369 + attribute \src "libresoc.v:132874.14-132874.43" + process $proc$libresoc.v:132874$5369 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:133082.14-133082.43" - process $proc$libresoc.v:133082$5370 + attribute \src "libresoc.v:132878.14-132878.43" + process $proc$libresoc.v:132878$5370 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:133086.7-133086.20" - process $proc$libresoc.v:133086$5371 + attribute \src "libresoc.v:132882.7-132882.20" + process $proc$libresoc.v:132882$5371 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:133162.3-133163.39" - process $proc$libresoc.v:133162$5155 + attribute \src "libresoc.v:132958.3-132959.39" + process $proc$libresoc.v:132958$5155 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:133164.3-133165.43" - process $proc$libresoc.v:133164$5156 + attribute \src "libresoc.v:132960.3-132961.43" + process $proc$libresoc.v:132960$5156 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:133166.3-133167.29" - process $proc$libresoc.v:133166$5157 + attribute \src "libresoc.v:132962.3-132963.29" + process $proc$libresoc.v:132962$5157 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:133168.3-133169.29" - process $proc$libresoc.v:133168$5158 + attribute \src "libresoc.v:132964.3-132965.29" + process $proc$libresoc.v:132964$5158 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:133170.3-133171.29" - process $proc$libresoc.v:133170$5159 + attribute \src "libresoc.v:132966.3-132967.29" + process $proc$libresoc.v:132966$5159 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:133172.3-133173.47" - process $proc$libresoc.v:133172$5160 + attribute \src "libresoc.v:132968.3-132969.47" + process $proc$libresoc.v:132968$5160 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:133174.3-133175.53" - process $proc$libresoc.v:133174$5161 + attribute \src "libresoc.v:132970.3-132971.53" + process $proc$libresoc.v:132970$5161 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:133176.3-133177.47" - process $proc$libresoc.v:133176$5162 + attribute \src "libresoc.v:132972.3-132973.47" + process $proc$libresoc.v:132972$5162 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:133178.3-133179.53" - process $proc$libresoc.v:133178$5163 + attribute \src "libresoc.v:132974.3-132975.53" + process $proc$libresoc.v:132974$5163 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:133180.3-133181.43" - process $proc$libresoc.v:133180$5164 + attribute \src "libresoc.v:132976.3-132977.43" + process $proc$libresoc.v:132976$5164 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:133182.3-133183.49" - process $proc$libresoc.v:133182$5165 + attribute \src "libresoc.v:132978.3-132979.49" + process $proc$libresoc.v:132978$5165 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:133184.3-133185.37" - process $proc$libresoc.v:133184$5166 + attribute \src "libresoc.v:132980.3-132981.37" + process $proc$libresoc.v:132980$5166 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:133186.3-133187.43" - process $proc$libresoc.v:133186$5167 + attribute \src "libresoc.v:132982.3-132983.43" + process $proc$libresoc.v:132982$5167 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:133188.3-133189.77" - process $proc$libresoc.v:133188$5168 + attribute \src "libresoc.v:132984.3-132985.77" + process $proc$libresoc.v:132984$5168 assign { } { } assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:133190.3-133191.73" - process $proc$libresoc.v:133190$5169 + attribute \src "libresoc.v:132986.3-132987.73" + process $proc$libresoc.v:132986$5169 assign { } { } assign $0\alu_div0_logical_op__fn_unit[13:0] \alu_div0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:133192.3-133193.87" - process $proc$libresoc.v:133192$5170 + attribute \src "libresoc.v:132988.3-132989.87" + process $proc$libresoc.v:132988$5170 assign { } { } assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:133194.3-133195.83" - process $proc$libresoc.v:133194$5171 + attribute \src "libresoc.v:132990.3-132991.83" + process $proc$libresoc.v:132990$5171 assign { } { } assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:133196.3-133197.71" - process $proc$libresoc.v:133196$5172 + attribute \src "libresoc.v:132992.3-132993.71" + process $proc$libresoc.v:132992$5172 assign { } { } assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:133198.3-133199.71" - process $proc$libresoc.v:133198$5173 + attribute \src "libresoc.v:132994.3-132995.71" + process $proc$libresoc.v:132994$5173 assign { } { } assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:133200.3-133201.71" - process $proc$libresoc.v:133200$5174 + attribute \src "libresoc.v:132996.3-132997.71" + process $proc$libresoc.v:132996$5174 assign { } { } assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:133202.3-133203.71" - process $proc$libresoc.v:133202$5175 + attribute \src "libresoc.v:132998.3-132999.71" + process $proc$libresoc.v:132998$5175 assign { } { } assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:133204.3-133205.77" - process $proc$libresoc.v:133204$5176 + attribute \src "libresoc.v:133000.3-133001.77" + process $proc$libresoc.v:133000$5176 assign { } { } assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:133206.3-133207.71" - process $proc$libresoc.v:133206$5177 + attribute \src "libresoc.v:133002.3-133003.71" + process $proc$libresoc.v:133002$5177 assign { } { } assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:133208.3-133209.81" - process $proc$libresoc.v:133208$5178 + attribute \src "libresoc.v:133004.3-133005.81" + process $proc$libresoc.v:133004$5178 assign { } { } assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:133210.3-133211.79" - process $proc$libresoc.v:133210$5179 + attribute \src "libresoc.v:133006.3-133007.79" + process $proc$libresoc.v:133006$5179 assign { } { } assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:133212.3-133213.77" - process $proc$libresoc.v:133212$5180 + attribute \src "libresoc.v:133008.3-133009.77" + process $proc$libresoc.v:133008$5180 assign { } { } assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:133214.3-133215.83" - process $proc$libresoc.v:133214$5181 + attribute \src "libresoc.v:133010.3-133011.83" + process $proc$libresoc.v:133010$5181 assign { } { } assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:133216.3-133217.75" - process $proc$libresoc.v:133216$5182 + attribute \src "libresoc.v:133012.3-133013.75" + process $proc$libresoc.v:133012$5182 assign { } { } assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:133218.3-133219.77" - process $proc$libresoc.v:133218$5183 + attribute \src "libresoc.v:133014.3-133015.77" + process $proc$libresoc.v:133014$5183 assign { } { } assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:133220.3-133221.75" - process $proc$libresoc.v:133220$5184 + attribute \src "libresoc.v:133016.3-133017.75" + process $proc$libresoc.v:133016$5184 assign { } { } assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next sync posedge \coresync_clk update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:133222.3-133223.67" - process $proc$libresoc.v:133222$5185 + attribute \src "libresoc.v:133018.3-133019.67" + process $proc$libresoc.v:133018$5185 assign { } { } assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next sync posedge \coresync_clk update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:133224.3-133225.39" - process $proc$libresoc.v:133224$5186 + attribute \src "libresoc.v:133020.3-133021.39" + process $proc$libresoc.v:133020$5186 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:133226.3-133227.39" - process $proc$libresoc.v:133226$5187 + attribute \src "libresoc.v:133022.3-133023.39" + process $proc$libresoc.v:133022$5187 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:133228.3-133229.39" - process $proc$libresoc.v:133228$5188 + attribute \src "libresoc.v:133024.3-133025.39" + process $proc$libresoc.v:133024$5188 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:133230.3-133231.39" - process $proc$libresoc.v:133230$5189 + attribute \src "libresoc.v:133026.3-133027.39" + process $proc$libresoc.v:133026$5189 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:133232.3-133233.39" - process $proc$libresoc.v:133232$5190 + attribute \src "libresoc.v:133028.3-133029.39" + process $proc$libresoc.v:133028$5190 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:133234.3-133235.39" - process $proc$libresoc.v:133234$5191 + attribute \src "libresoc.v:133030.3-133031.39" + process $proc$libresoc.v:133030$5191 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:133236.3-133237.39" - process $proc$libresoc.v:133236$5192 + attribute \src "libresoc.v:133032.3-133033.39" + process $proc$libresoc.v:133032$5192 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:133238.3-133239.39" - process $proc$libresoc.v:133238$5193 + attribute \src "libresoc.v:133034.3-133035.39" + process $proc$libresoc.v:133034$5193 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:133240.3-133241.41" - process $proc$libresoc.v:133240$5194 + attribute \src "libresoc.v:133036.3-133037.41" + process $proc$libresoc.v:133036$5194 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:133242.3-133243.41" - process $proc$libresoc.v:133242$5195 + attribute \src "libresoc.v:133038.3-133039.41" + process $proc$libresoc.v:133038$5195 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:133244.3-133245.37" - process $proc$libresoc.v:133244$5196 + attribute \src "libresoc.v:133040.3-133041.37" + process $proc$libresoc.v:133040$5196 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:133246.3-133247.40" - process $proc$libresoc.v:133246$5197 + attribute \src "libresoc.v:133042.3-133043.40" + process $proc$libresoc.v:133042$5197 assign { } { } assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:133248.3-133249.25" - process $proc$libresoc.v:133248$5198 + attribute \src "libresoc.v:133044.3-133045.25" + process $proc$libresoc.v:133044$5198 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:133335.3-133344.6" - process $proc$libresoc.v:133335$5199 + attribute \src "libresoc.v:133131.3-133140.6" + process $proc$libresoc.v:133131$5199 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:133336.5-133336.29" + attribute \src "libresoc.v:133132.5-133132.29" switch \initial - attribute \src "libresoc.v:133336.9-133336.17" + attribute \src "libresoc.v:133132.9-133132.17" case 1'1 case end @@ -210016,14 +209812,14 @@ module \div0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:133345.3-133353.6" - process $proc$libresoc.v:133345$5200 + attribute \src "libresoc.v:133141.3-133149.6" + process $proc$libresoc.v:133141$5200 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$5201 $1\rok_l_s_rdok$next[0:0]$5202 - attribute \src "libresoc.v:133346.5-133346.29" + attribute \src "libresoc.v:133142.5-133142.29" switch \initial - attribute \src "libresoc.v:133346.9-133346.17" + attribute \src "libresoc.v:133142.9-133142.17" case 1'1 case end @@ -210039,14 +209835,14 @@ module \div0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5201 end - attribute \src "libresoc.v:133354.3-133362.6" - process $proc$libresoc.v:133354$5203 + attribute \src "libresoc.v:133150.3-133158.6" + process $proc$libresoc.v:133150$5203 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$5204 $1\rok_l_r_rdok$next[0:0]$5205 - attribute \src "libresoc.v:133355.5-133355.29" + attribute \src "libresoc.v:133151.5-133151.29" switch \initial - attribute \src "libresoc.v:133355.9-133355.17" + attribute \src "libresoc.v:133151.9-133151.17" case 1'1 case end @@ -210062,14 +209858,14 @@ module \div0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5204 end - attribute \src "libresoc.v:133363.3-133371.6" - process $proc$libresoc.v:133363$5206 + attribute \src "libresoc.v:133159.3-133167.6" + process $proc$libresoc.v:133159$5206 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$5207 $1\rst_l_s_rst$next[0:0]$5208 - attribute \src "libresoc.v:133364.5-133364.29" + attribute \src "libresoc.v:133160.5-133160.29" switch \initial - attribute \src "libresoc.v:133364.9-133364.17" + attribute \src "libresoc.v:133160.9-133160.17" case 1'1 case end @@ -210085,14 +209881,14 @@ module \div0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5207 end - attribute \src "libresoc.v:133372.3-133380.6" - process $proc$libresoc.v:133372$5209 + attribute \src "libresoc.v:133168.3-133176.6" + process $proc$libresoc.v:133168$5209 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$5210 $1\rst_l_r_rst$next[0:0]$5211 - attribute \src "libresoc.v:133373.5-133373.29" + attribute \src "libresoc.v:133169.5-133169.29" switch \initial - attribute \src "libresoc.v:133373.9-133373.17" + attribute \src "libresoc.v:133169.9-133169.17" case 1'1 case end @@ -210108,14 +209904,14 @@ module \div0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5210 end - attribute \src "libresoc.v:133381.3-133389.6" - process $proc$libresoc.v:133381$5212 + attribute \src "libresoc.v:133177.3-133185.6" + process $proc$libresoc.v:133177$5212 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$5213 $1\opc_l_s_opc$next[0:0]$5214 - attribute \src "libresoc.v:133382.5-133382.29" + attribute \src "libresoc.v:133178.5-133178.29" switch \initial - attribute \src "libresoc.v:133382.9-133382.17" + attribute \src "libresoc.v:133178.9-133178.17" case 1'1 case end @@ -210131,14 +209927,14 @@ module \div0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5213 end - attribute \src "libresoc.v:133390.3-133398.6" - process $proc$libresoc.v:133390$5215 + attribute \src "libresoc.v:133186.3-133194.6" + process $proc$libresoc.v:133186$5215 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$5216 $1\opc_l_r_opc$next[0:0]$5217 - attribute \src "libresoc.v:133391.5-133391.29" + attribute \src "libresoc.v:133187.5-133187.29" switch \initial - attribute \src "libresoc.v:133391.9-133391.17" + attribute \src "libresoc.v:133187.9-133187.17" case 1'1 case end @@ -210154,14 +209950,14 @@ module \div0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5216 end - attribute \src "libresoc.v:133399.3-133407.6" - process $proc$libresoc.v:133399$5218 + attribute \src "libresoc.v:133195.3-133203.6" + process $proc$libresoc.v:133195$5218 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$5219 $1\src_l_s_src$next[2:0]$5220 - attribute \src "libresoc.v:133400.5-133400.29" + attribute \src "libresoc.v:133196.5-133196.29" switch \initial - attribute \src "libresoc.v:133400.9-133400.17" + attribute \src "libresoc.v:133196.9-133196.17" case 1'1 case end @@ -210177,14 +209973,14 @@ module \div0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5219 end - attribute \src "libresoc.v:133408.3-133416.6" - process $proc$libresoc.v:133408$5221 + attribute \src "libresoc.v:133204.3-133212.6" + process $proc$libresoc.v:133204$5221 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$5222 $1\src_l_r_src$next[2:0]$5223 - attribute \src "libresoc.v:133409.5-133409.29" + attribute \src "libresoc.v:133205.5-133205.29" switch \initial - attribute \src "libresoc.v:133409.9-133409.17" + attribute \src "libresoc.v:133205.9-133205.17" case 1'1 case end @@ -210200,14 +209996,14 @@ module \div0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5222 end - attribute \src "libresoc.v:133417.3-133425.6" - process $proc$libresoc.v:133417$5224 + attribute \src "libresoc.v:133213.3-133221.6" + process $proc$libresoc.v:133213$5224 assign { } { } assign { } { } assign $0\req_l_s_req$next[3:0]$5225 $1\req_l_s_req$next[3:0]$5226 - attribute \src "libresoc.v:133418.5-133418.29" + attribute \src "libresoc.v:133214.5-133214.29" switch \initial - attribute \src "libresoc.v:133418.9-133418.17" + attribute \src "libresoc.v:133214.9-133214.17" case 1'1 case end @@ -210223,14 +210019,14 @@ module \div0 sync always update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5225 end - attribute \src "libresoc.v:133426.3-133434.6" - process $proc$libresoc.v:133426$5227 + attribute \src "libresoc.v:133222.3-133230.6" + process $proc$libresoc.v:133222$5227 assign { } { } assign { } { } assign $0\req_l_r_req$next[3:0]$5228 $1\req_l_r_req$next[3:0]$5229 - attribute \src "libresoc.v:133427.5-133427.29" + attribute \src "libresoc.v:133223.5-133223.29" switch \initial - attribute \src "libresoc.v:133427.9-133427.17" + attribute \src "libresoc.v:133223.9-133223.17" case 1'1 case end @@ -210246,8 +210042,8 @@ module \div0 sync always update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5228 end - attribute \src "libresoc.v:133435.3-133473.6" - process $proc$libresoc.v:133435$5230 + attribute \src "libresoc.v:133231.3-133269.6" + process $proc$libresoc.v:133231$5230 assign { } { } assign { } { } assign { } { } @@ -210308,9 +210104,9 @@ module \div0 assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5243 $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5245 $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5246 $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 - attribute \src "libresoc.v:133436.5-133436.29" + attribute \src "libresoc.v:133232.5-133232.29" switch \initial - attribute \src "libresoc.v:133436.9-133436.17" + attribute \src "libresoc.v:133232.9-133232.17" case 1'1 case end @@ -210401,8 +210197,8 @@ module \div0 update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5247 update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5248 end - attribute \src "libresoc.v:133474.3-133495.6" - process $proc$libresoc.v:133474$5273 + attribute \src "libresoc.v:133270.3-133291.6" + process $proc$libresoc.v:133270$5273 assign { } { } assign { } { } assign { } { } @@ -210412,9 +210208,9 @@ module \div0 assign $0\data_r0__o$next[63:0]$5274 $2\data_r0__o$next[63:0]$5278 assign { } { } assign $0\data_r0__o_ok$next[0:0]$5275 $3\data_r0__o_ok$next[0:0]$5280 - attribute \src "libresoc.v:133475.5-133475.29" + attribute \src "libresoc.v:133271.5-133271.29" switch \initial - attribute \src "libresoc.v:133475.9-133475.17" + attribute \src "libresoc.v:133271.9-133271.17" case 1'1 case end @@ -210453,8 +210249,8 @@ module \div0 update \data_r0__o$next $0\data_r0__o$next[63:0]$5274 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5275 end - attribute \src "libresoc.v:133496.3-133517.6" - process $proc$libresoc.v:133496$5281 + attribute \src "libresoc.v:133292.3-133313.6" + process $proc$libresoc.v:133292$5281 assign { } { } assign { } { } assign { } { } @@ -210464,9 +210260,9 @@ module \div0 assign $0\data_r1__cr_a$next[3:0]$5282 $2\data_r1__cr_a$next[3:0]$5286 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$5283 $3\data_r1__cr_a_ok$next[0:0]$5288 - attribute \src "libresoc.v:133497.5-133497.29" + attribute \src "libresoc.v:133293.5-133293.29" switch \initial - attribute \src "libresoc.v:133497.9-133497.17" + attribute \src "libresoc.v:133293.9-133293.17" case 1'1 case end @@ -210505,8 +210301,8 @@ module \div0 update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5282 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5283 end - attribute \src "libresoc.v:133518.3-133539.6" - process $proc$libresoc.v:133518$5289 + attribute \src "libresoc.v:133314.3-133335.6" + process $proc$libresoc.v:133314$5289 assign { } { } assign { } { } assign { } { } @@ -210516,9 +210312,9 @@ module \div0 assign $0\data_r2__xer_ov$next[1:0]$5290 $2\data_r2__xer_ov$next[1:0]$5294 assign { } { } assign $0\data_r2__xer_ov_ok$next[0:0]$5291 $3\data_r2__xer_ov_ok$next[0:0]$5296 - attribute \src "libresoc.v:133519.5-133519.29" + attribute \src "libresoc.v:133315.5-133315.29" switch \initial - attribute \src "libresoc.v:133519.9-133519.17" + attribute \src "libresoc.v:133315.9-133315.17" case 1'1 case end @@ -210557,8 +210353,8 @@ module \div0 update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5290 update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5291 end - attribute \src "libresoc.v:133540.3-133561.6" - process $proc$libresoc.v:133540$5297 + attribute \src "libresoc.v:133336.3-133357.6" + process $proc$libresoc.v:133336$5297 assign { } { } assign { } { } assign { } { } @@ -210568,9 +210364,9 @@ module \div0 assign $0\data_r3__xer_so$next[0:0]$5298 $2\data_r3__xer_so$next[0:0]$5302 assign { } { } assign $0\data_r3__xer_so_ok$next[0:0]$5299 $3\data_r3__xer_so_ok$next[0:0]$5304 - attribute \src "libresoc.v:133541.5-133541.29" + attribute \src "libresoc.v:133337.5-133337.29" switch \initial - attribute \src "libresoc.v:133541.9-133541.17" + attribute \src "libresoc.v:133337.9-133337.17" case 1'1 case end @@ -210609,14 +210405,14 @@ module \div0 update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5298 update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5299 end - attribute \src "libresoc.v:133562.3-133571.6" - process $proc$libresoc.v:133562$5305 + attribute \src "libresoc.v:133358.3-133367.6" + process $proc$libresoc.v:133358$5305 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$5306 $1\src_r0$next[63:0]$5307 - attribute \src "libresoc.v:133563.5-133563.29" + attribute \src "libresoc.v:133359.5-133359.29" switch \initial - attribute \src "libresoc.v:133563.9-133563.17" + attribute \src "libresoc.v:133359.9-133359.17" case 1'1 case end @@ -210632,14 +210428,14 @@ module \div0 sync always update \src_r0$next $0\src_r0$next[63:0]$5306 end - attribute \src "libresoc.v:133572.3-133581.6" - process $proc$libresoc.v:133572$5308 + attribute \src "libresoc.v:133368.3-133377.6" + process $proc$libresoc.v:133368$5308 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$5309 $1\src_r1$next[63:0]$5310 - attribute \src "libresoc.v:133573.5-133573.29" + attribute \src "libresoc.v:133369.5-133369.29" switch \initial - attribute \src "libresoc.v:133573.9-133573.17" + attribute \src "libresoc.v:133369.9-133369.17" case 1'1 case end @@ -210655,14 +210451,14 @@ module \div0 sync always update \src_r1$next $0\src_r1$next[63:0]$5309 end - attribute \src "libresoc.v:133582.3-133591.6" - process $proc$libresoc.v:133582$5311 + attribute \src "libresoc.v:133378.3-133387.6" + process $proc$libresoc.v:133378$5311 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$5312 $1\src_r2$next[0:0]$5313 - attribute \src "libresoc.v:133583.5-133583.29" + attribute \src "libresoc.v:133379.5-133379.29" switch \initial - attribute \src "libresoc.v:133583.9-133583.17" + attribute \src "libresoc.v:133379.9-133379.17" case 1'1 case end @@ -210678,14 +210474,14 @@ module \div0 sync always update \src_r2$next $0\src_r2$next[0:0]$5312 end - attribute \src "libresoc.v:133592.3-133600.6" - process $proc$libresoc.v:133592$5314 + attribute \src "libresoc.v:133388.3-133396.6" + process $proc$libresoc.v:133388$5314 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$5315 $1\alui_l_r_alui$next[0:0]$5316 - attribute \src "libresoc.v:133593.5-133593.29" + attribute \src "libresoc.v:133389.5-133389.29" switch \initial - attribute \src "libresoc.v:133593.9-133593.17" + attribute \src "libresoc.v:133389.9-133389.17" case 1'1 case end @@ -210701,14 +210497,14 @@ module \div0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5315 end - attribute \src "libresoc.v:133601.3-133609.6" - process $proc$libresoc.v:133601$5317 + attribute \src "libresoc.v:133397.3-133405.6" + process $proc$libresoc.v:133397$5317 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$5318 $1\alu_l_r_alu$next[0:0]$5319 - attribute \src "libresoc.v:133602.5-133602.29" + attribute \src "libresoc.v:133398.5-133398.29" switch \initial - attribute \src "libresoc.v:133602.9-133602.17" + attribute \src "libresoc.v:133398.9-133398.17" case 1'1 case end @@ -210724,14 +210520,14 @@ module \div0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5318 end - attribute \src "libresoc.v:133610.3-133619.6" - process $proc$libresoc.v:133610$5320 + attribute \src "libresoc.v:133406.3-133415.6" + process $proc$libresoc.v:133406$5320 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:133611.5-133611.29" + attribute \src "libresoc.v:133407.5-133407.29" switch \initial - attribute \src "libresoc.v:133611.9-133611.17" + attribute \src "libresoc.v:133407.9-133407.17" case 1'1 case end @@ -210747,14 +210543,14 @@ module \div0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:133620.3-133629.6" - process $proc$libresoc.v:133620$5321 + attribute \src "libresoc.v:133416.3-133425.6" + process $proc$libresoc.v:133416$5321 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:133621.5-133621.29" + attribute \src "libresoc.v:133417.5-133417.29" switch \initial - attribute \src "libresoc.v:133621.9-133621.17" + attribute \src "libresoc.v:133417.9-133417.17" case 1'1 case end @@ -210770,14 +210566,14 @@ module \div0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:133630.3-133639.6" - process $proc$libresoc.v:133630$5322 + attribute \src "libresoc.v:133426.3-133435.6" + process $proc$libresoc.v:133426$5322 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:133631.5-133631.29" + attribute \src "libresoc.v:133427.5-133427.29" switch \initial - attribute \src "libresoc.v:133631.9-133631.17" + attribute \src "libresoc.v:133427.9-133427.17" case 1'1 case end @@ -210793,14 +210589,14 @@ module \div0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:133640.3-133649.6" - process $proc$libresoc.v:133640$5323 + attribute \src "libresoc.v:133436.3-133445.6" + process $proc$libresoc.v:133436$5323 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:133641.5-133641.29" + attribute \src "libresoc.v:133437.5-133437.29" switch \initial - attribute \src "libresoc.v:133641.9-133641.17" + attribute \src "libresoc.v:133437.9-133437.17" case 1'1 case end @@ -210816,14 +210612,14 @@ module \div0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:133650.3-133658.6" - process $proc$libresoc.v:133650$5324 + attribute \src "libresoc.v:133446.3-133454.6" + process $proc$libresoc.v:133446$5324 assign { } { } assign { } { } assign $0\prev_wr_go$next[3:0]$5325 $1\prev_wr_go$next[3:0]$5326 - attribute \src "libresoc.v:133651.5-133651.29" + attribute \src "libresoc.v:133447.5-133447.29" switch \initial - attribute \src "libresoc.v:133651.9-133651.17" + attribute \src "libresoc.v:133447.9-133447.17" case 1'1 case end @@ -210839,69 +210635,69 @@ module \div0 sync always update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5325 end - connect \$100 $not$libresoc.v:133099$5092_Y - connect \$102 $not$libresoc.v:133100$5093_Y - connect \$104 $and$libresoc.v:133101$5094_Y - connect \$106 $not$libresoc.v:133102$5095_Y - connect \$108 $and$libresoc.v:133103$5096_Y - connect \$10 $and$libresoc.v:133104$5097_Y - connect \$110 $and$libresoc.v:133105$5098_Y - connect \$112 $and$libresoc.v:133106$5099_Y - connect \$114 $and$libresoc.v:133107$5100_Y - connect \$116 $and$libresoc.v:133108$5101_Y - connect \$118 $and$libresoc.v:133109$5102_Y - connect \$120 $and$libresoc.v:133110$5103_Y - connect \$122 $and$libresoc.v:133111$5104_Y - connect \$124 $and$libresoc.v:133112$5105_Y - connect \$126 $and$libresoc.v:133113$5106_Y - connect \$128 $and$libresoc.v:133114$5107_Y - connect \$12 $not$libresoc.v:133115$5108_Y - connect \$14 $and$libresoc.v:133116$5109_Y - connect \$16 $not$libresoc.v:133117$5110_Y - connect \$18 $and$libresoc.v:133118$5111_Y - connect \$20 $and$libresoc.v:133119$5112_Y - connect \$24 $not$libresoc.v:133120$5113_Y - connect \$26 $and$libresoc.v:133121$5114_Y - connect \$23 $reduce_or$libresoc.v:133122$5115_Y - connect \$22 $not$libresoc.v:133123$5116_Y - connect \$2 $and$libresoc.v:133124$5117_Y - connect \$30 $and$libresoc.v:133125$5118_Y - connect \$32 $reduce_or$libresoc.v:133126$5119_Y - connect \$34 $reduce_or$libresoc.v:133127$5120_Y - connect \$36 $or$libresoc.v:133128$5121_Y - connect \$38 $not$libresoc.v:133129$5122_Y - connect \$40 $and$libresoc.v:133130$5123_Y - connect \$42 $and$libresoc.v:133131$5124_Y - connect \$44 $eq$libresoc.v:133132$5125_Y - connect \$46 $and$libresoc.v:133133$5126_Y - connect \$48 $eq$libresoc.v:133134$5127_Y - connect \$50 $and$libresoc.v:133135$5128_Y - connect \$52 $and$libresoc.v:133136$5129_Y - connect \$54 $and$libresoc.v:133137$5130_Y - connect \$56 $or$libresoc.v:133138$5131_Y - connect \$58 $or$libresoc.v:133139$5132_Y - connect \$5 $not$libresoc.v:133140$5133_Y - connect \$60 $or$libresoc.v:133141$5134_Y - connect \$62 $or$libresoc.v:133142$5135_Y - connect \$64 $and$libresoc.v:133143$5136_Y - connect \$66 $and$libresoc.v:133144$5137_Y - connect \$68 $or$libresoc.v:133145$5138_Y - connect \$70 $and$libresoc.v:133146$5139_Y - connect \$72 $and$libresoc.v:133147$5140_Y - connect \$74 $and$libresoc.v:133148$5141_Y - connect \$76 $and$libresoc.v:133149$5142_Y - connect \$78 $ternary$libresoc.v:133150$5143_Y - connect \$7 $or$libresoc.v:133151$5144_Y - connect \$80 $ternary$libresoc.v:133152$5145_Y - connect \$83 $ternary$libresoc.v:133153$5146_Y - connect \$86 $ternary$libresoc.v:133154$5147_Y - connect \$88 $ternary$libresoc.v:133155$5148_Y - connect \$4 $reduce_and$libresoc.v:133156$5149_Y - connect \$90 $ternary$libresoc.v:133157$5150_Y - connect \$92 $ternary$libresoc.v:133158$5151_Y - connect \$94 $and$libresoc.v:133159$5152_Y - connect \$96 $and$libresoc.v:133160$5153_Y - connect \$98 $and$libresoc.v:133161$5154_Y + connect \$100 $not$libresoc.v:132895$5092_Y + connect \$102 $not$libresoc.v:132896$5093_Y + connect \$104 $and$libresoc.v:132897$5094_Y + connect \$106 $not$libresoc.v:132898$5095_Y + connect \$108 $and$libresoc.v:132899$5096_Y + connect \$10 $and$libresoc.v:132900$5097_Y + connect \$110 $and$libresoc.v:132901$5098_Y + connect \$112 $and$libresoc.v:132902$5099_Y + connect \$114 $and$libresoc.v:132903$5100_Y + connect \$116 $and$libresoc.v:132904$5101_Y + connect \$118 $and$libresoc.v:132905$5102_Y + connect \$120 $and$libresoc.v:132906$5103_Y + connect \$122 $and$libresoc.v:132907$5104_Y + connect \$124 $and$libresoc.v:132908$5105_Y + connect \$126 $and$libresoc.v:132909$5106_Y + connect \$128 $and$libresoc.v:132910$5107_Y + connect \$12 $not$libresoc.v:132911$5108_Y + connect \$14 $and$libresoc.v:132912$5109_Y + connect \$16 $not$libresoc.v:132913$5110_Y + connect \$18 $and$libresoc.v:132914$5111_Y + connect \$20 $and$libresoc.v:132915$5112_Y + connect \$24 $not$libresoc.v:132916$5113_Y + connect \$26 $and$libresoc.v:132917$5114_Y + connect \$23 $reduce_or$libresoc.v:132918$5115_Y + connect \$22 $not$libresoc.v:132919$5116_Y + connect \$2 $and$libresoc.v:132920$5117_Y + connect \$30 $and$libresoc.v:132921$5118_Y + connect \$32 $reduce_or$libresoc.v:132922$5119_Y + connect \$34 $reduce_or$libresoc.v:132923$5120_Y + connect \$36 $or$libresoc.v:132924$5121_Y + connect \$38 $not$libresoc.v:132925$5122_Y + connect \$40 $and$libresoc.v:132926$5123_Y + connect \$42 $and$libresoc.v:132927$5124_Y + connect \$44 $eq$libresoc.v:132928$5125_Y + connect \$46 $and$libresoc.v:132929$5126_Y + connect \$48 $eq$libresoc.v:132930$5127_Y + connect \$50 $and$libresoc.v:132931$5128_Y + connect \$52 $and$libresoc.v:132932$5129_Y + connect \$54 $and$libresoc.v:132933$5130_Y + connect \$56 $or$libresoc.v:132934$5131_Y + connect \$58 $or$libresoc.v:132935$5132_Y + connect \$5 $not$libresoc.v:132936$5133_Y + connect \$60 $or$libresoc.v:132937$5134_Y + connect \$62 $or$libresoc.v:132938$5135_Y + connect \$64 $and$libresoc.v:132939$5136_Y + connect \$66 $and$libresoc.v:132940$5137_Y + connect \$68 $or$libresoc.v:132941$5138_Y + connect \$70 $and$libresoc.v:132942$5139_Y + connect \$72 $and$libresoc.v:132943$5140_Y + connect \$74 $and$libresoc.v:132944$5141_Y + connect \$76 $and$libresoc.v:132945$5142_Y + connect \$78 $ternary$libresoc.v:132946$5143_Y + connect \$7 $or$libresoc.v:132947$5144_Y + connect \$80 $ternary$libresoc.v:132948$5145_Y + connect \$83 $ternary$libresoc.v:132949$5146_Y + connect \$86 $ternary$libresoc.v:132950$5147_Y + connect \$88 $ternary$libresoc.v:132951$5148_Y + connect \$4 $reduce_and$libresoc.v:132952$5149_Y + connect \$90 $ternary$libresoc.v:132953$5150_Y + connect \$92 $ternary$libresoc.v:132954$5151_Y + connect \$94 $and$libresoc.v:132955$5152_Y + connect \$96 $and$libresoc.v:132956$5153_Y + connect \$98 $and$libresoc.v:132957$5154_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$120 @@ -210935,7 +210731,7 @@ module \div0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:133695.1-133704.10" +attribute \src "libresoc.v:133491.1-133500.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" attribute \generator "nMigen" @@ -210949,37 +210745,37 @@ module \div_state_init connect \o_dividend_quotient \dividend connect \o_q_bits_known 7'0000000 end -attribute \src "libresoc.v:133708.1-133790.10" +attribute \src "libresoc.v:133504.1-133586.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" attribute \generator "nMigen" module \div_state_next - attribute \src "libresoc.v:133709.7-133709.20" + attribute \src "libresoc.v:133505.7-133505.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133774.3-133785.6" + attribute \src "libresoc.v:133570.3-133581.6" wire width 128 $0\o_dividend_quotient[127:0] - attribute \src "libresoc.v:133762.3-133773.6" + attribute \src "libresoc.v:133558.3-133569.6" wire width 7 $0\o_q_bits_known[6:0] - attribute \src "libresoc.v:133750.3-133761.6" + attribute \src "libresoc.v:133546.3-133557.6" wire width 128 $0\value[127:0] - attribute \src "libresoc.v:133774.3-133785.6" + attribute \src "libresoc.v:133570.3-133581.6" wire width 128 $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:133762.3-133773.6" + attribute \src "libresoc.v:133558.3-133569.6" wire width 7 $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:133750.3-133761.6" + attribute \src "libresoc.v:133546.3-133557.6" wire width 128 $1\value[127:0] - attribute \src "libresoc.v:133744.18-133744.106" - wire width 8 $add$libresoc.v:133744$5372_Y - attribute \src "libresoc.v:133745.18-133745.109" - wire $ge$libresoc.v:133745$5373_Y - attribute \src "libresoc.v:133749.17-133749.108" - wire $ge$libresoc.v:133749$5377_Y - attribute \src "libresoc.v:133748.17-133748.101" - wire $not$libresoc.v:133748$5376_Y - attribute \src "libresoc.v:133746.17-133746.101" - wire width 127 $sshl$libresoc.v:133746$5374_Y - attribute \src "libresoc.v:133747.17-133747.109" - wire width 129 $sub$libresoc.v:133747$5375_Y + attribute \src "libresoc.v:133540.18-133540.106" + wire width 8 $add$libresoc.v:133540$5372_Y + attribute \src "libresoc.v:133541.18-133541.109" + wire $ge$libresoc.v:133541$5373_Y + attribute \src "libresoc.v:133545.17-133545.108" + wire $ge$libresoc.v:133545$5377_Y + attribute \src "libresoc.v:133544.17-133544.101" + wire $not$libresoc.v:133544$5376_Y + attribute \src "libresoc.v:133542.17-133542.101" + wire width 127 $sshl$libresoc.v:133542$5374_Y + attribute \src "libresoc.v:133543.17-133543.109" + wire width 129 $sub$libresoc.v:133543$5375_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 129 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" @@ -211004,7 +210800,7 @@ module \div_state_next wire width 128 input 3 \i_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 input 2 \i_q_bits_known - attribute \src "libresoc.v:133709.7-133709.15" + attribute \src "libresoc.v:133505.7-133505.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" wire \next_quotient_bit @@ -211015,7 +210811,7 @@ module \div_state_next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" wire width 128 \value attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - cell $add $add$libresoc.v:133744$5372 + cell $add $add$libresoc.v:133540$5372 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211023,10 +210819,10 @@ module \div_state_next parameter \Y_WIDTH 8 connect \A \i_q_bits_known connect \B 1'1 - connect \Y $add$libresoc.v:133744$5372_Y + connect \Y $add$libresoc.v:133540$5372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:133745$5373 + cell $ge $ge$libresoc.v:133541$5373 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211034,10 +210830,10 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:133745$5373_Y + connect \Y $ge$libresoc.v:133541$5373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:133749$5377 + cell $ge $ge$libresoc.v:133545$5377 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -211045,18 +210841,18 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:133749$5377_Y + connect \Y $ge$libresoc.v:133545$5377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - cell $not $not$libresoc.v:133748$5376 + cell $not $not$libresoc.v:133544$5376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \difference [127] - connect \Y $not$libresoc.v:133748$5376_Y + connect \Y $not$libresoc.v:133544$5376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sshl $sshl$libresoc.v:133746$5374 + cell $sshl $sshl$libresoc.v:133542$5374 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -211064,10 +210860,10 @@ module \div_state_next parameter \Y_WIDTH 127 connect \A \divisor connect \B 6'111111 - connect \Y $sshl$libresoc.v:133746$5374_Y + connect \Y $sshl$libresoc.v:133542$5374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sub $sub$libresoc.v:133747$5375 + cell $sub $sub$libresoc.v:133543$5375 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -211075,23 +210871,23 @@ module \div_state_next parameter \Y_WIDTH 129 connect \A \i_dividend_quotient connect \B \$2 - connect \Y $sub$libresoc.v:133747$5375_Y + connect \Y $sub$libresoc.v:133543$5375_Y end - attribute \src "libresoc.v:133709.7-133709.20" - process $proc$libresoc.v:133709$5381 + attribute \src "libresoc.v:133505.7-133505.20" + process $proc$libresoc.v:133505$5381 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133750.3-133761.6" - process $proc$libresoc.v:133750$5378 + attribute \src "libresoc.v:133546.3-133557.6" + process $proc$libresoc.v:133546$5378 assign { } { } assign $0\value[127:0] $1\value[127:0] - attribute \src "libresoc.v:133751.5-133751.29" + attribute \src "libresoc.v:133547.5-133547.29" switch \initial - attribute \src "libresoc.v:133751.9-133751.17" + attribute \src "libresoc.v:133547.9-133547.17" case 1'1 case end @@ -211109,13 +210905,13 @@ module \div_state_next sync always update \value $0\value[127:0] end - attribute \src "libresoc.v:133762.3-133773.6" - process $proc$libresoc.v:133762$5379 + attribute \src "libresoc.v:133558.3-133569.6" + process $proc$libresoc.v:133558$5379 assign { } { } assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:133763.5-133763.29" + attribute \src "libresoc.v:133559.5-133559.29" switch \initial - attribute \src "libresoc.v:133763.9-133763.17" + attribute \src "libresoc.v:133559.9-133559.17" case 1'1 case end @@ -211133,13 +210929,13 @@ module \div_state_next sync always update \o_q_bits_known $0\o_q_bits_known[6:0] end - attribute \src "libresoc.v:133774.3-133785.6" - process $proc$libresoc.v:133774$5380 + attribute \src "libresoc.v:133570.3-133581.6" + process $proc$libresoc.v:133570$5380 assign { } { } assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:133775.5-133775.29" + attribute \src "libresoc.v:133571.5-133571.29" switch \initial - attribute \src "libresoc.v:133775.9-133775.17" + attribute \src "libresoc.v:133571.9-133571.17" case 1'1 case end @@ -211157,18 +210953,18 @@ module \div_state_next sync always update \o_dividend_quotient $0\o_dividend_quotient[127:0] end - connect \$11 $add$libresoc.v:133744$5372_Y - connect \$13 $ge$libresoc.v:133745$5373_Y - connect \$2 $sshl$libresoc.v:133746$5374_Y - connect \$4 $sub$libresoc.v:133747$5375_Y - connect \$6 $not$libresoc.v:133748$5376_Y - connect \$8 $ge$libresoc.v:133749$5377_Y + connect \$11 $add$libresoc.v:133540$5372_Y + connect \$13 $ge$libresoc.v:133541$5373_Y + connect \$2 $sshl$libresoc.v:133542$5374_Y + connect \$4 $sub$libresoc.v:133543$5375_Y + connect \$6 $not$libresoc.v:133544$5376_Y + connect \$8 $ge$libresoc.v:133545$5377_Y connect \$1 \$4 connect \$10 \$11 connect \next_quotient_bit \$6 connect \difference \$4 [127:0] end -attribute \src "libresoc.v:133794.1-134037.10" +attribute \src "libresoc.v:133590.1-133833.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" attribute \generator "nMigen" @@ -211416,88 +211212,88 @@ module \dummy connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:134041.1-134172.10" +attribute \src "libresoc.v:133837.1-133968.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fast" attribute \generator "nMigen" module \fast - attribute \src "libresoc.v:134114.3-134119.6" - wire width 3 $0$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5393 - attribute \src "libresoc.v:134114.3-134119.6" - wire width 64 $0$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5394 - attribute \src "libresoc.v:134114.3-134119.6" - wire width 64 $0$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5395 - attribute \src "libresoc.v:134114.3-134119.6" - wire width 3 $0$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5396 - attribute \src "libresoc.v:134114.3-134119.6" - wire width 64 $0$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5397 - attribute \src "libresoc.v:134114.3-134119.6" - wire width 64 $0$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5398 - attribute \src "libresoc.v:134114.3-134119.6" + attribute \src "libresoc.v:133910.3-133915.6" + wire width 3 $0$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5393 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $0$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5394 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $0$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5395 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 3 $0$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5396 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $0$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5397 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $0$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5398 + attribute \src "libresoc.v:133910.3-133915.6" wire width 3 $0\_0_[2:0] - attribute \src "libresoc.v:134114.3-134119.6" + attribute \src "libresoc.v:133910.3-133915.6" wire width 3 $0\_1_[2:0] - attribute \src "libresoc.v:134042.7-134042.20" + attribute \src "libresoc.v:133838.7-133838.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134154.3-134163.6" + attribute \src "libresoc.v:133950.3-133959.6" wire width 64 $0\issue__data_o[63:0] - attribute \src "libresoc.v:134145.3-134153.6" + attribute \src "libresoc.v:133941.3-133949.6" wire $0\ren_delay$8$next[0:0]$5415 - attribute \src "libresoc.v:134122.3-134123.41" + attribute \src "libresoc.v:133918.3-133919.41" wire $0\ren_delay$8[0:0]$5408 - attribute \src "libresoc.v:134089.7-134089.27" + attribute \src "libresoc.v:133885.7-133885.27" wire $0\ren_delay$8[0:0]$5429 - attribute \src "libresoc.v:134126.3-134134.6" + attribute \src "libresoc.v:133922.3-133930.6" wire $0\ren_delay$next[0:0]$5411 - attribute \src "libresoc.v:134124.3-134125.35" + attribute \src "libresoc.v:133920.3-133921.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:134135.3-134144.6" + attribute \src "libresoc.v:133931.3-133940.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:134114.3-134119.6" - wire width 3 $1$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5399 - attribute \src "libresoc.v:134114.3-134119.6" - wire width 64 $1$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5400 - attribute \src "libresoc.v:134114.3-134119.6" - wire width 64 $1$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5401 - attribute \src "libresoc.v:134114.3-134119.6" - wire width 3 $1$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5402 - attribute \src "libresoc.v:134114.3-134119.6" - wire width 64 $1$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5403 - attribute \src "libresoc.v:134114.3-134119.6" - wire width 64 $1$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5404 - attribute \src "libresoc.v:134154.3-134163.6" + attribute \src "libresoc.v:133910.3-133915.6" + wire width 3 $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 3 $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 + attribute \src "libresoc.v:133950.3-133959.6" wire width 64 $1\issue__data_o[63:0] - attribute \src "libresoc.v:134145.3-134153.6" + attribute \src "libresoc.v:133941.3-133949.6" wire $1\ren_delay$8$next[0:0]$5416 - attribute \src "libresoc.v:134126.3-134134.6" + attribute \src "libresoc.v:133922.3-133930.6" wire $1\ren_delay$next[0:0]$5412 - attribute \src "libresoc.v:134087.7-134087.23" + attribute \src "libresoc.v:133883.7-133883.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:134135.3-134144.6" + attribute \src "libresoc.v:133931.3-133940.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:134120.26-134120.32" - wire width 64 $memrd$\memory$libresoc.v:134120$5405_DATA - attribute \src "libresoc.v:134121.30-134121.36" - wire width 64 $memrd$\memory$libresoc.v:134121$5406_DATA + attribute \src "libresoc.v:133916.26-133916.32" + wire width 64 $memrd$\memory$libresoc.v:133916$5405_DATA + attribute \src "libresoc.v:133917.30-133917.36" + wire width 64 $memrd$\memory$libresoc.v:133917$5406_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:134117$5390_ADDR + wire width 3 $memwr$\memory$libresoc.v:133913$5390_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:134117$5390_DATA + wire width 64 $memwr$\memory$libresoc.v:133913$5390_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:134117$5390_EN + wire width 64 $memwr$\memory$libresoc.v:133913$5390_EN attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:134118$5391_ADDR + wire width 3 $memwr$\memory$libresoc.v:133914$5391_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:134118$5391_DATA + wire width 64 $memwr$\memory$libresoc.v:133914$5391_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:134118$5391_EN - attribute \src "libresoc.v:134112.13-134112.16" + wire width 64 $memwr$\memory$libresoc.v:133914$5391_EN + attribute \src "libresoc.v:133908.13-133908.16" wire width 3 \_0_ - attribute \src "libresoc.v:134113.13-134113.16" + attribute \src "libresoc.v:133909.13-133909.16" wire width 3 \_1_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 14 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 12 \dest1__addr @@ -211505,7 +211301,7 @@ module \fast wire width 64 input 11 \dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \dest1__wen - attribute \src "libresoc.v:134042.7-134042.15" + attribute \src "libresoc.v:133838.7-133838.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \issue__addr @@ -211553,10 +211349,10 @@ module \fast wire width 64 output 8 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \src1__ren - attribute \src "libresoc.v:134101.14-134101.20" + attribute \src "libresoc.v:133897.14-133897.20" memory width 64 size 8 \memory - attribute \src "libresoc.v:134103.5-134103.37" - cell $meminit $meminit$\memory$libresoc.v:134103$5418 + attribute \src "libresoc.v:133899.5-133899.37" + cell $meminit $meminit$\memory$libresoc.v:133899$5418 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5418 @@ -211565,8 +211361,8 @@ module \fast connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:134104.5-134104.37" - cell $meminit $meminit$\memory$libresoc.v:134104$5419 + attribute \src "libresoc.v:133900.5-133900.37" + cell $meminit $meminit$\memory$libresoc.v:133900$5419 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5419 @@ -211575,8 +211371,8 @@ module \fast connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:134105.5-134105.37" - cell $meminit $meminit$\memory$libresoc.v:134105$5420 + attribute \src "libresoc.v:133901.5-133901.37" + cell $meminit $meminit$\memory$libresoc.v:133901$5420 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5420 @@ -211585,8 +211381,8 @@ module \fast connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:134106.5-134106.37" - cell $meminit $meminit$\memory$libresoc.v:134106$5421 + attribute \src "libresoc.v:133902.5-133902.37" + cell $meminit $meminit$\memory$libresoc.v:133902$5421 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5421 @@ -211595,8 +211391,8 @@ module \fast connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:134107.5-134107.37" - cell $meminit $meminit$\memory$libresoc.v:134107$5422 + attribute \src "libresoc.v:133903.5-133903.37" + cell $meminit $meminit$\memory$libresoc.v:133903$5422 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5422 @@ -211605,8 +211401,8 @@ module \fast connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:134108.5-134108.37" - cell $meminit $meminit$\memory$libresoc.v:134108$5423 + attribute \src "libresoc.v:133904.5-133904.37" + cell $meminit $meminit$\memory$libresoc.v:133904$5423 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5423 @@ -211615,8 +211411,8 @@ module \fast connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:134109.5-134109.37" - cell $meminit $meminit$\memory$libresoc.v:134109$5424 + attribute \src "libresoc.v:133905.5-133905.37" + cell $meminit $meminit$\memory$libresoc.v:133905$5424 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5424 @@ -211625,8 +211421,8 @@ module \fast connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:134110.5-134110.37" - cell $meminit $meminit$\memory$libresoc.v:134110$5425 + attribute \src "libresoc.v:133906.5-133906.37" + cell $meminit $meminit$\memory$libresoc.v:133906$5425 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5425 @@ -211635,8 +211431,8 @@ module \fast connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:134120.26-134120.32" - cell $memrd $memrd$\memory$libresoc.v:134120$5405 + attribute \src "libresoc.v:133916.26-133916.32" + cell $memrd $memrd$\memory$libresoc.v:133916$5405 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -211645,11 +211441,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:134120$5405_DATA + connect \DATA $memrd$\memory$libresoc.v:133916$5405_DATA connect \EN 1'x end - attribute \src "libresoc.v:134121.30-134121.36" - cell $memrd $memrd$\memory$libresoc.v:134121$5406 + attribute \src "libresoc.v:133917.30-133917.36" + cell $memrd $memrd$\memory$libresoc.v:133917$5406 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -211658,7 +211454,7 @@ module \fast parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:134121$5406_DATA + connect \DATA $memrd$\memory$libresoc.v:133917$5406_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" @@ -211666,32 +211462,32 @@ module \fast sync always sync init end - attribute \src "libresoc.v:134042.7-134042.20" - process $proc$libresoc.v:134042$5426 + attribute \src "libresoc.v:133838.7-133838.20" + process $proc$libresoc.v:133838$5426 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134087.7-134087.23" - process $proc$libresoc.v:134087$5427 + attribute \src "libresoc.v:133883.7-133883.23" + process $proc$libresoc.v:133883$5427 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:134089.7-134089.27" - process $proc$libresoc.v:134089$5428 + attribute \src "libresoc.v:133885.7-133885.27" + process $proc$libresoc.v:133885$5428 assign { } { } assign $0\ren_delay$8[0:0]$5429 1'0 sync always sync init update \ren_delay$8 $0\ren_delay$8[0:0]$5429 end - attribute \src "libresoc.v:134114.3-134119.6" - process $proc$libresoc.v:134114$5392 + attribute \src "libresoc.v:133910.3-133915.6" + process $proc$libresoc.v:133910$5392 assign { } { } assign { } { } assign { } { } @@ -211708,78 +211504,78 @@ module \fast assign { } { } assign $0\_0_[2:0] \memory_r_addr assign $0\_1_[2:0] \memory_r_addr$3 - assign $0$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5393 $1$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5399 - assign $0$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5394 $1$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5400 - assign $0$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5395 $1$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5401 - assign $0$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5396 $1$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5402 - assign $0$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5397 $1$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5403 - assign $0$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5398 $1$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5404 - attribute \src "libresoc.v:134117.5-134117.61" + assign $0$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5393 $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 + assign $0$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5394 $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 + assign $0$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5395 $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 + assign $0$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5396 $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 + assign $0$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5397 $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 + assign $0$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5398 $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 + attribute \src "libresoc.v:133913.5-133913.61" switch \memory_w_en - attribute \src "libresoc.v:134117.9-134117.20" + attribute \src "libresoc.v:133913.9-133913.20" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5399 \memory_w_addr - assign $1$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5400 \memory_w_data - assign $1$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5401 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 \memory_w_addr + assign $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 \memory_w_data + assign $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 64'1111111111111111111111111111111111111111111111111111111111111111 case - assign $1$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5399 3'xxx - assign $1$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5400 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5401 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 3'xxx + assign $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:134118.5-134118.73" + attribute \src "libresoc.v:133914.5-133914.73" switch \memory_w_en$5 - attribute \src "libresoc.v:134118.9-134118.23" + attribute \src "libresoc.v:133914.9-133914.23" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5402 \memory_w_addr$6 - assign $1$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5403 \memory_w_data$7 - assign $1$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5404 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 \memory_w_addr$6 + assign $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 \memory_w_data$7 + assign $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 64'1111111111111111111111111111111111111111111111111111111111111111 case - assign $1$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5402 3'xxx - assign $1$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5403 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5404 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 3'xxx + assign $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \coresync_clk update \_0_ $0\_0_[2:0] update \_1_ $0\_1_[2:0] - update $memwr$\memory$libresoc.v:134117$5390_ADDR $0$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5393 - update $memwr$\memory$libresoc.v:134117$5390_DATA $0$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5394 - update $memwr$\memory$libresoc.v:134117$5390_EN $0$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5395 - update $memwr$\memory$libresoc.v:134118$5391_ADDR $0$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5396 - update $memwr$\memory$libresoc.v:134118$5391_DATA $0$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5397 - update $memwr$\memory$libresoc.v:134118$5391_EN $0$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5398 - attribute \src "libresoc.v:134117.22-134117.60" - memwr \memory $1$memwr$\memory$libresoc.v:134117$5390_ADDR[2:0]$5399 $1$memwr$\memory$libresoc.v:134117$5390_DATA[63:0]$5400 $1$memwr$\memory$libresoc.v:134117$5390_EN[63:0]$5401 0' - attribute \src "libresoc.v:134118.26-134118.71" - memwr \memory $1$memwr$\memory$libresoc.v:134118$5391_ADDR[2:0]$5402 $1$memwr$\memory$libresoc.v:134118$5391_DATA[63:0]$5403 $1$memwr$\memory$libresoc.v:134118$5391_EN[63:0]$5404 1'1 - end - attribute \src "libresoc.v:134122.3-134123.41" - process $proc$libresoc.v:134122$5407 + update $memwr$\memory$libresoc.v:133913$5390_ADDR $0$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5393 + update $memwr$\memory$libresoc.v:133913$5390_DATA $0$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5394 + update $memwr$\memory$libresoc.v:133913$5390_EN $0$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5395 + update $memwr$\memory$libresoc.v:133914$5391_ADDR $0$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5396 + update $memwr$\memory$libresoc.v:133914$5391_DATA $0$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5397 + update $memwr$\memory$libresoc.v:133914$5391_EN $0$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5398 + attribute \src "libresoc.v:133913.22-133913.60" + memwr \memory $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 0' + attribute \src "libresoc.v:133914.26-133914.71" + memwr \memory $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 1'1 + end + attribute \src "libresoc.v:133918.3-133919.41" + process $proc$libresoc.v:133918$5407 assign { } { } assign $0\ren_delay$8[0:0]$5408 \ren_delay$8$next sync posedge \coresync_clk update \ren_delay$8 $0\ren_delay$8[0:0]$5408 end - attribute \src "libresoc.v:134124.3-134125.35" - process $proc$libresoc.v:134124$5409 + attribute \src "libresoc.v:133920.3-133921.35" + process $proc$libresoc.v:133920$5409 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:134126.3-134134.6" - process $proc$libresoc.v:134126$5410 + attribute \src "libresoc.v:133922.3-133930.6" + process $proc$libresoc.v:133922$5410 assign { } { } assign { } { } assign $0\ren_delay$next[0:0]$5411 $1\ren_delay$next[0:0]$5412 - attribute \src "libresoc.v:134127.5-134127.29" + attribute \src "libresoc.v:133923.5-133923.29" switch \initial - attribute \src "libresoc.v:134127.9-134127.17" + attribute \src "libresoc.v:133923.9-133923.17" case 1'1 case end @@ -211795,14 +211591,14 @@ module \fast sync always update \ren_delay$next $0\ren_delay$next[0:0]$5411 end - attribute \src "libresoc.v:134135.3-134144.6" - process $proc$libresoc.v:134135$5413 + attribute \src "libresoc.v:133931.3-133940.6" + process $proc$libresoc.v:133931$5413 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:134136.5-134136.29" + attribute \src "libresoc.v:133932.5-133932.29" switch \initial - attribute \src "libresoc.v:134136.9-134136.17" + attribute \src "libresoc.v:133932.9-133932.17" case 1'1 case end @@ -211818,14 +211614,14 @@ module \fast sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:134145.3-134153.6" - process $proc$libresoc.v:134145$5414 + attribute \src "libresoc.v:133941.3-133949.6" + process $proc$libresoc.v:133941$5414 assign { } { } assign { } { } assign $0\ren_delay$8$next[0:0]$5415 $1\ren_delay$8$next[0:0]$5416 - attribute \src "libresoc.v:134146.5-134146.29" + attribute \src "libresoc.v:133942.5-133942.29" switch \initial - attribute \src "libresoc.v:134146.9-134146.17" + attribute \src "libresoc.v:133942.9-133942.17" case 1'1 case end @@ -211841,14 +211637,14 @@ module \fast sync always update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5415 end - attribute \src "libresoc.v:134154.3-134163.6" - process $proc$libresoc.v:134154$5417 + attribute \src "libresoc.v:133950.3-133959.6" + process $proc$libresoc.v:133950$5417 assign { } { } assign { } { } assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] - attribute \src "libresoc.v:134155.5-134155.29" + attribute \src "libresoc.v:133951.5-133951.29" switch \initial - attribute \src "libresoc.v:134155.9-134155.17" + attribute \src "libresoc.v:133951.9-133951.17" case 1'1 case end @@ -211864,8 +211660,8 @@ module \fast sync always update \issue__data_o $0\issue__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:134120$5405_DATA - connect \memory_r_data$4 $memrd$\memory$libresoc.v:134121$5406_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:133916$5405_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:133917$5406_DATA connect \memory_w_data$7 \issue__data_i connect \memory_w_en$5 \issue__wen connect \memory_w_addr$6 \issue__addr$1 @@ -211875,14 +211671,14 @@ module \fast connect \memory_r_addr$3 \issue__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:134176.1-136126.10" +attribute \src "libresoc.v:133972.1-135922.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus" attribute \generator "nMigen" module \fus - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 330 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 257 \cr_a_ok @@ -213462,7 +213258,7 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 286 \xer_so_ok$131 attribute \module_not_derived 1 - attribute \src "libresoc.v:135758.8-135800.4" + attribute \src "libresoc.v:135554.8-135596.4" cell \alu0 \alu0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213507,7 +213303,7 @@ module \fus connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:135801.11-135828.4" + attribute \src "libresoc.v:135597.11-135624.4" cell \branch0 \branch0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213537,7 +213333,7 @@ module \fus connect \src3_i \src3_i$71 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135829.7-135854.4" + attribute \src "libresoc.v:135625.7-135650.4" cell \cr0 \cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213565,7 +213361,7 @@ module \fus connect \src6_i \src6_i$73 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135855.8-135894.4" + attribute \src "libresoc.v:135651.8-135690.4" cell \div0 \div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213607,7 +213403,7 @@ module \fus connect \xer_so_ok \xer_so_ok$130 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135895.9-135949.4" + attribute \src "libresoc.v:135691.9-135745.4" cell \ldst0 \ldst0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213664,7 +213460,7 @@ module \fus connect \src3_i \src3_i$49 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135950.12-135985.4" + attribute \src "libresoc.v:135746.12-135781.4" cell \logical0 \logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213702,7 +213498,7 @@ module \fus connect \src3_i \src3_i$61 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135986.8-136019.4" + attribute \src "libresoc.v:135782.8-135815.4" cell \mul0 \mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213738,7 +213534,7 @@ module \fus connect \xer_so_ok \xer_so_ok$131 end attribute \module_not_derived 1 - attribute \src "libresoc.v:136020.13-136058.4" + attribute \src "libresoc.v:135816.13-135854.4" cell \shiftrot0 \shiftrot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213779,7 +213575,7 @@ module \fus connect \xer_ca_ok \xer_ca_ok$121 end attribute \module_not_derived 1 - attribute \src "libresoc.v:136059.8-136091.4" + attribute \src "libresoc.v:135855.8-135887.4" cell \spr0 \spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213814,7 +213610,7 @@ module \fus connect \xer_so_ok \xer_so_ok$129 end attribute \module_not_derived 1 - attribute \src "libresoc.v:136092.9-136125.4" + attribute \src "libresoc.v:135888.9-135921.4" cell \trap0 \trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213850,37 +213646,37 @@ module \fus connect \src4_i \src4_i$78 end end -attribute \src "libresoc.v:136130.1-136188.10" +attribute \src "libresoc.v:135926.1-135984.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" attribute \generator "nMigen" module \idx_l - attribute \src "libresoc.v:136131.7-136131.20" + attribute \src "libresoc.v:135927.7-135927.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136176.3-136184.6" + attribute \src "libresoc.v:135972.3-135980.6" wire $0\q_int$next[0:0]$5441 - attribute \src "libresoc.v:136174.3-136175.27" + attribute \src "libresoc.v:135970.3-135971.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:136176.3-136184.6" + attribute \src "libresoc.v:135972.3-135980.6" wire $1\q_int$next[0:0]$5442 - attribute \src "libresoc.v:136155.7-136155.19" + attribute \src "libresoc.v:135951.7-135951.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:136166.17-136166.96" - wire $and$libresoc.v:136166$5431_Y - attribute \src "libresoc.v:136171.17-136171.96" - wire $and$libresoc.v:136171$5436_Y - attribute \src "libresoc.v:136168.18-136168.95" - wire $not$libresoc.v:136168$5433_Y - attribute \src "libresoc.v:136170.17-136170.94" - wire $not$libresoc.v:136170$5435_Y - attribute \src "libresoc.v:136173.17-136173.94" - wire $not$libresoc.v:136173$5438_Y - attribute \src "libresoc.v:136167.18-136167.100" - wire $or$libresoc.v:136167$5432_Y - attribute \src "libresoc.v:136169.18-136169.101" - wire $or$libresoc.v:136169$5434_Y - attribute \src "libresoc.v:136172.17-136172.99" - wire $or$libresoc.v:136172$5437_Y + attribute \src "libresoc.v:135962.17-135962.96" + wire $and$libresoc.v:135962$5431_Y + attribute \src "libresoc.v:135967.17-135967.96" + wire $and$libresoc.v:135967$5436_Y + attribute \src "libresoc.v:135964.18-135964.95" + wire $not$libresoc.v:135964$5433_Y + attribute \src "libresoc.v:135966.17-135966.94" + wire $not$libresoc.v:135966$5435_Y + attribute \src "libresoc.v:135969.17-135969.94" + wire $not$libresoc.v:135969$5438_Y + attribute \src "libresoc.v:135963.18-135963.100" + wire $or$libresoc.v:135963$5432_Y + attribute \src "libresoc.v:135965.18-135965.101" + wire $or$libresoc.v:135965$5434_Y + attribute \src "libresoc.v:135968.17-135968.99" + wire $or$libresoc.v:135968$5437_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -213897,11 +213693,11 @@ module \idx_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:136131.7-136131.15" + attribute \src "libresoc.v:135927.7-135927.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_idx_l @@ -213918,7 +213714,7 @@ module \idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:136166$5431 + cell $and $and$libresoc.v:135962$5431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213926,10 +213722,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:136166$5431_Y + connect \Y $and$libresoc.v:135962$5431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:136171$5436 + cell $and $and$libresoc.v:135967$5436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213937,34 +213733,34 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:136171$5436_Y + connect \Y $and$libresoc.v:135967$5436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:136168$5433 + cell $not $not$libresoc.v:135964$5433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_idx_l - connect \Y $not$libresoc.v:136168$5433_Y + connect \Y $not$libresoc.v:135964$5433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:136170$5435 + cell $not $not$libresoc.v:135966$5435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:136170$5435_Y + connect \Y $not$libresoc.v:135966$5435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:136173$5438 + cell $not $not$libresoc.v:135969$5438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:136173$5438_Y + connect \Y $not$libresoc.v:135969$5438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:136167$5432 + cell $or $or$libresoc.v:135963$5432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213972,10 +213768,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_idx_l - connect \Y $or$libresoc.v:136167$5432_Y + connect \Y $or$libresoc.v:135963$5432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:136169$5434 + cell $or $or$libresoc.v:135965$5434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213983,10 +213779,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_idx_l connect \B \q_int - connect \Y $or$libresoc.v:136169$5434_Y + connect \Y $or$libresoc.v:135965$5434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:136172$5437 + cell $or $or$libresoc.v:135968$5437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213994,39 +213790,39 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_idx_l - connect \Y $or$libresoc.v:136172$5437_Y + connect \Y $or$libresoc.v:135968$5437_Y end - attribute \src "libresoc.v:136131.7-136131.20" - process $proc$libresoc.v:136131$5443 + attribute \src "libresoc.v:135927.7-135927.20" + process $proc$libresoc.v:135927$5443 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136155.7-136155.19" - process $proc$libresoc.v:136155$5444 + attribute \src "libresoc.v:135951.7-135951.19" + process $proc$libresoc.v:135951$5444 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:136174.3-136175.27" - process $proc$libresoc.v:136174$5439 + attribute \src "libresoc.v:135970.3-135971.27" + process $proc$libresoc.v:135970$5439 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:136176.3-136184.6" - process $proc$libresoc.v:136176$5440 + attribute \src "libresoc.v:135972.3-135980.6" + process $proc$libresoc.v:135972$5440 assign { } { } assign { } { } assign $0\q_int$next[0:0]$5441 $1\q_int$next[0:0]$5442 - attribute \src "libresoc.v:136177.5-136177.29" + attribute \src "libresoc.v:135973.5-135973.29" switch \initial - attribute \src "libresoc.v:136177.9-136177.17" + attribute \src "libresoc.v:135973.9-135973.17" case 1'1 case end @@ -214042,185 +213838,185 @@ module \idx_l sync always update \q_int$next $0\q_int$next[0:0]$5441 end - connect \$9 $and$libresoc.v:136166$5431_Y - connect \$11 $or$libresoc.v:136167$5432_Y - connect \$13 $not$libresoc.v:136168$5433_Y - connect \$15 $or$libresoc.v:136169$5434_Y - connect \$1 $not$libresoc.v:136170$5435_Y - connect \$3 $and$libresoc.v:136171$5436_Y - connect \$5 $or$libresoc.v:136172$5437_Y - connect \$7 $not$libresoc.v:136173$5438_Y + connect \$9 $and$libresoc.v:135962$5431_Y + connect \$11 $or$libresoc.v:135963$5432_Y + connect \$13 $not$libresoc.v:135964$5433_Y + connect \$15 $or$libresoc.v:135965$5434_Y + connect \$1 $not$libresoc.v:135966$5435_Y + connect \$3 $and$libresoc.v:135967$5436_Y + connect \$5 $or$libresoc.v:135968$5437_Y + connect \$7 $not$libresoc.v:135969$5438_Y connect \qlq_idx_l \$15 connect \qn_idx_l \$13 connect \q_idx_l \$11 end -attribute \src "libresoc.v:136192.1-136571.10" +attribute \src "libresoc.v:135988.1-136367.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.imem" attribute \generator "nMigen" module \imem - attribute \src "libresoc.v:136523.3-136532.6" + attribute \src "libresoc.v:136319.3-136328.6" wire $0\a_busy_o[0:0] - attribute \src "libresoc.v:136503.3-136522.6" + attribute \src "libresoc.v:136299.3-136318.6" wire width 45 $0\f_badaddr_o$next[44:0]$5513 - attribute \src "libresoc.v:136334.3-136335.39" + attribute \src "libresoc.v:136130.3-136131.39" wire width 45 $0\f_badaddr_o[44:0] - attribute \src "libresoc.v:136533.3-136550.6" + attribute \src "libresoc.v:136329.3-136346.6" wire $0\f_busy_o[0:0] - attribute \src "libresoc.v:136480.3-136502.6" + attribute \src "libresoc.v:136276.3-136298.6" wire $0\f_fetch_err_o$next[0:0]$5508 - attribute \src "libresoc.v:136336.3-136337.43" + attribute \src "libresoc.v:136132.3-136133.43" wire $0\f_fetch_err_o[0:0] - attribute \src "libresoc.v:136551.3-136568.6" + attribute \src "libresoc.v:136347.3-136364.6" wire width 64 $0\f_instr_o[63:0] - attribute \src "libresoc.v:136457.3-136479.6" + attribute \src "libresoc.v:136253.3-136275.6" wire width 45 $0\ibus__adr$next[44:0]$5503 - attribute \src "libresoc.v:136338.3-136339.35" + attribute \src "libresoc.v:136134.3-136135.35" wire width 45 $0\ibus__adr[44:0] - attribute \src "libresoc.v:136348.3-136375.6" + attribute \src "libresoc.v:136144.3-136171.6" wire $0\ibus__cyc$next[0:0]$5479 - attribute \src "libresoc.v:136346.3-136347.35" + attribute \src "libresoc.v:136142.3-136143.35" wire $0\ibus__cyc[0:0] - attribute \src "libresoc.v:136404.3-136431.6" + attribute \src "libresoc.v:136200.3-136227.6" wire width 8 $0\ibus__sel$next[7:0]$5491 - attribute \src "libresoc.v:136342.3-136343.35" + attribute \src "libresoc.v:136138.3-136139.35" wire width 8 $0\ibus__sel[7:0] - attribute \src "libresoc.v:136376.3-136403.6" + attribute \src "libresoc.v:136172.3-136199.6" wire $0\ibus__stb$next[0:0]$5485 - attribute \src "libresoc.v:136344.3-136345.35" + attribute \src "libresoc.v:136140.3-136141.35" wire $0\ibus__stb[0:0] - attribute \src "libresoc.v:136432.3-136456.6" + attribute \src "libresoc.v:136228.3-136252.6" wire width 64 $0\ibus_rdata$next[63:0]$5497 - attribute \src "libresoc.v:136340.3-136341.37" + attribute \src "libresoc.v:136136.3-136137.37" wire width 64 $0\ibus_rdata[63:0] - attribute \src "libresoc.v:136193.7-136193.20" + attribute \src "libresoc.v:135989.7-135989.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136523.3-136532.6" + attribute \src "libresoc.v:136319.3-136328.6" wire $1\a_busy_o[0:0] - attribute \src "libresoc.v:136503.3-136522.6" + attribute \src "libresoc.v:136299.3-136318.6" wire width 45 $1\f_badaddr_o$next[44:0]$5514 - attribute \src "libresoc.v:136257.14-136257.44" + attribute \src "libresoc.v:136053.14-136053.44" wire width 45 $1\f_badaddr_o[44:0] - attribute \src "libresoc.v:136533.3-136550.6" + attribute \src "libresoc.v:136329.3-136346.6" wire $1\f_busy_o[0:0] - attribute \src "libresoc.v:136480.3-136502.6" + attribute \src "libresoc.v:136276.3-136298.6" wire $1\f_fetch_err_o$next[0:0]$5509 - attribute \src "libresoc.v:136264.7-136264.27" + attribute \src "libresoc.v:136060.7-136060.27" wire $1\f_fetch_err_o[0:0] - attribute \src "libresoc.v:136551.3-136568.6" + attribute \src "libresoc.v:136347.3-136364.6" wire width 64 $1\f_instr_o[63:0] - attribute \src "libresoc.v:136457.3-136479.6" + attribute \src "libresoc.v:136253.3-136275.6" wire width 45 $1\ibus__adr$next[44:0]$5504 - attribute \src "libresoc.v:136278.14-136278.42" + attribute \src "libresoc.v:136074.14-136074.42" wire width 45 $1\ibus__adr[44:0] - attribute \src "libresoc.v:136348.3-136375.6" + attribute \src "libresoc.v:136144.3-136171.6" wire $1\ibus__cyc$next[0:0]$5480 - attribute \src "libresoc.v:136283.7-136283.23" + attribute \src "libresoc.v:136079.7-136079.23" wire $1\ibus__cyc[0:0] - attribute \src "libresoc.v:136404.3-136431.6" + attribute \src "libresoc.v:136200.3-136227.6" wire width 8 $1\ibus__sel$next[7:0]$5492 - attribute \src "libresoc.v:136292.13-136292.30" + attribute \src "libresoc.v:136088.13-136088.30" wire width 8 $1\ibus__sel[7:0] - attribute \src "libresoc.v:136376.3-136403.6" + attribute \src "libresoc.v:136172.3-136199.6" wire $1\ibus__stb$next[0:0]$5486 - attribute \src "libresoc.v:136297.7-136297.23" + attribute \src "libresoc.v:136093.7-136093.23" wire $1\ibus__stb[0:0] - attribute \src "libresoc.v:136432.3-136456.6" + attribute \src "libresoc.v:136228.3-136252.6" wire width 64 $1\ibus_rdata$next[63:0]$5498 - attribute \src "libresoc.v:136301.14-136301.47" + attribute \src "libresoc.v:136097.14-136097.47" wire width 64 $1\ibus_rdata[63:0] - attribute \src "libresoc.v:136503.3-136522.6" + attribute \src "libresoc.v:136299.3-136318.6" wire width 45 $2\f_badaddr_o$next[44:0]$5515 - attribute \src "libresoc.v:136533.3-136550.6" + attribute \src "libresoc.v:136329.3-136346.6" wire $2\f_busy_o[0:0] - attribute \src "libresoc.v:136480.3-136502.6" + attribute \src "libresoc.v:136276.3-136298.6" wire $2\f_fetch_err_o$next[0:0]$5510 - attribute \src "libresoc.v:136551.3-136568.6" + attribute \src "libresoc.v:136347.3-136364.6" wire width 64 $2\f_instr_o[63:0] - attribute \src "libresoc.v:136457.3-136479.6" + attribute \src "libresoc.v:136253.3-136275.6" wire width 45 $2\ibus__adr$next[44:0]$5505 - attribute \src "libresoc.v:136348.3-136375.6" + attribute \src "libresoc.v:136144.3-136171.6" wire $2\ibus__cyc$next[0:0]$5481 - attribute \src "libresoc.v:136404.3-136431.6" + attribute \src "libresoc.v:136200.3-136227.6" wire width 8 $2\ibus__sel$next[7:0]$5493 - attribute \src "libresoc.v:136376.3-136403.6" + attribute \src "libresoc.v:136172.3-136199.6" wire $2\ibus__stb$next[0:0]$5487 - attribute \src "libresoc.v:136432.3-136456.6" + attribute \src "libresoc.v:136228.3-136252.6" wire width 64 $2\ibus_rdata$next[63:0]$5499 - attribute \src "libresoc.v:136503.3-136522.6" + attribute \src "libresoc.v:136299.3-136318.6" wire width 45 $3\f_badaddr_o$next[44:0]$5516 - attribute \src "libresoc.v:136480.3-136502.6" + attribute \src "libresoc.v:136276.3-136298.6" wire $3\f_fetch_err_o$next[0:0]$5511 - attribute \src "libresoc.v:136457.3-136479.6" + attribute \src "libresoc.v:136253.3-136275.6" wire width 45 $3\ibus__adr$next[44:0]$5506 - attribute \src "libresoc.v:136348.3-136375.6" + attribute \src "libresoc.v:136144.3-136171.6" wire $3\ibus__cyc$next[0:0]$5482 - attribute \src "libresoc.v:136404.3-136431.6" + attribute \src "libresoc.v:136200.3-136227.6" wire width 8 $3\ibus__sel$next[7:0]$5494 - attribute \src "libresoc.v:136376.3-136403.6" + attribute \src "libresoc.v:136172.3-136199.6" wire $3\ibus__stb$next[0:0]$5488 - attribute \src "libresoc.v:136432.3-136456.6" + attribute \src "libresoc.v:136228.3-136252.6" wire width 64 $3\ibus_rdata$next[63:0]$5500 - attribute \src "libresoc.v:136348.3-136375.6" + attribute \src "libresoc.v:136144.3-136171.6" wire $4\ibus__cyc$next[0:0]$5483 - attribute \src "libresoc.v:136404.3-136431.6" + attribute \src "libresoc.v:136200.3-136227.6" wire width 8 $4\ibus__sel$next[7:0]$5495 - attribute \src "libresoc.v:136376.3-136403.6" + attribute \src "libresoc.v:136172.3-136199.6" wire $4\ibus__stb$next[0:0]$5489 - attribute \src "libresoc.v:136432.3-136456.6" + attribute \src "libresoc.v:136228.3-136252.6" wire width 64 $4\ibus_rdata$next[63:0]$5501 - attribute \src "libresoc.v:136310.18-136310.110" - wire $and$libresoc.v:136310$5447_Y - attribute \src "libresoc.v:136316.18-136316.110" - wire $and$libresoc.v:136316$5453_Y - attribute \src "libresoc.v:136321.18-136321.110" - wire $and$libresoc.v:136321$5458_Y - attribute \src "libresoc.v:136324.17-136324.108" - wire $and$libresoc.v:136324$5461_Y - attribute \src "libresoc.v:136327.18-136327.110" - wire $and$libresoc.v:136327$5464_Y - attribute \src "libresoc.v:136328.18-136328.115" - wire $and$libresoc.v:136328$5465_Y - attribute \src "libresoc.v:136330.18-136330.115" - wire $and$libresoc.v:136330$5467_Y - attribute \src "libresoc.v:136309.18-136309.105" - wire $not$libresoc.v:136309$5446_Y - attribute \src "libresoc.v:136312.18-136312.105" - wire $not$libresoc.v:136312$5449_Y - attribute \src "libresoc.v:136313.17-136313.104" - wire $not$libresoc.v:136313$5450_Y - attribute \src "libresoc.v:136315.18-136315.105" - wire $not$libresoc.v:136315$5452_Y - attribute \src "libresoc.v:136318.18-136318.105" - wire $not$libresoc.v:136318$5455_Y - attribute \src "libresoc.v:136320.18-136320.105" - wire $not$libresoc.v:136320$5457_Y - attribute \src "libresoc.v:136323.18-136323.105" - wire $not$libresoc.v:136323$5460_Y - attribute \src "libresoc.v:136326.18-136326.105" - wire $not$libresoc.v:136326$5463_Y - attribute \src "libresoc.v:136329.18-136329.105" - wire $not$libresoc.v:136329$5466_Y - attribute \src "libresoc.v:136331.18-136331.105" - wire $not$libresoc.v:136331$5468_Y - attribute \src "libresoc.v:136333.17-136333.104" - wire $not$libresoc.v:136333$5470_Y - attribute \src "libresoc.v:136308.17-136308.103" - wire $or$libresoc.v:136308$5445_Y - attribute \src "libresoc.v:136311.18-136311.115" - wire $or$libresoc.v:136311$5448_Y - attribute \src "libresoc.v:136314.18-136314.106" - wire $or$libresoc.v:136314$5451_Y - attribute \src "libresoc.v:136317.18-136317.115" - wire $or$libresoc.v:136317$5454_Y - attribute \src "libresoc.v:136319.18-136319.106" - wire $or$libresoc.v:136319$5456_Y - attribute \src "libresoc.v:136322.18-136322.115" - wire $or$libresoc.v:136322$5459_Y - attribute \src "libresoc.v:136325.18-136325.106" - wire $or$libresoc.v:136325$5462_Y - attribute \src "libresoc.v:136332.17-136332.114" - wire $or$libresoc.v:136332$5469_Y + attribute \src "libresoc.v:136106.18-136106.110" + wire $and$libresoc.v:136106$5447_Y + attribute \src "libresoc.v:136112.18-136112.110" + wire $and$libresoc.v:136112$5453_Y + attribute \src "libresoc.v:136117.18-136117.110" + wire $and$libresoc.v:136117$5458_Y + attribute \src "libresoc.v:136120.17-136120.108" + wire $and$libresoc.v:136120$5461_Y + attribute \src "libresoc.v:136123.18-136123.110" + wire $and$libresoc.v:136123$5464_Y + attribute \src "libresoc.v:136124.18-136124.115" + wire $and$libresoc.v:136124$5465_Y + attribute \src "libresoc.v:136126.18-136126.115" + wire $and$libresoc.v:136126$5467_Y + attribute \src "libresoc.v:136105.18-136105.105" + wire $not$libresoc.v:136105$5446_Y + attribute \src "libresoc.v:136108.18-136108.105" + wire $not$libresoc.v:136108$5449_Y + attribute \src "libresoc.v:136109.17-136109.104" + wire $not$libresoc.v:136109$5450_Y + attribute \src "libresoc.v:136111.18-136111.105" + wire $not$libresoc.v:136111$5452_Y + attribute \src "libresoc.v:136114.18-136114.105" + wire $not$libresoc.v:136114$5455_Y + attribute \src "libresoc.v:136116.18-136116.105" + wire $not$libresoc.v:136116$5457_Y + attribute \src "libresoc.v:136119.18-136119.105" + wire $not$libresoc.v:136119$5460_Y + attribute \src "libresoc.v:136122.18-136122.105" + wire $not$libresoc.v:136122$5463_Y + attribute \src "libresoc.v:136125.18-136125.105" + wire $not$libresoc.v:136125$5466_Y + attribute \src "libresoc.v:136127.18-136127.105" + wire $not$libresoc.v:136127$5468_Y + attribute \src "libresoc.v:136129.17-136129.104" + wire $not$libresoc.v:136129$5470_Y + attribute \src "libresoc.v:136104.17-136104.103" + wire $or$libresoc.v:136104$5445_Y + attribute \src "libresoc.v:136107.18-136107.115" + wire $or$libresoc.v:136107$5448_Y + attribute \src "libresoc.v:136110.18-136110.106" + wire $or$libresoc.v:136110$5451_Y + attribute \src "libresoc.v:136113.18-136113.115" + wire $or$libresoc.v:136113$5454_Y + attribute \src "libresoc.v:136115.18-136115.106" + wire $or$libresoc.v:136115$5456_Y + attribute \src "libresoc.v:136118.18-136118.115" + wire $or$libresoc.v:136118$5459_Y + attribute \src "libresoc.v:136121.18-136121.106" + wire $or$libresoc.v:136121$5462_Y + attribute \src "libresoc.v:136128.17-136128.114" + wire $or$libresoc.v:136128$5469_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" @@ -214281,7 +214077,7 @@ module \imem wire \a_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" wire input 3 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 15 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" wire width 45 \f_badaddr_o @@ -214325,14 +214121,14 @@ module \imem wire width 64 \ibus_rdata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" wire width 64 \ibus_rdata$next - attribute \src "libresoc.v:136193.7-136193.15" + attribute \src "libresoc.v:135989.7-135989.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire input 7 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:136310$5447 + cell $and $and$libresoc.v:136106$5447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214340,10 +214136,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$11 - connect \Y $and$libresoc.v:136310$5447_Y + connect \Y $and$libresoc.v:136106$5447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:136316$5453 + cell $and $and$libresoc.v:136112$5453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214351,10 +214147,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$21 - connect \Y $and$libresoc.v:136316$5453_Y + connect \Y $and$libresoc.v:136112$5453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:136321$5458 + cell $and $and$libresoc.v:136117$5458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214362,10 +214158,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$31 - connect \Y $and$libresoc.v:136321$5458_Y + connect \Y $and$libresoc.v:136117$5458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:136324$5461 + cell $and $and$libresoc.v:136120$5461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214373,10 +214169,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$1 - connect \Y $and$libresoc.v:136324$5461_Y + connect \Y $and$libresoc.v:136120$5461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:136327$5464 + cell $and $and$libresoc.v:136123$5464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214384,10 +214180,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$41 - connect \Y $and$libresoc.v:136327$5464_Y + connect \Y $and$libresoc.v:136123$5464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:136328$5465 + cell $and $and$libresoc.v:136124$5465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214395,10 +214191,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:136328$5465_Y + connect \Y $and$libresoc.v:136124$5465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:136330$5467 + cell $and $and$libresoc.v:136126$5467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214406,98 +214202,98 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:136330$5467_Y + connect \Y $and$libresoc.v:136126$5467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:136309$5446 + cell $not $not$libresoc.v:136105$5446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:136309$5446_Y + connect \Y $not$libresoc.v:136105$5446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:136312$5449 + cell $not $not$libresoc.v:136108$5449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:136312$5449_Y + connect \Y $not$libresoc.v:136108$5449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:136313$5450 + cell $not $not$libresoc.v:136109$5450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:136313$5450_Y + connect \Y $not$libresoc.v:136109$5450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:136315$5452 + cell $not $not$libresoc.v:136111$5452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:136315$5452_Y + connect \Y $not$libresoc.v:136111$5452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:136318$5455 + cell $not $not$libresoc.v:136114$5455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:136318$5455_Y + connect \Y $not$libresoc.v:136114$5455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:136320$5457 + cell $not $not$libresoc.v:136116$5457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:136320$5457_Y + connect \Y $not$libresoc.v:136116$5457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:136323$5460 + cell $not $not$libresoc.v:136119$5460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:136323$5460_Y + connect \Y $not$libresoc.v:136119$5460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:136326$5463 + cell $not $not$libresoc.v:136122$5463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:136326$5463_Y + connect \Y $not$libresoc.v:136122$5463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:136329$5466 + cell $not $not$libresoc.v:136125$5466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:136329$5466_Y + connect \Y $not$libresoc.v:136125$5466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:136331$5468 + cell $not $not$libresoc.v:136127$5468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:136331$5468_Y + connect \Y $not$libresoc.v:136127$5468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:136333$5470 + cell $not $not$libresoc.v:136129$5470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:136333$5470_Y + connect \Y $not$libresoc.v:136129$5470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:136308$5445 + cell $or $or$libresoc.v:136104$5445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214505,10 +214301,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:136308$5445_Y + connect \Y $or$libresoc.v:136104$5445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:136311$5448 + cell $or $or$libresoc.v:136107$5448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214516,10 +214312,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:136311$5448_Y + connect \Y $or$libresoc.v:136107$5448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:136314$5451 + cell $or $or$libresoc.v:136110$5451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214527,10 +214323,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$15 connect \B \$17 - connect \Y $or$libresoc.v:136314$5451_Y + connect \Y $or$libresoc.v:136110$5451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:136317$5454 + cell $or $or$libresoc.v:136113$5454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214538,10 +214334,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:136317$5454_Y + connect \Y $or$libresoc.v:136113$5454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:136319$5456 + cell $or $or$libresoc.v:136115$5456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214549,10 +214345,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$25 connect \B \$27 - connect \Y $or$libresoc.v:136319$5456_Y + connect \Y $or$libresoc.v:136115$5456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:136322$5459 + cell $or $or$libresoc.v:136118$5459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214560,10 +214356,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:136322$5459_Y + connect \Y $or$libresoc.v:136118$5459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:136325$5462 + cell $or $or$libresoc.v:136121$5462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214571,10 +214367,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$35 connect \B \$37 - connect \Y $or$libresoc.v:136325$5462_Y + connect \Y $or$libresoc.v:136121$5462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:136332$5469 + cell $or $or$libresoc.v:136128$5469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214582,130 +214378,130 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:136332$5469_Y + connect \Y $or$libresoc.v:136128$5469_Y end - attribute \src "libresoc.v:136193.7-136193.20" - process $proc$libresoc.v:136193$5520 + attribute \src "libresoc.v:135989.7-135989.20" + process $proc$libresoc.v:135989$5520 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136257.14-136257.44" - process $proc$libresoc.v:136257$5521 + attribute \src "libresoc.v:136053.14-136053.44" + process $proc$libresoc.v:136053$5521 assign { } { } assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \f_badaddr_o $1\f_badaddr_o[44:0] end - attribute \src "libresoc.v:136264.7-136264.27" - process $proc$libresoc.v:136264$5522 + attribute \src "libresoc.v:136060.7-136060.27" + process $proc$libresoc.v:136060$5522 assign { } { } assign $1\f_fetch_err_o[0:0] 1'0 sync always sync init update \f_fetch_err_o $1\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:136278.14-136278.42" - process $proc$libresoc.v:136278$5523 + attribute \src "libresoc.v:136074.14-136074.42" + process $proc$libresoc.v:136074$5523 assign { } { } assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \ibus__adr $1\ibus__adr[44:0] end - attribute \src "libresoc.v:136283.7-136283.23" - process $proc$libresoc.v:136283$5524 + attribute \src "libresoc.v:136079.7-136079.23" + process $proc$libresoc.v:136079$5524 assign { } { } assign $1\ibus__cyc[0:0] 1'0 sync always sync init update \ibus__cyc $1\ibus__cyc[0:0] end - attribute \src "libresoc.v:136292.13-136292.30" - process $proc$libresoc.v:136292$5525 + attribute \src "libresoc.v:136088.13-136088.30" + process $proc$libresoc.v:136088$5525 assign { } { } assign $1\ibus__sel[7:0] 8'00000000 sync always sync init update \ibus__sel $1\ibus__sel[7:0] end - attribute \src "libresoc.v:136297.7-136297.23" - process $proc$libresoc.v:136297$5526 + attribute \src "libresoc.v:136093.7-136093.23" + process $proc$libresoc.v:136093$5526 assign { } { } assign $1\ibus__stb[0:0] 1'0 sync always sync init update \ibus__stb $1\ibus__stb[0:0] end - attribute \src "libresoc.v:136301.14-136301.47" - process $proc$libresoc.v:136301$5527 + attribute \src "libresoc.v:136097.14-136097.47" + process $proc$libresoc.v:136097$5527 assign { } { } assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ibus_rdata $1\ibus_rdata[63:0] end - attribute \src "libresoc.v:136334.3-136335.39" - process $proc$libresoc.v:136334$5471 + attribute \src "libresoc.v:136130.3-136131.39" + process $proc$libresoc.v:136130$5471 assign { } { } assign $0\f_badaddr_o[44:0] \f_badaddr_o$next sync posedge \clk update \f_badaddr_o $0\f_badaddr_o[44:0] end - attribute \src "libresoc.v:136336.3-136337.43" - process $proc$libresoc.v:136336$5472 + attribute \src "libresoc.v:136132.3-136133.43" + process $proc$libresoc.v:136132$5472 assign { } { } assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next sync posedge \clk update \f_fetch_err_o $0\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:136338.3-136339.35" - process $proc$libresoc.v:136338$5473 + attribute \src "libresoc.v:136134.3-136135.35" + process $proc$libresoc.v:136134$5473 assign { } { } assign $0\ibus__adr[44:0] \ibus__adr$next sync posedge \clk update \ibus__adr $0\ibus__adr[44:0] end - attribute \src "libresoc.v:136340.3-136341.37" - process $proc$libresoc.v:136340$5474 + attribute \src "libresoc.v:136136.3-136137.37" + process $proc$libresoc.v:136136$5474 assign { } { } assign $0\ibus_rdata[63:0] \ibus_rdata$next sync posedge \clk update \ibus_rdata $0\ibus_rdata[63:0] end - attribute \src "libresoc.v:136342.3-136343.35" - process $proc$libresoc.v:136342$5475 + attribute \src "libresoc.v:136138.3-136139.35" + process $proc$libresoc.v:136138$5475 assign { } { } assign $0\ibus__sel[7:0] \ibus__sel$next sync posedge \clk update \ibus__sel $0\ibus__sel[7:0] end - attribute \src "libresoc.v:136344.3-136345.35" - process $proc$libresoc.v:136344$5476 + attribute \src "libresoc.v:136140.3-136141.35" + process $proc$libresoc.v:136140$5476 assign { } { } assign $0\ibus__stb[0:0] \ibus__stb$next sync posedge \clk update \ibus__stb $0\ibus__stb[0:0] end - attribute \src "libresoc.v:136346.3-136347.35" - process $proc$libresoc.v:136346$5477 + attribute \src "libresoc.v:136142.3-136143.35" + process $proc$libresoc.v:136142$5477 assign { } { } assign $0\ibus__cyc[0:0] \ibus__cyc$next sync posedge \clk update \ibus__cyc $0\ibus__cyc[0:0] end - attribute \src "libresoc.v:136348.3-136375.6" - process $proc$libresoc.v:136348$5478 + attribute \src "libresoc.v:136144.3-136171.6" + process $proc$libresoc.v:136144$5478 assign { } { } assign { } { } assign { } { } assign $0\ibus__cyc$next[0:0]$5479 $4\ibus__cyc$next[0:0]$5483 - attribute \src "libresoc.v:136349.5-136349.29" + attribute \src "libresoc.v:136145.5-136145.29" switch \initial - attribute \src "libresoc.v:136349.9-136349.17" + attribute \src "libresoc.v:136145.9-136145.17" case 1'1 case end @@ -214752,15 +214548,15 @@ module \imem sync always update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5479 end - attribute \src "libresoc.v:136376.3-136403.6" - process $proc$libresoc.v:136376$5484 + attribute \src "libresoc.v:136172.3-136199.6" + process $proc$libresoc.v:136172$5484 assign { } { } assign { } { } assign { } { } assign $0\ibus__stb$next[0:0]$5485 $4\ibus__stb$next[0:0]$5489 - attribute \src "libresoc.v:136377.5-136377.29" + attribute \src "libresoc.v:136173.5-136173.29" switch \initial - attribute \src "libresoc.v:136377.9-136377.17" + attribute \src "libresoc.v:136173.9-136173.17" case 1'1 case end @@ -214807,15 +214603,15 @@ module \imem sync always update \ibus__stb$next $0\ibus__stb$next[0:0]$5485 end - attribute \src "libresoc.v:136404.3-136431.6" - process $proc$libresoc.v:136404$5490 + attribute \src "libresoc.v:136200.3-136227.6" + process $proc$libresoc.v:136200$5490 assign { } { } assign { } { } assign { } { } assign $0\ibus__sel$next[7:0]$5491 $4\ibus__sel$next[7:0]$5495 - attribute \src "libresoc.v:136405.5-136405.29" + attribute \src "libresoc.v:136201.5-136201.29" switch \initial - attribute \src "libresoc.v:136405.9-136405.17" + attribute \src "libresoc.v:136201.9-136201.17" case 1'1 case end @@ -214862,15 +214658,15 @@ module \imem sync always update \ibus__sel$next $0\ibus__sel$next[7:0]$5491 end - attribute \src "libresoc.v:136432.3-136456.6" - process $proc$libresoc.v:136432$5496 + attribute \src "libresoc.v:136228.3-136252.6" + process $proc$libresoc.v:136228$5496 assign { } { } assign { } { } assign { } { } assign $0\ibus_rdata$next[63:0]$5497 $4\ibus_rdata$next[63:0]$5501 - attribute \src "libresoc.v:136433.5-136433.29" + attribute \src "libresoc.v:136229.5-136229.29" switch \initial - attribute \src "libresoc.v:136433.9-136433.17" + attribute \src "libresoc.v:136229.9-136229.17" case 1'1 case end @@ -214913,15 +214709,15 @@ module \imem sync always update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5497 end - attribute \src "libresoc.v:136457.3-136479.6" - process $proc$libresoc.v:136457$5502 + attribute \src "libresoc.v:136253.3-136275.6" + process $proc$libresoc.v:136253$5502 assign { } { } assign { } { } assign { } { } assign $0\ibus__adr$next[44:0]$5503 $3\ibus__adr$next[44:0]$5506 - attribute \src "libresoc.v:136458.5-136458.29" + attribute \src "libresoc.v:136254.5-136254.29" switch \initial - attribute \src "libresoc.v:136458.9-136458.17" + attribute \src "libresoc.v:136254.9-136254.17" case 1'1 case end @@ -214958,15 +214754,15 @@ module \imem sync always update \ibus__adr$next $0\ibus__adr$next[44:0]$5503 end - attribute \src "libresoc.v:136480.3-136502.6" - process $proc$libresoc.v:136480$5507 + attribute \src "libresoc.v:136276.3-136298.6" + process $proc$libresoc.v:136276$5507 assign { } { } assign { } { } assign { } { } assign $0\f_fetch_err_o$next[0:0]$5508 $3\f_fetch_err_o$next[0:0]$5511 - attribute \src "libresoc.v:136481.5-136481.29" + attribute \src "libresoc.v:136277.5-136277.29" switch \initial - attribute \src "libresoc.v:136481.9-136481.17" + attribute \src "libresoc.v:136277.9-136277.17" case 1'1 case end @@ -215004,15 +214800,15 @@ module \imem sync always update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5508 end - attribute \src "libresoc.v:136503.3-136522.6" - process $proc$libresoc.v:136503$5512 + attribute \src "libresoc.v:136299.3-136318.6" + process $proc$libresoc.v:136299$5512 assign { } { } assign { } { } assign { } { } assign $0\f_badaddr_o$next[44:0]$5513 $3\f_badaddr_o$next[44:0]$5516 - attribute \src "libresoc.v:136504.5-136504.29" + attribute \src "libresoc.v:136300.5-136300.29" switch \initial - attribute \src "libresoc.v:136504.9-136504.17" + attribute \src "libresoc.v:136300.9-136300.17" case 1'1 case end @@ -215046,14 +214842,14 @@ module \imem sync always update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5513 end - attribute \src "libresoc.v:136523.3-136532.6" - process $proc$libresoc.v:136523$5517 + attribute \src "libresoc.v:136319.3-136328.6" + process $proc$libresoc.v:136319$5517 assign { } { } assign { } { } assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] - attribute \src "libresoc.v:136524.5-136524.29" + attribute \src "libresoc.v:136320.5-136320.29" switch \initial - attribute \src "libresoc.v:136524.9-136524.17" + attribute \src "libresoc.v:136320.9-136320.17" case 1'1 case end @@ -215069,14 +214865,14 @@ module \imem sync always update \a_busy_o $0\a_busy_o[0:0] end - attribute \src "libresoc.v:136533.3-136550.6" - process $proc$libresoc.v:136533$5518 + attribute \src "libresoc.v:136329.3-136346.6" + process $proc$libresoc.v:136329$5518 assign { } { } assign { } { } assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "libresoc.v:136534.5-136534.29" + attribute \src "libresoc.v:136330.5-136330.29" switch \initial - attribute \src "libresoc.v:136534.9-136534.17" + attribute \src "libresoc.v:136330.9-136330.17" case 1'1 case end @@ -215103,14 +214899,14 @@ module \imem sync always update \f_busy_o $0\f_busy_o[0:0] end - attribute \src "libresoc.v:136551.3-136568.6" - process $proc$libresoc.v:136551$5519 + attribute \src "libresoc.v:136347.3-136364.6" + process $proc$libresoc.v:136347$5519 assign { } { } assign { } { } assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "libresoc.v:136552.5-136552.29" + attribute \src "libresoc.v:136348.5-136348.29" switch \initial - attribute \src "libresoc.v:136552.9-136552.17" + attribute \src "libresoc.v:136348.9-136348.17" case 1'1 case end @@ -215136,52 +214932,52 @@ module \imem sync always update \f_instr_o $0\f_instr_o[63:0] end - connect \$9 $or$libresoc.v:136308$5445_Y - connect \$11 $not$libresoc.v:136309$5446_Y - connect \$13 $and$libresoc.v:136310$5447_Y - connect \$15 $or$libresoc.v:136311$5448_Y - connect \$17 $not$libresoc.v:136312$5449_Y - connect \$1 $not$libresoc.v:136313$5450_Y - connect \$19 $or$libresoc.v:136314$5451_Y - connect \$21 $not$libresoc.v:136315$5452_Y - connect \$23 $and$libresoc.v:136316$5453_Y - connect \$25 $or$libresoc.v:136317$5454_Y - connect \$27 $not$libresoc.v:136318$5455_Y - connect \$29 $or$libresoc.v:136319$5456_Y - connect \$31 $not$libresoc.v:136320$5457_Y - connect \$33 $and$libresoc.v:136321$5458_Y - connect \$35 $or$libresoc.v:136322$5459_Y - connect \$37 $not$libresoc.v:136323$5460_Y - connect \$3 $and$libresoc.v:136324$5461_Y - connect \$39 $or$libresoc.v:136325$5462_Y - connect \$41 $not$libresoc.v:136326$5463_Y - connect \$43 $and$libresoc.v:136327$5464_Y - connect \$45 $and$libresoc.v:136328$5465_Y - connect \$47 $not$libresoc.v:136329$5466_Y - connect \$49 $and$libresoc.v:136330$5467_Y - connect \$51 $not$libresoc.v:136331$5468_Y - connect \$5 $or$libresoc.v:136332$5469_Y - connect \$7 $not$libresoc.v:136333$5470_Y + connect \$9 $or$libresoc.v:136104$5445_Y + connect \$11 $not$libresoc.v:136105$5446_Y + connect \$13 $and$libresoc.v:136106$5447_Y + connect \$15 $or$libresoc.v:136107$5448_Y + connect \$17 $not$libresoc.v:136108$5449_Y + connect \$1 $not$libresoc.v:136109$5450_Y + connect \$19 $or$libresoc.v:136110$5451_Y + connect \$21 $not$libresoc.v:136111$5452_Y + connect \$23 $and$libresoc.v:136112$5453_Y + connect \$25 $or$libresoc.v:136113$5454_Y + connect \$27 $not$libresoc.v:136114$5455_Y + connect \$29 $or$libresoc.v:136115$5456_Y + connect \$31 $not$libresoc.v:136116$5457_Y + connect \$33 $and$libresoc.v:136117$5458_Y + connect \$35 $or$libresoc.v:136118$5459_Y + connect \$37 $not$libresoc.v:136119$5460_Y + connect \$3 $and$libresoc.v:136120$5461_Y + connect \$39 $or$libresoc.v:136121$5462_Y + connect \$41 $not$libresoc.v:136122$5463_Y + connect \$43 $and$libresoc.v:136123$5464_Y + connect \$45 $and$libresoc.v:136124$5465_Y + connect \$47 $not$libresoc.v:136125$5466_Y + connect \$49 $and$libresoc.v:136126$5467_Y + connect \$51 $not$libresoc.v:136127$5468_Y + connect \$5 $or$libresoc.v:136128$5469_Y + connect \$7 $not$libresoc.v:136129$5470_Y connect \a_stall_i 1'0 connect \f_stall_i 1'0 end -attribute \src "libresoc.v:136575.1-136902.10" +attribute \src "libresoc.v:136371.1-136698.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" attribute \generator "nMigen" module \input - attribute \src "libresoc.v:136865.3-136876.6" + attribute \src "libresoc.v:136661.3-136672.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:136576.7-136576.20" + attribute \src "libresoc.v:136372.7-136372.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136877.3-136895.6" + attribute \src "libresoc.v:136673.3-136691.6" wire width 2 $0\xer_ca$23[1:0]$5531 - attribute \src "libresoc.v:136865.3-136876.6" + attribute \src "libresoc.v:136661.3-136672.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:136877.3-136895.6" + attribute \src "libresoc.v:136673.3-136691.6" wire width 2 $1\xer_ca$23[1:0]$5532 - attribute \src "libresoc.v:136864.18-136864.100" - wire width 64 $not$libresoc.v:136864$5528_Y + attribute \src "libresoc.v:136660.18-136660.100" + wire width 64 $not$libresoc.v:136660$5528_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" @@ -215448,7 +215244,7 @@ module \input wire output 33 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:136576.7-136576.15" + attribute \src "libresoc.v:136372.7-136372.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -215471,28 +215267,28 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:136864$5528 + cell $not $not$libresoc.v:136660$5528 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:136864$5528_Y + connect \Y $not$libresoc.v:136660$5528_Y end - attribute \src "libresoc.v:136576.7-136576.20" - process $proc$libresoc.v:136576$5533 + attribute \src "libresoc.v:136372.7-136372.20" + process $proc$libresoc.v:136372$5533 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136865.3-136876.6" - process $proc$libresoc.v:136865$5529 + attribute \src "libresoc.v:136661.3-136672.6" + process $proc$libresoc.v:136661$5529 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:136866.5-136866.29" + attribute \src "libresoc.v:136662.5-136662.29" switch \initial - attribute \src "libresoc.v:136866.9-136866.17" + attribute \src "libresoc.v:136662.9-136662.17" case 1'1 case end @@ -215510,14 +215306,14 @@ module \input sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:136877.3-136895.6" - process $proc$libresoc.v:136877$5530 + attribute \src "libresoc.v:136673.3-136691.6" + process $proc$libresoc.v:136673$5530 assign { } { } assign { } { } assign $0\xer_ca$23[1:0]$5531 $1\xer_ca$23[1:0]$5532 - attribute \src "libresoc.v:136878.5-136878.29" + attribute \src "libresoc.v:136674.5-136674.29" switch \initial - attribute \src "libresoc.v:136878.9-136878.17" + attribute \src "libresoc.v:136674.9-136674.17" case 1'1 case end @@ -215541,7 +215337,7 @@ module \input sync always update \xer_ca$23 $0\xer_ca$23[1:0]$5531 end - connect \$24 $not$libresoc.v:136864$5528_Y + connect \$24 $not$libresoc.v:136660$5528_Y connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -215549,30 +215345,30 @@ module \input connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:136906.1-137234.10" +attribute \src "libresoc.v:136702.1-137030.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" attribute \generator "nMigen" module \input$113 - attribute \src "libresoc.v:137196.3-137207.6" + attribute \src "libresoc.v:136992.3-137003.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:136907.7-136907.20" + attribute \src "libresoc.v:136703.7-136703.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137208.3-137226.6" + attribute \src "libresoc.v:137004.3-137022.6" wire width 2 $0\xer_ca$23[1:0]$5537 - attribute \src "libresoc.v:137196.3-137207.6" + attribute \src "libresoc.v:136992.3-137003.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:137208.3-137226.6" + attribute \src "libresoc.v:137004.3-137022.6" wire width 2 $1\xer_ca$23[1:0]$5538 - attribute \src "libresoc.v:137195.18-137195.100" - wire width 64 $not$libresoc.v:137195$5534_Y + attribute \src "libresoc.v:136991.18-136991.100" + wire width 64 $not$libresoc.v:136991$5534_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:136907.7-136907.15" + attribute \src "libresoc.v:136703.7-136703.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -215855,28 +215651,28 @@ module \input$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:137195$5534 + cell $not $not$libresoc.v:136991$5534 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:137195$5534_Y + connect \Y $not$libresoc.v:136991$5534_Y end - attribute \src "libresoc.v:136907.7-136907.20" - process $proc$libresoc.v:136907$5539 + attribute \src "libresoc.v:136703.7-136703.20" + process $proc$libresoc.v:136703$5539 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137196.3-137207.6" - process $proc$libresoc.v:137196$5535 + attribute \src "libresoc.v:136992.3-137003.6" + process $proc$libresoc.v:136992$5535 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:137197.5-137197.29" + attribute \src "libresoc.v:136993.5-136993.29" switch \initial - attribute \src "libresoc.v:137197.9-137197.17" + attribute \src "libresoc.v:136993.9-136993.17" case 1'1 case end @@ -215894,14 +215690,14 @@ module \input$113 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:137208.3-137226.6" - process $proc$libresoc.v:137208$5536 + attribute \src "libresoc.v:137004.3-137022.6" + process $proc$libresoc.v:137004$5536 assign { } { } assign { } { } assign $0\xer_ca$23[1:0]$5537 $1\xer_ca$23[1:0]$5538 - attribute \src "libresoc.v:137209.5-137209.29" + attribute \src "libresoc.v:137005.5-137005.29" switch \initial - attribute \src "libresoc.v:137209.9-137209.17" + attribute \src "libresoc.v:137005.9-137005.17" case 1'1 case end @@ -215925,7 +215721,7 @@ module \input$113 sync always update \xer_ca$23 $0\xer_ca$23[1:0]$5537 end - connect \$24 $not$libresoc.v:137195$5534_Y + connect \$24 $not$libresoc.v:136991$5534_Y connect \rc$21 \rc connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid @@ -215934,26 +215730,26 @@ module \input$113 connect \b \rb connect \ra$19 \a end -attribute \src "libresoc.v:137238.1-137541.10" +attribute \src "libresoc.v:137034.1-137337.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" attribute \generator "nMigen" module \input$50 - attribute \src "libresoc.v:137523.3-137534.6" + attribute \src "libresoc.v:137319.3-137330.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:137239.7-137239.20" + attribute \src "libresoc.v:137035.7-137035.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137523.3-137534.6" + attribute \src "libresoc.v:137319.3-137330.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:137522.18-137522.100" - wire width 64 $not$libresoc.v:137522$5540_Y + attribute \src "libresoc.v:137318.18-137318.100" + wire width 64 $not$libresoc.v:137318$5540_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:137239.7-137239.15" + attribute \src "libresoc.v:137035.7-137035.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -216232,28 +216028,28 @@ module \input$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $not$libresoc.v:137522$5540 + cell $not $not$libresoc.v:137318$5540 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rb - connect \Y $not$libresoc.v:137522$5540_Y + connect \Y $not$libresoc.v:137318$5540_Y end - attribute \src "libresoc.v:137239.7-137239.20" - process $proc$libresoc.v:137239$5542 + attribute \src "libresoc.v:137035.7-137035.20" + process $proc$libresoc.v:137035$5542 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137523.3-137534.6" - process $proc$libresoc.v:137523$5541 + attribute \src "libresoc.v:137319.3-137330.6" + process $proc$libresoc.v:137319$5541 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:137524.5-137524.29" + attribute \src "libresoc.v:137320.5-137320.29" switch \initial - attribute \src "libresoc.v:137524.9-137524.17" + attribute \src "libresoc.v:137320.9-137320.17" case 1'1 case end @@ -216271,7 +216067,7 @@ module \input$50 sync always update \b $0\b[63:0] end - connect \$23 $not$libresoc.v:137522$5540_Y + connect \$23 $not$libresoc.v:137318$5540_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -216279,26 +216075,26 @@ module \input$50 connect \ra$20 \a connect \a \ra end -attribute \src "libresoc.v:137545.1-137848.10" +attribute \src "libresoc.v:137341.1-137644.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" attribute \generator "nMigen" module \input$78 - attribute \src "libresoc.v:137830.3-137841.6" + attribute \src "libresoc.v:137626.3-137637.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:137546.7-137546.20" + attribute \src "libresoc.v:137342.7-137342.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137830.3-137841.6" + attribute \src "libresoc.v:137626.3-137637.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:137829.18-137829.100" - wire width 64 $not$libresoc.v:137829$5543_Y + attribute \src "libresoc.v:137625.18-137625.100" + wire width 64 $not$libresoc.v:137625$5543_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:137546.7-137546.15" + attribute \src "libresoc.v:137342.7-137342.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -216577,28 +216373,28 @@ module \input$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:137829$5543 + cell $not $not$libresoc.v:137625$5543 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:137829$5543_Y + connect \Y $not$libresoc.v:137625$5543_Y end - attribute \src "libresoc.v:137546.7-137546.20" - process $proc$libresoc.v:137546$5545 + attribute \src "libresoc.v:137342.7-137342.20" + process $proc$libresoc.v:137342$5545 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137830.3-137841.6" - process $proc$libresoc.v:137830$5544 + attribute \src "libresoc.v:137626.3-137637.6" + process $proc$libresoc.v:137626$5544 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:137831.5-137831.29" + attribute \src "libresoc.v:137627.5-137627.29" switch \initial - attribute \src "libresoc.v:137831.9-137831.17" + attribute \src "libresoc.v:137627.9-137627.17" case 1'1 case end @@ -216616,7 +216412,7 @@ module \input$78 sync always update \a $0\a[63:0] end - connect \$23 $not$libresoc.v:137829$5543_Y + connect \$23 $not$libresoc.v:137625$5543_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -216624,7 +216420,7 @@ module \input$78 connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:137852.1-138108.10" +attribute \src "libresoc.v:137648.1-137904.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" attribute \generator "nMigen" @@ -216885,70 +216681,70 @@ module \input$95 connect \ra$14 \a connect \a \ra end -attribute \src "libresoc.v:138112.1-138251.10" +attribute \src "libresoc.v:137908.1-138047.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.int" attribute \generator "nMigen" module \int - attribute \src "libresoc.v:138197.3-138201.6" - wire width 5 $0$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5580 - attribute \src "libresoc.v:138197.3-138201.6" - wire width 64 $0$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5581 - attribute \src "libresoc.v:138197.3-138201.6" - wire width 64 $0$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5582 - attribute \src "libresoc.v:138197.3-138201.6" + attribute \src "libresoc.v:137993.3-137997.6" + wire width 5 $0$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5580 + attribute \src "libresoc.v:137993.3-137997.6" + wire width 64 $0$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5581 + attribute \src "libresoc.v:137993.3-137997.6" + wire width 64 $0$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5582 + attribute \src "libresoc.v:137993.3-137997.6" wire width 5 $0\_0_[4:0] - attribute \src "libresoc.v:138197.3-138201.6" + attribute \src "libresoc.v:137993.3-137997.6" wire width 5 $0\_1_[4:0] - attribute \src "libresoc.v:138217.3-138226.6" + attribute \src "libresoc.v:138013.3-138022.6" wire width 64 $0\dmi__data_o[63:0] - attribute \src "libresoc.v:138113.7-138113.20" + attribute \src "libresoc.v:137909.7-137909.20" wire $0\initial[0:0] - attribute \src "libresoc.v:138227.3-138235.6" + attribute \src "libresoc.v:138023.3-138031.6" wire $0\ren_delay$4$next[0:0]$5596 - attribute \src "libresoc.v:138204.3-138205.41" + attribute \src "libresoc.v:138000.3-138001.41" wire $0\ren_delay$4[0:0]$5589 - attribute \src "libresoc.v:138148.7-138148.27" + attribute \src "libresoc.v:137944.7-137944.27" wire $0\ren_delay$4[0:0]$5634 - attribute \src "libresoc.v:138208.3-138216.6" + attribute \src "libresoc.v:138004.3-138012.6" wire $0\ren_delay$next[0:0]$5592 - attribute \src "libresoc.v:138206.3-138207.35" + attribute \src "libresoc.v:138002.3-138003.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:138236.3-138245.6" - wire width 64 $0\src__data_o[63:0] - attribute \src "libresoc.v:138197.3-138201.6" - wire width 5 $1$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5583 - attribute \src "libresoc.v:138197.3-138201.6" - wire width 64 $1$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5584 - attribute \src "libresoc.v:138197.3-138201.6" - wire width 64 $1$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5585 - attribute \src "libresoc.v:138217.3-138226.6" + attribute \src "libresoc.v:138032.3-138041.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "libresoc.v:137993.3-137997.6" + wire width 5 $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 + attribute \src "libresoc.v:137993.3-137997.6" + wire width 64 $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 + attribute \src "libresoc.v:137993.3-137997.6" + wire width 64 $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 + attribute \src "libresoc.v:138013.3-138022.6" wire width 64 $1\dmi__data_o[63:0] - attribute \src "libresoc.v:138227.3-138235.6" + attribute \src "libresoc.v:138023.3-138031.6" wire $1\ren_delay$4$next[0:0]$5597 - attribute \src "libresoc.v:138208.3-138216.6" + attribute \src "libresoc.v:138004.3-138012.6" wire $1\ren_delay$next[0:0]$5593 - attribute \src "libresoc.v:138146.7-138146.23" + attribute \src "libresoc.v:137942.7-137942.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:138236.3-138245.6" - wire width 64 $1\src__data_o[63:0] - attribute \src "libresoc.v:138202.26-138202.32" - wire width 64 $memrd$\memory$libresoc.v:138202$5586_DATA - attribute \src "libresoc.v:138203.30-138203.36" - wire width 64 $memrd$\memory$libresoc.v:138203$5587_DATA + attribute \src "libresoc.v:138032.3-138041.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "libresoc.v:137998.26-137998.32" + wire width 64 $memrd$\memory$libresoc.v:137998$5586_DATA + attribute \src "libresoc.v:137999.30-137999.36" + wire width 64 $memrd$\memory$libresoc.v:137999$5587_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 5 $memwr$\memory$libresoc.v:138200$5578_ADDR + wire width 5 $memwr$\memory$libresoc.v:137996$5578_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:138200$5578_DATA + wire width 64 $memwr$\memory$libresoc.v:137996$5578_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:138200$5578_EN - attribute \src "libresoc.v:138195.13-138195.16" + wire width 64 $memwr$\memory$libresoc.v:137996$5578_EN + attribute \src "libresoc.v:137991.13-137991.16" wire width 5 \_0_ - attribute \src "libresoc.v:138196.13-138196.16" + attribute \src "libresoc.v:137992.13-137992.16" wire width 5 \_1_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 11 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 9 \dest1__addr @@ -216962,7 +216758,7 @@ module \int wire width 64 output 4 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 3 \dmi__ren - attribute \src "libresoc.v:138113.7-138113.15" + attribute \src "libresoc.v:137909.7-137909.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr @@ -216987,15 +216783,15 @@ module \int attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 input 6 \src__addr + wire width 5 input 6 \src1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 5 \src__data_o + wire width 64 output 5 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 7 \src__ren - attribute \src "libresoc.v:138160.14-138160.20" + wire input 7 \src1__ren + attribute \src "libresoc.v:137956.14-137956.20" memory width 64 size 32 \memory - attribute \src "libresoc.v:138162.5-138162.37" - cell $meminit $meminit$\memory$libresoc.v:138162$5599 + attribute \src "libresoc.v:137958.5-137958.37" + cell $meminit $meminit$\memory$libresoc.v:137958$5599 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5599 @@ -217004,8 +216800,8 @@ module \int connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138163.5-138163.37" - cell $meminit $meminit$\memory$libresoc.v:138163$5600 + attribute \src "libresoc.v:137959.5-137959.37" + cell $meminit $meminit$\memory$libresoc.v:137959$5600 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5600 @@ -217014,8 +216810,8 @@ module \int connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138164.5-138164.37" - cell $meminit $meminit$\memory$libresoc.v:138164$5601 + attribute \src "libresoc.v:137960.5-137960.37" + cell $meminit $meminit$\memory$libresoc.v:137960$5601 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5601 @@ -217024,8 +216820,8 @@ module \int connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138165.5-138165.37" - cell $meminit $meminit$\memory$libresoc.v:138165$5602 + attribute \src "libresoc.v:137961.5-137961.37" + cell $meminit $meminit$\memory$libresoc.v:137961$5602 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5602 @@ -217034,8 +216830,8 @@ module \int connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138166.5-138166.37" - cell $meminit $meminit$\memory$libresoc.v:138166$5603 + attribute \src "libresoc.v:137962.5-137962.37" + cell $meminit $meminit$\memory$libresoc.v:137962$5603 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5603 @@ -217044,8 +216840,8 @@ module \int connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138167.5-138167.37" - cell $meminit $meminit$\memory$libresoc.v:138167$5604 + attribute \src "libresoc.v:137963.5-137963.37" + cell $meminit $meminit$\memory$libresoc.v:137963$5604 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5604 @@ -217054,8 +216850,8 @@ module \int connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138168.5-138168.37" - cell $meminit $meminit$\memory$libresoc.v:138168$5605 + attribute \src "libresoc.v:137964.5-137964.37" + cell $meminit $meminit$\memory$libresoc.v:137964$5605 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5605 @@ -217064,8 +216860,8 @@ module \int connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138169.5-138169.37" - cell $meminit $meminit$\memory$libresoc.v:138169$5606 + attribute \src "libresoc.v:137965.5-137965.37" + cell $meminit $meminit$\memory$libresoc.v:137965$5606 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5606 @@ -217074,8 +216870,8 @@ module \int connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138170.5-138170.37" - cell $meminit $meminit$\memory$libresoc.v:138170$5607 + attribute \src "libresoc.v:137966.5-137966.37" + cell $meminit $meminit$\memory$libresoc.v:137966$5607 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5607 @@ -217084,8 +216880,8 @@ module \int connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138171.5-138171.37" - cell $meminit $meminit$\memory$libresoc.v:138171$5608 + attribute \src "libresoc.v:137967.5-137967.37" + cell $meminit $meminit$\memory$libresoc.v:137967$5608 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5608 @@ -217094,8 +216890,8 @@ module \int connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138172.5-138172.38" - cell $meminit $meminit$\memory$libresoc.v:138172$5609 + attribute \src "libresoc.v:137968.5-137968.38" + cell $meminit $meminit$\memory$libresoc.v:137968$5609 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5609 @@ -217104,8 +216900,8 @@ module \int connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138173.5-138173.38" - cell $meminit $meminit$\memory$libresoc.v:138173$5610 + attribute \src "libresoc.v:137969.5-137969.38" + cell $meminit $meminit$\memory$libresoc.v:137969$5610 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5610 @@ -217114,8 +216910,8 @@ module \int connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138174.5-138174.38" - cell $meminit $meminit$\memory$libresoc.v:138174$5611 + attribute \src "libresoc.v:137970.5-137970.38" + cell $meminit $meminit$\memory$libresoc.v:137970$5611 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5611 @@ -217124,8 +216920,8 @@ module \int connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138175.5-138175.38" - cell $meminit $meminit$\memory$libresoc.v:138175$5612 + attribute \src "libresoc.v:137971.5-137971.38" + cell $meminit $meminit$\memory$libresoc.v:137971$5612 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5612 @@ -217134,8 +216930,8 @@ module \int connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138176.5-138176.38" - cell $meminit $meminit$\memory$libresoc.v:138176$5613 + attribute \src "libresoc.v:137972.5-137972.38" + cell $meminit $meminit$\memory$libresoc.v:137972$5613 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5613 @@ -217144,8 +216940,8 @@ module \int connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138177.5-138177.38" - cell $meminit $meminit$\memory$libresoc.v:138177$5614 + attribute \src "libresoc.v:137973.5-137973.38" + cell $meminit $meminit$\memory$libresoc.v:137973$5614 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5614 @@ -217154,8 +216950,8 @@ module \int connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138178.5-138178.38" - cell $meminit $meminit$\memory$libresoc.v:138178$5615 + attribute \src "libresoc.v:137974.5-137974.38" + cell $meminit $meminit$\memory$libresoc.v:137974$5615 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5615 @@ -217164,8 +216960,8 @@ module \int connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138179.5-138179.38" - cell $meminit $meminit$\memory$libresoc.v:138179$5616 + attribute \src "libresoc.v:137975.5-137975.38" + cell $meminit $meminit$\memory$libresoc.v:137975$5616 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5616 @@ -217174,8 +216970,8 @@ module \int connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138180.5-138180.38" - cell $meminit $meminit$\memory$libresoc.v:138180$5617 + attribute \src "libresoc.v:137976.5-137976.38" + cell $meminit $meminit$\memory$libresoc.v:137976$5617 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5617 @@ -217184,8 +216980,8 @@ module \int connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138181.5-138181.38" - cell $meminit $meminit$\memory$libresoc.v:138181$5618 + attribute \src "libresoc.v:137977.5-137977.38" + cell $meminit $meminit$\memory$libresoc.v:137977$5618 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5618 @@ -217194,8 +216990,8 @@ module \int connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138182.5-138182.38" - cell $meminit $meminit$\memory$libresoc.v:138182$5619 + attribute \src "libresoc.v:137978.5-137978.38" + cell $meminit $meminit$\memory$libresoc.v:137978$5619 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5619 @@ -217204,8 +217000,8 @@ module \int connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138183.5-138183.38" - cell $meminit $meminit$\memory$libresoc.v:138183$5620 + attribute \src "libresoc.v:137979.5-137979.38" + cell $meminit $meminit$\memory$libresoc.v:137979$5620 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5620 @@ -217214,8 +217010,8 @@ module \int connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138184.5-138184.38" - cell $meminit $meminit$\memory$libresoc.v:138184$5621 + attribute \src "libresoc.v:137980.5-137980.38" + cell $meminit $meminit$\memory$libresoc.v:137980$5621 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5621 @@ -217224,8 +217020,8 @@ module \int connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138185.5-138185.38" - cell $meminit $meminit$\memory$libresoc.v:138185$5622 + attribute \src "libresoc.v:137981.5-137981.38" + cell $meminit $meminit$\memory$libresoc.v:137981$5622 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5622 @@ -217234,8 +217030,8 @@ module \int connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138186.5-138186.38" - cell $meminit $meminit$\memory$libresoc.v:138186$5623 + attribute \src "libresoc.v:137982.5-137982.38" + cell $meminit $meminit$\memory$libresoc.v:137982$5623 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5623 @@ -217244,8 +217040,8 @@ module \int connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138187.5-138187.38" - cell $meminit $meminit$\memory$libresoc.v:138187$5624 + attribute \src "libresoc.v:137983.5-137983.38" + cell $meminit $meminit$\memory$libresoc.v:137983$5624 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5624 @@ -217254,8 +217050,8 @@ module \int connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138188.5-138188.38" - cell $meminit $meminit$\memory$libresoc.v:138188$5625 + attribute \src "libresoc.v:137984.5-137984.38" + cell $meminit $meminit$\memory$libresoc.v:137984$5625 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5625 @@ -217264,8 +217060,8 @@ module \int connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138189.5-138189.38" - cell $meminit $meminit$\memory$libresoc.v:138189$5626 + attribute \src "libresoc.v:137985.5-137985.38" + cell $meminit $meminit$\memory$libresoc.v:137985$5626 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5626 @@ -217274,8 +217070,8 @@ module \int connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138190.5-138190.38" - cell $meminit $meminit$\memory$libresoc.v:138190$5627 + attribute \src "libresoc.v:137986.5-137986.38" + cell $meminit $meminit$\memory$libresoc.v:137986$5627 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5627 @@ -217284,8 +217080,8 @@ module \int connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138191.5-138191.38" - cell $meminit $meminit$\memory$libresoc.v:138191$5628 + attribute \src "libresoc.v:137987.5-137987.38" + cell $meminit $meminit$\memory$libresoc.v:137987$5628 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5628 @@ -217294,8 +217090,8 @@ module \int connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138192.5-138192.38" - cell $meminit $meminit$\memory$libresoc.v:138192$5629 + attribute \src "libresoc.v:137988.5-137988.38" + cell $meminit $meminit$\memory$libresoc.v:137988$5629 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5629 @@ -217304,8 +217100,8 @@ module \int connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138193.5-138193.38" - cell $meminit $meminit$\memory$libresoc.v:138193$5630 + attribute \src "libresoc.v:137989.5-137989.38" + cell $meminit $meminit$\memory$libresoc.v:137989$5630 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5630 @@ -217314,8 +217110,8 @@ module \int connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:138202.26-138202.32" - cell $memrd $memrd$\memory$libresoc.v:138202$5586 + attribute \src "libresoc.v:137998.26-137998.32" + cell $memrd $memrd$\memory$libresoc.v:137998$5586 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -217324,11 +217120,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:138202$5586_DATA + connect \DATA $memrd$\memory$libresoc.v:137998$5586_DATA connect \EN 1'x end - attribute \src "libresoc.v:138203.30-138203.36" - cell $memrd $memrd$\memory$libresoc.v:138203$5587 + attribute \src "libresoc.v:137999.30-137999.36" + cell $memrd $memrd$\memory$libresoc.v:137999$5587 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -217337,7 +217133,7 @@ module \int parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:138203$5587_DATA + connect \DATA $memrd$\memory$libresoc.v:137999$5587_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" @@ -217345,32 +217141,32 @@ module \int sync always sync init end - attribute \src "libresoc.v:138113.7-138113.20" - process $proc$libresoc.v:138113$5631 + attribute \src "libresoc.v:137909.7-137909.20" + process $proc$libresoc.v:137909$5631 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:138146.7-138146.23" - process $proc$libresoc.v:138146$5632 + attribute \src "libresoc.v:137942.7-137942.23" + process $proc$libresoc.v:137942$5632 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:138148.7-138148.27" - process $proc$libresoc.v:138148$5633 + attribute \src "libresoc.v:137944.7-137944.27" + process $proc$libresoc.v:137944$5633 assign { } { } assign $0\ren_delay$4[0:0]$5634 1'0 sync always sync init update \ren_delay$4 $0\ren_delay$4[0:0]$5634 end - attribute \src "libresoc.v:138197.3-138201.6" - process $proc$libresoc.v:138197$5579 + attribute \src "libresoc.v:137993.3-137997.6" + process $proc$libresoc.v:137993$5579 assign { } { } assign { } { } assign { } { } @@ -217381,55 +217177,55 @@ module \int assign { } { } assign $0\_0_[4:0] \memory_r_addr assign $0\_1_[4:0] \memory_r_addr$2 - assign $0$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5580 $1$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5583 - assign $0$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5581 $1$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5584 - assign $0$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5582 $1$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5585 - attribute \src "libresoc.v:138200.5-138200.61" + assign $0$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5580 $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 + assign $0$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5581 $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 + assign $0$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5582 $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 + attribute \src "libresoc.v:137996.5-137996.61" switch \memory_w_en - attribute \src "libresoc.v:138200.9-138200.20" + attribute \src "libresoc.v:137996.9-137996.20" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5583 \memory_w_addr - assign $1$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5584 \memory_w_data - assign $1$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5585 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 \memory_w_addr + assign $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 \memory_w_data + assign $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 64'1111111111111111111111111111111111111111111111111111111111111111 case - assign $1$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5583 5'xxxxx - assign $1$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5584 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5585 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 5'xxxxx + assign $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \coresync_clk update \_0_ $0\_0_[4:0] update \_1_ $0\_1_[4:0] - update $memwr$\memory$libresoc.v:138200$5578_ADDR $0$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5580 - update $memwr$\memory$libresoc.v:138200$5578_DATA $0$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5581 - update $memwr$\memory$libresoc.v:138200$5578_EN $0$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5582 - attribute \src "libresoc.v:138200.22-138200.60" - memwr \memory $1$memwr$\memory$libresoc.v:138200$5578_ADDR[4:0]$5583 $1$memwr$\memory$libresoc.v:138200$5578_DATA[63:0]$5584 $1$memwr$\memory$libresoc.v:138200$5578_EN[63:0]$5585 0' + update $memwr$\memory$libresoc.v:137996$5578_ADDR $0$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5580 + update $memwr$\memory$libresoc.v:137996$5578_DATA $0$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5581 + update $memwr$\memory$libresoc.v:137996$5578_EN $0$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5582 + attribute \src "libresoc.v:137996.22-137996.60" + memwr \memory $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 0' end - attribute \src "libresoc.v:138204.3-138205.41" - process $proc$libresoc.v:138204$5588 + attribute \src "libresoc.v:138000.3-138001.41" + process $proc$libresoc.v:138000$5588 assign { } { } assign $0\ren_delay$4[0:0]$5589 \ren_delay$4$next sync posedge \coresync_clk update \ren_delay$4 $0\ren_delay$4[0:0]$5589 end - attribute \src "libresoc.v:138206.3-138207.35" - process $proc$libresoc.v:138206$5590 + attribute \src "libresoc.v:138002.3-138003.35" + process $proc$libresoc.v:138002$5590 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:138208.3-138216.6" - process $proc$libresoc.v:138208$5591 + attribute \src "libresoc.v:138004.3-138012.6" + process $proc$libresoc.v:138004$5591 assign { } { } assign { } { } assign $0\ren_delay$next[0:0]$5592 $1\ren_delay$next[0:0]$5593 - attribute \src "libresoc.v:138209.5-138209.29" + attribute \src "libresoc.v:138005.5-138005.29" switch \initial - attribute \src "libresoc.v:138209.9-138209.17" + attribute \src "libresoc.v:138005.9-138005.17" case 1'1 case end @@ -217445,14 +217241,14 @@ module \int sync always update \ren_delay$next $0\ren_delay$next[0:0]$5592 end - attribute \src "libresoc.v:138217.3-138226.6" - process $proc$libresoc.v:138217$5594 + attribute \src "libresoc.v:138013.3-138022.6" + process $proc$libresoc.v:138013$5594 assign { } { } assign { } { } assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] - attribute \src "libresoc.v:138218.5-138218.29" + attribute \src "libresoc.v:138014.5-138014.29" switch \initial - attribute \src "libresoc.v:138218.9-138218.17" + attribute \src "libresoc.v:138014.9-138014.17" case 1'1 case end @@ -217468,14 +217264,14 @@ module \int sync always update \dmi__data_o $0\dmi__data_o[63:0] end - attribute \src "libresoc.v:138227.3-138235.6" - process $proc$libresoc.v:138227$5595 + attribute \src "libresoc.v:138023.3-138031.6" + process $proc$libresoc.v:138023$5595 assign { } { } assign { } { } assign $0\ren_delay$4$next[0:0]$5596 $1\ren_delay$4$next[0:0]$5597 - attribute \src "libresoc.v:138228.5-138228.29" + attribute \src "libresoc.v:138024.5-138024.29" switch \initial - attribute \src "libresoc.v:138228.9-138228.17" + attribute \src "libresoc.v:138024.9-138024.17" case 1'1 case end @@ -217486,19 +217282,19 @@ module \int assign { } { } assign $1\ren_delay$4$next[0:0]$5597 1'0 case - assign $1\ren_delay$4$next[0:0]$5597 \src__ren + assign $1\ren_delay$4$next[0:0]$5597 \src1__ren end sync always update \ren_delay$4$next $0\ren_delay$4$next[0:0]$5596 end - attribute \src "libresoc.v:138236.3-138245.6" - process $proc$libresoc.v:138236$5598 + attribute \src "libresoc.v:138032.3-138041.6" + process $proc$libresoc.v:138032$5598 assign { } { } assign { } { } - assign $0\src__data_o[63:0] $1\src__data_o[63:0] - attribute \src "libresoc.v:138237.5-138237.29" + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "libresoc.v:138033.5-138033.29" switch \initial - attribute \src "libresoc.v:138237.9-138237.17" + attribute \src "libresoc.v:138033.9-138033.17" case 1'1 case end @@ -217507,969 +217303,969 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src__data_o[63:0] \memory_r_data$3 + assign $1\src1__data_o[63:0] \memory_r_data$3 case - assign $1\src__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \src__data_o $0\src__data_o[63:0] + update \src1__data_o $0\src1__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:138202$5586_DATA - connect \memory_r_data$3 $memrd$\memory$libresoc.v:138203$5587_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:137998$5586_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:137999$5587_DATA connect \memory_w_data \dest1__data_i connect \memory_w_en \dest1__wen connect \memory_w_addr \dest1__addr - connect \memory_r_addr$2 \src__addr + connect \memory_r_addr$2 \src1__addr connect \memory_r_addr \dmi__addr end -attribute \src "libresoc.v:138255.1-140825.10" +attribute \src "libresoc.v:138051.1-140621.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag" attribute \generator "nMigen" module \jtag - attribute \src "libresoc.v:140239.3-140265.6" + attribute \src "libresoc.v:140035.3-140061.6" wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:139887.3-139902.6" + attribute \src "libresoc.v:139683.3-139698.6" wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:140420.3-140464.6" + attribute \src "libresoc.v:140216.3-140260.6" wire width 4 $0\dmi0__addr_i$next[3:0]$6023 - attribute \src "libresoc.v:139790.3-139791.41" + attribute \src "libresoc.v:139586.3-139587.41" wire width 4 $0\dmi0__addr_i[3:0] - attribute \src "libresoc.v:140518.3-140544.6" + attribute \src "libresoc.v:140314.3-140340.6" wire width 64 $0\dmi0__din$next[63:0]$6036 - attribute \src "libresoc.v:139786.3-139787.35" + attribute \src "libresoc.v:139582.3-139583.35" wire width 64 $0\dmi0__din[63:0] - attribute \src "libresoc.v:140089.3-140105.6" + attribute \src "libresoc.v:139885.3-139901.6" wire $0\dmi0_addrsr__oe$next[0:0]$5960 - attribute \src "libresoc.v:139818.3-139819.47" + attribute \src "libresoc.v:139614.3-139615.47" wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:140106.3-140126.6" + attribute \src "libresoc.v:139902.3-139922.6" wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5964 - attribute \src "libresoc.v:139816.3-139817.47" + attribute \src "libresoc.v:139612.3-139613.47" wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:140071.3-140079.6" + attribute \src "libresoc.v:139867.3-139875.6" wire $0\dmi0_addrsr_update_core$next[0:0]$5954 - attribute \src "libresoc.v:139822.3-139823.63" + attribute \src "libresoc.v:139618.3-139619.63" wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:140080.3-140088.6" + attribute \src "libresoc.v:139876.3-139884.6" wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5957 - attribute \src "libresoc.v:139820.3-139821.73" + attribute \src "libresoc.v:139616.3-139617.73" wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:140545.3-140573.6" + attribute \src "libresoc.v:140341.3-140369.6" wire width 64 $0\dmi0_datasr__i$next[63:0]$6041 - attribute \src "libresoc.v:139784.3-139785.45" + attribute \src "libresoc.v:139580.3-139581.45" wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:140145.3-140161.6" + attribute \src "libresoc.v:139941.3-139957.6" wire width 2 $0\dmi0_datasr__oe$next[1:0]$5975 - attribute \src "libresoc.v:139810.3-139811.47" + attribute \src "libresoc.v:139606.3-139607.47" wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:140162.3-140182.6" + attribute \src "libresoc.v:139958.3-139978.6" wire width 64 $0\dmi0_datasr_reg$next[63:0]$5979 - attribute \src "libresoc.v:139808.3-139809.47" + attribute \src "libresoc.v:139604.3-139605.47" wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:140127.3-140135.6" + attribute \src "libresoc.v:139923.3-139931.6" wire $0\dmi0_datasr_update_core$next[0:0]$5969 - attribute \src "libresoc.v:139814.3-139815.63" + attribute \src "libresoc.v:139610.3-139611.63" wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:140136.3-140144.6" + attribute \src "libresoc.v:139932.3-139940.6" wire $0\dmi0_datasr_update_core_prev$next[0:0]$5972 - attribute \src "libresoc.v:139812.3-139813.73" + attribute \src "libresoc.v:139608.3-139609.73" wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:140465.3-140517.6" + attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $0\fsm_state$455$next[2:0]$6029 - attribute \src "libresoc.v:139788.3-139789.45" + attribute \src "libresoc.v:139584.3-139585.45" wire width 3 $0\fsm_state$455[2:0]$5875 - attribute \src "libresoc.v:138853.13-138853.35" + attribute \src "libresoc.v:138649.13-138649.35" wire width 3 $0\fsm_state$455[2:0]$6078 - attribute \src "libresoc.v:140311.3-140363.6" + attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $0\fsm_state$next[2:0]$6006 - attribute \src "libresoc.v:139796.3-139797.35" + attribute \src "libresoc.v:139592.3-139593.35" wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:138256.7-138256.20" + attribute \src "libresoc.v:138052.7-138052.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140623.3-140643.6" + attribute \src "libresoc.v:140419.3-140439.6" wire width 130 $0\io_bd$next[129:0]$6061 - attribute \src "libresoc.v:139848.3-139849.27" + attribute \src "libresoc.v:139644.3-139645.27" wire width 130 $0\io_bd[129:0] - attribute \src "libresoc.v:140605.3-140622.6" + attribute \src "libresoc.v:140401.3-140418.6" wire width 130 $0\io_sr$next[129:0]$6057 - attribute \src "libresoc.v:139850.3-139851.27" + attribute \src "libresoc.v:139646.3-139647.27" wire width 130 $0\io_sr[129:0] - attribute \src "libresoc.v:140266.3-140310.6" + attribute \src "libresoc.v:140062.3-140106.6" wire width 29 $0\jtag_wb__adr$next[28:0]$6000 - attribute \src "libresoc.v:139798.3-139799.41" + attribute \src "libresoc.v:139594.3-139595.41" wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:140364.3-140390.6" + attribute \src "libresoc.v:140160.3-140186.6" wire width 64 $0\jtag_wb__dat_w$next[63:0]$6013 - attribute \src "libresoc.v:139794.3-139795.45" + attribute \src "libresoc.v:139590.3-139591.45" wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:139977.3-139993.6" + attribute \src "libresoc.v:139773.3-139789.6" wire $0\jtag_wb_addrsr__oe$next[0:0]$5930 - attribute \src "libresoc.v:139834.3-139835.53" + attribute \src "libresoc.v:139630.3-139631.53" wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:139994.3-140014.6" + attribute \src "libresoc.v:139790.3-139810.6" wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5934 - attribute \src "libresoc.v:139832.3-139833.53" + attribute \src "libresoc.v:139628.3-139629.53" wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:139959.3-139967.6" + attribute \src "libresoc.v:139755.3-139763.6" wire $0\jtag_wb_addrsr_update_core$next[0:0]$5924 - attribute \src "libresoc.v:139838.3-139839.69" + attribute \src "libresoc.v:139634.3-139635.69" wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:139968.3-139976.6" + attribute \src "libresoc.v:139764.3-139772.6" wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927 - attribute \src "libresoc.v:139836.3-139837.79" + attribute \src "libresoc.v:139632.3-139633.79" wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:140391.3-140419.6" + attribute \src "libresoc.v:140187.3-140215.6" wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6018 - attribute \src "libresoc.v:139792.3-139793.51" + attribute \src "libresoc.v:139588.3-139589.51" wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:140033.3-140049.6" + attribute \src "libresoc.v:139829.3-139845.6" wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5945 - attribute \src "libresoc.v:139826.3-139827.53" + attribute \src "libresoc.v:139622.3-139623.53" wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:140050.3-140070.6" + attribute \src "libresoc.v:139846.3-139866.6" wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5949 - attribute \src "libresoc.v:139824.3-139825.53" + attribute \src "libresoc.v:139620.3-139621.53" wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:140015.3-140023.6" + attribute \src "libresoc.v:139811.3-139819.6" wire $0\jtag_wb_datasr_update_core$next[0:0]$5939 - attribute \src "libresoc.v:139830.3-139831.69" + attribute \src "libresoc.v:139626.3-139627.69" wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:140024.3-140032.6" + attribute \src "libresoc.v:139820.3-139828.6" wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942 - attribute \src "libresoc.v:139828.3-139829.79" + attribute \src "libresoc.v:139624.3-139625.79" wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139921.3-139937.6" + attribute \src "libresoc.v:139717.3-139733.6" wire $0\sr0__oe$next[0:0]$5915 - attribute \src "libresoc.v:139842.3-139843.31" + attribute \src "libresoc.v:139638.3-139639.31" wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:139938.3-139958.6" + attribute \src "libresoc.v:139734.3-139754.6" wire width 3 $0\sr0_reg$next[2:0]$5919 - attribute \src "libresoc.v:139840.3-139841.31" + attribute \src "libresoc.v:139636.3-139637.31" wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:139903.3-139911.6" + attribute \src "libresoc.v:139699.3-139707.6" wire $0\sr0_update_core$next[0:0]$5909 - attribute \src "libresoc.v:139846.3-139847.47" + attribute \src "libresoc.v:139642.3-139643.47" wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:139912.3-139920.6" + attribute \src "libresoc.v:139708.3-139716.6" wire $0\sr0_update_core_prev$next[0:0]$5912 - attribute \src "libresoc.v:139844.3-139845.57" + attribute \src "libresoc.v:139640.3-139641.57" wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:140595.3-140604.6" + attribute \src "libresoc.v:140391.3-140400.6" wire width 3 $0\sr5__i[2:0] - attribute \src "libresoc.v:140201.3-140217.6" + attribute \src "libresoc.v:139997.3-140013.6" wire $0\sr5__oe$next[0:0]$5990 - attribute \src "libresoc.v:139802.3-139803.31" + attribute \src "libresoc.v:139598.3-139599.31" wire $0\sr5__oe[0:0] - attribute \src "libresoc.v:140218.3-140238.6" + attribute \src "libresoc.v:140014.3-140034.6" wire width 3 $0\sr5_reg$next[2:0]$5994 - attribute \src "libresoc.v:139800.3-139801.31" + attribute \src "libresoc.v:139596.3-139597.31" wire width 3 $0\sr5_reg[2:0] - attribute \src "libresoc.v:140183.3-140191.6" + attribute \src "libresoc.v:139979.3-139987.6" wire $0\sr5_update_core$next[0:0]$5984 - attribute \src "libresoc.v:139806.3-139807.47" + attribute \src "libresoc.v:139602.3-139603.47" wire $0\sr5_update_core[0:0] - attribute \src "libresoc.v:140192.3-140200.6" + attribute \src "libresoc.v:139988.3-139996.6" wire $0\sr5_update_core_prev$next[0:0]$5987 - attribute \src "libresoc.v:139804.3-139805.57" + attribute \src "libresoc.v:139600.3-139601.57" wire $0\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:140574.3-140594.6" + attribute \src "libresoc.v:140370.3-140390.6" wire $0\wb_dcache_en$next[0:0]$6046 - attribute \src "libresoc.v:139780.3-139781.41" + attribute \src "libresoc.v:139576.3-139577.41" wire $0\wb_dcache_en[0:0] - attribute \src "libresoc.v:140574.3-140594.6" + attribute \src "libresoc.v:140370.3-140390.6" wire $0\wb_icache_en$next[0:0]$6047 - attribute \src "libresoc.v:139778.3-139779.41" + attribute \src "libresoc.v:139574.3-139575.41" wire $0\wb_icache_en[0:0] - attribute \src "libresoc.v:140574.3-140594.6" + attribute \src "libresoc.v:140370.3-140390.6" wire $0\wb_sram_en$next[0:0]$6048 - attribute \src "libresoc.v:139782.3-139783.37" + attribute \src "libresoc.v:139578.3-139579.37" wire $0\wb_sram_en[0:0] - attribute \src "libresoc.v:140239.3-140265.6" + attribute \src "libresoc.v:140035.3-140061.6" wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:139887.3-139902.6" + attribute \src "libresoc.v:139683.3-139698.6" wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:140420.3-140464.6" + attribute \src "libresoc.v:140216.3-140260.6" wire width 4 $1\dmi0__addr_i$next[3:0]$6024 - attribute \src "libresoc.v:138766.13-138766.32" + attribute \src "libresoc.v:138562.13-138562.32" wire width 4 $1\dmi0__addr_i[3:0] - attribute \src "libresoc.v:140518.3-140544.6" + attribute \src "libresoc.v:140314.3-140340.6" wire width 64 $1\dmi0__din$next[63:0]$6037 - attribute \src "libresoc.v:138771.14-138771.46" + attribute \src "libresoc.v:138567.14-138567.46" wire width 64 $1\dmi0__din[63:0] - attribute \src "libresoc.v:140089.3-140105.6" + attribute \src "libresoc.v:139885.3-139901.6" wire $1\dmi0_addrsr__oe$next[0:0]$5961 - attribute \src "libresoc.v:138785.7-138785.29" + attribute \src "libresoc.v:138581.7-138581.29" wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:140106.3-140126.6" + attribute \src "libresoc.v:139902.3-139922.6" wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5965 - attribute \src "libresoc.v:138793.13-138793.36" + attribute \src "libresoc.v:138589.13-138589.36" wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:140071.3-140079.6" + attribute \src "libresoc.v:139867.3-139875.6" wire $1\dmi0_addrsr_update_core$next[0:0]$5955 - attribute \src "libresoc.v:138801.7-138801.37" + attribute \src "libresoc.v:138597.7-138597.37" wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:140080.3-140088.6" + attribute \src "libresoc.v:139876.3-139884.6" wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 - attribute \src "libresoc.v:138805.7-138805.42" + attribute \src "libresoc.v:138601.7-138601.42" wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:140545.3-140573.6" + attribute \src "libresoc.v:140341.3-140369.6" wire width 64 $1\dmi0_datasr__i$next[63:0]$6042 - attribute \src "libresoc.v:138809.14-138809.51" + attribute \src "libresoc.v:138605.14-138605.51" wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:140145.3-140161.6" + attribute \src "libresoc.v:139941.3-139957.6" wire width 2 $1\dmi0_datasr__oe$next[1:0]$5976 - attribute \src "libresoc.v:138815.13-138815.35" + attribute \src "libresoc.v:138611.13-138611.35" wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:140162.3-140182.6" + attribute \src "libresoc.v:139958.3-139978.6" wire width 64 $1\dmi0_datasr_reg$next[63:0]$5980 - attribute \src "libresoc.v:138823.14-138823.52" + attribute \src "libresoc.v:138619.14-138619.52" wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:140127.3-140135.6" + attribute \src "libresoc.v:139923.3-139931.6" wire $1\dmi0_datasr_update_core$next[0:0]$5970 - attribute \src "libresoc.v:138831.7-138831.37" + attribute \src "libresoc.v:138627.7-138627.37" wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:140136.3-140144.6" + attribute \src "libresoc.v:139932.3-139940.6" wire $1\dmi0_datasr_update_core_prev$next[0:0]$5973 - attribute \src "libresoc.v:138835.7-138835.42" + attribute \src "libresoc.v:138631.7-138631.42" wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:140465.3-140517.6" + attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $1\fsm_state$455$next[2:0]$6030 - attribute \src "libresoc.v:140311.3-140363.6" + attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $1\fsm_state$next[2:0]$6007 - attribute \src "libresoc.v:138851.13-138851.29" + attribute \src "libresoc.v:138647.13-138647.29" wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:140623.3-140643.6" + attribute \src "libresoc.v:140419.3-140439.6" wire width 130 $1\io_bd$next[129:0]$6062 - attribute \src "libresoc.v:139051.15-139051.61" + attribute \src "libresoc.v:138847.15-138847.61" wire width 130 $1\io_bd[129:0] - attribute \src "libresoc.v:140605.3-140622.6" + attribute \src "libresoc.v:140401.3-140418.6" wire width 130 $1\io_sr$next[129:0]$6058 - attribute \src "libresoc.v:139063.15-139063.61" + attribute \src "libresoc.v:138859.15-138859.61" wire width 130 $1\io_sr[129:0] - attribute \src "libresoc.v:140266.3-140310.6" + attribute \src "libresoc.v:140062.3-140106.6" wire width 29 $1\jtag_wb__adr$next[28:0]$6001 - attribute \src "libresoc.v:139072.14-139072.41" + attribute \src "libresoc.v:138868.14-138868.41" wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:140364.3-140390.6" + attribute \src "libresoc.v:140160.3-140186.6" wire width 64 $1\jtag_wb__dat_w$next[63:0]$6014 - attribute \src "libresoc.v:139081.14-139081.51" + attribute \src "libresoc.v:138877.14-138877.51" wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:139977.3-139993.6" + attribute \src "libresoc.v:139773.3-139789.6" wire $1\jtag_wb_addrsr__oe$next[0:0]$5931 - attribute \src "libresoc.v:139095.7-139095.32" + attribute \src "libresoc.v:138891.7-138891.32" wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:139994.3-140014.6" + attribute \src "libresoc.v:139790.3-139810.6" wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5935 - attribute \src "libresoc.v:139103.14-139103.47" + attribute \src "libresoc.v:138899.14-138899.47" wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:139959.3-139967.6" + attribute \src "libresoc.v:139755.3-139763.6" wire $1\jtag_wb_addrsr_update_core$next[0:0]$5925 - attribute \src "libresoc.v:139111.7-139111.40" + attribute \src "libresoc.v:138907.7-138907.40" wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:139968.3-139976.6" + attribute \src "libresoc.v:139764.3-139772.6" wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 - attribute \src "libresoc.v:139115.7-139115.45" + attribute \src "libresoc.v:138911.7-138911.45" wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:140391.3-140419.6" + attribute \src "libresoc.v:140187.3-140215.6" wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6019 - attribute \src "libresoc.v:139119.14-139119.54" + attribute \src "libresoc.v:138915.14-138915.54" wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:140033.3-140049.6" + attribute \src "libresoc.v:139829.3-139845.6" wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5946 - attribute \src "libresoc.v:139125.13-139125.38" + attribute \src "libresoc.v:138921.13-138921.38" wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:140050.3-140070.6" + attribute \src "libresoc.v:139846.3-139866.6" wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5950 - attribute \src "libresoc.v:139133.14-139133.55" + attribute \src "libresoc.v:138929.14-138929.55" wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:140015.3-140023.6" + attribute \src "libresoc.v:139811.3-139819.6" wire $1\jtag_wb_datasr_update_core$next[0:0]$5940 - attribute \src "libresoc.v:139141.7-139141.40" + attribute \src "libresoc.v:138937.7-138937.40" wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:140024.3-140032.6" + attribute \src "libresoc.v:139820.3-139828.6" wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 - attribute \src "libresoc.v:139145.7-139145.45" + attribute \src "libresoc.v:138941.7-138941.45" wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139921.3-139937.6" + attribute \src "libresoc.v:139717.3-139733.6" wire $1\sr0__oe$next[0:0]$5916 - attribute \src "libresoc.v:139479.7-139479.21" + attribute \src "libresoc.v:139275.7-139275.21" wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:139938.3-139958.6" + attribute \src "libresoc.v:139734.3-139754.6" wire width 3 $1\sr0_reg$next[2:0]$5920 - attribute \src "libresoc.v:139487.13-139487.27" + attribute \src "libresoc.v:139283.13-139283.27" wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:139903.3-139911.6" + attribute \src "libresoc.v:139699.3-139707.6" wire $1\sr0_update_core$next[0:0]$5910 - attribute \src "libresoc.v:139495.7-139495.29" + attribute \src "libresoc.v:139291.7-139291.29" wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:139912.3-139920.6" + attribute \src "libresoc.v:139708.3-139716.6" wire $1\sr0_update_core_prev$next[0:0]$5913 - attribute \src "libresoc.v:139499.7-139499.34" + attribute \src "libresoc.v:139295.7-139295.34" wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:140595.3-140604.6" + attribute \src "libresoc.v:140391.3-140400.6" wire width 3 $1\sr5__i[2:0] - attribute \src "libresoc.v:140201.3-140217.6" + attribute \src "libresoc.v:139997.3-140013.6" wire $1\sr5__oe$next[0:0]$5991 - attribute \src "libresoc.v:139509.7-139509.21" + attribute \src "libresoc.v:139305.7-139305.21" wire $1\sr5__oe[0:0] - attribute \src "libresoc.v:140218.3-140238.6" + attribute \src "libresoc.v:140014.3-140034.6" wire width 3 $1\sr5_reg$next[2:0]$5995 - attribute \src "libresoc.v:139517.13-139517.27" + attribute \src "libresoc.v:139313.13-139313.27" wire width 3 $1\sr5_reg[2:0] - attribute \src "libresoc.v:140183.3-140191.6" + attribute \src "libresoc.v:139979.3-139987.6" wire $1\sr5_update_core$next[0:0]$5985 - attribute \src "libresoc.v:139525.7-139525.29" + attribute \src "libresoc.v:139321.7-139321.29" wire $1\sr5_update_core[0:0] - attribute \src "libresoc.v:140192.3-140200.6" + attribute \src "libresoc.v:139988.3-139996.6" wire $1\sr5_update_core_prev$next[0:0]$5988 - attribute \src "libresoc.v:139529.7-139529.34" + attribute \src "libresoc.v:139325.7-139325.34" wire $1\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:140574.3-140594.6" + attribute \src "libresoc.v:140370.3-140390.6" wire $1\wb_dcache_en$next[0:0]$6049 - attribute \src "libresoc.v:139534.7-139534.26" + attribute \src "libresoc.v:139330.7-139330.26" wire $1\wb_dcache_en[0:0] - attribute \src "libresoc.v:140574.3-140594.6" + attribute \src "libresoc.v:140370.3-140390.6" wire $1\wb_icache_en$next[0:0]$6050 - attribute \src "libresoc.v:139539.7-139539.26" + attribute \src "libresoc.v:139335.7-139335.26" wire $1\wb_icache_en[0:0] - attribute \src "libresoc.v:140574.3-140594.6" + attribute \src "libresoc.v:140370.3-140390.6" wire $1\wb_sram_en$next[0:0]$6051 - attribute \src "libresoc.v:139543.7-139543.24" + attribute \src "libresoc.v:139339.7-139339.24" wire $1\wb_sram_en[0:0] - attribute \src "libresoc.v:140420.3-140464.6" + attribute \src "libresoc.v:140216.3-140260.6" wire width 4 $2\dmi0__addr_i$next[3:0]$6025 - attribute \src "libresoc.v:140518.3-140544.6" + attribute \src "libresoc.v:140314.3-140340.6" wire width 64 $2\dmi0__din$next[63:0]$6038 - attribute \src "libresoc.v:140089.3-140105.6" + attribute \src "libresoc.v:139885.3-139901.6" wire $2\dmi0_addrsr__oe$next[0:0]$5962 - attribute \src "libresoc.v:140106.3-140126.6" + attribute \src "libresoc.v:139902.3-139922.6" wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5966 - attribute \src "libresoc.v:140545.3-140573.6" + attribute \src "libresoc.v:140341.3-140369.6" wire width 64 $2\dmi0_datasr__i$next[63:0]$6043 - attribute \src "libresoc.v:140145.3-140161.6" + attribute \src "libresoc.v:139941.3-139957.6" wire width 2 $2\dmi0_datasr__oe$next[1:0]$5977 - attribute \src "libresoc.v:140162.3-140182.6" + attribute \src "libresoc.v:139958.3-139978.6" wire width 64 $2\dmi0_datasr_reg$next[63:0]$5981 - attribute \src "libresoc.v:140465.3-140517.6" + attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $2\fsm_state$455$next[2:0]$6031 - attribute \src "libresoc.v:140311.3-140363.6" + attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $2\fsm_state$next[2:0]$6008 - attribute \src "libresoc.v:140623.3-140643.6" + attribute \src "libresoc.v:140419.3-140439.6" wire width 130 $2\io_bd$next[129:0]$6063 - attribute \src "libresoc.v:140605.3-140622.6" + attribute \src "libresoc.v:140401.3-140418.6" wire width 130 $2\io_sr$next[129:0]$6059 - attribute \src "libresoc.v:140266.3-140310.6" + attribute \src "libresoc.v:140062.3-140106.6" wire width 29 $2\jtag_wb__adr$next[28:0]$6002 - attribute \src "libresoc.v:140364.3-140390.6" + attribute \src "libresoc.v:140160.3-140186.6" wire width 64 $2\jtag_wb__dat_w$next[63:0]$6015 - attribute \src "libresoc.v:139977.3-139993.6" + attribute \src "libresoc.v:139773.3-139789.6" wire $2\jtag_wb_addrsr__oe$next[0:0]$5932 - attribute \src "libresoc.v:139994.3-140014.6" + attribute \src "libresoc.v:139790.3-139810.6" wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5936 - attribute \src "libresoc.v:140391.3-140419.6" + attribute \src "libresoc.v:140187.3-140215.6" wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6020 - attribute \src "libresoc.v:140033.3-140049.6" + attribute \src "libresoc.v:139829.3-139845.6" wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5947 - attribute \src "libresoc.v:140050.3-140070.6" + attribute \src "libresoc.v:139846.3-139866.6" wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5951 - attribute \src "libresoc.v:139921.3-139937.6" + attribute \src "libresoc.v:139717.3-139733.6" wire $2\sr0__oe$next[0:0]$5917 - attribute \src "libresoc.v:139938.3-139958.6" + attribute \src "libresoc.v:139734.3-139754.6" wire width 3 $2\sr0_reg$next[2:0]$5921 - attribute \src "libresoc.v:140201.3-140217.6" + attribute \src "libresoc.v:139997.3-140013.6" wire $2\sr5__oe$next[0:0]$5992 - attribute \src "libresoc.v:140218.3-140238.6" + attribute \src "libresoc.v:140014.3-140034.6" wire width 3 $2\sr5_reg$next[2:0]$5996 - attribute \src "libresoc.v:140574.3-140594.6" + attribute \src "libresoc.v:140370.3-140390.6" wire $2\wb_dcache_en$next[0:0]$6052 - attribute \src "libresoc.v:140574.3-140594.6" + attribute \src "libresoc.v:140370.3-140390.6" wire $2\wb_icache_en$next[0:0]$6053 - attribute \src "libresoc.v:140574.3-140594.6" + attribute \src "libresoc.v:140370.3-140390.6" wire $2\wb_sram_en$next[0:0]$6054 - attribute \src "libresoc.v:140420.3-140464.6" + attribute \src "libresoc.v:140216.3-140260.6" wire width 4 $3\dmi0__addr_i$next[3:0]$6026 - attribute \src "libresoc.v:140518.3-140544.6" + attribute \src "libresoc.v:140314.3-140340.6" wire width 64 $3\dmi0__din$next[63:0]$6039 - attribute \src "libresoc.v:140106.3-140126.6" + attribute \src "libresoc.v:139902.3-139922.6" wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5967 - attribute \src "libresoc.v:140545.3-140573.6" + attribute \src "libresoc.v:140341.3-140369.6" wire width 64 $3\dmi0_datasr__i$next[63:0]$6044 - attribute \src "libresoc.v:140162.3-140182.6" + attribute \src "libresoc.v:139958.3-139978.6" wire width 64 $3\dmi0_datasr_reg$next[63:0]$5982 - attribute \src "libresoc.v:140465.3-140517.6" + attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $3\fsm_state$455$next[2:0]$6032 - attribute \src "libresoc.v:140311.3-140363.6" + attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $3\fsm_state$next[2:0]$6009 - attribute \src "libresoc.v:140266.3-140310.6" + attribute \src "libresoc.v:140062.3-140106.6" wire width 29 $3\jtag_wb__adr$next[28:0]$6003 - attribute \src "libresoc.v:140364.3-140390.6" + attribute \src "libresoc.v:140160.3-140186.6" wire width 64 $3\jtag_wb__dat_w$next[63:0]$6016 - attribute \src "libresoc.v:139994.3-140014.6" + attribute \src "libresoc.v:139790.3-139810.6" wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5937 - attribute \src "libresoc.v:140391.3-140419.6" + attribute \src "libresoc.v:140187.3-140215.6" wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6021 - attribute \src "libresoc.v:140050.3-140070.6" + attribute \src "libresoc.v:139846.3-139866.6" wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5952 - attribute \src "libresoc.v:139938.3-139958.6" + attribute \src "libresoc.v:139734.3-139754.6" wire width 3 $3\sr0_reg$next[2:0]$5922 - attribute \src "libresoc.v:140218.3-140238.6" + attribute \src "libresoc.v:140014.3-140034.6" wire width 3 $3\sr5_reg$next[2:0]$5997 - attribute \src "libresoc.v:140420.3-140464.6" + attribute \src "libresoc.v:140216.3-140260.6" wire width 4 $4\dmi0__addr_i$next[3:0]$6027 - attribute \src "libresoc.v:140465.3-140517.6" + attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $4\fsm_state$455$next[2:0]$6033 - attribute \src "libresoc.v:140311.3-140363.6" + attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $4\fsm_state$next[2:0]$6010 - attribute \src "libresoc.v:140266.3-140310.6" + attribute \src "libresoc.v:140062.3-140106.6" wire width 29 $4\jtag_wb__adr$next[28:0]$6004 - attribute \src "libresoc.v:140465.3-140517.6" + attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $5\fsm_state$455$next[2:0]$6034 - attribute \src "libresoc.v:140311.3-140363.6" + attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $5\fsm_state$next[2:0]$6011 - attribute \src "libresoc.v:139740.19-139740.112" - wire width 30 $add$libresoc.v:139740$5830_Y - attribute \src "libresoc.v:139741.19-139741.112" - wire width 30 $add$libresoc.v:139741$5831_Y - attribute \src "libresoc.v:139748.19-139748.112" - wire width 5 $add$libresoc.v:139748$5839_Y - attribute \src "libresoc.v:139749.19-139749.112" - wire width 5 $add$libresoc.v:139749$5840_Y - attribute \src "libresoc.v:139590.18-139590.112" - wire $and$libresoc.v:139590$5680_Y - attribute \src "libresoc.v:139657.18-139657.108" - wire $and$libresoc.v:139657$5747_Y - attribute \src "libresoc.v:139668.18-139668.110" - wire $and$libresoc.v:139668$5758_Y - attribute \src "libresoc.v:139670.19-139670.110" - wire $and$libresoc.v:139670$5760_Y - attribute \src "libresoc.v:139673.19-139673.114" - wire $and$libresoc.v:139673$5763_Y - attribute \src "libresoc.v:139675.19-139675.112" - wire $and$libresoc.v:139675$5765_Y - attribute \src "libresoc.v:139677.19-139677.113" - wire $and$libresoc.v:139677$5767_Y - attribute \src "libresoc.v:139680.19-139680.121" - wire $and$libresoc.v:139680$5770_Y - attribute \src "libresoc.v:139683.19-139683.114" - wire $and$libresoc.v:139683$5773_Y - attribute \src "libresoc.v:139685.19-139685.112" - wire $and$libresoc.v:139685$5775_Y - attribute \src "libresoc.v:139687.19-139687.113" - wire $and$libresoc.v:139687$5777_Y - attribute \src "libresoc.v:139689.19-139689.132" - wire $and$libresoc.v:139689$5779_Y - attribute \src "libresoc.v:139694.19-139694.114" - wire $and$libresoc.v:139694$5784_Y - attribute \src "libresoc.v:139696.19-139696.112" - wire $and$libresoc.v:139696$5786_Y - attribute \src "libresoc.v:139698.19-139698.113" - wire $and$libresoc.v:139698$5788_Y - attribute \src "libresoc.v:139700.19-139700.132" - wire $and$libresoc.v:139700$5790_Y - attribute \src "libresoc.v:139704.19-139704.114" - wire $and$libresoc.v:139704$5794_Y - attribute \src "libresoc.v:139706.19-139706.112" - wire $and$libresoc.v:139706$5796_Y - attribute \src "libresoc.v:139708.19-139708.113" - wire $and$libresoc.v:139708$5798_Y - attribute \src "libresoc.v:139710.19-139710.129" - wire $and$libresoc.v:139710$5800_Y - attribute \src "libresoc.v:139716.19-139716.114" - wire $and$libresoc.v:139716$5806_Y - attribute \src "libresoc.v:139718.19-139718.112" - wire $and$libresoc.v:139718$5808_Y - attribute \src "libresoc.v:139720.19-139720.113" - wire $and$libresoc.v:139720$5810_Y - attribute \src "libresoc.v:139722.19-139722.129" - wire $and$libresoc.v:139722$5812_Y - attribute \src "libresoc.v:139726.19-139726.114" - wire $and$libresoc.v:139726$5816_Y - attribute \src "libresoc.v:139728.19-139728.112" - wire $and$libresoc.v:139728$5818_Y - attribute \src "libresoc.v:139730.19-139730.113" - wire $and$libresoc.v:139730$5820_Y - attribute \src "libresoc.v:139732.19-139732.121" - wire $and$libresoc.v:139732$5822_Y - attribute \src "libresoc.v:139735.18-139735.108" - wire $and$libresoc.v:139735$5825_Y - attribute \src "libresoc.v:139745.18-139745.111" - wire $and$libresoc.v:139745$5836_Y - attribute \src "libresoc.v:139767.17-139767.106" - wire $and$libresoc.v:139767$5858_Y - attribute \src "libresoc.v:139546.17-139546.110" - wire $eq$libresoc.v:139546$5636_Y - attribute \src "libresoc.v:139557.18-139557.111" - wire $eq$libresoc.v:139557$5647_Y - attribute \src "libresoc.v:139568.18-139568.111" - wire $eq$libresoc.v:139568$5658_Y - attribute \src "libresoc.v:139601.17-139601.110" - wire $eq$libresoc.v:139601$5691_Y - attribute \src "libresoc.v:139602.18-139602.111" - wire $eq$libresoc.v:139602$5692_Y - attribute \src "libresoc.v:139613.18-139613.111" - wire $eq$libresoc.v:139613$5703_Y - attribute \src "libresoc.v:139635.18-139635.111" - wire $eq$libresoc.v:139635$5725_Y - attribute \src "libresoc.v:139664.19-139664.112" - wire $eq$libresoc.v:139664$5754_Y - attribute \src "libresoc.v:139665.19-139665.112" - wire $eq$libresoc.v:139665$5755_Y - attribute \src "libresoc.v:139667.19-139667.112" - wire $eq$libresoc.v:139667$5757_Y - attribute \src "libresoc.v:139671.19-139671.112" - wire $eq$libresoc.v:139671$5761_Y - attribute \src "libresoc.v:139679.18-139679.111" - wire $eq$libresoc.v:139679$5769_Y - attribute \src "libresoc.v:139681.19-139681.112" - wire $eq$libresoc.v:139681$5771_Y - attribute \src "libresoc.v:139690.18-139690.111" - wire $eq$libresoc.v:139690$5780_Y - attribute \src "libresoc.v:139691.19-139691.112" - wire $eq$libresoc.v:139691$5781_Y - attribute \src "libresoc.v:139692.19-139692.112" - wire $eq$libresoc.v:139692$5782_Y - attribute \src "libresoc.v:139702.19-139702.112" - wire $eq$libresoc.v:139702$5792_Y - attribute \src "libresoc.v:139711.19-139711.112" - wire $eq$libresoc.v:139711$5801_Y - attribute \src "libresoc.v:139712.17-139712.110" - wire $eq$libresoc.v:139712$5802_Y - attribute \src "libresoc.v:139713.18-139713.111" - wire $eq$libresoc.v:139713$5803_Y - attribute \src "libresoc.v:139714.19-139714.112" - wire $eq$libresoc.v:139714$5804_Y - attribute \src "libresoc.v:139723.19-139723.112" - wire $eq$libresoc.v:139723$5813_Y - attribute \src "libresoc.v:139733.19-139733.110" - wire $eq$libresoc.v:139733$5823_Y - attribute \src "libresoc.v:139736.19-139736.110" - wire $eq$libresoc.v:139736$5826_Y - attribute \src "libresoc.v:139737.19-139737.110" - wire $eq$libresoc.v:139737$5827_Y - attribute \src "libresoc.v:139739.19-139739.110" - wire $eq$libresoc.v:139739$5829_Y - attribute \src "libresoc.v:139743.19-139743.116" - wire $eq$libresoc.v:139743$5834_Y - attribute \src "libresoc.v:139744.19-139744.116" - wire $eq$libresoc.v:139744$5835_Y - attribute \src "libresoc.v:139747.19-139747.116" - wire $eq$libresoc.v:139747$5838_Y - attribute \src "libresoc.v:139750.18-139750.111" - wire $eq$libresoc.v:139750$5841_Y - attribute \src "libresoc.v:139751.18-139751.111" - wire $eq$libresoc.v:139751$5842_Y - attribute \src "libresoc.v:139742.19-139742.106" - wire width 8 $extend$libresoc.v:139742$5832_Y - attribute \src "libresoc.v:139672.19-139672.109" - wire $ne$libresoc.v:139672$5762_Y - attribute \src "libresoc.v:139674.19-139674.109" - wire $ne$libresoc.v:139674$5764_Y - attribute \src "libresoc.v:139676.19-139676.109" - wire $ne$libresoc.v:139676$5766_Y - attribute \src "libresoc.v:139682.19-139682.120" - wire $ne$libresoc.v:139682$5772_Y - attribute \src "libresoc.v:139684.19-139684.120" - wire $ne$libresoc.v:139684$5774_Y - attribute \src "libresoc.v:139686.19-139686.120" - wire $ne$libresoc.v:139686$5776_Y - attribute \src "libresoc.v:139693.19-139693.120" - wire $ne$libresoc.v:139693$5783_Y - attribute \src "libresoc.v:139695.19-139695.120" - wire $ne$libresoc.v:139695$5785_Y - attribute \src "libresoc.v:139697.19-139697.120" - wire $ne$libresoc.v:139697$5787_Y - attribute \src "libresoc.v:139703.19-139703.117" - wire $ne$libresoc.v:139703$5793_Y - attribute \src "libresoc.v:139705.19-139705.117" - wire $ne$libresoc.v:139705$5795_Y - attribute \src "libresoc.v:139707.19-139707.117" - wire $ne$libresoc.v:139707$5797_Y - attribute \src "libresoc.v:139715.19-139715.117" - wire $ne$libresoc.v:139715$5805_Y - attribute \src "libresoc.v:139717.19-139717.117" - wire $ne$libresoc.v:139717$5807_Y - attribute \src "libresoc.v:139719.19-139719.117" - wire $ne$libresoc.v:139719$5809_Y - attribute \src "libresoc.v:139725.19-139725.109" - wire $ne$libresoc.v:139725$5815_Y - attribute \src "libresoc.v:139727.19-139727.109" - wire $ne$libresoc.v:139727$5817_Y - attribute \src "libresoc.v:139729.19-139729.109" - wire $ne$libresoc.v:139729$5819_Y - attribute \src "libresoc.v:139678.19-139678.110" - wire $not$libresoc.v:139678$5768_Y - attribute \src "libresoc.v:139688.19-139688.121" - wire $not$libresoc.v:139688$5778_Y - attribute \src "libresoc.v:139699.19-139699.121" - wire $not$libresoc.v:139699$5789_Y - attribute \src "libresoc.v:139709.19-139709.118" - wire $not$libresoc.v:139709$5799_Y - attribute \src "libresoc.v:139721.19-139721.118" - wire $not$libresoc.v:139721$5811_Y - attribute \src "libresoc.v:139731.19-139731.110" - wire $not$libresoc.v:139731$5821_Y - attribute \src "libresoc.v:139734.19-139734.100" - wire $not$libresoc.v:139734$5824_Y - attribute \src "libresoc.v:139579.18-139579.104" - wire $or$libresoc.v:139579$5669_Y - attribute \src "libresoc.v:139624.18-139624.104" - wire $or$libresoc.v:139624$5714_Y - attribute \src "libresoc.v:139646.18-139646.104" - wire $or$libresoc.v:139646$5736_Y - attribute \src "libresoc.v:139666.19-139666.107" - wire $or$libresoc.v:139666$5756_Y - attribute \src "libresoc.v:139669.19-139669.107" - wire $or$libresoc.v:139669$5759_Y - attribute \src "libresoc.v:139701.18-139701.104" - wire $or$libresoc.v:139701$5791_Y - attribute \src "libresoc.v:139724.18-139724.104" - wire $or$libresoc.v:139724$5814_Y - attribute \src "libresoc.v:139738.19-139738.107" - wire $or$libresoc.v:139738$5828_Y - attribute \src "libresoc.v:139746.19-139746.107" - wire $or$libresoc.v:139746$5837_Y - attribute \src "libresoc.v:139756.17-139756.101" - wire $or$libresoc.v:139756$5847_Y - attribute \src "libresoc.v:139742.19-139742.106" - wire width 8 $pos$libresoc.v:139742$5833_Y - attribute \src "libresoc.v:139547.18-139547.133" - wire $ternary$libresoc.v:139547$5637_Y - attribute \src "libresoc.v:139548.19-139548.133" - wire $ternary$libresoc.v:139548$5638_Y - attribute \src "libresoc.v:139549.19-139549.134" - wire $ternary$libresoc.v:139549$5639_Y - attribute \src "libresoc.v:139550.19-139550.133" - wire $ternary$libresoc.v:139550$5640_Y - attribute \src "libresoc.v:139551.19-139551.132" - wire $ternary$libresoc.v:139551$5641_Y - attribute \src "libresoc.v:139552.19-139552.133" - wire $ternary$libresoc.v:139552$5642_Y - attribute \src "libresoc.v:139553.19-139553.133" - wire $ternary$libresoc.v:139553$5643_Y - attribute \src "libresoc.v:139554.19-139554.132" - wire $ternary$libresoc.v:139554$5644_Y - attribute \src "libresoc.v:139555.19-139555.133" - wire $ternary$libresoc.v:139555$5645_Y - attribute \src "libresoc.v:139556.19-139556.133" - wire $ternary$libresoc.v:139556$5646_Y - attribute \src "libresoc.v:139558.19-139558.132" - wire $ternary$libresoc.v:139558$5648_Y - attribute \src "libresoc.v:139559.19-139559.133" - wire $ternary$libresoc.v:139559$5649_Y - attribute \src "libresoc.v:139560.19-139560.133" - wire $ternary$libresoc.v:139560$5650_Y - attribute \src "libresoc.v:139561.19-139561.132" - wire $ternary$libresoc.v:139561$5651_Y - attribute \src "libresoc.v:139562.19-139562.133" - wire $ternary$libresoc.v:139562$5652_Y - attribute \src "libresoc.v:139563.19-139563.133" - wire $ternary$libresoc.v:139563$5653_Y - attribute \src "libresoc.v:139564.19-139564.132" - wire $ternary$libresoc.v:139564$5654_Y - attribute \src "libresoc.v:139565.19-139565.133" - wire $ternary$libresoc.v:139565$5655_Y - attribute \src "libresoc.v:139566.19-139566.133" - wire $ternary$libresoc.v:139566$5656_Y - attribute \src "libresoc.v:139567.19-139567.132" - wire $ternary$libresoc.v:139567$5657_Y - attribute \src "libresoc.v:139569.19-139569.133" - wire $ternary$libresoc.v:139569$5659_Y - attribute \src "libresoc.v:139570.19-139570.133" - wire $ternary$libresoc.v:139570$5660_Y - attribute \src "libresoc.v:139571.19-139571.132" - wire $ternary$libresoc.v:139571$5661_Y - attribute \src "libresoc.v:139572.19-139572.133" - wire $ternary$libresoc.v:139572$5662_Y - attribute \src "libresoc.v:139573.19-139573.133" - wire $ternary$libresoc.v:139573$5663_Y - attribute \src "libresoc.v:139574.19-139574.132" - wire $ternary$libresoc.v:139574$5664_Y - attribute \src "libresoc.v:139575.19-139575.133" - wire $ternary$libresoc.v:139575$5665_Y - attribute \src "libresoc.v:139576.19-139576.134" - wire $ternary$libresoc.v:139576$5666_Y - attribute \src "libresoc.v:139577.19-139577.135" - wire $ternary$libresoc.v:139577$5667_Y - attribute \src "libresoc.v:139578.19-139578.135" - wire $ternary$libresoc.v:139578$5668_Y - attribute \src "libresoc.v:139580.19-139580.136" - wire $ternary$libresoc.v:139580$5670_Y - attribute \src "libresoc.v:139581.19-139581.134" - wire $ternary$libresoc.v:139581$5671_Y - attribute \src "libresoc.v:139582.19-139582.133" - wire $ternary$libresoc.v:139582$5672_Y - attribute \src "libresoc.v:139583.19-139583.134" - wire $ternary$libresoc.v:139583$5673_Y - attribute \src "libresoc.v:139584.19-139584.133" - wire $ternary$libresoc.v:139584$5674_Y - attribute \src "libresoc.v:139585.19-139585.133" - wire $ternary$libresoc.v:139585$5675_Y - attribute \src "libresoc.v:139586.19-139586.134" - wire $ternary$libresoc.v:139586$5676_Y - attribute \src "libresoc.v:139587.19-139587.133" - wire $ternary$libresoc.v:139587$5677_Y - attribute \src "libresoc.v:139588.19-139588.134" - wire $ternary$libresoc.v:139588$5678_Y - attribute \src "libresoc.v:139589.19-139589.134" - wire $ternary$libresoc.v:139589$5679_Y - attribute \src "libresoc.v:139591.19-139591.133" - wire $ternary$libresoc.v:139591$5681_Y - attribute \src "libresoc.v:139592.19-139592.134" - wire $ternary$libresoc.v:139592$5682_Y - attribute \src "libresoc.v:139593.19-139593.134" - wire $ternary$libresoc.v:139593$5683_Y - attribute \src "libresoc.v:139594.19-139594.133" - wire $ternary$libresoc.v:139594$5684_Y - attribute \src "libresoc.v:139595.19-139595.134" - wire $ternary$libresoc.v:139595$5685_Y - attribute \src "libresoc.v:139596.19-139596.134" - wire $ternary$libresoc.v:139596$5686_Y - attribute \src "libresoc.v:139597.19-139597.133" - wire $ternary$libresoc.v:139597$5687_Y - attribute \src "libresoc.v:139598.19-139598.134" - wire $ternary$libresoc.v:139598$5688_Y - attribute \src "libresoc.v:139599.19-139599.134" - wire $ternary$libresoc.v:139599$5689_Y - attribute \src "libresoc.v:139600.19-139600.133" - wire $ternary$libresoc.v:139600$5690_Y - attribute \src "libresoc.v:139603.19-139603.134" - wire $ternary$libresoc.v:139603$5693_Y - attribute \src "libresoc.v:139604.19-139604.134" - wire $ternary$libresoc.v:139604$5694_Y - attribute \src "libresoc.v:139605.19-139605.133" - wire $ternary$libresoc.v:139605$5695_Y - attribute \src "libresoc.v:139606.19-139606.134" - wire $ternary$libresoc.v:139606$5696_Y - attribute \src "libresoc.v:139607.19-139607.134" - wire $ternary$libresoc.v:139607$5697_Y - attribute \src "libresoc.v:139608.19-139608.133" - wire $ternary$libresoc.v:139608$5698_Y - attribute \src "libresoc.v:139609.19-139609.134" - wire $ternary$libresoc.v:139609$5699_Y - attribute \src "libresoc.v:139610.19-139610.134" - wire $ternary$libresoc.v:139610$5700_Y - attribute \src "libresoc.v:139611.19-139611.133" - wire $ternary$libresoc.v:139611$5701_Y - attribute \src "libresoc.v:139612.19-139612.134" - wire $ternary$libresoc.v:139612$5702_Y - attribute \src "libresoc.v:139614.19-139614.132" - wire $ternary$libresoc.v:139614$5704_Y - attribute \src "libresoc.v:139615.19-139615.132" - wire $ternary$libresoc.v:139615$5705_Y - attribute \src "libresoc.v:139616.19-139616.132" - wire $ternary$libresoc.v:139616$5706_Y - attribute \src "libresoc.v:139617.19-139617.132" - wire $ternary$libresoc.v:139617$5707_Y - attribute \src "libresoc.v:139618.19-139618.132" - wire $ternary$libresoc.v:139618$5708_Y - attribute \src "libresoc.v:139619.19-139619.132" - wire $ternary$libresoc.v:139619$5709_Y - attribute \src "libresoc.v:139620.19-139620.132" - wire $ternary$libresoc.v:139620$5710_Y - attribute \src "libresoc.v:139621.19-139621.132" - wire $ternary$libresoc.v:139621$5711_Y - attribute \src "libresoc.v:139622.19-139622.132" - wire $ternary$libresoc.v:139622$5712_Y - attribute \src "libresoc.v:139623.19-139623.132" - wire $ternary$libresoc.v:139623$5713_Y - attribute \src "libresoc.v:139625.19-139625.133" - wire $ternary$libresoc.v:139625$5715_Y - attribute \src "libresoc.v:139626.19-139626.133" - wire $ternary$libresoc.v:139626$5716_Y - attribute \src "libresoc.v:139627.19-139627.134" - wire $ternary$libresoc.v:139627$5717_Y - attribute \src "libresoc.v:139628.19-139628.132" - wire $ternary$libresoc.v:139628$5718_Y - attribute \src "libresoc.v:139629.19-139629.134" - wire $ternary$libresoc.v:139629$5719_Y - attribute \src "libresoc.v:139630.19-139630.134" - wire $ternary$libresoc.v:139630$5720_Y - attribute \src "libresoc.v:139631.19-139631.134" - wire $ternary$libresoc.v:139631$5721_Y - attribute \src "libresoc.v:139632.19-139632.134" - wire $ternary$libresoc.v:139632$5722_Y - attribute \src "libresoc.v:139633.19-139633.134" - wire $ternary$libresoc.v:139633$5723_Y - attribute \src "libresoc.v:139634.19-139634.134" - wire $ternary$libresoc.v:139634$5724_Y - attribute \src "libresoc.v:139636.19-139636.134" - wire $ternary$libresoc.v:139636$5726_Y - attribute \src "libresoc.v:139637.19-139637.134" - wire $ternary$libresoc.v:139637$5727_Y - attribute \src "libresoc.v:139638.19-139638.135" - wire $ternary$libresoc.v:139638$5728_Y - attribute \src "libresoc.v:139639.19-139639.134" - wire $ternary$libresoc.v:139639$5729_Y - attribute \src "libresoc.v:139640.19-139640.135" - wire $ternary$libresoc.v:139640$5730_Y - attribute \src "libresoc.v:139641.19-139641.135" - wire $ternary$libresoc.v:139641$5731_Y - attribute \src "libresoc.v:139642.19-139642.134" - wire $ternary$libresoc.v:139642$5732_Y - attribute \src "libresoc.v:139643.19-139643.135" - wire $ternary$libresoc.v:139643$5733_Y - attribute \src "libresoc.v:139644.19-139644.136" - wire $ternary$libresoc.v:139644$5734_Y - attribute \src "libresoc.v:139645.19-139645.135" - wire $ternary$libresoc.v:139645$5735_Y - attribute \src "libresoc.v:139647.19-139647.136" - wire $ternary$libresoc.v:139647$5737_Y - attribute \src "libresoc.v:139648.19-139648.136" - wire $ternary$libresoc.v:139648$5738_Y - attribute \src "libresoc.v:139649.19-139649.135" - wire $ternary$libresoc.v:139649$5739_Y - attribute \src "libresoc.v:139650.19-139650.136" - wire $ternary$libresoc.v:139650$5740_Y - attribute \src "libresoc.v:139651.19-139651.136" - wire $ternary$libresoc.v:139651$5741_Y - attribute \src "libresoc.v:139652.19-139652.135" - wire $ternary$libresoc.v:139652$5742_Y - attribute \src "libresoc.v:139653.19-139653.136" - wire $ternary$libresoc.v:139653$5743_Y - attribute \src "libresoc.v:139654.19-139654.136" - wire $ternary$libresoc.v:139654$5744_Y - attribute \src "libresoc.v:139655.19-139655.135" - wire $ternary$libresoc.v:139655$5745_Y - attribute \src "libresoc.v:139656.19-139656.136" - wire $ternary$libresoc.v:139656$5746_Y - attribute \src "libresoc.v:139658.19-139658.136" - wire $ternary$libresoc.v:139658$5748_Y - attribute \src "libresoc.v:139659.19-139659.135" - wire $ternary$libresoc.v:139659$5749_Y - attribute \src "libresoc.v:139660.19-139660.136" - wire $ternary$libresoc.v:139660$5750_Y - attribute \src "libresoc.v:139661.19-139661.136" - wire $ternary$libresoc.v:139661$5751_Y - attribute \src "libresoc.v:139662.19-139662.135" - wire $ternary$libresoc.v:139662$5752_Y - attribute \src "libresoc.v:139663.19-139663.136" - wire $ternary$libresoc.v:139663$5753_Y - attribute \src "libresoc.v:139752.18-139752.130" - wire $ternary$libresoc.v:139752$5843_Y - attribute \src "libresoc.v:139753.18-139753.130" - wire $ternary$libresoc.v:139753$5844_Y - attribute \src "libresoc.v:139754.18-139754.130" - wire $ternary$libresoc.v:139754$5845_Y - attribute \src "libresoc.v:139755.18-139755.131" - wire $ternary$libresoc.v:139755$5846_Y - attribute \src "libresoc.v:139757.18-139757.130" - wire $ternary$libresoc.v:139757$5848_Y - attribute \src "libresoc.v:139758.18-139758.131" - wire $ternary$libresoc.v:139758$5849_Y - attribute \src "libresoc.v:139759.18-139759.131" - wire $ternary$libresoc.v:139759$5850_Y - attribute \src "libresoc.v:139760.18-139760.130" - wire $ternary$libresoc.v:139760$5851_Y - attribute \src "libresoc.v:139761.18-139761.131" - wire $ternary$libresoc.v:139761$5852_Y - attribute \src "libresoc.v:139762.18-139762.132" - wire $ternary$libresoc.v:139762$5853_Y - attribute \src "libresoc.v:139763.18-139763.132" - wire $ternary$libresoc.v:139763$5854_Y - attribute \src "libresoc.v:139764.18-139764.133" - wire $ternary$libresoc.v:139764$5855_Y - attribute \src "libresoc.v:139765.18-139765.133" - wire $ternary$libresoc.v:139765$5856_Y - attribute \src "libresoc.v:139766.18-139766.132" - wire $ternary$libresoc.v:139766$5857_Y - attribute \src "libresoc.v:139768.18-139768.133" - wire $ternary$libresoc.v:139768$5859_Y - attribute \src "libresoc.v:139769.18-139769.133" - wire $ternary$libresoc.v:139769$5860_Y - attribute \src "libresoc.v:139770.18-139770.132" - wire $ternary$libresoc.v:139770$5861_Y - attribute \src "libresoc.v:139771.18-139771.133" - wire $ternary$libresoc.v:139771$5862_Y - attribute \src "libresoc.v:139772.18-139772.133" - wire $ternary$libresoc.v:139772$5863_Y - attribute \src "libresoc.v:139773.18-139773.132" - wire $ternary$libresoc.v:139773$5864_Y - attribute \src "libresoc.v:139774.18-139774.133" - wire $ternary$libresoc.v:139774$5865_Y - attribute \src "libresoc.v:139775.18-139775.133" - wire $ternary$libresoc.v:139775$5866_Y - attribute \src "libresoc.v:139776.18-139776.132" - wire $ternary$libresoc.v:139776$5867_Y - attribute \src "libresoc.v:139777.18-139777.133" - wire $ternary$libresoc.v:139777$5868_Y + attribute \src "libresoc.v:139536.19-139536.112" + wire width 30 $add$libresoc.v:139536$5830_Y + attribute \src "libresoc.v:139537.19-139537.112" + wire width 30 $add$libresoc.v:139537$5831_Y + attribute \src "libresoc.v:139544.19-139544.112" + wire width 5 $add$libresoc.v:139544$5839_Y + attribute \src "libresoc.v:139545.19-139545.112" + wire width 5 $add$libresoc.v:139545$5840_Y + attribute \src "libresoc.v:139386.18-139386.112" + wire $and$libresoc.v:139386$5680_Y + attribute \src "libresoc.v:139453.18-139453.108" + wire $and$libresoc.v:139453$5747_Y + attribute \src "libresoc.v:139464.18-139464.110" + wire $and$libresoc.v:139464$5758_Y + attribute \src "libresoc.v:139466.19-139466.110" + wire $and$libresoc.v:139466$5760_Y + attribute \src "libresoc.v:139469.19-139469.114" + wire $and$libresoc.v:139469$5763_Y + attribute \src "libresoc.v:139471.19-139471.112" + wire $and$libresoc.v:139471$5765_Y + attribute \src "libresoc.v:139473.19-139473.113" + wire $and$libresoc.v:139473$5767_Y + attribute \src "libresoc.v:139476.19-139476.121" + wire $and$libresoc.v:139476$5770_Y + attribute \src "libresoc.v:139479.19-139479.114" + wire $and$libresoc.v:139479$5773_Y + attribute \src "libresoc.v:139481.19-139481.112" + wire $and$libresoc.v:139481$5775_Y + attribute \src "libresoc.v:139483.19-139483.113" + wire $and$libresoc.v:139483$5777_Y + attribute \src "libresoc.v:139485.19-139485.132" + wire $and$libresoc.v:139485$5779_Y + attribute \src "libresoc.v:139490.19-139490.114" + wire $and$libresoc.v:139490$5784_Y + attribute \src "libresoc.v:139492.19-139492.112" + wire $and$libresoc.v:139492$5786_Y + attribute \src "libresoc.v:139494.19-139494.113" + wire $and$libresoc.v:139494$5788_Y + attribute \src "libresoc.v:139496.19-139496.132" + wire $and$libresoc.v:139496$5790_Y + attribute \src "libresoc.v:139500.19-139500.114" + wire $and$libresoc.v:139500$5794_Y + attribute \src "libresoc.v:139502.19-139502.112" + wire $and$libresoc.v:139502$5796_Y + attribute \src "libresoc.v:139504.19-139504.113" + wire $and$libresoc.v:139504$5798_Y + attribute \src "libresoc.v:139506.19-139506.129" + wire $and$libresoc.v:139506$5800_Y + attribute \src "libresoc.v:139512.19-139512.114" + wire $and$libresoc.v:139512$5806_Y + attribute \src "libresoc.v:139514.19-139514.112" + wire $and$libresoc.v:139514$5808_Y + attribute \src "libresoc.v:139516.19-139516.113" + wire $and$libresoc.v:139516$5810_Y + attribute \src "libresoc.v:139518.19-139518.129" + wire $and$libresoc.v:139518$5812_Y + attribute \src "libresoc.v:139522.19-139522.114" + wire $and$libresoc.v:139522$5816_Y + attribute \src "libresoc.v:139524.19-139524.112" + wire $and$libresoc.v:139524$5818_Y + attribute \src "libresoc.v:139526.19-139526.113" + wire $and$libresoc.v:139526$5820_Y + attribute \src "libresoc.v:139528.19-139528.121" + wire $and$libresoc.v:139528$5822_Y + attribute \src "libresoc.v:139531.18-139531.108" + wire $and$libresoc.v:139531$5825_Y + attribute \src "libresoc.v:139541.18-139541.111" + wire $and$libresoc.v:139541$5836_Y + attribute \src "libresoc.v:139563.17-139563.106" + wire $and$libresoc.v:139563$5858_Y + attribute \src "libresoc.v:139342.17-139342.110" + wire $eq$libresoc.v:139342$5636_Y + attribute \src "libresoc.v:139353.18-139353.111" + wire $eq$libresoc.v:139353$5647_Y + attribute \src "libresoc.v:139364.18-139364.111" + wire $eq$libresoc.v:139364$5658_Y + attribute \src "libresoc.v:139397.17-139397.110" + wire $eq$libresoc.v:139397$5691_Y + attribute \src "libresoc.v:139398.18-139398.111" + wire $eq$libresoc.v:139398$5692_Y + attribute \src "libresoc.v:139409.18-139409.111" + wire $eq$libresoc.v:139409$5703_Y + attribute \src "libresoc.v:139431.18-139431.111" + wire $eq$libresoc.v:139431$5725_Y + attribute \src "libresoc.v:139460.19-139460.112" + wire $eq$libresoc.v:139460$5754_Y + attribute \src "libresoc.v:139461.19-139461.112" + wire $eq$libresoc.v:139461$5755_Y + attribute \src "libresoc.v:139463.19-139463.112" + wire $eq$libresoc.v:139463$5757_Y + attribute \src "libresoc.v:139467.19-139467.112" + wire $eq$libresoc.v:139467$5761_Y + attribute \src "libresoc.v:139475.18-139475.111" + wire $eq$libresoc.v:139475$5769_Y + attribute \src "libresoc.v:139477.19-139477.112" + wire $eq$libresoc.v:139477$5771_Y + attribute \src "libresoc.v:139486.18-139486.111" + wire $eq$libresoc.v:139486$5780_Y + attribute \src "libresoc.v:139487.19-139487.112" + wire $eq$libresoc.v:139487$5781_Y + attribute \src "libresoc.v:139488.19-139488.112" + wire $eq$libresoc.v:139488$5782_Y + attribute \src "libresoc.v:139498.19-139498.112" + wire $eq$libresoc.v:139498$5792_Y + attribute \src "libresoc.v:139507.19-139507.112" + wire $eq$libresoc.v:139507$5801_Y + attribute \src "libresoc.v:139508.17-139508.110" + wire $eq$libresoc.v:139508$5802_Y + attribute \src "libresoc.v:139509.18-139509.111" + wire $eq$libresoc.v:139509$5803_Y + attribute \src "libresoc.v:139510.19-139510.112" + wire $eq$libresoc.v:139510$5804_Y + attribute \src "libresoc.v:139519.19-139519.112" + wire $eq$libresoc.v:139519$5813_Y + attribute \src "libresoc.v:139529.19-139529.110" + wire $eq$libresoc.v:139529$5823_Y + attribute \src "libresoc.v:139532.19-139532.110" + wire $eq$libresoc.v:139532$5826_Y + attribute \src "libresoc.v:139533.19-139533.110" + wire $eq$libresoc.v:139533$5827_Y + attribute \src "libresoc.v:139535.19-139535.110" + wire $eq$libresoc.v:139535$5829_Y + attribute \src "libresoc.v:139539.19-139539.116" + wire $eq$libresoc.v:139539$5834_Y + attribute \src "libresoc.v:139540.19-139540.116" + wire $eq$libresoc.v:139540$5835_Y + attribute \src "libresoc.v:139543.19-139543.116" + wire $eq$libresoc.v:139543$5838_Y + attribute \src "libresoc.v:139546.18-139546.111" + wire $eq$libresoc.v:139546$5841_Y + attribute \src "libresoc.v:139547.18-139547.111" + wire $eq$libresoc.v:139547$5842_Y + attribute \src "libresoc.v:139538.19-139538.106" + wire width 8 $extend$libresoc.v:139538$5832_Y + attribute \src "libresoc.v:139468.19-139468.109" + wire $ne$libresoc.v:139468$5762_Y + attribute \src "libresoc.v:139470.19-139470.109" + wire $ne$libresoc.v:139470$5764_Y + attribute \src "libresoc.v:139472.19-139472.109" + wire $ne$libresoc.v:139472$5766_Y + attribute \src "libresoc.v:139478.19-139478.120" + wire $ne$libresoc.v:139478$5772_Y + attribute \src "libresoc.v:139480.19-139480.120" + wire $ne$libresoc.v:139480$5774_Y + attribute \src "libresoc.v:139482.19-139482.120" + wire $ne$libresoc.v:139482$5776_Y + attribute \src "libresoc.v:139489.19-139489.120" + wire $ne$libresoc.v:139489$5783_Y + attribute \src "libresoc.v:139491.19-139491.120" + wire $ne$libresoc.v:139491$5785_Y + attribute \src "libresoc.v:139493.19-139493.120" + wire $ne$libresoc.v:139493$5787_Y + attribute \src "libresoc.v:139499.19-139499.117" + wire $ne$libresoc.v:139499$5793_Y + attribute \src "libresoc.v:139501.19-139501.117" + wire $ne$libresoc.v:139501$5795_Y + attribute \src "libresoc.v:139503.19-139503.117" + wire $ne$libresoc.v:139503$5797_Y + attribute \src "libresoc.v:139511.19-139511.117" + wire $ne$libresoc.v:139511$5805_Y + attribute \src "libresoc.v:139513.19-139513.117" + wire $ne$libresoc.v:139513$5807_Y + attribute \src "libresoc.v:139515.19-139515.117" + wire $ne$libresoc.v:139515$5809_Y + attribute \src "libresoc.v:139521.19-139521.109" + wire $ne$libresoc.v:139521$5815_Y + attribute \src "libresoc.v:139523.19-139523.109" + wire $ne$libresoc.v:139523$5817_Y + attribute \src "libresoc.v:139525.19-139525.109" + wire $ne$libresoc.v:139525$5819_Y + attribute \src "libresoc.v:139474.19-139474.110" + wire $not$libresoc.v:139474$5768_Y + attribute \src "libresoc.v:139484.19-139484.121" + wire $not$libresoc.v:139484$5778_Y + attribute \src "libresoc.v:139495.19-139495.121" + wire $not$libresoc.v:139495$5789_Y + attribute \src "libresoc.v:139505.19-139505.118" + wire $not$libresoc.v:139505$5799_Y + attribute \src "libresoc.v:139517.19-139517.118" + wire $not$libresoc.v:139517$5811_Y + attribute \src "libresoc.v:139527.19-139527.110" + wire $not$libresoc.v:139527$5821_Y + attribute \src "libresoc.v:139530.19-139530.100" + wire $not$libresoc.v:139530$5824_Y + attribute \src "libresoc.v:139375.18-139375.104" + wire $or$libresoc.v:139375$5669_Y + attribute \src "libresoc.v:139420.18-139420.104" + wire $or$libresoc.v:139420$5714_Y + attribute \src "libresoc.v:139442.18-139442.104" + wire $or$libresoc.v:139442$5736_Y + attribute \src "libresoc.v:139462.19-139462.107" + wire $or$libresoc.v:139462$5756_Y + attribute \src "libresoc.v:139465.19-139465.107" + wire $or$libresoc.v:139465$5759_Y + attribute \src "libresoc.v:139497.18-139497.104" + wire $or$libresoc.v:139497$5791_Y + attribute \src "libresoc.v:139520.18-139520.104" + wire $or$libresoc.v:139520$5814_Y + attribute \src "libresoc.v:139534.19-139534.107" + wire $or$libresoc.v:139534$5828_Y + attribute \src "libresoc.v:139542.19-139542.107" + wire $or$libresoc.v:139542$5837_Y + attribute \src "libresoc.v:139552.17-139552.101" + wire $or$libresoc.v:139552$5847_Y + attribute \src "libresoc.v:139538.19-139538.106" + wire width 8 $pos$libresoc.v:139538$5833_Y + attribute \src "libresoc.v:139343.18-139343.132" + wire $ternary$libresoc.v:139343$5637_Y + attribute \src "libresoc.v:139344.19-139344.134" + wire $ternary$libresoc.v:139344$5638_Y + attribute \src "libresoc.v:139345.19-139345.134" + wire $ternary$libresoc.v:139345$5639_Y + attribute \src "libresoc.v:139346.19-139346.133" + wire $ternary$libresoc.v:139346$5640_Y + attribute \src "libresoc.v:139347.19-139347.134" + wire $ternary$libresoc.v:139347$5641_Y + attribute \src "libresoc.v:139348.19-139348.132" + wire $ternary$libresoc.v:139348$5642_Y + attribute \src "libresoc.v:139349.19-139349.132" + wire $ternary$libresoc.v:139349$5643_Y + attribute \src "libresoc.v:139350.19-139350.132" + wire $ternary$libresoc.v:139350$5644_Y + attribute \src "libresoc.v:139351.19-139351.132" + wire $ternary$libresoc.v:139351$5645_Y + attribute \src "libresoc.v:139352.19-139352.132" + wire $ternary$libresoc.v:139352$5646_Y + attribute \src "libresoc.v:139354.19-139354.132" + wire $ternary$libresoc.v:139354$5648_Y + attribute \src "libresoc.v:139355.19-139355.132" + wire $ternary$libresoc.v:139355$5649_Y + attribute \src "libresoc.v:139356.19-139356.132" + wire $ternary$libresoc.v:139356$5650_Y + attribute \src "libresoc.v:139357.19-139357.132" + wire $ternary$libresoc.v:139357$5651_Y + attribute \src "libresoc.v:139358.19-139358.132" + wire $ternary$libresoc.v:139358$5652_Y + attribute \src "libresoc.v:139359.19-139359.133" + wire $ternary$libresoc.v:139359$5653_Y + attribute \src "libresoc.v:139360.19-139360.133" + wire $ternary$libresoc.v:139360$5654_Y + attribute \src "libresoc.v:139361.19-139361.134" + wire $ternary$libresoc.v:139361$5655_Y + attribute \src "libresoc.v:139362.19-139362.132" + wire $ternary$libresoc.v:139362$5656_Y + attribute \src "libresoc.v:139363.19-139363.134" + wire $ternary$libresoc.v:139363$5657_Y + attribute \src "libresoc.v:139365.19-139365.134" + wire $ternary$libresoc.v:139365$5659_Y + attribute \src "libresoc.v:139366.19-139366.133" + wire $ternary$libresoc.v:139366$5660_Y + attribute \src "libresoc.v:139367.19-139367.133" + wire $ternary$libresoc.v:139367$5661_Y + attribute \src "libresoc.v:139368.19-139368.133" + wire $ternary$libresoc.v:139368$5662_Y + attribute \src "libresoc.v:139369.19-139369.133" + wire $ternary$libresoc.v:139369$5663_Y + attribute \src "libresoc.v:139370.19-139370.133" + wire $ternary$libresoc.v:139370$5664_Y + attribute \src "libresoc.v:139371.19-139371.133" + wire $ternary$libresoc.v:139371$5665_Y + attribute \src "libresoc.v:139372.19-139372.134" + wire $ternary$libresoc.v:139372$5666_Y + attribute \src "libresoc.v:139373.19-139373.133" + wire $ternary$libresoc.v:139373$5667_Y + attribute \src "libresoc.v:139374.19-139374.134" + wire $ternary$libresoc.v:139374$5668_Y + attribute \src "libresoc.v:139376.19-139376.134" + wire $ternary$libresoc.v:139376$5670_Y + attribute \src "libresoc.v:139377.19-139377.133" + wire $ternary$libresoc.v:139377$5671_Y + attribute \src "libresoc.v:139378.19-139378.134" + wire $ternary$libresoc.v:139378$5672_Y + attribute \src "libresoc.v:139379.19-139379.135" + wire $ternary$libresoc.v:139379$5673_Y + attribute \src "libresoc.v:139380.19-139380.134" + wire $ternary$libresoc.v:139380$5674_Y + attribute \src "libresoc.v:139381.19-139381.135" + wire $ternary$libresoc.v:139381$5675_Y + attribute \src "libresoc.v:139382.19-139382.135" + wire $ternary$libresoc.v:139382$5676_Y + attribute \src "libresoc.v:139383.19-139383.134" + wire $ternary$libresoc.v:139383$5677_Y + attribute \src "libresoc.v:139384.19-139384.135" + wire $ternary$libresoc.v:139384$5678_Y + attribute \src "libresoc.v:139385.19-139385.135" + wire $ternary$libresoc.v:139385$5679_Y + attribute \src "libresoc.v:139387.19-139387.134" + wire $ternary$libresoc.v:139387$5681_Y + attribute \src "libresoc.v:139388.19-139388.135" + wire $ternary$libresoc.v:139388$5682_Y + attribute \src "libresoc.v:139389.19-139389.135" + wire $ternary$libresoc.v:139389$5683_Y + attribute \src "libresoc.v:139390.19-139390.134" + wire $ternary$libresoc.v:139390$5684_Y + attribute \src "libresoc.v:139391.19-139391.135" + wire $ternary$libresoc.v:139391$5685_Y + attribute \src "libresoc.v:139392.19-139392.135" + wire $ternary$libresoc.v:139392$5686_Y + attribute \src "libresoc.v:139393.19-139393.134" + wire $ternary$libresoc.v:139393$5687_Y + attribute \src "libresoc.v:139394.19-139394.135" + wire $ternary$libresoc.v:139394$5688_Y + attribute \src "libresoc.v:139395.19-139395.135" + wire $ternary$libresoc.v:139395$5689_Y + attribute \src "libresoc.v:139396.19-139396.134" + wire $ternary$libresoc.v:139396$5690_Y + attribute \src "libresoc.v:139399.19-139399.135" + wire $ternary$libresoc.v:139399$5693_Y + attribute \src "libresoc.v:139400.19-139400.133" + wire $ternary$libresoc.v:139400$5694_Y + attribute \src "libresoc.v:139401.19-139401.132" + wire $ternary$libresoc.v:139401$5695_Y + attribute \src "libresoc.v:139402.19-139402.133" + wire $ternary$libresoc.v:139402$5696_Y + attribute \src "libresoc.v:139403.19-139403.133" + wire $ternary$libresoc.v:139403$5697_Y + attribute \src "libresoc.v:139404.19-139404.132" + wire $ternary$libresoc.v:139404$5698_Y + attribute \src "libresoc.v:139405.19-139405.133" + wire $ternary$libresoc.v:139405$5699_Y + attribute \src "libresoc.v:139406.19-139406.134" + wire $ternary$libresoc.v:139406$5700_Y + attribute \src "libresoc.v:139407.19-139407.133" + wire $ternary$libresoc.v:139407$5701_Y + attribute \src "libresoc.v:139408.19-139408.134" + wire $ternary$libresoc.v:139408$5702_Y + attribute \src "libresoc.v:139410.19-139410.134" + wire $ternary$libresoc.v:139410$5704_Y + attribute \src "libresoc.v:139411.19-139411.133" + wire $ternary$libresoc.v:139411$5705_Y + attribute \src "libresoc.v:139412.19-139412.134" + wire $ternary$libresoc.v:139412$5706_Y + attribute \src "libresoc.v:139413.19-139413.134" + wire $ternary$libresoc.v:139413$5707_Y + attribute \src "libresoc.v:139414.19-139414.133" + wire $ternary$libresoc.v:139414$5708_Y + attribute \src "libresoc.v:139415.19-139415.134" + wire $ternary$libresoc.v:139415$5709_Y + attribute \src "libresoc.v:139416.19-139416.134" + wire $ternary$libresoc.v:139416$5710_Y + attribute \src "libresoc.v:139417.19-139417.133" + wire $ternary$libresoc.v:139417$5711_Y + attribute \src "libresoc.v:139418.19-139418.134" + wire $ternary$libresoc.v:139418$5712_Y + attribute \src "libresoc.v:139419.19-139419.134" + wire $ternary$libresoc.v:139419$5713_Y + attribute \src "libresoc.v:139421.19-139421.133" + wire $ternary$libresoc.v:139421$5715_Y + attribute \src "libresoc.v:139422.19-139422.134" + wire $ternary$libresoc.v:139422$5716_Y + attribute \src "libresoc.v:139423.19-139423.134" + wire $ternary$libresoc.v:139423$5717_Y + attribute \src "libresoc.v:139424.19-139424.133" + wire $ternary$libresoc.v:139424$5718_Y + attribute \src "libresoc.v:139425.19-139425.134" + wire $ternary$libresoc.v:139425$5719_Y + attribute \src "libresoc.v:139426.19-139426.133" + wire $ternary$libresoc.v:139426$5720_Y + attribute \src "libresoc.v:139427.19-139427.133" + wire $ternary$libresoc.v:139427$5721_Y + attribute \src "libresoc.v:139428.19-139428.134" + wire $ternary$libresoc.v:139428$5722_Y + attribute \src "libresoc.v:139429.19-139429.134" + wire $ternary$libresoc.v:139429$5723_Y + attribute \src "libresoc.v:139430.19-139430.133" + wire $ternary$libresoc.v:139430$5724_Y + attribute \src "libresoc.v:139432.19-139432.134" + wire $ternary$libresoc.v:139432$5726_Y + attribute \src "libresoc.v:139433.19-139433.134" + wire $ternary$libresoc.v:139433$5727_Y + attribute \src "libresoc.v:139434.19-139434.133" + wire $ternary$libresoc.v:139434$5728_Y + attribute \src "libresoc.v:139435.19-139435.134" + wire $ternary$libresoc.v:139435$5729_Y + attribute \src "libresoc.v:139436.19-139436.134" + wire $ternary$libresoc.v:139436$5730_Y + attribute \src "libresoc.v:139437.19-139437.133" + wire $ternary$libresoc.v:139437$5731_Y + attribute \src "libresoc.v:139438.19-139438.134" + wire $ternary$libresoc.v:139438$5732_Y + attribute \src "libresoc.v:139439.19-139439.134" + wire $ternary$libresoc.v:139439$5733_Y + attribute \src "libresoc.v:139440.19-139440.133" + wire $ternary$libresoc.v:139440$5734_Y + attribute \src "libresoc.v:139441.19-139441.134" + wire $ternary$libresoc.v:139441$5735_Y + attribute \src "libresoc.v:139443.19-139443.134" + wire $ternary$libresoc.v:139443$5737_Y + attribute \src "libresoc.v:139444.19-139444.133" + wire $ternary$libresoc.v:139444$5738_Y + attribute \src "libresoc.v:139445.19-139445.134" + wire $ternary$libresoc.v:139445$5739_Y + attribute \src "libresoc.v:139446.19-139446.134" + wire $ternary$libresoc.v:139446$5740_Y + attribute \src "libresoc.v:139447.19-139447.133" + wire $ternary$libresoc.v:139447$5741_Y + attribute \src "libresoc.v:139448.19-139448.134" + wire $ternary$libresoc.v:139448$5742_Y + attribute \src "libresoc.v:139449.19-139449.134" + wire $ternary$libresoc.v:139449$5743_Y + attribute \src "libresoc.v:139450.19-139450.133" + wire $ternary$libresoc.v:139450$5744_Y + attribute \src "libresoc.v:139451.19-139451.134" + wire $ternary$libresoc.v:139451$5745_Y + attribute \src "libresoc.v:139452.19-139452.135" + wire $ternary$libresoc.v:139452$5746_Y + attribute \src "libresoc.v:139454.19-139454.134" + wire $ternary$libresoc.v:139454$5748_Y + attribute \src "libresoc.v:139455.19-139455.135" + wire $ternary$libresoc.v:139455$5749_Y + attribute \src "libresoc.v:139456.19-139456.134" + wire $ternary$libresoc.v:139456$5750_Y + attribute \src "libresoc.v:139457.19-139457.133" + wire $ternary$libresoc.v:139457$5751_Y + attribute \src "libresoc.v:139458.19-139458.133" + wire $ternary$libresoc.v:139458$5752_Y + attribute \src "libresoc.v:139459.19-139459.133" + wire $ternary$libresoc.v:139459$5753_Y + attribute \src "libresoc.v:139548.18-139548.132" + wire $ternary$libresoc.v:139548$5843_Y + attribute \src "libresoc.v:139549.18-139549.133" + wire $ternary$libresoc.v:139549$5844_Y + attribute \src "libresoc.v:139550.18-139550.133" + wire $ternary$libresoc.v:139550$5845_Y + attribute \src "libresoc.v:139551.18-139551.134" + wire $ternary$libresoc.v:139551$5846_Y + attribute \src "libresoc.v:139553.18-139553.131" + wire $ternary$libresoc.v:139553$5848_Y + attribute \src "libresoc.v:139554.18-139554.132" + wire $ternary$libresoc.v:139554$5849_Y + attribute \src "libresoc.v:139555.18-139555.131" + wire $ternary$libresoc.v:139555$5850_Y + attribute \src "libresoc.v:139556.18-139556.132" + wire $ternary$libresoc.v:139556$5851_Y + attribute \src "libresoc.v:139557.18-139557.132" + wire $ternary$libresoc.v:139557$5852_Y + attribute \src "libresoc.v:139558.18-139558.131" + wire $ternary$libresoc.v:139558$5853_Y + attribute \src "libresoc.v:139559.18-139559.133" + wire $ternary$libresoc.v:139559$5854_Y + attribute \src "libresoc.v:139560.18-139560.133" + wire $ternary$libresoc.v:139560$5855_Y + attribute \src "libresoc.v:139561.18-139561.132" + wire $ternary$libresoc.v:139561$5856_Y + attribute \src "libresoc.v:139562.18-139562.133" + wire $ternary$libresoc.v:139562$5857_Y + attribute \src "libresoc.v:139564.18-139564.133" + wire $ternary$libresoc.v:139564$5859_Y + attribute \src "libresoc.v:139565.18-139565.132" + wire $ternary$libresoc.v:139565$5860_Y + attribute \src "libresoc.v:139566.18-139566.133" + wire $ternary$libresoc.v:139566$5861_Y + attribute \src "libresoc.v:139567.18-139567.133" + wire $ternary$libresoc.v:139567$5862_Y + attribute \src "libresoc.v:139568.18-139568.132" + wire $ternary$libresoc.v:139568$5863_Y + attribute \src "libresoc.v:139569.18-139569.133" + wire $ternary$libresoc.v:139569$5864_Y + attribute \src "libresoc.v:139570.18-139570.133" + wire $ternary$libresoc.v:139570$5865_Y + attribute \src "libresoc.v:139571.18-139571.132" + wire $ternary$libresoc.v:139571$5866_Y + attribute \src "libresoc.v:139572.18-139572.133" + wire $ternary$libresoc.v:139572$5867_Y + attribute \src "libresoc.v:139573.18-139573.133" + wire $ternary$libresoc.v:139573$5868_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$101 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$103 + wire \$101 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$105 + wire \$103 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$107 + wire \$105 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$109 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$111 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$113 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$115 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$117 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$119 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$121 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$123 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$125 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$127 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$129 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$131 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$133 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$135 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$137 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$139 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$141 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$143 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$145 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$147 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$149 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$15 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$151 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$151 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$153 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$155 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$157 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$159 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$161 + wire \$159 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$163 + wire \$161 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$163 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$165 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$167 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$169 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" wire \$17 @@ -218525,107 +218321,107 @@ module \jtag wire \$215 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$217 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$219 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$221 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$223 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$225 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$227 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$229 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$231 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$233 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$235 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$237 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$239 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$241 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$243 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$245 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$247 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$249 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$251 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$253 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$255 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$257 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$259 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$261 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$263 + wire \$261 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$265 + wire \$263 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$267 + wire \$265 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$267 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$269 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$271 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$273 + wire \$271 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$275 + wire \$273 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$277 + wire \$275 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$279 + wire \$277 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$281 + wire \$279 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$283 + wire \$281 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$285 + wire \$283 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$287 + wire \$285 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$287 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$289 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$291 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$293 + wire \$291 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$295 + wire \$293 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$297 + wire \$295 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$297 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$299 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$301 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$301 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$303 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$305 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$307 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$309 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" wire \$31 @@ -218811,59 +218607,59 @@ module \jtag wire \$49 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$51 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$53 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$55 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$57 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$59 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$61 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$63 + wire \$61 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$65 + wire \$63 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$67 + wire \$65 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$69 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$71 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$73 + wire \$71 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$75 + wire \$73 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$77 + wire \$75 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$79 + wire \$77 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$81 + wire \$79 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$83 + wire \$81 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$85 + wire \$83 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$87 + wire \$85 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$89 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" wire \$9 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$91 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$93 + wire \$91 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$95 + wire \$93 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$97 + wire \$95 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 280 \TAP_bus__tck @@ -218895,24 +218691,24 @@ module \jtag wire width 4 \_irblock_ir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 282 \clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire input 6 \dmi0__ack_o + wire input 5 \dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 4 output 2 \dmi0__addr_i + wire width 4 output 1 \dmi0__addr_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 4 \dmi0__addr_i$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 output 5 \dmi0__din + wire width 64 output 4 \dmi0__din attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 64 \dmi0__din$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 input 7 \dmi0__dout + wire width 64 input 6 \dmi0__dout attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire output 3 \dmi0__req_i + wire output 2 \dmi0__req_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire output 4 \dmi0__we_i + wire output 3 \dmi0__we_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" wire width 8 \dmi0_addrsr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" @@ -218972,17 +218768,17 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 141 \eint_0__core__i + wire output 268 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 10 \eint_0__pad__i + wire input 137 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 142 \eint_1__core__i + wire output 269 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 11 \eint_1__pad__i + wire input 138 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 143 \eint_2__core__i + wire output 270 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 12 \eint_2__pad__i + wire input 139 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" @@ -218992,198 +218788,198 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 150 \gpio_e10__core__i + wire output 222 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 20 \gpio_e10__core__o + wire input 92 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 21 \gpio_e10__core__oe + wire input 93 \gpio_e10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 19 \gpio_e10__pad__i + wire input 91 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 151 \gpio_e10__pad__o + wire output 223 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 152 \gpio_e10__pad__oe + wire output 224 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 153 \gpio_e11__core__i + wire output 225 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 23 \gpio_e11__core__o + wire input 95 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \gpio_e11__core__oe + wire input 96 \gpio_e11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 22 \gpio_e11__pad__i + wire input 94 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 154 \gpio_e11__pad__o + wire output 226 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 155 \gpio_e11__pad__oe + wire output 227 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 156 \gpio_e12__core__i + wire output 228 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \gpio_e12__core__o + wire input 98 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e12__core__oe + wire input 99 \gpio_e12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 25 \gpio_e12__pad__i + wire input 97 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 157 \gpio_e12__pad__o + wire output 229 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 158 \gpio_e12__pad__oe + wire output 230 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 159 \gpio_e13__core__i + wire output 231 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 29 \gpio_e13__core__o + wire input 101 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 30 \gpio_e13__core__oe + wire input 102 \gpio_e13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e13__pad__i + wire input 100 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 160 \gpio_e13__pad__o + wire output 232 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 161 \gpio_e13__pad__oe + wire output 233 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 162 \gpio_e14__core__i + wire output 234 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e14__core__o + wire input 104 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e14__core__oe + wire input 105 \gpio_e14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 31 \gpio_e14__pad__i + wire input 103 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 163 \gpio_e14__pad__o + wire output 235 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 164 \gpio_e14__pad__oe + wire output 236 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 165 \gpio_e15__core__i + wire output 237 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 35 \gpio_e15__core__o + wire input 107 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 36 \gpio_e15__core__oe + wire input 108 \gpio_e15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e15__pad__i + wire input 106 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \gpio_e15__pad__o + wire output 238 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \gpio_e15__pad__oe + wire output 239 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 144 \gpio_e8__core__i + wire output 216 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 14 \gpio_e8__core__o + wire input 86 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 15 \gpio_e8__core__oe + wire input 87 \gpio_e8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 13 \gpio_e8__pad__i + wire input 85 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 145 \gpio_e8__pad__o + wire output 217 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 146 \gpio_e8__pad__oe + wire output 218 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 147 \gpio_e9__core__i + wire output 219 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 17 \gpio_e9__core__o + wire input 89 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 18 \gpio_e9__core__oe + wire input 90 \gpio_e9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 16 \gpio_e9__pad__i + wire input 88 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 148 \gpio_e9__pad__o + wire output 220 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 149 \gpio_e9__pad__oe + wire output 221 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \gpio_s0__core__i + wire output 240 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_s0__core__o + wire input 110 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_s0__core__oe + wire input 111 \gpio_s0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 37 \gpio_s0__pad__i + wire input 109 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_s0__pad__o + wire output 241 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_s0__pad__oe + wire output 242 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_s1__core__i + wire output 243 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 41 \gpio_s1__core__o + wire input 113 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 42 \gpio_s1__core__oe + wire input 114 \gpio_s1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_s1__pad__i + wire input 112 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_s1__pad__o + wire output 244 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_s1__pad__oe + wire output 245 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_s2__core__i + wire output 246 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_s2__core__o + wire input 116 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_s2__core__oe + wire input 117 \gpio_s2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 43 \gpio_s2__pad__i + wire input 115 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_s2__pad__o + wire output 247 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_s2__pad__oe + wire output 248 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_s3__core__i + wire output 249 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 47 \gpio_s3__core__o + wire input 119 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 48 \gpio_s3__core__oe + wire input 120 \gpio_s3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_s3__pad__i + wire input 118 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_s3__pad__o + wire output 250 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_s3__pad__oe + wire output 251 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_s4__core__i + wire output 252 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_s4__core__o + wire input 122 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_s4__core__oe + wire input 123 \gpio_s4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 49 \gpio_s4__pad__i + wire input 121 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_s4__pad__o + wire output 253 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_s4__pad__oe + wire output 254 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_s5__core__i + wire output 255 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 53 \gpio_s5__core__o + wire input 125 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 54 \gpio_s5__core__oe + wire input 126 \gpio_s5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_s5__pad__i + wire input 124 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_s5__pad__o + wire output 256 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_s5__pad__oe + wire output 257 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_s6__core__i + wire output 258 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_s6__core__o + wire input 128 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_s6__core__oe + wire input 129 \gpio_s6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 55 \gpio_s6__pad__i + wire input 127 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_s6__pad__o + wire output 259 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_s6__pad__oe + wire output 260 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_s7__core__i + wire output 261 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 59 \gpio_s7__core__o + wire input 131 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 60 \gpio_s7__core__oe + wire input 132 \gpio_s7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_s7__pad__i + wire input 130 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_s7__pad__o + wire output 262 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_s7__pad__oe - attribute \src "libresoc.v:138256.7-138256.15" + wire output 263 \gpio_s7__pad__oe + attribute \src "libresoc.v:138052.7-138052.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" wire width 130 \io_bd @@ -219282,37 +219078,37 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 61 \mspi0_clk__core__o + wire input 10 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \mspi0_clk__pad__o + wire output 141 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \mspi0_cs_n__core__o + wire input 11 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \mspi0_cs_n__pad__o + wire output 142 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \mspi0_miso__core__i + wire output 144 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \mspi0_miso__pad__i + wire input 13 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \mspi0_mosi__core__o + wire input 12 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \mspi0_mosi__pad__o + wire output 143 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \mtwi_scl__core__o + wire input 136 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \mtwi_scl__pad__o + wire output 267 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \mtwi_sda__core__i + wire output 264 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \mtwi_sda__core__o + wire input 134 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \mtwi_sda__core__oe + wire input 135 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 65 \mtwi_sda__pad__i + wire input 133 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \mtwi_sda__pad__o + wire output 265 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \mtwi_sda__pad__oe + wire output 266 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire \negjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" @@ -219321,292 +219117,292 @@ module \jtag wire \posjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" - wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" + wire input 7 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sdr_a_0__core__o + wire input 39 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \sdr_a_0__pad__o + wire output 170 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_a_10__core__o + wire input 57 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sdr_a_10__pad__o + wire output 188 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_a_11__core__o + wire input 58 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sdr_a_11__pad__o + wire output 189 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_a_12__core__o + wire input 59 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sdr_a_12__pad__o + wire output 190 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sdr_a_1__core__o + wire input 40 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \sdr_a_1__pad__o + wire output 171 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sdr_a_2__core__o + wire input 41 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \sdr_a_2__pad__o + wire output 172 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sdr_a_3__core__o + wire input 42 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \sdr_a_3__pad__o + wire output 173 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sdr_a_4__core__o + wire input 43 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \sdr_a_4__pad__o + wire output 174 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sdr_a_5__core__o + wire input 44 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sdr_a_5__pad__o + wire output 175 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sdr_a_6__core__o + wire input 45 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sdr_a_6__pad__o + wire output 176 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sdr_a_7__core__o + wire input 46 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sdr_a_7__pad__o + wire output 177 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sdr_a_8__core__o + wire input 47 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sdr_a_8__pad__o + wire output 178 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sdr_a_9__core__o + wire input 48 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sdr_a_9__pad__o + wire output 179 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sdr_ba_0__core__o + wire input 49 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sdr_ba_0__pad__o + wire output 180 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_ba_1__core__o + wire input 50 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sdr_ba_1__pad__o + wire output 181 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_cas_n__core__o + wire input 54 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sdr_cas_n__pad__o + wire output 185 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_cke__core__o + wire input 52 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sdr_cke__pad__o + wire output 183 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_clock__core__o + wire input 51 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sdr_clock__pad__o + wire output 182 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_cs_n__core__o + wire input 56 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sdr_cs_n__pad__o + wire output 187 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \sdr_dm_0__core__o + wire input 14 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \sdr_dm_0__pad__o + wire output 145 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dm_1__core__o + wire input 60 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_dm_1__pad__o + wire output 191 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \sdr_dq_0__core__i + wire output 146 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \sdr_dq_0__core__o + wire input 16 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \sdr_dq_0__core__oe + wire input 17 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \sdr_dq_0__pad__i + wire input 15 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \sdr_dq_0__pad__o + wire output 147 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \sdr_dq_0__pad__oe + wire output 148 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_10__core__i + wire output 198 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_dq_10__core__o + wire input 68 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_dq_10__core__oe + wire input 69 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_dq_10__pad__i + wire input 67 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_10__pad__o + wire output 199 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_10__pad__oe + wire output 200 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_11__core__i + wire output 201 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_dq_11__core__o + wire input 71 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_dq_11__core__oe + wire input 72 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_dq_11__pad__i + wire input 70 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_11__pad__o + wire output 202 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_11__pad__oe + wire output 203 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_12__core__i + wire output 204 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_dq_12__core__o + wire input 74 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_dq_12__core__oe + wire input 75 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_dq_12__pad__i + wire input 73 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_12__pad__o + wire output 205 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_12__pad__oe + wire output 206 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_13__core__i + wire output 207 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_dq_13__core__o + wire input 77 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_dq_13__core__oe + wire input 78 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_dq_13__pad__i + wire input 76 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_13__pad__o + wire output 208 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_13__pad__oe + wire output 209 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_14__core__i + wire output 210 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_dq_14__core__o + wire input 80 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_dq_14__core__oe + wire input 81 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_dq_14__pad__i + wire input 79 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_14__pad__o + wire output 211 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_14__pad__oe + wire output 212 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_15__core__i + wire output 213 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dq_15__core__o + wire input 83 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dq_15__core__oe + wire input 84 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_dq_15__pad__i + wire input 82 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_15__pad__o + wire output 214 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_15__pad__oe + wire output 215 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \sdr_dq_1__core__i + wire output 149 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \sdr_dq_1__core__o + wire input 19 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \sdr_dq_1__core__oe + wire input 20 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \sdr_dq_1__pad__i + wire input 18 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \sdr_dq_1__pad__o + wire output 150 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \sdr_dq_1__pad__oe + wire output 151 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \sdr_dq_2__core__i + wire output 152 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \sdr_dq_2__core__o + wire input 22 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \sdr_dq_2__core__oe + wire input 23 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \sdr_dq_2__pad__i + wire input 21 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \sdr_dq_2__pad__o + wire output 153 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \sdr_dq_2__pad__oe + wire output 154 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \sdr_dq_3__core__i + wire output 155 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \sdr_dq_3__core__o + wire input 25 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \sdr_dq_3__core__oe + wire input 26 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \sdr_dq_3__pad__i + wire input 24 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \sdr_dq_3__pad__o + wire output 156 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \sdr_dq_3__pad__oe + wire output 157 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \sdr_dq_4__core__i + wire output 158 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \sdr_dq_4__core__o + wire input 28 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \sdr_dq_4__core__oe + wire input 29 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \sdr_dq_4__pad__i + wire input 27 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \sdr_dq_4__pad__o + wire output 159 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \sdr_dq_4__pad__oe + wire output 160 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \sdr_dq_5__core__i + wire output 161 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \sdr_dq_5__core__o + wire input 31 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \sdr_dq_5__core__oe + wire input 32 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \sdr_dq_5__pad__i + wire input 30 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \sdr_dq_5__pad__o + wire output 162 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \sdr_dq_5__pad__oe + wire output 163 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \sdr_dq_6__core__i + wire output 164 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sdr_dq_6__core__o + wire input 34 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sdr_dq_6__core__oe + wire input 35 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \sdr_dq_6__pad__i + wire input 33 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \sdr_dq_6__pad__o + wire output 165 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \sdr_dq_6__pad__oe + wire output 166 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \sdr_dq_7__core__i + wire output 167 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sdr_dq_7__core__o + wire input 37 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sdr_dq_7__core__oe + wire input 38 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sdr_dq_7__pad__i + wire input 36 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \sdr_dq_7__pad__o + wire output 168 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \sdr_dq_7__pad__oe + wire output 169 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dq_8__core__i + wire output 192 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_dq_8__core__o + wire input 62 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_dq_8__core__oe + wire input 63 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_dq_8__pad__i + wire input 61 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_8__pad__o + wire output 193 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_8__pad__oe + wire output 194 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_dq_9__core__i + wire output 195 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_dq_9__core__o + wire input 65 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_dq_9__core__oe + wire input 66 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_dq_9__pad__i + wire input 64 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dq_9__pad__o + wire output 196 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_9__pad__oe + wire output 197 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_ras_n__core__o + wire input 53 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sdr_ras_n__pad__o + wire output 184 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_we_n__core__o + wire input 55 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sdr_we_n__pad__o + wire output 186 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" @@ -219678,7 +219474,7 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \wb_sram_en$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - cell $add $add$libresoc.v:139740$5830 + cell $add $add$libresoc.v:139536$5830 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -219686,10 +219482,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:139740$5830_Y + connect \Y $add$libresoc.v:139536$5830_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - cell $add $add$libresoc.v:139741$5831 + cell $add $add$libresoc.v:139537$5831 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -219697,10 +219493,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:139741$5831_Y + connect \Y $add$libresoc.v:139537$5831_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - cell $add $add$libresoc.v:139748$5839 + cell $add $add$libresoc.v:139544$5839 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -219708,10 +219504,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:139748$5839_Y + connect \Y $add$libresoc.v:139544$5839_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - cell $add $add$libresoc.v:139749$5840 + cell $add $add$libresoc.v:139545$5840 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -219719,10 +219515,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:139749$5840_Y + connect \Y $add$libresoc.v:139545$5840_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $and $and$libresoc.v:139590$5680 + cell $and $and$libresoc.v:139386$5680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219730,10 +219526,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$15 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139590$5680_Y + connect \Y $and$libresoc.v:139386$5680_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139657$5747 + cell $and $and$libresoc.v:139453$5747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219741,10 +219537,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$27 - connect \Y $and$libresoc.v:139657$5747_Y + connect \Y $and$libresoc.v:139453$5747_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - cell $and $and$libresoc.v:139668$5758 + cell $and $and$libresoc.v:139464$5758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219752,10 +219548,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$29 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139668$5758_Y + connect \Y $and$libresoc.v:139464$5758_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139670$5760 + cell $and $and$libresoc.v:139466$5760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219763,10 +219559,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$319 - connect \Y $and$libresoc.v:139670$5760_Y + connect \Y $and$libresoc.v:139466$5760_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139673$5763 + cell $and $and$libresoc.v:139469$5763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219774,10 +219570,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$325 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139673$5763_Y + connect \Y $and$libresoc.v:139469$5763_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139675$5765 + cell $and $and$libresoc.v:139471$5765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219785,10 +219581,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$329 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139675$5765_Y + connect \Y $and$libresoc.v:139471$5765_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139677$5767 + cell $and $and$libresoc.v:139473$5767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219796,10 +219592,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$333 connect \B \_fsm_update - connect \Y $and$libresoc.v:139677$5767_Y + connect \Y $and$libresoc.v:139473$5767_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139680$5770 + cell $and $and$libresoc.v:139476$5770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219807,10 +219603,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_update_core_prev connect \B \$337 - connect \Y $and$libresoc.v:139680$5770_Y + connect \Y $and$libresoc.v:139476$5770_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139683$5773 + cell $and $and$libresoc.v:139479$5773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219818,10 +219614,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$343 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139683$5773_Y + connect \Y $and$libresoc.v:139479$5773_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139685$5775 + cell $and $and$libresoc.v:139481$5775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219829,10 +219625,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$347 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139685$5775_Y + connect \Y $and$libresoc.v:139481$5775_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139687$5777 + cell $and $and$libresoc.v:139483$5777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219840,10 +219636,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$351 connect \B \_fsm_update - connect \Y $and$libresoc.v:139687$5777_Y + connect \Y $and$libresoc.v:139483$5777_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139689$5779 + cell $and $and$libresoc.v:139485$5779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219851,10 +219647,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core_prev connect \B \$355 - connect \Y $and$libresoc.v:139689$5779_Y + connect \Y $and$libresoc.v:139485$5779_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139694$5784 + cell $and $and$libresoc.v:139490$5784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219862,10 +219658,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$363 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139694$5784_Y + connect \Y $and$libresoc.v:139490$5784_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139696$5786 + cell $and $and$libresoc.v:139492$5786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219873,10 +219669,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$367 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139696$5786_Y + connect \Y $and$libresoc.v:139492$5786_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139698$5788 + cell $and $and$libresoc.v:139494$5788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219884,10 +219680,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$371 connect \B \_fsm_update - connect \Y $and$libresoc.v:139698$5788_Y + connect \Y $and$libresoc.v:139494$5788_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139700$5790 + cell $and $and$libresoc.v:139496$5790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219895,10 +219691,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core_prev connect \B \$375 - connect \Y $and$libresoc.v:139700$5790_Y + connect \Y $and$libresoc.v:139496$5790_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139704$5794 + cell $and $and$libresoc.v:139500$5794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219906,10 +219702,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$381 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139704$5794_Y + connect \Y $and$libresoc.v:139500$5794_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139706$5796 + cell $and $and$libresoc.v:139502$5796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219917,10 +219713,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$385 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139706$5796_Y + connect \Y $and$libresoc.v:139502$5796_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139708$5798 + cell $and $and$libresoc.v:139504$5798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219928,10 +219724,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$389 connect \B \_fsm_update - connect \Y $and$libresoc.v:139708$5798_Y + connect \Y $and$libresoc.v:139504$5798_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139710$5800 + cell $and $and$libresoc.v:139506$5800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219939,10 +219735,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core_prev connect \B \$393 - connect \Y $and$libresoc.v:139710$5800_Y + connect \Y $and$libresoc.v:139506$5800_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139716$5806 + cell $and $and$libresoc.v:139512$5806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219950,10 +219746,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$401 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139716$5806_Y + connect \Y $and$libresoc.v:139512$5806_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139718$5808 + cell $and $and$libresoc.v:139514$5808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219961,10 +219757,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$405 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139718$5808_Y + connect \Y $and$libresoc.v:139514$5808_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139720$5810 + cell $and $and$libresoc.v:139516$5810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219972,10 +219768,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$409 connect \B \_fsm_update - connect \Y $and$libresoc.v:139720$5810_Y + connect \Y $and$libresoc.v:139516$5810_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139722$5812 + cell $and $and$libresoc.v:139518$5812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219983,10 +219779,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core_prev connect \B \$413 - connect \Y $and$libresoc.v:139722$5812_Y + connect \Y $and$libresoc.v:139518$5812_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139726$5816 + cell $and $and$libresoc.v:139522$5816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219994,10 +219790,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$419 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139726$5816_Y + connect \Y $and$libresoc.v:139522$5816_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139728$5818 + cell $and $and$libresoc.v:139524$5818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220005,10 +219801,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$423 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139728$5818_Y + connect \Y $and$libresoc.v:139524$5818_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139730$5820 + cell $and $and$libresoc.v:139526$5820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220016,10 +219812,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$427 connect \B \_fsm_update - connect \Y $and$libresoc.v:139730$5820_Y + connect \Y $and$libresoc.v:139526$5820_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139732$5822 + cell $and $and$libresoc.v:139528$5822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220027,10 +219823,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_update_core_prev connect \B \$431 - connect \Y $and$libresoc.v:139732$5822_Y + connect \Y $and$libresoc.v:139528$5822_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139735$5825 + cell $and $and$libresoc.v:139531$5825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220038,10 +219834,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$41 - connect \Y $and$libresoc.v:139735$5825_Y + connect \Y $and$libresoc.v:139531$5825_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - cell $and $and$libresoc.v:139745$5836 + cell $and $and$libresoc.v:139541$5836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220049,10 +219845,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$43 connect \B \_fsm_update - connect \Y $and$libresoc.v:139745$5836_Y + connect \Y $and$libresoc.v:139541$5836_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $and $and$libresoc.v:139767$5858 + cell $and $and$libresoc.v:139563$5858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220060,10 +219856,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$5 - connect \Y $and$libresoc.v:139767$5858_Y + connect \Y $and$libresoc.v:139563$5858_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:139546$5636 + cell $eq $eq$libresoc.v:139342$5636 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220071,10 +219867,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:139546$5636_Y + connect \Y $eq$libresoc.v:139342$5636_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139557$5647 + cell $eq $eq$libresoc.v:139353$5647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220082,10 +219878,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139557$5647_Y + connect \Y $eq$libresoc.v:139353$5647_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139568$5658 + cell $eq $eq$libresoc.v:139364$5658 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220093,10 +219889,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139568$5658_Y + connect \Y $eq$libresoc.v:139364$5658_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:139601$5691 + cell $eq $eq$libresoc.v:139397$5691 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220104,10 +219900,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'1 - connect \Y $eq$libresoc.v:139601$5691_Y + connect \Y $eq$libresoc.v:139397$5691_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139602$5692 + cell $eq $eq$libresoc.v:139398$5692 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220115,10 +219911,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139602$5692_Y + connect \Y $eq$libresoc.v:139398$5692_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139613$5703 + cell $eq $eq$libresoc.v:139409$5703 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220126,10 +219922,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139613$5703_Y + connect \Y $eq$libresoc.v:139409$5703_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139635$5725 + cell $eq $eq$libresoc.v:139431$5725 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220137,10 +219933,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139635$5725_Y + connect \Y $eq$libresoc.v:139431$5725_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139664$5754 + cell $eq $eq$libresoc.v:139460$5754 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220148,10 +219944,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139664$5754_Y + connect \Y $eq$libresoc.v:139460$5754_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139665$5755 + cell $eq $eq$libresoc.v:139461$5755 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220159,10 +219955,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139665$5755_Y + connect \Y $eq$libresoc.v:139461$5755_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139667$5757 + cell $eq $eq$libresoc.v:139463$5757 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220170,10 +219966,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139667$5757_Y + connect \Y $eq$libresoc.v:139463$5757_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139671$5761 + cell $eq $eq$libresoc.v:139467$5761 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220181,10 +219977,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'100 - connect \Y $eq$libresoc.v:139671$5761_Y + connect \Y $eq$libresoc.v:139467$5761_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139679$5769 + cell $eq $eq$libresoc.v:139475$5769 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220192,10 +219988,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139679$5769_Y + connect \Y $eq$libresoc.v:139475$5769_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139681$5771 + cell $eq $eq$libresoc.v:139477$5771 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220203,10 +219999,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'101 - connect \Y $eq$libresoc.v:139681$5771_Y + connect \Y $eq$libresoc.v:139477$5771_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139690$5780 + cell $eq $eq$libresoc.v:139486$5780 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220214,10 +220010,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139690$5780_Y + connect \Y $eq$libresoc.v:139486$5780_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139691$5781 + cell $eq $eq$libresoc.v:139487$5781 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220225,10 +220021,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'110 - connect \Y $eq$libresoc.v:139691$5781_Y + connect \Y $eq$libresoc.v:139487$5781_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139692$5782 + cell $eq $eq$libresoc.v:139488$5782 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220236,10 +220032,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'111 - connect \Y $eq$libresoc.v:139692$5782_Y + connect \Y $eq$libresoc.v:139488$5782_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139702$5792 + cell $eq $eq$libresoc.v:139498$5792 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220247,10 +220043,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1000 - connect \Y $eq$libresoc.v:139702$5792_Y + connect \Y $eq$libresoc.v:139498$5792_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139711$5801 + cell $eq $eq$libresoc.v:139507$5801 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220258,10 +220054,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1001 - connect \Y $eq$libresoc.v:139711$5801_Y + connect \Y $eq$libresoc.v:139507$5801_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:139712$5802 + cell $eq $eq$libresoc.v:139508$5802 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220269,10 +220065,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:139712$5802_Y + connect \Y $eq$libresoc.v:139508$5802_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139713$5803 + cell $eq $eq$libresoc.v:139509$5803 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220280,10 +220076,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139713$5803_Y + connect \Y $eq$libresoc.v:139509$5803_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139714$5804 + cell $eq $eq$libresoc.v:139510$5804 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220291,10 +220087,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1010 - connect \Y $eq$libresoc.v:139714$5804_Y + connect \Y $eq$libresoc.v:139510$5804_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139723$5813 + cell $eq $eq$libresoc.v:139519$5813 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220302,10 +220098,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1011 - connect \Y $eq$libresoc.v:139723$5813_Y + connect \Y $eq$libresoc.v:139519$5813_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $eq $eq$libresoc.v:139733$5823 + cell $eq $eq$libresoc.v:139529$5823 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220313,10 +220109,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 - connect \Y $eq$libresoc.v:139733$5823_Y + connect \Y $eq$libresoc.v:139529$5823_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:139736$5826 + cell $eq $eq$libresoc.v:139532$5826 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220324,10 +220120,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'1 - connect \Y $eq$libresoc.v:139736$5826_Y + connect \Y $eq$libresoc.v:139532$5826_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:139737$5827 + cell $eq $eq$libresoc.v:139533$5827 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220335,10 +220131,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:139737$5827_Y + connect \Y $eq$libresoc.v:139533$5827_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - cell $eq $eq$libresoc.v:139739$5829 + cell $eq $eq$libresoc.v:139535$5829 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220346,10 +220142,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:139739$5829_Y + connect \Y $eq$libresoc.v:139535$5829_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:139743$5834 + cell $eq $eq$libresoc.v:139539$5834 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220357,10 +220153,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$455 connect \B 1'1 - connect \Y $eq$libresoc.v:139743$5834_Y + connect \Y $eq$libresoc.v:139539$5834_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:139744$5835 + cell $eq $eq$libresoc.v:139540$5835 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220368,10 +220164,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$455 connect \B 2'10 - connect \Y $eq$libresoc.v:139744$5835_Y + connect \Y $eq$libresoc.v:139540$5835_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - cell $eq $eq$libresoc.v:139747$5838 + cell $eq $eq$libresoc.v:139543$5838 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220379,10 +220175,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$455 connect \B 2'10 - connect \Y $eq$libresoc.v:139747$5838_Y + connect \Y $eq$libresoc.v:139543$5838_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - cell $eq $eq$libresoc.v:139750$5841 + cell $eq $eq$libresoc.v:139546$5841 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220390,10 +220186,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139750$5841_Y + connect \Y $eq$libresoc.v:139546$5841_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - cell $eq $eq$libresoc.v:139751$5842 + cell $eq $eq$libresoc.v:139547$5842 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220401,18 +220197,18 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139751$5842_Y + connect \Y $eq$libresoc.v:139547$5842_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $extend$libresoc.v:139742$5832 + cell $pos $extend$libresoc.v:139538$5832 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \dmi0__addr_i - connect \Y $extend$libresoc.v:139742$5832_Y + connect \Y $extend$libresoc.v:139538$5832_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139672$5762 + cell $ne $ne$libresoc.v:139468$5762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220420,10 +220216,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139672$5762_Y + connect \Y $ne$libresoc.v:139468$5762_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139674$5764 + cell $ne $ne$libresoc.v:139470$5764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220431,10 +220227,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139674$5764_Y + connect \Y $ne$libresoc.v:139470$5764_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139676$5766 + cell $ne $ne$libresoc.v:139472$5766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220442,10 +220238,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139676$5766_Y + connect \Y $ne$libresoc.v:139472$5766_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139682$5772 + cell $ne $ne$libresoc.v:139478$5772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220453,10 +220249,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139682$5772_Y + connect \Y $ne$libresoc.v:139478$5772_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139684$5774 + cell $ne $ne$libresoc.v:139480$5774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220464,10 +220260,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139684$5774_Y + connect \Y $ne$libresoc.v:139480$5774_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139686$5776 + cell $ne $ne$libresoc.v:139482$5776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220475,10 +220271,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139686$5776_Y + connect \Y $ne$libresoc.v:139482$5776_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139693$5783 + cell $ne $ne$libresoc.v:139489$5783 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220486,10 +220282,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139693$5783_Y + connect \Y $ne$libresoc.v:139489$5783_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139695$5785 + cell $ne $ne$libresoc.v:139491$5785 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220497,10 +220293,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139695$5785_Y + connect \Y $ne$libresoc.v:139491$5785_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139697$5787 + cell $ne $ne$libresoc.v:139493$5787 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220508,10 +220304,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139697$5787_Y + connect \Y $ne$libresoc.v:139493$5787_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139703$5793 + cell $ne $ne$libresoc.v:139499$5793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220519,10 +220315,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139703$5793_Y + connect \Y $ne$libresoc.v:139499$5793_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139705$5795 + cell $ne $ne$libresoc.v:139501$5795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220530,10 +220326,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139705$5795_Y + connect \Y $ne$libresoc.v:139501$5795_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139707$5797 + cell $ne $ne$libresoc.v:139503$5797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220541,10 +220337,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139707$5797_Y + connect \Y $ne$libresoc.v:139503$5797_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139715$5805 + cell $ne $ne$libresoc.v:139511$5805 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220552,10 +220348,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139715$5805_Y + connect \Y $ne$libresoc.v:139511$5805_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139717$5807 + cell $ne $ne$libresoc.v:139513$5807 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220563,10 +220359,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139717$5807_Y + connect \Y $ne$libresoc.v:139513$5807_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139719$5809 + cell $ne $ne$libresoc.v:139515$5809 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220574,10 +220370,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139719$5809_Y + connect \Y $ne$libresoc.v:139515$5809_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139725$5815 + cell $ne $ne$libresoc.v:139521$5815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220585,10 +220381,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139725$5815_Y + connect \Y $ne$libresoc.v:139521$5815_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139727$5817 + cell $ne $ne$libresoc.v:139523$5817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220596,10 +220392,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139727$5817_Y + connect \Y $ne$libresoc.v:139523$5817_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139729$5819 + cell $ne $ne$libresoc.v:139525$5819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220607,66 +220403,66 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139729$5819_Y + connect \Y $ne$libresoc.v:139525$5819_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139678$5768 + cell $not $not$libresoc.v:139474$5768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core - connect \Y $not$libresoc.v:139678$5768_Y + connect \Y $not$libresoc.v:139474$5768_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139688$5778 + cell $not $not$libresoc.v:139484$5778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:139688$5778_Y + connect \Y $not$libresoc.v:139484$5778_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139699$5789 + cell $not $not$libresoc.v:139495$5789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:139699$5789_Y + connect \Y $not$libresoc.v:139495$5789_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139709$5799 + cell $not $not$libresoc.v:139505$5799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:139709$5799_Y + connect \Y $not$libresoc.v:139505$5799_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139721$5811 + cell $not $not$libresoc.v:139517$5811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:139721$5811_Y + connect \Y $not$libresoc.v:139517$5811_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139731$5821 + cell $not $not$libresoc.v:139527$5821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core - connect \Y $not$libresoc.v:139731$5821_Y + connect \Y $not$libresoc.v:139527$5821_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $not $not$libresoc.v:139734$5824 + cell $not $not$libresoc.v:139530$5824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$436 - connect \Y $not$libresoc.v:139734$5824_Y + connect \Y $not$libresoc.v:139530$5824_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139579$5669 + cell $or $or$libresoc.v:139375$5669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220674,10 +220470,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$11 connect \B \$13 - connect \Y $or$libresoc.v:139579$5669_Y + connect \Y $or$libresoc.v:139375$5669_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139624$5714 + cell $or $or$libresoc.v:139420$5714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220685,10 +220481,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$19 connect \B \$21 - connect \Y $or$libresoc.v:139624$5714_Y + connect \Y $or$libresoc.v:139420$5714_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139646$5736 + cell $or $or$libresoc.v:139442$5736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220696,10 +220492,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:139646$5736_Y + connect \Y $or$libresoc.v:139442$5736_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139666$5756 + cell $or $or$libresoc.v:139462$5756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220707,10 +220503,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$311 connect \B \$313 - connect \Y $or$libresoc.v:139666$5756_Y + connect \Y $or$libresoc.v:139462$5756_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139669$5759 + cell $or $or$libresoc.v:139465$5759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220718,10 +220514,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$315 connect \B \$317 - connect \Y $or$libresoc.v:139669$5759_Y + connect \Y $or$libresoc.v:139465$5759_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139701$5791 + cell $or $or$libresoc.v:139497$5791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220729,10 +220525,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:139701$5791_Y + connect \Y $or$libresoc.v:139497$5791_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139724$5814 + cell $or $or$libresoc.v:139520$5814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220740,10 +220536,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:139724$5814_Y + connect \Y $or$libresoc.v:139520$5814_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $or $or$libresoc.v:139738$5828 + cell $or $or$libresoc.v:139534$5828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220751,10 +220547,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$439 connect \B \$441 - connect \Y $or$libresoc.v:139738$5828_Y + connect \Y $or$libresoc.v:139534$5828_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $or $or$libresoc.v:139746$5837 + cell $or $or$libresoc.v:139542$5837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220762,10 +220558,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$456 connect \B \$458 - connect \Y $or$libresoc.v:139746$5837_Y + connect \Y $or$libresoc.v:139542$5837_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $or $or$libresoc.v:139756$5847 + cell $or $or$libresoc.v:139552$5847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220773,1058 +220569,1058 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $or$libresoc.v:139756$5847_Y + connect \Y $or$libresoc.v:139552$5847_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $pos$libresoc.v:139742$5833 + cell $pos $pos$libresoc.v:139538$5833 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:139742$5832_Y - connect \Y $pos$libresoc.v:139742$5833_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139547$5637 - parameter \WIDTH 1 - connect \A \gpio_e15__pad__i - connect \B \io_bd [24] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139547$5637_Y + connect \A $extend$libresoc.v:139538$5832_Y + connect \Y $pos$libresoc.v:139538$5833_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139548$5638 + cell $mux $ternary$libresoc.v:139343$5637 parameter \WIDTH 1 - connect \A \gpio_e15__core__o - connect \B \io_bd [25] + connect \A \sdr_dq_6__core__o + connect \B \io_bd [24] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139548$5638_Y + connect \Y $ternary$libresoc.v:139343$5637_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139549$5639 + cell $mux $ternary$libresoc.v:139344$5638 parameter \WIDTH 1 - connect \A \gpio_e15__core__oe - connect \B \io_bd [26] + connect \A \sdr_dq_6__core__oe + connect \B \io_bd [25] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139549$5639_Y + connect \Y $ternary$libresoc.v:139344$5638_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139550$5640 + cell $mux $ternary$libresoc.v:139345$5639 parameter \WIDTH 1 - connect \A \gpio_s0__pad__i - connect \B \io_bd [27] + connect \A \sdr_dq_7__pad__i + connect \B \io_bd [26] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139550$5640_Y + connect \Y $ternary$libresoc.v:139345$5639_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139551$5641 + cell $mux $ternary$libresoc.v:139346$5640 parameter \WIDTH 1 - connect \A \gpio_s0__core__o - connect \B \io_bd [28] + connect \A \sdr_dq_7__core__o + connect \B \io_bd [27] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139551$5641_Y + connect \Y $ternary$libresoc.v:139346$5640_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139552$5642 + cell $mux $ternary$libresoc.v:139347$5641 parameter \WIDTH 1 - connect \A \gpio_s0__core__oe + connect \A \sdr_dq_7__core__oe + connect \B \io_bd [28] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139347$5641_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139348$5642 + parameter \WIDTH 1 + connect \A \sdr_a_0__core__o connect \B \io_bd [29] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139552$5642_Y + connect \Y $ternary$libresoc.v:139348$5642_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139553$5643 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139349$5643 parameter \WIDTH 1 - connect \A \gpio_s1__pad__i + connect \A \sdr_a_1__core__o connect \B \io_bd [30] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139553$5643_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139349$5643_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139554$5644 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139350$5644 parameter \WIDTH 1 - connect \A \gpio_s1__core__o + connect \A \sdr_a_2__core__o connect \B \io_bd [31] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139554$5644_Y + connect \Y $ternary$libresoc.v:139350$5644_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139555$5645 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139351$5645 parameter \WIDTH 1 - connect \A \gpio_s1__core__oe + connect \A \sdr_a_3__core__o connect \B \io_bd [32] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139555$5645_Y + connect \Y $ternary$libresoc.v:139351$5645_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139556$5646 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139352$5646 parameter \WIDTH 1 - connect \A \gpio_s2__pad__i + connect \A \sdr_a_4__core__o connect \B \io_bd [33] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139556$5646_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139352$5646_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139558$5648 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139354$5648 parameter \WIDTH 1 - connect \A \gpio_s2__core__o + connect \A \sdr_a_5__core__o connect \B \io_bd [34] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139558$5648_Y + connect \Y $ternary$libresoc.v:139354$5648_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139559$5649 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139355$5649 parameter \WIDTH 1 - connect \A \gpio_s2__core__oe + connect \A \sdr_a_6__core__o connect \B \io_bd [35] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139559$5649_Y + connect \Y $ternary$libresoc.v:139355$5649_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139560$5650 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139356$5650 parameter \WIDTH 1 - connect \A \gpio_s3__pad__i + connect \A \sdr_a_7__core__o connect \B \io_bd [36] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139560$5650_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139356$5650_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139561$5651 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139357$5651 parameter \WIDTH 1 - connect \A \gpio_s3__core__o + connect \A \sdr_a_8__core__o connect \B \io_bd [37] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139561$5651_Y + connect \Y $ternary$libresoc.v:139357$5651_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139562$5652 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139358$5652 parameter \WIDTH 1 - connect \A \gpio_s3__core__oe + connect \A \sdr_a_9__core__o connect \B \io_bd [38] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139562$5652_Y + connect \Y $ternary$libresoc.v:139358$5652_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139563$5653 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139359$5653 parameter \WIDTH 1 - connect \A \gpio_s4__pad__i + connect \A \sdr_ba_0__core__o connect \B \io_bd [39] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139563$5653_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139359$5653_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139564$5654 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139360$5654 parameter \WIDTH 1 - connect \A \gpio_s4__core__o + connect \A \sdr_ba_1__core__o connect \B \io_bd [40] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139564$5654_Y + connect \Y $ternary$libresoc.v:139360$5654_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139565$5655 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139361$5655 parameter \WIDTH 1 - connect \A \gpio_s4__core__oe + connect \A \sdr_clock__core__o connect \B \io_bd [41] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139565$5655_Y + connect \Y $ternary$libresoc.v:139361$5655_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139566$5656 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139362$5656 parameter \WIDTH 1 - connect \A \gpio_s5__pad__i + connect \A \sdr_cke__core__o connect \B \io_bd [42] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139566$5656_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139362$5656_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139567$5657 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139363$5657 parameter \WIDTH 1 - connect \A \gpio_s5__core__o + connect \A \sdr_ras_n__core__o connect \B \io_bd [43] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139567$5657_Y + connect \Y $ternary$libresoc.v:139363$5657_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139569$5659 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139365$5659 parameter \WIDTH 1 - connect \A \gpio_s5__core__oe + connect \A \sdr_cas_n__core__o connect \B \io_bd [44] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139569$5659_Y + connect \Y $ternary$libresoc.v:139365$5659_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139570$5660 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139366$5660 parameter \WIDTH 1 - connect \A \gpio_s6__pad__i + connect \A \sdr_we_n__core__o connect \B \io_bd [45] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139570$5660_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139366$5660_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139571$5661 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139367$5661 parameter \WIDTH 1 - connect \A \gpio_s6__core__o + connect \A \sdr_cs_n__core__o connect \B \io_bd [46] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139571$5661_Y + connect \Y $ternary$libresoc.v:139367$5661_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139572$5662 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139368$5662 parameter \WIDTH 1 - connect \A \gpio_s6__core__oe + connect \A \sdr_a_10__core__o connect \B \io_bd [47] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139572$5662_Y + connect \Y $ternary$libresoc.v:139368$5662_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139573$5663 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139369$5663 parameter \WIDTH 1 - connect \A \gpio_s7__pad__i + connect \A \sdr_a_11__core__o connect \B \io_bd [48] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139573$5663_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139369$5663_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139574$5664 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139370$5664 parameter \WIDTH 1 - connect \A \gpio_s7__core__o + connect \A \sdr_a_12__core__o connect \B \io_bd [49] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139574$5664_Y + connect \Y $ternary$libresoc.v:139370$5664_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139575$5665 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139371$5665 parameter \WIDTH 1 - connect \A \gpio_s7__core__oe + connect \A \sdr_dm_1__core__o connect \B \io_bd [50] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139575$5665_Y + connect \Y $ternary$libresoc.v:139371$5665_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139576$5666 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139372$5666 parameter \WIDTH 1 - connect \A \mspi0_clk__core__o + connect \A \sdr_dq_8__pad__i connect \B \io_bd [51] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139576$5666_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139372$5666_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139577$5667 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139373$5667 parameter \WIDTH 1 - connect \A \mspi0_cs_n__core__o + connect \A \sdr_dq_8__core__o connect \B \io_bd [52] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139577$5667_Y + connect \Y $ternary$libresoc.v:139373$5667_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139578$5668 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139374$5668 parameter \WIDTH 1 - connect \A \mspi0_mosi__core__o + connect \A \sdr_dq_8__core__oe connect \B \io_bd [53] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139578$5668_Y + connect \Y $ternary$libresoc.v:139374$5668_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139580$5670 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139376$5670 parameter \WIDTH 1 - connect \A \mspi0_miso__pad__i + connect \A \sdr_dq_9__pad__i connect \B \io_bd [54] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139580$5670_Y + connect \Y $ternary$libresoc.v:139376$5670_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139581$5671 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139377$5671 parameter \WIDTH 1 - connect \A \mtwi_sda__pad__i + connect \A \sdr_dq_9__core__o connect \B \io_bd [55] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139581$5671_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139377$5671_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139582$5672 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139378$5672 parameter \WIDTH 1 - connect \A \mtwi_sda__core__o + connect \A \sdr_dq_9__core__oe connect \B \io_bd [56] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139582$5672_Y + connect \Y $ternary$libresoc.v:139378$5672_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139583$5673 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139379$5673 parameter \WIDTH 1 - connect \A \mtwi_sda__core__oe + connect \A \sdr_dq_10__pad__i connect \B \io_bd [57] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139583$5673_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139379$5673_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139584$5674 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139380$5674 parameter \WIDTH 1 - connect \A \mtwi_scl__core__o + connect \A \sdr_dq_10__core__o connect \B \io_bd [58] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139584$5674_Y + connect \Y $ternary$libresoc.v:139380$5674_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139585$5675 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139381$5675 parameter \WIDTH 1 - connect \A \sdr_dm_0__core__o + connect \A \sdr_dq_10__core__oe connect \B \io_bd [59] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139585$5675_Y + connect \Y $ternary$libresoc.v:139381$5675_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139586$5676 + cell $mux $ternary$libresoc.v:139382$5676 parameter \WIDTH 1 - connect \A \sdr_dq_0__pad__i + connect \A \sdr_dq_11__pad__i connect \B \io_bd [60] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139586$5676_Y + connect \Y $ternary$libresoc.v:139382$5676_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139587$5677 + cell $mux $ternary$libresoc.v:139383$5677 parameter \WIDTH 1 - connect \A \sdr_dq_0__core__o + connect \A \sdr_dq_11__core__o connect \B \io_bd [61] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139587$5677_Y + connect \Y $ternary$libresoc.v:139383$5677_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139588$5678 + cell $mux $ternary$libresoc.v:139384$5678 parameter \WIDTH 1 - connect \A \sdr_dq_0__core__oe + connect \A \sdr_dq_11__core__oe connect \B \io_bd [62] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139588$5678_Y + connect \Y $ternary$libresoc.v:139384$5678_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139589$5679 + cell $mux $ternary$libresoc.v:139385$5679 parameter \WIDTH 1 - connect \A \sdr_dq_1__pad__i + connect \A \sdr_dq_12__pad__i connect \B \io_bd [63] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139589$5679_Y + connect \Y $ternary$libresoc.v:139385$5679_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139591$5681 + cell $mux $ternary$libresoc.v:139387$5681 parameter \WIDTH 1 - connect \A \sdr_dq_1__core__o + connect \A \sdr_dq_12__core__o connect \B \io_bd [64] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139591$5681_Y + connect \Y $ternary$libresoc.v:139387$5681_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139592$5682 + cell $mux $ternary$libresoc.v:139388$5682 parameter \WIDTH 1 - connect \A \sdr_dq_1__core__oe + connect \A \sdr_dq_12__core__oe connect \B \io_bd [65] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139592$5682_Y + connect \Y $ternary$libresoc.v:139388$5682_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139593$5683 + cell $mux $ternary$libresoc.v:139389$5683 parameter \WIDTH 1 - connect \A \sdr_dq_2__pad__i + connect \A \sdr_dq_13__pad__i connect \B \io_bd [66] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139593$5683_Y + connect \Y $ternary$libresoc.v:139389$5683_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139594$5684 + cell $mux $ternary$libresoc.v:139390$5684 parameter \WIDTH 1 - connect \A \sdr_dq_2__core__o + connect \A \sdr_dq_13__core__o connect \B \io_bd [67] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139594$5684_Y + connect \Y $ternary$libresoc.v:139390$5684_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139595$5685 + cell $mux $ternary$libresoc.v:139391$5685 parameter \WIDTH 1 - connect \A \sdr_dq_2__core__oe + connect \A \sdr_dq_13__core__oe connect \B \io_bd [68] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139595$5685_Y + connect \Y $ternary$libresoc.v:139391$5685_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139596$5686 + cell $mux $ternary$libresoc.v:139392$5686 parameter \WIDTH 1 - connect \A \sdr_dq_3__pad__i + connect \A \sdr_dq_14__pad__i connect \B \io_bd [69] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139596$5686_Y + connect \Y $ternary$libresoc.v:139392$5686_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139597$5687 + cell $mux $ternary$libresoc.v:139393$5687 parameter \WIDTH 1 - connect \A \sdr_dq_3__core__o + connect \A \sdr_dq_14__core__o connect \B \io_bd [70] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139597$5687_Y + connect \Y $ternary$libresoc.v:139393$5687_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139598$5688 + cell $mux $ternary$libresoc.v:139394$5688 parameter \WIDTH 1 - connect \A \sdr_dq_3__core__oe + connect \A \sdr_dq_14__core__oe connect \B \io_bd [71] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139598$5688_Y + connect \Y $ternary$libresoc.v:139394$5688_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139599$5689 + cell $mux $ternary$libresoc.v:139395$5689 parameter \WIDTH 1 - connect \A \sdr_dq_4__pad__i + connect \A \sdr_dq_15__pad__i connect \B \io_bd [72] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139599$5689_Y + connect \Y $ternary$libresoc.v:139395$5689_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139600$5690 + cell $mux $ternary$libresoc.v:139396$5690 parameter \WIDTH 1 - connect \A \sdr_dq_4__core__o + connect \A \sdr_dq_15__core__o connect \B \io_bd [73] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139600$5690_Y + connect \Y $ternary$libresoc.v:139396$5690_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139603$5693 + cell $mux $ternary$libresoc.v:139399$5693 parameter \WIDTH 1 - connect \A \sdr_dq_4__core__oe + connect \A \sdr_dq_15__core__oe connect \B \io_bd [74] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139603$5693_Y + connect \Y $ternary$libresoc.v:139399$5693_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139604$5694 + cell $mux $ternary$libresoc.v:139400$5694 parameter \WIDTH 1 - connect \A \sdr_dq_5__pad__i + connect \A \gpio_e8__pad__i connect \B \io_bd [75] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139604$5694_Y + connect \Y $ternary$libresoc.v:139400$5694_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139605$5695 + cell $mux $ternary$libresoc.v:139401$5695 parameter \WIDTH 1 - connect \A \sdr_dq_5__core__o + connect \A \gpio_e8__core__o connect \B \io_bd [76] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139605$5695_Y + connect \Y $ternary$libresoc.v:139401$5695_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139606$5696 + cell $mux $ternary$libresoc.v:139402$5696 parameter \WIDTH 1 - connect \A \sdr_dq_5__core__oe + connect \A \gpio_e8__core__oe connect \B \io_bd [77] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139606$5696_Y + connect \Y $ternary$libresoc.v:139402$5696_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139607$5697 + cell $mux $ternary$libresoc.v:139403$5697 parameter \WIDTH 1 - connect \A \sdr_dq_6__pad__i + connect \A \gpio_e9__pad__i connect \B \io_bd [78] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139607$5697_Y + connect \Y $ternary$libresoc.v:139403$5697_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139608$5698 + cell $mux $ternary$libresoc.v:139404$5698 parameter \WIDTH 1 - connect \A \sdr_dq_6__core__o + connect \A \gpio_e9__core__o connect \B \io_bd [79] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139608$5698_Y + connect \Y $ternary$libresoc.v:139404$5698_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139609$5699 + cell $mux $ternary$libresoc.v:139405$5699 parameter \WIDTH 1 - connect \A \sdr_dq_6__core__oe + connect \A \gpio_e9__core__oe connect \B \io_bd [80] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139609$5699_Y + connect \Y $ternary$libresoc.v:139405$5699_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139610$5700 + cell $mux $ternary$libresoc.v:139406$5700 parameter \WIDTH 1 - connect \A \sdr_dq_7__pad__i + connect \A \gpio_e10__pad__i connect \B \io_bd [81] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139610$5700_Y + connect \Y $ternary$libresoc.v:139406$5700_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139611$5701 + cell $mux $ternary$libresoc.v:139407$5701 parameter \WIDTH 1 - connect \A \sdr_dq_7__core__o + connect \A \gpio_e10__core__o connect \B \io_bd [82] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139611$5701_Y + connect \Y $ternary$libresoc.v:139407$5701_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139612$5702 + cell $mux $ternary$libresoc.v:139408$5702 parameter \WIDTH 1 - connect \A \sdr_dq_7__core__oe + connect \A \gpio_e10__core__oe connect \B \io_bd [83] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139612$5702_Y + connect \Y $ternary$libresoc.v:139408$5702_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139614$5704 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139410$5704 parameter \WIDTH 1 - connect \A \sdr_a_0__core__o + connect \A \gpio_e11__pad__i connect \B \io_bd [84] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139614$5704_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139410$5704_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139615$5705 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139411$5705 parameter \WIDTH 1 - connect \A \sdr_a_1__core__o + connect \A \gpio_e11__core__o connect \B \io_bd [85] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139615$5705_Y + connect \Y $ternary$libresoc.v:139411$5705_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139616$5706 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139412$5706 parameter \WIDTH 1 - connect \A \sdr_a_2__core__o + connect \A \gpio_e11__core__oe connect \B \io_bd [86] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139616$5706_Y + connect \Y $ternary$libresoc.v:139412$5706_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139617$5707 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139413$5707 parameter \WIDTH 1 - connect \A \sdr_a_3__core__o + connect \A \gpio_e12__pad__i connect \B \io_bd [87] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139617$5707_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139413$5707_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139618$5708 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139414$5708 parameter \WIDTH 1 - connect \A \sdr_a_4__core__o + connect \A \gpio_e12__core__o connect \B \io_bd [88] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139618$5708_Y + connect \Y $ternary$libresoc.v:139414$5708_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139619$5709 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139415$5709 parameter \WIDTH 1 - connect \A \sdr_a_5__core__o + connect \A \gpio_e12__core__oe connect \B \io_bd [89] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139619$5709_Y + connect \Y $ternary$libresoc.v:139415$5709_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139620$5710 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139416$5710 parameter \WIDTH 1 - connect \A \sdr_a_6__core__o + connect \A \gpio_e13__pad__i connect \B \io_bd [90] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139620$5710_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139416$5710_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139621$5711 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139417$5711 parameter \WIDTH 1 - connect \A \sdr_a_7__core__o + connect \A \gpio_e13__core__o connect \B \io_bd [91] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139621$5711_Y + connect \Y $ternary$libresoc.v:139417$5711_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139622$5712 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139418$5712 parameter \WIDTH 1 - connect \A \sdr_a_8__core__o + connect \A \gpio_e13__core__oe connect \B \io_bd [92] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139622$5712_Y + connect \Y $ternary$libresoc.v:139418$5712_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139623$5713 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139419$5713 parameter \WIDTH 1 - connect \A \sdr_a_9__core__o + connect \A \gpio_e14__pad__i connect \B \io_bd [93] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139623$5713_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139419$5713_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139625$5715 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139421$5715 parameter \WIDTH 1 - connect \A \sdr_ba_0__core__o + connect \A \gpio_e14__core__o connect \B \io_bd [94] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139625$5715_Y + connect \Y $ternary$libresoc.v:139421$5715_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139626$5716 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139422$5716 parameter \WIDTH 1 - connect \A \sdr_ba_1__core__o + connect \A \gpio_e14__core__oe connect \B \io_bd [95] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139626$5716_Y + connect \Y $ternary$libresoc.v:139422$5716_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139627$5717 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139423$5717 parameter \WIDTH 1 - connect \A \sdr_clock__core__o + connect \A \gpio_e15__pad__i connect \B \io_bd [96] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139627$5717_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139423$5717_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139628$5718 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139424$5718 parameter \WIDTH 1 - connect \A \sdr_cke__core__o + connect \A \gpio_e15__core__o connect \B \io_bd [97] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139628$5718_Y + connect \Y $ternary$libresoc.v:139424$5718_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139629$5719 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139425$5719 parameter \WIDTH 1 - connect \A \sdr_ras_n__core__o + connect \A \gpio_e15__core__oe connect \B \io_bd [98] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139629$5719_Y + connect \Y $ternary$libresoc.v:139425$5719_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139630$5720 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139426$5720 parameter \WIDTH 1 - connect \A \sdr_cas_n__core__o + connect \A \gpio_s0__pad__i connect \B \io_bd [99] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139630$5720_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139426$5720_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139631$5721 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139427$5721 parameter \WIDTH 1 - connect \A \sdr_we_n__core__o + connect \A \gpio_s0__core__o connect \B \io_bd [100] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139631$5721_Y + connect \Y $ternary$libresoc.v:139427$5721_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139632$5722 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139428$5722 parameter \WIDTH 1 - connect \A \sdr_cs_n__core__o + connect \A \gpio_s0__core__oe connect \B \io_bd [101] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139632$5722_Y + connect \Y $ternary$libresoc.v:139428$5722_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139633$5723 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139429$5723 parameter \WIDTH 1 - connect \A \sdr_a_10__core__o + connect \A \gpio_s1__pad__i connect \B \io_bd [102] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139633$5723_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139429$5723_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139634$5724 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139430$5724 parameter \WIDTH 1 - connect \A \sdr_a_11__core__o + connect \A \gpio_s1__core__o connect \B \io_bd [103] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139634$5724_Y + connect \Y $ternary$libresoc.v:139430$5724_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139636$5726 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139432$5726 parameter \WIDTH 1 - connect \A \sdr_a_12__core__o + connect \A \gpio_s1__core__oe connect \B \io_bd [104] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139636$5726_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139637$5727 - parameter \WIDTH 1 - connect \A \sdr_dm_1__core__o - connect \B \io_bd [105] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139637$5727_Y + connect \Y $ternary$libresoc.v:139432$5726_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139638$5728 + cell $mux $ternary$libresoc.v:139433$5727 parameter \WIDTH 1 - connect \A \sdr_dq_8__pad__i - connect \B \io_bd [106] + connect \A \gpio_s2__pad__i + connect \B \io_bd [105] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139638$5728_Y + connect \Y $ternary$libresoc.v:139433$5727_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139639$5729 + cell $mux $ternary$libresoc.v:139434$5728 parameter \WIDTH 1 - connect \A \sdr_dq_8__core__o - connect \B \io_bd [107] + connect \A \gpio_s2__core__o + connect \B \io_bd [106] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139639$5729_Y + connect \Y $ternary$libresoc.v:139434$5728_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139640$5730 + cell $mux $ternary$libresoc.v:139435$5729 parameter \WIDTH 1 - connect \A \sdr_dq_8__core__oe - connect \B \io_bd [108] + connect \A \gpio_s2__core__oe + connect \B \io_bd [107] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139640$5730_Y + connect \Y $ternary$libresoc.v:139435$5729_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139641$5731 + cell $mux $ternary$libresoc.v:139436$5730 parameter \WIDTH 1 - connect \A \sdr_dq_9__pad__i - connect \B \io_bd [109] + connect \A \gpio_s3__pad__i + connect \B \io_bd [108] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139641$5731_Y + connect \Y $ternary$libresoc.v:139436$5730_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139642$5732 + cell $mux $ternary$libresoc.v:139437$5731 parameter \WIDTH 1 - connect \A \sdr_dq_9__core__o - connect \B \io_bd [110] + connect \A \gpio_s3__core__o + connect \B \io_bd [109] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139642$5732_Y + connect \Y $ternary$libresoc.v:139437$5731_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139643$5733 + cell $mux $ternary$libresoc.v:139438$5732 parameter \WIDTH 1 - connect \A \sdr_dq_9__core__oe - connect \B \io_bd [111] + connect \A \gpio_s3__core__oe + connect \B \io_bd [110] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139643$5733_Y + connect \Y $ternary$libresoc.v:139438$5732_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139644$5734 + cell $mux $ternary$libresoc.v:139439$5733 parameter \WIDTH 1 - connect \A \sdr_dq_10__pad__i - connect \B \io_bd [112] + connect \A \gpio_s4__pad__i + connect \B \io_bd [111] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139644$5734_Y + connect \Y $ternary$libresoc.v:139439$5733_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139645$5735 + cell $mux $ternary$libresoc.v:139440$5734 parameter \WIDTH 1 - connect \A \sdr_dq_10__core__o - connect \B \io_bd [113] + connect \A \gpio_s4__core__o + connect \B \io_bd [112] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139645$5735_Y + connect \Y $ternary$libresoc.v:139440$5734_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139647$5737 + cell $mux $ternary$libresoc.v:139441$5735 parameter \WIDTH 1 - connect \A \sdr_dq_10__core__oe - connect \B \io_bd [114] + connect \A \gpio_s4__core__oe + connect \B \io_bd [113] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139647$5737_Y + connect \Y $ternary$libresoc.v:139441$5735_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139648$5738 + cell $mux $ternary$libresoc.v:139443$5737 parameter \WIDTH 1 - connect \A \sdr_dq_11__pad__i - connect \B \io_bd [115] + connect \A \gpio_s5__pad__i + connect \B \io_bd [114] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139648$5738_Y + connect \Y $ternary$libresoc.v:139443$5737_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139649$5739 + cell $mux $ternary$libresoc.v:139444$5738 parameter \WIDTH 1 - connect \A \sdr_dq_11__core__o - connect \B \io_bd [116] + connect \A \gpio_s5__core__o + connect \B \io_bd [115] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139649$5739_Y + connect \Y $ternary$libresoc.v:139444$5738_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139650$5740 + cell $mux $ternary$libresoc.v:139445$5739 parameter \WIDTH 1 - connect \A \sdr_dq_11__core__oe - connect \B \io_bd [117] + connect \A \gpio_s5__core__oe + connect \B \io_bd [116] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139650$5740_Y + connect \Y $ternary$libresoc.v:139445$5739_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139651$5741 + cell $mux $ternary$libresoc.v:139446$5740 parameter \WIDTH 1 - connect \A \sdr_dq_12__pad__i - connect \B \io_bd [118] + connect \A \gpio_s6__pad__i + connect \B \io_bd [117] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139651$5741_Y + connect \Y $ternary$libresoc.v:139446$5740_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139652$5742 + cell $mux $ternary$libresoc.v:139447$5741 parameter \WIDTH 1 - connect \A \sdr_dq_12__core__o - connect \B \io_bd [119] + connect \A \gpio_s6__core__o + connect \B \io_bd [118] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139652$5742_Y + connect \Y $ternary$libresoc.v:139447$5741_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139653$5743 + cell $mux $ternary$libresoc.v:139448$5742 parameter \WIDTH 1 - connect \A \sdr_dq_12__core__oe - connect \B \io_bd [120] + connect \A \gpio_s6__core__oe + connect \B \io_bd [119] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139653$5743_Y + connect \Y $ternary$libresoc.v:139448$5742_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139654$5744 + cell $mux $ternary$libresoc.v:139449$5743 parameter \WIDTH 1 - connect \A \sdr_dq_13__pad__i - connect \B \io_bd [121] + connect \A \gpio_s7__pad__i + connect \B \io_bd [120] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139654$5744_Y + connect \Y $ternary$libresoc.v:139449$5743_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139655$5745 + cell $mux $ternary$libresoc.v:139450$5744 parameter \WIDTH 1 - connect \A \sdr_dq_13__core__o - connect \B \io_bd [122] + connect \A \gpio_s7__core__o + connect \B \io_bd [121] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139655$5745_Y + connect \Y $ternary$libresoc.v:139450$5744_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139656$5746 + cell $mux $ternary$libresoc.v:139451$5745 parameter \WIDTH 1 - connect \A \sdr_dq_13__core__oe - connect \B \io_bd [123] + connect \A \gpio_s7__core__oe + connect \B \io_bd [122] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139656$5746_Y + connect \Y $ternary$libresoc.v:139451$5745_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139658$5748 + cell $mux $ternary$libresoc.v:139452$5746 parameter \WIDTH 1 - connect \A \sdr_dq_14__pad__i - connect \B \io_bd [124] + connect \A \mtwi_sda__pad__i + connect \B \io_bd [123] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139658$5748_Y + connect \Y $ternary$libresoc.v:139452$5746_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139659$5749 + cell $mux $ternary$libresoc.v:139454$5748 parameter \WIDTH 1 - connect \A \sdr_dq_14__core__o - connect \B \io_bd [125] + connect \A \mtwi_sda__core__o + connect \B \io_bd [124] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139659$5749_Y + connect \Y $ternary$libresoc.v:139454$5748_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139660$5750 + cell $mux $ternary$libresoc.v:139455$5749 parameter \WIDTH 1 - connect \A \sdr_dq_14__core__oe + connect \A \mtwi_sda__core__oe + connect \B \io_bd [125] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139455$5749_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139456$5750 + parameter \WIDTH 1 + connect \A \mtwi_scl__core__o connect \B \io_bd [126] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139660$5750_Y + connect \Y $ternary$libresoc.v:139456$5750_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139661$5751 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:139457$5751 parameter \WIDTH 1 - connect \A \sdr_dq_15__pad__i + connect \A \eint_0__pad__i connect \B \io_bd [127] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139661$5751_Y + connect \Y $ternary$libresoc.v:139457$5751_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139662$5752 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:139458$5752 parameter \WIDTH 1 - connect \A \sdr_dq_15__core__o + connect \A \eint_1__pad__i connect \B \io_bd [128] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139662$5752_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139458$5752_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139663$5753 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:139459$5753 parameter \WIDTH 1 - connect \A \sdr_dq_15__core__oe + connect \A \eint_2__pad__i connect \B \io_bd [129] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139663$5753_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139459$5753_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139752$5843 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139548$5843 parameter \WIDTH 1 - connect \A \eint_0__pad__i + connect \A \mspi0_clk__core__o connect \B \io_bd [0] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139752$5843_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139548$5843_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139753$5844 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139549$5844 parameter \WIDTH 1 - connect \A \eint_1__pad__i + connect \A \mspi0_cs_n__core__o connect \B \io_bd [1] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139753$5844_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139549$5844_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139754$5845 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139550$5845 parameter \WIDTH 1 - connect \A \eint_2__pad__i + connect \A \mspi0_mosi__core__o connect \B \io_bd [2] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139754$5845_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139550$5845_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139755$5846 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:139551$5846 parameter \WIDTH 1 - connect \A \gpio_e8__pad__i + connect \A \mspi0_miso__pad__i connect \B \io_bd [3] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139755$5846_Y + connect \Y $ternary$libresoc.v:139551$5846_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139757$5848 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139553$5848 parameter \WIDTH 1 - connect \A \gpio_e8__core__o + connect \A \sdr_dm_0__core__o connect \B \io_bd [4] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139757$5848_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139758$5849 - parameter \WIDTH 1 - connect \A \gpio_e8__core__oe - connect \B \io_bd [5] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139758$5849_Y + connect \Y $ternary$libresoc.v:139553$5848_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139759$5850 + cell $mux $ternary$libresoc.v:139554$5849 parameter \WIDTH 1 - connect \A \gpio_e9__pad__i - connect \B \io_bd [6] + connect \A \sdr_dq_0__pad__i + connect \B \io_bd [5] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139759$5850_Y + connect \Y $ternary$libresoc.v:139554$5849_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139760$5851 + cell $mux $ternary$libresoc.v:139555$5850 parameter \WIDTH 1 - connect \A \gpio_e9__core__o - connect \B \io_bd [7] + connect \A \sdr_dq_0__core__o + connect \B \io_bd [6] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139760$5851_Y + connect \Y $ternary$libresoc.v:139555$5850_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139761$5852 + cell $mux $ternary$libresoc.v:139556$5851 parameter \WIDTH 1 - connect \A \gpio_e9__core__oe - connect \B \io_bd [8] + connect \A \sdr_dq_0__core__oe + connect \B \io_bd [7] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139761$5852_Y + connect \Y $ternary$libresoc.v:139556$5851_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139762$5853 + cell $mux $ternary$libresoc.v:139557$5852 parameter \WIDTH 1 - connect \A \gpio_e10__pad__i - connect \B \io_bd [9] + connect \A \sdr_dq_1__pad__i + connect \B \io_bd [8] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139762$5853_Y + connect \Y $ternary$libresoc.v:139557$5852_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139763$5854 + cell $mux $ternary$libresoc.v:139558$5853 parameter \WIDTH 1 - connect \A \gpio_e10__core__o - connect \B \io_bd [10] + connect \A \sdr_dq_1__core__o + connect \B \io_bd [9] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139763$5854_Y + connect \Y $ternary$libresoc.v:139558$5853_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139764$5855 + cell $mux $ternary$libresoc.v:139559$5854 parameter \WIDTH 1 - connect \A \gpio_e10__core__oe - connect \B \io_bd [11] + connect \A \sdr_dq_1__core__oe + connect \B \io_bd [10] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139764$5855_Y + connect \Y $ternary$libresoc.v:139559$5854_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139765$5856 + cell $mux $ternary$libresoc.v:139560$5855 parameter \WIDTH 1 - connect \A \gpio_e11__pad__i - connect \B \io_bd [12] + connect \A \sdr_dq_2__pad__i + connect \B \io_bd [11] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139765$5856_Y + connect \Y $ternary$libresoc.v:139560$5855_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139766$5857 + cell $mux $ternary$libresoc.v:139561$5856 parameter \WIDTH 1 - connect \A \gpio_e11__core__o - connect \B \io_bd [13] + connect \A \sdr_dq_2__core__o + connect \B \io_bd [12] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139766$5857_Y + connect \Y $ternary$libresoc.v:139561$5856_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139768$5859 + cell $mux $ternary$libresoc.v:139562$5857 parameter \WIDTH 1 - connect \A \gpio_e11__core__oe - connect \B \io_bd [14] + connect \A \sdr_dq_2__core__oe + connect \B \io_bd [13] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139768$5859_Y + connect \Y $ternary$libresoc.v:139562$5857_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139769$5860 + cell $mux $ternary$libresoc.v:139564$5859 parameter \WIDTH 1 - connect \A \gpio_e12__pad__i - connect \B \io_bd [15] + connect \A \sdr_dq_3__pad__i + connect \B \io_bd [14] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139769$5860_Y + connect \Y $ternary$libresoc.v:139564$5859_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139770$5861 + cell $mux $ternary$libresoc.v:139565$5860 parameter \WIDTH 1 - connect \A \gpio_e12__core__o - connect \B \io_bd [16] + connect \A \sdr_dq_3__core__o + connect \B \io_bd [15] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139770$5861_Y + connect \Y $ternary$libresoc.v:139565$5860_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139771$5862 + cell $mux $ternary$libresoc.v:139566$5861 parameter \WIDTH 1 - connect \A \gpio_e12__core__oe - connect \B \io_bd [17] + connect \A \sdr_dq_3__core__oe + connect \B \io_bd [16] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139771$5862_Y + connect \Y $ternary$libresoc.v:139566$5861_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139772$5863 + cell $mux $ternary$libresoc.v:139567$5862 parameter \WIDTH 1 - connect \A \gpio_e13__pad__i - connect \B \io_bd [18] + connect \A \sdr_dq_4__pad__i + connect \B \io_bd [17] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139772$5863_Y + connect \Y $ternary$libresoc.v:139567$5862_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139773$5864 + cell $mux $ternary$libresoc.v:139568$5863 parameter \WIDTH 1 - connect \A \gpio_e13__core__o - connect \B \io_bd [19] + connect \A \sdr_dq_4__core__o + connect \B \io_bd [18] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139773$5864_Y + connect \Y $ternary$libresoc.v:139568$5863_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139774$5865 + cell $mux $ternary$libresoc.v:139569$5864 parameter \WIDTH 1 - connect \A \gpio_e13__core__oe - connect \B \io_bd [20] + connect \A \sdr_dq_4__core__oe + connect \B \io_bd [19] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139774$5865_Y + connect \Y $ternary$libresoc.v:139569$5864_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139775$5866 + cell $mux $ternary$libresoc.v:139570$5865 parameter \WIDTH 1 - connect \A \gpio_e14__pad__i - connect \B \io_bd [21] + connect \A \sdr_dq_5__pad__i + connect \B \io_bd [20] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139775$5866_Y + connect \Y $ternary$libresoc.v:139570$5865_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139776$5867 + cell $mux $ternary$libresoc.v:139571$5866 parameter \WIDTH 1 - connect \A \gpio_e14__core__o - connect \B \io_bd [22] + connect \A \sdr_dq_5__core__o + connect \B \io_bd [21] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139776$5867_Y + connect \Y $ternary$libresoc.v:139571$5866_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139777$5868 + cell $mux $ternary$libresoc.v:139572$5867 parameter \WIDTH 1 - connect \A \gpio_e14__core__oe - connect \B \io_bd [23] + connect \A \sdr_dq_5__core__oe + connect \B \io_bd [22] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139777$5868_Y + connect \Y $ternary$libresoc.v:139572$5867_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139573$5868 + parameter \WIDTH 1 + connect \A \sdr_dq_6__pad__i + connect \B \io_bd [23] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139573$5868_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:139852.8-139864.4" + attribute \src "libresoc.v:139648.8-139660.4" cell \_fsm \_fsm connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tms \TAP_bus__tms @@ -221839,7 +221635,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:139865.12-139875.4" + attribute \src "libresoc.v:139661.12-139671.4" cell \_idblock \_idblock connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_id_tdo \_idblock_TAP_id_tdo @@ -221852,7 +221648,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:139876.12-139886.4" + attribute \src "libresoc.v:139672.12-139682.4" cell \_irblock \_irblock connect \TAP_bus__tdi \TAP_bus__tdi connect \capture \_fsm_capture @@ -221864,577 +221660,577 @@ module \jtag connect \tdo \_irblock_tdo connect \update \_fsm_update end - attribute \src "libresoc.v:138256.7-138256.20" - process $proc$libresoc.v:138256$6064 + attribute \src "libresoc.v:138052.7-138052.20" + process $proc$libresoc.v:138052$6064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:138766.13-138766.32" - process $proc$libresoc.v:138766$6065 + attribute \src "libresoc.v:138562.13-138562.32" + process $proc$libresoc.v:138562$6065 assign { } { } assign $1\dmi0__addr_i[3:0] 4'0000 sync always sync init update \dmi0__addr_i $1\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:138771.14-138771.46" - process $proc$libresoc.v:138771$6066 + attribute \src "libresoc.v:138567.14-138567.46" + process $proc$libresoc.v:138567$6066 assign { } { } assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0__din $1\dmi0__din[63:0] end - attribute \src "libresoc.v:138785.7-138785.29" - process $proc$libresoc.v:138785$6067 + attribute \src "libresoc.v:138581.7-138581.29" + process $proc$libresoc.v:138581$6067 assign { } { } assign $1\dmi0_addrsr__oe[0:0] 1'0 sync always sync init update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:138793.13-138793.36" - process $proc$libresoc.v:138793$6068 + attribute \src "libresoc.v:138589.13-138589.36" + process $proc$libresoc.v:138589$6068 assign { } { } assign $1\dmi0_addrsr_reg[7:0] 8'00000000 sync always sync init update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:138801.7-138801.37" - process $proc$libresoc.v:138801$6069 + attribute \src "libresoc.v:138597.7-138597.37" + process $proc$libresoc.v:138597$6069 assign { } { } assign $1\dmi0_addrsr_update_core[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:138805.7-138805.42" - process $proc$libresoc.v:138805$6070 + attribute \src "libresoc.v:138601.7-138601.42" + process $proc$libresoc.v:138601$6070 assign { } { } assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:138809.14-138809.51" - process $proc$libresoc.v:138809$6071 + attribute \src "libresoc.v:138605.14-138605.51" + process $proc$libresoc.v:138605$6071 assign { } { } assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:138815.13-138815.35" - process $proc$libresoc.v:138815$6072 + attribute \src "libresoc.v:138611.13-138611.35" + process $proc$libresoc.v:138611$6072 assign { } { } assign $1\dmi0_datasr__oe[1:0] 2'00 sync always sync init update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:138823.14-138823.52" - process $proc$libresoc.v:138823$6073 + attribute \src "libresoc.v:138619.14-138619.52" + process $proc$libresoc.v:138619$6073 assign { } { } assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:138831.7-138831.37" - process $proc$libresoc.v:138831$6074 + attribute \src "libresoc.v:138627.7-138627.37" + process $proc$libresoc.v:138627$6074 assign { } { } assign $1\dmi0_datasr_update_core[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:138835.7-138835.42" - process $proc$libresoc.v:138835$6075 + attribute \src "libresoc.v:138631.7-138631.42" + process $proc$libresoc.v:138631$6075 assign { } { } assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:138851.13-138851.29" - process $proc$libresoc.v:138851$6076 + attribute \src "libresoc.v:138647.13-138647.29" + process $proc$libresoc.v:138647$6076 assign { } { } assign $1\fsm_state[2:0] 3'000 sync always sync init update \fsm_state $1\fsm_state[2:0] end - attribute \src "libresoc.v:138853.13-138853.35" - process $proc$libresoc.v:138853$6077 + attribute \src "libresoc.v:138649.13-138649.35" + process $proc$libresoc.v:138649$6077 assign { } { } assign $0\fsm_state$455[2:0]$6078 3'000 sync always sync init update \fsm_state$455 $0\fsm_state$455[2:0]$6078 end - attribute \src "libresoc.v:139051.15-139051.61" - process $proc$libresoc.v:139051$6079 + attribute \src "libresoc.v:138847.15-138847.61" + process $proc$libresoc.v:138847$6079 assign { } { } assign $1\io_bd[129:0] 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \io_bd $1\io_bd[129:0] end - attribute \src "libresoc.v:139063.15-139063.61" - process $proc$libresoc.v:139063$6080 + attribute \src "libresoc.v:138859.15-138859.61" + process $proc$libresoc.v:138859$6080 assign { } { } assign $1\io_sr[129:0] 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \io_sr $1\io_sr[129:0] end - attribute \src "libresoc.v:139072.14-139072.41" - process $proc$libresoc.v:139072$6081 + attribute \src "libresoc.v:138868.14-138868.41" + process $proc$libresoc.v:138868$6081 assign { } { } assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb__adr $1\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:139081.14-139081.51" - process $proc$libresoc.v:139081$6082 + attribute \src "libresoc.v:138877.14-138877.51" + process $proc$libresoc.v:138877$6082 assign { } { } assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:139095.7-139095.32" - process $proc$libresoc.v:139095$6083 + attribute \src "libresoc.v:138891.7-138891.32" + process $proc$libresoc.v:138891$6083 assign { } { } assign $1\jtag_wb_addrsr__oe[0:0] 1'0 sync always sync init update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:139103.14-139103.47" - process $proc$libresoc.v:139103$6084 + attribute \src "libresoc.v:138899.14-138899.47" + process $proc$libresoc.v:138899$6084 assign { } { } assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:139111.7-139111.40" - process $proc$libresoc.v:139111$6085 + attribute \src "libresoc.v:138907.7-138907.40" + process $proc$libresoc.v:138907$6085 assign { } { } assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:139115.7-139115.45" - process $proc$libresoc.v:139115$6086 + attribute \src "libresoc.v:138911.7-138911.45" + process $proc$libresoc.v:138911$6086 assign { } { } assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:139119.14-139119.54" - process $proc$libresoc.v:139119$6087 + attribute \src "libresoc.v:138915.14-138915.54" + process $proc$libresoc.v:138915$6087 assign { } { } assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:139125.13-139125.38" - process $proc$libresoc.v:139125$6088 + attribute \src "libresoc.v:138921.13-138921.38" + process $proc$libresoc.v:138921$6088 assign { } { } assign $1\jtag_wb_datasr__oe[1:0] 2'00 sync always sync init update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:139133.14-139133.55" - process $proc$libresoc.v:139133$6089 + attribute \src "libresoc.v:138929.14-138929.55" + process $proc$libresoc.v:138929$6089 assign { } { } assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:139141.7-139141.40" - process $proc$libresoc.v:139141$6090 + attribute \src "libresoc.v:138937.7-138937.40" + process $proc$libresoc.v:138937$6090 assign { } { } assign $1\jtag_wb_datasr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:139145.7-139145.45" - process $proc$libresoc.v:139145$6091 + attribute \src "libresoc.v:138941.7-138941.45" + process $proc$libresoc.v:138941$6091 assign { } { } assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:139479.7-139479.21" - process $proc$libresoc.v:139479$6092 + attribute \src "libresoc.v:139275.7-139275.21" + process $proc$libresoc.v:139275$6092 assign { } { } assign $1\sr0__oe[0:0] 1'0 sync always sync init update \sr0__oe $1\sr0__oe[0:0] end - attribute \src "libresoc.v:139487.13-139487.27" - process $proc$libresoc.v:139487$6093 + attribute \src "libresoc.v:139283.13-139283.27" + process $proc$libresoc.v:139283$6093 assign { } { } assign $1\sr0_reg[2:0] 3'000 sync always sync init update \sr0_reg $1\sr0_reg[2:0] end - attribute \src "libresoc.v:139495.7-139495.29" - process $proc$libresoc.v:139495$6094 + attribute \src "libresoc.v:139291.7-139291.29" + process $proc$libresoc.v:139291$6094 assign { } { } assign $1\sr0_update_core[0:0] 1'0 sync always sync init update \sr0_update_core $1\sr0_update_core[0:0] end - attribute \src "libresoc.v:139499.7-139499.34" - process $proc$libresoc.v:139499$6095 + attribute \src "libresoc.v:139295.7-139295.34" + process $proc$libresoc.v:139295$6095 assign { } { } assign $1\sr0_update_core_prev[0:0] 1'0 sync always sync init update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:139509.7-139509.21" - process $proc$libresoc.v:139509$6096 + attribute \src "libresoc.v:139305.7-139305.21" + process $proc$libresoc.v:139305$6096 assign { } { } assign $1\sr5__oe[0:0] 1'0 sync always sync init update \sr5__oe $1\sr5__oe[0:0] end - attribute \src "libresoc.v:139517.13-139517.27" - process $proc$libresoc.v:139517$6097 + attribute \src "libresoc.v:139313.13-139313.27" + process $proc$libresoc.v:139313$6097 assign { } { } assign $1\sr5_reg[2:0] 3'000 sync always sync init update \sr5_reg $1\sr5_reg[2:0] end - attribute \src "libresoc.v:139525.7-139525.29" - process $proc$libresoc.v:139525$6098 + attribute \src "libresoc.v:139321.7-139321.29" + process $proc$libresoc.v:139321$6098 assign { } { } assign $1\sr5_update_core[0:0] 1'0 sync always sync init update \sr5_update_core $1\sr5_update_core[0:0] end - attribute \src "libresoc.v:139529.7-139529.34" - process $proc$libresoc.v:139529$6099 + attribute \src "libresoc.v:139325.7-139325.34" + process $proc$libresoc.v:139325$6099 assign { } { } assign $1\sr5_update_core_prev[0:0] 1'0 sync always sync init update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:139534.7-139534.26" - process $proc$libresoc.v:139534$6100 + attribute \src "libresoc.v:139330.7-139330.26" + process $proc$libresoc.v:139330$6100 assign { } { } assign $1\wb_dcache_en[0:0] 1'1 sync always sync init update \wb_dcache_en $1\wb_dcache_en[0:0] end - attribute \src "libresoc.v:139539.7-139539.26" - process $proc$libresoc.v:139539$6101 + attribute \src "libresoc.v:139335.7-139335.26" + process $proc$libresoc.v:139335$6101 assign { } { } assign $1\wb_icache_en[0:0] 1'1 sync always sync init update \wb_icache_en $1\wb_icache_en[0:0] end - attribute \src "libresoc.v:139543.7-139543.24" - process $proc$libresoc.v:139543$6102 + attribute \src "libresoc.v:139339.7-139339.24" + process $proc$libresoc.v:139339$6102 assign { } { } assign $1\wb_sram_en[0:0] 1'1 sync always sync init update \wb_sram_en $1\wb_sram_en[0:0] end - attribute \src "libresoc.v:139778.3-139779.41" - process $proc$libresoc.v:139778$5869 + attribute \src "libresoc.v:139574.3-139575.41" + process $proc$libresoc.v:139574$5869 assign { } { } assign $0\wb_icache_en[0:0] \wb_icache_en$next sync posedge \clk update \wb_icache_en $0\wb_icache_en[0:0] end - attribute \src "libresoc.v:139780.3-139781.41" - process $proc$libresoc.v:139780$5870 + attribute \src "libresoc.v:139576.3-139577.41" + process $proc$libresoc.v:139576$5870 assign { } { } assign $0\wb_dcache_en[0:0] \wb_dcache_en$next sync posedge \clk update \wb_dcache_en $0\wb_dcache_en[0:0] end - attribute \src "libresoc.v:139782.3-139783.37" - process $proc$libresoc.v:139782$5871 + attribute \src "libresoc.v:139578.3-139579.37" + process $proc$libresoc.v:139578$5871 assign { } { } assign $0\wb_sram_en[0:0] \wb_sram_en$next sync posedge \clk update \wb_sram_en $0\wb_sram_en[0:0] end - attribute \src "libresoc.v:139784.3-139785.45" - process $proc$libresoc.v:139784$5872 + attribute \src "libresoc.v:139580.3-139581.45" + process $proc$libresoc.v:139580$5872 assign { } { } assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next sync posedge \clk update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:139786.3-139787.35" - process $proc$libresoc.v:139786$5873 + attribute \src "libresoc.v:139582.3-139583.35" + process $proc$libresoc.v:139582$5873 assign { } { } assign $0\dmi0__din[63:0] \dmi0__din$next sync posedge \clk update \dmi0__din $0\dmi0__din[63:0] end - attribute \src "libresoc.v:139788.3-139789.45" - process $proc$libresoc.v:139788$5874 + attribute \src "libresoc.v:139584.3-139585.45" + process $proc$libresoc.v:139584$5874 assign { } { } assign $0\fsm_state$455[2:0]$5875 \fsm_state$455$next sync posedge \clk update \fsm_state$455 $0\fsm_state$455[2:0]$5875 end - attribute \src "libresoc.v:139790.3-139791.41" - process $proc$libresoc.v:139790$5876 + attribute \src "libresoc.v:139586.3-139587.41" + process $proc$libresoc.v:139586$5876 assign { } { } assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next sync posedge \clk update \dmi0__addr_i $0\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:139792.3-139793.51" - process $proc$libresoc.v:139792$5877 + attribute \src "libresoc.v:139588.3-139589.51" + process $proc$libresoc.v:139588$5877 assign { } { } assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next sync posedge \clk update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:139794.3-139795.45" - process $proc$libresoc.v:139794$5878 + attribute \src "libresoc.v:139590.3-139591.45" + process $proc$libresoc.v:139590$5878 assign { } { } assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next sync posedge \clk update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:139796.3-139797.35" - process $proc$libresoc.v:139796$5879 + attribute \src "libresoc.v:139592.3-139593.35" + process $proc$libresoc.v:139592$5879 assign { } { } assign $0\fsm_state[2:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[2:0] end - attribute \src "libresoc.v:139798.3-139799.41" - process $proc$libresoc.v:139798$5880 + attribute \src "libresoc.v:139594.3-139595.41" + process $proc$libresoc.v:139594$5880 assign { } { } assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next sync posedge \clk update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:139800.3-139801.31" - process $proc$libresoc.v:139800$5881 + attribute \src "libresoc.v:139596.3-139597.31" + process $proc$libresoc.v:139596$5881 assign { } { } assign $0\sr5_reg[2:0] \sr5_reg$next sync posedge \posjtag_clk update \sr5_reg $0\sr5_reg[2:0] end - attribute \src "libresoc.v:139802.3-139803.31" - process $proc$libresoc.v:139802$5882 + attribute \src "libresoc.v:139598.3-139599.31" + process $proc$libresoc.v:139598$5882 assign { } { } assign $0\sr5__oe[0:0] \sr5__oe$next sync posedge \clk update \sr5__oe $0\sr5__oe[0:0] end - attribute \src "libresoc.v:139804.3-139805.57" - process $proc$libresoc.v:139804$5883 + attribute \src "libresoc.v:139600.3-139601.57" + process $proc$libresoc.v:139600$5883 assign { } { } assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next sync posedge \clk update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:139806.3-139807.47" - process $proc$libresoc.v:139806$5884 + attribute \src "libresoc.v:139602.3-139603.47" + process $proc$libresoc.v:139602$5884 assign { } { } assign $0\sr5_update_core[0:0] \sr5_update_core$next sync posedge \clk update \sr5_update_core $0\sr5_update_core[0:0] end - attribute \src "libresoc.v:139808.3-139809.47" - process $proc$libresoc.v:139808$5885 + attribute \src "libresoc.v:139604.3-139605.47" + process $proc$libresoc.v:139604$5885 assign { } { } assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next sync posedge \posjtag_clk update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:139810.3-139811.47" - process $proc$libresoc.v:139810$5886 + attribute \src "libresoc.v:139606.3-139607.47" + process $proc$libresoc.v:139606$5886 assign { } { } assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next sync posedge \clk update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:139812.3-139813.73" - process $proc$libresoc.v:139812$5887 + attribute \src "libresoc.v:139608.3-139609.73" + process $proc$libresoc.v:139608$5887 assign { } { } assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next sync posedge \clk update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:139814.3-139815.63" - process $proc$libresoc.v:139814$5888 + attribute \src "libresoc.v:139610.3-139611.63" + process $proc$libresoc.v:139610$5888 assign { } { } assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next sync posedge \clk update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:139816.3-139817.47" - process $proc$libresoc.v:139816$5889 + attribute \src "libresoc.v:139612.3-139613.47" + process $proc$libresoc.v:139612$5889 assign { } { } assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next sync posedge \posjtag_clk update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:139818.3-139819.47" - process $proc$libresoc.v:139818$5890 + attribute \src "libresoc.v:139614.3-139615.47" + process $proc$libresoc.v:139614$5890 assign { } { } assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next sync posedge \clk update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:139820.3-139821.73" - process $proc$libresoc.v:139820$5891 + attribute \src "libresoc.v:139616.3-139617.73" + process $proc$libresoc.v:139616$5891 assign { } { } assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next sync posedge \clk update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:139822.3-139823.63" - process $proc$libresoc.v:139822$5892 + attribute \src "libresoc.v:139618.3-139619.63" + process $proc$libresoc.v:139618$5892 assign { } { } assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next sync posedge \clk update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:139824.3-139825.53" - process $proc$libresoc.v:139824$5893 + attribute \src "libresoc.v:139620.3-139621.53" + process $proc$libresoc.v:139620$5893 assign { } { } assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next sync posedge \posjtag_clk update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:139826.3-139827.53" - process $proc$libresoc.v:139826$5894 + attribute \src "libresoc.v:139622.3-139623.53" + process $proc$libresoc.v:139622$5894 assign { } { } assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next sync posedge \clk update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:139828.3-139829.79" - process $proc$libresoc.v:139828$5895 + attribute \src "libresoc.v:139624.3-139625.79" + process $proc$libresoc.v:139624$5895 assign { } { } assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next sync posedge \clk update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:139830.3-139831.69" - process $proc$libresoc.v:139830$5896 + attribute \src "libresoc.v:139626.3-139627.69" + process $proc$libresoc.v:139626$5896 assign { } { } assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next sync posedge \clk update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:139832.3-139833.53" - process $proc$libresoc.v:139832$5897 + attribute \src "libresoc.v:139628.3-139629.53" + process $proc$libresoc.v:139628$5897 assign { } { } assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next sync posedge \posjtag_clk update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:139834.3-139835.53" - process $proc$libresoc.v:139834$5898 + attribute \src "libresoc.v:139630.3-139631.53" + process $proc$libresoc.v:139630$5898 assign { } { } assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next sync posedge \clk update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:139836.3-139837.79" - process $proc$libresoc.v:139836$5899 + attribute \src "libresoc.v:139632.3-139633.79" + process $proc$libresoc.v:139632$5899 assign { } { } assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next sync posedge \clk update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:139838.3-139839.69" - process $proc$libresoc.v:139838$5900 + attribute \src "libresoc.v:139634.3-139635.69" + process $proc$libresoc.v:139634$5900 assign { } { } assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next sync posedge \clk update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:139840.3-139841.31" - process $proc$libresoc.v:139840$5901 + attribute \src "libresoc.v:139636.3-139637.31" + process $proc$libresoc.v:139636$5901 assign { } { } assign $0\sr0_reg[2:0] \sr0_reg$next sync posedge \posjtag_clk update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "libresoc.v:139842.3-139843.31" - process $proc$libresoc.v:139842$5902 + attribute \src "libresoc.v:139638.3-139639.31" + process $proc$libresoc.v:139638$5902 assign { } { } assign $0\sr0__oe[0:0] \sr0__oe$next sync posedge \clk update \sr0__oe $0\sr0__oe[0:0] end - attribute \src "libresoc.v:139844.3-139845.57" - process $proc$libresoc.v:139844$5903 + attribute \src "libresoc.v:139640.3-139641.57" + process $proc$libresoc.v:139640$5903 assign { } { } assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next sync posedge \clk update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:139846.3-139847.47" - process $proc$libresoc.v:139846$5904 + attribute \src "libresoc.v:139642.3-139643.47" + process $proc$libresoc.v:139642$5904 assign { } { } assign $0\sr0_update_core[0:0] \sr0_update_core$next sync posedge \clk update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "libresoc.v:139848.3-139849.27" - process $proc$libresoc.v:139848$5905 + attribute \src "libresoc.v:139644.3-139645.27" + process $proc$libresoc.v:139644$5905 assign { } { } assign $0\io_bd[129:0] \io_bd$next sync negedge \negjtag_clk update \io_bd $0\io_bd[129:0] end - attribute \src "libresoc.v:139850.3-139851.27" - process $proc$libresoc.v:139850$5906 + attribute \src "libresoc.v:139646.3-139647.27" + process $proc$libresoc.v:139646$5906 assign { } { } assign $0\io_sr[129:0] \io_sr$next sync posedge \posjtag_clk update \io_sr $0\io_sr[129:0] end - attribute \src "libresoc.v:139887.3-139902.6" - process $proc$libresoc.v:139887$5907 + attribute \src "libresoc.v:139683.3-139698.6" + process $proc$libresoc.v:139683$5907 assign { } { } assign { } { } assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:139888.5-139888.29" + attribute \src "libresoc.v:139684.5-139684.29" switch \initial - attribute \src "libresoc.v:139888.9-139888.17" + attribute \src "libresoc.v:139684.9-139684.17" case 1'1 case end @@ -222458,14 +222254,14 @@ module \jtag sync always update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "libresoc.v:139903.3-139911.6" - process $proc$libresoc.v:139903$5908 + attribute \src "libresoc.v:139699.3-139707.6" + process $proc$libresoc.v:139699$5908 assign { } { } assign { } { } assign $0\sr0_update_core$next[0:0]$5909 $1\sr0_update_core$next[0:0]$5910 - attribute \src "libresoc.v:139904.5-139904.29" + attribute \src "libresoc.v:139700.5-139700.29" switch \initial - attribute \src "libresoc.v:139904.9-139904.17" + attribute \src "libresoc.v:139700.9-139700.17" case 1'1 case end @@ -222481,14 +222277,14 @@ module \jtag sync always update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5909 end - attribute \src "libresoc.v:139912.3-139920.6" - process $proc$libresoc.v:139912$5911 + attribute \src "libresoc.v:139708.3-139716.6" + process $proc$libresoc.v:139708$5911 assign { } { } assign { } { } assign $0\sr0_update_core_prev$next[0:0]$5912 $1\sr0_update_core_prev$next[0:0]$5913 - attribute \src "libresoc.v:139913.5-139913.29" + attribute \src "libresoc.v:139709.5-139709.29" switch \initial - attribute \src "libresoc.v:139913.9-139913.17" + attribute \src "libresoc.v:139709.9-139709.17" case 1'1 case end @@ -222504,14 +222300,14 @@ module \jtag sync always update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5912 end - attribute \src "libresoc.v:139921.3-139937.6" - process $proc$libresoc.v:139921$5914 + attribute \src "libresoc.v:139717.3-139733.6" + process $proc$libresoc.v:139717$5914 assign { } { } assign { } { } assign $0\sr0__oe$next[0:0]$5915 $2\sr0__oe$next[0:0]$5917 - attribute \src "libresoc.v:139922.5-139922.29" + attribute \src "libresoc.v:139718.5-139718.29" switch \initial - attribute \src "libresoc.v:139922.9-139922.17" + attribute \src "libresoc.v:139718.9-139718.17" case 1'1 case end @@ -222538,16 +222334,16 @@ module \jtag sync always update \sr0__oe$next $0\sr0__oe$next[0:0]$5915 end - attribute \src "libresoc.v:139938.3-139958.6" - process $proc$libresoc.v:139938$5918 + attribute \src "libresoc.v:139734.3-139754.6" + process $proc$libresoc.v:139734$5918 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sr0_reg$next[2:0]$5919 $3\sr0_reg$next[2:0]$5922 - attribute \src "libresoc.v:139939.5-139939.29" + attribute \src "libresoc.v:139735.5-139735.29" switch \initial - attribute \src "libresoc.v:139939.9-139939.17" + attribute \src "libresoc.v:139735.9-139735.17" case 1'1 case end @@ -222581,14 +222377,14 @@ module \jtag sync always update \sr0_reg$next $0\sr0_reg$next[2:0]$5919 end - attribute \src "libresoc.v:139959.3-139967.6" - process $proc$libresoc.v:139959$5923 + attribute \src "libresoc.v:139755.3-139763.6" + process $proc$libresoc.v:139755$5923 assign { } { } assign { } { } assign $0\jtag_wb_addrsr_update_core$next[0:0]$5924 $1\jtag_wb_addrsr_update_core$next[0:0]$5925 - attribute \src "libresoc.v:139960.5-139960.29" + attribute \src "libresoc.v:139756.5-139756.29" switch \initial - attribute \src "libresoc.v:139960.9-139960.17" + attribute \src "libresoc.v:139756.9-139756.17" case 1'1 case end @@ -222604,14 +222400,14 @@ module \jtag sync always update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5924 end - attribute \src "libresoc.v:139968.3-139976.6" - process $proc$libresoc.v:139968$5926 + attribute \src "libresoc.v:139764.3-139772.6" + process $proc$libresoc.v:139764$5926 assign { } { } assign { } { } assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 - attribute \src "libresoc.v:139969.5-139969.29" + attribute \src "libresoc.v:139765.5-139765.29" switch \initial - attribute \src "libresoc.v:139969.9-139969.17" + attribute \src "libresoc.v:139765.9-139765.17" case 1'1 case end @@ -222627,14 +222423,14 @@ module \jtag sync always update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927 end - attribute \src "libresoc.v:139977.3-139993.6" - process $proc$libresoc.v:139977$5929 + attribute \src "libresoc.v:139773.3-139789.6" + process $proc$libresoc.v:139773$5929 assign { } { } assign { } { } assign $0\jtag_wb_addrsr__oe$next[0:0]$5930 $2\jtag_wb_addrsr__oe$next[0:0]$5932 - attribute \src "libresoc.v:139978.5-139978.29" + attribute \src "libresoc.v:139774.5-139774.29" switch \initial - attribute \src "libresoc.v:139978.9-139978.17" + attribute \src "libresoc.v:139774.9-139774.17" case 1'1 case end @@ -222661,16 +222457,16 @@ module \jtag sync always update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5930 end - attribute \src "libresoc.v:139994.3-140014.6" - process $proc$libresoc.v:139994$5933 + attribute \src "libresoc.v:139790.3-139810.6" + process $proc$libresoc.v:139790$5933 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\jtag_wb_addrsr_reg$next[28:0]$5934 $3\jtag_wb_addrsr_reg$next[28:0]$5937 - attribute \src "libresoc.v:139995.5-139995.29" + attribute \src "libresoc.v:139791.5-139791.29" switch \initial - attribute \src "libresoc.v:139995.9-139995.17" + attribute \src "libresoc.v:139791.9-139791.17" case 1'1 case end @@ -222704,14 +222500,14 @@ module \jtag sync always update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5934 end - attribute \src "libresoc.v:140015.3-140023.6" - process $proc$libresoc.v:140015$5938 + attribute \src "libresoc.v:139811.3-139819.6" + process $proc$libresoc.v:139811$5938 assign { } { } assign { } { } assign $0\jtag_wb_datasr_update_core$next[0:0]$5939 $1\jtag_wb_datasr_update_core$next[0:0]$5940 - attribute \src "libresoc.v:140016.5-140016.29" + attribute \src "libresoc.v:139812.5-139812.29" switch \initial - attribute \src "libresoc.v:140016.9-140016.17" + attribute \src "libresoc.v:139812.9-139812.17" case 1'1 case end @@ -222727,14 +222523,14 @@ module \jtag sync always update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5939 end - attribute \src "libresoc.v:140024.3-140032.6" - process $proc$libresoc.v:140024$5941 + attribute \src "libresoc.v:139820.3-139828.6" + process $proc$libresoc.v:139820$5941 assign { } { } assign { } { } assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 - attribute \src "libresoc.v:140025.5-140025.29" + attribute \src "libresoc.v:139821.5-139821.29" switch \initial - attribute \src "libresoc.v:140025.9-140025.17" + attribute \src "libresoc.v:139821.9-139821.17" case 1'1 case end @@ -222750,14 +222546,14 @@ module \jtag sync always update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942 end - attribute \src "libresoc.v:140033.3-140049.6" - process $proc$libresoc.v:140033$5944 + attribute \src "libresoc.v:139829.3-139845.6" + process $proc$libresoc.v:139829$5944 assign { } { } assign { } { } assign $0\jtag_wb_datasr__oe$next[1:0]$5945 $2\jtag_wb_datasr__oe$next[1:0]$5947 - attribute \src "libresoc.v:140034.5-140034.29" + attribute \src "libresoc.v:139830.5-139830.29" switch \initial - attribute \src "libresoc.v:140034.9-140034.17" + attribute \src "libresoc.v:139830.9-139830.17" case 1'1 case end @@ -222784,16 +222580,16 @@ module \jtag sync always update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5945 end - attribute \src "libresoc.v:140050.3-140070.6" - process $proc$libresoc.v:140050$5948 + attribute \src "libresoc.v:139846.3-139866.6" + process $proc$libresoc.v:139846$5948 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\jtag_wb_datasr_reg$next[63:0]$5949 $3\jtag_wb_datasr_reg$next[63:0]$5952 - attribute \src "libresoc.v:140051.5-140051.29" + attribute \src "libresoc.v:139847.5-139847.29" switch \initial - attribute \src "libresoc.v:140051.9-140051.17" + attribute \src "libresoc.v:139847.9-139847.17" case 1'1 case end @@ -222827,14 +222623,14 @@ module \jtag sync always update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5949 end - attribute \src "libresoc.v:140071.3-140079.6" - process $proc$libresoc.v:140071$5953 + attribute \src "libresoc.v:139867.3-139875.6" + process $proc$libresoc.v:139867$5953 assign { } { } assign { } { } assign $0\dmi0_addrsr_update_core$next[0:0]$5954 $1\dmi0_addrsr_update_core$next[0:0]$5955 - attribute \src "libresoc.v:140072.5-140072.29" + attribute \src "libresoc.v:139868.5-139868.29" switch \initial - attribute \src "libresoc.v:140072.9-140072.17" + attribute \src "libresoc.v:139868.9-139868.17" case 1'1 case end @@ -222850,14 +222646,14 @@ module \jtag sync always update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5954 end - attribute \src "libresoc.v:140080.3-140088.6" - process $proc$libresoc.v:140080$5956 + attribute \src "libresoc.v:139876.3-139884.6" + process $proc$libresoc.v:139876$5956 assign { } { } assign { } { } assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5957 $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 - attribute \src "libresoc.v:140081.5-140081.29" + attribute \src "libresoc.v:139877.5-139877.29" switch \initial - attribute \src "libresoc.v:140081.9-140081.17" + attribute \src "libresoc.v:139877.9-139877.17" case 1'1 case end @@ -222873,14 +222669,14 @@ module \jtag sync always update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5957 end - attribute \src "libresoc.v:140089.3-140105.6" - process $proc$libresoc.v:140089$5959 + attribute \src "libresoc.v:139885.3-139901.6" + process $proc$libresoc.v:139885$5959 assign { } { } assign { } { } assign $0\dmi0_addrsr__oe$next[0:0]$5960 $2\dmi0_addrsr__oe$next[0:0]$5962 - attribute \src "libresoc.v:140090.5-140090.29" + attribute \src "libresoc.v:139886.5-139886.29" switch \initial - attribute \src "libresoc.v:140090.9-140090.17" + attribute \src "libresoc.v:139886.9-139886.17" case 1'1 case end @@ -222907,16 +222703,16 @@ module \jtag sync always update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5960 end - attribute \src "libresoc.v:140106.3-140126.6" - process $proc$libresoc.v:140106$5963 + attribute \src "libresoc.v:139902.3-139922.6" + process $proc$libresoc.v:139902$5963 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\dmi0_addrsr_reg$next[7:0]$5964 $3\dmi0_addrsr_reg$next[7:0]$5967 - attribute \src "libresoc.v:140107.5-140107.29" + attribute \src "libresoc.v:139903.5-139903.29" switch \initial - attribute \src "libresoc.v:140107.9-140107.17" + attribute \src "libresoc.v:139903.9-139903.17" case 1'1 case end @@ -222950,14 +222746,14 @@ module \jtag sync always update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5964 end - attribute \src "libresoc.v:140127.3-140135.6" - process $proc$libresoc.v:140127$5968 + attribute \src "libresoc.v:139923.3-139931.6" + process $proc$libresoc.v:139923$5968 assign { } { } assign { } { } assign $0\dmi0_datasr_update_core$next[0:0]$5969 $1\dmi0_datasr_update_core$next[0:0]$5970 - attribute \src "libresoc.v:140128.5-140128.29" + attribute \src "libresoc.v:139924.5-139924.29" switch \initial - attribute \src "libresoc.v:140128.9-140128.17" + attribute \src "libresoc.v:139924.9-139924.17" case 1'1 case end @@ -222973,14 +222769,14 @@ module \jtag sync always update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5969 end - attribute \src "libresoc.v:140136.3-140144.6" - process $proc$libresoc.v:140136$5971 + attribute \src "libresoc.v:139932.3-139940.6" + process $proc$libresoc.v:139932$5971 assign { } { } assign { } { } assign $0\dmi0_datasr_update_core_prev$next[0:0]$5972 $1\dmi0_datasr_update_core_prev$next[0:0]$5973 - attribute \src "libresoc.v:140137.5-140137.29" + attribute \src "libresoc.v:139933.5-139933.29" switch \initial - attribute \src "libresoc.v:140137.9-140137.17" + attribute \src "libresoc.v:139933.9-139933.17" case 1'1 case end @@ -222996,14 +222792,14 @@ module \jtag sync always update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5972 end - attribute \src "libresoc.v:140145.3-140161.6" - process $proc$libresoc.v:140145$5974 + attribute \src "libresoc.v:139941.3-139957.6" + process $proc$libresoc.v:139941$5974 assign { } { } assign { } { } assign $0\dmi0_datasr__oe$next[1:0]$5975 $2\dmi0_datasr__oe$next[1:0]$5977 - attribute \src "libresoc.v:140146.5-140146.29" + attribute \src "libresoc.v:139942.5-139942.29" switch \initial - attribute \src "libresoc.v:140146.9-140146.17" + attribute \src "libresoc.v:139942.9-139942.17" case 1'1 case end @@ -223030,16 +222826,16 @@ module \jtag sync always update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5975 end - attribute \src "libresoc.v:140162.3-140182.6" - process $proc$libresoc.v:140162$5978 + attribute \src "libresoc.v:139958.3-139978.6" + process $proc$libresoc.v:139958$5978 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\dmi0_datasr_reg$next[63:0]$5979 $3\dmi0_datasr_reg$next[63:0]$5982 - attribute \src "libresoc.v:140163.5-140163.29" + attribute \src "libresoc.v:139959.5-139959.29" switch \initial - attribute \src "libresoc.v:140163.9-140163.17" + attribute \src "libresoc.v:139959.9-139959.17" case 1'1 case end @@ -223073,14 +222869,14 @@ module \jtag sync always update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5979 end - attribute \src "libresoc.v:140183.3-140191.6" - process $proc$libresoc.v:140183$5983 + attribute \src "libresoc.v:139979.3-139987.6" + process $proc$libresoc.v:139979$5983 assign { } { } assign { } { } assign $0\sr5_update_core$next[0:0]$5984 $1\sr5_update_core$next[0:0]$5985 - attribute \src "libresoc.v:140184.5-140184.29" + attribute \src "libresoc.v:139980.5-139980.29" switch \initial - attribute \src "libresoc.v:140184.9-140184.17" + attribute \src "libresoc.v:139980.9-139980.17" case 1'1 case end @@ -223096,14 +222892,14 @@ module \jtag sync always update \sr5_update_core$next $0\sr5_update_core$next[0:0]$5984 end - attribute \src "libresoc.v:140192.3-140200.6" - process $proc$libresoc.v:140192$5986 + attribute \src "libresoc.v:139988.3-139996.6" + process $proc$libresoc.v:139988$5986 assign { } { } assign { } { } assign $0\sr5_update_core_prev$next[0:0]$5987 $1\sr5_update_core_prev$next[0:0]$5988 - attribute \src "libresoc.v:140193.5-140193.29" + attribute \src "libresoc.v:139989.5-139989.29" switch \initial - attribute \src "libresoc.v:140193.9-140193.17" + attribute \src "libresoc.v:139989.9-139989.17" case 1'1 case end @@ -223119,14 +222915,14 @@ module \jtag sync always update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$5987 end - attribute \src "libresoc.v:140201.3-140217.6" - process $proc$libresoc.v:140201$5989 + attribute \src "libresoc.v:139997.3-140013.6" + process $proc$libresoc.v:139997$5989 assign { } { } assign { } { } assign $0\sr5__oe$next[0:0]$5990 $2\sr5__oe$next[0:0]$5992 - attribute \src "libresoc.v:140202.5-140202.29" + attribute \src "libresoc.v:139998.5-139998.29" switch \initial - attribute \src "libresoc.v:140202.9-140202.17" + attribute \src "libresoc.v:139998.9-139998.17" case 1'1 case end @@ -223153,16 +222949,16 @@ module \jtag sync always update \sr5__oe$next $0\sr5__oe$next[0:0]$5990 end - attribute \src "libresoc.v:140218.3-140238.6" - process $proc$libresoc.v:140218$5993 + attribute \src "libresoc.v:140014.3-140034.6" + process $proc$libresoc.v:140014$5993 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sr5_reg$next[2:0]$5994 $3\sr5_reg$next[2:0]$5997 - attribute \src "libresoc.v:140219.5-140219.29" + attribute \src "libresoc.v:140015.5-140015.29" switch \initial - attribute \src "libresoc.v:140219.9-140219.17" + attribute \src "libresoc.v:140015.9-140015.17" case 1'1 case end @@ -223196,13 +222992,13 @@ module \jtag sync always update \sr5_reg$next $0\sr5_reg$next[2:0]$5994 end - attribute \src "libresoc.v:140239.3-140265.6" - process $proc$libresoc.v:140239$5998 + attribute \src "libresoc.v:140035.3-140061.6" + process $proc$libresoc.v:140035$5998 assign { } { } assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:140240.5-140240.29" + attribute \src "libresoc.v:140036.5-140036.29" switch \initial - attribute \src "libresoc.v:140240.9-140240.17" + attribute \src "libresoc.v:140036.9-140036.17" case 1'1 case end @@ -223240,15 +223036,15 @@ module \jtag sync always update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] end - attribute \src "libresoc.v:140266.3-140310.6" - process $proc$libresoc.v:140266$5999 + attribute \src "libresoc.v:140062.3-140106.6" + process $proc$libresoc.v:140062$5999 assign { } { } assign { } { } assign { } { } assign $0\jtag_wb__adr$next[28:0]$6000 $4\jtag_wb__adr$next[28:0]$6004 - attribute \src "libresoc.v:140267.5-140267.29" + attribute \src "libresoc.v:140063.5-140063.29" switch \initial - attribute \src "libresoc.v:140267.9-140267.17" + attribute \src "libresoc.v:140063.9-140063.17" case 1'1 case end @@ -223308,15 +223104,15 @@ module \jtag sync always update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6000 end - attribute \src "libresoc.v:140311.3-140363.6" - process $proc$libresoc.v:140311$6005 + attribute \src "libresoc.v:140107.3-140159.6" + process $proc$libresoc.v:140107$6005 assign { } { } assign { } { } assign { } { } assign $0\fsm_state$next[2:0]$6006 $5\fsm_state$next[2:0]$6011 - attribute \src "libresoc.v:140312.5-140312.29" + attribute \src "libresoc.v:140108.5-140108.29" switch \initial - attribute \src "libresoc.v:140312.9-140312.17" + attribute \src "libresoc.v:140108.9-140108.17" case 1'1 case end @@ -223392,15 +223188,15 @@ module \jtag sync always update \fsm_state$next $0\fsm_state$next[2:0]$6006 end - attribute \src "libresoc.v:140364.3-140390.6" - process $proc$libresoc.v:140364$6012 + attribute \src "libresoc.v:140160.3-140186.6" + process $proc$libresoc.v:140160$6012 assign { } { } assign { } { } assign { } { } assign $0\jtag_wb__dat_w$next[63:0]$6013 $3\jtag_wb__dat_w$next[63:0]$6016 - attribute \src "libresoc.v:140365.5-140365.29" + attribute \src "libresoc.v:140161.5-140161.29" switch \initial - attribute \src "libresoc.v:140365.9-140365.17" + attribute \src "libresoc.v:140161.9-140161.17" case 1'1 case end @@ -223440,15 +223236,15 @@ module \jtag sync always update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6013 end - attribute \src "libresoc.v:140391.3-140419.6" - process $proc$libresoc.v:140391$6017 + attribute \src "libresoc.v:140187.3-140215.6" + process $proc$libresoc.v:140187$6017 assign { } { } assign { } { } assign { } { } assign $0\jtag_wb_datasr__i$next[63:0]$6018 $3\jtag_wb_datasr__i$next[63:0]$6021 - attribute \src "libresoc.v:140392.5-140392.29" + attribute \src "libresoc.v:140188.5-140188.29" switch \initial - attribute \src "libresoc.v:140392.9-140392.17" + attribute \src "libresoc.v:140188.9-140188.17" case 1'1 case end @@ -223488,15 +223284,15 @@ module \jtag sync always update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6018 end - attribute \src "libresoc.v:140420.3-140464.6" - process $proc$libresoc.v:140420$6022 + attribute \src "libresoc.v:140216.3-140260.6" + process $proc$libresoc.v:140216$6022 assign { } { } assign { } { } assign { } { } assign $0\dmi0__addr_i$next[3:0]$6023 $4\dmi0__addr_i$next[3:0]$6027 - attribute \src "libresoc.v:140421.5-140421.29" + attribute \src "libresoc.v:140217.5-140217.29" switch \initial - attribute \src "libresoc.v:140421.9-140421.17" + attribute \src "libresoc.v:140217.9-140217.17" case 1'1 case end @@ -223556,15 +223352,15 @@ module \jtag sync always update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6023 end - attribute \src "libresoc.v:140465.3-140517.6" - process $proc$libresoc.v:140465$6028 + attribute \src "libresoc.v:140261.3-140313.6" + process $proc$libresoc.v:140261$6028 assign { } { } assign { } { } assign { } { } assign $0\fsm_state$455$next[2:0]$6029 $5\fsm_state$455$next[2:0]$6034 - attribute \src "libresoc.v:140466.5-140466.29" + attribute \src "libresoc.v:140262.5-140262.29" switch \initial - attribute \src "libresoc.v:140466.9-140466.17" + attribute \src "libresoc.v:140262.9-140262.17" case 1'1 case end @@ -223640,15 +223436,15 @@ module \jtag sync always update \fsm_state$455$next $0\fsm_state$455$next[2:0]$6029 end - attribute \src "libresoc.v:140518.3-140544.6" - process $proc$libresoc.v:140518$6035 + attribute \src "libresoc.v:140314.3-140340.6" + process $proc$libresoc.v:140314$6035 assign { } { } assign { } { } assign { } { } assign $0\dmi0__din$next[63:0]$6036 $3\dmi0__din$next[63:0]$6039 - attribute \src "libresoc.v:140519.5-140519.29" + attribute \src "libresoc.v:140315.5-140315.29" switch \initial - attribute \src "libresoc.v:140519.9-140519.17" + attribute \src "libresoc.v:140315.9-140315.17" case 1'1 case end @@ -223688,15 +223484,15 @@ module \jtag sync always update \dmi0__din$next $0\dmi0__din$next[63:0]$6036 end - attribute \src "libresoc.v:140545.3-140573.6" - process $proc$libresoc.v:140545$6040 + attribute \src "libresoc.v:140341.3-140369.6" + process $proc$libresoc.v:140341$6040 assign { } { } assign { } { } assign { } { } assign $0\dmi0_datasr__i$next[63:0]$6041 $3\dmi0_datasr__i$next[63:0]$6044 - attribute \src "libresoc.v:140546.5-140546.29" + attribute \src "libresoc.v:140342.5-140342.29" switch \initial - attribute \src "libresoc.v:140546.9-140546.17" + attribute \src "libresoc.v:140342.9-140342.17" case 1'1 case end @@ -223736,8 +223532,8 @@ module \jtag sync always update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6041 end - attribute \src "libresoc.v:140574.3-140594.6" - process $proc$libresoc.v:140574$6045 + attribute \src "libresoc.v:140370.3-140390.6" + process $proc$libresoc.v:140370$6045 assign { } { } assign { } { } assign { } { } @@ -223750,9 +223546,9 @@ module \jtag assign $0\wb_dcache_en$next[0:0]$6046 $2\wb_dcache_en$next[0:0]$6052 assign $0\wb_icache_en$next[0:0]$6047 $2\wb_icache_en$next[0:0]$6053 assign $0\wb_sram_en$next[0:0]$6048 $2\wb_sram_en$next[0:0]$6054 - attribute \src "libresoc.v:140575.5-140575.29" + attribute \src "libresoc.v:140371.5-140371.29" switch \initial - attribute \src "libresoc.v:140575.9-140575.17" + attribute \src "libresoc.v:140371.9-140371.17" case 1'1 case end @@ -223789,14 +223585,14 @@ module \jtag update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6047 update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6048 end - attribute \src "libresoc.v:140595.3-140604.6" - process $proc$libresoc.v:140595$6055 + attribute \src "libresoc.v:140391.3-140400.6" + process $proc$libresoc.v:140391$6055 assign { } { } assign { } { } assign $0\sr5__i[2:0] $1\sr5__i[2:0] - attribute \src "libresoc.v:140596.5-140596.29" + attribute \src "libresoc.v:140392.5-140392.29" switch \initial - attribute \src "libresoc.v:140596.9-140596.17" + attribute \src "libresoc.v:140392.9-140392.17" case 1'1 case end @@ -223812,15 +223608,15 @@ module \jtag sync always update \sr5__i $0\sr5__i[2:0] end - attribute \src "libresoc.v:140605.3-140622.6" - process $proc$libresoc.v:140605$6056 + attribute \src "libresoc.v:140401.3-140418.6" + process $proc$libresoc.v:140401$6056 assign { } { } assign { } { } assign { } { } assign $0\io_sr$next[129:0]$6057 $2\io_sr$next[129:0]$6059 - attribute \src "libresoc.v:140606.5-140606.29" + attribute \src "libresoc.v:140402.5-140402.29" switch \initial - attribute \src "libresoc.v:140606.9-140606.17" + attribute \src "libresoc.v:140402.9-140402.17" case 1'1 case end @@ -223829,7 +223625,7 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $1\io_sr$next[129:0]$6058 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + assign $1\io_sr$next[129:0]$6058 { \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o } attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } @@ -223849,15 +223645,15 @@ module \jtag sync always update \io_sr$next $0\io_sr$next[129:0]$6057 end - attribute \src "libresoc.v:140623.3-140643.6" - process $proc$libresoc.v:140623$6060 + attribute \src "libresoc.v:140419.3-140439.6" + process $proc$libresoc.v:140419$6060 assign { } { } assign { } { } assign { } { } assign $0\io_bd$next[129:0]$6061 $2\io_bd$next[129:0]$6063 - attribute \src "libresoc.v:140624.5-140624.29" + attribute \src "libresoc.v:140420.5-140420.29" switch \initial - attribute \src "libresoc.v:140624.9-140624.17" + attribute \src "libresoc.v:140420.9-140420.17" case 1'1 case end @@ -223888,238 +223684,238 @@ module \jtag sync always update \io_bd$next $0\io_bd$next[129:0]$6061 end - connect \$9 $eq$libresoc.v:139546$5636_Y - connect \$99 $ternary$libresoc.v:139547$5637_Y - connect \$101 $ternary$libresoc.v:139548$5638_Y - connect \$103 $ternary$libresoc.v:139549$5639_Y - connect \$105 $ternary$libresoc.v:139550$5640_Y - connect \$107 $ternary$libresoc.v:139551$5641_Y - connect \$109 $ternary$libresoc.v:139552$5642_Y - connect \$111 $ternary$libresoc.v:139553$5643_Y - connect \$113 $ternary$libresoc.v:139554$5644_Y - connect \$115 $ternary$libresoc.v:139555$5645_Y - connect \$117 $ternary$libresoc.v:139556$5646_Y - connect \$11 $eq$libresoc.v:139557$5647_Y - connect \$119 $ternary$libresoc.v:139558$5648_Y - connect \$121 $ternary$libresoc.v:139559$5649_Y - connect \$123 $ternary$libresoc.v:139560$5650_Y - connect \$125 $ternary$libresoc.v:139561$5651_Y - connect \$127 $ternary$libresoc.v:139562$5652_Y - connect \$129 $ternary$libresoc.v:139563$5653_Y - connect \$131 $ternary$libresoc.v:139564$5654_Y - connect \$133 $ternary$libresoc.v:139565$5655_Y - connect \$135 $ternary$libresoc.v:139566$5656_Y - connect \$137 $ternary$libresoc.v:139567$5657_Y - connect \$13 $eq$libresoc.v:139568$5658_Y - connect \$139 $ternary$libresoc.v:139569$5659_Y - connect \$141 $ternary$libresoc.v:139570$5660_Y - connect \$143 $ternary$libresoc.v:139571$5661_Y - connect \$145 $ternary$libresoc.v:139572$5662_Y - connect \$147 $ternary$libresoc.v:139573$5663_Y - connect \$149 $ternary$libresoc.v:139574$5664_Y - connect \$151 $ternary$libresoc.v:139575$5665_Y - connect \$153 $ternary$libresoc.v:139576$5666_Y - connect \$155 $ternary$libresoc.v:139577$5667_Y - connect \$157 $ternary$libresoc.v:139578$5668_Y - connect \$15 $or$libresoc.v:139579$5669_Y - connect \$159 $ternary$libresoc.v:139580$5670_Y - connect \$161 $ternary$libresoc.v:139581$5671_Y - connect \$163 $ternary$libresoc.v:139582$5672_Y - connect \$165 $ternary$libresoc.v:139583$5673_Y - connect \$167 $ternary$libresoc.v:139584$5674_Y - connect \$169 $ternary$libresoc.v:139585$5675_Y - connect \$171 $ternary$libresoc.v:139586$5676_Y - connect \$173 $ternary$libresoc.v:139587$5677_Y - connect \$175 $ternary$libresoc.v:139588$5678_Y - connect \$177 $ternary$libresoc.v:139589$5679_Y - connect \$17 $and$libresoc.v:139590$5680_Y - connect \$179 $ternary$libresoc.v:139591$5681_Y - connect \$181 $ternary$libresoc.v:139592$5682_Y - connect \$183 $ternary$libresoc.v:139593$5683_Y - connect \$185 $ternary$libresoc.v:139594$5684_Y - connect \$187 $ternary$libresoc.v:139595$5685_Y - connect \$189 $ternary$libresoc.v:139596$5686_Y - connect \$191 $ternary$libresoc.v:139597$5687_Y - connect \$193 $ternary$libresoc.v:139598$5688_Y - connect \$195 $ternary$libresoc.v:139599$5689_Y - connect \$197 $ternary$libresoc.v:139600$5690_Y - connect \$1 $eq$libresoc.v:139601$5691_Y - connect \$19 $eq$libresoc.v:139602$5692_Y - connect \$199 $ternary$libresoc.v:139603$5693_Y - connect \$201 $ternary$libresoc.v:139604$5694_Y - connect \$203 $ternary$libresoc.v:139605$5695_Y - connect \$205 $ternary$libresoc.v:139606$5696_Y - connect \$207 $ternary$libresoc.v:139607$5697_Y - connect \$209 $ternary$libresoc.v:139608$5698_Y - connect \$211 $ternary$libresoc.v:139609$5699_Y - connect \$213 $ternary$libresoc.v:139610$5700_Y - connect \$215 $ternary$libresoc.v:139611$5701_Y - connect \$217 $ternary$libresoc.v:139612$5702_Y - connect \$21 $eq$libresoc.v:139613$5703_Y - connect \$219 $ternary$libresoc.v:139614$5704_Y - connect \$221 $ternary$libresoc.v:139615$5705_Y - connect \$223 $ternary$libresoc.v:139616$5706_Y - connect \$225 $ternary$libresoc.v:139617$5707_Y - connect \$227 $ternary$libresoc.v:139618$5708_Y - connect \$229 $ternary$libresoc.v:139619$5709_Y - connect \$231 $ternary$libresoc.v:139620$5710_Y - connect \$233 $ternary$libresoc.v:139621$5711_Y - connect \$235 $ternary$libresoc.v:139622$5712_Y - connect \$237 $ternary$libresoc.v:139623$5713_Y - connect \$23 $or$libresoc.v:139624$5714_Y - connect \$239 $ternary$libresoc.v:139625$5715_Y - connect \$241 $ternary$libresoc.v:139626$5716_Y - connect \$243 $ternary$libresoc.v:139627$5717_Y - connect \$245 $ternary$libresoc.v:139628$5718_Y - connect \$247 $ternary$libresoc.v:139629$5719_Y - connect \$249 $ternary$libresoc.v:139630$5720_Y - connect \$251 $ternary$libresoc.v:139631$5721_Y - connect \$253 $ternary$libresoc.v:139632$5722_Y - connect \$255 $ternary$libresoc.v:139633$5723_Y - connect \$257 $ternary$libresoc.v:139634$5724_Y - connect \$25 $eq$libresoc.v:139635$5725_Y - connect \$259 $ternary$libresoc.v:139636$5726_Y - connect \$261 $ternary$libresoc.v:139637$5727_Y - connect \$263 $ternary$libresoc.v:139638$5728_Y - connect \$265 $ternary$libresoc.v:139639$5729_Y - connect \$267 $ternary$libresoc.v:139640$5730_Y - connect \$269 $ternary$libresoc.v:139641$5731_Y - connect \$271 $ternary$libresoc.v:139642$5732_Y - connect \$273 $ternary$libresoc.v:139643$5733_Y - connect \$275 $ternary$libresoc.v:139644$5734_Y - connect \$277 $ternary$libresoc.v:139645$5735_Y - connect \$27 $or$libresoc.v:139646$5736_Y - connect \$279 $ternary$libresoc.v:139647$5737_Y - connect \$281 $ternary$libresoc.v:139648$5738_Y - connect \$283 $ternary$libresoc.v:139649$5739_Y - connect \$285 $ternary$libresoc.v:139650$5740_Y - connect \$287 $ternary$libresoc.v:139651$5741_Y - connect \$289 $ternary$libresoc.v:139652$5742_Y - connect \$291 $ternary$libresoc.v:139653$5743_Y - connect \$293 $ternary$libresoc.v:139654$5744_Y - connect \$295 $ternary$libresoc.v:139655$5745_Y - connect \$297 $ternary$libresoc.v:139656$5746_Y - connect \$29 $and$libresoc.v:139657$5747_Y - connect \$299 $ternary$libresoc.v:139658$5748_Y - connect \$301 $ternary$libresoc.v:139659$5749_Y - connect \$303 $ternary$libresoc.v:139660$5750_Y - connect \$305 $ternary$libresoc.v:139661$5751_Y - connect \$307 $ternary$libresoc.v:139662$5752_Y - connect \$309 $ternary$libresoc.v:139663$5753_Y - connect \$311 $eq$libresoc.v:139664$5754_Y - connect \$313 $eq$libresoc.v:139665$5755_Y - connect \$315 $or$libresoc.v:139666$5756_Y - connect \$317 $eq$libresoc.v:139667$5757_Y - connect \$31 $and$libresoc.v:139668$5758_Y - connect \$319 $or$libresoc.v:139669$5759_Y - connect \$321 $and$libresoc.v:139670$5760_Y - connect \$323 $eq$libresoc.v:139671$5761_Y - connect \$325 $ne$libresoc.v:139672$5762_Y - connect \$327 $and$libresoc.v:139673$5763_Y - connect \$329 $ne$libresoc.v:139674$5764_Y - connect \$331 $and$libresoc.v:139675$5765_Y - connect \$333 $ne$libresoc.v:139676$5766_Y - connect \$335 $and$libresoc.v:139677$5767_Y - connect \$337 $not$libresoc.v:139678$5768_Y - connect \$33 $eq$libresoc.v:139679$5769_Y - connect \$339 $and$libresoc.v:139680$5770_Y - connect \$341 $eq$libresoc.v:139681$5771_Y - connect \$343 $ne$libresoc.v:139682$5772_Y - connect \$345 $and$libresoc.v:139683$5773_Y - connect \$347 $ne$libresoc.v:139684$5774_Y - connect \$349 $and$libresoc.v:139685$5775_Y - connect \$351 $ne$libresoc.v:139686$5776_Y - connect \$353 $and$libresoc.v:139687$5777_Y - connect \$355 $not$libresoc.v:139688$5778_Y - connect \$357 $and$libresoc.v:139689$5779_Y - connect \$35 $eq$libresoc.v:139690$5780_Y - connect \$359 $eq$libresoc.v:139691$5781_Y - connect \$361 $eq$libresoc.v:139692$5782_Y - connect \$363 $ne$libresoc.v:139693$5783_Y - connect \$365 $and$libresoc.v:139694$5784_Y - connect \$367 $ne$libresoc.v:139695$5785_Y - connect \$369 $and$libresoc.v:139696$5786_Y - connect \$371 $ne$libresoc.v:139697$5787_Y - connect \$373 $and$libresoc.v:139698$5788_Y - connect \$375 $not$libresoc.v:139699$5789_Y - connect \$377 $and$libresoc.v:139700$5790_Y - connect \$37 $or$libresoc.v:139701$5791_Y - connect \$379 $eq$libresoc.v:139702$5792_Y - connect \$381 $ne$libresoc.v:139703$5793_Y - connect \$383 $and$libresoc.v:139704$5794_Y - connect \$385 $ne$libresoc.v:139705$5795_Y - connect \$387 $and$libresoc.v:139706$5796_Y - connect \$389 $ne$libresoc.v:139707$5797_Y - connect \$391 $and$libresoc.v:139708$5798_Y - connect \$393 $not$libresoc.v:139709$5799_Y - connect \$395 $and$libresoc.v:139710$5800_Y - connect \$397 $eq$libresoc.v:139711$5801_Y - connect \$3 $eq$libresoc.v:139712$5802_Y - connect \$39 $eq$libresoc.v:139713$5803_Y - connect \$399 $eq$libresoc.v:139714$5804_Y - connect \$401 $ne$libresoc.v:139715$5805_Y - connect \$403 $and$libresoc.v:139716$5806_Y - connect \$405 $ne$libresoc.v:139717$5807_Y - connect \$407 $and$libresoc.v:139718$5808_Y - connect \$409 $ne$libresoc.v:139719$5809_Y - connect \$411 $and$libresoc.v:139720$5810_Y - connect \$413 $not$libresoc.v:139721$5811_Y - connect \$415 $and$libresoc.v:139722$5812_Y - connect \$417 $eq$libresoc.v:139723$5813_Y - connect \$41 $or$libresoc.v:139724$5814_Y - connect \$419 $ne$libresoc.v:139725$5815_Y - connect \$421 $and$libresoc.v:139726$5816_Y - connect \$423 $ne$libresoc.v:139727$5817_Y - connect \$425 $and$libresoc.v:139728$5818_Y - connect \$427 $ne$libresoc.v:139729$5819_Y - connect \$429 $and$libresoc.v:139730$5820_Y - connect \$431 $not$libresoc.v:139731$5821_Y - connect \$433 $and$libresoc.v:139732$5822_Y - connect \$436 $eq$libresoc.v:139733$5823_Y - connect \$435 $not$libresoc.v:139734$5824_Y - connect \$43 $and$libresoc.v:139735$5825_Y - connect \$439 $eq$libresoc.v:139736$5826_Y - connect \$441 $eq$libresoc.v:139737$5827_Y - connect \$443 $or$libresoc.v:139738$5828_Y - connect \$445 $eq$libresoc.v:139739$5829_Y - connect \$448 $add$libresoc.v:139740$5830_Y - connect \$451 $add$libresoc.v:139741$5831_Y - connect \$453 $pos$libresoc.v:139742$5833_Y - connect \$456 $eq$libresoc.v:139743$5834_Y - connect \$458 $eq$libresoc.v:139744$5835_Y - connect \$45 $and$libresoc.v:139745$5836_Y - connect \$460 $or$libresoc.v:139746$5837_Y - connect \$462 $eq$libresoc.v:139747$5838_Y - connect \$465 $add$libresoc.v:139748$5839_Y - connect \$468 $add$libresoc.v:139749$5840_Y - connect \$47 $eq$libresoc.v:139750$5841_Y - connect \$49 $eq$libresoc.v:139751$5842_Y - connect \$51 $ternary$libresoc.v:139752$5843_Y - connect \$53 $ternary$libresoc.v:139753$5844_Y - connect \$55 $ternary$libresoc.v:139754$5845_Y - connect \$57 $ternary$libresoc.v:139755$5846_Y - connect \$5 $or$libresoc.v:139756$5847_Y - connect \$59 $ternary$libresoc.v:139757$5848_Y - connect \$61 $ternary$libresoc.v:139758$5849_Y - connect \$63 $ternary$libresoc.v:139759$5850_Y - connect \$65 $ternary$libresoc.v:139760$5851_Y - connect \$67 $ternary$libresoc.v:139761$5852_Y - connect \$69 $ternary$libresoc.v:139762$5853_Y - connect \$71 $ternary$libresoc.v:139763$5854_Y - connect \$73 $ternary$libresoc.v:139764$5855_Y - connect \$75 $ternary$libresoc.v:139765$5856_Y - connect \$77 $ternary$libresoc.v:139766$5857_Y - connect \$7 $and$libresoc.v:139767$5858_Y - connect \$79 $ternary$libresoc.v:139768$5859_Y - connect \$81 $ternary$libresoc.v:139769$5860_Y - connect \$83 $ternary$libresoc.v:139770$5861_Y - connect \$85 $ternary$libresoc.v:139771$5862_Y - connect \$87 $ternary$libresoc.v:139772$5863_Y - connect \$89 $ternary$libresoc.v:139773$5864_Y - connect \$91 $ternary$libresoc.v:139774$5865_Y - connect \$93 $ternary$libresoc.v:139775$5866_Y - connect \$95 $ternary$libresoc.v:139776$5867_Y - connect \$97 $ternary$libresoc.v:139777$5868_Y + connect \$9 $eq$libresoc.v:139342$5636_Y + connect \$99 $ternary$libresoc.v:139343$5637_Y + connect \$101 $ternary$libresoc.v:139344$5638_Y + connect \$103 $ternary$libresoc.v:139345$5639_Y + connect \$105 $ternary$libresoc.v:139346$5640_Y + connect \$107 $ternary$libresoc.v:139347$5641_Y + connect \$109 $ternary$libresoc.v:139348$5642_Y + connect \$111 $ternary$libresoc.v:139349$5643_Y + connect \$113 $ternary$libresoc.v:139350$5644_Y + connect \$115 $ternary$libresoc.v:139351$5645_Y + connect \$117 $ternary$libresoc.v:139352$5646_Y + connect \$11 $eq$libresoc.v:139353$5647_Y + connect \$119 $ternary$libresoc.v:139354$5648_Y + connect \$121 $ternary$libresoc.v:139355$5649_Y + connect \$123 $ternary$libresoc.v:139356$5650_Y + connect \$125 $ternary$libresoc.v:139357$5651_Y + connect \$127 $ternary$libresoc.v:139358$5652_Y + connect \$129 $ternary$libresoc.v:139359$5653_Y + connect \$131 $ternary$libresoc.v:139360$5654_Y + connect \$133 $ternary$libresoc.v:139361$5655_Y + connect \$135 $ternary$libresoc.v:139362$5656_Y + connect \$137 $ternary$libresoc.v:139363$5657_Y + connect \$13 $eq$libresoc.v:139364$5658_Y + connect \$139 $ternary$libresoc.v:139365$5659_Y + connect \$141 $ternary$libresoc.v:139366$5660_Y + connect \$143 $ternary$libresoc.v:139367$5661_Y + connect \$145 $ternary$libresoc.v:139368$5662_Y + connect \$147 $ternary$libresoc.v:139369$5663_Y + connect \$149 $ternary$libresoc.v:139370$5664_Y + connect \$151 $ternary$libresoc.v:139371$5665_Y + connect \$153 $ternary$libresoc.v:139372$5666_Y + connect \$155 $ternary$libresoc.v:139373$5667_Y + connect \$157 $ternary$libresoc.v:139374$5668_Y + connect \$15 $or$libresoc.v:139375$5669_Y + connect \$159 $ternary$libresoc.v:139376$5670_Y + connect \$161 $ternary$libresoc.v:139377$5671_Y + connect \$163 $ternary$libresoc.v:139378$5672_Y + connect \$165 $ternary$libresoc.v:139379$5673_Y + connect \$167 $ternary$libresoc.v:139380$5674_Y + connect \$169 $ternary$libresoc.v:139381$5675_Y + connect \$171 $ternary$libresoc.v:139382$5676_Y + connect \$173 $ternary$libresoc.v:139383$5677_Y + connect \$175 $ternary$libresoc.v:139384$5678_Y + connect \$177 $ternary$libresoc.v:139385$5679_Y + connect \$17 $and$libresoc.v:139386$5680_Y + connect \$179 $ternary$libresoc.v:139387$5681_Y + connect \$181 $ternary$libresoc.v:139388$5682_Y + connect \$183 $ternary$libresoc.v:139389$5683_Y + connect \$185 $ternary$libresoc.v:139390$5684_Y + connect \$187 $ternary$libresoc.v:139391$5685_Y + connect \$189 $ternary$libresoc.v:139392$5686_Y + connect \$191 $ternary$libresoc.v:139393$5687_Y + connect \$193 $ternary$libresoc.v:139394$5688_Y + connect \$195 $ternary$libresoc.v:139395$5689_Y + connect \$197 $ternary$libresoc.v:139396$5690_Y + connect \$1 $eq$libresoc.v:139397$5691_Y + connect \$19 $eq$libresoc.v:139398$5692_Y + connect \$199 $ternary$libresoc.v:139399$5693_Y + connect \$201 $ternary$libresoc.v:139400$5694_Y + connect \$203 $ternary$libresoc.v:139401$5695_Y + connect \$205 $ternary$libresoc.v:139402$5696_Y + connect \$207 $ternary$libresoc.v:139403$5697_Y + connect \$209 $ternary$libresoc.v:139404$5698_Y + connect \$211 $ternary$libresoc.v:139405$5699_Y + connect \$213 $ternary$libresoc.v:139406$5700_Y + connect \$215 $ternary$libresoc.v:139407$5701_Y + connect \$217 $ternary$libresoc.v:139408$5702_Y + connect \$21 $eq$libresoc.v:139409$5703_Y + connect \$219 $ternary$libresoc.v:139410$5704_Y + connect \$221 $ternary$libresoc.v:139411$5705_Y + connect \$223 $ternary$libresoc.v:139412$5706_Y + connect \$225 $ternary$libresoc.v:139413$5707_Y + connect \$227 $ternary$libresoc.v:139414$5708_Y + connect \$229 $ternary$libresoc.v:139415$5709_Y + connect \$231 $ternary$libresoc.v:139416$5710_Y + connect \$233 $ternary$libresoc.v:139417$5711_Y + connect \$235 $ternary$libresoc.v:139418$5712_Y + connect \$237 $ternary$libresoc.v:139419$5713_Y + connect \$23 $or$libresoc.v:139420$5714_Y + connect \$239 $ternary$libresoc.v:139421$5715_Y + connect \$241 $ternary$libresoc.v:139422$5716_Y + connect \$243 $ternary$libresoc.v:139423$5717_Y + connect \$245 $ternary$libresoc.v:139424$5718_Y + connect \$247 $ternary$libresoc.v:139425$5719_Y + connect \$249 $ternary$libresoc.v:139426$5720_Y + connect \$251 $ternary$libresoc.v:139427$5721_Y + connect \$253 $ternary$libresoc.v:139428$5722_Y + connect \$255 $ternary$libresoc.v:139429$5723_Y + connect \$257 $ternary$libresoc.v:139430$5724_Y + connect \$25 $eq$libresoc.v:139431$5725_Y + connect \$259 $ternary$libresoc.v:139432$5726_Y + connect \$261 $ternary$libresoc.v:139433$5727_Y + connect \$263 $ternary$libresoc.v:139434$5728_Y + connect \$265 $ternary$libresoc.v:139435$5729_Y + connect \$267 $ternary$libresoc.v:139436$5730_Y + connect \$269 $ternary$libresoc.v:139437$5731_Y + connect \$271 $ternary$libresoc.v:139438$5732_Y + connect \$273 $ternary$libresoc.v:139439$5733_Y + connect \$275 $ternary$libresoc.v:139440$5734_Y + connect \$277 $ternary$libresoc.v:139441$5735_Y + connect \$27 $or$libresoc.v:139442$5736_Y + connect \$279 $ternary$libresoc.v:139443$5737_Y + connect \$281 $ternary$libresoc.v:139444$5738_Y + connect \$283 $ternary$libresoc.v:139445$5739_Y + connect \$285 $ternary$libresoc.v:139446$5740_Y + connect \$287 $ternary$libresoc.v:139447$5741_Y + connect \$289 $ternary$libresoc.v:139448$5742_Y + connect \$291 $ternary$libresoc.v:139449$5743_Y + connect \$293 $ternary$libresoc.v:139450$5744_Y + connect \$295 $ternary$libresoc.v:139451$5745_Y + connect \$297 $ternary$libresoc.v:139452$5746_Y + connect \$29 $and$libresoc.v:139453$5747_Y + connect \$299 $ternary$libresoc.v:139454$5748_Y + connect \$301 $ternary$libresoc.v:139455$5749_Y + connect \$303 $ternary$libresoc.v:139456$5750_Y + connect \$305 $ternary$libresoc.v:139457$5751_Y + connect \$307 $ternary$libresoc.v:139458$5752_Y + connect \$309 $ternary$libresoc.v:139459$5753_Y + connect \$311 $eq$libresoc.v:139460$5754_Y + connect \$313 $eq$libresoc.v:139461$5755_Y + connect \$315 $or$libresoc.v:139462$5756_Y + connect \$317 $eq$libresoc.v:139463$5757_Y + connect \$31 $and$libresoc.v:139464$5758_Y + connect \$319 $or$libresoc.v:139465$5759_Y + connect \$321 $and$libresoc.v:139466$5760_Y + connect \$323 $eq$libresoc.v:139467$5761_Y + connect \$325 $ne$libresoc.v:139468$5762_Y + connect \$327 $and$libresoc.v:139469$5763_Y + connect \$329 $ne$libresoc.v:139470$5764_Y + connect \$331 $and$libresoc.v:139471$5765_Y + connect \$333 $ne$libresoc.v:139472$5766_Y + connect \$335 $and$libresoc.v:139473$5767_Y + connect \$337 $not$libresoc.v:139474$5768_Y + connect \$33 $eq$libresoc.v:139475$5769_Y + connect \$339 $and$libresoc.v:139476$5770_Y + connect \$341 $eq$libresoc.v:139477$5771_Y + connect \$343 $ne$libresoc.v:139478$5772_Y + connect \$345 $and$libresoc.v:139479$5773_Y + connect \$347 $ne$libresoc.v:139480$5774_Y + connect \$349 $and$libresoc.v:139481$5775_Y + connect \$351 $ne$libresoc.v:139482$5776_Y + connect \$353 $and$libresoc.v:139483$5777_Y + connect \$355 $not$libresoc.v:139484$5778_Y + connect \$357 $and$libresoc.v:139485$5779_Y + connect \$35 $eq$libresoc.v:139486$5780_Y + connect \$359 $eq$libresoc.v:139487$5781_Y + connect \$361 $eq$libresoc.v:139488$5782_Y + connect \$363 $ne$libresoc.v:139489$5783_Y + connect \$365 $and$libresoc.v:139490$5784_Y + connect \$367 $ne$libresoc.v:139491$5785_Y + connect \$369 $and$libresoc.v:139492$5786_Y + connect \$371 $ne$libresoc.v:139493$5787_Y + connect \$373 $and$libresoc.v:139494$5788_Y + connect \$375 $not$libresoc.v:139495$5789_Y + connect \$377 $and$libresoc.v:139496$5790_Y + connect \$37 $or$libresoc.v:139497$5791_Y + connect \$379 $eq$libresoc.v:139498$5792_Y + connect \$381 $ne$libresoc.v:139499$5793_Y + connect \$383 $and$libresoc.v:139500$5794_Y + connect \$385 $ne$libresoc.v:139501$5795_Y + connect \$387 $and$libresoc.v:139502$5796_Y + connect \$389 $ne$libresoc.v:139503$5797_Y + connect \$391 $and$libresoc.v:139504$5798_Y + connect \$393 $not$libresoc.v:139505$5799_Y + connect \$395 $and$libresoc.v:139506$5800_Y + connect \$397 $eq$libresoc.v:139507$5801_Y + connect \$3 $eq$libresoc.v:139508$5802_Y + connect \$39 $eq$libresoc.v:139509$5803_Y + connect \$399 $eq$libresoc.v:139510$5804_Y + connect \$401 $ne$libresoc.v:139511$5805_Y + connect \$403 $and$libresoc.v:139512$5806_Y + connect \$405 $ne$libresoc.v:139513$5807_Y + connect \$407 $and$libresoc.v:139514$5808_Y + connect \$409 $ne$libresoc.v:139515$5809_Y + connect \$411 $and$libresoc.v:139516$5810_Y + connect \$413 $not$libresoc.v:139517$5811_Y + connect \$415 $and$libresoc.v:139518$5812_Y + connect \$417 $eq$libresoc.v:139519$5813_Y + connect \$41 $or$libresoc.v:139520$5814_Y + connect \$419 $ne$libresoc.v:139521$5815_Y + connect \$421 $and$libresoc.v:139522$5816_Y + connect \$423 $ne$libresoc.v:139523$5817_Y + connect \$425 $and$libresoc.v:139524$5818_Y + connect \$427 $ne$libresoc.v:139525$5819_Y + connect \$429 $and$libresoc.v:139526$5820_Y + connect \$431 $not$libresoc.v:139527$5821_Y + connect \$433 $and$libresoc.v:139528$5822_Y + connect \$436 $eq$libresoc.v:139529$5823_Y + connect \$435 $not$libresoc.v:139530$5824_Y + connect \$43 $and$libresoc.v:139531$5825_Y + connect \$439 $eq$libresoc.v:139532$5826_Y + connect \$441 $eq$libresoc.v:139533$5827_Y + connect \$443 $or$libresoc.v:139534$5828_Y + connect \$445 $eq$libresoc.v:139535$5829_Y + connect \$448 $add$libresoc.v:139536$5830_Y + connect \$451 $add$libresoc.v:139537$5831_Y + connect \$453 $pos$libresoc.v:139538$5833_Y + connect \$456 $eq$libresoc.v:139539$5834_Y + connect \$458 $eq$libresoc.v:139540$5835_Y + connect \$45 $and$libresoc.v:139541$5836_Y + connect \$460 $or$libresoc.v:139542$5837_Y + connect \$462 $eq$libresoc.v:139543$5838_Y + connect \$465 $add$libresoc.v:139544$5839_Y + connect \$468 $add$libresoc.v:139545$5840_Y + connect \$47 $eq$libresoc.v:139546$5841_Y + connect \$49 $eq$libresoc.v:139547$5842_Y + connect \$51 $ternary$libresoc.v:139548$5843_Y + connect \$53 $ternary$libresoc.v:139549$5844_Y + connect \$55 $ternary$libresoc.v:139550$5845_Y + connect \$57 $ternary$libresoc.v:139551$5846_Y + connect \$5 $or$libresoc.v:139552$5847_Y + connect \$59 $ternary$libresoc.v:139553$5848_Y + connect \$61 $ternary$libresoc.v:139554$5849_Y + connect \$63 $ternary$libresoc.v:139555$5850_Y + connect \$65 $ternary$libresoc.v:139556$5851_Y + connect \$67 $ternary$libresoc.v:139557$5852_Y + connect \$69 $ternary$libresoc.v:139558$5853_Y + connect \$71 $ternary$libresoc.v:139559$5854_Y + connect \$73 $ternary$libresoc.v:139560$5855_Y + connect \$75 $ternary$libresoc.v:139561$5856_Y + connect \$77 $ternary$libresoc.v:139562$5857_Y + connect \$7 $and$libresoc.v:139563$5858_Y + connect \$79 $ternary$libresoc.v:139564$5859_Y + connect \$81 $ternary$libresoc.v:139565$5860_Y + connect \$83 $ternary$libresoc.v:139566$5861_Y + connect \$85 $ternary$libresoc.v:139567$5862_Y + connect \$87 $ternary$libresoc.v:139568$5863_Y + connect \$89 $ternary$libresoc.v:139569$5864_Y + connect \$91 $ternary$libresoc.v:139570$5865_Y + connect \$93 $ternary$libresoc.v:139571$5866_Y + connect \$95 $ternary$libresoc.v:139572$5867_Y + connect \$97 $ternary$libresoc.v:139573$5868_Y connect \$447 \$448 connect \$450 \$451 connect \$464 \$465 @@ -224164,136 +223960,136 @@ module \jtag connect \sr0_capture \$327 connect \sr0_isir \$323 connect \sr0__o \sr0_reg - connect \sdr_dq_15__pad__oe \$309 - connect \sdr_dq_15__pad__o \$307 - connect \sdr_dq_15__core__i \$305 - connect \sdr_dq_14__pad__oe \$303 - connect \sdr_dq_14__pad__o \$301 - connect \sdr_dq_14__core__i \$299 - connect \sdr_dq_13__pad__oe \$297 - connect \sdr_dq_13__pad__o \$295 - connect \sdr_dq_13__core__i \$293 - connect \sdr_dq_12__pad__oe \$291 - connect \sdr_dq_12__pad__o \$289 - connect \sdr_dq_12__core__i \$287 - connect \sdr_dq_11__pad__oe \$285 - connect \sdr_dq_11__pad__o \$283 - connect \sdr_dq_11__core__i \$281 - connect \sdr_dq_10__pad__oe \$279 - connect \sdr_dq_10__pad__o \$277 - connect \sdr_dq_10__core__i \$275 - connect \sdr_dq_9__pad__oe \$273 - connect \sdr_dq_9__pad__o \$271 - connect \sdr_dq_9__core__i \$269 - connect \sdr_dq_8__pad__oe \$267 - connect \sdr_dq_8__pad__o \$265 - connect \sdr_dq_8__core__i \$263 - connect \sdr_dm_1__pad__o \$261 - connect \sdr_a_12__pad__o \$259 - connect \sdr_a_11__pad__o \$257 - connect \sdr_a_10__pad__o \$255 - connect \sdr_cs_n__pad__o \$253 - connect \sdr_we_n__pad__o \$251 - connect \sdr_cas_n__pad__o \$249 - connect \sdr_ras_n__pad__o \$247 - connect \sdr_cke__pad__o \$245 - connect \sdr_clock__pad__o \$243 - connect \sdr_ba_1__pad__o \$241 - connect \sdr_ba_0__pad__o \$239 - connect \sdr_a_9__pad__o \$237 - connect \sdr_a_8__pad__o \$235 - connect \sdr_a_7__pad__o \$233 - connect \sdr_a_6__pad__o \$231 - connect \sdr_a_5__pad__o \$229 - connect \sdr_a_4__pad__o \$227 - connect \sdr_a_3__pad__o \$225 - connect \sdr_a_2__pad__o \$223 - connect \sdr_a_1__pad__o \$221 - connect \sdr_a_0__pad__o \$219 - connect \sdr_dq_7__pad__oe \$217 - connect \sdr_dq_7__pad__o \$215 - connect \sdr_dq_7__core__i \$213 - connect \sdr_dq_6__pad__oe \$211 - connect \sdr_dq_6__pad__o \$209 - connect \sdr_dq_6__core__i \$207 - connect \sdr_dq_5__pad__oe \$205 - connect \sdr_dq_5__pad__o \$203 - connect \sdr_dq_5__core__i \$201 - connect \sdr_dq_4__pad__oe \$199 - connect \sdr_dq_4__pad__o \$197 - connect \sdr_dq_4__core__i \$195 - connect \sdr_dq_3__pad__oe \$193 - connect \sdr_dq_3__pad__o \$191 - connect \sdr_dq_3__core__i \$189 - connect \sdr_dq_2__pad__oe \$187 - connect \sdr_dq_2__pad__o \$185 - connect \sdr_dq_2__core__i \$183 - connect \sdr_dq_1__pad__oe \$181 - connect \sdr_dq_1__pad__o \$179 - connect \sdr_dq_1__core__i \$177 - connect \sdr_dq_0__pad__oe \$175 - connect \sdr_dq_0__pad__o \$173 - connect \sdr_dq_0__core__i \$171 - connect \sdr_dm_0__pad__o \$169 - connect \mtwi_scl__pad__o \$167 - connect \mtwi_sda__pad__oe \$165 - connect \mtwi_sda__pad__o \$163 - connect \mtwi_sda__core__i \$161 - connect \mspi0_miso__core__i \$159 - connect \mspi0_mosi__pad__o \$157 - connect \mspi0_cs_n__pad__o \$155 - connect \mspi0_clk__pad__o \$153 - connect \gpio_s7__pad__oe \$151 - connect \gpio_s7__pad__o \$149 - connect \gpio_s7__core__i \$147 - connect \gpio_s6__pad__oe \$145 - connect \gpio_s6__pad__o \$143 - connect \gpio_s6__core__i \$141 - connect \gpio_s5__pad__oe \$139 - connect \gpio_s5__pad__o \$137 - connect \gpio_s5__core__i \$135 - connect \gpio_s4__pad__oe \$133 - connect \gpio_s4__pad__o \$131 - connect \gpio_s4__core__i \$129 - connect \gpio_s3__pad__oe \$127 - connect \gpio_s3__pad__o \$125 - connect \gpio_s3__core__i \$123 - connect \gpio_s2__pad__oe \$121 - connect \gpio_s2__pad__o \$119 - connect \gpio_s2__core__i \$117 - connect \gpio_s1__pad__oe \$115 - connect \gpio_s1__pad__o \$113 - connect \gpio_s1__core__i \$111 - connect \gpio_s0__pad__oe \$109 - connect \gpio_s0__pad__o \$107 - connect \gpio_s0__core__i \$105 - connect \gpio_e15__pad__oe \$103 - connect \gpio_e15__pad__o \$101 - connect \gpio_e15__core__i \$99 - connect \gpio_e14__pad__oe \$97 - connect \gpio_e14__pad__o \$95 - connect \gpio_e14__core__i \$93 - connect \gpio_e13__pad__oe \$91 - connect \gpio_e13__pad__o \$89 - connect \gpio_e13__core__i \$87 - connect \gpio_e12__pad__oe \$85 - connect \gpio_e12__pad__o \$83 - connect \gpio_e12__core__i \$81 - connect \gpio_e11__pad__oe \$79 - connect \gpio_e11__pad__o \$77 - connect \gpio_e11__core__i \$75 - connect \gpio_e10__pad__oe \$73 - connect \gpio_e10__pad__o \$71 - connect \gpio_e10__core__i \$69 - connect \gpio_e9__pad__oe \$67 - connect \gpio_e9__pad__o \$65 - connect \gpio_e9__core__i \$63 - connect \gpio_e8__pad__oe \$61 - connect \gpio_e8__pad__o \$59 - connect \gpio_e8__core__i \$57 - connect \eint_2__core__i \$55 - connect \eint_1__core__i \$53 - connect \eint_0__core__i \$51 + connect \eint_2__core__i \$309 + connect \eint_1__core__i \$307 + connect \eint_0__core__i \$305 + connect \mtwi_scl__pad__o \$303 + connect \mtwi_sda__pad__oe \$301 + connect \mtwi_sda__pad__o \$299 + connect \mtwi_sda__core__i \$297 + connect \gpio_s7__pad__oe \$295 + connect \gpio_s7__pad__o \$293 + connect \gpio_s7__core__i \$291 + connect \gpio_s6__pad__oe \$289 + connect \gpio_s6__pad__o \$287 + connect \gpio_s6__core__i \$285 + connect \gpio_s5__pad__oe \$283 + connect \gpio_s5__pad__o \$281 + connect \gpio_s5__core__i \$279 + connect \gpio_s4__pad__oe \$277 + connect \gpio_s4__pad__o \$275 + connect \gpio_s4__core__i \$273 + connect \gpio_s3__pad__oe \$271 + connect \gpio_s3__pad__o \$269 + connect \gpio_s3__core__i \$267 + connect \gpio_s2__pad__oe \$265 + connect \gpio_s2__pad__o \$263 + connect \gpio_s2__core__i \$261 + connect \gpio_s1__pad__oe \$259 + connect \gpio_s1__pad__o \$257 + connect \gpio_s1__core__i \$255 + connect \gpio_s0__pad__oe \$253 + connect \gpio_s0__pad__o \$251 + connect \gpio_s0__core__i \$249 + connect \gpio_e15__pad__oe \$247 + connect \gpio_e15__pad__o \$245 + connect \gpio_e15__core__i \$243 + connect \gpio_e14__pad__oe \$241 + connect \gpio_e14__pad__o \$239 + connect \gpio_e14__core__i \$237 + connect \gpio_e13__pad__oe \$235 + connect \gpio_e13__pad__o \$233 + connect \gpio_e13__core__i \$231 + connect \gpio_e12__pad__oe \$229 + connect \gpio_e12__pad__o \$227 + connect \gpio_e12__core__i \$225 + connect \gpio_e11__pad__oe \$223 + connect \gpio_e11__pad__o \$221 + connect \gpio_e11__core__i \$219 + connect \gpio_e10__pad__oe \$217 + connect \gpio_e10__pad__o \$215 + connect \gpio_e10__core__i \$213 + connect \gpio_e9__pad__oe \$211 + connect \gpio_e9__pad__o \$209 + connect \gpio_e9__core__i \$207 + connect \gpio_e8__pad__oe \$205 + connect \gpio_e8__pad__o \$203 + connect \gpio_e8__core__i \$201 + connect \sdr_dq_15__pad__oe \$199 + connect \sdr_dq_15__pad__o \$197 + connect \sdr_dq_15__core__i \$195 + connect \sdr_dq_14__pad__oe \$193 + connect \sdr_dq_14__pad__o \$191 + connect \sdr_dq_14__core__i \$189 + connect \sdr_dq_13__pad__oe \$187 + connect \sdr_dq_13__pad__o \$185 + connect \sdr_dq_13__core__i \$183 + connect \sdr_dq_12__pad__oe \$181 + connect \sdr_dq_12__pad__o \$179 + connect \sdr_dq_12__core__i \$177 + connect \sdr_dq_11__pad__oe \$175 + connect \sdr_dq_11__pad__o \$173 + connect \sdr_dq_11__core__i \$171 + connect \sdr_dq_10__pad__oe \$169 + connect \sdr_dq_10__pad__o \$167 + connect \sdr_dq_10__core__i \$165 + connect \sdr_dq_9__pad__oe \$163 + connect \sdr_dq_9__pad__o \$161 + connect \sdr_dq_9__core__i \$159 + connect \sdr_dq_8__pad__oe \$157 + connect \sdr_dq_8__pad__o \$155 + connect \sdr_dq_8__core__i \$153 + connect \sdr_dm_1__pad__o \$151 + connect \sdr_a_12__pad__o \$149 + connect \sdr_a_11__pad__o \$147 + connect \sdr_a_10__pad__o \$145 + connect \sdr_cs_n__pad__o \$143 + connect \sdr_we_n__pad__o \$141 + connect \sdr_cas_n__pad__o \$139 + connect \sdr_ras_n__pad__o \$137 + connect \sdr_cke__pad__o \$135 + connect \sdr_clock__pad__o \$133 + connect \sdr_ba_1__pad__o \$131 + connect \sdr_ba_0__pad__o \$129 + connect \sdr_a_9__pad__o \$127 + connect \sdr_a_8__pad__o \$125 + connect \sdr_a_7__pad__o \$123 + connect \sdr_a_6__pad__o \$121 + connect \sdr_a_5__pad__o \$119 + connect \sdr_a_4__pad__o \$117 + connect \sdr_a_3__pad__o \$115 + connect \sdr_a_2__pad__o \$113 + connect \sdr_a_1__pad__o \$111 + connect \sdr_a_0__pad__o \$109 + connect \sdr_dq_7__pad__oe \$107 + connect \sdr_dq_7__pad__o \$105 + connect \sdr_dq_7__core__i \$103 + connect \sdr_dq_6__pad__oe \$101 + connect \sdr_dq_6__pad__o \$99 + connect \sdr_dq_6__core__i \$97 + connect \sdr_dq_5__pad__oe \$95 + connect \sdr_dq_5__pad__o \$93 + connect \sdr_dq_5__core__i \$91 + connect \sdr_dq_4__pad__oe \$89 + connect \sdr_dq_4__pad__o \$87 + connect \sdr_dq_4__core__i \$85 + connect \sdr_dq_3__pad__oe \$83 + connect \sdr_dq_3__pad__o \$81 + connect \sdr_dq_3__core__i \$79 + connect \sdr_dq_2__pad__oe \$77 + connect \sdr_dq_2__pad__o \$75 + connect \sdr_dq_2__core__i \$73 + connect \sdr_dq_1__pad__oe \$71 + connect \sdr_dq_1__pad__o \$69 + connect \sdr_dq_1__core__i \$67 + connect \sdr_dq_0__pad__oe \$65 + connect \sdr_dq_0__pad__o \$63 + connect \sdr_dq_0__core__i \$61 + connect \sdr_dm_0__pad__o \$59 + connect \mspi0_miso__core__i \$57 + connect \mspi0_mosi__pad__o \$55 + connect \mspi0_cs_n__pad__o \$53 + connect \mspi0_clk__pad__o \$51 connect \io_bd2core \$49 connect \io_bd2io \$47 connect \io_update \$45 @@ -224302,14 +224098,14 @@ module \jtag connect \_idblock_id_bypass \$9 connect \_idblock_select_id \$7 end -attribute \src "libresoc.v:140829.1-141018.10" +attribute \src "libresoc.v:140625.1-140814.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0" attribute \generator "nMigen" module \l0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 23 \dbus__ack @@ -224412,7 +224208,7 @@ module \l0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 21 \wb_dcache_en attribute \module_not_derived 1 - attribute \src "libresoc.v:140934.12-140968.4" + attribute \src "libresoc.v:140730.12-140764.4" cell \l0$130 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224449,7 +224245,7 @@ module \l0 connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:140969.9-140991.4" + attribute \src "libresoc.v:140765.9-140787.4" cell \lsmem \lsmem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224474,7 +224270,7 @@ module \l0 connect \x_valid_i \pimem_x_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:140992.9-141016.4" + attribute \src "libresoc.v:140788.9-140812.4" cell \pimem \pimem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224502,145 +224298,145 @@ module \l0 end connect \pimem_ldst_port0_exc_$signal 1'0 end -attribute \src "libresoc.v:141022.1-141430.10" +attribute \src "libresoc.v:140818.1-141226.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" attribute \generator "nMigen" module \l0$130 - attribute \src "libresoc.v:141285.3-141299.6" + attribute \src "libresoc.v:141081.3-141095.6" wire $0\idx_l$23$next[0:0]$6142 - attribute \src "libresoc.v:141185.3-141186.35" + attribute \src "libresoc.v:140981.3-140982.35" wire $0\idx_l$23[0:0]$6109 - attribute \src "libresoc.v:141043.7-141043.24" + attribute \src "libresoc.v:140839.7-140839.24" wire $0\idx_l$23[0:0]$6164 - attribute \src "libresoc.v:141340.3-141349.6" + attribute \src "libresoc.v:141136.3-141145.6" wire $0\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:141330.3-141339.6" + attribute \src "libresoc.v:141126.3-141135.6" wire $0\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:141023.7-141023.20" + attribute \src "libresoc.v:140819.7-140819.20" wire $0\initial[0:0] - attribute \src "libresoc.v:141206.3-141215.6" + attribute \src "libresoc.v:141002.3-141011.6" wire width 48 $0\ldst_port0_addr_i$12[47:0]$6111 - attribute \src "libresoc.v:141216.3-141225.6" + attribute \src "libresoc.v:141012.3-141021.6" wire $0\ldst_port0_addr_i_ok$13[0:0]$6114 - attribute \src "libresoc.v:141258.3-141267.6" + attribute \src "libresoc.v:141054.3-141063.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:141248.3-141257.6" + attribute \src "libresoc.v:141044.3-141053.6" wire $0\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:141320.3-141329.6" + attribute \src "libresoc.v:141116.3-141125.6" wire $0\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:141395.3-141404.6" + attribute \src "libresoc.v:141191.3-141200.6" wire width 4 $0\ldst_port0_data_len$11[3:0]$6159 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$1[0:0]$6126 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$2[0:0]$6127 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$3[0:0]$6128 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$4[0:0]$6129 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$5[0:0]$6130 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$6[0:0]$6131 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$7[0:0]$6132 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal[0:0]$6125 - attribute \src "libresoc.v:141405.3-141414.6" + attribute \src "libresoc.v:141201.3-141210.6" wire $0\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:141375.3-141384.6" + attribute \src "libresoc.v:141171.3-141180.6" wire $0\ldst_port0_is_ld_i$8[0:0]$6153 - attribute \src "libresoc.v:141385.3-141394.6" + attribute \src "libresoc.v:141181.3-141190.6" wire $0\ldst_port0_is_st_i$9[0:0]$6156 - attribute \src "libresoc.v:141237.3-141247.6" + attribute \src "libresoc.v:141033.3-141043.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:141237.3-141247.6" + attribute \src "libresoc.v:141033.3-141043.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:141310.3-141319.6" + attribute \src "libresoc.v:141106.3-141115.6" wire $0\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:141300.3-141309.6" + attribute \src "libresoc.v:141096.3-141105.6" wire $0\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:141226.3-141236.6" + attribute \src "libresoc.v:141022.3-141032.6" wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6117 - attribute \src "libresoc.v:141226.3-141236.6" + attribute \src "libresoc.v:141022.3-141032.6" wire $0\ldst_port0_st_data_i_ok$17[0:0]$6118 - attribute \src "libresoc.v:141183.3-141184.36" + attribute \src "libresoc.v:140979.3-140980.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:141365.3-141374.6" + attribute \src "libresoc.v:141161.3-141170.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:141350.3-141364.6" + attribute \src "libresoc.v:141146.3-141160.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:141285.3-141299.6" + attribute \src "libresoc.v:141081.3-141095.6" wire $1\idx_l$23$next[0:0]$6143 - attribute \src "libresoc.v:141340.3-141349.6" + attribute \src "libresoc.v:141136.3-141145.6" wire $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:141330.3-141339.6" + attribute \src "libresoc.v:141126.3-141135.6" wire $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:141206.3-141215.6" + attribute \src "libresoc.v:141002.3-141011.6" wire width 48 $1\ldst_port0_addr_i$12[47:0]$6112 - attribute \src "libresoc.v:141216.3-141225.6" + attribute \src "libresoc.v:141012.3-141021.6" wire $1\ldst_port0_addr_i_ok$13[0:0]$6115 - attribute \src "libresoc.v:141258.3-141267.6" + attribute \src "libresoc.v:141054.3-141063.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:141248.3-141257.6" + attribute \src "libresoc.v:141044.3-141053.6" wire $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:141320.3-141329.6" + attribute \src "libresoc.v:141116.3-141125.6" wire $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:141395.3-141404.6" + attribute \src "libresoc.v:141191.3-141200.6" wire width 4 $1\ldst_port0_data_len$11[3:0]$6160 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$1[0:0]$6134 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$2[0:0]$6135 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$3[0:0]$6136 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$4[0:0]$6137 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$5[0:0]$6138 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$6[0:0]$6139 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$7[0:0]$6140 - attribute \src "libresoc.v:141268.3-141284.6" + attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal[0:0]$6133 - attribute \src "libresoc.v:141405.3-141414.6" + attribute \src "libresoc.v:141201.3-141210.6" wire $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:141375.3-141384.6" + attribute \src "libresoc.v:141171.3-141180.6" wire $1\ldst_port0_is_ld_i$8[0:0]$6154 - attribute \src "libresoc.v:141385.3-141394.6" + attribute \src "libresoc.v:141181.3-141190.6" wire $1\ldst_port0_is_st_i$9[0:0]$6157 - attribute \src "libresoc.v:141237.3-141247.6" + attribute \src "libresoc.v:141033.3-141043.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:141237.3-141247.6" + attribute \src "libresoc.v:141033.3-141043.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:141310.3-141319.6" + attribute \src "libresoc.v:141106.3-141115.6" wire $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:141300.3-141309.6" + attribute \src "libresoc.v:141096.3-141105.6" wire $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:141226.3-141236.6" + attribute \src "libresoc.v:141022.3-141032.6" wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6119 - attribute \src "libresoc.v:141226.3-141236.6" + attribute \src "libresoc.v:141022.3-141032.6" wire $1\ldst_port0_st_data_i_ok$17[0:0]$6120 - attribute \src "libresoc.v:141170.7-141170.25" + attribute \src "libresoc.v:140966.7-140966.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:141365.3-141374.6" + attribute \src "libresoc.v:141161.3-141170.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:141350.3-141364.6" + attribute \src "libresoc.v:141146.3-141160.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:141285.3-141299.6" + attribute \src "libresoc.v:141081.3-141095.6" wire $2\idx_l$23$next[0:0]$6144 - attribute \src "libresoc.v:141350.3-141364.6" + attribute \src "libresoc.v:141146.3-141160.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:141181.18-141181.103" - wire $not$libresoc.v:141181$6105_Y - attribute \src "libresoc.v:141182.18-141182.118" - wire $not$libresoc.v:141182$6106_Y - attribute \src "libresoc.v:141179.18-141179.134" - wire $or$libresoc.v:141179$6103_Y - attribute \src "libresoc.v:141180.18-141180.120" - wire $ternary$libresoc.v:141180$6104_Y + attribute \src "libresoc.v:140977.18-140977.103" + wire $not$libresoc.v:140977$6105_Y + attribute \src "libresoc.v:140978.18-140978.118" + wire $not$libresoc.v:140978$6106_Y + attribute \src "libresoc.v:140975.18-140975.134" + wire $or$libresoc.v:140975$6103_Y + attribute \src "libresoc.v:140976.18-140976.120" + wire $ternary$libresoc.v:140976$6104_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" @@ -224655,9 +224451,9 @@ module \l0$130 wire width 96 \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" wire width 96 \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \idx_l$23 @@ -224669,7 +224465,7 @@ module \l0$130 wire \idx_l_r_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \idx_l_s_idx_l - attribute \src "libresoc.v:141023.7-141023.15" + attribute \src "libresoc.v:140819.7-140819.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 input 6 \ldst_port0_addr_i @@ -224780,23 +224576,23 @@ module \l0$130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$libresoc.v:141181$6105 + cell $not $not$libresoc.v:140977$6105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pick_n - connect \Y $not$libresoc.v:141181$6105_Y + connect \Y $not$libresoc.v:140977$6105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$libresoc.v:141182$6106 + cell $not $not$libresoc.v:140978$6106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o$10 - connect \Y $not$libresoc.v:141182$6106_Y + connect \Y $not$libresoc.v:140978$6106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$libresoc.v:141179$6103 + cell $or $or$libresoc.v:140975$6103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224804,18 +224600,18 @@ module \l0$130 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:141179$6103_Y + connect \Y $or$libresoc.v:140975$6103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:141180$6104 + cell $mux $ternary$libresoc.v:140976$6104 parameter \WIDTH 1 connect \A \idx_l$23 connect \B \pick_o connect \S \idx_l_q_idx_l - connect \Y $ternary$libresoc.v:141180$6104_Y + connect \Y $ternary$libresoc.v:140976$6104_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:141187.9-141193.4" + attribute \src "libresoc.v:140983.9-140989.4" cell \idx_l \idx_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224824,14 +224620,14 @@ module \l0$130 connect \s_idx_l \idx_l_s_idx_l end attribute \module_not_derived 1 - attribute \src "libresoc.v:141194.8-141198.4" + attribute \src "libresoc.v:140990.8-140994.4" cell \pick \pick connect \i \pick_i connect \n \pick_n connect \o \pick_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:141199.17-141205.4" + attribute \src "libresoc.v:140995.17-141001.4" cell \reset_l$131 \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224839,52 +224635,52 @@ module \l0$130 connect \r_reset \reset_l_r_reset connect \s_reset \reset_l_s_reset end - attribute \src "libresoc.v:141023.7-141023.20" - process $proc$libresoc.v:141023$6162 + attribute \src "libresoc.v:140819.7-140819.20" + process $proc$libresoc.v:140819$6162 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141043.7-141043.24" - process $proc$libresoc.v:141043$6163 + attribute \src "libresoc.v:140839.7-140839.24" + process $proc$libresoc.v:140839$6163 assign { } { } assign $0\idx_l$23[0:0]$6164 1'0 sync always sync init update \idx_l$23 $0\idx_l$23[0:0]$6164 end - attribute \src "libresoc.v:141170.7-141170.25" - process $proc$libresoc.v:141170$6165 + attribute \src "libresoc.v:140966.7-140966.25" + process $proc$libresoc.v:140966$6165 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:141183.3-141184.36" - process $proc$libresoc.v:141183$6107 + attribute \src "libresoc.v:140979.3-140980.36" + process $proc$libresoc.v:140979$6107 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:141185.3-141186.35" - process $proc$libresoc.v:141185$6108 + attribute \src "libresoc.v:140981.3-140982.35" + process $proc$libresoc.v:140981$6108 assign { } { } assign $0\idx_l$23[0:0]$6109 \idx_l$23$next sync posedge \coresync_clk update \idx_l$23 $0\idx_l$23[0:0]$6109 end - attribute \src "libresoc.v:141206.3-141215.6" - process $proc$libresoc.v:141206$6110 + attribute \src "libresoc.v:141002.3-141011.6" + process $proc$libresoc.v:141002$6110 assign { } { } assign { } { } assign $0\ldst_port0_addr_i$12[47:0]$6111 $1\ldst_port0_addr_i$12[47:0]$6112 - attribute \src "libresoc.v:141207.5-141207.29" + attribute \src "libresoc.v:141003.5-141003.29" switch \initial - attribute \src "libresoc.v:141207.9-141207.17" + attribute \src "libresoc.v:141003.9-141003.17" case 1'1 case end @@ -224900,14 +224696,14 @@ module \l0$130 sync always update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6111 end - attribute \src "libresoc.v:141216.3-141225.6" - process $proc$libresoc.v:141216$6113 + attribute \src "libresoc.v:141012.3-141021.6" + process $proc$libresoc.v:141012$6113 assign { } { } assign { } { } assign $0\ldst_port0_addr_i_ok$13[0:0]$6114 $1\ldst_port0_addr_i_ok$13[0:0]$6115 - attribute \src "libresoc.v:141217.5-141217.29" + attribute \src "libresoc.v:141013.5-141013.29" switch \initial - attribute \src "libresoc.v:141217.9-141217.17" + attribute \src "libresoc.v:141013.9-141013.17" case 1'1 case end @@ -224923,17 +224719,17 @@ module \l0$130 sync always update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6114 end - attribute \src "libresoc.v:141226.3-141236.6" - process $proc$libresoc.v:141226$6116 + attribute \src "libresoc.v:141022.3-141032.6" + process $proc$libresoc.v:141022$6116 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_st_data_i$18[63:0]$6117 $1\ldst_port0_st_data_i$18[63:0]$6119 assign $0\ldst_port0_st_data_i_ok$17[0:0]$6118 $1\ldst_port0_st_data_i_ok$17[0:0]$6120 - attribute \src "libresoc.v:141227.5-141227.29" + attribute \src "libresoc.v:141023.5-141023.29" switch \initial - attribute \src "libresoc.v:141227.9-141227.17" + attribute \src "libresoc.v:141023.9-141023.17" case 1'1 case end @@ -224952,17 +224748,17 @@ module \l0$130 update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6117 update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6118 end - attribute \src "libresoc.v:141237.3-141247.6" - process $proc$libresoc.v:141237$6121 + attribute \src "libresoc.v:141033.3-141043.6" + process $proc$libresoc.v:141033$6121 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:141238.5-141238.29" + attribute \src "libresoc.v:141034.5-141034.29" switch \initial - attribute \src "libresoc.v:141238.9-141238.17" + attribute \src "libresoc.v:141034.9-141034.17" case 1'1 case end @@ -224981,14 +224777,14 @@ module \l0$130 update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:141248.3-141257.6" - process $proc$libresoc.v:141248$6122 + attribute \src "libresoc.v:141044.3-141053.6" + process $proc$libresoc.v:141044$6122 assign { } { } assign { } { } assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:141249.5-141249.29" + attribute \src "libresoc.v:141045.5-141045.29" switch \initial - attribute \src "libresoc.v:141249.9-141249.17" + attribute \src "libresoc.v:141045.9-141045.17" case 1'1 case end @@ -225004,14 +224800,14 @@ module \l0$130 sync always update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end - attribute \src "libresoc.v:141258.3-141267.6" - process $proc$libresoc.v:141258$6123 + attribute \src "libresoc.v:141054.3-141063.6" + process $proc$libresoc.v:141054$6123 assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:141259.5-141259.29" + attribute \src "libresoc.v:141055.5-141055.29" switch \initial - attribute \src "libresoc.v:141259.9-141259.17" + attribute \src "libresoc.v:141055.9-141055.17" case 1'1 case end @@ -225027,8 +224823,8 @@ module \l0$130 sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:141268.3-141284.6" - process $proc$libresoc.v:141268$6124 + attribute \src "libresoc.v:141064.3-141080.6" + process $proc$libresoc.v:141064$6124 assign { } { } assign { } { } assign { } { } @@ -225053,9 +224849,9 @@ module \l0$130 assign $0\ldst_port0_exc_$signal$5[0:0]$6130 $1\ldst_port0_exc_$signal$5[0:0]$6138 assign $0\ldst_port0_exc_$signal$6[0:0]$6131 $1\ldst_port0_exc_$signal$6[0:0]$6139 assign $0\ldst_port0_exc_$signal$7[0:0]$6132 $1\ldst_port0_exc_$signal$7[0:0]$6140 - attribute \src "libresoc.v:141269.5-141269.29" + attribute \src "libresoc.v:141065.5-141065.29" switch \initial - attribute \src "libresoc.v:141269.9-141269.17" + attribute \src "libresoc.v:141065.9-141065.17" case 1'1 case end @@ -225092,15 +224888,15 @@ module \l0$130 update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6131 update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6132 end - attribute \src "libresoc.v:141285.3-141299.6" - process $proc$libresoc.v:141285$6141 + attribute \src "libresoc.v:141081.3-141095.6" + process $proc$libresoc.v:141081$6141 assign { } { } assign { } { } assign { } { } assign $0\idx_l$23$next[0:0]$6142 $2\idx_l$23$next[0:0]$6144 - attribute \src "libresoc.v:141286.5-141286.29" + attribute \src "libresoc.v:141082.5-141082.29" switch \initial - attribute \src "libresoc.v:141286.9-141286.17" + attribute \src "libresoc.v:141082.9-141082.17" case 1'1 case end @@ -225125,14 +224921,14 @@ module \l0$130 sync always update \idx_l$23$next $0\idx_l$23$next[0:0]$6142 end - attribute \src "libresoc.v:141300.3-141309.6" - process $proc$libresoc.v:141300$6145 + attribute \src "libresoc.v:141096.3-141105.6" + process $proc$libresoc.v:141096$6145 assign { } { } assign { } { } assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:141301.5-141301.29" + attribute \src "libresoc.v:141097.5-141097.29" switch \initial - attribute \src "libresoc.v:141301.9-141301.17" + attribute \src "libresoc.v:141097.9-141097.17" case 1'1 case end @@ -225148,14 +224944,14 @@ module \l0$130 sync always update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] end - attribute \src "libresoc.v:141310.3-141319.6" - process $proc$libresoc.v:141310$6146 + attribute \src "libresoc.v:141106.3-141115.6" + process $proc$libresoc.v:141106$6146 assign { } { } assign { } { } assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:141311.5-141311.29" + attribute \src "libresoc.v:141107.5-141107.29" switch \initial - attribute \src "libresoc.v:141311.9-141311.17" + attribute \src "libresoc.v:141107.9-141107.17" case 1'1 case end @@ -225171,14 +224967,14 @@ module \l0$130 sync always update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end - attribute \src "libresoc.v:141320.3-141329.6" - process $proc$libresoc.v:141320$6147 + attribute \src "libresoc.v:141116.3-141125.6" + process $proc$libresoc.v:141116$6147 assign { } { } assign { } { } assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:141321.5-141321.29" + attribute \src "libresoc.v:141117.5-141117.29" switch \initial - attribute \src "libresoc.v:141321.9-141321.17" + attribute \src "libresoc.v:141117.9-141117.17" case 1'1 case end @@ -225194,14 +224990,14 @@ module \l0$130 sync always update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] end - attribute \src "libresoc.v:141330.3-141339.6" - process $proc$libresoc.v:141330$6148 + attribute \src "libresoc.v:141126.3-141135.6" + process $proc$libresoc.v:141126$6148 assign { } { } assign { } { } assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:141331.5-141331.29" + attribute \src "libresoc.v:141127.5-141127.29" switch \initial - attribute \src "libresoc.v:141331.9-141331.17" + attribute \src "libresoc.v:141127.9-141127.17" case 1'1 case end @@ -225217,14 +225013,14 @@ module \l0$130 sync always update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end - attribute \src "libresoc.v:141340.3-141349.6" - process $proc$libresoc.v:141340$6149 + attribute \src "libresoc.v:141136.3-141145.6" + process $proc$libresoc.v:141136$6149 assign { } { } assign { } { } assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:141341.5-141341.29" + attribute \src "libresoc.v:141137.5-141137.29" switch \initial - attribute \src "libresoc.v:141341.9-141341.17" + attribute \src "libresoc.v:141137.9-141137.17" case 1'1 case end @@ -225240,14 +225036,14 @@ module \l0$130 sync always update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] end - attribute \src "libresoc.v:141350.3-141364.6" - process $proc$libresoc.v:141350$6150 + attribute \src "libresoc.v:141146.3-141160.6" + process $proc$libresoc.v:141146$6150 assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:141351.5-141351.29" + attribute \src "libresoc.v:141147.5-141147.29" switch \initial - attribute \src "libresoc.v:141351.9-141351.17" + attribute \src "libresoc.v:141147.9-141147.17" case 1'1 case end @@ -225272,14 +225068,14 @@ module \l0$130 sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:141365.3-141374.6" - process $proc$libresoc.v:141365$6151 + attribute \src "libresoc.v:141161.3-141170.6" + process $proc$libresoc.v:141161$6151 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:141366.5-141366.29" + attribute \src "libresoc.v:141162.5-141162.29" switch \initial - attribute \src "libresoc.v:141366.9-141366.17" + attribute \src "libresoc.v:141162.9-141162.17" case 1'1 case end @@ -225295,14 +225091,14 @@ module \l0$130 sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:141375.3-141384.6" - process $proc$libresoc.v:141375$6152 + attribute \src "libresoc.v:141171.3-141180.6" + process $proc$libresoc.v:141171$6152 assign { } { } assign { } { } assign $0\ldst_port0_is_ld_i$8[0:0]$6153 $1\ldst_port0_is_ld_i$8[0:0]$6154 - attribute \src "libresoc.v:141376.5-141376.29" + attribute \src "libresoc.v:141172.5-141172.29" switch \initial - attribute \src "libresoc.v:141376.9-141376.17" + attribute \src "libresoc.v:141172.9-141172.17" case 1'1 case end @@ -225318,14 +225114,14 @@ module \l0$130 sync always update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6153 end - attribute \src "libresoc.v:141385.3-141394.6" - process $proc$libresoc.v:141385$6155 + attribute \src "libresoc.v:141181.3-141190.6" + process $proc$libresoc.v:141181$6155 assign { } { } assign { } { } assign $0\ldst_port0_is_st_i$9[0:0]$6156 $1\ldst_port0_is_st_i$9[0:0]$6157 - attribute \src "libresoc.v:141386.5-141386.29" + attribute \src "libresoc.v:141182.5-141182.29" switch \initial - attribute \src "libresoc.v:141386.9-141386.17" + attribute \src "libresoc.v:141182.9-141182.17" case 1'1 case end @@ -225341,14 +225137,14 @@ module \l0$130 sync always update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6156 end - attribute \src "libresoc.v:141395.3-141404.6" - process $proc$libresoc.v:141395$6158 + attribute \src "libresoc.v:141191.3-141200.6" + process $proc$libresoc.v:141191$6158 assign { } { } assign { } { } assign $0\ldst_port0_data_len$11[3:0]$6159 $1\ldst_port0_data_len$11[3:0]$6160 - attribute \src "libresoc.v:141396.5-141396.29" + attribute \src "libresoc.v:141192.5-141192.29" switch \initial - attribute \src "libresoc.v:141396.9-141396.17" + attribute \src "libresoc.v:141192.9-141192.17" case 1'1 case end @@ -225364,14 +225160,14 @@ module \l0$130 sync always update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6159 end - attribute \src "libresoc.v:141405.3-141414.6" - process $proc$libresoc.v:141405$6161 + attribute \src "libresoc.v:141201.3-141210.6" + process $proc$libresoc.v:141201$6161 assign { } { } assign { } { } assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:141406.5-141406.29" + attribute \src "libresoc.v:141202.5-141202.29" switch \initial - attribute \src "libresoc.v:141406.9-141406.17" + attribute \src "libresoc.v:141202.9-141202.17" case 1'1 case end @@ -225387,10 +225183,10 @@ module \l0$130 sync always update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] end - connect \$20 $or$libresoc.v:141179$6103_Y - connect \$24 $ternary$libresoc.v:141180$6104_Y - connect \$26 $not$libresoc.v:141181$6105_Y - connect \$28 $not$libresoc.v:141182$6106_Y + connect \$20 $or$libresoc.v:140975$6103_Y + connect \$24 $ternary$libresoc.v:140976$6104_Y + connect \$26 $not$libresoc.v:140977$6105_Y + connect \$28 $not$libresoc.v:140978$6106_Y connect \$22 \$24 connect \$32 \ldst_port0_addr_i connect \ldst_port0_go_die_i$30 1'0 @@ -225407,37 +225203,37 @@ module \l0$130 connect \reset_delay$next \reset_l_q_reset connect \pick_i \$20 end -attribute \src "libresoc.v:141434.1-141492.10" +attribute \src "libresoc.v:141230.1-141288.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" attribute \generator "nMigen" module \ld_active - attribute \src "libresoc.v:141435.7-141435.20" + attribute \src "libresoc.v:141231.7-141231.20" wire $0\initial[0:0] - attribute \src "libresoc.v:141480.3-141488.6" + attribute \src "libresoc.v:141276.3-141284.6" wire $0\q_int$next[0:0]$6176 - attribute \src "libresoc.v:141478.3-141479.27" + attribute \src "libresoc.v:141274.3-141275.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:141480.3-141488.6" + attribute \src "libresoc.v:141276.3-141284.6" wire $1\q_int$next[0:0]$6177 - attribute \src "libresoc.v:141457.7-141457.19" + attribute \src "libresoc.v:141253.7-141253.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:141470.17-141470.96" - wire $and$libresoc.v:141470$6166_Y - attribute \src "libresoc.v:141475.17-141475.96" - wire $and$libresoc.v:141475$6171_Y - attribute \src "libresoc.v:141472.18-141472.99" - wire $not$libresoc.v:141472$6168_Y - attribute \src "libresoc.v:141474.17-141474.98" - wire $not$libresoc.v:141474$6170_Y - attribute \src "libresoc.v:141477.17-141477.98" - wire $not$libresoc.v:141477$6173_Y - attribute \src "libresoc.v:141471.18-141471.104" - wire $or$libresoc.v:141471$6167_Y - attribute \src "libresoc.v:141473.18-141473.105" - wire $or$libresoc.v:141473$6169_Y - attribute \src "libresoc.v:141476.17-141476.103" - wire $or$libresoc.v:141476$6172_Y + attribute \src "libresoc.v:141266.17-141266.96" + wire $and$libresoc.v:141266$6166_Y + attribute \src "libresoc.v:141271.17-141271.96" + wire $and$libresoc.v:141271$6171_Y + attribute \src "libresoc.v:141268.18-141268.99" + wire $not$libresoc.v:141268$6168_Y + attribute \src "libresoc.v:141270.17-141270.98" + wire $not$libresoc.v:141270$6170_Y + attribute \src "libresoc.v:141273.17-141273.98" + wire $not$libresoc.v:141273$6173_Y + attribute \src "libresoc.v:141267.18-141267.104" + wire $or$libresoc.v:141267$6167_Y + attribute \src "libresoc.v:141269.18-141269.105" + wire $or$libresoc.v:141269$6169_Y + attribute \src "libresoc.v:141272.17-141272.103" + wire $or$libresoc.v:141272$6172_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -225454,11 +225250,11 @@ module \ld_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:141435.7-141435.15" + attribute \src "libresoc.v:141231.7-141231.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -225475,7 +225271,7 @@ module \ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:141470$6166 + cell $and $and$libresoc.v:141266$6166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225483,10 +225279,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:141470$6166_Y + connect \Y $and$libresoc.v:141266$6166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:141475$6171 + cell $and $and$libresoc.v:141271$6171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225494,34 +225290,34 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:141475$6171_Y + connect \Y $and$libresoc.v:141271$6171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:141472$6168 + cell $not $not$libresoc.v:141268$6168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_ld_active - connect \Y $not$libresoc.v:141472$6168_Y + connect \Y $not$libresoc.v:141268$6168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:141474$6170 + cell $not $not$libresoc.v:141270$6170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:141474$6170_Y + connect \Y $not$libresoc.v:141270$6170_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:141477$6173 + cell $not $not$libresoc.v:141273$6173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:141477$6173_Y + connect \Y $not$libresoc.v:141273$6173_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:141471$6167 + cell $or $or$libresoc.v:141267$6167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225529,10 +225325,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_ld_active - connect \Y $or$libresoc.v:141471$6167_Y + connect \Y $or$libresoc.v:141267$6167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:141473$6169 + cell $or $or$libresoc.v:141269$6169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225540,10 +225336,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_ld_active connect \B \q_int - connect \Y $or$libresoc.v:141473$6169_Y + connect \Y $or$libresoc.v:141269$6169_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:141476$6172 + cell $or $or$libresoc.v:141272$6172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225551,39 +225347,39 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_ld_active - connect \Y $or$libresoc.v:141476$6172_Y + connect \Y $or$libresoc.v:141272$6172_Y end - attribute \src "libresoc.v:141435.7-141435.20" - process $proc$libresoc.v:141435$6178 + attribute \src "libresoc.v:141231.7-141231.20" + process $proc$libresoc.v:141231$6178 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141457.7-141457.19" - process $proc$libresoc.v:141457$6179 + attribute \src "libresoc.v:141253.7-141253.19" + process $proc$libresoc.v:141253$6179 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:141478.3-141479.27" - process $proc$libresoc.v:141478$6174 + attribute \src "libresoc.v:141274.3-141275.27" + process $proc$libresoc.v:141274$6174 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:141480.3-141488.6" - process $proc$libresoc.v:141480$6175 + attribute \src "libresoc.v:141276.3-141284.6" + process $proc$libresoc.v:141276$6175 assign { } { } assign { } { } assign $0\q_int$next[0:0]$6176 $1\q_int$next[0:0]$6177 - attribute \src "libresoc.v:141481.5-141481.29" + attribute \src "libresoc.v:141277.5-141277.29" switch \initial - attribute \src "libresoc.v:141481.9-141481.17" + attribute \src "libresoc.v:141277.9-141277.17" case 1'1 case end @@ -225599,565 +225395,565 @@ module \ld_active sync always update \q_int$next $0\q_int$next[0:0]$6176 end - connect \$9 $and$libresoc.v:141470$6166_Y - connect \$11 $or$libresoc.v:141471$6167_Y - connect \$13 $not$libresoc.v:141472$6168_Y - connect \$15 $or$libresoc.v:141473$6169_Y - connect \$1 $not$libresoc.v:141474$6170_Y - connect \$3 $and$libresoc.v:141475$6171_Y - connect \$5 $or$libresoc.v:141476$6172_Y - connect \$7 $not$libresoc.v:141477$6173_Y + connect \$9 $and$libresoc.v:141266$6166_Y + connect \$11 $or$libresoc.v:141267$6167_Y + connect \$13 $not$libresoc.v:141268$6168_Y + connect \$15 $or$libresoc.v:141269$6169_Y + connect \$1 $not$libresoc.v:141270$6170_Y + connect \$3 $and$libresoc.v:141271$6171_Y + connect \$5 $or$libresoc.v:141272$6172_Y + connect \$7 $not$libresoc.v:141273$6173_Y connect \qlq_ld_active \$15 connect \qn_ld_active \$13 connect \q_ld_active \$11 end -attribute \src "libresoc.v:141496.1-142859.10" +attribute \src "libresoc.v:141292.1-142655.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" attribute \generator "nMigen" module \ldst0 - attribute \src "libresoc.v:142514.3-142522.6" + attribute \src "libresoc.v:142310.3-142318.6" wire $0\adr_l_r_adr$next[0:0]$6322 - attribute \src "libresoc.v:142396.3-142397.39" + attribute \src "libresoc.v:142192.3-142193.39" wire $0\adr_l_r_adr[0:0] - attribute \src "libresoc.v:142342.3-142343.21" + attribute \src "libresoc.v:142138.3-142139.21" wire $0\alu_ok[0:0] - attribute \src "libresoc.v:142679.3-142688.6" + attribute \src "libresoc.v:142475.3-142484.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:142689.3-142698.6" + attribute \src "libresoc.v:142485.3-142494.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:142669.3-142678.6" + attribute \src "libresoc.v:142465.3-142474.6" wire width 64 $0\ea_r$next[63:0]$6410 - attribute \src "libresoc.v:142344.3-142345.25" + attribute \src "libresoc.v:142140.3-142141.25" wire width 64 $0\ea_r[63:0] - attribute \src "libresoc.v:141497.7-141497.20" + attribute \src "libresoc.v:141293.7-141293.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142744.3-142763.6" + attribute \src "libresoc.v:142540.3-142559.6" wire width 64 $0\ldd_o[63:0] - attribute \src "libresoc.v:142708.3-142731.6" + attribute \src "libresoc.v:142504.3-142527.6" wire width 64 $0\lddata_r[63:0] - attribute \src "libresoc.v:142611.3-142620.6" + attribute \src "libresoc.v:142407.3-142416.6" wire width 64 $0\ldo_r$next[63:0]$6395 - attribute \src "libresoc.v:142352.3-142353.27" + attribute \src "libresoc.v:142148.3-142149.27" wire width 64 $0\ldo_r[63:0] - attribute \src "libresoc.v:142340.3-142341.33" + attribute \src "libresoc.v:142136.3-142137.33" wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:142699.3-142707.6" + attribute \src "libresoc.v:142495.3-142503.6" wire $0\ldst_port0_addr_i_ok$next[0:0]$6415 - attribute \src "libresoc.v:142338.3-142339.57" + attribute \src "libresoc.v:142134.3-142135.57" wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:142788.3-142799.6" + attribute \src "libresoc.v:142584.3-142595.6" wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142559.3-142567.6" + attribute \src "libresoc.v:142355.3-142363.6" wire $0\lsd_l_r_lsd$next[0:0]$6337 - attribute \src "libresoc.v:142386.3-142387.39" + attribute \src "libresoc.v:142182.3-142183.39" wire $0\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:142487.3-142495.6" + attribute \src "libresoc.v:142283.3-142291.6" wire $0\opc_l_r_opc$next[0:0]$6313 - attribute \src "libresoc.v:142402.3-142403.39" + attribute \src "libresoc.v:142198.3-142199.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:142478.3-142486.6" + attribute \src "libresoc.v:142274.3-142282.6" wire $0\opc_l_s_opc$next[0:0]$6310 - attribute \src "libresoc.v:142404.3-142405.39" + attribute \src "libresoc.v:142200.3-142201.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__byte_reverse$next[0:0]$6340 - attribute \src "libresoc.v:142378.3-142379.57" + attribute \src "libresoc.v:142174.3-142175.57" wire $0\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 4 $0\oper_r__data_len$next[3:0]$6341 - attribute \src "libresoc.v:142376.3-142377.49" + attribute \src "libresoc.v:142172.3-142173.49" wire width 4 $0\oper_r__data_len[3:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 14 $0\oper_r__fn_unit$next[13:0]$6342 - attribute \src "libresoc.v:142356.3-142357.47" + attribute \src "libresoc.v:142152.3-142153.47" wire width 14 $0\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 64 $0\oper_r__imm_data__data$next[63:0]$6343 - attribute \src "libresoc.v:142358.3-142359.61" + attribute \src "libresoc.v:142154.3-142155.61" wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__imm_data__ok$next[0:0]$6344 - attribute \src "libresoc.v:142360.3-142361.57" + attribute \src "libresoc.v:142156.3-142157.57" wire $0\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 32 $0\oper_r__insn$next[31:0]$6345 - attribute \src "libresoc.v:142384.3-142385.41" + attribute \src "libresoc.v:142180.3-142181.41" wire width 32 $0\oper_r__insn[31:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 7 $0\oper_r__insn_type$next[6:0]$6346 - attribute \src "libresoc.v:142354.3-142355.51" + attribute \src "libresoc.v:142150.3-142151.51" wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__is_32bit$next[0:0]$6347 - attribute \src "libresoc.v:142372.3-142373.49" + attribute \src "libresoc.v:142168.3-142169.49" wire $0\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__is_signed$next[0:0]$6348 - attribute \src "libresoc.v:142374.3-142375.51" + attribute \src "libresoc.v:142170.3-142171.51" wire $0\oper_r__is_signed[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 2 $0\oper_r__ldst_mode$next[1:0]$6349 - attribute \src "libresoc.v:142382.3-142383.51" + attribute \src "libresoc.v:142178.3-142179.51" wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__oe__oe$next[0:0]$6350 - attribute \src "libresoc.v:142368.3-142369.45" + attribute \src "libresoc.v:142164.3-142165.45" wire $0\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__oe__ok$next[0:0]$6351 - attribute \src "libresoc.v:142370.3-142371.45" + attribute \src "libresoc.v:142166.3-142167.45" wire $0\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__rc__ok$next[0:0]$6352 - attribute \src "libresoc.v:142366.3-142367.45" + attribute \src "libresoc.v:142162.3-142163.45" wire $0\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__rc__rc$next[0:0]$6353 - attribute \src "libresoc.v:142364.3-142365.45" + attribute \src "libresoc.v:142160.3-142161.45" wire $0\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__sign_extend$next[0:0]$6354 - attribute \src "libresoc.v:142380.3-142381.55" + attribute \src "libresoc.v:142176.3-142177.55" wire $0\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__zero_a$next[0:0]$6355 - attribute \src "libresoc.v:142362.3-142363.45" + attribute \src "libresoc.v:142158.3-142159.45" wire $0\oper_r__zero_a[0:0] - attribute \src "libresoc.v:142406.3-142407.28" + attribute \src "libresoc.v:142202.3-142203.28" wire $0\p_st_go[0:0] - attribute \src "libresoc.v:142732.3-142743.6" + attribute \src "libresoc.v:142528.3-142539.6" wire width 64 $0\revnorev[63:0] - attribute \src "libresoc.v:142505.3-142513.6" + attribute \src "libresoc.v:142301.3-142309.6" wire width 3 $0\src_l_r_src$next[2:0]$6319 - attribute \src "libresoc.v:142398.3-142399.39" + attribute \src "libresoc.v:142194.3-142195.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:142496.3-142504.6" + attribute \src "libresoc.v:142292.3-142300.6" wire width 3 $0\src_l_s_src$next[2:0]$6316 - attribute \src "libresoc.v:142400.3-142401.39" + attribute \src "libresoc.v:142196.3-142197.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:142621.3-142636.6" + attribute \src "libresoc.v:142417.3-142432.6" wire width 64 $0\src_r0$next[63:0]$6398 - attribute \src "libresoc.v:142350.3-142351.29" + attribute \src "libresoc.v:142146.3-142147.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:142637.3-142652.6" + attribute \src "libresoc.v:142433.3-142448.6" wire width 64 $0\src_r1$next[63:0]$6402 - attribute \src "libresoc.v:142348.3-142349.29" + attribute \src "libresoc.v:142144.3-142145.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:142653.3-142668.6" + attribute \src "libresoc.v:142449.3-142464.6" wire width 64 $0\src_r2$next[63:0]$6406 - attribute \src "libresoc.v:142346.3-142347.29" + attribute \src "libresoc.v:142142.3-142143.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:142764.3-142787.6" + attribute \src "libresoc.v:142560.3-142583.6" wire width 64 $0\stdata_r[63:0] - attribute \src "libresoc.v:142550.3-142558.6" + attribute \src "libresoc.v:142346.3-142354.6" wire $0\sto_l_r_sto$next[0:0]$6334 - attribute \src "libresoc.v:142388.3-142389.39" + attribute \src "libresoc.v:142184.3-142185.39" wire $0\sto_l_r_sto[0:0] - attribute \src "libresoc.v:142541.3-142549.6" + attribute \src "libresoc.v:142337.3-142345.6" wire $0\upd_l_r_upd$next[0:0]$6331 - attribute \src "libresoc.v:142390.3-142391.39" + attribute \src "libresoc.v:142186.3-142187.39" wire $0\upd_l_r_upd[0:0] - attribute \src "libresoc.v:142532.3-142540.6" + attribute \src "libresoc.v:142328.3-142336.6" wire $0\upd_l_s_upd$next[0:0]$6328 - attribute \src "libresoc.v:142392.3-142393.39" + attribute \src "libresoc.v:142188.3-142189.39" wire $0\upd_l_s_upd[0:0] - attribute \src "libresoc.v:142523.3-142531.6" + attribute \src "libresoc.v:142319.3-142327.6" wire $0\wri_l_r_wri$next[0:0]$6325 - attribute \src "libresoc.v:142394.3-142395.39" + attribute \src "libresoc.v:142190.3-142191.39" wire $0\wri_l_r_wri[0:0] - attribute \src "libresoc.v:142514.3-142522.6" + attribute \src "libresoc.v:142310.3-142318.6" wire $1\adr_l_r_adr$next[0:0]$6323 - attribute \src "libresoc.v:141693.7-141693.25" + attribute \src "libresoc.v:141489.7-141489.25" wire $1\adr_l_r_adr[0:0] - attribute \src "libresoc.v:141707.7-141707.20" + attribute \src "libresoc.v:141503.7-141503.20" wire $1\alu_ok[0:0] - attribute \src "libresoc.v:142679.3-142688.6" + attribute \src "libresoc.v:142475.3-142484.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:142689.3-142698.6" + attribute \src "libresoc.v:142485.3-142494.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:142669.3-142678.6" + attribute \src "libresoc.v:142465.3-142474.6" wire width 64 $1\ea_r$next[63:0]$6411 - attribute \src "libresoc.v:141753.14-141753.41" + attribute \src "libresoc.v:141549.14-141549.41" wire width 64 $1\ea_r[63:0] - attribute \src "libresoc.v:142744.3-142763.6" + attribute \src "libresoc.v:142540.3-142559.6" wire width 64 $1\ldd_o[63:0] - attribute \src "libresoc.v:142708.3-142731.6" + attribute \src "libresoc.v:142504.3-142527.6" wire width 64 $1\lddata_r[63:0] - attribute \src "libresoc.v:142611.3-142620.6" + attribute \src "libresoc.v:142407.3-142416.6" wire width 64 $1\ldo_r$next[63:0]$6396 - attribute \src "libresoc.v:141783.14-141783.42" + attribute \src "libresoc.v:141579.14-141579.42" wire width 64 $1\ldo_r[63:0] - attribute \src "libresoc.v:141788.14-141788.62" + attribute \src "libresoc.v:141584.14-141584.62" wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:142699.3-142707.6" + attribute \src "libresoc.v:142495.3-142503.6" wire $1\ldst_port0_addr_i_ok$next[0:0]$6416 - attribute \src "libresoc.v:141793.7-141793.34" + attribute \src "libresoc.v:141589.7-141589.34" wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:142788.3-142799.6" + attribute \src "libresoc.v:142584.3-142595.6" wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142559.3-142567.6" + attribute \src "libresoc.v:142355.3-142363.6" wire $1\lsd_l_r_lsd$next[0:0]$6338 - attribute \src "libresoc.v:141842.7-141842.25" + attribute \src "libresoc.v:141638.7-141638.25" wire $1\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:142487.3-142495.6" + attribute \src "libresoc.v:142283.3-142291.6" wire $1\opc_l_r_opc$next[0:0]$6314 - attribute \src "libresoc.v:141856.7-141856.25" + attribute \src "libresoc.v:141652.7-141652.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:142478.3-142486.6" + attribute \src "libresoc.v:142274.3-142282.6" wire $1\opc_l_s_opc$next[0:0]$6311 - attribute \src "libresoc.v:141860.7-141860.25" + attribute \src "libresoc.v:141656.7-141656.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__byte_reverse$next[0:0]$6356 - attribute \src "libresoc.v:141991.7-141991.34" + attribute \src "libresoc.v:141787.7-141787.34" wire $1\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 4 $1\oper_r__data_len$next[3:0]$6357 - attribute \src "libresoc.v:141995.13-141995.36" + attribute \src "libresoc.v:141791.13-141791.36" wire width 4 $1\oper_r__data_len[3:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 14 $1\oper_r__fn_unit$next[13:0]$6358 - attribute \src "libresoc.v:142014.14-142014.40" + attribute \src "libresoc.v:141810.14-141810.40" wire width 14 $1\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 64 $1\oper_r__imm_data__data$next[63:0]$6359 - attribute \src "libresoc.v:142018.14-142018.59" + attribute \src "libresoc.v:141814.14-141814.59" wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__imm_data__ok$next[0:0]$6360 - attribute \src "libresoc.v:142022.7-142022.34" + attribute \src "libresoc.v:141818.7-141818.34" wire $1\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 32 $1\oper_r__insn$next[31:0]$6361 - attribute \src "libresoc.v:142026.14-142026.34" + attribute \src "libresoc.v:141822.14-141822.34" wire width 32 $1\oper_r__insn[31:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 7 $1\oper_r__insn_type$next[6:0]$6362 - attribute \src "libresoc.v:142105.13-142105.38" + attribute \src "libresoc.v:141901.13-141901.38" wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__is_32bit$next[0:0]$6363 - attribute \src "libresoc.v:142109.7-142109.30" + attribute \src "libresoc.v:141905.7-141905.30" wire $1\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__is_signed$next[0:0]$6364 - attribute \src "libresoc.v:142113.7-142113.31" + attribute \src "libresoc.v:141909.7-141909.31" wire $1\oper_r__is_signed[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 2 $1\oper_r__ldst_mode$next[1:0]$6365 - attribute \src "libresoc.v:142122.13-142122.37" + attribute \src "libresoc.v:141918.13-141918.37" wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__oe__oe$next[0:0]$6366 - attribute \src "libresoc.v:142126.7-142126.28" + attribute \src "libresoc.v:141922.7-141922.28" wire $1\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__oe__ok$next[0:0]$6367 - attribute \src "libresoc.v:142130.7-142130.28" + attribute \src "libresoc.v:141926.7-141926.28" wire $1\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__rc__ok$next[0:0]$6368 - attribute \src "libresoc.v:142134.7-142134.28" + attribute \src "libresoc.v:141930.7-141930.28" wire $1\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__rc__rc$next[0:0]$6369 - attribute \src "libresoc.v:142138.7-142138.28" + attribute \src "libresoc.v:141934.7-141934.28" wire $1\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__sign_extend$next[0:0]$6370 - attribute \src "libresoc.v:142142.7-142142.33" + attribute \src "libresoc.v:141938.7-141938.33" wire $1\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__zero_a$next[0:0]$6371 - attribute \src "libresoc.v:142146.7-142146.28" + attribute \src "libresoc.v:141942.7-141942.28" wire $1\oper_r__zero_a[0:0] - attribute \src "libresoc.v:142150.7-142150.21" + attribute \src "libresoc.v:141946.7-141946.21" wire $1\p_st_go[0:0] - attribute \src "libresoc.v:142732.3-142743.6" + attribute \src "libresoc.v:142528.3-142539.6" wire width 64 $1\revnorev[63:0] - attribute \src "libresoc.v:142505.3-142513.6" + attribute \src "libresoc.v:142301.3-142309.6" wire width 3 $1\src_l_r_src$next[2:0]$6320 - attribute \src "libresoc.v:142192.13-142192.31" + attribute \src "libresoc.v:141988.13-141988.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:142496.3-142504.6" + attribute \src "libresoc.v:142292.3-142300.6" wire width 3 $1\src_l_s_src$next[2:0]$6317 - attribute \src "libresoc.v:142196.13-142196.31" + attribute \src "libresoc.v:141992.13-141992.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:142621.3-142636.6" + attribute \src "libresoc.v:142417.3-142432.6" wire width 64 $1\src_r0$next[63:0]$6399 - attribute \src "libresoc.v:142200.14-142200.43" + attribute \src "libresoc.v:141996.14-141996.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:142637.3-142652.6" + attribute \src "libresoc.v:142433.3-142448.6" wire width 64 $1\src_r1$next[63:0]$6403 - attribute \src "libresoc.v:142204.14-142204.43" + attribute \src "libresoc.v:142000.14-142000.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:142653.3-142668.6" + attribute \src "libresoc.v:142449.3-142464.6" wire width 64 $1\src_r2$next[63:0]$6407 - attribute \src "libresoc.v:142208.14-142208.43" + attribute \src "libresoc.v:142004.14-142004.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:142764.3-142787.6" + attribute \src "libresoc.v:142560.3-142583.6" wire width 64 $1\stdata_r[63:0] - attribute \src "libresoc.v:142550.3-142558.6" + attribute \src "libresoc.v:142346.3-142354.6" wire $1\sto_l_r_sto$next[0:0]$6335 - attribute \src "libresoc.v:142218.7-142218.25" + attribute \src "libresoc.v:142014.7-142014.25" wire $1\sto_l_r_sto[0:0] - attribute \src "libresoc.v:142541.3-142549.6" + attribute \src "libresoc.v:142337.3-142345.6" wire $1\upd_l_r_upd$next[0:0]$6332 - attribute \src "libresoc.v:142228.7-142228.25" + attribute \src "libresoc.v:142024.7-142024.25" wire $1\upd_l_r_upd[0:0] - attribute \src "libresoc.v:142532.3-142540.6" + attribute \src "libresoc.v:142328.3-142336.6" wire $1\upd_l_s_upd$next[0:0]$6329 - attribute \src "libresoc.v:142232.7-142232.25" + attribute \src "libresoc.v:142028.7-142028.25" wire $1\upd_l_s_upd[0:0] - attribute \src "libresoc.v:142523.3-142531.6" + attribute \src "libresoc.v:142319.3-142327.6" wire $1\wri_l_r_wri$next[0:0]$6326 - attribute \src "libresoc.v:142242.7-142242.25" + attribute \src "libresoc.v:142038.7-142038.25" wire $1\wri_l_r_wri[0:0] - attribute \src "libresoc.v:142744.3-142763.6" + attribute \src "libresoc.v:142540.3-142559.6" wire width 64 $2\ldd_o[63:0] - attribute \src "libresoc.v:142708.3-142731.6" + attribute \src "libresoc.v:142504.3-142527.6" wire width 64 $2\lddata_r[63:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__byte_reverse$next[0:0]$6372 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 4 $2\oper_r__data_len$next[3:0]$6373 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 14 $2\oper_r__fn_unit$next[13:0]$6374 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 64 $2\oper_r__imm_data__data$next[63:0]$6375 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__imm_data__ok$next[0:0]$6376 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 32 $2\oper_r__insn$next[31:0]$6377 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 7 $2\oper_r__insn_type$next[6:0]$6378 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__is_32bit$next[0:0]$6379 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__is_signed$next[0:0]$6380 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 2 $2\oper_r__ldst_mode$next[1:0]$6381 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__oe__oe$next[0:0]$6382 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__oe__ok$next[0:0]$6383 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__rc__ok$next[0:0]$6384 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__rc__rc$next[0:0]$6385 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__sign_extend$next[0:0]$6386 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__zero_a$next[0:0]$6387 - attribute \src "libresoc.v:142621.3-142636.6" + attribute \src "libresoc.v:142417.3-142432.6" wire width 64 $2\src_r0$next[63:0]$6400 - attribute \src "libresoc.v:142637.3-142652.6" + attribute \src "libresoc.v:142433.3-142448.6" wire width 64 $2\src_r1$next[63:0]$6404 - attribute \src "libresoc.v:142653.3-142668.6" + attribute \src "libresoc.v:142449.3-142464.6" wire width 64 $2\src_r2$next[63:0]$6408 - attribute \src "libresoc.v:142764.3-142787.6" + attribute \src "libresoc.v:142560.3-142583.6" wire width 64 $2\stdata_r[63:0] - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire width 64 $3\oper_r__imm_data__data$next[63:0]$6388 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $3\oper_r__imm_data__ok$next[0:0]$6389 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $3\oper_r__oe__oe$next[0:0]$6390 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $3\oper_r__oe__ok$next[0:0]$6391 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $3\oper_r__rc__ok$next[0:0]$6392 - attribute \src "libresoc.v:142568.3-142610.6" + attribute \src "libresoc.v:142364.3-142406.6" wire $3\oper_r__rc__rc$next[0:0]$6393 - attribute \src "libresoc.v:142324.18-142324.124" - wire width 65 $add$libresoc.v:142324$6260_Y - attribute \src "libresoc.v:142247.19-142247.118" - wire $and$libresoc.v:142247$6180_Y - attribute \src "libresoc.v:142248.19-142248.125" - wire $and$libresoc.v:142248$6181_Y - attribute \src "libresoc.v:142249.19-142249.120" - wire $and$libresoc.v:142249$6182_Y - attribute \src "libresoc.v:142250.19-142250.125" - wire $and$libresoc.v:142250$6183_Y - attribute \src "libresoc.v:142251.19-142251.118" - wire $and$libresoc.v:142251$6184_Y - attribute \src "libresoc.v:142253.19-142253.119" - wire $and$libresoc.v:142253$6186_Y - attribute \src "libresoc.v:142254.19-142254.123" - wire $and$libresoc.v:142254$6187_Y - attribute \src "libresoc.v:142255.19-142255.123" - wire $and$libresoc.v:142255$6188_Y - attribute \src "libresoc.v:142256.19-142256.120" - wire $and$libresoc.v:142256$6189_Y - attribute \src "libresoc.v:142257.19-142257.123" - wire $and$libresoc.v:142257$6190_Y - attribute \src "libresoc.v:142258.19-142258.119" - wire $and$libresoc.v:142258$6191_Y - attribute \src "libresoc.v:142259.19-142259.123" - wire $and$libresoc.v:142259$6192_Y - attribute \src "libresoc.v:142260.19-142260.125" - wire $and$libresoc.v:142260$6193_Y - attribute \src "libresoc.v:142262.19-142262.116" - wire $and$libresoc.v:142262$6195_Y - attribute \src "libresoc.v:142264.19-142264.120" - wire $and$libresoc.v:142264$6197_Y - attribute \src "libresoc.v:142265.19-142265.123" - wire $and$libresoc.v:142265$6198_Y - attribute \src "libresoc.v:142269.19-142269.125" - wire $and$libresoc.v:142269$6202_Y - attribute \src "libresoc.v:142270.19-142270.123" - wire $and$libresoc.v:142270$6203_Y - attribute \src "libresoc.v:142275.19-142275.116" - wire $and$libresoc.v:142275$6208_Y - attribute \src "libresoc.v:142277.19-142277.116" - wire $and$libresoc.v:142277$6210_Y - attribute \src "libresoc.v:142280.19-142280.118" - wire $and$libresoc.v:142280$6213_Y - attribute \src "libresoc.v:142282.19-142282.125" - wire $and$libresoc.v:142282$6215_Y - attribute \src "libresoc.v:142285.19-142285.160" - wire width 3 $and$libresoc.v:142285$6218_Y - attribute \src "libresoc.v:142286.19-142286.122" - wire $and$libresoc.v:142286$6219_Y - attribute \src "libresoc.v:142287.19-142287.122" - wire $and$libresoc.v:142287$6220_Y - attribute \src "libresoc.v:142289.19-142289.122" - wire $and$libresoc.v:142289$6223_Y - attribute \src "libresoc.v:142301.18-142301.123" - wire $and$libresoc.v:142301$6237_Y - attribute \src "libresoc.v:142302.18-142302.123" - wire $and$libresoc.v:142302$6238_Y - attribute \src "libresoc.v:142304.18-142304.114" - wire $and$libresoc.v:142304$6240_Y - attribute \src "libresoc.v:142306.18-142306.113" - wire $and$libresoc.v:142306$6242_Y - attribute \src "libresoc.v:142309.18-142309.113" - wire $and$libresoc.v:142309$6245_Y - attribute \src "libresoc.v:142313.18-142313.113" - wire $and$libresoc.v:142313$6249_Y - attribute \src "libresoc.v:142316.18-142316.119" - wire $and$libresoc.v:142316$6252_Y - attribute \src "libresoc.v:142325.18-142325.150" - wire width 3 $and$libresoc.v:142325$6261_Y - attribute \src "libresoc.v:142327.18-142327.113" - wire width 3 $and$libresoc.v:142327$6263_Y - attribute \src "libresoc.v:142329.18-142329.113" - wire width 3 $and$libresoc.v:142329$6265_Y - attribute \src "libresoc.v:142330.18-142330.127" - wire $and$libresoc.v:142330$6266_Y - attribute \src "libresoc.v:142331.18-142331.117" - wire $and$libresoc.v:142331$6267_Y - attribute \src "libresoc.v:142336.18-142336.117" - wire $and$libresoc.v:142336$6272_Y - attribute \src "libresoc.v:142261.19-142261.127" - wire $eq$libresoc.v:142261$6194_Y - attribute \src "libresoc.v:142281.19-142281.127" - wire $eq$libresoc.v:142281$6214_Y - attribute \src "libresoc.v:142283.19-142283.127" - wire $eq$libresoc.v:142283$6216_Y - attribute \src "libresoc.v:142294.19-142294.126" - wire $eq$libresoc.v:142294$6229_Y - attribute \src "libresoc.v:142299.18-142299.127" - wire $eq$libresoc.v:142299$6235_Y - attribute \src "libresoc.v:142300.18-142300.127" - wire $eq$libresoc.v:142300$6236_Y - attribute \src "libresoc.v:142308.18-142308.126" - wire $eq$libresoc.v:142308$6244_Y - attribute \src "libresoc.v:142312.18-142312.126" - wire $eq$libresoc.v:142312$6248_Y - attribute \src "libresoc.v:142288.19-142288.110" - wire width 96 $extend$libresoc.v:142288$6221_Y - attribute \src "libresoc.v:142290.19-142290.116" - wire width 64 $extend$libresoc.v:142290$6224_Y - attribute \src "libresoc.v:142295.19-142295.102" - wire width 64 $extend$libresoc.v:142295$6230_Y - attribute \src "libresoc.v:142273.19-142273.109" - wire $not$libresoc.v:142273$6206_Y - attribute \src "libresoc.v:142278.19-142278.121" - wire $not$libresoc.v:142278$6211_Y - attribute \src "libresoc.v:142303.18-142303.112" - wire $not$libresoc.v:142303$6239_Y - attribute \src "libresoc.v:142305.18-142305.110" - wire $not$libresoc.v:142305$6241_Y - attribute \src "libresoc.v:142307.18-142307.120" - wire $not$libresoc.v:142307$6243_Y - attribute \src "libresoc.v:142311.18-142311.120" - wire $not$libresoc.v:142311$6247_Y - attribute \src "libresoc.v:142326.18-142326.143" - wire width 2 $not$libresoc.v:142326$6262_Y - attribute \src "libresoc.v:142328.18-142328.115" - wire width 3 $not$libresoc.v:142328$6264_Y - attribute \src "libresoc.v:142335.18-142335.107" - wire $not$libresoc.v:142335$6271_Y - attribute \src "libresoc.v:142337.18-142337.118" - wire $not$libresoc.v:142337$6273_Y - attribute \src "libresoc.v:142252.18-142252.124" - wire $or$libresoc.v:142252$6185_Y - attribute \src "libresoc.v:142263.18-142263.129" - wire $or$libresoc.v:142263$6196_Y - attribute \src "libresoc.v:142266.19-142266.123" - wire $or$libresoc.v:142266$6199_Y - attribute \src "libresoc.v:142267.19-142267.125" - wire $or$libresoc.v:142267$6200_Y - attribute \src "libresoc.v:142268.19-142268.125" - wire $or$libresoc.v:142268$6201_Y - attribute \src "libresoc.v:142271.19-142271.132" - wire $or$libresoc.v:142271$6204_Y - attribute \src "libresoc.v:142272.19-142272.126" - wire $or$libresoc.v:142272$6205_Y - attribute \src "libresoc.v:142274.18-142274.129" - wire $or$libresoc.v:142274$6207_Y - attribute \src "libresoc.v:142276.19-142276.125" - wire $or$libresoc.v:142276$6209_Y - attribute \src "libresoc.v:142279.19-142279.119" - wire $or$libresoc.v:142279$6212_Y - attribute \src "libresoc.v:142284.18-142284.126" - wire $or$libresoc.v:142284$6217_Y - attribute \src "libresoc.v:142292.18-142292.156" - wire width 3 $or$libresoc.v:142292$6227_Y - attribute \src "libresoc.v:142298.18-142298.126" - wire $or$libresoc.v:142298$6234_Y - attribute \src "libresoc.v:142310.18-142310.116" - wire $or$libresoc.v:142310$6246_Y - attribute \src "libresoc.v:142314.18-142314.116" - wire $or$libresoc.v:142314$6250_Y - attribute \src "libresoc.v:142315.18-142315.127" - wire width 2 $or$libresoc.v:142315$6251_Y - attribute \src "libresoc.v:142317.18-142317.118" - wire $or$libresoc.v:142317$6253_Y - attribute \src "libresoc.v:142318.18-142318.118" - wire $or$libresoc.v:142318$6254_Y - attribute \src "libresoc.v:142319.18-142319.114" - wire $or$libresoc.v:142319$6255_Y - attribute \src "libresoc.v:142332.17-142332.124" - wire $or$libresoc.v:142332$6268_Y - attribute \src "libresoc.v:142333.18-142333.132" - wire $or$libresoc.v:142333$6269_Y - attribute \src "libresoc.v:142334.18-142334.134" - wire $or$libresoc.v:142334$6270_Y - attribute \src "libresoc.v:142288.19-142288.110" - wire width 96 $pos$libresoc.v:142288$6222_Y - attribute \src "libresoc.v:142290.19-142290.116" - wire width 64 $pos$libresoc.v:142290$6225_Y - attribute \src "libresoc.v:142291.19-142291.148" - wire width 64 $pos$libresoc.v:142291$6226_Y - attribute \src "libresoc.v:142293.19-142293.206" - wire width 64 $pos$libresoc.v:142293$6228_Y - attribute \src "libresoc.v:142295.19-142295.102" - wire width 64 $pos$libresoc.v:142295$6231_Y - attribute \src "libresoc.v:142296.19-142296.120" - wire width 64 $pos$libresoc.v:142296$6232_Y - attribute \src "libresoc.v:142297.19-142297.150" - wire width 64 $pos$libresoc.v:142297$6233_Y - attribute \src "libresoc.v:142320.18-142320.107" - wire width 64 $ternary$libresoc.v:142320$6256_Y - attribute \src "libresoc.v:142321.18-142321.112" - wire width 64 $ternary$libresoc.v:142321$6257_Y - attribute \src "libresoc.v:142322.18-142322.147" - wire width 64 $ternary$libresoc.v:142322$6258_Y - attribute \src "libresoc.v:142323.18-142323.155" - wire width 64 $ternary$libresoc.v:142323$6259_Y + attribute \src "libresoc.v:142120.18-142120.124" + wire width 65 $add$libresoc.v:142120$6260_Y + attribute \src "libresoc.v:142043.19-142043.118" + wire $and$libresoc.v:142043$6180_Y + attribute \src "libresoc.v:142044.19-142044.125" + wire $and$libresoc.v:142044$6181_Y + attribute \src "libresoc.v:142045.19-142045.120" + wire $and$libresoc.v:142045$6182_Y + attribute \src "libresoc.v:142046.19-142046.125" + wire $and$libresoc.v:142046$6183_Y + attribute \src "libresoc.v:142047.19-142047.118" + wire $and$libresoc.v:142047$6184_Y + attribute \src "libresoc.v:142049.19-142049.119" + wire $and$libresoc.v:142049$6186_Y + attribute \src "libresoc.v:142050.19-142050.123" + wire $and$libresoc.v:142050$6187_Y + attribute \src "libresoc.v:142051.19-142051.123" + wire $and$libresoc.v:142051$6188_Y + attribute \src "libresoc.v:142052.19-142052.120" + wire $and$libresoc.v:142052$6189_Y + attribute \src "libresoc.v:142053.19-142053.123" + wire $and$libresoc.v:142053$6190_Y + attribute \src "libresoc.v:142054.19-142054.119" + wire $and$libresoc.v:142054$6191_Y + attribute \src "libresoc.v:142055.19-142055.123" + wire $and$libresoc.v:142055$6192_Y + attribute \src "libresoc.v:142056.19-142056.125" + wire $and$libresoc.v:142056$6193_Y + attribute \src "libresoc.v:142058.19-142058.116" + wire $and$libresoc.v:142058$6195_Y + attribute \src "libresoc.v:142060.19-142060.120" + wire $and$libresoc.v:142060$6197_Y + attribute \src "libresoc.v:142061.19-142061.123" + wire $and$libresoc.v:142061$6198_Y + attribute \src "libresoc.v:142065.19-142065.125" + wire $and$libresoc.v:142065$6202_Y + attribute \src "libresoc.v:142066.19-142066.123" + wire $and$libresoc.v:142066$6203_Y + attribute \src "libresoc.v:142071.19-142071.116" + wire $and$libresoc.v:142071$6208_Y + attribute \src "libresoc.v:142073.19-142073.116" + wire $and$libresoc.v:142073$6210_Y + attribute \src "libresoc.v:142076.19-142076.118" + wire $and$libresoc.v:142076$6213_Y + attribute \src "libresoc.v:142078.19-142078.125" + wire $and$libresoc.v:142078$6215_Y + attribute \src "libresoc.v:142081.19-142081.160" + wire width 3 $and$libresoc.v:142081$6218_Y + attribute \src "libresoc.v:142082.19-142082.122" + wire $and$libresoc.v:142082$6219_Y + attribute \src "libresoc.v:142083.19-142083.122" + wire $and$libresoc.v:142083$6220_Y + attribute \src "libresoc.v:142085.19-142085.122" + wire $and$libresoc.v:142085$6223_Y + attribute \src "libresoc.v:142097.18-142097.123" + wire $and$libresoc.v:142097$6237_Y + attribute \src "libresoc.v:142098.18-142098.123" + wire $and$libresoc.v:142098$6238_Y + attribute \src "libresoc.v:142100.18-142100.114" + wire $and$libresoc.v:142100$6240_Y + attribute \src "libresoc.v:142102.18-142102.113" + wire $and$libresoc.v:142102$6242_Y + attribute \src "libresoc.v:142105.18-142105.113" + wire $and$libresoc.v:142105$6245_Y + attribute \src "libresoc.v:142109.18-142109.113" + wire $and$libresoc.v:142109$6249_Y + attribute \src "libresoc.v:142112.18-142112.119" + wire $and$libresoc.v:142112$6252_Y + attribute \src "libresoc.v:142121.18-142121.150" + wire width 3 $and$libresoc.v:142121$6261_Y + attribute \src "libresoc.v:142123.18-142123.113" + wire width 3 $and$libresoc.v:142123$6263_Y + attribute \src "libresoc.v:142125.18-142125.113" + wire width 3 $and$libresoc.v:142125$6265_Y + attribute \src "libresoc.v:142126.18-142126.127" + wire $and$libresoc.v:142126$6266_Y + attribute \src "libresoc.v:142127.18-142127.117" + wire $and$libresoc.v:142127$6267_Y + attribute \src "libresoc.v:142132.18-142132.117" + wire $and$libresoc.v:142132$6272_Y + attribute \src "libresoc.v:142057.19-142057.127" + wire $eq$libresoc.v:142057$6194_Y + attribute \src "libresoc.v:142077.19-142077.127" + wire $eq$libresoc.v:142077$6214_Y + attribute \src "libresoc.v:142079.19-142079.127" + wire $eq$libresoc.v:142079$6216_Y + attribute \src "libresoc.v:142090.19-142090.126" + wire $eq$libresoc.v:142090$6229_Y + attribute \src "libresoc.v:142095.18-142095.127" + wire $eq$libresoc.v:142095$6235_Y + attribute \src "libresoc.v:142096.18-142096.127" + wire $eq$libresoc.v:142096$6236_Y + attribute \src "libresoc.v:142104.18-142104.126" + wire $eq$libresoc.v:142104$6244_Y + attribute \src "libresoc.v:142108.18-142108.126" + wire $eq$libresoc.v:142108$6248_Y + attribute \src "libresoc.v:142084.19-142084.110" + wire width 96 $extend$libresoc.v:142084$6221_Y + attribute \src "libresoc.v:142086.19-142086.116" + wire width 64 $extend$libresoc.v:142086$6224_Y + attribute \src "libresoc.v:142091.19-142091.102" + wire width 64 $extend$libresoc.v:142091$6230_Y + attribute \src "libresoc.v:142069.19-142069.109" + wire $not$libresoc.v:142069$6206_Y + attribute \src "libresoc.v:142074.19-142074.121" + wire $not$libresoc.v:142074$6211_Y + attribute \src "libresoc.v:142099.18-142099.112" + wire $not$libresoc.v:142099$6239_Y + attribute \src "libresoc.v:142101.18-142101.110" + wire $not$libresoc.v:142101$6241_Y + attribute \src "libresoc.v:142103.18-142103.120" + wire $not$libresoc.v:142103$6243_Y + attribute \src "libresoc.v:142107.18-142107.120" + wire $not$libresoc.v:142107$6247_Y + attribute \src "libresoc.v:142122.18-142122.143" + wire width 2 $not$libresoc.v:142122$6262_Y + attribute \src "libresoc.v:142124.18-142124.115" + wire width 3 $not$libresoc.v:142124$6264_Y + attribute \src "libresoc.v:142131.18-142131.107" + wire $not$libresoc.v:142131$6271_Y + attribute \src "libresoc.v:142133.18-142133.118" + wire $not$libresoc.v:142133$6273_Y + attribute \src "libresoc.v:142048.18-142048.124" + wire $or$libresoc.v:142048$6185_Y + attribute \src "libresoc.v:142059.18-142059.129" + wire $or$libresoc.v:142059$6196_Y + attribute \src "libresoc.v:142062.19-142062.123" + wire $or$libresoc.v:142062$6199_Y + attribute \src "libresoc.v:142063.19-142063.125" + wire $or$libresoc.v:142063$6200_Y + attribute \src "libresoc.v:142064.19-142064.125" + wire $or$libresoc.v:142064$6201_Y + attribute \src "libresoc.v:142067.19-142067.132" + wire $or$libresoc.v:142067$6204_Y + attribute \src "libresoc.v:142068.19-142068.126" + wire $or$libresoc.v:142068$6205_Y + attribute \src "libresoc.v:142070.18-142070.129" + wire $or$libresoc.v:142070$6207_Y + attribute \src "libresoc.v:142072.19-142072.125" + wire $or$libresoc.v:142072$6209_Y + attribute \src "libresoc.v:142075.19-142075.119" + wire $or$libresoc.v:142075$6212_Y + attribute \src "libresoc.v:142080.18-142080.126" + wire $or$libresoc.v:142080$6217_Y + attribute \src "libresoc.v:142088.18-142088.156" + wire width 3 $or$libresoc.v:142088$6227_Y + attribute \src "libresoc.v:142094.18-142094.126" + wire $or$libresoc.v:142094$6234_Y + attribute \src "libresoc.v:142106.18-142106.116" + wire $or$libresoc.v:142106$6246_Y + attribute \src "libresoc.v:142110.18-142110.116" + wire $or$libresoc.v:142110$6250_Y + attribute \src "libresoc.v:142111.18-142111.127" + wire width 2 $or$libresoc.v:142111$6251_Y + attribute \src "libresoc.v:142113.18-142113.118" + wire $or$libresoc.v:142113$6253_Y + attribute \src "libresoc.v:142114.18-142114.118" + wire $or$libresoc.v:142114$6254_Y + attribute \src "libresoc.v:142115.18-142115.114" + wire $or$libresoc.v:142115$6255_Y + attribute \src "libresoc.v:142128.17-142128.124" + wire $or$libresoc.v:142128$6268_Y + attribute \src "libresoc.v:142129.18-142129.132" + wire $or$libresoc.v:142129$6269_Y + attribute \src "libresoc.v:142130.18-142130.134" + wire $or$libresoc.v:142130$6270_Y + attribute \src "libresoc.v:142084.19-142084.110" + wire width 96 $pos$libresoc.v:142084$6222_Y + attribute \src "libresoc.v:142086.19-142086.116" + wire width 64 $pos$libresoc.v:142086$6225_Y + attribute \src "libresoc.v:142087.19-142087.148" + wire width 64 $pos$libresoc.v:142087$6226_Y + attribute \src "libresoc.v:142089.19-142089.206" + wire width 64 $pos$libresoc.v:142089$6228_Y + attribute \src "libresoc.v:142091.19-142091.102" + wire width 64 $pos$libresoc.v:142091$6231_Y + attribute \src "libresoc.v:142092.19-142092.120" + wire width 64 $pos$libresoc.v:142092$6232_Y + attribute \src "libresoc.v:142093.19-142093.150" + wire width 64 $pos$libresoc.v:142093$6233_Y + attribute \src "libresoc.v:142116.18-142116.107" + wire width 64 $ternary$libresoc.v:142116$6256_Y + attribute \src "libresoc.v:142117.18-142117.112" + wire width 64 $ternary$libresoc.v:142117$6257_Y + attribute \src "libresoc.v:142118.18-142118.147" + wire width 64 $ternary$libresoc.v:142118$6258_Y + attribute \src "libresoc.v:142119.18-142119.155" + wire width 64 $ternary$libresoc.v:142119$6259_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" @@ -226372,9 +226168,9 @@ module \ldst0 wire \alu_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" wire \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 3 \cu_ad__go_i @@ -226432,7 +226228,7 @@ module \ldst0 wire \exc_$signal$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$185 - attribute \src "libresoc.v:141497.7-141497.15" + attribute \src "libresoc.v:141293.7-141293.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" wire \ld_o @@ -226907,7 +226703,7 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \wri_l_s_wri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" - cell $add $add$libresoc.v:142324$6260 + cell $add $add$libresoc.v:142120$6260 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -226915,10 +226711,10 @@ module \ldst0 parameter \Y_WIDTH 65 connect \A \src1_or_z connect \B \src2_or_imm - connect \Y $add$libresoc.v:142324$6260_Y + connect \Y $add$libresoc.v:142120$6260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $and $and$libresoc.v:142247$6180 + cell $and $and$libresoc.v:142043$6180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226926,10 +226722,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \$98 - connect \Y $and$libresoc.v:142247$6180_Y + connect \Y $and$libresoc.v:142043$6180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:142248$6181 + cell $and $and$libresoc.v:142044$6181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226937,10 +226733,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \adr_l_q_adr - connect \Y $and$libresoc.v:142248$6181_Y + connect \Y $and$libresoc.v:142044$6181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:142249$6182 + cell $and $and$libresoc.v:142045$6182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226948,10 +226744,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$102 connect \B \cu_busy_o - connect \Y $and$libresoc.v:142249$6182_Y + connect \Y $and$libresoc.v:142045$6182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:142250$6183 + cell $and $and$libresoc.v:142046$6183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226959,10 +226755,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \sto_l_q_sto connect \B \cu_busy_o - connect \Y $and$libresoc.v:142250$6183_Y + connect \Y $and$libresoc.v:142046$6183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:142251$6184 + cell $and $and$libresoc.v:142047$6184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226970,10 +226766,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$106 connect \B \rd_done - connect \Y $and$libresoc.v:142251$6184_Y + connect \Y $and$libresoc.v:142047$6184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:142253$6186 + cell $and $and$libresoc.v:142049$6186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226981,10 +226777,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$108 connect \B \op_is_st - connect \Y $and$libresoc.v:142253$6186_Y + connect \Y $and$libresoc.v:142049$6186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $and $and$libresoc.v:142254$6187 + cell $and $and$libresoc.v:142050$6187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226992,10 +226788,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$110 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:142254$6187_Y + connect \Y $and$libresoc.v:142050$6187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:142255$6188 + cell $and $and$libresoc.v:142051$6188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227003,10 +226799,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd_done connect \B \wri_l_q_wri - connect \Y $and$libresoc.v:142255$6188_Y + connect \Y $and$libresoc.v:142051$6188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:142256$6189 + cell $and $and$libresoc.v:142052$6189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227014,10 +226810,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$114 connect \B \cu_busy_o - connect \Y $and$libresoc.v:142256$6189_Y + connect \Y $and$libresoc.v:142052$6189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:142257$6190 + cell $and $and$libresoc.v:142053$6190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227025,10 +226821,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$116 connect \B \lod_l_qn_lod - connect \Y $and$libresoc.v:142257$6190_Y + connect \Y $and$libresoc.v:142053$6190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:142258$6191 + cell $and $and$libresoc.v:142054$6191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227036,10 +226832,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$118 connect \B \op_is_ld - connect \Y $and$libresoc.v:142258$6191_Y + connect \Y $and$libresoc.v:142054$6191_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:142259$6192 + cell $and $and$libresoc.v:142055$6192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227047,10 +226843,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$120 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:142259$6192_Y + connect \Y $and$libresoc.v:142055$6192_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:142260$6193 + cell $and $and$libresoc.v:142056$6193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227058,10 +226854,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \upd_l_q_upd connect \B \cu_busy_o - connect \Y $and$libresoc.v:142260$6193_Y + connect \Y $and$libresoc.v:142056$6193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:142262$6195 + cell $and $and$libresoc.v:142058$6195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227069,10 +226865,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$124 connect \B \$126 - connect \Y $and$libresoc.v:142262$6195_Y + connect \Y $and$libresoc.v:142058$6195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:142264$6197 + cell $and $and$libresoc.v:142060$6197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227080,10 +226876,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$128 connect \B \alu_valid - connect \Y $and$libresoc.v:142264$6197_Y + connect \Y $and$libresoc.v:142060$6197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:142265$6198 + cell $and $and$libresoc.v:142061$6198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227091,10 +226887,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$130 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:142265$6198_Y + connect \Y $and$libresoc.v:142061$6198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:142269$6202 + cell $and $and$libresoc.v:142065$6202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227102,10 +226898,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rst_l_q_rst connect \B \cu_busy_o - connect \Y $and$libresoc.v:142269$6202_Y + connect \Y $and$libresoc.v:142065$6202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:142270$6203 + cell $and $and$libresoc.v:142066$6203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227113,10 +226909,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$140 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:142270$6203_Y + connect \Y $and$libresoc.v:142066$6203_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:142275$6208 + cell $and $and$libresoc.v:142071$6208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227124,10 +226920,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$142 connect \B \$144 - connect \Y $and$libresoc.v:142275$6208_Y + connect \Y $and$libresoc.v:142071$6208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $and $and$libresoc.v:142277$6210 + cell $and $and$libresoc.v:142073$6210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227135,10 +226931,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$150 connect \B \$152 - connect \Y $and$libresoc.v:142277$6210_Y + connect \Y $and$libresoc.v:142073$6210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $and $and$libresoc.v:142280$6213 + cell $and $and$libresoc.v:142076$6213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227146,10 +226942,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$158 - connect \Y $and$libresoc.v:142280$6213_Y + connect \Y $and$libresoc.v:142076$6213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - cell $and $and$libresoc.v:142282$6215 + cell $and $and$libresoc.v:142078$6215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227157,10 +226953,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$162 connect \B \cu_wr__go_i [1] - connect \Y $and$libresoc.v:142282$6215_Y + connect \Y $and$libresoc.v:142078$6215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" - cell $and $and$libresoc.v:142285$6218 + cell $and $and$libresoc.v:142081$6218 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227168,10 +226964,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } connect \B { 1'0 \$167 \op_is_ld } - connect \Y $and$libresoc.v:142285$6218_Y + connect \Y $and$libresoc.v:142081$6218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - cell $and $and$libresoc.v:142286$6219 + cell $and $and$libresoc.v:142082$6219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227179,10 +226975,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_busy_o - connect \Y $and$libresoc.v:142286$6219_Y + connect \Y $and$libresoc.v:142082$6219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" - cell $and $and$libresoc.v:142287$6220 + cell $and $and$libresoc.v:142083$6220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227190,10 +226986,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_busy_o - connect \Y $and$libresoc.v:142287$6220_Y + connect \Y $and$libresoc.v:142083$6220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" - cell $and $and$libresoc.v:142289$6223 + cell $and $and$libresoc.v:142085$6223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227201,10 +226997,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \lsd_l_q_lsd - connect \Y $and$libresoc.v:142289$6223_Y + connect \Y $and$libresoc.v:142085$6223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - cell $and $and$libresoc.v:142301$6237 + cell $and $and$libresoc.v:142097$6237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227212,10 +227008,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_ad__go_i - connect \Y $and$libresoc.v:142301$6237_Y + connect \Y $and$libresoc.v:142097$6237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" - cell $and $and$libresoc.v:142302$6238 + cell $and $and$libresoc.v:142098$6238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227223,10 +227019,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_st__go_i - connect \Y $and$libresoc.v:142302$6238_Y + connect \Y $and$libresoc.v:142098$6238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:142304$6240 + cell $and $and$libresoc.v:142100$6240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227234,10 +227030,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \$30 - connect \Y $and$libresoc.v:142304$6240_Y + connect \Y $and$libresoc.v:142100$6240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:142306$6242 + cell $and $and$libresoc.v:142102$6242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227245,10 +227041,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $and$libresoc.v:142306$6242_Y + connect \Y $and$libresoc.v:142102$6242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:142309$6245 + cell $and $and$libresoc.v:142105$6245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227256,10 +227052,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$41 - connect \Y $and$libresoc.v:142309$6245_Y + connect \Y $and$libresoc.v:142105$6245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:142313$6249 + cell $and $and$libresoc.v:142109$6249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227267,10 +227063,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \$49 - connect \Y $and$libresoc.v:142313$6249_Y + connect \Y $and$libresoc.v:142109$6249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $and $and$libresoc.v:142316$6252 + cell $and $and$libresoc.v:142112$6252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227278,10 +227074,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \addr_ok connect \B \op_is_st - connect \Y $and$libresoc.v:142316$6252_Y + connect \Y $and$libresoc.v:142112$6252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:142325$6261 + cell $and $and$libresoc.v:142121$6261 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227289,10 +227085,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:142325$6261_Y + connect \Y $and$libresoc.v:142121$6261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:142327$6263 + cell $and $and$libresoc.v:142123$6263 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227300,10 +227096,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:142327$6263_Y + connect \Y $and$libresoc.v:142123$6263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:142329$6265 + cell $and $and$libresoc.v:142125$6265 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227311,10 +227107,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$80 connect \B \$82 - connect \Y $and$libresoc.v:142329$6265_Y + connect \Y $and$libresoc.v:142125$6265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:142330$6266 + cell $and $and$libresoc.v:142126$6266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227322,10 +227118,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \src_l_q_src [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:142330$6266_Y + connect \Y $and$libresoc.v:142126$6266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:142331$6267 + cell $and $and$libresoc.v:142127$6267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227333,10 +227129,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$86 connect \B \op_is_st - connect \Y $and$libresoc.v:142331$6267_Y + connect \Y $and$libresoc.v:142127$6267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $and$libresoc.v:142336$6272 + cell $and $and$libresoc.v:142132$6272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227344,10 +227140,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$92 - connect \Y $and$libresoc.v:142336$6272_Y + connect \Y $and$libresoc.v:142132$6272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:142261$6194 + cell $eq $eq$libresoc.v:142057$6194 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227355,10 +227151,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:142261$6194_Y + connect \Y $eq$libresoc.v:142057$6194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:142281$6214 + cell $eq $eq$libresoc.v:142077$6214 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227366,10 +227162,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:142281$6214_Y + connect \Y $eq$libresoc.v:142077$6214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:142283$6216 + cell $eq $eq$libresoc.v:142079$6216 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227377,10 +227173,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:142283$6216_Y + connect \Y $eq$libresoc.v:142079$6216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - cell $eq $eq$libresoc.v:142294$6229 + cell $eq $eq$libresoc.v:142090$6229 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -227388,10 +227184,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:142294$6229_Y + connect \Y $eq$libresoc.v:142090$6229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $eq$libresoc.v:142299$6235 + cell $eq $eq$libresoc.v:142095$6235 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227399,10 +227195,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100110 - connect \Y $eq$libresoc.v:142299$6235_Y + connect \Y $eq$libresoc.v:142095$6235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:142300$6236 + cell $eq $eq$libresoc.v:142096$6236 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227410,10 +227206,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100101 - connect \Y $eq$libresoc.v:142300$6236_Y + connect \Y $eq$libresoc.v:142096$6236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:142308$6244 + cell $eq $eq$libresoc.v:142104$6244 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227421,10 +227217,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:142308$6244_Y + connect \Y $eq$libresoc.v:142104$6244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:142312$6248 + cell $eq $eq$libresoc.v:142108$6248 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227432,114 +227228,114 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:142312$6248_Y + connect \Y $eq$libresoc.v:142108$6248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $extend$libresoc.v:142288$6221 + cell $pos $extend$libresoc.v:142084$6221 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 96 connect \A \addr_r - connect \Y $extend$libresoc.v:142288$6221_Y + connect \Y $extend$libresoc.v:142084$6221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:142290$6224 + cell $pos $extend$libresoc.v:142086$6224 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \ldst_port0_ld_data_o [7:0] - connect \Y $extend$libresoc.v:142290$6224_Y + connect \Y $extend$libresoc.v:142086$6224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:142295$6230 + cell $pos $extend$libresoc.v:142091$6230 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \src_r2 [7:0] - connect \Y $extend$libresoc.v:142295$6230_Y + connect \Y $extend$libresoc.v:142091$6230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $not $not$libresoc.v:142273$6206 + cell $not $not$libresoc.v:142069$6206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$147 - connect \Y $not$libresoc.v:142273$6206_Y + connect \Y $not$libresoc.v:142069$6206_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $not $not$libresoc.v:142278$6211 + cell $not $not$libresoc.v:142074$6211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:142278$6211_Y + connect \Y $not$libresoc.v:142074$6211_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:142303$6239 + cell $not $not$libresoc.v:142099$6239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid - connect \Y $not$libresoc.v:142303$6239_Y + connect \Y $not$libresoc.v:142099$6239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:142305$6241 + cell $not $not$libresoc.v:142101$6241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rda_any - connect \Y $not$libresoc.v:142305$6241_Y + connect \Y $not$libresoc.v:142101$6241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:142307$6243 + cell $not $not$libresoc.v:142103$6243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:142307$6243_Y + connect \Y $not$libresoc.v:142103$6243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:142311$6247 + cell $not $not$libresoc.v:142107$6247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:142311$6247_Y + connect \Y $not$libresoc.v:142107$6247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:142326$6262 + cell $not $not$libresoc.v:142122$6262 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $not$libresoc.v:142326$6262_Y + connect \Y $not$libresoc.v:142122$6262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:142328$6264 + cell $not $not$libresoc.v:142124$6264 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:142328$6264_Y + connect \Y $not$libresoc.v:142124$6264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $not $not$libresoc.v:142335$6271 + cell $not $not$libresoc.v:142131$6271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$93 - connect \Y $not$libresoc.v:142335$6271_Y + connect \Y $not$libresoc.v:142131$6271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $not $not$libresoc.v:142337$6273 + cell $not $not$libresoc.v:142133$6273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [2] - connect \Y $not$libresoc.v:142337$6273_Y + connect \Y $not$libresoc.v:142133$6273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $or$libresoc.v:142252$6185 + cell $or $or$libresoc.v:142048$6185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227547,10 +227343,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_done_o connect \B \cu_go_die_i - connect \Y $or$libresoc.v:142252$6185_Y + connect \Y $or$libresoc.v:142048$6185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $or$libresoc.v:142263$6196 + cell $or $or$libresoc.v:142059$6196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227558,10 +227354,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:142263$6196_Y + connect \Y $or$libresoc.v:142059$6196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:142266$6199 + cell $or $or$libresoc.v:142062$6199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227569,10 +227365,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \p_st_go - connect \Y $or$libresoc.v:142266$6199_Y + connect \Y $or$libresoc.v:142062$6199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:142267$6200 + cell $or $or$libresoc.v:142063$6200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227580,10 +227376,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$134 connect \B \cu_wr__go_i [0] - connect \Y $or$libresoc.v:142267$6200_Y + connect \Y $or$libresoc.v:142063$6200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:142268$6201 + cell $or $or$libresoc.v:142064$6201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227591,10 +227387,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$136 connect \B \cu_wr__go_i [1] - connect \Y $or$libresoc.v:142268$6201_Y + connect \Y $or$libresoc.v:142064$6201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:142271$6204 + cell $or $or$libresoc.v:142067$6204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227602,10 +227398,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o connect \B \cu_wr__rel_o [0] - connect \Y $or$libresoc.v:142271$6204_Y + connect \Y $or$libresoc.v:142067$6204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:142272$6205 + cell $or $or$libresoc.v:142068$6205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227613,10 +227409,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$145 connect \B \cu_wr__rel_o [1] - connect \Y $or$libresoc.v:142272$6205_Y + connect \Y $or$libresoc.v:142068$6205_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $or$libresoc.v:142274$6207 + cell $or $or$libresoc.v:142070$6207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227624,10 +227420,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:142274$6207_Y + connect \Y $or$libresoc.v:142070$6207_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $or $or$libresoc.v:142276$6209 + cell $or $or$libresoc.v:142072$6209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227635,10 +227431,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \lod_l_qn_lod connect \B \op_is_st - connect \Y $or$libresoc.v:142276$6209_Y + connect \Y $or$libresoc.v:142072$6209_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $or $or$libresoc.v:142279$6212 + cell $or $or$libresoc.v:142075$6212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227646,10 +227442,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$156 connect \B \op_is_ld - connect \Y $or$libresoc.v:142279$6212_Y + connect \Y $or$libresoc.v:142075$6212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $or$libresoc.v:142284$6217 + cell $or $or$libresoc.v:142080$6217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227657,10 +227453,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:142284$6217_Y + connect \Y $or$libresoc.v:142080$6217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $or$libresoc.v:142292$6227 + cell $or $or$libresoc.v:142088$6227 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227668,10 +227464,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:142292$6227_Y + connect \Y $or$libresoc.v:142088$6227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - cell $or $or$libresoc.v:142298$6234 + cell $or $or$libresoc.v:142094$6234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227679,10 +227475,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_ad__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:142298$6234_Y + connect \Y $or$libresoc.v:142094$6234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:142310$6246 + cell $or $or$libresoc.v:142106$6246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227690,10 +227486,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$43 - connect \Y $or$libresoc.v:142310$6246_Y + connect \Y $or$libresoc.v:142106$6246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:142314$6250 + cell $or $or$libresoc.v:142110$6250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227701,10 +227497,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$51 - connect \Y $or$libresoc.v:142314$6250_Y + connect \Y $or$libresoc.v:142110$6250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" - cell $or $or$libresoc.v:142315$6251 + cell $or $or$libresoc.v:142111$6251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227712,10 +227508,10 @@ module \ldst0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B { \$45 \$53 } - connect \Y $or$libresoc.v:142315$6251_Y + connect \Y $or$libresoc.v:142111$6251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - cell $or $or$libresoc.v:142317$6253 + cell $or $or$libresoc.v:142113$6253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227723,10 +227519,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:142317$6253_Y + connect \Y $or$libresoc.v:142113$6253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:142318$6254 + cell $or $or$libresoc.v:142114$6254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227734,10 +227530,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:142318$6254_Y + connect \Y $or$libresoc.v:142114$6254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:142319$6255 + cell $or $or$libresoc.v:142115$6255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227745,10 +227541,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$61 connect \B \ld_ok - connect \Y $or$libresoc.v:142319$6255_Y + connect \Y $or$libresoc.v:142115$6255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $or$libresoc.v:142332$6268 + cell $or $or$libresoc.v:142128$6268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227756,10 +227552,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:142332$6268_Y + connect \Y $or$libresoc.v:142128$6268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - cell $or $or$libresoc.v:142333$6269 + cell $or $or$libresoc.v:142129$6269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227767,10 +227563,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__go_i [0] connect \B \cu_rd__go_i [1] - connect \Y $or$libresoc.v:142333$6269_Y + connect \Y $or$libresoc.v:142129$6269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $or $or$libresoc.v:142334$6270 + cell $or $or$libresoc.v:142130$6270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227778,98 +227574,98 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [0] connect \B \cu_rd__rel_o [1] - connect \Y $or$libresoc.v:142334$6270_Y + connect \Y $or$libresoc.v:142130$6270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $pos$libresoc.v:142288$6222 + cell $pos $pos$libresoc.v:142084$6222 parameter \A_SIGNED 0 parameter \A_WIDTH 96 parameter \Y_WIDTH 96 - connect \A $extend$libresoc.v:142288$6221_Y - connect \Y $pos$libresoc.v:142288$6222_Y + connect \A $extend$libresoc.v:142084$6221_Y + connect \Y $pos$libresoc.v:142084$6222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:142290$6225 + cell $pos $pos$libresoc.v:142086$6225 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:142290$6224_Y - connect \Y $pos$libresoc.v:142290$6225_Y + connect \A $extend$libresoc.v:142086$6224_Y + connect \Y $pos$libresoc.v:142086$6225_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:142291$6226 + cell $pos $pos$libresoc.v:142087$6226 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$libresoc.v:142291$6226_Y + connect \Y $pos$libresoc.v:142087$6226_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:142293$6228 + cell $pos $pos$libresoc.v:142089$6228 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$libresoc.v:142293$6228_Y + connect \Y $pos$libresoc.v:142089$6228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:142295$6231 + cell $pos $pos$libresoc.v:142091$6231 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:142295$6230_Y - connect \Y $pos$libresoc.v:142295$6231_Y + connect \A $extend$libresoc.v:142091$6230_Y + connect \Y $pos$libresoc.v:142091$6231_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:142296$6232 + cell $pos $pos$libresoc.v:142092$6232 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$libresoc.v:142296$6232_Y + connect \Y $pos$libresoc.v:142092$6232_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:142297$6233 + cell $pos $pos$libresoc.v:142093$6233 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$libresoc.v:142297$6233_Y + connect \Y $pos$libresoc.v:142093$6233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:142320$6256 + cell $mux $ternary$libresoc.v:142116$6256 parameter \WIDTH 64 connect \A \ldo_r connect \B \ldd_o connect \S \ld_ok - connect \Y $ternary$libresoc.v:142320$6256_Y + connect \Y $ternary$libresoc.v:142116$6256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:142321$6257 + cell $mux $ternary$libresoc.v:142117$6257 parameter \WIDTH 64 connect \A \ea_r connect \B \alu_o connect \S \alu_l_q_alu - connect \Y $ternary$libresoc.v:142321$6257_Y + connect \Y $ternary$libresoc.v:142117$6257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" - cell $mux $ternary$libresoc.v:142322$6258 + cell $mux $ternary$libresoc.v:142118$6258 parameter \WIDTH 64 connect \A \src_r0 connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $ternary$libresoc.v:142322$6258_Y + connect \Y $ternary$libresoc.v:142118$6258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" - cell $mux $ternary$libresoc.v:142323$6259 + cell $mux $ternary$libresoc.v:142119$6259 parameter \WIDTH 64 connect \A \src_r1 connect \B \oper_r__imm_data__data connect \S \oper_r__imm_data__ok - connect \Y $ternary$libresoc.v:142323$6259_Y + connect \Y $ternary$libresoc.v:142119$6259_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:142408.9-142414.4" + attribute \src "libresoc.v:142204.9-142210.4" cell \adr_l \adr_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -227878,7 +227674,7 @@ module \ldst0 connect \s_adr \adr_l_s_adr end attribute \module_not_derived 1 - attribute \src "libresoc.v:142415.15-142421.4" + attribute \src "libresoc.v:142211.15-142217.4" cell \alu_l$128 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -227887,7 +227683,7 @@ module \ldst0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:142422.9-142428.4" + attribute \src "libresoc.v:142218.9-142224.4" cell \lod_l \lod_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -227896,7 +227692,7 @@ module \ldst0 connect \s_lod \lod_l_s_lod end attribute \module_not_derived 1 - attribute \src "libresoc.v:142429.9-142435.4" + attribute \src "libresoc.v:142225.9-142231.4" cell \lsd_l \lsd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -227905,7 +227701,7 @@ module \ldst0 connect \s_lsd \lsd_l_s_lsd end attribute \module_not_derived 1 - attribute \src "libresoc.v:142436.15-142442.4" + attribute \src "libresoc.v:142232.15-142238.4" cell \opc_l$126 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -227914,7 +227710,7 @@ module \ldst0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:142443.15-142449.4" + attribute \src "libresoc.v:142239.15-142245.4" cell \rst_l$129 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -227923,7 +227719,7 @@ module \ldst0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:142450.15-142456.4" + attribute \src "libresoc.v:142246.15-142252.4" cell \src_l$127 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -227932,7 +227728,7 @@ module \ldst0 connect \s_src \src_l_s_src end attribute \module_not_derived 1 - attribute \src "libresoc.v:142457.9-142463.4" + attribute \src "libresoc.v:142253.9-142259.4" cell \sto_l \sto_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -227941,7 +227737,7 @@ module \ldst0 connect \s_sto \sto_l_s_sto end attribute \module_not_derived 1 - attribute \src "libresoc.v:142464.9-142470.4" + attribute \src "libresoc.v:142260.9-142266.4" cell \upd_l \upd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -227950,7 +227746,7 @@ module \ldst0 connect \s_upd \upd_l_s_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:142471.9-142477.4" + attribute \src "libresoc.v:142267.9-142273.4" cell \wri_l \wri_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -227958,547 +227754,547 @@ module \ldst0 connect \r_wri \wri_l_r_wri connect \s_wri \wri_l_s_wri end - attribute \src "libresoc.v:141497.7-141497.20" - process $proc$libresoc.v:141497$6422 + attribute \src "libresoc.v:141293.7-141293.20" + process $proc$libresoc.v:141293$6422 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141693.7-141693.25" - process $proc$libresoc.v:141693$6423 + attribute \src "libresoc.v:141489.7-141489.25" + process $proc$libresoc.v:141489$6423 assign { } { } assign $1\adr_l_r_adr[0:0] 1'1 sync always sync init update \adr_l_r_adr $1\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:141707.7-141707.20" - process $proc$libresoc.v:141707$6424 + attribute \src "libresoc.v:141503.7-141503.20" + process $proc$libresoc.v:141503$6424 assign { } { } assign $1\alu_ok[0:0] 1'0 sync always sync init update \alu_ok $1\alu_ok[0:0] end - attribute \src "libresoc.v:141753.14-141753.41" - process $proc$libresoc.v:141753$6425 + attribute \src "libresoc.v:141549.14-141549.41" + process $proc$libresoc.v:141549$6425 assign { } { } assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ea_r $1\ea_r[63:0] end - attribute \src "libresoc.v:141783.14-141783.42" - process $proc$libresoc.v:141783$6426 + attribute \src "libresoc.v:141579.14-141579.42" + process $proc$libresoc.v:141579$6426 assign { } { } assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldo_r $1\ldo_r[63:0] end - attribute \src "libresoc.v:141788.14-141788.62" - process $proc$libresoc.v:141788$6427 + attribute \src "libresoc.v:141584.14-141584.62" + process $proc$libresoc.v:141584$6427 assign { } { } assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:141793.7-141793.34" - process $proc$libresoc.v:141793$6428 + attribute \src "libresoc.v:141589.7-141589.34" + process $proc$libresoc.v:141589$6428 assign { } { } assign $1\ldst_port0_addr_i_ok[0:0] 1'0 sync always sync init update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:141842.7-141842.25" - process $proc$libresoc.v:141842$6429 + attribute \src "libresoc.v:141638.7-141638.25" + process $proc$libresoc.v:141638$6429 assign { } { } assign $1\lsd_l_r_lsd[0:0] 1'1 sync always sync init update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:141856.7-141856.25" - process $proc$libresoc.v:141856$6430 + attribute \src "libresoc.v:141652.7-141652.25" + process $proc$libresoc.v:141652$6430 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:141860.7-141860.25" - process $proc$libresoc.v:141860$6431 + attribute \src "libresoc.v:141656.7-141656.25" + process $proc$libresoc.v:141656$6431 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:141991.7-141991.34" - process $proc$libresoc.v:141991$6432 + attribute \src "libresoc.v:141787.7-141787.34" + process $proc$libresoc.v:141787$6432 assign { } { } assign $1\oper_r__byte_reverse[0:0] 1'0 sync always sync init update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:141995.13-141995.36" - process $proc$libresoc.v:141995$6433 + attribute \src "libresoc.v:141791.13-141791.36" + process $proc$libresoc.v:141791$6433 assign { } { } assign $1\oper_r__data_len[3:0] 4'0000 sync always sync init update \oper_r__data_len $1\oper_r__data_len[3:0] end - attribute \src "libresoc.v:142014.14-142014.40" - process $proc$libresoc.v:142014$6434 + attribute \src "libresoc.v:141810.14-141810.40" + process $proc$libresoc.v:141810$6434 assign { } { } assign $1\oper_r__fn_unit[13:0] 14'00000000000000 sync always sync init update \oper_r__fn_unit $1\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:142018.14-142018.59" - process $proc$libresoc.v:142018$6435 + attribute \src "libresoc.v:141814.14-141814.59" + process $proc$libresoc.v:141814$6435 assign { } { } assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:142022.7-142022.34" - process $proc$libresoc.v:142022$6436 + attribute \src "libresoc.v:141818.7-141818.34" + process $proc$libresoc.v:141818$6436 assign { } { } assign $1\oper_r__imm_data__ok[0:0] 1'0 sync always sync init update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:142026.14-142026.34" - process $proc$libresoc.v:142026$6437 + attribute \src "libresoc.v:141822.14-141822.34" + process $proc$libresoc.v:141822$6437 assign { } { } assign $1\oper_r__insn[31:0] 0 sync always sync init update \oper_r__insn $1\oper_r__insn[31:0] end - attribute \src "libresoc.v:142105.13-142105.38" - process $proc$libresoc.v:142105$6438 + attribute \src "libresoc.v:141901.13-141901.38" + process $proc$libresoc.v:141901$6438 assign { } { } assign $1\oper_r__insn_type[6:0] 7'0000000 sync always sync init update \oper_r__insn_type $1\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:142109.7-142109.30" - process $proc$libresoc.v:142109$6439 + attribute \src "libresoc.v:141905.7-141905.30" + process $proc$libresoc.v:141905$6439 assign { } { } assign $1\oper_r__is_32bit[0:0] 1'0 sync always sync init update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:142113.7-142113.31" - process $proc$libresoc.v:142113$6440 + attribute \src "libresoc.v:141909.7-141909.31" + process $proc$libresoc.v:141909$6440 assign { } { } assign $1\oper_r__is_signed[0:0] 1'0 sync always sync init update \oper_r__is_signed $1\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:142122.13-142122.37" - process $proc$libresoc.v:142122$6441 + attribute \src "libresoc.v:141918.13-141918.37" + process $proc$libresoc.v:141918$6441 assign { } { } assign $1\oper_r__ldst_mode[1:0] 2'00 sync always sync init update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:142126.7-142126.28" - process $proc$libresoc.v:142126$6442 + attribute \src "libresoc.v:141922.7-141922.28" + process $proc$libresoc.v:141922$6442 assign { } { } assign $1\oper_r__oe__oe[0:0] 1'0 sync always sync init update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:142130.7-142130.28" - process $proc$libresoc.v:142130$6443 + attribute \src "libresoc.v:141926.7-141926.28" + process $proc$libresoc.v:141926$6443 assign { } { } assign $1\oper_r__oe__ok[0:0] 1'0 sync always sync init update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:142134.7-142134.28" - process $proc$libresoc.v:142134$6444 + attribute \src "libresoc.v:141930.7-141930.28" + process $proc$libresoc.v:141930$6444 assign { } { } assign $1\oper_r__rc__ok[0:0] 1'0 sync always sync init update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:142138.7-142138.28" - process $proc$libresoc.v:142138$6445 + attribute \src "libresoc.v:141934.7-141934.28" + process $proc$libresoc.v:141934$6445 assign { } { } assign $1\oper_r__rc__rc[0:0] 1'0 sync always sync init update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:142142.7-142142.33" - process $proc$libresoc.v:142142$6446 + attribute \src "libresoc.v:141938.7-141938.33" + process $proc$libresoc.v:141938$6446 assign { } { } assign $1\oper_r__sign_extend[0:0] 1'0 sync always sync init update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:142146.7-142146.28" - process $proc$libresoc.v:142146$6447 + attribute \src "libresoc.v:141942.7-141942.28" + process $proc$libresoc.v:141942$6447 assign { } { } assign $1\oper_r__zero_a[0:0] 1'0 sync always sync init update \oper_r__zero_a $1\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:142150.7-142150.21" - process $proc$libresoc.v:142150$6448 + attribute \src "libresoc.v:141946.7-141946.21" + process $proc$libresoc.v:141946$6448 assign { } { } assign $1\p_st_go[0:0] 1'0 sync always sync init update \p_st_go $1\p_st_go[0:0] end - attribute \src "libresoc.v:142192.13-142192.31" - process $proc$libresoc.v:142192$6449 + attribute \src "libresoc.v:141988.13-141988.31" + process $proc$libresoc.v:141988$6449 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:142196.13-142196.31" - process $proc$libresoc.v:142196$6450 + attribute \src "libresoc.v:141992.13-141992.31" + process $proc$libresoc.v:141992$6450 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:142200.14-142200.43" - process $proc$libresoc.v:142200$6451 + attribute \src "libresoc.v:141996.14-141996.43" + process $proc$libresoc.v:141996$6451 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:142204.14-142204.43" - process $proc$libresoc.v:142204$6452 + attribute \src "libresoc.v:142000.14-142000.43" + process $proc$libresoc.v:142000$6452 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:142208.14-142208.43" - process $proc$libresoc.v:142208$6453 + attribute \src "libresoc.v:142004.14-142004.43" + process $proc$libresoc.v:142004$6453 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:142218.7-142218.25" - process $proc$libresoc.v:142218$6454 + attribute \src "libresoc.v:142014.7-142014.25" + process $proc$libresoc.v:142014$6454 assign { } { } assign $1\sto_l_r_sto[0:0] 1'1 sync always sync init update \sto_l_r_sto $1\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:142228.7-142228.25" - process $proc$libresoc.v:142228$6455 + attribute \src "libresoc.v:142024.7-142024.25" + process $proc$libresoc.v:142024$6455 assign { } { } assign $1\upd_l_r_upd[0:0] 1'1 sync always sync init update \upd_l_r_upd $1\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:142232.7-142232.25" - process $proc$libresoc.v:142232$6456 + attribute \src "libresoc.v:142028.7-142028.25" + process $proc$libresoc.v:142028$6456 assign { } { } assign $1\upd_l_s_upd[0:0] 1'0 sync always sync init update \upd_l_s_upd $1\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:142242.7-142242.25" - process $proc$libresoc.v:142242$6457 + attribute \src "libresoc.v:142038.7-142038.25" + process $proc$libresoc.v:142038$6457 assign { } { } assign $1\wri_l_r_wri[0:0] 1'1 sync always sync init update \wri_l_r_wri $1\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:142338.3-142339.57" - process $proc$libresoc.v:142338$6274 + attribute \src "libresoc.v:142134.3-142135.57" + process $proc$libresoc.v:142134$6274 assign { } { } assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next sync posedge \coresync_clk update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:142340.3-142341.33" - process $proc$libresoc.v:142340$6275 + attribute \src "libresoc.v:142136.3-142137.33" + process $proc$libresoc.v:142136$6275 assign { } { } assign $0\ldst_port0_addr_i[95:0] \$175 sync posedge \coresync_clk update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:142342.3-142343.21" - process $proc$libresoc.v:142342$6276 + attribute \src "libresoc.v:142138.3-142139.21" + process $proc$libresoc.v:142138$6276 assign { } { } assign $0\alu_ok[0:0] \$96 sync posedge \coresync_clk update \alu_ok $0\alu_ok[0:0] end - attribute \src "libresoc.v:142344.3-142345.25" - process $proc$libresoc.v:142344$6277 + attribute \src "libresoc.v:142140.3-142141.25" + process $proc$libresoc.v:142140$6277 assign { } { } assign $0\ea_r[63:0] \ea_r$next sync posedge \coresync_clk update \ea_r $0\ea_r[63:0] end - attribute \src "libresoc.v:142346.3-142347.29" - process $proc$libresoc.v:142346$6278 + attribute \src "libresoc.v:142142.3-142143.29" + process $proc$libresoc.v:142142$6278 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:142348.3-142349.29" - process $proc$libresoc.v:142348$6279 + attribute \src "libresoc.v:142144.3-142145.29" + process $proc$libresoc.v:142144$6279 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:142350.3-142351.29" - process $proc$libresoc.v:142350$6280 + attribute \src "libresoc.v:142146.3-142147.29" + process $proc$libresoc.v:142146$6280 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:142352.3-142353.27" - process $proc$libresoc.v:142352$6281 + attribute \src "libresoc.v:142148.3-142149.27" + process $proc$libresoc.v:142148$6281 assign { } { } assign $0\ldo_r[63:0] \ldo_r$next sync posedge \coresync_clk update \ldo_r $0\ldo_r[63:0] end - attribute \src "libresoc.v:142354.3-142355.51" - process $proc$libresoc.v:142354$6282 + attribute \src "libresoc.v:142150.3-142151.51" + process $proc$libresoc.v:142150$6282 assign { } { } assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next sync posedge \coresync_clk update \oper_r__insn_type $0\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:142356.3-142357.47" - process $proc$libresoc.v:142356$6283 + attribute \src "libresoc.v:142152.3-142153.47" + process $proc$libresoc.v:142152$6283 assign { } { } assign $0\oper_r__fn_unit[13:0] \oper_r__fn_unit$next sync posedge \coresync_clk update \oper_r__fn_unit $0\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:142358.3-142359.61" - process $proc$libresoc.v:142358$6284 + attribute \src "libresoc.v:142154.3-142155.61" + process $proc$libresoc.v:142154$6284 assign { } { } assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next sync posedge \coresync_clk update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:142360.3-142361.57" - process $proc$libresoc.v:142360$6285 + attribute \src "libresoc.v:142156.3-142157.57" + process $proc$libresoc.v:142156$6285 assign { } { } assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next sync posedge \coresync_clk update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:142362.3-142363.45" - process $proc$libresoc.v:142362$6286 + attribute \src "libresoc.v:142158.3-142159.45" + process $proc$libresoc.v:142158$6286 assign { } { } assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next sync posedge \coresync_clk update \oper_r__zero_a $0\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:142364.3-142365.45" - process $proc$libresoc.v:142364$6287 + attribute \src "libresoc.v:142160.3-142161.45" + process $proc$libresoc.v:142160$6287 assign { } { } assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next sync posedge \coresync_clk update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:142366.3-142367.45" - process $proc$libresoc.v:142366$6288 + attribute \src "libresoc.v:142162.3-142163.45" + process $proc$libresoc.v:142162$6288 assign { } { } assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next sync posedge \coresync_clk update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:142368.3-142369.45" - process $proc$libresoc.v:142368$6289 + attribute \src "libresoc.v:142164.3-142165.45" + process $proc$libresoc.v:142164$6289 assign { } { } assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next sync posedge \coresync_clk update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:142370.3-142371.45" - process $proc$libresoc.v:142370$6290 + attribute \src "libresoc.v:142166.3-142167.45" + process $proc$libresoc.v:142166$6290 assign { } { } assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next sync posedge \coresync_clk update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:142372.3-142373.49" - process $proc$libresoc.v:142372$6291 + attribute \src "libresoc.v:142168.3-142169.49" + process $proc$libresoc.v:142168$6291 assign { } { } assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next sync posedge \coresync_clk update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:142374.3-142375.51" - process $proc$libresoc.v:142374$6292 + attribute \src "libresoc.v:142170.3-142171.51" + process $proc$libresoc.v:142170$6292 assign { } { } assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next sync posedge \coresync_clk update \oper_r__is_signed $0\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:142376.3-142377.49" - process $proc$libresoc.v:142376$6293 + attribute \src "libresoc.v:142172.3-142173.49" + process $proc$libresoc.v:142172$6293 assign { } { } assign $0\oper_r__data_len[3:0] \oper_r__data_len$next sync posedge \coresync_clk update \oper_r__data_len $0\oper_r__data_len[3:0] end - attribute \src "libresoc.v:142378.3-142379.57" - process $proc$libresoc.v:142378$6294 + attribute \src "libresoc.v:142174.3-142175.57" + process $proc$libresoc.v:142174$6294 assign { } { } assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next sync posedge \coresync_clk update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:142380.3-142381.55" - process $proc$libresoc.v:142380$6295 + attribute \src "libresoc.v:142176.3-142177.55" + process $proc$libresoc.v:142176$6295 assign { } { } assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next sync posedge \coresync_clk update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:142382.3-142383.51" - process $proc$libresoc.v:142382$6296 + attribute \src "libresoc.v:142178.3-142179.51" + process $proc$libresoc.v:142178$6296 assign { } { } assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next sync posedge \coresync_clk update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:142384.3-142385.41" - process $proc$libresoc.v:142384$6297 + attribute \src "libresoc.v:142180.3-142181.41" + process $proc$libresoc.v:142180$6297 assign { } { } assign $0\oper_r__insn[31:0] \oper_r__insn$next sync posedge \coresync_clk update \oper_r__insn $0\oper_r__insn[31:0] end - attribute \src "libresoc.v:142386.3-142387.39" - process $proc$libresoc.v:142386$6298 + attribute \src "libresoc.v:142182.3-142183.39" + process $proc$libresoc.v:142182$6298 assign { } { } assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next sync posedge \coresync_clk update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:142388.3-142389.39" - process $proc$libresoc.v:142388$6299 + attribute \src "libresoc.v:142184.3-142185.39" + process $proc$libresoc.v:142184$6299 assign { } { } assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next sync posedge \coresync_clk update \sto_l_r_sto $0\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:142390.3-142391.39" - process $proc$libresoc.v:142390$6300 + attribute \src "libresoc.v:142186.3-142187.39" + process $proc$libresoc.v:142186$6300 assign { } { } assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next sync posedge \coresync_clk update \upd_l_r_upd $0\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:142392.3-142393.39" - process $proc$libresoc.v:142392$6301 + attribute \src "libresoc.v:142188.3-142189.39" + process $proc$libresoc.v:142188$6301 assign { } { } assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next sync posedge \coresync_clk update \upd_l_s_upd $0\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:142394.3-142395.39" - process $proc$libresoc.v:142394$6302 + attribute \src "libresoc.v:142190.3-142191.39" + process $proc$libresoc.v:142190$6302 assign { } { } assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next sync posedge \coresync_clk update \wri_l_r_wri $0\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:142396.3-142397.39" - process $proc$libresoc.v:142396$6303 + attribute \src "libresoc.v:142192.3-142193.39" + process $proc$libresoc.v:142192$6303 assign { } { } assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next sync posedge \coresync_clk update \adr_l_r_adr $0\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:142398.3-142399.39" - process $proc$libresoc.v:142398$6304 + attribute \src "libresoc.v:142194.3-142195.39" + process $proc$libresoc.v:142194$6304 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:142400.3-142401.39" - process $proc$libresoc.v:142400$6305 + attribute \src "libresoc.v:142196.3-142197.39" + process $proc$libresoc.v:142196$6305 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:142402.3-142403.39" - process $proc$libresoc.v:142402$6306 + attribute \src "libresoc.v:142198.3-142199.39" + process $proc$libresoc.v:142198$6306 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:142404.3-142405.39" - process $proc$libresoc.v:142404$6307 + attribute \src "libresoc.v:142200.3-142201.39" + process $proc$libresoc.v:142200$6307 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:142406.3-142407.28" - process $proc$libresoc.v:142406$6308 + attribute \src "libresoc.v:142202.3-142203.28" + process $proc$libresoc.v:142202$6308 assign { } { } assign $0\p_st_go[0:0] \cu_st__go_i sync posedge \coresync_clk update \p_st_go $0\p_st_go[0:0] end - attribute \src "libresoc.v:142478.3-142486.6" - process $proc$libresoc.v:142478$6309 + attribute \src "libresoc.v:142274.3-142282.6" + process $proc$libresoc.v:142274$6309 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$6310 $1\opc_l_s_opc$next[0:0]$6311 - attribute \src "libresoc.v:142479.5-142479.29" + attribute \src "libresoc.v:142275.5-142275.29" switch \initial - attribute \src "libresoc.v:142479.9-142479.17" + attribute \src "libresoc.v:142275.9-142275.17" case 1'1 case end @@ -228514,14 +228310,14 @@ module \ldst0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6310 end - attribute \src "libresoc.v:142487.3-142495.6" - process $proc$libresoc.v:142487$6312 + attribute \src "libresoc.v:142283.3-142291.6" + process $proc$libresoc.v:142283$6312 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$6313 $1\opc_l_r_opc$next[0:0]$6314 - attribute \src "libresoc.v:142488.5-142488.29" + attribute \src "libresoc.v:142284.5-142284.29" switch \initial - attribute \src "libresoc.v:142488.9-142488.17" + attribute \src "libresoc.v:142284.9-142284.17" case 1'1 case end @@ -228537,14 +228333,14 @@ module \ldst0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6313 end - attribute \src "libresoc.v:142496.3-142504.6" - process $proc$libresoc.v:142496$6315 + attribute \src "libresoc.v:142292.3-142300.6" + process $proc$libresoc.v:142292$6315 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$6316 $1\src_l_s_src$next[2:0]$6317 - attribute \src "libresoc.v:142497.5-142497.29" + attribute \src "libresoc.v:142293.5-142293.29" switch \initial - attribute \src "libresoc.v:142497.9-142497.17" + attribute \src "libresoc.v:142293.9-142293.17" case 1'1 case end @@ -228560,14 +228356,14 @@ module \ldst0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6316 end - attribute \src "libresoc.v:142505.3-142513.6" - process $proc$libresoc.v:142505$6318 + attribute \src "libresoc.v:142301.3-142309.6" + process $proc$libresoc.v:142301$6318 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$6319 $1\src_l_r_src$next[2:0]$6320 - attribute \src "libresoc.v:142506.5-142506.29" + attribute \src "libresoc.v:142302.5-142302.29" switch \initial - attribute \src "libresoc.v:142506.9-142506.17" + attribute \src "libresoc.v:142302.9-142302.17" case 1'1 case end @@ -228583,14 +228379,14 @@ module \ldst0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6319 end - attribute \src "libresoc.v:142514.3-142522.6" - process $proc$libresoc.v:142514$6321 + attribute \src "libresoc.v:142310.3-142318.6" + process $proc$libresoc.v:142310$6321 assign { } { } assign { } { } assign $0\adr_l_r_adr$next[0:0]$6322 $1\adr_l_r_adr$next[0:0]$6323 - attribute \src "libresoc.v:142515.5-142515.29" + attribute \src "libresoc.v:142311.5-142311.29" switch \initial - attribute \src "libresoc.v:142515.9-142515.17" + attribute \src "libresoc.v:142311.9-142311.17" case 1'1 case end @@ -228606,14 +228402,14 @@ module \ldst0 sync always update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6322 end - attribute \src "libresoc.v:142523.3-142531.6" - process $proc$libresoc.v:142523$6324 + attribute \src "libresoc.v:142319.3-142327.6" + process $proc$libresoc.v:142319$6324 assign { } { } assign { } { } assign $0\wri_l_r_wri$next[0:0]$6325 $1\wri_l_r_wri$next[0:0]$6326 - attribute \src "libresoc.v:142524.5-142524.29" + attribute \src "libresoc.v:142320.5-142320.29" switch \initial - attribute \src "libresoc.v:142524.9-142524.17" + attribute \src "libresoc.v:142320.9-142320.17" case 1'1 case end @@ -228629,14 +228425,14 @@ module \ldst0 sync always update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6325 end - attribute \src "libresoc.v:142532.3-142540.6" - process $proc$libresoc.v:142532$6327 + attribute \src "libresoc.v:142328.3-142336.6" + process $proc$libresoc.v:142328$6327 assign { } { } assign { } { } assign $0\upd_l_s_upd$next[0:0]$6328 $1\upd_l_s_upd$next[0:0]$6329 - attribute \src "libresoc.v:142533.5-142533.29" + attribute \src "libresoc.v:142329.5-142329.29" switch \initial - attribute \src "libresoc.v:142533.9-142533.17" + attribute \src "libresoc.v:142329.9-142329.17" case 1'1 case end @@ -228652,14 +228448,14 @@ module \ldst0 sync always update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6328 end - attribute \src "libresoc.v:142541.3-142549.6" - process $proc$libresoc.v:142541$6330 + attribute \src "libresoc.v:142337.3-142345.6" + process $proc$libresoc.v:142337$6330 assign { } { } assign { } { } assign $0\upd_l_r_upd$next[0:0]$6331 $1\upd_l_r_upd$next[0:0]$6332 - attribute \src "libresoc.v:142542.5-142542.29" + attribute \src "libresoc.v:142338.5-142338.29" switch \initial - attribute \src "libresoc.v:142542.9-142542.17" + attribute \src "libresoc.v:142338.9-142338.17" case 1'1 case end @@ -228675,14 +228471,14 @@ module \ldst0 sync always update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6331 end - attribute \src "libresoc.v:142550.3-142558.6" - process $proc$libresoc.v:142550$6333 + attribute \src "libresoc.v:142346.3-142354.6" + process $proc$libresoc.v:142346$6333 assign { } { } assign { } { } assign $0\sto_l_r_sto$next[0:0]$6334 $1\sto_l_r_sto$next[0:0]$6335 - attribute \src "libresoc.v:142551.5-142551.29" + attribute \src "libresoc.v:142347.5-142347.29" switch \initial - attribute \src "libresoc.v:142551.9-142551.17" + attribute \src "libresoc.v:142347.9-142347.17" case 1'1 case end @@ -228698,14 +228494,14 @@ module \ldst0 sync always update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6334 end - attribute \src "libresoc.v:142559.3-142567.6" - process $proc$libresoc.v:142559$6336 + attribute \src "libresoc.v:142355.3-142363.6" + process $proc$libresoc.v:142355$6336 assign { } { } assign { } { } assign $0\lsd_l_r_lsd$next[0:0]$6337 $1\lsd_l_r_lsd$next[0:0]$6338 - attribute \src "libresoc.v:142560.5-142560.29" + attribute \src "libresoc.v:142356.5-142356.29" switch \initial - attribute \src "libresoc.v:142560.9-142560.17" + attribute \src "libresoc.v:142356.9-142356.17" case 1'1 case end @@ -228721,8 +228517,8 @@ module \ldst0 sync always update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6337 end - attribute \src "libresoc.v:142568.3-142610.6" - process $proc$libresoc.v:142568$6339 + attribute \src "libresoc.v:142364.3-142406.6" + process $proc$libresoc.v:142364$6339 assign { } { } assign { } { } assign { } { } @@ -228793,9 +228589,9 @@ module \ldst0 assign $0\oper_r__oe__ok$next[0:0]$6351 $3\oper_r__oe__ok$next[0:0]$6391 assign $0\oper_r__rc__ok$next[0:0]$6352 $3\oper_r__rc__ok$next[0:0]$6392 assign $0\oper_r__rc__rc$next[0:0]$6353 $3\oper_r__rc__rc$next[0:0]$6393 - attribute \src "libresoc.v:142569.5-142569.29" + attribute \src "libresoc.v:142365.5-142365.29" switch \initial - attribute \src "libresoc.v:142569.9-142569.17" + attribute \src "libresoc.v:142365.9-142365.17" case 1'1 case end @@ -228919,14 +228715,14 @@ module \ldst0 update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6354 update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6355 end - attribute \src "libresoc.v:142611.3-142620.6" - process $proc$libresoc.v:142611$6394 + attribute \src "libresoc.v:142407.3-142416.6" + process $proc$libresoc.v:142407$6394 assign { } { } assign { } { } assign $0\ldo_r$next[63:0]$6395 $1\ldo_r$next[63:0]$6396 - attribute \src "libresoc.v:142612.5-142612.29" + attribute \src "libresoc.v:142408.5-142408.29" switch \initial - attribute \src "libresoc.v:142612.9-142612.17" + attribute \src "libresoc.v:142408.9-142408.17" case 1'1 case end @@ -228942,15 +228738,15 @@ module \ldst0 sync always update \ldo_r$next $0\ldo_r$next[63:0]$6395 end - attribute \src "libresoc.v:142621.3-142636.6" - process $proc$libresoc.v:142621$6397 + attribute \src "libresoc.v:142417.3-142432.6" + process $proc$libresoc.v:142417$6397 assign { } { } assign { } { } assign { } { } assign $0\src_r0$next[63:0]$6398 $2\src_r0$next[63:0]$6400 - attribute \src "libresoc.v:142622.5-142622.29" + attribute \src "libresoc.v:142418.5-142418.29" switch \initial - attribute \src "libresoc.v:142622.9-142622.17" + attribute \src "libresoc.v:142418.9-142418.17" case 1'1 case end @@ -228975,15 +228771,15 @@ module \ldst0 sync always update \src_r0$next $0\src_r0$next[63:0]$6398 end - attribute \src "libresoc.v:142637.3-142652.6" - process $proc$libresoc.v:142637$6401 + attribute \src "libresoc.v:142433.3-142448.6" + process $proc$libresoc.v:142433$6401 assign { } { } assign { } { } assign { } { } assign $0\src_r1$next[63:0]$6402 $2\src_r1$next[63:0]$6404 - attribute \src "libresoc.v:142638.5-142638.29" + attribute \src "libresoc.v:142434.5-142434.29" switch \initial - attribute \src "libresoc.v:142638.9-142638.17" + attribute \src "libresoc.v:142434.9-142434.17" case 1'1 case end @@ -229008,15 +228804,15 @@ module \ldst0 sync always update \src_r1$next $0\src_r1$next[63:0]$6402 end - attribute \src "libresoc.v:142653.3-142668.6" - process $proc$libresoc.v:142653$6405 + attribute \src "libresoc.v:142449.3-142464.6" + process $proc$libresoc.v:142449$6405 assign { } { } assign { } { } assign { } { } assign $0\src_r2$next[63:0]$6406 $2\src_r2$next[63:0]$6408 - attribute \src "libresoc.v:142654.5-142654.29" + attribute \src "libresoc.v:142450.5-142450.29" switch \initial - attribute \src "libresoc.v:142654.9-142654.17" + attribute \src "libresoc.v:142450.9-142450.17" case 1'1 case end @@ -229041,14 +228837,14 @@ module \ldst0 sync always update \src_r2$next $0\src_r2$next[63:0]$6406 end - attribute \src "libresoc.v:142669.3-142678.6" - process $proc$libresoc.v:142669$6409 + attribute \src "libresoc.v:142465.3-142474.6" + process $proc$libresoc.v:142465$6409 assign { } { } assign { } { } assign $0\ea_r$next[63:0]$6410 $1\ea_r$next[63:0]$6411 - attribute \src "libresoc.v:142670.5-142670.29" + attribute \src "libresoc.v:142466.5-142466.29" switch \initial - attribute \src "libresoc.v:142670.9-142670.17" + attribute \src "libresoc.v:142466.9-142466.17" case 1'1 case end @@ -229064,14 +228860,14 @@ module \ldst0 sync always update \ea_r$next $0\ea_r$next[63:0]$6410 end - attribute \src "libresoc.v:142679.3-142688.6" - process $proc$libresoc.v:142679$6412 + attribute \src "libresoc.v:142475.3-142484.6" + process $proc$libresoc.v:142475$6412 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:142680.5-142680.29" + attribute \src "libresoc.v:142476.5-142476.29" switch \initial - attribute \src "libresoc.v:142680.9-142680.17" + attribute \src "libresoc.v:142476.9-142476.17" case 1'1 case end @@ -229087,14 +228883,14 @@ module \ldst0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:142689.3-142698.6" - process $proc$libresoc.v:142689$6413 + attribute \src "libresoc.v:142485.3-142494.6" + process $proc$libresoc.v:142485$6413 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:142690.5-142690.29" + attribute \src "libresoc.v:142486.5-142486.29" switch \initial - attribute \src "libresoc.v:142690.9-142690.17" + attribute \src "libresoc.v:142486.9-142486.17" case 1'1 case end @@ -229110,14 +228906,14 @@ module \ldst0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:142699.3-142707.6" - process $proc$libresoc.v:142699$6414 + attribute \src "libresoc.v:142495.3-142503.6" + process $proc$libresoc.v:142495$6414 assign { } { } assign { } { } assign $0\ldst_port0_addr_i_ok$next[0:0]$6415 $1\ldst_port0_addr_i_ok$next[0:0]$6416 - attribute \src "libresoc.v:142700.5-142700.29" + attribute \src "libresoc.v:142496.5-142496.29" switch \initial - attribute \src "libresoc.v:142700.9-142700.17" + attribute \src "libresoc.v:142496.9-142496.17" case 1'1 case end @@ -229133,14 +228929,14 @@ module \ldst0 sync always update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6415 end - attribute \src "libresoc.v:142708.3-142731.6" - process $proc$libresoc.v:142708$6417 + attribute \src "libresoc.v:142504.3-142527.6" + process $proc$libresoc.v:142504$6417 assign { } { } assign { } { } assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "libresoc.v:142709.5-142709.29" + attribute \src "libresoc.v:142505.5-142505.29" switch \initial - attribute \src "libresoc.v:142709.9-142709.17" + attribute \src "libresoc.v:142505.9-142505.17" case 1'1 case end @@ -229177,13 +228973,13 @@ module \ldst0 sync always update \lddata_r $0\lddata_r[63:0] end - attribute \src "libresoc.v:142732.3-142743.6" - process $proc$libresoc.v:142732$6418 + attribute \src "libresoc.v:142528.3-142539.6" + process $proc$libresoc.v:142528$6418 assign { } { } assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "libresoc.v:142733.5-142733.29" + attribute \src "libresoc.v:142529.5-142529.29" switch \initial - attribute \src "libresoc.v:142733.9-142733.17" + attribute \src "libresoc.v:142529.9-142529.17" case 1'1 case end @@ -229201,13 +228997,13 @@ module \ldst0 sync always update \revnorev $0\revnorev[63:0] end - attribute \src "libresoc.v:142744.3-142763.6" - process $proc$libresoc.v:142744$6419 + attribute \src "libresoc.v:142540.3-142559.6" + process $proc$libresoc.v:142540$6419 assign { } { } assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "libresoc.v:142745.5-142745.29" + attribute \src "libresoc.v:142541.5-142541.29" switch \initial - attribute \src "libresoc.v:142745.9-142745.17" + attribute \src "libresoc.v:142541.9-142541.17" case 1'1 case end @@ -229236,14 +229032,14 @@ module \ldst0 sync always update \ldd_o $0\ldd_o[63:0] end - attribute \src "libresoc.v:142764.3-142787.6" - process $proc$libresoc.v:142764$6420 + attribute \src "libresoc.v:142560.3-142583.6" + process $proc$libresoc.v:142560$6420 assign { } { } assign { } { } assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "libresoc.v:142765.5-142765.29" + attribute \src "libresoc.v:142561.5-142561.29" switch \initial - attribute \src "libresoc.v:142765.9-142765.17" + attribute \src "libresoc.v:142561.9-142561.17" case 1'1 case end @@ -229280,13 +229076,13 @@ module \ldst0 sync always update \stdata_r $0\stdata_r[63:0] end - attribute \src "libresoc.v:142788.3-142799.6" - process $proc$libresoc.v:142788$6421 + attribute \src "libresoc.v:142584.3-142595.6" + process $proc$libresoc.v:142584$6421 assign { } { } assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142789.5-142789.29" + attribute \src "libresoc.v:142585.5-142585.29" switch \initial - attribute \src "libresoc.v:142789.9-142789.17" + attribute \src "libresoc.v:142585.9-142585.17" case 1'1 case end @@ -229304,97 +229100,97 @@ module \ldst0 sync always update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] end - connect \$100 $and$libresoc.v:142247$6180_Y - connect \$102 $and$libresoc.v:142248$6181_Y - connect \$104 $and$libresoc.v:142249$6182_Y - connect \$106 $and$libresoc.v:142250$6183_Y - connect \$108 $and$libresoc.v:142251$6184_Y - connect \$10 $or$libresoc.v:142252$6185_Y - connect \$110 $and$libresoc.v:142253$6186_Y - connect \$112 $and$libresoc.v:142254$6187_Y - connect \$114 $and$libresoc.v:142255$6188_Y - connect \$116 $and$libresoc.v:142256$6189_Y - connect \$118 $and$libresoc.v:142257$6190_Y - connect \$120 $and$libresoc.v:142258$6191_Y - connect \$122 $and$libresoc.v:142259$6192_Y - connect \$124 $and$libresoc.v:142260$6193_Y - connect \$126 $eq$libresoc.v:142261$6194_Y - connect \$128 $and$libresoc.v:142262$6195_Y - connect \$12 $or$libresoc.v:142263$6196_Y - connect \$130 $and$libresoc.v:142264$6197_Y - connect \$132 $and$libresoc.v:142265$6198_Y - connect \$134 $or$libresoc.v:142266$6199_Y - connect \$136 $or$libresoc.v:142267$6200_Y - connect \$138 $or$libresoc.v:142268$6201_Y - connect \$140 $and$libresoc.v:142269$6202_Y - connect \$142 $and$libresoc.v:142270$6203_Y - connect \$145 $or$libresoc.v:142271$6204_Y - connect \$147 $or$libresoc.v:142272$6205_Y - connect \$144 $not$libresoc.v:142273$6206_Y - connect \$14 $or$libresoc.v:142274$6207_Y - connect \$150 $and$libresoc.v:142275$6208_Y - connect \$152 $or$libresoc.v:142276$6209_Y - connect \$154 $and$libresoc.v:142277$6210_Y - connect \$156 $not$libresoc.v:142278$6211_Y - connect \$158 $or$libresoc.v:142279$6212_Y - connect \$160 $and$libresoc.v:142280$6213_Y - connect \$162 $eq$libresoc.v:142281$6214_Y - connect \$164 $and$libresoc.v:142282$6215_Y - connect \$167 $eq$libresoc.v:142283$6216_Y - connect \$16 $or$libresoc.v:142284$6217_Y - connect \$169 $and$libresoc.v:142285$6218_Y - connect \$171 $and$libresoc.v:142286$6219_Y - connect \$173 $and$libresoc.v:142287$6220_Y - connect \$175 $pos$libresoc.v:142288$6222_Y - connect \$177 $and$libresoc.v:142289$6223_Y - connect \$186 $pos$libresoc.v:142290$6225_Y - connect \$188 $pos$libresoc.v:142291$6226_Y - connect \$18 $or$libresoc.v:142292$6227_Y - connect \$190 $pos$libresoc.v:142293$6228_Y - connect \$192 $eq$libresoc.v:142294$6229_Y - connect \$194 $pos$libresoc.v:142295$6231_Y - connect \$196 $pos$libresoc.v:142296$6232_Y - connect \$198 $pos$libresoc.v:142297$6233_Y - connect \$20 $or$libresoc.v:142298$6234_Y - connect \$22 $eq$libresoc.v:142299$6235_Y - connect \$24 $eq$libresoc.v:142300$6236_Y - connect \$26 $and$libresoc.v:142301$6237_Y - connect \$28 $and$libresoc.v:142302$6238_Y - connect \$30 $not$libresoc.v:142303$6239_Y - connect \$32 $and$libresoc.v:142304$6240_Y - connect \$34 $not$libresoc.v:142305$6241_Y - connect \$36 $and$libresoc.v:142306$6242_Y - connect \$39 $not$libresoc.v:142307$6243_Y - connect \$41 $eq$libresoc.v:142308$6244_Y - connect \$43 $and$libresoc.v:142309$6245_Y - connect \$45 $or$libresoc.v:142310$6246_Y - connect \$47 $not$libresoc.v:142311$6247_Y - connect \$49 $eq$libresoc.v:142312$6248_Y - connect \$51 $and$libresoc.v:142313$6249_Y - connect \$53 $or$libresoc.v:142314$6250_Y - connect \$55 $or$libresoc.v:142315$6251_Y - connect \$57 $and$libresoc.v:142316$6252_Y - connect \$59 $or$libresoc.v:142317$6253_Y - connect \$61 $or$libresoc.v:142318$6254_Y - connect \$63 $or$libresoc.v:142319$6255_Y - connect \$65 $ternary$libresoc.v:142320$6256_Y - connect \$67 $ternary$libresoc.v:142321$6257_Y - connect \$69 $ternary$libresoc.v:142322$6258_Y - connect \$71 $ternary$libresoc.v:142323$6259_Y - connect \$74 $add$libresoc.v:142324$6260_Y - connect \$76 $and$libresoc.v:142325$6261_Y - connect \$78 $not$libresoc.v:142326$6262_Y - connect \$80 $and$libresoc.v:142327$6263_Y - connect \$82 $not$libresoc.v:142328$6264_Y - connect \$84 $and$libresoc.v:142329$6265_Y - connect \$86 $and$libresoc.v:142330$6266_Y - connect \$88 $and$libresoc.v:142331$6267_Y - connect \$8 $or$libresoc.v:142332$6268_Y - connect \$90 $or$libresoc.v:142333$6269_Y - connect \$93 $or$libresoc.v:142334$6270_Y - connect \$92 $not$libresoc.v:142335$6271_Y - connect \$96 $and$libresoc.v:142336$6272_Y - connect \$98 $not$libresoc.v:142337$6273_Y + connect \$100 $and$libresoc.v:142043$6180_Y + connect \$102 $and$libresoc.v:142044$6181_Y + connect \$104 $and$libresoc.v:142045$6182_Y + connect \$106 $and$libresoc.v:142046$6183_Y + connect \$108 $and$libresoc.v:142047$6184_Y + connect \$10 $or$libresoc.v:142048$6185_Y + connect \$110 $and$libresoc.v:142049$6186_Y + connect \$112 $and$libresoc.v:142050$6187_Y + connect \$114 $and$libresoc.v:142051$6188_Y + connect \$116 $and$libresoc.v:142052$6189_Y + connect \$118 $and$libresoc.v:142053$6190_Y + connect \$120 $and$libresoc.v:142054$6191_Y + connect \$122 $and$libresoc.v:142055$6192_Y + connect \$124 $and$libresoc.v:142056$6193_Y + connect \$126 $eq$libresoc.v:142057$6194_Y + connect \$128 $and$libresoc.v:142058$6195_Y + connect \$12 $or$libresoc.v:142059$6196_Y + connect \$130 $and$libresoc.v:142060$6197_Y + connect \$132 $and$libresoc.v:142061$6198_Y + connect \$134 $or$libresoc.v:142062$6199_Y + connect \$136 $or$libresoc.v:142063$6200_Y + connect \$138 $or$libresoc.v:142064$6201_Y + connect \$140 $and$libresoc.v:142065$6202_Y + connect \$142 $and$libresoc.v:142066$6203_Y + connect \$145 $or$libresoc.v:142067$6204_Y + connect \$147 $or$libresoc.v:142068$6205_Y + connect \$144 $not$libresoc.v:142069$6206_Y + connect \$14 $or$libresoc.v:142070$6207_Y + connect \$150 $and$libresoc.v:142071$6208_Y + connect \$152 $or$libresoc.v:142072$6209_Y + connect \$154 $and$libresoc.v:142073$6210_Y + connect \$156 $not$libresoc.v:142074$6211_Y + connect \$158 $or$libresoc.v:142075$6212_Y + connect \$160 $and$libresoc.v:142076$6213_Y + connect \$162 $eq$libresoc.v:142077$6214_Y + connect \$164 $and$libresoc.v:142078$6215_Y + connect \$167 $eq$libresoc.v:142079$6216_Y + connect \$16 $or$libresoc.v:142080$6217_Y + connect \$169 $and$libresoc.v:142081$6218_Y + connect \$171 $and$libresoc.v:142082$6219_Y + connect \$173 $and$libresoc.v:142083$6220_Y + connect \$175 $pos$libresoc.v:142084$6222_Y + connect \$177 $and$libresoc.v:142085$6223_Y + connect \$186 $pos$libresoc.v:142086$6225_Y + connect \$188 $pos$libresoc.v:142087$6226_Y + connect \$18 $or$libresoc.v:142088$6227_Y + connect \$190 $pos$libresoc.v:142089$6228_Y + connect \$192 $eq$libresoc.v:142090$6229_Y + connect \$194 $pos$libresoc.v:142091$6231_Y + connect \$196 $pos$libresoc.v:142092$6232_Y + connect \$198 $pos$libresoc.v:142093$6233_Y + connect \$20 $or$libresoc.v:142094$6234_Y + connect \$22 $eq$libresoc.v:142095$6235_Y + connect \$24 $eq$libresoc.v:142096$6236_Y + connect \$26 $and$libresoc.v:142097$6237_Y + connect \$28 $and$libresoc.v:142098$6238_Y + connect \$30 $not$libresoc.v:142099$6239_Y + connect \$32 $and$libresoc.v:142100$6240_Y + connect \$34 $not$libresoc.v:142101$6241_Y + connect \$36 $and$libresoc.v:142102$6242_Y + connect \$39 $not$libresoc.v:142103$6243_Y + connect \$41 $eq$libresoc.v:142104$6244_Y + connect \$43 $and$libresoc.v:142105$6245_Y + connect \$45 $or$libresoc.v:142106$6246_Y + connect \$47 $not$libresoc.v:142107$6247_Y + connect \$49 $eq$libresoc.v:142108$6248_Y + connect \$51 $and$libresoc.v:142109$6249_Y + connect \$53 $or$libresoc.v:142110$6250_Y + connect \$55 $or$libresoc.v:142111$6251_Y + connect \$57 $and$libresoc.v:142112$6252_Y + connect \$59 $or$libresoc.v:142113$6253_Y + connect \$61 $or$libresoc.v:142114$6254_Y + connect \$63 $or$libresoc.v:142115$6255_Y + connect \$65 $ternary$libresoc.v:142116$6256_Y + connect \$67 $ternary$libresoc.v:142117$6257_Y + connect \$69 $ternary$libresoc.v:142118$6258_Y + connect \$71 $ternary$libresoc.v:142119$6259_Y + connect \$74 $add$libresoc.v:142120$6260_Y + connect \$76 $and$libresoc.v:142121$6261_Y + connect \$78 $not$libresoc.v:142122$6262_Y + connect \$80 $and$libresoc.v:142123$6263_Y + connect \$82 $not$libresoc.v:142124$6264_Y + connect \$84 $and$libresoc.v:142125$6265_Y + connect \$86 $and$libresoc.v:142126$6266_Y + connect \$88 $and$libresoc.v:142127$6267_Y + connect \$8 $or$libresoc.v:142128$6268_Y + connect \$90 $or$libresoc.v:142129$6269_Y + connect \$93 $or$libresoc.v:142130$6270_Y + connect \$92 $not$libresoc.v:142131$6271_Y + connect \$96 $and$libresoc.v:142132$6272_Y + connect \$98 $not$libresoc.v:142133$6273_Y connect \$38 \$55 connect \$73 \$74 connect \$166 \$169 @@ -229455,271 +229251,271 @@ module \ldst0 connect \reset_o \$10 connect \reset_i \$8 end -attribute \src "libresoc.v:142863.1-143450.10" +attribute \src "libresoc.v:142659.1-143246.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" module \left_mask - attribute \src "libresoc.v:142864.7-142864.20" + attribute \src "libresoc.v:142660.7-142660.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $10\mask[9:9] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $11\mask[10:10] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $12\mask[11:11] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $13\mask[12:12] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $14\mask[13:13] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $15\mask[14:14] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $16\mask[15:15] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $17\mask[16:16] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $18\mask[17:17] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $19\mask[18:18] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $1\mask[0:0] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $20\mask[19:19] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $21\mask[20:20] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $22\mask[21:21] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $23\mask[22:22] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $24\mask[23:23] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $25\mask[24:24] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $26\mask[25:25] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $27\mask[26:26] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $28\mask[27:27] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $29\mask[28:28] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $2\mask[1:1] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $30\mask[29:29] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $31\mask[30:30] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $32\mask[31:31] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $33\mask[32:32] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $34\mask[33:33] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $35\mask[34:34] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $36\mask[35:35] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $37\mask[36:36] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $38\mask[37:37] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $39\mask[38:38] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $3\mask[2:2] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $40\mask[39:39] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $41\mask[40:40] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $42\mask[41:41] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $43\mask[42:42] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $44\mask[43:43] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $45\mask[44:44] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $46\mask[45:45] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $47\mask[46:46] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $48\mask[47:47] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $49\mask[48:48] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $4\mask[3:3] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $50\mask[49:49] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $51\mask[50:50] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $52\mask[51:51] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $53\mask[52:52] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $54\mask[53:53] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $55\mask[54:54] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $56\mask[55:55] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $57\mask[56:56] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $58\mask[57:57] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $59\mask[58:58] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $5\mask[4:4] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $60\mask[59:59] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $61\mask[60:60] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $62\mask[61:61] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $63\mask[62:62] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $64\mask[63:63] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $6\mask[5:5] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $7\mask[6:6] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $8\mask[7:7] - attribute \src "libresoc.v:143062.3-143449.6" + attribute \src "libresoc.v:142858.3-143245.6" wire $9\mask[8:8] - attribute \src "libresoc.v:142998.17-142998.96" - wire $gt$libresoc.v:142998$6458_Y - attribute \src "libresoc.v:142999.18-142999.98" - wire $gt$libresoc.v:142999$6459_Y - attribute \src "libresoc.v:143000.19-143000.99" - wire $gt$libresoc.v:143000$6460_Y - attribute \src "libresoc.v:143001.19-143001.99" - wire $gt$libresoc.v:143001$6461_Y - attribute \src "libresoc.v:143002.19-143002.99" - wire $gt$libresoc.v:143002$6462_Y - attribute \src "libresoc.v:143003.19-143003.99" - wire $gt$libresoc.v:143003$6463_Y - attribute \src "libresoc.v:143004.19-143004.99" - wire $gt$libresoc.v:143004$6464_Y - attribute \src "libresoc.v:143005.19-143005.99" - wire $gt$libresoc.v:143005$6465_Y - attribute \src "libresoc.v:143006.19-143006.99" - wire $gt$libresoc.v:143006$6466_Y - attribute \src "libresoc.v:143007.19-143007.99" - wire $gt$libresoc.v:143007$6467_Y - attribute \src "libresoc.v:143008.19-143008.99" - wire $gt$libresoc.v:143008$6468_Y - attribute \src "libresoc.v:143009.18-143009.97" - wire $gt$libresoc.v:143009$6469_Y - attribute \src "libresoc.v:143010.19-143010.99" - wire $gt$libresoc.v:143010$6470_Y - attribute \src "libresoc.v:143011.19-143011.99" - wire $gt$libresoc.v:143011$6471_Y - attribute \src "libresoc.v:143012.19-143012.99" - wire $gt$libresoc.v:143012$6472_Y - attribute \src "libresoc.v:143013.19-143013.99" - wire $gt$libresoc.v:143013$6473_Y - attribute \src "libresoc.v:143014.19-143014.99" - wire $gt$libresoc.v:143014$6474_Y - attribute \src "libresoc.v:143015.18-143015.97" - wire $gt$libresoc.v:143015$6475_Y - attribute \src "libresoc.v:143016.18-143016.97" - wire $gt$libresoc.v:143016$6476_Y - attribute \src "libresoc.v:143017.18-143017.97" - wire $gt$libresoc.v:143017$6477_Y - attribute \src "libresoc.v:143018.17-143018.96" - wire $gt$libresoc.v:143018$6478_Y - attribute \src "libresoc.v:143019.18-143019.97" - wire $gt$libresoc.v:143019$6479_Y - attribute \src "libresoc.v:143020.18-143020.97" - wire $gt$libresoc.v:143020$6480_Y - attribute \src "libresoc.v:143021.18-143021.97" - wire $gt$libresoc.v:143021$6481_Y - attribute \src "libresoc.v:143022.18-143022.97" - wire $gt$libresoc.v:143022$6482_Y - attribute \src "libresoc.v:143023.18-143023.97" - wire $gt$libresoc.v:143023$6483_Y - attribute \src "libresoc.v:143024.18-143024.97" - wire $gt$libresoc.v:143024$6484_Y - attribute \src "libresoc.v:143025.18-143025.97" - wire $gt$libresoc.v:143025$6485_Y - attribute \src "libresoc.v:143026.18-143026.98" - wire $gt$libresoc.v:143026$6486_Y - attribute \src "libresoc.v:143027.18-143027.98" - wire $gt$libresoc.v:143027$6487_Y - attribute \src "libresoc.v:143028.18-143028.98" - wire $gt$libresoc.v:143028$6488_Y - attribute \src "libresoc.v:143029.17-143029.96" - wire $gt$libresoc.v:143029$6489_Y - attribute \src "libresoc.v:143030.18-143030.98" - wire $gt$libresoc.v:143030$6490_Y - attribute \src "libresoc.v:143031.18-143031.98" - wire $gt$libresoc.v:143031$6491_Y - attribute \src "libresoc.v:143032.18-143032.98" - wire $gt$libresoc.v:143032$6492_Y - attribute \src "libresoc.v:143033.18-143033.98" - wire $gt$libresoc.v:143033$6493_Y - attribute \src "libresoc.v:143034.18-143034.98" - wire $gt$libresoc.v:143034$6494_Y - attribute \src "libresoc.v:143035.18-143035.98" - wire $gt$libresoc.v:143035$6495_Y - attribute \src "libresoc.v:143036.18-143036.98" - wire $gt$libresoc.v:143036$6496_Y - attribute \src "libresoc.v:143037.18-143037.98" - wire $gt$libresoc.v:143037$6497_Y - attribute \src "libresoc.v:143038.18-143038.98" - wire $gt$libresoc.v:143038$6498_Y - attribute \src "libresoc.v:143039.18-143039.98" - wire $gt$libresoc.v:143039$6499_Y - attribute \src "libresoc.v:143040.17-143040.96" - wire $gt$libresoc.v:143040$6500_Y - attribute \src "libresoc.v:143041.18-143041.98" - wire $gt$libresoc.v:143041$6501_Y - attribute \src "libresoc.v:143042.18-143042.98" - wire $gt$libresoc.v:143042$6502_Y - attribute \src "libresoc.v:143043.18-143043.98" - wire $gt$libresoc.v:143043$6503_Y - attribute \src "libresoc.v:143044.18-143044.98" - wire $gt$libresoc.v:143044$6504_Y - attribute \src "libresoc.v:143045.18-143045.98" - wire $gt$libresoc.v:143045$6505_Y - attribute \src "libresoc.v:143046.18-143046.98" - wire $gt$libresoc.v:143046$6506_Y - attribute \src "libresoc.v:143047.18-143047.98" - wire $gt$libresoc.v:143047$6507_Y - attribute \src "libresoc.v:143048.18-143048.98" - wire $gt$libresoc.v:143048$6508_Y - attribute \src "libresoc.v:143049.18-143049.98" - wire $gt$libresoc.v:143049$6509_Y - attribute \src "libresoc.v:143050.18-143050.98" - wire $gt$libresoc.v:143050$6510_Y - attribute \src "libresoc.v:143051.17-143051.96" - wire $gt$libresoc.v:143051$6511_Y - attribute \src "libresoc.v:143052.18-143052.98" - wire $gt$libresoc.v:143052$6512_Y - attribute \src "libresoc.v:143053.18-143053.98" - wire $gt$libresoc.v:143053$6513_Y - attribute \src "libresoc.v:143054.18-143054.98" - wire $gt$libresoc.v:143054$6514_Y - attribute \src "libresoc.v:143055.18-143055.98" - wire $gt$libresoc.v:143055$6515_Y - attribute \src "libresoc.v:143056.18-143056.98" - wire $gt$libresoc.v:143056$6516_Y - attribute \src "libresoc.v:143057.18-143057.98" - wire $gt$libresoc.v:143057$6517_Y - attribute \src "libresoc.v:143058.18-143058.98" - wire $gt$libresoc.v:143058$6518_Y - attribute \src "libresoc.v:143059.18-143059.98" - wire $gt$libresoc.v:143059$6519_Y - attribute \src "libresoc.v:143060.18-143060.98" - wire $gt$libresoc.v:143060$6520_Y - attribute \src "libresoc.v:143061.18-143061.98" - wire $gt$libresoc.v:143061$6521_Y + attribute \src "libresoc.v:142794.17-142794.96" + wire $gt$libresoc.v:142794$6458_Y + attribute \src "libresoc.v:142795.18-142795.98" + wire $gt$libresoc.v:142795$6459_Y + attribute \src "libresoc.v:142796.19-142796.99" + wire $gt$libresoc.v:142796$6460_Y + attribute \src "libresoc.v:142797.19-142797.99" + wire $gt$libresoc.v:142797$6461_Y + attribute \src "libresoc.v:142798.19-142798.99" + wire $gt$libresoc.v:142798$6462_Y + attribute \src "libresoc.v:142799.19-142799.99" + wire $gt$libresoc.v:142799$6463_Y + attribute \src "libresoc.v:142800.19-142800.99" + wire $gt$libresoc.v:142800$6464_Y + attribute \src "libresoc.v:142801.19-142801.99" + wire $gt$libresoc.v:142801$6465_Y + attribute \src "libresoc.v:142802.19-142802.99" + wire $gt$libresoc.v:142802$6466_Y + attribute \src "libresoc.v:142803.19-142803.99" + wire $gt$libresoc.v:142803$6467_Y + attribute \src "libresoc.v:142804.19-142804.99" + wire $gt$libresoc.v:142804$6468_Y + attribute \src "libresoc.v:142805.18-142805.97" + wire $gt$libresoc.v:142805$6469_Y + attribute \src "libresoc.v:142806.19-142806.99" + wire $gt$libresoc.v:142806$6470_Y + attribute \src "libresoc.v:142807.19-142807.99" + wire $gt$libresoc.v:142807$6471_Y + attribute \src "libresoc.v:142808.19-142808.99" + wire $gt$libresoc.v:142808$6472_Y + attribute \src "libresoc.v:142809.19-142809.99" + wire $gt$libresoc.v:142809$6473_Y + attribute \src "libresoc.v:142810.19-142810.99" + wire $gt$libresoc.v:142810$6474_Y + attribute \src "libresoc.v:142811.18-142811.97" + wire $gt$libresoc.v:142811$6475_Y + attribute \src "libresoc.v:142812.18-142812.97" + wire $gt$libresoc.v:142812$6476_Y + attribute \src "libresoc.v:142813.18-142813.97" + wire $gt$libresoc.v:142813$6477_Y + attribute \src "libresoc.v:142814.17-142814.96" + wire $gt$libresoc.v:142814$6478_Y + attribute \src "libresoc.v:142815.18-142815.97" + wire $gt$libresoc.v:142815$6479_Y + attribute \src "libresoc.v:142816.18-142816.97" + wire $gt$libresoc.v:142816$6480_Y + attribute \src "libresoc.v:142817.18-142817.97" + wire $gt$libresoc.v:142817$6481_Y + attribute \src "libresoc.v:142818.18-142818.97" + wire $gt$libresoc.v:142818$6482_Y + attribute \src "libresoc.v:142819.18-142819.97" + wire $gt$libresoc.v:142819$6483_Y + attribute \src "libresoc.v:142820.18-142820.97" + wire $gt$libresoc.v:142820$6484_Y + attribute \src "libresoc.v:142821.18-142821.97" + wire $gt$libresoc.v:142821$6485_Y + attribute \src "libresoc.v:142822.18-142822.98" + wire $gt$libresoc.v:142822$6486_Y + attribute \src "libresoc.v:142823.18-142823.98" + wire $gt$libresoc.v:142823$6487_Y + attribute \src "libresoc.v:142824.18-142824.98" + wire $gt$libresoc.v:142824$6488_Y + attribute \src "libresoc.v:142825.17-142825.96" + wire $gt$libresoc.v:142825$6489_Y + attribute \src "libresoc.v:142826.18-142826.98" + wire $gt$libresoc.v:142826$6490_Y + attribute \src "libresoc.v:142827.18-142827.98" + wire $gt$libresoc.v:142827$6491_Y + attribute \src "libresoc.v:142828.18-142828.98" + wire $gt$libresoc.v:142828$6492_Y + attribute \src "libresoc.v:142829.18-142829.98" + wire $gt$libresoc.v:142829$6493_Y + attribute \src "libresoc.v:142830.18-142830.98" + wire $gt$libresoc.v:142830$6494_Y + attribute \src "libresoc.v:142831.18-142831.98" + wire $gt$libresoc.v:142831$6495_Y + attribute \src "libresoc.v:142832.18-142832.98" + wire $gt$libresoc.v:142832$6496_Y + attribute \src "libresoc.v:142833.18-142833.98" + wire $gt$libresoc.v:142833$6497_Y + attribute \src "libresoc.v:142834.18-142834.98" + wire $gt$libresoc.v:142834$6498_Y + attribute \src "libresoc.v:142835.18-142835.98" + wire $gt$libresoc.v:142835$6499_Y + attribute \src "libresoc.v:142836.17-142836.96" + wire $gt$libresoc.v:142836$6500_Y + attribute \src "libresoc.v:142837.18-142837.98" + wire $gt$libresoc.v:142837$6501_Y + attribute \src "libresoc.v:142838.18-142838.98" + wire $gt$libresoc.v:142838$6502_Y + attribute \src "libresoc.v:142839.18-142839.98" + wire $gt$libresoc.v:142839$6503_Y + attribute \src "libresoc.v:142840.18-142840.98" + wire $gt$libresoc.v:142840$6504_Y + attribute \src "libresoc.v:142841.18-142841.98" + wire $gt$libresoc.v:142841$6505_Y + attribute \src "libresoc.v:142842.18-142842.98" + wire $gt$libresoc.v:142842$6506_Y + attribute \src "libresoc.v:142843.18-142843.98" + wire $gt$libresoc.v:142843$6507_Y + attribute \src "libresoc.v:142844.18-142844.98" + wire $gt$libresoc.v:142844$6508_Y + attribute \src "libresoc.v:142845.18-142845.98" + wire $gt$libresoc.v:142845$6509_Y + attribute \src "libresoc.v:142846.18-142846.98" + wire $gt$libresoc.v:142846$6510_Y + attribute \src "libresoc.v:142847.17-142847.96" + wire $gt$libresoc.v:142847$6511_Y + attribute \src "libresoc.v:142848.18-142848.98" + wire $gt$libresoc.v:142848$6512_Y + attribute \src "libresoc.v:142849.18-142849.98" + wire $gt$libresoc.v:142849$6513_Y + attribute \src "libresoc.v:142850.18-142850.98" + wire $gt$libresoc.v:142850$6514_Y + attribute \src "libresoc.v:142851.18-142851.98" + wire $gt$libresoc.v:142851$6515_Y + attribute \src "libresoc.v:142852.18-142852.98" + wire $gt$libresoc.v:142852$6516_Y + attribute \src "libresoc.v:142853.18-142853.98" + wire $gt$libresoc.v:142853$6517_Y + attribute \src "libresoc.v:142854.18-142854.98" + wire $gt$libresoc.v:142854$6518_Y + attribute \src "libresoc.v:142855.18-142855.98" + wire $gt$libresoc.v:142855$6519_Y + attribute \src "libresoc.v:142856.18-142856.98" + wire $gt$libresoc.v:142856$6520_Y + attribute \src "libresoc.v:142857.18-142857.98" + wire $gt$libresoc.v:142857$6521_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -229848,14 +229644,14 @@ module \left_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:142864.7-142864.15" + attribute \src "libresoc.v:142660.7-142660.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142998$6458 + cell $gt $gt$libresoc.v:142794$6458 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229863,10 +229659,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:142998$6458_Y + connect \Y $gt$libresoc.v:142794$6458_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142999$6459 + cell $gt $gt$libresoc.v:142795$6459 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229874,10 +229670,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:142999$6459_Y + connect \Y $gt$libresoc.v:142795$6459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143000$6460 + cell $gt $gt$libresoc.v:142796$6460 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229885,10 +229681,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:143000$6460_Y + connect \Y $gt$libresoc.v:142796$6460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143001$6461 + cell $gt $gt$libresoc.v:142797$6461 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229896,10 +229692,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:143001$6461_Y + connect \Y $gt$libresoc.v:142797$6461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143002$6462 + cell $gt $gt$libresoc.v:142798$6462 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229907,10 +229703,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:143002$6462_Y + connect \Y $gt$libresoc.v:142798$6462_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143003$6463 + cell $gt $gt$libresoc.v:142799$6463 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229918,10 +229714,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:143003$6463_Y + connect \Y $gt$libresoc.v:142799$6463_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143004$6464 + cell $gt $gt$libresoc.v:142800$6464 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229929,10 +229725,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:143004$6464_Y + connect \Y $gt$libresoc.v:142800$6464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143005$6465 + cell $gt $gt$libresoc.v:142801$6465 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229940,10 +229736,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:143005$6465_Y + connect \Y $gt$libresoc.v:142801$6465_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143006$6466 + cell $gt $gt$libresoc.v:142802$6466 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229951,10 +229747,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:143006$6466_Y + connect \Y $gt$libresoc.v:142802$6466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143007$6467 + cell $gt $gt$libresoc.v:142803$6467 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229962,10 +229758,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:143007$6467_Y + connect \Y $gt$libresoc.v:142803$6467_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143008$6468 + cell $gt $gt$libresoc.v:142804$6468 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229973,10 +229769,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:143008$6468_Y + connect \Y $gt$libresoc.v:142804$6468_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143009$6469 + cell $gt $gt$libresoc.v:142805$6469 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229984,10 +229780,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:143009$6469_Y + connect \Y $gt$libresoc.v:142805$6469_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143010$6470 + cell $gt $gt$libresoc.v:142806$6470 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -229995,10 +229791,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:143010$6470_Y + connect \Y $gt$libresoc.v:142806$6470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143011$6471 + cell $gt $gt$libresoc.v:142807$6471 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230006,10 +229802,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:143011$6471_Y + connect \Y $gt$libresoc.v:142807$6471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143012$6472 + cell $gt $gt$libresoc.v:142808$6472 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230017,10 +229813,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:143012$6472_Y + connect \Y $gt$libresoc.v:142808$6472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143013$6473 + cell $gt $gt$libresoc.v:142809$6473 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230028,10 +229824,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:143013$6473_Y + connect \Y $gt$libresoc.v:142809$6473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143014$6474 + cell $gt $gt$libresoc.v:142810$6474 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230039,10 +229835,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:143014$6474_Y + connect \Y $gt$libresoc.v:142810$6474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143015$6475 + cell $gt $gt$libresoc.v:142811$6475 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230050,10 +229846,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:143015$6475_Y + connect \Y $gt$libresoc.v:142811$6475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143016$6476 + cell $gt $gt$libresoc.v:142812$6476 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230061,10 +229857,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:143016$6476_Y + connect \Y $gt$libresoc.v:142812$6476_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143017$6477 + cell $gt $gt$libresoc.v:142813$6477 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230072,10 +229868,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:143017$6477_Y + connect \Y $gt$libresoc.v:142813$6477_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143018$6478 + cell $gt $gt$libresoc.v:142814$6478 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230083,10 +229879,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:143018$6478_Y + connect \Y $gt$libresoc.v:142814$6478_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143019$6479 + cell $gt $gt$libresoc.v:142815$6479 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230094,10 +229890,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:143019$6479_Y + connect \Y $gt$libresoc.v:142815$6479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143020$6480 + cell $gt $gt$libresoc.v:142816$6480 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230105,10 +229901,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:143020$6480_Y + connect \Y $gt$libresoc.v:142816$6480_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143021$6481 + cell $gt $gt$libresoc.v:142817$6481 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230116,10 +229912,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:143021$6481_Y + connect \Y $gt$libresoc.v:142817$6481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143022$6482 + cell $gt $gt$libresoc.v:142818$6482 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230127,10 +229923,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:143022$6482_Y + connect \Y $gt$libresoc.v:142818$6482_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143023$6483 + cell $gt $gt$libresoc.v:142819$6483 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230138,10 +229934,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:143023$6483_Y + connect \Y $gt$libresoc.v:142819$6483_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143024$6484 + cell $gt $gt$libresoc.v:142820$6484 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230149,10 +229945,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:143024$6484_Y + connect \Y $gt$libresoc.v:142820$6484_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143025$6485 + cell $gt $gt$libresoc.v:142821$6485 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230160,10 +229956,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:143025$6485_Y + connect \Y $gt$libresoc.v:142821$6485_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143026$6486 + cell $gt $gt$libresoc.v:142822$6486 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230171,10 +229967,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:143026$6486_Y + connect \Y $gt$libresoc.v:142822$6486_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143027$6487 + cell $gt $gt$libresoc.v:142823$6487 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230182,10 +229978,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:143027$6487_Y + connect \Y $gt$libresoc.v:142823$6487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143028$6488 + cell $gt $gt$libresoc.v:142824$6488 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230193,10 +229989,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:143028$6488_Y + connect \Y $gt$libresoc.v:142824$6488_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143029$6489 + cell $gt $gt$libresoc.v:142825$6489 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230204,10 +230000,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:143029$6489_Y + connect \Y $gt$libresoc.v:142825$6489_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143030$6490 + cell $gt $gt$libresoc.v:142826$6490 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230215,10 +230011,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:143030$6490_Y + connect \Y $gt$libresoc.v:142826$6490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143031$6491 + cell $gt $gt$libresoc.v:142827$6491 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230226,10 +230022,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:143031$6491_Y + connect \Y $gt$libresoc.v:142827$6491_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143032$6492 + cell $gt $gt$libresoc.v:142828$6492 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230237,10 +230033,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:143032$6492_Y + connect \Y $gt$libresoc.v:142828$6492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143033$6493 + cell $gt $gt$libresoc.v:142829$6493 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230248,10 +230044,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:143033$6493_Y + connect \Y $gt$libresoc.v:142829$6493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143034$6494 + cell $gt $gt$libresoc.v:142830$6494 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230259,10 +230055,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:143034$6494_Y + connect \Y $gt$libresoc.v:142830$6494_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143035$6495 + cell $gt $gt$libresoc.v:142831$6495 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230270,10 +230066,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:143035$6495_Y + connect \Y $gt$libresoc.v:142831$6495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143036$6496 + cell $gt $gt$libresoc.v:142832$6496 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230281,10 +230077,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:143036$6496_Y + connect \Y $gt$libresoc.v:142832$6496_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143037$6497 + cell $gt $gt$libresoc.v:142833$6497 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230292,10 +230088,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:143037$6497_Y + connect \Y $gt$libresoc.v:142833$6497_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143038$6498 + cell $gt $gt$libresoc.v:142834$6498 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230303,10 +230099,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:143038$6498_Y + connect \Y $gt$libresoc.v:142834$6498_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143039$6499 + cell $gt $gt$libresoc.v:142835$6499 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230314,10 +230110,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:143039$6499_Y + connect \Y $gt$libresoc.v:142835$6499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143040$6500 + cell $gt $gt$libresoc.v:142836$6500 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230325,10 +230121,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:143040$6500_Y + connect \Y $gt$libresoc.v:142836$6500_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143041$6501 + cell $gt $gt$libresoc.v:142837$6501 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230336,10 +230132,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:143041$6501_Y + connect \Y $gt$libresoc.v:142837$6501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143042$6502 + cell $gt $gt$libresoc.v:142838$6502 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230347,10 +230143,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:143042$6502_Y + connect \Y $gt$libresoc.v:142838$6502_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143043$6503 + cell $gt $gt$libresoc.v:142839$6503 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230358,10 +230154,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:143043$6503_Y + connect \Y $gt$libresoc.v:142839$6503_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143044$6504 + cell $gt $gt$libresoc.v:142840$6504 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230369,10 +230165,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:143044$6504_Y + connect \Y $gt$libresoc.v:142840$6504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143045$6505 + cell $gt $gt$libresoc.v:142841$6505 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230380,10 +230176,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:143045$6505_Y + connect \Y $gt$libresoc.v:142841$6505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143046$6506 + cell $gt $gt$libresoc.v:142842$6506 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230391,10 +230187,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:143046$6506_Y + connect \Y $gt$libresoc.v:142842$6506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143047$6507 + cell $gt $gt$libresoc.v:142843$6507 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230402,10 +230198,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:143047$6507_Y + connect \Y $gt$libresoc.v:142843$6507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143048$6508 + cell $gt $gt$libresoc.v:142844$6508 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230413,10 +230209,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:143048$6508_Y + connect \Y $gt$libresoc.v:142844$6508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143049$6509 + cell $gt $gt$libresoc.v:142845$6509 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230424,10 +230220,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:143049$6509_Y + connect \Y $gt$libresoc.v:142845$6509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143050$6510 + cell $gt $gt$libresoc.v:142846$6510 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230435,10 +230231,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:143050$6510_Y + connect \Y $gt$libresoc.v:142846$6510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143051$6511 + cell $gt $gt$libresoc.v:142847$6511 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230446,10 +230242,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:143051$6511_Y + connect \Y $gt$libresoc.v:142847$6511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143052$6512 + cell $gt $gt$libresoc.v:142848$6512 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230457,10 +230253,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:143052$6512_Y + connect \Y $gt$libresoc.v:142848$6512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143053$6513 + cell $gt $gt$libresoc.v:142849$6513 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230468,10 +230264,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:143053$6513_Y + connect \Y $gt$libresoc.v:142849$6513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143054$6514 + cell $gt $gt$libresoc.v:142850$6514 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230479,10 +230275,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:143054$6514_Y + connect \Y $gt$libresoc.v:142850$6514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143055$6515 + cell $gt $gt$libresoc.v:142851$6515 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230490,10 +230286,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:143055$6515_Y + connect \Y $gt$libresoc.v:142851$6515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143056$6516 + cell $gt $gt$libresoc.v:142852$6516 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230501,10 +230297,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:143056$6516_Y + connect \Y $gt$libresoc.v:142852$6516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143057$6517 + cell $gt $gt$libresoc.v:142853$6517 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230512,10 +230308,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:143057$6517_Y + connect \Y $gt$libresoc.v:142853$6517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143058$6518 + cell $gt $gt$libresoc.v:142854$6518 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230523,10 +230319,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:143058$6518_Y + connect \Y $gt$libresoc.v:142854$6518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143059$6519 + cell $gt $gt$libresoc.v:142855$6519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230534,10 +230330,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:143059$6519_Y + connect \Y $gt$libresoc.v:142855$6519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143060$6520 + cell $gt $gt$libresoc.v:142856$6520 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230545,10 +230341,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:143060$6520_Y + connect \Y $gt$libresoc.v:142856$6520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:143061$6521 + cell $gt $gt$libresoc.v:142857$6521 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230556,18 +230352,18 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:143061$6521_Y + connect \Y $gt$libresoc.v:142857$6521_Y end - attribute \src "libresoc.v:142864.7-142864.20" - process $proc$libresoc.v:142864$6523 + attribute \src "libresoc.v:142660.7-142660.20" + process $proc$libresoc.v:142660$6523 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143062.3-143449.6" - process $proc$libresoc.v:143062$6522 + attribute \src "libresoc.v:142858.3-143245.6" + process $proc$libresoc.v:142858$6522 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -230634,9 +230430,9 @@ module \left_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:143063.5-143063.29" + attribute \src "libresoc.v:142859.5-142859.29" switch \initial - attribute \src "libresoc.v:143063.9-143063.17" + attribute \src "libresoc.v:142859.9-142859.17" case 1'1 case end @@ -231219,86 +231015,86 @@ module \left_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:142998$6458_Y - connect \$99 $gt$libresoc.v:142999$6459_Y - connect \$101 $gt$libresoc.v:143000$6460_Y - connect \$103 $gt$libresoc.v:143001$6461_Y - connect \$105 $gt$libresoc.v:143002$6462_Y - connect \$107 $gt$libresoc.v:143003$6463_Y - connect \$109 $gt$libresoc.v:143004$6464_Y - connect \$111 $gt$libresoc.v:143005$6465_Y - connect \$113 $gt$libresoc.v:143006$6466_Y - connect \$115 $gt$libresoc.v:143007$6467_Y - connect \$117 $gt$libresoc.v:143008$6468_Y - connect \$11 $gt$libresoc.v:143009$6469_Y - connect \$119 $gt$libresoc.v:143010$6470_Y - connect \$121 $gt$libresoc.v:143011$6471_Y - connect \$123 $gt$libresoc.v:143012$6472_Y - connect \$125 $gt$libresoc.v:143013$6473_Y - connect \$127 $gt$libresoc.v:143014$6474_Y - connect \$13 $gt$libresoc.v:143015$6475_Y - connect \$15 $gt$libresoc.v:143016$6476_Y - connect \$17 $gt$libresoc.v:143017$6477_Y - connect \$1 $gt$libresoc.v:143018$6478_Y - connect \$19 $gt$libresoc.v:143019$6479_Y - connect \$21 $gt$libresoc.v:143020$6480_Y - connect \$23 $gt$libresoc.v:143021$6481_Y - connect \$25 $gt$libresoc.v:143022$6482_Y - connect \$27 $gt$libresoc.v:143023$6483_Y - connect \$29 $gt$libresoc.v:143024$6484_Y - connect \$31 $gt$libresoc.v:143025$6485_Y - connect \$33 $gt$libresoc.v:143026$6486_Y - connect \$35 $gt$libresoc.v:143027$6487_Y - connect \$37 $gt$libresoc.v:143028$6488_Y - connect \$3 $gt$libresoc.v:143029$6489_Y - connect \$39 $gt$libresoc.v:143030$6490_Y - connect \$41 $gt$libresoc.v:143031$6491_Y - connect \$43 $gt$libresoc.v:143032$6492_Y - connect \$45 $gt$libresoc.v:143033$6493_Y - connect \$47 $gt$libresoc.v:143034$6494_Y - connect \$49 $gt$libresoc.v:143035$6495_Y - connect \$51 $gt$libresoc.v:143036$6496_Y - connect \$53 $gt$libresoc.v:143037$6497_Y - connect \$55 $gt$libresoc.v:143038$6498_Y - connect \$57 $gt$libresoc.v:143039$6499_Y - connect \$5 $gt$libresoc.v:143040$6500_Y - connect \$59 $gt$libresoc.v:143041$6501_Y - connect \$61 $gt$libresoc.v:143042$6502_Y - connect \$63 $gt$libresoc.v:143043$6503_Y - connect \$65 $gt$libresoc.v:143044$6504_Y - connect \$67 $gt$libresoc.v:143045$6505_Y - connect \$69 $gt$libresoc.v:143046$6506_Y - connect \$71 $gt$libresoc.v:143047$6507_Y - connect \$73 $gt$libresoc.v:143048$6508_Y - connect \$75 $gt$libresoc.v:143049$6509_Y - connect \$77 $gt$libresoc.v:143050$6510_Y - connect \$7 $gt$libresoc.v:143051$6511_Y - connect \$79 $gt$libresoc.v:143052$6512_Y - connect \$81 $gt$libresoc.v:143053$6513_Y - connect \$83 $gt$libresoc.v:143054$6514_Y - connect \$85 $gt$libresoc.v:143055$6515_Y - connect \$87 $gt$libresoc.v:143056$6516_Y - connect \$89 $gt$libresoc.v:143057$6517_Y - connect \$91 $gt$libresoc.v:143058$6518_Y - connect \$93 $gt$libresoc.v:143059$6519_Y - connect \$95 $gt$libresoc.v:143060$6520_Y - connect \$97 $gt$libresoc.v:143061$6521_Y + connect \$9 $gt$libresoc.v:142794$6458_Y + connect \$99 $gt$libresoc.v:142795$6459_Y + connect \$101 $gt$libresoc.v:142796$6460_Y + connect \$103 $gt$libresoc.v:142797$6461_Y + connect \$105 $gt$libresoc.v:142798$6462_Y + connect \$107 $gt$libresoc.v:142799$6463_Y + connect \$109 $gt$libresoc.v:142800$6464_Y + connect \$111 $gt$libresoc.v:142801$6465_Y + connect \$113 $gt$libresoc.v:142802$6466_Y + connect \$115 $gt$libresoc.v:142803$6467_Y + connect \$117 $gt$libresoc.v:142804$6468_Y + connect \$11 $gt$libresoc.v:142805$6469_Y + connect \$119 $gt$libresoc.v:142806$6470_Y + connect \$121 $gt$libresoc.v:142807$6471_Y + connect \$123 $gt$libresoc.v:142808$6472_Y + connect \$125 $gt$libresoc.v:142809$6473_Y + connect \$127 $gt$libresoc.v:142810$6474_Y + connect \$13 $gt$libresoc.v:142811$6475_Y + connect \$15 $gt$libresoc.v:142812$6476_Y + connect \$17 $gt$libresoc.v:142813$6477_Y + connect \$1 $gt$libresoc.v:142814$6478_Y + connect \$19 $gt$libresoc.v:142815$6479_Y + connect \$21 $gt$libresoc.v:142816$6480_Y + connect \$23 $gt$libresoc.v:142817$6481_Y + connect \$25 $gt$libresoc.v:142818$6482_Y + connect \$27 $gt$libresoc.v:142819$6483_Y + connect \$29 $gt$libresoc.v:142820$6484_Y + connect \$31 $gt$libresoc.v:142821$6485_Y + connect \$33 $gt$libresoc.v:142822$6486_Y + connect \$35 $gt$libresoc.v:142823$6487_Y + connect \$37 $gt$libresoc.v:142824$6488_Y + connect \$3 $gt$libresoc.v:142825$6489_Y + connect \$39 $gt$libresoc.v:142826$6490_Y + connect \$41 $gt$libresoc.v:142827$6491_Y + connect \$43 $gt$libresoc.v:142828$6492_Y + connect \$45 $gt$libresoc.v:142829$6493_Y + connect \$47 $gt$libresoc.v:142830$6494_Y + connect \$49 $gt$libresoc.v:142831$6495_Y + connect \$51 $gt$libresoc.v:142832$6496_Y + connect \$53 $gt$libresoc.v:142833$6497_Y + connect \$55 $gt$libresoc.v:142834$6498_Y + connect \$57 $gt$libresoc.v:142835$6499_Y + connect \$5 $gt$libresoc.v:142836$6500_Y + connect \$59 $gt$libresoc.v:142837$6501_Y + connect \$61 $gt$libresoc.v:142838$6502_Y + connect \$63 $gt$libresoc.v:142839$6503_Y + connect \$65 $gt$libresoc.v:142840$6504_Y + connect \$67 $gt$libresoc.v:142841$6505_Y + connect \$69 $gt$libresoc.v:142842$6506_Y + connect \$71 $gt$libresoc.v:142843$6507_Y + connect \$73 $gt$libresoc.v:142844$6508_Y + connect \$75 $gt$libresoc.v:142845$6509_Y + connect \$77 $gt$libresoc.v:142846$6510_Y + connect \$7 $gt$libresoc.v:142847$6511_Y + connect \$79 $gt$libresoc.v:142848$6512_Y + connect \$81 $gt$libresoc.v:142849$6513_Y + connect \$83 $gt$libresoc.v:142850$6514_Y + connect \$85 $gt$libresoc.v:142851$6515_Y + connect \$87 $gt$libresoc.v:142852$6516_Y + connect \$89 $gt$libresoc.v:142853$6517_Y + connect \$91 $gt$libresoc.v:142854$6518_Y + connect \$93 $gt$libresoc.v:142855$6519_Y + connect \$95 $gt$libresoc.v:142856$6520_Y + connect \$97 $gt$libresoc.v:142857$6521_Y end -attribute \src "libresoc.v:143454.1-143483.10" +attribute \src "libresoc.v:143250.1-143279.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" attribute \generator "nMigen" module \lenexp - attribute \src "libresoc.v:143478.17-143478.101" - wire width 64 $extend$libresoc.v:143478$6527_Y - attribute \src "libresoc.v:143478.17-143478.101" - wire width 64 $pos$libresoc.v:143478$6528_Y - attribute \src "libresoc.v:143475.17-143475.111" - wire width 20 $sshl$libresoc.v:143475$6524_Y - attribute \src "libresoc.v:143477.17-143477.113" - wire width 32 $sshl$libresoc.v:143477$6526_Y - attribute \src "libresoc.v:143476.17-143476.107" - wire width 21 $sub$libresoc.v:143476$6525_Y + attribute \src "libresoc.v:143274.17-143274.101" + wire width 64 $extend$libresoc.v:143274$6527_Y + attribute \src "libresoc.v:143274.17-143274.101" + wire width 64 $pos$libresoc.v:143274$6528_Y + attribute \src "libresoc.v:143271.17-143271.111" + wire width 20 $sshl$libresoc.v:143271$6524_Y + attribute \src "libresoc.v:143273.17-143273.113" + wire width 32 $sshl$libresoc.v:143273$6526_Y + attribute \src "libresoc.v:143272.17-143272.107" + wire width 21 $sub$libresoc.v:143272$6525_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 21 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" @@ -231320,23 +231116,23 @@ module \lenexp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" wire width 176 output 3 \rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$libresoc.v:143478$6527 + cell $pos $extend$libresoc.v:143274$6527 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$7 - connect \Y $extend$libresoc.v:143478$6527_Y + connect \Y $extend$libresoc.v:143274$6527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$libresoc.v:143478$6528 + cell $pos $pos$libresoc.v:143274$6528 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:143478$6527_Y - connect \Y $pos$libresoc.v:143478$6528_Y + connect \A $extend$libresoc.v:143274$6527_Y + connect \Y $pos$libresoc.v:143274$6528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$libresoc.v:143475$6524 + cell $sshl $sshl$libresoc.v:143271$6524 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -231344,10 +231140,10 @@ module \lenexp parameter \Y_WIDTH 20 connect \A 5'00001 connect \B \len_i - connect \Y $sshl$libresoc.v:143475$6524_Y + connect \Y $sshl$libresoc.v:143271$6524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$libresoc.v:143477$6526 + cell $sshl $sshl$libresoc.v:143273$6526 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 @@ -231355,10 +231151,10 @@ module \lenexp parameter \Y_WIDTH 32 connect \A \binlen connect \B \addr_i - connect \Y $sshl$libresoc.v:143477$6526_Y + connect \Y $sshl$libresoc.v:143273$6526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$libresoc.v:143476$6525 + cell $sub $sub$libresoc.v:143272$6525 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -231366,48 +231162,48 @@ module \lenexp parameter \Y_WIDTH 21 connect \A \$2 connect \B 1'1 - connect \Y $sub$libresoc.v:143476$6525_Y + connect \Y $sub$libresoc.v:143272$6525_Y end - connect \$2 $sshl$libresoc.v:143475$6524_Y - connect \$4 $sub$libresoc.v:143476$6525_Y - connect \$7 $sshl$libresoc.v:143477$6526_Y - connect \$6 $pos$libresoc.v:143478$6528_Y + connect \$2 $sshl$libresoc.v:143271$6524_Y + connect \$4 $sub$libresoc.v:143272$6525_Y + connect \$7 $sshl$libresoc.v:143273$6526_Y + connect \$6 $pos$libresoc.v:143274$6528_Y connect \$1 \$4 connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } connect \lexp_o \$6 connect \binlen \$4 [16:0] end -attribute \src "libresoc.v:143487.1-143545.10" +attribute \src "libresoc.v:143283.1-143341.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" attribute \generator "nMigen" module \lod_l - attribute \src "libresoc.v:143488.7-143488.20" + attribute \src "libresoc.v:143284.7-143284.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143533.3-143541.6" + attribute \src "libresoc.v:143329.3-143337.6" wire $0\q_int$next[0:0]$6539 - attribute \src "libresoc.v:143531.3-143532.27" + attribute \src "libresoc.v:143327.3-143328.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:143533.3-143541.6" + attribute \src "libresoc.v:143329.3-143337.6" wire $1\q_int$next[0:0]$6540 - attribute \src "libresoc.v:143510.7-143510.19" + attribute \src "libresoc.v:143306.7-143306.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:143523.17-143523.96" - wire $and$libresoc.v:143523$6529_Y - attribute \src "libresoc.v:143528.17-143528.96" - wire $and$libresoc.v:143528$6534_Y - attribute \src "libresoc.v:143525.18-143525.93" - wire $not$libresoc.v:143525$6531_Y - attribute \src "libresoc.v:143527.17-143527.92" - wire $not$libresoc.v:143527$6533_Y - attribute \src "libresoc.v:143530.17-143530.92" - wire $not$libresoc.v:143530$6536_Y - attribute \src "libresoc.v:143524.18-143524.98" - wire $or$libresoc.v:143524$6530_Y - attribute \src "libresoc.v:143526.18-143526.99" - wire $or$libresoc.v:143526$6532_Y - attribute \src "libresoc.v:143529.17-143529.97" - wire $or$libresoc.v:143529$6535_Y + attribute \src "libresoc.v:143319.17-143319.96" + wire $and$libresoc.v:143319$6529_Y + attribute \src "libresoc.v:143324.17-143324.96" + wire $and$libresoc.v:143324$6534_Y + attribute \src "libresoc.v:143321.18-143321.93" + wire $not$libresoc.v:143321$6531_Y + attribute \src "libresoc.v:143323.17-143323.92" + wire $not$libresoc.v:143323$6533_Y + attribute \src "libresoc.v:143326.17-143326.92" + wire $not$libresoc.v:143326$6536_Y + attribute \src "libresoc.v:143320.18-143320.98" + wire $or$libresoc.v:143320$6530_Y + attribute \src "libresoc.v:143322.18-143322.99" + wire $or$libresoc.v:143322$6532_Y + attribute \src "libresoc.v:143325.17-143325.97" + wire $or$libresoc.v:143325$6535_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -231424,11 +231220,11 @@ module \lod_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:143488.7-143488.15" + attribute \src "libresoc.v:143284.7-143284.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -231445,7 +231241,7 @@ module \lod_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:143523$6529 + cell $and $and$libresoc.v:143319$6529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231453,10 +231249,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:143523$6529_Y + connect \Y $and$libresoc.v:143319$6529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:143528$6534 + cell $and $and$libresoc.v:143324$6534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231464,34 +231260,34 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:143528$6534_Y + connect \Y $and$libresoc.v:143324$6534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:143525$6531 + cell $not $not$libresoc.v:143321$6531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lod - connect \Y $not$libresoc.v:143525$6531_Y + connect \Y $not$libresoc.v:143321$6531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:143527$6533 + cell $not $not$libresoc.v:143323$6533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:143527$6533_Y + connect \Y $not$libresoc.v:143323$6533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:143530$6536 + cell $not $not$libresoc.v:143326$6536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:143530$6536_Y + connect \Y $not$libresoc.v:143326$6536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:143524$6530 + cell $or $or$libresoc.v:143320$6530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231499,10 +231295,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lod - connect \Y $or$libresoc.v:143524$6530_Y + connect \Y $or$libresoc.v:143320$6530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:143526$6532 + cell $or $or$libresoc.v:143322$6532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231510,10 +231306,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_lod connect \B \q_int - connect \Y $or$libresoc.v:143526$6532_Y + connect \Y $or$libresoc.v:143322$6532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:143529$6535 + cell $or $or$libresoc.v:143325$6535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231521,39 +231317,39 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lod - connect \Y $or$libresoc.v:143529$6535_Y + connect \Y $or$libresoc.v:143325$6535_Y end - attribute \src "libresoc.v:143488.7-143488.20" - process $proc$libresoc.v:143488$6541 + attribute \src "libresoc.v:143284.7-143284.20" + process $proc$libresoc.v:143284$6541 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143510.7-143510.19" - process $proc$libresoc.v:143510$6542 + attribute \src "libresoc.v:143306.7-143306.19" + process $proc$libresoc.v:143306$6542 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:143531.3-143532.27" - process $proc$libresoc.v:143531$6537 + attribute \src "libresoc.v:143327.3-143328.27" + process $proc$libresoc.v:143327$6537 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:143533.3-143541.6" - process $proc$libresoc.v:143533$6538 + attribute \src "libresoc.v:143329.3-143337.6" + process $proc$libresoc.v:143329$6538 assign { } { } assign { } { } assign $0\q_int$next[0:0]$6539 $1\q_int$next[0:0]$6540 - attribute \src "libresoc.v:143534.5-143534.29" + attribute \src "libresoc.v:143330.5-143330.29" switch \initial - attribute \src "libresoc.v:143534.9-143534.17" + attribute \src "libresoc.v:143330.9-143330.17" case 1'1 case end @@ -231569,487 +231365,487 @@ module \lod_l sync always update \q_int$next $0\q_int$next[0:0]$6539 end - connect \$9 $and$libresoc.v:143523$6529_Y - connect \$11 $or$libresoc.v:143524$6530_Y - connect \$13 $not$libresoc.v:143525$6531_Y - connect \$15 $or$libresoc.v:143526$6532_Y - connect \$1 $not$libresoc.v:143527$6533_Y - connect \$3 $and$libresoc.v:143528$6534_Y - connect \$5 $or$libresoc.v:143529$6535_Y - connect \$7 $not$libresoc.v:143530$6536_Y + connect \$9 $and$libresoc.v:143319$6529_Y + connect \$11 $or$libresoc.v:143320$6530_Y + connect \$13 $not$libresoc.v:143321$6531_Y + connect \$15 $or$libresoc.v:143322$6532_Y + connect \$1 $not$libresoc.v:143323$6533_Y + connect \$3 $and$libresoc.v:143324$6534_Y + connect \$5 $or$libresoc.v:143325$6535_Y + connect \$7 $not$libresoc.v:143326$6536_Y connect \qlq_lod \$15 connect \qn_lod \$13 connect \q_lod \$11 end -attribute \src "libresoc.v:143549.1-144669.10" +attribute \src "libresoc.v:143345.1-144465.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" attribute \generator "nMigen" module \logical0 - attribute \src "libresoc.v:144294.3-144295.24" + attribute \src "libresoc.v:144090.3-144091.24" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:144292.3-144293.44" + attribute \src "libresoc.v:144088.3-144089.44" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:144599.3-144607.6" + attribute \src "libresoc.v:144395.3-144403.6" wire $0\alu_l_r_alu$next[0:0]$6743 - attribute \src "libresoc.v:144216.3-144217.39" + attribute \src "libresoc.v:144012.3-144013.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6672 - attribute \src "libresoc.v:144266.3-144267.83" + attribute \src "libresoc.v:144062.3-144063.83" wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6673 - attribute \src "libresoc.v:144236.3-144237.81" + attribute \src "libresoc.v:144032.3-144033.81" wire width 14 $0\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6674 - attribute \src "libresoc.v:144238.3-144239.95" + attribute \src "libresoc.v:144034.3-144035.95" wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6675 - attribute \src "libresoc.v:144240.3-144241.91" + attribute \src "libresoc.v:144036.3-144037.91" wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6676 - attribute \src "libresoc.v:144254.3-144255.89" + attribute \src "libresoc.v:144050.3-144051.89" wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6677 - attribute \src "libresoc.v:144268.3-144269.75" + attribute \src "libresoc.v:144064.3-144065.75" wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6678 - attribute \src "libresoc.v:144234.3-144235.85" + attribute \src "libresoc.v:144030.3-144031.85" wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6679 - attribute \src "libresoc.v:144250.3-144251.85" + attribute \src "libresoc.v:144046.3-144047.85" wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6680 - attribute \src "libresoc.v:144256.3-144257.87" + attribute \src "libresoc.v:144052.3-144053.87" wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6681 - attribute \src "libresoc.v:144262.3-144263.83" + attribute \src "libresoc.v:144058.3-144059.83" wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6682 - attribute \src "libresoc.v:144264.3-144265.85" + attribute \src "libresoc.v:144060.3-144061.85" wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6683 - attribute \src "libresoc.v:144246.3-144247.79" + attribute \src "libresoc.v:144042.3-144043.79" wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6684 - attribute \src "libresoc.v:144248.3-144249.79" + attribute \src "libresoc.v:144044.3-144045.79" wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6685 - attribute \src "libresoc.v:144260.3-144261.91" + attribute \src "libresoc.v:144056.3-144057.91" wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6686 - attribute \src "libresoc.v:144244.3-144245.79" + attribute \src "libresoc.v:144040.3-144041.79" wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6687 - attribute \src "libresoc.v:144242.3-144243.79" + attribute \src "libresoc.v:144038.3-144039.79" wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6688 - attribute \src "libresoc.v:144258.3-144259.85" + attribute \src "libresoc.v:144054.3-144055.85" wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6689 - attribute \src "libresoc.v:144252.3-144253.79" + attribute \src "libresoc.v:144048.3-144049.79" wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:144590.3-144598.6" + attribute \src "libresoc.v:144386.3-144394.6" wire $0\alui_l_r_alui$next[0:0]$6740 - attribute \src "libresoc.v:144218.3-144219.43" + attribute \src "libresoc.v:144014.3-144015.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:144516.3-144537.6" + attribute \src "libresoc.v:144312.3-144333.6" wire width 64 $0\data_r0__o$next[63:0]$6715 - attribute \src "libresoc.v:144230.3-144231.37" + attribute \src "libresoc.v:144026.3-144027.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:144516.3-144537.6" + attribute \src "libresoc.v:144312.3-144333.6" wire $0\data_r0__o_ok$next[0:0]$6716 - attribute \src "libresoc.v:144232.3-144233.43" + attribute \src "libresoc.v:144028.3-144029.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:144538.3-144559.6" + attribute \src "libresoc.v:144334.3-144355.6" wire width 4 $0\data_r1__cr_a$next[3:0]$6723 - attribute \src "libresoc.v:144226.3-144227.43" + attribute \src "libresoc.v:144022.3-144023.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:144538.3-144559.6" + attribute \src "libresoc.v:144334.3-144355.6" wire $0\data_r1__cr_a_ok$next[0:0]$6724 - attribute \src "libresoc.v:144228.3-144229.49" + attribute \src "libresoc.v:144024.3-144025.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:144608.3-144617.6" + attribute \src "libresoc.v:144404.3-144413.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:144618.3-144627.6" + attribute \src "libresoc.v:144414.3-144423.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:143550.7-143550.20" + attribute \src "libresoc.v:143346.7-143346.20" wire $0\initial[0:0] - attribute \src "libresoc.v:144432.3-144440.6" + attribute \src "libresoc.v:144228.3-144236.6" wire $0\opc_l_r_opc$next[0:0]$6657 - attribute \src "libresoc.v:144278.3-144279.39" + attribute \src "libresoc.v:144074.3-144075.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:144423.3-144431.6" + attribute \src "libresoc.v:144219.3-144227.6" wire $0\opc_l_s_opc$next[0:0]$6654 - attribute \src "libresoc.v:144280.3-144281.39" + attribute \src "libresoc.v:144076.3-144077.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:144628.3-144636.6" + attribute \src "libresoc.v:144424.3-144432.6" wire width 2 $0\prev_wr_go$next[1:0]$6748 - attribute \src "libresoc.v:144290.3-144291.37" + attribute \src "libresoc.v:144086.3-144087.37" wire width 2 $0\prev_wr_go[1:0] - attribute \src "libresoc.v:144377.3-144386.6" + attribute \src "libresoc.v:144173.3-144182.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:144468.3-144476.6" + attribute \src "libresoc.v:144264.3-144272.6" wire width 2 $0\req_l_r_req$next[1:0]$6669 - attribute \src "libresoc.v:144270.3-144271.39" + attribute \src "libresoc.v:144066.3-144067.39" wire width 2 $0\req_l_r_req[1:0] - attribute \src "libresoc.v:144459.3-144467.6" + attribute \src "libresoc.v:144255.3-144263.6" wire width 2 $0\req_l_s_req$next[1:0]$6666 - attribute \src "libresoc.v:144272.3-144273.39" + attribute \src "libresoc.v:144068.3-144069.39" wire width 2 $0\req_l_s_req[1:0] - attribute \src "libresoc.v:144396.3-144404.6" + attribute \src "libresoc.v:144192.3-144200.6" wire $0\rok_l_r_rdok$next[0:0]$6645 - attribute \src "libresoc.v:144286.3-144287.41" + attribute \src "libresoc.v:144082.3-144083.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:144387.3-144395.6" + attribute \src "libresoc.v:144183.3-144191.6" wire $0\rok_l_s_rdok$next[0:0]$6642 - attribute \src "libresoc.v:144288.3-144289.41" + attribute \src "libresoc.v:144084.3-144085.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:144414.3-144422.6" + attribute \src "libresoc.v:144210.3-144218.6" wire $0\rst_l_r_rst$next[0:0]$6651 - attribute \src "libresoc.v:144282.3-144283.39" + attribute \src "libresoc.v:144078.3-144079.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:144405.3-144413.6" + attribute \src "libresoc.v:144201.3-144209.6" wire $0\rst_l_s_rst$next[0:0]$6648 - attribute \src "libresoc.v:144284.3-144285.39" + attribute \src "libresoc.v:144080.3-144081.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:144450.3-144458.6" + attribute \src "libresoc.v:144246.3-144254.6" wire width 3 $0\src_l_r_src$next[2:0]$6663 - attribute \src "libresoc.v:144274.3-144275.39" + attribute \src "libresoc.v:144070.3-144071.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:144441.3-144449.6" + attribute \src "libresoc.v:144237.3-144245.6" wire width 3 $0\src_l_s_src$next[2:0]$6660 - attribute \src "libresoc.v:144276.3-144277.39" + attribute \src "libresoc.v:144072.3-144073.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:144560.3-144569.6" + attribute \src "libresoc.v:144356.3-144365.6" wire width 64 $0\src_r0$next[63:0]$6731 - attribute \src "libresoc.v:144224.3-144225.29" + attribute \src "libresoc.v:144020.3-144021.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:144570.3-144579.6" + attribute \src "libresoc.v:144366.3-144375.6" wire width 64 $0\src_r1$next[63:0]$6734 - attribute \src "libresoc.v:144222.3-144223.29" + attribute \src "libresoc.v:144018.3-144019.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:144580.3-144589.6" + attribute \src "libresoc.v:144376.3-144385.6" wire $0\src_r2$next[0:0]$6737 - attribute \src "libresoc.v:144220.3-144221.29" + attribute \src "libresoc.v:144016.3-144017.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:143668.7-143668.24" + attribute \src "libresoc.v:143464.7-143464.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:143678.7-143678.26" + attribute \src "libresoc.v:143474.7-143474.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:144599.3-144607.6" + attribute \src "libresoc.v:144395.3-144403.6" wire $1\alu_l_r_alu$next[0:0]$6744 - attribute \src "libresoc.v:143686.7-143686.25" + attribute \src "libresoc.v:143482.7-143482.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6690 - attribute \src "libresoc.v:143694.13-143694.53" + attribute \src "libresoc.v:143490.13-143490.53" wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691 - attribute \src "libresoc.v:143713.14-143713.57" + attribute \src "libresoc.v:143509.14-143509.57" wire width 14 $1\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692 - attribute \src "libresoc.v:143717.14-143717.76" + attribute \src "libresoc.v:143513.14-143513.76" wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693 - attribute \src "libresoc.v:143721.7-143721.51" + attribute \src "libresoc.v:143517.7-143517.51" wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6694 - attribute \src "libresoc.v:143729.13-143729.56" + attribute \src "libresoc.v:143525.13-143525.56" wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6695 - attribute \src "libresoc.v:143733.14-143733.51" + attribute \src "libresoc.v:143529.14-143529.51" wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6696 - attribute \src "libresoc.v:143812.13-143812.55" + attribute \src "libresoc.v:143608.13-143608.55" wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6697 - attribute \src "libresoc.v:143816.7-143816.48" + attribute \src "libresoc.v:143612.7-143612.48" wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6698 - attribute \src "libresoc.v:143820.7-143820.49" + attribute \src "libresoc.v:143616.7-143616.49" wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699 - attribute \src "libresoc.v:143824.7-143824.47" + attribute \src "libresoc.v:143620.7-143620.47" wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6700 - attribute \src "libresoc.v:143828.7-143828.48" + attribute \src "libresoc.v:143624.7-143624.48" wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701 - attribute \src "libresoc.v:143832.7-143832.45" + attribute \src "libresoc.v:143628.7-143628.45" wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702 - attribute \src "libresoc.v:143836.7-143836.45" + attribute \src "libresoc.v:143632.7-143632.45" wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6703 - attribute \src "libresoc.v:143840.7-143840.51" + attribute \src "libresoc.v:143636.7-143636.51" wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704 - attribute \src "libresoc.v:143844.7-143844.45" + attribute \src "libresoc.v:143640.7-143640.45" wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705 - attribute \src "libresoc.v:143848.7-143848.45" + attribute \src "libresoc.v:143644.7-143644.45" wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706 - attribute \src "libresoc.v:143852.7-143852.48" + attribute \src "libresoc.v:143648.7-143648.48" wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6707 - attribute \src "libresoc.v:143856.7-143856.45" + attribute \src "libresoc.v:143652.7-143652.45" wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:144590.3-144598.6" + attribute \src "libresoc.v:144386.3-144394.6" wire $1\alui_l_r_alui$next[0:0]$6741 - attribute \src "libresoc.v:143882.7-143882.27" + attribute \src "libresoc.v:143678.7-143678.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:144516.3-144537.6" + attribute \src "libresoc.v:144312.3-144333.6" wire width 64 $1\data_r0__o$next[63:0]$6717 - attribute \src "libresoc.v:143916.14-143916.47" + attribute \src "libresoc.v:143712.14-143712.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:144516.3-144537.6" + attribute \src "libresoc.v:144312.3-144333.6" wire $1\data_r0__o_ok$next[0:0]$6718 - attribute \src "libresoc.v:143920.7-143920.27" + attribute \src "libresoc.v:143716.7-143716.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:144538.3-144559.6" + attribute \src "libresoc.v:144334.3-144355.6" wire width 4 $1\data_r1__cr_a$next[3:0]$6725 - attribute \src "libresoc.v:143924.13-143924.33" + attribute \src "libresoc.v:143720.13-143720.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:144538.3-144559.6" + attribute \src "libresoc.v:144334.3-144355.6" wire $1\data_r1__cr_a_ok$next[0:0]$6726 - attribute \src "libresoc.v:143928.7-143928.30" + attribute \src "libresoc.v:143724.7-143724.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:144608.3-144617.6" + attribute \src "libresoc.v:144404.3-144413.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:144618.3-144627.6" + attribute \src "libresoc.v:144414.3-144423.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:144432.3-144440.6" + attribute \src "libresoc.v:144228.3-144236.6" wire $1\opc_l_r_opc$next[0:0]$6658 - attribute \src "libresoc.v:143942.7-143942.25" + attribute \src "libresoc.v:143738.7-143738.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:144423.3-144431.6" + attribute \src "libresoc.v:144219.3-144227.6" wire $1\opc_l_s_opc$next[0:0]$6655 - attribute \src "libresoc.v:143946.7-143946.25" + attribute \src "libresoc.v:143742.7-143742.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:144628.3-144636.6" + attribute \src "libresoc.v:144424.3-144432.6" wire width 2 $1\prev_wr_go$next[1:0]$6749 - attribute \src "libresoc.v:144080.13-144080.30" + attribute \src "libresoc.v:143876.13-143876.30" wire width 2 $1\prev_wr_go[1:0] - attribute \src "libresoc.v:144377.3-144386.6" + attribute \src "libresoc.v:144173.3-144182.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:144468.3-144476.6" + attribute \src "libresoc.v:144264.3-144272.6" wire width 2 $1\req_l_r_req$next[1:0]$6670 - attribute \src "libresoc.v:144088.13-144088.31" + attribute \src "libresoc.v:143884.13-143884.31" wire width 2 $1\req_l_r_req[1:0] - attribute \src "libresoc.v:144459.3-144467.6" + attribute \src "libresoc.v:144255.3-144263.6" wire width 2 $1\req_l_s_req$next[1:0]$6667 - attribute \src "libresoc.v:144092.13-144092.31" + attribute \src "libresoc.v:143888.13-143888.31" wire width 2 $1\req_l_s_req[1:0] - attribute \src "libresoc.v:144396.3-144404.6" + attribute \src "libresoc.v:144192.3-144200.6" wire $1\rok_l_r_rdok$next[0:0]$6646 - attribute \src "libresoc.v:144104.7-144104.26" + attribute \src "libresoc.v:143900.7-143900.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:144387.3-144395.6" + attribute \src "libresoc.v:144183.3-144191.6" wire $1\rok_l_s_rdok$next[0:0]$6643 - attribute \src "libresoc.v:144108.7-144108.26" + attribute \src "libresoc.v:143904.7-143904.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:144414.3-144422.6" + attribute \src "libresoc.v:144210.3-144218.6" wire $1\rst_l_r_rst$next[0:0]$6652 - attribute \src "libresoc.v:144112.7-144112.25" + attribute \src "libresoc.v:143908.7-143908.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:144405.3-144413.6" + attribute \src "libresoc.v:144201.3-144209.6" wire $1\rst_l_s_rst$next[0:0]$6649 - attribute \src "libresoc.v:144116.7-144116.25" + attribute \src "libresoc.v:143912.7-143912.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:144450.3-144458.6" + attribute \src "libresoc.v:144246.3-144254.6" wire width 3 $1\src_l_r_src$next[2:0]$6664 - attribute \src "libresoc.v:144130.13-144130.31" + attribute \src "libresoc.v:143926.13-143926.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:144441.3-144449.6" + attribute \src "libresoc.v:144237.3-144245.6" wire width 3 $1\src_l_s_src$next[2:0]$6661 - attribute \src "libresoc.v:144134.13-144134.31" + attribute \src "libresoc.v:143930.13-143930.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:144560.3-144569.6" + attribute \src "libresoc.v:144356.3-144365.6" wire width 64 $1\src_r0$next[63:0]$6732 - attribute \src "libresoc.v:144142.14-144142.43" + attribute \src "libresoc.v:143938.14-143938.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:144570.3-144579.6" + attribute \src "libresoc.v:144366.3-144375.6" wire width 64 $1\src_r1$next[63:0]$6735 - attribute \src "libresoc.v:144146.14-144146.43" + attribute \src "libresoc.v:143942.14-143942.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:144580.3-144589.6" + attribute \src "libresoc.v:144376.3-144385.6" wire $1\src_r2$next[0:0]$6738 - attribute \src "libresoc.v:144150.7-144150.20" + attribute \src "libresoc.v:143946.7-143946.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708 - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709 - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710 - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711 - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712 - attribute \src "libresoc.v:144477.3-144515.6" + attribute \src "libresoc.v:144273.3-144311.6" wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713 - attribute \src "libresoc.v:144516.3-144537.6" + attribute \src "libresoc.v:144312.3-144333.6" wire width 64 $2\data_r0__o$next[63:0]$6719 - attribute \src "libresoc.v:144516.3-144537.6" + attribute \src "libresoc.v:144312.3-144333.6" wire $2\data_r0__o_ok$next[0:0]$6720 - attribute \src "libresoc.v:144538.3-144559.6" + attribute \src "libresoc.v:144334.3-144355.6" wire width 4 $2\data_r1__cr_a$next[3:0]$6727 - attribute \src "libresoc.v:144538.3-144559.6" + attribute \src "libresoc.v:144334.3-144355.6" wire $2\data_r1__cr_a_ok$next[0:0]$6728 - attribute \src "libresoc.v:144516.3-144537.6" + attribute \src "libresoc.v:144312.3-144333.6" wire $3\data_r0__o_ok$next[0:0]$6721 - attribute \src "libresoc.v:144538.3-144559.6" + attribute \src "libresoc.v:144334.3-144355.6" wire $3\data_r1__cr_a_ok$next[0:0]$6729 - attribute \src "libresoc.v:144159.17-144159.109" - wire $and$libresoc.v:144159$6543_Y - attribute \src "libresoc.v:144160.18-144160.130" - wire width 3 $and$libresoc.v:144160$6544_Y - attribute \src "libresoc.v:144162.19-144162.114" - wire width 3 $and$libresoc.v:144162$6546_Y - attribute \src "libresoc.v:144163.19-144163.125" - wire $and$libresoc.v:144163$6547_Y - attribute \src "libresoc.v:144164.19-144164.125" - wire $and$libresoc.v:144164$6548_Y - attribute \src "libresoc.v:144165.19-144165.133" - wire width 2 $and$libresoc.v:144165$6549_Y - attribute \src "libresoc.v:144166.19-144166.121" - wire width 2 $and$libresoc.v:144166$6550_Y - attribute \src "libresoc.v:144167.19-144167.127" - wire $and$libresoc.v:144167$6551_Y - attribute \src "libresoc.v:144168.19-144168.127" - wire $and$libresoc.v:144168$6552_Y - attribute \src "libresoc.v:144170.18-144170.98" - wire $and$libresoc.v:144170$6554_Y - attribute \src "libresoc.v:144172.18-144172.100" - wire $and$libresoc.v:144172$6556_Y - attribute \src "libresoc.v:144173.17-144173.123" - wire $and$libresoc.v:144173$6557_Y - attribute \src "libresoc.v:144174.18-144174.138" - wire width 2 $and$libresoc.v:144174$6558_Y - attribute \src "libresoc.v:144176.18-144176.119" - wire width 2 $and$libresoc.v:144176$6560_Y - attribute \src "libresoc.v:144179.18-144179.116" - wire $and$libresoc.v:144179$6563_Y - attribute \src "libresoc.v:144184.18-144184.113" - wire $and$libresoc.v:144184$6568_Y - attribute \src "libresoc.v:144185.18-144185.125" - wire width 2 $and$libresoc.v:144185$6569_Y - attribute \src "libresoc.v:144187.18-144187.112" - wire $and$libresoc.v:144187$6571_Y - attribute \src "libresoc.v:144190.18-144190.130" - wire $and$libresoc.v:144190$6574_Y - attribute \src "libresoc.v:144191.18-144191.130" - wire $and$libresoc.v:144191$6575_Y - attribute \src "libresoc.v:144192.18-144192.117" - wire $and$libresoc.v:144192$6576_Y - attribute \src "libresoc.v:144197.18-144197.134" - wire $and$libresoc.v:144197$6581_Y - attribute \src "libresoc.v:144198.18-144198.124" - wire width 2 $and$libresoc.v:144198$6582_Y - attribute \src "libresoc.v:144201.18-144201.116" - wire $and$libresoc.v:144201$6585_Y - attribute \src "libresoc.v:144202.18-144202.119" - wire $and$libresoc.v:144202$6586_Y - attribute \src "libresoc.v:144211.18-144211.138" - wire $and$libresoc.v:144211$6595_Y - attribute \src "libresoc.v:144212.18-144212.136" - wire $and$libresoc.v:144212$6596_Y - attribute \src "libresoc.v:144213.18-144213.149" - wire width 3 $and$libresoc.v:144213$6597_Y - attribute \src "libresoc.v:144186.18-144186.113" - wire $eq$libresoc.v:144186$6570_Y - attribute \src "libresoc.v:144188.18-144188.119" - wire $eq$libresoc.v:144188$6572_Y - attribute \src "libresoc.v:144161.19-144161.115" - wire width 3 $not$libresoc.v:144161$6545_Y - attribute \src "libresoc.v:144169.18-144169.97" - wire $not$libresoc.v:144169$6553_Y - attribute \src "libresoc.v:144171.18-144171.99" - wire $not$libresoc.v:144171$6555_Y - attribute \src "libresoc.v:144175.18-144175.113" - wire width 2 $not$libresoc.v:144175$6559_Y - attribute \src "libresoc.v:144178.18-144178.106" - wire $not$libresoc.v:144178$6562_Y - attribute \src "libresoc.v:144183.18-144183.124" - wire $not$libresoc.v:144183$6567_Y - attribute \src "libresoc.v:144189.17-144189.113" - wire width 3 $not$libresoc.v:144189$6573_Y - attribute \src "libresoc.v:144214.18-144214.133" - wire $not$libresoc.v:144214$6598_Y - attribute \src "libresoc.v:144215.18-144215.139" - wire $not$libresoc.v:144215$6599_Y - attribute \src "libresoc.v:144182.18-144182.112" - wire $or$libresoc.v:144182$6566_Y - attribute \src "libresoc.v:144193.18-144193.122" - wire $or$libresoc.v:144193$6577_Y - attribute \src "libresoc.v:144194.18-144194.124" - wire $or$libresoc.v:144194$6578_Y - attribute \src "libresoc.v:144195.18-144195.142" - wire width 2 $or$libresoc.v:144195$6579_Y - attribute \src "libresoc.v:144196.18-144196.155" - wire width 3 $or$libresoc.v:144196$6580_Y - attribute \src "libresoc.v:144199.18-144199.120" - wire width 2 $or$libresoc.v:144199$6583_Y - attribute \src "libresoc.v:144200.17-144200.117" - wire width 3 $or$libresoc.v:144200$6584_Y - attribute \src "libresoc.v:144206.17-144206.104" - wire $reduce_and$libresoc.v:144206$6590_Y - attribute \src "libresoc.v:144177.18-144177.106" - wire $reduce_or$libresoc.v:144177$6561_Y - attribute \src "libresoc.v:144180.18-144180.113" - wire $reduce_or$libresoc.v:144180$6564_Y - attribute \src "libresoc.v:144181.18-144181.112" - wire $reduce_or$libresoc.v:144181$6565_Y - attribute \src "libresoc.v:144203.18-144203.162" - wire $ternary$libresoc.v:144203$6587_Y - attribute \src "libresoc.v:144204.18-144204.163" - wire width 64 $ternary$libresoc.v:144204$6588_Y - attribute \src "libresoc.v:144205.18-144205.168" - wire $ternary$libresoc.v:144205$6589_Y - attribute \src "libresoc.v:144207.18-144207.188" - wire width 64 $ternary$libresoc.v:144207$6591_Y - attribute \src "libresoc.v:144208.18-144208.115" - wire width 64 $ternary$libresoc.v:144208$6592_Y - attribute \src "libresoc.v:144209.18-144209.125" - wire width 64 $ternary$libresoc.v:144209$6593_Y - attribute \src "libresoc.v:144210.18-144210.118" - wire $ternary$libresoc.v:144210$6594_Y + attribute \src "libresoc.v:143955.17-143955.109" + wire $and$libresoc.v:143955$6543_Y + attribute \src "libresoc.v:143956.18-143956.130" + wire width 3 $and$libresoc.v:143956$6544_Y + attribute \src "libresoc.v:143958.19-143958.114" + wire width 3 $and$libresoc.v:143958$6546_Y + attribute \src "libresoc.v:143959.19-143959.125" + wire $and$libresoc.v:143959$6547_Y + attribute \src "libresoc.v:143960.19-143960.125" + wire $and$libresoc.v:143960$6548_Y + attribute \src "libresoc.v:143961.19-143961.133" + wire width 2 $and$libresoc.v:143961$6549_Y + attribute \src "libresoc.v:143962.19-143962.121" + wire width 2 $and$libresoc.v:143962$6550_Y + attribute \src "libresoc.v:143963.19-143963.127" + wire $and$libresoc.v:143963$6551_Y + attribute \src "libresoc.v:143964.19-143964.127" + wire $and$libresoc.v:143964$6552_Y + attribute \src "libresoc.v:143966.18-143966.98" + wire $and$libresoc.v:143966$6554_Y + attribute \src "libresoc.v:143968.18-143968.100" + wire $and$libresoc.v:143968$6556_Y + attribute \src "libresoc.v:143969.17-143969.123" + wire $and$libresoc.v:143969$6557_Y + attribute \src "libresoc.v:143970.18-143970.138" + wire width 2 $and$libresoc.v:143970$6558_Y + attribute \src "libresoc.v:143972.18-143972.119" + wire width 2 $and$libresoc.v:143972$6560_Y + attribute \src "libresoc.v:143975.18-143975.116" + wire $and$libresoc.v:143975$6563_Y + attribute \src "libresoc.v:143980.18-143980.113" + wire $and$libresoc.v:143980$6568_Y + attribute \src "libresoc.v:143981.18-143981.125" + wire width 2 $and$libresoc.v:143981$6569_Y + attribute \src "libresoc.v:143983.18-143983.112" + wire $and$libresoc.v:143983$6571_Y + attribute \src "libresoc.v:143986.18-143986.130" + wire $and$libresoc.v:143986$6574_Y + attribute \src "libresoc.v:143987.18-143987.130" + wire $and$libresoc.v:143987$6575_Y + attribute \src "libresoc.v:143988.18-143988.117" + wire $and$libresoc.v:143988$6576_Y + attribute \src "libresoc.v:143993.18-143993.134" + wire $and$libresoc.v:143993$6581_Y + attribute \src "libresoc.v:143994.18-143994.124" + wire width 2 $and$libresoc.v:143994$6582_Y + attribute \src "libresoc.v:143997.18-143997.116" + wire $and$libresoc.v:143997$6585_Y + attribute \src "libresoc.v:143998.18-143998.119" + wire $and$libresoc.v:143998$6586_Y + attribute \src "libresoc.v:144007.18-144007.138" + wire $and$libresoc.v:144007$6595_Y + attribute \src "libresoc.v:144008.18-144008.136" + wire $and$libresoc.v:144008$6596_Y + attribute \src "libresoc.v:144009.18-144009.149" + wire width 3 $and$libresoc.v:144009$6597_Y + attribute \src "libresoc.v:143982.18-143982.113" + wire $eq$libresoc.v:143982$6570_Y + attribute \src "libresoc.v:143984.18-143984.119" + wire $eq$libresoc.v:143984$6572_Y + attribute \src "libresoc.v:143957.19-143957.115" + wire width 3 $not$libresoc.v:143957$6545_Y + attribute \src "libresoc.v:143965.18-143965.97" + wire $not$libresoc.v:143965$6553_Y + attribute \src "libresoc.v:143967.18-143967.99" + wire $not$libresoc.v:143967$6555_Y + attribute \src "libresoc.v:143971.18-143971.113" + wire width 2 $not$libresoc.v:143971$6559_Y + attribute \src "libresoc.v:143974.18-143974.106" + wire $not$libresoc.v:143974$6562_Y + attribute \src "libresoc.v:143979.18-143979.124" + wire $not$libresoc.v:143979$6567_Y + attribute \src "libresoc.v:143985.17-143985.113" + wire width 3 $not$libresoc.v:143985$6573_Y + attribute \src "libresoc.v:144010.18-144010.133" + wire $not$libresoc.v:144010$6598_Y + attribute \src "libresoc.v:144011.18-144011.139" + wire $not$libresoc.v:144011$6599_Y + attribute \src "libresoc.v:143978.18-143978.112" + wire $or$libresoc.v:143978$6566_Y + attribute \src "libresoc.v:143989.18-143989.122" + wire $or$libresoc.v:143989$6577_Y + attribute \src "libresoc.v:143990.18-143990.124" + wire $or$libresoc.v:143990$6578_Y + attribute \src "libresoc.v:143991.18-143991.142" + wire width 2 $or$libresoc.v:143991$6579_Y + attribute \src "libresoc.v:143992.18-143992.155" + wire width 3 $or$libresoc.v:143992$6580_Y + attribute \src "libresoc.v:143995.18-143995.120" + wire width 2 $or$libresoc.v:143995$6583_Y + attribute \src "libresoc.v:143996.17-143996.117" + wire width 3 $or$libresoc.v:143996$6584_Y + attribute \src "libresoc.v:144002.17-144002.104" + wire $reduce_and$libresoc.v:144002$6590_Y + attribute \src "libresoc.v:143973.18-143973.106" + wire $reduce_or$libresoc.v:143973$6561_Y + attribute \src "libresoc.v:143976.18-143976.113" + wire $reduce_or$libresoc.v:143976$6564_Y + attribute \src "libresoc.v:143977.18-143977.112" + wire $reduce_or$libresoc.v:143977$6565_Y + attribute \src "libresoc.v:143999.18-143999.162" + wire $ternary$libresoc.v:143999$6587_Y + attribute \src "libresoc.v:144000.18-144000.163" + wire width 64 $ternary$libresoc.v:144000$6588_Y + attribute \src "libresoc.v:144001.18-144001.168" + wire $ternary$libresoc.v:144001$6589_Y + attribute \src "libresoc.v:144003.18-144003.188" + wire width 64 $ternary$libresoc.v:144003$6591_Y + attribute \src "libresoc.v:144004.18-144004.115" + wire width 64 $ternary$libresoc.v:144004$6592_Y + attribute \src "libresoc.v:144005.18-144005.125" + wire width 64 $ternary$libresoc.v:144005$6593_Y + attribute \src "libresoc.v:144006.18-144006.118" + wire $ternary$libresoc.v:144006$6594_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -232386,9 +232182,9 @@ module \logical0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \cr_a_ok @@ -232434,7 +232230,7 @@ module \logical0 wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 33 \dest2_o - attribute \src "libresoc.v:143550.7-143550.15" + attribute \src "libresoc.v:143346.7-143346.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \o_ok @@ -232659,7 +232455,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:144159$6543 + cell $and $and$libresoc.v:143955$6543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232667,10 +232463,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:144159$6543_Y + connect \Y $and$libresoc.v:143955$6543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:144160$6544 + cell $and $and$libresoc.v:143956$6544 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -232678,10 +232474,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$93 connect \B { 1'1 \$97 \$95 } - connect \Y $and$libresoc.v:144160$6544_Y + connect \Y $and$libresoc.v:143956$6544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:144162$6546 + cell $and $and$libresoc.v:143958$6546 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -232689,10 +232485,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$99 connect \B \$101 - connect \Y $and$libresoc.v:144162$6546_Y + connect \Y $and$libresoc.v:143958$6546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:144163$6547 + cell $and $and$libresoc.v:143959$6547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232700,10 +232496,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:144163$6547_Y + connect \Y $and$libresoc.v:143959$6547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:144164$6548 + cell $and $and$libresoc.v:143960$6548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232711,10 +232507,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:144164$6548_Y + connect \Y $and$libresoc.v:143960$6548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:144165$6549 + cell $and $and$libresoc.v:143961$6549 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -232722,10 +232518,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B { \$105 \$107 } - connect \Y $and$libresoc.v:144165$6549_Y + connect \Y $and$libresoc.v:143961$6549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:144166$6550 + cell $and $and$libresoc.v:143962$6550 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -232733,10 +232529,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \$109 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:144166$6550_Y + connect \Y $and$libresoc.v:143962$6550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:144167$6551 + cell $and $and$libresoc.v:143963$6551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232744,10 +232540,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:144167$6551_Y + connect \Y $and$libresoc.v:143963$6551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:144168$6552 + cell $and $and$libresoc.v:143964$6552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232755,10 +232551,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:144168$6552_Y + connect \Y $and$libresoc.v:143964$6552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:144170$6554 + cell $and $and$libresoc.v:143966$6554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232766,10 +232562,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$11 - connect \Y $and$libresoc.v:144170$6554_Y + connect \Y $and$libresoc.v:143966$6554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:144172$6556 + cell $and $and$libresoc.v:143968$6556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232777,10 +232573,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$15 - connect \Y $and$libresoc.v:144172$6556_Y + connect \Y $and$libresoc.v:143968$6556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:144173$6557 + cell $and $and$libresoc.v:143969$6557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232788,10 +232584,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:144173$6557_Y + connect \Y $and$libresoc.v:143969$6557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:144174$6558 + cell $and $and$libresoc.v:143970$6558 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -232799,10 +232595,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:144174$6558_Y + connect \Y $and$libresoc.v:143970$6558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:144176$6560 + cell $and $and$libresoc.v:143972$6560 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -232810,10 +232606,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__rel_o connect \B \$23 - connect \Y $and$libresoc.v:144176$6560_Y + connect \Y $and$libresoc.v:143972$6560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:144179$6563 + cell $and $and$libresoc.v:143975$6563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232821,10 +232617,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$21 - connect \Y $and$libresoc.v:144179$6563_Y + connect \Y $and$libresoc.v:143975$6563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:144184$6568 + cell $and $and$libresoc.v:143980$6568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232832,10 +232628,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$37 - connect \Y $and$libresoc.v:144184$6568_Y + connect \Y $and$libresoc.v:143980$6568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:144185$6569 + cell $and $and$libresoc.v:143981$6569 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -232843,10 +232639,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:144185$6569_Y + connect \Y $and$libresoc.v:143981$6569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:144187$6571 + cell $and $and$libresoc.v:143983$6571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232854,10 +232650,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$43 - connect \Y $and$libresoc.v:144187$6571_Y + connect \Y $and$libresoc.v:143983$6571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:144190$6574 + cell $and $and$libresoc.v:143986$6574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232865,10 +232661,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \alu_logical0_n_ready_i - connect \Y $and$libresoc.v:144190$6574_Y + connect \Y $and$libresoc.v:143986$6574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:144191$6575 + cell $and $and$libresoc.v:143987$6575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232876,10 +232672,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_logical0_n_valid_o - connect \Y $and$libresoc.v:144191$6575_Y + connect \Y $and$libresoc.v:143987$6575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:144192$6576 + cell $and $and$libresoc.v:143988$6576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232887,10 +232683,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \cu_busy_o - connect \Y $and$libresoc.v:144192$6576_Y + connect \Y $and$libresoc.v:143988$6576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:144197$6581 + cell $and $and$libresoc.v:143993$6581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232898,10 +232694,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:144197$6581_Y + connect \Y $and$libresoc.v:143993$6581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:144198$6582 + cell $and $and$libresoc.v:143994$6582 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -232909,10 +232705,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:144198$6582_Y + connect \Y $and$libresoc.v:143994$6582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:144201$6585 + cell $and $and$libresoc.v:143997$6585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232920,10 +232716,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:144201$6585_Y + connect \Y $and$libresoc.v:143997$6585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:144202$6586 + cell $and $and$libresoc.v:143998$6586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232931,10 +232727,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:144202$6586_Y + connect \Y $and$libresoc.v:143998$6586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:144211$6595 + cell $and $and$libresoc.v:144007$6595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232942,10 +232738,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:144211$6595_Y + connect \Y $and$libresoc.v:144007$6595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:144212$6596 + cell $and $and$libresoc.v:144008$6596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232953,10 +232749,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:144212$6596_Y + connect \Y $and$libresoc.v:144008$6596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:144213$6597 + cell $and $and$libresoc.v:144009$6597 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -232964,10 +232760,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:144213$6597_Y + connect \Y $and$libresoc.v:144009$6597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:144186$6570 + cell $eq $eq$libresoc.v:143982$6570 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -232975,10 +232771,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$41 connect \B 1'0 - connect \Y $eq$libresoc.v:144186$6570_Y + connect \Y $eq$libresoc.v:143982$6570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:144188$6572 + cell $eq $eq$libresoc.v:143984$6572 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -232986,82 +232782,82 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:144188$6572_Y + connect \Y $eq$libresoc.v:143984$6572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:144161$6545 + cell $not $not$libresoc.v:143957$6545 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:144161$6545_Y + connect \Y $not$libresoc.v:143957$6545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:144169$6553 + cell $not $not$libresoc.v:143965$6553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:144169$6553_Y + connect \Y $not$libresoc.v:143965$6553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:144171$6555 + cell $not $not$libresoc.v:143967$6555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:144171$6555_Y + connect \Y $not$libresoc.v:143967$6555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:144175$6559 + cell $not $not$libresoc.v:143971$6559 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:144175$6559_Y + connect \Y $not$libresoc.v:143971$6559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:144178$6562 + cell $not $not$libresoc.v:143974$6562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 - connect \Y $not$libresoc.v:144178$6562_Y + connect \Y $not$libresoc.v:143974$6562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:144183$6567 + cell $not $not$libresoc.v:143979$6567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_ready_i - connect \Y $not$libresoc.v:144183$6567_Y + connect \Y $not$libresoc.v:143979$6567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:144189$6573 + cell $not $not$libresoc.v:143985$6573 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:144189$6573_Y + connect \Y $not$libresoc.v:143985$6573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:144214$6598 + cell $not $not$libresoc.v:144010$6598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__zero_a - connect \Y $not$libresoc.v:144214$6598_Y + connect \Y $not$libresoc.v:144010$6598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:144215$6599 + cell $not $not$libresoc.v:144011$6599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:144215$6599_Y + connect \Y $not$libresoc.v:144011$6599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:144182$6566 + cell $or $or$libresoc.v:143978$6566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233069,10 +232865,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $or$libresoc.v:144182$6566_Y + connect \Y $or$libresoc.v:143978$6566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:144193$6577 + cell $or $or$libresoc.v:143989$6577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233080,10 +232876,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:144193$6577_Y + connect \Y $or$libresoc.v:143989$6577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:144194$6578 + cell $or $or$libresoc.v:143990$6578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233091,10 +232887,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:144194$6578_Y + connect \Y $or$libresoc.v:143990$6578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:144195$6579 + cell $or $or$libresoc.v:143991$6579 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233102,10 +232898,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:144195$6579_Y + connect \Y $or$libresoc.v:143991$6579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:144196$6580 + cell $or $or$libresoc.v:143992$6580 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233113,10 +232909,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:144196$6580_Y + connect \Y $or$libresoc.v:143992$6580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:144199$6583 + cell $or $or$libresoc.v:143995$6583 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233124,10 +232920,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:144199$6583_Y + connect \Y $or$libresoc.v:143995$6583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:144200$6584 + cell $or $or$libresoc.v:143996$6584 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233135,98 +232931,98 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$4 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:144200$6584_Y + connect \Y $or$libresoc.v:143996$6584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:144206$6590 + cell $reduce_and $reduce_and$libresoc.v:144002$6590 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$6 - connect \Y $reduce_and$libresoc.v:144206$6590_Y + connect \Y $reduce_and$libresoc.v:144002$6590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:144177$6561 + cell $reduce_or $reduce_or$libresoc.v:143973$6561 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$25 - connect \Y $reduce_or$libresoc.v:144177$6561_Y + connect \Y $reduce_or$libresoc.v:143973$6561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:144180$6564 + cell $reduce_or $reduce_or$libresoc.v:143976$6564 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:144180$6564_Y + connect \Y $reduce_or$libresoc.v:143976$6564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:144181$6565 + cell $reduce_or $reduce_or$libresoc.v:143977$6565 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:144181$6565_Y + connect \Y $reduce_or$libresoc.v:143977$6565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:144203$6587 + cell $mux $ternary$libresoc.v:143999$6587 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:144203$6587_Y + connect \Y $ternary$libresoc.v:143999$6587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:144204$6588 + cell $mux $ternary$libresoc.v:144000$6588 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:144204$6588_Y + connect \Y $ternary$libresoc.v:144000$6588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:144205$6589 + cell $mux $ternary$libresoc.v:144001$6589 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:144205$6589_Y + connect \Y $ternary$libresoc.v:144001$6589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:144207$6591 + cell $mux $ternary$libresoc.v:144003$6591 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_logical0_logical_op__imm_data__data connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:144207$6591_Y + connect \Y $ternary$libresoc.v:144003$6591_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:144208$6592 + cell $mux $ternary$libresoc.v:144004$6592 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:144208$6592_Y + connect \Y $ternary$libresoc.v:144004$6592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:144209$6593 + cell $mux $ternary$libresoc.v:144005$6593 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$80 connect \S \src_sel$77 - connect \Y $ternary$libresoc.v:144209$6593_Y + connect \Y $ternary$libresoc.v:144005$6593_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:144210$6594 + cell $mux $ternary$libresoc.v:144006$6594 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:144210$6594_Y + connect \Y $ternary$libresoc.v:144006$6594_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:144296.14-144302.4" + attribute \src "libresoc.v:144092.14-144098.4" cell \alu_l$61 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233235,7 +233031,7 @@ module \logical0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:144303.16-144335.4" + attribute \src "libresoc.v:144099.16-144131.4" cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233270,7 +233066,7 @@ module \logical0 connect \xer_so \alu_logical0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:144336.15-144342.4" + attribute \src "libresoc.v:144132.15-144138.4" cell \alui_l$60 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233279,7 +233075,7 @@ module \logical0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:144343.14-144349.4" + attribute \src "libresoc.v:144139.14-144145.4" cell \opc_l$56 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233288,7 +233084,7 @@ module \logical0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:144350.14-144356.4" + attribute \src "libresoc.v:144146.14-144152.4" cell \req_l$57 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233297,7 +233093,7 @@ module \logical0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:144357.14-144363.4" + attribute \src "libresoc.v:144153.14-144159.4" cell \rok_l$59 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233306,7 +233102,7 @@ module \logical0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:144364.14-144369.4" + attribute \src "libresoc.v:144160.14-144165.4" cell \rst_l$58 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233314,7 +233110,7 @@ module \logical0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:144370.14-144376.4" + attribute \src "libresoc.v:144166.14-144172.4" cell \src_l$55 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233322,622 +233118,622 @@ module \logical0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:143550.7-143550.20" - process $proc$libresoc.v:143550$6750 + attribute \src "libresoc.v:143346.7-143346.20" + process $proc$libresoc.v:143346$6750 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143668.7-143668.24" - process $proc$libresoc.v:143668$6751 + attribute \src "libresoc.v:143464.7-143464.24" + process $proc$libresoc.v:143464$6751 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:143678.7-143678.26" - process $proc$libresoc.v:143678$6752 + attribute \src "libresoc.v:143474.7-143474.26" + process $proc$libresoc.v:143474$6752 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:143686.7-143686.25" - process $proc$libresoc.v:143686$6753 + attribute \src "libresoc.v:143482.7-143482.25" + process $proc$libresoc.v:143482$6753 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:143694.13-143694.53" - process $proc$libresoc.v:143694$6754 + attribute \src "libresoc.v:143490.13-143490.53" + process $proc$libresoc.v:143490$6754 assign { } { } assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:143713.14-143713.57" - process $proc$libresoc.v:143713$6755 + attribute \src "libresoc.v:143509.14-143509.57" + process $proc$libresoc.v:143509$6755 assign { } { } assign $1\alu_logical0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:143717.14-143717.76" - process $proc$libresoc.v:143717$6756 + attribute \src "libresoc.v:143513.14-143513.76" + process $proc$libresoc.v:143513$6756 assign { } { } assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:143721.7-143721.51" - process $proc$libresoc.v:143721$6757 + attribute \src "libresoc.v:143517.7-143517.51" + process $proc$libresoc.v:143517$6757 assign { } { } assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:143729.13-143729.56" - process $proc$libresoc.v:143729$6758 + attribute \src "libresoc.v:143525.13-143525.56" + process $proc$libresoc.v:143525$6758 assign { } { } assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:143733.14-143733.51" - process $proc$libresoc.v:143733$6759 + attribute \src "libresoc.v:143529.14-143529.51" + process $proc$libresoc.v:143529$6759 assign { } { } assign $1\alu_logical0_logical_op__insn[31:0] 0 sync always sync init update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:143812.13-143812.55" - process $proc$libresoc.v:143812$6760 + attribute \src "libresoc.v:143608.13-143608.55" + process $proc$libresoc.v:143608$6760 assign { } { } assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:143816.7-143816.48" - process $proc$libresoc.v:143816$6761 + attribute \src "libresoc.v:143612.7-143612.48" + process $proc$libresoc.v:143612$6761 assign { } { } assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:143820.7-143820.49" - process $proc$libresoc.v:143820$6762 + attribute \src "libresoc.v:143616.7-143616.49" + process $proc$libresoc.v:143616$6762 assign { } { } assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:143824.7-143824.47" - process $proc$libresoc.v:143824$6763 + attribute \src "libresoc.v:143620.7-143620.47" + process $proc$libresoc.v:143620$6763 assign { } { } assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:143828.7-143828.48" - process $proc$libresoc.v:143828$6764 + attribute \src "libresoc.v:143624.7-143624.48" + process $proc$libresoc.v:143624$6764 assign { } { } assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:143832.7-143832.45" - process $proc$libresoc.v:143832$6765 + attribute \src "libresoc.v:143628.7-143628.45" + process $proc$libresoc.v:143628$6765 assign { } { } assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:143836.7-143836.45" - process $proc$libresoc.v:143836$6766 + attribute \src "libresoc.v:143632.7-143632.45" + process $proc$libresoc.v:143632$6766 assign { } { } assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:143840.7-143840.51" - process $proc$libresoc.v:143840$6767 + attribute \src "libresoc.v:143636.7-143636.51" + process $proc$libresoc.v:143636$6767 assign { } { } assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:143844.7-143844.45" - process $proc$libresoc.v:143844$6768 + attribute \src "libresoc.v:143640.7-143640.45" + process $proc$libresoc.v:143640$6768 assign { } { } assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:143848.7-143848.45" - process $proc$libresoc.v:143848$6769 + attribute \src "libresoc.v:143644.7-143644.45" + process $proc$libresoc.v:143644$6769 assign { } { } assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:143852.7-143852.48" - process $proc$libresoc.v:143852$6770 + attribute \src "libresoc.v:143648.7-143648.48" + process $proc$libresoc.v:143648$6770 assign { } { } assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:143856.7-143856.45" - process $proc$libresoc.v:143856$6771 + attribute \src "libresoc.v:143652.7-143652.45" + process $proc$libresoc.v:143652$6771 assign { } { } assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:143882.7-143882.27" - process $proc$libresoc.v:143882$6772 + attribute \src "libresoc.v:143678.7-143678.27" + process $proc$libresoc.v:143678$6772 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:143916.14-143916.47" - process $proc$libresoc.v:143916$6773 + attribute \src "libresoc.v:143712.14-143712.47" + process $proc$libresoc.v:143712$6773 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:143920.7-143920.27" - process $proc$libresoc.v:143920$6774 + attribute \src "libresoc.v:143716.7-143716.27" + process $proc$libresoc.v:143716$6774 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:143924.13-143924.33" - process $proc$libresoc.v:143924$6775 + attribute \src "libresoc.v:143720.13-143720.33" + process $proc$libresoc.v:143720$6775 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:143928.7-143928.30" - process $proc$libresoc.v:143928$6776 + attribute \src "libresoc.v:143724.7-143724.30" + process $proc$libresoc.v:143724$6776 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:143942.7-143942.25" - process $proc$libresoc.v:143942$6777 + attribute \src "libresoc.v:143738.7-143738.25" + process $proc$libresoc.v:143738$6777 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:143946.7-143946.25" - process $proc$libresoc.v:143946$6778 + attribute \src "libresoc.v:143742.7-143742.25" + process $proc$libresoc.v:143742$6778 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:144080.13-144080.30" - process $proc$libresoc.v:144080$6779 + attribute \src "libresoc.v:143876.13-143876.30" + process $proc$libresoc.v:143876$6779 assign { } { } assign $1\prev_wr_go[1:0] 2'00 sync always sync init update \prev_wr_go $1\prev_wr_go[1:0] end - attribute \src "libresoc.v:144088.13-144088.31" - process $proc$libresoc.v:144088$6780 + attribute \src "libresoc.v:143884.13-143884.31" + process $proc$libresoc.v:143884$6780 assign { } { } assign $1\req_l_r_req[1:0] 2'11 sync always sync init update \req_l_r_req $1\req_l_r_req[1:0] end - attribute \src "libresoc.v:144092.13-144092.31" - process $proc$libresoc.v:144092$6781 + attribute \src "libresoc.v:143888.13-143888.31" + process $proc$libresoc.v:143888$6781 assign { } { } assign $1\req_l_s_req[1:0] 2'00 sync always sync init update \req_l_s_req $1\req_l_s_req[1:0] end - attribute \src "libresoc.v:144104.7-144104.26" - process $proc$libresoc.v:144104$6782 + attribute \src "libresoc.v:143900.7-143900.26" + process $proc$libresoc.v:143900$6782 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:144108.7-144108.26" - process $proc$libresoc.v:144108$6783 + attribute \src "libresoc.v:143904.7-143904.26" + process $proc$libresoc.v:143904$6783 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:144112.7-144112.25" - process $proc$libresoc.v:144112$6784 + attribute \src "libresoc.v:143908.7-143908.25" + process $proc$libresoc.v:143908$6784 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:144116.7-144116.25" - process $proc$libresoc.v:144116$6785 + attribute \src "libresoc.v:143912.7-143912.25" + process $proc$libresoc.v:143912$6785 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:144130.13-144130.31" - process $proc$libresoc.v:144130$6786 + attribute \src "libresoc.v:143926.13-143926.31" + process $proc$libresoc.v:143926$6786 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:144134.13-144134.31" - process $proc$libresoc.v:144134$6787 + attribute \src "libresoc.v:143930.13-143930.31" + process $proc$libresoc.v:143930$6787 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:144142.14-144142.43" - process $proc$libresoc.v:144142$6788 + attribute \src "libresoc.v:143938.14-143938.43" + process $proc$libresoc.v:143938$6788 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:144146.14-144146.43" - process $proc$libresoc.v:144146$6789 + attribute \src "libresoc.v:143942.14-143942.43" + process $proc$libresoc.v:143942$6789 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:144150.7-144150.20" - process $proc$libresoc.v:144150$6790 + attribute \src "libresoc.v:143946.7-143946.20" + process $proc$libresoc.v:143946$6790 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:144216.3-144217.39" - process $proc$libresoc.v:144216$6600 + attribute \src "libresoc.v:144012.3-144013.39" + process $proc$libresoc.v:144012$6600 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:144218.3-144219.43" - process $proc$libresoc.v:144218$6601 + attribute \src "libresoc.v:144014.3-144015.43" + process $proc$libresoc.v:144014$6601 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:144220.3-144221.29" - process $proc$libresoc.v:144220$6602 + attribute \src "libresoc.v:144016.3-144017.29" + process $proc$libresoc.v:144016$6602 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:144222.3-144223.29" - process $proc$libresoc.v:144222$6603 + attribute \src "libresoc.v:144018.3-144019.29" + process $proc$libresoc.v:144018$6603 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:144224.3-144225.29" - process $proc$libresoc.v:144224$6604 + attribute \src "libresoc.v:144020.3-144021.29" + process $proc$libresoc.v:144020$6604 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:144226.3-144227.43" - process $proc$libresoc.v:144226$6605 + attribute \src "libresoc.v:144022.3-144023.43" + process $proc$libresoc.v:144022$6605 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:144228.3-144229.49" - process $proc$libresoc.v:144228$6606 + attribute \src "libresoc.v:144024.3-144025.49" + process $proc$libresoc.v:144024$6606 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:144230.3-144231.37" - process $proc$libresoc.v:144230$6607 + attribute \src "libresoc.v:144026.3-144027.37" + process $proc$libresoc.v:144026$6607 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:144232.3-144233.43" - process $proc$libresoc.v:144232$6608 + attribute \src "libresoc.v:144028.3-144029.43" + process $proc$libresoc.v:144028$6608 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:144234.3-144235.85" - process $proc$libresoc.v:144234$6609 + attribute \src "libresoc.v:144030.3-144031.85" + process $proc$libresoc.v:144030$6609 assign { } { } assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:144236.3-144237.81" - process $proc$libresoc.v:144236$6610 + attribute \src "libresoc.v:144032.3-144033.81" + process $proc$libresoc.v:144032$6610 assign { } { } assign $0\alu_logical0_logical_op__fn_unit[13:0] \alu_logical0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:144238.3-144239.95" - process $proc$libresoc.v:144238$6611 + attribute \src "libresoc.v:144034.3-144035.95" + process $proc$libresoc.v:144034$6611 assign { } { } assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:144240.3-144241.91" - process $proc$libresoc.v:144240$6612 + attribute \src "libresoc.v:144036.3-144037.91" + process $proc$libresoc.v:144036$6612 assign { } { } assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:144242.3-144243.79" - process $proc$libresoc.v:144242$6613 + attribute \src "libresoc.v:144038.3-144039.79" + process $proc$libresoc.v:144038$6613 assign { } { } assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:144244.3-144245.79" - process $proc$libresoc.v:144244$6614 + attribute \src "libresoc.v:144040.3-144041.79" + process $proc$libresoc.v:144040$6614 assign { } { } assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:144246.3-144247.79" - process $proc$libresoc.v:144246$6615 + attribute \src "libresoc.v:144042.3-144043.79" + process $proc$libresoc.v:144042$6615 assign { } { } assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:144248.3-144249.79" - process $proc$libresoc.v:144248$6616 + attribute \src "libresoc.v:144044.3-144045.79" + process $proc$libresoc.v:144044$6616 assign { } { } assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:144250.3-144251.85" - process $proc$libresoc.v:144250$6617 + attribute \src "libresoc.v:144046.3-144047.85" + process $proc$libresoc.v:144046$6617 assign { } { } assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:144252.3-144253.79" - process $proc$libresoc.v:144252$6618 + attribute \src "libresoc.v:144048.3-144049.79" + process $proc$libresoc.v:144048$6618 assign { } { } assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:144254.3-144255.89" - process $proc$libresoc.v:144254$6619 + attribute \src "libresoc.v:144050.3-144051.89" + process $proc$libresoc.v:144050$6619 assign { } { } assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:144256.3-144257.87" - process $proc$libresoc.v:144256$6620 + attribute \src "libresoc.v:144052.3-144053.87" + process $proc$libresoc.v:144052$6620 assign { } { } assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:144258.3-144259.85" - process $proc$libresoc.v:144258$6621 + attribute \src "libresoc.v:144054.3-144055.85" + process $proc$libresoc.v:144054$6621 assign { } { } assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:144260.3-144261.91" - process $proc$libresoc.v:144260$6622 + attribute \src "libresoc.v:144056.3-144057.91" + process $proc$libresoc.v:144056$6622 assign { } { } assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:144262.3-144263.83" - process $proc$libresoc.v:144262$6623 + attribute \src "libresoc.v:144058.3-144059.83" + process $proc$libresoc.v:144058$6623 assign { } { } assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:144264.3-144265.85" - process $proc$libresoc.v:144264$6624 + attribute \src "libresoc.v:144060.3-144061.85" + process $proc$libresoc.v:144060$6624 assign { } { } assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:144266.3-144267.83" - process $proc$libresoc.v:144266$6625 + attribute \src "libresoc.v:144062.3-144063.83" + process $proc$libresoc.v:144062$6625 assign { } { } assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next sync posedge \coresync_clk update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:144268.3-144269.75" - process $proc$libresoc.v:144268$6626 + attribute \src "libresoc.v:144064.3-144065.75" + process $proc$libresoc.v:144064$6626 assign { } { } assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:144270.3-144271.39" - process $proc$libresoc.v:144270$6627 + attribute \src "libresoc.v:144066.3-144067.39" + process $proc$libresoc.v:144066$6627 assign { } { } assign $0\req_l_r_req[1:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[1:0] end - attribute \src "libresoc.v:144272.3-144273.39" - process $proc$libresoc.v:144272$6628 + attribute \src "libresoc.v:144068.3-144069.39" + process $proc$libresoc.v:144068$6628 assign { } { } assign $0\req_l_s_req[1:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[1:0] end - attribute \src "libresoc.v:144274.3-144275.39" - process $proc$libresoc.v:144274$6629 + attribute \src "libresoc.v:144070.3-144071.39" + process $proc$libresoc.v:144070$6629 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:144276.3-144277.39" - process $proc$libresoc.v:144276$6630 + attribute \src "libresoc.v:144072.3-144073.39" + process $proc$libresoc.v:144072$6630 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:144278.3-144279.39" - process $proc$libresoc.v:144278$6631 + attribute \src "libresoc.v:144074.3-144075.39" + process $proc$libresoc.v:144074$6631 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:144280.3-144281.39" - process $proc$libresoc.v:144280$6632 + attribute \src "libresoc.v:144076.3-144077.39" + process $proc$libresoc.v:144076$6632 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:144282.3-144283.39" - process $proc$libresoc.v:144282$6633 + attribute \src "libresoc.v:144078.3-144079.39" + process $proc$libresoc.v:144078$6633 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:144284.3-144285.39" - process $proc$libresoc.v:144284$6634 + attribute \src "libresoc.v:144080.3-144081.39" + process $proc$libresoc.v:144080$6634 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:144286.3-144287.41" - process $proc$libresoc.v:144286$6635 + attribute \src "libresoc.v:144082.3-144083.41" + process $proc$libresoc.v:144082$6635 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:144288.3-144289.41" - process $proc$libresoc.v:144288$6636 + attribute \src "libresoc.v:144084.3-144085.41" + process $proc$libresoc.v:144084$6636 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:144290.3-144291.37" - process $proc$libresoc.v:144290$6637 + attribute \src "libresoc.v:144086.3-144087.37" + process $proc$libresoc.v:144086$6637 assign { } { } assign $0\prev_wr_go[1:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[1:0] end - attribute \src "libresoc.v:144292.3-144293.44" - process $proc$libresoc.v:144292$6638 + attribute \src "libresoc.v:144088.3-144089.44" + process $proc$libresoc.v:144088$6638 assign { } { } assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:144294.3-144295.24" - process $proc$libresoc.v:144294$6639 + attribute \src "libresoc.v:144090.3-144091.24" + process $proc$libresoc.v:144090$6639 assign { } { } assign $0\all_rd_dly[0:0] \$9 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:144377.3-144386.6" - process $proc$libresoc.v:144377$6640 + attribute \src "libresoc.v:144173.3-144182.6" + process $proc$libresoc.v:144173$6640 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:144378.5-144378.29" + attribute \src "libresoc.v:144174.5-144174.29" switch \initial - attribute \src "libresoc.v:144378.9-144378.17" + attribute \src "libresoc.v:144174.9-144174.17" case 1'1 case end @@ -233953,14 +233749,14 @@ module \logical0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:144387.3-144395.6" - process $proc$libresoc.v:144387$6641 + attribute \src "libresoc.v:144183.3-144191.6" + process $proc$libresoc.v:144183$6641 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$6642 $1\rok_l_s_rdok$next[0:0]$6643 - attribute \src "libresoc.v:144388.5-144388.29" + attribute \src "libresoc.v:144184.5-144184.29" switch \initial - attribute \src "libresoc.v:144388.9-144388.17" + attribute \src "libresoc.v:144184.9-144184.17" case 1'1 case end @@ -233976,14 +233772,14 @@ module \logical0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6642 end - attribute \src "libresoc.v:144396.3-144404.6" - process $proc$libresoc.v:144396$6644 + attribute \src "libresoc.v:144192.3-144200.6" + process $proc$libresoc.v:144192$6644 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$6645 $1\rok_l_r_rdok$next[0:0]$6646 - attribute \src "libresoc.v:144397.5-144397.29" + attribute \src "libresoc.v:144193.5-144193.29" switch \initial - attribute \src "libresoc.v:144397.9-144397.17" + attribute \src "libresoc.v:144193.9-144193.17" case 1'1 case end @@ -233999,14 +233795,14 @@ module \logical0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6645 end - attribute \src "libresoc.v:144405.3-144413.6" - process $proc$libresoc.v:144405$6647 + attribute \src "libresoc.v:144201.3-144209.6" + process $proc$libresoc.v:144201$6647 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$6648 $1\rst_l_s_rst$next[0:0]$6649 - attribute \src "libresoc.v:144406.5-144406.29" + attribute \src "libresoc.v:144202.5-144202.29" switch \initial - attribute \src "libresoc.v:144406.9-144406.17" + attribute \src "libresoc.v:144202.9-144202.17" case 1'1 case end @@ -234022,14 +233818,14 @@ module \logical0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6648 end - attribute \src "libresoc.v:144414.3-144422.6" - process $proc$libresoc.v:144414$6650 + attribute \src "libresoc.v:144210.3-144218.6" + process $proc$libresoc.v:144210$6650 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$6651 $1\rst_l_r_rst$next[0:0]$6652 - attribute \src "libresoc.v:144415.5-144415.29" + attribute \src "libresoc.v:144211.5-144211.29" switch \initial - attribute \src "libresoc.v:144415.9-144415.17" + attribute \src "libresoc.v:144211.9-144211.17" case 1'1 case end @@ -234045,14 +233841,14 @@ module \logical0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6651 end - attribute \src "libresoc.v:144423.3-144431.6" - process $proc$libresoc.v:144423$6653 + attribute \src "libresoc.v:144219.3-144227.6" + process $proc$libresoc.v:144219$6653 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$6654 $1\opc_l_s_opc$next[0:0]$6655 - attribute \src "libresoc.v:144424.5-144424.29" + attribute \src "libresoc.v:144220.5-144220.29" switch \initial - attribute \src "libresoc.v:144424.9-144424.17" + attribute \src "libresoc.v:144220.9-144220.17" case 1'1 case end @@ -234068,14 +233864,14 @@ module \logical0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6654 end - attribute \src "libresoc.v:144432.3-144440.6" - process $proc$libresoc.v:144432$6656 + attribute \src "libresoc.v:144228.3-144236.6" + process $proc$libresoc.v:144228$6656 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$6657 $1\opc_l_r_opc$next[0:0]$6658 - attribute \src "libresoc.v:144433.5-144433.29" + attribute \src "libresoc.v:144229.5-144229.29" switch \initial - attribute \src "libresoc.v:144433.9-144433.17" + attribute \src "libresoc.v:144229.9-144229.17" case 1'1 case end @@ -234091,14 +233887,14 @@ module \logical0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6657 end - attribute \src "libresoc.v:144441.3-144449.6" - process $proc$libresoc.v:144441$6659 + attribute \src "libresoc.v:144237.3-144245.6" + process $proc$libresoc.v:144237$6659 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$6660 $1\src_l_s_src$next[2:0]$6661 - attribute \src "libresoc.v:144442.5-144442.29" + attribute \src "libresoc.v:144238.5-144238.29" switch \initial - attribute \src "libresoc.v:144442.9-144442.17" + attribute \src "libresoc.v:144238.9-144238.17" case 1'1 case end @@ -234114,14 +233910,14 @@ module \logical0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6660 end - attribute \src "libresoc.v:144450.3-144458.6" - process $proc$libresoc.v:144450$6662 + attribute \src "libresoc.v:144246.3-144254.6" + process $proc$libresoc.v:144246$6662 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$6663 $1\src_l_r_src$next[2:0]$6664 - attribute \src "libresoc.v:144451.5-144451.29" + attribute \src "libresoc.v:144247.5-144247.29" switch \initial - attribute \src "libresoc.v:144451.9-144451.17" + attribute \src "libresoc.v:144247.9-144247.17" case 1'1 case end @@ -234137,14 +233933,14 @@ module \logical0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6663 end - attribute \src "libresoc.v:144459.3-144467.6" - process $proc$libresoc.v:144459$6665 + attribute \src "libresoc.v:144255.3-144263.6" + process $proc$libresoc.v:144255$6665 assign { } { } assign { } { } assign $0\req_l_s_req$next[1:0]$6666 $1\req_l_s_req$next[1:0]$6667 - attribute \src "libresoc.v:144460.5-144460.29" + attribute \src "libresoc.v:144256.5-144256.29" switch \initial - attribute \src "libresoc.v:144460.9-144460.17" + attribute \src "libresoc.v:144256.9-144256.17" case 1'1 case end @@ -234160,14 +233956,14 @@ module \logical0 sync always update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6666 end - attribute \src "libresoc.v:144468.3-144476.6" - process $proc$libresoc.v:144468$6668 + attribute \src "libresoc.v:144264.3-144272.6" + process $proc$libresoc.v:144264$6668 assign { } { } assign { } { } assign $0\req_l_r_req$next[1:0]$6669 $1\req_l_r_req$next[1:0]$6670 - attribute \src "libresoc.v:144469.5-144469.29" + attribute \src "libresoc.v:144265.5-144265.29" switch \initial - attribute \src "libresoc.v:144469.9-144469.17" + attribute \src "libresoc.v:144265.9-144265.17" case 1'1 case end @@ -234183,8 +233979,8 @@ module \logical0 sync always update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6669 end - attribute \src "libresoc.v:144477.3-144515.6" - process $proc$libresoc.v:144477$6671 + attribute \src "libresoc.v:144273.3-144311.6" + process $proc$libresoc.v:144273$6671 assign { } { } assign { } { } assign { } { } @@ -234245,9 +234041,9 @@ module \logical0 assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6684 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711 assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6686 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712 assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6687 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713 - attribute \src "libresoc.v:144478.5-144478.29" + attribute \src "libresoc.v:144274.5-144274.29" switch \initial - attribute \src "libresoc.v:144478.9-144478.17" + attribute \src "libresoc.v:144274.9-144274.17" case 1'1 case end @@ -234338,8 +234134,8 @@ module \logical0 update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6688 update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6689 end - attribute \src "libresoc.v:144516.3-144537.6" - process $proc$libresoc.v:144516$6714 + attribute \src "libresoc.v:144312.3-144333.6" + process $proc$libresoc.v:144312$6714 assign { } { } assign { } { } assign { } { } @@ -234349,9 +234145,9 @@ module \logical0 assign $0\data_r0__o$next[63:0]$6715 $2\data_r0__o$next[63:0]$6719 assign { } { } assign $0\data_r0__o_ok$next[0:0]$6716 $3\data_r0__o_ok$next[0:0]$6721 - attribute \src "libresoc.v:144517.5-144517.29" + attribute \src "libresoc.v:144313.5-144313.29" switch \initial - attribute \src "libresoc.v:144517.9-144517.17" + attribute \src "libresoc.v:144313.9-144313.17" case 1'1 case end @@ -234390,8 +234186,8 @@ module \logical0 update \data_r0__o$next $0\data_r0__o$next[63:0]$6715 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6716 end - attribute \src "libresoc.v:144538.3-144559.6" - process $proc$libresoc.v:144538$6722 + attribute \src "libresoc.v:144334.3-144355.6" + process $proc$libresoc.v:144334$6722 assign { } { } assign { } { } assign { } { } @@ -234401,9 +234197,9 @@ module \logical0 assign $0\data_r1__cr_a$next[3:0]$6723 $2\data_r1__cr_a$next[3:0]$6727 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$6724 $3\data_r1__cr_a_ok$next[0:0]$6729 - attribute \src "libresoc.v:144539.5-144539.29" + attribute \src "libresoc.v:144335.5-144335.29" switch \initial - attribute \src "libresoc.v:144539.9-144539.17" + attribute \src "libresoc.v:144335.9-144335.17" case 1'1 case end @@ -234442,14 +234238,14 @@ module \logical0 update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6723 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6724 end - attribute \src "libresoc.v:144560.3-144569.6" - process $proc$libresoc.v:144560$6730 + attribute \src "libresoc.v:144356.3-144365.6" + process $proc$libresoc.v:144356$6730 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$6731 $1\src_r0$next[63:0]$6732 - attribute \src "libresoc.v:144561.5-144561.29" + attribute \src "libresoc.v:144357.5-144357.29" switch \initial - attribute \src "libresoc.v:144561.9-144561.17" + attribute \src "libresoc.v:144357.9-144357.17" case 1'1 case end @@ -234465,14 +234261,14 @@ module \logical0 sync always update \src_r0$next $0\src_r0$next[63:0]$6731 end - attribute \src "libresoc.v:144570.3-144579.6" - process $proc$libresoc.v:144570$6733 + attribute \src "libresoc.v:144366.3-144375.6" + process $proc$libresoc.v:144366$6733 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$6734 $1\src_r1$next[63:0]$6735 - attribute \src "libresoc.v:144571.5-144571.29" + attribute \src "libresoc.v:144367.5-144367.29" switch \initial - attribute \src "libresoc.v:144571.9-144571.17" + attribute \src "libresoc.v:144367.9-144367.17" case 1'1 case end @@ -234488,14 +234284,14 @@ module \logical0 sync always update \src_r1$next $0\src_r1$next[63:0]$6734 end - attribute \src "libresoc.v:144580.3-144589.6" - process $proc$libresoc.v:144580$6736 + attribute \src "libresoc.v:144376.3-144385.6" + process $proc$libresoc.v:144376$6736 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$6737 $1\src_r2$next[0:0]$6738 - attribute \src "libresoc.v:144581.5-144581.29" + attribute \src "libresoc.v:144377.5-144377.29" switch \initial - attribute \src "libresoc.v:144581.9-144581.17" + attribute \src "libresoc.v:144377.9-144377.17" case 1'1 case end @@ -234511,14 +234307,14 @@ module \logical0 sync always update \src_r2$next $0\src_r2$next[0:0]$6737 end - attribute \src "libresoc.v:144590.3-144598.6" - process $proc$libresoc.v:144590$6739 + attribute \src "libresoc.v:144386.3-144394.6" + process $proc$libresoc.v:144386$6739 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$6740 $1\alui_l_r_alui$next[0:0]$6741 - attribute \src "libresoc.v:144591.5-144591.29" + attribute \src "libresoc.v:144387.5-144387.29" switch \initial - attribute \src "libresoc.v:144591.9-144591.17" + attribute \src "libresoc.v:144387.9-144387.17" case 1'1 case end @@ -234534,14 +234330,14 @@ module \logical0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6740 end - attribute \src "libresoc.v:144599.3-144607.6" - process $proc$libresoc.v:144599$6742 + attribute \src "libresoc.v:144395.3-144403.6" + process $proc$libresoc.v:144395$6742 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$6743 $1\alu_l_r_alu$next[0:0]$6744 - attribute \src "libresoc.v:144600.5-144600.29" + attribute \src "libresoc.v:144396.5-144396.29" switch \initial - attribute \src "libresoc.v:144600.9-144600.17" + attribute \src "libresoc.v:144396.9-144396.17" case 1'1 case end @@ -234557,14 +234353,14 @@ module \logical0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6743 end - attribute \src "libresoc.v:144608.3-144617.6" - process $proc$libresoc.v:144608$6745 + attribute \src "libresoc.v:144404.3-144413.6" + process $proc$libresoc.v:144404$6745 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:144609.5-144609.29" + attribute \src "libresoc.v:144405.5-144405.29" switch \initial - attribute \src "libresoc.v:144609.9-144609.17" + attribute \src "libresoc.v:144405.9-144405.17" case 1'1 case end @@ -234580,14 +234376,14 @@ module \logical0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:144618.3-144627.6" - process $proc$libresoc.v:144618$6746 + attribute \src "libresoc.v:144414.3-144423.6" + process $proc$libresoc.v:144414$6746 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:144619.5-144619.29" + attribute \src "libresoc.v:144415.5-144415.29" switch \initial - attribute \src "libresoc.v:144619.9-144619.17" + attribute \src "libresoc.v:144415.9-144415.17" case 1'1 case end @@ -234603,14 +234399,14 @@ module \logical0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:144628.3-144636.6" - process $proc$libresoc.v:144628$6747 + attribute \src "libresoc.v:144424.3-144432.6" + process $proc$libresoc.v:144424$6747 assign { } { } assign { } { } assign $0\prev_wr_go$next[1:0]$6748 $1\prev_wr_go$next[1:0]$6749 - attribute \src "libresoc.v:144629.5-144629.29" + attribute \src "libresoc.v:144425.5-144425.29" switch \initial - attribute \src "libresoc.v:144629.9-144629.17" + attribute \src "libresoc.v:144425.9-144425.17" case 1'1 case end @@ -234626,63 +234422,63 @@ module \logical0 sync always update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6748 end - connect \$9 $and$libresoc.v:144159$6543_Y - connect \$99 $and$libresoc.v:144160$6544_Y - connect \$101 $not$libresoc.v:144161$6545_Y - connect \$103 $and$libresoc.v:144162$6546_Y - connect \$105 $and$libresoc.v:144163$6547_Y - connect \$107 $and$libresoc.v:144164$6548_Y - connect \$109 $and$libresoc.v:144165$6549_Y - connect \$111 $and$libresoc.v:144166$6550_Y - connect \$113 $and$libresoc.v:144167$6551_Y - connect \$115 $and$libresoc.v:144168$6552_Y - connect \$11 $not$libresoc.v:144169$6553_Y - connect \$13 $and$libresoc.v:144170$6554_Y - connect \$15 $not$libresoc.v:144171$6555_Y - connect \$17 $and$libresoc.v:144172$6556_Y - connect \$1 $and$libresoc.v:144173$6557_Y - connect \$19 $and$libresoc.v:144174$6558_Y - connect \$23 $not$libresoc.v:144175$6559_Y - connect \$25 $and$libresoc.v:144176$6560_Y - connect \$22 $reduce_or$libresoc.v:144177$6561_Y - connect \$21 $not$libresoc.v:144178$6562_Y - connect \$29 $and$libresoc.v:144179$6563_Y - connect \$31 $reduce_or$libresoc.v:144180$6564_Y - connect \$33 $reduce_or$libresoc.v:144181$6565_Y - connect \$35 $or$libresoc.v:144182$6566_Y - connect \$37 $not$libresoc.v:144183$6567_Y - connect \$39 $and$libresoc.v:144184$6568_Y - connect \$41 $and$libresoc.v:144185$6569_Y - connect \$43 $eq$libresoc.v:144186$6570_Y - connect \$45 $and$libresoc.v:144187$6571_Y - connect \$47 $eq$libresoc.v:144188$6572_Y - connect \$4 $not$libresoc.v:144189$6573_Y - connect \$49 $and$libresoc.v:144190$6574_Y - connect \$51 $and$libresoc.v:144191$6575_Y - connect \$53 $and$libresoc.v:144192$6576_Y - connect \$55 $or$libresoc.v:144193$6577_Y - connect \$57 $or$libresoc.v:144194$6578_Y - connect \$59 $or$libresoc.v:144195$6579_Y - connect \$61 $or$libresoc.v:144196$6580_Y - connect \$63 $and$libresoc.v:144197$6581_Y - connect \$65 $and$libresoc.v:144198$6582_Y - connect \$67 $or$libresoc.v:144199$6583_Y - connect \$6 $or$libresoc.v:144200$6584_Y - connect \$69 $and$libresoc.v:144201$6585_Y - connect \$71 $and$libresoc.v:144202$6586_Y - connect \$73 $ternary$libresoc.v:144203$6587_Y - connect \$75 $ternary$libresoc.v:144204$6588_Y - connect \$78 $ternary$libresoc.v:144205$6589_Y - connect \$3 $reduce_and$libresoc.v:144206$6590_Y - connect \$81 $ternary$libresoc.v:144207$6591_Y - connect \$83 $ternary$libresoc.v:144208$6592_Y - connect \$85 $ternary$libresoc.v:144209$6593_Y - connect \$87 $ternary$libresoc.v:144210$6594_Y - connect \$89 $and$libresoc.v:144211$6595_Y - connect \$91 $and$libresoc.v:144212$6596_Y - connect \$93 $and$libresoc.v:144213$6597_Y - connect \$95 $not$libresoc.v:144214$6598_Y - connect \$97 $not$libresoc.v:144215$6599_Y + connect \$9 $and$libresoc.v:143955$6543_Y + connect \$99 $and$libresoc.v:143956$6544_Y + connect \$101 $not$libresoc.v:143957$6545_Y + connect \$103 $and$libresoc.v:143958$6546_Y + connect \$105 $and$libresoc.v:143959$6547_Y + connect \$107 $and$libresoc.v:143960$6548_Y + connect \$109 $and$libresoc.v:143961$6549_Y + connect \$111 $and$libresoc.v:143962$6550_Y + connect \$113 $and$libresoc.v:143963$6551_Y + connect \$115 $and$libresoc.v:143964$6552_Y + connect \$11 $not$libresoc.v:143965$6553_Y + connect \$13 $and$libresoc.v:143966$6554_Y + connect \$15 $not$libresoc.v:143967$6555_Y + connect \$17 $and$libresoc.v:143968$6556_Y + connect \$1 $and$libresoc.v:143969$6557_Y + connect \$19 $and$libresoc.v:143970$6558_Y + connect \$23 $not$libresoc.v:143971$6559_Y + connect \$25 $and$libresoc.v:143972$6560_Y + connect \$22 $reduce_or$libresoc.v:143973$6561_Y + connect \$21 $not$libresoc.v:143974$6562_Y + connect \$29 $and$libresoc.v:143975$6563_Y + connect \$31 $reduce_or$libresoc.v:143976$6564_Y + connect \$33 $reduce_or$libresoc.v:143977$6565_Y + connect \$35 $or$libresoc.v:143978$6566_Y + connect \$37 $not$libresoc.v:143979$6567_Y + connect \$39 $and$libresoc.v:143980$6568_Y + connect \$41 $and$libresoc.v:143981$6569_Y + connect \$43 $eq$libresoc.v:143982$6570_Y + connect \$45 $and$libresoc.v:143983$6571_Y + connect \$47 $eq$libresoc.v:143984$6572_Y + connect \$4 $not$libresoc.v:143985$6573_Y + connect \$49 $and$libresoc.v:143986$6574_Y + connect \$51 $and$libresoc.v:143987$6575_Y + connect \$53 $and$libresoc.v:143988$6576_Y + connect \$55 $or$libresoc.v:143989$6577_Y + connect \$57 $or$libresoc.v:143990$6578_Y + connect \$59 $or$libresoc.v:143991$6579_Y + connect \$61 $or$libresoc.v:143992$6580_Y + connect \$63 $and$libresoc.v:143993$6581_Y + connect \$65 $and$libresoc.v:143994$6582_Y + connect \$67 $or$libresoc.v:143995$6583_Y + connect \$6 $or$libresoc.v:143996$6584_Y + connect \$69 $and$libresoc.v:143997$6585_Y + connect \$71 $and$libresoc.v:143998$6586_Y + connect \$73 $ternary$libresoc.v:143999$6587_Y + connect \$75 $ternary$libresoc.v:144000$6588_Y + connect \$78 $ternary$libresoc.v:144001$6589_Y + connect \$3 $reduce_and$libresoc.v:144002$6590_Y + connect \$81 $ternary$libresoc.v:144003$6591_Y + connect \$83 $ternary$libresoc.v:144004$6592_Y + connect \$85 $ternary$libresoc.v:144005$6593_Y + connect \$87 $ternary$libresoc.v:144006$6594_Y + connect \$89 $and$libresoc.v:144007$6595_Y + connect \$91 $and$libresoc.v:144008$6596_Y + connect \$93 $and$libresoc.v:144009$6597_Y + connect \$95 $not$libresoc.v:144010$6598_Y + connect \$97 $not$libresoc.v:144011$6599_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$111 @@ -234716,248 +234512,248 @@ module \logical0 connect \all_rd_dly$next \all_rd connect \all_rd \$9 end -attribute \src "libresoc.v:144673.1-146064.10" +attribute \src "libresoc.v:144469.1-145860.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" attribute \generator "nMigen" module \logical_pipe1 - attribute \src "libresoc.v:146003.3-146021.6" + attribute \src "libresoc.v:145799.3-145817.6" wire width 4 $0\cr_a$next[3:0]$6875 - attribute \src "libresoc.v:145763.3-145764.25" + attribute \src "libresoc.v:145559.3-145560.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:146003.3-146021.6" + attribute \src "libresoc.v:145799.3-145817.6" wire $0\cr_a_ok$next[0:0]$6876 - attribute \src "libresoc.v:145765.3-145766.31" + attribute \src "libresoc.v:145561.3-145562.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:144674.7-144674.20" + attribute \src "libresoc.v:144470.7-144470.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 4 $0\logical_op__data_len$next[3:0]$6826 - attribute \src "libresoc.v:145803.3-145804.57" + attribute \src "libresoc.v:145599.3-145600.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 14 $0\logical_op__fn_unit$next[13:0]$6827 - attribute \src "libresoc.v:145773.3-145774.55" + attribute \src "libresoc.v:145569.3-145570.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 64 $0\logical_op__imm_data__data$next[63:0]$6828 - attribute \src "libresoc.v:145775.3-145776.69" + attribute \src "libresoc.v:145571.3-145572.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__imm_data__ok$next[0:0]$6829 - attribute \src "libresoc.v:145777.3-145778.65" + attribute \src "libresoc.v:145573.3-145574.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 2 $0\logical_op__input_carry$next[1:0]$6830 - attribute \src "libresoc.v:145791.3-145792.63" + attribute \src "libresoc.v:145587.3-145588.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 32 $0\logical_op__insn$next[31:0]$6831 - attribute \src "libresoc.v:145805.3-145806.49" + attribute \src "libresoc.v:145601.3-145602.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 7 $0\logical_op__insn_type$next[6:0]$6832 - attribute \src "libresoc.v:145771.3-145772.59" + attribute \src "libresoc.v:145567.3-145568.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__invert_in$next[0:0]$6833 - attribute \src "libresoc.v:145787.3-145788.59" + attribute \src "libresoc.v:145583.3-145584.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__invert_out$next[0:0]$6834 - attribute \src "libresoc.v:145793.3-145794.61" + attribute \src "libresoc.v:145589.3-145590.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__is_32bit$next[0:0]$6835 - attribute \src "libresoc.v:145799.3-145800.57" + attribute \src "libresoc.v:145595.3-145596.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__is_signed$next[0:0]$6836 - attribute \src "libresoc.v:145801.3-145802.59" + attribute \src "libresoc.v:145597.3-145598.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__oe__oe$next[0:0]$6837 - attribute \src "libresoc.v:145783.3-145784.53" + attribute \src "libresoc.v:145579.3-145580.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__oe__ok$next[0:0]$6838 - attribute \src "libresoc.v:145785.3-145786.53" + attribute \src "libresoc.v:145581.3-145582.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__output_carry$next[0:0]$6839 - attribute \src "libresoc.v:145797.3-145798.65" + attribute \src "libresoc.v:145593.3-145594.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__rc__ok$next[0:0]$6840 - attribute \src "libresoc.v:145781.3-145782.53" + attribute \src "libresoc.v:145577.3-145578.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__rc__rc$next[0:0]$6841 - attribute \src "libresoc.v:145779.3-145780.53" + attribute \src "libresoc.v:145575.3-145576.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__write_cr0$next[0:0]$6842 - attribute \src "libresoc.v:145795.3-145796.59" + attribute \src "libresoc.v:145591.3-145592.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__zero_a$next[0:0]$6843 - attribute \src "libresoc.v:145789.3-145790.53" + attribute \src "libresoc.v:145585.3-145586.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:145929.3-145941.6" + attribute \src "libresoc.v:145725.3-145737.6" wire width 2 $0\muxid$next[1:0]$6823 - attribute \src "libresoc.v:145807.3-145808.27" + attribute \src "libresoc.v:145603.3-145604.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:145984.3-146002.6" + attribute \src "libresoc.v:145780.3-145798.6" wire width 64 $0\o$next[63:0]$6869 - attribute \src "libresoc.v:145767.3-145768.19" + attribute \src "libresoc.v:145563.3-145564.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:145984.3-146002.6" + attribute \src "libresoc.v:145780.3-145798.6" wire $0\o_ok$next[0:0]$6870 - attribute \src "libresoc.v:145769.3-145770.25" + attribute \src "libresoc.v:145565.3-145566.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:145911.3-145928.6" + attribute \src "libresoc.v:145707.3-145724.6" wire $0\r_busy$next[0:0]$6819 - attribute \src "libresoc.v:145809.3-145810.29" + attribute \src "libresoc.v:145605.3-145606.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:146022.3-146040.6" + attribute \src "libresoc.v:145818.3-145836.6" wire $0\xer_so$next[0:0]$6881 - attribute \src "libresoc.v:145759.3-145760.29" + attribute \src "libresoc.v:145555.3-145556.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:146022.3-146040.6" + attribute \src "libresoc.v:145818.3-145836.6" wire $0\xer_so_ok$next[0:0]$6882 - attribute \src "libresoc.v:145761.3-145762.35" + attribute \src "libresoc.v:145557.3-145558.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:146003.3-146021.6" + attribute \src "libresoc.v:145799.3-145817.6" wire width 4 $1\cr_a$next[3:0]$6877 - attribute \src "libresoc.v:144683.13-144683.24" + attribute \src "libresoc.v:144479.13-144479.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:146003.3-146021.6" + attribute \src "libresoc.v:145799.3-145817.6" wire $1\cr_a_ok$next[0:0]$6878 - attribute \src "libresoc.v:144692.7-144692.21" + attribute \src "libresoc.v:144488.7-144488.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 4 $1\logical_op__data_len$next[3:0]$6844 - attribute \src "libresoc.v:144977.13-144977.40" + attribute \src "libresoc.v:144773.13-144773.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 14 $1\logical_op__fn_unit$next[13:0]$6845 - attribute \src "libresoc.v:145001.14-145001.44" + attribute \src "libresoc.v:144797.14-144797.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 64 $1\logical_op__imm_data__data$next[63:0]$6846 - attribute \src "libresoc.v:145040.14-145040.63" + attribute \src "libresoc.v:144836.14-144836.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__imm_data__ok$next[0:0]$6847 - attribute \src "libresoc.v:145049.7-145049.38" + attribute \src "libresoc.v:144845.7-144845.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 2 $1\logical_op__input_carry$next[1:0]$6848 - attribute \src "libresoc.v:145062.13-145062.43" + attribute \src "libresoc.v:144858.13-144858.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 32 $1\logical_op__insn$next[31:0]$6849 - attribute \src "libresoc.v:145079.14-145079.38" + attribute \src "libresoc.v:144875.14-144875.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 7 $1\logical_op__insn_type$next[6:0]$6850 - attribute \src "libresoc.v:145163.13-145163.42" + attribute \src "libresoc.v:144959.13-144959.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__invert_in$next[0:0]$6851 - attribute \src "libresoc.v:145322.7-145322.35" + attribute \src "libresoc.v:145118.7-145118.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__invert_out$next[0:0]$6852 - attribute \src "libresoc.v:145331.7-145331.36" + attribute \src "libresoc.v:145127.7-145127.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__is_32bit$next[0:0]$6853 - attribute \src "libresoc.v:145340.7-145340.34" + attribute \src "libresoc.v:145136.7-145136.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__is_signed$next[0:0]$6854 - attribute \src "libresoc.v:145349.7-145349.35" + attribute \src "libresoc.v:145145.7-145145.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__oe__oe$next[0:0]$6855 - attribute \src "libresoc.v:145358.7-145358.32" + attribute \src "libresoc.v:145154.7-145154.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__oe__ok$next[0:0]$6856 - attribute \src "libresoc.v:145367.7-145367.32" + attribute \src "libresoc.v:145163.7-145163.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__output_carry$next[0:0]$6857 - attribute \src "libresoc.v:145376.7-145376.38" + attribute \src "libresoc.v:145172.7-145172.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__rc__ok$next[0:0]$6858 - attribute \src "libresoc.v:145385.7-145385.32" + attribute \src "libresoc.v:145181.7-145181.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__rc__rc$next[0:0]$6859 - attribute \src "libresoc.v:145394.7-145394.32" + attribute \src "libresoc.v:145190.7-145190.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__write_cr0$next[0:0]$6860 - attribute \src "libresoc.v:145403.7-145403.35" + attribute \src "libresoc.v:145199.7-145199.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__zero_a$next[0:0]$6861 - attribute \src "libresoc.v:145412.7-145412.32" + attribute \src "libresoc.v:145208.7-145208.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:145929.3-145941.6" + attribute \src "libresoc.v:145725.3-145737.6" wire width 2 $1\muxid$next[1:0]$6824 - attribute \src "libresoc.v:145697.13-145697.25" + attribute \src "libresoc.v:145493.13-145493.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:145984.3-146002.6" + attribute \src "libresoc.v:145780.3-145798.6" wire width 64 $1\o$next[63:0]$6871 - attribute \src "libresoc.v:145712.14-145712.38" + attribute \src "libresoc.v:145508.14-145508.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:145984.3-146002.6" + attribute \src "libresoc.v:145780.3-145798.6" wire $1\o_ok$next[0:0]$6872 - attribute \src "libresoc.v:145719.7-145719.18" + attribute \src "libresoc.v:145515.7-145515.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:145911.3-145928.6" + attribute \src "libresoc.v:145707.3-145724.6" wire $1\r_busy$next[0:0]$6820 - attribute \src "libresoc.v:145733.7-145733.20" + attribute \src "libresoc.v:145529.7-145529.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:146022.3-146040.6" + attribute \src "libresoc.v:145818.3-145836.6" wire $1\xer_so$next[0:0]$6883 - attribute \src "libresoc.v:145742.7-145742.20" + attribute \src "libresoc.v:145538.7-145538.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:146022.3-146040.6" + attribute \src "libresoc.v:145818.3-145836.6" wire $1\xer_so_ok$next[0:0]$6884 - attribute \src "libresoc.v:145751.7-145751.23" + attribute \src "libresoc.v:145547.7-145547.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:146003.3-146021.6" + attribute \src "libresoc.v:145799.3-145817.6" wire $2\cr_a_ok$next[0:0]$6879 - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire width 64 $2\logical_op__imm_data__data$next[63:0]$6862 - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $2\logical_op__imm_data__ok$next[0:0]$6863 - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $2\logical_op__oe__oe$next[0:0]$6864 - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $2\logical_op__oe__ok$next[0:0]$6865 - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $2\logical_op__rc__ok$next[0:0]$6866 - attribute \src "libresoc.v:145942.3-145983.6" + attribute \src "libresoc.v:145738.3-145779.6" wire $2\logical_op__rc__rc$next[0:0]$6867 - attribute \src "libresoc.v:145984.3-146002.6" + attribute \src "libresoc.v:145780.3-145798.6" wire $2\o_ok$next[0:0]$6873 - attribute \src "libresoc.v:145911.3-145928.6" + attribute \src "libresoc.v:145707.3-145724.6" wire $2\r_busy$next[0:0]$6821 - attribute \src "libresoc.v:146022.3-146040.6" + attribute \src "libresoc.v:145818.3-145836.6" wire $2\xer_so_ok$next[0:0]$6885 - attribute \src "libresoc.v:145758.18-145758.118" - wire $and$libresoc.v:145758$6791_Y + attribute \src "libresoc.v:145554.18-145554.118" + wire $and$libresoc.v:145554$6791_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a @@ -234975,7 +234771,7 @@ module \logical_pipe1 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next - attribute \src "libresoc.v:144674.7-144674.15" + attribute \src "libresoc.v:144470.7-144470.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -236014,7 +235810,7 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:145758$6791 + cell $and $and$libresoc.v:145554$6791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236022,10 +235818,10 @@ module \logical_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$63 connect \B \p_ready_o - connect \Y $and$libresoc.v:145758$6791_Y + connect \Y $and$libresoc.v:145554$6791_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:145811.14-145856.4" + attribute \src "libresoc.v:145607.14-145652.4" cell \input$50 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$38 @@ -236073,7 +235869,7 @@ module \logical_pipe1 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:145857.13-145902.4" + attribute \src "libresoc.v:145653.13-145698.4" cell \main$51 \main connect \logical_op__data_len \main_logical_op__data_len connect \logical_op__data_len$18 \main_logical_op__data_len$60 @@ -236121,424 +235917,424 @@ module \logical_pipe1 connect \xer_so$20 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:145903.10-145906.4" + attribute \src "libresoc.v:145699.10-145702.4" cell \n$49 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:145907.10-145910.4" + attribute \src "libresoc.v:145703.10-145706.4" cell \p$48 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:144674.7-144674.20" - process $proc$libresoc.v:144674$6886 + attribute \src "libresoc.v:144470.7-144470.20" + process $proc$libresoc.v:144470$6886 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:144683.13-144683.24" - process $proc$libresoc.v:144683$6887 + attribute \src "libresoc.v:144479.13-144479.24" + process $proc$libresoc.v:144479$6887 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:144692.7-144692.21" - process $proc$libresoc.v:144692$6888 + attribute \src "libresoc.v:144488.7-144488.21" + process $proc$libresoc.v:144488$6888 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:144977.13-144977.40" - process $proc$libresoc.v:144977$6889 + attribute \src "libresoc.v:144773.13-144773.40" + process $proc$libresoc.v:144773$6889 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:145001.14-145001.44" - process $proc$libresoc.v:145001$6890 + attribute \src "libresoc.v:144797.14-144797.44" + process $proc$libresoc.v:144797$6890 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:145040.14-145040.63" - process $proc$libresoc.v:145040$6891 + attribute \src "libresoc.v:144836.14-144836.63" + process $proc$libresoc.v:144836$6891 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:145049.7-145049.38" - process $proc$libresoc.v:145049$6892 + attribute \src "libresoc.v:144845.7-144845.38" + process $proc$libresoc.v:144845$6892 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:145062.13-145062.43" - process $proc$libresoc.v:145062$6893 + attribute \src "libresoc.v:144858.13-144858.43" + process $proc$libresoc.v:144858$6893 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:145079.14-145079.38" - process $proc$libresoc.v:145079$6894 + attribute \src "libresoc.v:144875.14-144875.38" + process $proc$libresoc.v:144875$6894 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:145163.13-145163.42" - process $proc$libresoc.v:145163$6895 + attribute \src "libresoc.v:144959.13-144959.42" + process $proc$libresoc.v:144959$6895 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:145322.7-145322.35" - process $proc$libresoc.v:145322$6896 + attribute \src "libresoc.v:145118.7-145118.35" + process $proc$libresoc.v:145118$6896 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:145331.7-145331.36" - process $proc$libresoc.v:145331$6897 + attribute \src "libresoc.v:145127.7-145127.36" + process $proc$libresoc.v:145127$6897 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:145340.7-145340.34" - process $proc$libresoc.v:145340$6898 + attribute \src "libresoc.v:145136.7-145136.34" + process $proc$libresoc.v:145136$6898 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:145349.7-145349.35" - process $proc$libresoc.v:145349$6899 + attribute \src "libresoc.v:145145.7-145145.35" + process $proc$libresoc.v:145145$6899 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:145358.7-145358.32" - process $proc$libresoc.v:145358$6900 + attribute \src "libresoc.v:145154.7-145154.32" + process $proc$libresoc.v:145154$6900 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:145367.7-145367.32" - process $proc$libresoc.v:145367$6901 + attribute \src "libresoc.v:145163.7-145163.32" + process $proc$libresoc.v:145163$6901 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:145376.7-145376.38" - process $proc$libresoc.v:145376$6902 + attribute \src "libresoc.v:145172.7-145172.38" + process $proc$libresoc.v:145172$6902 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:145385.7-145385.32" - process $proc$libresoc.v:145385$6903 + attribute \src "libresoc.v:145181.7-145181.32" + process $proc$libresoc.v:145181$6903 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:145394.7-145394.32" - process $proc$libresoc.v:145394$6904 + attribute \src "libresoc.v:145190.7-145190.32" + process $proc$libresoc.v:145190$6904 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:145403.7-145403.35" - process $proc$libresoc.v:145403$6905 + attribute \src "libresoc.v:145199.7-145199.35" + process $proc$libresoc.v:145199$6905 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:145412.7-145412.32" - process $proc$libresoc.v:145412$6906 + attribute \src "libresoc.v:145208.7-145208.32" + process $proc$libresoc.v:145208$6906 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:145697.13-145697.25" - process $proc$libresoc.v:145697$6907 + attribute \src "libresoc.v:145493.13-145493.25" + process $proc$libresoc.v:145493$6907 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:145712.14-145712.38" - process $proc$libresoc.v:145712$6908 + attribute \src "libresoc.v:145508.14-145508.38" + process $proc$libresoc.v:145508$6908 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:145719.7-145719.18" - process $proc$libresoc.v:145719$6909 + attribute \src "libresoc.v:145515.7-145515.18" + process $proc$libresoc.v:145515$6909 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:145733.7-145733.20" - process $proc$libresoc.v:145733$6910 + attribute \src "libresoc.v:145529.7-145529.20" + process $proc$libresoc.v:145529$6910 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:145742.7-145742.20" - process $proc$libresoc.v:145742$6911 + attribute \src "libresoc.v:145538.7-145538.20" + process $proc$libresoc.v:145538$6911 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:145751.7-145751.23" - process $proc$libresoc.v:145751$6912 + attribute \src "libresoc.v:145547.7-145547.23" + process $proc$libresoc.v:145547$6912 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:145759.3-145760.29" - process $proc$libresoc.v:145759$6792 + attribute \src "libresoc.v:145555.3-145556.29" + process $proc$libresoc.v:145555$6792 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:145761.3-145762.35" - process $proc$libresoc.v:145761$6793 + attribute \src "libresoc.v:145557.3-145558.35" + process $proc$libresoc.v:145557$6793 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:145763.3-145764.25" - process $proc$libresoc.v:145763$6794 + attribute \src "libresoc.v:145559.3-145560.25" + process $proc$libresoc.v:145559$6794 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:145765.3-145766.31" - process $proc$libresoc.v:145765$6795 + attribute \src "libresoc.v:145561.3-145562.31" + process $proc$libresoc.v:145561$6795 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:145767.3-145768.19" - process $proc$libresoc.v:145767$6796 + attribute \src "libresoc.v:145563.3-145564.19" + process $proc$libresoc.v:145563$6796 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:145769.3-145770.25" - process $proc$libresoc.v:145769$6797 + attribute \src "libresoc.v:145565.3-145566.25" + process $proc$libresoc.v:145565$6797 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:145771.3-145772.59" - process $proc$libresoc.v:145771$6798 + attribute \src "libresoc.v:145567.3-145568.59" + process $proc$libresoc.v:145567$6798 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:145773.3-145774.55" - process $proc$libresoc.v:145773$6799 + attribute \src "libresoc.v:145569.3-145570.55" + process $proc$libresoc.v:145569$6799 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:145775.3-145776.69" - process $proc$libresoc.v:145775$6800 + attribute \src "libresoc.v:145571.3-145572.69" + process $proc$libresoc.v:145571$6800 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:145777.3-145778.65" - process $proc$libresoc.v:145777$6801 + attribute \src "libresoc.v:145573.3-145574.65" + process $proc$libresoc.v:145573$6801 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:145779.3-145780.53" - process $proc$libresoc.v:145779$6802 + attribute \src "libresoc.v:145575.3-145576.53" + process $proc$libresoc.v:145575$6802 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:145781.3-145782.53" - process $proc$libresoc.v:145781$6803 + attribute \src "libresoc.v:145577.3-145578.53" + process $proc$libresoc.v:145577$6803 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:145783.3-145784.53" - process $proc$libresoc.v:145783$6804 + attribute \src "libresoc.v:145579.3-145580.53" + process $proc$libresoc.v:145579$6804 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:145785.3-145786.53" - process $proc$libresoc.v:145785$6805 + attribute \src "libresoc.v:145581.3-145582.53" + process $proc$libresoc.v:145581$6805 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:145787.3-145788.59" - process $proc$libresoc.v:145787$6806 + attribute \src "libresoc.v:145583.3-145584.59" + process $proc$libresoc.v:145583$6806 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:145789.3-145790.53" - process $proc$libresoc.v:145789$6807 + attribute \src "libresoc.v:145585.3-145586.53" + process $proc$libresoc.v:145585$6807 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:145791.3-145792.63" - process $proc$libresoc.v:145791$6808 + attribute \src "libresoc.v:145587.3-145588.63" + process $proc$libresoc.v:145587$6808 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:145793.3-145794.61" - process $proc$libresoc.v:145793$6809 + attribute \src "libresoc.v:145589.3-145590.61" + process $proc$libresoc.v:145589$6809 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:145795.3-145796.59" - process $proc$libresoc.v:145795$6810 + attribute \src "libresoc.v:145591.3-145592.59" + process $proc$libresoc.v:145591$6810 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:145797.3-145798.65" - process $proc$libresoc.v:145797$6811 + attribute \src "libresoc.v:145593.3-145594.65" + process $proc$libresoc.v:145593$6811 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:145799.3-145800.57" - process $proc$libresoc.v:145799$6812 + attribute \src "libresoc.v:145595.3-145596.57" + process $proc$libresoc.v:145595$6812 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:145801.3-145802.59" - process $proc$libresoc.v:145801$6813 + attribute \src "libresoc.v:145597.3-145598.59" + process $proc$libresoc.v:145597$6813 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:145803.3-145804.57" - process $proc$libresoc.v:145803$6814 + attribute \src "libresoc.v:145599.3-145600.57" + process $proc$libresoc.v:145599$6814 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:145805.3-145806.49" - process $proc$libresoc.v:145805$6815 + attribute \src "libresoc.v:145601.3-145602.49" + process $proc$libresoc.v:145601$6815 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:145807.3-145808.27" - process $proc$libresoc.v:145807$6816 + attribute \src "libresoc.v:145603.3-145604.27" + process $proc$libresoc.v:145603$6816 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:145809.3-145810.29" - process $proc$libresoc.v:145809$6817 + attribute \src "libresoc.v:145605.3-145606.29" + process $proc$libresoc.v:145605$6817 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:145911.3-145928.6" - process $proc$libresoc.v:145911$6818 + attribute \src "libresoc.v:145707.3-145724.6" + process $proc$libresoc.v:145707$6818 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$6819 $2\r_busy$next[0:0]$6821 - attribute \src "libresoc.v:145912.5-145912.29" + attribute \src "libresoc.v:145708.5-145708.29" switch \initial - attribute \src "libresoc.v:145912.9-145912.17" + attribute \src "libresoc.v:145708.9-145708.17" case 1'1 case end @@ -236567,14 +236363,14 @@ module \logical_pipe1 sync always update \r_busy$next $0\r_busy$next[0:0]$6819 end - attribute \src "libresoc.v:145929.3-145941.6" - process $proc$libresoc.v:145929$6822 + attribute \src "libresoc.v:145725.3-145737.6" + process $proc$libresoc.v:145725$6822 assign { } { } assign { } { } assign $0\muxid$next[1:0]$6823 $1\muxid$next[1:0]$6824 - attribute \src "libresoc.v:145930.5-145930.29" + attribute \src "libresoc.v:145726.5-145726.29" switch \initial - attribute \src "libresoc.v:145930.9-145930.17" + attribute \src "libresoc.v:145726.9-145726.17" case 1'1 case end @@ -236594,8 +236390,8 @@ module \logical_pipe1 sync always update \muxid$next $0\muxid$next[1:0]$6823 end - attribute \src "libresoc.v:145942.3-145983.6" - process $proc$libresoc.v:145942$6825 + attribute \src "libresoc.v:145738.3-145779.6" + process $proc$libresoc.v:145738$6825 assign { } { } assign { } { } assign { } { } @@ -236656,9 +236452,9 @@ module \logical_pipe1 assign $0\logical_op__oe__ok$next[0:0]$6838 $2\logical_op__oe__ok$next[0:0]$6865 assign $0\logical_op__rc__ok$next[0:0]$6840 $2\logical_op__rc__ok$next[0:0]$6866 assign $0\logical_op__rc__rc$next[0:0]$6841 $2\logical_op__rc__rc$next[0:0]$6867 - attribute \src "libresoc.v:145943.5-145943.29" + attribute \src "libresoc.v:145739.5-145739.29" switch \initial - attribute \src "libresoc.v:145943.9-145943.17" + attribute \src "libresoc.v:145739.9-145739.17" case 1'1 case end @@ -236770,8 +236566,8 @@ module \logical_pipe1 update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6842 update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6843 end - attribute \src "libresoc.v:145984.3-146002.6" - process $proc$libresoc.v:145984$6868 + attribute \src "libresoc.v:145780.3-145798.6" + process $proc$libresoc.v:145780$6868 assign { } { } assign { } { } assign { } { } @@ -236779,9 +236575,9 @@ module \logical_pipe1 assign $0\o$next[63:0]$6869 $1\o$next[63:0]$6871 assign { } { } assign $0\o_ok$next[0:0]$6870 $2\o_ok$next[0:0]$6873 - attribute \src "libresoc.v:145985.5-145985.29" + attribute \src "libresoc.v:145781.5-145781.29" switch \initial - attribute \src "libresoc.v:145985.9-145985.17" + attribute \src "libresoc.v:145781.9-145781.17" case 1'1 case end @@ -236814,8 +236610,8 @@ module \logical_pipe1 update \o$next $0\o$next[63:0]$6869 update \o_ok$next $0\o_ok$next[0:0]$6870 end - attribute \src "libresoc.v:146003.3-146021.6" - process $proc$libresoc.v:146003$6874 + attribute \src "libresoc.v:145799.3-145817.6" + process $proc$libresoc.v:145799$6874 assign { } { } assign { } { } assign { } { } @@ -236823,9 +236619,9 @@ module \logical_pipe1 assign $0\cr_a$next[3:0]$6875 $1\cr_a$next[3:0]$6877 assign { } { } assign $0\cr_a_ok$next[0:0]$6876 $2\cr_a_ok$next[0:0]$6879 - attribute \src "libresoc.v:146004.5-146004.29" + attribute \src "libresoc.v:145800.5-145800.29" switch \initial - attribute \src "libresoc.v:146004.9-146004.17" + attribute \src "libresoc.v:145800.9-145800.17" case 1'1 case end @@ -236858,8 +236654,8 @@ module \logical_pipe1 update \cr_a$next $0\cr_a$next[3:0]$6875 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6876 end - attribute \src "libresoc.v:146022.3-146040.6" - process $proc$libresoc.v:146022$6880 + attribute \src "libresoc.v:145818.3-145836.6" + process $proc$libresoc.v:145818$6880 assign { } { } assign { } { } assign { } { } @@ -236867,9 +236663,9 @@ module \logical_pipe1 assign $0\xer_so$next[0:0]$6881 $1\xer_so$next[0:0]$6883 assign { } { } assign $0\xer_so_ok$next[0:0]$6882 $2\xer_so_ok$next[0:0]$6885 - attribute \src "libresoc.v:146023.5-146023.29" + attribute \src "libresoc.v:145819.5-145819.29" switch \initial - attribute \src "libresoc.v:146023.9-146023.17" + attribute \src "libresoc.v:145819.9-145819.17" case 1'1 case end @@ -236902,7 +236698,7 @@ module \logical_pipe1 update \xer_so$next $0\xer_so$next[0:0]$6881 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6882 end - connect \$64 $and$libresoc.v:145758$6791_Y + connect \$64 $and$libresoc.v:145554$6791_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -236927,230 +236723,230 @@ module \logical_pipe1 connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:146068.1-147101.10" +attribute \src "libresoc.v:145864.1-146897.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" attribute \generator "nMigen" module \logical_pipe2 - attribute \src "libresoc.v:147068.3-147086.6" + attribute \src "libresoc.v:146864.3-146882.6" wire width 4 $0\cr_a$22$next[3:0]$7018 - attribute \src "libresoc.v:146872.3-146873.33" + attribute \src "libresoc.v:146668.3-146669.33" wire width 4 $0\cr_a$22[3:0]$6915 - attribute \src "libresoc.v:146080.13-146080.29" + attribute \src "libresoc.v:145876.13-145876.29" wire width 4 $0\cr_a$22[3:0]$7025 - attribute \src "libresoc.v:147068.3-147086.6" + attribute \src "libresoc.v:146864.3-146882.6" wire $0\cr_a_ok$23$next[0:0]$7019 - attribute \src "libresoc.v:146874.3-146875.39" + attribute \src "libresoc.v:146670.3-146671.39" wire $0\cr_a_ok$23[0:0]$6917 - attribute \src "libresoc.v:146089.7-146089.26" + attribute \src "libresoc.v:145885.7-145885.26" wire $0\cr_a_ok$23[0:0]$7027 - attribute \src "libresoc.v:146069.7-146069.20" + attribute \src "libresoc.v:145865.7-145865.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 4 $0\logical_op__data_len$18$next[3:0]$6969 - attribute \src "libresoc.v:146912.3-146913.65" + attribute \src "libresoc.v:146708.3-146709.65" wire width 4 $0\logical_op__data_len$18[3:0]$6955 - attribute \src "libresoc.v:146100.13-146100.45" + attribute \src "libresoc.v:145896.13-145896.45" wire width 4 $0\logical_op__data_len$18[3:0]$7029 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 14 $0\logical_op__fn_unit$3$next[13:0]$6970 - attribute \src "libresoc.v:146882.3-146883.61" + attribute \src "libresoc.v:146678.3-146679.61" wire width 14 $0\logical_op__fn_unit$3[13:0]$6925 - attribute \src "libresoc.v:146139.14-146139.48" + attribute \src "libresoc.v:145935.14-145935.48" wire width 14 $0\logical_op__fn_unit$3[13:0]$7031 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6971 - attribute \src "libresoc.v:146884.3-146885.75" + attribute \src "libresoc.v:146680.3-146681.75" wire width 64 $0\logical_op__imm_data__data$4[63:0]$6927 - attribute \src "libresoc.v:146163.14-146163.67" + attribute \src "libresoc.v:145959.14-145959.67" wire width 64 $0\logical_op__imm_data__data$4[63:0]$7033 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__imm_data__ok$5$next[0:0]$6972 - attribute \src "libresoc.v:146886.3-146887.71" + attribute \src "libresoc.v:146682.3-146683.71" wire $0\logical_op__imm_data__ok$5[0:0]$6929 - attribute \src "libresoc.v:146172.7-146172.42" + attribute \src "libresoc.v:145968.7-145968.42" wire $0\logical_op__imm_data__ok$5[0:0]$7035 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 2 $0\logical_op__input_carry$12$next[1:0]$6973 - attribute \src "libresoc.v:146900.3-146901.71" + attribute \src "libresoc.v:146696.3-146697.71" wire width 2 $0\logical_op__input_carry$12[1:0]$6943 - attribute \src "libresoc.v:146189.13-146189.48" + attribute \src "libresoc.v:145985.13-145985.48" wire width 2 $0\logical_op__input_carry$12[1:0]$7037 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 32 $0\logical_op__insn$19$next[31:0]$6974 - attribute \src "libresoc.v:146914.3-146915.57" + attribute \src "libresoc.v:146710.3-146711.57" wire width 32 $0\logical_op__insn$19[31:0]$6957 - attribute \src "libresoc.v:146202.14-146202.43" + attribute \src "libresoc.v:145998.14-145998.43" wire width 32 $0\logical_op__insn$19[31:0]$7039 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 7 $0\logical_op__insn_type$2$next[6:0]$6975 - attribute \src "libresoc.v:146880.3-146881.65" + attribute \src "libresoc.v:146676.3-146677.65" wire width 7 $0\logical_op__insn_type$2[6:0]$6923 - attribute \src "libresoc.v:146361.13-146361.46" + attribute \src "libresoc.v:146157.13-146157.46" wire width 7 $0\logical_op__insn_type$2[6:0]$7041 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__invert_in$10$next[0:0]$6976 - attribute \src "libresoc.v:146896.3-146897.67" + attribute \src "libresoc.v:146692.3-146693.67" wire $0\logical_op__invert_in$10[0:0]$6939 - attribute \src "libresoc.v:146445.7-146445.40" + attribute \src "libresoc.v:146241.7-146241.40" wire $0\logical_op__invert_in$10[0:0]$7043 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__invert_out$13$next[0:0]$6977 - attribute \src "libresoc.v:146902.3-146903.69" + attribute \src "libresoc.v:146698.3-146699.69" wire $0\logical_op__invert_out$13[0:0]$6945 - attribute \src "libresoc.v:146454.7-146454.41" + attribute \src "libresoc.v:146250.7-146250.41" wire $0\logical_op__invert_out$13[0:0]$7045 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__is_32bit$16$next[0:0]$6978 - attribute \src "libresoc.v:146908.3-146909.65" + attribute \src "libresoc.v:146704.3-146705.65" wire $0\logical_op__is_32bit$16[0:0]$6951 - attribute \src "libresoc.v:146463.7-146463.39" + attribute \src "libresoc.v:146259.7-146259.39" wire $0\logical_op__is_32bit$16[0:0]$7047 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__is_signed$17$next[0:0]$6979 - attribute \src "libresoc.v:146910.3-146911.67" + attribute \src "libresoc.v:146706.3-146707.67" wire $0\logical_op__is_signed$17[0:0]$6953 - attribute \src "libresoc.v:146472.7-146472.40" + attribute \src "libresoc.v:146268.7-146268.40" wire $0\logical_op__is_signed$17[0:0]$7049 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__oe__oe$8$next[0:0]$6980 - attribute \src "libresoc.v:146892.3-146893.59" + attribute \src "libresoc.v:146688.3-146689.59" wire $0\logical_op__oe__oe$8[0:0]$6935 - attribute \src "libresoc.v:146483.7-146483.36" + attribute \src "libresoc.v:146279.7-146279.36" wire $0\logical_op__oe__oe$8[0:0]$7051 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__oe__ok$9$next[0:0]$6981 - attribute \src "libresoc.v:146894.3-146895.59" + attribute \src "libresoc.v:146690.3-146691.59" wire $0\logical_op__oe__ok$9[0:0]$6937 - attribute \src "libresoc.v:146492.7-146492.36" + attribute \src "libresoc.v:146288.7-146288.36" wire $0\logical_op__oe__ok$9[0:0]$7053 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__output_carry$15$next[0:0]$6982 - attribute \src "libresoc.v:146906.3-146907.73" + attribute \src "libresoc.v:146702.3-146703.73" wire $0\logical_op__output_carry$15[0:0]$6949 - attribute \src "libresoc.v:146499.7-146499.43" + attribute \src "libresoc.v:146295.7-146295.43" wire $0\logical_op__output_carry$15[0:0]$7055 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__rc__ok$7$next[0:0]$6983 - attribute \src "libresoc.v:146890.3-146891.59" + attribute \src "libresoc.v:146686.3-146687.59" wire $0\logical_op__rc__ok$7[0:0]$6933 - attribute \src "libresoc.v:146510.7-146510.36" + attribute \src "libresoc.v:146306.7-146306.36" wire $0\logical_op__rc__ok$7[0:0]$7057 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__rc__rc$6$next[0:0]$6984 - attribute \src "libresoc.v:146888.3-146889.59" + attribute \src "libresoc.v:146684.3-146685.59" wire $0\logical_op__rc__rc$6[0:0]$6931 - attribute \src "libresoc.v:146519.7-146519.36" + attribute \src "libresoc.v:146315.7-146315.36" wire $0\logical_op__rc__rc$6[0:0]$7059 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__write_cr0$14$next[0:0]$6985 - attribute \src "libresoc.v:146904.3-146905.67" + attribute \src "libresoc.v:146700.3-146701.67" wire $0\logical_op__write_cr0$14[0:0]$6947 - attribute \src "libresoc.v:146526.7-146526.40" + attribute \src "libresoc.v:146322.7-146322.40" wire $0\logical_op__write_cr0$14[0:0]$7061 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__zero_a$11$next[0:0]$6986 - attribute \src "libresoc.v:146898.3-146899.61" + attribute \src "libresoc.v:146694.3-146695.61" wire $0\logical_op__zero_a$11[0:0]$6941 - attribute \src "libresoc.v:146535.7-146535.37" + attribute \src "libresoc.v:146331.7-146331.37" wire $0\logical_op__zero_a$11[0:0]$7063 - attribute \src "libresoc.v:146994.3-147006.6" + attribute \src "libresoc.v:146790.3-146802.6" wire width 2 $0\muxid$1$next[1:0]$6966 - attribute \src "libresoc.v:146916.3-146917.33" + attribute \src "libresoc.v:146712.3-146713.33" wire width 2 $0\muxid$1[1:0]$6959 - attribute \src "libresoc.v:146544.13-146544.29" + attribute \src "libresoc.v:146340.13-146340.29" wire width 2 $0\muxid$1[1:0]$7065 - attribute \src "libresoc.v:147049.3-147067.6" + attribute \src "libresoc.v:146845.3-146863.6" wire width 64 $0\o$20$next[63:0]$7012 - attribute \src "libresoc.v:146876.3-146877.27" + attribute \src "libresoc.v:146672.3-146673.27" wire width 64 $0\o$20[63:0]$6919 - attribute \src "libresoc.v:146559.14-146559.43" + attribute \src "libresoc.v:146355.14-146355.43" wire width 64 $0\o$20[63:0]$7067 - attribute \src "libresoc.v:147049.3-147067.6" + attribute \src "libresoc.v:146845.3-146863.6" wire $0\o_ok$21$next[0:0]$7013 - attribute \src "libresoc.v:146878.3-146879.33" + attribute \src "libresoc.v:146674.3-146675.33" wire $0\o_ok$21[0:0]$6921 - attribute \src "libresoc.v:146568.7-146568.23" + attribute \src "libresoc.v:146364.7-146364.23" wire $0\o_ok$21[0:0]$7069 - attribute \src "libresoc.v:146976.3-146993.6" + attribute \src "libresoc.v:146772.3-146789.6" wire $0\r_busy$next[0:0]$6962 - attribute \src "libresoc.v:146918.3-146919.29" + attribute \src "libresoc.v:146714.3-146715.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:147068.3-147086.6" + attribute \src "libresoc.v:146864.3-146882.6" wire width 4 $1\cr_a$22$next[3:0]$7020 - attribute \src "libresoc.v:147068.3-147086.6" + attribute \src "libresoc.v:146864.3-146882.6" wire $1\cr_a_ok$23$next[0:0]$7021 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 4 $1\logical_op__data_len$18$next[3:0]$6987 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 14 $1\logical_op__fn_unit$3$next[13:0]$6988 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6989 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__imm_data__ok$5$next[0:0]$6990 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 2 $1\logical_op__input_carry$12$next[1:0]$6991 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 32 $1\logical_op__insn$19$next[31:0]$6992 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 7 $1\logical_op__insn_type$2$next[6:0]$6993 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__invert_in$10$next[0:0]$6994 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__invert_out$13$next[0:0]$6995 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__is_32bit$16$next[0:0]$6996 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__is_signed$17$next[0:0]$6997 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__oe__oe$8$next[0:0]$6998 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__oe__ok$9$next[0:0]$6999 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__output_carry$15$next[0:0]$7000 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__rc__ok$7$next[0:0]$7001 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__rc__rc$6$next[0:0]$7002 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__write_cr0$14$next[0:0]$7003 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__zero_a$11$next[0:0]$7004 - attribute \src "libresoc.v:146994.3-147006.6" + attribute \src "libresoc.v:146790.3-146802.6" wire width 2 $1\muxid$1$next[1:0]$6967 - attribute \src "libresoc.v:147049.3-147067.6" + attribute \src "libresoc.v:146845.3-146863.6" wire width 64 $1\o$20$next[63:0]$7014 - attribute \src "libresoc.v:147049.3-147067.6" + attribute \src "libresoc.v:146845.3-146863.6" wire $1\o_ok$21$next[0:0]$7015 - attribute \src "libresoc.v:146976.3-146993.6" + attribute \src "libresoc.v:146772.3-146789.6" wire $1\r_busy$next[0:0]$6963 - attribute \src "libresoc.v:146862.7-146862.20" + attribute \src "libresoc.v:146658.7-146658.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:147068.3-147086.6" + attribute \src "libresoc.v:146864.3-146882.6" wire $2\cr_a_ok$23$next[0:0]$7022 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7005 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $2\logical_op__imm_data__ok$5$next[0:0]$7006 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $2\logical_op__oe__oe$8$next[0:0]$7007 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $2\logical_op__oe__ok$9$next[0:0]$7008 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $2\logical_op__rc__ok$7$next[0:0]$7009 - attribute \src "libresoc.v:147007.3-147048.6" + attribute \src "libresoc.v:146803.3-146844.6" wire $2\logical_op__rc__rc$6$next[0:0]$7010 - attribute \src "libresoc.v:147049.3-147067.6" + attribute \src "libresoc.v:146845.3-146863.6" wire $2\o_ok$21$next[0:0]$7016 - attribute \src "libresoc.v:146976.3-146993.6" + attribute \src "libresoc.v:146772.3-146789.6" wire $2\r_busy$next[0:0]$6964 - attribute \src "libresoc.v:146871.18-146871.118" - wire $and$libresoc.v:146871$6913_Y + attribute \src "libresoc.v:146667.18-146667.118" + wire $and$libresoc.v:146667$6913_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 25 \cr_a @@ -237170,7 +236966,7 @@ module \logical_pipe2 wire \cr_a_ok$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$73 - attribute \src "libresoc.v:146069.7-146069.15" + attribute \src "libresoc.v:145865.7-145865.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -237927,7 +237723,7 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:146871$6913 + cell $and $and$libresoc.v:146667$6913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237935,16 +237731,16 @@ module \logical_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$48 connect \B \p_ready_o - connect \Y $and$libresoc.v:146871$6913_Y + connect \Y $and$libresoc.v:146667$6913_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:146920.10-146923.4" + attribute \src "libresoc.v:146716.10-146719.4" cell \n$53 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:146924.15-146971.4" + attribute \src "libresoc.v:146720.15-146767.4" cell \output$54 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$45 @@ -237994,388 +237790,388 @@ module \logical_pipe2 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:146972.10-146975.4" + attribute \src "libresoc.v:146768.10-146771.4" cell \p$52 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:146069.7-146069.20" - process $proc$libresoc.v:146069$7023 + attribute \src "libresoc.v:145865.7-145865.20" + process $proc$libresoc.v:145865$7023 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146080.13-146080.29" - process $proc$libresoc.v:146080$7024 + attribute \src "libresoc.v:145876.13-145876.29" + process $proc$libresoc.v:145876$7024 assign { } { } assign $0\cr_a$22[3:0]$7025 4'0000 sync always sync init update \cr_a$22 $0\cr_a$22[3:0]$7025 end - attribute \src "libresoc.v:146089.7-146089.26" - process $proc$libresoc.v:146089$7026 + attribute \src "libresoc.v:145885.7-145885.26" + process $proc$libresoc.v:145885$7026 assign { } { } assign $0\cr_a_ok$23[0:0]$7027 1'0 sync always sync init update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7027 end - attribute \src "libresoc.v:146100.13-146100.45" - process $proc$libresoc.v:146100$7028 + attribute \src "libresoc.v:145896.13-145896.45" + process $proc$libresoc.v:145896$7028 assign { } { } assign $0\logical_op__data_len$18[3:0]$7029 4'0000 sync always sync init update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7029 end - attribute \src "libresoc.v:146139.14-146139.48" - process $proc$libresoc.v:146139$7030 + attribute \src "libresoc.v:145935.14-145935.48" + process $proc$libresoc.v:145935$7030 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$7031 14'00000000000000 sync always sync init update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7031 end - attribute \src "libresoc.v:146163.14-146163.67" - process $proc$libresoc.v:146163$7032 + attribute \src "libresoc.v:145959.14-145959.67" + process $proc$libresoc.v:145959$7032 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$7033 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7033 end - attribute \src "libresoc.v:146172.7-146172.42" - process $proc$libresoc.v:146172$7034 + attribute \src "libresoc.v:145968.7-145968.42" + process $proc$libresoc.v:145968$7034 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$7035 1'0 sync always sync init update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7035 end - attribute \src "libresoc.v:146189.13-146189.48" - process $proc$libresoc.v:146189$7036 + attribute \src "libresoc.v:145985.13-145985.48" + process $proc$libresoc.v:145985$7036 assign { } { } assign $0\logical_op__input_carry$12[1:0]$7037 2'00 sync always sync init update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7037 end - attribute \src "libresoc.v:146202.14-146202.43" - process $proc$libresoc.v:146202$7038 + attribute \src "libresoc.v:145998.14-145998.43" + process $proc$libresoc.v:145998$7038 assign { } { } assign $0\logical_op__insn$19[31:0]$7039 0 sync always sync init update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7039 end - attribute \src "libresoc.v:146361.13-146361.46" - process $proc$libresoc.v:146361$7040 + attribute \src "libresoc.v:146157.13-146157.46" + process $proc$libresoc.v:146157$7040 assign { } { } assign $0\logical_op__insn_type$2[6:0]$7041 7'0000000 sync always sync init update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7041 end - attribute \src "libresoc.v:146445.7-146445.40" - process $proc$libresoc.v:146445$7042 + attribute \src "libresoc.v:146241.7-146241.40" + process $proc$libresoc.v:146241$7042 assign { } { } assign $0\logical_op__invert_in$10[0:0]$7043 1'0 sync always sync init update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7043 end - attribute \src "libresoc.v:146454.7-146454.41" - process $proc$libresoc.v:146454$7044 + attribute \src "libresoc.v:146250.7-146250.41" + process $proc$libresoc.v:146250$7044 assign { } { } assign $0\logical_op__invert_out$13[0:0]$7045 1'0 sync always sync init update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7045 end - attribute \src "libresoc.v:146463.7-146463.39" - process $proc$libresoc.v:146463$7046 + attribute \src "libresoc.v:146259.7-146259.39" + process $proc$libresoc.v:146259$7046 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$7047 1'0 sync always sync init update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7047 end - attribute \src "libresoc.v:146472.7-146472.40" - process $proc$libresoc.v:146472$7048 + attribute \src "libresoc.v:146268.7-146268.40" + process $proc$libresoc.v:146268$7048 assign { } { } assign $0\logical_op__is_signed$17[0:0]$7049 1'0 sync always sync init update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7049 end - attribute \src "libresoc.v:146483.7-146483.36" - process $proc$libresoc.v:146483$7050 + attribute \src "libresoc.v:146279.7-146279.36" + process $proc$libresoc.v:146279$7050 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$7051 1'0 sync always sync init update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7051 end - attribute \src "libresoc.v:146492.7-146492.36" - process $proc$libresoc.v:146492$7052 + attribute \src "libresoc.v:146288.7-146288.36" + process $proc$libresoc.v:146288$7052 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$7053 1'0 sync always sync init update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7053 end - attribute \src "libresoc.v:146499.7-146499.43" - process $proc$libresoc.v:146499$7054 + attribute \src "libresoc.v:146295.7-146295.43" + process $proc$libresoc.v:146295$7054 assign { } { } assign $0\logical_op__output_carry$15[0:0]$7055 1'0 sync always sync init update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7055 end - attribute \src "libresoc.v:146510.7-146510.36" - process $proc$libresoc.v:146510$7056 + attribute \src "libresoc.v:146306.7-146306.36" + process $proc$libresoc.v:146306$7056 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$7057 1'0 sync always sync init update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7057 end - attribute \src "libresoc.v:146519.7-146519.36" - process $proc$libresoc.v:146519$7058 + attribute \src "libresoc.v:146315.7-146315.36" + process $proc$libresoc.v:146315$7058 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$7059 1'0 sync always sync init update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7059 end - attribute \src "libresoc.v:146526.7-146526.40" - process $proc$libresoc.v:146526$7060 + attribute \src "libresoc.v:146322.7-146322.40" + process $proc$libresoc.v:146322$7060 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$7061 1'0 sync always sync init update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7061 end - attribute \src "libresoc.v:146535.7-146535.37" - process $proc$libresoc.v:146535$7062 + attribute \src "libresoc.v:146331.7-146331.37" + process $proc$libresoc.v:146331$7062 assign { } { } assign $0\logical_op__zero_a$11[0:0]$7063 1'0 sync always sync init update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7063 end - attribute \src "libresoc.v:146544.13-146544.29" - process $proc$libresoc.v:146544$7064 + attribute \src "libresoc.v:146340.13-146340.29" + process $proc$libresoc.v:146340$7064 assign { } { } assign $0\muxid$1[1:0]$7065 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$7065 end - attribute \src "libresoc.v:146559.14-146559.43" - process $proc$libresoc.v:146559$7066 + attribute \src "libresoc.v:146355.14-146355.43" + process $proc$libresoc.v:146355$7066 assign { } { } assign $0\o$20[63:0]$7067 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$20 $0\o$20[63:0]$7067 end - attribute \src "libresoc.v:146568.7-146568.23" - process $proc$libresoc.v:146568$7068 + attribute \src "libresoc.v:146364.7-146364.23" + process $proc$libresoc.v:146364$7068 assign { } { } assign $0\o_ok$21[0:0]$7069 1'0 sync always sync init update \o_ok$21 $0\o_ok$21[0:0]$7069 end - attribute \src "libresoc.v:146862.7-146862.20" - process $proc$libresoc.v:146862$7070 + attribute \src "libresoc.v:146658.7-146658.20" + process $proc$libresoc.v:146658$7070 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:146872.3-146873.33" - process $proc$libresoc.v:146872$6914 + attribute \src "libresoc.v:146668.3-146669.33" + process $proc$libresoc.v:146668$6914 assign { } { } assign $0\cr_a$22[3:0]$6915 \cr_a$22$next sync posedge \coresync_clk update \cr_a$22 $0\cr_a$22[3:0]$6915 end - attribute \src "libresoc.v:146874.3-146875.39" - process $proc$libresoc.v:146874$6916 + attribute \src "libresoc.v:146670.3-146671.39" + process $proc$libresoc.v:146670$6916 assign { } { } assign $0\cr_a_ok$23[0:0]$6917 \cr_a_ok$23$next sync posedge \coresync_clk update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6917 end - attribute \src "libresoc.v:146876.3-146877.27" - process $proc$libresoc.v:146876$6918 + attribute \src "libresoc.v:146672.3-146673.27" + process $proc$libresoc.v:146672$6918 assign { } { } assign $0\o$20[63:0]$6919 \o$20$next sync posedge \coresync_clk update \o$20 $0\o$20[63:0]$6919 end - attribute \src "libresoc.v:146878.3-146879.33" - process $proc$libresoc.v:146878$6920 + attribute \src "libresoc.v:146674.3-146675.33" + process $proc$libresoc.v:146674$6920 assign { } { } assign $0\o_ok$21[0:0]$6921 \o_ok$21$next sync posedge \coresync_clk update \o_ok$21 $0\o_ok$21[0:0]$6921 end - attribute \src "libresoc.v:146880.3-146881.65" - process $proc$libresoc.v:146880$6922 + attribute \src "libresoc.v:146676.3-146677.65" + process $proc$libresoc.v:146676$6922 assign { } { } assign $0\logical_op__insn_type$2[6:0]$6923 \logical_op__insn_type$2$next sync posedge \coresync_clk update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6923 end - attribute \src "libresoc.v:146882.3-146883.61" - process $proc$libresoc.v:146882$6924 + attribute \src "libresoc.v:146678.3-146679.61" + process $proc$libresoc.v:146678$6924 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$6925 \logical_op__fn_unit$3$next sync posedge \coresync_clk update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6925 end - attribute \src "libresoc.v:146884.3-146885.75" - process $proc$libresoc.v:146884$6926 + attribute \src "libresoc.v:146680.3-146681.75" + process $proc$libresoc.v:146680$6926 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$6927 \logical_op__imm_data__data$4$next sync posedge \coresync_clk update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6927 end - attribute \src "libresoc.v:146886.3-146887.71" - process $proc$libresoc.v:146886$6928 + attribute \src "libresoc.v:146682.3-146683.71" + process $proc$libresoc.v:146682$6928 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$6929 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6929 end - attribute \src "libresoc.v:146888.3-146889.59" - process $proc$libresoc.v:146888$6930 + attribute \src "libresoc.v:146684.3-146685.59" + process $proc$libresoc.v:146684$6930 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$6931 \logical_op__rc__rc$6$next sync posedge \coresync_clk update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6931 end - attribute \src "libresoc.v:146890.3-146891.59" - process $proc$libresoc.v:146890$6932 + attribute \src "libresoc.v:146686.3-146687.59" + process $proc$libresoc.v:146686$6932 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$6933 \logical_op__rc__ok$7$next sync posedge \coresync_clk update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6933 end - attribute \src "libresoc.v:146892.3-146893.59" - process $proc$libresoc.v:146892$6934 + attribute \src "libresoc.v:146688.3-146689.59" + process $proc$libresoc.v:146688$6934 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$6935 \logical_op__oe__oe$8$next sync posedge \coresync_clk update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6935 end - attribute \src "libresoc.v:146894.3-146895.59" - process $proc$libresoc.v:146894$6936 + attribute \src "libresoc.v:146690.3-146691.59" + process $proc$libresoc.v:146690$6936 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$6937 \logical_op__oe__ok$9$next sync posedge \coresync_clk update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6937 end - attribute \src "libresoc.v:146896.3-146897.67" - process $proc$libresoc.v:146896$6938 + attribute \src "libresoc.v:146692.3-146693.67" + process $proc$libresoc.v:146692$6938 assign { } { } assign $0\logical_op__invert_in$10[0:0]$6939 \logical_op__invert_in$10$next sync posedge \coresync_clk update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6939 end - attribute \src "libresoc.v:146898.3-146899.61" - process $proc$libresoc.v:146898$6940 + attribute \src "libresoc.v:146694.3-146695.61" + process $proc$libresoc.v:146694$6940 assign { } { } assign $0\logical_op__zero_a$11[0:0]$6941 \logical_op__zero_a$11$next sync posedge \coresync_clk update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6941 end - attribute \src "libresoc.v:146900.3-146901.71" - process $proc$libresoc.v:146900$6942 + attribute \src "libresoc.v:146696.3-146697.71" + process $proc$libresoc.v:146696$6942 assign { } { } assign $0\logical_op__input_carry$12[1:0]$6943 \logical_op__input_carry$12$next sync posedge \coresync_clk update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6943 end - attribute \src "libresoc.v:146902.3-146903.69" - process $proc$libresoc.v:146902$6944 + attribute \src "libresoc.v:146698.3-146699.69" + process $proc$libresoc.v:146698$6944 assign { } { } assign $0\logical_op__invert_out$13[0:0]$6945 \logical_op__invert_out$13$next sync posedge \coresync_clk update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6945 end - attribute \src "libresoc.v:146904.3-146905.67" - process $proc$libresoc.v:146904$6946 + attribute \src "libresoc.v:146700.3-146701.67" + process $proc$libresoc.v:146700$6946 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$6947 \logical_op__write_cr0$14$next sync posedge \coresync_clk update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6947 end - attribute \src "libresoc.v:146906.3-146907.73" - process $proc$libresoc.v:146906$6948 + attribute \src "libresoc.v:146702.3-146703.73" + process $proc$libresoc.v:146702$6948 assign { } { } assign $0\logical_op__output_carry$15[0:0]$6949 \logical_op__output_carry$15$next sync posedge \coresync_clk update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6949 end - attribute \src "libresoc.v:146908.3-146909.65" - process $proc$libresoc.v:146908$6950 + attribute \src "libresoc.v:146704.3-146705.65" + process $proc$libresoc.v:146704$6950 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$6951 \logical_op__is_32bit$16$next sync posedge \coresync_clk update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6951 end - attribute \src "libresoc.v:146910.3-146911.67" - process $proc$libresoc.v:146910$6952 + attribute \src "libresoc.v:146706.3-146707.67" + process $proc$libresoc.v:146706$6952 assign { } { } assign $0\logical_op__is_signed$17[0:0]$6953 \logical_op__is_signed$17$next sync posedge \coresync_clk update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6953 end - attribute \src "libresoc.v:146912.3-146913.65" - process $proc$libresoc.v:146912$6954 + attribute \src "libresoc.v:146708.3-146709.65" + process $proc$libresoc.v:146708$6954 assign { } { } assign $0\logical_op__data_len$18[3:0]$6955 \logical_op__data_len$18$next sync posedge \coresync_clk update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6955 end - attribute \src "libresoc.v:146914.3-146915.57" - process $proc$libresoc.v:146914$6956 + attribute \src "libresoc.v:146710.3-146711.57" + process $proc$libresoc.v:146710$6956 assign { } { } assign $0\logical_op__insn$19[31:0]$6957 \logical_op__insn$19$next sync posedge \coresync_clk update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6957 end - attribute \src "libresoc.v:146916.3-146917.33" - process $proc$libresoc.v:146916$6958 + attribute \src "libresoc.v:146712.3-146713.33" + process $proc$libresoc.v:146712$6958 assign { } { } assign $0\muxid$1[1:0]$6959 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$6959 end - attribute \src "libresoc.v:146918.3-146919.29" - process $proc$libresoc.v:146918$6960 + attribute \src "libresoc.v:146714.3-146715.29" + process $proc$libresoc.v:146714$6960 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:146976.3-146993.6" - process $proc$libresoc.v:146976$6961 + attribute \src "libresoc.v:146772.3-146789.6" + process $proc$libresoc.v:146772$6961 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$6962 $2\r_busy$next[0:0]$6964 - attribute \src "libresoc.v:146977.5-146977.29" + attribute \src "libresoc.v:146773.5-146773.29" switch \initial - attribute \src "libresoc.v:146977.9-146977.17" + attribute \src "libresoc.v:146773.9-146773.17" case 1'1 case end @@ -238404,14 +238200,14 @@ module \logical_pipe2 sync always update \r_busy$next $0\r_busy$next[0:0]$6962 end - attribute \src "libresoc.v:146994.3-147006.6" - process $proc$libresoc.v:146994$6965 + attribute \src "libresoc.v:146790.3-146802.6" + process $proc$libresoc.v:146790$6965 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$6966 $1\muxid$1$next[1:0]$6967 - attribute \src "libresoc.v:146995.5-146995.29" + attribute \src "libresoc.v:146791.5-146791.29" switch \initial - attribute \src "libresoc.v:146995.9-146995.17" + attribute \src "libresoc.v:146791.9-146791.17" case 1'1 case end @@ -238431,8 +238227,8 @@ module \logical_pipe2 sync always update \muxid$1$next $0\muxid$1$next[1:0]$6966 end - attribute \src "libresoc.v:147007.3-147048.6" - process $proc$libresoc.v:147007$6968 + attribute \src "libresoc.v:146803.3-146844.6" + process $proc$libresoc.v:146803$6968 assign { } { } assign { } { } assign { } { } @@ -238493,9 +238289,9 @@ module \logical_pipe2 assign $0\logical_op__oe__ok$9$next[0:0]$6981 $2\logical_op__oe__ok$9$next[0:0]$7008 assign $0\logical_op__rc__ok$7$next[0:0]$6983 $2\logical_op__rc__ok$7$next[0:0]$7009 assign $0\logical_op__rc__rc$6$next[0:0]$6984 $2\logical_op__rc__rc$6$next[0:0]$7010 - attribute \src "libresoc.v:147008.5-147008.29" + attribute \src "libresoc.v:146804.5-146804.29" switch \initial - attribute \src "libresoc.v:147008.9-147008.17" + attribute \src "libresoc.v:146804.9-146804.17" case 1'1 case end @@ -238607,8 +238403,8 @@ module \logical_pipe2 update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6985 update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6986 end - attribute \src "libresoc.v:147049.3-147067.6" - process $proc$libresoc.v:147049$7011 + attribute \src "libresoc.v:146845.3-146863.6" + process $proc$libresoc.v:146845$7011 assign { } { } assign { } { } assign { } { } @@ -238616,9 +238412,9 @@ module \logical_pipe2 assign $0\o$20$next[63:0]$7012 $1\o$20$next[63:0]$7014 assign { } { } assign $0\o_ok$21$next[0:0]$7013 $2\o_ok$21$next[0:0]$7016 - attribute \src "libresoc.v:147050.5-147050.29" + attribute \src "libresoc.v:146846.5-146846.29" switch \initial - attribute \src "libresoc.v:147050.9-147050.17" + attribute \src "libresoc.v:146846.9-146846.17" case 1'1 case end @@ -238651,8 +238447,8 @@ module \logical_pipe2 update \o$20$next $0\o$20$next[63:0]$7012 update \o_ok$21$next $0\o_ok$21$next[0:0]$7013 end - attribute \src "libresoc.v:147068.3-147086.6" - process $proc$libresoc.v:147068$7017 + attribute \src "libresoc.v:146864.3-146882.6" + process $proc$libresoc.v:146864$7017 assign { } { } assign { } { } assign { } { } @@ -238660,9 +238456,9 @@ module \logical_pipe2 assign $0\cr_a$22$next[3:0]$7018 $1\cr_a$22$next[3:0]$7020 assign { } { } assign $0\cr_a_ok$23$next[0:0]$7019 $2\cr_a_ok$23$next[0:0]$7022 - attribute \src "libresoc.v:147069.5-147069.29" + attribute \src "libresoc.v:146865.5-146865.29" switch \initial - attribute \src "libresoc.v:147069.9-147069.17" + attribute \src "libresoc.v:146865.9-146865.17" case 1'1 case end @@ -238695,7 +238491,7 @@ module \logical_pipe2 update \cr_a$22$next $0\cr_a$22$next[3:0]$7018 update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7019 end - connect \$49 $and$libresoc.v:146871$6913_Y + connect \$49 $and$libresoc.v:146667$6913_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } @@ -238711,7877 +238507,7873 @@ module \logical_pipe2 connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_muxid \muxid end -attribute \src "ls180.v:4.1-5951.10" +attribute \src "ls180.v:4.1-5943.10" attribute \cells_not_processed 1 module \ls180 - attribute \src "ls180.v:5495.1-5505.4" - wire width 7 $0$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1435 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $0$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1436 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $0$memwr$\mem$ls180.v:5497$1_EN[31:0]$1437 - attribute \src "ls180.v:5495.1-5505.4" - wire width 7 $0$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1438 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $0$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1439 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $0$memwr$\mem$ls180.v:5499$2_EN[31:0]$1440 - attribute \src "ls180.v:5495.1-5505.4" - wire width 7 $0$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1441 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $0$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1442 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $0$memwr$\mem$ls180.v:5501$3_EN[31:0]$1443 - attribute \src "ls180.v:5495.1-5505.4" - wire width 7 $0$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1444 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $0$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1445 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $0$memwr$\mem$ls180.v:5503$4_EN[31:0]$1446 - attribute \src "ls180.v:5515.1-5525.4" - wire width 5 $0$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1461 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $0$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1462 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $0$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1463 - attribute \src "ls180.v:5515.1-5525.4" - wire width 5 $0$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1464 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $0$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1465 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $0$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1466 - attribute \src "ls180.v:5515.1-5525.4" - wire width 5 $0$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1467 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $0$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1468 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $0$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1469 - attribute \src "ls180.v:5515.1-5525.4" - wire width 5 $0$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1470 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $0$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1471 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $0$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1472 - attribute \src "ls180.v:5535.1-5539.4" - wire width 3 $0$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1487 - attribute \src "ls180.v:5535.1-5539.4" - wire width 25 $0$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1488 - attribute \src "ls180.v:5535.1-5539.4" - wire width 25 $0$memwr$\storage$ls180.v:5537$9_EN[24:0]$1489 - attribute \src "ls180.v:5549.1-5553.4" - wire width 3 $0$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1497 - attribute \src "ls180.v:5549.1-5553.4" - wire width 25 $0$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1498 - attribute \src "ls180.v:5549.1-5553.4" - wire width 25 $0$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1499 - attribute \src "ls180.v:5563.1-5567.4" - wire width 3 $0$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1507 - attribute \src "ls180.v:5563.1-5567.4" - wire width 25 $0$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1508 - attribute \src "ls180.v:5563.1-5567.4" - wire width 25 $0$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1509 - attribute \src "ls180.v:5577.1-5581.4" - wire width 3 $0$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1517 - attribute \src "ls180.v:5577.1-5581.4" - wire width 25 $0$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1518 - attribute \src "ls180.v:5577.1-5581.4" - wire width 25 $0$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1519 - attribute \src "ls180.v:5592.1-5596.4" - wire width 4 $0$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1527 - attribute \src "ls180.v:5592.1-5596.4" - wire width 10 $0$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1528 - attribute \src "ls180.v:5592.1-5596.4" - wire width 10 $0$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1529 - attribute \src "ls180.v:5609.1-5613.4" - wire width 4 $0$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1537 - attribute \src "ls180.v:5609.1-5613.4" - wire width 10 $0$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1538 - attribute \src "ls180.v:5609.1-5613.4" - wire width 10 $0$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1539 - attribute \src "ls180.v:3949.1-3965.4" + attribute \src "ls180.v:5490.1-5500.4" + wire width 7 $0$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1439 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $0$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1440 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $0$memwr$\mem$ls180.v:5492$1_EN[31:0]$1441 + attribute \src "ls180.v:5490.1-5500.4" + wire width 7 $0$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1442 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $0$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1443 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $0$memwr$\mem$ls180.v:5494$2_EN[31:0]$1444 + attribute \src "ls180.v:5490.1-5500.4" + wire width 7 $0$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1445 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $0$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1446 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $0$memwr$\mem$ls180.v:5496$3_EN[31:0]$1447 + attribute \src "ls180.v:5490.1-5500.4" + wire width 7 $0$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1448 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $0$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1449 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $0$memwr$\mem$ls180.v:5498$4_EN[31:0]$1450 + attribute \src "ls180.v:5510.1-5520.4" + wire width 5 $0$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1465 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1466 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1467 + attribute \src "ls180.v:5510.1-5520.4" + wire width 5 $0$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1468 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1469 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1470 + attribute \src "ls180.v:5510.1-5520.4" + wire width 5 $0$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1471 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1472 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1473 + attribute \src "ls180.v:5510.1-5520.4" + wire width 5 $0$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1474 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1475 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1476 + attribute \src "ls180.v:5530.1-5534.4" + wire width 3 $0$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1491 + attribute \src "ls180.v:5530.1-5534.4" + wire width 25 $0$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1492 + attribute \src "ls180.v:5530.1-5534.4" + wire width 25 $0$memwr$\storage$ls180.v:5532$9_EN[24:0]$1493 + attribute \src "ls180.v:5544.1-5548.4" + wire width 3 $0$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1501 + attribute \src "ls180.v:5544.1-5548.4" + wire width 25 $0$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1502 + attribute \src "ls180.v:5544.1-5548.4" + wire width 25 $0$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1503 + attribute \src "ls180.v:5558.1-5562.4" + wire width 3 $0$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1511 + attribute \src "ls180.v:5558.1-5562.4" + wire width 25 $0$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1512 + attribute \src "ls180.v:5558.1-5562.4" + wire width 25 $0$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1513 + attribute \src "ls180.v:5572.1-5576.4" + wire width 3 $0$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1521 + attribute \src "ls180.v:5572.1-5576.4" + wire width 25 $0$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1522 + attribute \src "ls180.v:5572.1-5576.4" + wire width 25 $0$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1523 + attribute \src "ls180.v:5587.1-5591.4" + wire width 4 $0$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1531 + attribute \src "ls180.v:5587.1-5591.4" + wire width 10 $0$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1532 + attribute \src "ls180.v:5587.1-5591.4" + wire width 10 $0$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1533 + attribute \src "ls180.v:5604.1-5608.4" + wire width 4 $0$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1541 + attribute \src "ls180.v:5604.1-5608.4" + wire width 10 $0$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1542 + attribute \src "ls180.v:5604.1-5608.4" + wire width 10 $0$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1543 + attribute \src "ls180.v:3940.1-3956.4" wire width 2 $0\array_muxed0[1:0] - attribute \src "ls180.v:3966.1-3982.4" + attribute \src "ls180.v:3957.1-3973.4" wire width 13 $0\array_muxed1[12:0] - attribute \src "ls180.v:3983.1-3999.4" + attribute \src "ls180.v:3974.1-3990.4" wire $0\array_muxed2[0:0] - attribute \src "ls180.v:4000.1-4016.4" + attribute \src "ls180.v:3991.1-4007.4" wire $0\array_muxed3[0:0] - attribute \src "ls180.v:4017.1-4033.4" + attribute \src "ls180.v:4008.1-4024.4" wire $0\array_muxed4[0:0] - attribute \src "ls180.v:4034.1-4050.4" + attribute \src "ls180.v:4025.1-4041.4" wire $0\array_muxed5[0:0] - attribute \src "ls180.v:4051.1-4067.4" + attribute \src "ls180.v:4042.1-4058.4" wire $0\array_muxed6[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\cmd_consumed[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\converter_counter[0:0] - attribute \src "ls180.v:2795.1-2841.4" + attribute \src "ls180.v:2786.1-2832.4" wire $0\converter_counter_subfragments_next_value[0:0] - attribute \src "ls180.v:2795.1-2841.4" + attribute \src "ls180.v:2786.1-2832.4" wire $0\converter_counter_subfragments_next_value_ce[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\converter_dat_r[31:0] - attribute \src "ls180.v:2795.1-2841.4" + attribute \src "ls180.v:2786.1-2832.4" wire $0\converter_skip[0:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire width 16 $0\dfi_p0_rddata[15:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:4285.1-5491.4" - wire width 36 $0\dummy[35:0] - attribute \src "ls180.v:1499.1-1504.4" + attribute \src "ls180.v:4276.1-5486.4" + wire width 40 $0\dummy[39:0] + attribute \src "ls180.v:1490.1-1495.4" wire width 3 $0\eint_tmp[2:0] - attribute \src "ls180.v:2903.1-2907.4" + attribute \src "ls180.v:2894.1-2898.4" wire width 2 $0\eventmanager_pending_w[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\eventmanager_re[0:0] - attribute \src "ls180.v:2892.1-2896.4" + attribute \src "ls180.v:2883.1-2887.4" wire width 2 $0\eventmanager_status_w[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\eventmanager_storage[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\gpio0_oe_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\gpio0_oe_storage[7:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\gpio0_out_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\gpio0_out_storage[7:0] - attribute \src "ls180.v:2971.1-2981.4" + attribute \src "ls180.v:2962.1-2972.4" wire width 8 $0\gpio0_pads_gpio0i[7:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio0_pads_gpio0o[7:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio0_pads_gpio0oe[7:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio0_status[7:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\gpio1_oe_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\gpio1_oe_storage[7:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\gpio1_out_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\gpio1_out_storage[7:0] - attribute \src "ls180.v:2982.1-2992.4" + attribute \src "ls180.v:2973.1-2983.4" wire width 8 $0\gpio1_pads_gpio1i[7:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio1_pads_gpio1o[7:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio1_pads_gpio1oe[7:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio1_status[7:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\i2c_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\i2c_storage[2:0] - attribute \src "ls180.v:4174.1-4176.4" + attribute \src "ls180.v:4165.1-4167.4" wire $0\int_rst[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_bus_errors[31:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:1532.1-1578.4" + attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] - attribute \src "ls180.v:1532.1-1578.4" + attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 64 $0\libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:1532.1-1578.4" + attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:1592.1-1638.4" + attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] - attribute \src "ls180.v:1592.1-1638.4" + attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 64 $0\libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:1592.1-1638.4" + attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:1652.1-1698.4" + attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] - attribute \src "ls180.v:1652.1-1698.4" + attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 64 $0\libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:1652.1-1698.4" + attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 20 $0\libresocsim_count[19:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_en_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_en_storage[0:0] - attribute \src "ls180.v:3149.1-3160.4" + attribute \src "ls180.v:3140.1-3151.4" wire $0\libresocsim_error[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\libresocsim_grant[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1532.1-1578.4" + attribute \src "ls180.v:1523.1-1569.4" wire width 30 $0\libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:152.11-152.64" + attribute \src "ls180.v:146.11-146.64" wire width 2 $0\libresocsim_interface0_converted_interface_bte[1:0] - attribute \src "ls180.v:151.11-151.64" + attribute \src "ls180.v:145.11-145.64" wire width 3 $0\libresocsim_interface0_converted_interface_cti[2:0] - attribute \src "ls180.v:1532.1-1578.4" + attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:1520.1-1530.4" + attribute \src "ls180.v:1511.1-1521.4" wire width 32 $0\libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:1532.1-1578.4" + attribute \src "ls180.v:1523.1-1569.4" wire width 4 $0\libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:1532.1-1578.4" + attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:1532.1-1578.4" + attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1592.1-1638.4" + attribute \src "ls180.v:1583.1-1629.4" wire width 30 $0\libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:167.11-167.64" + attribute \src "ls180.v:161.11-161.64" wire width 2 $0\libresocsim_interface1_converted_interface_bte[1:0] - attribute \src "ls180.v:166.11-166.64" + attribute \src "ls180.v:160.11-160.64" wire width 3 $0\libresocsim_interface1_converted_interface_cti[2:0] - attribute \src "ls180.v:1592.1-1638.4" + attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:1580.1-1590.4" + attribute \src "ls180.v:1571.1-1581.4" wire width 32 $0\libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:1592.1-1638.4" + attribute \src "ls180.v:1583.1-1629.4" wire width 4 $0\libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:1592.1-1638.4" + attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:1592.1-1638.4" + attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1652.1-1698.4" + attribute \src "ls180.v:1643.1-1689.4" wire width 30 $0\libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:182.11-182.64" + attribute \src "ls180.v:176.11-176.64" wire width 2 $0\libresocsim_interface2_converted_interface_bte[1:0] - attribute \src "ls180.v:181.11-181.64" + attribute \src "ls180.v:175.11-175.64" wire width 3 $0\libresocsim_interface2_converted_interface_cti[2:0] - attribute \src "ls180.v:1652.1-1698.4" + attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:1640.1-1650.4" + attribute \src "ls180.v:1631.1-1641.4" wire width 32 $0\libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:1652.1-1698.4" + attribute \src "ls180.v:1643.1-1689.4" wire width 4 $0\libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:1652.1-1698.4" + attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:1652.1-1698.4" + attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2993.1-3011.4" + attribute \src "ls180.v:2984.1-3002.4" wire width 16 $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] - attribute \src "ls180.v:3012.1-3030.4" + attribute \src "ls180.v:3003.1-3021.4" wire width 16 $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire width 13 $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire width 2 $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire width 2 $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire width 16 $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] - attribute \src "ls180.v:4178.1-4283.4" + attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] - attribute \src "ls180.v:136.5-136.64" + attribute \src "ls180.v:133.5-133.64" wire $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] - attribute \src "ls180.v:138.5-138.65" + attribute \src "ls180.v:135.5-135.65" wire $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] - attribute \src "ls180.v:137.5-137.65" + attribute \src "ls180.v:134.5-134.65" wire $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] - attribute \src "ls180.v:116.5-116.58" + attribute \src "ls180.v:117.5-117.58" wire $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] - attribute \src "ls180.v:1592.1-1638.4" + attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:64.5-64.41" + attribute \src "ls180.v:61.5-61.41" wire $0\libresocsim_libresoc_dbus_err[0:0] - attribute \src "ls180.v:1532.1-1578.4" + attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:73.5-73.41" + attribute \src "ls180.v:70.5-70.41" wire $0\libresocsim_libresoc_ibus_err[0:0] - attribute \src "ls180.v:1511.1-1518.4" + attribute \src "ls180.v:1502.1-1509.4" wire width 16 $0\libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:1652.1-1698.4" + attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:104.5-104.44" + attribute \src "ls180.v:101.5-101.44" wire $0\libresocsim_libresoc_jtag_wb_err[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 14 $0\libresocsim_libresocsim_adr[13:0] - attribute \src "ls180.v:3035.1-3071.4" + attribute \src "ls180.v:3026.1-3062.4" wire width 14 $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] - attribute \src "ls180.v:3035.1-3071.4" + attribute \src "ls180.v:3026.1-3062.4" wire $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_libresocsim_dat_w[7:0] - attribute \src "ls180.v:3035.1-3071.4" + attribute \src "ls180.v:3026.1-3062.4" wire width 8 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] - attribute \src "ls180.v:3035.1-3071.4" + attribute \src "ls180.v:3026.1-3062.4" wire $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_libresocsim_we[0:0] - attribute \src "ls180.v:3035.1-3071.4" + attribute \src "ls180.v:3026.1-3062.4" wire $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] - attribute \src "ls180.v:3035.1-3071.4" + attribute \src "ls180.v:3026.1-3062.4" wire $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] - attribute \src "ls180.v:3035.1-3071.4" + attribute \src "ls180.v:3026.1-3062.4" wire $0\libresocsim_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:3035.1-3071.4" + attribute \src "ls180.v:3026.1-3062.4" wire width 32 $0\libresocsim_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1071.5-1071.48" + attribute \src "ls180.v:1065.5-1065.48" wire $0\libresocsim_libresocsim_wishbone_err[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_load_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_load_storage[31:0] - attribute \src "ls180.v:3035.1-3071.4" + attribute \src "ls180.v:3026.1-3062.4" wire width 2 $0\libresocsim_next_state[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:198.5-198.35" + attribute \src "ls180.v:192.5-192.35" wire $0\libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_reload_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_reload_storage[31:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_reset_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_reset_storage[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_scratch_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:3149.1-3160.4" + attribute \src "ls180.v:3140.1-3151.4" wire $0\libresocsim_shared_ack[0:0] - attribute \src "ls180.v:3149.1-3160.4" + attribute \src "ls180.v:3140.1-3151.4" wire width 32 $0\libresocsim_shared_dat_r[31:0] - attribute \src "ls180.v:3090.1-3098.4" + attribute \src "ls180.v:3081.1-3089.4" wire width 6 $0\libresocsim_slave_sel[5:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 6 $0\libresocsim_slave_sel_r[5:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\libresocsim_state[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_update_value_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_value[31:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_value_status[31:0] - attribute \src "ls180.v:1701.1-1707.4" + attribute \src "ls180.v:1692.1-1698.4" wire width 4 $0\libresocsim_we[3:0] - attribute \src "ls180.v:1713.1-1718.4" + attribute \src "ls180.v:1704.1-1709.4" wire $0\libresocsim_zero_clear[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_zero_pending[0:0] - attribute \src "ls180.v:2795.1-2841.4" + attribute \src "ls180.v:2786.1-2832.4" wire width 30 $0\litedram_wb_adr[29:0] - attribute \src "ls180.v:2795.1-2841.4" + attribute \src "ls180.v:2786.1-2832.4" wire $0\litedram_wb_cyc[0:0] - attribute \src "ls180.v:2783.1-2793.4" + attribute \src "ls180.v:2774.1-2784.4" wire width 16 $0\litedram_wb_dat_w[15:0] - attribute \src "ls180.v:2795.1-2841.4" + attribute \src "ls180.v:2786.1-2832.4" wire width 2 $0\litedram_wb_sel[1:0] - attribute \src "ls180.v:2795.1-2841.4" + attribute \src "ls180.v:2786.1-2832.4" wire $0\litedram_wb_stb[0:0] - attribute \src "ls180.v:2795.1-2841.4" + attribute \src "ls180.v:2786.1-2832.4" wire $0\litedram_wb_we[0:0] - attribute \src "ls180.v:5495.1-5505.4" + attribute \src "ls180.v:5490.1-5500.4" wire width 7 $0\memadr[6:0] - attribute \src "ls180.v:5515.1-5525.4" + attribute \src "ls180.v:5510.1-5520.4" wire width 5 $0\memadr_1[4:0] - attribute \src "ls180.v:5535.1-5539.4" + attribute \src "ls180.v:5530.1-5534.4" wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:5549.1-5553.4" + attribute \src "ls180.v:5544.1-5548.4" wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:5563.1-5567.4" + attribute \src "ls180.v:5558.1-5562.4" wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:5577.1-5581.4" + attribute \src "ls180.v:5572.1-5576.4" wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:5592.1-5596.4" + attribute \src "ls180.v:5587.1-5591.4" wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:5598.1-5601.4" + attribute \src "ls180.v:5593.1-5596.4" wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:5609.1-5613.4" + attribute \src "ls180.v:5604.1-5608.4" wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:5615.1-5618.4" + attribute \src "ls180.v:5610.1-5613.4" wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\ram_bus_ram_bus_ack[0:0] - attribute \src "ls180.v:240.5-240.31" + attribute \src "ls180.v:234.5-234.31" wire $0\ram_bus_ram_bus_err[0:0] - attribute \src "ls180.v:1722.1-1728.4" + attribute \src "ls180.v:1713.1-1719.4" wire width 4 $0\ram_we[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\rddata_en[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\regs0[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\regs1[0:0] - attribute \src "ls180.v:978.5-978.17" + attribute \src "ls180.v:972.5-972.17" wire $0\reset[0:0] - attribute \src "ls180.v:3435.1-3451.4" + attribute \src "ls180.v:3426.1-3442.4" wire $0\rhs_array_muxed0[0:0] - attribute \src "ls180.v:3656.1-3672.4" + attribute \src "ls180.v:3647.1-3663.4" wire $0\rhs_array_muxed10[0:0] - attribute \src "ls180.v:3673.1-3689.4" + attribute \src "ls180.v:3664.1-3680.4" wire $0\rhs_array_muxed11[0:0] - attribute \src "ls180.v:3741.1-3748.4" + attribute \src "ls180.v:3732.1-3739.4" wire width 22 $0\rhs_array_muxed12[21:0] - attribute \src "ls180.v:3749.1-3756.4" + attribute \src "ls180.v:3740.1-3747.4" wire $0\rhs_array_muxed13[0:0] - attribute \src "ls180.v:3757.1-3764.4" + attribute \src "ls180.v:3748.1-3755.4" wire $0\rhs_array_muxed14[0:0] - attribute \src "ls180.v:3765.1-3772.4" + attribute \src "ls180.v:3756.1-3763.4" wire width 22 $0\rhs_array_muxed15[21:0] - attribute \src "ls180.v:3773.1-3780.4" + attribute \src "ls180.v:3764.1-3771.4" wire $0\rhs_array_muxed16[0:0] - attribute \src "ls180.v:3781.1-3788.4" + attribute \src "ls180.v:3772.1-3779.4" wire $0\rhs_array_muxed17[0:0] - attribute \src "ls180.v:3789.1-3796.4" + attribute \src "ls180.v:3780.1-3787.4" wire width 22 $0\rhs_array_muxed18[21:0] - attribute \src "ls180.v:3797.1-3804.4" + attribute \src "ls180.v:3788.1-3795.4" wire $0\rhs_array_muxed19[0:0] - attribute \src "ls180.v:3452.1-3468.4" + attribute \src "ls180.v:3443.1-3459.4" wire width 13 $0\rhs_array_muxed1[12:0] - attribute \src "ls180.v:3805.1-3812.4" + attribute \src "ls180.v:3796.1-3803.4" wire $0\rhs_array_muxed20[0:0] - attribute \src "ls180.v:3813.1-3820.4" + attribute \src "ls180.v:3804.1-3811.4" wire width 22 $0\rhs_array_muxed21[21:0] - attribute \src "ls180.v:3821.1-3828.4" + attribute \src "ls180.v:3812.1-3819.4" wire $0\rhs_array_muxed22[0:0] - attribute \src "ls180.v:3829.1-3836.4" + attribute \src "ls180.v:3820.1-3827.4" wire $0\rhs_array_muxed23[0:0] - attribute \src "ls180.v:3837.1-3850.4" + attribute \src "ls180.v:3828.1-3841.4" wire width 30 $0\rhs_array_muxed24[29:0] - attribute \src "ls180.v:3851.1-3864.4" + attribute \src "ls180.v:3842.1-3855.4" wire width 32 $0\rhs_array_muxed25[31:0] - attribute \src "ls180.v:3865.1-3878.4" + attribute \src "ls180.v:3856.1-3869.4" wire width 4 $0\rhs_array_muxed26[3:0] - attribute \src "ls180.v:3879.1-3892.4" + attribute \src "ls180.v:3870.1-3883.4" wire $0\rhs_array_muxed27[0:0] - attribute \src "ls180.v:3893.1-3906.4" + attribute \src "ls180.v:3884.1-3897.4" wire $0\rhs_array_muxed28[0:0] - attribute \src "ls180.v:3907.1-3920.4" + attribute \src "ls180.v:3898.1-3911.4" wire $0\rhs_array_muxed29[0:0] - attribute \src "ls180.v:3469.1-3485.4" + attribute \src "ls180.v:3460.1-3476.4" wire width 2 $0\rhs_array_muxed2[1:0] - attribute \src "ls180.v:3921.1-3934.4" + attribute \src "ls180.v:3912.1-3925.4" wire width 3 $0\rhs_array_muxed30[2:0] - attribute \src "ls180.v:3935.1-3948.4" + attribute \src "ls180.v:3926.1-3939.4" wire width 2 $0\rhs_array_muxed31[1:0] - attribute \src "ls180.v:3486.1-3502.4" + attribute \src "ls180.v:3477.1-3493.4" wire $0\rhs_array_muxed3[0:0] - attribute \src "ls180.v:3503.1-3519.4" + attribute \src "ls180.v:3494.1-3510.4" wire $0\rhs_array_muxed4[0:0] - attribute \src "ls180.v:3520.1-3536.4" + attribute \src "ls180.v:3511.1-3527.4" wire $0\rhs_array_muxed5[0:0] - attribute \src "ls180.v:3588.1-3604.4" + attribute \src "ls180.v:3579.1-3595.4" wire $0\rhs_array_muxed6[0:0] - attribute \src "ls180.v:3605.1-3621.4" + attribute \src "ls180.v:3596.1-3612.4" wire width 13 $0\rhs_array_muxed7[12:0] - attribute \src "ls180.v:3622.1-3638.4" + attribute \src "ls180.v:3613.1-3629.4" wire width 2 $0\rhs_array_muxed8[1:0] - attribute \src "ls180.v:3639.1-3655.4" + attribute \src "ls180.v:3630.1-3646.4" wire $0\rhs_array_muxed9[0:0] - attribute \src "ls180.v:2897.1-2902.4" + attribute \src "ls180.v:2888.1-2893.4" wire $0\rx_clear[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\rx_fifo_consume[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 5 $0\rx_fifo_level0[4:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\rx_fifo_produce[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\rx_fifo_readable[0:0] - attribute \src "ls180.v:960.5-960.27" + attribute \src "ls180.v:954.5-954.27" wire $0\rx_fifo_replace[0:0] - attribute \src "ls180.v:2955.1-2962.4" + attribute \src "ls180.v:2946.1-2953.4" wire width 4 $0\rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\rx_old_trigger[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\rx_pending[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_address_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_address_storage[12:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_baddress_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\sdram_baddress_storage[1:0] - attribute \src "ls180.v:1940.1-1947.4" + attribute \src "ls180.v:1931.1-1938.4" wire $0\sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:445.5-445.59" + attribute \src "ls180.v:439.5-439.59" wire $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:428.5-428.62" + attribute \src "ls180.v:422.5-422.62" wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:429.5-429.61" + attribute \src "ls180.v:423.5-423.61" wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:1962.1-1969.4" + attribute \src "ls180.v:1953.1-1960.4" wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 22 $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:1929.1-1936.4" + attribute \src "ls180.v:1920.1-1927.4" wire width 13 $0\sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:2627.1-2635.4" + attribute \src "ls180.v:2618.1-2626.4" wire $0\sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:487.32-487.71" + attribute \src "ls180.v:481.32-481.71" wire $0\sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:485.32-485.70" + attribute \src "ls180.v:479.32-479.70" wire $0\sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:2097.1-2104.4" + attribute \src "ls180.v:2088.1-2095.4" wire $0\sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:527.5-527.59" + attribute \src "ls180.v:521.5-521.59" wire $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:510.5-510.62" + attribute \src "ls180.v:504.5-504.62" wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:511.5-511.61" + attribute \src "ls180.v:505.5-505.61" wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:2119.1-2126.4" + attribute \src "ls180.v:2110.1-2117.4" wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 22 $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:2086.1-2093.4" + attribute \src "ls180.v:2077.1-2084.4" wire width 13 $0\sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:2636.1-2644.4" + attribute \src "ls180.v:2627.1-2635.4" wire $0\sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:569.32-569.71" + attribute \src "ls180.v:563.32-563.71" wire $0\sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:567.32-567.70" + attribute \src "ls180.v:561.32-561.70" wire $0\sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:2254.1-2261.4" + attribute \src "ls180.v:2245.1-2252.4" wire $0\sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:609.5-609.59" + attribute \src "ls180.v:603.5-603.59" wire $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:592.5-592.62" + attribute \src "ls180.v:586.5-586.62" wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:593.5-593.61" + attribute \src "ls180.v:587.5-587.61" wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:2276.1-2283.4" + attribute \src "ls180.v:2267.1-2274.4" wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 22 $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:2243.1-2250.4" + attribute \src "ls180.v:2234.1-2241.4" wire width 13 $0\sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:2645.1-2653.4" + attribute \src "ls180.v:2636.1-2644.4" wire $0\sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:651.32-651.71" + attribute \src "ls180.v:645.32-645.71" wire $0\sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:649.32-649.70" + attribute \src "ls180.v:643.32-643.70" wire $0\sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:2411.1-2418.4" + attribute \src "ls180.v:2402.1-2409.4" wire $0\sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:691.5-691.59" + attribute \src "ls180.v:685.5-685.59" wire $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:674.5-674.62" + attribute \src "ls180.v:668.5-668.62" wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:675.5-675.61" + attribute \src "ls180.v:669.5-669.61" wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:2433.1-2440.4" + attribute \src "ls180.v:2424.1-2431.4" wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 22 $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:2400.1-2407.4" + attribute \src "ls180.v:2391.1-2398.4" wire width 13 $0\sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:2654.1-2662.4" + attribute \src "ls180.v:2645.1-2653.4" wire $0\sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:733.32-733.71" + attribute \src "ls180.v:727.32-727.71" wire $0\sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:731.32-731.70" + attribute \src "ls180.v:725.32-725.70" wire $0\sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:2576.1-2581.4" + attribute \src "ls180.v:2567.1-2572.4" wire $0\sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:2582.1-2587.4" + attribute \src "ls180.v:2573.1-2578.4" wire $0\sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:2588.1-2593.4" + attribute \src "ls180.v:2579.1-2584.4" wire $0\sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:741.5-741.38" + attribute \src "ls180.v:735.5-735.38" wire $0\sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:2562.1-2568.4" + attribute \src "ls180.v:2553.1-2559.4" wire width 4 $0\sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:739.5-739.43" + attribute \src "ls180.v:733.5-733.43" wire $0\sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:738.5-738.38" + attribute \src "ls180.v:732.5-732.38" wire $0\sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:736.5-736.39" + attribute \src "ls180.v:730.5-730.39" wire $0\sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:737.5-737.40" + attribute \src "ls180.v:731.5-731.40" wire $0\sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:2609.1-2614.4" + attribute \src "ls180.v:2600.1-2605.4" wire $0\sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:2615.1-2620.4" + attribute \src "ls180.v:2606.1-2611.4" wire $0\sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:2621.1-2626.4" + attribute \src "ls180.v:2612.1-2617.4" wire $0\sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:2667.1-2739.4" + attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\sdram_choose_req_grant[1:0] - attribute \src "ls180.v:2595.1-2601.4" + attribute \src "ls180.v:2586.1-2592.4" wire width 4 $0\sdram_choose_req_valids[3:0] - attribute \src "ls180.v:2667.1-2739.4" + attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:2667.1-2739.4" + attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:2667.1-2739.4" + attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:1884.1-1914.4" + attribute \src "ls180.v:1875.1-1905.4" wire $0\sdram_cmd_last[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:389.5-389.37" + attribute \src "ls180.v:383.5-383.37" wire $0\sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:390.5-390.38" + attribute \src "ls180.v:384.5-384.38" wire $0\sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:2667.1-2739.4" + attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_cmd_ready[0:0] - attribute \src "ls180.v:1884.1-1914.4" + attribute \src "ls180.v:1875.1-1905.4" wire $0\sdram_cmd_valid[0:0] - attribute \src "ls180.v:325.5-325.33" + attribute \src "ls180.v:319.5-319.33" wire $0\sdram_command_issue_w[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_command_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 6 $0\sdram_command_storage[5:0] - attribute \src "ls180.v:374.5-374.30" + attribute \src "ls180.v:368.5-368.30" wire $0\sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:2667.1-2739.4" + attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_en0[0:0] - attribute \src "ls180.v:2667.1-2739.4" + attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_en1[0:0] - attribute \src "ls180.v:2763.1-2776.4" + attribute \src "ls180.v:2754.1-2767.4" wire width 16 $0\sdram_interface_wdata[15:0] - attribute \src "ls180.v:2763.1-2776.4" + attribute \src "ls180.v:2754.1-2767.4" wire width 2 $0\sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:275.5-275.31" + attribute \src "ls180.v:269.5-269.31" wire $0\sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:1825.1-1841.4" + attribute \src "ls180.v:1816.1-1832.4" wire $0\sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:1825.1-1841.4" + attribute \src "ls180.v:1816.1-1832.4" wire $0\sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:1825.1-1841.4" + attribute \src "ls180.v:1816.1-1832.4" wire $0\sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire width 16 $0\sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:1825.1-1841.4" + attribute \src "ls180.v:1816.1-1832.4" wire $0\sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire width 13 $0\sdram_master_p0_address[12:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire width 2 $0\sdram_master_p0_bank[1:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_cke[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_odt[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire width 16 $0\sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire width 2 $0\sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:772.12-772.31" + attribute \src "ls180.v:766.12-766.31" wire width 13 $0\sdram_nop_a[12:0] - attribute \src "ls180.v:773.11-773.30" + attribute \src "ls180.v:767.11-767.30" wire width 2 $0\sdram_nop_ba[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_postponer_count[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_postponer_req_o[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_sequencer_count[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_sequencer_counter[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_sequencer_done1[0:0] - attribute \src "ls180.v:1884.1-1914.4" + attribute \src "ls180.v:1875.1-1905.4" wire $0\sdram_sequencer_start0[0:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire width 16 $0\sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:1767.1-1821.4" + attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 16 $0\sdram_status[15:0] - attribute \src "ls180.v:775.5-775.26" + attribute \src "ls180.v:769.5-769.26" wire $0\sdram_steerer0[0:0] - attribute \src "ls180.v:776.5-776.26" + attribute \src "ls180.v:770.5-770.26" wire $0\sdram_steerer1[0:0] - attribute \src "ls180.v:2667.1-2739.4" + attribute \src "ls180.v:2658.1-2730.4" wire width 2 $0\sdram_steerer_sel[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_storage[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_tccdcon_count[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:780.32-780.58" + attribute \src "ls180.v:774.32-774.58" wire $0\sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 5 $0\sdram_time0[4:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_time1[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 10 $0\sdram_timer_count1[9:0] - attribute \src "ls180.v:778.32-778.58" + attribute \src "ls180.v:772.32-772.58" wire $0\sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_twtrcon_count[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_wrdata_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 16 $0\sdram_wrdata_storage[15:0] - attribute \src "ls180.v:1978.1-2071.4" + attribute \src "ls180.v:1969.1-2062.4" wire width 3 $0\subfragments_bankmachine0_next_state[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\subfragments_bankmachine0_state[2:0] - attribute \src "ls180.v:2135.1-2228.4" + attribute \src "ls180.v:2126.1-2219.4" wire width 3 $0\subfragments_bankmachine1_next_state[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\subfragments_bankmachine1_state[2:0] - attribute \src "ls180.v:2292.1-2385.4" + attribute \src "ls180.v:2283.1-2376.4" wire width 3 $0\subfragments_bankmachine2_next_state[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\subfragments_bankmachine2_state[2:0] - attribute \src "ls180.v:2449.1-2542.4" + attribute \src "ls180.v:2440.1-2533.4" wire width 3 $0\subfragments_bankmachine3_next_state[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\subfragments_bankmachine3_state[2:0] - attribute \src "ls180.v:1532.1-1578.4" + attribute \src "ls180.v:1523.1-1569.4" wire $0\subfragments_converter0_next_state[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_converter0_state[0:0] - attribute \src "ls180.v:1592.1-1638.4" + attribute \src "ls180.v:1583.1-1629.4" wire $0\subfragments_converter1_next_state[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_converter1_state[0:0] - attribute \src "ls180.v:1652.1-1698.4" + attribute \src "ls180.v:1643.1-1689.4" wire $0\subfragments_converter2_next_state[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_converter2_state[0:0] - attribute \src "ls180.v:1044.5-1044.32" + attribute \src "ls180.v:1038.5-1038.32" wire $0\subfragments_locked0[0:0] - attribute \src "ls180.v:1045.5-1045.32" + attribute \src "ls180.v:1039.5-1039.32" wire $0\subfragments_locked1[0:0] - attribute \src "ls180.v:1046.5-1046.32" + attribute \src "ls180.v:1040.5-1040.32" wire $0\subfragments_locked2[0:0] - attribute \src "ls180.v:1047.5-1047.32" + attribute \src "ls180.v:1041.5-1041.32" wire $0\subfragments_locked3[0:0] - attribute \src "ls180.v:2667.1-2739.4" + attribute \src "ls180.v:2658.1-2730.4" wire width 3 $0\subfragments_multiplexer_next_state[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\subfragments_multiplexer_state[2:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2795.1-2841.4" + attribute \src "ls180.v:2786.1-2832.4" wire $0\subfragments_next_state[0:0] - attribute \src "ls180.v:1884.1-1914.4" + attribute \src "ls180.v:1875.1-1905.4" wire width 2 $0\subfragments_refresher_next_state[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\subfragments_refresher_state[1:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_state[0:0] - attribute \src "ls180.v:3537.1-3553.4" + attribute \src "ls180.v:3528.1-3544.4" wire $0\t_array_muxed0[0:0] - attribute \src "ls180.v:3554.1-3570.4" + attribute \src "ls180.v:3545.1-3561.4" wire $0\t_array_muxed1[0:0] - attribute \src "ls180.v:3571.1-3587.4" + attribute \src "ls180.v:3562.1-3578.4" wire $0\t_array_muxed2[0:0] - attribute \src "ls180.v:3690.1-3706.4" + attribute \src "ls180.v:3681.1-3697.4" wire $0\t_array_muxed3[0:0] - attribute \src "ls180.v:3707.1-3723.4" + attribute \src "ls180.v:3698.1-3714.4" wire $0\t_array_muxed4[0:0] - attribute \src "ls180.v:3724.1-3740.4" + attribute \src "ls180.v:3715.1-3731.4" wire $0\t_array_muxed5[0:0] - attribute \src "ls180.v:2886.1-2891.4" + attribute \src "ls180.v:2877.1-2882.4" wire $0\tx_clear[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\tx_fifo_consume[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 5 $0\tx_fifo_level0[4:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\tx_fifo_produce[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\tx_fifo_readable[0:0] - attribute \src "ls180.v:923.5-923.27" + attribute \src "ls180.v:917.5-917.27" wire $0\tx_fifo_replace[0:0] - attribute \src "ls180.v:906.5-906.30" + attribute \src "ls180.v:900.5-900.30" wire $0\tx_fifo_sink_first[0:0] - attribute \src "ls180.v:907.5-907.29" + attribute \src "ls180.v:901.5-901.29" wire $0\tx_fifo_sink_last[0:0] - attribute \src "ls180.v:2925.1-2932.4" + attribute \src "ls180.v:2916.1-2923.4" wire width 4 $0\tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\tx_old_trigger[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\tx_pending[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_re[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_rx_busy[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_rx_r[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\uart_phy_rx_reg[7:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_sink_ready[0:0] - attribute \src "ls180.v:851.5-851.33" + attribute \src "ls180.v:845.5-845.33" wire $0\uart_phy_source_first[0:0] - attribute \src "ls180.v:852.5-852.32" + attribute \src "ls180.v:846.5-846.32" wire $0\uart_phy_source_last[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_source_valid[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\uart_phy_storage[31:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_tx_busy[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\uart_phy_tx_reg[7:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:2795.1-2841.4" + attribute \src "ls180.v:2786.1-2832.4" wire $0\wb_sdram_ack[0:0] - attribute \src "ls180.v:819.5-819.24" + attribute \src "ls180.v:813.5-813.24" wire $0\wb_sdram_err[0:0] - attribute \src "ls180.v:4285.1-5491.4" + attribute \src "ls180.v:4276.1-5486.4" wire $0\wdata_consumed[0:0] - attribute \src "ls180.v:5495.1-5505.4" - wire width 7 $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 - attribute \src "ls180.v:5495.1-5505.4" - wire width 7 $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 - attribute \src "ls180.v:5495.1-5505.4" - wire width 7 $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 - attribute \src "ls180.v:5495.1-5505.4" - wire width 7 $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 - attribute \src "ls180.v:5495.1-5505.4" - wire width 32 $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 - attribute \src "ls180.v:5515.1-5525.4" - wire width 5 $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 - attribute \src "ls180.v:5515.1-5525.4" - wire width 5 $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 - attribute \src "ls180.v:5515.1-5525.4" - wire width 5 $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 - attribute \src "ls180.v:5515.1-5525.4" - wire width 5 $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 - attribute \src "ls180.v:5515.1-5525.4" - wire width 32 $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 - attribute \src "ls180.v:5535.1-5539.4" - wire width 3 $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 - attribute \src "ls180.v:5535.1-5539.4" - wire width 25 $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 - attribute \src "ls180.v:5535.1-5539.4" - wire width 25 $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 - attribute \src "ls180.v:5549.1-5553.4" - wire width 3 $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 - attribute \src "ls180.v:5549.1-5553.4" - wire width 25 $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 - attribute \src "ls180.v:5549.1-5553.4" - wire width 25 $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 - attribute \src "ls180.v:5563.1-5567.4" - wire width 3 $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 - attribute \src "ls180.v:5563.1-5567.4" - wire width 25 $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 - attribute \src "ls180.v:5563.1-5567.4" - wire width 25 $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 - attribute \src "ls180.v:5577.1-5581.4" - wire width 3 $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 - attribute \src "ls180.v:5577.1-5581.4" - wire width 25 $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 - attribute \src "ls180.v:5577.1-5581.4" - wire width 25 $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 - attribute \src "ls180.v:5592.1-5596.4" - wire width 4 $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 - attribute \src "ls180.v:5592.1-5596.4" - wire width 10 $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 - attribute \src "ls180.v:5592.1-5596.4" - wire width 10 $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 - attribute \src "ls180.v:5609.1-5613.4" - wire width 4 $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 - attribute \src "ls180.v:5609.1-5613.4" - wire width 10 $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 - attribute \src "ls180.v:5609.1-5613.4" - wire width 10 $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 - attribute \src "ls180.v:1381.11-1381.30" + attribute \src "ls180.v:5490.1-5500.4" + wire width 7 $1$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1451 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $1$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1452 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $1$memwr$\mem$ls180.v:5492$1_EN[31:0]$1453 + attribute \src "ls180.v:5490.1-5500.4" + wire width 7 $1$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1454 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $1$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1455 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $1$memwr$\mem$ls180.v:5494$2_EN[31:0]$1456 + attribute \src "ls180.v:5490.1-5500.4" + wire width 7 $1$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1457 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $1$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1458 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $1$memwr$\mem$ls180.v:5496$3_EN[31:0]$1459 + attribute \src "ls180.v:5490.1-5500.4" + wire width 7 $1$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1460 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $1$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1461 + attribute \src "ls180.v:5490.1-5500.4" + wire width 32 $1$memwr$\mem$ls180.v:5498$4_EN[31:0]$1462 + attribute \src "ls180.v:5510.1-5520.4" + wire width 5 $1$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1477 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1478 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1479 + attribute \src "ls180.v:5510.1-5520.4" + wire width 5 $1$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1480 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1481 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1482 + attribute \src "ls180.v:5510.1-5520.4" + wire width 5 $1$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1483 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1484 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1485 + attribute \src "ls180.v:5510.1-5520.4" + wire width 5 $1$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1486 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1487 + attribute \src "ls180.v:5510.1-5520.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1488 + attribute \src "ls180.v:5530.1-5534.4" + wire width 3 $1$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1494 + attribute \src "ls180.v:5530.1-5534.4" + wire width 25 $1$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1495 + attribute \src "ls180.v:5530.1-5534.4" + wire width 25 $1$memwr$\storage$ls180.v:5532$9_EN[24:0]$1496 + attribute \src "ls180.v:5544.1-5548.4" + wire width 3 $1$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1504 + attribute \src "ls180.v:5544.1-5548.4" + wire width 25 $1$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1505 + attribute \src "ls180.v:5544.1-5548.4" + wire width 25 $1$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1506 + attribute \src "ls180.v:5558.1-5562.4" + wire width 3 $1$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1514 + attribute \src "ls180.v:5558.1-5562.4" + wire width 25 $1$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1515 + attribute \src "ls180.v:5558.1-5562.4" + wire width 25 $1$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1516 + attribute \src "ls180.v:5572.1-5576.4" + wire width 3 $1$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1524 + attribute \src "ls180.v:5572.1-5576.4" + wire width 25 $1$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1525 + attribute \src "ls180.v:5572.1-5576.4" + wire width 25 $1$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1526 + attribute \src "ls180.v:5587.1-5591.4" + wire width 4 $1$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1534 + attribute \src "ls180.v:5587.1-5591.4" + wire width 10 $1$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1535 + attribute \src "ls180.v:5587.1-5591.4" + wire width 10 $1$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1536 + attribute \src "ls180.v:5604.1-5608.4" + wire width 4 $1$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1544 + attribute \src "ls180.v:5604.1-5608.4" + wire width 10 $1$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1545 + attribute \src "ls180.v:5604.1-5608.4" + wire width 10 $1$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1546 + attribute \src "ls180.v:1375.11-1375.30" wire width 2 $1\array_muxed0[1:0] - attribute \src "ls180.v:1382.12-1382.32" + attribute \src "ls180.v:1376.12-1376.32" wire width 13 $1\array_muxed1[12:0] - attribute \src "ls180.v:1383.5-1383.24" + attribute \src "ls180.v:1377.5-1377.24" wire $1\array_muxed2[0:0] - attribute \src "ls180.v:1384.5-1384.24" + attribute \src "ls180.v:1378.5-1378.24" wire $1\array_muxed3[0:0] - attribute \src "ls180.v:1385.5-1385.24" + attribute \src "ls180.v:1379.5-1379.24" wire $1\array_muxed4[0:0] - attribute \src "ls180.v:1386.5-1386.24" + attribute \src "ls180.v:1380.5-1380.24" wire $1\array_muxed5[0:0] - attribute \src "ls180.v:1387.5-1387.24" + attribute \src "ls180.v:1381.5-1381.24" wire $1\array_muxed6[0:0] - attribute \src "ls180.v:832.5-832.24" + attribute \src "ls180.v:826.5-826.24" wire $1\cmd_consumed[0:0] - attribute \src "ls180.v:829.5-829.29" + attribute \src "ls180.v:823.5-823.29" wire $1\converter_counter[0:0] - attribute \src "ls180.v:1055.5-1055.53" + attribute \src "ls180.v:1049.5-1049.53" wire $1\converter_counter_subfragments_next_value[0:0] - attribute \src "ls180.v:1056.5-1056.56" + attribute \src "ls180.v:1050.5-1050.56" wire $1\converter_counter_subfragments_next_value_ce[0:0] - attribute \src "ls180.v:831.12-831.35" + attribute \src "ls180.v:825.12-825.35" wire width 32 $1\converter_dat_r[31:0] - attribute \src "ls180.v:828.5-828.26" + attribute \src "ls180.v:822.5-822.26" wire $1\converter_skip[0:0] - attribute \src "ls180.v:263.12-263.33" + attribute \src "ls180.v:257.12-257.33" wire width 16 $1\dfi_p0_rddata[15:0] - attribute \src "ls180.v:264.5-264.31" + attribute \src "ls180.v:258.5-258.31" wire $1\dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:999.12-999.25" - wire width 36 $1\dummy[35:0] - attribute \src "ls180.v:997.11-997.26" + attribute \src "ls180.v:993.12-993.25" + wire width 40 $1\dummy[39:0] + attribute \src "ls180.v:991.11-991.26" wire width 3 $1\eint_tmp[2:0] - attribute \src "ls180.v:887.11-887.40" + attribute \src "ls180.v:881.11-881.40" wire width 2 $1\eventmanager_pending_w[1:0] - attribute \src "ls180.v:889.5-889.27" + attribute \src "ls180.v:883.5-883.27" wire $1\eventmanager_re[0:0] - attribute \src "ls180.v:883.11-883.39" + attribute \src "ls180.v:877.11-877.39" wire width 2 $1\eventmanager_status_w[1:0] - attribute \src "ls180.v:888.11-888.38" + attribute \src "ls180.v:882.11-882.38" wire width 2 $1\eventmanager_storage[1:0] - attribute \src "ls180.v:980.5-980.23" + attribute \src "ls180.v:974.5-974.23" wire $1\gpio0_oe_re[0:0] - attribute \src "ls180.v:979.11-979.34" + attribute \src "ls180.v:973.11-973.34" wire width 8 $1\gpio0_oe_storage[7:0] - attribute \src "ls180.v:984.5-984.24" + attribute \src "ls180.v:978.5-978.24" wire $1\gpio0_out_re[0:0] - attribute \src "ls180.v:983.11-983.35" + attribute \src "ls180.v:977.11-977.35" wire width 8 $1\gpio0_out_storage[7:0] - attribute \src "ls180.v:985.11-985.35" + attribute \src "ls180.v:979.11-979.35" wire width 8 $1\gpio0_pads_gpio0i[7:0] - attribute \src "ls180.v:986.11-986.35" + attribute \src "ls180.v:980.11-980.35" wire width 8 $1\gpio0_pads_gpio0o[7:0] - attribute \src "ls180.v:987.11-987.36" + attribute \src "ls180.v:981.11-981.36" wire width 8 $1\gpio0_pads_gpio0oe[7:0] - attribute \src "ls180.v:981.11-981.30" + attribute \src "ls180.v:975.11-975.30" wire width 8 $1\gpio0_status[7:0] - attribute \src "ls180.v:989.5-989.23" + attribute \src "ls180.v:983.5-983.23" wire $1\gpio1_oe_re[0:0] - attribute \src "ls180.v:988.11-988.34" + attribute \src "ls180.v:982.11-982.34" wire width 8 $1\gpio1_oe_storage[7:0] - attribute \src "ls180.v:993.5-993.24" + attribute \src "ls180.v:987.5-987.24" wire $1\gpio1_out_re[0:0] - attribute \src "ls180.v:992.11-992.35" + attribute \src "ls180.v:986.11-986.35" wire width 8 $1\gpio1_out_storage[7:0] - attribute \src "ls180.v:994.11-994.35" + attribute \src "ls180.v:988.11-988.35" wire width 8 $1\gpio1_pads_gpio1i[7:0] - attribute \src "ls180.v:995.11-995.35" + attribute \src "ls180.v:989.11-989.35" wire width 8 $1\gpio1_pads_gpio1o[7:0] - attribute \src "ls180.v:996.11-996.36" + attribute \src "ls180.v:990.11-990.36" wire width 8 $1\gpio1_pads_gpio1oe[7:0] - attribute \src "ls180.v:990.11-990.30" + attribute \src "ls180.v:984.11-984.30" wire width 8 $1\gpio1_status[7:0] - attribute \src "ls180.v:1004.5-1004.18" + attribute \src "ls180.v:998.5-998.18" wire $1\i2c_re[0:0] - attribute \src "ls180.v:1003.11-1003.29" + attribute \src "ls180.v:997.11-997.29" wire width 3 $1\i2c_storage[2:0] - attribute \src "ls180.v:248.5-248.19" + attribute \src "ls180.v:242.5-242.19" wire $1\int_rst[0:0] - attribute \src "ls180.v:53.12-53.42" + attribute \src "ls180.v:50.12-50.42" wire width 32 $1\libresocsim_bus_errors[31:0] - attribute \src "ls180.v:155.5-155.42" + attribute \src "ls180.v:149.5-149.42" wire $1\libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:1010.5-1010.77" + attribute \src "ls180.v:1004.5-1004.77" wire $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] - attribute \src "ls180.v:1011.5-1011.80" + attribute \src "ls180.v:1005.5-1005.80" wire $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] - attribute \src "ls180.v:157.12-157.48" + attribute \src "ls180.v:151.12-151.48" wire width 64 $1\libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:154.5-154.39" + attribute \src "ls180.v:148.5-148.39" wire $1\libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:170.5-170.42" + attribute \src "ls180.v:164.5-164.42" wire $1\libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:1014.5-1014.77" + attribute \src "ls180.v:1008.5-1008.77" wire $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] - attribute \src "ls180.v:1015.5-1015.80" + attribute \src "ls180.v:1009.5-1009.80" wire $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] - attribute \src "ls180.v:172.12-172.48" + attribute \src "ls180.v:166.12-166.48" wire width 64 $1\libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:169.5-169.39" + attribute \src "ls180.v:163.5-163.39" wire $1\libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:185.5-185.42" + attribute \src "ls180.v:179.5-179.42" wire $1\libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:1018.5-1018.77" + attribute \src "ls180.v:1012.5-1012.77" wire $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] - attribute \src "ls180.v:1019.5-1019.80" + attribute \src "ls180.v:1013.5-1013.80" wire $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] - attribute \src "ls180.v:187.12-187.48" + attribute \src "ls180.v:181.12-181.48" wire width 64 $1\libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:184.5-184.39" + attribute \src "ls180.v:178.5-178.39" wire $1\libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:1090.12-1090.43" + attribute \src "ls180.v:1084.12-1084.43" wire width 20 $1\libresocsim_count[19:0] - attribute \src "ls180.v:208.5-208.29" + attribute \src "ls180.v:202.5-202.29" wire $1\libresocsim_en_re[0:0] - attribute \src "ls180.v:207.5-207.34" + attribute \src "ls180.v:201.5-201.34" wire $1\libresocsim_en_storage[0:0] - attribute \src "ls180.v:1087.5-1087.29" + attribute \src "ls180.v:1081.5-1081.29" wire $1\libresocsim_error[0:0] - attribute \src "ls180.v:228.5-228.39" + attribute \src "ls180.v:222.5-222.39" wire $1\libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:227.5-227.44" + attribute \src "ls180.v:221.5-221.44" wire $1\libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:1084.11-1084.35" + attribute \src "ls180.v:1078.11-1078.35" wire width 2 $1\libresocsim_grant[1:0] - attribute \src "ls180.v:1094.11-1094.55" + attribute \src "ls180.v:1088.11-1088.55" wire width 8 $1\libresocsim_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:143.12-143.66" + attribute \src "ls180.v:137.12-137.66" wire width 30 $1\libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:147.5-147.58" + attribute \src "ls180.v:141.5-141.58" wire $1\libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:144.12-144.68" + attribute \src "ls180.v:138.12-138.68" wire width 32 $1\libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:146.11-146.64" + attribute \src "ls180.v:140.11-140.64" wire width 4 $1\libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:148.5-148.58" + attribute \src "ls180.v:142.5-142.58" wire $1\libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:150.5-150.57" + attribute \src "ls180.v:144.5-144.57" wire $1\libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:1135.11-1135.55" + attribute \src "ls180.v:1129.11-1129.55" wire width 8 $1\libresocsim_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:158.12-158.66" + attribute \src "ls180.v:152.12-152.66" wire width 30 $1\libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:162.5-162.58" + attribute \src "ls180.v:156.5-156.58" wire $1\libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:159.12-159.68" + attribute \src "ls180.v:153.12-153.68" wire width 32 $1\libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:161.11-161.64" + attribute \src "ls180.v:155.11-155.64" wire width 4 $1\libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:163.5-163.58" + attribute \src "ls180.v:157.5-157.58" wire $1\libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:165.5-165.57" + attribute \src "ls180.v:159.5-159.57" wire $1\libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:1152.11-1152.55" + attribute \src "ls180.v:1146.11-1146.55" wire width 8 $1\libresocsim_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:173.12-173.66" + attribute \src "ls180.v:167.12-167.66" wire width 30 $1\libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:177.5-177.58" + attribute \src "ls180.v:171.5-171.58" wire $1\libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:174.12-174.68" + attribute \src "ls180.v:168.12-168.68" wire width 32 $1\libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:176.11-176.64" + attribute \src "ls180.v:170.11-170.64" wire width 4 $1\libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:178.5-178.58" + attribute \src "ls180.v:172.5-172.58" wire $1\libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:180.5-180.57" + attribute \src "ls180.v:174.5-174.57" wire $1\libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:1169.11-1169.55" + attribute \src "ls180.v:1163.11-1163.55" wire width 8 $1\libresocsim_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1182.11-1182.55" + attribute \src "ls180.v:1176.11-1176.55" wire width 8 $1\libresocsim_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1223.11-1223.55" + attribute \src "ls180.v:1217.11-1217.55" wire width 8 $1\libresocsim_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1288.11-1288.55" + attribute \src "ls180.v:1282.11-1282.55" wire width 8 $1\libresocsim_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1313.11-1313.55" + attribute \src "ls180.v:1307.11-1307.55" wire width 8 $1\libresocsim_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:141.12-141.65" + attribute \src "ls180.v:131.12-131.65" wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] - attribute \src "ls180.v:142.12-142.66" + attribute \src "ls180.v:132.12-132.66" wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] - attribute \src "ls180.v:120.12-120.66" + attribute \src "ls180.v:118.12-118.66" wire width 13 $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] - attribute \src "ls180.v:129.11-129.65" + attribute \src "ls180.v:127.11-127.65" wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] - attribute \src "ls180.v:126.5-126.62" + attribute \src "ls180.v:124.5-124.62" wire $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] - attribute \src "ls180.v:128.5-128.60" + attribute \src "ls180.v:126.5-126.60" wire $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] - attribute \src "ls180.v:131.5-131.62" + attribute \src "ls180.v:129.5-129.62" wire $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] - attribute \src "ls180.v:127.5-127.61" + attribute \src "ls180.v:125.5-125.61" wire $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] - attribute \src "ls180.v:130.11-130.65" + attribute \src "ls180.v:128.11-128.65" wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] - attribute \src "ls180.v:122.12-122.69" + attribute \src "ls180.v:120.12-120.69" wire width 16 $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] - attribute \src "ls180.v:123.5-123.62" + attribute \src "ls180.v:121.5-121.62" wire $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] - attribute \src "ls180.v:125.5-125.62" + attribute \src "ls180.v:123.5-123.62" wire $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] - attribute \src "ls180.v:124.5-124.61" + attribute \src "ls180.v:122.5-122.61" wire $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] - attribute \src "ls180.v:115.5-115.58" + attribute \src "ls180.v:116.5-116.58" wire $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] - attribute \src "ls180.v:62.5-62.41" + attribute \src "ls180.v:59.5-59.41" wire $1\libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:71.5-71.41" + attribute \src "ls180.v:68.5-68.41" wire $1\libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:55.12-55.50" + attribute \src "ls180.v:52.12-52.50" wire width 16 $1\libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:102.5-102.44" + attribute \src "ls180.v:99.5-99.44" wire $1\libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:1057.12-1057.47" + attribute \src "ls180.v:1051.12-1051.47" wire width 14 $1\libresocsim_libresocsim_adr[13:0] - attribute \src "ls180.v:1339.12-1339.71" + attribute \src "ls180.v:1333.12-1333.71" wire width 14 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] - attribute \src "ls180.v:1340.5-1340.66" + attribute \src "ls180.v:1334.5-1334.66" wire $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] - attribute \src "ls180.v:1059.11-1059.47" + attribute \src "ls180.v:1053.11-1053.47" wire width 8 $1\libresocsim_libresocsim_dat_w[7:0] - attribute \src "ls180.v:1337.11-1337.71" + attribute \src "ls180.v:1331.11-1331.71" wire width 8 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] - attribute \src "ls180.v:1338.5-1338.68" + attribute \src "ls180.v:1332.5-1332.68" wire $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] - attribute \src "ls180.v:1058.5-1058.38" + attribute \src "ls180.v:1052.5-1052.38" wire $1\libresocsim_libresocsim_we[0:0] - attribute \src "ls180.v:1341.5-1341.62" + attribute \src "ls180.v:1335.5-1335.62" wire $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] - attribute \src "ls180.v:1342.5-1342.65" + attribute \src "ls180.v:1336.5-1336.65" wire $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] - attribute \src "ls180.v:1067.5-1067.48" + attribute \src "ls180.v:1061.5-1061.48" wire $1\libresocsim_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1063.12-1063.58" + attribute \src "ls180.v:1057.12-1057.58" wire width 32 $1\libresocsim_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:204.5-204.31" + attribute \src "ls180.v:198.5-198.31" wire $1\libresocsim_load_re[0:0] - attribute \src "ls180.v:203.12-203.44" + attribute \src "ls180.v:197.12-197.44" wire width 32 $1\libresocsim_load_storage[31:0] - attribute \src "ls180.v:1336.11-1336.40" + attribute \src "ls180.v:1330.11-1330.40" wire width 2 $1\libresocsim_next_state[1:0] - attribute \src "ls180.v:194.5-194.35" + attribute \src "ls180.v:188.5-188.35" wire $1\libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:206.5-206.33" + attribute \src "ls180.v:200.5-200.33" wire $1\libresocsim_reload_re[0:0] - attribute \src "ls180.v:205.12-205.46" + attribute \src "ls180.v:199.12-199.46" wire width 32 $1\libresocsim_reload_storage[31:0] - attribute \src "ls180.v:46.5-46.32" + attribute \src "ls180.v:43.5-43.32" wire $1\libresocsim_reset_re[0:0] - attribute \src "ls180.v:45.5-45.37" + attribute \src "ls180.v:42.5-42.37" wire $1\libresocsim_reset_storage[0:0] - attribute \src "ls180.v:48.5-48.34" + attribute \src "ls180.v:45.5-45.34" wire $1\libresocsim_scratch_re[0:0] - attribute \src "ls180.v:47.12-47.55" + attribute \src "ls180.v:44.12-44.55" wire width 32 $1\libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:1078.5-1078.34" + attribute \src "ls180.v:1072.5-1072.34" wire $1\libresocsim_shared_ack[0:0] - attribute \src "ls180.v:1074.12-1074.44" + attribute \src "ls180.v:1068.12-1068.44" wire width 32 $1\libresocsim_shared_dat_r[31:0] - attribute \src "ls180.v:1085.11-1085.39" + attribute \src "ls180.v:1079.11-1079.39" wire width 6 $1\libresocsim_slave_sel[5:0] - attribute \src "ls180.v:1086.11-1086.41" + attribute \src "ls180.v:1080.11-1080.41" wire width 6 $1\libresocsim_slave_sel_r[5:0] - attribute \src "ls180.v:1335.11-1335.35" + attribute \src "ls180.v:1329.11-1329.35" wire width 2 $1\libresocsim_state[1:0] - attribute \src "ls180.v:210.5-210.39" + attribute \src "ls180.v:204.5-204.39" wire $1\libresocsim_update_value_re[0:0] - attribute \src "ls180.v:209.5-209.44" + attribute \src "ls180.v:203.5-203.44" wire $1\libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:229.12-229.37" + attribute \src "ls180.v:223.12-223.37" wire width 32 $1\libresocsim_value[31:0] - attribute \src "ls180.v:211.12-211.44" + attribute \src "ls180.v:205.12-205.44" wire width 32 $1\libresocsim_value_status[31:0] - attribute \src "ls180.v:201.11-201.32" + attribute \src "ls180.v:195.11-195.32" wire width 4 $1\libresocsim_we[3:0] - attribute \src "ls180.v:217.5-217.34" + attribute \src "ls180.v:211.5-211.34" wire $1\libresocsim_zero_clear[0:0] - attribute \src "ls180.v:218.5-218.40" + attribute \src "ls180.v:212.5-212.40" wire $1\libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:215.5-215.36" + attribute \src "ls180.v:209.5-209.36" wire $1\libresocsim_zero_pending[0:0] - attribute \src "ls180.v:820.12-820.35" + attribute \src "ls180.v:814.12-814.35" wire width 30 $1\litedram_wb_adr[29:0] - attribute \src "ls180.v:824.5-824.27" + attribute \src "ls180.v:818.5-818.27" wire $1\litedram_wb_cyc[0:0] - attribute \src "ls180.v:821.12-821.37" + attribute \src "ls180.v:815.12-815.37" wire width 16 $1\litedram_wb_dat_w[15:0] - attribute \src "ls180.v:823.11-823.33" + attribute \src "ls180.v:817.11-817.33" wire width 2 $1\litedram_wb_sel[1:0] - attribute \src "ls180.v:825.5-825.27" + attribute \src "ls180.v:819.5-819.27" wire $1\litedram_wb_stb[0:0] - attribute \src "ls180.v:827.5-827.26" + attribute \src "ls180.v:821.5-821.26" wire $1\litedram_wb_we[0:0] - attribute \src "ls180.v:236.5-236.31" + attribute \src "ls180.v:230.5-230.31" wire $1\ram_bus_ram_bus_ack[0:0] - attribute \src "ls180.v:243.11-243.24" + attribute \src "ls180.v:237.11-237.24" wire width 4 $1\ram_we[3:0] - attribute \src "ls180.v:265.11-265.27" + attribute \src "ls180.v:259.11-259.27" wire width 3 $1\rddata_en[2:0] - attribute \src "ls180.v:1444.32-1444.44" + attribute \src "ls180.v:1438.32-1438.44" wire $1\regs0[0:0] - attribute \src "ls180.v:1445.32-1445.44" + attribute \src "ls180.v:1439.32-1439.44" wire $1\regs1[0:0] - attribute \src "ls180.v:1343.5-1343.28" + attribute \src "ls180.v:1337.5-1337.28" wire $1\rhs_array_muxed0[0:0] - attribute \src "ls180.v:1356.5-1356.29" + attribute \src "ls180.v:1350.5-1350.29" wire $1\rhs_array_muxed10[0:0] - attribute \src "ls180.v:1357.5-1357.29" + attribute \src "ls180.v:1351.5-1351.29" wire $1\rhs_array_muxed11[0:0] - attribute \src "ls180.v:1361.12-1361.37" + attribute \src "ls180.v:1355.12-1355.37" wire width 22 $1\rhs_array_muxed12[21:0] - attribute \src "ls180.v:1362.5-1362.29" + attribute \src "ls180.v:1356.5-1356.29" wire $1\rhs_array_muxed13[0:0] - attribute \src "ls180.v:1363.5-1363.29" + attribute \src "ls180.v:1357.5-1357.29" wire $1\rhs_array_muxed14[0:0] - attribute \src "ls180.v:1364.12-1364.37" + attribute \src "ls180.v:1358.12-1358.37" wire width 22 $1\rhs_array_muxed15[21:0] - attribute \src "ls180.v:1365.5-1365.29" + attribute \src "ls180.v:1359.5-1359.29" wire $1\rhs_array_muxed16[0:0] - attribute \src "ls180.v:1366.5-1366.29" + attribute \src "ls180.v:1360.5-1360.29" wire $1\rhs_array_muxed17[0:0] - attribute \src "ls180.v:1367.12-1367.37" + attribute \src "ls180.v:1361.12-1361.37" wire width 22 $1\rhs_array_muxed18[21:0] - attribute \src "ls180.v:1368.5-1368.29" + attribute \src "ls180.v:1362.5-1362.29" wire $1\rhs_array_muxed19[0:0] - attribute \src "ls180.v:1344.12-1344.36" + attribute \src "ls180.v:1338.12-1338.36" wire width 13 $1\rhs_array_muxed1[12:0] - attribute \src "ls180.v:1369.5-1369.29" + attribute \src "ls180.v:1363.5-1363.29" wire $1\rhs_array_muxed20[0:0] - attribute \src "ls180.v:1370.12-1370.37" + attribute \src "ls180.v:1364.12-1364.37" wire width 22 $1\rhs_array_muxed21[21:0] - attribute \src "ls180.v:1371.5-1371.29" + attribute \src "ls180.v:1365.5-1365.29" wire $1\rhs_array_muxed22[0:0] - attribute \src "ls180.v:1372.5-1372.29" + attribute \src "ls180.v:1366.5-1366.29" wire $1\rhs_array_muxed23[0:0] - attribute \src "ls180.v:1373.12-1373.37" + attribute \src "ls180.v:1367.12-1367.37" wire width 30 $1\rhs_array_muxed24[29:0] - attribute \src "ls180.v:1374.12-1374.37" + attribute \src "ls180.v:1368.12-1368.37" wire width 32 $1\rhs_array_muxed25[31:0] - attribute \src "ls180.v:1375.11-1375.35" + attribute \src "ls180.v:1369.11-1369.35" wire width 4 $1\rhs_array_muxed26[3:0] - attribute \src "ls180.v:1376.5-1376.29" + attribute \src "ls180.v:1370.5-1370.29" wire $1\rhs_array_muxed27[0:0] - attribute \src "ls180.v:1377.5-1377.29" + attribute \src "ls180.v:1371.5-1371.29" wire $1\rhs_array_muxed28[0:0] - attribute \src "ls180.v:1378.5-1378.29" + attribute \src "ls180.v:1372.5-1372.29" wire $1\rhs_array_muxed29[0:0] - attribute \src "ls180.v:1345.11-1345.34" + attribute \src "ls180.v:1339.11-1339.34" wire width 2 $1\rhs_array_muxed2[1:0] - attribute \src "ls180.v:1379.11-1379.35" + attribute \src "ls180.v:1373.11-1373.35" wire width 3 $1\rhs_array_muxed30[2:0] - attribute \src "ls180.v:1380.11-1380.35" + attribute \src "ls180.v:1374.11-1374.35" wire width 2 $1\rhs_array_muxed31[1:0] - attribute \src "ls180.v:1346.5-1346.28" + attribute \src "ls180.v:1340.5-1340.28" wire $1\rhs_array_muxed3[0:0] - attribute \src "ls180.v:1347.5-1347.28" + attribute \src "ls180.v:1341.5-1341.28" wire $1\rhs_array_muxed4[0:0] - attribute \src "ls180.v:1348.5-1348.28" + attribute \src "ls180.v:1342.5-1342.28" wire $1\rhs_array_muxed5[0:0] - attribute \src "ls180.v:1352.5-1352.28" + attribute \src "ls180.v:1346.5-1346.28" wire $1\rhs_array_muxed6[0:0] - attribute \src "ls180.v:1353.12-1353.36" + attribute \src "ls180.v:1347.12-1347.36" wire width 13 $1\rhs_array_muxed7[12:0] - attribute \src "ls180.v:1354.11-1354.34" + attribute \src "ls180.v:1348.11-1348.34" wire width 2 $1\rhs_array_muxed8[1:0] - attribute \src "ls180.v:1355.5-1355.28" + attribute \src "ls180.v:1349.5-1349.28" wire $1\rhs_array_muxed9[0:0] - attribute \src "ls180.v:878.5-878.20" + attribute \src "ls180.v:872.5-872.20" wire $1\rx_clear[0:0] - attribute \src "ls180.v:962.11-962.33" + attribute \src "ls180.v:956.11-956.33" wire width 4 $1\rx_fifo_consume[3:0] - attribute \src "ls180.v:959.11-959.32" + attribute \src "ls180.v:953.11-953.32" wire width 5 $1\rx_fifo_level0[4:0] - attribute \src "ls180.v:961.11-961.33" + attribute \src "ls180.v:955.11-955.33" wire width 4 $1\rx_fifo_produce[3:0] - attribute \src "ls180.v:952.5-952.28" + attribute \src "ls180.v:946.5-946.28" wire $1\rx_fifo_readable[0:0] - attribute \src "ls180.v:963.11-963.36" + attribute \src "ls180.v:957.11-957.36" wire width 4 $1\rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:879.5-879.26" + attribute \src "ls180.v:873.5-873.26" wire $1\rx_old_trigger[0:0] - attribute \src "ls180.v:876.5-876.22" + attribute \src "ls180.v:870.5-870.22" wire $1\rx_pending[0:0] - attribute \src "ls180.v:327.5-327.28" + attribute \src "ls180.v:321.5-321.28" wire $1\sdram_address_re[0:0] - attribute \src "ls180.v:326.12-326.41" + attribute \src "ls180.v:320.12-320.41" wire width 13 $1\sdram_address_storage[12:0] - attribute \src "ls180.v:329.5-329.29" + attribute \src "ls180.v:323.5-323.29" wire $1\sdram_baddress_re[0:0] - attribute \src "ls180.v:328.11-328.40" + attribute \src "ls180.v:322.11-322.40" wire width 2 $1\sdram_baddress_storage[1:0] - attribute \src "ls180.v:425.5-425.45" + attribute \src "ls180.v:419.5-419.45" wire $1\sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:447.11-447.65" + attribute \src "ls180.v:441.11-441.65" wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:444.11-444.63" + attribute \src "ls180.v:438.11-438.63" wire width 4 $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:446.11-446.65" + attribute \src "ls180.v:440.11-440.65" wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:448.11-448.68" + attribute \src "ls180.v:442.11-442.68" wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:471.5-471.54" + attribute \src "ls180.v:465.5-465.54" wire $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:472.5-472.53" + attribute \src "ls180.v:466.5-466.53" wire $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:474.12-474.69" + attribute \src "ls180.v:468.12-468.69" wire width 22 $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:473.5-473.59" + attribute \src "ls180.v:467.5-467.59" wire $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:469.5-469.54" + attribute \src "ls180.v:463.5-463.54" wire $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:417.12-417.52" + attribute \src "ls180.v:411.12-411.52" wire width 13 $1\sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:419.5-419.46" + attribute \src "ls180.v:413.5-413.46" wire $1\sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:422.5-422.49" + attribute \src "ls180.v:416.5-416.49" wire $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:423.5-423.50" + attribute \src "ls180.v:417.5-417.50" wire $1\sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:424.5-424.51" + attribute \src "ls180.v:418.5-418.51" wire $1\sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:420.5-420.46" + attribute \src "ls180.v:414.5-414.46" wire $1\sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:421.5-421.45" + attribute \src "ls180.v:415.5-415.45" wire $1\sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:416.5-416.40" + attribute \src "ls180.v:410.5-410.40" wire $1\sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:415.5-415.40" + attribute \src "ls180.v:409.5-409.40" wire $1\sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:414.5-414.42" + attribute \src "ls180.v:408.5-408.42" wire $1\sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:412.5-412.46" + attribute \src "ls180.v:406.5-406.46" wire $1\sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:411.5-411.46" + attribute \src "ls180.v:405.5-405.46" wire $1\sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:475.12-475.42" + attribute \src "ls180.v:469.12-469.42" wire width 13 $1\sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:479.5-479.40" + attribute \src "ls180.v:473.5-473.40" wire $1\sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:480.5-480.49" + attribute \src "ls180.v:474.5-474.49" wire $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:478.5-478.39" + attribute \src "ls180.v:472.5-472.39" wire $1\sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:476.5-476.41" + attribute \src "ls180.v:470.5-470.41" wire $1\sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:483.11-483.50" + attribute \src "ls180.v:477.11-477.50" wire width 3 $1\sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:482.32-482.71" + attribute \src "ls180.v:476.32-476.71" wire $1\sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:507.5-507.45" + attribute \src "ls180.v:501.5-501.45" wire $1\sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:529.11-529.65" + attribute \src "ls180.v:523.11-523.65" wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:526.11-526.63" + attribute \src "ls180.v:520.11-520.63" wire width 4 $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:528.11-528.65" + attribute \src "ls180.v:522.11-522.65" wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:530.11-530.68" + attribute \src "ls180.v:524.11-524.68" wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:553.5-553.54" + attribute \src "ls180.v:547.5-547.54" wire $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:554.5-554.53" + attribute \src "ls180.v:548.5-548.53" wire $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:556.12-556.69" + attribute \src "ls180.v:550.12-550.69" wire width 22 $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:555.5-555.59" + attribute \src "ls180.v:549.5-549.59" wire $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:551.5-551.54" + attribute \src "ls180.v:545.5-545.54" wire $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:499.12-499.52" + attribute \src "ls180.v:493.12-493.52" wire width 13 $1\sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:501.5-501.46" + attribute \src "ls180.v:495.5-495.46" wire $1\sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:504.5-504.49" + attribute \src "ls180.v:498.5-498.49" wire $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:505.5-505.50" + attribute \src "ls180.v:499.5-499.50" wire $1\sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:506.5-506.51" + attribute \src "ls180.v:500.5-500.51" wire $1\sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:502.5-502.46" + attribute \src "ls180.v:496.5-496.46" wire $1\sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:503.5-503.45" + attribute \src "ls180.v:497.5-497.45" wire $1\sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:498.5-498.40" + attribute \src "ls180.v:492.5-492.40" wire $1\sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:497.5-497.40" + attribute \src "ls180.v:491.5-491.40" wire $1\sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:496.5-496.42" + attribute \src "ls180.v:490.5-490.42" wire $1\sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:494.5-494.46" + attribute \src "ls180.v:488.5-488.46" wire $1\sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:493.5-493.46" + attribute \src "ls180.v:487.5-487.46" wire $1\sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:557.12-557.42" + attribute \src "ls180.v:551.12-551.42" wire width 13 $1\sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:561.5-561.40" + attribute \src "ls180.v:555.5-555.40" wire $1\sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:562.5-562.49" + attribute \src "ls180.v:556.5-556.49" wire $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:560.5-560.39" + attribute \src "ls180.v:554.5-554.39" wire $1\sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:558.5-558.41" + attribute \src "ls180.v:552.5-552.41" wire $1\sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:565.11-565.50" + attribute \src "ls180.v:559.11-559.50" wire width 3 $1\sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:564.32-564.71" + attribute \src "ls180.v:558.32-558.71" wire $1\sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:589.5-589.45" + attribute \src "ls180.v:583.5-583.45" wire $1\sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:611.11-611.65" + attribute \src "ls180.v:605.11-605.65" wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:608.11-608.63" + attribute \src "ls180.v:602.11-602.63" wire width 4 $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:610.11-610.65" + attribute \src "ls180.v:604.11-604.65" wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:612.11-612.68" + attribute \src "ls180.v:606.11-606.68" wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:635.5-635.54" + attribute \src "ls180.v:629.5-629.54" wire $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:636.5-636.53" + attribute \src "ls180.v:630.5-630.53" wire $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:638.12-638.69" + attribute \src "ls180.v:632.12-632.69" wire width 22 $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:637.5-637.59" + attribute \src "ls180.v:631.5-631.59" wire $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:633.5-633.54" + attribute \src "ls180.v:627.5-627.54" wire $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:581.12-581.52" + attribute \src "ls180.v:575.12-575.52" wire width 13 $1\sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:583.5-583.46" + attribute \src "ls180.v:577.5-577.46" wire $1\sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:586.5-586.49" + attribute \src "ls180.v:580.5-580.49" wire $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:587.5-587.50" + attribute \src "ls180.v:581.5-581.50" wire $1\sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:588.5-588.51" + attribute \src "ls180.v:582.5-582.51" wire $1\sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:584.5-584.46" + attribute \src "ls180.v:578.5-578.46" wire $1\sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:585.5-585.45" + attribute \src "ls180.v:579.5-579.45" wire $1\sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:580.5-580.40" + attribute \src "ls180.v:574.5-574.40" wire $1\sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:579.5-579.40" + attribute \src "ls180.v:573.5-573.40" wire $1\sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:578.5-578.42" + attribute \src "ls180.v:572.5-572.42" wire $1\sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:576.5-576.46" + attribute \src "ls180.v:570.5-570.46" wire $1\sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:575.5-575.46" + attribute \src "ls180.v:569.5-569.46" wire $1\sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:639.12-639.42" + attribute \src "ls180.v:633.12-633.42" wire width 13 $1\sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:643.5-643.40" + attribute \src "ls180.v:637.5-637.40" wire $1\sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:644.5-644.49" + attribute \src "ls180.v:638.5-638.49" wire $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:642.5-642.39" + attribute \src "ls180.v:636.5-636.39" wire $1\sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:640.5-640.41" + attribute \src "ls180.v:634.5-634.41" wire $1\sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:647.11-647.50" + attribute \src "ls180.v:641.11-641.50" wire width 3 $1\sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:646.32-646.71" + attribute \src "ls180.v:640.32-640.71" wire $1\sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:671.5-671.45" + attribute \src "ls180.v:665.5-665.45" wire $1\sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:693.11-693.65" + attribute \src "ls180.v:687.11-687.65" wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:690.11-690.63" + attribute \src "ls180.v:684.11-684.63" wire width 4 $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:692.11-692.65" + attribute \src "ls180.v:686.11-686.65" wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:694.11-694.68" + attribute \src "ls180.v:688.11-688.68" wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:717.5-717.54" + attribute \src "ls180.v:711.5-711.54" wire $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:718.5-718.53" + attribute \src "ls180.v:712.5-712.53" wire $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:720.12-720.69" + attribute \src "ls180.v:714.12-714.69" wire width 22 $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:719.5-719.59" + attribute \src "ls180.v:713.5-713.59" wire $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:715.5-715.54" + attribute \src "ls180.v:709.5-709.54" wire $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:663.12-663.52" + attribute \src "ls180.v:657.12-657.52" wire width 13 $1\sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:665.5-665.46" + attribute \src "ls180.v:659.5-659.46" wire $1\sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:668.5-668.49" + attribute \src "ls180.v:662.5-662.49" wire $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:669.5-669.50" + attribute \src "ls180.v:663.5-663.50" wire $1\sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:670.5-670.51" + attribute \src "ls180.v:664.5-664.51" wire $1\sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:666.5-666.46" + attribute \src "ls180.v:660.5-660.46" wire $1\sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:667.5-667.45" + attribute \src "ls180.v:661.5-661.45" wire $1\sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:662.5-662.40" + attribute \src "ls180.v:656.5-656.40" wire $1\sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:661.5-661.40" + attribute \src "ls180.v:655.5-655.40" wire $1\sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:660.5-660.42" + attribute \src "ls180.v:654.5-654.42" wire $1\sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:658.5-658.46" + attribute \src "ls180.v:652.5-652.46" wire $1\sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:657.5-657.46" + attribute \src "ls180.v:651.5-651.46" wire $1\sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:721.12-721.42" + attribute \src "ls180.v:715.12-715.42" wire width 13 $1\sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:725.5-725.40" + attribute \src "ls180.v:719.5-719.40" wire $1\sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:726.5-726.49" + attribute \src "ls180.v:720.5-720.49" wire $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:724.5-724.39" + attribute \src "ls180.v:718.5-718.39" wire $1\sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:722.5-722.41" + attribute \src "ls180.v:716.5-716.41" wire $1\sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:729.11-729.50" + attribute \src "ls180.v:723.11-723.50" wire width 3 $1\sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:728.32-728.71" + attribute \src "ls180.v:722.32-722.71" wire $1\sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:744.5-744.44" + attribute \src "ls180.v:738.5-738.44" wire $1\sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:745.5-745.44" + attribute \src "ls180.v:739.5-739.44" wire $1\sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:746.5-746.43" + attribute \src "ls180.v:740.5-740.43" wire $1\sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:752.11-752.40" + attribute \src "ls180.v:746.11-746.40" wire width 2 $1\sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:750.11-750.41" + attribute \src "ls180.v:744.11-744.41" wire width 4 $1\sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:762.5-762.44" + attribute \src "ls180.v:756.5-756.44" wire $1\sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:763.5-763.44" + attribute \src "ls180.v:757.5-757.44" wire $1\sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:764.5-764.43" + attribute \src "ls180.v:758.5-758.43" wire $1\sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:759.5-759.38" + attribute \src "ls180.v:753.5-753.38" wire $1\sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:770.11-770.40" + attribute \src "ls180.v:764.11-764.40" wire width 2 $1\sdram_choose_req_grant[1:0] - attribute \src "ls180.v:768.11-768.41" + attribute \src "ls180.v:762.11-762.41" wire width 4 $1\sdram_choose_req_valids[3:0] - attribute \src "ls180.v:757.5-757.43" + attribute \src "ls180.v:751.5-751.43" wire $1\sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:754.5-754.39" + attribute \src "ls180.v:748.5-748.39" wire $1\sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:755.5-755.40" + attribute \src "ls180.v:749.5-749.40" wire $1\sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:383.5-383.26" + attribute \src "ls180.v:377.5-377.26" wire $1\sdram_cmd_last[0:0] - attribute \src "ls180.v:384.12-384.39" + attribute \src "ls180.v:378.12-378.39" wire width 13 $1\sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:385.11-385.38" + attribute \src "ls180.v:379.11-379.38" wire width 2 $1\sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:386.5-386.33" + attribute \src "ls180.v:380.5-380.33" wire $1\sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:387.5-387.33" + attribute \src "ls180.v:381.5-381.33" wire $1\sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:388.5-388.32" + attribute \src "ls180.v:382.5-382.32" wire $1\sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:382.5-382.27" + attribute \src "ls180.v:376.5-376.27" wire $1\sdram_cmd_ready[0:0] - attribute \src "ls180.v:381.5-381.27" + attribute \src "ls180.v:375.5-375.27" wire $1\sdram_cmd_valid[0:0] - attribute \src "ls180.v:321.5-321.28" + attribute \src "ls180.v:315.5-315.28" wire $1\sdram_command_re[0:0] - attribute \src "ls180.v:320.11-320.39" + attribute \src "ls180.v:314.11-314.39" wire width 6 $1\sdram_command_storage[5:0] - attribute \src "ls180.v:365.12-365.40" + attribute \src "ls180.v:359.12-359.40" wire width 13 $1\sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:366.11-366.35" + attribute \src "ls180.v:360.11-360.35" wire width 2 $1\sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:367.5-367.30" + attribute \src "ls180.v:361.5-361.30" wire $1\sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:368.5-368.29" + attribute \src "ls180.v:362.5-362.29" wire $1\sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:369.5-369.30" + attribute \src "ls180.v:363.5-363.30" wire $1\sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:378.5-378.34" + attribute \src "ls180.v:372.5-372.34" wire $1\sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:370.5-370.29" + attribute \src "ls180.v:364.5-364.29" wire $1\sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:376.5-376.34" + attribute \src "ls180.v:370.5-370.34" wire $1\sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:789.5-789.21" + attribute \src "ls180.v:783.5-783.21" wire $1\sdram_en0[0:0] - attribute \src "ls180.v:792.5-792.21" + attribute \src "ls180.v:786.5-786.21" wire $1\sdram_en1[0:0] - attribute \src "ls180.v:362.12-362.41" + attribute \src "ls180.v:356.12-356.41" wire width 16 $1\sdram_interface_wdata[15:0] - attribute \src "ls180.v:363.11-363.42" + attribute \src "ls180.v:357.11-357.42" wire width 2 $1\sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:268.5-268.31" + attribute \src "ls180.v:262.5-262.31" wire $1\sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:269.5-269.30" + attribute \src "ls180.v:263.5-263.30" wire $1\sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:270.5-270.31" + attribute \src "ls180.v:264.5-264.31" wire $1\sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:280.12-280.40" + attribute \src "ls180.v:274.12-274.40" wire width 16 $1\sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:281.5-281.38" + attribute \src "ls180.v:275.5-275.38" wire $1\sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:271.5-271.30" + attribute \src "ls180.v:265.5-265.30" wire $1\sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:307.5-307.33" + attribute \src "ls180.v:301.5-301.33" wire $1\sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:298.12-298.43" + attribute \src "ls180.v:292.12-292.43" wire width 13 $1\sdram_master_p0_address[12:0] - attribute \src "ls180.v:299.11-299.38" + attribute \src "ls180.v:293.11-293.38" wire width 2 $1\sdram_master_p0_bank[1:0] - attribute \src "ls180.v:300.5-300.33" + attribute \src "ls180.v:294.5-294.33" wire $1\sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:304.5-304.31" + attribute \src "ls180.v:298.5-298.31" wire $1\sdram_master_p0_cke[0:0] - attribute \src "ls180.v:301.5-301.32" + attribute \src "ls180.v:295.5-295.32" wire $1\sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:305.5-305.31" + attribute \src "ls180.v:299.5-299.31" wire $1\sdram_master_p0_odt[0:0] - attribute \src "ls180.v:302.5-302.33" + attribute \src "ls180.v:296.5-296.33" wire $1\sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:311.5-311.37" + attribute \src "ls180.v:305.5-305.37" wire $1\sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:306.5-306.35" + attribute \src "ls180.v:300.5-300.35" wire $1\sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:303.5-303.32" + attribute \src "ls180.v:297.5-297.32" wire $1\sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:308.12-308.42" + attribute \src "ls180.v:302.12-302.42" wire width 16 $1\sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:309.5-309.37" + attribute \src "ls180.v:303.5-303.37" wire $1\sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:310.11-310.45" + attribute \src "ls180.v:304.11-304.45" wire width 2 $1\sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:399.5-399.33" + attribute \src "ls180.v:393.5-393.33" wire $1\sdram_postponer_count[0:0] - attribute \src "ls180.v:398.5-398.33" + attribute \src "ls180.v:392.5-392.33" wire $1\sdram_postponer_req_o[0:0] - attribute \src "ls180.v:319.5-319.20" + attribute \src "ls180.v:313.5-313.20" wire $1\sdram_re[0:0] - attribute \src "ls180.v:405.5-405.33" + attribute \src "ls180.v:399.5-399.33" wire $1\sdram_sequencer_count[0:0] - attribute \src "ls180.v:404.11-404.41" + attribute \src "ls180.v:398.11-398.41" wire width 4 $1\sdram_sequencer_counter[3:0] - attribute \src "ls180.v:403.5-403.33" + attribute \src "ls180.v:397.5-397.33" wire $1\sdram_sequencer_done1[0:0] - attribute \src "ls180.v:400.5-400.34" + attribute \src "ls180.v:394.5-394.34" wire $1\sdram_sequencer_start0[0:0] - attribute \src "ls180.v:296.12-296.41" + attribute \src "ls180.v:290.12-290.41" wire width 16 $1\sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:297.5-297.39" + attribute \src "ls180.v:291.5-291.39" wire $1\sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:332.12-332.32" + attribute \src "ls180.v:326.12-326.32" wire width 16 $1\sdram_status[15:0] - attribute \src "ls180.v:774.11-774.35" + attribute \src "ls180.v:768.11-768.35" wire width 2 $1\sdram_steerer_sel[1:0] - attribute \src "ls180.v:318.11-318.31" + attribute \src "ls180.v:312.11-312.31" wire width 4 $1\sdram_storage[3:0] - attribute \src "ls180.v:783.5-783.31" + attribute \src "ls180.v:777.5-777.31" wire $1\sdram_tccdcon_count[0:0] - attribute \src "ls180.v:782.32-782.58" + attribute \src "ls180.v:776.32-776.58" wire $1\sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:791.11-791.29" + attribute \src "ls180.v:785.11-785.29" wire width 5 $1\sdram_time0[4:0] - attribute \src "ls180.v:794.11-794.29" + attribute \src "ls180.v:788.11-788.29" wire width 4 $1\sdram_time1[3:0] - attribute \src "ls180.v:396.11-396.39" + attribute \src "ls180.v:390.11-390.39" wire width 10 $1\sdram_timer_count1[9:0] - attribute \src "ls180.v:786.11-786.37" + attribute \src "ls180.v:780.11-780.37" wire width 3 $1\sdram_twtrcon_count[2:0] - attribute \src "ls180.v:785.32-785.58" + attribute \src "ls180.v:779.32-779.58" wire $1\sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:331.5-331.27" + attribute \src "ls180.v:325.5-325.27" wire $1\sdram_wrdata_re[0:0] - attribute \src "ls180.v:330.12-330.40" + attribute \src "ls180.v:324.12-324.40" wire width 16 $1\sdram_wrdata_storage[15:0] - attribute \src "ls180.v:1023.11-1023.54" + attribute \src "ls180.v:1017.11-1017.54" wire width 3 $1\subfragments_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1022.11-1022.49" + attribute \src "ls180.v:1016.11-1016.49" wire width 3 $1\subfragments_bankmachine0_state[2:0] - attribute \src "ls180.v:1025.11-1025.54" + attribute \src "ls180.v:1019.11-1019.54" wire width 3 $1\subfragments_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1024.11-1024.49" + attribute \src "ls180.v:1018.11-1018.49" wire width 3 $1\subfragments_bankmachine1_state[2:0] - attribute \src "ls180.v:1027.11-1027.54" + attribute \src "ls180.v:1021.11-1021.54" wire width 3 $1\subfragments_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1026.11-1026.49" + attribute \src "ls180.v:1020.11-1020.49" wire width 3 $1\subfragments_bankmachine2_state[2:0] - attribute \src "ls180.v:1029.11-1029.54" + attribute \src "ls180.v:1023.11-1023.54" wire width 3 $1\subfragments_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1028.11-1028.49" + attribute \src "ls180.v:1022.11-1022.49" wire width 3 $1\subfragments_bankmachine3_state[2:0] - attribute \src "ls180.v:1009.5-1009.46" + attribute \src "ls180.v:1003.5-1003.46" wire $1\subfragments_converter0_next_state[0:0] - attribute \src "ls180.v:1008.5-1008.41" + attribute \src "ls180.v:1002.5-1002.41" wire $1\subfragments_converter0_state[0:0] - attribute \src "ls180.v:1013.5-1013.46" + attribute \src "ls180.v:1007.5-1007.46" wire $1\subfragments_converter1_next_state[0:0] - attribute \src "ls180.v:1012.5-1012.41" + attribute \src "ls180.v:1006.5-1006.41" wire $1\subfragments_converter1_state[0:0] - attribute \src "ls180.v:1017.5-1017.46" + attribute \src "ls180.v:1011.5-1011.46" wire $1\subfragments_converter2_next_state[0:0] - attribute \src "ls180.v:1016.5-1016.41" + attribute \src "ls180.v:1010.5-1010.41" wire $1\subfragments_converter2_state[0:0] - attribute \src "ls180.v:1031.11-1031.53" + attribute \src "ls180.v:1025.11-1025.53" wire width 3 $1\subfragments_multiplexer_next_state[2:0] - attribute \src "ls180.v:1030.11-1030.48" + attribute \src "ls180.v:1024.11-1024.48" wire width 3 $1\subfragments_multiplexer_state[2:0] - attribute \src "ls180.v:1049.5-1049.48" + attribute \src "ls180.v:1043.5-1043.48" wire $1\subfragments_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1050.5-1050.48" + attribute \src "ls180.v:1044.5-1044.48" wire $1\subfragments_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1051.5-1051.48" + attribute \src "ls180.v:1045.5-1045.48" wire $1\subfragments_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1052.5-1052.48" + attribute \src "ls180.v:1046.5-1046.48" wire $1\subfragments_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1048.5-1048.47" + attribute \src "ls180.v:1042.5-1042.47" wire $1\subfragments_new_master_wdata_ready[0:0] - attribute \src "ls180.v:1054.5-1054.35" + attribute \src "ls180.v:1048.5-1048.35" wire $1\subfragments_next_state[0:0] - attribute \src "ls180.v:1021.11-1021.51" + attribute \src "ls180.v:1015.11-1015.51" wire width 2 $1\subfragments_refresher_next_state[1:0] - attribute \src "ls180.v:1020.11-1020.46" + attribute \src "ls180.v:1014.11-1014.46" wire width 2 $1\subfragments_refresher_state[1:0] - attribute \src "ls180.v:1053.5-1053.30" + attribute \src "ls180.v:1047.5-1047.30" wire $1\subfragments_state[0:0] - attribute \src "ls180.v:1349.5-1349.26" + attribute \src "ls180.v:1343.5-1343.26" wire $1\t_array_muxed0[0:0] - attribute \src "ls180.v:1350.5-1350.26" + attribute \src "ls180.v:1344.5-1344.26" wire $1\t_array_muxed1[0:0] - attribute \src "ls180.v:1351.5-1351.26" + attribute \src "ls180.v:1345.5-1345.26" wire $1\t_array_muxed2[0:0] - attribute \src "ls180.v:1358.5-1358.26" + attribute \src "ls180.v:1352.5-1352.26" wire $1\t_array_muxed3[0:0] - attribute \src "ls180.v:1359.5-1359.26" + attribute \src "ls180.v:1353.5-1353.26" wire $1\t_array_muxed4[0:0] - attribute \src "ls180.v:1360.5-1360.26" + attribute \src "ls180.v:1354.5-1354.26" wire $1\t_array_muxed5[0:0] - attribute \src "ls180.v:873.5-873.20" + attribute \src "ls180.v:867.5-867.20" wire $1\tx_clear[0:0] - attribute \src "ls180.v:925.11-925.33" + attribute \src "ls180.v:919.11-919.33" wire width 4 $1\tx_fifo_consume[3:0] - attribute \src "ls180.v:922.11-922.32" + attribute \src "ls180.v:916.11-916.32" wire width 5 $1\tx_fifo_level0[4:0] - attribute \src "ls180.v:924.11-924.33" + attribute \src "ls180.v:918.11-918.33" wire width 4 $1\tx_fifo_produce[3:0] - attribute \src "ls180.v:915.5-915.28" + attribute \src "ls180.v:909.5-909.28" wire $1\tx_fifo_readable[0:0] - attribute \src "ls180.v:926.11-926.36" + attribute \src "ls180.v:920.11-920.36" wire width 4 $1\tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:874.5-874.26" + attribute \src "ls180.v:868.5-868.26" wire $1\tx_old_trigger[0:0] - attribute \src "ls180.v:871.5-871.22" + attribute \src "ls180.v:865.5-865.22" wire $1\tx_pending[0:0] - attribute \src "ls180.v:855.12-855.49" + attribute \src "ls180.v:849.12-849.49" wire width 32 $1\uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:845.12-845.49" + attribute \src "ls180.v:839.12-839.49" wire width 32 $1\uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:838.5-838.23" + attribute \src "ls180.v:832.5-832.23" wire $1\uart_phy_re[0:0] - attribute \src "ls180.v:859.11-859.38" + attribute \src "ls180.v:853.11-853.38" wire width 4 $1\uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:860.5-860.28" + attribute \src "ls180.v:854.5-854.28" wire $1\uart_phy_rx_busy[0:0] - attribute \src "ls180.v:857.5-857.25" + attribute \src "ls180.v:851.5-851.25" wire $1\uart_phy_rx_r[0:0] - attribute \src "ls180.v:858.11-858.33" + attribute \src "ls180.v:852.11-852.33" wire width 8 $1\uart_phy_rx_reg[7:0] - attribute \src "ls180.v:840.5-840.31" + attribute \src "ls180.v:834.5-834.31" wire $1\uart_phy_sink_ready[0:0] - attribute \src "ls180.v:853.11-853.46" + attribute \src "ls180.v:847.11-847.46" wire width 8 $1\uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:849.5-849.33" + attribute \src "ls180.v:843.5-843.33" wire $1\uart_phy_source_valid[0:0] - attribute \src "ls180.v:837.12-837.42" + attribute \src "ls180.v:831.12-831.42" wire width 32 $1\uart_phy_storage[31:0] - attribute \src "ls180.v:847.11-847.38" + attribute \src "ls180.v:841.11-841.38" wire width 4 $1\uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:848.5-848.28" + attribute \src "ls180.v:842.5-842.28" wire $1\uart_phy_tx_busy[0:0] - attribute \src "ls180.v:846.11-846.33" + attribute \src "ls180.v:840.11-840.33" wire width 8 $1\uart_phy_tx_reg[7:0] - attribute \src "ls180.v:854.5-854.34" + attribute \src "ls180.v:848.5-848.34" wire $1\uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:844.5-844.34" + attribute \src "ls180.v:838.5-838.34" wire $1\uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:815.5-815.24" + attribute \src "ls180.v:809.5-809.24" wire $1\wb_sdram_ack[0:0] - attribute \src "ls180.v:833.5-833.26" + attribute \src "ls180.v:827.5-827.26" wire $1\wdata_consumed[0:0] - attribute \src "ls180.v:1561.76-1561.113" - wire $add$ls180.v:1561$25_Y - attribute \src "ls180.v:1621.76-1621.113" - wire $add$ls180.v:1621$36_Y - attribute \src "ls180.v:1681.76-1681.113" - wire $add$ls180.v:1681$47_Y - attribute \src "ls180.v:2824.52-2824.76" - wire $add$ls180.v:2824$553_Y - attribute \src "ls180.v:2924.26-2924.59" - wire width 5 $add$ls180.v:2924$599_Y - attribute \src "ls180.v:2954.26-2954.59" - wire width 5 $add$ls180.v:2954$610_Y - attribute \src "ls180.v:4357.31-4357.60" - wire width 32 $add$ls180.v:4357$1256_Y - attribute \src "ls180.v:4446.32-4446.62" - wire width 4 $add$ls180.v:4446$1280_Y - attribute \src "ls180.v:4463.55-4463.109" - wire width 3 $add$ls180.v:4463$1284_Y - attribute \src "ls180.v:4466.55-4466.109" - wire width 3 $add$ls180.v:4466$1285_Y - attribute \src "ls180.v:4470.54-4470.106" - wire width 4 $add$ls180.v:4470$1290_Y - attribute \src "ls180.v:4509.55-4509.109" - wire width 3 $add$ls180.v:4509$1300_Y - attribute \src "ls180.v:4512.55-4512.109" - wire width 3 $add$ls180.v:4512$1301_Y - attribute \src "ls180.v:4516.54-4516.106" - wire width 4 $add$ls180.v:4516$1306_Y - attribute \src "ls180.v:4555.55-4555.109" - wire width 3 $add$ls180.v:4555$1316_Y - attribute \src "ls180.v:4558.55-4558.109" - wire width 3 $add$ls180.v:4558$1317_Y - attribute \src "ls180.v:4562.54-4562.106" - wire width 4 $add$ls180.v:4562$1322_Y - attribute \src "ls180.v:4601.55-4601.109" - wire width 3 $add$ls180.v:4601$1332_Y - attribute \src "ls180.v:4604.55-4604.109" - wire width 3 $add$ls180.v:4604$1333_Y - attribute \src "ls180.v:4608.54-4608.106" - wire width 4 $add$ls180.v:4608$1338_Y - attribute \src "ls180.v:4838.29-4838.56" - wire width 4 $add$ls180.v:4838$1392_Y - attribute \src "ls180.v:4854.63-4854.111" - wire width 33 $add$ls180.v:4854$1395_Y - attribute \src "ls180.v:4867.29-4867.56" - wire width 4 $add$ls180.v:4867$1399_Y - attribute \src "ls180.v:4886.63-4886.111" - wire width 33 $add$ls180.v:4886$1402_Y - attribute \src "ls180.v:4912.23-4912.45" - wire width 4 $add$ls180.v:4912$1410_Y - attribute \src "ls180.v:4915.23-4915.45" - wire width 4 $add$ls180.v:4915$1411_Y - attribute \src "ls180.v:4919.23-4919.44" - wire width 5 $add$ls180.v:4919$1416_Y - attribute \src "ls180.v:4934.23-4934.45" - wire width 4 $add$ls180.v:4934$1421_Y - attribute \src "ls180.v:4937.23-4937.45" - wire width 4 $add$ls180.v:4937$1422_Y - attribute \src "ls180.v:4941.23-4941.44" - wire width 5 $add$ls180.v:4941$1427_Y - attribute \src "ls180.v:1555.9-1555.70" - wire $and$ls180.v:1555$20_Y - attribute \src "ls180.v:1573.9-1573.70" - wire $and$ls180.v:1573$27_Y - attribute \src "ls180.v:1615.9-1615.70" - wire $and$ls180.v:1615$31_Y - attribute \src "ls180.v:1633.9-1633.70" - wire $and$ls180.v:1633$38_Y - attribute \src "ls180.v:1675.9-1675.76" - wire $and$ls180.v:1675$42_Y - attribute \src "ls180.v:1693.9-1693.76" - wire $and$ls180.v:1693$49_Y - attribute \src "ls180.v:1703.26-1703.75" - wire $and$ls180.v:1703$51_Y - attribute \src "ls180.v:1703.25-1703.101" - wire $and$ls180.v:1703$52_Y - attribute \src "ls180.v:1703.24-1703.131" - wire $and$ls180.v:1703$53_Y - attribute \src "ls180.v:1704.26-1704.75" - wire $and$ls180.v:1704$54_Y - attribute \src "ls180.v:1704.25-1704.101" - wire $and$ls180.v:1704$55_Y - attribute \src "ls180.v:1704.24-1704.131" - wire $and$ls180.v:1704$56_Y - attribute \src "ls180.v:1705.26-1705.75" - wire $and$ls180.v:1705$57_Y - attribute \src "ls180.v:1705.25-1705.101" - wire $and$ls180.v:1705$58_Y - attribute \src "ls180.v:1705.24-1705.131" - wire $and$ls180.v:1705$59_Y - attribute \src "ls180.v:1706.26-1706.75" - wire $and$ls180.v:1706$60_Y - attribute \src "ls180.v:1706.25-1706.101" - wire $and$ls180.v:1706$61_Y - attribute \src "ls180.v:1706.24-1706.131" - wire $and$ls180.v:1706$62_Y - attribute \src "ls180.v:1715.7-1715.79" - wire $and$ls180.v:1715$65_Y - attribute \src "ls180.v:1720.27-1720.96" - wire $and$ls180.v:1720$66_Y - attribute \src "ls180.v:1724.18-1724.59" - wire $and$ls180.v:1724$68_Y - attribute \src "ls180.v:1724.17-1724.81" - wire $and$ls180.v:1724$69_Y - attribute \src "ls180.v:1724.16-1724.107" - wire $and$ls180.v:1724$70_Y - attribute \src "ls180.v:1725.18-1725.59" - wire $and$ls180.v:1725$71_Y - attribute \src "ls180.v:1725.17-1725.81" - wire $and$ls180.v:1725$72_Y - attribute \src "ls180.v:1725.16-1725.107" - wire $and$ls180.v:1725$73_Y - attribute \src "ls180.v:1726.18-1726.59" - wire $and$ls180.v:1726$74_Y - attribute \src "ls180.v:1726.17-1726.81" - wire $and$ls180.v:1726$75_Y - attribute \src "ls180.v:1726.16-1726.107" - wire $and$ls180.v:1726$76_Y - attribute \src "ls180.v:1727.18-1727.59" - wire $and$ls180.v:1727$77_Y - attribute \src "ls180.v:1727.17-1727.81" - wire $and$ls180.v:1727$78_Y - attribute \src "ls180.v:1727.16-1727.107" - wire $and$ls180.v:1727$79_Y - attribute \src "ls180.v:1844.35-1844.84" - wire $and$ls180.v:1844$86_Y - attribute \src "ls180.v:1845.35-1845.84" - wire $and$ls180.v:1845$87_Y - attribute \src "ls180.v:1883.33-1883.88" - wire $and$ls180.v:1883$93_Y - attribute \src "ls180.v:1937.45-1937.104" - wire $and$ls180.v:1937$101_Y - attribute \src "ls180.v:1937.44-1937.147" - wire $and$ls180.v:1937$102_Y - attribute \src "ls180.v:1938.44-1938.103" - wire $and$ls180.v:1938$103_Y - attribute \src "ls180.v:1938.43-1938.134" - wire $and$ls180.v:1938$104_Y - attribute \src "ls180.v:1939.45-1939.104" - wire $and$ls180.v:1939$105_Y - attribute \src "ls180.v:1939.44-1939.135" - wire $and$ls180.v:1939$106_Y - attribute \src "ls180.v:1942.7-1942.104" - wire $and$ls180.v:1942$108_Y - attribute \src "ls180.v:1971.61-1971.226" - wire $and$ls180.v:1971$114_Y - attribute \src "ls180.v:1972.59-1972.172" - wire $and$ls180.v:1972$115_Y - attribute \src "ls180.v:1996.9-1996.76" - wire $and$ls180.v:1996$121_Y - attribute \src "ls180.v:2008.9-2008.76" - wire $and$ls180.v:2008$122_Y - attribute \src "ls180.v:2058.13-2058.77" - wire $and$ls180.v:2058$124_Y - attribute \src "ls180.v:2094.45-2094.104" - wire $and$ls180.v:2094$131_Y - attribute \src "ls180.v:2094.44-2094.147" - wire $and$ls180.v:2094$132_Y - attribute \src "ls180.v:2095.44-2095.103" - wire $and$ls180.v:2095$133_Y - attribute \src "ls180.v:2095.43-2095.134" - wire $and$ls180.v:2095$134_Y - attribute \src "ls180.v:2096.45-2096.104" - wire $and$ls180.v:2096$135_Y - attribute \src "ls180.v:2096.44-2096.135" - wire $and$ls180.v:2096$136_Y - attribute \src "ls180.v:2099.7-2099.104" - wire $and$ls180.v:2099$138_Y - attribute \src "ls180.v:2128.61-2128.226" - wire $and$ls180.v:2128$144_Y - attribute \src "ls180.v:2129.59-2129.172" - wire $and$ls180.v:2129$145_Y - attribute \src "ls180.v:2153.9-2153.76" - wire $and$ls180.v:2153$151_Y - attribute \src "ls180.v:2165.9-2165.76" - wire $and$ls180.v:2165$152_Y - attribute \src "ls180.v:2215.13-2215.77" - wire $and$ls180.v:2215$154_Y - attribute \src "ls180.v:2251.45-2251.104" - wire $and$ls180.v:2251$161_Y - attribute \src "ls180.v:2251.44-2251.147" - wire $and$ls180.v:2251$162_Y - attribute \src "ls180.v:2252.44-2252.103" - wire $and$ls180.v:2252$163_Y - attribute \src "ls180.v:2252.43-2252.134" - wire $and$ls180.v:2252$164_Y - attribute \src "ls180.v:2253.45-2253.104" - wire $and$ls180.v:2253$165_Y - attribute \src "ls180.v:2253.44-2253.135" - wire $and$ls180.v:2253$166_Y - attribute \src "ls180.v:2256.7-2256.104" - wire $and$ls180.v:2256$168_Y - attribute \src "ls180.v:2285.61-2285.226" - wire $and$ls180.v:2285$174_Y - attribute \src "ls180.v:2286.59-2286.172" - wire $and$ls180.v:2286$175_Y - attribute \src "ls180.v:2310.9-2310.76" - wire $and$ls180.v:2310$181_Y - attribute \src "ls180.v:2322.9-2322.76" - wire $and$ls180.v:2322$182_Y - attribute \src "ls180.v:2372.13-2372.77" - wire $and$ls180.v:2372$184_Y - attribute \src "ls180.v:2408.45-2408.104" - wire $and$ls180.v:2408$191_Y - attribute \src "ls180.v:2408.44-2408.147" - wire $and$ls180.v:2408$192_Y - attribute \src "ls180.v:2409.44-2409.103" - wire $and$ls180.v:2409$193_Y - attribute \src "ls180.v:2409.43-2409.134" - wire $and$ls180.v:2409$194_Y - attribute \src "ls180.v:2410.45-2410.104" - wire $and$ls180.v:2410$195_Y - attribute \src "ls180.v:2410.44-2410.135" - wire $and$ls180.v:2410$196_Y - attribute \src "ls180.v:2413.7-2413.104" - wire $and$ls180.v:2413$198_Y - attribute \src "ls180.v:2442.61-2442.226" - wire $and$ls180.v:2442$204_Y - attribute \src "ls180.v:2443.59-2443.172" - wire $and$ls180.v:2443$205_Y - attribute \src "ls180.v:2467.9-2467.76" - wire $and$ls180.v:2467$211_Y - attribute \src "ls180.v:2479.9-2479.76" - wire $and$ls180.v:2479$212_Y - attribute \src "ls180.v:2529.13-2529.77" - wire $and$ls180.v:2529$214_Y - attribute \src "ls180.v:2544.32-2544.87" - wire $and$ls180.v:2544$215_Y - attribute \src "ls180.v:2544.93-2544.163" - wire $and$ls180.v:2544$217_Y - attribute \src "ls180.v:2544.92-2544.201" - wire $and$ls180.v:2544$219_Y - attribute \src "ls180.v:2544.31-2544.202" - wire $and$ls180.v:2544$220_Y - attribute \src "ls180.v:2545.32-2545.87" - wire $and$ls180.v:2545$221_Y - attribute \src "ls180.v:2545.93-2545.163" - wire $and$ls180.v:2545$223_Y - attribute \src "ls180.v:2545.92-2545.201" - wire $and$ls180.v:2545$225_Y - attribute \src "ls180.v:2545.31-2545.202" - wire $and$ls180.v:2545$226_Y - attribute \src "ls180.v:2546.29-2546.70" - wire $and$ls180.v:2546$227_Y - attribute \src "ls180.v:2547.32-2547.87" - wire $and$ls180.v:2547$228_Y - attribute \src "ls180.v:2547.31-2547.169" - wire $and$ls180.v:2547$230_Y - attribute \src "ls180.v:2549.32-2549.87" - wire $and$ls180.v:2549$231_Y - attribute \src "ls180.v:2549.31-2549.128" - wire $and$ls180.v:2549$232_Y - attribute \src "ls180.v:2550.35-2550.104" - wire $and$ls180.v:2550$233_Y - attribute \src "ls180.v:2550.109-2550.178" - wire $and$ls180.v:2550$234_Y - attribute \src "ls180.v:2550.184-2550.253" - wire $and$ls180.v:2550$236_Y - attribute \src "ls180.v:2550.259-2550.328" - wire $and$ls180.v:2550$238_Y - attribute \src "ls180.v:2551.36-2551.106" - wire $and$ls180.v:2551$240_Y - attribute \src "ls180.v:2551.111-2551.181" - wire $and$ls180.v:2551$241_Y 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"ls180.v:2740.220-2740.258" - wire $eq$ls180.v:2740$420_Y - attribute \src "ls180.v:2740.295-2740.333" - wire $eq$ls180.v:2740$423_Y - attribute \src "ls180.v:2745.47-2745.82" - wire $eq$ls180.v:2745$432_Y - attribute \src "ls180.v:2745.145-2745.183" - wire $eq$ls180.v:2745$433_Y - attribute \src "ls180.v:2745.220-2745.258" - wire $eq$ls180.v:2745$436_Y - attribute \src "ls180.v:2745.295-2745.333" - wire $eq$ls180.v:2745$439_Y - attribute \src "ls180.v:2750.47-2750.82" - wire $eq$ls180.v:2750$448_Y - attribute \src "ls180.v:2750.145-2750.183" - wire $eq$ls180.v:2750$449_Y - attribute \src "ls180.v:2750.220-2750.258" - wire $eq$ls180.v:2750$452_Y - attribute \src "ls180.v:2750.295-2750.333" - wire $eq$ls180.v:2750$455_Y - attribute \src "ls180.v:2755.47-2755.82" - wire $eq$ls180.v:2755$464_Y - attribute \src "ls180.v:2755.145-2755.183" - wire $eq$ls180.v:2755$465_Y - attribute \src "ls180.v:2755.220-2755.258" - wire $eq$ls180.v:2755$468_Y - attribute \src "ls180.v:2755.295-2755.333" - wire $eq$ls180.v:2755$471_Y - attribute \src "ls180.v:2760.39-2760.77" - wire $eq$ls180.v:2760$480_Y - attribute \src "ls180.v:2760.83-2760.118" - wire $eq$ls180.v:2760$481_Y - attribute \src "ls180.v:2760.181-2760.219" - wire $eq$ls180.v:2760$482_Y - attribute \src "ls180.v:2760.256-2760.294" - wire $eq$ls180.v:2760$485_Y - attribute \src "ls180.v:2760.331-2760.369" - wire $eq$ls180.v:2760$488_Y - attribute \src "ls180.v:2760.413-2760.451" - wire $eq$ls180.v:2760$496_Y - attribute \src "ls180.v:2760.457-2760.492" - wire $eq$ls180.v:2760$497_Y - attribute \src "ls180.v:2760.555-2760.593" - wire $eq$ls180.v:2760$498_Y - attribute \src "ls180.v:2760.630-2760.668" - wire $eq$ls180.v:2760$501_Y - attribute \src "ls180.v:2760.705-2760.743" - wire $eq$ls180.v:2760$504_Y - attribute \src "ls180.v:2760.787-2760.825" - wire $eq$ls180.v:2760$512_Y - attribute \src "ls180.v:2760.831-2760.866" - wire $eq$ls180.v:2760$513_Y - attribute \src "ls180.v:2760.929-2760.967" - wire $eq$ls180.v:2760$514_Y - attribute \src "ls180.v:2760.1004-2760.1042" - wire $eq$ls180.v:2760$517_Y - attribute \src "ls180.v:2760.1079-2760.1117" - wire $eq$ls180.v:2760$520_Y - attribute \src "ls180.v:2760.1161-2760.1199" - wire $eq$ls180.v:2760$528_Y - attribute \src "ls180.v:2760.1205-2760.1240" - wire $eq$ls180.v:2760$529_Y - attribute \src "ls180.v:2760.1303-2760.1341" - wire $eq$ls180.v:2760$530_Y - attribute \src "ls180.v:2760.1378-2760.1416" - wire $eq$ls180.v:2760$533_Y - attribute \src "ls180.v:2760.1453-2760.1491" - wire $eq$ls180.v:2760$536_Y - attribute \src "ls180.v:2819.24-2819.47" - wire $eq$ls180.v:2819$549_Y - attribute \src "ls180.v:2826.11-2826.36" - wire $eq$ls180.v:2826$554_Y - attribute \src "ls180.v:3083.84-3083.109" - wire $eq$ls180.v:3083$626_Y - attribute \src "ls180.v:3084.84-3084.109" - wire $eq$ls180.v:3084$628_Y - attribute \src "ls180.v:3085.84-3085.109" - wire $eq$ls180.v:3085$630_Y - attribute \src "ls180.v:3086.84-3086.109" - wire $eq$ls180.v:3086$632_Y - attribute \src "ls180.v:3087.84-3087.109" - wire $eq$ls180.v:3087$634_Y - attribute \src "ls180.v:3088.84-3088.109" - wire $eq$ls180.v:3088$636_Y - attribute \src "ls180.v:3092.31-3092.67" - wire $eq$ls180.v:3092$639_Y - attribute \src "ls180.v:3093.31-3093.68" - wire $eq$ls180.v:3093$640_Y - attribute \src "ls180.v:3094.31-3094.76" - wire $eq$ls180.v:3094$641_Y - attribute \src "ls180.v:3095.31-3095.74" - wire $eq$ls180.v:3095$642_Y - attribute \src "ls180.v:3096.31-3096.69" - wire $eq$ls180.v:3096$643_Y - attribute \src "ls180.v:3097.31-3097.73" - wire $eq$ls180.v:3097$644_Y - attribute \src "ls180.v:3161.28-3161.53" - wire $eq$ls180.v:3161$676_Y - attribute \src "ls180.v:3162.36-3162.85" - wire $eq$ls180.v:3162$677_Y - attribute \src "ls180.v:3164.109-3164.157" - wire $eq$ls180.v:3164$679_Y - attribute \src "ls180.v:3165.112-3165.160" - wire $eq$ls180.v:3165$683_Y + wire $eq$ls180.v:2650$393_Y + attribute \src "ls180.v:2731.47-2731.82" + wire $eq$ls180.v:2731$416_Y + attribute \src "ls180.v:2731.145-2731.183" + wire $eq$ls180.v:2731$417_Y + attribute \src "ls180.v:2731.220-2731.258" + wire $eq$ls180.v:2731$420_Y + attribute \src "ls180.v:2731.295-2731.333" + wire $eq$ls180.v:2731$423_Y + attribute \src "ls180.v:2736.47-2736.82" + wire $eq$ls180.v:2736$432_Y + attribute \src "ls180.v:2736.145-2736.183" + wire $eq$ls180.v:2736$433_Y + attribute \src "ls180.v:2736.220-2736.258" + wire $eq$ls180.v:2736$436_Y + attribute \src "ls180.v:2736.295-2736.333" + wire $eq$ls180.v:2736$439_Y + attribute \src "ls180.v:2741.47-2741.82" + wire $eq$ls180.v:2741$448_Y + attribute \src "ls180.v:2741.145-2741.183" + wire $eq$ls180.v:2741$449_Y + attribute \src "ls180.v:2741.220-2741.258" + wire $eq$ls180.v:2741$452_Y + attribute \src "ls180.v:2741.295-2741.333" + wire $eq$ls180.v:2741$455_Y + attribute \src "ls180.v:2746.47-2746.82" + wire $eq$ls180.v:2746$464_Y + attribute \src "ls180.v:2746.145-2746.183" + wire $eq$ls180.v:2746$465_Y + attribute \src "ls180.v:2746.220-2746.258" + wire $eq$ls180.v:2746$468_Y + attribute \src "ls180.v:2746.295-2746.333" + wire $eq$ls180.v:2746$471_Y + attribute \src "ls180.v:2751.39-2751.77" + wire $eq$ls180.v:2751$480_Y + attribute \src "ls180.v:2751.83-2751.118" + wire $eq$ls180.v:2751$481_Y + attribute \src "ls180.v:2751.181-2751.219" + wire $eq$ls180.v:2751$482_Y + attribute \src "ls180.v:2751.256-2751.294" + wire $eq$ls180.v:2751$485_Y + attribute \src "ls180.v:2751.331-2751.369" + wire $eq$ls180.v:2751$488_Y + attribute \src "ls180.v:2751.413-2751.451" + wire $eq$ls180.v:2751$496_Y + attribute \src "ls180.v:2751.457-2751.492" + wire $eq$ls180.v:2751$497_Y + attribute \src "ls180.v:2751.555-2751.593" + wire $eq$ls180.v:2751$498_Y + attribute \src "ls180.v:2751.630-2751.668" + wire $eq$ls180.v:2751$501_Y + attribute \src "ls180.v:2751.705-2751.743" + wire $eq$ls180.v:2751$504_Y + attribute \src "ls180.v:2751.787-2751.825" + wire $eq$ls180.v:2751$512_Y + attribute \src "ls180.v:2751.831-2751.866" + wire $eq$ls180.v:2751$513_Y + attribute \src "ls180.v:2751.929-2751.967" + wire $eq$ls180.v:2751$514_Y + attribute \src "ls180.v:2751.1004-2751.1042" + wire $eq$ls180.v:2751$517_Y + attribute \src "ls180.v:2751.1079-2751.1117" + wire $eq$ls180.v:2751$520_Y + attribute \src "ls180.v:2751.1161-2751.1199" + wire $eq$ls180.v:2751$528_Y + attribute \src "ls180.v:2751.1205-2751.1240" + wire $eq$ls180.v:2751$529_Y + attribute \src "ls180.v:2751.1303-2751.1341" + wire $eq$ls180.v:2751$530_Y + attribute \src "ls180.v:2751.1378-2751.1416" + wire $eq$ls180.v:2751$533_Y + attribute \src "ls180.v:2751.1453-2751.1491" + wire $eq$ls180.v:2751$536_Y + attribute \src "ls180.v:2810.24-2810.47" + wire $eq$ls180.v:2810$549_Y + attribute \src "ls180.v:2817.11-2817.36" + wire $eq$ls180.v:2817$554_Y + attribute \src "ls180.v:3074.84-3074.109" + wire $eq$ls180.v:3074$626_Y + attribute \src "ls180.v:3075.84-3075.109" + wire $eq$ls180.v:3075$628_Y + attribute \src "ls180.v:3076.84-3076.109" + wire $eq$ls180.v:3076$630_Y + attribute \src "ls180.v:3077.84-3077.109" + wire $eq$ls180.v:3077$632_Y + attribute \src "ls180.v:3078.84-3078.109" + wire $eq$ls180.v:3078$634_Y + attribute \src "ls180.v:3079.84-3079.109" + wire $eq$ls180.v:3079$636_Y + attribute \src "ls180.v:3083.31-3083.67" + wire $eq$ls180.v:3083$639_Y + attribute \src "ls180.v:3084.31-3084.68" + wire $eq$ls180.v:3084$640_Y + attribute \src "ls180.v:3085.31-3085.76" + wire $eq$ls180.v:3085$641_Y + attribute \src "ls180.v:3086.31-3086.74" + wire $eq$ls180.v:3086$642_Y + attribute \src "ls180.v:3087.31-3087.69" + wire $eq$ls180.v:3087$643_Y + attribute \src "ls180.v:3088.31-3088.73" + wire $eq$ls180.v:3088$644_Y + attribute \src "ls180.v:3152.28-3152.53" + wire $eq$ls180.v:3152$676_Y + attribute \src "ls180.v:3153.36-3153.85" + wire $eq$ls180.v:3153$677_Y + attribute \src "ls180.v:3155.109-3155.157" + wire $eq$ls180.v:3155$679_Y + attribute \src "ls180.v:3156.112-3156.160" + wire $eq$ls180.v:3156$683_Y + attribute \src "ls180.v:3158.111-3158.159" + wire $eq$ls180.v:3158$686_Y + attribute \src "ls180.v:3159.114-3159.162" + wire $eq$ls180.v:3159$690_Y + attribute \src "ls180.v:3161.111-3161.159" + wire $eq$ls180.v:3161$693_Y + attribute \src "ls180.v:3162.114-3162.162" + wire $eq$ls180.v:3162$697_Y + attribute \src "ls180.v:3164.111-3164.159" + wire $eq$ls180.v:3164$700_Y + attribute \src "ls180.v:3165.114-3165.162" + wire $eq$ls180.v:3165$704_Y attribute \src "ls180.v:3167.111-3167.159" - wire $eq$ls180.v:3167$686_Y + wire $eq$ls180.v:3167$707_Y attribute \src "ls180.v:3168.114-3168.162" - wire $eq$ls180.v:3168$690_Y - attribute \src "ls180.v:3170.111-3170.159" - wire $eq$ls180.v:3170$693_Y - attribute \src "ls180.v:3171.114-3171.162" - wire $eq$ls180.v:3171$697_Y - attribute \src "ls180.v:3173.111-3173.159" - wire $eq$ls180.v:3173$700_Y - attribute \src "ls180.v:3174.114-3174.162" - wire $eq$ls180.v:3174$704_Y - attribute \src "ls180.v:3176.111-3176.159" - wire $eq$ls180.v:3176$707_Y - attribute \src "ls180.v:3177.114-3177.162" - wire $eq$ls180.v:3177$711_Y + wire $eq$ls180.v:3168$711_Y + attribute \src "ls180.v:3170.114-3170.162" + wire $eq$ls180.v:3170$714_Y + attribute \src "ls180.v:3171.117-3171.165" + wire $eq$ls180.v:3171$718_Y + attribute \src "ls180.v:3173.114-3173.162" + wire $eq$ls180.v:3173$721_Y + attribute \src "ls180.v:3174.117-3174.165" + wire $eq$ls180.v:3174$725_Y + attribute \src "ls180.v:3176.114-3176.162" + wire $eq$ls180.v:3176$728_Y + attribute \src "ls180.v:3177.117-3177.165" + wire $eq$ls180.v:3177$732_Y attribute \src "ls180.v:3179.114-3179.162" - wire $eq$ls180.v:3179$714_Y + wire $eq$ls180.v:3179$735_Y attribute \src "ls180.v:3180.117-3180.165" - wire $eq$ls180.v:3180$718_Y - attribute \src "ls180.v:3182.114-3182.162" - wire $eq$ls180.v:3182$721_Y - attribute \src "ls180.v:3183.117-3183.165" - wire $eq$ls180.v:3183$725_Y - attribute \src "ls180.v:3185.114-3185.162" - wire $eq$ls180.v:3185$728_Y - attribute \src "ls180.v:3186.117-3186.165" - wire $eq$ls180.v:3186$732_Y - attribute \src "ls180.v:3188.114-3188.162" - wire $eq$ls180.v:3188$735_Y - attribute \src "ls180.v:3189.117-3189.165" - wire $eq$ls180.v:3189$739_Y - attribute \src "ls180.v:3200.36-3200.85" - wire $eq$ls180.v:3200$741_Y - attribute \src "ls180.v:3202.106-3202.154" - wire $eq$ls180.v:3202$743_Y - attribute \src "ls180.v:3203.109-3203.157" - wire $eq$ls180.v:3203$747_Y - attribute \src "ls180.v:3205.105-3205.153" - wire $eq$ls180.v:3205$750_Y - attribute \src "ls180.v:3206.108-3206.156" - wire $eq$ls180.v:3206$754_Y - attribute \src "ls180.v:3208.107-3208.155" - wire $eq$ls180.v:3208$757_Y - attribute \src "ls180.v:3209.110-3209.158" - wire $eq$ls180.v:3209$761_Y - attribute \src "ls180.v:3214.36-3214.85" - wire $eq$ls180.v:3214$763_Y - attribute \src "ls180.v:3216.106-3216.154" - wire $eq$ls180.v:3216$765_Y - attribute \src "ls180.v:3217.109-3217.157" - wire $eq$ls180.v:3217$769_Y - attribute \src "ls180.v:3219.105-3219.153" - wire $eq$ls180.v:3219$772_Y - attribute \src "ls180.v:3220.108-3220.156" - wire $eq$ls180.v:3220$776_Y - attribute \src "ls180.v:3222.107-3222.155" - wire $eq$ls180.v:3222$779_Y - attribute \src "ls180.v:3223.110-3223.158" - wire $eq$ls180.v:3223$783_Y - attribute \src "ls180.v:3228.36-3228.85" - wire $eq$ls180.v:3228$785_Y - attribute \src "ls180.v:3230.105-3230.151" - wire $eq$ls180.v:3230$787_Y - attribute \src "ls180.v:3231.108-3231.154" - wire $eq$ls180.v:3231$791_Y - attribute \src "ls180.v:3233.104-3233.150" - wire $eq$ls180.v:3233$794_Y - attribute \src "ls180.v:3234.107-3234.153" - wire $eq$ls180.v:3234$798_Y - attribute \src "ls180.v:3242.36-3242.85" - wire $eq$ls180.v:3242$800_Y - attribute \src "ls180.v:3244.116-3244.164" - wire $eq$ls180.v:3244$802_Y - attribute \src "ls180.v:3245.119-3245.167" - wire $eq$ls180.v:3245$806_Y + wire $eq$ls180.v:3180$739_Y + attribute \src "ls180.v:3191.36-3191.85" + wire $eq$ls180.v:3191$741_Y + attribute \src "ls180.v:3193.106-3193.154" + wire $eq$ls180.v:3193$743_Y + attribute \src "ls180.v:3194.109-3194.157" + wire $eq$ls180.v:3194$747_Y + attribute \src "ls180.v:3196.105-3196.153" + wire $eq$ls180.v:3196$750_Y + attribute \src "ls180.v:3197.108-3197.156" + wire $eq$ls180.v:3197$754_Y + attribute \src "ls180.v:3199.107-3199.155" + wire $eq$ls180.v:3199$757_Y + attribute \src "ls180.v:3200.110-3200.158" + wire $eq$ls180.v:3200$761_Y + attribute \src "ls180.v:3205.36-3205.85" + wire $eq$ls180.v:3205$763_Y + attribute \src "ls180.v:3207.106-3207.154" + wire $eq$ls180.v:3207$765_Y + attribute \src "ls180.v:3208.109-3208.157" + wire $eq$ls180.v:3208$769_Y + attribute \src "ls180.v:3210.105-3210.153" + wire $eq$ls180.v:3210$772_Y + attribute \src "ls180.v:3211.108-3211.156" + wire $eq$ls180.v:3211$776_Y + attribute \src "ls180.v:3213.107-3213.155" + wire $eq$ls180.v:3213$779_Y + attribute \src "ls180.v:3214.110-3214.158" + wire $eq$ls180.v:3214$783_Y + attribute \src "ls180.v:3219.36-3219.85" + wire $eq$ls180.v:3219$785_Y + attribute \src "ls180.v:3221.105-3221.151" + wire $eq$ls180.v:3221$787_Y + attribute \src "ls180.v:3222.108-3222.154" + wire $eq$ls180.v:3222$791_Y + attribute \src "ls180.v:3224.104-3224.150" + wire $eq$ls180.v:3224$794_Y + attribute \src "ls180.v:3225.107-3225.153" + wire $eq$ls180.v:3225$798_Y + attribute \src "ls180.v:3233.36-3233.85" + wire $eq$ls180.v:3233$800_Y + attribute \src "ls180.v:3235.116-3235.164" + wire $eq$ls180.v:3235$802_Y + attribute \src "ls180.v:3236.119-3236.167" + wire $eq$ls180.v:3236$806_Y + attribute \src "ls180.v:3238.120-3238.168" + wire $eq$ls180.v:3238$809_Y + attribute \src "ls180.v:3239.123-3239.171" + wire $eq$ls180.v:3239$813_Y + attribute \src "ls180.v:3241.101-3241.149" + wire $eq$ls180.v:3241$816_Y + attribute \src "ls180.v:3242.104-3242.152" + wire $eq$ls180.v:3242$820_Y + attribute \src "ls180.v:3244.120-3244.168" + wire $eq$ls180.v:3244$823_Y + attribute \src "ls180.v:3245.123-3245.171" + wire $eq$ls180.v:3245$827_Y attribute \src "ls180.v:3247.120-3247.168" - wire $eq$ls180.v:3247$809_Y + wire $eq$ls180.v:3247$830_Y attribute \src "ls180.v:3248.123-3248.171" - wire $eq$ls180.v:3248$813_Y - attribute \src "ls180.v:3250.101-3250.149" - wire $eq$ls180.v:3250$816_Y - attribute \src "ls180.v:3251.104-3251.152" - wire $eq$ls180.v:3251$820_Y - attribute \src "ls180.v:3253.120-3253.168" - wire $eq$ls180.v:3253$823_Y - attribute \src "ls180.v:3254.123-3254.171" - wire $eq$ls180.v:3254$827_Y - attribute \src "ls180.v:3256.120-3256.168" - wire $eq$ls180.v:3256$830_Y - attribute \src "ls180.v:3257.123-3257.171" - wire $eq$ls180.v:3257$834_Y - attribute \src "ls180.v:3259.121-3259.169" - wire $eq$ls180.v:3259$837_Y - attribute \src "ls180.v:3260.124-3260.172" - wire $eq$ls180.v:3260$841_Y + wire $eq$ls180.v:3248$834_Y + attribute \src "ls180.v:3250.121-3250.169" + wire $eq$ls180.v:3250$837_Y + attribute \src "ls180.v:3251.124-3251.172" + wire $eq$ls180.v:3251$841_Y + attribute \src "ls180.v:3253.119-3253.167" + wire $eq$ls180.v:3253$844_Y + attribute \src "ls180.v:3254.122-3254.170" + wire $eq$ls180.v:3254$848_Y + attribute \src "ls180.v:3256.119-3256.167" + wire $eq$ls180.v:3256$851_Y + attribute \src "ls180.v:3257.122-3257.170" + wire $eq$ls180.v:3257$855_Y + attribute \src "ls180.v:3259.119-3259.167" + wire $eq$ls180.v:3259$858_Y + attribute \src "ls180.v:3260.122-3260.170" + wire $eq$ls180.v:3260$862_Y attribute \src "ls180.v:3262.119-3262.167" - wire $eq$ls180.v:3262$844_Y + wire $eq$ls180.v:3262$865_Y attribute \src "ls180.v:3263.122-3263.170" - wire $eq$ls180.v:3263$848_Y - attribute \src "ls180.v:3265.119-3265.167" - wire $eq$ls180.v:3265$851_Y - attribute \src "ls180.v:3266.122-3266.170" - wire $eq$ls180.v:3266$855_Y - attribute \src "ls180.v:3268.119-3268.167" - wire $eq$ls180.v:3268$858_Y - attribute \src "ls180.v:3269.122-3269.170" - wire $eq$ls180.v:3269$862_Y - attribute \src "ls180.v:3271.119-3271.167" - wire $eq$ls180.v:3271$865_Y - attribute \src "ls180.v:3272.122-3272.170" - wire $eq$ls180.v:3272$869_Y - attribute \src "ls180.v:3287.36-3287.85" - wire $eq$ls180.v:3287$871_Y + wire $eq$ls180.v:3263$869_Y + attribute \src "ls180.v:3278.36-3278.85" + wire $eq$ls180.v:3278$871_Y + attribute \src "ls180.v:3280.108-3280.156" + wire $eq$ls180.v:3280$873_Y + attribute \src "ls180.v:3281.111-3281.159" + wire $eq$ls180.v:3281$877_Y + attribute \src "ls180.v:3283.108-3283.156" + wire $eq$ls180.v:3283$880_Y + attribute \src "ls180.v:3284.111-3284.159" + wire $eq$ls180.v:3284$884_Y + attribute \src "ls180.v:3286.108-3286.156" + wire $eq$ls180.v:3286$887_Y + attribute \src "ls180.v:3287.111-3287.159" + wire $eq$ls180.v:3287$891_Y attribute \src "ls180.v:3289.108-3289.156" - wire $eq$ls180.v:3289$873_Y + wire $eq$ls180.v:3289$894_Y attribute \src "ls180.v:3290.111-3290.159" - wire $eq$ls180.v:3290$877_Y - attribute \src "ls180.v:3292.108-3292.156" - wire $eq$ls180.v:3292$880_Y - attribute \src "ls180.v:3293.111-3293.159" - wire $eq$ls180.v:3293$884_Y - attribute \src "ls180.v:3295.108-3295.156" - wire $eq$ls180.v:3295$887_Y - attribute \src "ls180.v:3296.111-3296.159" - wire $eq$ls180.v:3296$891_Y - attribute \src "ls180.v:3298.108-3298.156" - wire $eq$ls180.v:3298$894_Y - attribute \src "ls180.v:3299.111-3299.159" - wire $eq$ls180.v:3299$898_Y + wire $eq$ls180.v:3290$898_Y + attribute \src "ls180.v:3292.110-3292.158" + wire $eq$ls180.v:3292$901_Y + attribute \src "ls180.v:3293.113-3293.161" + wire $eq$ls180.v:3293$905_Y + attribute \src "ls180.v:3295.110-3295.158" + wire $eq$ls180.v:3295$908_Y + attribute \src "ls180.v:3296.113-3296.161" + wire $eq$ls180.v:3296$912_Y + attribute \src "ls180.v:3298.110-3298.158" + wire $eq$ls180.v:3298$915_Y + attribute \src "ls180.v:3299.113-3299.161" + wire $eq$ls180.v:3299$919_Y attribute \src "ls180.v:3301.110-3301.158" - wire $eq$ls180.v:3301$901_Y + wire $eq$ls180.v:3301$922_Y attribute \src "ls180.v:3302.113-3302.161" - wire $eq$ls180.v:3302$905_Y - attribute \src "ls180.v:3304.110-3304.158" - wire $eq$ls180.v:3304$908_Y - attribute \src "ls180.v:3305.113-3305.161" - wire $eq$ls180.v:3305$912_Y - attribute \src "ls180.v:3307.110-3307.158" - wire $eq$ls180.v:3307$915_Y - attribute \src "ls180.v:3308.113-3308.161" - wire $eq$ls180.v:3308$919_Y - attribute \src "ls180.v:3310.110-3310.158" - wire $eq$ls180.v:3310$922_Y - attribute \src "ls180.v:3311.113-3311.161" - wire $eq$ls180.v:3311$926_Y - attribute \src "ls180.v:3313.106-3313.154" - wire $eq$ls180.v:3313$929_Y - attribute \src "ls180.v:3314.109-3314.157" - wire $eq$ls180.v:3314$933_Y - attribute \src "ls180.v:3316.116-3316.164" - wire $eq$ls180.v:3316$936_Y - attribute \src "ls180.v:3317.119-3317.167" - wire $eq$ls180.v:3317$940_Y + wire $eq$ls180.v:3302$926_Y + attribute \src "ls180.v:3304.106-3304.154" + wire $eq$ls180.v:3304$929_Y + attribute \src "ls180.v:3305.109-3305.157" + wire $eq$ls180.v:3305$933_Y + attribute \src "ls180.v:3307.116-3307.164" + wire $eq$ls180.v:3307$936_Y + attribute \src "ls180.v:3308.119-3308.167" + wire $eq$ls180.v:3308$940_Y + attribute \src "ls180.v:3310.109-3310.158" + wire $eq$ls180.v:3310$943_Y + attribute \src "ls180.v:3311.112-3311.161" + wire $eq$ls180.v:3311$947_Y + attribute \src "ls180.v:3313.109-3313.158" + wire $eq$ls180.v:3313$950_Y + attribute \src "ls180.v:3314.112-3314.161" + wire $eq$ls180.v:3314$954_Y + attribute \src "ls180.v:3316.109-3316.158" + wire $eq$ls180.v:3316$957_Y + attribute \src "ls180.v:3317.112-3317.161" + wire $eq$ls180.v:3317$961_Y attribute \src "ls180.v:3319.109-3319.158" - wire $eq$ls180.v:3319$943_Y + wire $eq$ls180.v:3319$964_Y attribute \src "ls180.v:3320.112-3320.161" - wire $eq$ls180.v:3320$947_Y - attribute \src "ls180.v:3322.109-3322.158" - wire $eq$ls180.v:3322$950_Y - attribute \src "ls180.v:3323.112-3323.161" - wire $eq$ls180.v:3323$954_Y - attribute \src "ls180.v:3325.109-3325.158" - wire $eq$ls180.v:3325$957_Y - attribute \src "ls180.v:3326.112-3326.161" - wire $eq$ls180.v:3326$961_Y - attribute \src "ls180.v:3328.109-3328.158" - wire $eq$ls180.v:3328$964_Y - attribute \src "ls180.v:3329.112-3329.161" - wire $eq$ls180.v:3329$968_Y - attribute \src "ls180.v:3331.113-3331.162" - wire $eq$ls180.v:3331$971_Y - attribute \src "ls180.v:3332.116-3332.165" - wire $eq$ls180.v:3332$975_Y - attribute \src "ls180.v:3334.114-3334.163" - wire $eq$ls180.v:3334$978_Y - attribute \src "ls180.v:3335.117-3335.166" - wire $eq$ls180.v:3335$982_Y - attribute \src "ls180.v:3337.113-3337.162" - wire $eq$ls180.v:3337$985_Y - attribute \src "ls180.v:3338.116-3338.165" - wire $eq$ls180.v:3338$989_Y - attribute \src "ls180.v:3355.36-3355.85" - wire $eq$ls180.v:3355$991_Y - attribute \src "ls180.v:3357.86-3357.134" - wire $eq$ls180.v:3357$993_Y - attribute \src "ls180.v:3358.89-3358.137" - wire $eq$ls180.v:3358$997_Y - attribute \src "ls180.v:3360.109-3360.157" - wire $eq$ls180.v:3360$1000_Y - attribute \src "ls180.v:3361.112-3361.160" - wire $eq$ls180.v:3361$1004_Y - attribute \src "ls180.v:3363.110-3363.158" - wire $eq$ls180.v:3363$1007_Y - attribute \src "ls180.v:3364.113-3364.161" - wire $eq$ls180.v:3364$1011_Y - attribute \src "ls180.v:3366.101-3366.149" - wire $eq$ls180.v:3366$1014_Y - attribute \src "ls180.v:3367.104-3367.152" - wire $eq$ls180.v:3367$1018_Y - attribute \src "ls180.v:3369.102-3369.150" - wire $eq$ls180.v:3369$1021_Y - attribute \src "ls180.v:3370.105-3370.153" - wire $eq$ls180.v:3370$1025_Y - attribute \src "ls180.v:3372.113-3372.161" - wire $eq$ls180.v:3372$1028_Y - attribute \src "ls180.v:3373.116-3373.164" - wire $eq$ls180.v:3373$1032_Y - attribute \src "ls180.v:3375.110-3375.158" - wire $eq$ls180.v:3375$1035_Y - attribute \src "ls180.v:3376.113-3376.161" - wire $eq$ls180.v:3376$1039_Y - attribute \src "ls180.v:3378.109-3378.157" - wire $eq$ls180.v:3378$1042_Y - attribute \src "ls180.v:3379.112-3379.160" - wire $eq$ls180.v:3379$1046_Y - attribute \src "ls180.v:3389.36-3389.85" - wire $eq$ls180.v:3389$1048_Y + wire $eq$ls180.v:3320$968_Y + attribute \src "ls180.v:3322.113-3322.162" + wire $eq$ls180.v:3322$971_Y + attribute \src "ls180.v:3323.116-3323.165" + wire $eq$ls180.v:3323$975_Y + attribute \src "ls180.v:3325.114-3325.163" + wire $eq$ls180.v:3325$978_Y + attribute \src "ls180.v:3326.117-3326.166" + wire $eq$ls180.v:3326$982_Y + attribute \src "ls180.v:3328.113-3328.162" + wire $eq$ls180.v:3328$985_Y + attribute \src "ls180.v:3329.116-3329.165" + wire $eq$ls180.v:3329$989_Y + attribute \src "ls180.v:3346.36-3346.85" + wire $eq$ls180.v:3346$991_Y + attribute \src "ls180.v:3348.86-3348.134" + wire $eq$ls180.v:3348$993_Y + attribute \src "ls180.v:3349.89-3349.137" + wire $eq$ls180.v:3349$997_Y + attribute \src "ls180.v:3351.109-3351.157" + wire $eq$ls180.v:3351$1000_Y + attribute \src "ls180.v:3352.112-3352.160" + wire $eq$ls180.v:3352$1004_Y + attribute \src "ls180.v:3354.110-3354.158" + wire $eq$ls180.v:3354$1007_Y + attribute \src "ls180.v:3355.113-3355.161" + wire $eq$ls180.v:3355$1011_Y + attribute \src "ls180.v:3357.101-3357.149" + wire $eq$ls180.v:3357$1014_Y + attribute \src "ls180.v:3358.104-3358.152" + wire $eq$ls180.v:3358$1018_Y + attribute \src "ls180.v:3360.102-3360.150" + wire $eq$ls180.v:3360$1021_Y + attribute \src "ls180.v:3361.105-3361.153" + wire $eq$ls180.v:3361$1025_Y + attribute \src "ls180.v:3363.113-3363.161" + wire $eq$ls180.v:3363$1028_Y + attribute \src "ls180.v:3364.116-3364.164" + wire $eq$ls180.v:3364$1032_Y + attribute \src "ls180.v:3366.110-3366.158" + wire $eq$ls180.v:3366$1035_Y + attribute \src "ls180.v:3367.113-3367.161" + wire $eq$ls180.v:3367$1039_Y + attribute \src "ls180.v:3369.109-3369.157" + wire $eq$ls180.v:3369$1042_Y + attribute \src "ls180.v:3370.112-3370.160" + wire $eq$ls180.v:3370$1046_Y + attribute \src "ls180.v:3380.36-3380.85" + wire $eq$ls180.v:3380$1048_Y + attribute \src "ls180.v:3382.115-3382.163" + wire $eq$ls180.v:3382$1050_Y + attribute \src "ls180.v:3383.118-3383.166" + wire $eq$ls180.v:3383$1054_Y + attribute \src "ls180.v:3385.115-3385.163" + wire $eq$ls180.v:3385$1057_Y + attribute \src "ls180.v:3386.118-3386.166" + wire $eq$ls180.v:3386$1061_Y + attribute \src "ls180.v:3388.115-3388.163" + wire $eq$ls180.v:3388$1064_Y + attribute \src "ls180.v:3389.118-3389.166" + wire $eq$ls180.v:3389$1068_Y attribute \src "ls180.v:3391.115-3391.163" - wire $eq$ls180.v:3391$1050_Y + wire $eq$ls180.v:3391$1071_Y attribute \src "ls180.v:3392.118-3392.166" - wire $eq$ls180.v:3392$1054_Y - attribute \src "ls180.v:3394.115-3394.163" - wire $eq$ls180.v:3394$1057_Y - attribute \src "ls180.v:3395.118-3395.166" - wire $eq$ls180.v:3395$1061_Y - attribute \src "ls180.v:3397.115-3397.163" - wire $eq$ls180.v:3397$1064_Y - attribute \src "ls180.v:3398.118-3398.166" - wire $eq$ls180.v:3398$1068_Y - attribute \src "ls180.v:3400.115-3400.163" - wire $eq$ls180.v:3400$1071_Y - attribute \src "ls180.v:3401.118-3401.166" - wire $eq$ls180.v:3401$1075_Y - attribute \src "ls180.v:3761.28-3761.63" - wire $eq$ls180.v:3761$1105_Y - attribute \src "ls180.v:3761.126-3761.164" - wire $eq$ls180.v:3761$1106_Y - attribute \src "ls180.v:3761.201-3761.239" - wire $eq$ls180.v:3761$1109_Y - attribute \src "ls180.v:3761.276-3761.314" - wire $eq$ls180.v:3761$1112_Y - attribute \src "ls180.v:3785.28-3785.63" - wire $eq$ls180.v:3785$1121_Y - attribute \src "ls180.v:3785.126-3785.164" - wire $eq$ls180.v:3785$1122_Y - attribute \src "ls180.v:3785.201-3785.239" - wire $eq$ls180.v:3785$1125_Y - attribute \src "ls180.v:3785.276-3785.314" - wire $eq$ls180.v:3785$1128_Y - attribute \src "ls180.v:3809.28-3809.63" - wire $eq$ls180.v:3809$1137_Y - attribute \src "ls180.v:3809.126-3809.164" - wire $eq$ls180.v:3809$1138_Y - attribute \src "ls180.v:3809.201-3809.239" - wire $eq$ls180.v:3809$1141_Y - attribute \src "ls180.v:3809.276-3809.314" - wire $eq$ls180.v:3809$1144_Y - attribute \src "ls180.v:3833.28-3833.63" - wire $eq$ls180.v:3833$1153_Y - attribute \src "ls180.v:3833.126-3833.164" - wire $eq$ls180.v:3833$1154_Y - attribute \src "ls180.v:3833.201-3833.239" - wire $eq$ls180.v:3833$1157_Y - attribute \src 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$eq$ls180.v:4803$1360_Y - attribute \src "ls180.v:4803.136-4803.174" - wire $eq$ls180.v:4803$1363_Y - attribute \src "ls180.v:4803.218-4803.256" - wire $eq$ls180.v:4803$1366_Y - attribute \src "ls180.v:4803.300-4803.338" - wire $eq$ls180.v:4803$1369_Y - attribute \src "ls180.v:4804.55-4804.93" - wire $eq$ls180.v:4804$1372_Y - attribute \src "ls180.v:4804.137-4804.175" - wire $eq$ls180.v:4804$1375_Y - attribute \src "ls180.v:4804.219-4804.257" - wire $eq$ls180.v:4804$1378_Y - attribute \src "ls180.v:4804.301-4804.339" - wire $eq$ls180.v:4804$1381_Y - attribute \src "ls180.v:4839.9-4839.37" - wire $eq$ls180.v:4839$1393_Y - attribute \src "ls180.v:4842.10-4842.38" - wire $eq$ls180.v:4842$1394_Y - attribute \src "ls180.v:4868.9-4868.37" - wire $eq$ls180.v:4868$1400_Y - attribute \src "ls180.v:4873.10-4873.38" - wire $eq$ls180.v:4873$1401_Y - attribute \src "ls180.v:5507.28-5507.31" - wire width 32 $memrd$\mem$ls180.v:5507$1459_DATA - attribute \src "ls180.v:5527.20-5527.25" - wire width 32 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$sub$ls180.v:4626$1347_Y + attribute \src "ls180.v:4637.20-4637.38" + wire width 5 $sub$ls180.v:4637$1351_Y + attribute \src "ls180.v:4644.20-4644.38" + wire width 4 $sub$ls180.v:4644$1354_Y + attribute \src "ls180.v:4776.28-4776.54" + wire $sub$ls180.v:4776$1359_Y + attribute \src "ls180.v:4791.28-4791.54" + wire width 3 $sub$ls180.v:4791$1362_Y + attribute \src "ls180.v:4918.23-4918.44" + wire width 5 $sub$ls180.v:4918$1421_Y + attribute \src "ls180.v:4940.23-4940.44" + wire width 5 $sub$ls180.v:4940$1432_Y + attribute \src "ls180.v:5005.26-5005.50" + wire width 20 $sub$ls180.v:5005$1437_Y + attribute \src "ls180.v:828.6-828.13" wire \ack_cmd - attribute \src "ls180.v:836.6-836.15" + attribute \src "ls180.v:830.6-830.15" wire \ack_rdata - attribute \src "ls180.v:835.6-835.15" + attribute \src "ls180.v:829.6-829.15" wire \ack_wdata - attribute \src "ls180.v:1381.11-1381.23" + attribute \src "ls180.v:1375.11-1375.23" wire width 2 \array_muxed0 - attribute \src "ls180.v:1382.12-1382.24" + attribute \src "ls180.v:1376.12-1376.24" wire width 13 \array_muxed1 - attribute \src "ls180.v:1383.5-1383.17" + attribute \src "ls180.v:1377.5-1377.17" wire \array_muxed2 - attribute \src "ls180.v:1384.5-1384.17" + attribute \src "ls180.v:1378.5-1378.17" wire \array_muxed3 - attribute \src "ls180.v:1385.5-1385.17" + attribute \src "ls180.v:1379.5-1379.17" wire \array_muxed4 - attribute \src "ls180.v:1386.5-1386.17" + attribute \src "ls180.v:1380.5-1380.17" wire \array_muxed5 - attribute \src "ls180.v:1387.5-1387.17" + attribute \src "ls180.v:1381.5-1381.17" wire \array_muxed6 - attribute \src "ls180.v:832.5-832.17" + attribute \src "ls180.v:826.5-826.17" wire \cmd_consumed - attribute \src "ls180.v:829.5-829.22" + attribute \src "ls180.v:823.5-823.22" wire \converter_counter - attribute \src "ls180.v:1055.5-1055.46" + attribute \src "ls180.v:1049.5-1049.46" wire \converter_counter_subfragments_next_value - attribute \src "ls180.v:1056.5-1056.49" + attribute \src "ls180.v:1050.5-1050.49" wire \converter_counter_subfragments_next_value_ce - attribute \src "ls180.v:831.12-831.27" + attribute \src "ls180.v:825.12-825.27" wire width 32 \converter_dat_r - attribute \src "ls180.v:830.6-830.21" + attribute \src "ls180.v:824.6-824.21" wire \converter_reset - attribute \src "ls180.v:828.5-828.19" + attribute \src "ls180.v:822.5-822.19" wire \converter_skip - attribute \src "ls180.v:258.6-258.18" + attribute \src "ls180.v:252.6-252.18" wire \dfi_p0_act_n - attribute \src "ls180.v:249.13-249.27" + attribute \src "ls180.v:243.13-243.27" wire width 13 \dfi_p0_address - attribute \src "ls180.v:250.12-250.23" + attribute \src "ls180.v:244.12-244.23" wire width 2 \dfi_p0_bank - attribute \src "ls180.v:251.6-251.18" + attribute \src "ls180.v:245.6-245.18" wire \dfi_p0_cas_n - attribute \src "ls180.v:255.6-255.16" + attribute \src "ls180.v:249.6-249.16" wire \dfi_p0_cke - attribute \src "ls180.v:252.6-252.17" + attribute \src "ls180.v:246.6-246.17" wire \dfi_p0_cs_n - attribute \src "ls180.v:256.6-256.16" + attribute \src "ls180.v:250.6-250.16" wire \dfi_p0_odt - attribute \src "ls180.v:253.6-253.18" + attribute \src "ls180.v:247.6-247.18" wire \dfi_p0_ras_n - attribute \src "ls180.v:263.12-263.25" + attribute \src "ls180.v:257.12-257.25" wire width 16 \dfi_p0_rddata - attribute \src "ls180.v:262.6-262.22" + attribute \src "ls180.v:256.6-256.22" wire \dfi_p0_rddata_en - attribute \src "ls180.v:264.5-264.24" + attribute \src "ls180.v:258.5-258.24" wire \dfi_p0_rddata_valid - attribute \src "ls180.v:257.6-257.20" + attribute \src "ls180.v:251.6-251.20" wire \dfi_p0_reset_n - attribute \src "ls180.v:254.6-254.17" + attribute \src "ls180.v:248.6-248.17" wire \dfi_p0_we_n - attribute \src "ls180.v:259.13-259.26" + attribute \src "ls180.v:253.13-253.26" wire width 16 \dfi_p0_wrdata - attribute \src "ls180.v:260.6-260.22" + attribute \src "ls180.v:254.6-254.22" wire \dfi_p0_wrdata_en - attribute \src "ls180.v:261.12-261.30" + attribute \src "ls180.v:255.12-255.30" wire width 2 \dfi_p0_wrdata_mask - attribute \src "ls180.v:999.12-999.17" - wire width 36 \dummy + attribute \src "ls180.v:993.12-993.17" + wire width 40 \dummy + attribute \src "ls180.v:5.13-5.19" + wire input 1 \eint_0 + attribute \src "ls180.v:6.13-6.19" + wire input 2 \eint_1 attribute \src "ls180.v:7.13-7.19" - wire input 3 \eint_0 - attribute \src "ls180.v:8.13-8.19" - wire input 4 \eint_1 - attribute \src "ls180.v:9.13-9.19" - wire input 5 \eint_2 - attribute \src "ls180.v:997.11-997.19" + wire input 3 \eint_2 + attribute \src "ls180.v:991.11-991.19" wire width 3 \eint_tmp - attribute \src "ls180.v:885.12-885.34" + attribute \src "ls180.v:879.12-879.34" wire width 2 \eventmanager_pending_r - attribute \src "ls180.v:884.6-884.29" + attribute \src "ls180.v:878.6-878.29" wire \eventmanager_pending_re - attribute \src "ls180.v:887.11-887.33" + attribute \src "ls180.v:881.11-881.33" wire width 2 \eventmanager_pending_w - attribute \src "ls180.v:886.6-886.29" + attribute \src "ls180.v:880.6-880.29" wire \eventmanager_pending_we - attribute \src "ls180.v:889.5-889.20" + attribute \src "ls180.v:883.5-883.20" wire \eventmanager_re - attribute \src "ls180.v:881.12-881.33" + attribute \src "ls180.v:875.12-875.33" wire width 2 \eventmanager_status_r - attribute \src "ls180.v:880.6-880.28" + attribute \src "ls180.v:874.6-874.28" wire \eventmanager_status_re - attribute \src "ls180.v:883.11-883.32" + attribute \src "ls180.v:877.11-877.32" wire width 2 \eventmanager_status_w - attribute \src "ls180.v:882.6-882.28" + attribute \src "ls180.v:876.6-876.28" wire \eventmanager_status_we - attribute \src "ls180.v:888.11-888.31" + attribute \src "ls180.v:882.11-882.31" wire width 2 \eventmanager_storage - attribute \src "ls180.v:980.5-980.16" + attribute \src "ls180.v:974.5-974.16" wire \gpio0_oe_re - attribute \src "ls180.v:979.11-979.27" + attribute \src "ls180.v:973.11-973.27" wire width 8 \gpio0_oe_storage - attribute \src "ls180.v:984.5-984.17" + attribute \src "ls180.v:978.5-978.17" wire \gpio0_out_re - attribute \src "ls180.v:983.11-983.28" + attribute \src "ls180.v:977.11-977.28" wire width 8 \gpio0_out_storage - attribute \src "ls180.v:985.11-985.28" + attribute \src "ls180.v:979.11-979.28" wire width 8 \gpio0_pads_gpio0i - attribute \src "ls180.v:986.11-986.28" + attribute \src "ls180.v:980.11-980.28" wire width 8 \gpio0_pads_gpio0o - attribute \src "ls180.v:987.11-987.29" + attribute \src "ls180.v:981.11-981.29" wire width 8 \gpio0_pads_gpio0oe - attribute \src "ls180.v:981.11-981.23" + attribute \src "ls180.v:975.11-975.23" wire width 8 \gpio0_status - attribute \src "ls180.v:982.6-982.14" + attribute \src "ls180.v:976.6-976.14" wire \gpio0_we - attribute \src "ls180.v:989.5-989.16" + attribute \src "ls180.v:983.5-983.16" wire \gpio1_oe_re - attribute \src "ls180.v:988.11-988.27" + attribute \src "ls180.v:982.11-982.27" wire width 8 \gpio1_oe_storage - attribute \src "ls180.v:993.5-993.17" + attribute \src "ls180.v:987.5-987.17" wire \gpio1_out_re - attribute \src "ls180.v:992.11-992.28" + attribute \src "ls180.v:986.11-986.28" wire width 8 \gpio1_out_storage - attribute \src "ls180.v:994.11-994.28" + attribute \src "ls180.v:988.11-988.28" wire width 8 \gpio1_pads_gpio1i - attribute \src "ls180.v:995.11-995.28" + attribute \src "ls180.v:989.11-989.28" wire width 8 \gpio1_pads_gpio1o - attribute \src "ls180.v:996.11-996.29" + attribute \src "ls180.v:990.11-990.29" wire width 8 \gpio1_pads_gpio1oe - attribute \src "ls180.v:990.11-990.23" + attribute \src "ls180.v:984.11-984.23" wire width 8 \gpio1_status - attribute \src "ls180.v:991.6-991.14" + attribute \src "ls180.v:985.6-985.14" wire \gpio1_we - attribute \src "ls180.v:30.20-30.26" - wire width 16 input 26 \gpio_i - attribute \src "ls180.v:31.21-31.27" - wire width 16 output 27 \gpio_o - attribute \src "ls180.v:32.21-32.28" - wire width 16 output 28 \gpio_oe - attribute \src "ls180.v:1001.6-1001.12" + attribute \src "ls180.v:26.20-26.26" + wire width 16 input 22 \gpio_i + attribute \src "ls180.v:27.21-27.27" + wire width 16 output 23 \gpio_o + attribute \src "ls180.v:28.21-28.28" + wire width 16 output 24 \gpio_oe + attribute \src "ls180.v:995.6-995.12" wire \i2c_oe - attribute \src "ls180.v:1004.5-1004.11" + attribute \src "ls180.v:998.5-998.11" wire \i2c_re - attribute \src "ls180.v:22.14-22.21" - wire output 18 \i2c_scl - attribute \src "ls180.v:1000.6-1000.15" + attribute \src "ls180.v:8.14-8.21" + wire output 4 \i2c_scl + attribute \src "ls180.v:994.6-994.15" wire \i2c_scl_1 - attribute \src "ls180.v:1002.6-1002.14" + attribute \src "ls180.v:996.6-996.14" wire \i2c_sda0 - attribute \src "ls180.v:1005.6-1005.14" + attribute \src "ls180.v:999.6-999.14" wire \i2c_sda1 - attribute \src "ls180.v:23.13-23.22" - wire input 19 \i2c_sda_i - attribute \src "ls180.v:24.14-24.23" - wire output 20 \i2c_sda_o - attribute \src "ls180.v:25.14-25.24" - wire output 21 \i2c_sda_oe - attribute \src "ls180.v:1006.6-1006.16" + attribute \src "ls180.v:9.13-9.22" + wire input 5 \i2c_sda_i + attribute \src "ls180.v:10.14-10.23" + wire output 6 \i2c_sda_o + attribute \src "ls180.v:11.14-11.24" + wire output 7 \i2c_sda_oe + attribute \src "ls180.v:1000.6-1000.16" wire \i2c_status - attribute \src "ls180.v:1003.11-1003.22" + attribute \src "ls180.v:997.11-997.22" wire width 3 \i2c_storage - attribute \src "ls180.v:1007.6-1007.12" + attribute \src "ls180.v:1001.6-1001.12" wire \i2c_we - attribute \src "ls180.v:248.5-248.12" + attribute \src "ls180.v:242.5-242.12" wire \int_rst - attribute \src "ls180.v:869.6-869.9" + attribute \src "ls180.v:863.6-863.9" wire \irq - attribute \src "ls180.v:39.13-39.21" - wire input 35 \jtag_tck - attribute \src "ls180.v:40.13-40.21" - wire input 36 \jtag_tdi - attribute \src "ls180.v:41.14-41.22" - wire output 37 \jtag_tdo - attribute \src "ls180.v:38.13-38.21" - wire input 34 \jtag_tms - attribute \src "ls180.v:199.12-199.27" + attribute \src "ls180.v:36.13-36.21" + wire input 32 \jtag_tck + attribute \src "ls180.v:37.13-37.21" + wire input 33 \jtag_tdi + attribute \src "ls180.v:38.14-38.22" + wire output 34 \jtag_tdo + attribute \src "ls180.v:35.13-35.21" + wire input 31 \jtag_tms + attribute \src "ls180.v:193.12-193.27" wire width 7 \libresocsim_adr - attribute \src "ls180.v:52.6-52.27" + attribute \src "ls180.v:49.6-49.27" wire \libresocsim_bus_error - attribute \src "ls180.v:53.12-53.34" + attribute \src "ls180.v:50.12-50.34" wire width 32 \libresocsim_bus_errors - attribute \src "ls180.v:49.13-49.42" + attribute \src "ls180.v:46.13-46.42" wire width 32 \libresocsim_bus_errors_status - attribute \src "ls180.v:50.6-50.31" + attribute \src "ls180.v:47.6-47.31" wire \libresocsim_bus_errors_we - attribute \src "ls180.v:155.5-155.35" + attribute \src "ls180.v:149.5-149.35" wire \libresocsim_converter0_counter - attribute \src "ls180.v:1010.5-1010.70" + attribute \src "ls180.v:1004.5-1004.70" wire \libresocsim_converter0_counter_subfragments_converter0_next_value - attribute \src "ls180.v:1011.5-1011.73" + attribute \src "ls180.v:1005.5-1005.73" wire \libresocsim_converter0_counter_subfragments_converter0_next_value_ce - attribute \src "ls180.v:157.12-157.40" + attribute \src "ls180.v:151.12-151.40" wire width 64 \libresocsim_converter0_dat_r - attribute \src "ls180.v:156.6-156.34" + attribute \src "ls180.v:150.6-150.34" wire \libresocsim_converter0_reset - attribute \src "ls180.v:154.5-154.32" + attribute \src "ls180.v:148.5-148.32" wire \libresocsim_converter0_skip - attribute \src "ls180.v:170.5-170.35" + attribute \src "ls180.v:164.5-164.35" wire \libresocsim_converter1_counter - attribute \src "ls180.v:1014.5-1014.70" + attribute \src "ls180.v:1008.5-1008.70" wire \libresocsim_converter1_counter_subfragments_converter1_next_value - attribute \src "ls180.v:1015.5-1015.73" + attribute \src "ls180.v:1009.5-1009.73" wire \libresocsim_converter1_counter_subfragments_converter1_next_value_ce - attribute \src "ls180.v:172.12-172.40" + attribute \src "ls180.v:166.12-166.40" wire width 64 \libresocsim_converter1_dat_r - attribute \src "ls180.v:171.6-171.34" + attribute \src "ls180.v:165.6-165.34" wire \libresocsim_converter1_reset - attribute \src "ls180.v:169.5-169.32" + attribute \src "ls180.v:163.5-163.32" wire \libresocsim_converter1_skip - attribute \src "ls180.v:185.5-185.35" + attribute \src "ls180.v:179.5-179.35" wire \libresocsim_converter2_counter - attribute \src "ls180.v:1018.5-1018.70" + attribute \src "ls180.v:1012.5-1012.70" wire \libresocsim_converter2_counter_subfragments_converter2_next_value - attribute \src "ls180.v:1019.5-1019.73" + attribute \src "ls180.v:1013.5-1013.73" wire \libresocsim_converter2_counter_subfragments_converter2_next_value_ce - attribute \src "ls180.v:187.12-187.40" + attribute \src "ls180.v:181.12-181.40" wire width 64 \libresocsim_converter2_dat_r - attribute \src "ls180.v:186.6-186.34" + attribute \src "ls180.v:180.6-180.34" wire \libresocsim_converter2_reset - attribute \src "ls180.v:184.5-184.32" + attribute \src "ls180.v:178.5-178.32" wire \libresocsim_converter2_skip - attribute \src "ls180.v:1090.12-1090.29" + attribute \src "ls180.v:1084.12-1084.29" wire width 20 \libresocsim_count - attribute \src "ls180.v:1331.13-1331.45" + attribute \src "ls180.v:1325.13-1325.45" wire width 14 \libresocsim_csr_interconnect_adr - attribute \src "ls180.v:1334.12-1334.46" + attribute \src "ls180.v:1328.12-1328.46" wire width 8 \libresocsim_csr_interconnect_dat_r - attribute \src "ls180.v:1333.12-1333.46" + attribute \src "ls180.v:1327.12-1327.46" wire width 8 \libresocsim_csr_interconnect_dat_w - attribute \src "ls180.v:1332.6-1332.37" + attribute \src "ls180.v:1326.6-1326.37" wire \libresocsim_csr_interconnect_we - attribute \src "ls180.v:1128.12-1128.46" + attribute \src "ls180.v:1122.12-1122.46" wire width 8 \libresocsim_csrbank0_bus_errors0_r - attribute \src "ls180.v:1127.6-1127.41" + attribute \src "ls180.v:1121.6-1121.41" wire \libresocsim_csrbank0_bus_errors0_re - attribute \src "ls180.v:1130.12-1130.46" + attribute \src "ls180.v:1124.12-1124.46" wire width 8 \libresocsim_csrbank0_bus_errors0_w - attribute \src "ls180.v:1129.6-1129.41" + attribute \src "ls180.v:1123.6-1123.41" wire \libresocsim_csrbank0_bus_errors0_we - attribute \src "ls180.v:1124.12-1124.46" + attribute \src "ls180.v:1118.12-1118.46" wire width 8 \libresocsim_csrbank0_bus_errors1_r - attribute \src "ls180.v:1123.6-1123.41" + attribute \src "ls180.v:1117.6-1117.41" wire \libresocsim_csrbank0_bus_errors1_re - attribute \src "ls180.v:1126.12-1126.46" + attribute \src "ls180.v:1120.12-1120.46" wire width 8 \libresocsim_csrbank0_bus_errors1_w - attribute \src "ls180.v:1125.6-1125.41" + attribute \src "ls180.v:1119.6-1119.41" wire \libresocsim_csrbank0_bus_errors1_we - attribute \src "ls180.v:1120.12-1120.46" + attribute \src "ls180.v:1114.12-1114.46" wire width 8 \libresocsim_csrbank0_bus_errors2_r - attribute \src "ls180.v:1119.6-1119.41" + attribute \src "ls180.v:1113.6-1113.41" wire \libresocsim_csrbank0_bus_errors2_re - attribute \src "ls180.v:1122.12-1122.46" + attribute \src "ls180.v:1116.12-1116.46" wire width 8 \libresocsim_csrbank0_bus_errors2_w - attribute \src "ls180.v:1121.6-1121.41" + attribute \src "ls180.v:1115.6-1115.41" wire \libresocsim_csrbank0_bus_errors2_we - attribute \src "ls180.v:1116.12-1116.46" + attribute \src "ls180.v:1110.12-1110.46" wire width 8 \libresocsim_csrbank0_bus_errors3_r - attribute \src "ls180.v:1115.6-1115.41" + attribute \src "ls180.v:1109.6-1109.41" wire \libresocsim_csrbank0_bus_errors3_re - attribute \src "ls180.v:1118.12-1118.46" + attribute \src "ls180.v:1112.12-1112.46" wire width 8 \libresocsim_csrbank0_bus_errors3_w - attribute \src "ls180.v:1117.6-1117.41" + attribute \src "ls180.v:1111.6-1111.41" wire \libresocsim_csrbank0_bus_errors3_we - attribute \src "ls180.v:1096.6-1096.35" + attribute \src "ls180.v:1090.6-1090.35" wire \libresocsim_csrbank0_reset0_r - attribute \src "ls180.v:1095.6-1095.36" + attribute \src "ls180.v:1089.6-1089.36" wire \libresocsim_csrbank0_reset0_re - attribute \src "ls180.v:1098.6-1098.35" + attribute \src "ls180.v:1092.6-1092.35" wire \libresocsim_csrbank0_reset0_w - attribute \src "ls180.v:1097.6-1097.36" + attribute \src "ls180.v:1091.6-1091.36" wire \libresocsim_csrbank0_reset0_we - attribute \src "ls180.v:1112.12-1112.43" + attribute \src "ls180.v:1106.12-1106.43" wire width 8 \libresocsim_csrbank0_scratch0_r - attribute \src "ls180.v:1111.6-1111.38" + attribute \src "ls180.v:1105.6-1105.38" wire \libresocsim_csrbank0_scratch0_re - attribute \src "ls180.v:1114.12-1114.43" + attribute \src "ls180.v:1108.12-1108.43" wire width 8 \libresocsim_csrbank0_scratch0_w - attribute \src "ls180.v:1113.6-1113.38" + attribute \src "ls180.v:1107.6-1107.38" wire \libresocsim_csrbank0_scratch0_we - attribute \src "ls180.v:1108.12-1108.43" + attribute \src "ls180.v:1102.12-1102.43" wire width 8 \libresocsim_csrbank0_scratch1_r - attribute \src "ls180.v:1107.6-1107.38" + attribute \src "ls180.v:1101.6-1101.38" wire \libresocsim_csrbank0_scratch1_re - attribute \src "ls180.v:1110.12-1110.43" + attribute \src "ls180.v:1104.12-1104.43" wire width 8 \libresocsim_csrbank0_scratch1_w - attribute \src "ls180.v:1109.6-1109.38" + attribute \src "ls180.v:1103.6-1103.38" wire \libresocsim_csrbank0_scratch1_we - attribute \src "ls180.v:1104.12-1104.43" + attribute \src "ls180.v:1098.12-1098.43" wire width 8 \libresocsim_csrbank0_scratch2_r - attribute \src "ls180.v:1103.6-1103.38" + attribute \src "ls180.v:1097.6-1097.38" wire \libresocsim_csrbank0_scratch2_re - attribute \src "ls180.v:1106.12-1106.43" + attribute \src "ls180.v:1100.12-1100.43" wire width 8 \libresocsim_csrbank0_scratch2_w - attribute \src "ls180.v:1105.6-1105.38" + attribute \src "ls180.v:1099.6-1099.38" wire \libresocsim_csrbank0_scratch2_we - attribute \src "ls180.v:1100.12-1100.43" + attribute \src "ls180.v:1094.12-1094.43" wire width 8 \libresocsim_csrbank0_scratch3_r - attribute \src "ls180.v:1099.6-1099.38" + attribute \src "ls180.v:1093.6-1093.38" wire \libresocsim_csrbank0_scratch3_re - attribute \src "ls180.v:1102.12-1102.43" + attribute \src "ls180.v:1096.12-1096.43" wire width 8 \libresocsim_csrbank0_scratch3_w - attribute \src "ls180.v:1101.6-1101.38" + attribute \src "ls180.v:1095.6-1095.38" wire \libresocsim_csrbank0_scratch3_we - attribute \src "ls180.v:1131.6-1131.30" + attribute \src "ls180.v:1125.6-1125.30" wire \libresocsim_csrbank0_sel - attribute \src "ls180.v:1141.12-1141.37" + attribute \src "ls180.v:1135.12-1135.37" wire width 8 \libresocsim_csrbank1_in_r - attribute \src "ls180.v:1140.6-1140.32" + attribute \src "ls180.v:1134.6-1134.32" wire \libresocsim_csrbank1_in_re - attribute \src "ls180.v:1143.12-1143.37" + attribute \src "ls180.v:1137.12-1137.37" wire width 8 \libresocsim_csrbank1_in_w - attribute \src "ls180.v:1142.6-1142.32" + attribute \src "ls180.v:1136.6-1136.32" wire \libresocsim_csrbank1_in_we - attribute \src "ls180.v:1137.12-1137.38" + attribute \src "ls180.v:1131.12-1131.38" wire width 8 \libresocsim_csrbank1_oe0_r - attribute \src "ls180.v:1136.6-1136.33" + attribute \src "ls180.v:1130.6-1130.33" wire \libresocsim_csrbank1_oe0_re - attribute \src "ls180.v:1139.12-1139.38" + attribute \src "ls180.v:1133.12-1133.38" wire width 8 \libresocsim_csrbank1_oe0_w - attribute \src "ls180.v:1138.6-1138.33" + attribute \src "ls180.v:1132.6-1132.33" wire \libresocsim_csrbank1_oe0_we - attribute \src "ls180.v:1145.12-1145.39" + attribute \src "ls180.v:1139.12-1139.39" wire width 8 \libresocsim_csrbank1_out0_r - attribute \src "ls180.v:1144.6-1144.34" + attribute \src "ls180.v:1138.6-1138.34" wire \libresocsim_csrbank1_out0_re - attribute \src "ls180.v:1147.12-1147.39" + attribute \src "ls180.v:1141.12-1141.39" wire width 8 \libresocsim_csrbank1_out0_w - attribute \src "ls180.v:1146.6-1146.34" + attribute \src "ls180.v:1140.6-1140.34" wire \libresocsim_csrbank1_out0_we - attribute \src "ls180.v:1148.6-1148.30" + attribute \src "ls180.v:1142.6-1142.30" wire \libresocsim_csrbank1_sel - attribute \src "ls180.v:1158.12-1158.37" + attribute \src "ls180.v:1152.12-1152.37" wire width 8 \libresocsim_csrbank2_in_r - attribute \src "ls180.v:1157.6-1157.32" + attribute \src "ls180.v:1151.6-1151.32" wire \libresocsim_csrbank2_in_re - attribute \src "ls180.v:1160.12-1160.37" + attribute \src "ls180.v:1154.12-1154.37" wire width 8 \libresocsim_csrbank2_in_w - attribute \src "ls180.v:1159.6-1159.32" + attribute \src "ls180.v:1153.6-1153.32" wire \libresocsim_csrbank2_in_we - attribute \src "ls180.v:1154.12-1154.38" + attribute \src "ls180.v:1148.12-1148.38" wire width 8 \libresocsim_csrbank2_oe0_r - attribute \src "ls180.v:1153.6-1153.33" + attribute \src "ls180.v:1147.6-1147.33" wire \libresocsim_csrbank2_oe0_re - attribute \src "ls180.v:1156.12-1156.38" + attribute \src "ls180.v:1150.12-1150.38" wire width 8 \libresocsim_csrbank2_oe0_w - attribute \src "ls180.v:1155.6-1155.33" + attribute \src "ls180.v:1149.6-1149.33" wire \libresocsim_csrbank2_oe0_we - attribute \src "ls180.v:1162.12-1162.39" + attribute \src "ls180.v:1156.12-1156.39" wire width 8 \libresocsim_csrbank2_out0_r - attribute \src "ls180.v:1161.6-1161.34" + attribute \src "ls180.v:1155.6-1155.34" wire \libresocsim_csrbank2_out0_re - attribute \src "ls180.v:1164.12-1164.39" + attribute \src "ls180.v:1158.12-1158.39" wire width 8 \libresocsim_csrbank2_out0_w - attribute \src "ls180.v:1163.6-1163.34" + attribute \src "ls180.v:1157.6-1157.34" wire \libresocsim_csrbank2_out0_we - attribute \src "ls180.v:1165.6-1165.30" + attribute \src "ls180.v:1159.6-1159.30" wire \libresocsim_csrbank2_sel - attribute \src "ls180.v:1175.6-1175.30" + attribute \src "ls180.v:1169.6-1169.30" wire \libresocsim_csrbank3_r_r - attribute \src "ls180.v:1174.6-1174.31" + attribute \src "ls180.v:1168.6-1168.31" wire \libresocsim_csrbank3_r_re - attribute \src "ls180.v:1177.6-1177.30" + attribute \src "ls180.v:1171.6-1171.30" wire \libresocsim_csrbank3_r_w - attribute \src "ls180.v:1176.6-1176.31" + attribute \src "ls180.v:1170.6-1170.31" wire \libresocsim_csrbank3_r_we - attribute \src "ls180.v:1178.6-1178.30" + attribute \src "ls180.v:1172.6-1172.30" wire \libresocsim_csrbank3_sel - attribute \src "ls180.v:1171.12-1171.37" + attribute \src "ls180.v:1165.12-1165.37" wire width 3 \libresocsim_csrbank3_w0_r - attribute \src "ls180.v:1170.6-1170.32" + attribute \src "ls180.v:1164.6-1164.32" wire \libresocsim_csrbank3_w0_re - attribute \src "ls180.v:1173.12-1173.37" + attribute \src "ls180.v:1167.12-1167.37" wire width 3 \libresocsim_csrbank3_w0_w - attribute \src "ls180.v:1172.6-1172.32" + attribute \src "ls180.v:1166.6-1166.32" wire \libresocsim_csrbank3_w0_we - attribute \src "ls180.v:1184.12-1184.48" + attribute \src "ls180.v:1178.12-1178.48" wire width 4 \libresocsim_csrbank4_dfii_control0_r - attribute \src "ls180.v:1183.6-1183.43" + attribute \src "ls180.v:1177.6-1177.43" wire \libresocsim_csrbank4_dfii_control0_re - attribute \src "ls180.v:1186.12-1186.48" + attribute \src "ls180.v:1180.12-1180.48" wire width 4 \libresocsim_csrbank4_dfii_control0_w - attribute \src "ls180.v:1185.6-1185.43" + attribute \src "ls180.v:1179.6-1179.43" wire \libresocsim_csrbank4_dfii_control0_we - attribute \src "ls180.v:1196.12-1196.52" + attribute \src "ls180.v:1190.12-1190.52" wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_r - attribute \src "ls180.v:1195.6-1195.47" + attribute \src "ls180.v:1189.6-1189.47" wire \libresocsim_csrbank4_dfii_pi0_address0_re - attribute \src "ls180.v:1198.12-1198.52" + attribute \src "ls180.v:1192.12-1192.52" wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_w - attribute \src "ls180.v:1197.6-1197.47" + attribute \src "ls180.v:1191.6-1191.47" wire \libresocsim_csrbank4_dfii_pi0_address0_we - attribute \src "ls180.v:1192.12-1192.52" + attribute \src "ls180.v:1186.12-1186.52" wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_r - attribute \src "ls180.v:1191.6-1191.47" + attribute \src "ls180.v:1185.6-1185.47" wire \libresocsim_csrbank4_dfii_pi0_address1_re - attribute \src "ls180.v:1194.12-1194.52" + attribute \src "ls180.v:1188.12-1188.52" wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_w - attribute \src "ls180.v:1193.6-1193.47" + attribute \src "ls180.v:1187.6-1187.47" wire \libresocsim_csrbank4_dfii_pi0_address1_we - attribute \src "ls180.v:1200.12-1200.53" + attribute \src "ls180.v:1194.12-1194.53" wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_r - attribute \src "ls180.v:1199.6-1199.48" + attribute \src "ls180.v:1193.6-1193.48" wire \libresocsim_csrbank4_dfii_pi0_baddress0_re - attribute \src "ls180.v:1202.12-1202.53" + attribute \src "ls180.v:1196.12-1196.53" wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_w - attribute \src "ls180.v:1201.6-1201.48" + attribute \src "ls180.v:1195.6-1195.48" wire \libresocsim_csrbank4_dfii_pi0_baddress0_we - attribute \src "ls180.v:1188.12-1188.52" + attribute \src "ls180.v:1182.12-1182.52" wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_r - attribute \src "ls180.v:1187.6-1187.47" + attribute \src "ls180.v:1181.6-1181.47" wire \libresocsim_csrbank4_dfii_pi0_command0_re - attribute \src "ls180.v:1190.12-1190.52" + attribute \src "ls180.v:1184.12-1184.52" wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_w - attribute \src "ls180.v:1189.6-1189.47" + attribute \src "ls180.v:1183.6-1183.47" wire \libresocsim_csrbank4_dfii_pi0_command0_we - attribute \src "ls180.v:1216.12-1216.51" + attribute \src "ls180.v:1210.12-1210.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_r - attribute \src "ls180.v:1215.6-1215.46" + attribute \src "ls180.v:1209.6-1209.46" wire \libresocsim_csrbank4_dfii_pi0_rddata0_re - attribute \src "ls180.v:1218.12-1218.51" + attribute \src "ls180.v:1212.12-1212.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_w - attribute \src "ls180.v:1217.6-1217.46" + attribute \src "ls180.v:1211.6-1211.46" wire \libresocsim_csrbank4_dfii_pi0_rddata0_we - attribute \src "ls180.v:1212.12-1212.51" + attribute \src "ls180.v:1206.12-1206.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_r - attribute \src "ls180.v:1211.6-1211.46" + attribute \src "ls180.v:1205.6-1205.46" wire \libresocsim_csrbank4_dfii_pi0_rddata1_re - attribute \src "ls180.v:1214.12-1214.51" + attribute \src "ls180.v:1208.12-1208.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_w - attribute \src "ls180.v:1213.6-1213.46" + attribute \src "ls180.v:1207.6-1207.46" wire \libresocsim_csrbank4_dfii_pi0_rddata1_we - attribute \src "ls180.v:1208.12-1208.51" + attribute \src "ls180.v:1202.12-1202.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_r - attribute \src "ls180.v:1207.6-1207.46" + attribute \src "ls180.v:1201.6-1201.46" wire \libresocsim_csrbank4_dfii_pi0_wrdata0_re - attribute \src "ls180.v:1210.12-1210.51" + attribute \src "ls180.v:1204.12-1204.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_w - attribute \src "ls180.v:1209.6-1209.46" + attribute \src "ls180.v:1203.6-1203.46" wire \libresocsim_csrbank4_dfii_pi0_wrdata0_we - attribute \src "ls180.v:1204.12-1204.51" + attribute \src "ls180.v:1198.12-1198.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_r - attribute \src "ls180.v:1203.6-1203.46" + attribute \src "ls180.v:1197.6-1197.46" wire \libresocsim_csrbank4_dfii_pi0_wrdata1_re - attribute \src "ls180.v:1206.12-1206.51" + attribute \src "ls180.v:1200.12-1200.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_w - attribute \src "ls180.v:1205.6-1205.46" + attribute \src "ls180.v:1199.6-1199.46" wire \libresocsim_csrbank4_dfii_pi0_wrdata1_we - attribute \src "ls180.v:1219.6-1219.30" + attribute \src "ls180.v:1213.6-1213.30" wire \libresocsim_csrbank4_sel - attribute \src "ls180.v:1257.6-1257.32" + attribute \src "ls180.v:1251.6-1251.32" wire \libresocsim_csrbank5_en0_r - attribute \src "ls180.v:1256.6-1256.33" + attribute \src "ls180.v:1250.6-1250.33" wire \libresocsim_csrbank5_en0_re - attribute \src "ls180.v:1259.6-1259.32" + attribute \src "ls180.v:1253.6-1253.32" wire \libresocsim_csrbank5_en0_w - attribute \src "ls180.v:1258.6-1258.33" + attribute \src "ls180.v:1252.6-1252.33" wire \libresocsim_csrbank5_en0_we - attribute \src "ls180.v:1281.6-1281.39" + attribute \src "ls180.v:1275.6-1275.39" wire \libresocsim_csrbank5_ev_enable0_r - attribute \src "ls180.v:1280.6-1280.40" + attribute \src "ls180.v:1274.6-1274.40" wire \libresocsim_csrbank5_ev_enable0_re - attribute \src "ls180.v:1283.6-1283.39" + attribute \src "ls180.v:1277.6-1277.39" wire \libresocsim_csrbank5_ev_enable0_w - attribute \src "ls180.v:1282.6-1282.40" + attribute \src "ls180.v:1276.6-1276.40" wire \libresocsim_csrbank5_ev_enable0_we - attribute \src "ls180.v:1237.12-1237.40" + attribute \src "ls180.v:1231.12-1231.40" wire width 8 \libresocsim_csrbank5_load0_r - attribute \src "ls180.v:1236.6-1236.35" + attribute \src "ls180.v:1230.6-1230.35" wire \libresocsim_csrbank5_load0_re - attribute \src "ls180.v:1239.12-1239.40" + attribute \src "ls180.v:1233.12-1233.40" wire width 8 \libresocsim_csrbank5_load0_w - attribute \src "ls180.v:1238.6-1238.35" + attribute \src "ls180.v:1232.6-1232.35" wire \libresocsim_csrbank5_load0_we - attribute \src "ls180.v:1233.12-1233.40" + attribute \src "ls180.v:1227.12-1227.40" wire width 8 \libresocsim_csrbank5_load1_r - attribute \src "ls180.v:1232.6-1232.35" + attribute \src "ls180.v:1226.6-1226.35" wire \libresocsim_csrbank5_load1_re - attribute \src "ls180.v:1235.12-1235.40" + attribute \src "ls180.v:1229.12-1229.40" wire width 8 \libresocsim_csrbank5_load1_w - attribute \src "ls180.v:1234.6-1234.35" + attribute \src "ls180.v:1228.6-1228.35" wire \libresocsim_csrbank5_load1_we - attribute \src "ls180.v:1229.12-1229.40" + attribute \src "ls180.v:1223.12-1223.40" wire width 8 \libresocsim_csrbank5_load2_r - attribute \src "ls180.v:1228.6-1228.35" + attribute \src "ls180.v:1222.6-1222.35" wire \libresocsim_csrbank5_load2_re - attribute \src "ls180.v:1231.12-1231.40" + attribute \src "ls180.v:1225.12-1225.40" wire width 8 \libresocsim_csrbank5_load2_w - attribute \src "ls180.v:1230.6-1230.35" + attribute \src "ls180.v:1224.6-1224.35" wire \libresocsim_csrbank5_load2_we - attribute \src "ls180.v:1225.12-1225.40" + attribute \src "ls180.v:1219.12-1219.40" wire width 8 \libresocsim_csrbank5_load3_r - attribute \src "ls180.v:1224.6-1224.35" + attribute \src "ls180.v:1218.6-1218.35" wire \libresocsim_csrbank5_load3_re - attribute \src "ls180.v:1227.12-1227.40" + attribute \src "ls180.v:1221.12-1221.40" wire width 8 \libresocsim_csrbank5_load3_w - attribute \src "ls180.v:1226.6-1226.35" + attribute \src "ls180.v:1220.6-1220.35" wire \libresocsim_csrbank5_load3_we - attribute \src "ls180.v:1253.12-1253.42" + attribute \src "ls180.v:1247.12-1247.42" wire width 8 \libresocsim_csrbank5_reload0_r - attribute \src "ls180.v:1252.6-1252.37" + attribute \src "ls180.v:1246.6-1246.37" wire \libresocsim_csrbank5_reload0_re - attribute \src "ls180.v:1255.12-1255.42" + attribute \src "ls180.v:1249.12-1249.42" wire width 8 \libresocsim_csrbank5_reload0_w - attribute \src "ls180.v:1254.6-1254.37" + attribute \src "ls180.v:1248.6-1248.37" wire \libresocsim_csrbank5_reload0_we - attribute \src "ls180.v:1249.12-1249.42" + attribute \src "ls180.v:1243.12-1243.42" wire width 8 \libresocsim_csrbank5_reload1_r - attribute \src "ls180.v:1248.6-1248.37" + attribute \src "ls180.v:1242.6-1242.37" wire \libresocsim_csrbank5_reload1_re - attribute \src "ls180.v:1251.12-1251.42" + attribute \src "ls180.v:1245.12-1245.42" wire width 8 \libresocsim_csrbank5_reload1_w - attribute \src "ls180.v:1250.6-1250.37" + attribute \src "ls180.v:1244.6-1244.37" wire \libresocsim_csrbank5_reload1_we - attribute \src "ls180.v:1245.12-1245.42" + attribute \src "ls180.v:1239.12-1239.42" wire width 8 \libresocsim_csrbank5_reload2_r - attribute \src "ls180.v:1244.6-1244.37" + attribute \src "ls180.v:1238.6-1238.37" wire \libresocsim_csrbank5_reload2_re - attribute \src "ls180.v:1247.12-1247.42" + attribute \src "ls180.v:1241.12-1241.42" wire width 8 \libresocsim_csrbank5_reload2_w - attribute \src "ls180.v:1246.6-1246.37" + attribute \src "ls180.v:1240.6-1240.37" wire \libresocsim_csrbank5_reload2_we - attribute \src "ls180.v:1241.12-1241.42" + attribute \src "ls180.v:1235.12-1235.42" wire width 8 \libresocsim_csrbank5_reload3_r - attribute \src "ls180.v:1240.6-1240.37" + attribute \src "ls180.v:1234.6-1234.37" wire \libresocsim_csrbank5_reload3_re - attribute \src "ls180.v:1243.12-1243.42" + attribute \src "ls180.v:1237.12-1237.42" wire width 8 \libresocsim_csrbank5_reload3_w - attribute \src "ls180.v:1242.6-1242.37" + attribute \src "ls180.v:1236.6-1236.37" wire \libresocsim_csrbank5_reload3_we - attribute \src "ls180.v:1284.6-1284.30" + attribute \src "ls180.v:1278.6-1278.30" wire \libresocsim_csrbank5_sel - attribute \src "ls180.v:1261.6-1261.42" + attribute \src "ls180.v:1255.6-1255.42" wire \libresocsim_csrbank5_update_value0_r - attribute \src "ls180.v:1260.6-1260.43" + attribute \src "ls180.v:1254.6-1254.43" wire \libresocsim_csrbank5_update_value0_re - attribute \src "ls180.v:1263.6-1263.42" + attribute \src "ls180.v:1257.6-1257.42" wire \libresocsim_csrbank5_update_value0_w - attribute \src "ls180.v:1262.6-1262.43" + attribute \src "ls180.v:1256.6-1256.43" wire \libresocsim_csrbank5_update_value0_we - attribute \src "ls180.v:1277.12-1277.41" + attribute \src "ls180.v:1271.12-1271.41" wire width 8 \libresocsim_csrbank5_value0_r - attribute \src "ls180.v:1276.6-1276.36" + attribute \src "ls180.v:1270.6-1270.36" wire \libresocsim_csrbank5_value0_re - attribute \src "ls180.v:1279.12-1279.41" + attribute \src "ls180.v:1273.12-1273.41" wire width 8 \libresocsim_csrbank5_value0_w - attribute \src "ls180.v:1278.6-1278.36" + attribute \src "ls180.v:1272.6-1272.36" wire \libresocsim_csrbank5_value0_we - attribute \src "ls180.v:1273.12-1273.41" + attribute \src "ls180.v:1267.12-1267.41" wire width 8 \libresocsim_csrbank5_value1_r - attribute \src "ls180.v:1272.6-1272.36" + attribute \src "ls180.v:1266.6-1266.36" wire \libresocsim_csrbank5_value1_re - attribute \src "ls180.v:1275.12-1275.41" + attribute \src "ls180.v:1269.12-1269.41" wire width 8 \libresocsim_csrbank5_value1_w - attribute \src "ls180.v:1274.6-1274.36" + attribute \src "ls180.v:1268.6-1268.36" wire \libresocsim_csrbank5_value1_we - attribute \src "ls180.v:1269.12-1269.41" + attribute \src "ls180.v:1263.12-1263.41" wire width 8 \libresocsim_csrbank5_value2_r - attribute \src "ls180.v:1268.6-1268.36" + attribute \src "ls180.v:1262.6-1262.36" wire \libresocsim_csrbank5_value2_re - attribute \src "ls180.v:1271.12-1271.41" + attribute \src "ls180.v:1265.12-1265.41" wire width 8 \libresocsim_csrbank5_value2_w - attribute \src "ls180.v:1270.6-1270.36" + attribute \src "ls180.v:1264.6-1264.36" wire \libresocsim_csrbank5_value2_we - attribute \src "ls180.v:1265.12-1265.41" + attribute \src "ls180.v:1259.12-1259.41" wire width 8 \libresocsim_csrbank5_value3_r - attribute \src "ls180.v:1264.6-1264.36" + attribute \src "ls180.v:1258.6-1258.36" wire \libresocsim_csrbank5_value3_re - attribute \src "ls180.v:1267.12-1267.41" + attribute \src "ls180.v:1261.12-1261.41" wire width 8 \libresocsim_csrbank5_value3_w - attribute \src "ls180.v:1266.6-1266.36" + attribute \src "ls180.v:1260.6-1260.36" wire \libresocsim_csrbank5_value3_we - attribute \src "ls180.v:1298.12-1298.45" + attribute \src "ls180.v:1292.12-1292.45" wire width 2 \libresocsim_csrbank6_ev_enable0_r - attribute \src "ls180.v:1297.6-1297.40" + attribute \src "ls180.v:1291.6-1291.40" wire \libresocsim_csrbank6_ev_enable0_re - attribute \src "ls180.v:1300.12-1300.45" + attribute \src "ls180.v:1294.12-1294.45" wire width 2 \libresocsim_csrbank6_ev_enable0_w - attribute \src "ls180.v:1299.6-1299.40" + attribute \src "ls180.v:1293.6-1293.40" wire \libresocsim_csrbank6_ev_enable0_we - attribute \src "ls180.v:1294.6-1294.36" + attribute \src "ls180.v:1288.6-1288.36" wire \libresocsim_csrbank6_rxempty_r - attribute \src "ls180.v:1293.6-1293.37" + attribute \src "ls180.v:1287.6-1287.37" wire \libresocsim_csrbank6_rxempty_re - attribute \src "ls180.v:1296.6-1296.36" + attribute \src "ls180.v:1290.6-1290.36" wire \libresocsim_csrbank6_rxempty_w - attribute \src "ls180.v:1295.6-1295.37" + attribute \src "ls180.v:1289.6-1289.37" wire \libresocsim_csrbank6_rxempty_we - attribute \src "ls180.v:1306.6-1306.35" + attribute \src "ls180.v:1300.6-1300.35" wire \libresocsim_csrbank6_rxfull_r - attribute \src "ls180.v:1305.6-1305.36" + attribute \src "ls180.v:1299.6-1299.36" wire \libresocsim_csrbank6_rxfull_re - attribute \src "ls180.v:1308.6-1308.35" + attribute \src "ls180.v:1302.6-1302.35" wire \libresocsim_csrbank6_rxfull_w - attribute \src "ls180.v:1307.6-1307.36" + attribute \src "ls180.v:1301.6-1301.36" wire \libresocsim_csrbank6_rxfull_we - attribute \src "ls180.v:1309.6-1309.30" + attribute \src "ls180.v:1303.6-1303.30" wire \libresocsim_csrbank6_sel - attribute \src "ls180.v:1302.6-1302.36" + attribute \src "ls180.v:1296.6-1296.36" wire \libresocsim_csrbank6_txempty_r - attribute \src "ls180.v:1301.6-1301.37" + attribute \src "ls180.v:1295.6-1295.37" wire \libresocsim_csrbank6_txempty_re - attribute \src "ls180.v:1304.6-1304.36" + attribute \src "ls180.v:1298.6-1298.36" wire \libresocsim_csrbank6_txempty_w - attribute \src "ls180.v:1303.6-1303.37" + attribute \src "ls180.v:1297.6-1297.37" wire \libresocsim_csrbank6_txempty_we - attribute \src "ls180.v:1290.6-1290.35" + attribute \src "ls180.v:1284.6-1284.35" wire \libresocsim_csrbank6_txfull_r - attribute \src "ls180.v:1289.6-1289.36" + attribute \src "ls180.v:1283.6-1283.36" wire \libresocsim_csrbank6_txfull_re - attribute \src "ls180.v:1292.6-1292.35" + attribute \src "ls180.v:1286.6-1286.35" wire \libresocsim_csrbank6_txfull_w - attribute \src "ls180.v:1291.6-1291.36" + attribute \src "ls180.v:1285.6-1285.36" wire \libresocsim_csrbank6_txfull_we - attribute \src "ls180.v:1330.6-1330.30" + attribute \src "ls180.v:1324.6-1324.30" wire \libresocsim_csrbank7_sel - attribute \src "ls180.v:1327.12-1327.47" + attribute \src "ls180.v:1321.12-1321.47" wire width 8 \libresocsim_csrbank7_tuning_word0_r - attribute \src "ls180.v:1326.6-1326.42" + attribute \src "ls180.v:1320.6-1320.42" wire \libresocsim_csrbank7_tuning_word0_re - attribute \src "ls180.v:1329.12-1329.47" + attribute \src "ls180.v:1323.12-1323.47" wire width 8 \libresocsim_csrbank7_tuning_word0_w - attribute \src "ls180.v:1328.6-1328.42" + attribute \src "ls180.v:1322.6-1322.42" wire \libresocsim_csrbank7_tuning_word0_we - attribute \src "ls180.v:1323.12-1323.47" + attribute \src "ls180.v:1317.12-1317.47" wire width 8 \libresocsim_csrbank7_tuning_word1_r - attribute \src "ls180.v:1322.6-1322.42" + attribute \src "ls180.v:1316.6-1316.42" wire \libresocsim_csrbank7_tuning_word1_re - attribute \src "ls180.v:1325.12-1325.47" + attribute \src "ls180.v:1319.12-1319.47" wire width 8 \libresocsim_csrbank7_tuning_word1_w - attribute \src "ls180.v:1324.6-1324.42" + attribute \src "ls180.v:1318.6-1318.42" wire \libresocsim_csrbank7_tuning_word1_we - attribute \src "ls180.v:1319.12-1319.47" + attribute \src "ls180.v:1313.12-1313.47" wire width 8 \libresocsim_csrbank7_tuning_word2_r - attribute \src "ls180.v:1318.6-1318.42" + attribute \src "ls180.v:1312.6-1312.42" wire \libresocsim_csrbank7_tuning_word2_re - attribute \src "ls180.v:1321.12-1321.47" + attribute \src "ls180.v:1315.12-1315.47" wire width 8 \libresocsim_csrbank7_tuning_word2_w - attribute \src "ls180.v:1320.6-1320.42" + attribute \src "ls180.v:1314.6-1314.42" wire \libresocsim_csrbank7_tuning_word2_we - attribute \src "ls180.v:1315.12-1315.47" + attribute \src "ls180.v:1309.12-1309.47" wire width 8 \libresocsim_csrbank7_tuning_word3_r - attribute \src "ls180.v:1314.6-1314.42" + attribute \src "ls180.v:1308.6-1308.42" wire \libresocsim_csrbank7_tuning_word3_re - attribute \src "ls180.v:1317.12-1317.47" + attribute \src "ls180.v:1311.12-1311.47" wire width 8 \libresocsim_csrbank7_tuning_word3_w - attribute \src "ls180.v:1316.6-1316.42" + attribute \src "ls180.v:1310.6-1310.42" wire \libresocsim_csrbank7_tuning_word3_we - attribute \src "ls180.v:200.13-200.30" + attribute \src "ls180.v:194.13-194.30" wire width 32 \libresocsim_dat_r - attribute \src "ls180.v:202.13-202.30" + attribute \src "ls180.v:196.13-196.30" wire width 32 \libresocsim_dat_w - attribute \src "ls180.v:1089.6-1089.22" + attribute \src "ls180.v:1083.6-1083.22" wire \libresocsim_done - attribute \src "ls180.v:208.5-208.22" + attribute \src "ls180.v:202.5-202.22" wire \libresocsim_en_re - attribute \src "ls180.v:207.5-207.27" + attribute \src "ls180.v:201.5-201.27" wire \libresocsim_en_storage - attribute \src "ls180.v:1087.5-1087.22" + attribute \src "ls180.v:1081.5-1081.22" wire \libresocsim_error - attribute \src "ls180.v:224.6-224.40" + attribute \src "ls180.v:218.6-218.40" wire \libresocsim_eventmanager_pending_r - attribute \src "ls180.v:223.6-223.41" + attribute \src "ls180.v:217.6-217.41" wire \libresocsim_eventmanager_pending_re - attribute \src "ls180.v:226.6-226.40" + attribute \src "ls180.v:220.6-220.40" wire \libresocsim_eventmanager_pending_w - attribute \src "ls180.v:225.6-225.41" + attribute \src "ls180.v:219.6-219.41" wire \libresocsim_eventmanager_pending_we - attribute \src "ls180.v:228.5-228.32" + attribute \src "ls180.v:222.5-222.32" wire \libresocsim_eventmanager_re - attribute \src "ls180.v:220.6-220.39" + attribute \src "ls180.v:214.6-214.39" wire \libresocsim_eventmanager_status_r - attribute \src "ls180.v:219.6-219.40" + attribute \src "ls180.v:213.6-213.40" wire \libresocsim_eventmanager_status_re - attribute \src "ls180.v:222.6-222.39" + attribute \src "ls180.v:216.6-216.39" wire \libresocsim_eventmanager_status_w - attribute \src "ls180.v:221.6-221.40" + attribute \src "ls180.v:215.6-215.40" wire \libresocsim_eventmanager_status_we - attribute \src "ls180.v:227.5-227.37" + attribute \src "ls180.v:221.5-221.37" wire \libresocsim_eventmanager_storage - attribute \src "ls180.v:1084.11-1084.28" + attribute \src "ls180.v:1078.11-1078.28" wire width 2 \libresocsim_grant - attribute \src "ls180.v:1091.13-1091.48" + attribute \src "ls180.v:1085.13-1085.48" wire width 14 \libresocsim_interface0_bank_bus_adr - attribute \src "ls180.v:1094.11-1094.48" + attribute \src "ls180.v:1088.11-1088.48" wire width 8 \libresocsim_interface0_bank_bus_dat_r - attribute \src "ls180.v:1093.12-1093.49" + attribute \src "ls180.v:1087.12-1087.49" wire width 8 \libresocsim_interface0_bank_bus_dat_w - attribute \src "ls180.v:1092.6-1092.40" + attribute \src "ls180.v:1086.6-1086.40" wire \libresocsim_interface0_bank_bus_we - attribute \src "ls180.v:149.6-149.52" + attribute \src "ls180.v:143.6-143.52" wire \libresocsim_interface0_converted_interface_ack - attribute \src "ls180.v:143.12-143.58" + attribute \src "ls180.v:137.12-137.58" wire width 30 \libresocsim_interface0_converted_interface_adr - attribute \src "ls180.v:152.11-152.57" + attribute \src "ls180.v:146.11-146.57" wire width 2 \libresocsim_interface0_converted_interface_bte - attribute \src "ls180.v:151.11-151.57" + attribute \src "ls180.v:145.11-145.57" wire width 3 \libresocsim_interface0_converted_interface_cti - attribute \src "ls180.v:147.5-147.51" + attribute \src "ls180.v:141.5-141.51" wire \libresocsim_interface0_converted_interface_cyc - attribute \src "ls180.v:145.13-145.61" + attribute \src "ls180.v:139.13-139.61" wire width 32 \libresocsim_interface0_converted_interface_dat_r - attribute \src "ls180.v:144.12-144.60" + attribute \src "ls180.v:138.12-138.60" wire width 32 \libresocsim_interface0_converted_interface_dat_w - attribute \src "ls180.v:153.6-153.52" + attribute \src "ls180.v:147.6-147.52" wire \libresocsim_interface0_converted_interface_err - attribute \src "ls180.v:146.11-146.57" + attribute \src "ls180.v:140.11-140.57" wire width 4 \libresocsim_interface0_converted_interface_sel - attribute \src "ls180.v:148.5-148.51" + attribute \src "ls180.v:142.5-142.51" wire \libresocsim_interface0_converted_interface_stb - attribute \src "ls180.v:150.5-150.50" + attribute \src "ls180.v:144.5-144.50" wire \libresocsim_interface0_converted_interface_we - attribute \src "ls180.v:1132.13-1132.48" + attribute \src "ls180.v:1126.13-1126.48" wire width 14 \libresocsim_interface1_bank_bus_adr - attribute \src "ls180.v:1135.11-1135.48" + attribute \src "ls180.v:1129.11-1129.48" wire width 8 \libresocsim_interface1_bank_bus_dat_r - attribute \src "ls180.v:1134.12-1134.49" + attribute \src "ls180.v:1128.12-1128.49" wire width 8 \libresocsim_interface1_bank_bus_dat_w - attribute \src "ls180.v:1133.6-1133.40" + attribute \src "ls180.v:1127.6-1127.40" wire \libresocsim_interface1_bank_bus_we - attribute \src "ls180.v:164.6-164.52" + attribute \src "ls180.v:158.6-158.52" wire \libresocsim_interface1_converted_interface_ack - attribute \src "ls180.v:158.12-158.58" + attribute \src "ls180.v:152.12-152.58" wire width 30 \libresocsim_interface1_converted_interface_adr - attribute \src "ls180.v:167.11-167.57" + attribute \src "ls180.v:161.11-161.57" wire width 2 \libresocsim_interface1_converted_interface_bte - attribute \src "ls180.v:166.11-166.57" + attribute \src "ls180.v:160.11-160.57" wire width 3 \libresocsim_interface1_converted_interface_cti - attribute \src "ls180.v:162.5-162.51" + attribute \src "ls180.v:156.5-156.51" wire \libresocsim_interface1_converted_interface_cyc - attribute \src "ls180.v:160.13-160.61" + attribute \src "ls180.v:154.13-154.61" wire width 32 \libresocsim_interface1_converted_interface_dat_r - attribute \src "ls180.v:159.12-159.60" + attribute \src "ls180.v:153.12-153.60" wire width 32 \libresocsim_interface1_converted_interface_dat_w - attribute \src "ls180.v:168.6-168.52" + attribute \src "ls180.v:162.6-162.52" wire \libresocsim_interface1_converted_interface_err - attribute \src "ls180.v:161.11-161.57" + attribute \src "ls180.v:155.11-155.57" wire width 4 \libresocsim_interface1_converted_interface_sel - attribute \src "ls180.v:163.5-163.51" + attribute \src "ls180.v:157.5-157.51" wire \libresocsim_interface1_converted_interface_stb - attribute \src "ls180.v:165.5-165.50" + attribute \src "ls180.v:159.5-159.50" wire \libresocsim_interface1_converted_interface_we - attribute \src "ls180.v:1149.13-1149.48" + attribute \src "ls180.v:1143.13-1143.48" wire width 14 \libresocsim_interface2_bank_bus_adr - attribute \src "ls180.v:1152.11-1152.48" + attribute \src "ls180.v:1146.11-1146.48" wire width 8 \libresocsim_interface2_bank_bus_dat_r - attribute \src "ls180.v:1151.12-1151.49" + attribute \src "ls180.v:1145.12-1145.49" wire width 8 \libresocsim_interface2_bank_bus_dat_w - attribute \src "ls180.v:1150.6-1150.40" + attribute \src "ls180.v:1144.6-1144.40" wire \libresocsim_interface2_bank_bus_we - attribute \src "ls180.v:179.6-179.52" + attribute \src "ls180.v:173.6-173.52" wire \libresocsim_interface2_converted_interface_ack - attribute \src "ls180.v:173.12-173.58" + attribute \src "ls180.v:167.12-167.58" wire width 30 \libresocsim_interface2_converted_interface_adr - attribute \src "ls180.v:182.11-182.57" + attribute \src "ls180.v:176.11-176.57" wire width 2 \libresocsim_interface2_converted_interface_bte - attribute \src "ls180.v:181.11-181.57" + attribute \src "ls180.v:175.11-175.57" wire width 3 \libresocsim_interface2_converted_interface_cti - attribute \src "ls180.v:177.5-177.51" + attribute \src "ls180.v:171.5-171.51" wire \libresocsim_interface2_converted_interface_cyc - attribute \src "ls180.v:175.13-175.61" + attribute \src "ls180.v:169.13-169.61" wire width 32 \libresocsim_interface2_converted_interface_dat_r - attribute \src "ls180.v:174.12-174.60" + attribute \src "ls180.v:168.12-168.60" wire width 32 \libresocsim_interface2_converted_interface_dat_w - attribute \src "ls180.v:183.6-183.52" + attribute \src "ls180.v:177.6-177.52" wire \libresocsim_interface2_converted_interface_err - attribute \src "ls180.v:176.11-176.57" + attribute \src "ls180.v:170.11-170.57" wire width 4 \libresocsim_interface2_converted_interface_sel - attribute \src "ls180.v:178.5-178.51" + attribute \src "ls180.v:172.5-172.51" wire \libresocsim_interface2_converted_interface_stb - attribute \src "ls180.v:180.5-180.50" + attribute \src "ls180.v:174.5-174.50" wire \libresocsim_interface2_converted_interface_we - attribute \src "ls180.v:1166.13-1166.48" + attribute \src "ls180.v:1160.13-1160.48" wire width 14 \libresocsim_interface3_bank_bus_adr - attribute \src "ls180.v:1169.11-1169.48" + attribute \src "ls180.v:1163.11-1163.48" wire width 8 \libresocsim_interface3_bank_bus_dat_r - attribute \src "ls180.v:1168.12-1168.49" + attribute \src "ls180.v:1162.12-1162.49" wire width 8 \libresocsim_interface3_bank_bus_dat_w - attribute \src "ls180.v:1167.6-1167.40" + attribute \src "ls180.v:1161.6-1161.40" wire \libresocsim_interface3_bank_bus_we - attribute \src "ls180.v:1179.13-1179.48" + attribute \src "ls180.v:1173.13-1173.48" wire width 14 \libresocsim_interface4_bank_bus_adr - attribute \src "ls180.v:1182.11-1182.48" + attribute \src "ls180.v:1176.11-1176.48" wire width 8 \libresocsim_interface4_bank_bus_dat_r - attribute \src "ls180.v:1181.12-1181.49" + attribute \src "ls180.v:1175.12-1175.49" wire width 8 \libresocsim_interface4_bank_bus_dat_w - attribute \src "ls180.v:1180.6-1180.40" + attribute \src "ls180.v:1174.6-1174.40" wire \libresocsim_interface4_bank_bus_we - attribute \src "ls180.v:1220.13-1220.48" + attribute \src "ls180.v:1214.13-1214.48" wire width 14 \libresocsim_interface5_bank_bus_adr - attribute \src "ls180.v:1223.11-1223.48" + attribute \src "ls180.v:1217.11-1217.48" wire width 8 \libresocsim_interface5_bank_bus_dat_r - attribute \src "ls180.v:1222.12-1222.49" + attribute \src "ls180.v:1216.12-1216.49" wire width 8 \libresocsim_interface5_bank_bus_dat_w - attribute \src "ls180.v:1221.6-1221.40" + attribute \src "ls180.v:1215.6-1215.40" wire \libresocsim_interface5_bank_bus_we - attribute \src "ls180.v:1285.13-1285.48" + attribute \src "ls180.v:1279.13-1279.48" wire width 14 \libresocsim_interface6_bank_bus_adr - attribute \src "ls180.v:1288.11-1288.48" + attribute \src "ls180.v:1282.11-1282.48" wire width 8 \libresocsim_interface6_bank_bus_dat_r - attribute \src "ls180.v:1287.12-1287.49" + attribute \src "ls180.v:1281.12-1281.49" wire width 8 \libresocsim_interface6_bank_bus_dat_w - attribute \src "ls180.v:1286.6-1286.40" + attribute \src "ls180.v:1280.6-1280.40" wire \libresocsim_interface6_bank_bus_we - attribute \src "ls180.v:1310.13-1310.48" + attribute \src "ls180.v:1304.13-1304.48" wire width 14 \libresocsim_interface7_bank_bus_adr - attribute \src "ls180.v:1313.11-1313.48" + attribute \src "ls180.v:1307.11-1307.48" wire width 8 \libresocsim_interface7_bank_bus_dat_r - attribute \src "ls180.v:1312.12-1312.49" + attribute \src "ls180.v:1306.12-1306.49" wire width 8 \libresocsim_interface7_bank_bus_dat_w - attribute \src "ls180.v:1311.6-1311.40" + attribute \src "ls180.v:1305.6-1305.40" wire \libresocsim_interface7_bank_bus_we - attribute \src "ls180.v:213.6-213.21" + attribute \src "ls180.v:207.6-207.21" wire \libresocsim_irq - attribute \src "ls180.v:109.6-109.27" + attribute \src "ls180.v:106.6-106.27" wire \libresocsim_libresoc0 - attribute \src "ls180.v:110.6-110.27" + attribute \src "ls180.v:107.6-107.27" wire \libresocsim_libresoc1 - attribute \src "ls180.v:111.13-111.34" + attribute \src "ls180.v:108.13-108.34" wire width 64 \libresocsim_libresoc2 - attribute \src "ls180.v:113.12-113.40" - wire width 2 \libresocsim_libresoc_clk_sel - attribute \src "ls180.v:117.6-117.51" + attribute \src "ls180.v:109.6-109.51" wire \libresocsim_libresoc_constraintmanager_eint_0 - attribute \src "ls180.v:118.6-118.51" + attribute \src "ls180.v:110.6-110.51" wire \libresocsim_libresoc_constraintmanager_eint_1 - attribute \src "ls180.v:119.6-119.51" + attribute \src "ls180.v:111.6-111.51" wire \libresocsim_libresoc_constraintmanager_eint_2 - attribute \src "ls180.v:140.13-140.58" + attribute \src "ls180.v:130.13-130.58" wire width 16 \libresocsim_libresoc_constraintmanager_gpio_i - attribute \src "ls180.v:141.12-141.57" + attribute \src "ls180.v:131.12-131.57" wire width 16 \libresocsim_libresoc_constraintmanager_gpio_o - attribute \src "ls180.v:142.12-142.58" + attribute \src "ls180.v:132.12-132.58" wire width 16 \libresocsim_libresoc_constraintmanager_gpio_oe - attribute \src "ls180.v:132.6-132.52" + attribute \src "ls180.v:112.6-112.52" wire \libresocsim_libresoc_constraintmanager_i2c_scl - attribute \src "ls180.v:133.6-133.54" + attribute \src "ls180.v:113.6-113.54" wire \libresocsim_libresoc_constraintmanager_i2c_sda_i - attribute \src "ls180.v:134.6-134.54" + attribute \src "ls180.v:114.6-114.54" wire \libresocsim_libresoc_constraintmanager_i2c_sda_o - attribute \src "ls180.v:135.6-135.55" + attribute \src "ls180.v:115.6-115.55" wire \libresocsim_libresoc_constraintmanager_i2c_sda_oe - attribute \src "ls180.v:120.12-120.58" + attribute \src "ls180.v:118.12-118.58" wire width 13 \libresocsim_libresoc_constraintmanager_sdram_a - attribute \src "ls180.v:129.11-129.58" + attribute \src "ls180.v:127.11-127.58" wire width 2 \libresocsim_libresoc_constraintmanager_sdram_ba - attribute \src "ls180.v:126.5-126.55" + attribute \src "ls180.v:124.5-124.55" wire \libresocsim_libresoc_constraintmanager_sdram_cas_n - attribute \src "ls180.v:128.5-128.53" + attribute \src "ls180.v:126.5-126.53" wire \libresocsim_libresoc_constraintmanager_sdram_cke - attribute \src "ls180.v:131.5-131.55" + attribute \src "ls180.v:129.5-129.55" wire \libresocsim_libresoc_constraintmanager_sdram_clock - attribute \src "ls180.v:127.5-127.54" + attribute \src "ls180.v:125.5-125.54" wire \libresocsim_libresoc_constraintmanager_sdram_cs_n - attribute \src "ls180.v:130.11-130.58" + attribute \src "ls180.v:128.11-128.58" wire width 2 \libresocsim_libresoc_constraintmanager_sdram_dm - attribute \src "ls180.v:121.13-121.62" + attribute \src "ls180.v:119.13-119.62" wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_i - attribute \src "ls180.v:122.12-122.61" + attribute \src "ls180.v:120.12-120.61" wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_o - attribute \src "ls180.v:123.5-123.55" + attribute \src "ls180.v:121.5-121.55" wire \libresocsim_libresoc_constraintmanager_sdram_dq_oe - attribute \src "ls180.v:125.5-125.55" + attribute \src "ls180.v:123.5-123.55" wire \libresocsim_libresoc_constraintmanager_sdram_ras_n - attribute \src "ls180.v:124.5-124.54" + attribute \src "ls180.v:122.5-122.54" wire \libresocsim_libresoc_constraintmanager_sdram_we_n - attribute \src "ls180.v:136.5-136.57" + attribute \src "ls180.v:133.5-133.57" wire \libresocsim_libresoc_constraintmanager_spimaster_clk - attribute \src "ls180.v:138.5-138.58" + attribute \src "ls180.v:135.5-135.58" wire \libresocsim_libresoc_constraintmanager_spimaster_cs_n - attribute \src "ls180.v:139.6-139.59" + attribute \src "ls180.v:136.6-136.59" wire \libresocsim_libresoc_constraintmanager_spimaster_miso - attribute \src "ls180.v:137.5-137.58" + attribute \src "ls180.v:134.5-134.58" wire \libresocsim_libresoc_constraintmanager_spimaster_mosi - attribute \src "ls180.v:116.5-116.51" + attribute \src "ls180.v:117.5-117.51" wire \libresocsim_libresoc_constraintmanager_uart_rx - attribute \src "ls180.v:115.5-115.51" + attribute \src "ls180.v:116.5-116.51" wire \libresocsim_libresoc_constraintmanager_uart_tx - attribute \src "ls180.v:62.5-62.34" + attribute \src "ls180.v:59.5-59.34" wire \libresocsim_libresoc_dbus_ack - attribute \src "ls180.v:56.13-56.42" + attribute \src "ls180.v:53.13-53.42" wire width 29 \libresocsim_libresoc_dbus_adr - attribute \src "ls180.v:60.6-60.35" + attribute \src "ls180.v:57.6-57.35" wire \libresocsim_libresoc_dbus_cyc - attribute \src "ls180.v:58.13-58.44" + attribute \src "ls180.v:55.13-55.44" wire width 64 \libresocsim_libresoc_dbus_dat_r - attribute \src "ls180.v:57.13-57.44" + attribute \src "ls180.v:54.13-54.44" wire width 64 \libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:64.5-64.34" + attribute \src "ls180.v:61.5-61.34" wire \libresocsim_libresoc_dbus_err - attribute \src "ls180.v:59.12-59.41" + attribute \src "ls180.v:56.12-56.41" wire width 8 \libresocsim_libresoc_dbus_sel - attribute \src "ls180.v:61.6-61.35" + attribute \src "ls180.v:58.6-58.35" wire \libresocsim_libresoc_dbus_stb - attribute \src "ls180.v:63.6-63.34" + attribute \src "ls180.v:60.6-60.34" wire \libresocsim_libresoc_dbus_we - attribute \src "ls180.v:71.5-71.34" + attribute \src "ls180.v:68.5-68.34" wire \libresocsim_libresoc_ibus_ack - attribute \src "ls180.v:65.13-65.42" + attribute \src "ls180.v:62.13-62.42" wire width 29 \libresocsim_libresoc_ibus_adr - attribute \src "ls180.v:69.6-69.35" + attribute \src "ls180.v:66.6-66.35" wire \libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:67.13-67.44" + attribute \src "ls180.v:64.13-64.44" wire width 64 \libresocsim_libresoc_ibus_dat_r - attribute \src "ls180.v:66.13-66.44" + attribute \src "ls180.v:63.13-63.44" wire width 64 \libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:73.5-73.34" + attribute \src "ls180.v:70.5-70.34" wire \libresocsim_libresoc_ibus_err - attribute \src "ls180.v:68.12-68.41" + attribute \src "ls180.v:65.12-65.41" wire width 8 \libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:70.6-70.35" + attribute \src "ls180.v:67.6-67.35" wire \libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:72.6-72.34" + attribute \src "ls180.v:69.6-69.34" wire \libresocsim_libresoc_ibus_we - attribute \src "ls180.v:55.12-55.42" + attribute \src "ls180.v:52.12-52.42" wire width 16 \libresocsim_libresoc_interrupt - attribute \src "ls180.v:105.6-105.35" + attribute \src "ls180.v:102.6-102.35" wire \libresocsim_libresoc_jtag_tck - attribute \src "ls180.v:107.6-107.35" + attribute \src "ls180.v:104.6-104.35" wire \libresocsim_libresoc_jtag_tdi - attribute \src "ls180.v:108.6-108.35" + attribute \src "ls180.v:105.6-105.35" wire \libresocsim_libresoc_jtag_tdo - attribute \src "ls180.v:106.6-106.35" + attribute \src "ls180.v:103.6-103.35" wire \libresocsim_libresoc_jtag_tms - attribute \src "ls180.v:102.5-102.37" + attribute \src "ls180.v:99.5-99.37" wire \libresocsim_libresoc_jtag_wb_ack - attribute \src "ls180.v:96.13-96.45" + attribute \src "ls180.v:93.13-93.45" wire width 29 \libresocsim_libresoc_jtag_wb_adr - attribute \src "ls180.v:100.6-100.38" + attribute \src "ls180.v:97.6-97.38" wire \libresocsim_libresoc_jtag_wb_cyc - attribute \src "ls180.v:98.13-98.47" + attribute \src "ls180.v:95.13-95.47" wire width 64 \libresocsim_libresoc_jtag_wb_dat_r - attribute \src "ls180.v:97.13-97.47" + attribute \src "ls180.v:94.13-94.47" wire width 64 \libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:104.5-104.37" + attribute \src "ls180.v:101.5-101.37" wire \libresocsim_libresoc_jtag_wb_err - attribute \src "ls180.v:99.12-99.44" + attribute \src "ls180.v:96.12-96.44" wire width 8 \libresocsim_libresoc_jtag_wb_sel - attribute \src "ls180.v:101.6-101.38" + attribute \src "ls180.v:98.6-98.38" wire \libresocsim_libresoc_jtag_wb_stb - attribute \src "ls180.v:103.6-103.37" + attribute \src "ls180.v:100.6-100.37" wire \libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:112.6-112.35" - wire \libresocsim_libresoc_pll_18_o - attribute \src "ls180.v:114.6-114.36" - wire \libresocsim_libresoc_pll_lck_o - attribute \src "ls180.v:54.6-54.32" + attribute \src "ls180.v:51.6-51.32" wire \libresocsim_libresoc_reset - attribute \src "ls180.v:80.6-80.39" + attribute \src "ls180.v:77.6-77.39" wire \libresocsim_libresoc_xics_icp_ack - attribute \src "ls180.v:74.13-74.46" + attribute \src "ls180.v:71.13-71.46" wire width 30 \libresocsim_libresoc_xics_icp_adr - attribute \src "ls180.v:83.12-83.45" + attribute \src "ls180.v:80.12-80.45" wire width 2 \libresocsim_libresoc_xics_icp_bte - attribute \src "ls180.v:82.12-82.45" + attribute \src "ls180.v:79.12-79.45" wire width 3 \libresocsim_libresoc_xics_icp_cti - attribute \src "ls180.v:78.6-78.39" + attribute \src "ls180.v:75.6-75.39" wire \libresocsim_libresoc_xics_icp_cyc - attribute \src "ls180.v:76.13-76.48" + attribute \src "ls180.v:73.13-73.48" wire width 32 \libresocsim_libresoc_xics_icp_dat_r - attribute \src "ls180.v:75.13-75.48" + attribute \src "ls180.v:72.13-72.48" wire width 32 \libresocsim_libresoc_xics_icp_dat_w - attribute \src "ls180.v:84.6-84.39" + attribute \src "ls180.v:81.6-81.39" wire \libresocsim_libresoc_xics_icp_err - attribute \src "ls180.v:77.12-77.45" + attribute \src "ls180.v:74.12-74.45" wire width 4 \libresocsim_libresoc_xics_icp_sel - attribute \src "ls180.v:79.6-79.39" + attribute \src "ls180.v:76.6-76.39" wire \libresocsim_libresoc_xics_icp_stb - attribute \src "ls180.v:81.6-81.38" + attribute \src "ls180.v:78.6-78.38" wire \libresocsim_libresoc_xics_icp_we - attribute \src "ls180.v:91.6-91.39" + attribute \src "ls180.v:88.6-88.39" wire \libresocsim_libresoc_xics_ics_ack - attribute \src "ls180.v:85.13-85.46" + attribute \src "ls180.v:82.13-82.46" wire width 30 \libresocsim_libresoc_xics_ics_adr - attribute \src "ls180.v:94.12-94.45" + attribute \src "ls180.v:91.12-91.45" wire width 2 \libresocsim_libresoc_xics_ics_bte - attribute \src "ls180.v:93.12-93.45" + attribute \src "ls180.v:90.12-90.45" wire width 3 \libresocsim_libresoc_xics_ics_cti - attribute \src "ls180.v:89.6-89.39" + attribute \src "ls180.v:86.6-86.39" wire \libresocsim_libresoc_xics_ics_cyc - attribute \src "ls180.v:87.13-87.48" + attribute \src "ls180.v:84.13-84.48" wire width 32 \libresocsim_libresoc_xics_ics_dat_r - attribute \src "ls180.v:86.13-86.48" + attribute \src "ls180.v:83.13-83.48" wire width 32 \libresocsim_libresoc_xics_ics_dat_w - attribute \src "ls180.v:95.6-95.39" + attribute \src "ls180.v:92.6-92.39" wire \libresocsim_libresoc_xics_ics_err - attribute \src "ls180.v:88.12-88.45" + attribute \src "ls180.v:85.12-85.45" wire width 4 \libresocsim_libresoc_xics_ics_sel - attribute \src "ls180.v:90.6-90.39" + attribute \src "ls180.v:87.6-87.39" wire \libresocsim_libresoc_xics_ics_stb - attribute \src "ls180.v:92.6-92.38" + attribute \src "ls180.v:89.6-89.38" wire \libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:1057.12-1057.39" + attribute \src "ls180.v:1051.12-1051.39" wire width 14 \libresocsim_libresocsim_adr - attribute \src "ls180.v:1339.12-1339.63" + attribute \src "ls180.v:1333.12-1333.63" wire width 14 \libresocsim_libresocsim_adr_libresocsim_next_value1 - attribute \src "ls180.v:1340.5-1340.59" + attribute \src "ls180.v:1334.5-1334.59" wire \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 - attribute \src "ls180.v:1060.12-1060.41" + attribute \src "ls180.v:1054.12-1054.41" wire width 8 \libresocsim_libresocsim_dat_r - attribute \src "ls180.v:1059.11-1059.40" + attribute \src "ls180.v:1053.11-1053.40" wire width 8 \libresocsim_libresocsim_dat_w - attribute \src "ls180.v:1337.11-1337.64" + attribute \src "ls180.v:1331.11-1331.64" wire width 8 \libresocsim_libresocsim_dat_w_libresocsim_next_value0 - attribute \src "ls180.v:1338.5-1338.61" + attribute \src "ls180.v:1332.5-1332.61" wire \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 - attribute \src "ls180.v:1058.5-1058.31" + attribute \src "ls180.v:1052.5-1052.31" wire \libresocsim_libresocsim_we - attribute \src "ls180.v:1341.5-1341.55" + attribute \src "ls180.v:1335.5-1335.55" wire \libresocsim_libresocsim_we_libresocsim_next_value2 - attribute \src "ls180.v:1342.5-1342.58" + attribute \src "ls180.v:1336.5-1336.58" wire \libresocsim_libresocsim_we_libresocsim_next_value_ce2 - attribute \src "ls180.v:1067.5-1067.41" + attribute \src "ls180.v:1061.5-1061.41" wire \libresocsim_libresocsim_wishbone_ack - attribute \src "ls180.v:1061.13-1061.49" + attribute \src "ls180.v:1055.13-1055.49" wire width 30 \libresocsim_libresocsim_wishbone_adr - attribute \src "ls180.v:1070.12-1070.48" + attribute \src "ls180.v:1064.12-1064.48" wire width 2 \libresocsim_libresocsim_wishbone_bte - attribute \src "ls180.v:1069.12-1069.48" + attribute \src "ls180.v:1063.12-1063.48" wire width 3 \libresocsim_libresocsim_wishbone_cti - attribute \src "ls180.v:1065.6-1065.42" + attribute \src "ls180.v:1059.6-1059.42" wire \libresocsim_libresocsim_wishbone_cyc - attribute \src "ls180.v:1063.12-1063.50" + attribute \src "ls180.v:1057.12-1057.50" wire width 32 \libresocsim_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1062.13-1062.51" + attribute \src "ls180.v:1056.13-1056.51" wire width 32 \libresocsim_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1071.5-1071.41" + attribute \src "ls180.v:1065.5-1065.41" wire \libresocsim_libresocsim_wishbone_err - attribute \src "ls180.v:1064.12-1064.48" + attribute \src "ls180.v:1058.12-1058.48" wire width 4 \libresocsim_libresocsim_wishbone_sel - attribute \src "ls180.v:1066.6-1066.42" + attribute \src "ls180.v:1060.6-1060.42" wire \libresocsim_libresocsim_wishbone_stb - attribute \src "ls180.v:1068.6-1068.41" + attribute \src "ls180.v:1062.6-1062.41" wire \libresocsim_libresocsim_wishbone_we - attribute \src "ls180.v:204.5-204.24" + attribute \src "ls180.v:198.5-198.24" wire \libresocsim_load_re - attribute \src "ls180.v:203.12-203.36" + attribute \src "ls180.v:197.12-197.36" wire width 32 \libresocsim_load_storage - attribute \src "ls180.v:1336.11-1336.33" + attribute \src "ls180.v:1330.11-1330.33" wire width 2 \libresocsim_next_state - attribute \src "ls180.v:194.5-194.28" + attribute \src "ls180.v:188.5-188.28" wire \libresocsim_ram_bus_ack - attribute \src "ls180.v:188.13-188.36" + attribute \src "ls180.v:182.13-182.36" wire width 30 \libresocsim_ram_bus_adr - attribute \src "ls180.v:197.12-197.35" + attribute \src "ls180.v:191.12-191.35" wire width 2 \libresocsim_ram_bus_bte - attribute \src "ls180.v:196.12-196.35" + attribute \src "ls180.v:190.12-190.35" wire width 3 \libresocsim_ram_bus_cti - attribute \src "ls180.v:192.6-192.29" + attribute \src "ls180.v:186.6-186.29" wire \libresocsim_ram_bus_cyc - attribute \src "ls180.v:190.13-190.38" + attribute \src "ls180.v:184.13-184.38" wire width 32 \libresocsim_ram_bus_dat_r - attribute \src "ls180.v:189.13-189.38" + attribute \src "ls180.v:183.13-183.38" wire width 32 \libresocsim_ram_bus_dat_w - attribute \src "ls180.v:198.5-198.28" + attribute \src "ls180.v:192.5-192.28" wire \libresocsim_ram_bus_err - attribute \src "ls180.v:191.12-191.35" + attribute \src "ls180.v:185.12-185.35" wire width 4 \libresocsim_ram_bus_sel - attribute \src "ls180.v:193.6-193.29" + attribute \src "ls180.v:187.6-187.29" wire \libresocsim_ram_bus_stb - attribute \src "ls180.v:195.6-195.28" + attribute \src "ls180.v:189.6-189.28" wire \libresocsim_ram_bus_we - attribute \src "ls180.v:206.5-206.26" + attribute \src "ls180.v:200.5-200.26" wire \libresocsim_reload_re - attribute \src "ls180.v:205.12-205.38" + attribute \src "ls180.v:199.12-199.38" wire width 32 \libresocsim_reload_storage - attribute \src "ls180.v:1083.12-1083.31" + attribute \src "ls180.v:1077.12-1077.31" wire width 3 \libresocsim_request - attribute \src "ls180.v:51.6-51.23" + attribute \src "ls180.v:48.6-48.23" wire \libresocsim_reset - attribute \src "ls180.v:46.5-46.25" + attribute \src "ls180.v:43.5-43.25" wire \libresocsim_reset_re - attribute \src "ls180.v:45.5-45.30" + attribute \src "ls180.v:42.5-42.30" wire \libresocsim_reset_storage - attribute \src "ls180.v:48.5-48.27" + attribute \src "ls180.v:45.5-45.27" wire \libresocsim_scratch_re - attribute \src "ls180.v:47.12-47.39" + attribute \src "ls180.v:44.12-44.39" wire width 32 \libresocsim_scratch_storage - attribute \src "ls180.v:1078.5-1078.27" + attribute \src "ls180.v:1072.5-1072.27" wire \libresocsim_shared_ack - attribute \src "ls180.v:1072.13-1072.35" + attribute \src "ls180.v:1066.13-1066.35" wire width 30 \libresocsim_shared_adr - attribute \src "ls180.v:1081.12-1081.34" + attribute \src "ls180.v:1075.12-1075.34" wire width 2 \libresocsim_shared_bte - attribute \src "ls180.v:1080.12-1080.34" + attribute \src "ls180.v:1074.12-1074.34" wire width 3 \libresocsim_shared_cti - attribute \src "ls180.v:1076.6-1076.28" + attribute \src "ls180.v:1070.6-1070.28" wire \libresocsim_shared_cyc - attribute \src "ls180.v:1074.12-1074.36" + attribute \src "ls180.v:1068.12-1068.36" wire width 32 \libresocsim_shared_dat_r - attribute \src "ls180.v:1073.13-1073.37" + attribute \src "ls180.v:1067.13-1067.37" wire width 32 \libresocsim_shared_dat_w - attribute \src "ls180.v:1082.6-1082.28" + attribute \src "ls180.v:1076.6-1076.28" wire \libresocsim_shared_err - attribute \src "ls180.v:1075.12-1075.34" + attribute \src "ls180.v:1069.12-1069.34" wire width 4 \libresocsim_shared_sel - attribute \src "ls180.v:1077.6-1077.28" + attribute \src "ls180.v:1071.6-1071.28" wire \libresocsim_shared_stb - attribute \src "ls180.v:1079.6-1079.27" + attribute \src "ls180.v:1073.6-1073.27" wire \libresocsim_shared_we - attribute \src "ls180.v:1085.11-1085.32" + attribute \src "ls180.v:1079.11-1079.32" wire width 6 \libresocsim_slave_sel - attribute \src "ls180.v:1086.11-1086.34" + attribute \src "ls180.v:1080.11-1080.34" wire width 6 \libresocsim_slave_sel_r - attribute \src "ls180.v:1335.11-1335.28" + attribute \src "ls180.v:1329.11-1329.28" wire width 2 \libresocsim_state - attribute \src "ls180.v:210.5-210.32" + attribute \src "ls180.v:204.5-204.32" wire \libresocsim_update_value_re - attribute \src "ls180.v:209.5-209.37" + attribute \src "ls180.v:203.5-203.37" wire \libresocsim_update_value_storage - attribute \src "ls180.v:229.12-229.29" + attribute \src "ls180.v:223.12-223.29" wire width 32 \libresocsim_value - attribute \src "ls180.v:211.12-211.36" + attribute \src "ls180.v:205.12-205.36" wire width 32 \libresocsim_value_status - attribute \src "ls180.v:212.6-212.26" + attribute \src "ls180.v:206.6-206.26" wire \libresocsim_value_we - attribute \src "ls180.v:1088.6-1088.22" + attribute \src "ls180.v:1082.6-1082.22" wire \libresocsim_wait - attribute \src "ls180.v:201.11-201.25" + attribute \src "ls180.v:195.11-195.25" wire width 4 \libresocsim_we - attribute \src "ls180.v:217.5-217.27" + attribute \src "ls180.v:211.5-211.27" wire \libresocsim_zero_clear - attribute \src "ls180.v:218.5-218.33" + attribute \src "ls180.v:212.5-212.33" wire \libresocsim_zero_old_trigger - attribute \src "ls180.v:215.5-215.29" + attribute \src "ls180.v:209.5-209.29" wire \libresocsim_zero_pending - attribute \src "ls180.v:214.6-214.29" + attribute \src "ls180.v:208.6-208.29" wire \libresocsim_zero_status - attribute \src "ls180.v:216.6-216.30" + attribute \src "ls180.v:210.6-210.30" wire \libresocsim_zero_trigger - attribute \src "ls180.v:826.6-826.21" + attribute \src "ls180.v:820.6-820.21" wire \litedram_wb_ack - attribute \src "ls180.v:820.12-820.27" + attribute \src "ls180.v:814.12-814.27" wire width 30 \litedram_wb_adr - attribute \src "ls180.v:824.5-824.20" + attribute \src "ls180.v:818.5-818.20" wire \litedram_wb_cyc - attribute \src "ls180.v:822.13-822.30" + attribute \src "ls180.v:816.13-816.30" wire width 16 \litedram_wb_dat_r - attribute \src "ls180.v:821.12-821.29" + attribute \src "ls180.v:815.12-815.29" wire width 16 \litedram_wb_dat_w - attribute \src "ls180.v:823.11-823.26" + attribute \src "ls180.v:817.11-817.26" wire width 2 \litedram_wb_sel - attribute \src "ls180.v:825.5-825.20" + attribute \src "ls180.v:819.5-819.20" wire \litedram_wb_stb - attribute \src "ls180.v:827.5-827.19" + attribute \src "ls180.v:821.5-821.19" wire \litedram_wb_we - attribute \src "ls180.v:5494.11-5494.17" + attribute \src "ls180.v:5489.11-5489.17" wire width 7 \memadr - attribute \src "ls180.v:5514.11-5514.19" + attribute \src "ls180.v:5509.11-5509.19" wire width 5 \memadr_1 - attribute \src "ls180.v:5534.12-5534.18" + attribute \src "ls180.v:5529.12-5529.18" wire width 25 \memdat - attribute \src "ls180.v:5548.12-5548.20" + attribute \src "ls180.v:5543.12-5543.20" wire width 25 \memdat_1 - attribute \src "ls180.v:5562.12-5562.20" + attribute \src "ls180.v:5557.12-5557.20" wire width 25 \memdat_2 - attribute \src "ls180.v:5576.12-5576.20" + attribute \src "ls180.v:5571.12-5571.20" wire width 25 \memdat_3 - attribute \src "ls180.v:5590.11-5590.19" + attribute \src "ls180.v:5585.11-5585.19" wire width 10 \memdat_4 - attribute \src "ls180.v:5591.11-5591.19" + attribute \src "ls180.v:5586.11-5586.19" wire width 10 \memdat_5 - attribute \src "ls180.v:5607.11-5607.19" + attribute \src "ls180.v:5602.11-5602.19" wire width 10 \memdat_6 - attribute \src "ls180.v:5608.11-5608.19" + attribute \src "ls180.v:5603.11-5603.19" wire width 10 \memdat_7 - attribute \src "ls180.v:42.20-42.22" - wire width 36 input 38 \nc - attribute \src "ls180.v:998.13-998.17" - wire width 36 \nc_1 - attribute \src "ls180.v:247.6-247.13" + attribute \src "ls180.v:39.20-39.22" + wire width 40 input 35 \nc + attribute \src "ls180.v:992.13-992.17" + wire width 40 \nc_1 + attribute \src "ls180.v:241.6-241.13" wire \por_clk - attribute \src "ls180.v:799.6-799.19" + attribute \src "ls180.v:793.6-793.19" wire \port_cmd_last - attribute \src "ls180.v:801.13-801.34" + attribute \src "ls180.v:795.13-795.34" wire width 24 \port_cmd_payload_addr - attribute \src "ls180.v:800.6-800.25" + attribute \src "ls180.v:794.6-794.25" wire \port_cmd_payload_we - attribute \src "ls180.v:798.6-798.20" + attribute \src "ls180.v:792.6-792.20" wire \port_cmd_ready - attribute \src "ls180.v:797.6-797.20" + attribute \src "ls180.v:791.6-791.20" wire \port_cmd_valid - attribute \src "ls180.v:796.6-796.16" + attribute \src "ls180.v:790.6-790.16" wire \port_flush - attribute \src "ls180.v:808.13-808.36" + attribute \src "ls180.v:802.13-802.36" wire width 16 \port_rdata_payload_data - attribute \src "ls180.v:807.6-807.22" + attribute \src "ls180.v:801.6-801.22" wire \port_rdata_ready - attribute \src "ls180.v:806.6-806.22" + attribute \src "ls180.v:800.6-800.22" wire \port_rdata_valid - attribute \src "ls180.v:804.13-804.36" + attribute \src "ls180.v:798.13-798.36" wire width 16 \port_wdata_payload_data - attribute \src "ls180.v:805.12-805.33" + attribute \src "ls180.v:799.12-799.33" wire width 2 \port_wdata_payload_we - attribute \src "ls180.v:803.6-803.22" + attribute \src "ls180.v:797.6-797.22" wire \port_wdata_ready - attribute \src "ls180.v:802.6-802.22" + attribute \src "ls180.v:796.6-796.22" wire \port_wdata_valid - attribute \src "ls180.v:241.12-241.19" + attribute \src "ls180.v:235.12-235.19" wire width 5 \ram_adr - attribute \src "ls180.v:236.5-236.24" + attribute \src "ls180.v:230.5-230.24" wire \ram_bus_ram_bus_ack - attribute \src "ls180.v:230.13-230.32" + attribute \src "ls180.v:224.13-224.32" wire width 30 \ram_bus_ram_bus_adr - attribute \src "ls180.v:239.12-239.31" + attribute \src "ls180.v:233.12-233.31" wire width 2 \ram_bus_ram_bus_bte - attribute \src "ls180.v:238.12-238.31" + attribute \src "ls180.v:232.12-232.31" wire width 3 \ram_bus_ram_bus_cti - attribute \src "ls180.v:234.6-234.25" + attribute \src "ls180.v:228.6-228.25" wire \ram_bus_ram_bus_cyc - attribute \src "ls180.v:232.13-232.34" + attribute \src "ls180.v:226.13-226.34" wire width 32 \ram_bus_ram_bus_dat_r - attribute \src "ls180.v:231.13-231.34" + attribute \src "ls180.v:225.13-225.34" wire width 32 \ram_bus_ram_bus_dat_w - attribute \src "ls180.v:240.5-240.24" + attribute \src "ls180.v:234.5-234.24" wire \ram_bus_ram_bus_err - attribute \src "ls180.v:233.12-233.31" + attribute \src "ls180.v:227.12-227.31" wire width 4 \ram_bus_ram_bus_sel - attribute \src "ls180.v:235.6-235.25" + attribute \src "ls180.v:229.6-229.25" wire \ram_bus_ram_bus_stb - attribute \src "ls180.v:237.6-237.24" + attribute \src "ls180.v:231.6-231.24" wire \ram_bus_ram_bus_we - attribute \src "ls180.v:242.13-242.22" + attribute \src "ls180.v:236.13-236.22" wire width 32 \ram_dat_r - attribute \src "ls180.v:244.13-244.22" + attribute \src "ls180.v:238.13-238.22" wire width 32 \ram_dat_w - attribute \src "ls180.v:243.11-243.17" + attribute \src "ls180.v:237.11-237.17" wire width 4 \ram_we - attribute \src "ls180.v:265.11-265.20" + attribute \src "ls180.v:259.11-259.20" wire width 3 \rddata_en attribute \no_retiming "true" - attribute \src "ls180.v:1444.32-1444.37" + attribute \src "ls180.v:1438.32-1438.37" wire \regs0 attribute \no_retiming "true" - attribute \src "ls180.v:1445.32-1445.37" + attribute \src "ls180.v:1439.32-1439.37" wire \regs1 - attribute \src "ls180.v:978.5-978.10" + attribute \src "ls180.v:972.5-972.10" wire \reset - attribute \src "ls180.v:1343.5-1343.21" + attribute \src "ls180.v:1337.5-1337.21" wire \rhs_array_muxed0 - attribute \src "ls180.v:1344.12-1344.28" + attribute \src "ls180.v:1338.12-1338.28" wire width 13 \rhs_array_muxed1 - attribute \src "ls180.v:1356.5-1356.22" + attribute \src "ls180.v:1350.5-1350.22" wire \rhs_array_muxed10 - attribute \src "ls180.v:1357.5-1357.22" + attribute \src "ls180.v:1351.5-1351.22" wire \rhs_array_muxed11 - attribute \src "ls180.v:1361.12-1361.29" + attribute \src "ls180.v:1355.12-1355.29" wire width 22 \rhs_array_muxed12 - attribute \src "ls180.v:1362.5-1362.22" + attribute \src "ls180.v:1356.5-1356.22" wire \rhs_array_muxed13 - attribute \src "ls180.v:1363.5-1363.22" + attribute \src "ls180.v:1357.5-1357.22" wire \rhs_array_muxed14 - attribute \src "ls180.v:1364.12-1364.29" + attribute \src "ls180.v:1358.12-1358.29" wire width 22 \rhs_array_muxed15 - attribute \src "ls180.v:1365.5-1365.22" + attribute \src "ls180.v:1359.5-1359.22" wire \rhs_array_muxed16 - attribute \src "ls180.v:1366.5-1366.22" + attribute \src "ls180.v:1360.5-1360.22" wire \rhs_array_muxed17 - attribute \src "ls180.v:1367.12-1367.29" + attribute \src "ls180.v:1361.12-1361.29" wire width 22 \rhs_array_muxed18 - attribute \src "ls180.v:1368.5-1368.22" + attribute \src "ls180.v:1362.5-1362.22" wire \rhs_array_muxed19 - attribute \src "ls180.v:1345.11-1345.27" + attribute \src "ls180.v:1339.11-1339.27" wire width 2 \rhs_array_muxed2 - attribute \src "ls180.v:1369.5-1369.22" + attribute \src "ls180.v:1363.5-1363.22" wire \rhs_array_muxed20 - attribute \src "ls180.v:1370.12-1370.29" + attribute \src "ls180.v:1364.12-1364.29" wire width 22 \rhs_array_muxed21 - attribute \src "ls180.v:1371.5-1371.22" + attribute \src "ls180.v:1365.5-1365.22" wire \rhs_array_muxed22 - attribute \src "ls180.v:1372.5-1372.22" + attribute \src "ls180.v:1366.5-1366.22" wire \rhs_array_muxed23 - attribute \src "ls180.v:1373.12-1373.29" + attribute \src "ls180.v:1367.12-1367.29" wire width 30 \rhs_array_muxed24 - attribute \src "ls180.v:1374.12-1374.29" + attribute \src "ls180.v:1368.12-1368.29" wire width 32 \rhs_array_muxed25 - attribute \src "ls180.v:1375.11-1375.28" + attribute \src "ls180.v:1369.11-1369.28" wire width 4 \rhs_array_muxed26 - attribute \src "ls180.v:1376.5-1376.22" + attribute \src "ls180.v:1370.5-1370.22" wire \rhs_array_muxed27 - attribute \src "ls180.v:1377.5-1377.22" + attribute \src "ls180.v:1371.5-1371.22" wire \rhs_array_muxed28 - attribute \src "ls180.v:1378.5-1378.22" + attribute \src "ls180.v:1372.5-1372.22" wire \rhs_array_muxed29 - attribute \src "ls180.v:1346.5-1346.21" + attribute \src "ls180.v:1340.5-1340.21" wire \rhs_array_muxed3 - attribute \src "ls180.v:1379.11-1379.28" + attribute \src "ls180.v:1373.11-1373.28" wire width 3 \rhs_array_muxed30 - attribute \src "ls180.v:1380.11-1380.28" + attribute \src "ls180.v:1374.11-1374.28" wire width 2 \rhs_array_muxed31 - attribute \src "ls180.v:1347.5-1347.21" + attribute \src "ls180.v:1341.5-1341.21" wire \rhs_array_muxed4 - attribute \src "ls180.v:1348.5-1348.21" + attribute \src "ls180.v:1342.5-1342.21" wire \rhs_array_muxed5 - attribute \src "ls180.v:1352.5-1352.21" + attribute \src "ls180.v:1346.5-1346.21" wire \rhs_array_muxed6 - attribute \src "ls180.v:1353.12-1353.28" + attribute \src "ls180.v:1347.12-1347.28" wire width 13 \rhs_array_muxed7 - attribute \src "ls180.v:1354.11-1354.27" + attribute \src "ls180.v:1348.11-1348.27" wire width 2 \rhs_array_muxed8 - attribute \src "ls180.v:1355.5-1355.21" + attribute \src "ls180.v:1349.5-1349.21" wire \rhs_array_muxed9 - attribute \src "ls180.v:878.5-878.13" + attribute \src "ls180.v:872.5-872.13" wire \rx_clear - attribute \src "ls180.v:962.11-962.26" + attribute \src "ls180.v:956.11-956.26" wire width 4 \rx_fifo_consume - attribute \src "ls180.v:967.6-967.21" + attribute \src "ls180.v:961.6-961.21" wire \rx_fifo_do_read - attribute \src "ls180.v:973.6-973.27" + attribute \src "ls180.v:967.6-967.27" wire \rx_fifo_fifo_in_first - attribute \src "ls180.v:974.6-974.26" + attribute \src "ls180.v:968.6-968.26" wire \rx_fifo_fifo_in_last - attribute \src "ls180.v:972.12-972.40" + attribute \src "ls180.v:966.12-966.40" wire width 8 \rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:976.6-976.28" + attribute \src "ls180.v:970.6-970.28" wire \rx_fifo_fifo_out_first - attribute \src "ls180.v:977.6-977.27" + attribute \src "ls180.v:971.6-971.27" wire \rx_fifo_fifo_out_last - attribute \src "ls180.v:975.12-975.41" + attribute \src "ls180.v:969.12-969.41" wire width 8 \rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:959.11-959.25" + attribute \src "ls180.v:953.11-953.25" wire width 5 \rx_fifo_level0 - attribute \src "ls180.v:971.12-971.26" + attribute \src "ls180.v:965.12-965.26" wire width 5 \rx_fifo_level1 - attribute \src "ls180.v:961.11-961.26" + attribute \src "ls180.v:955.11-955.26" wire width 4 \rx_fifo_produce - attribute \src "ls180.v:968.12-968.30" + attribute \src "ls180.v:962.12-962.30" wire width 4 \rx_fifo_rdport_adr - attribute \src "ls180.v:969.12-969.32" + attribute \src "ls180.v:963.12-963.32" wire width 10 \rx_fifo_rdport_dat_r - attribute \src "ls180.v:970.6-970.23" + attribute \src "ls180.v:964.6-964.23" wire \rx_fifo_rdport_re - attribute \src "ls180.v:951.6-951.16" + attribute \src "ls180.v:945.6-945.16" wire \rx_fifo_re - attribute \src "ls180.v:952.5-952.21" + attribute \src "ls180.v:946.5-946.21" wire \rx_fifo_readable - attribute \src "ls180.v:960.5-960.20" + attribute \src "ls180.v:954.5-954.20" wire \rx_fifo_replace - attribute \src "ls180.v:943.6-943.24" + attribute \src "ls180.v:937.6-937.24" wire \rx_fifo_sink_first - attribute \src "ls180.v:944.6-944.23" + attribute \src "ls180.v:938.6-938.23" wire \rx_fifo_sink_last - attribute \src "ls180.v:945.12-945.37" + attribute \src "ls180.v:939.12-939.37" wire width 8 \rx_fifo_sink_payload_data - attribute \src "ls180.v:942.6-942.24" + attribute \src "ls180.v:936.6-936.24" wire \rx_fifo_sink_ready - attribute \src "ls180.v:941.6-941.24" + attribute \src "ls180.v:935.6-935.24" wire \rx_fifo_sink_valid - attribute \src "ls180.v:948.6-948.26" + attribute \src "ls180.v:942.6-942.26" wire \rx_fifo_source_first - attribute \src "ls180.v:949.6-949.25" + attribute \src "ls180.v:943.6-943.25" wire \rx_fifo_source_last - attribute \src "ls180.v:950.12-950.39" + attribute \src "ls180.v:944.12-944.39" wire width 8 \rx_fifo_source_payload_data - attribute \src "ls180.v:947.6-947.26" + attribute \src "ls180.v:941.6-941.26" wire \rx_fifo_source_ready - attribute \src "ls180.v:946.6-946.26" + attribute \src "ls180.v:940.6-940.26" wire \rx_fifo_source_valid - attribute \src "ls180.v:957.12-957.32" + attribute \src "ls180.v:951.12-951.32" wire width 10 \rx_fifo_syncfifo_din - attribute \src "ls180.v:958.12-958.33" + attribute \src "ls180.v:952.12-952.33" wire width 10 \rx_fifo_syncfifo_dout - attribute \src "ls180.v:955.6-955.25" + attribute \src "ls180.v:949.6-949.25" wire \rx_fifo_syncfifo_re - attribute \src "ls180.v:956.6-956.31" + attribute \src "ls180.v:950.6-950.31" wire \rx_fifo_syncfifo_readable - attribute \src "ls180.v:953.6-953.25" + attribute \src "ls180.v:947.6-947.25" wire \rx_fifo_syncfifo_we - attribute \src "ls180.v:954.6-954.31" + attribute \src "ls180.v:948.6-948.31" wire \rx_fifo_syncfifo_writable - attribute \src "ls180.v:963.11-963.29" + attribute \src "ls180.v:957.11-957.29" wire width 4 \rx_fifo_wrport_adr - attribute \src "ls180.v:964.12-964.32" + attribute \src "ls180.v:958.12-958.32" wire width 10 \rx_fifo_wrport_dat_r - attribute \src "ls180.v:966.12-966.32" + attribute \src "ls180.v:960.12-960.32" wire width 10 \rx_fifo_wrport_dat_w - attribute \src "ls180.v:965.6-965.23" + attribute \src "ls180.v:959.6-959.23" wire \rx_fifo_wrport_we - attribute \src "ls180.v:879.5-879.19" + attribute \src "ls180.v:873.5-873.19" wire \rx_old_trigger - attribute \src "ls180.v:876.5-876.15" + attribute \src "ls180.v:870.5-870.15" wire \rx_pending - attribute \src "ls180.v:875.6-875.15" + attribute \src "ls180.v:869.6-869.15" wire \rx_status - attribute \src "ls180.v:877.6-877.16" + attribute \src "ls180.v:871.6-871.16" wire \rx_trigger - attribute \src "ls180.v:867.6-867.20" + attribute \src "ls180.v:861.6-861.20" wire \rxempty_status - attribute \src "ls180.v:868.6-868.16" + attribute \src "ls180.v:862.6-862.16" wire \rxempty_we - attribute \src "ls180.v:892.6-892.19" + attribute \src "ls180.v:886.6-886.19" wire \rxfull_status - attribute \src "ls180.v:893.6-893.15" + attribute \src "ls180.v:887.6-887.15" wire \rxfull_we - attribute \src "ls180.v:862.12-862.18" + attribute \src "ls180.v:856.12-856.18" wire width 8 \rxtx_r - attribute \src "ls180.v:861.6-861.13" + attribute \src "ls180.v:855.6-855.13" wire \rxtx_re - attribute \src "ls180.v:864.12-864.18" + attribute \src "ls180.v:858.12-858.18" wire width 8 \rxtx_w - attribute \src "ls180.v:863.6-863.13" + attribute \src "ls180.v:857.6-857.13" wire \rxtx_we - attribute \src "ls180.v:10.21-10.28" - wire width 13 output 6 \sdram_a - attribute \src "ls180.v:327.5-327.21" + attribute \src "ls180.v:14.21-14.28" + wire width 13 output 10 \sdram_a + attribute \src "ls180.v:321.5-321.21" wire \sdram_address_re - attribute \src "ls180.v:326.12-326.33" + attribute \src "ls180.v:320.12-320.33" wire width 13 \sdram_address_storage - attribute \src "ls180.v:19.20-19.28" - wire width 2 output 15 \sdram_ba - attribute \src "ls180.v:329.5-329.22" + attribute \src "ls180.v:23.20-23.28" + wire width 2 output 19 \sdram_ba + attribute \src "ls180.v:323.5-323.22" wire \sdram_baddress_re - attribute \src "ls180.v:328.11-328.33" + attribute \src "ls180.v:322.11-322.33" wire width 2 \sdram_baddress_storage - attribute \src "ls180.v:425.5-425.38" + attribute \src "ls180.v:419.5-419.38" wire \sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:447.11-447.58" + attribute \src "ls180.v:441.11-441.58" wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:452.6-452.53" + attribute \src "ls180.v:446.6-446.53" wire \sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:457.6-457.59" + attribute \src "ls180.v:451.6-451.59" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:458.6-458.58" + attribute \src "ls180.v:452.6-452.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:456.13-456.73" + attribute \src "ls180.v:450.13-450.73" wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:455.6-455.64" + attribute \src "ls180.v:449.6-449.64" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:461.6-461.60" + attribute \src "ls180.v:455.6-455.60" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:462.6-462.59" + attribute \src "ls180.v:456.6-456.59" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:460.13-460.74" + attribute \src "ls180.v:454.13-454.74" wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:459.6-459.65" + attribute \src "ls180.v:453.6-453.65" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:444.11-444.56" + attribute \src "ls180.v:438.11-438.56" wire width 4 \sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:446.11-446.58" + attribute \src "ls180.v:440.11-440.58" wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:453.12-453.62" + attribute \src "ls180.v:447.12-447.62" wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:454.13-454.65" + attribute \src "ls180.v:448.13-448.65" wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:445.5-445.52" + attribute \src "ls180.v:439.5-439.52" wire \sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:428.5-428.55" + attribute \src "ls180.v:422.5-422.55" wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:429.5-429.54" + attribute \src "ls180.v:423.5-423.54" wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:431.13-431.70" + attribute \src "ls180.v:425.13-425.70" wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:430.6-430.61" + attribute \src "ls180.v:424.6-424.61" wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:427.6-427.56" + attribute \src "ls180.v:421.6-421.56" wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:426.6-426.56" + attribute \src "ls180.v:420.6-420.56" wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:434.6-434.58" + attribute \src "ls180.v:428.6-428.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:435.6-435.57" + attribute \src "ls180.v:429.6-429.57" wire \sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:437.13-437.72" + attribute \src "ls180.v:431.13-431.72" wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:436.6-436.63" + attribute \src "ls180.v:430.6-430.63" wire \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:433.6-433.58" + attribute \src "ls180.v:427.6-427.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:432.6-432.58" + attribute \src "ls180.v:426.6-426.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:442.13-442.66" + attribute \src "ls180.v:436.13-436.66" wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:443.13-443.67" + attribute \src "ls180.v:437.13-437.67" wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:440.6-440.58" + attribute \src "ls180.v:434.6-434.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:441.6-441.64" + attribute \src "ls180.v:435.6-435.64" wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:438.6-438.58" + attribute \src "ls180.v:432.6-432.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:439.6-439.64" + attribute \src "ls180.v:433.6-433.64" wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:448.11-448.61" + attribute \src "ls180.v:442.11-442.61" wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:449.13-449.65" + attribute \src "ls180.v:443.13-443.65" wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:451.13-451.65" + attribute \src "ls180.v:445.13-445.65" wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:450.6-450.55" + attribute \src "ls180.v:444.6-444.55" wire \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:465.6-465.46" + attribute \src "ls180.v:459.6-459.46" wire \sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:466.6-466.45" + attribute \src "ls180.v:460.6-460.45" wire \sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:468.13-468.60" + attribute \src "ls180.v:462.13-462.60" wire width 22 \sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:467.6-467.51" + attribute \src "ls180.v:461.6-461.51" wire \sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:464.6-464.46" + attribute \src "ls180.v:458.6-458.46" wire \sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:463.6-463.46" + attribute \src "ls180.v:457.6-457.46" wire \sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:471.5-471.47" + attribute \src "ls180.v:465.5-465.47" wire \sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:472.5-472.46" + attribute \src "ls180.v:466.5-466.46" wire \sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:474.12-474.61" + attribute \src "ls180.v:468.12-468.61" wire width 22 \sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:473.5-473.52" + attribute \src "ls180.v:467.5-467.52" wire \sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:470.6-470.48" + attribute \src "ls180.v:464.6-464.48" wire \sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:469.5-469.47" + attribute \src "ls180.v:463.5-463.47" wire \sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:417.12-417.44" + attribute \src "ls180.v:411.12-411.44" wire width 13 \sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:418.12-418.45" + attribute \src "ls180.v:412.12-412.45" wire width 2 \sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:419.5-419.39" + attribute \src "ls180.v:413.5-413.39" wire \sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:422.5-422.42" + attribute \src "ls180.v:416.5-416.42" wire \sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:423.5-423.43" + attribute \src "ls180.v:417.5-417.43" wire \sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:424.5-424.44" + attribute \src "ls180.v:418.5-418.44" wire \sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:420.5-420.39" + attribute \src "ls180.v:414.5-414.39" wire \sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:421.5-421.38" + attribute \src "ls180.v:415.5-415.38" wire \sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:416.5-416.33" + attribute \src "ls180.v:410.5-410.33" wire \sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:415.5-415.33" + attribute \src "ls180.v:409.5-409.33" wire \sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:414.5-414.35" + attribute \src "ls180.v:408.5-408.35" wire \sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:413.6-413.36" + attribute \src "ls180.v:407.6-407.36" wire \sdram_bankmachine0_refresh_req - attribute \src "ls180.v:409.13-409.40" + attribute \src "ls180.v:403.13-403.40" wire width 22 \sdram_bankmachine0_req_addr - attribute \src "ls180.v:410.6-410.33" + attribute \src "ls180.v:404.6-404.33" wire \sdram_bankmachine0_req_lock - attribute \src "ls180.v:412.5-412.39" + attribute \src "ls180.v:406.5-406.39" wire \sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:407.6-407.34" + attribute \src "ls180.v:401.6-401.34" wire \sdram_bankmachine0_req_ready - attribute \src "ls180.v:406.6-406.34" + attribute \src "ls180.v:400.6-400.34" wire \sdram_bankmachine0_req_valid - attribute \src "ls180.v:411.5-411.39" + attribute \src "ls180.v:405.5-405.39" wire \sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:408.6-408.31" + attribute \src "ls180.v:402.6-402.31" wire \sdram_bankmachine0_req_we - attribute \src "ls180.v:475.12-475.34" + attribute \src "ls180.v:469.12-469.34" wire width 13 \sdram_bankmachine0_row - attribute \src "ls180.v:479.5-479.33" + attribute \src "ls180.v:473.5-473.33" wire \sdram_bankmachine0_row_close - attribute \src "ls180.v:480.5-480.42" + attribute \src "ls180.v:474.5-474.42" wire \sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:477.6-477.32" + attribute \src "ls180.v:471.6-471.32" wire \sdram_bankmachine0_row_hit - attribute \src "ls180.v:478.5-478.32" + attribute \src "ls180.v:472.5-472.32" wire \sdram_bankmachine0_row_open - attribute \src "ls180.v:476.5-476.34" + attribute \src "ls180.v:470.5-470.34" wire \sdram_bankmachine0_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:487.32-487.64" + attribute \src "ls180.v:481.32-481.64" wire \sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:486.6-486.38" + attribute \src "ls180.v:480.6-480.38" wire \sdram_bankmachine0_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:485.32-485.63" + attribute \src "ls180.v:479.32-479.63" wire \sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:484.6-484.37" + attribute \src "ls180.v:478.6-478.37" wire \sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:483.11-483.43" + attribute \src "ls180.v:477.11-477.43" wire width 3 \sdram_bankmachine0_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:482.32-482.64" + attribute \src "ls180.v:476.32-476.64" wire \sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:481.6-481.38" + attribute \src "ls180.v:475.6-475.38" wire \sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:507.5-507.38" + attribute \src "ls180.v:501.5-501.38" wire \sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:529.11-529.58" + attribute \src "ls180.v:523.11-523.58" wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:534.6-534.53" + attribute \src "ls180.v:528.6-528.53" wire \sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:539.6-539.59" + attribute \src "ls180.v:533.6-533.59" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:540.6-540.58" + attribute \src "ls180.v:534.6-534.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:538.13-538.73" + attribute \src "ls180.v:532.13-532.73" wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:537.6-537.64" + attribute \src "ls180.v:531.6-531.64" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:543.6-543.60" + attribute \src "ls180.v:537.6-537.60" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:544.6-544.59" + attribute \src "ls180.v:538.6-538.59" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:542.13-542.74" + attribute \src "ls180.v:536.13-536.74" wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:541.6-541.65" + attribute \src "ls180.v:535.6-535.65" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:526.11-526.56" + attribute \src "ls180.v:520.11-520.56" wire width 4 \sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:528.11-528.58" + attribute \src "ls180.v:522.11-522.58" wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:535.12-535.62" + attribute \src "ls180.v:529.12-529.62" wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:536.13-536.65" + attribute \src "ls180.v:530.13-530.65" wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:527.5-527.52" + attribute \src "ls180.v:521.5-521.52" wire \sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:510.5-510.55" + attribute \src "ls180.v:504.5-504.55" wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:511.5-511.54" + attribute \src "ls180.v:505.5-505.54" wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:513.13-513.70" + attribute \src "ls180.v:507.13-507.70" wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:512.6-512.61" + attribute \src "ls180.v:506.6-506.61" wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:509.6-509.56" + attribute \src "ls180.v:503.6-503.56" wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:508.6-508.56" + attribute \src "ls180.v:502.6-502.56" wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:516.6-516.58" + attribute \src "ls180.v:510.6-510.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:517.6-517.57" + attribute \src "ls180.v:511.6-511.57" wire \sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:519.13-519.72" + attribute \src "ls180.v:513.13-513.72" wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:518.6-518.63" + attribute \src "ls180.v:512.6-512.63" wire \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:515.6-515.58" + attribute \src "ls180.v:509.6-509.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:514.6-514.58" + attribute \src "ls180.v:508.6-508.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:524.13-524.66" + attribute \src "ls180.v:518.13-518.66" wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:525.13-525.67" + attribute \src "ls180.v:519.13-519.67" wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:522.6-522.58" + attribute \src "ls180.v:516.6-516.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:523.6-523.64" + attribute \src "ls180.v:517.6-517.64" wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:520.6-520.58" + attribute \src "ls180.v:514.6-514.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:521.6-521.64" + attribute \src "ls180.v:515.6-515.64" wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:530.11-530.61" + attribute \src "ls180.v:524.11-524.61" wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:531.13-531.65" + attribute \src "ls180.v:525.13-525.65" wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:533.13-533.65" + attribute \src "ls180.v:527.13-527.65" wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:532.6-532.55" + attribute \src "ls180.v:526.6-526.55" wire \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:547.6-547.46" + attribute \src "ls180.v:541.6-541.46" wire \sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:548.6-548.45" + attribute \src "ls180.v:542.6-542.45" wire \sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:550.13-550.60" + attribute \src "ls180.v:544.13-544.60" wire width 22 \sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:549.6-549.51" + attribute \src "ls180.v:543.6-543.51" wire \sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:546.6-546.46" + attribute \src "ls180.v:540.6-540.46" wire \sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:545.6-545.46" + attribute \src "ls180.v:539.6-539.46" wire \sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:553.5-553.47" + attribute \src "ls180.v:547.5-547.47" wire \sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:554.5-554.46" + attribute \src "ls180.v:548.5-548.46" wire \sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:556.12-556.61" + attribute \src "ls180.v:550.12-550.61" wire width 22 \sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:555.5-555.52" + attribute \src "ls180.v:549.5-549.52" wire \sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:552.6-552.48" + attribute \src "ls180.v:546.6-546.48" wire \sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:551.5-551.47" + attribute \src "ls180.v:545.5-545.47" wire \sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:499.12-499.44" + attribute \src "ls180.v:493.12-493.44" wire width 13 \sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:500.12-500.45" + attribute \src "ls180.v:494.12-494.45" wire width 2 \sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:501.5-501.39" + attribute \src "ls180.v:495.5-495.39" wire \sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:504.5-504.42" + attribute \src "ls180.v:498.5-498.42" wire \sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:505.5-505.43" + attribute \src "ls180.v:499.5-499.43" wire \sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:506.5-506.44" + attribute \src "ls180.v:500.5-500.44" wire \sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:502.5-502.39" + attribute \src "ls180.v:496.5-496.39" wire \sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:503.5-503.38" + attribute \src "ls180.v:497.5-497.38" wire \sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:498.5-498.33" + attribute \src "ls180.v:492.5-492.33" wire \sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:497.5-497.33" + attribute \src "ls180.v:491.5-491.33" wire \sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:496.5-496.35" + attribute \src "ls180.v:490.5-490.35" wire \sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:495.6-495.36" + attribute \src "ls180.v:489.6-489.36" wire \sdram_bankmachine1_refresh_req - attribute \src "ls180.v:491.13-491.40" + attribute \src "ls180.v:485.13-485.40" wire width 22 \sdram_bankmachine1_req_addr - attribute \src "ls180.v:492.6-492.33" + attribute \src "ls180.v:486.6-486.33" wire \sdram_bankmachine1_req_lock - attribute \src "ls180.v:494.5-494.39" + attribute \src "ls180.v:488.5-488.39" wire \sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:489.6-489.34" + attribute \src "ls180.v:483.6-483.34" wire \sdram_bankmachine1_req_ready - attribute \src "ls180.v:488.6-488.34" + attribute \src "ls180.v:482.6-482.34" wire \sdram_bankmachine1_req_valid - attribute \src "ls180.v:493.5-493.39" + attribute \src "ls180.v:487.5-487.39" wire \sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:490.6-490.31" + attribute \src "ls180.v:484.6-484.31" wire \sdram_bankmachine1_req_we - attribute \src "ls180.v:557.12-557.34" + attribute \src "ls180.v:551.12-551.34" wire width 13 \sdram_bankmachine1_row - attribute \src "ls180.v:561.5-561.33" + attribute \src "ls180.v:555.5-555.33" wire \sdram_bankmachine1_row_close - attribute \src "ls180.v:562.5-562.42" + attribute \src "ls180.v:556.5-556.42" wire \sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:559.6-559.32" + attribute \src "ls180.v:553.6-553.32" wire \sdram_bankmachine1_row_hit - attribute \src "ls180.v:560.5-560.32" + attribute \src "ls180.v:554.5-554.32" wire \sdram_bankmachine1_row_open - attribute \src "ls180.v:558.5-558.34" + attribute \src "ls180.v:552.5-552.34" wire \sdram_bankmachine1_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:569.32-569.64" + attribute \src "ls180.v:563.32-563.64" wire \sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:568.6-568.38" + attribute \src "ls180.v:562.6-562.38" wire \sdram_bankmachine1_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:567.32-567.63" + attribute \src "ls180.v:561.32-561.63" wire \sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:566.6-566.37" + attribute \src "ls180.v:560.6-560.37" wire \sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:565.11-565.43" + attribute \src "ls180.v:559.11-559.43" wire width 3 \sdram_bankmachine1_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:564.32-564.64" + attribute \src "ls180.v:558.32-558.64" wire \sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:563.6-563.38" + attribute \src "ls180.v:557.6-557.38" wire \sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:589.5-589.38" + attribute \src "ls180.v:583.5-583.38" wire \sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:611.11-611.58" + attribute \src "ls180.v:605.11-605.58" wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:616.6-616.53" + attribute \src "ls180.v:610.6-610.53" wire \sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:621.6-621.59" + attribute \src "ls180.v:615.6-615.59" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:622.6-622.58" + attribute \src "ls180.v:616.6-616.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:620.13-620.73" + attribute \src "ls180.v:614.13-614.73" wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:619.6-619.64" + attribute \src "ls180.v:613.6-613.64" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:625.6-625.60" + attribute \src "ls180.v:619.6-619.60" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:626.6-626.59" + attribute \src "ls180.v:620.6-620.59" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:624.13-624.74" + attribute \src "ls180.v:618.13-618.74" wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:623.6-623.65" + attribute \src "ls180.v:617.6-617.65" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:608.11-608.56" + attribute \src "ls180.v:602.11-602.56" wire width 4 \sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:610.11-610.58" + attribute \src "ls180.v:604.11-604.58" wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:617.12-617.62" + attribute \src "ls180.v:611.12-611.62" wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:618.13-618.65" + attribute \src "ls180.v:612.13-612.65" wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:609.5-609.52" + attribute \src "ls180.v:603.5-603.52" wire \sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:592.5-592.55" + attribute \src "ls180.v:586.5-586.55" wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:593.5-593.54" + attribute \src "ls180.v:587.5-587.54" wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:595.13-595.70" + attribute \src "ls180.v:589.13-589.70" wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:594.6-594.61" + attribute \src "ls180.v:588.6-588.61" wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:591.6-591.56" + attribute \src "ls180.v:585.6-585.56" wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:590.6-590.56" + attribute \src "ls180.v:584.6-584.56" wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:598.6-598.58" + attribute \src "ls180.v:592.6-592.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:599.6-599.57" + attribute \src "ls180.v:593.6-593.57" wire \sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:601.13-601.72" + attribute \src "ls180.v:595.13-595.72" wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:600.6-600.63" + attribute \src "ls180.v:594.6-594.63" wire \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:597.6-597.58" + attribute \src "ls180.v:591.6-591.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:596.6-596.58" + attribute \src "ls180.v:590.6-590.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:606.13-606.66" + attribute \src "ls180.v:600.13-600.66" wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:607.13-607.67" + attribute \src "ls180.v:601.13-601.67" wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:604.6-604.58" + attribute \src "ls180.v:598.6-598.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:605.6-605.64" + attribute \src "ls180.v:599.6-599.64" wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:602.6-602.58" + attribute \src "ls180.v:596.6-596.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:603.6-603.64" + attribute \src "ls180.v:597.6-597.64" wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:612.11-612.61" + attribute \src "ls180.v:606.11-606.61" wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:613.13-613.65" + attribute \src "ls180.v:607.13-607.65" wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:615.13-615.65" + attribute \src "ls180.v:609.13-609.65" wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:614.6-614.55" + attribute \src "ls180.v:608.6-608.55" wire \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:629.6-629.46" + attribute \src "ls180.v:623.6-623.46" wire \sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:630.6-630.45" + attribute \src "ls180.v:624.6-624.45" wire \sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:632.13-632.60" + attribute \src "ls180.v:626.13-626.60" wire width 22 \sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:631.6-631.51" + attribute \src "ls180.v:625.6-625.51" wire \sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:628.6-628.46" + attribute \src "ls180.v:622.6-622.46" wire \sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:627.6-627.46" + attribute \src "ls180.v:621.6-621.46" wire \sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:635.5-635.47" + attribute \src "ls180.v:629.5-629.47" wire \sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:636.5-636.46" + attribute \src "ls180.v:630.5-630.46" wire \sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:638.12-638.61" + attribute \src "ls180.v:632.12-632.61" wire width 22 \sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:637.5-637.52" + attribute \src "ls180.v:631.5-631.52" wire \sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:634.6-634.48" + attribute \src "ls180.v:628.6-628.48" wire \sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:633.5-633.47" + attribute \src "ls180.v:627.5-627.47" wire \sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:581.12-581.44" + attribute \src "ls180.v:575.12-575.44" wire width 13 \sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:582.12-582.45" + attribute \src "ls180.v:576.12-576.45" wire width 2 \sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:583.5-583.39" + attribute \src "ls180.v:577.5-577.39" wire \sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:586.5-586.42" + attribute \src "ls180.v:580.5-580.42" wire \sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:587.5-587.43" + attribute \src "ls180.v:581.5-581.43" wire \sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:588.5-588.44" + attribute \src "ls180.v:582.5-582.44" wire \sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:584.5-584.39" + attribute \src "ls180.v:578.5-578.39" wire \sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:585.5-585.38" + attribute \src "ls180.v:579.5-579.38" wire \sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:580.5-580.33" + attribute \src "ls180.v:574.5-574.33" wire \sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:579.5-579.33" + attribute \src "ls180.v:573.5-573.33" wire \sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:578.5-578.35" + attribute \src "ls180.v:572.5-572.35" wire \sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:577.6-577.36" + attribute \src "ls180.v:571.6-571.36" wire \sdram_bankmachine2_refresh_req - attribute \src "ls180.v:573.13-573.40" + attribute \src "ls180.v:567.13-567.40" wire width 22 \sdram_bankmachine2_req_addr - attribute \src "ls180.v:574.6-574.33" + attribute \src "ls180.v:568.6-568.33" wire \sdram_bankmachine2_req_lock - attribute \src "ls180.v:576.5-576.39" + attribute \src "ls180.v:570.5-570.39" wire \sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:571.6-571.34" + attribute \src "ls180.v:565.6-565.34" wire \sdram_bankmachine2_req_ready - attribute \src "ls180.v:570.6-570.34" + attribute \src "ls180.v:564.6-564.34" wire \sdram_bankmachine2_req_valid - attribute \src "ls180.v:575.5-575.39" + attribute \src "ls180.v:569.5-569.39" wire \sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:572.6-572.31" + attribute \src "ls180.v:566.6-566.31" wire \sdram_bankmachine2_req_we - attribute \src "ls180.v:639.12-639.34" + attribute \src "ls180.v:633.12-633.34" wire width 13 \sdram_bankmachine2_row - attribute \src "ls180.v:643.5-643.33" + attribute \src "ls180.v:637.5-637.33" wire \sdram_bankmachine2_row_close - attribute \src "ls180.v:644.5-644.42" + attribute \src "ls180.v:638.5-638.42" wire \sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:641.6-641.32" + attribute \src "ls180.v:635.6-635.32" wire \sdram_bankmachine2_row_hit - attribute \src "ls180.v:642.5-642.32" + attribute \src "ls180.v:636.5-636.32" wire \sdram_bankmachine2_row_open - attribute \src "ls180.v:640.5-640.34" + attribute \src "ls180.v:634.5-634.34" wire \sdram_bankmachine2_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:651.32-651.64" + attribute \src "ls180.v:645.32-645.64" wire \sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:650.6-650.38" + attribute \src "ls180.v:644.6-644.38" wire \sdram_bankmachine2_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:649.32-649.63" + attribute \src "ls180.v:643.32-643.63" wire \sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:648.6-648.37" + attribute \src "ls180.v:642.6-642.37" wire \sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:647.11-647.43" + attribute \src "ls180.v:641.11-641.43" wire width 3 \sdram_bankmachine2_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:646.32-646.64" + attribute \src "ls180.v:640.32-640.64" wire \sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:645.6-645.38" + attribute \src "ls180.v:639.6-639.38" wire \sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:671.5-671.38" + attribute \src "ls180.v:665.5-665.38" wire \sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:693.11-693.58" + attribute \src "ls180.v:687.11-687.58" wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:698.6-698.53" + attribute \src "ls180.v:692.6-692.53" wire \sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:703.6-703.59" + attribute \src "ls180.v:697.6-697.59" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:704.6-704.58" + attribute \src "ls180.v:698.6-698.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:702.13-702.73" + attribute \src "ls180.v:696.13-696.73" wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:701.6-701.64" + attribute \src "ls180.v:695.6-695.64" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:707.6-707.60" + attribute \src "ls180.v:701.6-701.60" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:708.6-708.59" + attribute \src "ls180.v:702.6-702.59" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:706.13-706.74" + attribute \src "ls180.v:700.13-700.74" wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:705.6-705.65" + attribute \src "ls180.v:699.6-699.65" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:690.11-690.56" + attribute \src "ls180.v:684.11-684.56" wire width 4 \sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:692.11-692.58" + attribute \src "ls180.v:686.11-686.58" wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:699.12-699.62" + attribute \src "ls180.v:693.12-693.62" wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:700.13-700.65" + attribute \src "ls180.v:694.13-694.65" wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:691.5-691.52" + attribute \src "ls180.v:685.5-685.52" wire \sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:674.5-674.55" + attribute \src "ls180.v:668.5-668.55" wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:675.5-675.54" + attribute \src "ls180.v:669.5-669.54" wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:677.13-677.70" + attribute \src "ls180.v:671.13-671.70" wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:676.6-676.61" + attribute \src "ls180.v:670.6-670.61" wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:673.6-673.56" + attribute \src "ls180.v:667.6-667.56" wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:672.6-672.56" + attribute \src "ls180.v:666.6-666.56" wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:680.6-680.58" + attribute \src "ls180.v:674.6-674.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:681.6-681.57" + attribute \src "ls180.v:675.6-675.57" wire \sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:683.13-683.72" + attribute \src "ls180.v:677.13-677.72" wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:682.6-682.63" + attribute \src "ls180.v:676.6-676.63" wire \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:679.6-679.58" + attribute \src "ls180.v:673.6-673.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:678.6-678.58" + attribute \src "ls180.v:672.6-672.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:688.13-688.66" + attribute \src "ls180.v:682.13-682.66" wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:689.13-689.67" + attribute \src "ls180.v:683.13-683.67" wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:686.6-686.58" + attribute \src "ls180.v:680.6-680.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:687.6-687.64" + attribute \src "ls180.v:681.6-681.64" wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:684.6-684.58" + attribute \src "ls180.v:678.6-678.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:685.6-685.64" + attribute \src "ls180.v:679.6-679.64" wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:694.11-694.61" + attribute \src "ls180.v:688.11-688.61" wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:695.13-695.65" + attribute \src "ls180.v:689.13-689.65" wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:697.13-697.65" + attribute \src "ls180.v:691.13-691.65" wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:696.6-696.55" + attribute \src "ls180.v:690.6-690.55" wire \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:711.6-711.46" + attribute \src "ls180.v:705.6-705.46" wire \sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:712.6-712.45" + attribute \src "ls180.v:706.6-706.45" wire \sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:714.13-714.60" + attribute \src "ls180.v:708.13-708.60" wire width 22 \sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:713.6-713.51" + attribute \src "ls180.v:707.6-707.51" wire \sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:710.6-710.46" + attribute \src "ls180.v:704.6-704.46" wire \sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:709.6-709.46" + attribute \src "ls180.v:703.6-703.46" wire \sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:717.5-717.47" + attribute \src "ls180.v:711.5-711.47" wire \sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:718.5-718.46" + attribute \src "ls180.v:712.5-712.46" wire \sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:720.12-720.61" + attribute \src "ls180.v:714.12-714.61" wire width 22 \sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:719.5-719.52" + attribute \src "ls180.v:713.5-713.52" wire \sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:716.6-716.48" + attribute \src "ls180.v:710.6-710.48" wire \sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:715.5-715.47" + attribute \src "ls180.v:709.5-709.47" wire \sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:663.12-663.44" + attribute \src "ls180.v:657.12-657.44" wire width 13 \sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:664.12-664.45" + attribute \src "ls180.v:658.12-658.45" wire width 2 \sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:665.5-665.39" + attribute \src "ls180.v:659.5-659.39" wire \sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:668.5-668.42" + attribute \src "ls180.v:662.5-662.42" wire \sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:669.5-669.43" + attribute \src "ls180.v:663.5-663.43" wire \sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:670.5-670.44" + attribute \src "ls180.v:664.5-664.44" wire \sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:666.5-666.39" + attribute \src "ls180.v:660.5-660.39" wire \sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:667.5-667.38" + attribute \src "ls180.v:661.5-661.38" wire \sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:662.5-662.33" + attribute \src "ls180.v:656.5-656.33" wire \sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:661.5-661.33" + attribute \src "ls180.v:655.5-655.33" wire \sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:660.5-660.35" + attribute \src "ls180.v:654.5-654.35" wire \sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:659.6-659.36" + attribute \src "ls180.v:653.6-653.36" wire \sdram_bankmachine3_refresh_req - attribute \src "ls180.v:655.13-655.40" + attribute \src "ls180.v:649.13-649.40" wire width 22 \sdram_bankmachine3_req_addr - attribute \src "ls180.v:656.6-656.33" + attribute \src "ls180.v:650.6-650.33" wire \sdram_bankmachine3_req_lock - attribute \src "ls180.v:658.5-658.39" + attribute \src "ls180.v:652.5-652.39" wire \sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:653.6-653.34" + attribute \src "ls180.v:647.6-647.34" wire \sdram_bankmachine3_req_ready - attribute \src "ls180.v:652.6-652.34" + attribute \src "ls180.v:646.6-646.34" wire \sdram_bankmachine3_req_valid - attribute \src "ls180.v:657.5-657.39" + attribute \src "ls180.v:651.5-651.39" wire \sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:654.6-654.31" + attribute \src "ls180.v:648.6-648.31" wire \sdram_bankmachine3_req_we - attribute \src "ls180.v:721.12-721.34" + attribute \src "ls180.v:715.12-715.34" wire width 13 \sdram_bankmachine3_row - attribute \src "ls180.v:725.5-725.33" + attribute \src "ls180.v:719.5-719.33" wire \sdram_bankmachine3_row_close - attribute \src "ls180.v:726.5-726.42" + attribute \src "ls180.v:720.5-720.42" wire \sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:723.6-723.32" + attribute \src "ls180.v:717.6-717.32" wire \sdram_bankmachine3_row_hit - attribute \src "ls180.v:724.5-724.32" + attribute \src "ls180.v:718.5-718.32" wire \sdram_bankmachine3_row_open - attribute \src "ls180.v:722.5-722.34" + attribute \src "ls180.v:716.5-716.34" wire \sdram_bankmachine3_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:733.32-733.64" + attribute \src "ls180.v:727.32-727.64" wire \sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:732.6-732.38" + attribute \src "ls180.v:726.6-726.38" wire \sdram_bankmachine3_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:731.32-731.63" + attribute \src "ls180.v:725.32-725.63" wire \sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:730.6-730.37" + attribute \src "ls180.v:724.6-724.37" wire \sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:729.11-729.43" + attribute \src "ls180.v:723.11-723.43" wire width 3 \sdram_bankmachine3_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:728.32-728.64" + attribute \src "ls180.v:722.32-722.64" wire \sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:727.6-727.38" + attribute \src "ls180.v:721.6-721.38" wire \sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:735.6-735.23" + attribute \src "ls180.v:729.6-729.23" wire \sdram_cas_allowed - attribute \src "ls180.v:16.14-16.25" - wire output 12 \sdram_cas_n - attribute \src "ls180.v:753.6-753.25" + attribute \src "ls180.v:20.14-20.25" + wire output 16 \sdram_cas_n + attribute \src "ls180.v:747.6-747.25" wire \sdram_choose_cmd_ce - attribute \src "ls180.v:742.13-742.43" + attribute \src "ls180.v:736.13-736.43" wire width 13 \sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:743.12-743.43" + attribute \src "ls180.v:737.12-737.43" wire width 2 \sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:744.5-744.37" + attribute \src "ls180.v:738.5-738.37" wire \sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:747.6-747.41" + attribute \src "ls180.v:741.6-741.41" wire \sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:748.6-748.42" + attribute \src "ls180.v:742.6-742.42" wire \sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:749.6-749.43" + attribute \src "ls180.v:743.6-743.43" wire \sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:745.5-745.37" + attribute \src "ls180.v:739.5-739.37" wire \sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:746.5-746.36" + attribute \src "ls180.v:740.5-740.36" wire \sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:741.5-741.31" + attribute \src "ls180.v:735.5-735.31" wire \sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:740.6-740.32" + attribute \src "ls180.v:734.6-734.32" wire \sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:752.11-752.33" + attribute \src "ls180.v:746.11-746.33" wire width 2 \sdram_choose_cmd_grant - attribute \src "ls180.v:751.12-751.36" + attribute \src "ls180.v:745.12-745.36" wire width 4 \sdram_choose_cmd_request - attribute \src "ls180.v:750.11-750.34" + attribute \src "ls180.v:744.11-744.34" wire width 4 \sdram_choose_cmd_valids - attribute \src "ls180.v:739.5-739.36" + attribute \src "ls180.v:733.5-733.36" wire \sdram_choose_cmd_want_activates - attribute \src "ls180.v:738.5-738.31" + attribute \src "ls180.v:732.5-732.31" wire \sdram_choose_cmd_want_cmds - attribute \src "ls180.v:736.5-736.32" + attribute \src "ls180.v:730.5-730.32" wire \sdram_choose_cmd_want_reads - attribute \src "ls180.v:737.5-737.33" + attribute \src "ls180.v:731.5-731.33" wire \sdram_choose_cmd_want_writes - attribute \src "ls180.v:771.6-771.25" + attribute \src "ls180.v:765.6-765.25" wire \sdram_choose_req_ce - attribute \src "ls180.v:760.13-760.43" + attribute \src "ls180.v:754.13-754.43" wire width 13 \sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:761.12-761.43" + attribute \src "ls180.v:755.12-755.43" wire width 2 \sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:762.5-762.37" + attribute \src "ls180.v:756.5-756.37" wire \sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:765.6-765.41" + attribute \src "ls180.v:759.6-759.41" wire \sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:766.6-766.42" + attribute \src "ls180.v:760.6-760.42" wire \sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:767.6-767.43" + attribute \src "ls180.v:761.6-761.43" wire \sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:763.5-763.37" + attribute \src "ls180.v:757.5-757.37" wire \sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:764.5-764.36" + attribute \src "ls180.v:758.5-758.36" wire \sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:759.5-759.31" + attribute \src "ls180.v:753.5-753.31" wire \sdram_choose_req_cmd_ready - attribute \src "ls180.v:758.6-758.32" + attribute \src "ls180.v:752.6-752.32" wire \sdram_choose_req_cmd_valid - attribute \src "ls180.v:770.11-770.33" + attribute \src "ls180.v:764.11-764.33" wire width 2 \sdram_choose_req_grant - attribute \src "ls180.v:769.12-769.36" + attribute \src "ls180.v:763.12-763.36" wire width 4 \sdram_choose_req_request - attribute \src "ls180.v:768.11-768.34" + attribute \src "ls180.v:762.11-762.34" wire width 4 \sdram_choose_req_valids - attribute \src "ls180.v:757.5-757.36" + attribute \src "ls180.v:751.5-751.36" wire \sdram_choose_req_want_activates - attribute \src "ls180.v:756.6-756.32" + attribute \src "ls180.v:750.6-750.32" wire \sdram_choose_req_want_cmds - attribute \src "ls180.v:754.5-754.32" + attribute \src "ls180.v:748.5-748.32" wire \sdram_choose_req_want_reads - attribute \src "ls180.v:755.5-755.33" + attribute \src "ls180.v:749.5-749.33" wire \sdram_choose_req_want_writes - attribute \src "ls180.v:18.14-18.23" - wire output 14 \sdram_cke - attribute \src "ls180.v:315.6-315.17" + attribute \src "ls180.v:22.14-22.23" + wire output 18 \sdram_cke + attribute \src "ls180.v:309.6-309.17" wire \sdram_cke_1 - attribute \src "ls180.v:21.14-21.25" - wire output 17 \sdram_clock - attribute \src "ls180.v:383.5-383.19" + attribute \src "ls180.v:25.14-25.25" + wire output 21 \sdram_clock + attribute \src "ls180.v:377.5-377.19" wire \sdram_cmd_last - attribute \src "ls180.v:384.12-384.31" + attribute \src "ls180.v:378.12-378.31" wire width 13 \sdram_cmd_payload_a - attribute \src "ls180.v:385.11-385.31" + attribute \src "ls180.v:379.11-379.31" wire width 2 \sdram_cmd_payload_ba - attribute \src "ls180.v:386.5-386.26" + attribute \src "ls180.v:380.5-380.26" wire \sdram_cmd_payload_cas - attribute \src "ls180.v:389.5-389.30" + attribute \src "ls180.v:383.5-383.30" wire \sdram_cmd_payload_is_read - attribute \src "ls180.v:390.5-390.31" + attribute \src "ls180.v:384.5-384.31" wire \sdram_cmd_payload_is_write - attribute \src "ls180.v:387.5-387.26" + attribute \src "ls180.v:381.5-381.26" wire \sdram_cmd_payload_ras - attribute \src "ls180.v:388.5-388.25" + attribute \src "ls180.v:382.5-382.25" wire \sdram_cmd_payload_we - attribute \src "ls180.v:382.5-382.20" + attribute \src "ls180.v:376.5-376.20" wire \sdram_cmd_ready - attribute \src "ls180.v:381.5-381.20" + attribute \src "ls180.v:375.5-375.20" wire \sdram_cmd_valid - attribute \src "ls180.v:323.6-323.27" + attribute \src "ls180.v:317.6-317.27" wire \sdram_command_issue_r - attribute \src "ls180.v:322.6-322.28" + attribute \src "ls180.v:316.6-316.28" wire \sdram_command_issue_re - attribute \src "ls180.v:325.5-325.26" + attribute \src "ls180.v:319.5-319.26" wire \sdram_command_issue_w - attribute \src "ls180.v:324.6-324.28" + attribute \src "ls180.v:318.6-318.28" wire \sdram_command_issue_we - attribute \src "ls180.v:321.5-321.21" + attribute \src "ls180.v:315.5-315.21" wire \sdram_command_re - attribute \src "ls180.v:320.11-320.32" + attribute \src "ls180.v:314.11-314.32" wire width 6 \sdram_command_storage - attribute \src "ls180.v:17.14-17.24" - wire output 13 \sdram_cs_n - attribute \src "ls180.v:374.5-374.23" + attribute \src "ls180.v:21.14-21.24" + wire output 17 \sdram_cs_n + attribute \src "ls180.v:368.5-368.23" wire \sdram_dfi_p0_act_n - attribute \src "ls180.v:365.12-365.32" + attribute \src "ls180.v:359.12-359.32" wire width 13 \sdram_dfi_p0_address - attribute \src "ls180.v:366.11-366.28" + attribute \src "ls180.v:360.11-360.28" wire width 2 \sdram_dfi_p0_bank - attribute \src "ls180.v:367.5-367.23" + attribute \src "ls180.v:361.5-361.23" wire \sdram_dfi_p0_cas_n - attribute \src "ls180.v:371.6-371.22" + attribute \src "ls180.v:365.6-365.22" wire \sdram_dfi_p0_cke - attribute \src "ls180.v:368.5-368.22" + attribute \src "ls180.v:362.5-362.22" wire \sdram_dfi_p0_cs_n - attribute \src "ls180.v:372.6-372.22" + attribute \src "ls180.v:366.6-366.22" wire \sdram_dfi_p0_odt - attribute \src "ls180.v:369.5-369.23" + attribute \src "ls180.v:363.5-363.23" wire \sdram_dfi_p0_ras_n - attribute \src "ls180.v:379.13-379.32" + attribute \src "ls180.v:373.13-373.32" wire width 16 \sdram_dfi_p0_rddata - attribute \src "ls180.v:378.5-378.27" + attribute \src "ls180.v:372.5-372.27" wire \sdram_dfi_p0_rddata_en - attribute \src "ls180.v:380.6-380.31" + attribute \src "ls180.v:374.6-374.31" wire \sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:373.6-373.26" + attribute \src "ls180.v:367.6-367.26" wire \sdram_dfi_p0_reset_n - attribute \src "ls180.v:370.5-370.22" + attribute \src "ls180.v:364.5-364.22" wire \sdram_dfi_p0_we_n - attribute \src "ls180.v:375.13-375.32" + attribute \src "ls180.v:369.13-369.32" wire width 16 \sdram_dfi_p0_wrdata - attribute \src "ls180.v:376.5-376.27" + attribute \src "ls180.v:370.5-370.27" wire \sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:377.12-377.36" + attribute \src "ls180.v:371.12-371.36" wire width 2 \sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:20.20-20.28" - wire width 2 output 16 \sdram_dm - attribute \src "ls180.v:11.20-11.30" - wire width 16 input 7 \sdram_dq_i - attribute \src "ls180.v:12.21-12.31" - wire width 16 output 8 \sdram_dq_o - attribute \src "ls180.v:13.14-13.25" - wire output 9 \sdram_dq_oe - attribute \src "ls180.v:789.5-789.14" + attribute \src "ls180.v:24.20-24.28" + wire width 2 output 20 \sdram_dm + attribute \src "ls180.v:15.20-15.30" + wire width 16 input 11 \sdram_dq_i + attribute \src "ls180.v:16.21-16.31" + wire width 16 output 12 \sdram_dq_o + attribute \src "ls180.v:17.14-17.25" + wire output 13 \sdram_dq_oe + attribute \src "ls180.v:783.5-783.14" wire \sdram_en0 - attribute \src "ls180.v:792.5-792.14" + attribute \src "ls180.v:786.5-786.14" wire \sdram_en1 - attribute \src "ls180.v:795.6-795.25" + attribute \src "ls180.v:789.6-789.25" wire \sdram_go_to_refresh - attribute \src "ls180.v:337.13-337.39" + attribute \src "ls180.v:331.13-331.39" wire width 22 \sdram_interface_bank0_addr - attribute \src "ls180.v:338.6-338.32" + attribute \src "ls180.v:332.6-332.32" wire \sdram_interface_bank0_lock - attribute \src "ls180.v:340.6-340.39" + attribute \src "ls180.v:334.6-334.39" wire \sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:335.6-335.33" + attribute \src "ls180.v:329.6-329.33" wire \sdram_interface_bank0_ready - attribute \src "ls180.v:334.6-334.33" + attribute \src "ls180.v:328.6-328.33" wire \sdram_interface_bank0_valid - attribute \src "ls180.v:339.6-339.39" + attribute \src "ls180.v:333.6-333.39" wire \sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:336.6-336.30" + attribute \src "ls180.v:330.6-330.30" wire \sdram_interface_bank0_we - attribute \src "ls180.v:344.13-344.39" + attribute \src "ls180.v:338.13-338.39" wire width 22 \sdram_interface_bank1_addr - attribute \src "ls180.v:345.6-345.32" + attribute \src "ls180.v:339.6-339.32" wire \sdram_interface_bank1_lock - attribute \src "ls180.v:347.6-347.39" + attribute \src "ls180.v:341.6-341.39" wire \sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:342.6-342.33" + attribute \src "ls180.v:336.6-336.33" wire \sdram_interface_bank1_ready - attribute \src "ls180.v:341.6-341.33" + attribute \src "ls180.v:335.6-335.33" wire \sdram_interface_bank1_valid - attribute \src "ls180.v:346.6-346.39" + attribute \src "ls180.v:340.6-340.39" wire \sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:343.6-343.30" + attribute \src "ls180.v:337.6-337.30" wire \sdram_interface_bank1_we - attribute \src "ls180.v:351.13-351.39" + attribute \src "ls180.v:345.13-345.39" wire width 22 \sdram_interface_bank2_addr - attribute \src "ls180.v:352.6-352.32" + attribute \src "ls180.v:346.6-346.32" wire \sdram_interface_bank2_lock - attribute \src "ls180.v:354.6-354.39" + attribute \src "ls180.v:348.6-348.39" wire \sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:349.6-349.33" + attribute \src "ls180.v:343.6-343.33" wire \sdram_interface_bank2_ready - attribute \src "ls180.v:348.6-348.33" + attribute \src "ls180.v:342.6-342.33" wire \sdram_interface_bank2_valid - attribute \src "ls180.v:353.6-353.39" + attribute \src "ls180.v:347.6-347.39" wire \sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:350.6-350.30" + attribute \src "ls180.v:344.6-344.30" wire \sdram_interface_bank2_we - attribute \src "ls180.v:358.13-358.39" + attribute \src "ls180.v:352.13-352.39" wire width 22 \sdram_interface_bank3_addr - attribute \src "ls180.v:359.6-359.32" + attribute \src "ls180.v:353.6-353.32" wire \sdram_interface_bank3_lock - attribute \src "ls180.v:361.6-361.39" + attribute \src "ls180.v:355.6-355.39" wire \sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:356.6-356.33" + attribute \src "ls180.v:350.6-350.33" wire \sdram_interface_bank3_ready - attribute \src "ls180.v:355.6-355.33" + attribute \src "ls180.v:349.6-349.33" wire \sdram_interface_bank3_valid - attribute \src "ls180.v:360.6-360.39" + attribute \src "ls180.v:354.6-354.39" wire \sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:357.6-357.30" + attribute \src "ls180.v:351.6-351.30" wire \sdram_interface_bank3_we - attribute \src "ls180.v:364.13-364.34" + attribute \src "ls180.v:358.13-358.34" wire width 16 \sdram_interface_rdata - attribute \src "ls180.v:362.12-362.33" + attribute \src "ls180.v:356.12-356.33" wire width 16 \sdram_interface_wdata - attribute \src "ls180.v:363.11-363.35" + attribute \src "ls180.v:357.11-357.35" wire width 2 \sdram_interface_wdata_we - attribute \src "ls180.v:275.5-275.24" + attribute \src "ls180.v:269.5-269.24" wire \sdram_inti_p0_act_n - attribute \src "ls180.v:266.13-266.34" + attribute \src "ls180.v:260.13-260.34" wire width 13 \sdram_inti_p0_address - attribute \src "ls180.v:267.12-267.30" + attribute \src "ls180.v:261.12-261.30" wire width 2 \sdram_inti_p0_bank - attribute \src "ls180.v:268.5-268.24" + attribute \src "ls180.v:262.5-262.24" wire \sdram_inti_p0_cas_n - attribute \src "ls180.v:272.6-272.23" + attribute \src "ls180.v:266.6-266.23" wire \sdram_inti_p0_cke - attribute \src "ls180.v:269.5-269.23" + attribute \src "ls180.v:263.5-263.23" wire \sdram_inti_p0_cs_n - attribute \src "ls180.v:273.6-273.23" + attribute \src "ls180.v:267.6-267.23" wire \sdram_inti_p0_odt - attribute \src "ls180.v:270.5-270.24" + attribute \src "ls180.v:264.5-264.24" wire \sdram_inti_p0_ras_n - attribute \src "ls180.v:280.12-280.32" + attribute \src "ls180.v:274.12-274.32" wire width 16 \sdram_inti_p0_rddata - attribute \src "ls180.v:279.6-279.29" + attribute \src "ls180.v:273.6-273.29" wire \sdram_inti_p0_rddata_en - attribute \src "ls180.v:281.5-281.31" + attribute \src "ls180.v:275.5-275.31" wire \sdram_inti_p0_rddata_valid - attribute \src "ls180.v:274.6-274.27" + attribute \src "ls180.v:268.6-268.27" wire \sdram_inti_p0_reset_n - attribute \src "ls180.v:271.5-271.23" + attribute \src "ls180.v:265.5-265.23" wire \sdram_inti_p0_we_n - attribute \src "ls180.v:276.13-276.33" + attribute \src "ls180.v:270.13-270.33" wire width 16 \sdram_inti_p0_wrdata - attribute \src "ls180.v:277.6-277.29" + attribute \src "ls180.v:271.6-271.29" wire \sdram_inti_p0_wrdata_en - attribute \src "ls180.v:278.12-278.37" + attribute \src "ls180.v:272.12-272.37" wire width 2 \sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:307.5-307.26" + attribute \src "ls180.v:301.5-301.26" wire \sdram_master_p0_act_n - attribute \src "ls180.v:298.12-298.35" + attribute \src "ls180.v:292.12-292.35" wire width 13 \sdram_master_p0_address - attribute \src "ls180.v:299.11-299.31" + attribute \src "ls180.v:293.11-293.31" wire width 2 \sdram_master_p0_bank - attribute \src "ls180.v:300.5-300.26" + attribute \src "ls180.v:294.5-294.26" wire \sdram_master_p0_cas_n - attribute \src "ls180.v:304.5-304.24" + attribute \src "ls180.v:298.5-298.24" wire \sdram_master_p0_cke - attribute \src "ls180.v:301.5-301.25" + attribute \src "ls180.v:295.5-295.25" wire \sdram_master_p0_cs_n - attribute \src "ls180.v:305.5-305.24" + attribute \src "ls180.v:299.5-299.24" wire \sdram_master_p0_odt - attribute \src "ls180.v:302.5-302.26" + attribute \src "ls180.v:296.5-296.26" wire \sdram_master_p0_ras_n - attribute \src "ls180.v:312.13-312.35" + attribute \src "ls180.v:306.13-306.35" wire width 16 \sdram_master_p0_rddata - attribute \src "ls180.v:311.5-311.30" + attribute \src "ls180.v:305.5-305.30" wire \sdram_master_p0_rddata_en - attribute \src "ls180.v:313.6-313.34" + attribute \src "ls180.v:307.6-307.34" wire \sdram_master_p0_rddata_valid - attribute \src "ls180.v:306.5-306.28" + attribute \src "ls180.v:300.5-300.28" wire \sdram_master_p0_reset_n - attribute \src "ls180.v:303.5-303.25" + attribute \src "ls180.v:297.5-297.25" wire \sdram_master_p0_we_n - attribute \src "ls180.v:308.12-308.34" + attribute \src "ls180.v:302.12-302.34" wire width 16 \sdram_master_p0_wrdata - attribute \src "ls180.v:309.5-309.30" + attribute \src "ls180.v:303.5-303.30" wire \sdram_master_p0_wrdata_en - attribute \src "ls180.v:310.11-310.38" + attribute \src "ls180.v:304.11-304.38" wire width 2 \sdram_master_p0_wrdata_mask - attribute \src "ls180.v:790.6-790.21" + attribute \src "ls180.v:784.6-784.21" wire \sdram_max_time0 - attribute \src "ls180.v:793.6-793.21" + attribute \src "ls180.v:787.6-787.21" wire \sdram_max_time1 - attribute \src "ls180.v:772.12-772.23" + attribute \src "ls180.v:766.12-766.23" wire width 13 \sdram_nop_a - attribute \src "ls180.v:773.11-773.23" + attribute \src "ls180.v:767.11-767.23" wire width 2 \sdram_nop_ba - attribute \src "ls180.v:316.6-316.15" + attribute \src "ls180.v:310.6-310.15" wire \sdram_odt - attribute \src "ls180.v:399.5-399.26" + attribute \src "ls180.v:393.5-393.26" wire \sdram_postponer_count - attribute \src "ls180.v:397.6-397.27" + attribute \src "ls180.v:391.6-391.27" wire \sdram_postponer_req_i - attribute \src "ls180.v:398.5-398.26" + attribute \src "ls180.v:392.5-392.26" wire \sdram_postponer_req_o - attribute \src "ls180.v:734.6-734.23" + attribute \src "ls180.v:728.6-728.23" wire \sdram_ras_allowed - attribute \src "ls180.v:15.14-15.25" - wire output 11 \sdram_ras_n - attribute \src "ls180.v:319.5-319.13" + attribute \src "ls180.v:19.14-19.25" + wire output 15 \sdram_ras_n + attribute \src "ls180.v:313.5-313.13" wire \sdram_re - attribute \src "ls180.v:787.6-787.26" + attribute \src "ls180.v:781.6-781.26" wire \sdram_read_available - attribute \src "ls180.v:317.6-317.19" + attribute \src "ls180.v:311.6-311.19" wire \sdram_reset_n - attribute \src "ls180.v:314.6-314.15" + attribute \src "ls180.v:308.6-308.15" wire \sdram_sel - attribute \src "ls180.v:405.5-405.26" + attribute \src "ls180.v:399.5-399.26" wire \sdram_sequencer_count - attribute \src "ls180.v:404.11-404.34" + attribute \src "ls180.v:398.11-398.34" wire width 4 \sdram_sequencer_counter - attribute \src "ls180.v:401.6-401.27" + attribute \src "ls180.v:395.6-395.27" wire \sdram_sequencer_done0 - attribute \src "ls180.v:403.5-403.26" + attribute \src "ls180.v:397.5-397.26" wire \sdram_sequencer_done1 - attribute \src "ls180.v:400.5-400.27" + attribute \src "ls180.v:394.5-394.27" wire \sdram_sequencer_start0 - attribute \src "ls180.v:402.6-402.28" + attribute \src "ls180.v:396.6-396.28" wire \sdram_sequencer_start1 - attribute \src "ls180.v:291.6-291.26" + attribute \src "ls180.v:285.6-285.26" wire \sdram_slave_p0_act_n - attribute \src "ls180.v:282.13-282.35" + attribute \src "ls180.v:276.13-276.35" wire width 13 \sdram_slave_p0_address - attribute \src "ls180.v:283.12-283.31" + attribute \src "ls180.v:277.12-277.31" wire width 2 \sdram_slave_p0_bank - attribute \src "ls180.v:284.6-284.26" + attribute \src "ls180.v:278.6-278.26" wire \sdram_slave_p0_cas_n - attribute \src "ls180.v:288.6-288.24" + attribute \src "ls180.v:282.6-282.24" wire \sdram_slave_p0_cke - attribute \src "ls180.v:285.6-285.25" + attribute \src "ls180.v:279.6-279.25" wire \sdram_slave_p0_cs_n - attribute \src "ls180.v:289.6-289.24" + attribute \src "ls180.v:283.6-283.24" wire \sdram_slave_p0_odt - attribute \src "ls180.v:286.6-286.26" + attribute \src "ls180.v:280.6-280.26" wire \sdram_slave_p0_ras_n - attribute \src "ls180.v:296.12-296.33" + attribute \src "ls180.v:290.12-290.33" wire width 16 \sdram_slave_p0_rddata - attribute \src "ls180.v:295.6-295.30" + attribute \src "ls180.v:289.6-289.30" wire \sdram_slave_p0_rddata_en - attribute \src "ls180.v:297.5-297.32" + attribute \src "ls180.v:291.5-291.32" wire \sdram_slave_p0_rddata_valid - attribute \src "ls180.v:290.6-290.28" + attribute \src "ls180.v:284.6-284.28" wire \sdram_slave_p0_reset_n - attribute \src "ls180.v:287.6-287.25" + attribute \src "ls180.v:281.6-281.25" wire \sdram_slave_p0_we_n - attribute \src "ls180.v:292.13-292.34" + attribute \src "ls180.v:286.13-286.34" wire width 16 \sdram_slave_p0_wrdata - attribute \src "ls180.v:293.6-293.30" + attribute \src "ls180.v:287.6-287.30" wire \sdram_slave_p0_wrdata_en - attribute \src "ls180.v:294.12-294.38" + attribute \src "ls180.v:288.12-288.38" wire width 2 \sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:332.12-332.24" + attribute \src "ls180.v:326.12-326.24" wire width 16 \sdram_status - attribute \src "ls180.v:775.5-775.19" + attribute \src "ls180.v:769.5-769.19" wire \sdram_steerer0 - attribute \src "ls180.v:776.5-776.19" + attribute \src "ls180.v:770.5-770.19" wire \sdram_steerer1 - attribute \src "ls180.v:774.11-774.28" + attribute \src "ls180.v:768.11-768.28" wire width 2 \sdram_steerer_sel - attribute \src "ls180.v:318.11-318.24" + attribute \src "ls180.v:312.11-312.24" wire width 4 \sdram_storage - attribute \src "ls180.v:783.5-783.24" + attribute \src "ls180.v:777.5-777.24" wire \sdram_tccdcon_count attribute \no_retiming "true" - attribute \src "ls180.v:782.32-782.51" + attribute \src "ls180.v:776.32-776.51" wire \sdram_tccdcon_ready - attribute \src "ls180.v:781.6-781.25" + attribute \src "ls180.v:775.6-775.25" wire \sdram_tccdcon_valid attribute \no_retiming "true" - attribute \src "ls180.v:780.32-780.51" + attribute \src "ls180.v:774.32-774.51" wire \sdram_tfawcon_ready - attribute \src "ls180.v:779.6-779.25" + attribute \src "ls180.v:773.6-773.25" wire \sdram_tfawcon_valid - attribute \src "ls180.v:791.11-791.22" + attribute \src "ls180.v:785.11-785.22" wire width 5 \sdram_time0 - attribute \src "ls180.v:794.11-794.22" + attribute \src "ls180.v:788.11-788.22" wire width 4 \sdram_time1 - attribute \src "ls180.v:394.12-394.30" + attribute \src "ls180.v:388.12-388.30" wire width 10 \sdram_timer_count0 - attribute \src "ls180.v:396.11-396.29" + attribute \src "ls180.v:390.11-390.29" wire width 10 \sdram_timer_count1 - attribute \src "ls180.v:393.6-393.23" + attribute \src "ls180.v:387.6-387.23" wire \sdram_timer_done0 - attribute \src "ls180.v:395.6-395.23" + attribute \src "ls180.v:389.6-389.23" wire \sdram_timer_done1 - attribute \src "ls180.v:392.6-392.22" + attribute \src "ls180.v:386.6-386.22" wire \sdram_timer_wait attribute \no_retiming "true" - attribute \src "ls180.v:778.32-778.51" + attribute \src "ls180.v:772.32-772.51" wire \sdram_trrdcon_ready - attribute \src "ls180.v:777.6-777.25" + attribute \src "ls180.v:771.6-771.25" wire \sdram_trrdcon_valid - attribute \src "ls180.v:786.11-786.30" + attribute \src "ls180.v:780.11-780.30" wire width 3 \sdram_twtrcon_count attribute \no_retiming "true" - attribute \src "ls180.v:785.32-785.51" + attribute \src "ls180.v:779.32-779.51" wire \sdram_twtrcon_ready - attribute \src "ls180.v:784.6-784.25" + attribute \src "ls180.v:778.6-778.25" wire \sdram_twtrcon_valid - attribute \src "ls180.v:391.6-391.25" + attribute \src "ls180.v:385.6-385.25" wire \sdram_wants_refresh - attribute \src "ls180.v:333.6-333.14" + attribute \src "ls180.v:327.6-327.14" wire \sdram_we - attribute \src "ls180.v:14.14-14.24" - wire output 10 \sdram_we_n - attribute \src "ls180.v:331.5-331.20" + attribute \src "ls180.v:18.14-18.24" + wire output 14 \sdram_we_n + attribute \src "ls180.v:325.5-325.20" wire \sdram_wrdata_re - attribute \src "ls180.v:330.12-330.32" + attribute \src "ls180.v:324.12-324.32" wire width 16 \sdram_wrdata_storage - attribute \src "ls180.v:788.6-788.27" + attribute \src "ls180.v:782.6-782.27" wire \sdram_write_available - attribute \src "ls180.v:1388.6-1388.15" + attribute \src "ls180.v:1382.6-1382.15" wire \sdrio_clk - attribute \src "ls180.v:1389.6-1389.17" + attribute \src "ls180.v:1383.6-1383.17" wire \sdrio_clk_1 - attribute \src "ls180.v:1398.6-1398.18" + attribute \src "ls180.v:1392.6-1392.18" wire \sdrio_clk_10 - attribute \src "ls180.v:1490.6-1490.19" + attribute \src "ls180.v:1484.6-1484.19" wire \sdrio_clk_100 - attribute \src "ls180.v:1491.6-1491.19" + attribute \src "ls180.v:1485.6-1485.19" wire \sdrio_clk_101 - attribute \src "ls180.v:1492.6-1492.19" + attribute \src "ls180.v:1486.6-1486.19" wire \sdrio_clk_102 - attribute \src "ls180.v:1493.6-1493.19" + attribute \src "ls180.v:1487.6-1487.19" wire \sdrio_clk_103 - attribute \src "ls180.v:1399.6-1399.18" + attribute \src "ls180.v:1393.6-1393.18" wire \sdrio_clk_11 - attribute \src "ls180.v:1400.6-1400.18" + attribute \src "ls180.v:1394.6-1394.18" wire \sdrio_clk_12 - attribute \src "ls180.v:1401.6-1401.18" + attribute \src "ls180.v:1395.6-1395.18" wire \sdrio_clk_13 - attribute \src "ls180.v:1402.6-1402.18" + attribute \src "ls180.v:1396.6-1396.18" wire \sdrio_clk_14 - attribute \src "ls180.v:1403.6-1403.18" + attribute \src "ls180.v:1397.6-1397.18" wire \sdrio_clk_15 - attribute \src "ls180.v:1404.6-1404.18" + attribute \src "ls180.v:1398.6-1398.18" wire \sdrio_clk_16 - attribute \src "ls180.v:1405.6-1405.18" + attribute \src "ls180.v:1399.6-1399.18" wire \sdrio_clk_17 - attribute \src "ls180.v:1406.6-1406.18" + attribute \src "ls180.v:1400.6-1400.18" wire \sdrio_clk_18 - attribute \src "ls180.v:1407.6-1407.18" + attribute \src "ls180.v:1401.6-1401.18" wire \sdrio_clk_19 - attribute \src "ls180.v:1390.6-1390.17" + attribute \src "ls180.v:1384.6-1384.17" wire \sdrio_clk_2 - attribute \src "ls180.v:1408.6-1408.18" + attribute \src "ls180.v:1402.6-1402.18" wire \sdrio_clk_20 - attribute \src "ls180.v:1409.6-1409.18" + attribute \src "ls180.v:1403.6-1403.18" wire \sdrio_clk_21 - attribute \src "ls180.v:1410.6-1410.18" + attribute \src "ls180.v:1404.6-1404.18" wire \sdrio_clk_22 - attribute \src "ls180.v:1411.6-1411.18" + attribute \src "ls180.v:1405.6-1405.18" wire \sdrio_clk_23 - attribute \src "ls180.v:1412.6-1412.18" + attribute \src "ls180.v:1406.6-1406.18" wire \sdrio_clk_24 - attribute \src "ls180.v:1413.6-1413.18" + attribute \src "ls180.v:1407.6-1407.18" wire \sdrio_clk_25 - attribute \src "ls180.v:1414.6-1414.18" + attribute \src "ls180.v:1408.6-1408.18" wire \sdrio_clk_26 - attribute \src "ls180.v:1415.6-1415.18" + attribute \src "ls180.v:1409.6-1409.18" wire \sdrio_clk_27 - attribute \src "ls180.v:1416.6-1416.18" + attribute \src "ls180.v:1410.6-1410.18" wire \sdrio_clk_28 - attribute \src "ls180.v:1417.6-1417.18" + attribute \src "ls180.v:1411.6-1411.18" wire \sdrio_clk_29 - attribute \src "ls180.v:1391.6-1391.17" + attribute \src "ls180.v:1385.6-1385.17" wire \sdrio_clk_3 - attribute \src "ls180.v:1418.6-1418.18" + attribute \src "ls180.v:1412.6-1412.18" wire \sdrio_clk_30 - attribute \src "ls180.v:1419.6-1419.18" + attribute \src "ls180.v:1413.6-1413.18" wire \sdrio_clk_31 - attribute \src "ls180.v:1420.6-1420.18" + attribute \src "ls180.v:1414.6-1414.18" wire \sdrio_clk_32 - attribute \src "ls180.v:1421.6-1421.18" + attribute \src "ls180.v:1415.6-1415.18" wire \sdrio_clk_33 - attribute \src "ls180.v:1422.6-1422.18" + attribute \src "ls180.v:1416.6-1416.18" wire \sdrio_clk_34 - attribute \src "ls180.v:1423.6-1423.18" + attribute \src "ls180.v:1417.6-1417.18" wire \sdrio_clk_35 - attribute \src "ls180.v:1424.6-1424.18" + attribute \src "ls180.v:1418.6-1418.18" wire \sdrio_clk_36 - attribute \src "ls180.v:1425.6-1425.18" + attribute \src "ls180.v:1419.6-1419.18" wire \sdrio_clk_37 - attribute \src "ls180.v:1426.6-1426.18" + attribute \src "ls180.v:1420.6-1420.18" wire \sdrio_clk_38 - attribute \src "ls180.v:1427.6-1427.18" + attribute \src "ls180.v:1421.6-1421.18" wire \sdrio_clk_39 - attribute \src "ls180.v:1392.6-1392.17" + attribute \src "ls180.v:1386.6-1386.17" wire \sdrio_clk_4 - attribute \src "ls180.v:1428.6-1428.18" + attribute \src "ls180.v:1422.6-1422.18" wire \sdrio_clk_40 - attribute \src "ls180.v:1429.6-1429.18" + attribute \src "ls180.v:1423.6-1423.18" wire \sdrio_clk_41 - attribute \src "ls180.v:1430.6-1430.18" + attribute \src "ls180.v:1424.6-1424.18" wire \sdrio_clk_42 - attribute \src "ls180.v:1431.6-1431.18" + attribute \src "ls180.v:1425.6-1425.18" wire \sdrio_clk_43 - attribute \src "ls180.v:1432.6-1432.18" + attribute \src "ls180.v:1426.6-1426.18" wire \sdrio_clk_44 - attribute \src "ls180.v:1433.6-1433.18" + attribute \src "ls180.v:1427.6-1427.18" wire \sdrio_clk_45 - attribute \src "ls180.v:1434.6-1434.18" + attribute \src "ls180.v:1428.6-1428.18" wire \sdrio_clk_46 - attribute \src "ls180.v:1435.6-1435.18" + attribute \src "ls180.v:1429.6-1429.18" wire \sdrio_clk_47 - attribute \src "ls180.v:1436.6-1436.18" + attribute \src "ls180.v:1430.6-1430.18" wire \sdrio_clk_48 - attribute \src "ls180.v:1437.6-1437.18" + attribute \src "ls180.v:1431.6-1431.18" wire \sdrio_clk_49 - attribute \src "ls180.v:1393.6-1393.17" + attribute \src "ls180.v:1387.6-1387.17" wire \sdrio_clk_5 - attribute \src "ls180.v:1438.6-1438.18" + attribute \src "ls180.v:1432.6-1432.18" wire \sdrio_clk_50 - attribute \src "ls180.v:1439.6-1439.18" + attribute \src "ls180.v:1433.6-1433.18" wire \sdrio_clk_51 - attribute \src "ls180.v:1440.6-1440.18" + attribute \src "ls180.v:1434.6-1434.18" wire \sdrio_clk_52 - attribute \src "ls180.v:1441.6-1441.18" + attribute \src "ls180.v:1435.6-1435.18" wire \sdrio_clk_53 - attribute \src "ls180.v:1442.6-1442.18" + attribute \src "ls180.v:1436.6-1436.18" wire \sdrio_clk_54 - attribute \src "ls180.v:1443.6-1443.18" + attribute \src "ls180.v:1437.6-1437.18" wire \sdrio_clk_55 - attribute \src "ls180.v:1446.6-1446.18" + attribute \src "ls180.v:1440.6-1440.18" wire \sdrio_clk_56 - attribute \src "ls180.v:1447.6-1447.18" + attribute \src "ls180.v:1441.6-1441.18" wire \sdrio_clk_57 - attribute \src "ls180.v:1448.6-1448.18" + attribute \src "ls180.v:1442.6-1442.18" wire \sdrio_clk_58 - attribute \src "ls180.v:1449.6-1449.18" + attribute \src "ls180.v:1443.6-1443.18" wire \sdrio_clk_59 - attribute \src "ls180.v:1394.6-1394.17" + attribute \src "ls180.v:1388.6-1388.17" wire \sdrio_clk_6 - attribute \src "ls180.v:1450.6-1450.18" + attribute \src "ls180.v:1444.6-1444.18" wire \sdrio_clk_60 - attribute \src "ls180.v:1451.6-1451.18" + attribute \src "ls180.v:1445.6-1445.18" wire \sdrio_clk_61 - attribute \src "ls180.v:1452.6-1452.18" + attribute \src "ls180.v:1446.6-1446.18" wire \sdrio_clk_62 - attribute \src "ls180.v:1453.6-1453.18" + attribute \src "ls180.v:1447.6-1447.18" wire \sdrio_clk_63 - attribute \src "ls180.v:1454.6-1454.18" + attribute \src "ls180.v:1448.6-1448.18" wire \sdrio_clk_64 - attribute \src "ls180.v:1455.6-1455.18" + attribute \src "ls180.v:1449.6-1449.18" wire \sdrio_clk_65 - attribute \src "ls180.v:1456.6-1456.18" + attribute \src "ls180.v:1450.6-1450.18" wire \sdrio_clk_66 - attribute \src "ls180.v:1457.6-1457.18" + attribute \src "ls180.v:1451.6-1451.18" wire \sdrio_clk_67 - attribute \src "ls180.v:1458.6-1458.18" + attribute \src "ls180.v:1452.6-1452.18" wire \sdrio_clk_68 - attribute \src "ls180.v:1459.6-1459.18" + attribute \src "ls180.v:1453.6-1453.18" wire \sdrio_clk_69 - attribute \src "ls180.v:1395.6-1395.17" + attribute \src "ls180.v:1389.6-1389.17" wire \sdrio_clk_7 - attribute \src "ls180.v:1460.6-1460.18" + attribute \src "ls180.v:1454.6-1454.18" wire \sdrio_clk_70 - attribute \src "ls180.v:1461.6-1461.18" + attribute \src "ls180.v:1455.6-1455.18" wire \sdrio_clk_71 - attribute \src "ls180.v:1462.6-1462.18" + attribute \src "ls180.v:1456.6-1456.18" wire \sdrio_clk_72 - attribute \src "ls180.v:1463.6-1463.18" + attribute \src "ls180.v:1457.6-1457.18" wire \sdrio_clk_73 - attribute \src "ls180.v:1464.6-1464.18" + attribute \src "ls180.v:1458.6-1458.18" wire \sdrio_clk_74 - attribute \src "ls180.v:1465.6-1465.18" + attribute \src "ls180.v:1459.6-1459.18" wire \sdrio_clk_75 - attribute \src "ls180.v:1466.6-1466.18" + attribute \src "ls180.v:1460.6-1460.18" wire \sdrio_clk_76 - attribute \src "ls180.v:1467.6-1467.18" + attribute \src "ls180.v:1461.6-1461.18" wire \sdrio_clk_77 - attribute \src "ls180.v:1468.6-1468.18" + attribute \src "ls180.v:1462.6-1462.18" wire \sdrio_clk_78 - attribute \src "ls180.v:1469.6-1469.18" + attribute \src "ls180.v:1463.6-1463.18" wire \sdrio_clk_79 - attribute \src "ls180.v:1396.6-1396.17" + attribute \src "ls180.v:1390.6-1390.17" wire \sdrio_clk_8 - attribute \src "ls180.v:1470.6-1470.18" + attribute \src "ls180.v:1464.6-1464.18" wire \sdrio_clk_80 - attribute \src "ls180.v:1471.6-1471.18" + attribute \src "ls180.v:1465.6-1465.18" wire \sdrio_clk_81 - attribute \src "ls180.v:1472.6-1472.18" + attribute \src "ls180.v:1466.6-1466.18" wire \sdrio_clk_82 - attribute \src "ls180.v:1473.6-1473.18" + attribute \src "ls180.v:1467.6-1467.18" wire \sdrio_clk_83 - attribute \src "ls180.v:1474.6-1474.18" + attribute \src "ls180.v:1468.6-1468.18" wire \sdrio_clk_84 - attribute \src "ls180.v:1475.6-1475.18" + attribute \src "ls180.v:1469.6-1469.18" wire \sdrio_clk_85 - attribute \src "ls180.v:1476.6-1476.18" + attribute \src "ls180.v:1470.6-1470.18" wire \sdrio_clk_86 - attribute \src "ls180.v:1477.6-1477.18" + attribute \src "ls180.v:1471.6-1471.18" wire \sdrio_clk_87 - attribute \src "ls180.v:1478.6-1478.18" + attribute \src "ls180.v:1472.6-1472.18" wire \sdrio_clk_88 - attribute \src "ls180.v:1479.6-1479.18" + attribute \src "ls180.v:1473.6-1473.18" wire \sdrio_clk_89 - attribute \src "ls180.v:1397.6-1397.17" + attribute \src "ls180.v:1391.6-1391.17" wire \sdrio_clk_9 - attribute \src "ls180.v:1480.6-1480.18" + attribute \src "ls180.v:1474.6-1474.18" wire \sdrio_clk_90 - attribute \src "ls180.v:1481.6-1481.18" + attribute \src "ls180.v:1475.6-1475.18" wire \sdrio_clk_91 - attribute \src "ls180.v:1482.6-1482.18" + attribute \src "ls180.v:1476.6-1476.18" wire \sdrio_clk_92 - attribute \src "ls180.v:1483.6-1483.18" + attribute \src "ls180.v:1477.6-1477.18" wire \sdrio_clk_93 - attribute \src "ls180.v:1484.6-1484.18" + attribute \src "ls180.v:1478.6-1478.18" wire \sdrio_clk_94 - attribute \src "ls180.v:1485.6-1485.18" + attribute \src "ls180.v:1479.6-1479.18" wire \sdrio_clk_95 - attribute \src "ls180.v:1486.6-1486.18" + attribute \src "ls180.v:1480.6-1480.18" wire \sdrio_clk_96 - attribute \src "ls180.v:1487.6-1487.18" + attribute \src "ls180.v:1481.6-1481.18" wire \sdrio_clk_97 - attribute \src "ls180.v:1488.6-1488.18" + attribute \src "ls180.v:1482.6-1482.18" wire \sdrio_clk_98 - attribute \src "ls180.v:1489.6-1489.18" + attribute \src "ls180.v:1483.6-1483.18" wire \sdrio_clk_99 - attribute \src "ls180.v:26.14-26.27" - wire output 22 \spimaster_clk - attribute \src "ls180.v:28.14-28.28" - wire output 24 \spimaster_cs_n - attribute \src "ls180.v:29.13-29.27" - wire input 25 \spimaster_miso - attribute \src "ls180.v:27.14-27.28" - wire output 23 \spimaster_mosi - attribute \src "ls180.v:1023.11-1023.47" + attribute \src "ls180.v:29.14-29.27" + wire output 25 \spimaster_clk + attribute \src "ls180.v:31.14-31.28" + wire output 27 \spimaster_cs_n + attribute \src "ls180.v:32.13-32.27" + wire input 28 \spimaster_miso + attribute \src "ls180.v:30.14-30.28" + wire output 26 \spimaster_mosi + attribute \src "ls180.v:1017.11-1017.47" wire width 3 \subfragments_bankmachine0_next_state - attribute \src "ls180.v:1022.11-1022.42" + attribute \src "ls180.v:1016.11-1016.42" wire width 3 \subfragments_bankmachine0_state - attribute \src "ls180.v:1025.11-1025.47" + attribute \src "ls180.v:1019.11-1019.47" wire width 3 \subfragments_bankmachine1_next_state - attribute \src "ls180.v:1024.11-1024.42" + attribute \src "ls180.v:1018.11-1018.42" wire width 3 \subfragments_bankmachine1_state - attribute \src "ls180.v:1027.11-1027.47" + attribute \src "ls180.v:1021.11-1021.47" wire width 3 \subfragments_bankmachine2_next_state - attribute \src "ls180.v:1026.11-1026.42" + attribute \src "ls180.v:1020.11-1020.42" wire width 3 \subfragments_bankmachine2_state - attribute \src "ls180.v:1029.11-1029.47" + attribute \src "ls180.v:1023.11-1023.47" wire width 3 \subfragments_bankmachine3_next_state - attribute \src "ls180.v:1028.11-1028.42" + attribute \src "ls180.v:1022.11-1022.42" wire width 3 \subfragments_bankmachine3_state - attribute \src "ls180.v:1009.5-1009.39" + attribute \src "ls180.v:1003.5-1003.39" wire \subfragments_converter0_next_state - attribute \src "ls180.v:1008.5-1008.34" + attribute \src "ls180.v:1002.5-1002.34" wire \subfragments_converter0_state - attribute \src "ls180.v:1013.5-1013.39" + attribute \src "ls180.v:1007.5-1007.39" wire \subfragments_converter1_next_state - attribute \src "ls180.v:1012.5-1012.34" + attribute \src "ls180.v:1006.5-1006.34" wire \subfragments_converter1_state - attribute \src "ls180.v:1017.5-1017.39" + attribute \src "ls180.v:1011.5-1011.39" wire \subfragments_converter2_next_state - attribute \src "ls180.v:1016.5-1016.34" + attribute \src "ls180.v:1010.5-1010.34" wire \subfragments_converter2_state - attribute \src "ls180.v:1044.5-1044.25" + attribute \src "ls180.v:1038.5-1038.25" wire \subfragments_locked0 - attribute \src "ls180.v:1045.5-1045.25" + attribute \src "ls180.v:1039.5-1039.25" wire \subfragments_locked1 - attribute \src "ls180.v:1046.5-1046.25" + attribute \src "ls180.v:1040.5-1040.25" wire \subfragments_locked2 - attribute \src "ls180.v:1047.5-1047.25" + attribute \src "ls180.v:1041.5-1041.25" wire \subfragments_locked3 - attribute \src "ls180.v:1031.11-1031.46" + attribute \src "ls180.v:1025.11-1025.46" wire width 3 \subfragments_multiplexer_next_state - attribute \src "ls180.v:1030.11-1030.41" + attribute \src "ls180.v:1024.11-1024.41" wire width 3 \subfragments_multiplexer_state - attribute \src "ls180.v:1049.5-1049.41" + attribute \src "ls180.v:1043.5-1043.41" wire \subfragments_new_master_rdata_valid0 - attribute \src "ls180.v:1050.5-1050.41" + attribute \src "ls180.v:1044.5-1044.41" wire \subfragments_new_master_rdata_valid1 - attribute \src "ls180.v:1051.5-1051.41" + attribute \src "ls180.v:1045.5-1045.41" wire \subfragments_new_master_rdata_valid2 - attribute \src "ls180.v:1052.5-1052.41" + attribute \src "ls180.v:1046.5-1046.41" wire \subfragments_new_master_rdata_valid3 - attribute \src "ls180.v:1048.5-1048.40" + attribute \src "ls180.v:1042.5-1042.40" wire \subfragments_new_master_wdata_ready - attribute \src "ls180.v:1054.5-1054.28" + attribute \src "ls180.v:1048.5-1048.28" wire \subfragments_next_state - attribute \src "ls180.v:1021.11-1021.44" + attribute \src "ls180.v:1015.11-1015.44" wire width 2 \subfragments_refresher_next_state - attribute \src "ls180.v:1020.11-1020.39" + attribute \src "ls180.v:1014.11-1014.39" wire width 2 \subfragments_refresher_state - attribute \src "ls180.v:1034.6-1034.33" + attribute \src "ls180.v:1028.6-1028.33" wire \subfragments_roundrobin0_ce - attribute \src "ls180.v:1033.6-1033.36" + attribute \src "ls180.v:1027.6-1027.36" wire \subfragments_roundrobin0_grant - attribute \src "ls180.v:1032.6-1032.38" + attribute \src "ls180.v:1026.6-1026.38" wire \subfragments_roundrobin0_request - attribute \src "ls180.v:1037.6-1037.33" + attribute \src "ls180.v:1031.6-1031.33" wire \subfragments_roundrobin1_ce - attribute \src "ls180.v:1036.6-1036.36" + attribute \src "ls180.v:1030.6-1030.36" wire \subfragments_roundrobin1_grant - attribute \src "ls180.v:1035.6-1035.38" + attribute \src "ls180.v:1029.6-1029.38" wire \subfragments_roundrobin1_request - attribute \src "ls180.v:1040.6-1040.33" + attribute \src "ls180.v:1034.6-1034.33" wire \subfragments_roundrobin2_ce - attribute \src "ls180.v:1039.6-1039.36" + attribute \src "ls180.v:1033.6-1033.36" wire \subfragments_roundrobin2_grant - attribute \src "ls180.v:1038.6-1038.38" + attribute \src "ls180.v:1032.6-1032.38" wire \subfragments_roundrobin2_request - attribute \src "ls180.v:1043.6-1043.33" + attribute \src "ls180.v:1037.6-1037.33" wire \subfragments_roundrobin3_ce - attribute \src "ls180.v:1042.6-1042.36" + attribute \src "ls180.v:1036.6-1036.36" wire \subfragments_roundrobin3_grant - attribute \src "ls180.v:1041.6-1041.38" + attribute \src "ls180.v:1035.6-1035.38" wire \subfragments_roundrobin3_request - attribute \src "ls180.v:1053.5-1053.23" + attribute \src "ls180.v:1047.5-1047.23" wire \subfragments_state attribute \src "ls180.v:33.13-33.20" wire input 29 \sys_clk - attribute \src "ls180.v:245.6-245.15" + attribute \src "ls180.v:239.6-239.15" wire \sys_clk_1 - attribute \src "ls180.v:35.19-35.31" - wire width 2 input 31 \sys_clksel_i - attribute \src "ls180.v:36.14-36.26" - wire output 32 \sys_pll_18_o - attribute \src "ls180.v:37.14-37.27" - wire output 33 \sys_pll_lck_o attribute \src "ls180.v:34.13-34.20" wire input 30 \sys_rst - attribute \src "ls180.v:246.6-246.15" + attribute \src "ls180.v:240.6-240.15" wire \sys_rst_1 - attribute \src "ls180.v:1349.5-1349.19" + attribute \src "ls180.v:1343.5-1343.19" wire \t_array_muxed0 - attribute \src "ls180.v:1350.5-1350.19" + attribute \src "ls180.v:1344.5-1344.19" wire \t_array_muxed1 - attribute \src "ls180.v:1351.5-1351.19" + attribute \src "ls180.v:1345.5-1345.19" wire \t_array_muxed2 - attribute \src "ls180.v:1358.5-1358.19" + attribute \src "ls180.v:1352.5-1352.19" wire \t_array_muxed3 - attribute \src "ls180.v:1359.5-1359.19" + attribute \src "ls180.v:1353.5-1353.19" wire \t_array_muxed4 - attribute \src "ls180.v:1360.5-1360.19" + attribute \src "ls180.v:1354.5-1354.19" wire \t_array_muxed5 - attribute \src "ls180.v:873.5-873.13" + attribute \src "ls180.v:867.5-867.13" wire \tx_clear - attribute \src "ls180.v:925.11-925.26" + attribute \src "ls180.v:919.11-919.26" wire width 4 \tx_fifo_consume - attribute \src "ls180.v:930.6-930.21" + attribute \src "ls180.v:924.6-924.21" wire \tx_fifo_do_read - attribute \src "ls180.v:936.6-936.27" + attribute \src "ls180.v:930.6-930.27" wire \tx_fifo_fifo_in_first - attribute \src "ls180.v:937.6-937.26" + attribute \src "ls180.v:931.6-931.26" wire \tx_fifo_fifo_in_last - attribute \src "ls180.v:935.12-935.40" + attribute \src "ls180.v:929.12-929.40" wire width 8 \tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:939.6-939.28" + attribute \src "ls180.v:933.6-933.28" wire \tx_fifo_fifo_out_first - attribute \src "ls180.v:940.6-940.27" + attribute \src "ls180.v:934.6-934.27" wire \tx_fifo_fifo_out_last - attribute \src "ls180.v:938.12-938.41" + attribute \src "ls180.v:932.12-932.41" wire width 8 \tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:922.11-922.25" + attribute \src "ls180.v:916.11-916.25" wire width 5 \tx_fifo_level0 - attribute \src "ls180.v:934.12-934.26" + attribute \src "ls180.v:928.12-928.26" wire width 5 \tx_fifo_level1 - attribute \src "ls180.v:924.11-924.26" + attribute \src "ls180.v:918.11-918.26" wire width 4 \tx_fifo_produce - attribute \src "ls180.v:931.12-931.30" + attribute \src "ls180.v:925.12-925.30" wire width 4 \tx_fifo_rdport_adr - attribute \src "ls180.v:932.12-932.32" + attribute \src "ls180.v:926.12-926.32" wire width 10 \tx_fifo_rdport_dat_r - attribute \src "ls180.v:933.6-933.23" + attribute \src "ls180.v:927.6-927.23" wire \tx_fifo_rdport_re - attribute \src "ls180.v:914.6-914.16" + attribute \src "ls180.v:908.6-908.16" wire \tx_fifo_re - attribute \src "ls180.v:915.5-915.21" + attribute \src "ls180.v:909.5-909.21" wire \tx_fifo_readable - attribute \src "ls180.v:923.5-923.20" + attribute \src "ls180.v:917.5-917.20" wire \tx_fifo_replace - attribute \src "ls180.v:906.5-906.23" + attribute \src "ls180.v:900.5-900.23" wire \tx_fifo_sink_first - attribute \src "ls180.v:907.5-907.22" + attribute \src "ls180.v:901.5-901.22" wire \tx_fifo_sink_last - attribute \src "ls180.v:908.12-908.37" + attribute \src "ls180.v:902.12-902.37" wire width 8 \tx_fifo_sink_payload_data - attribute \src "ls180.v:905.6-905.24" + attribute \src "ls180.v:899.6-899.24" wire \tx_fifo_sink_ready - attribute \src "ls180.v:904.6-904.24" + attribute \src "ls180.v:898.6-898.24" wire \tx_fifo_sink_valid - attribute \src "ls180.v:911.6-911.26" + attribute \src "ls180.v:905.6-905.26" wire \tx_fifo_source_first - attribute \src "ls180.v:912.6-912.25" + attribute \src "ls180.v:906.6-906.25" wire \tx_fifo_source_last - attribute \src "ls180.v:913.12-913.39" + attribute \src "ls180.v:907.12-907.39" wire width 8 \tx_fifo_source_payload_data - attribute \src "ls180.v:910.6-910.26" + attribute \src "ls180.v:904.6-904.26" wire \tx_fifo_source_ready - attribute \src "ls180.v:909.6-909.26" + attribute \src "ls180.v:903.6-903.26" wire \tx_fifo_source_valid - attribute \src "ls180.v:920.12-920.32" + attribute \src "ls180.v:914.12-914.32" wire width 10 \tx_fifo_syncfifo_din - attribute \src "ls180.v:921.12-921.33" + attribute \src "ls180.v:915.12-915.33" wire width 10 \tx_fifo_syncfifo_dout - attribute \src "ls180.v:918.6-918.25" + attribute \src "ls180.v:912.6-912.25" wire \tx_fifo_syncfifo_re - attribute \src "ls180.v:919.6-919.31" + attribute \src "ls180.v:913.6-913.31" wire \tx_fifo_syncfifo_readable - attribute \src "ls180.v:916.6-916.25" + attribute \src "ls180.v:910.6-910.25" wire \tx_fifo_syncfifo_we - attribute \src "ls180.v:917.6-917.31" + attribute \src "ls180.v:911.6-911.31" wire \tx_fifo_syncfifo_writable - attribute \src "ls180.v:926.11-926.29" + attribute \src "ls180.v:920.11-920.29" wire width 4 \tx_fifo_wrport_adr - attribute \src "ls180.v:927.12-927.32" + attribute \src "ls180.v:921.12-921.32" wire width 10 \tx_fifo_wrport_dat_r - attribute \src "ls180.v:929.12-929.32" + attribute \src "ls180.v:923.12-923.32" wire width 10 \tx_fifo_wrport_dat_w - attribute \src "ls180.v:928.6-928.23" + attribute \src "ls180.v:922.6-922.23" wire \tx_fifo_wrport_we - attribute \src "ls180.v:874.5-874.19" + attribute \src "ls180.v:868.5-868.19" wire \tx_old_trigger - attribute \src "ls180.v:871.5-871.15" + attribute \src "ls180.v:865.5-865.15" wire \tx_pending - attribute \src "ls180.v:870.6-870.15" + attribute \src "ls180.v:864.6-864.15" wire \tx_status - attribute \src "ls180.v:872.6-872.16" + attribute \src "ls180.v:866.6-866.16" wire \tx_trigger - attribute \src "ls180.v:890.6-890.20" + attribute \src "ls180.v:884.6-884.20" wire \txempty_status - attribute \src "ls180.v:891.6-891.16" + attribute \src "ls180.v:885.6-885.16" wire \txempty_we - attribute \src "ls180.v:865.6-865.19" + attribute \src "ls180.v:859.6-859.19" wire \txfull_status - attribute \src "ls180.v:866.6-866.15" + attribute \src "ls180.v:860.6-860.15" wire \txfull_we - attribute \src "ls180.v:855.12-855.41" + attribute \src "ls180.v:849.12-849.41" wire width 32 \uart_phy_phase_accumulator_rx - attribute \src "ls180.v:845.12-845.41" + attribute \src "ls180.v:839.12-839.41" wire width 32 \uart_phy_phase_accumulator_tx - attribute \src "ls180.v:838.5-838.16" + attribute \src "ls180.v:832.5-832.16" wire \uart_phy_re - attribute \src "ls180.v:856.6-856.17" + attribute \src "ls180.v:850.6-850.17" wire \uart_phy_rx - attribute \src "ls180.v:859.11-859.31" + attribute \src "ls180.v:853.11-853.31" wire width 4 \uart_phy_rx_bitcount - attribute \src "ls180.v:860.5-860.21" + attribute \src "ls180.v:854.5-854.21" wire \uart_phy_rx_busy - attribute \src "ls180.v:857.5-857.18" + attribute \src "ls180.v:851.5-851.18" wire \uart_phy_rx_r - attribute \src "ls180.v:858.11-858.26" + attribute \src "ls180.v:852.11-852.26" wire width 8 \uart_phy_rx_reg - attribute \src "ls180.v:841.6-841.25" + attribute \src "ls180.v:835.6-835.25" wire \uart_phy_sink_first - attribute \src "ls180.v:842.6-842.24" + attribute \src "ls180.v:836.6-836.24" wire \uart_phy_sink_last - attribute \src "ls180.v:843.12-843.38" + attribute \src "ls180.v:837.12-837.38" wire width 8 \uart_phy_sink_payload_data - attribute \src "ls180.v:840.5-840.24" + attribute \src "ls180.v:834.5-834.24" wire \uart_phy_sink_ready - attribute \src "ls180.v:839.6-839.25" + attribute \src "ls180.v:833.6-833.25" wire \uart_phy_sink_valid - attribute \src "ls180.v:851.5-851.26" + attribute \src "ls180.v:845.5-845.26" wire \uart_phy_source_first - attribute \src "ls180.v:852.5-852.25" + attribute \src "ls180.v:846.5-846.25" wire \uart_phy_source_last - attribute \src "ls180.v:853.11-853.39" + attribute \src "ls180.v:847.11-847.39" wire width 8 \uart_phy_source_payload_data - attribute \src "ls180.v:850.6-850.27" + attribute \src "ls180.v:844.6-844.27" wire \uart_phy_source_ready - attribute \src "ls180.v:849.5-849.26" + attribute \src "ls180.v:843.5-843.26" wire \uart_phy_source_valid - attribute \src "ls180.v:837.12-837.28" + attribute \src "ls180.v:831.12-831.28" wire width 32 \uart_phy_storage - attribute \src "ls180.v:847.11-847.31" + attribute \src "ls180.v:841.11-841.31" wire width 4 \uart_phy_tx_bitcount - attribute \src "ls180.v:848.5-848.21" + attribute \src "ls180.v:842.5-842.21" wire \uart_phy_tx_busy - attribute \src "ls180.v:846.11-846.26" + attribute \src "ls180.v:840.11-840.26" wire width 8 \uart_phy_tx_reg - attribute \src "ls180.v:854.5-854.27" + attribute \src "ls180.v:848.5-848.27" wire \uart_phy_uart_clk_rxen - attribute \src "ls180.v:844.5-844.27" + attribute \src "ls180.v:838.5-838.27" wire \uart_phy_uart_clk_txen - attribute \src "ls180.v:6.13-6.20" - wire input 2 \uart_rx - attribute \src "ls180.v:896.6-896.21" + attribute \src "ls180.v:13.13-13.20" + wire input 9 \uart_rx + attribute \src "ls180.v:890.6-890.21" wire \uart_sink_first - attribute \src "ls180.v:897.6-897.20" + attribute \src "ls180.v:891.6-891.20" wire \uart_sink_last - attribute \src "ls180.v:898.12-898.34" + attribute \src "ls180.v:892.12-892.34" wire width 8 \uart_sink_payload_data - attribute \src "ls180.v:895.6-895.21" + attribute \src "ls180.v:889.6-889.21" wire \uart_sink_ready - attribute \src "ls180.v:894.6-894.21" + attribute \src "ls180.v:888.6-888.21" wire \uart_sink_valid - attribute \src "ls180.v:901.6-901.23" + attribute \src "ls180.v:895.6-895.23" wire \uart_source_first - attribute \src "ls180.v:902.6-902.22" + attribute \src "ls180.v:896.6-896.22" wire \uart_source_last - attribute \src "ls180.v:903.12-903.36" + attribute \src "ls180.v:897.12-897.36" wire width 8 \uart_source_payload_data - attribute \src "ls180.v:900.6-900.23" + attribute \src "ls180.v:894.6-894.23" wire \uart_source_ready - attribute \src "ls180.v:899.6-899.23" + attribute \src "ls180.v:893.6-893.23" wire \uart_source_valid - attribute \src "ls180.v:5.13-5.20" - wire input 1 \uart_tx - attribute \src "ls180.v:815.5-815.17" + attribute \src "ls180.v:12.13-12.20" + wire input 8 \uart_tx + attribute \src "ls180.v:809.5-809.17" wire \wb_sdram_ack - attribute \src "ls180.v:809.13-809.25" + attribute \src "ls180.v:803.13-803.25" wire width 30 \wb_sdram_adr - attribute \src "ls180.v:818.12-818.24" + attribute \src "ls180.v:812.12-812.24" wire width 2 \wb_sdram_bte - attribute \src "ls180.v:817.12-817.24" + attribute \src "ls180.v:811.12-811.24" wire width 3 \wb_sdram_cti - attribute \src "ls180.v:813.6-813.18" + attribute \src "ls180.v:807.6-807.18" wire \wb_sdram_cyc - attribute \src "ls180.v:811.13-811.27" + attribute \src "ls180.v:805.13-805.27" wire width 32 \wb_sdram_dat_r - attribute \src "ls180.v:810.13-810.27" + attribute \src "ls180.v:804.13-804.27" wire width 32 \wb_sdram_dat_w - attribute \src "ls180.v:819.5-819.17" + attribute \src "ls180.v:813.5-813.17" wire \wb_sdram_err - attribute \src "ls180.v:812.12-812.24" + attribute \src "ls180.v:806.12-806.24" wire width 4 \wb_sdram_sel - attribute \src "ls180.v:814.6-814.18" + attribute \src "ls180.v:808.6-808.18" wire \wb_sdram_stb - attribute \src "ls180.v:816.6-816.17" + attribute \src "ls180.v:810.6-810.17" wire \wb_sdram_we - attribute \src "ls180.v:833.5-833.19" + attribute \src "ls180.v:827.5-827.19" wire \wdata_consumed - attribute \src "ls180.v:5493.12-5493.15" + attribute \src "ls180.v:5488.12-5488.15" memory width 32 size 128 \mem - attribute \src "ls180.v:5513.12-5513.17" + attribute \src "ls180.v:5508.12-5508.17" memory width 32 size 32 \mem_1 - attribute \src "ls180.v:5533.12-5533.19" + attribute \src "ls180.v:5528.12-5528.19" memory width 25 size 8 \storage - attribute \src "ls180.v:5547.12-5547.21" + attribute \src "ls180.v:5542.12-5542.21" memory width 25 size 8 \storage_1 - attribute \src "ls180.v:5561.12-5561.21" + attribute \src "ls180.v:5556.12-5556.21" memory width 25 size 8 \storage_2 - attribute \src "ls180.v:5575.12-5575.21" + attribute \src "ls180.v:5570.12-5570.21" memory width 25 size 8 \storage_3 - attribute \src "ls180.v:5589.11-5589.20" + attribute \src "ls180.v:5584.11-5584.20" memory width 10 size 16 \storage_4 - attribute \src "ls180.v:5606.11-5606.20" + attribute \src "ls180.v:5601.11-5601.20" memory width 10 size 16 \storage_5 - attribute \src "ls180.v:1561.76-1561.113" - cell $add $add$ls180.v:1561$25 + attribute \src "ls180.v:1552.76-1552.113" + cell $add $add$ls180.v:1552$25 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246589,10 +246381,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_converter0_counter connect \B 1'1 - connect \Y $add$ls180.v:1561$25_Y + connect \Y $add$ls180.v:1552$25_Y end - attribute \src "ls180.v:1621.76-1621.113" - cell $add $add$ls180.v:1621$36 + attribute \src "ls180.v:1612.76-1612.113" + cell $add $add$ls180.v:1612$36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246600,10 +246392,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_converter1_counter connect \B 1'1 - connect \Y $add$ls180.v:1621$36_Y + connect \Y $add$ls180.v:1612$36_Y end - attribute \src "ls180.v:1681.76-1681.113" - cell $add $add$ls180.v:1681$47 + attribute \src "ls180.v:1672.76-1672.113" + cell $add $add$ls180.v:1672$47 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246611,10 +246403,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_converter2_counter connect \B 1'1 - connect \Y $add$ls180.v:1681$47_Y + connect \Y $add$ls180.v:1672$47_Y end - attribute \src "ls180.v:2824.52-2824.76" - cell $add $add$ls180.v:2824$553 + attribute \src "ls180.v:2815.52-2815.76" + cell $add $add$ls180.v:2815$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246622,10 +246414,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \converter_counter connect \B 1'1 - connect \Y $add$ls180.v:2824$553_Y + connect \Y $add$ls180.v:2815$553_Y end - attribute \src "ls180.v:2924.26-2924.59" - cell $add $add$ls180.v:2924$599 + attribute \src "ls180.v:2915.26-2915.59" + cell $add $add$ls180.v:2915$599 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -246633,10 +246425,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \tx_fifo_level0 connect \B \tx_fifo_readable - connect \Y $add$ls180.v:2924$599_Y + connect \Y $add$ls180.v:2915$599_Y end - attribute \src "ls180.v:2954.26-2954.59" - cell $add $add$ls180.v:2954$610 + attribute \src "ls180.v:2945.26-2945.59" + cell $add $add$ls180.v:2945$610 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -246644,10 +246436,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \rx_fifo_level0 connect \B \rx_fifo_readable - connect \Y $add$ls180.v:2954$610_Y + connect \Y $add$ls180.v:2945$610_Y end - attribute \src "ls180.v:4357.31-4357.60" - cell $add $add$ls180.v:4357$1256 + attribute \src "ls180.v:4352.31-4352.60" + cell $add $add$ls180.v:4352$1260 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -246655,10 +246447,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:4357$1256_Y + connect \Y $add$ls180.v:4352$1260_Y end - attribute \src "ls180.v:4446.32-4446.62" - cell $add $add$ls180.v:4446$1280 + attribute \src "ls180.v:4441.32-4441.62" + cell $add $add$ls180.v:4441$1284 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -246666,10 +246458,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:4446$1280_Y + connect \Y $add$ls180.v:4441$1284_Y end - attribute \src "ls180.v:4463.55-4463.109" - cell $add $add$ls180.v:4463$1284 + attribute \src "ls180.v:4458.55-4458.109" + cell $add $add$ls180.v:4458$1288 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -246677,10 +246469,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:4463$1284_Y + connect \Y $add$ls180.v:4458$1288_Y end - attribute \src "ls180.v:4466.55-4466.109" - cell $add $add$ls180.v:4466$1285 + attribute \src "ls180.v:4461.55-4461.109" + cell $add $add$ls180.v:4461$1289 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -246688,10 +246480,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:4466$1285_Y + connect \Y $add$ls180.v:4461$1289_Y end - attribute \src "ls180.v:4470.54-4470.106" - cell $add $add$ls180.v:4470$1290 + attribute \src "ls180.v:4465.54-4465.106" + cell $add $add$ls180.v:4465$1294 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -246699,10 +246491,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:4470$1290_Y + connect \Y $add$ls180.v:4465$1294_Y end - attribute \src "ls180.v:4509.55-4509.109" - cell $add $add$ls180.v:4509$1300 + attribute \src "ls180.v:4504.55-4504.109" + cell $add $add$ls180.v:4504$1304 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -246710,10 +246502,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:4509$1300_Y + connect \Y $add$ls180.v:4504$1304_Y end - attribute \src "ls180.v:4512.55-4512.109" - cell $add $add$ls180.v:4512$1301 + attribute \src "ls180.v:4507.55-4507.109" + cell $add $add$ls180.v:4507$1305 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -246721,10 +246513,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:4512$1301_Y + connect \Y $add$ls180.v:4507$1305_Y end - attribute \src "ls180.v:4516.54-4516.106" - cell $add $add$ls180.v:4516$1306 + attribute \src "ls180.v:4511.54-4511.106" + cell $add $add$ls180.v:4511$1310 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -246732,10 +246524,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:4516$1306_Y + connect \Y $add$ls180.v:4511$1310_Y end - attribute \src "ls180.v:4555.55-4555.109" - cell $add $add$ls180.v:4555$1316 + attribute \src "ls180.v:4550.55-4550.109" + cell $add $add$ls180.v:4550$1320 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -246743,10 +246535,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:4555$1316_Y + connect \Y $add$ls180.v:4550$1320_Y end - attribute \src "ls180.v:4558.55-4558.109" - cell $add $add$ls180.v:4558$1317 + attribute \src "ls180.v:4553.55-4553.109" + cell $add $add$ls180.v:4553$1321 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -246754,10 +246546,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:4558$1317_Y + connect \Y $add$ls180.v:4553$1321_Y end - attribute \src "ls180.v:4562.54-4562.106" - cell $add $add$ls180.v:4562$1322 + attribute \src "ls180.v:4557.54-4557.106" + cell $add $add$ls180.v:4557$1326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -246765,10 +246557,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:4562$1322_Y + connect \Y $add$ls180.v:4557$1326_Y end - attribute \src "ls180.v:4601.55-4601.109" - cell $add $add$ls180.v:4601$1332 + attribute \src "ls180.v:4596.55-4596.109" + cell $add $add$ls180.v:4596$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -246776,10 +246568,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:4601$1332_Y + connect \Y $add$ls180.v:4596$1336_Y end - attribute \src "ls180.v:4604.55-4604.109" - cell $add $add$ls180.v:4604$1333 + attribute \src "ls180.v:4599.55-4599.109" + cell $add $add$ls180.v:4599$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -246787,10 +246579,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:4604$1333_Y + connect \Y $add$ls180.v:4599$1337_Y end - attribute \src "ls180.v:4608.54-4608.106" - cell $add $add$ls180.v:4608$1338 + attribute \src "ls180.v:4603.54-4603.106" + cell $add $add$ls180.v:4603$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -246798,10 +246590,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:4608$1338_Y + connect \Y $add$ls180.v:4603$1342_Y end - attribute \src "ls180.v:4838.29-4838.56" - cell $add $add$ls180.v:4838$1392 + attribute \src "ls180.v:4833.29-4833.56" + cell $add $add$ls180.v:4833$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -246809,10 +246601,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \uart_phy_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:4838$1392_Y + connect \Y $add$ls180.v:4833$1396_Y end - attribute \src "ls180.v:4854.63-4854.111" - cell $add $add$ls180.v:4854$1395 + attribute \src "ls180.v:4849.63-4849.111" + cell $add $add$ls180.v:4849$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -246820,10 +246612,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \uart_phy_phase_accumulator_tx connect \B \uart_phy_storage - connect \Y $add$ls180.v:4854$1395_Y + connect \Y $add$ls180.v:4849$1399_Y end - attribute \src "ls180.v:4867.29-4867.56" - cell $add $add$ls180.v:4867$1399 + attribute \src "ls180.v:4862.29-4862.56" + cell $add $add$ls180.v:4862$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -246831,10 +246623,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \uart_phy_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:4867$1399_Y + connect \Y $add$ls180.v:4862$1403_Y end - attribute \src "ls180.v:4886.63-4886.111" - cell $add $add$ls180.v:4886$1402 + attribute \src "ls180.v:4881.63-4881.111" + cell $add $add$ls180.v:4881$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -246842,10 +246634,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \uart_phy_phase_accumulator_rx connect \B \uart_phy_storage - connect \Y $add$ls180.v:4886$1402_Y + connect \Y $add$ls180.v:4881$1406_Y end - attribute \src "ls180.v:4912.23-4912.45" - cell $add $add$ls180.v:4912$1410 + attribute \src "ls180.v:4907.23-4907.45" + cell $add $add$ls180.v:4907$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -246853,10 +246645,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:4912$1410_Y + connect \Y $add$ls180.v:4907$1414_Y end - attribute \src "ls180.v:4915.23-4915.45" - cell $add $add$ls180.v:4915$1411 + attribute \src "ls180.v:4910.23-4910.45" + cell $add $add$ls180.v:4910$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -246864,10 +246656,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:4915$1411_Y + connect \Y $add$ls180.v:4910$1415_Y end - attribute \src "ls180.v:4919.23-4919.44" - cell $add $add$ls180.v:4919$1416 + attribute \src "ls180.v:4914.23-4914.44" + cell $add $add$ls180.v:4914$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -246875,10 +246667,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:4919$1416_Y + connect \Y $add$ls180.v:4914$1420_Y end - attribute \src "ls180.v:4934.23-4934.45" - cell $add $add$ls180.v:4934$1421 + attribute \src "ls180.v:4929.23-4929.45" + cell $add $add$ls180.v:4929$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -246886,10 +246678,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:4934$1421_Y + connect \Y $add$ls180.v:4929$1425_Y end - attribute \src "ls180.v:4937.23-4937.45" - cell $add $add$ls180.v:4937$1422 + attribute \src "ls180.v:4932.23-4932.45" + cell $add $add$ls180.v:4932$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -246897,10 +246689,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:4937$1422_Y + connect \Y $add$ls180.v:4932$1426_Y end - attribute \src "ls180.v:4941.23-4941.44" - cell $add $add$ls180.v:4941$1427 + attribute \src "ls180.v:4936.23-4936.44" + cell $add $add$ls180.v:4936$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -246908,10 +246700,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:4941$1427_Y + connect \Y $add$ls180.v:4936$1431_Y end - attribute \src "ls180.v:1555.9-1555.70" - cell $and $and$ls180.v:1555$20 + attribute \src "ls180.v:1546.9-1546.70" + cell $and $and$ls180.v:1546$20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246919,10 +246711,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_ibus_stb connect \B \libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:1555$20_Y + connect \Y $and$ls180.v:1546$20_Y end - attribute \src "ls180.v:1573.9-1573.70" - cell $and $and$ls180.v:1573$27 + attribute \src "ls180.v:1564.9-1564.70" + cell $and $and$ls180.v:1564$27 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246930,10 +246722,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_ibus_stb connect \B \libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:1573$27_Y + connect \Y $and$ls180.v:1564$27_Y end - attribute \src "ls180.v:1615.9-1615.70" - cell $and $and$ls180.v:1615$31 + attribute \src "ls180.v:1606.9-1606.70" + cell $and $and$ls180.v:1606$31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246941,10 +246733,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_dbus_stb connect \B \libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:1615$31_Y + connect \Y $and$ls180.v:1606$31_Y end - attribute \src "ls180.v:1633.9-1633.70" - cell $and $and$ls180.v:1633$38 + attribute \src "ls180.v:1624.9-1624.70" + cell $and $and$ls180.v:1624$38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246952,10 +246744,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_dbus_stb connect \B \libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:1633$38_Y + connect \Y $and$ls180.v:1624$38_Y end - attribute \src "ls180.v:1675.9-1675.76" - cell $and $and$ls180.v:1675$42 + attribute \src "ls180.v:1666.9-1666.76" + cell $and $and$ls180.v:1666$42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246963,10 +246755,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_jtag_wb_stb connect \B \libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:1675$42_Y + connect \Y $and$ls180.v:1666$42_Y end - attribute \src "ls180.v:1693.9-1693.76" - cell $and $and$ls180.v:1693$49 + attribute \src "ls180.v:1684.9-1684.76" + cell $and $and$ls180.v:1684$49 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246974,10 +246766,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_jtag_wb_stb connect \B \libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:1693$49_Y + connect \Y $and$ls180.v:1684$49_Y end - attribute \src "ls180.v:1703.26-1703.75" - cell $and $and$ls180.v:1703$51 + attribute \src "ls180.v:1694.26-1694.75" + cell $and $and$ls180.v:1694$51 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246985,32 +246777,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_cyc connect \B \libresocsim_ram_bus_stb - connect \Y $and$ls180.v:1703$51_Y + connect \Y $and$ls180.v:1694$51_Y end - attribute \src "ls180.v:1703.25-1703.101" - cell $and $and$ls180.v:1703$52 + attribute \src "ls180.v:1694.25-1694.101" + cell $and $and$ls180.v:1694$52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1703$51_Y + connect \A $and$ls180.v:1694$51_Y connect \B \libresocsim_ram_bus_we - connect \Y $and$ls180.v:1703$52_Y + connect \Y $and$ls180.v:1694$52_Y end - attribute \src "ls180.v:1703.24-1703.131" - cell $and $and$ls180.v:1703$53 + attribute \src "ls180.v:1694.24-1694.131" + cell $and $and$ls180.v:1694$53 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1703$52_Y + connect \A $and$ls180.v:1694$52_Y connect \B \libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:1703$53_Y + connect \Y $and$ls180.v:1694$53_Y end - attribute \src "ls180.v:1704.26-1704.75" - cell $and $and$ls180.v:1704$54 + attribute \src "ls180.v:1695.26-1695.75" + cell $and $and$ls180.v:1695$54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247018,32 +246810,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_cyc connect \B \libresocsim_ram_bus_stb - connect \Y $and$ls180.v:1704$54_Y + connect \Y $and$ls180.v:1695$54_Y end - attribute \src "ls180.v:1704.25-1704.101" - cell $and $and$ls180.v:1704$55 + attribute \src "ls180.v:1695.25-1695.101" + cell $and $and$ls180.v:1695$55 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1704$54_Y + connect \A $and$ls180.v:1695$54_Y connect \B \libresocsim_ram_bus_we - connect \Y $and$ls180.v:1704$55_Y + connect \Y $and$ls180.v:1695$55_Y end - attribute \src "ls180.v:1704.24-1704.131" - cell $and $and$ls180.v:1704$56 + attribute \src "ls180.v:1695.24-1695.131" + cell $and $and$ls180.v:1695$56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1704$55_Y + connect \A $and$ls180.v:1695$55_Y connect \B \libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:1704$56_Y + connect \Y $and$ls180.v:1695$56_Y end - attribute \src "ls180.v:1705.26-1705.75" - cell $and $and$ls180.v:1705$57 + attribute \src "ls180.v:1696.26-1696.75" + cell $and $and$ls180.v:1696$57 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247051,32 +246843,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_cyc connect \B \libresocsim_ram_bus_stb - connect \Y $and$ls180.v:1705$57_Y + connect \Y $and$ls180.v:1696$57_Y end - attribute \src "ls180.v:1705.25-1705.101" - cell $and $and$ls180.v:1705$58 + attribute \src "ls180.v:1696.25-1696.101" + cell $and $and$ls180.v:1696$58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1705$57_Y + connect \A $and$ls180.v:1696$57_Y connect \B \libresocsim_ram_bus_we - connect \Y $and$ls180.v:1705$58_Y + connect \Y $and$ls180.v:1696$58_Y end - attribute \src "ls180.v:1705.24-1705.131" - cell $and $and$ls180.v:1705$59 + attribute \src "ls180.v:1696.24-1696.131" + cell $and $and$ls180.v:1696$59 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1705$58_Y + connect \A $and$ls180.v:1696$58_Y connect \B \libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:1705$59_Y + connect \Y $and$ls180.v:1696$59_Y end - attribute \src "ls180.v:1706.26-1706.75" - cell $and $and$ls180.v:1706$60 + attribute \src "ls180.v:1697.26-1697.75" + cell $and $and$ls180.v:1697$60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247084,32 +246876,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_cyc connect \B \libresocsim_ram_bus_stb - connect \Y $and$ls180.v:1706$60_Y + connect \Y $and$ls180.v:1697$60_Y end - attribute \src "ls180.v:1706.25-1706.101" - cell $and $and$ls180.v:1706$61 + attribute \src "ls180.v:1697.25-1697.101" + cell $and $and$ls180.v:1697$61 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1706$60_Y + connect \A $and$ls180.v:1697$60_Y connect \B \libresocsim_ram_bus_we - connect \Y $and$ls180.v:1706$61_Y + connect \Y $and$ls180.v:1697$61_Y end - attribute \src "ls180.v:1706.24-1706.131" - cell $and $and$ls180.v:1706$62 + attribute \src "ls180.v:1697.24-1697.131" + cell $and $and$ls180.v:1697$62 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1706$61_Y + connect \A $and$ls180.v:1697$61_Y connect \B \libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:1706$62_Y + connect \Y $and$ls180.v:1697$62_Y end - attribute \src "ls180.v:1715.7-1715.79" - cell $and $and$ls180.v:1715$65 + attribute \src "ls180.v:1706.7-1706.79" + cell $and $and$ls180.v:1706$65 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247117,10 +246909,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_eventmanager_pending_re connect \B \libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:1715$65_Y + connect \Y $and$ls180.v:1706$65_Y end - attribute \src "ls180.v:1720.27-1720.96" - cell $and $and$ls180.v:1720$66 + attribute \src "ls180.v:1711.27-1711.96" + cell $and $and$ls180.v:1711$66 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247128,10 +246920,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_eventmanager_pending_w connect \B \libresocsim_eventmanager_storage - connect \Y $and$ls180.v:1720$66_Y + connect \Y $and$ls180.v:1711$66_Y end - attribute \src "ls180.v:1724.18-1724.59" - cell $and $and$ls180.v:1724$68 + attribute \src "ls180.v:1715.18-1715.59" + cell $and $and$ls180.v:1715$68 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247139,32 +246931,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_cyc connect \B \ram_bus_ram_bus_stb - connect \Y $and$ls180.v:1724$68_Y + connect \Y $and$ls180.v:1715$68_Y end - attribute \src "ls180.v:1724.17-1724.81" - cell $and $and$ls180.v:1724$69 + attribute \src "ls180.v:1715.17-1715.81" + cell $and $and$ls180.v:1715$69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1724$68_Y + connect \A $and$ls180.v:1715$68_Y connect \B \ram_bus_ram_bus_we - connect \Y $and$ls180.v:1724$69_Y + connect \Y $and$ls180.v:1715$69_Y end - attribute \src "ls180.v:1724.16-1724.107" - cell $and $and$ls180.v:1724$70 + attribute \src "ls180.v:1715.16-1715.107" + cell $and $and$ls180.v:1715$70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1724$69_Y + connect \A $and$ls180.v:1715$69_Y connect \B \ram_bus_ram_bus_sel [0] - connect \Y $and$ls180.v:1724$70_Y + connect \Y $and$ls180.v:1715$70_Y end - attribute \src "ls180.v:1725.18-1725.59" - cell $and $and$ls180.v:1725$71 + attribute \src "ls180.v:1716.18-1716.59" + cell $and $and$ls180.v:1716$71 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247172,32 +246964,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_cyc connect \B \ram_bus_ram_bus_stb - connect \Y $and$ls180.v:1725$71_Y + connect \Y $and$ls180.v:1716$71_Y end - attribute \src "ls180.v:1725.17-1725.81" - cell $and $and$ls180.v:1725$72 + attribute \src "ls180.v:1716.17-1716.81" + cell $and $and$ls180.v:1716$72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1725$71_Y + connect \A $and$ls180.v:1716$71_Y connect \B \ram_bus_ram_bus_we - connect \Y $and$ls180.v:1725$72_Y + connect \Y $and$ls180.v:1716$72_Y end - attribute \src "ls180.v:1725.16-1725.107" - cell $and $and$ls180.v:1725$73 + attribute \src "ls180.v:1716.16-1716.107" + cell $and $and$ls180.v:1716$73 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1725$72_Y + connect \A $and$ls180.v:1716$72_Y connect \B \ram_bus_ram_bus_sel [1] - connect \Y $and$ls180.v:1725$73_Y + connect \Y $and$ls180.v:1716$73_Y end - attribute \src "ls180.v:1726.18-1726.59" - cell $and $and$ls180.v:1726$74 + attribute \src "ls180.v:1717.18-1717.59" + cell $and $and$ls180.v:1717$74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247205,32 +246997,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_cyc connect \B \ram_bus_ram_bus_stb - connect \Y $and$ls180.v:1726$74_Y + connect \Y $and$ls180.v:1717$74_Y end - attribute \src "ls180.v:1726.17-1726.81" - cell $and $and$ls180.v:1726$75 + attribute \src "ls180.v:1717.17-1717.81" + cell $and $and$ls180.v:1717$75 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1726$74_Y + connect \A $and$ls180.v:1717$74_Y connect \B \ram_bus_ram_bus_we - connect \Y $and$ls180.v:1726$75_Y + connect \Y $and$ls180.v:1717$75_Y end - attribute \src "ls180.v:1726.16-1726.107" - cell $and $and$ls180.v:1726$76 + attribute \src "ls180.v:1717.16-1717.107" + cell $and $and$ls180.v:1717$76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1726$75_Y + connect \A $and$ls180.v:1717$75_Y connect \B \ram_bus_ram_bus_sel [2] - connect \Y $and$ls180.v:1726$76_Y + connect \Y $and$ls180.v:1717$76_Y end - attribute \src "ls180.v:1727.18-1727.59" - cell $and $and$ls180.v:1727$77 + attribute \src "ls180.v:1718.18-1718.59" + cell $and $and$ls180.v:1718$77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247238,32 +247030,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_cyc connect \B \ram_bus_ram_bus_stb - connect \Y $and$ls180.v:1727$77_Y + connect \Y $and$ls180.v:1718$77_Y end - attribute \src "ls180.v:1727.17-1727.81" - cell $and $and$ls180.v:1727$78 + attribute \src "ls180.v:1718.17-1718.81" + cell $and $and$ls180.v:1718$78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1727$77_Y + connect \A $and$ls180.v:1718$77_Y connect \B \ram_bus_ram_bus_we - connect \Y $and$ls180.v:1727$78_Y + connect \Y $and$ls180.v:1718$78_Y end - attribute \src "ls180.v:1727.16-1727.107" - cell $and $and$ls180.v:1727$79 + attribute \src "ls180.v:1718.16-1718.107" + cell $and $and$ls180.v:1718$79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1727$78_Y + connect \A $and$ls180.v:1718$78_Y connect \B \ram_bus_ram_bus_sel [3] - connect \Y $and$ls180.v:1727$79_Y + connect \Y $and$ls180.v:1718$79_Y end - attribute \src "ls180.v:1844.35-1844.84" - cell $and $and$ls180.v:1844$86 + attribute \src "ls180.v:1835.35-1835.84" + cell $and $and$ls180.v:1835$86 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247271,10 +247063,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_command_issue_re connect \B \sdram_command_storage [4] - connect \Y $and$ls180.v:1844$86_Y + connect \Y $and$ls180.v:1835$86_Y end - attribute \src "ls180.v:1845.35-1845.84" - cell $and $and$ls180.v:1845$87 + attribute \src "ls180.v:1836.35-1836.84" + cell $and $and$ls180.v:1836$87 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247282,21 +247074,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_command_issue_re connect \B \sdram_command_storage [5] - connect \Y $and$ls180.v:1845$87_Y + connect \Y $and$ls180.v:1836$87_Y end - attribute \src "ls180.v:1883.33-1883.88" - cell $and $and$ls180.v:1883$93 + attribute \src "ls180.v:1874.33-1874.88" + cell $and $and$ls180.v:1874$93 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_done1 - connect \B $eq$ls180.v:1883$92_Y - connect \Y $and$ls180.v:1883$93_Y + connect \B $eq$ls180.v:1874$92_Y + connect \Y $and$ls180.v:1874$93_Y end - attribute \src "ls180.v:1937.45-1937.104" - cell $and $and$ls180.v:1937$101 + attribute \src "ls180.v:1928.45-1928.104" + cell $and $and$ls180.v:1928$101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247304,21 +247096,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B \sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:1937$101_Y + connect \Y $and$ls180.v:1928$101_Y end - attribute \src "ls180.v:1937.44-1937.147" - cell $and $and$ls180.v:1937$102 + attribute \src "ls180.v:1928.44-1928.147" + cell $and $and$ls180.v:1928$102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1937$101_Y + connect \A $and$ls180.v:1928$101_Y connect \B \sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:1937$102_Y + connect \Y $and$ls180.v:1928$102_Y end - attribute \src "ls180.v:1938.44-1938.103" - cell $and $and$ls180.v:1938$103 + attribute \src "ls180.v:1929.44-1929.103" + cell $and $and$ls180.v:1929$103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247326,21 +247118,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B \sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:1938$103_Y + connect \Y $and$ls180.v:1929$103_Y end - attribute \src "ls180.v:1938.43-1938.134" - cell $and $and$ls180.v:1938$104 + attribute \src "ls180.v:1929.43-1929.134" + cell $and $and$ls180.v:1929$104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1938$103_Y + connect \A $and$ls180.v:1929$103_Y connect \B \sdram_bankmachine0_row_open - connect \Y $and$ls180.v:1938$104_Y + connect \Y $and$ls180.v:1929$104_Y end - attribute \src "ls180.v:1939.45-1939.104" - cell $and $and$ls180.v:1939$105 + attribute \src "ls180.v:1930.45-1930.104" + cell $and $and$ls180.v:1930$105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247348,21 +247140,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B \sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:1939$105_Y + connect \Y $and$ls180.v:1930$105_Y end - attribute \src "ls180.v:1939.44-1939.135" - cell $and $and$ls180.v:1939$106 + attribute \src "ls180.v:1930.44-1930.135" + cell $and $and$ls180.v:1930$106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:1939$105_Y + connect \A $and$ls180.v:1930$105_Y connect \B \sdram_bankmachine0_row_open - connect \Y $and$ls180.v:1939$106_Y + connect \Y $and$ls180.v:1930$106_Y end - attribute \src "ls180.v:1942.7-1942.104" - cell $and $and$ls180.v:1942$108 + attribute \src "ls180.v:1933.7-1933.104" + cell $and $and$ls180.v:1933$108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247370,21 +247162,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:1942$108_Y + connect \Y $and$ls180.v:1933$108_Y end - attribute \src "ls180.v:1971.61-1971.226" - cell $and $and$ls180.v:1971$114 + attribute \src "ls180.v:1962.61-1962.226" + cell $and $and$ls180.v:1962$114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:1971$113_Y - connect \Y $and$ls180.v:1971$114_Y + connect \B $or$ls180.v:1962$113_Y + connect \Y $and$ls180.v:1962$114_Y end - attribute \src "ls180.v:1972.59-1972.172" - cell $and $and$ls180.v:1972$115 + attribute \src "ls180.v:1963.59-1963.172" + cell $and $and$ls180.v:1963$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247392,10 +247184,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:1972$115_Y + connect \Y $and$ls180.v:1963$115_Y end - attribute \src "ls180.v:1996.9-1996.76" - cell $and $and$ls180.v:1996$121 + attribute \src "ls180.v:1987.9-1987.76" + cell $and $and$ls180.v:1987$121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247403,10 +247195,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_twtpcon_ready connect \B \sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:1996$121_Y + connect \Y $and$ls180.v:1987$121_Y end - attribute \src "ls180.v:2008.9-2008.76" - cell $and $and$ls180.v:2008$122 + attribute \src "ls180.v:1999.9-1999.76" + cell $and $and$ls180.v:1999$122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247414,10 +247206,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_twtpcon_ready connect \B \sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:2008$122_Y + connect \Y $and$ls180.v:1999$122_Y end - attribute \src "ls180.v:2058.13-2058.77" - cell $and $and$ls180.v:2058$124 + attribute \src "ls180.v:2049.13-2049.77" + cell $and $and$ls180.v:2049$124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247425,10 +247217,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_ready connect \B \sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:2058$124_Y + connect \Y $and$ls180.v:2049$124_Y end - attribute \src "ls180.v:2094.45-2094.104" - cell $and $and$ls180.v:2094$131 + attribute \src "ls180.v:2085.45-2085.104" + cell $and $and$ls180.v:2085$131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247436,21 +247228,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B \sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:2094$131_Y + connect \Y $and$ls180.v:2085$131_Y end - attribute \src "ls180.v:2094.44-2094.147" - cell $and $and$ls180.v:2094$132 + attribute \src "ls180.v:2085.44-2085.147" + cell $and $and$ls180.v:2085$132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2094$131_Y + connect \A $and$ls180.v:2085$131_Y connect \B \sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:2094$132_Y + connect \Y $and$ls180.v:2085$132_Y end - attribute \src "ls180.v:2095.44-2095.103" - cell $and $and$ls180.v:2095$133 + attribute \src "ls180.v:2086.44-2086.103" + cell $and $and$ls180.v:2086$133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247458,21 +247250,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B \sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:2095$133_Y + connect \Y $and$ls180.v:2086$133_Y end - attribute \src "ls180.v:2095.43-2095.134" - cell $and $and$ls180.v:2095$134 + attribute \src "ls180.v:2086.43-2086.134" + cell $and $and$ls180.v:2086$134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2095$133_Y + connect \A $and$ls180.v:2086$133_Y connect \B \sdram_bankmachine1_row_open - connect \Y $and$ls180.v:2095$134_Y + connect \Y $and$ls180.v:2086$134_Y end - attribute \src "ls180.v:2096.45-2096.104" - cell $and $and$ls180.v:2096$135 + attribute \src "ls180.v:2087.45-2087.104" + cell $and $and$ls180.v:2087$135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247480,21 +247272,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B \sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:2096$135_Y + connect \Y $and$ls180.v:2087$135_Y end - attribute \src "ls180.v:2096.44-2096.135" - cell $and $and$ls180.v:2096$136 + attribute \src "ls180.v:2087.44-2087.135" + cell $and $and$ls180.v:2087$136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2096$135_Y + connect \A $and$ls180.v:2087$135_Y connect \B \sdram_bankmachine1_row_open - connect \Y $and$ls180.v:2096$136_Y + connect \Y $and$ls180.v:2087$136_Y end - attribute \src "ls180.v:2099.7-2099.104" - cell $and $and$ls180.v:2099$138 + attribute \src "ls180.v:2090.7-2090.104" + cell $and $and$ls180.v:2090$138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247502,21 +247294,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:2099$138_Y + connect \Y $and$ls180.v:2090$138_Y end - attribute \src "ls180.v:2128.61-2128.226" - cell $and $and$ls180.v:2128$144 + attribute \src "ls180.v:2119.61-2119.226" + cell $and $and$ls180.v:2119$144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:2128$143_Y - connect \Y $and$ls180.v:2128$144_Y + connect \B $or$ls180.v:2119$143_Y + connect \Y $and$ls180.v:2119$144_Y end - attribute \src "ls180.v:2129.59-2129.172" - cell $and $and$ls180.v:2129$145 + attribute \src "ls180.v:2120.59-2120.172" + cell $and $and$ls180.v:2120$145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247524,10 +247316,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:2129$145_Y + connect \Y $and$ls180.v:2120$145_Y end - attribute \src "ls180.v:2153.9-2153.76" - cell $and $and$ls180.v:2153$151 + attribute \src "ls180.v:2144.9-2144.76" + cell $and $and$ls180.v:2144$151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247535,10 +247327,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_twtpcon_ready connect \B \sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:2153$151_Y + connect \Y $and$ls180.v:2144$151_Y end - attribute \src "ls180.v:2165.9-2165.76" - cell $and $and$ls180.v:2165$152 + attribute \src "ls180.v:2156.9-2156.76" + cell $and $and$ls180.v:2156$152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247546,10 +247338,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_twtpcon_ready connect \B \sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:2165$152_Y + connect \Y $and$ls180.v:2156$152_Y end - attribute \src "ls180.v:2215.13-2215.77" - cell $and $and$ls180.v:2215$154 + attribute \src "ls180.v:2206.13-2206.77" + cell $and $and$ls180.v:2206$154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247557,10 +247349,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_ready connect \B \sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:2215$154_Y + connect \Y $and$ls180.v:2206$154_Y end - attribute \src "ls180.v:2251.45-2251.104" - cell $and $and$ls180.v:2251$161 + attribute \src "ls180.v:2242.45-2242.104" + cell $and $and$ls180.v:2242$161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247568,21 +247360,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B \sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:2251$161_Y + connect \Y $and$ls180.v:2242$161_Y end - attribute \src "ls180.v:2251.44-2251.147" - cell $and $and$ls180.v:2251$162 + attribute \src "ls180.v:2242.44-2242.147" + cell $and $and$ls180.v:2242$162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2251$161_Y + connect \A $and$ls180.v:2242$161_Y connect \B \sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:2251$162_Y + connect \Y $and$ls180.v:2242$162_Y end - attribute \src "ls180.v:2252.44-2252.103" - cell $and $and$ls180.v:2252$163 + attribute \src "ls180.v:2243.44-2243.103" + cell $and $and$ls180.v:2243$163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247590,21 +247382,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B \sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:2252$163_Y + connect \Y $and$ls180.v:2243$163_Y end - attribute \src "ls180.v:2252.43-2252.134" - cell $and $and$ls180.v:2252$164 + attribute \src "ls180.v:2243.43-2243.134" + cell $and $and$ls180.v:2243$164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2252$163_Y + connect \A $and$ls180.v:2243$163_Y connect \B \sdram_bankmachine2_row_open - connect \Y $and$ls180.v:2252$164_Y + connect \Y $and$ls180.v:2243$164_Y end - attribute \src "ls180.v:2253.45-2253.104" - cell $and $and$ls180.v:2253$165 + attribute \src "ls180.v:2244.45-2244.104" + cell $and $and$ls180.v:2244$165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247612,21 +247404,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B \sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:2253$165_Y + connect \Y $and$ls180.v:2244$165_Y end - attribute \src "ls180.v:2253.44-2253.135" - cell $and $and$ls180.v:2253$166 + attribute \src "ls180.v:2244.44-2244.135" + cell $and $and$ls180.v:2244$166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2253$165_Y + connect \A $and$ls180.v:2244$165_Y connect \B \sdram_bankmachine2_row_open - connect \Y $and$ls180.v:2253$166_Y + connect \Y $and$ls180.v:2244$166_Y end - attribute \src "ls180.v:2256.7-2256.104" - cell $and $and$ls180.v:2256$168 + attribute \src "ls180.v:2247.7-2247.104" + cell $and $and$ls180.v:2247$168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247634,21 +247426,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:2256$168_Y + connect \Y $and$ls180.v:2247$168_Y end - attribute \src "ls180.v:2285.61-2285.226" - cell $and $and$ls180.v:2285$174 + attribute \src "ls180.v:2276.61-2276.226" + cell $and $and$ls180.v:2276$174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:2285$173_Y - connect \Y $and$ls180.v:2285$174_Y + connect \B $or$ls180.v:2276$173_Y + connect \Y $and$ls180.v:2276$174_Y end - attribute \src "ls180.v:2286.59-2286.172" - cell $and $and$ls180.v:2286$175 + attribute \src "ls180.v:2277.59-2277.172" + cell $and $and$ls180.v:2277$175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247656,10 +247448,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:2286$175_Y + connect \Y $and$ls180.v:2277$175_Y end - attribute \src "ls180.v:2310.9-2310.76" - cell $and $and$ls180.v:2310$181 + attribute \src "ls180.v:2301.9-2301.76" + cell $and $and$ls180.v:2301$181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247667,10 +247459,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_twtpcon_ready connect \B \sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:2310$181_Y + connect \Y $and$ls180.v:2301$181_Y end - attribute \src "ls180.v:2322.9-2322.76" - cell $and $and$ls180.v:2322$182 + attribute \src "ls180.v:2313.9-2313.76" + cell $and $and$ls180.v:2313$182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247678,10 +247470,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_twtpcon_ready connect \B \sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:2322$182_Y + connect \Y $and$ls180.v:2313$182_Y end - attribute \src "ls180.v:2372.13-2372.77" - cell $and $and$ls180.v:2372$184 + attribute \src "ls180.v:2363.13-2363.77" + cell $and $and$ls180.v:2363$184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247689,10 +247481,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_ready connect \B \sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:2372$184_Y + connect \Y $and$ls180.v:2363$184_Y end - attribute \src "ls180.v:2408.45-2408.104" - cell $and $and$ls180.v:2408$191 + attribute \src "ls180.v:2399.45-2399.104" + cell $and $and$ls180.v:2399$191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247700,21 +247492,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B \sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:2408$191_Y + connect \Y $and$ls180.v:2399$191_Y end - attribute \src "ls180.v:2408.44-2408.147" - cell $and $and$ls180.v:2408$192 + attribute \src "ls180.v:2399.44-2399.147" + cell $and $and$ls180.v:2399$192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2408$191_Y + connect \A $and$ls180.v:2399$191_Y connect \B \sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:2408$192_Y + connect \Y $and$ls180.v:2399$192_Y end - attribute \src "ls180.v:2409.44-2409.103" - cell $and $and$ls180.v:2409$193 + attribute \src "ls180.v:2400.44-2400.103" + cell $and $and$ls180.v:2400$193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247722,21 +247514,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B \sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:2409$193_Y + connect \Y $and$ls180.v:2400$193_Y end - attribute \src "ls180.v:2409.43-2409.134" - cell $and $and$ls180.v:2409$194 + attribute \src "ls180.v:2400.43-2400.134" + cell $and $and$ls180.v:2400$194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2409$193_Y + connect \A $and$ls180.v:2400$193_Y connect \B \sdram_bankmachine3_row_open - connect \Y $and$ls180.v:2409$194_Y + connect \Y $and$ls180.v:2400$194_Y end - attribute \src "ls180.v:2410.45-2410.104" - cell $and $and$ls180.v:2410$195 + attribute \src "ls180.v:2401.45-2401.104" + cell $and $and$ls180.v:2401$195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247744,21 +247536,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B \sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:2410$195_Y + connect \Y $and$ls180.v:2401$195_Y end - attribute \src "ls180.v:2410.44-2410.135" - cell $and $and$ls180.v:2410$196 + attribute \src "ls180.v:2401.44-2401.135" + cell $and $and$ls180.v:2401$196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2410$195_Y + connect \A $and$ls180.v:2401$195_Y connect \B \sdram_bankmachine3_row_open - connect \Y $and$ls180.v:2410$196_Y + connect \Y $and$ls180.v:2401$196_Y end - attribute \src "ls180.v:2413.7-2413.104" - cell $and $and$ls180.v:2413$198 + attribute \src "ls180.v:2404.7-2404.104" + cell $and $and$ls180.v:2404$198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247766,21 +247558,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:2413$198_Y + connect \Y $and$ls180.v:2404$198_Y end - attribute \src "ls180.v:2442.61-2442.226" - cell $and $and$ls180.v:2442$204 + attribute \src "ls180.v:2433.61-2433.226" + cell $and $and$ls180.v:2433$204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:2442$203_Y - connect \Y $and$ls180.v:2442$204_Y + connect \B $or$ls180.v:2433$203_Y + connect \Y $and$ls180.v:2433$204_Y end - attribute \src "ls180.v:2443.59-2443.172" - cell $and $and$ls180.v:2443$205 + attribute \src "ls180.v:2434.59-2434.172" + cell $and $and$ls180.v:2434$205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247788,10 +247580,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:2443$205_Y + connect \Y $and$ls180.v:2434$205_Y end - attribute \src "ls180.v:2467.9-2467.76" - cell $and $and$ls180.v:2467$211 + attribute \src "ls180.v:2458.9-2458.76" + cell $and $and$ls180.v:2458$211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247799,10 +247591,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_twtpcon_ready connect \B \sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:2467$211_Y + connect \Y $and$ls180.v:2458$211_Y end - attribute \src "ls180.v:2479.9-2479.76" - cell $and $and$ls180.v:2479$212 + attribute \src "ls180.v:2470.9-2470.76" + cell $and $and$ls180.v:2470$212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247810,10 +247602,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_twtpcon_ready connect \B \sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:2479$212_Y + connect \Y $and$ls180.v:2470$212_Y end - attribute \src "ls180.v:2529.13-2529.77" - cell $and $and$ls180.v:2529$214 + attribute \src "ls180.v:2520.13-2520.77" + cell $and $and$ls180.v:2520$214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247821,10 +247613,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_ready connect \B \sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:2529$214_Y + connect \Y $and$ls180.v:2520$214_Y end - attribute \src "ls180.v:2544.32-2544.87" - cell $and $and$ls180.v:2544$215 + attribute \src "ls180.v:2535.32-2535.87" + cell $and $and$ls180.v:2535$215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247832,43 +247624,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:2544$215_Y + connect \Y $and$ls180.v:2535$215_Y end - attribute \src "ls180.v:2544.93-2544.163" - cell $and $and$ls180.v:2544$217 + attribute \src "ls180.v:2535.93-2535.163" + cell $and $and$ls180.v:2535$217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:2544$216_Y - connect \Y $and$ls180.v:2544$217_Y + connect \B $not$ls180.v:2535$216_Y + connect \Y $and$ls180.v:2535$217_Y end - attribute \src "ls180.v:2544.92-2544.201" - cell $and $and$ls180.v:2544$219 + attribute \src "ls180.v:2535.92-2535.201" + cell $and $and$ls180.v:2535$219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2544$217_Y - connect \B $not$ls180.v:2544$218_Y - connect \Y $and$ls180.v:2544$219_Y + connect \A $and$ls180.v:2535$217_Y + connect \B $not$ls180.v:2535$218_Y + connect \Y $and$ls180.v:2535$219_Y end - attribute \src "ls180.v:2544.31-2544.202" - cell $and $and$ls180.v:2544$220 + attribute \src "ls180.v:2535.31-2535.202" + cell $and $and$ls180.v:2535$220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2544$215_Y - connect \B $and$ls180.v:2544$219_Y - connect \Y $and$ls180.v:2544$220_Y + connect \A $and$ls180.v:2535$215_Y + connect \B $and$ls180.v:2535$219_Y + connect \Y $and$ls180.v:2535$220_Y end - attribute \src "ls180.v:2545.32-2545.87" - cell $and $and$ls180.v:2545$221 + attribute \src "ls180.v:2536.32-2536.87" + cell $and $and$ls180.v:2536$221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247876,43 +247668,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:2545$221_Y + connect \Y $and$ls180.v:2536$221_Y end - attribute \src "ls180.v:2545.93-2545.163" - cell $and $and$ls180.v:2545$223 + attribute \src "ls180.v:2536.93-2536.163" + cell $and $and$ls180.v:2536$223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:2545$222_Y - connect \Y $and$ls180.v:2545$223_Y + connect \B $not$ls180.v:2536$222_Y + connect \Y $and$ls180.v:2536$223_Y end - attribute \src "ls180.v:2545.92-2545.201" - cell $and $and$ls180.v:2545$225 + attribute \src "ls180.v:2536.92-2536.201" + cell $and $and$ls180.v:2536$225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2545$223_Y - connect \B $not$ls180.v:2545$224_Y - connect \Y $and$ls180.v:2545$225_Y + connect \A $and$ls180.v:2536$223_Y + connect \B $not$ls180.v:2536$224_Y + connect \Y $and$ls180.v:2536$225_Y end - attribute \src "ls180.v:2545.31-2545.202" - cell $and $and$ls180.v:2545$226 + attribute \src "ls180.v:2536.31-2536.202" + cell $and $and$ls180.v:2536$226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2545$221_Y - connect \B $and$ls180.v:2545$225_Y - connect \Y $and$ls180.v:2545$226_Y + connect \A $and$ls180.v:2536$221_Y + connect \B $and$ls180.v:2536$225_Y + connect \Y $and$ls180.v:2536$226_Y end - attribute \src "ls180.v:2546.29-2546.70" - cell $and $and$ls180.v:2546$227 + attribute \src "ls180.v:2537.29-2537.70" + cell $and $and$ls180.v:2537$227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247920,10 +247712,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_trrdcon_ready connect \B \sdram_tfawcon_ready - connect \Y $and$ls180.v:2546$227_Y + connect \Y $and$ls180.v:2537$227_Y end - attribute \src "ls180.v:2547.32-2547.87" - cell $and $and$ls180.v:2547$228 + attribute \src "ls180.v:2538.32-2538.87" + cell $and $and$ls180.v:2538$228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247931,21 +247723,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:2547$228_Y + connect \Y $and$ls180.v:2538$228_Y end - attribute \src "ls180.v:2547.31-2547.169" - cell $and $and$ls180.v:2547$230 + attribute \src "ls180.v:2538.31-2538.169" + cell $and $and$ls180.v:2538$230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2547$228_Y - connect \B $or$ls180.v:2547$229_Y - connect \Y $and$ls180.v:2547$230_Y + connect \A $and$ls180.v:2538$228_Y + connect \B $or$ls180.v:2538$229_Y + connect \Y $and$ls180.v:2538$230_Y end - attribute \src "ls180.v:2549.32-2549.87" - cell $and $and$ls180.v:2549$231 + attribute \src "ls180.v:2540.32-2540.87" + cell $and $and$ls180.v:2540$231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247953,21 +247745,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:2549$231_Y + connect \Y $and$ls180.v:2540$231_Y end - attribute \src "ls180.v:2549.31-2549.128" - cell $and $and$ls180.v:2549$232 + attribute \src "ls180.v:2540.31-2540.128" + cell $and $and$ls180.v:2540$232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2549$231_Y + connect \A $and$ls180.v:2540$231_Y connect \B \sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:2549$232_Y + connect \Y $and$ls180.v:2540$232_Y end - attribute \src "ls180.v:2550.35-2550.104" - cell $and $and$ls180.v:2550$233 + attribute \src "ls180.v:2541.35-2541.104" + cell $and $and$ls180.v:2541$233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247975,10 +247767,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B \sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:2550$233_Y + connect \Y $and$ls180.v:2541$233_Y end - attribute \src "ls180.v:2550.109-2550.178" - cell $and $and$ls180.v:2550$234 + attribute \src "ls180.v:2541.109-2541.178" + cell $and $and$ls180.v:2541$234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247986,10 +247778,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B \sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:2550$234_Y + connect \Y $and$ls180.v:2541$234_Y end - attribute \src "ls180.v:2550.184-2550.253" - cell $and $and$ls180.v:2550$236 + attribute \src "ls180.v:2541.184-2541.253" + cell $and $and$ls180.v:2541$236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247997,10 +247789,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B \sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:2550$236_Y + connect \Y $and$ls180.v:2541$236_Y end - attribute \src "ls180.v:2550.259-2550.328" - cell $and $and$ls180.v:2550$238 + attribute \src "ls180.v:2541.259-2541.328" + cell $and $and$ls180.v:2541$238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248008,10 +247800,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B \sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:2550$238_Y + connect \Y $and$ls180.v:2541$238_Y end - attribute \src "ls180.v:2551.36-2551.106" - cell $and $and$ls180.v:2551$240 + attribute \src "ls180.v:2542.36-2542.106" + cell $and $and$ls180.v:2542$240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248019,10 +247811,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B \sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:2551$240_Y + connect \Y $and$ls180.v:2542$240_Y end - attribute \src "ls180.v:2551.111-2551.181" - cell $and $and$ls180.v:2551$241 + attribute \src "ls180.v:2542.111-2542.181" + cell $and $and$ls180.v:2542$241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248030,10 +247822,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B \sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:2551$241_Y + connect \Y $and$ls180.v:2542$241_Y end - attribute \src "ls180.v:2551.187-2551.257" - cell $and $and$ls180.v:2551$243 + attribute \src "ls180.v:2542.187-2542.257" + cell $and $and$ls180.v:2542$243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248041,10 +247833,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B \sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:2551$243_Y + connect \Y $and$ls180.v:2542$243_Y end - attribute \src "ls180.v:2551.263-2551.333" - cell $and $and$ls180.v:2551$245 + attribute \src "ls180.v:2542.263-2542.333" + cell $and $and$ls180.v:2542$245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248052,10 +247844,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B \sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:2551$245_Y + connect \Y $and$ls180.v:2542$245_Y end - attribute \src "ls180.v:2558.33-2558.96" - cell $and $and$ls180.v:2558$249 + attribute \src "ls180.v:2549.33-2549.96" + cell $and $and$ls180.v:2549$249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248063,32 +247855,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_refresh_gnt connect \B \sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:2558$249_Y + connect \Y $and$ls180.v:2549$249_Y end - attribute \src "ls180.v:2558.32-2558.130" - cell $and $and$ls180.v:2558$250 + attribute \src "ls180.v:2549.32-2549.130" + cell $and $and$ls180.v:2549$250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2558$249_Y + connect \A $and$ls180.v:2549$249_Y connect \B \sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:2558$250_Y + connect \Y $and$ls180.v:2549$250_Y end - attribute \src "ls180.v:2558.31-2558.164" - cell $and $and$ls180.v:2558$251 + attribute \src "ls180.v:2549.31-2549.164" + cell $and $and$ls180.v:2549$251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2558$250_Y + connect \A $and$ls180.v:2549$250_Y connect \B \sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:2558$251_Y + connect \Y $and$ls180.v:2549$251_Y end - attribute \src "ls180.v:2564.67-2564.133" - cell $and $and$ls180.v:2564$254 + attribute \src "ls180.v:2555.67-2555.133" + cell $and $and$ls180.v:2555$254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248096,65 +247888,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_cmd connect \B \sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:2564$254_Y + connect \Y $and$ls180.v:2555$254_Y end - attribute \src "ls180.v:2564.142-2564.216" - cell $and $and$ls180.v:2564$256 + attribute \src "ls180.v:2555.142-2555.216" + cell $and $and$ls180.v:2555$256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:2564$255_Y - connect \Y $and$ls180.v:2564$256_Y + connect \B $not$ls180.v:2555$255_Y + connect \Y $and$ls180.v:2555$256_Y end - attribute \src "ls180.v:2564.141-2564.256" - cell $and $and$ls180.v:2564$258 + attribute \src "ls180.v:2555.141-2555.256" + cell $and $and$ls180.v:2555$258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2564$256_Y - connect \B $not$ls180.v:2564$257_Y - connect \Y $and$ls180.v:2564$258_Y + connect \A $and$ls180.v:2555$256_Y + connect \B $not$ls180.v:2555$257_Y + connect \Y $and$ls180.v:2555$258_Y end - attribute \src "ls180.v:2564.66-2564.293" - cell $and $and$ls180.v:2564$261 + attribute \src "ls180.v:2555.66-2555.293" + cell $and $and$ls180.v:2555$261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2564$254_Y - connect \B $or$ls180.v:2564$260_Y - connect \Y $and$ls180.v:2564$261_Y + connect \A $and$ls180.v:2555$254_Y + connect \B $or$ls180.v:2555$260_Y + connect \Y $and$ls180.v:2555$261_Y end - attribute \src "ls180.v:2564.298-2564.445" - cell $and $and$ls180.v:2564$264 + attribute \src "ls180.v:2555.298-2555.445" + cell $and $and$ls180.v:2555$264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2564$262_Y - connect \B $eq$ls180.v:2564$263_Y - connect \Y $and$ls180.v:2564$264_Y + connect \A $eq$ls180.v:2555$262_Y + connect \B $eq$ls180.v:2555$263_Y + connect \Y $and$ls180.v:2555$264_Y end - attribute \src "ls180.v:2564.33-2564.447" - cell $and $and$ls180.v:2564$266 + attribute \src "ls180.v:2555.33-2555.447" + cell $and $and$ls180.v:2555$266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:2564$265_Y - connect \Y $and$ls180.v:2564$266_Y + connect \B $or$ls180.v:2555$265_Y + connect \Y $and$ls180.v:2555$266_Y end - attribute \src "ls180.v:2565.67-2565.133" - cell $and $and$ls180.v:2565$267 + attribute \src "ls180.v:2556.67-2556.133" + cell $and $and$ls180.v:2556$267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248162,65 +247954,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_cmd connect \B \sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:2565$267_Y + connect \Y $and$ls180.v:2556$267_Y end - attribute \src "ls180.v:2565.142-2565.216" - cell $and $and$ls180.v:2565$269 + attribute \src "ls180.v:2556.142-2556.216" + cell $and $and$ls180.v:2556$269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:2565$268_Y - connect \Y $and$ls180.v:2565$269_Y + connect \B $not$ls180.v:2556$268_Y + connect \Y $and$ls180.v:2556$269_Y end - attribute \src "ls180.v:2565.141-2565.256" - cell $and $and$ls180.v:2565$271 + attribute \src "ls180.v:2556.141-2556.256" + cell $and $and$ls180.v:2556$271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2565$269_Y - connect \B $not$ls180.v:2565$270_Y - connect \Y $and$ls180.v:2565$271_Y + connect \A $and$ls180.v:2556$269_Y + connect \B $not$ls180.v:2556$270_Y + connect \Y $and$ls180.v:2556$271_Y end - attribute \src "ls180.v:2565.66-2565.293" - cell $and $and$ls180.v:2565$274 + attribute \src "ls180.v:2556.66-2556.293" + cell $and $and$ls180.v:2556$274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2565$267_Y - connect \B $or$ls180.v:2565$273_Y - connect \Y $and$ls180.v:2565$274_Y + connect \A $and$ls180.v:2556$267_Y + connect \B $or$ls180.v:2556$273_Y + connect \Y $and$ls180.v:2556$274_Y end - attribute \src "ls180.v:2565.298-2565.445" - cell $and $and$ls180.v:2565$277 + attribute \src "ls180.v:2556.298-2556.445" + cell $and $and$ls180.v:2556$277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2565$275_Y - connect \B $eq$ls180.v:2565$276_Y - connect \Y $and$ls180.v:2565$277_Y + connect \A $eq$ls180.v:2556$275_Y + connect \B $eq$ls180.v:2556$276_Y + connect \Y $and$ls180.v:2556$277_Y end - attribute \src "ls180.v:2565.33-2565.447" - cell $and $and$ls180.v:2565$279 + attribute \src "ls180.v:2556.33-2556.447" + cell $and $and$ls180.v:2556$279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:2565$278_Y - connect \Y $and$ls180.v:2565$279_Y + connect \B $or$ls180.v:2556$278_Y + connect \Y $and$ls180.v:2556$279_Y end - attribute \src "ls180.v:2566.67-2566.133" - cell $and $and$ls180.v:2566$280 + attribute \src "ls180.v:2557.67-2557.133" + cell $and $and$ls180.v:2557$280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248228,65 +248020,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_cmd connect \B \sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:2566$280_Y + connect \Y $and$ls180.v:2557$280_Y end - attribute \src "ls180.v:2566.142-2566.216" - cell $and $and$ls180.v:2566$282 + attribute \src "ls180.v:2557.142-2557.216" + cell $and $and$ls180.v:2557$282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:2566$281_Y - connect \Y $and$ls180.v:2566$282_Y + connect \B $not$ls180.v:2557$281_Y + connect \Y $and$ls180.v:2557$282_Y end - attribute \src "ls180.v:2566.141-2566.256" - cell $and $and$ls180.v:2566$284 + attribute \src "ls180.v:2557.141-2557.256" + cell $and $and$ls180.v:2557$284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2566$282_Y - connect \B $not$ls180.v:2566$283_Y - connect \Y $and$ls180.v:2566$284_Y + connect \A $and$ls180.v:2557$282_Y + connect \B $not$ls180.v:2557$283_Y + connect \Y $and$ls180.v:2557$284_Y end - attribute \src "ls180.v:2566.66-2566.293" - cell $and $and$ls180.v:2566$287 + attribute \src "ls180.v:2557.66-2557.293" + cell $and $and$ls180.v:2557$287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2566$280_Y - connect \B $or$ls180.v:2566$286_Y - connect \Y $and$ls180.v:2566$287_Y + connect \A $and$ls180.v:2557$280_Y + connect \B $or$ls180.v:2557$286_Y + connect \Y $and$ls180.v:2557$287_Y end - attribute \src "ls180.v:2566.298-2566.445" - cell $and $and$ls180.v:2566$290 + attribute \src "ls180.v:2557.298-2557.445" + cell $and $and$ls180.v:2557$290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2566$288_Y - connect \B $eq$ls180.v:2566$289_Y - connect \Y $and$ls180.v:2566$290_Y + connect \A $eq$ls180.v:2557$288_Y + connect \B $eq$ls180.v:2557$289_Y + connect \Y $and$ls180.v:2557$290_Y end - attribute \src "ls180.v:2566.33-2566.447" - cell $and $and$ls180.v:2566$292 + attribute \src "ls180.v:2557.33-2557.447" + cell $and $and$ls180.v:2557$292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:2566$291_Y - connect \Y $and$ls180.v:2566$292_Y + connect \B $or$ls180.v:2557$291_Y + connect \Y $and$ls180.v:2557$292_Y end - attribute \src "ls180.v:2567.67-2567.133" - cell $and $and$ls180.v:2567$293 + attribute \src "ls180.v:2558.67-2558.133" + cell $and $and$ls180.v:2558$293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248294,65 +248086,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_cmd connect \B \sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:2567$293_Y + connect \Y $and$ls180.v:2558$293_Y end - attribute \src "ls180.v:2567.142-2567.216" - cell $and $and$ls180.v:2567$295 + attribute \src "ls180.v:2558.142-2558.216" + cell $and $and$ls180.v:2558$295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:2567$294_Y - connect \Y $and$ls180.v:2567$295_Y + connect \B $not$ls180.v:2558$294_Y + connect \Y $and$ls180.v:2558$295_Y end - attribute \src "ls180.v:2567.141-2567.256" - cell $and $and$ls180.v:2567$297 + attribute \src "ls180.v:2558.141-2558.256" + cell $and $and$ls180.v:2558$297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2567$295_Y - connect \B $not$ls180.v:2567$296_Y - connect \Y $and$ls180.v:2567$297_Y + connect \A $and$ls180.v:2558$295_Y + connect \B $not$ls180.v:2558$296_Y + connect \Y $and$ls180.v:2558$297_Y end - attribute \src "ls180.v:2567.66-2567.293" - cell $and $and$ls180.v:2567$300 + attribute \src "ls180.v:2558.66-2558.293" + cell $and $and$ls180.v:2558$300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2567$293_Y - connect \B $or$ls180.v:2567$299_Y - connect \Y $and$ls180.v:2567$300_Y + connect \A $and$ls180.v:2558$293_Y + connect \B $or$ls180.v:2558$299_Y + connect \Y $and$ls180.v:2558$300_Y end - attribute \src "ls180.v:2567.298-2567.445" - cell $and $and$ls180.v:2567$303 + attribute \src "ls180.v:2558.298-2558.445" + cell $and $and$ls180.v:2558$303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2567$301_Y - connect \B $eq$ls180.v:2567$302_Y - connect \Y $and$ls180.v:2567$303_Y + connect \A $eq$ls180.v:2558$301_Y + connect \B $eq$ls180.v:2558$302_Y + connect \Y $and$ls180.v:2558$303_Y end - attribute \src "ls180.v:2567.33-2567.447" - cell $and $and$ls180.v:2567$305 + attribute \src "ls180.v:2558.33-2558.447" + cell $and $and$ls180.v:2558$305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:2567$304_Y - connect \Y $and$ls180.v:2567$305_Y + connect \B $or$ls180.v:2558$304_Y + connect \Y $and$ls180.v:2558$305_Y end - attribute \src "ls180.v:2597.67-2597.133" - cell $and $and$ls180.v:2597$312 + attribute \src "ls180.v:2588.67-2588.133" + cell $and $and$ls180.v:2588$312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248360,65 +248152,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_cmd connect \B \sdram_choose_req_want_cmds - connect \Y $and$ls180.v:2597$312_Y + connect \Y $and$ls180.v:2588$312_Y end - attribute \src "ls180.v:2597.142-2597.216" - cell $and $and$ls180.v:2597$314 + attribute \src "ls180.v:2588.142-2588.216" + cell $and $and$ls180.v:2588$314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:2597$313_Y - connect \Y $and$ls180.v:2597$314_Y + connect \B $not$ls180.v:2588$313_Y + connect \Y $and$ls180.v:2588$314_Y end - attribute \src "ls180.v:2597.141-2597.256" - cell $and $and$ls180.v:2597$316 + attribute \src "ls180.v:2588.141-2588.256" + cell $and $and$ls180.v:2588$316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2597$314_Y - connect \B $not$ls180.v:2597$315_Y - connect \Y $and$ls180.v:2597$316_Y + connect \A $and$ls180.v:2588$314_Y + connect \B $not$ls180.v:2588$315_Y + connect \Y $and$ls180.v:2588$316_Y end - attribute \src "ls180.v:2597.66-2597.293" - cell $and $and$ls180.v:2597$319 + attribute \src "ls180.v:2588.66-2588.293" + cell $and $and$ls180.v:2588$319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2597$312_Y - connect \B $or$ls180.v:2597$318_Y - connect \Y $and$ls180.v:2597$319_Y + connect \A $and$ls180.v:2588$312_Y + connect \B $or$ls180.v:2588$318_Y + connect \Y $and$ls180.v:2588$319_Y end - attribute \src "ls180.v:2597.298-2597.445" - cell $and $and$ls180.v:2597$322 + attribute \src "ls180.v:2588.298-2588.445" + cell $and $and$ls180.v:2588$322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2597$320_Y - connect \B $eq$ls180.v:2597$321_Y - connect \Y $and$ls180.v:2597$322_Y + connect \A $eq$ls180.v:2588$320_Y + connect \B $eq$ls180.v:2588$321_Y + connect \Y $and$ls180.v:2588$322_Y end - attribute \src "ls180.v:2597.33-2597.447" - cell $and $and$ls180.v:2597$324 + attribute \src "ls180.v:2588.33-2588.447" + cell $and $and$ls180.v:2588$324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:2597$323_Y - connect \Y $and$ls180.v:2597$324_Y + connect \B $or$ls180.v:2588$323_Y + connect \Y $and$ls180.v:2588$324_Y end - attribute \src "ls180.v:2598.67-2598.133" - cell $and $and$ls180.v:2598$325 + attribute \src "ls180.v:2589.67-2589.133" + cell $and $and$ls180.v:2589$325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248426,65 +248218,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_cmd connect \B \sdram_choose_req_want_cmds - connect \Y $and$ls180.v:2598$325_Y + connect \Y $and$ls180.v:2589$325_Y end - attribute \src "ls180.v:2598.142-2598.216" - cell $and $and$ls180.v:2598$327 + attribute \src "ls180.v:2589.142-2589.216" + cell $and $and$ls180.v:2589$327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:2598$326_Y - connect \Y $and$ls180.v:2598$327_Y + connect \B $not$ls180.v:2589$326_Y + connect \Y $and$ls180.v:2589$327_Y end - attribute \src "ls180.v:2598.141-2598.256" - cell $and $and$ls180.v:2598$329 + attribute \src "ls180.v:2589.141-2589.256" + cell $and $and$ls180.v:2589$329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2598$327_Y - connect \B $not$ls180.v:2598$328_Y - connect \Y $and$ls180.v:2598$329_Y + connect \A $and$ls180.v:2589$327_Y + connect \B $not$ls180.v:2589$328_Y + connect \Y $and$ls180.v:2589$329_Y end - attribute \src "ls180.v:2598.66-2598.293" - cell $and $and$ls180.v:2598$332 + attribute \src "ls180.v:2589.66-2589.293" + cell $and $and$ls180.v:2589$332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2598$325_Y - connect \B $or$ls180.v:2598$331_Y - connect \Y $and$ls180.v:2598$332_Y + connect \A $and$ls180.v:2589$325_Y + connect \B $or$ls180.v:2589$331_Y + connect \Y $and$ls180.v:2589$332_Y end - attribute \src "ls180.v:2598.298-2598.445" - cell $and $and$ls180.v:2598$335 + attribute \src "ls180.v:2589.298-2589.445" + cell $and $and$ls180.v:2589$335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2598$333_Y - connect \B $eq$ls180.v:2598$334_Y - connect \Y $and$ls180.v:2598$335_Y + connect \A $eq$ls180.v:2589$333_Y + connect \B $eq$ls180.v:2589$334_Y + connect \Y $and$ls180.v:2589$335_Y end - attribute \src "ls180.v:2598.33-2598.447" - cell $and $and$ls180.v:2598$337 + attribute \src "ls180.v:2589.33-2589.447" + cell $and $and$ls180.v:2589$337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:2598$336_Y - connect \Y $and$ls180.v:2598$337_Y + connect \B $or$ls180.v:2589$336_Y + connect \Y $and$ls180.v:2589$337_Y end - attribute \src "ls180.v:2599.67-2599.133" - cell $and $and$ls180.v:2599$338 + attribute \src "ls180.v:2590.67-2590.133" + cell $and $and$ls180.v:2590$338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248492,65 +248284,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_cmd connect \B \sdram_choose_req_want_cmds - connect \Y $and$ls180.v:2599$338_Y + connect \Y $and$ls180.v:2590$338_Y end - attribute \src "ls180.v:2599.142-2599.216" - cell $and $and$ls180.v:2599$340 + attribute \src "ls180.v:2590.142-2590.216" + cell $and $and$ls180.v:2590$340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:2599$339_Y - connect \Y $and$ls180.v:2599$340_Y + connect \B $not$ls180.v:2590$339_Y + connect \Y $and$ls180.v:2590$340_Y end - attribute \src "ls180.v:2599.141-2599.256" - cell $and $and$ls180.v:2599$342 + attribute \src "ls180.v:2590.141-2590.256" + cell $and $and$ls180.v:2590$342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2599$340_Y - connect \B $not$ls180.v:2599$341_Y - connect \Y $and$ls180.v:2599$342_Y + connect \A $and$ls180.v:2590$340_Y + connect \B $not$ls180.v:2590$341_Y + connect \Y $and$ls180.v:2590$342_Y end - attribute \src "ls180.v:2599.66-2599.293" - cell $and $and$ls180.v:2599$345 + attribute \src "ls180.v:2590.66-2590.293" + cell $and $and$ls180.v:2590$345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2599$338_Y - connect \B $or$ls180.v:2599$344_Y - connect \Y $and$ls180.v:2599$345_Y + connect \A $and$ls180.v:2590$338_Y + connect \B $or$ls180.v:2590$344_Y + connect \Y $and$ls180.v:2590$345_Y end - attribute \src "ls180.v:2599.298-2599.445" - cell $and $and$ls180.v:2599$348 + attribute \src "ls180.v:2590.298-2590.445" + cell $and $and$ls180.v:2590$348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2599$346_Y - connect \B $eq$ls180.v:2599$347_Y - connect \Y $and$ls180.v:2599$348_Y + connect \A $eq$ls180.v:2590$346_Y + connect \B $eq$ls180.v:2590$347_Y + connect \Y $and$ls180.v:2590$348_Y end - attribute \src "ls180.v:2599.33-2599.447" - cell $and $and$ls180.v:2599$350 + attribute \src "ls180.v:2590.33-2590.447" + cell $and $and$ls180.v:2590$350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:2599$349_Y - connect \Y $and$ls180.v:2599$350_Y + connect \B $or$ls180.v:2590$349_Y + connect \Y $and$ls180.v:2590$350_Y end - attribute \src "ls180.v:2600.67-2600.133" - cell $and $and$ls180.v:2600$351 + attribute \src "ls180.v:2591.67-2591.133" + cell $and $and$ls180.v:2591$351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248558,65 +248350,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_cmd connect \B \sdram_choose_req_want_cmds - connect \Y $and$ls180.v:2600$351_Y + connect \Y $and$ls180.v:2591$351_Y end - attribute \src "ls180.v:2600.142-2600.216" - cell $and $and$ls180.v:2600$353 + attribute \src "ls180.v:2591.142-2591.216" + cell $and $and$ls180.v:2591$353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:2600$352_Y - connect \Y $and$ls180.v:2600$353_Y + connect \B $not$ls180.v:2591$352_Y + connect \Y $and$ls180.v:2591$353_Y end - attribute \src "ls180.v:2600.141-2600.256" - cell $and $and$ls180.v:2600$355 + attribute \src "ls180.v:2591.141-2591.256" + cell $and $and$ls180.v:2591$355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2600$353_Y - connect \B $not$ls180.v:2600$354_Y - connect \Y $and$ls180.v:2600$355_Y + connect \A $and$ls180.v:2591$353_Y + connect \B $not$ls180.v:2591$354_Y + connect \Y $and$ls180.v:2591$355_Y end - attribute \src "ls180.v:2600.66-2600.293" - cell $and $and$ls180.v:2600$358 + attribute \src "ls180.v:2591.66-2591.293" + cell $and $and$ls180.v:2591$358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2600$351_Y - connect \B $or$ls180.v:2600$357_Y - connect \Y $and$ls180.v:2600$358_Y + connect \A $and$ls180.v:2591$351_Y + connect \B $or$ls180.v:2591$357_Y + connect \Y $and$ls180.v:2591$358_Y end - attribute \src "ls180.v:2600.298-2600.445" - cell $and $and$ls180.v:2600$361 + attribute \src "ls180.v:2591.298-2591.445" + cell $and $and$ls180.v:2591$361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2600$359_Y - connect \B $eq$ls180.v:2600$360_Y - connect \Y $and$ls180.v:2600$361_Y + connect \A $eq$ls180.v:2591$359_Y + connect \B $eq$ls180.v:2591$360_Y + connect \Y $and$ls180.v:2591$361_Y end - attribute \src "ls180.v:2600.33-2600.447" - cell $and $and$ls180.v:2600$363 + attribute \src "ls180.v:2591.33-2591.447" + cell $and $and$ls180.v:2591$363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:2600$362_Y - connect \Y $and$ls180.v:2600$363_Y + connect \B $or$ls180.v:2591$362_Y + connect \Y $and$ls180.v:2591$363_Y end - attribute \src "ls180.v:2629.8-2629.63" - cell $and $and$ls180.v:2629$368 + attribute \src "ls180.v:2620.8-2620.63" + cell $and $and$ls180.v:2620$368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248624,21 +248416,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_valid connect \B \sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:2629$368_Y + connect \Y $and$ls180.v:2620$368_Y end - attribute \src "ls180.v:2629.7-2629.99" - cell $and $and$ls180.v:2629$370 + attribute \src "ls180.v:2620.7-2620.99" + cell $and $and$ls180.v:2620$370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2629$368_Y - connect \B $eq$ls180.v:2629$369_Y - connect \Y $and$ls180.v:2629$370_Y + connect \A $and$ls180.v:2620$368_Y + connect \B $eq$ls180.v:2620$369_Y + connect \Y $and$ls180.v:2620$370_Y end - attribute \src "ls180.v:2632.8-2632.63" - cell $and $and$ls180.v:2632$371 + attribute \src "ls180.v:2623.8-2623.63" + cell $and $and$ls180.v:2623$371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248646,21 +248438,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:2632$371_Y + connect \Y $and$ls180.v:2623$371_Y end - attribute \src "ls180.v:2632.7-2632.99" - cell $and $and$ls180.v:2632$373 + attribute \src "ls180.v:2623.7-2623.99" + cell $and $and$ls180.v:2623$373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2632$371_Y - connect \B $eq$ls180.v:2632$372_Y - connect \Y $and$ls180.v:2632$373_Y + connect \A $and$ls180.v:2623$371_Y + connect \B $eq$ls180.v:2623$372_Y + connect \Y $and$ls180.v:2623$373_Y end - attribute \src "ls180.v:2638.8-2638.63" - cell $and $and$ls180.v:2638$375 + attribute \src "ls180.v:2629.8-2629.63" + cell $and $and$ls180.v:2629$375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248668,21 +248460,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_valid connect \B \sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:2638$375_Y + connect \Y $and$ls180.v:2629$375_Y end - attribute \src "ls180.v:2638.7-2638.99" - cell $and $and$ls180.v:2638$377 + attribute \src "ls180.v:2629.7-2629.99" + cell $and $and$ls180.v:2629$377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2638$375_Y - connect \B $eq$ls180.v:2638$376_Y - connect \Y $and$ls180.v:2638$377_Y + connect \A $and$ls180.v:2629$375_Y + connect \B $eq$ls180.v:2629$376_Y + connect \Y $and$ls180.v:2629$377_Y end - attribute \src "ls180.v:2641.8-2641.63" - cell $and $and$ls180.v:2641$378 + attribute \src "ls180.v:2632.8-2632.63" + cell $and $and$ls180.v:2632$378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248690,21 +248482,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:2641$378_Y + connect \Y $and$ls180.v:2632$378_Y end - attribute \src "ls180.v:2641.7-2641.99" - cell $and $and$ls180.v:2641$380 + attribute \src "ls180.v:2632.7-2632.99" + cell $and $and$ls180.v:2632$380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2641$378_Y - connect \B $eq$ls180.v:2641$379_Y - connect \Y $and$ls180.v:2641$380_Y + connect \A $and$ls180.v:2632$378_Y + connect \B $eq$ls180.v:2632$379_Y + connect \Y $and$ls180.v:2632$380_Y end - attribute \src "ls180.v:2647.8-2647.63" - cell $and $and$ls180.v:2647$382 + attribute \src "ls180.v:2638.8-2638.63" + cell $and $and$ls180.v:2638$382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248712,21 +248504,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_valid connect \B \sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:2647$382_Y + connect \Y $and$ls180.v:2638$382_Y end - attribute \src "ls180.v:2647.7-2647.99" - cell $and $and$ls180.v:2647$384 + attribute \src "ls180.v:2638.7-2638.99" + cell $and $and$ls180.v:2638$384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2647$382_Y - connect \B $eq$ls180.v:2647$383_Y - connect \Y $and$ls180.v:2647$384_Y + connect \A $and$ls180.v:2638$382_Y + connect \B $eq$ls180.v:2638$383_Y + connect \Y $and$ls180.v:2638$384_Y end - attribute \src "ls180.v:2650.8-2650.63" - cell $and $and$ls180.v:2650$385 + attribute \src "ls180.v:2641.8-2641.63" + cell $and $and$ls180.v:2641$385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248734,21 +248526,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:2650$385_Y + connect \Y $and$ls180.v:2641$385_Y end - attribute \src "ls180.v:2650.7-2650.99" - cell $and $and$ls180.v:2650$387 + attribute \src "ls180.v:2641.7-2641.99" + cell $and $and$ls180.v:2641$387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2650$385_Y - connect \B $eq$ls180.v:2650$386_Y - connect \Y $and$ls180.v:2650$387_Y + connect \A $and$ls180.v:2641$385_Y + connect \B $eq$ls180.v:2641$386_Y + connect \Y $and$ls180.v:2641$387_Y end - attribute \src "ls180.v:2656.8-2656.63" - cell $and $and$ls180.v:2656$389 + attribute \src "ls180.v:2647.8-2647.63" + cell $and $and$ls180.v:2647$389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248756,21 +248548,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_valid connect \B \sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:2656$389_Y + connect \Y $and$ls180.v:2647$389_Y end - attribute \src "ls180.v:2656.7-2656.99" - cell $and $and$ls180.v:2656$391 + attribute \src "ls180.v:2647.7-2647.99" + cell $and $and$ls180.v:2647$391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2656$389_Y - connect \B $eq$ls180.v:2656$390_Y - connect \Y $and$ls180.v:2656$391_Y + connect \A $and$ls180.v:2647$389_Y + connect \B $eq$ls180.v:2647$390_Y + connect \Y $and$ls180.v:2647$391_Y end - attribute \src "ls180.v:2659.8-2659.63" - cell $and $and$ls180.v:2659$392 + attribute \src "ls180.v:2650.8-2650.63" + cell $and $and$ls180.v:2650$392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248778,615 +248570,615 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:2659$392_Y + connect \Y $and$ls180.v:2650$392_Y end - attribute \src "ls180.v:2659.7-2659.99" - cell $and $and$ls180.v:2659$394 + attribute \src "ls180.v:2650.7-2650.99" + cell $and $and$ls180.v:2650$394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2659$392_Y - connect \B $eq$ls180.v:2659$393_Y - connect \Y $and$ls180.v:2659$394_Y + connect \A $and$ls180.v:2650$392_Y + connect \B $eq$ls180.v:2650$393_Y + connect \Y $and$ls180.v:2650$394_Y end - attribute \src "ls180.v:2684.61-2684.131" - cell $and $and$ls180.v:2684$399 + attribute \src "ls180.v:2675.61-2675.131" + cell $and $and$ls180.v:2675$399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:2684$398_Y - connect \Y $and$ls180.v:2684$399_Y + connect \B $not$ls180.v:2675$398_Y + connect \Y $and$ls180.v:2675$399_Y end - attribute \src "ls180.v:2684.60-2684.169" - cell $and $and$ls180.v:2684$401 + attribute \src "ls180.v:2675.60-2675.169" + cell $and $and$ls180.v:2675$401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2684$399_Y - connect \B $not$ls180.v:2684$400_Y - connect \Y $and$ls180.v:2684$401_Y + connect \A $and$ls180.v:2675$399_Y + connect \B $not$ls180.v:2675$400_Y + connect \Y $and$ls180.v:2675$401_Y end - attribute \src "ls180.v:2684.36-2684.192" - cell $and $and$ls180.v:2684$404 + attribute \src "ls180.v:2675.36-2675.192" + cell $and $and$ls180.v:2675$404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_cas_allowed - connect \B $or$ls180.v:2684$403_Y - connect \Y $and$ls180.v:2684$404_Y + connect \B $or$ls180.v:2675$403_Y + connect \Y $and$ls180.v:2675$404_Y end - attribute \src "ls180.v:2722.61-2722.131" - cell $and $and$ls180.v:2722$408 + attribute \src "ls180.v:2713.61-2713.131" + cell $and $and$ls180.v:2713$408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:2722$407_Y - connect \Y $and$ls180.v:2722$408_Y + connect \B $not$ls180.v:2713$407_Y + connect \Y $and$ls180.v:2713$408_Y end - attribute \src "ls180.v:2722.60-2722.169" - cell $and $and$ls180.v:2722$410 + attribute \src "ls180.v:2713.60-2713.169" + cell $and $and$ls180.v:2713$410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2722$408_Y - connect \B $not$ls180.v:2722$409_Y - connect \Y $and$ls180.v:2722$410_Y + connect \A $and$ls180.v:2713$408_Y + connect \B $not$ls180.v:2713$409_Y + connect \Y $and$ls180.v:2713$410_Y end - attribute \src "ls180.v:2722.36-2722.192" - cell $and $and$ls180.v:2722$413 + attribute \src "ls180.v:2713.36-2713.192" + cell $and $and$ls180.v:2713$413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_cas_allowed - connect \B $or$ls180.v:2722$412_Y - connect \Y $and$ls180.v:2722$413_Y + connect \B $or$ls180.v:2713$412_Y + connect \Y $and$ls180.v:2713$413_Y end - attribute \src "ls180.v:2740.115-2740.184" - cell $and $and$ls180.v:2740$418 + attribute \src "ls180.v:2731.115-2731.184" + cell $and $and$ls180.v:2731$418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock - connect \B $eq$ls180.v:2740$417_Y - connect \Y $and$ls180.v:2740$418_Y + connect \B $eq$ls180.v:2731$417_Y + connect \Y $and$ls180.v:2731$418_Y end - attribute \src "ls180.v:2740.190-2740.259" - cell $and $and$ls180.v:2740$421 + attribute \src "ls180.v:2731.190-2731.259" + cell $and $and$ls180.v:2731$421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock - connect \B $eq$ls180.v:2740$420_Y - connect \Y $and$ls180.v:2740$421_Y + connect \B $eq$ls180.v:2731$420_Y + connect \Y $and$ls180.v:2731$421_Y end - attribute \src "ls180.v:2740.265-2740.334" - cell $and $and$ls180.v:2740$424 + attribute \src "ls180.v:2731.265-2731.334" + cell $and $and$ls180.v:2731$424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock - connect \B $eq$ls180.v:2740$423_Y - connect \Y $and$ls180.v:2740$424_Y + connect \B $eq$ls180.v:2731$423_Y + connect \Y $and$ls180.v:2731$424_Y end - attribute \src "ls180.v:2740.46-2740.337" - cell $and $and$ls180.v:2740$427 + attribute \src "ls180.v:2731.46-2731.337" + cell $and $and$ls180.v:2731$427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2740$416_Y - connect \B $not$ls180.v:2740$426_Y - connect \Y $and$ls180.v:2740$427_Y + connect \A $eq$ls180.v:2731$416_Y + connect \B $not$ls180.v:2731$426_Y + connect \Y $and$ls180.v:2731$427_Y end - attribute \src "ls180.v:2740.45-2740.355" - cell $and $and$ls180.v:2740$428 + attribute \src "ls180.v:2731.45-2731.355" + cell $and $and$ls180.v:2731$428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2740$427_Y + connect \A $and$ls180.v:2731$427_Y connect \B \port_cmd_valid - connect \Y $and$ls180.v:2740$428_Y + connect \Y $and$ls180.v:2731$428_Y end - attribute \src "ls180.v:2741.39-2741.101" - cell $and $and$ls180.v:2741$431 + attribute \src "ls180.v:2732.39-2732.101" + cell $and $and$ls180.v:2732$431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2741$429_Y - connect \B $not$ls180.v:2741$430_Y - connect \Y $and$ls180.v:2741$431_Y + connect \A $not$ls180.v:2732$429_Y + connect \B $not$ls180.v:2732$430_Y + connect \Y $and$ls180.v:2732$431_Y end - attribute \src "ls180.v:2745.115-2745.184" - cell $and $and$ls180.v:2745$434 + attribute \src "ls180.v:2736.115-2736.184" + cell $and $and$ls180.v:2736$434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock - connect \B $eq$ls180.v:2745$433_Y - connect \Y $and$ls180.v:2745$434_Y + connect \B $eq$ls180.v:2736$433_Y + connect \Y $and$ls180.v:2736$434_Y end - attribute \src "ls180.v:2745.190-2745.259" - cell $and $and$ls180.v:2745$437 + attribute \src "ls180.v:2736.190-2736.259" + cell $and $and$ls180.v:2736$437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock - connect \B $eq$ls180.v:2745$436_Y - connect \Y $and$ls180.v:2745$437_Y + connect \B $eq$ls180.v:2736$436_Y + connect \Y $and$ls180.v:2736$437_Y end - attribute \src "ls180.v:2745.265-2745.334" - cell $and $and$ls180.v:2745$440 + attribute \src "ls180.v:2736.265-2736.334" + cell $and $and$ls180.v:2736$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock - connect \B $eq$ls180.v:2745$439_Y - connect \Y $and$ls180.v:2745$440_Y + connect \B $eq$ls180.v:2736$439_Y + connect \Y $and$ls180.v:2736$440_Y end - attribute \src "ls180.v:2745.46-2745.337" - cell $and $and$ls180.v:2745$443 + attribute \src "ls180.v:2736.46-2736.337" + cell $and $and$ls180.v:2736$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2745$432_Y - connect \B $not$ls180.v:2745$442_Y - connect \Y $and$ls180.v:2745$443_Y + connect \A $eq$ls180.v:2736$432_Y + connect \B $not$ls180.v:2736$442_Y + connect \Y $and$ls180.v:2736$443_Y end - attribute \src "ls180.v:2745.45-2745.355" - cell $and $and$ls180.v:2745$444 + attribute \src "ls180.v:2736.45-2736.355" + cell $and $and$ls180.v:2736$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2745$443_Y + connect \A $and$ls180.v:2736$443_Y connect \B \port_cmd_valid - connect \Y $and$ls180.v:2745$444_Y + connect \Y $and$ls180.v:2736$444_Y end - attribute \src "ls180.v:2746.39-2746.101" - cell $and $and$ls180.v:2746$447 + attribute \src "ls180.v:2737.39-2737.101" + cell $and $and$ls180.v:2737$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2746$445_Y - connect \B $not$ls180.v:2746$446_Y - connect \Y $and$ls180.v:2746$447_Y + connect \A $not$ls180.v:2737$445_Y + connect \B $not$ls180.v:2737$446_Y + connect \Y $and$ls180.v:2737$447_Y end - attribute \src "ls180.v:2750.115-2750.184" - cell $and $and$ls180.v:2750$450 + attribute \src "ls180.v:2741.115-2741.184" + cell $and $and$ls180.v:2741$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock - connect \B $eq$ls180.v:2750$449_Y - connect \Y $and$ls180.v:2750$450_Y + connect \B $eq$ls180.v:2741$449_Y + connect \Y $and$ls180.v:2741$450_Y end - attribute \src "ls180.v:2750.190-2750.259" - cell $and $and$ls180.v:2750$453 + attribute \src "ls180.v:2741.190-2741.259" + cell $and $and$ls180.v:2741$453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock - connect \B $eq$ls180.v:2750$452_Y - connect \Y $and$ls180.v:2750$453_Y + connect \B $eq$ls180.v:2741$452_Y + connect \Y $and$ls180.v:2741$453_Y end - attribute \src "ls180.v:2750.265-2750.334" - cell $and $and$ls180.v:2750$456 + attribute \src "ls180.v:2741.265-2741.334" + cell $and $and$ls180.v:2741$456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock - connect \B $eq$ls180.v:2750$455_Y - connect \Y $and$ls180.v:2750$456_Y + connect \B $eq$ls180.v:2741$455_Y + connect \Y $and$ls180.v:2741$456_Y end - attribute \src "ls180.v:2750.46-2750.337" - cell $and $and$ls180.v:2750$459 + attribute \src "ls180.v:2741.46-2741.337" + cell $and $and$ls180.v:2741$459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2750$448_Y - connect \B $not$ls180.v:2750$458_Y - connect \Y $and$ls180.v:2750$459_Y + connect \A $eq$ls180.v:2741$448_Y + connect \B $not$ls180.v:2741$458_Y + connect \Y $and$ls180.v:2741$459_Y end - attribute \src "ls180.v:2750.45-2750.355" - cell $and $and$ls180.v:2750$460 + attribute \src "ls180.v:2741.45-2741.355" + cell $and $and$ls180.v:2741$460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2750$459_Y + connect \A $and$ls180.v:2741$459_Y connect \B \port_cmd_valid - connect \Y $and$ls180.v:2750$460_Y + connect \Y $and$ls180.v:2741$460_Y end - attribute \src "ls180.v:2751.39-2751.101" - cell $and $and$ls180.v:2751$463 + attribute \src "ls180.v:2742.39-2742.101" + cell $and $and$ls180.v:2742$463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2751$461_Y - connect \B $not$ls180.v:2751$462_Y - connect \Y $and$ls180.v:2751$463_Y + connect \A $not$ls180.v:2742$461_Y + connect \B $not$ls180.v:2742$462_Y + connect \Y $and$ls180.v:2742$463_Y end - attribute \src "ls180.v:2755.115-2755.184" - cell $and $and$ls180.v:2755$466 + attribute \src "ls180.v:2746.115-2746.184" + cell $and $and$ls180.v:2746$466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock - connect \B $eq$ls180.v:2755$465_Y - connect \Y $and$ls180.v:2755$466_Y + connect \B $eq$ls180.v:2746$465_Y + connect \Y $and$ls180.v:2746$466_Y end - attribute \src "ls180.v:2755.190-2755.259" - cell $and $and$ls180.v:2755$469 + attribute \src "ls180.v:2746.190-2746.259" + cell $and $and$ls180.v:2746$469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock - connect \B $eq$ls180.v:2755$468_Y - connect \Y $and$ls180.v:2755$469_Y + connect \B $eq$ls180.v:2746$468_Y + connect \Y $and$ls180.v:2746$469_Y end - attribute \src "ls180.v:2755.265-2755.334" - cell $and $and$ls180.v:2755$472 + attribute \src "ls180.v:2746.265-2746.334" + cell $and $and$ls180.v:2746$472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock - connect \B $eq$ls180.v:2755$471_Y - connect \Y $and$ls180.v:2755$472_Y + connect \B $eq$ls180.v:2746$471_Y + connect \Y $and$ls180.v:2746$472_Y end - attribute \src "ls180.v:2755.46-2755.337" - cell $and $and$ls180.v:2755$475 + attribute \src "ls180.v:2746.46-2746.337" + cell $and $and$ls180.v:2746$475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2755$464_Y - connect \B $not$ls180.v:2755$474_Y - connect \Y $and$ls180.v:2755$475_Y + connect \A $eq$ls180.v:2746$464_Y + connect \B $not$ls180.v:2746$474_Y + connect \Y $and$ls180.v:2746$475_Y end - attribute \src "ls180.v:2755.45-2755.355" - cell $and $and$ls180.v:2755$476 + attribute \src "ls180.v:2746.45-2746.355" + cell $and $and$ls180.v:2746$476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2755$475_Y + connect \A $and$ls180.v:2746$475_Y connect \B \port_cmd_valid - connect \Y $and$ls180.v:2755$476_Y + connect \Y $and$ls180.v:2746$476_Y end - attribute \src "ls180.v:2756.39-2756.101" - cell $and $and$ls180.v:2756$479 + attribute \src "ls180.v:2747.39-2747.101" + cell $and $and$ls180.v:2747$479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2756$477_Y - connect \B $not$ls180.v:2756$478_Y - connect \Y $and$ls180.v:2756$479_Y + connect \A $not$ls180.v:2747$477_Y + connect \B $not$ls180.v:2747$478_Y + connect \Y $and$ls180.v:2747$479_Y end - attribute \src "ls180.v:2760.151-2760.220" - cell $and $and$ls180.v:2760$483 + attribute \src "ls180.v:2751.151-2751.220" + cell $and $and$ls180.v:2751$483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock - connect \B $eq$ls180.v:2760$482_Y - connect \Y $and$ls180.v:2760$483_Y + connect \B $eq$ls180.v:2751$482_Y + connect \Y $and$ls180.v:2751$483_Y end - attribute \src "ls180.v:2760.226-2760.295" - cell $and $and$ls180.v:2760$486 + attribute \src "ls180.v:2751.226-2751.295" + cell $and $and$ls180.v:2751$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock - connect \B $eq$ls180.v:2760$485_Y - connect \Y $and$ls180.v:2760$486_Y + connect \B $eq$ls180.v:2751$485_Y + connect \Y $and$ls180.v:2751$486_Y end - attribute \src "ls180.v:2760.301-2760.370" - cell $and $and$ls180.v:2760$489 + attribute \src "ls180.v:2751.301-2751.370" + cell $and $and$ls180.v:2751$489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock - connect \B $eq$ls180.v:2760$488_Y - connect \Y $and$ls180.v:2760$489_Y + connect \B $eq$ls180.v:2751$488_Y + connect \Y $and$ls180.v:2751$489_Y end - attribute \src "ls180.v:2760.82-2760.373" - cell $and $and$ls180.v:2760$492 + attribute \src "ls180.v:2751.82-2751.373" + cell $and $and$ls180.v:2751$492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2760$481_Y - connect \B $not$ls180.v:2760$491_Y - connect \Y $and$ls180.v:2760$492_Y + connect \A $eq$ls180.v:2751$481_Y + connect \B $not$ls180.v:2751$491_Y + connect \Y $and$ls180.v:2751$492_Y end - attribute \src "ls180.v:2760.38-2760.374" - cell $and $and$ls180.v:2760$493 + attribute \src "ls180.v:2751.38-2751.374" + cell $and $and$ls180.v:2751$493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2760$480_Y - connect \B $and$ls180.v:2760$492_Y - connect \Y $and$ls180.v:2760$493_Y + connect \A $eq$ls180.v:2751$480_Y + connect \B $and$ls180.v:2751$492_Y + connect \Y $and$ls180.v:2751$493_Y end - attribute \src "ls180.v:2760.37-2760.405" - cell $and $and$ls180.v:2760$494 + attribute \src "ls180.v:2751.37-2751.405" + cell $and $and$ls180.v:2751$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2760$493_Y + connect \A $and$ls180.v:2751$493_Y connect \B \sdram_interface_bank0_ready - connect \Y $and$ls180.v:2760$494_Y + connect \Y $and$ls180.v:2751$494_Y end - attribute \src "ls180.v:2760.525-2760.594" - cell $and $and$ls180.v:2760$499 + attribute \src "ls180.v:2751.525-2751.594" + cell $and $and$ls180.v:2751$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock - connect \B $eq$ls180.v:2760$498_Y - connect \Y $and$ls180.v:2760$499_Y + connect \B $eq$ls180.v:2751$498_Y + connect \Y $and$ls180.v:2751$499_Y end - attribute \src "ls180.v:2760.600-2760.669" - cell $and $and$ls180.v:2760$502 + attribute \src "ls180.v:2751.600-2751.669" + cell $and $and$ls180.v:2751$502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock - connect \B $eq$ls180.v:2760$501_Y - connect \Y $and$ls180.v:2760$502_Y + connect \B $eq$ls180.v:2751$501_Y + connect \Y $and$ls180.v:2751$502_Y end - attribute \src "ls180.v:2760.675-2760.744" - cell $and $and$ls180.v:2760$505 + attribute \src "ls180.v:2751.675-2751.744" + cell $and $and$ls180.v:2751$505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock - connect \B $eq$ls180.v:2760$504_Y - connect \Y $and$ls180.v:2760$505_Y + connect \B $eq$ls180.v:2751$504_Y + connect \Y $and$ls180.v:2751$505_Y end - attribute \src "ls180.v:2760.456-2760.747" - cell $and $and$ls180.v:2760$508 + attribute \src "ls180.v:2751.456-2751.747" + cell $and $and$ls180.v:2751$508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2760$497_Y - connect \B $not$ls180.v:2760$507_Y - connect \Y $and$ls180.v:2760$508_Y + connect \A $eq$ls180.v:2751$497_Y + connect \B $not$ls180.v:2751$507_Y + connect \Y $and$ls180.v:2751$508_Y end - attribute \src "ls180.v:2760.412-2760.748" - cell $and $and$ls180.v:2760$509 + attribute \src "ls180.v:2751.412-2751.748" + cell $and $and$ls180.v:2751$509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2760$496_Y - connect \B $and$ls180.v:2760$508_Y - connect \Y $and$ls180.v:2760$509_Y + connect \A $eq$ls180.v:2751$496_Y + connect \B $and$ls180.v:2751$508_Y + connect \Y $and$ls180.v:2751$509_Y end - attribute \src "ls180.v:2760.411-2760.779" - cell $and $and$ls180.v:2760$510 + attribute \src "ls180.v:2751.411-2751.779" + cell $and $and$ls180.v:2751$510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2760$509_Y + connect \A $and$ls180.v:2751$509_Y connect \B \sdram_interface_bank1_ready - connect \Y $and$ls180.v:2760$510_Y + connect \Y $and$ls180.v:2751$510_Y end - attribute \src "ls180.v:2760.899-2760.968" - cell $and $and$ls180.v:2760$515 + attribute \src "ls180.v:2751.899-2751.968" + cell $and $and$ls180.v:2751$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock - connect \B $eq$ls180.v:2760$514_Y - connect \Y $and$ls180.v:2760$515_Y + connect \B $eq$ls180.v:2751$514_Y + connect \Y $and$ls180.v:2751$515_Y end - attribute \src "ls180.v:2760.974-2760.1043" - cell $and $and$ls180.v:2760$518 + attribute \src "ls180.v:2751.974-2751.1043" + cell $and $and$ls180.v:2751$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock - connect \B $eq$ls180.v:2760$517_Y - connect \Y $and$ls180.v:2760$518_Y + connect \B $eq$ls180.v:2751$517_Y + connect \Y $and$ls180.v:2751$518_Y end - attribute \src "ls180.v:2760.1049-2760.1118" - cell $and $and$ls180.v:2760$521 + attribute \src "ls180.v:2751.1049-2751.1118" + cell $and $and$ls180.v:2751$521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock - connect \B $eq$ls180.v:2760$520_Y - connect \Y $and$ls180.v:2760$521_Y + connect \B $eq$ls180.v:2751$520_Y + connect \Y $and$ls180.v:2751$521_Y end - attribute \src "ls180.v:2760.830-2760.1121" - cell $and $and$ls180.v:2760$524 + attribute \src "ls180.v:2751.830-2751.1121" + cell $and $and$ls180.v:2751$524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2760$513_Y - connect \B $not$ls180.v:2760$523_Y - connect \Y $and$ls180.v:2760$524_Y + connect \A $eq$ls180.v:2751$513_Y + connect \B $not$ls180.v:2751$523_Y + connect \Y $and$ls180.v:2751$524_Y end - attribute \src "ls180.v:2760.786-2760.1122" - cell $and $and$ls180.v:2760$525 + attribute \src "ls180.v:2751.786-2751.1122" + cell $and $and$ls180.v:2751$525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2760$512_Y - connect \B $and$ls180.v:2760$524_Y - connect \Y $and$ls180.v:2760$525_Y + connect \A $eq$ls180.v:2751$512_Y + connect \B $and$ls180.v:2751$524_Y + connect \Y $and$ls180.v:2751$525_Y end - attribute \src "ls180.v:2760.785-2760.1153" - cell $and $and$ls180.v:2760$526 + attribute \src "ls180.v:2751.785-2751.1153" + cell $and $and$ls180.v:2751$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2760$525_Y + connect \A $and$ls180.v:2751$525_Y connect \B \sdram_interface_bank2_ready - connect \Y $and$ls180.v:2760$526_Y + connect \Y $and$ls180.v:2751$526_Y end - attribute \src "ls180.v:2760.1273-2760.1342" - cell $and $and$ls180.v:2760$531 + attribute \src "ls180.v:2751.1273-2751.1342" + cell $and $and$ls180.v:2751$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock - connect \B $eq$ls180.v:2760$530_Y - connect \Y $and$ls180.v:2760$531_Y + connect \B $eq$ls180.v:2751$530_Y + connect \Y $and$ls180.v:2751$531_Y end - attribute \src "ls180.v:2760.1348-2760.1417" - cell $and $and$ls180.v:2760$534 + attribute \src "ls180.v:2751.1348-2751.1417" + cell $and $and$ls180.v:2751$534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock - connect \B $eq$ls180.v:2760$533_Y - connect \Y $and$ls180.v:2760$534_Y + connect \B $eq$ls180.v:2751$533_Y + connect \Y $and$ls180.v:2751$534_Y end - attribute \src "ls180.v:2760.1423-2760.1492" - cell $and $and$ls180.v:2760$537 + attribute \src "ls180.v:2751.1423-2751.1492" + cell $and $and$ls180.v:2751$537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock - connect \B $eq$ls180.v:2760$536_Y - connect \Y $and$ls180.v:2760$537_Y + connect \B $eq$ls180.v:2751$536_Y + connect \Y $and$ls180.v:2751$537_Y end - attribute \src "ls180.v:2760.1204-2760.1495" - cell $and $and$ls180.v:2760$540 + attribute \src "ls180.v:2751.1204-2751.1495" + cell $and $and$ls180.v:2751$540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2760$529_Y - connect \B $not$ls180.v:2760$539_Y - connect \Y $and$ls180.v:2760$540_Y + connect \A $eq$ls180.v:2751$529_Y + connect \B $not$ls180.v:2751$539_Y + connect \Y $and$ls180.v:2751$540_Y end - attribute \src "ls180.v:2760.1160-2760.1496" - cell $and $and$ls180.v:2760$541 + attribute \src "ls180.v:2751.1160-2751.1496" + cell $and $and$ls180.v:2751$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:2760$528_Y - connect \B $and$ls180.v:2760$540_Y - connect \Y $and$ls180.v:2760$541_Y + connect \A $eq$ls180.v:2751$528_Y + connect \B $and$ls180.v:2751$540_Y + connect \Y $and$ls180.v:2751$541_Y end - attribute \src "ls180.v:2760.1159-2760.1527" - cell $and $and$ls180.v:2760$542 + attribute \src "ls180.v:2751.1159-2751.1527" + cell $and $and$ls180.v:2751$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2760$541_Y + connect \A $and$ls180.v:2751$541_Y connect \B \sdram_interface_bank3_ready - connect \Y $and$ls180.v:2760$542_Y + connect \Y $and$ls180.v:2751$542_Y end - attribute \src "ls180.v:2818.9-2818.36" - cell $and $and$ls180.v:2818$548 + attribute \src "ls180.v:2809.9-2809.36" + cell $and $and$ls180.v:2809$548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249394,10 +249186,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \wb_sdram_stb connect \B \wb_sdram_cyc - connect \Y $and$ls180.v:2818$548_Y + connect \Y $and$ls180.v:2809$548_Y end - attribute \src "ls180.v:2836.9-2836.36" - cell $and $and$ls180.v:2836$555 + attribute \src "ls180.v:2827.9-2827.36" + cell $and $and$ls180.v:2827$555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249405,10 +249197,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \wb_sdram_stb connect \B \wb_sdram_cyc - connect \Y $and$ls180.v:2836$555_Y + connect \Y $and$ls180.v:2827$555_Y end - attribute \src "ls180.v:2849.27-2849.60" - cell $and $and$ls180.v:2849$559 + attribute \src "ls180.v:2840.27-2840.60" + cell $and $and$ls180.v:2840$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249416,54 +249208,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \litedram_wb_cyc connect \B \litedram_wb_stb - connect \Y $and$ls180.v:2849$559_Y + connect \Y $and$ls180.v:2840$559_Y end - attribute \src "ls180.v:2849.26-2849.79" - cell $and $and$ls180.v:2849$561 + attribute \src "ls180.v:2840.26-2840.79" + cell $and $and$ls180.v:2840$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2849$559_Y - connect \B $not$ls180.v:2849$560_Y - connect \Y $and$ls180.v:2849$561_Y + connect \A $and$ls180.v:2840$559_Y + connect \B $not$ls180.v:2840$560_Y + connect \Y $and$ls180.v:2840$561_Y end - attribute \src "ls180.v:2850.29-2850.82" - cell $and $and$ls180.v:2850$563 + attribute \src "ls180.v:2841.29-2841.82" + cell $and $and$ls180.v:2841$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2850$562_Y + connect \A $or$ls180.v:2841$562_Y connect \B \port_cmd_payload_we - connect \Y $and$ls180.v:2850$563_Y + connect \Y $and$ls180.v:2841$563_Y end - attribute \src "ls180.v:2850.28-2850.103" - cell $and $and$ls180.v:2850$565 + attribute \src "ls180.v:2841.28-2841.103" + cell $and $and$ls180.v:2841$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2850$563_Y - connect \B $not$ls180.v:2850$564_Y - connect \Y $and$ls180.v:2850$565_Y + connect \A $and$ls180.v:2841$563_Y + connect \B $not$ls180.v:2841$564_Y + connect \Y $and$ls180.v:2841$565_Y end - attribute \src "ls180.v:2851.28-2851.84" - cell $and $and$ls180.v:2851$568 + attribute \src "ls180.v:2842.28-2842.84" + cell $and $and$ls180.v:2842$568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2851$566_Y - connect \B $not$ls180.v:2851$567_Y - connect \Y $and$ls180.v:2851$568_Y + connect \A $or$ls180.v:2842$566_Y + connect \B $not$ls180.v:2842$567_Y + connect \Y $and$ls180.v:2842$568_Y end - attribute \src "ls180.v:2852.39-2852.65" - cell $and $and$ls180.v:2852$569 + attribute \src "ls180.v:2843.39-2843.65" + cell $and $and$ls180.v:2843$569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249471,32 +249263,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \litedram_wb_we connect \B \ack_wdata - connect \Y $and$ls180.v:2852$569_Y + connect \Y $and$ls180.v:2843$569_Y end - attribute \src "ls180.v:2852.70-2852.99" - cell $and $and$ls180.v:2852$571 + attribute \src "ls180.v:2843.70-2843.99" + cell $and $and$ls180.v:2843$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2852$570_Y + connect \A $not$ls180.v:2843$570_Y connect \B \ack_rdata - connect \Y $and$ls180.v:2852$571_Y + connect \Y $and$ls180.v:2843$571_Y end - attribute \src "ls180.v:2852.27-2852.101" - cell $and $and$ls180.v:2852$573 + attribute \src "ls180.v:2843.27-2843.101" + cell $and $and$ls180.v:2843$573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ack_cmd - connect \B $or$ls180.v:2852$572_Y - connect \Y $and$ls180.v:2852$573_Y + connect \B $or$ls180.v:2843$572_Y + connect \Y $and$ls180.v:2843$573_Y end - attribute \src "ls180.v:2853.20-2853.51" - cell $and $and$ls180.v:2853$574 + attribute \src "ls180.v:2844.20-2844.51" + cell $and $and$ls180.v:2844$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249504,10 +249296,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_valid connect \B \port_cmd_ready - connect \Y $and$ls180.v:2853$574_Y + connect \Y $and$ls180.v:2844$574_Y end - attribute \src "ls180.v:2854.22-2854.57" - cell $and $and$ls180.v:2854$576 + attribute \src "ls180.v:2845.22-2845.57" + cell $and $and$ls180.v:2845$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249515,10 +249307,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_wdata_valid connect \B \port_wdata_ready - connect \Y $and$ls180.v:2854$576_Y + connect \Y $and$ls180.v:2845$576_Y end - attribute \src "ls180.v:2855.21-2855.56" - cell $and $and$ls180.v:2855$578 + attribute \src "ls180.v:2846.21-2846.56" + cell $and $and$ls180.v:2846$578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249526,10 +249318,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_rdata_valid connect \B \port_rdata_ready - connect \Y $and$ls180.v:2855$578_Y + connect \Y $and$ls180.v:2846$578_Y end - attribute \src "ls180.v:2884.44-2884.58" - cell $and $and$ls180.v:2884$584 + attribute \src "ls180.v:2875.44-2875.58" + cell $and $and$ls180.v:2875$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249537,10 +249329,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A 1'0 connect \B \rxtx_we - connect \Y $and$ls180.v:2884$584_Y + connect \Y $and$ls180.v:2875$584_Y end - attribute \src "ls180.v:2888.7-2888.58" - cell $and $and$ls180.v:2888$588 + attribute \src "ls180.v:2879.7-2879.58" + cell $and $and$ls180.v:2879$588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249548,10 +249340,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \eventmanager_pending_re connect \B \eventmanager_pending_r [0] - connect \Y $and$ls180.v:2888$588_Y + connect \Y $and$ls180.v:2879$588_Y end - attribute \src "ls180.v:2899.7-2899.58" - cell $and $and$ls180.v:2899$591 + attribute \src "ls180.v:2890.7-2890.58" + cell $and $and$ls180.v:2890$591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249559,10 +249351,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \eventmanager_pending_re connect \B \eventmanager_pending_r [1] - connect \Y $and$ls180.v:2899$591_Y + connect \Y $and$ls180.v:2890$591_Y end - attribute \src "ls180.v:2908.16-2908.67" - cell $and $and$ls180.v:2908$593 + attribute \src "ls180.v:2899.16-2899.67" + cell $and $and$ls180.v:2899$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249570,10 +249362,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \eventmanager_pending_w [0] connect \B \eventmanager_storage [0] - connect \Y $and$ls180.v:2908$593_Y + connect \Y $and$ls180.v:2899$593_Y end - attribute \src "ls180.v:2908.72-2908.123" - cell $and $and$ls180.v:2908$594 + attribute \src "ls180.v:2899.72-2899.123" + cell $and $and$ls180.v:2899$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249581,32 +249373,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \eventmanager_pending_w [1] connect \B \eventmanager_storage [1] - connect \Y $and$ls180.v:2908$594_Y + connect \Y $and$ls180.v:2899$594_Y end - attribute \src "ls180.v:2923.31-2923.93" - cell $and $and$ls180.v:2923$598 + attribute \src "ls180.v:2914.31-2914.93" + cell $and $and$ls180.v:2914$598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_readable - connect \B $or$ls180.v:2923$597_Y - connect \Y $and$ls180.v:2923$598_Y + connect \B $or$ls180.v:2914$597_Y + connect \Y $and$ls180.v:2914$598_Y end - attribute \src "ls180.v:2934.29-2934.96" - cell $and $and$ls180.v:2934$603 + attribute \src "ls180.v:2925.29-2925.96" + cell $and $and$ls180.v:2925$603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_we - connect \B $or$ls180.v:2934$602_Y - connect \Y $and$ls180.v:2934$603_Y + connect \B $or$ls180.v:2925$602_Y + connect \Y $and$ls180.v:2925$603_Y end - attribute \src "ls180.v:2935.27-2935.74" - cell $and $and$ls180.v:2935$604 + attribute \src "ls180.v:2926.27-2926.74" + cell $and $and$ls180.v:2926$604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249614,32 +249406,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_readable connect \B \tx_fifo_syncfifo_re - connect \Y $and$ls180.v:2935$604_Y + connect \Y $and$ls180.v:2926$604_Y end - attribute \src "ls180.v:2953.31-2953.93" - cell $and $and$ls180.v:2953$609 + attribute \src "ls180.v:2944.31-2944.93" + cell $and $and$ls180.v:2944$609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_readable - connect \B $or$ls180.v:2953$608_Y - connect \Y $and$ls180.v:2953$609_Y + connect \B $or$ls180.v:2944$608_Y + connect \Y $and$ls180.v:2944$609_Y end - attribute \src "ls180.v:2964.29-2964.96" - cell $and $and$ls180.v:2964$614 + attribute \src "ls180.v:2955.29-2955.96" + cell $and $and$ls180.v:2955$614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_we - connect \B $or$ls180.v:2964$613_Y - connect \Y $and$ls180.v:2964$614_Y + connect \B $or$ls180.v:2955$613_Y + connect \Y $and$ls180.v:2955$614_Y end - attribute \src "ls180.v:2965.27-2965.74" - cell $and $and$ls180.v:2965$615 + attribute \src "ls180.v:2956.27-2956.74" + cell $and $and$ls180.v:2956$615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249647,10 +249439,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_readable connect \B \rx_fifo_syncfifo_re - connect \Y $and$ls180.v:2965$615_Y + connect \Y $and$ls180.v:2956$615_Y end - attribute \src "ls180.v:3062.9-3062.84" - cell $and $and$ls180.v:3062$623 + attribute \src "ls180.v:3053.9-3053.84" + cell $and $and$ls180.v:3053$623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249658,87 +249450,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_libresocsim_wishbone_cyc connect \B \libresocsim_libresocsim_wishbone_stb - connect \Y $and$ls180.v:3062$623_Y + connect \Y $and$ls180.v:3053$623_Y end - attribute \src "ls180.v:3065.60-3065.144" - cell $and $and$ls180.v:3065$625 + attribute \src "ls180.v:3056.60-3056.144" + cell $and $and$ls180.v:3056$625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresocsim_wishbone_we - connect \B $ne$ls180.v:3065$624_Y - connect \Y $and$ls180.v:3065$625_Y + connect \B $ne$ls180.v:3056$624_Y + connect \Y $and$ls180.v:3056$625_Y end - attribute \src "ls180.v:3083.58-3083.110" - cell $and $and$ls180.v:3083$627 + attribute \src "ls180.v:3074.58-3074.110" + cell $and $and$ls180.v:3074$627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_ack - connect \B $eq$ls180.v:3083$626_Y - connect \Y $and$ls180.v:3083$627_Y + connect \B $eq$ls180.v:3074$626_Y + connect \Y $and$ls180.v:3074$627_Y end - attribute \src "ls180.v:3084.58-3084.110" - cell $and $and$ls180.v:3084$629 + attribute \src "ls180.v:3075.58-3075.110" + cell $and $and$ls180.v:3075$629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_ack - connect \B $eq$ls180.v:3084$628_Y - connect \Y $and$ls180.v:3084$629_Y + connect \B $eq$ls180.v:3075$628_Y + connect \Y $and$ls180.v:3075$629_Y end - attribute \src "ls180.v:3085.58-3085.110" - cell $and $and$ls180.v:3085$631 + attribute \src "ls180.v:3076.58-3076.110" + cell $and $and$ls180.v:3076$631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_ack - connect \B $eq$ls180.v:3085$630_Y - connect \Y $and$ls180.v:3085$631_Y + connect \B $eq$ls180.v:3076$630_Y + connect \Y $and$ls180.v:3076$631_Y end - attribute \src "ls180.v:3086.58-3086.110" - cell $and $and$ls180.v:3086$633 + attribute \src "ls180.v:3077.58-3077.110" + cell $and $and$ls180.v:3077$633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_err - connect \B $eq$ls180.v:3086$632_Y - connect \Y $and$ls180.v:3086$633_Y + connect \B $eq$ls180.v:3077$632_Y + connect \Y $and$ls180.v:3077$633_Y end - attribute \src "ls180.v:3087.58-3087.110" - cell $and $and$ls180.v:3087$635 + attribute \src "ls180.v:3078.58-3078.110" + cell $and $and$ls180.v:3078$635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_err - connect \B $eq$ls180.v:3087$634_Y - connect \Y $and$ls180.v:3087$635_Y + connect \B $eq$ls180.v:3078$634_Y + connect \Y $and$ls180.v:3078$635_Y end - attribute \src "ls180.v:3088.58-3088.110" - cell $and $and$ls180.v:3088$637 + attribute \src "ls180.v:3079.58-3079.110" + cell $and $and$ls180.v:3079$637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_err - connect \B $eq$ls180.v:3088$636_Y - connect \Y $and$ls180.v:3088$637_Y + connect \B $eq$ls180.v:3079$636_Y + connect \Y $and$ls180.v:3079$637_Y end - attribute \src "ls180.v:3141.35-3141.84" - cell $and $and$ls180.v:3141$645 + attribute \src "ls180.v:3132.35-3132.84" + cell $and $and$ls180.v:3132$645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249746,10 +249538,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [0] - connect \Y $and$ls180.v:3141$645_Y + connect \Y $and$ls180.v:3132$645_Y end - attribute \src "ls180.v:3142.31-3142.80" - cell $and $and$ls180.v:3142$646 + attribute \src "ls180.v:3133.31-3133.80" + cell $and $and$ls180.v:3133$646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249757,10 +249549,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [1] - connect \Y $and$ls180.v:3142$646_Y + connect \Y $and$ls180.v:3133$646_Y end - attribute \src "ls180.v:3143.45-3143.94" - cell $and $and$ls180.v:3143$647 + attribute \src "ls180.v:3134.45-3134.94" + cell $and $and$ls180.v:3134$647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249768,10 +249560,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [2] - connect \Y $and$ls180.v:3143$647_Y + connect \Y $and$ls180.v:3134$647_Y end - attribute \src "ls180.v:3144.45-3144.94" - cell $and $and$ls180.v:3144$648 + attribute \src "ls180.v:3135.45-3135.94" + cell $and $and$ls180.v:3135$648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249779,10 +249571,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [3] - connect \Y $and$ls180.v:3144$648_Y + connect \Y $and$ls180.v:3135$648_Y end - attribute \src "ls180.v:3145.24-3145.73" - cell $and $and$ls180.v:3145$649 + attribute \src "ls180.v:3136.24-3136.73" + cell $and $and$ls180.v:3136$649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249790,10 +249582,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [4] - connect \Y $and$ls180.v:3145$649_Y + connect \Y $and$ls180.v:3136$649_Y end - attribute \src "ls180.v:3146.48-3146.97" - cell $and $and$ls180.v:3146$650 + attribute \src "ls180.v:3137.48-3137.97" + cell $and $and$ls180.v:3137$650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249801,10 +249593,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [5] - connect \Y $and$ls180.v:3146$650_Y + connect \Y $and$ls180.v:3137$650_Y end - attribute \src "ls180.v:3148.29-3148.76" - cell $and $and$ls180.v:3148$656 + attribute \src "ls180.v:3139.29-3139.76" + cell $and $and$ls180.v:3139$656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249812,21 +249604,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_stb connect \B \libresocsim_shared_cyc - connect \Y $and$ls180.v:3148$656_Y + connect \Y $and$ls180.v:3139$656_Y end - attribute \src "ls180.v:3148.28-3148.105" - cell $and $and$ls180.v:3148$658 + attribute \src "ls180.v:3139.28-3139.105" + cell $and $and$ls180.v:3139$658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3148$656_Y - connect \B $not$ls180.v:3148$657_Y - connect \Y $and$ls180.v:3148$658_Y + connect \A $and$ls180.v:3139$656_Y + connect \B $not$ls180.v:3139$657_Y + connect \Y $and$ls180.v:3139$658_Y end - attribute \src "ls180.v:3154.36-3154.96" - cell $and $and$ls180.v:3154$665 + attribute \src "ls180.v:3145.36-3145.96" + cell $and $and$ls180.v:3145$665 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249834,10 +249626,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] } connect \B \libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:3154$665_Y + connect \Y $and$ls180.v:3145$665_Y end - attribute \src "ls180.v:3154.101-3154.157" - cell $and $and$ls180.v:3154$666 + attribute \src "ls180.v:3145.101-3145.157" + cell $and $and$ls180.v:3145$666 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249845,10 +249637,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] } connect \B \ram_bus_ram_bus_dat_r - connect \Y $and$ls180.v:3154$666_Y + connect \Y $and$ls180.v:3145$666_Y end - attribute \src "ls180.v:3154.163-3154.233" - cell $and $and$ls180.v:3154$668 + attribute \src "ls180.v:3145.163-3145.233" + cell $and $and$ls180.v:3145$668 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249856,10 +249648,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] } connect \B \libresocsim_libresoc_xics_icp_dat_r - connect \Y $and$ls180.v:3154$668_Y + connect \Y $and$ls180.v:3145$668_Y end - attribute \src "ls180.v:3154.239-3154.309" - cell $and $and$ls180.v:3154$670 + attribute \src "ls180.v:3145.239-3145.309" + cell $and $and$ls180.v:3145$670 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249867,10 +249659,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] } connect \B \libresocsim_libresoc_xics_ics_dat_r - connect \Y $and$ls180.v:3154$670_Y + connect \Y $and$ls180.v:3145$670_Y end - attribute \src "ls180.v:3154.315-3154.364" - cell $and $and$ls180.v:3154$672 + attribute \src "ls180.v:3145.315-3145.364" + cell $and $and$ls180.v:3145$672 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249878,10 +249670,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] } connect \B \wb_sdram_dat_r - connect \Y $and$ls180.v:3154$672_Y + connect \Y $and$ls180.v:3145$672_Y end - attribute \src "ls180.v:3154.370-3154.443" - cell $and $and$ls180.v:3154$674 + attribute \src "ls180.v:3145.370-3145.443" + cell $and $and$ls180.v:3145$674 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249889,10 +249681,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] } connect \B \libresocsim_libresocsim_wishbone_dat_r - connect \Y $and$ls180.v:3154$674_Y + connect \Y $and$ls180.v:3145$674_Y end - attribute \src "ls180.v:3164.43-3164.104" - cell $and $and$ls180.v:3164$678 + attribute \src "ls180.v:3155.43-3155.104" + cell $and $and$ls180.v:3155$678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249900,43 +249692,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we - connect \Y $and$ls180.v:3164$678_Y + connect \Y $and$ls180.v:3155$678_Y end - attribute \src "ls180.v:3164.42-3164.158" - cell $and $and$ls180.v:3164$680 + attribute \src "ls180.v:3155.42-3155.158" + cell $and $and$ls180.v:3155$680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3164$678_Y - connect \B $eq$ls180.v:3164$679_Y - connect \Y $and$ls180.v:3164$680_Y + connect \A $and$ls180.v:3155$678_Y + connect \B $eq$ls180.v:3155$679_Y + connect \Y $and$ls180.v:3155$680_Y end - attribute \src "ls180.v:3165.43-3165.107" - cell $and $and$ls180.v:3165$682 + attribute \src "ls180.v:3156.43-3156.107" + cell $and $and$ls180.v:3156$682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel - connect \B $not$ls180.v:3165$681_Y - connect \Y $and$ls180.v:3165$682_Y + connect \B $not$ls180.v:3156$681_Y + connect \Y $and$ls180.v:3156$682_Y end - attribute \src "ls180.v:3165.42-3165.161" - cell $and $and$ls180.v:3165$684 + attribute \src "ls180.v:3156.42-3156.161" + cell $and $and$ls180.v:3156$684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3165$682_Y - connect \B $eq$ls180.v:3165$683_Y - connect \Y $and$ls180.v:3165$684_Y + connect \A $and$ls180.v:3156$682_Y + connect \B $eq$ls180.v:3156$683_Y + connect \Y $and$ls180.v:3156$684_Y end - attribute \src "ls180.v:3167.45-3167.106" - cell $and $and$ls180.v:3167$685 + attribute \src "ls180.v:3158.45-3158.106" + cell $and $and$ls180.v:3158$685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249944,43 +249736,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we - connect \Y $and$ls180.v:3167$685_Y + connect \Y $and$ls180.v:3158$685_Y end - attribute \src "ls180.v:3167.44-3167.160" - cell $and $and$ls180.v:3167$687 + attribute \src "ls180.v:3158.44-3158.160" + cell $and $and$ls180.v:3158$687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3167$685_Y - connect \B $eq$ls180.v:3167$686_Y - connect \Y $and$ls180.v:3167$687_Y + connect \A $and$ls180.v:3158$685_Y + connect \B $eq$ls180.v:3158$686_Y + connect \Y $and$ls180.v:3158$687_Y end - attribute \src "ls180.v:3168.45-3168.109" - cell $and $and$ls180.v:3168$689 + attribute \src "ls180.v:3159.45-3159.109" + cell $and $and$ls180.v:3159$689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel - connect \B $not$ls180.v:3168$688_Y - connect \Y $and$ls180.v:3168$689_Y + connect \B $not$ls180.v:3159$688_Y + connect \Y $and$ls180.v:3159$689_Y end - attribute \src "ls180.v:3168.44-3168.163" - cell $and $and$ls180.v:3168$691 + attribute \src "ls180.v:3159.44-3159.163" + cell $and $and$ls180.v:3159$691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3168$689_Y - connect \B $eq$ls180.v:3168$690_Y - connect \Y $and$ls180.v:3168$691_Y + connect \A $and$ls180.v:3159$689_Y + connect \B $eq$ls180.v:3159$690_Y + connect \Y $and$ls180.v:3159$691_Y end - attribute \src "ls180.v:3170.45-3170.106" - cell $and $and$ls180.v:3170$692 + attribute \src "ls180.v:3161.45-3161.106" + cell $and $and$ls180.v:3161$692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249988,43 +249780,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we - connect \Y $and$ls180.v:3170$692_Y + connect \Y $and$ls180.v:3161$692_Y end - attribute \src "ls180.v:3170.44-3170.160" - cell $and $and$ls180.v:3170$694 + attribute \src "ls180.v:3161.44-3161.160" + cell $and $and$ls180.v:3161$694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3170$692_Y - connect \B $eq$ls180.v:3170$693_Y - connect \Y $and$ls180.v:3170$694_Y + connect \A $and$ls180.v:3161$692_Y + connect \B $eq$ls180.v:3161$693_Y + connect \Y $and$ls180.v:3161$694_Y end - attribute \src "ls180.v:3171.45-3171.109" - cell $and $and$ls180.v:3171$696 + attribute \src "ls180.v:3162.45-3162.109" + cell $and $and$ls180.v:3162$696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel - connect \B $not$ls180.v:3171$695_Y - connect \Y $and$ls180.v:3171$696_Y + connect \B $not$ls180.v:3162$695_Y + connect \Y $and$ls180.v:3162$696_Y end - attribute \src "ls180.v:3171.44-3171.163" - cell $and $and$ls180.v:3171$698 + attribute \src "ls180.v:3162.44-3162.163" + cell $and $and$ls180.v:3162$698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3171$696_Y - connect \B $eq$ls180.v:3171$697_Y - connect \Y $and$ls180.v:3171$698_Y + connect \A $and$ls180.v:3162$696_Y + connect \B $eq$ls180.v:3162$697_Y + connect \Y $and$ls180.v:3162$698_Y end - attribute \src "ls180.v:3173.45-3173.106" - cell $and $and$ls180.v:3173$699 + attribute \src "ls180.v:3164.45-3164.106" + cell $and $and$ls180.v:3164$699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250032,43 +249824,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we - connect \Y $and$ls180.v:3173$699_Y + connect \Y $and$ls180.v:3164$699_Y end - attribute \src "ls180.v:3173.44-3173.160" - cell $and $and$ls180.v:3173$701 + attribute \src "ls180.v:3164.44-3164.160" + cell $and $and$ls180.v:3164$701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3173$699_Y - connect \B $eq$ls180.v:3173$700_Y - connect \Y $and$ls180.v:3173$701_Y + connect \A $and$ls180.v:3164$699_Y + connect \B $eq$ls180.v:3164$700_Y + connect \Y $and$ls180.v:3164$701_Y end - attribute \src "ls180.v:3174.45-3174.109" - cell $and $and$ls180.v:3174$703 + attribute \src "ls180.v:3165.45-3165.109" + cell $and $and$ls180.v:3165$703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel - connect \B $not$ls180.v:3174$702_Y - connect \Y $and$ls180.v:3174$703_Y + connect \B $not$ls180.v:3165$702_Y + connect \Y $and$ls180.v:3165$703_Y end - attribute \src "ls180.v:3174.44-3174.163" - cell $and $and$ls180.v:3174$705 + attribute \src "ls180.v:3165.44-3165.163" + cell $and $and$ls180.v:3165$705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3174$703_Y - connect \B $eq$ls180.v:3174$704_Y - connect \Y $and$ls180.v:3174$705_Y + connect \A $and$ls180.v:3165$703_Y + connect \B $eq$ls180.v:3165$704_Y + connect \Y $and$ls180.v:3165$705_Y end - attribute \src "ls180.v:3176.45-3176.106" - cell $and $and$ls180.v:3176$706 + attribute \src "ls180.v:3167.45-3167.106" + cell $and $and$ls180.v:3167$706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250076,43 +249868,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we - connect \Y $and$ls180.v:3176$706_Y + connect \Y $and$ls180.v:3167$706_Y end - attribute \src "ls180.v:3176.44-3176.160" - cell $and $and$ls180.v:3176$708 + attribute \src "ls180.v:3167.44-3167.160" + cell $and $and$ls180.v:3167$708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3176$706_Y - connect \B $eq$ls180.v:3176$707_Y - connect \Y $and$ls180.v:3176$708_Y + connect \A $and$ls180.v:3167$706_Y + connect \B $eq$ls180.v:3167$707_Y + connect \Y $and$ls180.v:3167$708_Y end - attribute \src "ls180.v:3177.45-3177.109" - cell $and $and$ls180.v:3177$710 + attribute \src "ls180.v:3168.45-3168.109" + cell $and $and$ls180.v:3168$710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel - connect \B $not$ls180.v:3177$709_Y - connect \Y $and$ls180.v:3177$710_Y + connect \B $not$ls180.v:3168$709_Y + connect \Y $and$ls180.v:3168$710_Y end - attribute \src "ls180.v:3177.44-3177.163" - cell $and $and$ls180.v:3177$712 + attribute \src "ls180.v:3168.44-3168.163" + cell $and $and$ls180.v:3168$712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3177$710_Y - connect \B $eq$ls180.v:3177$711_Y - connect \Y $and$ls180.v:3177$712_Y + connect \A $and$ls180.v:3168$710_Y + connect \B $eq$ls180.v:3168$711_Y + connect \Y $and$ls180.v:3168$712_Y end - attribute \src "ls180.v:3179.48-3179.109" - cell $and $and$ls180.v:3179$713 + attribute \src "ls180.v:3170.48-3170.109" + cell $and $and$ls180.v:3170$713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250120,43 +249912,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we - connect \Y $and$ls180.v:3179$713_Y + connect \Y $and$ls180.v:3170$713_Y end - attribute \src "ls180.v:3179.47-3179.163" - cell $and $and$ls180.v:3179$715 + attribute \src "ls180.v:3170.47-3170.163" + cell $and $and$ls180.v:3170$715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3179$713_Y - connect \B $eq$ls180.v:3179$714_Y - connect \Y $and$ls180.v:3179$715_Y + connect \A $and$ls180.v:3170$713_Y + connect \B $eq$ls180.v:3170$714_Y + connect \Y $and$ls180.v:3170$715_Y end - attribute \src "ls180.v:3180.48-3180.112" - cell $and $and$ls180.v:3180$717 + attribute \src "ls180.v:3171.48-3171.112" + cell $and $and$ls180.v:3171$717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel - connect \B $not$ls180.v:3180$716_Y - connect \Y $and$ls180.v:3180$717_Y + connect \B $not$ls180.v:3171$716_Y + connect \Y $and$ls180.v:3171$717_Y end - attribute \src "ls180.v:3180.47-3180.166" - cell $and $and$ls180.v:3180$719 + attribute \src "ls180.v:3171.47-3171.166" + cell $and $and$ls180.v:3171$719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3180$717_Y - connect \B $eq$ls180.v:3180$718_Y - connect \Y $and$ls180.v:3180$719_Y + connect \A $and$ls180.v:3171$717_Y + connect \B $eq$ls180.v:3171$718_Y + connect \Y $and$ls180.v:3171$719_Y end - attribute \src "ls180.v:3182.48-3182.109" - cell $and $and$ls180.v:3182$720 + attribute \src "ls180.v:3173.48-3173.109" + cell $and $and$ls180.v:3173$720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250164,43 +249956,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we - connect \Y $and$ls180.v:3182$720_Y + connect \Y $and$ls180.v:3173$720_Y end - attribute \src "ls180.v:3182.47-3182.163" - cell $and $and$ls180.v:3182$722 + attribute \src "ls180.v:3173.47-3173.163" + cell $and $and$ls180.v:3173$722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3182$720_Y - connect \B $eq$ls180.v:3182$721_Y - connect \Y $and$ls180.v:3182$722_Y + connect \A $and$ls180.v:3173$720_Y + connect \B $eq$ls180.v:3173$721_Y + connect \Y $and$ls180.v:3173$722_Y end - attribute \src "ls180.v:3183.48-3183.112" - cell $and $and$ls180.v:3183$724 + attribute \src "ls180.v:3174.48-3174.112" + cell $and $and$ls180.v:3174$724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel - connect \B $not$ls180.v:3183$723_Y - connect \Y $and$ls180.v:3183$724_Y + connect \B $not$ls180.v:3174$723_Y + connect \Y $and$ls180.v:3174$724_Y end - attribute \src "ls180.v:3183.47-3183.166" - cell $and $and$ls180.v:3183$726 + attribute \src "ls180.v:3174.47-3174.166" + cell $and $and$ls180.v:3174$726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3183$724_Y - connect \B $eq$ls180.v:3183$725_Y - connect \Y $and$ls180.v:3183$726_Y + connect \A $and$ls180.v:3174$724_Y + connect \B $eq$ls180.v:3174$725_Y + connect \Y $and$ls180.v:3174$726_Y end - attribute \src "ls180.v:3185.48-3185.109" - cell $and $and$ls180.v:3185$727 + attribute \src "ls180.v:3176.48-3176.109" + cell $and $and$ls180.v:3176$727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250208,43 +250000,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we - connect \Y $and$ls180.v:3185$727_Y + connect \Y $and$ls180.v:3176$727_Y end - attribute \src "ls180.v:3185.47-3185.163" - cell $and $and$ls180.v:3185$729 + attribute \src "ls180.v:3176.47-3176.163" + cell $and $and$ls180.v:3176$729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3185$727_Y - connect \B $eq$ls180.v:3185$728_Y - connect \Y $and$ls180.v:3185$729_Y + connect \A $and$ls180.v:3176$727_Y + connect \B $eq$ls180.v:3176$728_Y + connect \Y $and$ls180.v:3176$729_Y end - attribute \src "ls180.v:3186.48-3186.112" - cell $and $and$ls180.v:3186$731 + attribute \src "ls180.v:3177.48-3177.112" + cell $and $and$ls180.v:3177$731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel - connect \B $not$ls180.v:3186$730_Y - connect \Y $and$ls180.v:3186$731_Y + connect \B $not$ls180.v:3177$730_Y + connect \Y $and$ls180.v:3177$731_Y end - attribute \src "ls180.v:3186.47-3186.166" - cell $and $and$ls180.v:3186$733 + attribute \src "ls180.v:3177.47-3177.166" + cell $and $and$ls180.v:3177$733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3186$731_Y - connect \B $eq$ls180.v:3186$732_Y - connect \Y $and$ls180.v:3186$733_Y + connect \A $and$ls180.v:3177$731_Y + connect \B $eq$ls180.v:3177$732_Y + connect \Y $and$ls180.v:3177$733_Y end - attribute \src "ls180.v:3188.48-3188.109" - cell $and $and$ls180.v:3188$734 + attribute \src "ls180.v:3179.48-3179.109" + cell $and $and$ls180.v:3179$734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250252,43 +250044,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we - connect \Y $and$ls180.v:3188$734_Y + connect \Y $and$ls180.v:3179$734_Y end - attribute \src "ls180.v:3188.47-3188.163" - cell $and $and$ls180.v:3188$736 + attribute \src "ls180.v:3179.47-3179.163" + cell $and $and$ls180.v:3179$736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3188$734_Y - connect \B $eq$ls180.v:3188$735_Y - connect \Y $and$ls180.v:3188$736_Y + connect \A $and$ls180.v:3179$734_Y + connect \B $eq$ls180.v:3179$735_Y + connect \Y $and$ls180.v:3179$736_Y end - attribute \src "ls180.v:3189.48-3189.112" - cell $and $and$ls180.v:3189$738 + attribute \src "ls180.v:3180.48-3180.112" + cell $and $and$ls180.v:3180$738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel - connect \B $not$ls180.v:3189$737_Y - connect \Y $and$ls180.v:3189$738_Y + connect \B $not$ls180.v:3180$737_Y + connect \Y $and$ls180.v:3180$738_Y end - attribute \src "ls180.v:3189.47-3189.166" - cell $and $and$ls180.v:3189$740 + attribute \src "ls180.v:3180.47-3180.166" + cell $and $and$ls180.v:3180$740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3189$738_Y - connect \B $eq$ls180.v:3189$739_Y - connect \Y $and$ls180.v:3189$740_Y + connect \A $and$ls180.v:3180$738_Y + connect \B $eq$ls180.v:3180$739_Y + connect \Y $and$ls180.v:3180$740_Y end - attribute \src "ls180.v:3202.40-3202.101" - cell $and $and$ls180.v:3202$742 + attribute \src "ls180.v:3193.40-3193.101" + cell $and $and$ls180.v:3193$742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250296,43 +250088,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel connect \B \libresocsim_interface1_bank_bus_we - connect \Y $and$ls180.v:3202$742_Y + connect \Y $and$ls180.v:3193$742_Y end - attribute \src "ls180.v:3202.39-3202.155" - cell $and $and$ls180.v:3202$744 + attribute \src "ls180.v:3193.39-3193.155" + cell $and $and$ls180.v:3193$744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3202$742_Y - connect \B $eq$ls180.v:3202$743_Y - connect \Y $and$ls180.v:3202$744_Y + connect \A $and$ls180.v:3193$742_Y + connect \B $eq$ls180.v:3193$743_Y + connect \Y $and$ls180.v:3193$744_Y end - attribute \src "ls180.v:3203.40-3203.104" - cell $and $and$ls180.v:3203$746 + attribute \src "ls180.v:3194.40-3194.104" + cell $and $and$ls180.v:3194$746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel - connect \B $not$ls180.v:3203$745_Y - connect \Y $and$ls180.v:3203$746_Y + connect \B $not$ls180.v:3194$745_Y + connect \Y $and$ls180.v:3194$746_Y end - attribute \src "ls180.v:3203.39-3203.158" - cell $and $and$ls180.v:3203$748 + attribute \src "ls180.v:3194.39-3194.158" + cell $and $and$ls180.v:3194$748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3203$746_Y - connect \B $eq$ls180.v:3203$747_Y - connect \Y $and$ls180.v:3203$748_Y + connect \A $and$ls180.v:3194$746_Y + connect \B $eq$ls180.v:3194$747_Y + connect \Y $and$ls180.v:3194$748_Y end - attribute \src "ls180.v:3205.39-3205.100" - cell $and $and$ls180.v:3205$749 + attribute \src "ls180.v:3196.39-3196.100" + cell $and $and$ls180.v:3196$749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250340,43 +250132,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel connect \B \libresocsim_interface1_bank_bus_we - connect \Y $and$ls180.v:3205$749_Y + connect \Y $and$ls180.v:3196$749_Y end - attribute \src "ls180.v:3205.38-3205.154" - cell $and $and$ls180.v:3205$751 + attribute \src "ls180.v:3196.38-3196.154" + cell $and $and$ls180.v:3196$751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3205$749_Y - connect \B $eq$ls180.v:3205$750_Y - connect \Y $and$ls180.v:3205$751_Y + connect \A $and$ls180.v:3196$749_Y + connect \B $eq$ls180.v:3196$750_Y + connect \Y $and$ls180.v:3196$751_Y end - attribute \src "ls180.v:3206.39-3206.103" - cell $and $and$ls180.v:3206$753 + attribute \src "ls180.v:3197.39-3197.103" + cell $and $and$ls180.v:3197$753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel - connect \B $not$ls180.v:3206$752_Y - connect \Y $and$ls180.v:3206$753_Y + connect \B $not$ls180.v:3197$752_Y + connect \Y $and$ls180.v:3197$753_Y end - attribute \src "ls180.v:3206.38-3206.157" - cell $and $and$ls180.v:3206$755 + attribute \src "ls180.v:3197.38-3197.157" + cell $and $and$ls180.v:3197$755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3206$753_Y - connect \B $eq$ls180.v:3206$754_Y - connect \Y $and$ls180.v:3206$755_Y + connect \A $and$ls180.v:3197$753_Y + connect \B $eq$ls180.v:3197$754_Y + connect \Y $and$ls180.v:3197$755_Y end - attribute \src "ls180.v:3208.41-3208.102" - cell $and $and$ls180.v:3208$756 + attribute \src "ls180.v:3199.41-3199.102" + cell $and $and$ls180.v:3199$756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250384,43 +250176,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel connect \B \libresocsim_interface1_bank_bus_we - connect \Y $and$ls180.v:3208$756_Y + connect \Y $and$ls180.v:3199$756_Y end - attribute \src "ls180.v:3208.40-3208.156" - cell $and $and$ls180.v:3208$758 + attribute \src "ls180.v:3199.40-3199.156" + cell $and $and$ls180.v:3199$758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3208$756_Y - connect \B $eq$ls180.v:3208$757_Y - connect \Y $and$ls180.v:3208$758_Y + connect \A $and$ls180.v:3199$756_Y + connect \B $eq$ls180.v:3199$757_Y + connect \Y $and$ls180.v:3199$758_Y end - attribute \src "ls180.v:3209.41-3209.105" - cell $and $and$ls180.v:3209$760 + attribute \src "ls180.v:3200.41-3200.105" + cell $and $and$ls180.v:3200$760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel - connect \B $not$ls180.v:3209$759_Y - connect \Y $and$ls180.v:3209$760_Y + connect \B $not$ls180.v:3200$759_Y + connect \Y $and$ls180.v:3200$760_Y end - attribute \src "ls180.v:3209.40-3209.159" - cell $and $and$ls180.v:3209$762 + attribute \src "ls180.v:3200.40-3200.159" + cell $and $and$ls180.v:3200$762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3209$760_Y - connect \B $eq$ls180.v:3209$761_Y - connect \Y $and$ls180.v:3209$762_Y + connect \A $and$ls180.v:3200$760_Y + connect \B $eq$ls180.v:3200$761_Y + connect \Y $and$ls180.v:3200$762_Y end - attribute \src "ls180.v:3216.40-3216.101" - cell $and $and$ls180.v:3216$764 + attribute \src "ls180.v:3207.40-3207.101" + cell $and $and$ls180.v:3207$764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250428,43 +250220,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel connect \B \libresocsim_interface2_bank_bus_we - connect \Y $and$ls180.v:3216$764_Y + connect \Y $and$ls180.v:3207$764_Y end - attribute \src "ls180.v:3216.39-3216.155" - cell $and $and$ls180.v:3216$766 + attribute \src "ls180.v:3207.39-3207.155" + cell $and $and$ls180.v:3207$766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3216$764_Y - connect \B $eq$ls180.v:3216$765_Y - connect \Y $and$ls180.v:3216$766_Y + connect \A $and$ls180.v:3207$764_Y + connect \B $eq$ls180.v:3207$765_Y + connect \Y $and$ls180.v:3207$766_Y end - attribute \src "ls180.v:3217.40-3217.104" - cell $and $and$ls180.v:3217$768 + attribute \src "ls180.v:3208.40-3208.104" + cell $and $and$ls180.v:3208$768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel - connect \B $not$ls180.v:3217$767_Y - connect \Y $and$ls180.v:3217$768_Y + connect \B $not$ls180.v:3208$767_Y + connect \Y $and$ls180.v:3208$768_Y end - attribute \src "ls180.v:3217.39-3217.158" - cell $and $and$ls180.v:3217$770 + attribute \src "ls180.v:3208.39-3208.158" + cell $and $and$ls180.v:3208$770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3217$768_Y - connect \B $eq$ls180.v:3217$769_Y - connect \Y $and$ls180.v:3217$770_Y + connect \A $and$ls180.v:3208$768_Y + connect \B $eq$ls180.v:3208$769_Y + connect \Y $and$ls180.v:3208$770_Y end - attribute \src "ls180.v:3219.39-3219.100" - cell $and $and$ls180.v:3219$771 + attribute \src "ls180.v:3210.39-3210.100" + cell $and $and$ls180.v:3210$771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250472,43 +250264,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel connect \B \libresocsim_interface2_bank_bus_we - connect \Y $and$ls180.v:3219$771_Y + connect \Y $and$ls180.v:3210$771_Y end - attribute \src "ls180.v:3219.38-3219.154" - cell $and $and$ls180.v:3219$773 + attribute \src "ls180.v:3210.38-3210.154" + cell $and $and$ls180.v:3210$773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3219$771_Y - connect \B $eq$ls180.v:3219$772_Y - connect \Y $and$ls180.v:3219$773_Y + connect \A $and$ls180.v:3210$771_Y + connect \B $eq$ls180.v:3210$772_Y + connect \Y $and$ls180.v:3210$773_Y end - attribute \src "ls180.v:3220.39-3220.103" - cell $and $and$ls180.v:3220$775 + attribute \src "ls180.v:3211.39-3211.103" + cell $and $and$ls180.v:3211$775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel - connect \B $not$ls180.v:3220$774_Y - connect \Y $and$ls180.v:3220$775_Y + connect \B $not$ls180.v:3211$774_Y + connect \Y $and$ls180.v:3211$775_Y end - attribute \src "ls180.v:3220.38-3220.157" - cell $and $and$ls180.v:3220$777 + attribute \src "ls180.v:3211.38-3211.157" + cell $and $and$ls180.v:3211$777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3220$775_Y - connect \B $eq$ls180.v:3220$776_Y - connect \Y $and$ls180.v:3220$777_Y + connect \A $and$ls180.v:3211$775_Y + connect \B $eq$ls180.v:3211$776_Y + connect \Y $and$ls180.v:3211$777_Y end - attribute \src "ls180.v:3222.41-3222.102" - cell $and $and$ls180.v:3222$778 + attribute \src "ls180.v:3213.41-3213.102" + cell $and $and$ls180.v:3213$778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250516,43 +250308,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel connect \B \libresocsim_interface2_bank_bus_we - connect \Y $and$ls180.v:3222$778_Y + connect \Y $and$ls180.v:3213$778_Y end - attribute \src "ls180.v:3222.40-3222.156" - cell $and $and$ls180.v:3222$780 + attribute \src "ls180.v:3213.40-3213.156" + cell $and $and$ls180.v:3213$780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3222$778_Y - connect \B $eq$ls180.v:3222$779_Y - connect \Y $and$ls180.v:3222$780_Y + connect \A $and$ls180.v:3213$778_Y + connect \B $eq$ls180.v:3213$779_Y + connect \Y $and$ls180.v:3213$780_Y end - attribute \src "ls180.v:3223.41-3223.105" - cell $and $and$ls180.v:3223$782 + attribute \src "ls180.v:3214.41-3214.105" + cell $and $and$ls180.v:3214$782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel - connect \B $not$ls180.v:3223$781_Y - connect \Y $and$ls180.v:3223$782_Y + connect \B $not$ls180.v:3214$781_Y + connect \Y $and$ls180.v:3214$782_Y end - attribute \src "ls180.v:3223.40-3223.159" - cell $and $and$ls180.v:3223$784 + attribute \src "ls180.v:3214.40-3214.159" + cell $and $and$ls180.v:3214$784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3223$782_Y - connect \B $eq$ls180.v:3223$783_Y - connect \Y $and$ls180.v:3223$784_Y + connect \A $and$ls180.v:3214$782_Y + connect \B $eq$ls180.v:3214$783_Y + connect \Y $and$ls180.v:3214$784_Y end - attribute \src "ls180.v:3230.39-3230.100" - cell $and $and$ls180.v:3230$786 + attribute \src "ls180.v:3221.39-3221.100" + cell $and $and$ls180.v:3221$786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250560,43 +250352,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank3_sel connect \B \libresocsim_interface3_bank_bus_we - connect \Y $and$ls180.v:3230$786_Y + connect \Y $and$ls180.v:3221$786_Y end - attribute \src "ls180.v:3230.38-3230.152" - cell $and $and$ls180.v:3230$788 + attribute \src "ls180.v:3221.38-3221.152" + cell $and $and$ls180.v:3221$788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3230$786_Y - connect \B $eq$ls180.v:3230$787_Y - connect \Y $and$ls180.v:3230$788_Y + connect \A $and$ls180.v:3221$786_Y + connect \B $eq$ls180.v:3221$787_Y + connect \Y $and$ls180.v:3221$788_Y end - attribute \src "ls180.v:3231.39-3231.103" - cell $and $and$ls180.v:3231$790 + attribute \src "ls180.v:3222.39-3222.103" + cell $and $and$ls180.v:3222$790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank3_sel - connect \B $not$ls180.v:3231$789_Y - connect \Y $and$ls180.v:3231$790_Y + connect \B $not$ls180.v:3222$789_Y + connect \Y $and$ls180.v:3222$790_Y end - attribute \src "ls180.v:3231.38-3231.155" - cell $and $and$ls180.v:3231$792 + attribute \src "ls180.v:3222.38-3222.155" + cell $and $and$ls180.v:3222$792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3231$790_Y - connect \B $eq$ls180.v:3231$791_Y - connect \Y $and$ls180.v:3231$792_Y + connect \A $and$ls180.v:3222$790_Y + connect \B $eq$ls180.v:3222$791_Y + connect \Y $and$ls180.v:3222$792_Y end - attribute \src "ls180.v:3233.38-3233.99" - cell $and $and$ls180.v:3233$793 + attribute \src "ls180.v:3224.38-3224.99" + cell $and $and$ls180.v:3224$793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250604,43 +250396,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank3_sel connect \B \libresocsim_interface3_bank_bus_we - connect \Y $and$ls180.v:3233$793_Y + connect \Y $and$ls180.v:3224$793_Y end - attribute \src "ls180.v:3233.37-3233.151" - cell $and $and$ls180.v:3233$795 + attribute \src "ls180.v:3224.37-3224.151" + cell $and $and$ls180.v:3224$795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3233$793_Y - connect \B $eq$ls180.v:3233$794_Y - connect \Y $and$ls180.v:3233$795_Y + connect \A $and$ls180.v:3224$793_Y + connect \B $eq$ls180.v:3224$794_Y + connect \Y $and$ls180.v:3224$795_Y end - attribute \src "ls180.v:3234.38-3234.102" - cell $and $and$ls180.v:3234$797 + attribute \src "ls180.v:3225.38-3225.102" + cell $and $and$ls180.v:3225$797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank3_sel - connect \B $not$ls180.v:3234$796_Y - connect \Y $and$ls180.v:3234$797_Y + connect \B $not$ls180.v:3225$796_Y + connect \Y $and$ls180.v:3225$797_Y end - attribute \src "ls180.v:3234.37-3234.154" - cell $and $and$ls180.v:3234$799 + attribute \src "ls180.v:3225.37-3225.154" + cell $and $and$ls180.v:3225$799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3234$797_Y - connect \B $eq$ls180.v:3234$798_Y - connect \Y $and$ls180.v:3234$799_Y + connect \A $and$ls180.v:3225$797_Y + connect \B $eq$ls180.v:3225$798_Y + connect \Y $and$ls180.v:3225$799_Y end - attribute \src "ls180.v:3244.50-3244.111" - cell $and $and$ls180.v:3244$801 + attribute \src "ls180.v:3235.50-3235.111" + cell $and $and$ls180.v:3235$801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250648,43 +250440,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we - connect \Y $and$ls180.v:3244$801_Y + connect \Y $and$ls180.v:3235$801_Y end - attribute \src "ls180.v:3244.49-3244.165" - cell $and $and$ls180.v:3244$803 + attribute \src "ls180.v:3235.49-3235.165" + cell $and $and$ls180.v:3235$803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3244$801_Y - connect \B $eq$ls180.v:3244$802_Y - connect \Y $and$ls180.v:3244$803_Y + connect \A $and$ls180.v:3235$801_Y + connect \B $eq$ls180.v:3235$802_Y + connect \Y $and$ls180.v:3235$803_Y end - attribute \src "ls180.v:3245.50-3245.114" - cell $and $and$ls180.v:3245$805 + attribute \src "ls180.v:3236.50-3236.114" + cell $and $and$ls180.v:3236$805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel - connect \B $not$ls180.v:3245$804_Y - connect \Y $and$ls180.v:3245$805_Y + connect \B $not$ls180.v:3236$804_Y + connect \Y $and$ls180.v:3236$805_Y end - attribute \src "ls180.v:3245.49-3245.168" - cell $and $and$ls180.v:3245$807 + attribute \src "ls180.v:3236.49-3236.168" + cell $and $and$ls180.v:3236$807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3245$805_Y - connect \B $eq$ls180.v:3245$806_Y - connect \Y $and$ls180.v:3245$807_Y + connect \A $and$ls180.v:3236$805_Y + connect \B $eq$ls180.v:3236$806_Y + connect \Y $and$ls180.v:3236$807_Y end - attribute \src "ls180.v:3247.54-3247.115" - cell $and $and$ls180.v:3247$808 + attribute \src "ls180.v:3238.54-3238.115" + cell $and $and$ls180.v:3238$808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250692,43 +250484,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we - connect \Y $and$ls180.v:3247$808_Y + connect \Y $and$ls180.v:3238$808_Y end - attribute \src "ls180.v:3247.53-3247.169" - cell $and $and$ls180.v:3247$810 + attribute \src "ls180.v:3238.53-3238.169" + cell $and $and$ls180.v:3238$810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3247$808_Y - connect \B $eq$ls180.v:3247$809_Y - connect \Y $and$ls180.v:3247$810_Y + connect \A $and$ls180.v:3238$808_Y + connect \B $eq$ls180.v:3238$809_Y + connect \Y $and$ls180.v:3238$810_Y end - attribute \src "ls180.v:3248.54-3248.118" - cell $and $and$ls180.v:3248$812 + attribute \src "ls180.v:3239.54-3239.118" + cell $and $and$ls180.v:3239$812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel - connect \B $not$ls180.v:3248$811_Y - connect \Y $and$ls180.v:3248$812_Y + connect \B $not$ls180.v:3239$811_Y + connect \Y $and$ls180.v:3239$812_Y end - attribute \src "ls180.v:3248.53-3248.172" - cell $and $and$ls180.v:3248$814 + attribute \src "ls180.v:3239.53-3239.172" + cell $and $and$ls180.v:3239$814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3248$812_Y - connect \B $eq$ls180.v:3248$813_Y - connect \Y $and$ls180.v:3248$814_Y + connect \A $and$ls180.v:3239$812_Y + connect \B $eq$ls180.v:3239$813_Y + connect \Y $and$ls180.v:3239$814_Y end - attribute \src "ls180.v:3250.35-3250.96" - cell $and $and$ls180.v:3250$815 + attribute \src "ls180.v:3241.35-3241.96" + cell $and $and$ls180.v:3241$815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250736,43 +250528,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we - connect \Y $and$ls180.v:3250$815_Y + connect \Y $and$ls180.v:3241$815_Y end - attribute \src "ls180.v:3250.34-3250.150" - cell $and $and$ls180.v:3250$817 + attribute \src "ls180.v:3241.34-3241.150" + cell $and $and$ls180.v:3241$817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3250$815_Y - connect \B $eq$ls180.v:3250$816_Y - connect \Y $and$ls180.v:3250$817_Y + connect \A $and$ls180.v:3241$815_Y + connect \B $eq$ls180.v:3241$816_Y + connect \Y $and$ls180.v:3241$817_Y end - attribute \src "ls180.v:3251.35-3251.99" - cell $and $and$ls180.v:3251$819 + attribute \src "ls180.v:3242.35-3242.99" + cell $and $and$ls180.v:3242$819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel - connect \B $not$ls180.v:3251$818_Y - connect \Y $and$ls180.v:3251$819_Y + connect \B $not$ls180.v:3242$818_Y + connect \Y $and$ls180.v:3242$819_Y end - attribute \src "ls180.v:3251.34-3251.153" - cell $and $and$ls180.v:3251$821 + attribute \src "ls180.v:3242.34-3242.153" + cell $and $and$ls180.v:3242$821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3251$819_Y - connect \B $eq$ls180.v:3251$820_Y - connect \Y $and$ls180.v:3251$821_Y + connect \A $and$ls180.v:3242$819_Y + connect \B $eq$ls180.v:3242$820_Y + connect \Y $and$ls180.v:3242$821_Y end - attribute \src "ls180.v:3253.54-3253.115" - cell $and $and$ls180.v:3253$822 + attribute \src "ls180.v:3244.54-3244.115" + cell $and $and$ls180.v:3244$822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250780,43 +250572,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we - connect \Y $and$ls180.v:3253$822_Y + connect \Y $and$ls180.v:3244$822_Y end - attribute \src "ls180.v:3253.53-3253.169" - cell $and $and$ls180.v:3253$824 + attribute \src "ls180.v:3244.53-3244.169" + cell $and $and$ls180.v:3244$824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3253$822_Y - connect \B $eq$ls180.v:3253$823_Y - connect \Y $and$ls180.v:3253$824_Y + connect \A $and$ls180.v:3244$822_Y + connect \B $eq$ls180.v:3244$823_Y + connect \Y $and$ls180.v:3244$824_Y end - attribute \src "ls180.v:3254.54-3254.118" - cell $and $and$ls180.v:3254$826 + attribute \src "ls180.v:3245.54-3245.118" + cell $and $and$ls180.v:3245$826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel - connect \B $not$ls180.v:3254$825_Y - connect \Y $and$ls180.v:3254$826_Y + connect \B $not$ls180.v:3245$825_Y + connect \Y $and$ls180.v:3245$826_Y end - attribute \src "ls180.v:3254.53-3254.172" - cell $and $and$ls180.v:3254$828 + attribute \src "ls180.v:3245.53-3245.172" + cell $and $and$ls180.v:3245$828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3254$826_Y - connect \B $eq$ls180.v:3254$827_Y - connect \Y $and$ls180.v:3254$828_Y + connect \A $and$ls180.v:3245$826_Y + connect \B $eq$ls180.v:3245$827_Y + connect \Y $and$ls180.v:3245$828_Y end - attribute \src "ls180.v:3256.54-3256.115" - cell $and $and$ls180.v:3256$829 + attribute \src "ls180.v:3247.54-3247.115" + cell $and $and$ls180.v:3247$829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250824,43 +250616,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we - connect \Y $and$ls180.v:3256$829_Y + connect \Y $and$ls180.v:3247$829_Y end - attribute \src "ls180.v:3256.53-3256.169" - cell $and $and$ls180.v:3256$831 + attribute \src "ls180.v:3247.53-3247.169" + cell $and $and$ls180.v:3247$831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3256$829_Y - connect \B $eq$ls180.v:3256$830_Y - connect \Y $and$ls180.v:3256$831_Y + connect \A $and$ls180.v:3247$829_Y + connect \B $eq$ls180.v:3247$830_Y + connect \Y $and$ls180.v:3247$831_Y end - attribute \src "ls180.v:3257.54-3257.118" - cell $and $and$ls180.v:3257$833 + attribute \src "ls180.v:3248.54-3248.118" + cell $and $and$ls180.v:3248$833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel - connect \B $not$ls180.v:3257$832_Y - connect \Y $and$ls180.v:3257$833_Y + connect \B $not$ls180.v:3248$832_Y + connect \Y $and$ls180.v:3248$833_Y end - attribute \src "ls180.v:3257.53-3257.172" - cell $and $and$ls180.v:3257$835 + attribute \src "ls180.v:3248.53-3248.172" + cell $and $and$ls180.v:3248$835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3257$833_Y - connect \B $eq$ls180.v:3257$834_Y - connect \Y $and$ls180.v:3257$835_Y + connect \A $and$ls180.v:3248$833_Y + connect \B $eq$ls180.v:3248$834_Y + connect \Y $and$ls180.v:3248$835_Y end - attribute \src "ls180.v:3259.55-3259.116" - cell $and $and$ls180.v:3259$836 + attribute \src "ls180.v:3250.55-3250.116" + cell $and $and$ls180.v:3250$836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250868,43 +250660,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we - connect \Y $and$ls180.v:3259$836_Y + connect \Y $and$ls180.v:3250$836_Y end - attribute \src "ls180.v:3259.54-3259.170" - cell $and $and$ls180.v:3259$838 + attribute \src "ls180.v:3250.54-3250.170" + cell $and $and$ls180.v:3250$838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3259$836_Y - connect \B $eq$ls180.v:3259$837_Y - connect \Y $and$ls180.v:3259$838_Y + connect \A $and$ls180.v:3250$836_Y + connect \B $eq$ls180.v:3250$837_Y + connect \Y $and$ls180.v:3250$838_Y end - attribute \src "ls180.v:3260.55-3260.119" - cell $and $and$ls180.v:3260$840 + attribute \src "ls180.v:3251.55-3251.119" + cell $and $and$ls180.v:3251$840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel - connect \B $not$ls180.v:3260$839_Y - connect \Y $and$ls180.v:3260$840_Y + connect \B $not$ls180.v:3251$839_Y + connect \Y $and$ls180.v:3251$840_Y end - attribute \src "ls180.v:3260.54-3260.173" - cell $and $and$ls180.v:3260$842 + attribute \src "ls180.v:3251.54-3251.173" + cell $and $and$ls180.v:3251$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3260$840_Y - connect \B $eq$ls180.v:3260$841_Y - connect \Y $and$ls180.v:3260$842_Y + connect \A $and$ls180.v:3251$840_Y + connect \B $eq$ls180.v:3251$841_Y + connect \Y $and$ls180.v:3251$842_Y end - attribute \src "ls180.v:3262.53-3262.114" - cell $and $and$ls180.v:3262$843 + attribute \src "ls180.v:3253.53-3253.114" + cell $and $and$ls180.v:3253$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250912,43 +250704,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we - connect \Y $and$ls180.v:3262$843_Y + connect \Y $and$ls180.v:3253$843_Y end - attribute \src "ls180.v:3262.52-3262.168" - cell $and $and$ls180.v:3262$845 + attribute \src "ls180.v:3253.52-3253.168" + cell $and $and$ls180.v:3253$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3262$843_Y - connect \B $eq$ls180.v:3262$844_Y - connect \Y $and$ls180.v:3262$845_Y + connect \A $and$ls180.v:3253$843_Y + connect \B $eq$ls180.v:3253$844_Y + connect \Y $and$ls180.v:3253$845_Y end - attribute \src "ls180.v:3263.53-3263.117" - cell $and $and$ls180.v:3263$847 + attribute \src "ls180.v:3254.53-3254.117" + cell $and $and$ls180.v:3254$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel - connect \B $not$ls180.v:3263$846_Y - connect \Y $and$ls180.v:3263$847_Y + connect \B $not$ls180.v:3254$846_Y + connect \Y $and$ls180.v:3254$847_Y end - attribute \src "ls180.v:3263.52-3263.171" - cell $and $and$ls180.v:3263$849 + attribute \src "ls180.v:3254.52-3254.171" + cell $and $and$ls180.v:3254$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3263$847_Y - connect \B $eq$ls180.v:3263$848_Y - connect \Y $and$ls180.v:3263$849_Y + connect \A $and$ls180.v:3254$847_Y + connect \B $eq$ls180.v:3254$848_Y + connect \Y $and$ls180.v:3254$849_Y end - attribute \src "ls180.v:3265.53-3265.114" - cell $and $and$ls180.v:3265$850 + attribute \src "ls180.v:3256.53-3256.114" + cell $and $and$ls180.v:3256$850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250956,43 +250748,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we - connect \Y $and$ls180.v:3265$850_Y + connect \Y $and$ls180.v:3256$850_Y end - attribute \src "ls180.v:3265.52-3265.168" - cell $and $and$ls180.v:3265$852 + attribute \src "ls180.v:3256.52-3256.168" + cell $and $and$ls180.v:3256$852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3265$850_Y - connect \B $eq$ls180.v:3265$851_Y - connect \Y $and$ls180.v:3265$852_Y + connect \A $and$ls180.v:3256$850_Y + connect \B $eq$ls180.v:3256$851_Y + connect \Y $and$ls180.v:3256$852_Y end - attribute \src "ls180.v:3266.53-3266.117" - cell $and $and$ls180.v:3266$854 + attribute \src "ls180.v:3257.53-3257.117" + cell $and $and$ls180.v:3257$854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel - connect \B $not$ls180.v:3266$853_Y - connect \Y $and$ls180.v:3266$854_Y + connect \B $not$ls180.v:3257$853_Y + connect \Y $and$ls180.v:3257$854_Y end - attribute \src "ls180.v:3266.52-3266.171" - cell $and $and$ls180.v:3266$856 + attribute \src "ls180.v:3257.52-3257.171" + cell $and $and$ls180.v:3257$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3266$854_Y - connect \B $eq$ls180.v:3266$855_Y - connect \Y $and$ls180.v:3266$856_Y + connect \A $and$ls180.v:3257$854_Y + connect \B $eq$ls180.v:3257$855_Y + connect \Y $and$ls180.v:3257$856_Y end - attribute \src "ls180.v:3268.53-3268.114" - cell $and $and$ls180.v:3268$857 + attribute \src "ls180.v:3259.53-3259.114" + cell $and $and$ls180.v:3259$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251000,43 +250792,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we - connect \Y $and$ls180.v:3268$857_Y + connect \Y $and$ls180.v:3259$857_Y end - attribute \src "ls180.v:3268.52-3268.168" - cell $and $and$ls180.v:3268$859 + attribute \src "ls180.v:3259.52-3259.168" + cell $and $and$ls180.v:3259$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3268$857_Y - connect \B $eq$ls180.v:3268$858_Y - connect \Y $and$ls180.v:3268$859_Y + connect \A $and$ls180.v:3259$857_Y + connect \B $eq$ls180.v:3259$858_Y + connect \Y $and$ls180.v:3259$859_Y end - attribute \src "ls180.v:3269.53-3269.117" - cell $and $and$ls180.v:3269$861 + attribute \src "ls180.v:3260.53-3260.117" + cell $and $and$ls180.v:3260$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel - connect \B $not$ls180.v:3269$860_Y - connect \Y $and$ls180.v:3269$861_Y + connect \B $not$ls180.v:3260$860_Y + connect \Y $and$ls180.v:3260$861_Y end - attribute \src "ls180.v:3269.52-3269.171" - cell $and $and$ls180.v:3269$863 + attribute \src "ls180.v:3260.52-3260.171" + cell $and $and$ls180.v:3260$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3269$861_Y - connect \B $eq$ls180.v:3269$862_Y - connect \Y $and$ls180.v:3269$863_Y + connect \A $and$ls180.v:3260$861_Y + connect \B $eq$ls180.v:3260$862_Y + connect \Y $and$ls180.v:3260$863_Y end - attribute \src "ls180.v:3271.53-3271.114" - cell $and $and$ls180.v:3271$864 + attribute \src "ls180.v:3262.53-3262.114" + cell $and $and$ls180.v:3262$864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251044,43 +250836,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we - connect \Y $and$ls180.v:3271$864_Y + connect \Y $and$ls180.v:3262$864_Y end - attribute \src "ls180.v:3271.52-3271.168" - cell $and $and$ls180.v:3271$866 + attribute \src "ls180.v:3262.52-3262.168" + cell $and $and$ls180.v:3262$866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3271$864_Y - connect \B $eq$ls180.v:3271$865_Y - connect \Y $and$ls180.v:3271$866_Y + connect \A $and$ls180.v:3262$864_Y + connect \B $eq$ls180.v:3262$865_Y + connect \Y $and$ls180.v:3262$866_Y end - attribute \src "ls180.v:3272.53-3272.117" - cell $and $and$ls180.v:3272$868 + attribute \src "ls180.v:3263.53-3263.117" + cell $and $and$ls180.v:3263$868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel - connect \B $not$ls180.v:3272$867_Y - connect \Y $and$ls180.v:3272$868_Y + connect \B $not$ls180.v:3263$867_Y + connect \Y $and$ls180.v:3263$868_Y end - attribute \src "ls180.v:3272.52-3272.171" - cell $and $and$ls180.v:3272$870 + attribute \src "ls180.v:3263.52-3263.171" + cell $and $and$ls180.v:3263$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3272$868_Y - connect \B $eq$ls180.v:3272$869_Y - connect \Y $and$ls180.v:3272$870_Y + connect \A $and$ls180.v:3263$868_Y + connect \B $eq$ls180.v:3263$869_Y + connect \Y $and$ls180.v:3263$870_Y end - attribute \src "ls180.v:3289.42-3289.103" - cell $and $and$ls180.v:3289$872 + attribute \src "ls180.v:3280.42-3280.103" + cell $and $and$ls180.v:3280$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251088,43 +250880,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3289$872_Y + connect \Y $and$ls180.v:3280$872_Y end - attribute \src "ls180.v:3289.41-3289.157" - cell $and $and$ls180.v:3289$874 + attribute \src "ls180.v:3280.41-3280.157" + cell $and $and$ls180.v:3280$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3289$872_Y - connect \B $eq$ls180.v:3289$873_Y - connect \Y $and$ls180.v:3289$874_Y + connect \A $and$ls180.v:3280$872_Y + connect \B $eq$ls180.v:3280$873_Y + connect \Y $and$ls180.v:3280$874_Y end - attribute \src "ls180.v:3290.42-3290.106" - cell $and $and$ls180.v:3290$876 + attribute \src "ls180.v:3281.42-3281.106" + cell $and $and$ls180.v:3281$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3290$875_Y - connect \Y $and$ls180.v:3290$876_Y + connect \B $not$ls180.v:3281$875_Y + connect \Y $and$ls180.v:3281$876_Y end - attribute \src "ls180.v:3290.41-3290.160" - cell $and $and$ls180.v:3290$878 + attribute \src "ls180.v:3281.41-3281.160" + cell $and $and$ls180.v:3281$878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3290$876_Y - connect \B $eq$ls180.v:3290$877_Y - connect \Y $and$ls180.v:3290$878_Y + connect \A $and$ls180.v:3281$876_Y + connect \B $eq$ls180.v:3281$877_Y + connect \Y $and$ls180.v:3281$878_Y end - attribute \src "ls180.v:3292.42-3292.103" - cell $and $and$ls180.v:3292$879 + attribute \src "ls180.v:3283.42-3283.103" + cell $and $and$ls180.v:3283$879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251132,43 +250924,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3292$879_Y + connect \Y $and$ls180.v:3283$879_Y end - attribute \src "ls180.v:3292.41-3292.157" - cell $and $and$ls180.v:3292$881 + attribute \src "ls180.v:3283.41-3283.157" + cell $and $and$ls180.v:3283$881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3292$879_Y - connect \B $eq$ls180.v:3292$880_Y - connect \Y $and$ls180.v:3292$881_Y + connect \A $and$ls180.v:3283$879_Y + connect \B $eq$ls180.v:3283$880_Y + connect \Y $and$ls180.v:3283$881_Y end - attribute \src "ls180.v:3293.42-3293.106" - cell $and $and$ls180.v:3293$883 + attribute \src "ls180.v:3284.42-3284.106" + cell $and $and$ls180.v:3284$883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3293$882_Y - connect \Y $and$ls180.v:3293$883_Y + connect \B $not$ls180.v:3284$882_Y + connect \Y $and$ls180.v:3284$883_Y end - attribute \src "ls180.v:3293.41-3293.160" - cell $and $and$ls180.v:3293$885 + attribute \src "ls180.v:3284.41-3284.160" + cell $and $and$ls180.v:3284$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3293$883_Y - connect \B $eq$ls180.v:3293$884_Y - connect \Y $and$ls180.v:3293$885_Y + connect \A $and$ls180.v:3284$883_Y + connect \B $eq$ls180.v:3284$884_Y + connect \Y $and$ls180.v:3284$885_Y end - attribute \src "ls180.v:3295.42-3295.103" - cell $and $and$ls180.v:3295$886 + attribute \src "ls180.v:3286.42-3286.103" + cell $and $and$ls180.v:3286$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251176,43 +250968,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3295$886_Y + connect \Y $and$ls180.v:3286$886_Y end - attribute \src "ls180.v:3295.41-3295.157" - cell $and $and$ls180.v:3295$888 + attribute \src "ls180.v:3286.41-3286.157" + cell $and $and$ls180.v:3286$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3295$886_Y - connect \B $eq$ls180.v:3295$887_Y - connect \Y $and$ls180.v:3295$888_Y + connect \A $and$ls180.v:3286$886_Y + connect \B $eq$ls180.v:3286$887_Y + connect \Y $and$ls180.v:3286$888_Y end - attribute \src "ls180.v:3296.42-3296.106" - cell $and $and$ls180.v:3296$890 + attribute \src "ls180.v:3287.42-3287.106" + cell $and $and$ls180.v:3287$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3296$889_Y - connect \Y $and$ls180.v:3296$890_Y + connect \B $not$ls180.v:3287$889_Y + connect \Y $and$ls180.v:3287$890_Y end - attribute \src "ls180.v:3296.41-3296.160" - cell $and $and$ls180.v:3296$892 + attribute \src "ls180.v:3287.41-3287.160" + cell $and $and$ls180.v:3287$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3296$890_Y - connect \B $eq$ls180.v:3296$891_Y - connect \Y $and$ls180.v:3296$892_Y + connect \A $and$ls180.v:3287$890_Y + connect \B $eq$ls180.v:3287$891_Y + connect \Y $and$ls180.v:3287$892_Y end - attribute \src "ls180.v:3298.42-3298.103" - cell $and $and$ls180.v:3298$893 + attribute \src "ls180.v:3289.42-3289.103" + cell $and $and$ls180.v:3289$893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251220,43 +251012,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3298$893_Y + connect \Y $and$ls180.v:3289$893_Y end - attribute \src "ls180.v:3298.41-3298.157" - cell $and $and$ls180.v:3298$895 + attribute \src "ls180.v:3289.41-3289.157" + cell $and $and$ls180.v:3289$895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3298$893_Y - connect \B $eq$ls180.v:3298$894_Y - connect \Y $and$ls180.v:3298$895_Y + connect \A $and$ls180.v:3289$893_Y + connect \B $eq$ls180.v:3289$894_Y + connect \Y $and$ls180.v:3289$895_Y end - attribute \src "ls180.v:3299.42-3299.106" - cell $and $and$ls180.v:3299$897 + attribute \src "ls180.v:3290.42-3290.106" + cell $and $and$ls180.v:3290$897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3299$896_Y - connect \Y $and$ls180.v:3299$897_Y + connect \B $not$ls180.v:3290$896_Y + connect \Y $and$ls180.v:3290$897_Y end - attribute \src "ls180.v:3299.41-3299.160" - cell $and $and$ls180.v:3299$899 + attribute \src "ls180.v:3290.41-3290.160" + cell $and $and$ls180.v:3290$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3299$897_Y - connect \B $eq$ls180.v:3299$898_Y - connect \Y $and$ls180.v:3299$899_Y + connect \A $and$ls180.v:3290$897_Y + connect \B $eq$ls180.v:3290$898_Y + connect \Y $and$ls180.v:3290$899_Y end - attribute \src "ls180.v:3301.44-3301.105" - cell $and $and$ls180.v:3301$900 + attribute \src "ls180.v:3292.44-3292.105" + cell $and $and$ls180.v:3292$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251264,43 +251056,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3301$900_Y + connect \Y $and$ls180.v:3292$900_Y end - attribute \src "ls180.v:3301.43-3301.159" - cell $and $and$ls180.v:3301$902 + attribute \src "ls180.v:3292.43-3292.159" + cell $and $and$ls180.v:3292$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3301$900_Y - connect \B $eq$ls180.v:3301$901_Y - connect \Y $and$ls180.v:3301$902_Y + connect \A $and$ls180.v:3292$900_Y + connect \B $eq$ls180.v:3292$901_Y + connect \Y $and$ls180.v:3292$902_Y end - attribute \src "ls180.v:3302.44-3302.108" - cell $and $and$ls180.v:3302$904 + attribute \src "ls180.v:3293.44-3293.108" + cell $and $and$ls180.v:3293$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3302$903_Y - connect \Y $and$ls180.v:3302$904_Y + connect \B $not$ls180.v:3293$903_Y + connect \Y $and$ls180.v:3293$904_Y end - attribute \src "ls180.v:3302.43-3302.162" - cell $and $and$ls180.v:3302$906 + attribute \src "ls180.v:3293.43-3293.162" + cell $and $and$ls180.v:3293$906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3302$904_Y - connect \B $eq$ls180.v:3302$905_Y - connect \Y $and$ls180.v:3302$906_Y + connect \A $and$ls180.v:3293$904_Y + connect \B $eq$ls180.v:3293$905_Y + connect \Y $and$ls180.v:3293$906_Y end - attribute \src "ls180.v:3304.44-3304.105" - cell $and $and$ls180.v:3304$907 + attribute \src "ls180.v:3295.44-3295.105" + cell $and $and$ls180.v:3295$907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251308,43 +251100,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3304$907_Y + connect \Y $and$ls180.v:3295$907_Y end - attribute \src "ls180.v:3304.43-3304.159" - cell $and $and$ls180.v:3304$909 + attribute \src "ls180.v:3295.43-3295.159" + cell $and $and$ls180.v:3295$909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3304$907_Y - connect \B $eq$ls180.v:3304$908_Y - connect \Y $and$ls180.v:3304$909_Y + connect \A $and$ls180.v:3295$907_Y + connect \B $eq$ls180.v:3295$908_Y + connect \Y $and$ls180.v:3295$909_Y end - attribute \src "ls180.v:3305.44-3305.108" - cell $and $and$ls180.v:3305$911 + attribute \src "ls180.v:3296.44-3296.108" + cell $and $and$ls180.v:3296$911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3305$910_Y - connect \Y $and$ls180.v:3305$911_Y + connect \B $not$ls180.v:3296$910_Y + connect \Y $and$ls180.v:3296$911_Y end - attribute \src "ls180.v:3305.43-3305.162" - cell $and $and$ls180.v:3305$913 + attribute \src "ls180.v:3296.43-3296.162" + cell $and $and$ls180.v:3296$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3305$911_Y - connect \B $eq$ls180.v:3305$912_Y - connect \Y $and$ls180.v:3305$913_Y + connect \A $and$ls180.v:3296$911_Y + connect \B $eq$ls180.v:3296$912_Y + connect \Y $and$ls180.v:3296$913_Y end - attribute \src "ls180.v:3307.44-3307.105" - cell $and $and$ls180.v:3307$914 + attribute \src "ls180.v:3298.44-3298.105" + cell $and $and$ls180.v:3298$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251352,43 +251144,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3307$914_Y + connect \Y $and$ls180.v:3298$914_Y end - attribute \src "ls180.v:3307.43-3307.159" - cell $and $and$ls180.v:3307$916 + attribute \src "ls180.v:3298.43-3298.159" + cell $and $and$ls180.v:3298$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3307$914_Y - connect \B $eq$ls180.v:3307$915_Y - connect \Y $and$ls180.v:3307$916_Y + connect \A $and$ls180.v:3298$914_Y + connect \B $eq$ls180.v:3298$915_Y + connect \Y $and$ls180.v:3298$916_Y end - attribute \src "ls180.v:3308.44-3308.108" - cell $and $and$ls180.v:3308$918 + attribute \src "ls180.v:3299.44-3299.108" + cell $and $and$ls180.v:3299$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3308$917_Y - connect \Y $and$ls180.v:3308$918_Y + connect \B $not$ls180.v:3299$917_Y + connect \Y $and$ls180.v:3299$918_Y end - attribute \src "ls180.v:3308.43-3308.162" - cell $and $and$ls180.v:3308$920 + attribute \src "ls180.v:3299.43-3299.162" + cell $and $and$ls180.v:3299$920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3308$918_Y - connect \B $eq$ls180.v:3308$919_Y - connect \Y $and$ls180.v:3308$920_Y + connect \A $and$ls180.v:3299$918_Y + connect \B $eq$ls180.v:3299$919_Y + connect \Y $and$ls180.v:3299$920_Y end - attribute \src "ls180.v:3310.44-3310.105" - cell $and $and$ls180.v:3310$921 + attribute \src "ls180.v:3301.44-3301.105" + cell $and $and$ls180.v:3301$921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251396,43 +251188,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3310$921_Y + connect \Y $and$ls180.v:3301$921_Y end - attribute \src "ls180.v:3310.43-3310.159" - cell $and $and$ls180.v:3310$923 + attribute \src "ls180.v:3301.43-3301.159" + cell $and $and$ls180.v:3301$923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3310$921_Y - connect \B $eq$ls180.v:3310$922_Y - connect \Y $and$ls180.v:3310$923_Y + connect \A $and$ls180.v:3301$921_Y + connect \B $eq$ls180.v:3301$922_Y + connect \Y $and$ls180.v:3301$923_Y end - attribute \src "ls180.v:3311.44-3311.108" - cell $and $and$ls180.v:3311$925 + attribute \src "ls180.v:3302.44-3302.108" + cell $and $and$ls180.v:3302$925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3311$924_Y - connect \Y $and$ls180.v:3311$925_Y + connect \B $not$ls180.v:3302$924_Y + connect \Y $and$ls180.v:3302$925_Y end - attribute \src "ls180.v:3311.43-3311.162" - cell $and $and$ls180.v:3311$927 + attribute \src "ls180.v:3302.43-3302.162" + cell $and $and$ls180.v:3302$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3311$925_Y - connect \B $eq$ls180.v:3311$926_Y - connect \Y $and$ls180.v:3311$927_Y + connect \A $and$ls180.v:3302$925_Y + connect \B $eq$ls180.v:3302$926_Y + connect \Y $and$ls180.v:3302$927_Y end - attribute \src "ls180.v:3313.40-3313.101" - cell $and $and$ls180.v:3313$928 + attribute \src "ls180.v:3304.40-3304.101" + cell $and $and$ls180.v:3304$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251440,43 +251232,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3313$928_Y + connect \Y $and$ls180.v:3304$928_Y end - attribute \src "ls180.v:3313.39-3313.155" - cell $and $and$ls180.v:3313$930 + attribute \src "ls180.v:3304.39-3304.155" + cell $and $and$ls180.v:3304$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3313$928_Y - connect \B $eq$ls180.v:3313$929_Y - connect \Y $and$ls180.v:3313$930_Y + connect \A $and$ls180.v:3304$928_Y + connect \B $eq$ls180.v:3304$929_Y + connect \Y $and$ls180.v:3304$930_Y end - attribute \src "ls180.v:3314.40-3314.104" - cell $and $and$ls180.v:3314$932 + attribute \src "ls180.v:3305.40-3305.104" + cell $and $and$ls180.v:3305$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3314$931_Y - connect \Y $and$ls180.v:3314$932_Y + connect \B $not$ls180.v:3305$931_Y + connect \Y $and$ls180.v:3305$932_Y end - attribute \src "ls180.v:3314.39-3314.158" - cell $and $and$ls180.v:3314$934 + attribute \src "ls180.v:3305.39-3305.158" + cell $and $and$ls180.v:3305$934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3314$932_Y - connect \B $eq$ls180.v:3314$933_Y - connect \Y $and$ls180.v:3314$934_Y + connect \A $and$ls180.v:3305$932_Y + connect \B $eq$ls180.v:3305$933_Y + connect \Y $and$ls180.v:3305$934_Y end - attribute \src "ls180.v:3316.50-3316.111" - cell $and $and$ls180.v:3316$935 + attribute \src "ls180.v:3307.50-3307.111" + cell $and $and$ls180.v:3307$935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251484,43 +251276,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3316$935_Y + connect \Y $and$ls180.v:3307$935_Y end - attribute \src "ls180.v:3316.49-3316.165" - cell $and $and$ls180.v:3316$937 + attribute \src "ls180.v:3307.49-3307.165" + cell $and $and$ls180.v:3307$937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3316$935_Y - connect \B $eq$ls180.v:3316$936_Y - connect \Y $and$ls180.v:3316$937_Y + connect \A $and$ls180.v:3307$935_Y + connect \B $eq$ls180.v:3307$936_Y + connect \Y $and$ls180.v:3307$937_Y end - attribute \src "ls180.v:3317.50-3317.114" - cell $and $and$ls180.v:3317$939 + attribute \src "ls180.v:3308.50-3308.114" + cell $and $and$ls180.v:3308$939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3317$938_Y - connect \Y $and$ls180.v:3317$939_Y + connect \B $not$ls180.v:3308$938_Y + connect \Y $and$ls180.v:3308$939_Y end - attribute \src "ls180.v:3317.49-3317.168" - cell $and $and$ls180.v:3317$941 + attribute \src "ls180.v:3308.49-3308.168" + cell $and $and$ls180.v:3308$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3317$939_Y - connect \B $eq$ls180.v:3317$940_Y - connect \Y $and$ls180.v:3317$941_Y + connect \A $and$ls180.v:3308$939_Y + connect \B $eq$ls180.v:3308$940_Y + connect \Y $and$ls180.v:3308$941_Y end - attribute \src "ls180.v:3319.43-3319.104" - cell $and $and$ls180.v:3319$942 + attribute \src "ls180.v:3310.43-3310.104" + cell $and $and$ls180.v:3310$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251528,43 +251320,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3319$942_Y + connect \Y $and$ls180.v:3310$942_Y end - attribute \src "ls180.v:3319.42-3319.159" - cell $and $and$ls180.v:3319$944 + attribute \src "ls180.v:3310.42-3310.159" + cell $and $and$ls180.v:3310$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3319$942_Y - connect \B $eq$ls180.v:3319$943_Y - connect \Y $and$ls180.v:3319$944_Y + connect \A $and$ls180.v:3310$942_Y + connect \B $eq$ls180.v:3310$943_Y + connect \Y $and$ls180.v:3310$944_Y end - attribute \src "ls180.v:3320.43-3320.107" - cell $and $and$ls180.v:3320$946 + attribute \src "ls180.v:3311.43-3311.107" + cell $and $and$ls180.v:3311$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3320$945_Y - connect \Y $and$ls180.v:3320$946_Y + connect \B $not$ls180.v:3311$945_Y + connect \Y $and$ls180.v:3311$946_Y end - attribute \src "ls180.v:3320.42-3320.162" - cell $and $and$ls180.v:3320$948 + attribute \src "ls180.v:3311.42-3311.162" + cell $and $and$ls180.v:3311$948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3320$946_Y - connect \B $eq$ls180.v:3320$947_Y - connect \Y $and$ls180.v:3320$948_Y + connect \A $and$ls180.v:3311$946_Y + connect \B $eq$ls180.v:3311$947_Y + connect \Y $and$ls180.v:3311$948_Y end - attribute \src "ls180.v:3322.43-3322.104" - cell $and $and$ls180.v:3322$949 + attribute \src "ls180.v:3313.43-3313.104" + cell $and $and$ls180.v:3313$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251572,43 +251364,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3322$949_Y + connect \Y $and$ls180.v:3313$949_Y end - attribute \src "ls180.v:3322.42-3322.159" - cell $and $and$ls180.v:3322$951 + attribute \src "ls180.v:3313.42-3313.159" + cell $and $and$ls180.v:3313$951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3322$949_Y - connect \B $eq$ls180.v:3322$950_Y - connect \Y $and$ls180.v:3322$951_Y + connect \A $and$ls180.v:3313$949_Y + connect \B $eq$ls180.v:3313$950_Y + connect \Y $and$ls180.v:3313$951_Y end - attribute \src "ls180.v:3323.43-3323.107" - cell $and $and$ls180.v:3323$953 + attribute \src "ls180.v:3314.43-3314.107" + cell $and $and$ls180.v:3314$953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3323$952_Y - connect \Y $and$ls180.v:3323$953_Y + connect \B $not$ls180.v:3314$952_Y + connect \Y $and$ls180.v:3314$953_Y end - attribute \src "ls180.v:3323.42-3323.162" - cell $and $and$ls180.v:3323$955 + attribute \src "ls180.v:3314.42-3314.162" + cell $and $and$ls180.v:3314$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3323$953_Y - connect \B $eq$ls180.v:3323$954_Y - connect \Y $and$ls180.v:3323$955_Y + connect \A $and$ls180.v:3314$953_Y + connect \B $eq$ls180.v:3314$954_Y + connect \Y $and$ls180.v:3314$955_Y end - attribute \src "ls180.v:3325.43-3325.104" - cell $and $and$ls180.v:3325$956 + attribute \src "ls180.v:3316.43-3316.104" + cell $and $and$ls180.v:3316$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251616,43 +251408,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3325$956_Y + connect \Y $and$ls180.v:3316$956_Y end - attribute \src "ls180.v:3325.42-3325.159" - cell $and $and$ls180.v:3325$958 + attribute \src "ls180.v:3316.42-3316.159" + cell $and $and$ls180.v:3316$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3325$956_Y - connect \B $eq$ls180.v:3325$957_Y - connect \Y $and$ls180.v:3325$958_Y + connect \A $and$ls180.v:3316$956_Y + connect \B $eq$ls180.v:3316$957_Y + connect \Y $and$ls180.v:3316$958_Y end - attribute \src "ls180.v:3326.43-3326.107" - cell $and $and$ls180.v:3326$960 + attribute \src "ls180.v:3317.43-3317.107" + cell $and $and$ls180.v:3317$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3326$959_Y - connect \Y $and$ls180.v:3326$960_Y + connect \B $not$ls180.v:3317$959_Y + connect \Y $and$ls180.v:3317$960_Y end - attribute \src "ls180.v:3326.42-3326.162" - cell $and $and$ls180.v:3326$962 + attribute \src "ls180.v:3317.42-3317.162" + cell $and $and$ls180.v:3317$962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3326$960_Y - connect \B $eq$ls180.v:3326$961_Y - connect \Y $and$ls180.v:3326$962_Y + connect \A $and$ls180.v:3317$960_Y + connect \B $eq$ls180.v:3317$961_Y + connect \Y $and$ls180.v:3317$962_Y end - attribute \src "ls180.v:3328.43-3328.104" - cell $and $and$ls180.v:3328$963 + attribute \src "ls180.v:3319.43-3319.104" + cell $and $and$ls180.v:3319$963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251660,43 +251452,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3328$963_Y + connect \Y $and$ls180.v:3319$963_Y end - attribute \src "ls180.v:3328.42-3328.159" - cell $and $and$ls180.v:3328$965 + attribute \src "ls180.v:3319.42-3319.159" + cell $and $and$ls180.v:3319$965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3328$963_Y - connect \B $eq$ls180.v:3328$964_Y - connect \Y $and$ls180.v:3328$965_Y + connect \A $and$ls180.v:3319$963_Y + connect \B $eq$ls180.v:3319$964_Y + connect \Y $and$ls180.v:3319$965_Y end - attribute \src "ls180.v:3329.43-3329.107" - cell $and $and$ls180.v:3329$967 + attribute \src "ls180.v:3320.43-3320.107" + cell $and $and$ls180.v:3320$967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3329$966_Y - connect \Y $and$ls180.v:3329$967_Y + connect \B $not$ls180.v:3320$966_Y + connect \Y $and$ls180.v:3320$967_Y end - attribute \src "ls180.v:3329.42-3329.162" - cell $and $and$ls180.v:3329$969 + attribute \src "ls180.v:3320.42-3320.162" + cell $and $and$ls180.v:3320$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3329$967_Y - connect \B $eq$ls180.v:3329$968_Y - connect \Y $and$ls180.v:3329$969_Y + connect \A $and$ls180.v:3320$967_Y + connect \B $eq$ls180.v:3320$968_Y + connect \Y $and$ls180.v:3320$969_Y end - attribute \src "ls180.v:3331.47-3331.108" - cell $and $and$ls180.v:3331$970 + attribute \src "ls180.v:3322.47-3322.108" + cell $and $and$ls180.v:3322$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251704,43 +251496,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3331$970_Y + connect \Y $and$ls180.v:3322$970_Y end - attribute \src "ls180.v:3331.46-3331.163" - cell $and $and$ls180.v:3331$972 + attribute \src "ls180.v:3322.46-3322.163" + cell $and $and$ls180.v:3322$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3331$970_Y - connect \B $eq$ls180.v:3331$971_Y - connect \Y $and$ls180.v:3331$972_Y + connect \A $and$ls180.v:3322$970_Y + connect \B $eq$ls180.v:3322$971_Y + connect \Y $and$ls180.v:3322$972_Y end - attribute \src "ls180.v:3332.47-3332.111" - cell $and $and$ls180.v:3332$974 + attribute \src "ls180.v:3323.47-3323.111" + cell $and $and$ls180.v:3323$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3332$973_Y - connect \Y $and$ls180.v:3332$974_Y + connect \B $not$ls180.v:3323$973_Y + connect \Y $and$ls180.v:3323$974_Y end - attribute \src "ls180.v:3332.46-3332.166" - cell $and $and$ls180.v:3332$976 + attribute \src "ls180.v:3323.46-3323.166" + cell $and $and$ls180.v:3323$976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3332$974_Y - connect \B $eq$ls180.v:3332$975_Y - connect \Y $and$ls180.v:3332$976_Y + connect \A $and$ls180.v:3323$974_Y + connect \B $eq$ls180.v:3323$975_Y + connect \Y $and$ls180.v:3323$976_Y end - attribute \src "ls180.v:3334.48-3334.109" - cell $and $and$ls180.v:3334$977 + attribute \src "ls180.v:3325.48-3325.109" + cell $and $and$ls180.v:3325$977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251748,43 +251540,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3334$977_Y + connect \Y $and$ls180.v:3325$977_Y end - attribute \src "ls180.v:3334.47-3334.164" - cell $and $and$ls180.v:3334$979 + attribute \src "ls180.v:3325.47-3325.164" + cell $and $and$ls180.v:3325$979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3334$977_Y - connect \B $eq$ls180.v:3334$978_Y - connect \Y $and$ls180.v:3334$979_Y + connect \A $and$ls180.v:3325$977_Y + connect \B $eq$ls180.v:3325$978_Y + connect \Y $and$ls180.v:3325$979_Y end - attribute \src "ls180.v:3335.48-3335.112" - cell $and $and$ls180.v:3335$981 + attribute \src "ls180.v:3326.48-3326.112" + cell $and $and$ls180.v:3326$981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3335$980_Y - connect \Y $and$ls180.v:3335$981_Y + connect \B $not$ls180.v:3326$980_Y + connect \Y $and$ls180.v:3326$981_Y end - attribute \src "ls180.v:3335.47-3335.167" - cell $and $and$ls180.v:3335$983 + attribute \src "ls180.v:3326.47-3326.167" + cell $and $and$ls180.v:3326$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3335$981_Y - connect \B $eq$ls180.v:3335$982_Y - connect \Y $and$ls180.v:3335$983_Y + connect \A $and$ls180.v:3326$981_Y + connect \B $eq$ls180.v:3326$982_Y + connect \Y $and$ls180.v:3326$983_Y end - attribute \src "ls180.v:3337.47-3337.108" - cell $and $and$ls180.v:3337$984 + attribute \src "ls180.v:3328.47-3328.108" + cell $and $and$ls180.v:3328$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251792,43 +251584,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we - connect \Y $and$ls180.v:3337$984_Y + connect \Y $and$ls180.v:3328$984_Y end - attribute \src "ls180.v:3337.46-3337.163" - cell $and $and$ls180.v:3337$986 + attribute \src "ls180.v:3328.46-3328.163" + cell $and $and$ls180.v:3328$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3337$984_Y - connect \B $eq$ls180.v:3337$985_Y - connect \Y $and$ls180.v:3337$986_Y + connect \A $and$ls180.v:3328$984_Y + connect \B $eq$ls180.v:3328$985_Y + connect \Y $and$ls180.v:3328$986_Y end - attribute \src "ls180.v:3338.47-3338.111" - cell $and $and$ls180.v:3338$988 + attribute \src "ls180.v:3329.47-3329.111" + cell $and $and$ls180.v:3329$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel - connect \B $not$ls180.v:3338$987_Y - connect \Y $and$ls180.v:3338$988_Y + connect \B $not$ls180.v:3329$987_Y + connect \Y $and$ls180.v:3329$988_Y end - attribute \src "ls180.v:3338.46-3338.166" - cell $and $and$ls180.v:3338$990 + attribute \src "ls180.v:3329.46-3329.166" + cell $and $and$ls180.v:3329$990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3338$988_Y - connect \B $eq$ls180.v:3338$989_Y - connect \Y $and$ls180.v:3338$990_Y + connect \A $and$ls180.v:3329$988_Y + connect \B $eq$ls180.v:3329$989_Y + connect \Y $and$ls180.v:3329$990_Y end - attribute \src "ls180.v:3357.20-3357.81" - cell $and $and$ls180.v:3357$992 + attribute \src "ls180.v:3348.20-3348.81" + cell $and $and$ls180.v:3348$992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251836,54 +251628,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we - connect \Y $and$ls180.v:3357$992_Y + connect \Y $and$ls180.v:3348$992_Y end - attribute \src "ls180.v:3357.19-3357.135" - cell $and $and$ls180.v:3357$994 + attribute \src "ls180.v:3348.19-3348.135" + cell $and $and$ls180.v:3348$994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3357$992_Y - connect \B $eq$ls180.v:3357$993_Y - connect \Y $and$ls180.v:3357$994_Y + connect \A $and$ls180.v:3348$992_Y + connect \B $eq$ls180.v:3348$993_Y + connect \Y $and$ls180.v:3348$994_Y end - attribute \src "ls180.v:3358.20-3358.84" - cell $and $and$ls180.v:3358$996 + attribute \src "ls180.v:3349.20-3349.84" + cell $and $and$ls180.v:3349$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel - connect \B $not$ls180.v:3358$995_Y - connect \Y $and$ls180.v:3358$996_Y + connect \B $not$ls180.v:3349$995_Y + connect \Y $and$ls180.v:3349$996_Y end - attribute \src "ls180.v:3358.19-3358.138" - cell $and $and$ls180.v:3358$998 + attribute \src "ls180.v:3349.19-3349.138" + cell $and $and$ls180.v:3349$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3358$996_Y - connect \B $eq$ls180.v:3358$997_Y - connect \Y $and$ls180.v:3358$998_Y + connect \A $and$ls180.v:3349$996_Y + connect \B $eq$ls180.v:3349$997_Y + connect \Y $and$ls180.v:3349$998_Y end - attribute \src "ls180.v:3360.42-3360.158" - cell $and $and$ls180.v:3360$1001 + attribute \src "ls180.v:3351.42-3351.158" + cell $and $and$ls180.v:3351$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3360$999_Y - connect \B $eq$ls180.v:3360$1000_Y - connect \Y $and$ls180.v:3360$1001_Y + connect \A $and$ls180.v:3351$999_Y + connect \B $eq$ls180.v:3351$1000_Y + connect \Y $and$ls180.v:3351$1001_Y end - attribute \src "ls180.v:3360.43-3360.104" - cell $and $and$ls180.v:3360$999 + attribute \src "ls180.v:3351.43-3351.104" + cell $and $and$ls180.v:3351$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251891,32 +251683,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we - connect \Y $and$ls180.v:3360$999_Y + connect \Y $and$ls180.v:3351$999_Y end - attribute \src "ls180.v:3361.43-3361.107" - cell $and $and$ls180.v:3361$1003 + attribute \src "ls180.v:3352.43-3352.107" + cell $and $and$ls180.v:3352$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel - connect \B $not$ls180.v:3361$1002_Y - connect \Y $and$ls180.v:3361$1003_Y + connect \B $not$ls180.v:3352$1002_Y + connect \Y $and$ls180.v:3352$1003_Y end - attribute \src "ls180.v:3361.42-3361.161" - cell $and $and$ls180.v:3361$1005 + attribute \src "ls180.v:3352.42-3352.161" + cell $and $and$ls180.v:3352$1005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3361$1003_Y - connect \B $eq$ls180.v:3361$1004_Y - connect \Y $and$ls180.v:3361$1005_Y + connect \A $and$ls180.v:3352$1003_Y + connect \B $eq$ls180.v:3352$1004_Y + connect \Y $and$ls180.v:3352$1005_Y end - attribute \src "ls180.v:3363.44-3363.105" - cell $and $and$ls180.v:3363$1006 + attribute \src "ls180.v:3354.44-3354.105" + cell $and $and$ls180.v:3354$1006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251924,43 +251716,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we - connect \Y $and$ls180.v:3363$1006_Y + connect \Y $and$ls180.v:3354$1006_Y end - attribute \src "ls180.v:3363.43-3363.159" - cell $and $and$ls180.v:3363$1008 + attribute \src "ls180.v:3354.43-3354.159" + cell $and $and$ls180.v:3354$1008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3363$1006_Y - connect \B $eq$ls180.v:3363$1007_Y - connect \Y $and$ls180.v:3363$1008_Y + connect \A $and$ls180.v:3354$1006_Y + connect \B $eq$ls180.v:3354$1007_Y + connect \Y $and$ls180.v:3354$1008_Y end - attribute \src "ls180.v:3364.44-3364.108" - cell $and $and$ls180.v:3364$1010 + attribute \src "ls180.v:3355.44-3355.108" + cell $and $and$ls180.v:3355$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel - connect \B $not$ls180.v:3364$1009_Y - connect \Y $and$ls180.v:3364$1010_Y + connect \B $not$ls180.v:3355$1009_Y + connect \Y $and$ls180.v:3355$1010_Y end - attribute \src "ls180.v:3364.43-3364.162" - cell $and $and$ls180.v:3364$1012 + attribute \src "ls180.v:3355.43-3355.162" + cell $and $and$ls180.v:3355$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3364$1010_Y - connect \B $eq$ls180.v:3364$1011_Y - connect \Y $and$ls180.v:3364$1012_Y + connect \A $and$ls180.v:3355$1010_Y + connect \B $eq$ls180.v:3355$1011_Y + connect \Y $and$ls180.v:3355$1012_Y end - attribute \src "ls180.v:3366.35-3366.96" - cell $and $and$ls180.v:3366$1013 + attribute \src "ls180.v:3357.35-3357.96" + cell $and $and$ls180.v:3357$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251968,43 +251760,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we - connect \Y $and$ls180.v:3366$1013_Y + connect \Y $and$ls180.v:3357$1013_Y end - attribute \src "ls180.v:3366.34-3366.150" - cell $and $and$ls180.v:3366$1015 + attribute \src "ls180.v:3357.34-3357.150" + cell $and $and$ls180.v:3357$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3366$1013_Y - connect \B $eq$ls180.v:3366$1014_Y - connect \Y $and$ls180.v:3366$1015_Y + connect \A $and$ls180.v:3357$1013_Y + connect \B $eq$ls180.v:3357$1014_Y + connect \Y $and$ls180.v:3357$1015_Y end - attribute \src "ls180.v:3367.35-3367.99" - cell $and $and$ls180.v:3367$1017 + attribute \src "ls180.v:3358.35-3358.99" + cell $and $and$ls180.v:3358$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel - connect \B $not$ls180.v:3367$1016_Y - connect \Y $and$ls180.v:3367$1017_Y + connect \B $not$ls180.v:3358$1016_Y + connect \Y $and$ls180.v:3358$1017_Y end - attribute \src "ls180.v:3367.34-3367.153" - cell $and $and$ls180.v:3367$1019 + attribute \src "ls180.v:3358.34-3358.153" + cell $and $and$ls180.v:3358$1019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3367$1017_Y - connect \B $eq$ls180.v:3367$1018_Y - connect \Y $and$ls180.v:3367$1019_Y + connect \A $and$ls180.v:3358$1017_Y + connect \B $eq$ls180.v:3358$1018_Y + connect \Y $and$ls180.v:3358$1019_Y end - attribute \src "ls180.v:3369.36-3369.97" - cell $and $and$ls180.v:3369$1020 + attribute \src "ls180.v:3360.36-3360.97" + cell $and $and$ls180.v:3360$1020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252012,43 +251804,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we - connect \Y $and$ls180.v:3369$1020_Y + connect \Y $and$ls180.v:3360$1020_Y end - attribute \src "ls180.v:3369.35-3369.151" - cell $and $and$ls180.v:3369$1022 + attribute \src "ls180.v:3360.35-3360.151" + cell $and $and$ls180.v:3360$1022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3369$1020_Y - connect \B $eq$ls180.v:3369$1021_Y - connect \Y $and$ls180.v:3369$1022_Y + connect \A $and$ls180.v:3360$1020_Y + connect \B $eq$ls180.v:3360$1021_Y + connect \Y $and$ls180.v:3360$1022_Y end - attribute \src "ls180.v:3370.36-3370.100" - cell $and $and$ls180.v:3370$1024 + attribute \src "ls180.v:3361.36-3361.100" + cell $and $and$ls180.v:3361$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel - connect \B $not$ls180.v:3370$1023_Y - connect \Y $and$ls180.v:3370$1024_Y + connect \B $not$ls180.v:3361$1023_Y + connect \Y $and$ls180.v:3361$1024_Y end - attribute \src "ls180.v:3370.35-3370.154" - cell $and $and$ls180.v:3370$1026 + attribute \src "ls180.v:3361.35-3361.154" + cell $and $and$ls180.v:3361$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3370$1024_Y - connect \B $eq$ls180.v:3370$1025_Y - connect \Y $and$ls180.v:3370$1026_Y + connect \A $and$ls180.v:3361$1024_Y + connect \B $eq$ls180.v:3361$1025_Y + connect \Y $and$ls180.v:3361$1026_Y end - attribute \src "ls180.v:3372.47-3372.108" - cell $and $and$ls180.v:3372$1027 + attribute \src "ls180.v:3363.47-3363.108" + cell $and $and$ls180.v:3363$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252056,43 +251848,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we - connect \Y $and$ls180.v:3372$1027_Y + connect \Y $and$ls180.v:3363$1027_Y end - attribute \src "ls180.v:3372.46-3372.162" - cell $and $and$ls180.v:3372$1029 + attribute \src "ls180.v:3363.46-3363.162" + cell $and $and$ls180.v:3363$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3372$1027_Y - connect \B $eq$ls180.v:3372$1028_Y - connect \Y $and$ls180.v:3372$1029_Y + connect \A $and$ls180.v:3363$1027_Y + connect \B $eq$ls180.v:3363$1028_Y + connect \Y $and$ls180.v:3363$1029_Y end - attribute \src "ls180.v:3373.47-3373.111" - cell $and $and$ls180.v:3373$1031 + attribute \src "ls180.v:3364.47-3364.111" + cell $and $and$ls180.v:3364$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel - connect \B $not$ls180.v:3373$1030_Y - connect \Y $and$ls180.v:3373$1031_Y + connect \B $not$ls180.v:3364$1030_Y + connect \Y $and$ls180.v:3364$1031_Y end - attribute \src "ls180.v:3373.46-3373.165" - cell $and $and$ls180.v:3373$1033 + attribute \src "ls180.v:3364.46-3364.165" + cell $and $and$ls180.v:3364$1033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3373$1031_Y - connect \B $eq$ls180.v:3373$1032_Y - connect \Y $and$ls180.v:3373$1033_Y + connect \A $and$ls180.v:3364$1031_Y + connect \B $eq$ls180.v:3364$1032_Y + connect \Y $and$ls180.v:3364$1033_Y end - attribute \src "ls180.v:3375.44-3375.105" - cell $and $and$ls180.v:3375$1034 + attribute \src "ls180.v:3366.44-3366.105" + cell $and $and$ls180.v:3366$1034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252100,43 +251892,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we - connect \Y $and$ls180.v:3375$1034_Y + connect \Y $and$ls180.v:3366$1034_Y end - attribute \src "ls180.v:3375.43-3375.159" - cell $and $and$ls180.v:3375$1036 + attribute \src "ls180.v:3366.43-3366.159" + cell $and $and$ls180.v:3366$1036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3375$1034_Y - connect \B $eq$ls180.v:3375$1035_Y - connect \Y $and$ls180.v:3375$1036_Y + connect \A $and$ls180.v:3366$1034_Y + connect \B $eq$ls180.v:3366$1035_Y + connect \Y $and$ls180.v:3366$1036_Y end - attribute \src "ls180.v:3376.44-3376.108" - cell $and $and$ls180.v:3376$1038 + attribute \src "ls180.v:3367.44-3367.108" + cell $and $and$ls180.v:3367$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel - connect \B $not$ls180.v:3376$1037_Y - connect \Y $and$ls180.v:3376$1038_Y + connect \B $not$ls180.v:3367$1037_Y + connect \Y $and$ls180.v:3367$1038_Y end - attribute \src "ls180.v:3376.43-3376.162" - cell $and $and$ls180.v:3376$1040 + attribute \src "ls180.v:3367.43-3367.162" + cell $and $and$ls180.v:3367$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3376$1038_Y - connect \B $eq$ls180.v:3376$1039_Y - connect \Y $and$ls180.v:3376$1040_Y + connect \A $and$ls180.v:3367$1038_Y + connect \B $eq$ls180.v:3367$1039_Y + connect \Y $and$ls180.v:3367$1040_Y end - attribute \src "ls180.v:3378.43-3378.104" - cell $and $and$ls180.v:3378$1041 + attribute \src "ls180.v:3369.43-3369.104" + cell $and $and$ls180.v:3369$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252144,43 +251936,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we - connect \Y $and$ls180.v:3378$1041_Y + connect \Y $and$ls180.v:3369$1041_Y end - attribute \src "ls180.v:3378.42-3378.158" - cell $and $and$ls180.v:3378$1043 + attribute \src "ls180.v:3369.42-3369.158" + cell $and $and$ls180.v:3369$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3378$1041_Y - connect \B $eq$ls180.v:3378$1042_Y - connect \Y $and$ls180.v:3378$1043_Y + connect \A $and$ls180.v:3369$1041_Y + connect \B $eq$ls180.v:3369$1042_Y + connect \Y $and$ls180.v:3369$1043_Y end - attribute \src "ls180.v:3379.43-3379.107" - cell $and $and$ls180.v:3379$1045 + attribute \src "ls180.v:3370.43-3370.107" + cell $and $and$ls180.v:3370$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel - connect \B $not$ls180.v:3379$1044_Y - connect \Y $and$ls180.v:3379$1045_Y + connect \B $not$ls180.v:3370$1044_Y + connect \Y $and$ls180.v:3370$1045_Y end - attribute \src "ls180.v:3379.42-3379.161" - cell $and $and$ls180.v:3379$1047 + attribute \src "ls180.v:3370.42-3370.161" + cell $and $and$ls180.v:3370$1047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3379$1045_Y - connect \B $eq$ls180.v:3379$1046_Y - connect \Y $and$ls180.v:3379$1047_Y + connect \A $and$ls180.v:3370$1045_Y + connect \B $eq$ls180.v:3370$1046_Y + connect \Y $and$ls180.v:3370$1047_Y end - attribute \src "ls180.v:3391.49-3391.110" - cell $and $and$ls180.v:3391$1049 + attribute \src "ls180.v:3382.49-3382.110" + cell $and $and$ls180.v:3382$1049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252188,43 +251980,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B \libresocsim_interface7_bank_bus_we - connect \Y $and$ls180.v:3391$1049_Y + connect \Y $and$ls180.v:3382$1049_Y end - attribute \src "ls180.v:3391.48-3391.164" - cell $and $and$ls180.v:3391$1051 + attribute \src "ls180.v:3382.48-3382.164" + cell $and $and$ls180.v:3382$1051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3391$1049_Y - connect \B $eq$ls180.v:3391$1050_Y - connect \Y $and$ls180.v:3391$1051_Y + connect \A $and$ls180.v:3382$1049_Y + connect \B $eq$ls180.v:3382$1050_Y + connect \Y $and$ls180.v:3382$1051_Y end - attribute \src "ls180.v:3392.49-3392.113" - cell $and $and$ls180.v:3392$1053 + attribute \src "ls180.v:3383.49-3383.113" + cell $and $and$ls180.v:3383$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel - connect \B $not$ls180.v:3392$1052_Y - connect \Y $and$ls180.v:3392$1053_Y + connect \B $not$ls180.v:3383$1052_Y + connect \Y $and$ls180.v:3383$1053_Y end - attribute \src "ls180.v:3392.48-3392.167" - cell $and $and$ls180.v:3392$1055 + attribute \src "ls180.v:3383.48-3383.167" + cell $and $and$ls180.v:3383$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3392$1053_Y - connect \B $eq$ls180.v:3392$1054_Y - connect \Y $and$ls180.v:3392$1055_Y + connect \A $and$ls180.v:3383$1053_Y + connect \B $eq$ls180.v:3383$1054_Y + connect \Y $and$ls180.v:3383$1055_Y end - attribute \src "ls180.v:3394.49-3394.110" - cell $and $and$ls180.v:3394$1056 + attribute \src "ls180.v:3385.49-3385.110" + cell $and $and$ls180.v:3385$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252232,43 +252024,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B \libresocsim_interface7_bank_bus_we - connect \Y $and$ls180.v:3394$1056_Y + connect \Y $and$ls180.v:3385$1056_Y end - attribute \src "ls180.v:3394.48-3394.164" - cell $and $and$ls180.v:3394$1058 + attribute \src "ls180.v:3385.48-3385.164" + cell $and $and$ls180.v:3385$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3394$1056_Y - connect \B $eq$ls180.v:3394$1057_Y - connect \Y $and$ls180.v:3394$1058_Y + connect \A $and$ls180.v:3385$1056_Y + connect \B $eq$ls180.v:3385$1057_Y + connect \Y $and$ls180.v:3385$1058_Y end - attribute \src "ls180.v:3395.49-3395.113" - cell $and $and$ls180.v:3395$1060 + attribute \src "ls180.v:3386.49-3386.113" + cell $and $and$ls180.v:3386$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel - connect \B $not$ls180.v:3395$1059_Y - connect \Y $and$ls180.v:3395$1060_Y + connect \B $not$ls180.v:3386$1059_Y + connect \Y $and$ls180.v:3386$1060_Y end - attribute \src "ls180.v:3395.48-3395.167" - cell $and $and$ls180.v:3395$1062 + attribute \src "ls180.v:3386.48-3386.167" + cell $and $and$ls180.v:3386$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3395$1060_Y - connect \B $eq$ls180.v:3395$1061_Y - connect \Y $and$ls180.v:3395$1062_Y + connect \A $and$ls180.v:3386$1060_Y + connect \B $eq$ls180.v:3386$1061_Y + connect \Y $and$ls180.v:3386$1062_Y end - attribute \src "ls180.v:3397.49-3397.110" - cell $and $and$ls180.v:3397$1063 + attribute \src "ls180.v:3388.49-3388.110" + cell $and $and$ls180.v:3388$1063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252276,43 +252068,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B \libresocsim_interface7_bank_bus_we - connect \Y $and$ls180.v:3397$1063_Y + connect \Y $and$ls180.v:3388$1063_Y end - attribute \src "ls180.v:3397.48-3397.164" - cell $and $and$ls180.v:3397$1065 + attribute \src "ls180.v:3388.48-3388.164" + cell $and $and$ls180.v:3388$1065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3397$1063_Y - connect \B $eq$ls180.v:3397$1064_Y - connect \Y $and$ls180.v:3397$1065_Y + connect \A $and$ls180.v:3388$1063_Y + connect \B $eq$ls180.v:3388$1064_Y + connect \Y $and$ls180.v:3388$1065_Y end - attribute \src "ls180.v:3398.49-3398.113" - cell $and $and$ls180.v:3398$1067 + attribute \src "ls180.v:3389.49-3389.113" + cell $and $and$ls180.v:3389$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel - connect \B $not$ls180.v:3398$1066_Y - connect \Y $and$ls180.v:3398$1067_Y + connect \B $not$ls180.v:3389$1066_Y + connect \Y $and$ls180.v:3389$1067_Y end - attribute \src "ls180.v:3398.48-3398.167" - cell $and $and$ls180.v:3398$1069 + attribute \src "ls180.v:3389.48-3389.167" + cell $and $and$ls180.v:3389$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3398$1067_Y - connect \B $eq$ls180.v:3398$1068_Y - connect \Y $and$ls180.v:3398$1069_Y + connect \A $and$ls180.v:3389$1067_Y + connect \B $eq$ls180.v:3389$1068_Y + connect \Y $and$ls180.v:3389$1069_Y end - attribute \src "ls180.v:3400.49-3400.110" - cell $and $and$ls180.v:3400$1070 + attribute \src "ls180.v:3391.49-3391.110" + cell $and $and$ls180.v:3391$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252320,263 +252112,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B \libresocsim_interface7_bank_bus_we - connect \Y $and$ls180.v:3400$1070_Y + connect \Y $and$ls180.v:3391$1070_Y end - attribute \src "ls180.v:3400.48-3400.164" - cell $and $and$ls180.v:3400$1072 + attribute \src "ls180.v:3391.48-3391.164" + cell $and $and$ls180.v:3391$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3400$1070_Y - connect \B $eq$ls180.v:3400$1071_Y - connect \Y $and$ls180.v:3400$1072_Y + connect \A $and$ls180.v:3391$1070_Y + connect \B $eq$ls180.v:3391$1071_Y + connect \Y $and$ls180.v:3391$1072_Y end - attribute \src "ls180.v:3401.49-3401.113" - cell $and $and$ls180.v:3401$1074 + attribute \src "ls180.v:3392.49-3392.113" + cell $and $and$ls180.v:3392$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel - connect \B $not$ls180.v:3401$1073_Y - connect \Y $and$ls180.v:3401$1074_Y + connect \B $not$ls180.v:3392$1073_Y + connect \Y $and$ls180.v:3392$1074_Y end - attribute \src "ls180.v:3401.48-3401.167" - cell $and $and$ls180.v:3401$1076 + attribute \src "ls180.v:3392.48-3392.167" + cell $and $and$ls180.v:3392$1076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3401$1074_Y - connect \B $eq$ls180.v:3401$1075_Y - connect \Y $and$ls180.v:3401$1076_Y + connect \A $and$ls180.v:3392$1074_Y + connect \B $eq$ls180.v:3392$1075_Y + connect \Y $and$ls180.v:3392$1076_Y end - attribute \src "ls180.v:3761.96-3761.165" - cell $and $and$ls180.v:3761$1107 + attribute \src "ls180.v:3752.96-3752.165" + cell $and $and$ls180.v:3752$1107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock - connect \B $eq$ls180.v:3761$1106_Y - connect \Y $and$ls180.v:3761$1107_Y + connect \B $eq$ls180.v:3752$1106_Y + connect \Y $and$ls180.v:3752$1107_Y end - attribute \src "ls180.v:3761.171-3761.240" - cell $and $and$ls180.v:3761$1110 + attribute \src "ls180.v:3752.171-3752.240" + cell $and $and$ls180.v:3752$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock - connect \B $eq$ls180.v:3761$1109_Y - connect \Y $and$ls180.v:3761$1110_Y + connect \B $eq$ls180.v:3752$1109_Y + connect \Y $and$ls180.v:3752$1110_Y end - attribute \src "ls180.v:3761.246-3761.315" - cell $and $and$ls180.v:3761$1113 + attribute \src "ls180.v:3752.246-3752.315" + cell $and $and$ls180.v:3752$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock - connect \B $eq$ls180.v:3761$1112_Y - connect \Y $and$ls180.v:3761$1113_Y + connect \B $eq$ls180.v:3752$1112_Y + connect \Y $and$ls180.v:3752$1113_Y end - attribute \src "ls180.v:3761.27-3761.318" - cell $and $and$ls180.v:3761$1116 + attribute \src "ls180.v:3752.27-3752.318" + cell $and $and$ls180.v:3752$1116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3761$1105_Y - connect \B $not$ls180.v:3761$1115_Y - connect \Y $and$ls180.v:3761$1116_Y + connect \A $eq$ls180.v:3752$1105_Y + connect \B $not$ls180.v:3752$1115_Y + connect \Y $and$ls180.v:3752$1116_Y end - attribute \src "ls180.v:3761.26-3761.336" - cell $and $and$ls180.v:3761$1117 + attribute \src "ls180.v:3752.26-3752.336" + cell $and $and$ls180.v:3752$1117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3761$1116_Y + connect \A $and$ls180.v:3752$1116_Y connect \B \port_cmd_valid - connect \Y $and$ls180.v:3761$1117_Y + connect \Y $and$ls180.v:3752$1117_Y end - attribute \src "ls180.v:3785.96-3785.165" - cell $and $and$ls180.v:3785$1123 + attribute \src "ls180.v:3776.96-3776.165" + cell $and $and$ls180.v:3776$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock - connect \B $eq$ls180.v:3785$1122_Y - connect \Y $and$ls180.v:3785$1123_Y + connect \B $eq$ls180.v:3776$1122_Y + connect \Y $and$ls180.v:3776$1123_Y end - attribute \src "ls180.v:3785.171-3785.240" - cell $and $and$ls180.v:3785$1126 + attribute \src "ls180.v:3776.171-3776.240" + cell $and $and$ls180.v:3776$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock - connect \B $eq$ls180.v:3785$1125_Y - connect \Y $and$ls180.v:3785$1126_Y + connect \B $eq$ls180.v:3776$1125_Y + connect \Y $and$ls180.v:3776$1126_Y end - attribute \src "ls180.v:3785.246-3785.315" - cell $and $and$ls180.v:3785$1129 + attribute \src "ls180.v:3776.246-3776.315" + cell $and $and$ls180.v:3776$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock - connect \B $eq$ls180.v:3785$1128_Y - connect \Y $and$ls180.v:3785$1129_Y + connect \B $eq$ls180.v:3776$1128_Y + connect \Y $and$ls180.v:3776$1129_Y end - attribute \src "ls180.v:3785.27-3785.318" - cell $and $and$ls180.v:3785$1132 + attribute \src "ls180.v:3776.27-3776.318" + cell $and $and$ls180.v:3776$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3785$1121_Y - connect \B $not$ls180.v:3785$1131_Y - connect \Y $and$ls180.v:3785$1132_Y + connect \A $eq$ls180.v:3776$1121_Y + connect \B $not$ls180.v:3776$1131_Y + connect \Y $and$ls180.v:3776$1132_Y end - attribute \src "ls180.v:3785.26-3785.336" - cell $and $and$ls180.v:3785$1133 + attribute \src "ls180.v:3776.26-3776.336" + cell $and $and$ls180.v:3776$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3785$1132_Y + connect \A $and$ls180.v:3776$1132_Y connect \B \port_cmd_valid - connect \Y $and$ls180.v:3785$1133_Y + connect \Y $and$ls180.v:3776$1133_Y end - attribute \src "ls180.v:3809.96-3809.165" - cell $and $and$ls180.v:3809$1139 + attribute \src "ls180.v:3800.96-3800.165" + cell $and $and$ls180.v:3800$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock - connect \B $eq$ls180.v:3809$1138_Y - connect \Y $and$ls180.v:3809$1139_Y + connect \B $eq$ls180.v:3800$1138_Y + connect \Y $and$ls180.v:3800$1139_Y end - attribute \src "ls180.v:3809.171-3809.240" - cell $and $and$ls180.v:3809$1142 + attribute \src "ls180.v:3800.171-3800.240" + cell $and $and$ls180.v:3800$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock - connect \B $eq$ls180.v:3809$1141_Y - connect \Y $and$ls180.v:3809$1142_Y + connect \B $eq$ls180.v:3800$1141_Y + connect \Y $and$ls180.v:3800$1142_Y end - attribute \src "ls180.v:3809.246-3809.315" - cell $and $and$ls180.v:3809$1145 + attribute \src "ls180.v:3800.246-3800.315" + cell $and $and$ls180.v:3800$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock - connect \B $eq$ls180.v:3809$1144_Y - connect \Y $and$ls180.v:3809$1145_Y + connect \B $eq$ls180.v:3800$1144_Y + connect \Y $and$ls180.v:3800$1145_Y end - attribute \src "ls180.v:3809.27-3809.318" - cell $and $and$ls180.v:3809$1148 + attribute \src "ls180.v:3800.27-3800.318" + cell $and $and$ls180.v:3800$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3809$1137_Y - connect \B $not$ls180.v:3809$1147_Y - connect \Y $and$ls180.v:3809$1148_Y + connect \A $eq$ls180.v:3800$1137_Y + connect \B $not$ls180.v:3800$1147_Y + connect \Y $and$ls180.v:3800$1148_Y end - attribute \src "ls180.v:3809.26-3809.336" - cell $and $and$ls180.v:3809$1149 + attribute \src "ls180.v:3800.26-3800.336" + cell $and $and$ls180.v:3800$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3809$1148_Y + connect \A $and$ls180.v:3800$1148_Y connect \B \port_cmd_valid - connect \Y $and$ls180.v:3809$1149_Y + connect \Y $and$ls180.v:3800$1149_Y end - attribute \src "ls180.v:3833.96-3833.165" - cell $and $and$ls180.v:3833$1155 + attribute \src "ls180.v:3824.96-3824.165" + cell $and $and$ls180.v:3824$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock - connect \B $eq$ls180.v:3833$1154_Y - connect \Y $and$ls180.v:3833$1155_Y + connect \B $eq$ls180.v:3824$1154_Y + connect \Y $and$ls180.v:3824$1155_Y end - attribute \src "ls180.v:3833.171-3833.240" - cell $and $and$ls180.v:3833$1158 + attribute \src "ls180.v:3824.171-3824.240" + cell $and $and$ls180.v:3824$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock - connect \B $eq$ls180.v:3833$1157_Y - connect \Y $and$ls180.v:3833$1158_Y + connect \B $eq$ls180.v:3824$1157_Y + connect \Y $and$ls180.v:3824$1158_Y end - attribute \src "ls180.v:3833.246-3833.315" - cell $and $and$ls180.v:3833$1161 + attribute \src "ls180.v:3824.246-3824.315" + cell $and $and$ls180.v:3824$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock - connect \B $eq$ls180.v:3833$1160_Y - connect \Y $and$ls180.v:3833$1161_Y + connect \B $eq$ls180.v:3824$1160_Y + connect \Y $and$ls180.v:3824$1161_Y end - attribute \src "ls180.v:3833.27-3833.318" - cell $and $and$ls180.v:3833$1164 + attribute \src "ls180.v:3824.27-3824.318" + cell $and $and$ls180.v:3824$1164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3833$1153_Y - connect \B $not$ls180.v:3833$1163_Y - connect \Y $and$ls180.v:3833$1164_Y + connect \A $eq$ls180.v:3824$1153_Y + connect \B $not$ls180.v:3824$1163_Y + connect \Y $and$ls180.v:3824$1164_Y end - attribute \src "ls180.v:3833.26-3833.336" - cell $and $and$ls180.v:3833$1165 + attribute \src "ls180.v:3824.26-3824.336" + cell $and $and$ls180.v:3824$1165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3833$1164_Y + connect \A $and$ls180.v:3824$1164_Y connect \B \port_cmd_valid - connect \Y $and$ls180.v:3833$1165_Y + connect \Y $and$ls180.v:3824$1165_Y end - attribute \src "ls180.v:3990.22-3990.77" - cell $and $and$ls180.v:3990$1177 + attribute \src "ls180.v:3981.22-3981.77" + cell $and $and$ls180.v:3981$1177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252584,21 +252376,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3990$1177_Y + connect \Y $and$ls180.v:3981$1177_Y end - attribute \src "ls180.v:3990.21-3990.113" - cell $and $and$ls180.v:3990$1178 + attribute \src "ls180.v:3981.21-3981.113" + cell $and $and$ls180.v:3981$1178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3990$1177_Y + connect \A $and$ls180.v:3981$1177_Y connect \B \sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:3990$1178_Y + connect \Y $and$ls180.v:3981$1178_Y end - attribute \src "ls180.v:3993.22-3993.77" - cell $and $and$ls180.v:3993$1179 + attribute \src "ls180.v:3984.22-3984.77" + cell $and $and$ls180.v:3984$1179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252606,21 +252398,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3993$1179_Y + connect \Y $and$ls180.v:3984$1179_Y end - attribute \src "ls180.v:3993.21-3993.113" - cell $and $and$ls180.v:3993$1180 + attribute \src "ls180.v:3984.21-3984.113" + cell $and $and$ls180.v:3984$1180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3993$1179_Y + connect \A $and$ls180.v:3984$1179_Y connect \B \sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:3993$1180_Y + connect \Y $and$ls180.v:3984$1180_Y end - attribute \src "ls180.v:3996.22-3996.55" - cell $and $and$ls180.v:3996$1181 + attribute \src "ls180.v:3987.22-3987.55" + cell $and $and$ls180.v:3987$1181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252628,21 +252420,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_cmd_valid connect \B \sdram_cmd_ready - connect \Y $and$ls180.v:3996$1181_Y + connect \Y $and$ls180.v:3987$1181_Y end - attribute \src "ls180.v:3996.21-3996.80" - cell $and $and$ls180.v:3996$1182 + attribute \src "ls180.v:3987.21-3987.80" + cell $and $and$ls180.v:3987$1182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3996$1181_Y + connect \A $and$ls180.v:3987$1181_Y connect \B \sdram_cmd_payload_cas - connect \Y $and$ls180.v:3996$1182_Y + connect \Y $and$ls180.v:3987$1182_Y end - attribute \src "ls180.v:4007.22-4007.77" - cell $and $and$ls180.v:4007$1184 + attribute \src "ls180.v:3998.22-3998.77" + cell $and $and$ls180.v:3998$1184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252650,21 +252442,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4007$1184_Y + connect \Y $and$ls180.v:3998$1184_Y end - attribute \src "ls180.v:4007.21-4007.113" - cell $and $and$ls180.v:4007$1185 + attribute \src "ls180.v:3998.21-3998.113" + cell $and $and$ls180.v:3998$1185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4007$1184_Y + connect \A $and$ls180.v:3998$1184_Y connect \B \sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:4007$1185_Y + connect \Y $and$ls180.v:3998$1185_Y end - attribute \src "ls180.v:4010.22-4010.77" - cell $and $and$ls180.v:4010$1186 + attribute \src "ls180.v:4001.22-4001.77" + cell $and $and$ls180.v:4001$1186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252672,21 +252464,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4010$1186_Y + connect \Y $and$ls180.v:4001$1186_Y end - attribute \src "ls180.v:4010.21-4010.113" - cell $and $and$ls180.v:4010$1187 + attribute \src "ls180.v:4001.21-4001.113" + cell $and $and$ls180.v:4001$1187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4010$1186_Y + connect \A $and$ls180.v:4001$1186_Y connect \B \sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:4010$1187_Y + connect \Y $and$ls180.v:4001$1187_Y end - attribute \src "ls180.v:4013.22-4013.55" - cell $and $and$ls180.v:4013$1188 + attribute \src "ls180.v:4004.22-4004.55" + cell $and $and$ls180.v:4004$1188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252694,21 +252486,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_cmd_valid connect \B \sdram_cmd_ready - connect \Y $and$ls180.v:4013$1188_Y + connect \Y $and$ls180.v:4004$1188_Y end - attribute \src "ls180.v:4013.21-4013.80" - cell $and $and$ls180.v:4013$1189 + attribute \src "ls180.v:4004.21-4004.80" + cell $and $and$ls180.v:4004$1189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4013$1188_Y + connect \A $and$ls180.v:4004$1188_Y connect \B \sdram_cmd_payload_ras - connect \Y $and$ls180.v:4013$1189_Y + connect \Y $and$ls180.v:4004$1189_Y end - attribute \src "ls180.v:4024.22-4024.77" - cell $and $and$ls180.v:4024$1191 + attribute \src "ls180.v:4015.22-4015.77" + cell $and $and$ls180.v:4015$1191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252716,21 +252508,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4024$1191_Y + connect \Y $and$ls180.v:4015$1191_Y end - attribute \src "ls180.v:4024.21-4024.112" - cell $and $and$ls180.v:4024$1192 + attribute \src "ls180.v:4015.21-4015.112" + cell $and $and$ls180.v:4015$1192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4024$1191_Y + connect \A $and$ls180.v:4015$1191_Y connect \B \sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:4024$1192_Y + connect \Y $and$ls180.v:4015$1192_Y end - attribute \src "ls180.v:4027.22-4027.77" - cell $and $and$ls180.v:4027$1193 + attribute \src "ls180.v:4018.22-4018.77" + cell $and $and$ls180.v:4018$1193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252738,21 +252530,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4027$1193_Y + connect \Y $and$ls180.v:4018$1193_Y end - attribute \src "ls180.v:4027.21-4027.112" - cell $and $and$ls180.v:4027$1194 + attribute \src "ls180.v:4018.21-4018.112" + cell $and $and$ls180.v:4018$1194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4027$1193_Y + connect \A $and$ls180.v:4018$1193_Y connect \B \sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:4027$1194_Y + connect \Y $and$ls180.v:4018$1194_Y end - attribute \src "ls180.v:4030.22-4030.55" - cell $and $and$ls180.v:4030$1195 + attribute \src "ls180.v:4021.22-4021.55" + cell $and $and$ls180.v:4021$1195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252760,21 +252552,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_cmd_valid connect \B \sdram_cmd_ready - connect \Y $and$ls180.v:4030$1195_Y + connect \Y $and$ls180.v:4021$1195_Y end - attribute \src "ls180.v:4030.21-4030.79" - cell $and $and$ls180.v:4030$1196 + attribute \src "ls180.v:4021.21-4021.79" + cell $and $and$ls180.v:4021$1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4030$1195_Y + connect \A $and$ls180.v:4021$1195_Y connect \B \sdram_cmd_payload_we - connect \Y $and$ls180.v:4030$1196_Y + connect \Y $and$ls180.v:4021$1196_Y end - attribute \src "ls180.v:4041.22-4041.77" - cell $and $and$ls180.v:4041$1198 + attribute \src "ls180.v:4032.22-4032.77" + cell $and $and$ls180.v:4032$1198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252782,21 +252574,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4041$1198_Y + connect \Y $and$ls180.v:4032$1198_Y end - attribute \src "ls180.v:4041.21-4041.117" - cell $and $and$ls180.v:4041$1199 + attribute \src "ls180.v:4032.21-4032.117" + cell $and $and$ls180.v:4032$1199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4041$1198_Y + connect \A $and$ls180.v:4032$1198_Y connect \B \sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:4041$1199_Y + connect \Y $and$ls180.v:4032$1199_Y end - attribute \src "ls180.v:4044.22-4044.77" - cell $and $and$ls180.v:4044$1200 + attribute \src "ls180.v:4035.22-4035.77" + cell $and $and$ls180.v:4035$1200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252804,21 +252596,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4044$1200_Y + connect \Y $and$ls180.v:4035$1200_Y end - attribute \src "ls180.v:4044.21-4044.117" - cell $and $and$ls180.v:4044$1201 + attribute \src "ls180.v:4035.21-4035.117" + cell $and $and$ls180.v:4035$1201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4044$1200_Y + connect \A $and$ls180.v:4035$1200_Y connect \B \sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:4044$1201_Y + connect \Y $and$ls180.v:4035$1201_Y end - attribute \src "ls180.v:4047.22-4047.55" - cell $and $and$ls180.v:4047$1202 + attribute \src "ls180.v:4038.22-4038.55" + cell $and $and$ls180.v:4038$1202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252826,21 +252618,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_cmd_valid connect \B \sdram_cmd_ready - connect \Y $and$ls180.v:4047$1202_Y + connect \Y $and$ls180.v:4038$1202_Y end - attribute \src "ls180.v:4047.21-4047.84" - cell $and $and$ls180.v:4047$1203 + attribute \src "ls180.v:4038.21-4038.84" + cell $and $and$ls180.v:4038$1203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4047$1202_Y + connect \A $and$ls180.v:4038$1202_Y connect \B \sdram_cmd_payload_is_read - connect \Y $and$ls180.v:4047$1203_Y + connect \Y $and$ls180.v:4038$1203_Y end - attribute \src "ls180.v:4058.22-4058.77" - cell $and $and$ls180.v:4058$1205 + attribute \src "ls180.v:4049.22-4049.77" + cell $and $and$ls180.v:4049$1205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252848,21 +252640,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4058$1205_Y + connect \Y $and$ls180.v:4049$1205_Y end - attribute \src "ls180.v:4058.21-4058.118" - cell $and $and$ls180.v:4058$1206 + attribute \src "ls180.v:4049.21-4049.118" + cell $and $and$ls180.v:4049$1206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4058$1205_Y + connect \A $and$ls180.v:4049$1205_Y connect \B \sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:4058$1206_Y + connect \Y $and$ls180.v:4049$1206_Y end - attribute \src "ls180.v:4061.22-4061.77" - cell $and $and$ls180.v:4061$1207 + attribute \src "ls180.v:4052.22-4052.77" + cell $and $and$ls180.v:4052$1207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252870,21 +252662,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4061$1207_Y + connect \Y $and$ls180.v:4052$1207_Y end - attribute \src "ls180.v:4061.21-4061.118" - cell $and $and$ls180.v:4061$1208 + attribute \src "ls180.v:4052.21-4052.118" + cell $and $and$ls180.v:4052$1208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4061$1207_Y + connect \A $and$ls180.v:4052$1207_Y connect \B \sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:4061$1208_Y + connect \Y $and$ls180.v:4052$1208_Y end - attribute \src "ls180.v:4064.22-4064.55" - cell $and $and$ls180.v:4064$1209 + attribute \src "ls180.v:4055.22-4055.55" + cell $and $and$ls180.v:4055$1209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252892,21 +252684,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_cmd_valid connect \B \sdram_cmd_ready - connect \Y $and$ls180.v:4064$1209_Y + connect \Y $and$ls180.v:4055$1209_Y end - attribute \src "ls180.v:4064.21-4064.85" - cell $and $and$ls180.v:4064$1210 + attribute \src "ls180.v:4055.21-4055.85" + cell $and $and$ls180.v:4055$1210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4064$1209_Y + connect \A $and$ls180.v:4055$1209_Y connect \B \sdram_cmd_payload_is_write - connect \Y $and$ls180.v:4064$1210_Y + connect \Y $and$ls180.v:4055$1210_Y end - attribute \src "ls180.v:4232.57-4232.97" - cell $and $and$ls180.v:4232$1213 + attribute \src "ls180.v:4223.57-4223.97" + cell $and $and$ls180.v:4223$1213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252914,10 +252706,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \dfi_p0_wrdata_en connect \B \dfi_p0_wrdata_mask [0] - connect \Y $and$ls180.v:4232$1213_Y + connect \Y $and$ls180.v:4223$1213_Y end - attribute \src "ls180.v:4233.57-4233.97" - cell $and $and$ls180.v:4233$1214 + attribute \src "ls180.v:4224.57-4224.97" + cell $and $and$ls180.v:4224$1214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252925,10 +252717,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \dfi_p0_wrdata_en connect \B \dfi_p0_wrdata_mask [1] - connect \Y $and$ls180.v:4233$1214_Y + connect \Y $and$ls180.v:4224$1214_Y end - attribute \src "ls180.v:4361.8-4361.57" - cell $and $and$ls180.v:4361$1257 + attribute \src "ls180.v:4356.8-4356.57" + cell $and $and$ls180.v:4356$1261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252936,32 +252728,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_cyc connect \B \libresocsim_ram_bus_stb - connect \Y $and$ls180.v:4361$1257_Y + connect \Y $and$ls180.v:4356$1261_Y end - attribute \src "ls180.v:4361.7-4361.87" - cell $and $and$ls180.v:4361$1259 + attribute \src "ls180.v:4356.7-4356.87" + cell $and $and$ls180.v:4356$1263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4361$1257_Y - connect \B $not$ls180.v:4361$1258_Y - connect \Y $and$ls180.v:4361$1259_Y + connect \A $and$ls180.v:4356$1261_Y + connect \B $not$ls180.v:4356$1262_Y + connect \Y $and$ls180.v:4356$1263_Y end - attribute \src "ls180.v:4380.7-4380.65" - cell $and $and$ls180.v:4380$1263 + attribute \src "ls180.v:4375.7-4375.65" + cell $and $and$ls180.v:4375$1267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4380$1262_Y + connect \A $not$ls180.v:4375$1266_Y connect \B \libresocsim_zero_old_trigger - connect \Y $and$ls180.v:4380$1263_Y + connect \Y $and$ls180.v:4375$1267_Y end - attribute \src "ls180.v:4384.8-4384.49" - cell $and $and$ls180.v:4384$1264 + attribute \src "ls180.v:4379.8-4379.49" + cell $and $and$ls180.v:4379$1268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252969,43 +252761,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_cyc connect \B \ram_bus_ram_bus_stb - connect \Y $and$ls180.v:4384$1264_Y + connect \Y $and$ls180.v:4379$1268_Y end - attribute \src "ls180.v:4384.7-4384.75" - cell $and $and$ls180.v:4384$1266 + attribute \src "ls180.v:4379.7-4379.75" + cell $and $and$ls180.v:4379$1270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4384$1264_Y - connect \B $not$ls180.v:4384$1265_Y - connect \Y $and$ls180.v:4384$1266_Y + connect \A $and$ls180.v:4379$1268_Y + connect \B $not$ls180.v:4379$1269_Y + connect \Y $and$ls180.v:4379$1270_Y end - attribute \src "ls180.v:4392.7-4392.46" - cell $and $and$ls180.v:4392$1268 + attribute \src "ls180.v:4387.7-4387.46" + cell $and $and$ls180.v:4387$1272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_timer_wait - connect \B $not$ls180.v:4392$1267_Y - connect \Y $and$ls180.v:4392$1268_Y + connect \B $not$ls180.v:4387$1271_Y + connect \Y $and$ls180.v:4387$1272_Y end - attribute \src "ls180.v:4420.7-4420.65" - cell $and $and$ls180.v:4420$1275 + attribute \src "ls180.v:4415.7-4415.65" + cell $and $and$ls180.v:4415$1279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_start1 - connect \B $eq$ls180.v:4420$1274_Y - connect \Y $and$ls180.v:4420$1275_Y + connect \B $eq$ls180.v:4415$1278_Y + connect \Y $and$ls180.v:4415$1279_Y end - attribute \src "ls180.v:4462.8-4462.121" - cell $and $and$ls180.v:4462$1281 + attribute \src "ls180.v:4457.8-4457.121" + cell $and $and$ls180.v:4457$1285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253013,21 +252805,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:4462$1281_Y + connect \Y $and$ls180.v:4457$1285_Y end - attribute \src "ls180.v:4462.7-4462.175" - cell $and $and$ls180.v:4462$1283 + attribute \src "ls180.v:4457.7-4457.175" + cell $and $and$ls180.v:4457$1287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4462$1281_Y - connect \B $not$ls180.v:4462$1282_Y - connect \Y $and$ls180.v:4462$1283_Y + connect \A $and$ls180.v:4457$1285_Y + connect \B $not$ls180.v:4457$1286_Y + connect \Y $and$ls180.v:4457$1287_Y end - attribute \src "ls180.v:4468.8-4468.121" - cell $and $and$ls180.v:4468$1286 + attribute \src "ls180.v:4463.8-4463.121" + cell $and $and$ls180.v:4463$1290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253035,21 +252827,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:4468$1286_Y + connect \Y $and$ls180.v:4463$1290_Y end - attribute \src "ls180.v:4468.7-4468.175" - cell $and $and$ls180.v:4468$1288 + attribute \src "ls180.v:4463.7-4463.175" + cell $and $and$ls180.v:4463$1292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4468$1286_Y - connect \B $not$ls180.v:4468$1287_Y - connect \Y $and$ls180.v:4468$1288_Y + connect \A $and$ls180.v:4463$1290_Y + connect \B $not$ls180.v:4463$1291_Y + connect \Y $and$ls180.v:4463$1292_Y end - attribute \src "ls180.v:4508.8-4508.121" - cell $and $and$ls180.v:4508$1297 + attribute \src "ls180.v:4503.8-4503.121" + cell $and $and$ls180.v:4503$1301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253057,21 +252849,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:4508$1297_Y + connect \Y $and$ls180.v:4503$1301_Y end - attribute \src "ls180.v:4508.7-4508.175" - cell $and $and$ls180.v:4508$1299 + attribute \src "ls180.v:4503.7-4503.175" + cell $and $and$ls180.v:4503$1303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4508$1297_Y - connect \B $not$ls180.v:4508$1298_Y - connect \Y $and$ls180.v:4508$1299_Y + connect \A $and$ls180.v:4503$1301_Y + connect \B $not$ls180.v:4503$1302_Y + connect \Y $and$ls180.v:4503$1303_Y end - attribute \src "ls180.v:4514.8-4514.121" - cell $and $and$ls180.v:4514$1302 + attribute \src "ls180.v:4509.8-4509.121" + cell $and $and$ls180.v:4509$1306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253079,21 +252871,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:4514$1302_Y + connect \Y $and$ls180.v:4509$1306_Y end - attribute \src "ls180.v:4514.7-4514.175" - cell $and $and$ls180.v:4514$1304 + attribute \src "ls180.v:4509.7-4509.175" + cell $and $and$ls180.v:4509$1308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4514$1302_Y - connect \B $not$ls180.v:4514$1303_Y - connect \Y $and$ls180.v:4514$1304_Y + connect \A $and$ls180.v:4509$1306_Y + connect \B $not$ls180.v:4509$1307_Y + connect \Y $and$ls180.v:4509$1308_Y end - attribute \src "ls180.v:4554.8-4554.121" - cell $and $and$ls180.v:4554$1313 + attribute \src "ls180.v:4549.8-4549.121" + cell $and $and$ls180.v:4549$1317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253101,21 +252893,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:4554$1313_Y + connect \Y $and$ls180.v:4549$1317_Y end - attribute \src "ls180.v:4554.7-4554.175" - cell $and $and$ls180.v:4554$1315 + attribute \src "ls180.v:4549.7-4549.175" + cell $and $and$ls180.v:4549$1319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4554$1313_Y - connect \B $not$ls180.v:4554$1314_Y - connect \Y $and$ls180.v:4554$1315_Y + connect \A $and$ls180.v:4549$1317_Y + connect \B $not$ls180.v:4549$1318_Y + connect \Y $and$ls180.v:4549$1319_Y end - attribute \src "ls180.v:4560.8-4560.121" - cell $and $and$ls180.v:4560$1318 + attribute \src "ls180.v:4555.8-4555.121" + cell $and $and$ls180.v:4555$1322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253123,21 +252915,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:4560$1318_Y + connect \Y $and$ls180.v:4555$1322_Y end - attribute \src "ls180.v:4560.7-4560.175" - cell $and $and$ls180.v:4560$1320 + attribute \src "ls180.v:4555.7-4555.175" + cell $and $and$ls180.v:4555$1324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4560$1318_Y - connect \B $not$ls180.v:4560$1319_Y - connect \Y $and$ls180.v:4560$1320_Y + connect \A $and$ls180.v:4555$1322_Y + connect \B $not$ls180.v:4555$1323_Y + connect \Y $and$ls180.v:4555$1324_Y end - attribute \src "ls180.v:4600.8-4600.121" - cell $and $and$ls180.v:4600$1329 + attribute \src "ls180.v:4595.8-4595.121" + cell $and $and$ls180.v:4595$1333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253145,21 +252937,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:4600$1329_Y + connect \Y $and$ls180.v:4595$1333_Y end - attribute \src "ls180.v:4600.7-4600.175" - cell $and $and$ls180.v:4600$1331 + attribute \src "ls180.v:4595.7-4595.175" + cell $and $and$ls180.v:4595$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4600$1329_Y - connect \B $not$ls180.v:4600$1330_Y - connect \Y $and$ls180.v:4600$1331_Y + connect \A $and$ls180.v:4595$1333_Y + connect \B $not$ls180.v:4595$1334_Y + connect \Y $and$ls180.v:4595$1335_Y end - attribute \src "ls180.v:4606.8-4606.121" - cell $and $and$ls180.v:4606$1334 + attribute \src "ls180.v:4601.8-4601.121" + cell $and $and$ls180.v:4601$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253167,109 +252959,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:4606$1334_Y + connect \Y $and$ls180.v:4601$1338_Y end - attribute \src "ls180.v:4606.7-4606.175" - cell $and $and$ls180.v:4606$1336 + attribute \src "ls180.v:4601.7-4601.175" + cell $and $and$ls180.v:4601$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4606$1334_Y - connect \B $not$ls180.v:4606$1335_Y - connect \Y $and$ls180.v:4606$1336_Y + connect \A $and$ls180.v:4601$1338_Y + connect \B $not$ls180.v:4601$1339_Y + connect \Y $and$ls180.v:4601$1340_Y end - attribute \src "ls180.v:4803.53-4803.129" - cell $and $and$ls180.v:4803$1361 + attribute \src "ls180.v:4798.53-4798.129" + cell $and $and$ls180.v:4798$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4803$1360_Y + connect \A $eq$ls180.v:4798$1364_Y connect \B \sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:4803$1361_Y + connect \Y $and$ls180.v:4798$1365_Y end - attribute \src "ls180.v:4803.135-4803.211" - cell $and $and$ls180.v:4803$1364 + attribute \src "ls180.v:4798.135-4798.211" + cell $and $and$ls180.v:4798$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4803$1363_Y + connect \A $eq$ls180.v:4798$1367_Y connect \B \sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:4803$1364_Y + connect \Y $and$ls180.v:4798$1368_Y end - attribute \src "ls180.v:4803.217-4803.293" - cell $and $and$ls180.v:4803$1367 + attribute \src "ls180.v:4798.217-4798.293" + cell $and $and$ls180.v:4798$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4803$1366_Y + connect \A $eq$ls180.v:4798$1370_Y connect \B \sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:4803$1367_Y + connect \Y $and$ls180.v:4798$1371_Y end - attribute \src "ls180.v:4803.299-4803.375" - cell $and $and$ls180.v:4803$1370 + attribute \src "ls180.v:4798.299-4798.375" + cell $and $and$ls180.v:4798$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4803$1369_Y + connect \A $eq$ls180.v:4798$1373_Y connect \B \sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:4803$1370_Y + connect \Y $and$ls180.v:4798$1374_Y end - attribute \src "ls180.v:4804.54-4804.130" - cell $and $and$ls180.v:4804$1373 + attribute \src "ls180.v:4799.54-4799.130" + cell $and $and$ls180.v:4799$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4804$1372_Y + connect \A $eq$ls180.v:4799$1376_Y connect \B \sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:4804$1373_Y + connect \Y $and$ls180.v:4799$1377_Y end - attribute \src "ls180.v:4804.136-4804.212" - cell $and $and$ls180.v:4804$1376 + attribute \src "ls180.v:4799.136-4799.212" + cell $and $and$ls180.v:4799$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4804$1375_Y + connect \A $eq$ls180.v:4799$1379_Y connect \B \sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:4804$1376_Y + connect \Y $and$ls180.v:4799$1380_Y end - attribute \src "ls180.v:4804.218-4804.294" - cell $and $and$ls180.v:4804$1379 + attribute \src "ls180.v:4799.218-4799.294" + cell $and $and$ls180.v:4799$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4804$1378_Y + connect \A $eq$ls180.v:4799$1382_Y connect \B \sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:4804$1379_Y + connect \Y $and$ls180.v:4799$1383_Y end - attribute \src "ls180.v:4804.300-4804.376" - cell $and $and$ls180.v:4804$1382 + attribute \src "ls180.v:4799.300-4799.376" + cell $and $and$ls180.v:4799$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4804$1381_Y + connect \A $eq$ls180.v:4799$1385_Y connect \B \sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:4804$1382_Y + connect \Y $and$ls180.v:4799$1386_Y end - attribute \src "ls180.v:4823.8-4823.39" - cell $and $and$ls180.v:4823$1385 + attribute \src "ls180.v:4818.8-4818.39" + cell $and $and$ls180.v:4818$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253277,10 +253069,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_valid connect \B \port_cmd_ready - connect \Y $and$ls180.v:4823$1385_Y + connect \Y $and$ls180.v:4818$1389_Y end - attribute \src "ls180.v:4826.8-4826.43" - cell $and $and$ls180.v:4826$1386 + attribute \src "ls180.v:4821.8-4821.43" + cell $and $and$ls180.v:4821$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253288,32 +253080,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_wdata_valid connect \B \port_wdata_ready - connect \Y $and$ls180.v:4826$1386_Y + connect \Y $and$ls180.v:4821$1390_Y end - attribute \src "ls180.v:4831.8-4831.49" - cell $and $and$ls180.v:4831$1388 + attribute \src "ls180.v:4826.8-4826.49" + cell $and $and$ls180.v:4826$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_sink_valid - connect \B $not$ls180.v:4831$1387_Y - connect \Y $and$ls180.v:4831$1388_Y + connect \B $not$ls180.v:4826$1391_Y + connect \Y $and$ls180.v:4826$1392_Y end - attribute \src "ls180.v:4831.7-4831.75" - cell $and $and$ls180.v:4831$1390 + attribute \src "ls180.v:4826.7-4826.75" + cell $and $and$ls180.v:4826$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4831$1388_Y - connect \B $not$ls180.v:4831$1389_Y - connect \Y $and$ls180.v:4831$1390_Y + connect \A $and$ls180.v:4826$1392_Y + connect \B $not$ls180.v:4826$1393_Y + connect \Y $and$ls180.v:4826$1394_Y end - attribute \src "ls180.v:4837.8-4837.49" - cell $and $and$ls180.v:4837$1391 + attribute \src "ls180.v:4832.8-4832.49" + cell $and $and$ls180.v:4832$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253321,43 +253113,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \uart_phy_uart_clk_txen connect \B \uart_phy_tx_busy - connect \Y $and$ls180.v:4837$1391_Y + connect \Y $and$ls180.v:4832$1395_Y end - attribute \src "ls180.v:4861.8-4861.38" - cell $and $and$ls180.v:4861$1398 + attribute \src "ls180.v:4856.8-4856.38" + cell $and $and$ls180.v:4856$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4861$1397_Y + connect \A $not$ls180.v:4856$1401_Y connect \B \uart_phy_rx_r - connect \Y $and$ls180.v:4861$1398_Y + connect \Y $and$ls180.v:4856$1402_Y end - attribute \src "ls180.v:4894.7-4894.37" - cell $and $and$ls180.v:4894$1404 + attribute \src "ls180.v:4889.7-4889.37" + cell $and $and$ls180.v:4889$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4894$1403_Y + connect \A $not$ls180.v:4889$1407_Y connect \B \tx_old_trigger - connect \Y $and$ls180.v:4894$1404_Y + connect \Y $and$ls180.v:4889$1408_Y end - attribute \src "ls180.v:4901.7-4901.37" - cell $and $and$ls180.v:4901$1406 + attribute \src "ls180.v:4896.7-4896.37" + cell $and $and$ls180.v:4896$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4901$1405_Y + connect \A $not$ls180.v:4896$1409_Y connect \B \rx_old_trigger - connect \Y $and$ls180.v:4901$1406_Y + connect \Y $and$ls180.v:4896$1410_Y end - attribute \src "ls180.v:4911.8-4911.55" - cell $and $and$ls180.v:4911$1407 + attribute \src "ls180.v:4906.8-4906.55" + cell $and $and$ls180.v:4906$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253365,21 +253157,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_we connect \B \tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:4911$1407_Y + connect \Y $and$ls180.v:4906$1411_Y end - attribute \src "ls180.v:4911.7-4911.77" - cell $and $and$ls180.v:4911$1409 + attribute \src "ls180.v:4906.7-4906.77" + cell $and $and$ls180.v:4906$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4911$1407_Y - connect \B $not$ls180.v:4911$1408_Y - connect \Y $and$ls180.v:4911$1409_Y + connect \A $and$ls180.v:4906$1411_Y + connect \B $not$ls180.v:4906$1412_Y + connect \Y $and$ls180.v:4906$1413_Y end - attribute \src "ls180.v:4917.8-4917.55" - cell $and $and$ls180.v:4917$1412 + attribute \src "ls180.v:4912.8-4912.55" + cell $and $and$ls180.v:4912$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253387,21 +253179,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_we connect \B \tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:4917$1412_Y + connect \Y $and$ls180.v:4912$1416_Y end - attribute \src "ls180.v:4917.7-4917.77" - cell $and $and$ls180.v:4917$1414 + attribute \src "ls180.v:4912.7-4912.77" + cell $and $and$ls180.v:4912$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4917$1412_Y - connect \B $not$ls180.v:4917$1413_Y - connect \Y $and$ls180.v:4917$1414_Y + connect \A $and$ls180.v:4912$1416_Y + connect \B $not$ls180.v:4912$1417_Y + connect \Y $and$ls180.v:4912$1418_Y end - attribute \src "ls180.v:4933.8-4933.55" - cell $and $and$ls180.v:4933$1418 + attribute \src "ls180.v:4928.8-4928.55" + cell $and $and$ls180.v:4928$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253409,21 +253201,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_we connect \B \rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:4933$1418_Y + connect \Y $and$ls180.v:4928$1422_Y end - attribute \src "ls180.v:4933.7-4933.77" - cell $and $and$ls180.v:4933$1420 + attribute \src "ls180.v:4928.7-4928.77" + cell $and $and$ls180.v:4928$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4933$1418_Y - connect \B $not$ls180.v:4933$1419_Y - connect \Y $and$ls180.v:4933$1420_Y + connect \A $and$ls180.v:4928$1422_Y + connect \B $not$ls180.v:4928$1423_Y + connect \Y $and$ls180.v:4928$1424_Y end - attribute \src "ls180.v:4939.8-4939.55" - cell $and $and$ls180.v:4939$1423 + attribute \src "ls180.v:4934.8-4934.55" + cell $and $and$ls180.v:4934$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253431,21 +253223,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_we connect \B \rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:4939$1423_Y + connect \Y $and$ls180.v:4934$1427_Y end - attribute \src "ls180.v:4939.7-4939.77" - cell $and $and$ls180.v:4939$1425 + attribute \src "ls180.v:4934.7-4934.77" + cell $and $and$ls180.v:4934$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4939$1423_Y - connect \B $not$ls180.v:4939$1424_Y - connect \Y $and$ls180.v:4939$1425_Y + connect \A $and$ls180.v:4934$1427_Y + connect \B $not$ls180.v:4934$1428_Y + connect \Y $and$ls180.v:4934$1429_Y end - attribute \src "ls180.v:1556.37-1556.91" - cell $eq $eq$ls180.v:1556$21 + attribute \src "ls180.v:1547.37-1547.91" + cell $eq $eq$ls180.v:1547$21 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253453,10 +253245,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_converted_interface_sel connect \B 1'0 - connect \Y $eq$ls180.v:1556$21_Y + connect \Y $eq$ls180.v:1547$21_Y end - attribute \src "ls180.v:1563.11-1563.49" - cell $eq $eq$ls180.v:1563$26 + attribute \src "ls180.v:1554.11-1554.49" + cell $eq $eq$ls180.v:1554$26 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253464,10 +253256,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_converter0_counter connect \B 1'1 - connect \Y $eq$ls180.v:1563$26_Y + connect \Y $eq$ls180.v:1554$26_Y end - attribute \src "ls180.v:1616.37-1616.91" - cell $eq $eq$ls180.v:1616$32 + attribute \src "ls180.v:1607.37-1607.91" + cell $eq $eq$ls180.v:1607$32 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253475,10 +253267,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_converted_interface_sel connect \B 1'0 - connect \Y $eq$ls180.v:1616$32_Y + connect \Y $eq$ls180.v:1607$32_Y end - attribute \src "ls180.v:1623.11-1623.49" - cell $eq $eq$ls180.v:1623$37 + attribute \src "ls180.v:1614.11-1614.49" + cell $eq $eq$ls180.v:1614$37 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253486,10 +253278,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_converter1_counter connect \B 1'1 - connect \Y $eq$ls180.v:1623$37_Y + connect \Y $eq$ls180.v:1614$37_Y end - attribute \src "ls180.v:1676.37-1676.91" - cell $eq $eq$ls180.v:1676$43 + attribute \src "ls180.v:1667.37-1667.91" + cell $eq $eq$ls180.v:1667$43 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253497,10 +253289,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_converted_interface_sel connect \B 1'0 - connect \Y $eq$ls180.v:1676$43_Y + connect \Y $eq$ls180.v:1667$43_Y end - attribute \src "ls180.v:1683.11-1683.49" - cell $eq $eq$ls180.v:1683$48 + attribute \src "ls180.v:1674.11-1674.49" + cell $eq $eq$ls180.v:1674$48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253508,10 +253300,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_converter2_counter connect \B 1'1 - connect \Y $eq$ls180.v:1683$48_Y + connect \Y $eq$ls180.v:1674$48_Y end - attribute \src "ls180.v:1879.29-1879.55" - cell $eq $eq$ls180.v:1879$89 + attribute \src "ls180.v:1870.29-1870.55" + cell $eq $eq$ls180.v:1870$89 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -253519,10 +253311,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_timer_count1 connect \B 1'0 - connect \Y $eq$ls180.v:1879$89_Y + connect \Y $eq$ls180.v:1870$89_Y end - attribute \src "ls180.v:1883.58-1883.87" - cell $eq $eq$ls180.v:1883$92 + attribute \src "ls180.v:1874.58-1874.87" + cell $eq $eq$ls180.v:1874$92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253530,10 +253322,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_count connect \B 1'0 - connect \Y $eq$ls180.v:1883$92_Y + connect \Y $eq$ls180.v:1874$92_Y end - attribute \src "ls180.v:1927.38-1927.119" - cell $eq $eq$ls180.v:1927$97 + attribute \src "ls180.v:1918.38-1918.119" + cell $eq $eq$ls180.v:1918$97 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -253541,10 +253333,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_row connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:1927$97_Y + connect \Y $eq$ls180.v:1918$97_Y end - attribute \src "ls180.v:1944.42-1944.78" - cell $eq $eq$ls180.v:1944$110 + attribute \src "ls180.v:1935.42-1935.78" + cell $eq $eq$ls180.v:1935$110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253552,10 +253344,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_row_close connect \B 1'0 - connect \Y $eq$ls180.v:1944$110_Y + connect \Y $eq$ls180.v:1935$110_Y end - attribute \src "ls180.v:2084.38-2084.119" - cell $eq $eq$ls180.v:2084$127 + attribute \src "ls180.v:2075.38-2075.119" + cell $eq $eq$ls180.v:2075$127 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -253563,10 +253355,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_row connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:2084$127_Y + connect \Y $eq$ls180.v:2075$127_Y end - attribute \src "ls180.v:2101.42-2101.78" - cell $eq $eq$ls180.v:2101$140 + attribute \src "ls180.v:2092.42-2092.78" + cell $eq $eq$ls180.v:2092$140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253574,10 +253366,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_row_close connect \B 1'0 - connect \Y $eq$ls180.v:2101$140_Y + connect \Y $eq$ls180.v:2092$140_Y end - attribute \src "ls180.v:2241.38-2241.119" - cell $eq $eq$ls180.v:2241$157 + attribute \src "ls180.v:2232.38-2232.119" + cell $eq $eq$ls180.v:2232$157 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -253585,10 +253377,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_row connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:2241$157_Y + connect \Y $eq$ls180.v:2232$157_Y end - attribute \src "ls180.v:2258.42-2258.78" - cell $eq $eq$ls180.v:2258$170 + attribute \src "ls180.v:2249.42-2249.78" + cell $eq $eq$ls180.v:2249$170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253596,10 +253388,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_row_close connect \B 1'0 - connect \Y $eq$ls180.v:2258$170_Y + connect \Y $eq$ls180.v:2249$170_Y end - attribute \src "ls180.v:2398.38-2398.119" - cell $eq $eq$ls180.v:2398$187 + attribute \src "ls180.v:2389.38-2389.119" + cell $eq $eq$ls180.v:2389$187 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -253607,10 +253399,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_row connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:2398$187_Y + connect \Y $eq$ls180.v:2389$187_Y end - attribute \src "ls180.v:2415.42-2415.78" - cell $eq $eq$ls180.v:2415$200 + attribute \src "ls180.v:2406.42-2406.78" + cell $eq $eq$ls180.v:2406$200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253618,10 +253410,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_row_close connect \B 1'0 - connect \Y $eq$ls180.v:2415$200_Y + connect \Y $eq$ls180.v:2406$200_Y end - attribute \src "ls180.v:2552.27-2552.46" - cell $eq $eq$ls180.v:2552$247 + attribute \src "ls180.v:2543.27-2543.46" + cell $eq $eq$ls180.v:2543$247 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253629,10 +253421,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_time0 connect \B 1'0 - connect \Y $eq$ls180.v:2552$247_Y + connect \Y $eq$ls180.v:2543$247_Y end - attribute \src "ls180.v:2553.27-2553.46" - cell $eq $eq$ls180.v:2553$248 + attribute \src "ls180.v:2544.27-2544.46" + cell $eq $eq$ls180.v:2544$248 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253640,10 +253432,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_time1 connect \B 1'0 - connect \Y $eq$ls180.v:2553$248_Y + connect \Y $eq$ls180.v:2544$248_Y end - attribute \src "ls180.v:2564.299-2564.368" - cell $eq $eq$ls180.v:2564$262 + attribute \src "ls180.v:2555.299-2555.368" + cell $eq $eq$ls180.v:2555$262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253651,10 +253443,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_read connect \B \sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:2564$262_Y + connect \Y $eq$ls180.v:2555$262_Y end - attribute \src "ls180.v:2564.373-2564.444" - cell $eq $eq$ls180.v:2564$263 + attribute \src "ls180.v:2555.373-2555.444" + cell $eq $eq$ls180.v:2555$263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253662,10 +253454,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_write connect \B \sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:2564$263_Y + connect \Y $eq$ls180.v:2555$263_Y end - attribute \src "ls180.v:2565.299-2565.368" - cell $eq $eq$ls180.v:2565$275 + attribute \src "ls180.v:2556.299-2556.368" + cell $eq $eq$ls180.v:2556$275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253673,10 +253465,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_read connect \B \sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:2565$275_Y + connect \Y $eq$ls180.v:2556$275_Y end - attribute \src "ls180.v:2565.373-2565.444" - cell $eq $eq$ls180.v:2565$276 + attribute \src "ls180.v:2556.373-2556.444" + cell $eq $eq$ls180.v:2556$276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253684,10 +253476,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_write connect \B \sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:2565$276_Y + connect \Y $eq$ls180.v:2556$276_Y end - attribute \src "ls180.v:2566.299-2566.368" - cell $eq $eq$ls180.v:2566$288 + attribute \src "ls180.v:2557.299-2557.368" + cell $eq $eq$ls180.v:2557$288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253695,10 +253487,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_read connect \B \sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:2566$288_Y + connect \Y $eq$ls180.v:2557$288_Y end - attribute \src "ls180.v:2566.373-2566.444" - cell $eq $eq$ls180.v:2566$289 + attribute \src "ls180.v:2557.373-2557.444" + cell $eq $eq$ls180.v:2557$289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253706,10 +253498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_write connect \B \sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:2566$289_Y + connect \Y $eq$ls180.v:2557$289_Y end - attribute \src "ls180.v:2567.299-2567.368" - cell $eq $eq$ls180.v:2567$301 + attribute \src "ls180.v:2558.299-2558.368" + cell $eq $eq$ls180.v:2558$301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253717,10 +253509,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_read connect \B \sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:2567$301_Y + connect \Y $eq$ls180.v:2558$301_Y end - attribute \src "ls180.v:2567.373-2567.444" - cell $eq $eq$ls180.v:2567$302 + attribute \src "ls180.v:2558.373-2558.444" + cell $eq $eq$ls180.v:2558$302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253728,10 +253520,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_write connect \B \sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:2567$302_Y + connect \Y $eq$ls180.v:2558$302_Y end - attribute \src "ls180.v:2597.299-2597.368" - cell $eq $eq$ls180.v:2597$320 + attribute \src "ls180.v:2588.299-2588.368" + cell $eq $eq$ls180.v:2588$320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253739,10 +253531,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_read connect \B \sdram_choose_req_want_reads - connect \Y $eq$ls180.v:2597$320_Y + connect \Y $eq$ls180.v:2588$320_Y end - attribute \src "ls180.v:2597.373-2597.444" - cell $eq $eq$ls180.v:2597$321 + attribute \src "ls180.v:2588.373-2588.444" + cell $eq $eq$ls180.v:2588$321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253750,10 +253542,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_write connect \B \sdram_choose_req_want_writes - connect \Y $eq$ls180.v:2597$321_Y + connect \Y $eq$ls180.v:2588$321_Y end - attribute \src "ls180.v:2598.299-2598.368" - cell $eq $eq$ls180.v:2598$333 + attribute \src "ls180.v:2589.299-2589.368" + cell $eq $eq$ls180.v:2589$333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253761,10 +253553,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_read connect \B \sdram_choose_req_want_reads - connect \Y $eq$ls180.v:2598$333_Y + connect \Y $eq$ls180.v:2589$333_Y end - attribute \src "ls180.v:2598.373-2598.444" - cell $eq $eq$ls180.v:2598$334 + attribute \src "ls180.v:2589.373-2589.444" + cell $eq $eq$ls180.v:2589$334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253772,10 +253564,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_write connect \B \sdram_choose_req_want_writes - connect \Y $eq$ls180.v:2598$334_Y + connect \Y $eq$ls180.v:2589$334_Y end - attribute \src "ls180.v:2599.299-2599.368" - cell $eq $eq$ls180.v:2599$346 + attribute \src "ls180.v:2590.299-2590.368" + cell $eq $eq$ls180.v:2590$346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253783,10 +253575,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_read connect \B \sdram_choose_req_want_reads - connect \Y $eq$ls180.v:2599$346_Y + connect \Y $eq$ls180.v:2590$346_Y end - attribute \src "ls180.v:2599.373-2599.444" - cell $eq $eq$ls180.v:2599$347 + attribute \src "ls180.v:2590.373-2590.444" + cell $eq $eq$ls180.v:2590$347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253794,10 +253586,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_write connect \B \sdram_choose_req_want_writes - connect \Y $eq$ls180.v:2599$347_Y + connect \Y $eq$ls180.v:2590$347_Y end - attribute \src "ls180.v:2600.299-2600.368" - cell $eq $eq$ls180.v:2600$359 + attribute \src "ls180.v:2591.299-2591.368" + cell $eq $eq$ls180.v:2591$359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253805,10 +253597,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_read connect \B \sdram_choose_req_want_reads - connect \Y $eq$ls180.v:2600$359_Y + connect \Y $eq$ls180.v:2591$359_Y end - attribute \src "ls180.v:2600.373-2600.444" - cell $eq $eq$ls180.v:2600$360 + attribute \src "ls180.v:2591.373-2591.444" + cell $eq $eq$ls180.v:2591$360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253816,10 +253608,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_write connect \B \sdram_choose_req_want_writes - connect \Y $eq$ls180.v:2600$360_Y + connect \Y $eq$ls180.v:2591$360_Y end - attribute \src "ls180.v:2629.68-2629.98" - cell $eq $eq$ls180.v:2629$369 + attribute \src "ls180.v:2620.68-2620.98" + cell $eq $eq$ls180.v:2620$369 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253827,10 +253619,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_grant connect \B 1'0 - connect \Y $eq$ls180.v:2629$369_Y + connect \Y $eq$ls180.v:2620$369_Y end - attribute \src "ls180.v:2632.68-2632.98" - cell $eq $eq$ls180.v:2632$372 + attribute \src "ls180.v:2623.68-2623.98" + cell $eq $eq$ls180.v:2623$372 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253838,10 +253630,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_grant connect \B 1'0 - connect \Y $eq$ls180.v:2632$372_Y + connect \Y $eq$ls180.v:2623$372_Y end - attribute \src "ls180.v:2638.68-2638.98" - cell $eq $eq$ls180.v:2638$376 + attribute \src "ls180.v:2629.68-2629.98" + cell $eq $eq$ls180.v:2629$376 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253849,10 +253641,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_grant connect \B 1'1 - connect \Y $eq$ls180.v:2638$376_Y + connect \Y $eq$ls180.v:2629$376_Y end - attribute \src "ls180.v:2641.68-2641.98" - cell $eq $eq$ls180.v:2641$379 + attribute \src "ls180.v:2632.68-2632.98" + cell $eq $eq$ls180.v:2632$379 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253860,10 +253652,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_grant connect \B 1'1 - connect \Y $eq$ls180.v:2641$379_Y + connect \Y $eq$ls180.v:2632$379_Y end - attribute \src "ls180.v:2647.68-2647.98" - cell $eq $eq$ls180.v:2647$383 + attribute \src "ls180.v:2638.68-2638.98" + cell $eq $eq$ls180.v:2638$383 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253871,10 +253663,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_grant connect \B 2'10 - connect \Y $eq$ls180.v:2647$383_Y + connect \Y $eq$ls180.v:2638$383_Y end - attribute \src "ls180.v:2650.68-2650.98" - cell $eq $eq$ls180.v:2650$386 + attribute \src "ls180.v:2641.68-2641.98" + cell $eq $eq$ls180.v:2641$386 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253882,10 +253674,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_grant connect \B 2'10 - connect \Y $eq$ls180.v:2650$386_Y + connect \Y $eq$ls180.v:2641$386_Y end - attribute \src "ls180.v:2656.68-2656.98" - cell $eq $eq$ls180.v:2656$390 + attribute \src "ls180.v:2647.68-2647.98" + cell $eq $eq$ls180.v:2647$390 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253893,10 +253685,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_grant connect \B 2'11 - connect \Y $eq$ls180.v:2656$390_Y + connect \Y $eq$ls180.v:2647$390_Y end - attribute \src "ls180.v:2659.68-2659.98" - cell $eq $eq$ls180.v:2659$393 + attribute \src "ls180.v:2650.68-2650.98" + cell $eq $eq$ls180.v:2650$393 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253904,10 +253696,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_grant connect \B 2'11 - connect \Y $eq$ls180.v:2659$393_Y + connect \Y $eq$ls180.v:2650$393_Y end - attribute \src "ls180.v:2740.47-2740.82" - cell $eq $eq$ls180.v:2740$416 + attribute \src "ls180.v:2731.47-2731.82" + cell $eq $eq$ls180.v:2731$416 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253915,10 +253707,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:2740$416_Y + connect \Y $eq$ls180.v:2731$416_Y end - attribute \src "ls180.v:2740.145-2740.183" - cell $eq $eq$ls180.v:2740$417 + attribute \src "ls180.v:2731.145-2731.183" + cell $eq $eq$ls180.v:2731$417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253926,10 +253718,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:2740$417_Y + connect \Y $eq$ls180.v:2731$417_Y end - attribute \src "ls180.v:2740.220-2740.258" - cell $eq $eq$ls180.v:2740$420 + attribute \src "ls180.v:2731.220-2731.258" + cell $eq $eq$ls180.v:2731$420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253937,10 +253729,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:2740$420_Y + connect \Y $eq$ls180.v:2731$420_Y end - attribute \src "ls180.v:2740.295-2740.333" - cell $eq $eq$ls180.v:2740$423 + attribute \src "ls180.v:2731.295-2731.333" + cell $eq $eq$ls180.v:2731$423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253948,10 +253740,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:2740$423_Y + connect \Y $eq$ls180.v:2731$423_Y end - attribute \src "ls180.v:2745.47-2745.82" - cell $eq $eq$ls180.v:2745$432 + attribute \src "ls180.v:2736.47-2736.82" + cell $eq $eq$ls180.v:2736$432 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253959,10 +253751,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:2745$432_Y + connect \Y $eq$ls180.v:2736$432_Y end - attribute \src "ls180.v:2745.145-2745.183" - cell $eq $eq$ls180.v:2745$433 + attribute \src "ls180.v:2736.145-2736.183" + cell $eq $eq$ls180.v:2736$433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253970,10 +253762,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:2745$433_Y + connect \Y $eq$ls180.v:2736$433_Y end - attribute \src "ls180.v:2745.220-2745.258" - cell $eq $eq$ls180.v:2745$436 + attribute \src "ls180.v:2736.220-2736.258" + cell $eq $eq$ls180.v:2736$436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253981,10 +253773,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:2745$436_Y + connect \Y $eq$ls180.v:2736$436_Y end - attribute \src "ls180.v:2745.295-2745.333" - cell $eq $eq$ls180.v:2745$439 + attribute \src "ls180.v:2736.295-2736.333" + cell $eq $eq$ls180.v:2736$439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253992,10 +253784,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:2745$439_Y + connect \Y $eq$ls180.v:2736$439_Y end - attribute \src "ls180.v:2750.47-2750.82" - cell $eq $eq$ls180.v:2750$448 + attribute \src "ls180.v:2741.47-2741.82" + cell $eq $eq$ls180.v:2741$448 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254003,10 +253795,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:2750$448_Y + connect \Y $eq$ls180.v:2741$448_Y end - attribute \src "ls180.v:2750.145-2750.183" - cell $eq $eq$ls180.v:2750$449 + attribute \src "ls180.v:2741.145-2741.183" + cell $eq $eq$ls180.v:2741$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254014,10 +253806,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:2750$449_Y + connect \Y $eq$ls180.v:2741$449_Y end - attribute \src "ls180.v:2750.220-2750.258" - cell $eq $eq$ls180.v:2750$452 + attribute \src "ls180.v:2741.220-2741.258" + cell $eq $eq$ls180.v:2741$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254025,10 +253817,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:2750$452_Y + connect \Y $eq$ls180.v:2741$452_Y end - attribute \src "ls180.v:2750.295-2750.333" - cell $eq $eq$ls180.v:2750$455 + attribute \src "ls180.v:2741.295-2741.333" + cell $eq $eq$ls180.v:2741$455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254036,10 +253828,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:2750$455_Y + connect \Y $eq$ls180.v:2741$455_Y end - attribute \src "ls180.v:2755.47-2755.82" - cell $eq $eq$ls180.v:2755$464 + attribute \src "ls180.v:2746.47-2746.82" + cell $eq $eq$ls180.v:2746$464 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254047,10 +253839,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:2755$464_Y + connect \Y $eq$ls180.v:2746$464_Y end - attribute \src "ls180.v:2755.145-2755.183" - cell $eq $eq$ls180.v:2755$465 + attribute \src "ls180.v:2746.145-2746.183" + cell $eq $eq$ls180.v:2746$465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254058,10 +253850,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:2755$465_Y + connect \Y $eq$ls180.v:2746$465_Y end - attribute \src "ls180.v:2755.220-2755.258" - cell $eq $eq$ls180.v:2755$468 + attribute \src "ls180.v:2746.220-2746.258" + cell $eq $eq$ls180.v:2746$468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254069,10 +253861,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:2755$468_Y + connect \Y $eq$ls180.v:2746$468_Y end - attribute \src "ls180.v:2755.295-2755.333" - cell $eq $eq$ls180.v:2755$471 + attribute \src "ls180.v:2746.295-2746.333" + cell $eq $eq$ls180.v:2746$471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254080,10 +253872,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:2755$471_Y + connect \Y $eq$ls180.v:2746$471_Y end - attribute \src "ls180.v:2760.39-2760.77" - cell $eq $eq$ls180.v:2760$480 + attribute \src "ls180.v:2751.39-2751.77" + cell $eq $eq$ls180.v:2751$480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254091,10 +253883,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$480_Y + connect \Y $eq$ls180.v:2751$480_Y end - attribute \src "ls180.v:2760.83-2760.118" - cell $eq $eq$ls180.v:2760$481 + attribute \src "ls180.v:2751.83-2751.118" + cell $eq $eq$ls180.v:2751$481 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254102,10 +253894,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:2760$481_Y + connect \Y $eq$ls180.v:2751$481_Y end - attribute \src "ls180.v:2760.181-2760.219" - cell $eq $eq$ls180.v:2760$482 + attribute \src "ls180.v:2751.181-2751.219" + cell $eq $eq$ls180.v:2751$482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254113,10 +253905,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$482_Y + connect \Y $eq$ls180.v:2751$482_Y end - attribute \src "ls180.v:2760.256-2760.294" - cell $eq $eq$ls180.v:2760$485 + attribute \src "ls180.v:2751.256-2751.294" + cell $eq $eq$ls180.v:2751$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254124,10 +253916,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$485_Y + connect \Y $eq$ls180.v:2751$485_Y end - attribute \src "ls180.v:2760.331-2760.369" - cell $eq $eq$ls180.v:2760$488 + attribute \src "ls180.v:2751.331-2751.369" + cell $eq $eq$ls180.v:2751$488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254135,10 +253927,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$488_Y + connect \Y $eq$ls180.v:2751$488_Y end - attribute \src "ls180.v:2760.413-2760.451" - cell $eq $eq$ls180.v:2760$496 + attribute \src "ls180.v:2751.413-2751.451" + cell $eq $eq$ls180.v:2751$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254146,10 +253938,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$496_Y + connect \Y $eq$ls180.v:2751$496_Y end - attribute \src "ls180.v:2760.457-2760.492" - cell $eq $eq$ls180.v:2760$497 + attribute \src "ls180.v:2751.457-2751.492" + cell $eq $eq$ls180.v:2751$497 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254157,10 +253949,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:2760$497_Y + connect \Y $eq$ls180.v:2751$497_Y end - attribute \src "ls180.v:2760.555-2760.593" - cell $eq $eq$ls180.v:2760$498 + attribute \src "ls180.v:2751.555-2751.593" + cell $eq $eq$ls180.v:2751$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254168,10 +253960,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$498_Y + connect \Y $eq$ls180.v:2751$498_Y end - attribute \src "ls180.v:2760.630-2760.668" - cell $eq $eq$ls180.v:2760$501 + attribute \src "ls180.v:2751.630-2751.668" + cell $eq $eq$ls180.v:2751$501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254179,10 +253971,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$501_Y + connect \Y $eq$ls180.v:2751$501_Y end - attribute \src "ls180.v:2760.705-2760.743" - cell $eq $eq$ls180.v:2760$504 + attribute \src "ls180.v:2751.705-2751.743" + cell $eq $eq$ls180.v:2751$504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254190,10 +253982,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$504_Y + connect \Y $eq$ls180.v:2751$504_Y end - attribute \src "ls180.v:2760.787-2760.825" - cell $eq $eq$ls180.v:2760$512 + attribute \src "ls180.v:2751.787-2751.825" + cell $eq $eq$ls180.v:2751$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254201,10 +253993,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$512_Y + connect \Y $eq$ls180.v:2751$512_Y end - attribute \src "ls180.v:2760.831-2760.866" - cell $eq $eq$ls180.v:2760$513 + attribute \src "ls180.v:2751.831-2751.866" + cell $eq $eq$ls180.v:2751$513 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254212,10 +254004,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:2760$513_Y + connect \Y $eq$ls180.v:2751$513_Y end - attribute \src "ls180.v:2760.929-2760.967" - cell $eq $eq$ls180.v:2760$514 + attribute \src "ls180.v:2751.929-2751.967" + cell $eq $eq$ls180.v:2751$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254223,10 +254015,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$514_Y + connect \Y $eq$ls180.v:2751$514_Y end - attribute \src "ls180.v:2760.1004-2760.1042" - cell $eq $eq$ls180.v:2760$517 + attribute \src "ls180.v:2751.1004-2751.1042" + cell $eq $eq$ls180.v:2751$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254234,10 +254026,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$517_Y + connect \Y $eq$ls180.v:2751$517_Y end - attribute \src "ls180.v:2760.1079-2760.1117" - cell $eq $eq$ls180.v:2760$520 + attribute \src "ls180.v:2751.1079-2751.1117" + cell $eq $eq$ls180.v:2751$520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254245,10 +254037,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$520_Y + connect \Y $eq$ls180.v:2751$520_Y end - attribute \src "ls180.v:2760.1161-2760.1199" - cell $eq $eq$ls180.v:2760$528 + attribute \src "ls180.v:2751.1161-2751.1199" + cell $eq $eq$ls180.v:2751$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254256,10 +254048,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$528_Y + connect \Y $eq$ls180.v:2751$528_Y end - attribute \src "ls180.v:2760.1205-2760.1240" - cell $eq $eq$ls180.v:2760$529 + attribute \src "ls180.v:2751.1205-2751.1240" + cell $eq $eq$ls180.v:2751$529 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254267,10 +254059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:2760$529_Y + connect \Y $eq$ls180.v:2751$529_Y end - attribute \src "ls180.v:2760.1303-2760.1341" - cell $eq $eq$ls180.v:2760$530 + attribute \src "ls180.v:2751.1303-2751.1341" + cell $eq $eq$ls180.v:2751$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254278,10 +254070,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$530_Y + connect \Y $eq$ls180.v:2751$530_Y end - attribute \src "ls180.v:2760.1378-2760.1416" - cell $eq $eq$ls180.v:2760$533 + attribute \src "ls180.v:2751.1378-2751.1416" + cell $eq $eq$ls180.v:2751$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254289,10 +254081,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$533_Y + connect \Y $eq$ls180.v:2751$533_Y end - attribute \src "ls180.v:2760.1453-2760.1491" - cell $eq $eq$ls180.v:2760$536 + attribute \src "ls180.v:2751.1453-2751.1491" + cell $eq $eq$ls180.v:2751$536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254300,10 +254092,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:2760$536_Y + connect \Y $eq$ls180.v:2751$536_Y end - attribute \src "ls180.v:2819.24-2819.47" - cell $eq $eq$ls180.v:2819$549 + attribute \src "ls180.v:2810.24-2810.47" + cell $eq $eq$ls180.v:2810$549 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254311,10 +254103,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \litedram_wb_sel connect \B 1'0 - connect \Y $eq$ls180.v:2819$549_Y + connect \Y $eq$ls180.v:2810$549_Y end - attribute \src "ls180.v:2826.11-2826.36" - cell $eq $eq$ls180.v:2826$554 + attribute \src "ls180.v:2817.11-2817.36" + cell $eq $eq$ls180.v:2817$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254322,10 +254114,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \converter_counter connect \B 1'1 - connect \Y $eq$ls180.v:2826$554_Y + connect \Y $eq$ls180.v:2817$554_Y end - attribute \src "ls180.v:3083.84-3083.109" - cell $eq $eq$ls180.v:3083$626 + attribute \src "ls180.v:3074.84-3074.109" + cell $eq $eq$ls180.v:3074$626 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254333,10 +254125,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 1'0 - connect \Y $eq$ls180.v:3083$626_Y + connect \Y $eq$ls180.v:3074$626_Y end - attribute \src "ls180.v:3084.84-3084.109" - cell $eq $eq$ls180.v:3084$628 + attribute \src "ls180.v:3075.84-3075.109" + cell $eq $eq$ls180.v:3075$628 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254344,10 +254136,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 1'1 - connect \Y $eq$ls180.v:3084$628_Y + connect \Y $eq$ls180.v:3075$628_Y end - attribute \src "ls180.v:3085.84-3085.109" - cell $eq $eq$ls180.v:3085$630 + attribute \src "ls180.v:3076.84-3076.109" + cell $eq $eq$ls180.v:3076$630 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254355,10 +254147,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 2'10 - connect \Y $eq$ls180.v:3085$630_Y + connect \Y $eq$ls180.v:3076$630_Y end - attribute \src "ls180.v:3086.84-3086.109" - cell $eq $eq$ls180.v:3086$632 + attribute \src "ls180.v:3077.84-3077.109" + cell $eq $eq$ls180.v:3077$632 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254366,10 +254158,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 1'0 - connect \Y $eq$ls180.v:3086$632_Y + connect \Y $eq$ls180.v:3077$632_Y end - attribute \src "ls180.v:3087.84-3087.109" - cell $eq $eq$ls180.v:3087$634 + attribute \src "ls180.v:3078.84-3078.109" + cell $eq $eq$ls180.v:3078$634 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254377,10 +254169,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 1'1 - connect \Y $eq$ls180.v:3087$634_Y + connect \Y $eq$ls180.v:3078$634_Y end - attribute \src "ls180.v:3088.84-3088.109" - cell $eq $eq$ls180.v:3088$636 + attribute \src "ls180.v:3079.84-3079.109" + cell $eq $eq$ls180.v:3079$636 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254388,10 +254180,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 2'10 - connect \Y $eq$ls180.v:3088$636_Y + connect \Y $eq$ls180.v:3079$636_Y end - attribute \src "ls180.v:3092.31-3092.67" - cell $eq $eq$ls180.v:3092$639 + attribute \src "ls180.v:3083.31-3083.67" + cell $eq $eq$ls180.v:3083$639 parameter \A_SIGNED 0 parameter \A_WIDTH 23 parameter \B_SIGNED 0 @@ -254399,10 +254191,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:7] connect \B 1'0 - connect \Y $eq$ls180.v:3092$639_Y + connect \Y $eq$ls180.v:3083$639_Y end - attribute \src "ls180.v:3093.31-3093.68" - cell $eq $eq$ls180.v:3093$640 + attribute \src "ls180.v:3084.31-3084.68" + cell $eq $eq$ls180.v:3084$640 parameter \A_SIGNED 0 parameter \A_WIDTH 25 parameter \B_SIGNED 0 @@ -254410,10 +254202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:5] connect \B 4'1110 - connect \Y $eq$ls180.v:3093$640_Y + connect \Y $eq$ls180.v:3084$640_Y end - attribute \src "ls180.v:3094.31-3094.76" - cell $eq $eq$ls180.v:3094$641 + attribute \src "ls180.v:3085.31-3085.76" + cell $eq $eq$ls180.v:3085$641 parameter \A_SIGNED 0 parameter \A_WIDTH 27 parameter \B_SIGNED 0 @@ -254421,10 +254213,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:3] connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:3094$641_Y + connect \Y $eq$ls180.v:3085$641_Y end - attribute \src "ls180.v:3095.31-3095.74" - cell $eq $eq$ls180.v:3095$642 + attribute \src "ls180.v:3086.31-3086.74" + cell $eq $eq$ls180.v:3086$642 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -254432,10 +254224,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:10] connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:3095$642_Y + connect \Y $eq$ls180.v:3086$642_Y end - attribute \src "ls180.v:3096.31-3096.69" - cell $eq $eq$ls180.v:3096$643 + attribute \src "ls180.v:3087.31-3087.69" + cell $eq $eq$ls180.v:3087$643 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -254443,10 +254235,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:23] connect \B 7'1001000 - connect \Y $eq$ls180.v:3096$643_Y + connect \Y $eq$ls180.v:3087$643_Y end - attribute \src "ls180.v:3097.31-3097.73" - cell $eq $eq$ls180.v:3097$644 + attribute \src "ls180.v:3088.31-3088.73" + cell $eq $eq$ls180.v:3088$644 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -254454,10 +254246,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:14] connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:3097$644_Y + connect \Y $eq$ls180.v:3088$644_Y end - attribute \src "ls180.v:3161.28-3161.53" - cell $eq $eq$ls180.v:3161$676 + attribute \src "ls180.v:3152.28-3152.53" + cell $eq $eq$ls180.v:3152$676 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -254465,10 +254257,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_count connect \B 1'0 - connect \Y $eq$ls180.v:3161$676_Y + connect \Y $eq$ls180.v:3152$676_Y end - attribute \src "ls180.v:3162.36-3162.85" - cell $eq $eq$ls180.v:3162$677 + attribute \src "ls180.v:3153.36-3153.85" + cell $eq $eq$ls180.v:3153$677 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254476,10 +254268,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [13:9] connect \B 1'0 - connect \Y $eq$ls180.v:3162$677_Y + connect \Y $eq$ls180.v:3153$677_Y end - attribute \src "ls180.v:3164.109-3164.157" - cell $eq $eq$ls180.v:3164$679 + attribute \src "ls180.v:3155.109-3155.157" + cell $eq $eq$ls180.v:3155$679 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254487,10 +254279,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:3164$679_Y + connect \Y $eq$ls180.v:3155$679_Y end - attribute \src "ls180.v:3165.112-3165.160" - cell $eq $eq$ls180.v:3165$683 + attribute \src "ls180.v:3156.112-3156.160" + cell $eq $eq$ls180.v:3156$683 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254498,10 +254290,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:3165$683_Y + connect \Y $eq$ls180.v:3156$683_Y end - attribute \src "ls180.v:3167.111-3167.159" - cell $eq $eq$ls180.v:3167$686 + attribute \src "ls180.v:3158.111-3158.159" + cell $eq $eq$ls180.v:3158$686 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254509,10 +254301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:3167$686_Y + connect \Y $eq$ls180.v:3158$686_Y end - attribute \src "ls180.v:3168.114-3168.162" - cell $eq $eq$ls180.v:3168$690 + attribute \src "ls180.v:3159.114-3159.162" + cell $eq $eq$ls180.v:3159$690 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254520,10 +254312,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:3168$690_Y + connect \Y $eq$ls180.v:3159$690_Y end - attribute \src "ls180.v:3170.111-3170.159" - cell $eq $eq$ls180.v:3170$693 + attribute \src "ls180.v:3161.111-3161.159" + cell $eq $eq$ls180.v:3161$693 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254531,10 +254323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:3170$693_Y + connect \Y $eq$ls180.v:3161$693_Y end - attribute \src "ls180.v:3171.114-3171.162" - cell $eq $eq$ls180.v:3171$697 + attribute \src "ls180.v:3162.114-3162.162" + cell $eq $eq$ls180.v:3162$697 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254542,10 +254334,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:3171$697_Y + connect \Y $eq$ls180.v:3162$697_Y end - attribute \src "ls180.v:3173.111-3173.159" - cell $eq $eq$ls180.v:3173$700 + attribute \src "ls180.v:3164.111-3164.159" + cell $eq $eq$ls180.v:3164$700 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254553,10 +254345,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:3173$700_Y + connect \Y $eq$ls180.v:3164$700_Y end - attribute \src "ls180.v:3174.114-3174.162" - cell $eq $eq$ls180.v:3174$704 + attribute \src "ls180.v:3165.114-3165.162" + cell $eq $eq$ls180.v:3165$704 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254564,10 +254356,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:3174$704_Y + connect \Y $eq$ls180.v:3165$704_Y end - attribute \src "ls180.v:3176.111-3176.159" - cell $eq $eq$ls180.v:3176$707 + attribute \src "ls180.v:3167.111-3167.159" + cell $eq $eq$ls180.v:3167$707 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254575,10 +254367,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:3176$707_Y + connect \Y $eq$ls180.v:3167$707_Y end - attribute \src "ls180.v:3177.114-3177.162" - cell $eq $eq$ls180.v:3177$711 + attribute \src "ls180.v:3168.114-3168.162" + cell $eq $eq$ls180.v:3168$711 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254586,10 +254378,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:3177$711_Y + connect \Y $eq$ls180.v:3168$711_Y end - attribute \src "ls180.v:3179.114-3179.162" - cell $eq $eq$ls180.v:3179$714 + attribute \src "ls180.v:3170.114-3170.162" + cell $eq $eq$ls180.v:3170$714 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254597,10 +254389,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:3179$714_Y + connect \Y $eq$ls180.v:3170$714_Y end - attribute \src "ls180.v:3180.117-3180.165" - cell $eq $eq$ls180.v:3180$718 + attribute \src "ls180.v:3171.117-3171.165" + cell $eq $eq$ls180.v:3171$718 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254608,10 +254400,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:3180$718_Y + connect \Y $eq$ls180.v:3171$718_Y end - attribute \src "ls180.v:3182.114-3182.162" - cell $eq $eq$ls180.v:3182$721 + attribute \src "ls180.v:3173.114-3173.162" + cell $eq $eq$ls180.v:3173$721 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254619,10 +254411,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:3182$721_Y + connect \Y $eq$ls180.v:3173$721_Y end - attribute \src "ls180.v:3183.117-3183.165" - cell $eq $eq$ls180.v:3183$725 + attribute \src "ls180.v:3174.117-3174.165" + cell $eq $eq$ls180.v:3174$725 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254630,10 +254422,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:3183$725_Y + connect \Y $eq$ls180.v:3174$725_Y end - attribute \src "ls180.v:3185.114-3185.162" - cell $eq $eq$ls180.v:3185$728 + attribute \src "ls180.v:3176.114-3176.162" + cell $eq $eq$ls180.v:3176$728 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254641,10 +254433,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:3185$728_Y + connect \Y $eq$ls180.v:3176$728_Y end - attribute \src "ls180.v:3186.117-3186.165" - cell $eq $eq$ls180.v:3186$732 + attribute \src "ls180.v:3177.117-3177.165" + cell $eq $eq$ls180.v:3177$732 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254652,10 +254444,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:3186$732_Y + connect \Y $eq$ls180.v:3177$732_Y end - attribute \src "ls180.v:3188.114-3188.162" - cell $eq $eq$ls180.v:3188$735 + attribute \src "ls180.v:3179.114-3179.162" + cell $eq $eq$ls180.v:3179$735 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254663,10 +254455,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:3188$735_Y + connect \Y $eq$ls180.v:3179$735_Y end - attribute \src "ls180.v:3189.117-3189.165" - cell $eq $eq$ls180.v:3189$739 + attribute \src "ls180.v:3180.117-3180.165" + cell $eq $eq$ls180.v:3180$739 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254674,10 +254466,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:3189$739_Y + connect \Y $eq$ls180.v:3180$739_Y end - attribute \src "ls180.v:3200.36-3200.85" - cell $eq $eq$ls180.v:3200$741 + attribute \src "ls180.v:3191.36-3191.85" + cell $eq $eq$ls180.v:3191$741 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254685,10 +254477,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [13:9] connect \B 3'110 - connect \Y $eq$ls180.v:3200$741_Y + connect \Y $eq$ls180.v:3191$741_Y end - attribute \src "ls180.v:3202.106-3202.154" - cell $eq $eq$ls180.v:3202$743 + attribute \src "ls180.v:3193.106-3193.154" + cell $eq $eq$ls180.v:3193$743 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254696,10 +254488,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:3202$743_Y + connect \Y $eq$ls180.v:3193$743_Y end - attribute \src "ls180.v:3203.109-3203.157" - cell $eq $eq$ls180.v:3203$747 + attribute \src "ls180.v:3194.109-3194.157" + cell $eq $eq$ls180.v:3194$747 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254707,10 +254499,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:3203$747_Y + connect \Y $eq$ls180.v:3194$747_Y end - attribute \src "ls180.v:3205.105-3205.153" - cell $eq $eq$ls180.v:3205$750 + attribute \src "ls180.v:3196.105-3196.153" + cell $eq $eq$ls180.v:3196$750 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254718,10 +254510,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:3205$750_Y + connect \Y $eq$ls180.v:3196$750_Y end - attribute \src "ls180.v:3206.108-3206.156" - cell $eq $eq$ls180.v:3206$754 + attribute \src "ls180.v:3197.108-3197.156" + cell $eq $eq$ls180.v:3197$754 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254729,10 +254521,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:3206$754_Y + connect \Y $eq$ls180.v:3197$754_Y end - attribute \src "ls180.v:3208.107-3208.155" - cell $eq $eq$ls180.v:3208$757 + attribute \src "ls180.v:3199.107-3199.155" + cell $eq $eq$ls180.v:3199$757 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254740,10 +254532,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:3208$757_Y + connect \Y $eq$ls180.v:3199$757_Y end - attribute \src "ls180.v:3209.110-3209.158" - cell $eq $eq$ls180.v:3209$761 + attribute \src "ls180.v:3200.110-3200.158" + cell $eq $eq$ls180.v:3200$761 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254751,10 +254543,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:3209$761_Y + connect \Y $eq$ls180.v:3200$761_Y end - attribute \src "ls180.v:3214.36-3214.85" - cell $eq $eq$ls180.v:3214$763 + attribute \src "ls180.v:3205.36-3205.85" + cell $eq $eq$ls180.v:3205$763 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254762,10 +254554,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [13:9] connect \B 3'111 - connect \Y $eq$ls180.v:3214$763_Y + connect \Y $eq$ls180.v:3205$763_Y end - attribute \src "ls180.v:3216.106-3216.154" - cell $eq $eq$ls180.v:3216$765 + attribute \src "ls180.v:3207.106-3207.154" + cell $eq $eq$ls180.v:3207$765 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254773,10 +254565,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:3216$765_Y + connect \Y $eq$ls180.v:3207$765_Y end - attribute \src "ls180.v:3217.109-3217.157" - cell $eq $eq$ls180.v:3217$769 + attribute \src "ls180.v:3208.109-3208.157" + cell $eq $eq$ls180.v:3208$769 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254784,10 +254576,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:3217$769_Y + connect \Y $eq$ls180.v:3208$769_Y end - attribute \src "ls180.v:3219.105-3219.153" - cell $eq $eq$ls180.v:3219$772 + attribute \src "ls180.v:3210.105-3210.153" + cell $eq $eq$ls180.v:3210$772 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254795,10 +254587,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:3219$772_Y + connect \Y $eq$ls180.v:3210$772_Y end - attribute \src "ls180.v:3220.108-3220.156" - cell $eq $eq$ls180.v:3220$776 + attribute \src "ls180.v:3211.108-3211.156" + cell $eq $eq$ls180.v:3211$776 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254806,10 +254598,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:3220$776_Y + connect \Y $eq$ls180.v:3211$776_Y end - attribute \src "ls180.v:3222.107-3222.155" - cell $eq $eq$ls180.v:3222$779 + attribute \src "ls180.v:3213.107-3213.155" + cell $eq $eq$ls180.v:3213$779 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254817,10 +254609,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:3222$779_Y + connect \Y $eq$ls180.v:3213$779_Y end - attribute \src "ls180.v:3223.110-3223.158" - cell $eq $eq$ls180.v:3223$783 + attribute \src "ls180.v:3214.110-3214.158" + cell $eq $eq$ls180.v:3214$783 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254828,10 +254620,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:3223$783_Y + connect \Y $eq$ls180.v:3214$783_Y end - attribute \src "ls180.v:3228.36-3228.85" - cell $eq $eq$ls180.v:3228$785 + attribute \src "ls180.v:3219.36-3219.85" + cell $eq $eq$ls180.v:3219$785 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254839,10 +254631,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_adr [13:9] connect \B 4'1000 - connect \Y $eq$ls180.v:3228$785_Y + connect \Y $eq$ls180.v:3219$785_Y end - attribute \src "ls180.v:3230.105-3230.151" - cell $eq $eq$ls180.v:3230$787 + attribute \src "ls180.v:3221.105-3221.151" + cell $eq $eq$ls180.v:3221$787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254850,10 +254642,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:3230$787_Y + connect \Y $eq$ls180.v:3221$787_Y end - attribute \src "ls180.v:3231.108-3231.154" - cell $eq $eq$ls180.v:3231$791 + attribute \src "ls180.v:3222.108-3222.154" + cell $eq $eq$ls180.v:3222$791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254861,10 +254653,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:3231$791_Y + connect \Y $eq$ls180.v:3222$791_Y end - attribute \src "ls180.v:3233.104-3233.150" - cell $eq $eq$ls180.v:3233$794 + attribute \src "ls180.v:3224.104-3224.150" + cell $eq $eq$ls180.v:3224$794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254872,10 +254664,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:3233$794_Y + connect \Y $eq$ls180.v:3224$794_Y end - attribute \src "ls180.v:3234.107-3234.153" - cell $eq $eq$ls180.v:3234$798 + attribute \src "ls180.v:3225.107-3225.153" + cell $eq $eq$ls180.v:3225$798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254883,10 +254675,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:3234$798_Y + connect \Y $eq$ls180.v:3225$798_Y end - attribute \src "ls180.v:3242.36-3242.85" - cell $eq $eq$ls180.v:3242$800 + attribute \src "ls180.v:3233.36-3233.85" + cell $eq $eq$ls180.v:3233$800 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254894,10 +254686,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [13:9] connect \B 2'11 - connect \Y $eq$ls180.v:3242$800_Y + connect \Y $eq$ls180.v:3233$800_Y end - attribute \src "ls180.v:3244.116-3244.164" - cell $eq $eq$ls180.v:3244$802 + attribute \src "ls180.v:3235.116-3235.164" + cell $eq $eq$ls180.v:3235$802 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254905,10 +254697,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:3244$802_Y + connect \Y $eq$ls180.v:3235$802_Y end - attribute \src "ls180.v:3245.119-3245.167" - cell $eq $eq$ls180.v:3245$806 + attribute \src "ls180.v:3236.119-3236.167" + cell $eq $eq$ls180.v:3236$806 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254916,10 +254708,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:3245$806_Y + connect \Y $eq$ls180.v:3236$806_Y end - attribute \src "ls180.v:3247.120-3247.168" - cell $eq $eq$ls180.v:3247$809 + attribute \src "ls180.v:3238.120-3238.168" + cell $eq $eq$ls180.v:3238$809 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254927,10 +254719,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:3247$809_Y + connect \Y $eq$ls180.v:3238$809_Y end - attribute \src "ls180.v:3248.123-3248.171" - cell $eq $eq$ls180.v:3248$813 + attribute \src "ls180.v:3239.123-3239.171" + cell $eq $eq$ls180.v:3239$813 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254938,10 +254730,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:3248$813_Y + connect \Y $eq$ls180.v:3239$813_Y end - attribute \src "ls180.v:3250.101-3250.149" - cell $eq $eq$ls180.v:3250$816 + attribute \src "ls180.v:3241.101-3241.149" + cell $eq $eq$ls180.v:3241$816 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254949,10 +254741,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:3250$816_Y + connect \Y $eq$ls180.v:3241$816_Y end - attribute \src "ls180.v:3251.104-3251.152" - cell $eq $eq$ls180.v:3251$820 + attribute \src "ls180.v:3242.104-3242.152" + cell $eq $eq$ls180.v:3242$820 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254960,10 +254752,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:3251$820_Y + connect \Y $eq$ls180.v:3242$820_Y end - attribute \src "ls180.v:3253.120-3253.168" - cell $eq $eq$ls180.v:3253$823 + attribute \src "ls180.v:3244.120-3244.168" + cell $eq $eq$ls180.v:3244$823 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254971,10 +254763,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:3253$823_Y + connect \Y $eq$ls180.v:3244$823_Y end - attribute \src "ls180.v:3254.123-3254.171" - cell $eq $eq$ls180.v:3254$827 + attribute \src "ls180.v:3245.123-3245.171" + cell $eq $eq$ls180.v:3245$827 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254982,10 +254774,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:3254$827_Y + connect \Y $eq$ls180.v:3245$827_Y end - attribute \src "ls180.v:3256.120-3256.168" - cell $eq $eq$ls180.v:3256$830 + attribute \src "ls180.v:3247.120-3247.168" + cell $eq $eq$ls180.v:3247$830 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254993,10 +254785,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:3256$830_Y + connect \Y $eq$ls180.v:3247$830_Y end - attribute \src "ls180.v:3257.123-3257.171" - cell $eq $eq$ls180.v:3257$834 + attribute \src "ls180.v:3248.123-3248.171" + cell $eq $eq$ls180.v:3248$834 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255004,10 +254796,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:3257$834_Y + connect \Y $eq$ls180.v:3248$834_Y end - attribute \src "ls180.v:3259.121-3259.169" - cell $eq $eq$ls180.v:3259$837 + attribute \src "ls180.v:3250.121-3250.169" + cell $eq $eq$ls180.v:3250$837 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255015,10 +254807,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:3259$837_Y + connect \Y $eq$ls180.v:3250$837_Y end - attribute \src "ls180.v:3260.124-3260.172" - cell $eq $eq$ls180.v:3260$841 + attribute \src "ls180.v:3251.124-3251.172" + cell $eq $eq$ls180.v:3251$841 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255026,10 +254818,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:3260$841_Y + connect \Y $eq$ls180.v:3251$841_Y end - attribute \src "ls180.v:3262.119-3262.167" - cell $eq $eq$ls180.v:3262$844 + attribute \src "ls180.v:3253.119-3253.167" + cell $eq $eq$ls180.v:3253$844 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255037,10 +254829,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:3262$844_Y + connect \Y $eq$ls180.v:3253$844_Y end - attribute \src "ls180.v:3263.122-3263.170" - cell $eq $eq$ls180.v:3263$848 + attribute \src "ls180.v:3254.122-3254.170" + cell $eq $eq$ls180.v:3254$848 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255048,10 +254840,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:3263$848_Y + connect \Y $eq$ls180.v:3254$848_Y end - attribute \src "ls180.v:3265.119-3265.167" - cell $eq $eq$ls180.v:3265$851 + attribute \src "ls180.v:3256.119-3256.167" + cell $eq $eq$ls180.v:3256$851 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255059,10 +254851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:3265$851_Y + connect \Y $eq$ls180.v:3256$851_Y end - attribute \src "ls180.v:3266.122-3266.170" - cell $eq $eq$ls180.v:3266$855 + attribute \src "ls180.v:3257.122-3257.170" + cell $eq $eq$ls180.v:3257$855 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255070,10 +254862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:3266$855_Y + connect \Y $eq$ls180.v:3257$855_Y end - attribute \src "ls180.v:3268.119-3268.167" - cell $eq $eq$ls180.v:3268$858 + attribute \src "ls180.v:3259.119-3259.167" + cell $eq $eq$ls180.v:3259$858 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255081,10 +254873,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:3268$858_Y + connect \Y $eq$ls180.v:3259$858_Y end - attribute \src "ls180.v:3269.122-3269.170" - cell $eq $eq$ls180.v:3269$862 + attribute \src "ls180.v:3260.122-3260.170" + cell $eq $eq$ls180.v:3260$862 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255092,10 +254884,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:3269$862_Y + connect \Y $eq$ls180.v:3260$862_Y end - attribute \src "ls180.v:3271.119-3271.167" - cell $eq $eq$ls180.v:3271$865 + attribute \src "ls180.v:3262.119-3262.167" + cell $eq $eq$ls180.v:3262$865 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255103,10 +254895,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:3271$865_Y + connect \Y $eq$ls180.v:3262$865_Y end - attribute \src "ls180.v:3272.122-3272.170" - cell $eq $eq$ls180.v:3272$869 + attribute \src "ls180.v:3263.122-3263.170" + cell $eq $eq$ls180.v:3263$869 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255114,10 +254906,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:3272$869_Y + connect \Y $eq$ls180.v:3263$869_Y end - attribute \src "ls180.v:3287.36-3287.85" - cell $eq $eq$ls180.v:3287$871 + attribute \src "ls180.v:3278.36-3278.85" + cell $eq $eq$ls180.v:3278$871 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255125,10 +254917,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [13:9] connect \B 2'10 - connect \Y $eq$ls180.v:3287$871_Y + connect \Y $eq$ls180.v:3278$871_Y end - attribute \src "ls180.v:3289.108-3289.156" - cell $eq $eq$ls180.v:3289$873 + attribute \src "ls180.v:3280.108-3280.156" + cell $eq $eq$ls180.v:3280$873 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255136,10 +254928,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:3289$873_Y + connect \Y $eq$ls180.v:3280$873_Y end - attribute \src "ls180.v:3290.111-3290.159" - cell $eq $eq$ls180.v:3290$877 + attribute \src "ls180.v:3281.111-3281.159" + cell $eq $eq$ls180.v:3281$877 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255147,10 +254939,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:3290$877_Y + connect \Y $eq$ls180.v:3281$877_Y end - attribute \src "ls180.v:3292.108-3292.156" - cell $eq $eq$ls180.v:3292$880 + attribute \src "ls180.v:3283.108-3283.156" + cell $eq $eq$ls180.v:3283$880 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255158,10 +254950,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:3292$880_Y + connect \Y $eq$ls180.v:3283$880_Y end - attribute \src "ls180.v:3293.111-3293.159" - cell $eq $eq$ls180.v:3293$884 + attribute \src "ls180.v:3284.111-3284.159" + cell $eq $eq$ls180.v:3284$884 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255169,10 +254961,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:3293$884_Y + connect \Y $eq$ls180.v:3284$884_Y end - attribute \src "ls180.v:3295.108-3295.156" - cell $eq $eq$ls180.v:3295$887 + attribute \src "ls180.v:3286.108-3286.156" + cell $eq $eq$ls180.v:3286$887 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255180,10 +254972,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:3295$887_Y + connect \Y $eq$ls180.v:3286$887_Y end - attribute \src "ls180.v:3296.111-3296.159" - cell $eq $eq$ls180.v:3296$891 + attribute \src "ls180.v:3287.111-3287.159" + cell $eq $eq$ls180.v:3287$891 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255191,10 +254983,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:3296$891_Y + connect \Y $eq$ls180.v:3287$891_Y end - attribute \src "ls180.v:3298.108-3298.156" - cell $eq $eq$ls180.v:3298$894 + attribute \src "ls180.v:3289.108-3289.156" + cell $eq $eq$ls180.v:3289$894 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255202,10 +254994,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:3298$894_Y + connect \Y $eq$ls180.v:3289$894_Y end - attribute \src "ls180.v:3299.111-3299.159" - cell $eq $eq$ls180.v:3299$898 + attribute \src "ls180.v:3290.111-3290.159" + cell $eq $eq$ls180.v:3290$898 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255213,10 +255005,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:3299$898_Y + connect \Y $eq$ls180.v:3290$898_Y end - attribute \src "ls180.v:3301.110-3301.158" - cell $eq $eq$ls180.v:3301$901 + attribute \src "ls180.v:3292.110-3292.158" + cell $eq $eq$ls180.v:3292$901 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255224,10 +255016,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:3301$901_Y + connect \Y $eq$ls180.v:3292$901_Y end - attribute \src "ls180.v:3302.113-3302.161" - cell $eq $eq$ls180.v:3302$905 + attribute \src "ls180.v:3293.113-3293.161" + cell $eq $eq$ls180.v:3293$905 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255235,10 +255027,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:3302$905_Y + connect \Y $eq$ls180.v:3293$905_Y end - attribute \src "ls180.v:3304.110-3304.158" - cell $eq $eq$ls180.v:3304$908 + attribute \src "ls180.v:3295.110-3295.158" + cell $eq $eq$ls180.v:3295$908 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255246,10 +255038,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:3304$908_Y + connect \Y $eq$ls180.v:3295$908_Y end - attribute \src "ls180.v:3305.113-3305.161" - cell $eq $eq$ls180.v:3305$912 + attribute \src "ls180.v:3296.113-3296.161" + cell $eq $eq$ls180.v:3296$912 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255257,10 +255049,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:3305$912_Y + connect \Y $eq$ls180.v:3296$912_Y end - attribute \src "ls180.v:3307.110-3307.158" - cell $eq $eq$ls180.v:3307$915 + attribute \src "ls180.v:3298.110-3298.158" + cell $eq $eq$ls180.v:3298$915 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255268,10 +255060,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:3307$915_Y + connect \Y $eq$ls180.v:3298$915_Y end - attribute \src "ls180.v:3308.113-3308.161" - cell $eq $eq$ls180.v:3308$919 + attribute \src "ls180.v:3299.113-3299.161" + cell $eq $eq$ls180.v:3299$919 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255279,10 +255071,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:3308$919_Y + connect \Y $eq$ls180.v:3299$919_Y end - attribute \src "ls180.v:3310.110-3310.158" - cell $eq $eq$ls180.v:3310$922 + attribute \src "ls180.v:3301.110-3301.158" + cell $eq $eq$ls180.v:3301$922 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255290,10 +255082,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:3310$922_Y + connect \Y $eq$ls180.v:3301$922_Y end - attribute \src "ls180.v:3311.113-3311.161" - cell $eq $eq$ls180.v:3311$926 + attribute \src "ls180.v:3302.113-3302.161" + cell $eq $eq$ls180.v:3302$926 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255301,10 +255093,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:3311$926_Y + connect \Y $eq$ls180.v:3302$926_Y end - attribute \src "ls180.v:3313.106-3313.154" - cell $eq $eq$ls180.v:3313$929 + attribute \src "ls180.v:3304.106-3304.154" + cell $eq $eq$ls180.v:3304$929 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255312,10 +255104,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:3313$929_Y + connect \Y $eq$ls180.v:3304$929_Y end - attribute \src "ls180.v:3314.109-3314.157" - cell $eq $eq$ls180.v:3314$933 + attribute \src "ls180.v:3305.109-3305.157" + cell $eq $eq$ls180.v:3305$933 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255323,10 +255115,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:3314$933_Y + connect \Y $eq$ls180.v:3305$933_Y end - attribute \src "ls180.v:3316.116-3316.164" - cell $eq $eq$ls180.v:3316$936 + attribute \src "ls180.v:3307.116-3307.164" + cell $eq $eq$ls180.v:3307$936 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255334,10 +255126,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:3316$936_Y + connect \Y $eq$ls180.v:3307$936_Y end - attribute \src "ls180.v:3317.119-3317.167" - cell $eq $eq$ls180.v:3317$940 + attribute \src "ls180.v:3308.119-3308.167" + cell $eq $eq$ls180.v:3308$940 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255345,10 +255137,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:3317$940_Y + connect \Y $eq$ls180.v:3308$940_Y end - attribute \src "ls180.v:3319.109-3319.158" - cell $eq $eq$ls180.v:3319$943 + attribute \src "ls180.v:3310.109-3310.158" + cell $eq $eq$ls180.v:3310$943 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255356,10 +255148,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:3319$943_Y + connect \Y $eq$ls180.v:3310$943_Y end - attribute \src "ls180.v:3320.112-3320.161" - cell $eq $eq$ls180.v:3320$947 + attribute \src "ls180.v:3311.112-3311.161" + cell $eq $eq$ls180.v:3311$947 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255367,10 +255159,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:3320$947_Y + connect \Y $eq$ls180.v:3311$947_Y end - attribute \src "ls180.v:3322.109-3322.158" - cell $eq $eq$ls180.v:3322$950 + attribute \src "ls180.v:3313.109-3313.158" + cell $eq $eq$ls180.v:3313$950 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255378,10 +255170,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:3322$950_Y + connect \Y $eq$ls180.v:3313$950_Y end - attribute \src "ls180.v:3323.112-3323.161" - cell $eq $eq$ls180.v:3323$954 + attribute \src "ls180.v:3314.112-3314.161" + cell $eq $eq$ls180.v:3314$954 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255389,10 +255181,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:3323$954_Y + connect \Y $eq$ls180.v:3314$954_Y end - attribute \src "ls180.v:3325.109-3325.158" - cell $eq $eq$ls180.v:3325$957 + attribute \src "ls180.v:3316.109-3316.158" + cell $eq $eq$ls180.v:3316$957 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255400,10 +255192,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:3325$957_Y + connect \Y $eq$ls180.v:3316$957_Y end - attribute \src "ls180.v:3326.112-3326.161" - cell $eq $eq$ls180.v:3326$961 + attribute \src "ls180.v:3317.112-3317.161" + cell $eq $eq$ls180.v:3317$961 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255411,10 +255203,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:3326$961_Y + connect \Y $eq$ls180.v:3317$961_Y end - attribute \src "ls180.v:3328.109-3328.158" - cell $eq $eq$ls180.v:3328$964 + attribute \src "ls180.v:3319.109-3319.158" + cell $eq $eq$ls180.v:3319$964 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255422,10 +255214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:3328$964_Y + connect \Y $eq$ls180.v:3319$964_Y end - attribute \src "ls180.v:3329.112-3329.161" - cell $eq $eq$ls180.v:3329$968 + attribute \src "ls180.v:3320.112-3320.161" + cell $eq $eq$ls180.v:3320$968 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255433,10 +255225,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:3329$968_Y + connect \Y $eq$ls180.v:3320$968_Y end - attribute \src "ls180.v:3331.113-3331.162" - cell $eq $eq$ls180.v:3331$971 + attribute \src "ls180.v:3322.113-3322.162" + cell $eq $eq$ls180.v:3322$971 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255444,10 +255236,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:3331$971_Y + connect \Y $eq$ls180.v:3322$971_Y end - attribute \src "ls180.v:3332.116-3332.165" - cell $eq $eq$ls180.v:3332$975 + attribute \src "ls180.v:3323.116-3323.165" + cell $eq $eq$ls180.v:3323$975 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255455,10 +255247,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:3332$975_Y + connect \Y $eq$ls180.v:3323$975_Y end - attribute \src "ls180.v:3334.114-3334.163" - cell $eq $eq$ls180.v:3334$978 + attribute \src "ls180.v:3325.114-3325.163" + cell $eq $eq$ls180.v:3325$978 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255466,10 +255258,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:3334$978_Y + connect \Y $eq$ls180.v:3325$978_Y end - attribute \src "ls180.v:3335.117-3335.166" - cell $eq $eq$ls180.v:3335$982 + attribute \src "ls180.v:3326.117-3326.166" + cell $eq $eq$ls180.v:3326$982 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255477,10 +255269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:3335$982_Y + connect \Y $eq$ls180.v:3326$982_Y end - attribute \src "ls180.v:3337.113-3337.162" - cell $eq $eq$ls180.v:3337$985 + attribute \src "ls180.v:3328.113-3328.162" + cell $eq $eq$ls180.v:3328$985 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255488,10 +255280,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:3337$985_Y + connect \Y $eq$ls180.v:3328$985_Y end - attribute \src "ls180.v:3338.116-3338.165" - cell $eq $eq$ls180.v:3338$989 + attribute \src "ls180.v:3329.116-3329.165" + cell $eq $eq$ls180.v:3329$989 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255499,10 +255291,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:3338$989_Y + connect \Y $eq$ls180.v:3329$989_Y end - attribute \src "ls180.v:3355.36-3355.85" - cell $eq $eq$ls180.v:3355$991 + attribute \src "ls180.v:3346.36-3346.85" + cell $eq $eq$ls180.v:3346$991 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255510,10 +255302,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [13:9] connect \B 3'101 - connect \Y $eq$ls180.v:3355$991_Y + connect \Y $eq$ls180.v:3346$991_Y end - attribute \src "ls180.v:3357.86-3357.134" - cell $eq $eq$ls180.v:3357$993 + attribute \src "ls180.v:3348.86-3348.134" + cell $eq $eq$ls180.v:3348$993 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255521,10 +255313,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:3357$993_Y + connect \Y $eq$ls180.v:3348$993_Y end - attribute \src "ls180.v:3358.89-3358.137" - cell $eq $eq$ls180.v:3358$997 + attribute \src "ls180.v:3349.89-3349.137" + cell $eq $eq$ls180.v:3349$997 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255532,10 +255324,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:3358$997_Y + connect \Y $eq$ls180.v:3349$997_Y end - attribute \src "ls180.v:3360.109-3360.157" - cell $eq $eq$ls180.v:3360$1000 + attribute \src "ls180.v:3351.109-3351.157" + cell $eq $eq$ls180.v:3351$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255543,10 +255335,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:3360$1000_Y + connect \Y $eq$ls180.v:3351$1000_Y end - attribute \src "ls180.v:3361.112-3361.160" - cell $eq $eq$ls180.v:3361$1004 + attribute \src "ls180.v:3352.112-3352.160" + cell $eq $eq$ls180.v:3352$1004 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255554,10 +255346,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:3361$1004_Y + connect \Y $eq$ls180.v:3352$1004_Y end - attribute \src "ls180.v:3363.110-3363.158" - cell $eq $eq$ls180.v:3363$1007 + attribute \src "ls180.v:3354.110-3354.158" + cell $eq $eq$ls180.v:3354$1007 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255565,10 +255357,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:3363$1007_Y + connect \Y $eq$ls180.v:3354$1007_Y end - attribute \src "ls180.v:3364.113-3364.161" - cell $eq $eq$ls180.v:3364$1011 + attribute \src "ls180.v:3355.113-3355.161" + cell $eq $eq$ls180.v:3355$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255576,10 +255368,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:3364$1011_Y + connect \Y $eq$ls180.v:3355$1011_Y end - attribute \src "ls180.v:3366.101-3366.149" - cell $eq $eq$ls180.v:3366$1014 + attribute \src "ls180.v:3357.101-3357.149" + cell $eq $eq$ls180.v:3357$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255587,10 +255379,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:3366$1014_Y + connect \Y $eq$ls180.v:3357$1014_Y end - attribute \src "ls180.v:3367.104-3367.152" - cell $eq $eq$ls180.v:3367$1018 + attribute \src "ls180.v:3358.104-3358.152" + cell $eq $eq$ls180.v:3358$1018 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255598,10 +255390,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:3367$1018_Y + connect \Y $eq$ls180.v:3358$1018_Y end - attribute \src "ls180.v:3369.102-3369.150" - cell $eq $eq$ls180.v:3369$1021 + attribute \src "ls180.v:3360.102-3360.150" + cell $eq $eq$ls180.v:3360$1021 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255609,10 +255401,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:3369$1021_Y + connect \Y $eq$ls180.v:3360$1021_Y end - attribute \src "ls180.v:3370.105-3370.153" - cell $eq $eq$ls180.v:3370$1025 + attribute \src "ls180.v:3361.105-3361.153" + cell $eq $eq$ls180.v:3361$1025 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255620,10 +255412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:3370$1025_Y + connect \Y $eq$ls180.v:3361$1025_Y end - attribute \src "ls180.v:3372.113-3372.161" - cell $eq $eq$ls180.v:3372$1028 + attribute \src "ls180.v:3363.113-3363.161" + cell $eq $eq$ls180.v:3363$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255631,10 +255423,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:3372$1028_Y + connect \Y $eq$ls180.v:3363$1028_Y end - attribute \src "ls180.v:3373.116-3373.164" - cell $eq $eq$ls180.v:3373$1032 + attribute \src "ls180.v:3364.116-3364.164" + cell $eq $eq$ls180.v:3364$1032 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255642,10 +255434,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:3373$1032_Y + connect \Y $eq$ls180.v:3364$1032_Y end - attribute \src "ls180.v:3375.110-3375.158" - cell $eq $eq$ls180.v:3375$1035 + attribute \src "ls180.v:3366.110-3366.158" + cell $eq $eq$ls180.v:3366$1035 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255653,10 +255445,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:3375$1035_Y + connect \Y $eq$ls180.v:3366$1035_Y end - attribute \src "ls180.v:3376.113-3376.161" - cell $eq $eq$ls180.v:3376$1039 + attribute \src "ls180.v:3367.113-3367.161" + cell $eq $eq$ls180.v:3367$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255664,10 +255456,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:3376$1039_Y + connect \Y $eq$ls180.v:3367$1039_Y end - attribute \src "ls180.v:3378.109-3378.157" - cell $eq $eq$ls180.v:3378$1042 + attribute \src "ls180.v:3369.109-3369.157" + cell $eq $eq$ls180.v:3369$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255675,10 +255467,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:3378$1042_Y + connect \Y $eq$ls180.v:3369$1042_Y end - attribute \src "ls180.v:3379.112-3379.160" - cell $eq $eq$ls180.v:3379$1046 + attribute \src "ls180.v:3370.112-3370.160" + cell $eq $eq$ls180.v:3370$1046 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255686,10 +255478,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:3379$1046_Y + connect \Y $eq$ls180.v:3370$1046_Y end - attribute \src "ls180.v:3389.36-3389.85" - cell $eq $eq$ls180.v:3389$1048 + attribute \src "ls180.v:3380.36-3380.85" + cell $eq $eq$ls180.v:3380$1048 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255697,10 +255489,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [13:9] connect \B 3'100 - connect \Y $eq$ls180.v:3389$1048_Y + connect \Y $eq$ls180.v:3380$1048_Y end - attribute \src "ls180.v:3391.115-3391.163" - cell $eq $eq$ls180.v:3391$1050 + attribute \src "ls180.v:3382.115-3382.163" + cell $eq $eq$ls180.v:3382$1050 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255708,10 +255500,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:3391$1050_Y + connect \Y $eq$ls180.v:3382$1050_Y end - attribute \src "ls180.v:3392.118-3392.166" - cell $eq $eq$ls180.v:3392$1054 + attribute \src "ls180.v:3383.118-3383.166" + cell $eq $eq$ls180.v:3383$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255719,10 +255511,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:3392$1054_Y + connect \Y $eq$ls180.v:3383$1054_Y end - attribute \src "ls180.v:3394.115-3394.163" - cell $eq $eq$ls180.v:3394$1057 + attribute \src "ls180.v:3385.115-3385.163" + cell $eq $eq$ls180.v:3385$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255730,10 +255522,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:3394$1057_Y + connect \Y $eq$ls180.v:3385$1057_Y end - attribute \src "ls180.v:3395.118-3395.166" - cell $eq $eq$ls180.v:3395$1061 + attribute \src "ls180.v:3386.118-3386.166" + cell $eq $eq$ls180.v:3386$1061 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255741,10 +255533,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:3395$1061_Y + connect \Y $eq$ls180.v:3386$1061_Y end - attribute \src "ls180.v:3397.115-3397.163" - cell $eq $eq$ls180.v:3397$1064 + attribute \src "ls180.v:3388.115-3388.163" + cell $eq $eq$ls180.v:3388$1064 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255752,10 +255544,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:3397$1064_Y + connect \Y $eq$ls180.v:3388$1064_Y end - attribute \src "ls180.v:3398.118-3398.166" - cell $eq $eq$ls180.v:3398$1068 + attribute \src "ls180.v:3389.118-3389.166" + cell $eq $eq$ls180.v:3389$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255763,10 +255555,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:3398$1068_Y + connect \Y $eq$ls180.v:3389$1068_Y end - attribute \src "ls180.v:3400.115-3400.163" - cell $eq $eq$ls180.v:3400$1071 + attribute \src "ls180.v:3391.115-3391.163" + cell $eq $eq$ls180.v:3391$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255774,10 +255566,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:3400$1071_Y + connect \Y $eq$ls180.v:3391$1071_Y end - attribute \src "ls180.v:3401.118-3401.166" - cell $eq $eq$ls180.v:3401$1075 + attribute \src "ls180.v:3392.118-3392.166" + cell $eq $eq$ls180.v:3392$1075 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255785,10 +255577,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:3401$1075_Y + connect \Y $eq$ls180.v:3392$1075_Y end - attribute \src "ls180.v:3761.28-3761.63" - cell $eq $eq$ls180.v:3761$1105 + attribute \src "ls180.v:3752.28-3752.63" + cell $eq $eq$ls180.v:3752$1105 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255796,10 +255588,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:3761$1105_Y + connect \Y $eq$ls180.v:3752$1105_Y end - attribute \src "ls180.v:3761.126-3761.164" - cell $eq $eq$ls180.v:3761$1106 + attribute \src "ls180.v:3752.126-3752.164" + cell $eq $eq$ls180.v:3752$1106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255807,10 +255599,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3761$1106_Y + connect \Y $eq$ls180.v:3752$1106_Y end - attribute \src "ls180.v:3761.201-3761.239" - cell $eq $eq$ls180.v:3761$1109 + attribute \src "ls180.v:3752.201-3752.239" + cell $eq $eq$ls180.v:3752$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255818,10 +255610,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3761$1109_Y + connect \Y $eq$ls180.v:3752$1109_Y end - attribute \src "ls180.v:3761.276-3761.314" - cell $eq $eq$ls180.v:3761$1112 + attribute \src "ls180.v:3752.276-3752.314" + cell $eq $eq$ls180.v:3752$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255829,10 +255621,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3761$1112_Y + connect \Y $eq$ls180.v:3752$1112_Y end - attribute \src "ls180.v:3785.28-3785.63" - cell $eq $eq$ls180.v:3785$1121 + attribute \src "ls180.v:3776.28-3776.63" + cell $eq $eq$ls180.v:3776$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255840,10 +255632,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:3785$1121_Y + connect \Y $eq$ls180.v:3776$1121_Y end - attribute \src "ls180.v:3785.126-3785.164" - cell $eq $eq$ls180.v:3785$1122 + attribute \src "ls180.v:3776.126-3776.164" + cell $eq $eq$ls180.v:3776$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255851,10 +255643,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3785$1122_Y + connect \Y $eq$ls180.v:3776$1122_Y end - attribute \src "ls180.v:3785.201-3785.239" - cell $eq $eq$ls180.v:3785$1125 + attribute \src "ls180.v:3776.201-3776.239" + cell $eq $eq$ls180.v:3776$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255862,10 +255654,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3785$1125_Y + connect \Y $eq$ls180.v:3776$1125_Y end - attribute \src "ls180.v:3785.276-3785.314" - cell $eq $eq$ls180.v:3785$1128 + attribute \src "ls180.v:3776.276-3776.314" + cell $eq $eq$ls180.v:3776$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255873,10 +255665,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3785$1128_Y + connect \Y $eq$ls180.v:3776$1128_Y end - attribute \src "ls180.v:3809.28-3809.63" - cell $eq $eq$ls180.v:3809$1137 + attribute \src "ls180.v:3800.28-3800.63" + cell $eq $eq$ls180.v:3800$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255884,10 +255676,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:3809$1137_Y + connect \Y $eq$ls180.v:3800$1137_Y end - attribute \src "ls180.v:3809.126-3809.164" - cell $eq $eq$ls180.v:3809$1138 + attribute \src "ls180.v:3800.126-3800.164" + cell $eq $eq$ls180.v:3800$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255895,10 +255687,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3809$1138_Y + connect \Y $eq$ls180.v:3800$1138_Y end - attribute \src "ls180.v:3809.201-3809.239" - cell $eq $eq$ls180.v:3809$1141 + attribute \src "ls180.v:3800.201-3800.239" + cell $eq $eq$ls180.v:3800$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255906,10 +255698,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3809$1141_Y + connect \Y $eq$ls180.v:3800$1141_Y end - attribute \src "ls180.v:3809.276-3809.314" - cell $eq $eq$ls180.v:3809$1144 + attribute \src "ls180.v:3800.276-3800.314" + cell $eq $eq$ls180.v:3800$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255917,10 +255709,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3809$1144_Y + connect \Y $eq$ls180.v:3800$1144_Y end - attribute \src "ls180.v:3833.28-3833.63" - cell $eq $eq$ls180.v:3833$1153 + attribute \src "ls180.v:3824.28-3824.63" + cell $eq $eq$ls180.v:3824$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -255928,10 +255720,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:3833$1153_Y + connect \Y $eq$ls180.v:3824$1153_Y end - attribute \src "ls180.v:3833.126-3833.164" - cell $eq $eq$ls180.v:3833$1154 + attribute \src "ls180.v:3824.126-3824.164" + cell $eq $eq$ls180.v:3824$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255939,10 +255731,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3833$1154_Y + connect \Y $eq$ls180.v:3824$1154_Y end - attribute \src "ls180.v:3833.201-3833.239" - cell $eq $eq$ls180.v:3833$1157 + attribute \src "ls180.v:3824.201-3824.239" + cell $eq $eq$ls180.v:3824$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255950,10 +255742,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3833$1157_Y + connect \Y $eq$ls180.v:3824$1157_Y end - attribute \src "ls180.v:3833.276-3833.314" - cell $eq $eq$ls180.v:3833$1160 + attribute \src "ls180.v:3824.276-3824.314" + cell $eq $eq$ls180.v:3824$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255961,10 +255753,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3833$1160_Y + connect \Y $eq$ls180.v:3824$1160_Y end - attribute \src "ls180.v:4365.8-4365.33" - cell $eq $eq$ls180.v:4365$1260 + attribute \src "ls180.v:4360.8-4360.33" + cell $eq $eq$ls180.v:4360$1264 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255972,10 +255764,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_value connect \B 1'0 - connect \Y $eq$ls180.v:4365$1260_Y + connect \Y $eq$ls180.v:4360$1264_Y end - attribute \src "ls180.v:4400.8-4400.37" - cell $eq $eq$ls180.v:4400$1271 + attribute \src "ls180.v:4395.8-4395.37" + cell $eq $eq$ls180.v:4395$1275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255983,10 +255775,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_postponer_count connect \B 1'0 - connect \Y $eq$ls180.v:4400$1271_Y + connect \Y $eq$ls180.v:4395$1275_Y end - attribute \src "ls180.v:4420.33-4420.64" - cell $eq $eq$ls180.v:4420$1274 + attribute \src "ls180.v:4415.33-4415.64" + cell $eq $eq$ls180.v:4415$1278 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255994,10 +255786,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_counter connect \B 1'0 - connect \Y $eq$ls180.v:4420$1274_Y + connect \Y $eq$ls180.v:4415$1278_Y end - attribute \src "ls180.v:4427.7-4427.38" - cell $eq $eq$ls180.v:4427$1276 + attribute \src "ls180.v:4422.7-4422.38" + cell $eq $eq$ls180.v:4422$1280 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256005,10 +255797,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_counter connect \B 2'10 - connect \Y $eq$ls180.v:4427$1276_Y + connect \Y $eq$ls180.v:4422$1280_Y end - attribute \src "ls180.v:4434.7-4434.38" - cell $eq $eq$ls180.v:4434$1277 + attribute \src "ls180.v:4429.7-4429.38" + cell $eq $eq$ls180.v:4429$1281 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256016,10 +255808,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:4434$1277_Y + connect \Y $eq$ls180.v:4429$1281_Y end - attribute \src "ls180.v:4442.7-4442.38" - cell $eq $eq$ls180.v:4442$1278 + attribute \src "ls180.v:4437.7-4437.38" + cell $eq $eq$ls180.v:4437$1282 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256027,10 +255819,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:4442$1278_Y + connect \Y $eq$ls180.v:4437$1282_Y end - attribute \src "ls180.v:4494.9-4494.49" - cell $eq $eq$ls180.v:4494$1296 + attribute \src "ls180.v:4489.9-4489.49" + cell $eq $eq$ls180.v:4489$1300 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -256038,10 +255830,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:4494$1296_Y + connect \Y $eq$ls180.v:4489$1300_Y end - attribute \src "ls180.v:4540.9-4540.49" - cell $eq $eq$ls180.v:4540$1312 + attribute \src "ls180.v:4535.9-4535.49" + cell $eq $eq$ls180.v:4535$1316 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -256049,10 +255841,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:4540$1312_Y + connect \Y $eq$ls180.v:4535$1316_Y end - attribute \src "ls180.v:4586.9-4586.49" - cell $eq $eq$ls180.v:4586$1328 + attribute \src "ls180.v:4581.9-4581.49" + cell $eq $eq$ls180.v:4581$1332 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -256060,10 +255852,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:4586$1328_Y + connect \Y $eq$ls180.v:4581$1332_Y end - attribute \src "ls180.v:4632.9-4632.49" - cell $eq $eq$ls180.v:4632$1344 + attribute \src "ls180.v:4627.9-4627.49" + cell $eq $eq$ls180.v:4627$1348 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -256071,10 +255863,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:4632$1344_Y + connect \Y $eq$ls180.v:4627$1348_Y end - attribute \src "ls180.v:4782.9-4782.36" - cell $eq $eq$ls180.v:4782$1356 + attribute \src "ls180.v:4777.9-4777.36" + cell $eq $eq$ls180.v:4777$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256082,10 +255874,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_tccdcon_count connect \B 1'1 - connect \Y $eq$ls180.v:4782$1356_Y + connect \Y $eq$ls180.v:4777$1360_Y end - attribute \src "ls180.v:4797.9-4797.36" - cell $eq $eq$ls180.v:4797$1359 + attribute \src "ls180.v:4792.9-4792.36" + cell $eq $eq$ls180.v:4792$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -256093,10 +255885,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_twtrcon_count connect \B 1'1 - connect \Y $eq$ls180.v:4797$1359_Y + connect \Y $eq$ls180.v:4792$1363_Y end - attribute \src "ls180.v:4803.54-4803.92" - cell $eq $eq$ls180.v:4803$1360 + attribute \src "ls180.v:4798.54-4798.92" + cell $eq $eq$ls180.v:4798$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256104,10 +255896,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4803$1360_Y + connect \Y $eq$ls180.v:4798$1364_Y end - attribute \src "ls180.v:4803.136-4803.174" - cell $eq $eq$ls180.v:4803$1363 + attribute \src "ls180.v:4798.136-4798.174" + cell $eq $eq$ls180.v:4798$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256115,10 +255907,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4803$1363_Y + connect \Y $eq$ls180.v:4798$1367_Y end - attribute \src "ls180.v:4803.218-4803.256" - cell $eq $eq$ls180.v:4803$1366 + attribute \src "ls180.v:4798.218-4798.256" + cell $eq $eq$ls180.v:4798$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256126,10 +255918,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4803$1366_Y + connect \Y $eq$ls180.v:4798$1370_Y end - attribute \src "ls180.v:4803.300-4803.338" - cell $eq $eq$ls180.v:4803$1369 + attribute \src "ls180.v:4798.300-4798.338" + cell $eq $eq$ls180.v:4798$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256137,10 +255929,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4803$1369_Y + connect \Y $eq$ls180.v:4798$1373_Y end - attribute \src "ls180.v:4804.55-4804.93" - cell $eq $eq$ls180.v:4804$1372 + attribute \src "ls180.v:4799.55-4799.93" + cell $eq $eq$ls180.v:4799$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256148,10 +255940,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4804$1372_Y + connect \Y $eq$ls180.v:4799$1376_Y end - attribute \src "ls180.v:4804.137-4804.175" - cell $eq $eq$ls180.v:4804$1375 + attribute \src "ls180.v:4799.137-4799.175" + cell $eq $eq$ls180.v:4799$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256159,10 +255951,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4804$1375_Y + connect \Y $eq$ls180.v:4799$1379_Y end - attribute \src "ls180.v:4804.219-4804.257" - cell $eq $eq$ls180.v:4804$1378 + attribute \src "ls180.v:4799.219-4799.257" + cell $eq $eq$ls180.v:4799$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256170,10 +255962,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4804$1378_Y + connect \Y $eq$ls180.v:4799$1382_Y end - attribute \src "ls180.v:4804.301-4804.339" - cell $eq $eq$ls180.v:4804$1381 + attribute \src "ls180.v:4799.301-4799.339" + cell $eq $eq$ls180.v:4799$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256181,10 +255973,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4804$1381_Y + connect \Y $eq$ls180.v:4799$1385_Y end - attribute \src "ls180.v:4839.9-4839.37" - cell $eq $eq$ls180.v:4839$1393 + attribute \src "ls180.v:4834.9-4834.37" + cell $eq $eq$ls180.v:4834$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256192,10 +255984,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \uart_phy_tx_bitcount connect \B 4'1000 - connect \Y $eq$ls180.v:4839$1393_Y + connect \Y $eq$ls180.v:4834$1397_Y end - attribute \src "ls180.v:4842.10-4842.38" - cell $eq $eq$ls180.v:4842$1394 + attribute \src "ls180.v:4837.10-4837.38" + cell $eq $eq$ls180.v:4837$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256203,10 +255995,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \uart_phy_tx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:4842$1394_Y + connect \Y $eq$ls180.v:4837$1398_Y end - attribute \src "ls180.v:4868.9-4868.37" - cell $eq $eq$ls180.v:4868$1400 + attribute \src "ls180.v:4863.9-4863.37" + cell $eq $eq$ls180.v:4863$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256214,10 +256006,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \uart_phy_rx_bitcount connect \B 1'0 - connect \Y $eq$ls180.v:4868$1400_Y + connect \Y $eq$ls180.v:4863$1404_Y end - attribute \src "ls180.v:4873.10-4873.38" - cell $eq $eq$ls180.v:4873$1401 + attribute \src "ls180.v:4868.10-4868.38" + cell $eq $eq$ls180.v:4868$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256225,10 +256017,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \uart_phy_rx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:4873$1401_Y + connect \Y $eq$ls180.v:4868$1405_Y end - attribute \src "ls180.v:5507.28-5507.31" - cell $memrd $memrd$\mem$ls180.v:5507$1459 + attribute \src "ls180.v:5502.28-5502.31" + cell $memrd $memrd$\mem$ls180.v:5502$1463 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256237,11 +256029,11 @@ module \ls180 parameter \WIDTH 32 connect \ADDR \memadr connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:5507$1459_DATA + connect \DATA $memrd$\mem$ls180.v:5502$1463_DATA connect \EN 1'x end - attribute \src "ls180.v:5527.20-5527.25" - cell $memrd $memrd$\mem_1$ls180.v:5527$1485 + attribute \src "ls180.v:5522.20-5522.25" + cell $memrd $memrd$\mem_1$ls180.v:5522$1489 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256250,11 +256042,11 @@ module \ls180 parameter \WIDTH 32 connect \ADDR \memadr_1 connect \CLK 1'x - connect \DATA $memrd$\mem_1$ls180.v:5527$1485_DATA + connect \DATA $memrd$\mem_1$ls180.v:5522$1489_DATA connect \EN 1'x end - attribute \src "ls180.v:5538.12-5538.19" - cell $memrd $memrd$\storage$ls180.v:5538$1493 + attribute \src "ls180.v:5533.12-5533.19" + cell $memrd $memrd$\storage$ls180.v:5533$1497 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256263,11 +256055,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:5538$1493_DATA + connect \DATA $memrd$\storage$ls180.v:5533$1497_DATA connect \EN 1'x end - attribute \src "ls180.v:5545.63-5545.70" - cell $memrd $memrd$\storage$ls180.v:5545$1495 + attribute \src "ls180.v:5540.63-5540.70" + cell $memrd $memrd$\storage$ls180.v:5540$1499 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256276,11 +256068,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:5545$1495_DATA + connect \DATA $memrd$\storage$ls180.v:5540$1499_DATA connect \EN 1'x end - attribute \src "ls180.v:5552.14-5552.23" - cell $memrd $memrd$\storage_1$ls180.v:5552$1503 + attribute \src "ls180.v:5547.14-5547.23" + cell $memrd $memrd$\storage_1$ls180.v:5547$1507 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256289,11 +256081,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:5552$1503_DATA + connect \DATA $memrd$\storage_1$ls180.v:5547$1507_DATA connect \EN 1'x end - attribute \src "ls180.v:5559.63-5559.72" - cell $memrd $memrd$\storage_1$ls180.v:5559$1505 + attribute \src "ls180.v:5554.63-5554.72" + cell $memrd $memrd$\storage_1$ls180.v:5554$1509 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256302,11 +256094,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:5559$1505_DATA + connect \DATA $memrd$\storage_1$ls180.v:5554$1509_DATA connect \EN 1'x end - attribute \src "ls180.v:5566.14-5566.23" - cell $memrd $memrd$\storage_2$ls180.v:5566$1513 + attribute \src "ls180.v:5561.14-5561.23" + cell $memrd $memrd$\storage_2$ls180.v:5561$1517 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256315,11 +256107,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:5566$1513_DATA + connect \DATA $memrd$\storage_2$ls180.v:5561$1517_DATA connect \EN 1'x end - attribute \src "ls180.v:5573.63-5573.72" - cell $memrd $memrd$\storage_2$ls180.v:5573$1515 + attribute \src "ls180.v:5568.63-5568.72" + cell $memrd $memrd$\storage_2$ls180.v:5568$1519 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256328,11 +256120,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:5573$1515_DATA + connect \DATA $memrd$\storage_2$ls180.v:5568$1519_DATA connect \EN 1'x end - attribute \src "ls180.v:5580.14-5580.23" - cell $memrd $memrd$\storage_3$ls180.v:5580$1523 + attribute \src "ls180.v:5575.14-5575.23" + cell $memrd $memrd$\storage_3$ls180.v:5575$1527 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256341,11 +256133,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:5580$1523_DATA + connect \DATA $memrd$\storage_3$ls180.v:5575$1527_DATA connect \EN 1'x end - attribute \src "ls180.v:5587.63-5587.72" - cell $memrd $memrd$\storage_3$ls180.v:5587$1525 + attribute \src "ls180.v:5582.63-5582.72" + cell $memrd $memrd$\storage_3$ls180.v:5582$1529 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256354,11 +256146,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:5587$1525_DATA + connect \DATA $memrd$\storage_3$ls180.v:5582$1529_DATA connect \EN 1'x end - attribute \src "ls180.v:5595.14-5595.23" - cell $memrd $memrd$\storage_4$ls180.v:5595$1533 + attribute \src "ls180.v:5590.14-5590.23" + cell $memrd $memrd$\storage_4$ls180.v:5590$1537 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256367,11 +256159,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \tx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:5595$1533_DATA + connect \DATA $memrd$\storage_4$ls180.v:5590$1537_DATA connect \EN 1'x end - attribute \src "ls180.v:5600.15-5600.24" - cell $memrd $memrd$\storage_4$ls180.v:5600$1535 + attribute \src "ls180.v:5595.15-5595.24" + cell $memrd $memrd$\storage_4$ls180.v:5595$1539 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256380,11 +256172,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \tx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:5600$1535_DATA + connect \DATA $memrd$\storage_4$ls180.v:5595$1539_DATA connect \EN 1'x end - attribute \src "ls180.v:5612.14-5612.23" - cell $memrd $memrd$\storage_5$ls180.v:5612$1543 + attribute \src "ls180.v:5607.14-5607.23" + cell $memrd $memrd$\storage_5$ls180.v:5607$1547 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256393,11 +256185,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \rx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:5612$1543_DATA + connect \DATA $memrd$\storage_5$ls180.v:5607$1547_DATA connect \EN 1'x end - attribute \src "ls180.v:5617.15-5617.24" - cell $memrd $memrd$\storage_5$ls180.v:5617$1545 + attribute \src "ls180.v:5612.15-5612.24" + cell $memrd $memrd$\storage_5$ls180.v:5612$1549 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -256406,11 +256198,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \rx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:5617$1545_DATA + connect \DATA $memrd$\storage_5$ls180.v:5612$1549_DATA connect \EN 1'x end - attribute \src "ls180.v:1711.36-1711.61" - cell $ne $ne$ls180.v:1711$63 + attribute \src "ls180.v:1702.36-1702.61" + cell $ne $ne$ls180.v:1702$63 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -256418,10 +256210,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_value connect \B 1'0 - connect \Y $ne$ls180.v:1711$63_Y + connect \Y $ne$ls180.v:1702$63_Y end - attribute \src "ls180.v:1882.60-1882.89" - cell $ne $ne$ls180.v:1882$90 + attribute \src "ls180.v:1873.60-1873.89" + cell $ne $ne$ls180.v:1873$90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256429,10 +256221,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:1882$90_Y + connect \Y $ne$ls180.v:1873$90_Y end - attribute \src "ls180.v:1943.8-1943.132" - cell $ne $ne$ls180.v:1943$109 + attribute \src "ls180.v:1934.8-1934.132" + cell $ne $ne$ls180.v:1934$109 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -256440,10 +256232,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:1943$109_Y + connect \Y $ne$ls180.v:1934$109_Y end - attribute \src "ls180.v:1975.70-1975.123" - cell $ne $ne$ls180.v:1975$116 + attribute \src "ls180.v:1966.70-1966.123" + cell $ne $ne$ls180.v:1966$116 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256451,10 +256243,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:1975$116_Y + connect \Y $ne$ls180.v:1966$116_Y end - attribute \src "ls180.v:1976.70-1976.123" - cell $ne $ne$ls180.v:1976$117 + attribute \src "ls180.v:1967.70-1967.123" + cell $ne $ne$ls180.v:1967$117 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256462,10 +256254,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:1976$117_Y + connect \Y $ne$ls180.v:1967$117_Y end - attribute \src "ls180.v:2100.8-2100.132" - cell $ne $ne$ls180.v:2100$139 + attribute \src "ls180.v:2091.8-2091.132" + cell $ne $ne$ls180.v:2091$139 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -256473,10 +256265,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:2100$139_Y + connect \Y $ne$ls180.v:2091$139_Y end - attribute \src "ls180.v:2132.70-2132.123" - cell $ne $ne$ls180.v:2132$146 + attribute \src "ls180.v:2123.70-2123.123" + cell $ne $ne$ls180.v:2123$146 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256484,10 +256276,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:2132$146_Y + connect \Y $ne$ls180.v:2123$146_Y end - attribute \src "ls180.v:2133.70-2133.123" - cell $ne $ne$ls180.v:2133$147 + attribute \src "ls180.v:2124.70-2124.123" + cell $ne $ne$ls180.v:2124$147 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256495,10 +256287,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:2133$147_Y + connect \Y $ne$ls180.v:2124$147_Y end - attribute \src "ls180.v:2257.8-2257.132" - cell $ne $ne$ls180.v:2257$169 + attribute \src "ls180.v:2248.8-2248.132" + cell $ne $ne$ls180.v:2248$169 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -256506,10 +256298,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:2257$169_Y + connect \Y $ne$ls180.v:2248$169_Y end - attribute \src "ls180.v:2289.70-2289.123" - cell $ne $ne$ls180.v:2289$176 + attribute \src "ls180.v:2280.70-2280.123" + cell $ne $ne$ls180.v:2280$176 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256517,10 +256309,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:2289$176_Y + connect \Y $ne$ls180.v:2280$176_Y end - attribute \src "ls180.v:2290.70-2290.123" - cell $ne $ne$ls180.v:2290$177 + attribute \src "ls180.v:2281.70-2281.123" + cell $ne $ne$ls180.v:2281$177 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256528,10 +256320,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:2290$177_Y + connect \Y $ne$ls180.v:2281$177_Y end - attribute \src "ls180.v:2414.8-2414.132" - cell $ne $ne$ls180.v:2414$199 + attribute \src "ls180.v:2405.8-2405.132" + cell $ne $ne$ls180.v:2405$199 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -256539,10 +256331,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:2414$199_Y + connect \Y $ne$ls180.v:2405$199_Y end - attribute \src "ls180.v:2446.70-2446.123" - cell $ne $ne$ls180.v:2446$206 + attribute \src "ls180.v:2437.70-2437.123" + cell $ne $ne$ls180.v:2437$206 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256550,10 +256342,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:2446$206_Y + connect \Y $ne$ls180.v:2437$206_Y end - attribute \src "ls180.v:2447.70-2447.123" - cell $ne $ne$ls180.v:2447$207 + attribute \src "ls180.v:2438.70-2438.123" + cell $ne $ne$ls180.v:2438$207 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256561,10 +256353,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:2447$207_Y + connect \Y $ne$ls180.v:2438$207_Y end - attribute \src "ls180.v:2939.37-2939.60" - cell $ne $ne$ls180.v:2939$605 + attribute \src "ls180.v:2930.37-2930.60" + cell $ne $ne$ls180.v:2930$605 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -256572,10 +256364,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \tx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:2939$605_Y + connect \Y $ne$ls180.v:2930$605_Y end - attribute \src "ls180.v:2940.37-2940.59" - cell $ne $ne$ls180.v:2940$606 + attribute \src "ls180.v:2931.37-2931.59" + cell $ne $ne$ls180.v:2931$606 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -256583,10 +256375,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \tx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:2940$606_Y + connect \Y $ne$ls180.v:2931$606_Y end - attribute \src "ls180.v:2969.37-2969.60" - cell $ne $ne$ls180.v:2969$616 + attribute \src "ls180.v:2960.37-2960.60" + cell $ne $ne$ls180.v:2960$616 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -256594,10 +256386,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \rx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:2969$616_Y + connect \Y $ne$ls180.v:2960$616_Y end - attribute \src "ls180.v:2970.37-2970.59" - cell $ne $ne$ls180.v:2970$617 + attribute \src "ls180.v:2961.37-2961.59" + cell $ne $ne$ls180.v:2961$617 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -256605,10 +256397,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \rx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:2970$617_Y + connect \Y $ne$ls180.v:2961$617_Y end - attribute \src "ls180.v:3065.99-3065.143" - cell $ne $ne$ls180.v:3065$624 + attribute \src "ls180.v:3056.99-3056.143" + cell $ne $ne$ls180.v:3056$624 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256616,10 +256408,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_libresocsim_wishbone_sel connect \B 1'0 - connect \Y $ne$ls180.v:3065$624_Y + connect \Y $ne$ls180.v:3056$624_Y end - attribute \src "ls180.v:4355.7-4355.47" - cell $ne $ne$ls180.v:4355$1255 + attribute \src "ls180.v:4350.7-4350.47" + cell $ne $ne$ls180.v:4350$1259 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -256627,10 +256419,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_bus_errors connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:4355$1255_Y + connect \Y $ne$ls180.v:4350$1259_Y end - attribute \src "ls180.v:4409.9-4409.38" - cell $ne $ne$ls180.v:4409$1272 + attribute \src "ls180.v:4404.9-4404.38" + cell $ne $ne$ls180.v:4404$1276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256638,10 +256430,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:4409$1272_Y + connect \Y $ne$ls180.v:4404$1276_Y end - attribute \src "ls180.v:4445.8-4445.39" - cell $ne $ne$ls180.v:4445$1279 + attribute \src "ls180.v:4440.8-4440.39" + cell $ne $ne$ls180.v:4440$1283 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -256649,1642 +256441,1642 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_counter connect \B 1'0 - connect \Y $ne$ls180.v:4445$1279_Y + connect \Y $ne$ls180.v:4440$1283_Y end - attribute \src "ls180.v:1519.40-1519.70" - cell $not $not$ls180.v:1519$17 + attribute \src "ls180.v:1510.40-1510.70" + cell $not $not$ls180.v:1510$17 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_ibus_cyc - connect \Y $not$ls180.v:1519$17_Y + connect \Y $not$ls180.v:1510$17_Y end - attribute \src "ls180.v:1558.56-1558.84" - cell $not $not$ls180.v:1558$22 + attribute \src "ls180.v:1549.56-1549.84" + cell $not $not$ls180.v:1549$22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter0_skip - connect \Y $not$ls180.v:1558$22_Y + connect \Y $not$ls180.v:1549$22_Y end - attribute \src "ls180.v:1559.56-1559.84" - cell $not $not$ls180.v:1559$23 + attribute \src "ls180.v:1550.56-1550.84" + cell $not $not$ls180.v:1550$23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter0_skip - connect \Y $not$ls180.v:1559$23_Y + connect \Y $not$ls180.v:1550$23_Y end - attribute \src "ls180.v:1579.40-1579.70" - cell $not $not$ls180.v:1579$28 + attribute \src "ls180.v:1570.40-1570.70" + cell $not $not$ls180.v:1570$28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_dbus_cyc - connect \Y $not$ls180.v:1579$28_Y + connect \Y $not$ls180.v:1570$28_Y end - attribute \src "ls180.v:1618.56-1618.84" - cell $not $not$ls180.v:1618$33 + attribute \src "ls180.v:1609.56-1609.84" + cell $not $not$ls180.v:1609$33 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter1_skip - connect \Y $not$ls180.v:1618$33_Y + connect \Y $not$ls180.v:1609$33_Y end - attribute \src "ls180.v:1619.56-1619.84" - cell $not $not$ls180.v:1619$34 + attribute \src "ls180.v:1610.56-1610.84" + cell $not $not$ls180.v:1610$34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter1_skip - connect \Y $not$ls180.v:1619$34_Y + connect \Y $not$ls180.v:1610$34_Y end - attribute \src "ls180.v:1639.40-1639.73" - cell $not $not$ls180.v:1639$39 + attribute \src "ls180.v:1630.40-1630.73" + cell $not $not$ls180.v:1630$39 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_jtag_wb_cyc - connect \Y $not$ls180.v:1639$39_Y + connect \Y $not$ls180.v:1630$39_Y end - attribute \src "ls180.v:1678.56-1678.84" - cell $not $not$ls180.v:1678$44 + attribute \src "ls180.v:1669.56-1669.84" + cell $not $not$ls180.v:1669$44 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter2_skip - connect \Y $not$ls180.v:1678$44_Y + connect \Y $not$ls180.v:1669$44_Y end - attribute \src "ls180.v:1679.56-1679.84" - cell $not $not$ls180.v:1679$45 + attribute \src "ls180.v:1670.56-1670.84" + cell $not $not$ls180.v:1670$45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter2_skip - connect \Y $not$ls180.v:1679$45_Y + connect \Y $not$ls180.v:1670$45_Y end - attribute \src "ls180.v:1831.29-1831.54" - cell $not $not$ls180.v:1831$82 + attribute \src "ls180.v:1822.29-1822.54" + cell $not $not$ls180.v:1822$82 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_command_storage [0] - connect \Y $not$ls180.v:1831$82_Y + connect \Y $not$ls180.v:1822$82_Y end - attribute \src "ls180.v:1832.26-1832.51" - cell $not $not$ls180.v:1832$83 + attribute \src "ls180.v:1823.26-1823.51" + cell $not $not$ls180.v:1823$83 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_command_storage [1] - connect \Y $not$ls180.v:1832$83_Y + connect \Y $not$ls180.v:1823$83_Y end - attribute \src "ls180.v:1833.27-1833.52" - cell $not $not$ls180.v:1833$84 + attribute \src "ls180.v:1824.27-1824.52" + cell $not $not$ls180.v:1824$84 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_command_storage [2] - connect \Y $not$ls180.v:1833$84_Y + connect \Y $not$ls180.v:1824$84_Y end - attribute \src "ls180.v:1834.27-1834.52" - cell $not $not$ls180.v:1834$85 + attribute \src "ls180.v:1825.27-1825.52" + cell $not $not$ls180.v:1825$85 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_command_storage [3] - connect \Y $not$ls180.v:1834$85_Y + connect \Y $not$ls180.v:1825$85_Y end - attribute \src "ls180.v:1876.28-1876.46" - cell $not $not$ls180.v:1876$88 + attribute \src "ls180.v:1867.28-1867.46" + cell $not $not$ls180.v:1867$88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_timer_done0 - connect \Y $not$ls180.v:1876$88_Y + connect \Y $not$ls180.v:1867$88_Y end - attribute \src "ls180.v:1977.53-1977.96" - cell $not $not$ls180.v:1977$118 + attribute \src "ls180.v:1968.53-1968.96" + cell $not $not$ls180.v:1968$118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:1977$118_Y + connect \Y $not$ls180.v:1968$118_Y end - attribute \src "ls180.v:2031.9-2031.40" - cell $not $not$ls180.v:2031$123 + attribute \src "ls180.v:2022.9-2022.40" + cell $not $not$ls180.v:2022$123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:2031$123_Y + connect \Y $not$ls180.v:2022$123_Y end - attribute \src "ls180.v:2134.53-2134.96" - cell $not $not$ls180.v:2134$148 + attribute \src "ls180.v:2125.53-2125.96" + cell $not $not$ls180.v:2125$148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:2134$148_Y + connect \Y $not$ls180.v:2125$148_Y end - attribute \src "ls180.v:2188.9-2188.40" - cell $not $not$ls180.v:2188$153 + attribute \src "ls180.v:2179.9-2179.40" + cell $not $not$ls180.v:2179$153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:2188$153_Y + connect \Y $not$ls180.v:2179$153_Y end - attribute \src "ls180.v:2291.53-2291.96" - cell $not $not$ls180.v:2291$178 + attribute \src "ls180.v:2282.53-2282.96" + cell $not $not$ls180.v:2282$178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:2291$178_Y + connect \Y $not$ls180.v:2282$178_Y end - attribute \src "ls180.v:2345.9-2345.40" - cell $not $not$ls180.v:2345$183 + attribute \src "ls180.v:2336.9-2336.40" + cell $not $not$ls180.v:2336$183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:2345$183_Y + connect \Y $not$ls180.v:2336$183_Y end - attribute \src "ls180.v:2448.53-2448.96" - cell $not $not$ls180.v:2448$208 + attribute \src "ls180.v:2439.53-2439.96" + cell $not $not$ls180.v:2439$208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:2448$208_Y + connect \Y $not$ls180.v:2439$208_Y end - attribute \src "ls180.v:2502.9-2502.40" - cell $not $not$ls180.v:2502$213 + attribute \src "ls180.v:2493.9-2493.40" + cell $not $not$ls180.v:2493$213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:2502$213_Y + connect \Y $not$ls180.v:2493$213_Y end - attribute \src "ls180.v:2544.129-2544.162" - cell $not $not$ls180.v:2544$216 + attribute \src "ls180.v:2535.129-2535.162" + cell $not $not$ls180.v:2535$216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:2544$216_Y + connect \Y $not$ls180.v:2535$216_Y end - attribute \src "ls180.v:2544.168-2544.200" - cell $not $not$ls180.v:2544$218 + attribute \src "ls180.v:2535.168-2535.200" + cell $not $not$ls180.v:2535$218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:2544$218_Y + connect \Y $not$ls180.v:2535$218_Y end - attribute \src "ls180.v:2545.129-2545.162" - cell $not $not$ls180.v:2545$222 + attribute \src "ls180.v:2536.129-2536.162" + cell $not $not$ls180.v:2536$222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:2545$222_Y + connect \Y $not$ls180.v:2536$222_Y end - attribute \src "ls180.v:2545.168-2545.200" - cell $not $not$ls180.v:2545$224 + attribute \src "ls180.v:2536.168-2536.200" + cell $not $not$ls180.v:2536$224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:2545$224_Y + connect \Y $not$ls180.v:2536$224_Y end - attribute \src "ls180.v:2561.38-2561.63" - cell $not $not$ls180.v:2561$252 + attribute \src "ls180.v:2552.38-2552.63" + cell $not $not$ls180.v:2552$252 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \sdram_interface_wdata_we - connect \Y $not$ls180.v:2561$252_Y + connect \Y $not$ls180.v:2552$252_Y end - attribute \src "ls180.v:2564.180-2564.215" - cell $not $not$ls180.v:2564$255 + attribute \src "ls180.v:2555.180-2555.215" + cell $not $not$ls180.v:2555$255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:2564$255_Y + connect \Y $not$ls180.v:2555$255_Y end - attribute \src "ls180.v:2564.221-2564.255" - cell $not $not$ls180.v:2564$257 + attribute \src "ls180.v:2555.221-2555.255" + cell $not $not$ls180.v:2555$257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:2564$257_Y + connect \Y $not$ls180.v:2555$257_Y end - attribute \src "ls180.v:2564.139-2564.257" - cell $not $not$ls180.v:2564$259 + attribute \src "ls180.v:2555.139-2555.257" + cell $not $not$ls180.v:2555$259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2564$258_Y - connect \Y $not$ls180.v:2564$259_Y + connect \A $and$ls180.v:2555$258_Y + connect \Y $not$ls180.v:2555$259_Y end - attribute \src "ls180.v:2565.180-2565.215" - cell $not $not$ls180.v:2565$268 + attribute \src "ls180.v:2556.180-2556.215" + cell $not $not$ls180.v:2556$268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:2565$268_Y + connect \Y $not$ls180.v:2556$268_Y end - attribute \src "ls180.v:2565.221-2565.255" - cell $not $not$ls180.v:2565$270 + attribute \src "ls180.v:2556.221-2556.255" + cell $not $not$ls180.v:2556$270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:2565$270_Y + connect \Y $not$ls180.v:2556$270_Y end - attribute \src "ls180.v:2565.139-2565.257" - cell $not $not$ls180.v:2565$272 + attribute \src "ls180.v:2556.139-2556.257" + cell $not $not$ls180.v:2556$272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2565$271_Y - connect \Y $not$ls180.v:2565$272_Y + connect \A $and$ls180.v:2556$271_Y + connect \Y $not$ls180.v:2556$272_Y end - attribute \src "ls180.v:2566.180-2566.215" - cell $not $not$ls180.v:2566$281 + attribute \src "ls180.v:2557.180-2557.215" + cell $not $not$ls180.v:2557$281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:2566$281_Y + connect \Y $not$ls180.v:2557$281_Y end - attribute \src "ls180.v:2566.221-2566.255" - cell $not $not$ls180.v:2566$283 + attribute \src "ls180.v:2557.221-2557.255" + cell $not $not$ls180.v:2557$283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:2566$283_Y + connect \Y $not$ls180.v:2557$283_Y end - attribute \src "ls180.v:2566.139-2566.257" - cell $not $not$ls180.v:2566$285 + attribute \src "ls180.v:2557.139-2557.257" + cell $not $not$ls180.v:2557$285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2566$284_Y - connect \Y $not$ls180.v:2566$285_Y + connect \A $and$ls180.v:2557$284_Y + connect \Y $not$ls180.v:2557$285_Y end - attribute \src "ls180.v:2567.180-2567.215" - cell $not $not$ls180.v:2567$294 + attribute \src "ls180.v:2558.180-2558.215" + cell $not $not$ls180.v:2558$294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:2567$294_Y + connect \Y $not$ls180.v:2558$294_Y end - attribute \src "ls180.v:2567.221-2567.255" - cell $not $not$ls180.v:2567$296 + attribute \src "ls180.v:2558.221-2558.255" + cell $not $not$ls180.v:2558$296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:2567$296_Y + connect \Y $not$ls180.v:2558$296_Y end - attribute \src "ls180.v:2567.139-2567.257" - cell $not $not$ls180.v:2567$298 + attribute \src "ls180.v:2558.139-2558.257" + cell $not $not$ls180.v:2558$298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2567$297_Y - connect \Y $not$ls180.v:2567$298_Y + connect \A $and$ls180.v:2558$297_Y + connect \Y $not$ls180.v:2558$298_Y end - attribute \src "ls180.v:2594.61-2594.88" - cell $not $not$ls180.v:2594$309 + attribute \src "ls180.v:2585.61-2585.88" + cell $not $not$ls180.v:2585$309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:2594$309_Y + connect \Y $not$ls180.v:2585$309_Y end - attribute \src "ls180.v:2597.180-2597.215" - cell $not $not$ls180.v:2597$313 + attribute \src "ls180.v:2588.180-2588.215" + cell $not $not$ls180.v:2588$313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:2597$313_Y + connect \Y $not$ls180.v:2588$313_Y end - attribute \src "ls180.v:2597.221-2597.255" - cell $not $not$ls180.v:2597$315 + attribute \src "ls180.v:2588.221-2588.255" + cell $not $not$ls180.v:2588$315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:2597$315_Y + connect \Y $not$ls180.v:2588$315_Y end - attribute \src "ls180.v:2597.139-2597.257" - cell $not $not$ls180.v:2597$317 + attribute \src "ls180.v:2588.139-2588.257" + cell $not $not$ls180.v:2588$317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2597$316_Y - connect \Y $not$ls180.v:2597$317_Y + connect \A $and$ls180.v:2588$316_Y + connect \Y $not$ls180.v:2588$317_Y end - attribute \src "ls180.v:2598.180-2598.215" - cell $not $not$ls180.v:2598$326 + attribute \src "ls180.v:2589.180-2589.215" + cell $not $not$ls180.v:2589$326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:2598$326_Y + connect \Y $not$ls180.v:2589$326_Y end - attribute \src "ls180.v:2598.221-2598.255" - cell $not $not$ls180.v:2598$328 + attribute \src "ls180.v:2589.221-2589.255" + cell $not $not$ls180.v:2589$328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:2598$328_Y + connect \Y $not$ls180.v:2589$328_Y end - attribute \src "ls180.v:2598.139-2598.257" - cell $not $not$ls180.v:2598$330 + attribute \src "ls180.v:2589.139-2589.257" + cell $not $not$ls180.v:2589$330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2598$329_Y - connect \Y $not$ls180.v:2598$330_Y + connect \A $and$ls180.v:2589$329_Y + connect \Y $not$ls180.v:2589$330_Y end - attribute \src "ls180.v:2599.180-2599.215" - cell $not $not$ls180.v:2599$339 + attribute \src "ls180.v:2590.180-2590.215" + cell $not $not$ls180.v:2590$339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:2599$339_Y + connect \Y $not$ls180.v:2590$339_Y end - attribute \src "ls180.v:2599.221-2599.255" - cell $not $not$ls180.v:2599$341 + attribute \src "ls180.v:2590.221-2590.255" + cell $not $not$ls180.v:2590$341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:2599$341_Y + connect \Y $not$ls180.v:2590$341_Y end - attribute \src "ls180.v:2599.139-2599.257" - cell $not $not$ls180.v:2599$343 + attribute \src "ls180.v:2590.139-2590.257" + cell $not $not$ls180.v:2590$343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2599$342_Y - connect \Y $not$ls180.v:2599$343_Y + connect \A $and$ls180.v:2590$342_Y + connect \Y $not$ls180.v:2590$343_Y end - attribute \src "ls180.v:2600.180-2600.215" - cell $not $not$ls180.v:2600$352 + attribute \src "ls180.v:2591.180-2591.215" + cell $not $not$ls180.v:2591$352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:2600$352_Y + connect \Y $not$ls180.v:2591$352_Y end - attribute \src "ls180.v:2600.221-2600.255" - cell $not $not$ls180.v:2600$354 + attribute \src "ls180.v:2591.221-2591.255" + cell $not $not$ls180.v:2591$354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:2600$354_Y + connect \Y $not$ls180.v:2591$354_Y end - attribute \src "ls180.v:2600.139-2600.257" - cell $not $not$ls180.v:2600$356 + attribute \src "ls180.v:2591.139-2591.257" + cell $not $not$ls180.v:2591$356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2600$355_Y - connect \Y $not$ls180.v:2600$356_Y + connect \A $and$ls180.v:2591$355_Y + connect \Y $not$ls180.v:2591$356_Y end - attribute \src "ls180.v:2663.61-2663.88" - cell $not $not$ls180.v:2663$395 + attribute \src "ls180.v:2654.61-2654.88" + cell $not $not$ls180.v:2654$395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:2663$395_Y + connect \Y $not$ls180.v:2654$395_Y end - attribute \src "ls180.v:2684.97-2684.130" - cell $not $not$ls180.v:2684$398 + attribute \src "ls180.v:2675.97-2675.130" + cell $not $not$ls180.v:2675$398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:2684$398_Y + connect \Y $not$ls180.v:2675$398_Y end - attribute \src "ls180.v:2684.136-2684.168" - cell $not $not$ls180.v:2684$400 + attribute \src "ls180.v:2675.136-2675.168" + cell $not $not$ls180.v:2675$400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:2684$400_Y + connect \Y $not$ls180.v:2675$400_Y end - attribute \src "ls180.v:2684.58-2684.170" - cell $not $not$ls180.v:2684$402 + attribute \src "ls180.v:2675.58-2675.170" + cell $not $not$ls180.v:2675$402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2684$401_Y - connect \Y $not$ls180.v:2684$402_Y + connect \A $and$ls180.v:2675$401_Y + connect \Y $not$ls180.v:2675$402_Y end - attribute \src "ls180.v:2692.11-2692.33" - cell $not $not$ls180.v:2692$405 + attribute \src "ls180.v:2683.11-2683.33" + cell $not $not$ls180.v:2683$405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_write_available - connect \Y $not$ls180.v:2692$405_Y + connect \Y $not$ls180.v:2683$405_Y end - attribute \src "ls180.v:2722.97-2722.130" - cell $not $not$ls180.v:2722$407 + attribute \src "ls180.v:2713.97-2713.130" + cell $not $not$ls180.v:2713$407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:2722$407_Y + connect \Y $not$ls180.v:2713$407_Y end - attribute \src "ls180.v:2722.136-2722.168" - cell $not $not$ls180.v:2722$409 + attribute \src "ls180.v:2713.136-2713.168" + cell $not $not$ls180.v:2713$409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:2722$409_Y + connect \Y $not$ls180.v:2713$409_Y end - attribute \src "ls180.v:2722.58-2722.170" - cell $not $not$ls180.v:2722$411 + attribute \src "ls180.v:2713.58-2713.170" + cell $not $not$ls180.v:2713$411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2722$410_Y - connect \Y $not$ls180.v:2722$411_Y + connect \A $and$ls180.v:2713$410_Y + connect \Y $not$ls180.v:2713$411_Y end - attribute \src "ls180.v:2730.11-2730.32" - cell $not $not$ls180.v:2730$414 + attribute \src "ls180.v:2721.11-2721.32" + cell $not $not$ls180.v:2721$414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_read_available - connect \Y $not$ls180.v:2730$414_Y + connect \Y $not$ls180.v:2721$414_Y end - attribute \src "ls180.v:2740.87-2740.336" - cell $not $not$ls180.v:2740$426 + attribute \src "ls180.v:2731.87-2731.336" + cell $not $not$ls180.v:2731$426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2740$425_Y - connect \Y $not$ls180.v:2740$426_Y + connect \A $or$ls180.v:2731$425_Y + connect \Y $not$ls180.v:2731$426_Y end - attribute \src "ls180.v:2741.40-2741.68" - cell $not $not$ls180.v:2741$429 + attribute \src "ls180.v:2732.40-2732.68" + cell $not $not$ls180.v:2732$429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_valid - connect \Y $not$ls180.v:2741$429_Y + connect \Y $not$ls180.v:2732$429_Y end - attribute \src "ls180.v:2741.73-2741.100" - cell $not $not$ls180.v:2741$430 + attribute \src "ls180.v:2732.73-2732.100" + cell $not $not$ls180.v:2732$430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock - connect \Y $not$ls180.v:2741$430_Y + connect \Y $not$ls180.v:2732$430_Y end - attribute \src "ls180.v:2745.87-2745.336" - cell $not $not$ls180.v:2745$442 + attribute \src "ls180.v:2736.87-2736.336" + cell $not $not$ls180.v:2736$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2745$441_Y - connect \Y $not$ls180.v:2745$442_Y + connect \A $or$ls180.v:2736$441_Y + connect \Y $not$ls180.v:2736$442_Y end - attribute \src "ls180.v:2746.40-2746.68" - cell $not $not$ls180.v:2746$445 + attribute \src "ls180.v:2737.40-2737.68" + cell $not $not$ls180.v:2737$445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_valid - connect \Y $not$ls180.v:2746$445_Y + connect \Y $not$ls180.v:2737$445_Y end - attribute \src "ls180.v:2746.73-2746.100" - cell $not $not$ls180.v:2746$446 + attribute \src "ls180.v:2737.73-2737.100" + cell $not $not$ls180.v:2737$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock - connect \Y $not$ls180.v:2746$446_Y + connect \Y $not$ls180.v:2737$446_Y end - attribute \src "ls180.v:2750.87-2750.336" - cell $not $not$ls180.v:2750$458 + attribute \src "ls180.v:2741.87-2741.336" + cell $not $not$ls180.v:2741$458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2750$457_Y - connect \Y $not$ls180.v:2750$458_Y + connect \A $or$ls180.v:2741$457_Y + connect \Y $not$ls180.v:2741$458_Y end - attribute \src "ls180.v:2751.40-2751.68" - cell $not $not$ls180.v:2751$461 + attribute \src "ls180.v:2742.40-2742.68" + cell $not $not$ls180.v:2742$461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_valid - connect \Y $not$ls180.v:2751$461_Y + connect \Y $not$ls180.v:2742$461_Y end - attribute \src "ls180.v:2751.73-2751.100" - cell $not $not$ls180.v:2751$462 + attribute \src "ls180.v:2742.73-2742.100" + cell $not $not$ls180.v:2742$462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock - connect \Y $not$ls180.v:2751$462_Y + connect \Y $not$ls180.v:2742$462_Y end - attribute \src "ls180.v:2755.87-2755.336" - cell $not $not$ls180.v:2755$474 + attribute \src "ls180.v:2746.87-2746.336" + cell $not $not$ls180.v:2746$474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2755$473_Y - connect \Y $not$ls180.v:2755$474_Y + connect \A $or$ls180.v:2746$473_Y + connect \Y $not$ls180.v:2746$474_Y end - attribute \src "ls180.v:2756.40-2756.68" - cell $not $not$ls180.v:2756$477 + attribute \src "ls180.v:2747.40-2747.68" + cell $not $not$ls180.v:2747$477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_valid - connect \Y $not$ls180.v:2756$477_Y + connect \Y $not$ls180.v:2747$477_Y end - attribute \src "ls180.v:2756.73-2756.100" - cell $not $not$ls180.v:2756$478 + attribute \src "ls180.v:2747.73-2747.100" + cell $not $not$ls180.v:2747$478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock - connect \Y $not$ls180.v:2756$478_Y + connect \Y $not$ls180.v:2747$478_Y end - attribute \src "ls180.v:2760.123-2760.372" - cell $not $not$ls180.v:2760$491 + attribute \src "ls180.v:2751.123-2751.372" + cell $not $not$ls180.v:2751$491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$490_Y - connect \Y $not$ls180.v:2760$491_Y + connect \A $or$ls180.v:2751$490_Y + connect \Y $not$ls180.v:2751$491_Y end - attribute \src "ls180.v:2760.497-2760.746" - cell $not $not$ls180.v:2760$507 + attribute \src "ls180.v:2751.497-2751.746" + cell $not $not$ls180.v:2751$507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$506_Y - connect \Y $not$ls180.v:2760$507_Y + connect \A $or$ls180.v:2751$506_Y + connect \Y $not$ls180.v:2751$507_Y end - attribute \src "ls180.v:2760.871-2760.1120" - cell $not $not$ls180.v:2760$523 + attribute \src "ls180.v:2751.871-2751.1120" + cell $not $not$ls180.v:2751$523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$522_Y - connect \Y $not$ls180.v:2760$523_Y + connect \A $or$ls180.v:2751$522_Y + connect \Y $not$ls180.v:2751$523_Y end - attribute \src "ls180.v:2760.1245-2760.1494" - cell $not $not$ls180.v:2760$539 + attribute \src "ls180.v:2751.1245-2751.1494" + cell $not $not$ls180.v:2751$539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$538_Y - connect \Y $not$ls180.v:2760$539_Y + connect \A $or$ls180.v:2751$538_Y + connect \Y $not$ls180.v:2751$539_Y end - attribute \src "ls180.v:2782.27-2782.40" - cell $not $not$ls180.v:2782$545 + attribute \src "ls180.v:2773.27-2773.40" + cell $not $not$ls180.v:2773$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wb_sdram_cyc - connect \Y $not$ls180.v:2782$545_Y + connect \Y $not$ls180.v:2773$545_Y end - attribute \src "ls180.v:2821.25-2821.40" - cell $not $not$ls180.v:2821$550 + attribute \src "ls180.v:2812.25-2812.40" + cell $not $not$ls180.v:2812$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \converter_skip - connect \Y $not$ls180.v:2821$550_Y + connect \Y $not$ls180.v:2812$550_Y end - attribute \src "ls180.v:2822.25-2822.40" - cell $not $not$ls180.v:2822$551 + attribute \src "ls180.v:2813.25-2813.40" + cell $not $not$ls180.v:2813$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \converter_skip - connect \Y $not$ls180.v:2822$551_Y + connect \Y $not$ls180.v:2813$551_Y end - attribute \src "ls180.v:2847.22-2847.38" - cell $not $not$ls180.v:2847$557 + attribute \src "ls180.v:2838.22-2838.38" + cell $not $not$ls180.v:2838$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \litedram_wb_cyc - connect \Y $not$ls180.v:2847$557_Y + connect \Y $not$ls180.v:2838$557_Y end - attribute \src "ls180.v:2848.25-2848.40" - cell $not $not$ls180.v:2848$558 + attribute \src "ls180.v:2839.25-2839.40" + cell $not $not$ls180.v:2839$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \litedram_wb_we - connect \Y $not$ls180.v:2848$558_Y + connect \Y $not$ls180.v:2839$558_Y end - attribute \src "ls180.v:2849.65-2849.78" - cell $not $not$ls180.v:2849$560 + attribute \src "ls180.v:2840.65-2840.78" + cell $not $not$ls180.v:2840$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cmd_consumed - connect \Y $not$ls180.v:2849$560_Y + connect \Y $not$ls180.v:2840$560_Y end - attribute \src "ls180.v:2850.87-2850.102" - cell $not $not$ls180.v:2850$564 + attribute \src "ls180.v:2841.87-2841.102" + cell $not $not$ls180.v:2841$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wdata_consumed - connect \Y $not$ls180.v:2850$564_Y + connect \Y $not$ls180.v:2841$564_Y end - attribute \src "ls180.v:2851.63-2851.83" - cell $not $not$ls180.v:2851$567 + attribute \src "ls180.v:2842.63-2842.83" + cell $not $not$ls180.v:2842$567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_we - connect \Y $not$ls180.v:2851$567_Y + connect \Y $not$ls180.v:2842$567_Y end - attribute \src "ls180.v:2852.71-2852.86" - cell $not $not$ls180.v:2852$570 + attribute \src "ls180.v:2843.71-2843.86" + cell $not $not$ls180.v:2843$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \litedram_wb_we - connect \Y $not$ls180.v:2852$570_Y + connect \Y $not$ls180.v:2843$570_Y end - attribute \src "ls180.v:2868.25-2868.44" - cell $not $not$ls180.v:2868$579 + attribute \src "ls180.v:2859.25-2859.44" + cell $not $not$ls180.v:2859$579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_sink_ready - connect \Y $not$ls180.v:2868$579_Y + connect \Y $not$ls180.v:2859$579_Y end - attribute \src "ls180.v:2869.26-2869.47" - cell $not $not$ls180.v:2869$580 + attribute \src "ls180.v:2860.26-2860.47" + cell $not $not$ls180.v:2860$580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_source_valid - connect \Y $not$ls180.v:2869$580_Y + connect \Y $not$ls180.v:2860$580_Y end - attribute \src "ls180.v:2875.22-2875.41" - cell $not $not$ls180.v:2875$581 + attribute \src "ls180.v:2866.22-2866.41" + cell $not $not$ls180.v:2866$581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_sink_ready - connect \Y $not$ls180.v:2875$581_Y + connect \Y $not$ls180.v:2866$581_Y end - attribute \src "ls180.v:2881.26-2881.47" - cell $not $not$ls180.v:2881$582 + attribute \src "ls180.v:2872.26-2872.47" + cell $not $not$ls180.v:2872$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_source_valid - connect \Y $not$ls180.v:2881$582_Y + connect \Y $not$ls180.v:2872$582_Y end - attribute \src "ls180.v:2882.25-2882.44" - cell $not $not$ls180.v:2882$583 + attribute \src "ls180.v:2873.25-2873.44" + cell $not $not$ls180.v:2873$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_sink_ready - connect \Y $not$ls180.v:2882$583_Y + connect \Y $not$ls180.v:2873$583_Y end - attribute \src "ls180.v:2885.22-2885.43" - cell $not $not$ls180.v:2885$586 + attribute \src "ls180.v:2876.22-2876.43" + cell $not $not$ls180.v:2876$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_source_valid - connect \Y $not$ls180.v:2885$586_Y + connect \Y $not$ls180.v:2876$586_Y end - attribute \src "ls180.v:2923.61-2923.78" - cell $not $not$ls180.v:2923$596 + attribute \src "ls180.v:2914.61-2914.78" + cell $not $not$ls180.v:2914$596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_readable - connect \Y $not$ls180.v:2923$596_Y + connect \Y $not$ls180.v:2914$596_Y end - attribute \src "ls180.v:2953.61-2953.78" - cell $not $not$ls180.v:2953$607 + attribute \src "ls180.v:2944.61-2944.78" + cell $not $not$ls180.v:2944$607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_readable - connect \Y $not$ls180.v:2953$607_Y + connect \Y $not$ls180.v:2944$607_Y end - attribute \src "ls180.v:3148.81-3148.104" - cell $not $not$ls180.v:3148$657 + attribute \src "ls180.v:3139.81-3139.104" + cell $not $not$ls180.v:3139$657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_ack - connect \Y $not$ls180.v:3148$657_Y + connect \Y $not$ls180.v:3139$657_Y end - attribute \src "ls180.v:3165.71-3165.106" - cell $not $not$ls180.v:3165$681 + attribute \src "ls180.v:3156.71-3156.106" + cell $not $not$ls180.v:3156$681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we - connect \Y $not$ls180.v:3165$681_Y + connect \Y $not$ls180.v:3156$681_Y end - attribute \src "ls180.v:3168.73-3168.108" - cell $not $not$ls180.v:3168$688 + attribute \src "ls180.v:3159.73-3159.108" + cell $not $not$ls180.v:3159$688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we - connect \Y $not$ls180.v:3168$688_Y + connect \Y $not$ls180.v:3159$688_Y end - attribute \src "ls180.v:3171.73-3171.108" - cell $not $not$ls180.v:3171$695 + attribute \src "ls180.v:3162.73-3162.108" + cell $not $not$ls180.v:3162$695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we - connect \Y $not$ls180.v:3171$695_Y + connect \Y $not$ls180.v:3162$695_Y end - attribute \src "ls180.v:3174.73-3174.108" - cell $not $not$ls180.v:3174$702 + attribute \src "ls180.v:3165.73-3165.108" + cell $not $not$ls180.v:3165$702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we - connect \Y $not$ls180.v:3174$702_Y + connect \Y $not$ls180.v:3165$702_Y end - attribute \src "ls180.v:3177.73-3177.108" - cell $not $not$ls180.v:3177$709 + attribute \src "ls180.v:3168.73-3168.108" + cell $not $not$ls180.v:3168$709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we - connect \Y $not$ls180.v:3177$709_Y + connect \Y $not$ls180.v:3168$709_Y end - attribute \src "ls180.v:3180.76-3180.111" - cell $not $not$ls180.v:3180$716 + attribute \src "ls180.v:3171.76-3171.111" + cell $not $not$ls180.v:3171$716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we - connect \Y $not$ls180.v:3180$716_Y + connect \Y $not$ls180.v:3171$716_Y end - attribute \src "ls180.v:3183.76-3183.111" - cell $not $not$ls180.v:3183$723 + attribute \src "ls180.v:3174.76-3174.111" + cell $not $not$ls180.v:3174$723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we - connect \Y $not$ls180.v:3183$723_Y + connect \Y $not$ls180.v:3174$723_Y end - attribute \src "ls180.v:3186.76-3186.111" - cell $not $not$ls180.v:3186$730 + attribute \src "ls180.v:3177.76-3177.111" + cell $not $not$ls180.v:3177$730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we - connect \Y $not$ls180.v:3186$730_Y + connect \Y $not$ls180.v:3177$730_Y end - attribute \src "ls180.v:3189.76-3189.111" - cell $not $not$ls180.v:3189$737 + attribute \src "ls180.v:3180.76-3180.111" + cell $not $not$ls180.v:3180$737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we - connect \Y $not$ls180.v:3189$737_Y + connect \Y $not$ls180.v:3180$737_Y end - attribute \src "ls180.v:3203.68-3203.103" - cell $not $not$ls180.v:3203$745 + attribute \src "ls180.v:3194.68-3194.103" + cell $not $not$ls180.v:3194$745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_we - connect \Y $not$ls180.v:3203$745_Y + connect \Y $not$ls180.v:3194$745_Y end - attribute \src "ls180.v:3206.67-3206.102" - cell $not $not$ls180.v:3206$752 + attribute \src "ls180.v:3197.67-3197.102" + cell $not $not$ls180.v:3197$752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_we - connect \Y $not$ls180.v:3206$752_Y + connect \Y $not$ls180.v:3197$752_Y end - attribute \src "ls180.v:3209.69-3209.104" - cell $not $not$ls180.v:3209$759 + attribute \src "ls180.v:3200.69-3200.104" + cell $not $not$ls180.v:3200$759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_we - connect \Y $not$ls180.v:3209$759_Y + connect \Y $not$ls180.v:3200$759_Y end - attribute \src "ls180.v:3217.68-3217.103" - cell $not $not$ls180.v:3217$767 + attribute \src "ls180.v:3208.68-3208.103" + cell $not $not$ls180.v:3208$767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_we - connect \Y $not$ls180.v:3217$767_Y + connect \Y $not$ls180.v:3208$767_Y end - attribute \src "ls180.v:3220.67-3220.102" - cell $not $not$ls180.v:3220$774 + attribute \src "ls180.v:3211.67-3211.102" + cell $not $not$ls180.v:3211$774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_we - connect \Y $not$ls180.v:3220$774_Y + connect \Y $not$ls180.v:3211$774_Y end - attribute \src "ls180.v:3223.69-3223.104" - cell $not $not$ls180.v:3223$781 + attribute \src "ls180.v:3214.69-3214.104" + cell $not $not$ls180.v:3214$781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_we - connect \Y $not$ls180.v:3223$781_Y + connect \Y $not$ls180.v:3214$781_Y end - attribute \src "ls180.v:3231.67-3231.102" - cell $not $not$ls180.v:3231$789 + attribute \src "ls180.v:3222.67-3222.102" + cell $not $not$ls180.v:3222$789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_we - connect \Y $not$ls180.v:3231$789_Y + connect \Y $not$ls180.v:3222$789_Y end - attribute \src "ls180.v:3234.66-3234.101" - cell $not $not$ls180.v:3234$796 + attribute \src "ls180.v:3225.66-3225.101" + cell $not $not$ls180.v:3225$796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_we - connect \Y $not$ls180.v:3234$796_Y + connect \Y $not$ls180.v:3225$796_Y end - attribute \src "ls180.v:3245.78-3245.113" - cell $not $not$ls180.v:3245$804 + attribute \src "ls180.v:3236.78-3236.113" + cell $not $not$ls180.v:3236$804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we - connect \Y $not$ls180.v:3245$804_Y + connect \Y $not$ls180.v:3236$804_Y end - attribute \src "ls180.v:3248.82-3248.117" - cell $not $not$ls180.v:3248$811 + attribute \src "ls180.v:3239.82-3239.117" + cell $not $not$ls180.v:3239$811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we - connect \Y $not$ls180.v:3248$811_Y + connect \Y $not$ls180.v:3239$811_Y end - attribute \src "ls180.v:3251.63-3251.98" - cell $not $not$ls180.v:3251$818 + attribute \src "ls180.v:3242.63-3242.98" + cell $not $not$ls180.v:3242$818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we - connect \Y $not$ls180.v:3251$818_Y + connect \Y $not$ls180.v:3242$818_Y end - attribute \src "ls180.v:3254.82-3254.117" - cell $not $not$ls180.v:3254$825 + attribute \src "ls180.v:3245.82-3245.117" + cell $not $not$ls180.v:3245$825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we - connect \Y $not$ls180.v:3254$825_Y + connect \Y $not$ls180.v:3245$825_Y end - attribute \src "ls180.v:3257.82-3257.117" - cell $not $not$ls180.v:3257$832 + attribute \src "ls180.v:3248.82-3248.117" + cell $not $not$ls180.v:3248$832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we - connect \Y $not$ls180.v:3257$832_Y + connect \Y $not$ls180.v:3248$832_Y end - attribute \src "ls180.v:3260.83-3260.118" - cell $not $not$ls180.v:3260$839 + attribute \src "ls180.v:3251.83-3251.118" + cell $not $not$ls180.v:3251$839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we - connect \Y $not$ls180.v:3260$839_Y + connect \Y $not$ls180.v:3251$839_Y end - attribute \src "ls180.v:3263.81-3263.116" - cell $not $not$ls180.v:3263$846 + attribute \src "ls180.v:3254.81-3254.116" + cell $not $not$ls180.v:3254$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we - connect \Y $not$ls180.v:3263$846_Y + connect \Y $not$ls180.v:3254$846_Y end - attribute \src "ls180.v:3266.81-3266.116" - cell $not $not$ls180.v:3266$853 + attribute \src "ls180.v:3257.81-3257.116" + cell $not $not$ls180.v:3257$853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we - connect \Y $not$ls180.v:3266$853_Y + connect \Y $not$ls180.v:3257$853_Y end - attribute \src "ls180.v:3269.81-3269.116" - cell $not $not$ls180.v:3269$860 + attribute \src "ls180.v:3260.81-3260.116" + cell $not $not$ls180.v:3260$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we - connect \Y $not$ls180.v:3269$860_Y + connect \Y $not$ls180.v:3260$860_Y end - attribute \src "ls180.v:3272.81-3272.116" - cell $not $not$ls180.v:3272$867 + attribute \src "ls180.v:3263.81-3263.116" + cell $not $not$ls180.v:3263$867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we - connect \Y $not$ls180.v:3272$867_Y + connect \Y $not$ls180.v:3263$867_Y end - attribute \src "ls180.v:3290.70-3290.105" - cell $not $not$ls180.v:3290$875 + attribute \src "ls180.v:3281.70-3281.105" + cell $not $not$ls180.v:3281$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3290$875_Y + connect \Y $not$ls180.v:3281$875_Y end - attribute \src "ls180.v:3293.70-3293.105" - cell $not $not$ls180.v:3293$882 + attribute \src "ls180.v:3284.70-3284.105" + cell $not $not$ls180.v:3284$882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3293$882_Y + connect \Y $not$ls180.v:3284$882_Y end - attribute \src "ls180.v:3296.70-3296.105" - cell $not $not$ls180.v:3296$889 + attribute \src "ls180.v:3287.70-3287.105" + cell $not $not$ls180.v:3287$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3296$889_Y + connect \Y $not$ls180.v:3287$889_Y end - attribute \src "ls180.v:3299.70-3299.105" - cell $not $not$ls180.v:3299$896 + attribute \src "ls180.v:3290.70-3290.105" + cell $not $not$ls180.v:3290$896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3299$896_Y + connect \Y $not$ls180.v:3290$896_Y end - attribute \src "ls180.v:3302.72-3302.107" - cell $not $not$ls180.v:3302$903 + attribute \src "ls180.v:3293.72-3293.107" + cell $not $not$ls180.v:3293$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3302$903_Y + connect \Y $not$ls180.v:3293$903_Y end - attribute \src "ls180.v:3305.72-3305.107" - cell $not $not$ls180.v:3305$910 + attribute \src "ls180.v:3296.72-3296.107" + cell $not $not$ls180.v:3296$910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3305$910_Y + connect \Y $not$ls180.v:3296$910_Y end - attribute \src "ls180.v:3308.72-3308.107" - cell $not $not$ls180.v:3308$917 + attribute \src "ls180.v:3299.72-3299.107" + cell $not $not$ls180.v:3299$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3308$917_Y + connect \Y $not$ls180.v:3299$917_Y end - attribute \src "ls180.v:3311.72-3311.107" - cell $not $not$ls180.v:3311$924 + attribute \src "ls180.v:3302.72-3302.107" + cell $not $not$ls180.v:3302$924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3311$924_Y + connect \Y $not$ls180.v:3302$924_Y end - attribute \src "ls180.v:3314.68-3314.103" - cell $not $not$ls180.v:3314$931 + attribute \src "ls180.v:3305.68-3305.103" + cell $not $not$ls180.v:3305$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3314$931_Y + connect \Y $not$ls180.v:3305$931_Y end - attribute \src "ls180.v:3317.78-3317.113" - cell $not $not$ls180.v:3317$938 + attribute \src "ls180.v:3308.78-3308.113" + cell $not $not$ls180.v:3308$938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3317$938_Y + connect \Y $not$ls180.v:3308$938_Y end - attribute \src "ls180.v:3320.71-3320.106" - cell $not $not$ls180.v:3320$945 + attribute \src "ls180.v:3311.71-3311.106" + cell $not $not$ls180.v:3311$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3320$945_Y + connect \Y $not$ls180.v:3311$945_Y end - attribute \src "ls180.v:3323.71-3323.106" - cell $not $not$ls180.v:3323$952 + attribute \src "ls180.v:3314.71-3314.106" + cell $not $not$ls180.v:3314$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3323$952_Y + connect \Y $not$ls180.v:3314$952_Y end - attribute \src "ls180.v:3326.71-3326.106" - cell $not $not$ls180.v:3326$959 + attribute \src "ls180.v:3317.71-3317.106" + cell $not $not$ls180.v:3317$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3326$959_Y + connect \Y $not$ls180.v:3317$959_Y end - attribute \src "ls180.v:3329.71-3329.106" - cell $not $not$ls180.v:3329$966 + attribute \src "ls180.v:3320.71-3320.106" + cell $not $not$ls180.v:3320$966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3329$966_Y + connect \Y $not$ls180.v:3320$966_Y end - attribute \src "ls180.v:3332.75-3332.110" - cell $not $not$ls180.v:3332$973 + attribute \src "ls180.v:3323.75-3323.110" + cell $not $not$ls180.v:3323$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3332$973_Y + connect \Y $not$ls180.v:3323$973_Y end - attribute \src "ls180.v:3335.76-3335.111" - cell $not $not$ls180.v:3335$980 + attribute \src "ls180.v:3326.76-3326.111" + cell $not $not$ls180.v:3326$980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3335$980_Y + connect \Y $not$ls180.v:3326$980_Y end - attribute \src "ls180.v:3338.75-3338.110" - cell $not $not$ls180.v:3338$987 + attribute \src "ls180.v:3329.75-3329.110" + cell $not $not$ls180.v:3329$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we - connect \Y $not$ls180.v:3338$987_Y + connect \Y $not$ls180.v:3329$987_Y end - attribute \src "ls180.v:3358.48-3358.83" - cell $not $not$ls180.v:3358$995 + attribute \src "ls180.v:3349.48-3349.83" + cell $not $not$ls180.v:3349$995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we - connect \Y $not$ls180.v:3358$995_Y + connect \Y $not$ls180.v:3349$995_Y end - attribute \src "ls180.v:3361.71-3361.106" - cell $not $not$ls180.v:3361$1002 + attribute \src "ls180.v:3352.71-3352.106" + cell $not $not$ls180.v:3352$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we - connect \Y $not$ls180.v:3361$1002_Y + connect \Y $not$ls180.v:3352$1002_Y end - attribute \src "ls180.v:3364.72-3364.107" - cell $not $not$ls180.v:3364$1009 + attribute \src "ls180.v:3355.72-3355.107" + cell $not $not$ls180.v:3355$1009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we - connect \Y $not$ls180.v:3364$1009_Y + connect \Y $not$ls180.v:3355$1009_Y end - attribute \src "ls180.v:3367.63-3367.98" - cell $not $not$ls180.v:3367$1016 + attribute \src "ls180.v:3358.63-3358.98" + cell $not $not$ls180.v:3358$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we - connect \Y $not$ls180.v:3367$1016_Y + connect \Y $not$ls180.v:3358$1016_Y end - attribute \src "ls180.v:3370.64-3370.99" - cell $not $not$ls180.v:3370$1023 + attribute \src "ls180.v:3361.64-3361.99" + cell $not $not$ls180.v:3361$1023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we - connect \Y $not$ls180.v:3370$1023_Y + connect \Y $not$ls180.v:3361$1023_Y end - attribute \src "ls180.v:3373.75-3373.110" - cell $not $not$ls180.v:3373$1030 + attribute \src "ls180.v:3364.75-3364.110" + cell $not $not$ls180.v:3364$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we - connect \Y $not$ls180.v:3373$1030_Y + connect \Y $not$ls180.v:3364$1030_Y end - attribute \src "ls180.v:3376.72-3376.107" - cell $not $not$ls180.v:3376$1037 + attribute \src "ls180.v:3367.72-3367.107" + cell $not $not$ls180.v:3367$1037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we - connect \Y $not$ls180.v:3376$1037_Y + connect \Y $not$ls180.v:3367$1037_Y end - attribute \src "ls180.v:3379.71-3379.106" - cell $not $not$ls180.v:3379$1044 + attribute \src "ls180.v:3370.71-3370.106" + cell $not $not$ls180.v:3370$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we - connect \Y $not$ls180.v:3379$1044_Y + connect \Y $not$ls180.v:3370$1044_Y end - attribute \src "ls180.v:3392.77-3392.112" - cell $not $not$ls180.v:3392$1052 + attribute \src "ls180.v:3383.77-3383.112" + cell $not $not$ls180.v:3383$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_we - connect \Y $not$ls180.v:3392$1052_Y + connect \Y $not$ls180.v:3383$1052_Y end - attribute \src "ls180.v:3395.77-3395.112" - cell $not $not$ls180.v:3395$1059 + attribute \src "ls180.v:3386.77-3386.112" + cell $not $not$ls180.v:3386$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_we - connect \Y $not$ls180.v:3395$1059_Y + connect \Y $not$ls180.v:3386$1059_Y end - attribute \src "ls180.v:3398.77-3398.112" - cell $not $not$ls180.v:3398$1066 + attribute \src "ls180.v:3389.77-3389.112" + cell $not $not$ls180.v:3389$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_we - connect \Y $not$ls180.v:3398$1066_Y + connect \Y $not$ls180.v:3389$1066_Y end - attribute \src "ls180.v:3401.77-3401.112" - cell $not $not$ls180.v:3401$1073 + attribute \src "ls180.v:3392.77-3392.112" + cell $not $not$ls180.v:3392$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_we - connect \Y $not$ls180.v:3401$1073_Y + connect \Y $not$ls180.v:3392$1073_Y end - attribute \src "ls180.v:3761.68-3761.317" - cell $not $not$ls180.v:3761$1115 + attribute \src "ls180.v:3752.68-3752.317" + cell $not $not$ls180.v:3752$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3761$1114_Y - connect \Y $not$ls180.v:3761$1115_Y + connect \A $or$ls180.v:3752$1114_Y + connect \Y $not$ls180.v:3752$1115_Y end - attribute \src "ls180.v:3785.68-3785.317" - cell $not $not$ls180.v:3785$1131 + attribute \src "ls180.v:3776.68-3776.317" + cell $not $not$ls180.v:3776$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3785$1130_Y - connect \Y $not$ls180.v:3785$1131_Y + connect \A $or$ls180.v:3776$1130_Y + connect \Y $not$ls180.v:3776$1131_Y end - attribute \src "ls180.v:3809.68-3809.317" - cell $not $not$ls180.v:3809$1147 + attribute \src "ls180.v:3800.68-3800.317" + cell $not $not$ls180.v:3800$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3809$1146_Y - connect \Y $not$ls180.v:3809$1147_Y + connect \A $or$ls180.v:3800$1146_Y + connect \Y $not$ls180.v:3800$1147_Y end - attribute \src "ls180.v:3833.68-3833.317" - cell $not $not$ls180.v:3833$1163 + attribute \src "ls180.v:3824.68-3824.317" + cell $not $not$ls180.v:3824$1163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3833$1162_Y - connect \Y $not$ls180.v:3833$1163_Y + connect \A $or$ls180.v:3824$1162_Y + connect \Y $not$ls180.v:3824$1163_Y end - attribute \src "ls180.v:4361.62-4361.86" - cell $not $not$ls180.v:4361$1258 + attribute \src "ls180.v:4356.62-4356.86" + cell $not $not$ls180.v:4356$1262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_ack - connect \Y $not$ls180.v:4361$1258_Y + connect \Y $not$ls180.v:4356$1262_Y end - attribute \src "ls180.v:4380.8-4380.33" - cell $not $not$ls180.v:4380$1262 + attribute \src "ls180.v:4375.8-4375.33" + cell $not $not$ls180.v:4375$1266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_zero_trigger - connect \Y $not$ls180.v:4380$1262_Y + connect \Y $not$ls180.v:4375$1266_Y end - attribute \src "ls180.v:4384.54-4384.74" - cell $not $not$ls180.v:4384$1265 + attribute \src "ls180.v:4379.54-4379.74" + cell $not $not$ls180.v:4379$1269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_ack - connect \Y $not$ls180.v:4384$1265_Y + connect \Y $not$ls180.v:4379$1269_Y end - attribute \src "ls180.v:4392.27-4392.45" - cell $not $not$ls180.v:4392$1267 + attribute \src "ls180.v:4387.27-4387.45" + cell $not $not$ls180.v:4387$1271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_timer_done0 - connect \Y $not$ls180.v:4392$1267_Y + connect \Y $not$ls180.v:4387$1271_Y end - attribute \src "ls180.v:4462.126-4462.174" - cell $not $not$ls180.v:4462$1282 + attribute \src "ls180.v:4457.126-4457.174" + cell $not $not$ls180.v:4457$1286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:4462$1282_Y + connect \Y $not$ls180.v:4457$1286_Y end - attribute \src "ls180.v:4468.126-4468.174" - cell $not $not$ls180.v:4468$1287 + attribute \src "ls180.v:4463.126-4463.174" + cell $not $not$ls180.v:4463$1291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:4468$1287_Y + connect \Y $not$ls180.v:4463$1291_Y end - attribute \src "ls180.v:4469.8-4469.56" - cell $not $not$ls180.v:4469$1289 + attribute \src "ls180.v:4464.8-4464.56" + cell $not $not$ls180.v:4464$1293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:4469$1289_Y + connect \Y $not$ls180.v:4464$1293_Y end - attribute \src "ls180.v:4477.8-4477.51" - cell $not $not$ls180.v:4477$1292 + attribute \src "ls180.v:4472.8-4472.51" + cell $not $not$ls180.v:4472$1296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:4477$1292_Y + connect \Y $not$ls180.v:4472$1296_Y end - attribute \src "ls180.v:4492.8-4492.41" - cell $not $not$ls180.v:4492$1294 + attribute \src "ls180.v:4487.8-4487.41" + cell $not $not$ls180.v:4487$1298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:4492$1294_Y + connect \Y $not$ls180.v:4487$1298_Y end - attribute \src "ls180.v:4508.126-4508.174" - cell $not $not$ls180.v:4508$1298 + attribute \src "ls180.v:4503.126-4503.174" + cell $not $not$ls180.v:4503$1302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:4508$1298_Y + connect \Y $not$ls180.v:4503$1302_Y end - attribute \src "ls180.v:4514.126-4514.174" - cell $not $not$ls180.v:4514$1303 + attribute \src "ls180.v:4509.126-4509.174" + cell $not $not$ls180.v:4509$1307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:4514$1303_Y + connect \Y $not$ls180.v:4509$1307_Y end - attribute \src "ls180.v:4515.8-4515.56" - cell $not $not$ls180.v:4515$1305 + attribute \src "ls180.v:4510.8-4510.56" + cell $not $not$ls180.v:4510$1309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:4515$1305_Y + connect \Y $not$ls180.v:4510$1309_Y end - attribute \src "ls180.v:4523.8-4523.51" - cell $not $not$ls180.v:4523$1308 + attribute \src "ls180.v:4518.8-4518.51" + cell $not $not$ls180.v:4518$1312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:4523$1308_Y + connect \Y $not$ls180.v:4518$1312_Y end - attribute \src "ls180.v:4538.8-4538.41" - cell $not $not$ls180.v:4538$1310 + attribute \src "ls180.v:4533.8-4533.41" + cell $not $not$ls180.v:4533$1314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:4538$1310_Y + connect \Y $not$ls180.v:4533$1314_Y end - attribute \src "ls180.v:4554.126-4554.174" - cell $not $not$ls180.v:4554$1314 + attribute \src "ls180.v:4549.126-4549.174" + cell $not $not$ls180.v:4549$1318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:4554$1314_Y + connect \Y $not$ls180.v:4549$1318_Y end - attribute \src "ls180.v:4560.126-4560.174" - cell $not $not$ls180.v:4560$1319 + attribute \src "ls180.v:4555.126-4555.174" + cell $not $not$ls180.v:4555$1323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:4560$1319_Y + connect \Y $not$ls180.v:4555$1323_Y end - attribute \src "ls180.v:4561.8-4561.56" - cell $not $not$ls180.v:4561$1321 + attribute \src "ls180.v:4556.8-4556.56" + cell $not $not$ls180.v:4556$1325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:4561$1321_Y + connect \Y $not$ls180.v:4556$1325_Y end - attribute \src "ls180.v:4569.8-4569.51" - cell $not $not$ls180.v:4569$1324 + attribute \src "ls180.v:4564.8-4564.51" + cell $not $not$ls180.v:4564$1328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:4569$1324_Y + connect \Y $not$ls180.v:4564$1328_Y end - attribute \src "ls180.v:4584.8-4584.41" - cell $not $not$ls180.v:4584$1326 + attribute \src "ls180.v:4579.8-4579.41" + cell $not $not$ls180.v:4579$1330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:4584$1326_Y + connect \Y $not$ls180.v:4579$1330_Y end - attribute \src "ls180.v:4600.126-4600.174" - cell $not $not$ls180.v:4600$1330 + attribute \src "ls180.v:4595.126-4595.174" + cell $not $not$ls180.v:4595$1334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:4600$1330_Y + connect \Y $not$ls180.v:4595$1334_Y end - attribute \src "ls180.v:4606.126-4606.174" - cell $not $not$ls180.v:4606$1335 + attribute \src "ls180.v:4601.126-4601.174" + cell $not $not$ls180.v:4601$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:4606$1335_Y + connect \Y $not$ls180.v:4601$1339_Y end - attribute \src "ls180.v:4607.8-4607.56" - cell $not $not$ls180.v:4607$1337 + attribute \src "ls180.v:4602.8-4602.56" + cell $not $not$ls180.v:4602$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:4607$1337_Y + connect \Y $not$ls180.v:4602$1341_Y end - attribute \src "ls180.v:4615.8-4615.51" - cell $not $not$ls180.v:4615$1340 + attribute \src "ls180.v:4610.8-4610.51" + cell $not $not$ls180.v:4610$1344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:4615$1340_Y + connect \Y $not$ls180.v:4610$1344_Y end - attribute \src "ls180.v:4630.8-4630.41" - cell $not $not$ls180.v:4630$1342 + attribute \src "ls180.v:4625.8-4625.41" + cell $not $not$ls180.v:4625$1346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:4630$1342_Y + connect \Y $not$ls180.v:4625$1346_Y end - attribute \src "ls180.v:4638.7-4638.17" - cell $not $not$ls180.v:4638$1345 + attribute \src "ls180.v:4633.7-4633.17" + cell $not $not$ls180.v:4633$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_en0 - connect \Y $not$ls180.v:4638$1345_Y + connect \Y $not$ls180.v:4633$1349_Y end - attribute \src "ls180.v:4641.8-4641.24" - cell $not $not$ls180.v:4641$1346 + attribute \src "ls180.v:4636.8-4636.24" + cell $not $not$ls180.v:4636$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_max_time0 - connect \Y $not$ls180.v:4641$1346_Y + connect \Y $not$ls180.v:4636$1350_Y end - attribute \src "ls180.v:4645.7-4645.17" - cell $not $not$ls180.v:4645$1348 + attribute \src "ls180.v:4640.7-4640.17" + cell $not $not$ls180.v:4640$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_en1 - connect \Y $not$ls180.v:4645$1348_Y + connect \Y $not$ls180.v:4640$1352_Y end - attribute \src "ls180.v:4648.8-4648.24" - cell $not $not$ls180.v:4648$1349 + attribute \src "ls180.v:4643.8-4643.24" + cell $not $not$ls180.v:4643$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_max_time1 - connect \Y $not$ls180.v:4648$1349_Y + connect \Y $not$ls180.v:4643$1353_Y end - attribute \src "ls180.v:4767.25-4767.38" - cell $not $not$ls180.v:4767$1351 + attribute \src "ls180.v:4762.25-4762.38" + cell $not $not$ls180.v:4762$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \array_muxed2 - connect \Y $not$ls180.v:4767$1351_Y + connect \Y $not$ls180.v:4762$1355_Y end - attribute \src "ls180.v:4768.25-4768.38" - cell $not $not$ls180.v:4768$1352 + attribute \src "ls180.v:4763.25-4763.38" + cell $not $not$ls180.v:4763$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \array_muxed3 - connect \Y $not$ls180.v:4768$1352_Y + connect \Y $not$ls180.v:4763$1356_Y end - attribute \src "ls180.v:4769.24-4769.37" - cell $not $not$ls180.v:4769$1353 + attribute \src "ls180.v:4764.24-4764.37" + cell $not $not$ls180.v:4764$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \array_muxed4 - connect \Y $not$ls180.v:4769$1353_Y + connect \Y $not$ls180.v:4764$1357_Y end - attribute \src "ls180.v:4780.8-4780.28" - cell $not $not$ls180.v:4780$1354 + attribute \src "ls180.v:4775.8-4775.28" + cell $not $not$ls180.v:4775$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_tccdcon_ready - connect \Y $not$ls180.v:4780$1354_Y + connect \Y $not$ls180.v:4775$1358_Y end - attribute \src "ls180.v:4795.8-4795.28" - cell $not $not$ls180.v:4795$1357 + attribute \src "ls180.v:4790.8-4790.28" + cell $not $not$ls180.v:4790$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_twtrcon_ready - connect \Y $not$ls180.v:4795$1357_Y + connect \Y $not$ls180.v:4790$1361_Y end - attribute \src "ls180.v:4831.31-4831.48" - cell $not $not$ls180.v:4831$1387 + attribute \src "ls180.v:4826.31-4826.48" + cell $not $not$ls180.v:4826$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_tx_busy - connect \Y $not$ls180.v:4831$1387_Y + connect \Y $not$ls180.v:4826$1391_Y end - attribute \src "ls180.v:4831.54-4831.74" - cell $not $not$ls180.v:4831$1389 + attribute \src "ls180.v:4826.54-4826.74" + cell $not $not$ls180.v:4826$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_sink_ready - connect \Y $not$ls180.v:4831$1389_Y + connect \Y $not$ls180.v:4826$1393_Y end - attribute \src "ls180.v:4860.7-4860.24" - cell $not $not$ls180.v:4860$1396 + attribute \src "ls180.v:4855.7-4855.24" + cell $not $not$ls180.v:4855$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_rx_busy - connect \Y $not$ls180.v:4860$1396_Y + connect \Y $not$ls180.v:4855$1400_Y end - attribute \src "ls180.v:4861.9-4861.21" - cell $not $not$ls180.v:4861$1397 + attribute \src "ls180.v:4856.9-4856.21" + cell $not $not$ls180.v:4856$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_rx - connect \Y $not$ls180.v:4861$1397_Y + connect \Y $not$ls180.v:4856$1401_Y end - attribute \src "ls180.v:4894.8-4894.19" - cell $not $not$ls180.v:4894$1403 + attribute \src "ls180.v:4889.8-4889.19" + cell $not $not$ls180.v:4889$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_trigger - connect \Y $not$ls180.v:4894$1403_Y + connect \Y $not$ls180.v:4889$1407_Y end - attribute \src "ls180.v:4901.8-4901.19" - cell $not $not$ls180.v:4901$1405 + attribute \src "ls180.v:4896.8-4896.19" + cell $not $not$ls180.v:4896$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_trigger - connect \Y $not$ls180.v:4901$1405_Y + connect \Y $not$ls180.v:4896$1409_Y end - attribute \src "ls180.v:4911.60-4911.76" - cell $not $not$ls180.v:4911$1408 + attribute \src "ls180.v:4906.60-4906.76" + cell $not $not$ls180.v:4906$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_replace - connect \Y $not$ls180.v:4911$1408_Y + connect \Y $not$ls180.v:4906$1412_Y end - attribute \src "ls180.v:4917.60-4917.76" - cell $not $not$ls180.v:4917$1413 + attribute \src "ls180.v:4912.60-4912.76" + cell $not $not$ls180.v:4912$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_replace - connect \Y $not$ls180.v:4917$1413_Y + connect \Y $not$ls180.v:4912$1417_Y end - attribute \src "ls180.v:4918.8-4918.24" - cell $not $not$ls180.v:4918$1415 + attribute \src "ls180.v:4913.8-4913.24" + cell $not $not$ls180.v:4913$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_do_read - connect \Y $not$ls180.v:4918$1415_Y + connect \Y $not$ls180.v:4913$1419_Y end - attribute \src "ls180.v:4933.60-4933.76" - cell $not $not$ls180.v:4933$1419 + attribute \src "ls180.v:4928.60-4928.76" + cell $not $not$ls180.v:4928$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_replace - connect \Y $not$ls180.v:4933$1419_Y + connect \Y $not$ls180.v:4928$1423_Y end - attribute \src "ls180.v:4939.60-4939.76" - cell $not $not$ls180.v:4939$1424 + attribute \src "ls180.v:4934.60-4934.76" + cell $not $not$ls180.v:4934$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_replace - connect \Y $not$ls180.v:4939$1424_Y + connect \Y $not$ls180.v:4934$1428_Y end - attribute \src "ls180.v:4940.8-4940.24" - cell $not $not$ls180.v:4940$1426 + attribute \src "ls180.v:4935.8-4935.24" + cell $not $not$ls180.v:4935$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_do_read - connect \Y $not$ls180.v:4940$1426_Y + connect \Y $not$ls180.v:4935$1430_Y end - attribute \src "ls180.v:4974.9-4974.32" - cell $not $not$ls180.v:4974$1429 + attribute \src "ls180.v:4969.9-4969.32" + cell $not $not$ls180.v:4969$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_request [0] - connect \Y $not$ls180.v:4974$1429_Y + connect \Y $not$ls180.v:4969$1433_Y end - attribute \src "ls180.v:4985.9-4985.32" - cell $not $not$ls180.v:4985$1430 + attribute \src "ls180.v:4980.9-4980.32" + cell $not $not$ls180.v:4980$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_request [1] - connect \Y $not$ls180.v:4985$1430_Y + connect \Y $not$ls180.v:4980$1434_Y end - attribute \src "ls180.v:4996.9-4996.32" - cell $not $not$ls180.v:4996$1431 + attribute \src "ls180.v:4991.9-4991.32" + cell $not $not$ls180.v:4991$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_request [2] - connect \Y $not$ls180.v:4996$1431_Y + connect \Y $not$ls180.v:4991$1435_Y end - attribute \src "ls180.v:5009.8-5009.25" - cell $not $not$ls180.v:5009$1432 + attribute \src "ls180.v:5004.8-5004.25" + cell $not $not$ls180.v:5004$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_done - connect \Y $not$ls180.v:5009$1432_Y + connect \Y $not$ls180.v:5004$1436_Y end - attribute \src "ls180.v:1560.10-1560.86" - cell $or $or$ls180.v:1560$24 + attribute \src "ls180.v:1551.10-1551.86" + cell $or $or$ls180.v:1551$24 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258292,10 +258084,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_converted_interface_ack connect \B \libresocsim_converter0_skip - connect \Y $or$ls180.v:1560$24_Y + connect \Y $or$ls180.v:1551$24_Y end - attribute \src "ls180.v:1620.10-1620.86" - cell $or $or$ls180.v:1620$35 + attribute \src "ls180.v:1611.10-1611.86" + cell $or $or$ls180.v:1611$35 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258303,10 +258095,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_converted_interface_ack connect \B \libresocsim_converter1_skip - connect \Y $or$ls180.v:1620$35_Y + connect \Y $or$ls180.v:1611$35_Y end - attribute \src "ls180.v:1680.10-1680.86" - cell $or $or$ls180.v:1680$46 + attribute \src "ls180.v:1671.10-1671.86" + cell $or $or$ls180.v:1671$46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258314,21 +258106,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_converted_interface_ack connect \B \libresocsim_converter2_skip - connect \Y $or$ls180.v:1680$46_Y + connect \Y $or$ls180.v:1671$46_Y end - attribute \src "ls180.v:1882.34-1882.90" - cell $or $or$ls180.v:1882$91 + attribute \src "ls180.v:1873.34-1873.90" + cell $or $or$ls180.v:1873$91 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_start0 - connect \B $ne$ls180.v:1882$90_Y - connect \Y $or$ls180.v:1882$91_Y + connect \B $ne$ls180.v:1873$90_Y + connect \Y $or$ls180.v:1873$91_Y end - attribute \src "ls180.v:1925.54-1925.125" - cell $or $or$ls180.v:1925$95 + attribute \src "ls180.v:1916.54-1916.125" + cell $or $or$ls180.v:1916$95 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258336,10 +258128,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_req_wdata_ready connect \B \sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:1925$95_Y + connect \Y $or$ls180.v:1916$95_Y end - attribute \src "ls180.v:1926.39-1926.136" - cell $or $or$ls180.v:1926$96 + attribute \src "ls180.v:1917.39-1917.136" + cell $or $or$ls180.v:1917$96 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258347,21 +258139,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:1926$96_Y + connect \Y $or$ls180.v:1917$96_Y end - attribute \src "ls180.v:1934.40-1934.155" - cell $or $or$ls180.v:1934$100 + attribute \src "ls180.v:1925.40-1925.155" + cell $or $or$ls180.v:1925$100 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:1934$99_Y + connect \A $sshl$ls180.v:1925$99_Y connect \B { 4'0000 \sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:1934$100_Y + connect \Y $or$ls180.v:1925$100_Y end - attribute \src "ls180.v:1971.117-1971.225" - cell $or $or$ls180.v:1971$113 + attribute \src "ls180.v:1962.117-1962.225" + cell $or $or$ls180.v:1962$113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258369,21 +258161,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \B \sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:1971$113_Y + connect \Y $or$ls180.v:1962$113_Y end - attribute \src "ls180.v:1977.52-1977.142" - cell $or $or$ls180.v:1977$119 + attribute \src "ls180.v:1968.52-1968.142" + cell $or $or$ls180.v:1968$119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:1977$118_Y + connect \A $not$ls180.v:1968$118_Y connect \B \sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:1977$119_Y + connect \Y $or$ls180.v:1968$119_Y end - attribute \src "ls180.v:2082.54-2082.125" - cell $or $or$ls180.v:2082$125 + attribute \src "ls180.v:2073.54-2073.125" + cell $or $or$ls180.v:2073$125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258391,10 +258183,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_req_wdata_ready connect \B \sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:2082$125_Y + connect \Y $or$ls180.v:2073$125_Y end - attribute \src "ls180.v:2083.39-2083.136" - cell $or $or$ls180.v:2083$126 + attribute \src "ls180.v:2074.39-2074.136" + cell $or $or$ls180.v:2074$126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258402,21 +258194,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:2083$126_Y + connect \Y $or$ls180.v:2074$126_Y end - attribute \src "ls180.v:2091.40-2091.155" - cell $or $or$ls180.v:2091$130 + attribute \src "ls180.v:2082.40-2082.155" + cell $or $or$ls180.v:2082$130 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:2091$129_Y + connect \A $sshl$ls180.v:2082$129_Y connect \B { 4'0000 \sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:2091$130_Y + connect \Y $or$ls180.v:2082$130_Y end - attribute \src "ls180.v:2128.117-2128.225" - cell $or $or$ls180.v:2128$143 + attribute \src "ls180.v:2119.117-2119.225" + cell $or $or$ls180.v:2119$143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258424,21 +258216,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \B \sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:2128$143_Y + connect \Y $or$ls180.v:2119$143_Y end - attribute \src "ls180.v:2134.52-2134.142" - cell $or $or$ls180.v:2134$149 + attribute \src "ls180.v:2125.52-2125.142" + cell $or $or$ls180.v:2125$149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2134$148_Y + connect \A $not$ls180.v:2125$148_Y connect \B \sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:2134$149_Y + connect \Y $or$ls180.v:2125$149_Y end - attribute \src "ls180.v:2239.54-2239.125" - cell $or $or$ls180.v:2239$155 + attribute \src "ls180.v:2230.54-2230.125" + cell $or $or$ls180.v:2230$155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258446,10 +258238,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_req_wdata_ready connect \B \sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:2239$155_Y + connect \Y $or$ls180.v:2230$155_Y end - attribute \src "ls180.v:2240.39-2240.136" - cell $or $or$ls180.v:2240$156 + attribute \src "ls180.v:2231.39-2231.136" + cell $or $or$ls180.v:2231$156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258457,21 +258249,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:2240$156_Y + connect \Y $or$ls180.v:2231$156_Y end - attribute \src "ls180.v:2248.40-2248.155" - cell $or $or$ls180.v:2248$160 + attribute \src "ls180.v:2239.40-2239.155" + cell $or $or$ls180.v:2239$160 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:2248$159_Y + connect \A $sshl$ls180.v:2239$159_Y connect \B { 4'0000 \sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:2248$160_Y + connect \Y $or$ls180.v:2239$160_Y end - attribute \src "ls180.v:2285.117-2285.225" - cell $or $or$ls180.v:2285$173 + attribute \src "ls180.v:2276.117-2276.225" + cell $or $or$ls180.v:2276$173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258479,21 +258271,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \B \sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:2285$173_Y + connect \Y $or$ls180.v:2276$173_Y end - attribute \src "ls180.v:2291.52-2291.142" - cell $or $or$ls180.v:2291$179 + attribute \src "ls180.v:2282.52-2282.142" + cell $or $or$ls180.v:2282$179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2291$178_Y + connect \A $not$ls180.v:2282$178_Y connect \B \sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:2291$179_Y + connect \Y $or$ls180.v:2282$179_Y end - attribute \src "ls180.v:2396.54-2396.125" - cell $or $or$ls180.v:2396$185 + attribute \src "ls180.v:2387.54-2387.125" + cell $or $or$ls180.v:2387$185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258501,10 +258293,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_req_wdata_ready connect \B \sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:2396$185_Y + connect \Y $or$ls180.v:2387$185_Y end - attribute \src "ls180.v:2397.39-2397.136" - cell $or $or$ls180.v:2397$186 + attribute \src "ls180.v:2388.39-2388.136" + cell $or $or$ls180.v:2388$186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258512,21 +258304,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:2397$186_Y + connect \Y $or$ls180.v:2388$186_Y end - attribute \src "ls180.v:2405.40-2405.155" - cell $or $or$ls180.v:2405$190 + attribute \src "ls180.v:2396.40-2396.155" + cell $or $or$ls180.v:2396$190 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:2405$189_Y + connect \A $sshl$ls180.v:2396$189_Y connect \B { 4'0000 \sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:2405$190_Y + connect \Y $or$ls180.v:2396$190_Y end - attribute \src "ls180.v:2442.117-2442.225" - cell $or $or$ls180.v:2442$203 + attribute \src "ls180.v:2433.117-2433.225" + cell $or $or$ls180.v:2433$203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258534,21 +258326,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \B \sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:2442$203_Y + connect \Y $or$ls180.v:2433$203_Y end - attribute \src "ls180.v:2448.52-2448.142" - cell $or $or$ls180.v:2448$209 + attribute \src "ls180.v:2439.52-2439.142" + cell $or $or$ls180.v:2439$209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2448$208_Y + connect \A $not$ls180.v:2439$208_Y connect \B \sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:2448$209_Y + connect \Y $or$ls180.v:2439$209_Y end - attribute \src "ls180.v:2547.92-2547.168" - cell $or $or$ls180.v:2547$229 + attribute \src "ls180.v:2538.92-2538.168" + cell $or $or$ls180.v:2538$229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258556,626 +258348,626 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_is_write connect \B \sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:2547$229_Y + connect \Y $or$ls180.v:2538$229_Y end - attribute \src "ls180.v:2550.34-2550.179" - cell $or $or$ls180.v:2550$235 + attribute \src "ls180.v:2541.34-2541.179" + cell $or $or$ls180.v:2541$235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2550$233_Y - connect \B $and$ls180.v:2550$234_Y - connect \Y $or$ls180.v:2550$235_Y + connect \A $and$ls180.v:2541$233_Y + connect \B $and$ls180.v:2541$234_Y + connect \Y $or$ls180.v:2541$235_Y end - attribute \src "ls180.v:2550.33-2550.254" - cell $or $or$ls180.v:2550$237 + attribute \src "ls180.v:2541.33-2541.254" + cell $or $or$ls180.v:2541$237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2550$235_Y - connect \B $and$ls180.v:2550$236_Y - connect \Y $or$ls180.v:2550$237_Y + connect \A $or$ls180.v:2541$235_Y + connect \B $and$ls180.v:2541$236_Y + connect \Y $or$ls180.v:2541$237_Y end - attribute \src "ls180.v:2550.32-2550.329" - cell $or $or$ls180.v:2550$239 + attribute \src "ls180.v:2541.32-2541.329" + cell $or $or$ls180.v:2541$239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2550$237_Y - connect \B $and$ls180.v:2550$238_Y - connect \Y $or$ls180.v:2550$239_Y + connect \A $or$ls180.v:2541$237_Y + connect \B $and$ls180.v:2541$238_Y + connect \Y $or$ls180.v:2541$239_Y end - attribute \src "ls180.v:2551.35-2551.182" - cell $or $or$ls180.v:2551$242 + attribute \src "ls180.v:2542.35-2542.182" + cell $or $or$ls180.v:2542$242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2551$240_Y - connect \B $and$ls180.v:2551$241_Y - connect \Y $or$ls180.v:2551$242_Y + connect \A $and$ls180.v:2542$240_Y + connect \B $and$ls180.v:2542$241_Y + connect \Y $or$ls180.v:2542$242_Y end - attribute \src "ls180.v:2551.34-2551.258" - cell $or $or$ls180.v:2551$244 + attribute \src "ls180.v:2542.34-2542.258" + cell $or $or$ls180.v:2542$244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2551$242_Y - connect \B $and$ls180.v:2551$243_Y - connect \Y $or$ls180.v:2551$244_Y + connect \A $or$ls180.v:2542$242_Y + connect \B $and$ls180.v:2542$243_Y + connect \Y $or$ls180.v:2542$244_Y end - attribute \src "ls180.v:2551.33-2551.334" - cell $or $or$ls180.v:2551$246 + attribute \src "ls180.v:2542.33-2542.334" + cell $or $or$ls180.v:2542$246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2551$244_Y - connect \B $and$ls180.v:2551$245_Y - connect \Y $or$ls180.v:2551$246_Y + connect \A $or$ls180.v:2542$244_Y + connect \B $and$ls180.v:2542$245_Y + connect \Y $or$ls180.v:2542$246_Y end - attribute \src "ls180.v:2564.138-2564.292" - cell $or $or$ls180.v:2564$260 + attribute \src "ls180.v:2555.138-2555.292" + cell $or $or$ls180.v:2555$260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2564$259_Y + connect \A $not$ls180.v:2555$259_Y connect \B \sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:2564$260_Y + connect \Y $or$ls180.v:2555$260_Y end - attribute \src "ls180.v:2564.65-2564.446" - cell $or $or$ls180.v:2564$265 + attribute \src "ls180.v:2555.65-2555.446" + cell $or $or$ls180.v:2555$265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2564$261_Y - connect \B $and$ls180.v:2564$264_Y - connect \Y $or$ls180.v:2564$265_Y + connect \A $and$ls180.v:2555$261_Y + connect \B $and$ls180.v:2555$264_Y + connect \Y $or$ls180.v:2555$265_Y end - attribute \src "ls180.v:2565.138-2565.292" - cell $or $or$ls180.v:2565$273 + attribute \src "ls180.v:2556.138-2556.292" + cell $or $or$ls180.v:2556$273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2565$272_Y + connect \A $not$ls180.v:2556$272_Y connect \B \sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:2565$273_Y + connect \Y $or$ls180.v:2556$273_Y end - attribute \src "ls180.v:2565.65-2565.446" - cell $or $or$ls180.v:2565$278 + attribute \src "ls180.v:2556.65-2556.446" + cell $or $or$ls180.v:2556$278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2565$274_Y - connect \B $and$ls180.v:2565$277_Y - connect \Y $or$ls180.v:2565$278_Y + connect \A $and$ls180.v:2556$274_Y + connect \B $and$ls180.v:2556$277_Y + connect \Y $or$ls180.v:2556$278_Y end - attribute \src "ls180.v:2566.138-2566.292" - cell $or $or$ls180.v:2566$286 + attribute \src "ls180.v:2557.138-2557.292" + cell $or $or$ls180.v:2557$286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2566$285_Y + connect \A $not$ls180.v:2557$285_Y connect \B \sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:2566$286_Y + connect \Y $or$ls180.v:2557$286_Y end - attribute \src "ls180.v:2566.65-2566.446" - cell $or $or$ls180.v:2566$291 + attribute \src "ls180.v:2557.65-2557.446" + cell $or $or$ls180.v:2557$291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2566$287_Y - connect \B $and$ls180.v:2566$290_Y - connect \Y $or$ls180.v:2566$291_Y + connect \A $and$ls180.v:2557$287_Y + connect \B $and$ls180.v:2557$290_Y + connect \Y $or$ls180.v:2557$291_Y end - attribute \src "ls180.v:2567.138-2567.292" - cell $or $or$ls180.v:2567$299 + attribute \src "ls180.v:2558.138-2558.292" + cell $or $or$ls180.v:2558$299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2567$298_Y + connect \A $not$ls180.v:2558$298_Y connect \B \sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:2567$299_Y + connect \Y $or$ls180.v:2558$299_Y end - attribute \src "ls180.v:2567.65-2567.446" - cell $or $or$ls180.v:2567$304 + attribute \src "ls180.v:2558.65-2558.446" + cell $or $or$ls180.v:2558$304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2567$300_Y - connect \B $and$ls180.v:2567$303_Y - connect \Y $or$ls180.v:2567$304_Y + connect \A $and$ls180.v:2558$300_Y + connect \B $and$ls180.v:2558$303_Y + connect \Y $or$ls180.v:2558$304_Y end - attribute \src "ls180.v:2594.31-2594.89" - cell $or $or$ls180.v:2594$310 + attribute \src "ls180.v:2585.31-2585.89" + cell $or $or$ls180.v:2585$310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:2594$309_Y - connect \Y $or$ls180.v:2594$310_Y + connect \B $not$ls180.v:2585$309_Y + connect \Y $or$ls180.v:2585$310_Y end - attribute \src "ls180.v:2597.138-2597.292" - cell $or $or$ls180.v:2597$318 + attribute \src "ls180.v:2588.138-2588.292" + cell $or $or$ls180.v:2588$318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2597$317_Y + connect \A $not$ls180.v:2588$317_Y connect \B \sdram_choose_req_want_activates - connect \Y $or$ls180.v:2597$318_Y + connect \Y $or$ls180.v:2588$318_Y end - attribute \src "ls180.v:2597.65-2597.446" - cell $or $or$ls180.v:2597$323 + attribute \src "ls180.v:2588.65-2588.446" + cell $or $or$ls180.v:2588$323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2597$319_Y - connect \B $and$ls180.v:2597$322_Y - connect \Y $or$ls180.v:2597$323_Y + connect \A $and$ls180.v:2588$319_Y + connect \B $and$ls180.v:2588$322_Y + connect \Y $or$ls180.v:2588$323_Y end - attribute \src "ls180.v:2598.138-2598.292" - cell $or $or$ls180.v:2598$331 + attribute \src "ls180.v:2589.138-2589.292" + cell $or $or$ls180.v:2589$331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2598$330_Y + connect \A $not$ls180.v:2589$330_Y connect \B \sdram_choose_req_want_activates - connect \Y $or$ls180.v:2598$331_Y + connect \Y $or$ls180.v:2589$331_Y end - attribute \src "ls180.v:2598.65-2598.446" - cell $or $or$ls180.v:2598$336 + attribute \src "ls180.v:2589.65-2589.446" + cell $or $or$ls180.v:2589$336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2598$332_Y - connect \B $and$ls180.v:2598$335_Y - connect \Y $or$ls180.v:2598$336_Y + connect \A $and$ls180.v:2589$332_Y + connect \B $and$ls180.v:2589$335_Y + connect \Y $or$ls180.v:2589$336_Y end - attribute \src "ls180.v:2599.138-2599.292" - cell $or $or$ls180.v:2599$344 + attribute \src "ls180.v:2590.138-2590.292" + cell $or $or$ls180.v:2590$344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2599$343_Y + connect \A $not$ls180.v:2590$343_Y connect \B \sdram_choose_req_want_activates - connect \Y $or$ls180.v:2599$344_Y + connect \Y $or$ls180.v:2590$344_Y end - attribute \src "ls180.v:2599.65-2599.446" - cell $or $or$ls180.v:2599$349 + attribute \src "ls180.v:2590.65-2590.446" + cell $or $or$ls180.v:2590$349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2599$345_Y - connect \B $and$ls180.v:2599$348_Y - connect \Y $or$ls180.v:2599$349_Y + connect \A $and$ls180.v:2590$345_Y + connect \B $and$ls180.v:2590$348_Y + connect \Y $or$ls180.v:2590$349_Y end - attribute \src "ls180.v:2600.138-2600.292" - cell $or $or$ls180.v:2600$357 + attribute \src "ls180.v:2591.138-2591.292" + cell $or $or$ls180.v:2591$357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2600$356_Y + connect \A $not$ls180.v:2591$356_Y connect \B \sdram_choose_req_want_activates - connect \Y $or$ls180.v:2600$357_Y + connect \Y $or$ls180.v:2591$357_Y end - attribute \src "ls180.v:2600.65-2600.446" - cell $or $or$ls180.v:2600$362 + attribute \src "ls180.v:2591.65-2591.446" + cell $or $or$ls180.v:2591$362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2600$358_Y - connect \B $and$ls180.v:2600$361_Y - connect \Y $or$ls180.v:2600$362_Y + connect \A $and$ls180.v:2591$358_Y + connect \B $and$ls180.v:2591$361_Y + connect \Y $or$ls180.v:2591$362_Y end - attribute \src "ls180.v:2663.31-2663.89" - cell $or $or$ls180.v:2663$396 + attribute \src "ls180.v:2654.31-2654.89" + cell $or $or$ls180.v:2654$396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_ready - connect \B $not$ls180.v:2663$395_Y - connect \Y $or$ls180.v:2663$396_Y + connect \B $not$ls180.v:2654$395_Y + connect \Y $or$ls180.v:2654$396_Y end - attribute \src "ls180.v:2684.57-2684.191" - cell $or $or$ls180.v:2684$403 + attribute \src "ls180.v:2675.57-2675.191" + cell $or $or$ls180.v:2675$403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2684$402_Y + connect \A $not$ls180.v:2675$402_Y connect \B \sdram_ras_allowed - connect \Y $or$ls180.v:2684$403_Y + connect \Y $or$ls180.v:2675$403_Y end - attribute \src "ls180.v:2692.10-2692.52" - cell $or $or$ls180.v:2692$406 + attribute \src "ls180.v:2683.10-2683.52" + cell $or $or$ls180.v:2683$406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2692$405_Y + connect \A $not$ls180.v:2683$405_Y connect \B \sdram_max_time1 - connect \Y $or$ls180.v:2692$406_Y + connect \Y $or$ls180.v:2683$406_Y end - attribute \src "ls180.v:2722.57-2722.191" - cell $or $or$ls180.v:2722$412 + attribute \src "ls180.v:2713.57-2713.191" + cell $or $or$ls180.v:2713$412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2722$411_Y + connect \A $not$ls180.v:2713$411_Y connect \B \sdram_ras_allowed - connect \Y $or$ls180.v:2722$412_Y + connect \Y $or$ls180.v:2713$412_Y end - attribute \src "ls180.v:2730.10-2730.51" - cell $or $or$ls180.v:2730$415 + attribute \src "ls180.v:2721.10-2721.51" + cell $or $or$ls180.v:2721$415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2730$414_Y + connect \A $not$ls180.v:2721$414_Y connect \B \sdram_max_time0 - connect \Y $or$ls180.v:2730$415_Y + connect \Y $or$ls180.v:2721$415_Y end - attribute \src "ls180.v:2740.91-2740.185" - cell $or $or$ls180.v:2740$419 + attribute \src "ls180.v:2731.91-2731.185" + cell $or $or$ls180.v:2731$419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked0 - connect \B $and$ls180.v:2740$418_Y - connect \Y $or$ls180.v:2740$419_Y + connect \B $and$ls180.v:2731$418_Y + connect \Y $or$ls180.v:2731$419_Y end - attribute \src "ls180.v:2740.90-2740.260" - cell $or $or$ls180.v:2740$422 + attribute \src "ls180.v:2731.90-2731.260" + cell $or $or$ls180.v:2731$422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2740$419_Y - connect \B $and$ls180.v:2740$421_Y - connect \Y $or$ls180.v:2740$422_Y + connect \A $or$ls180.v:2731$419_Y + connect \B $and$ls180.v:2731$421_Y + connect \Y $or$ls180.v:2731$422_Y end - attribute \src "ls180.v:2740.89-2740.335" - cell $or $or$ls180.v:2740$425 + attribute \src "ls180.v:2731.89-2731.335" + cell $or $or$ls180.v:2731$425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2740$422_Y - connect \B $and$ls180.v:2740$424_Y - connect \Y $or$ls180.v:2740$425_Y + connect \A $or$ls180.v:2731$422_Y + connect \B $and$ls180.v:2731$424_Y + connect \Y $or$ls180.v:2731$425_Y end - attribute \src "ls180.v:2745.91-2745.185" - cell $or $or$ls180.v:2745$435 + attribute \src "ls180.v:2736.91-2736.185" + cell $or $or$ls180.v:2736$435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked1 - connect \B $and$ls180.v:2745$434_Y - connect \Y $or$ls180.v:2745$435_Y + connect \B $and$ls180.v:2736$434_Y + connect \Y $or$ls180.v:2736$435_Y end - attribute \src "ls180.v:2745.90-2745.260" - cell $or $or$ls180.v:2745$438 + attribute \src "ls180.v:2736.90-2736.260" + cell $or $or$ls180.v:2736$438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2745$435_Y - connect \B $and$ls180.v:2745$437_Y - connect \Y $or$ls180.v:2745$438_Y + connect \A $or$ls180.v:2736$435_Y + connect \B $and$ls180.v:2736$437_Y + connect \Y $or$ls180.v:2736$438_Y end - attribute \src "ls180.v:2745.89-2745.335" - cell $or $or$ls180.v:2745$441 + attribute \src "ls180.v:2736.89-2736.335" + cell $or $or$ls180.v:2736$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2745$438_Y - connect \B $and$ls180.v:2745$440_Y - connect \Y $or$ls180.v:2745$441_Y + connect \A $or$ls180.v:2736$438_Y + connect \B $and$ls180.v:2736$440_Y + connect \Y $or$ls180.v:2736$441_Y end - attribute \src "ls180.v:2750.91-2750.185" - cell $or $or$ls180.v:2750$451 + attribute \src "ls180.v:2741.91-2741.185" + cell $or $or$ls180.v:2741$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked2 - connect \B $and$ls180.v:2750$450_Y - connect \Y $or$ls180.v:2750$451_Y + connect \B $and$ls180.v:2741$450_Y + connect \Y $or$ls180.v:2741$451_Y end - attribute \src "ls180.v:2750.90-2750.260" - cell $or $or$ls180.v:2750$454 + attribute \src "ls180.v:2741.90-2741.260" + cell $or $or$ls180.v:2741$454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2750$451_Y - connect \B $and$ls180.v:2750$453_Y - connect \Y $or$ls180.v:2750$454_Y + connect \A $or$ls180.v:2741$451_Y + connect \B $and$ls180.v:2741$453_Y + connect \Y $or$ls180.v:2741$454_Y end - attribute \src "ls180.v:2750.89-2750.335" - cell $or $or$ls180.v:2750$457 + attribute \src "ls180.v:2741.89-2741.335" + cell $or $or$ls180.v:2741$457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2750$454_Y - connect \B $and$ls180.v:2750$456_Y - connect \Y $or$ls180.v:2750$457_Y + connect \A $or$ls180.v:2741$454_Y + connect \B $and$ls180.v:2741$456_Y + connect \Y $or$ls180.v:2741$457_Y end - attribute \src "ls180.v:2755.91-2755.185" - cell $or $or$ls180.v:2755$467 + attribute \src "ls180.v:2746.91-2746.185" + cell $or $or$ls180.v:2746$467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked3 - connect \B $and$ls180.v:2755$466_Y - connect \Y $or$ls180.v:2755$467_Y + connect \B $and$ls180.v:2746$466_Y + connect \Y $or$ls180.v:2746$467_Y end - attribute \src "ls180.v:2755.90-2755.260" - cell $or $or$ls180.v:2755$470 + attribute \src "ls180.v:2746.90-2746.260" + cell $or $or$ls180.v:2746$470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2755$467_Y - connect \B $and$ls180.v:2755$469_Y - connect \Y $or$ls180.v:2755$470_Y + connect \A $or$ls180.v:2746$467_Y + connect \B $and$ls180.v:2746$469_Y + connect \Y $or$ls180.v:2746$470_Y end - attribute \src "ls180.v:2755.89-2755.335" - cell $or $or$ls180.v:2755$473 + attribute \src "ls180.v:2746.89-2746.335" + cell $or $or$ls180.v:2746$473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2755$470_Y - connect \B $and$ls180.v:2755$472_Y - connect \Y $or$ls180.v:2755$473_Y + connect \A $or$ls180.v:2746$470_Y + connect \B $and$ls180.v:2746$472_Y + connect \Y $or$ls180.v:2746$473_Y end - attribute \src "ls180.v:2760.127-2760.221" - cell $or $or$ls180.v:2760$484 + attribute \src "ls180.v:2751.127-2751.221" + cell $or $or$ls180.v:2751$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked0 - connect \B $and$ls180.v:2760$483_Y - connect \Y $or$ls180.v:2760$484_Y + connect \B $and$ls180.v:2751$483_Y + connect \Y $or$ls180.v:2751$484_Y end - attribute \src "ls180.v:2760.126-2760.296" - cell $or $or$ls180.v:2760$487 + attribute \src "ls180.v:2751.126-2751.296" + cell $or $or$ls180.v:2751$487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$484_Y - connect \B $and$ls180.v:2760$486_Y - connect \Y $or$ls180.v:2760$487_Y + connect \A $or$ls180.v:2751$484_Y + connect \B $and$ls180.v:2751$486_Y + connect \Y $or$ls180.v:2751$487_Y end - attribute \src "ls180.v:2760.125-2760.371" - cell $or $or$ls180.v:2760$490 + attribute \src "ls180.v:2751.125-2751.371" + cell $or $or$ls180.v:2751$490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$487_Y - connect \B $and$ls180.v:2760$489_Y - connect \Y $or$ls180.v:2760$490_Y + connect \A $or$ls180.v:2751$487_Y + connect \B $and$ls180.v:2751$489_Y + connect \Y $or$ls180.v:2751$490_Y end - attribute \src "ls180.v:2760.29-2760.406" - cell $or $or$ls180.v:2760$495 + attribute \src "ls180.v:2751.29-2751.406" + cell $or $or$ls180.v:2751$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:2760$494_Y - connect \Y $or$ls180.v:2760$495_Y + connect \B $and$ls180.v:2751$494_Y + connect \Y $or$ls180.v:2751$495_Y end - attribute \src "ls180.v:2760.501-2760.595" - cell $or $or$ls180.v:2760$500 + attribute \src "ls180.v:2751.501-2751.595" + cell $or $or$ls180.v:2751$500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked1 - connect \B $and$ls180.v:2760$499_Y - connect \Y $or$ls180.v:2760$500_Y + connect \B $and$ls180.v:2751$499_Y + connect \Y $or$ls180.v:2751$500_Y end - attribute \src "ls180.v:2760.500-2760.670" - cell $or $or$ls180.v:2760$503 + attribute \src "ls180.v:2751.500-2751.670" + cell $or $or$ls180.v:2751$503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$500_Y - connect \B $and$ls180.v:2760$502_Y - connect \Y $or$ls180.v:2760$503_Y + connect \A $or$ls180.v:2751$500_Y + connect \B $and$ls180.v:2751$502_Y + connect \Y $or$ls180.v:2751$503_Y end - attribute \src "ls180.v:2760.499-2760.745" - cell $or $or$ls180.v:2760$506 + attribute \src "ls180.v:2751.499-2751.745" + cell $or $or$ls180.v:2751$506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$503_Y - connect \B $and$ls180.v:2760$505_Y - connect \Y $or$ls180.v:2760$506_Y + connect \A $or$ls180.v:2751$503_Y + connect \B $and$ls180.v:2751$505_Y + connect \Y $or$ls180.v:2751$506_Y end - attribute \src "ls180.v:2760.28-2760.780" - cell $or $or$ls180.v:2760$511 + attribute \src "ls180.v:2751.28-2751.780" + cell $or $or$ls180.v:2751$511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$495_Y - connect \B $and$ls180.v:2760$510_Y - connect \Y $or$ls180.v:2760$511_Y + connect \A $or$ls180.v:2751$495_Y + connect \B $and$ls180.v:2751$510_Y + connect \Y $or$ls180.v:2751$511_Y end - attribute \src "ls180.v:2760.875-2760.969" - cell $or $or$ls180.v:2760$516 + attribute \src "ls180.v:2751.875-2751.969" + cell $or $or$ls180.v:2751$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked2 - connect \B $and$ls180.v:2760$515_Y - connect \Y $or$ls180.v:2760$516_Y + connect \B $and$ls180.v:2751$515_Y + connect \Y $or$ls180.v:2751$516_Y end - attribute \src "ls180.v:2760.874-2760.1044" - cell $or $or$ls180.v:2760$519 + attribute \src "ls180.v:2751.874-2751.1044" + cell $or $or$ls180.v:2751$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$516_Y - connect \B $and$ls180.v:2760$518_Y - connect \Y $or$ls180.v:2760$519_Y + connect \A $or$ls180.v:2751$516_Y + connect \B $and$ls180.v:2751$518_Y + connect \Y $or$ls180.v:2751$519_Y end - attribute \src "ls180.v:2760.873-2760.1119" - cell $or $or$ls180.v:2760$522 + attribute \src "ls180.v:2751.873-2751.1119" + cell $or $or$ls180.v:2751$522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$519_Y - connect \B $and$ls180.v:2760$521_Y - connect \Y $or$ls180.v:2760$522_Y + connect \A $or$ls180.v:2751$519_Y + connect \B $and$ls180.v:2751$521_Y + connect \Y $or$ls180.v:2751$522_Y end - attribute \src "ls180.v:2760.27-2760.1154" - cell $or $or$ls180.v:2760$527 + attribute \src "ls180.v:2751.27-2751.1154" + cell $or $or$ls180.v:2751$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$511_Y - connect \B $and$ls180.v:2760$526_Y - connect \Y $or$ls180.v:2760$527_Y + connect \A $or$ls180.v:2751$511_Y + connect \B $and$ls180.v:2751$526_Y + connect \Y $or$ls180.v:2751$527_Y end - attribute \src "ls180.v:2760.1249-2760.1343" - cell $or $or$ls180.v:2760$532 + attribute \src "ls180.v:2751.1249-2751.1343" + cell $or $or$ls180.v:2751$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked3 - connect \B $and$ls180.v:2760$531_Y - connect \Y $or$ls180.v:2760$532_Y + connect \B $and$ls180.v:2751$531_Y + connect \Y $or$ls180.v:2751$532_Y end - attribute \src "ls180.v:2760.1248-2760.1418" - cell $or $or$ls180.v:2760$535 + attribute \src "ls180.v:2751.1248-2751.1418" + cell $or $or$ls180.v:2751$535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$532_Y - connect \B $and$ls180.v:2760$534_Y - connect \Y $or$ls180.v:2760$535_Y + connect \A $or$ls180.v:2751$532_Y + connect \B $and$ls180.v:2751$534_Y + connect \Y $or$ls180.v:2751$535_Y end - attribute \src "ls180.v:2760.1247-2760.1493" - cell $or $or$ls180.v:2760$538 + attribute \src "ls180.v:2751.1247-2751.1493" + cell $or $or$ls180.v:2751$538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$535_Y - connect \B $and$ls180.v:2760$537_Y - connect \Y $or$ls180.v:2760$538_Y + connect \A $or$ls180.v:2751$535_Y + connect \B $and$ls180.v:2751$537_Y + connect \Y $or$ls180.v:2751$538_Y end - attribute \src "ls180.v:2760.26-2760.1528" - cell $or $or$ls180.v:2760$543 + attribute \src "ls180.v:2751.26-2751.1528" + cell $or $or$ls180.v:2751$543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:2760$527_Y - connect \B $and$ls180.v:2760$542_Y - connect \Y $or$ls180.v:2760$543_Y + connect \A $or$ls180.v:2751$527_Y + connect \B $and$ls180.v:2751$542_Y + connect \Y $or$ls180.v:2751$543_Y end - attribute \src "ls180.v:2823.10-2823.42" - cell $or $or$ls180.v:2823$552 + attribute \src "ls180.v:2814.10-2814.42" + cell $or $or$ls180.v:2814$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259183,10 +258975,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \litedram_wb_ack connect \B \converter_skip - connect \Y $or$ls180.v:2823$552_Y + connect \Y $or$ls180.v:2814$552_Y end - attribute \src "ls180.v:2850.30-2850.59" - cell $or $or$ls180.v:2850$562 + attribute \src "ls180.v:2841.30-2841.59" + cell $or $or$ls180.v:2841$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259194,10 +258986,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_valid connect \B \cmd_consumed - connect \Y $or$ls180.v:2850$562_Y + connect \Y $or$ls180.v:2841$562_Y end - attribute \src "ls180.v:2851.29-2851.58" - cell $or $or$ls180.v:2851$566 + attribute \src "ls180.v:2842.29-2842.58" + cell $or $or$ls180.v:2842$566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259205,76 +258997,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \port_cmd_valid connect \B \cmd_consumed - connect \Y $or$ls180.v:2851$566_Y + connect \Y $or$ls180.v:2842$566_Y end - attribute \src "ls180.v:2852.38-2852.100" - cell $or $or$ls180.v:2852$572 + attribute \src "ls180.v:2843.38-2843.100" + cell $or $or$ls180.v:2843$572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2852$569_Y - connect \B $and$ls180.v:2852$571_Y - connect \Y $or$ls180.v:2852$572_Y + connect \A $and$ls180.v:2843$569_Y + connect \B $and$ls180.v:2843$571_Y + connect \Y $or$ls180.v:2843$572_Y end - attribute \src "ls180.v:2853.19-2853.67" - cell $or $or$ls180.v:2853$575 + attribute \src "ls180.v:2844.19-2844.67" + cell $or $or$ls180.v:2844$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2853$574_Y + connect \A $and$ls180.v:2844$574_Y connect \B \cmd_consumed - connect \Y $or$ls180.v:2853$575_Y + connect \Y $or$ls180.v:2844$575_Y end - attribute \src "ls180.v:2854.21-2854.75" - cell $or $or$ls180.v:2854$577 + attribute \src "ls180.v:2845.21-2845.75" + cell $or $or$ls180.v:2845$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2854$576_Y + connect \A $and$ls180.v:2845$576_Y connect \B \wdata_consumed - connect \Y $or$ls180.v:2854$577_Y + connect \Y $or$ls180.v:2845$577_Y end - attribute \src "ls180.v:2884.32-2884.59" - cell $or $or$ls180.v:2884$585 + attribute \src "ls180.v:2875.32-2875.59" + cell $or $or$ls180.v:2875$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_clear - connect \B $and$ls180.v:2884$584_Y - connect \Y $or$ls180.v:2884$585_Y + connect \B $and$ls180.v:2875$584_Y + connect \Y $or$ls180.v:2875$585_Y end - attribute \src "ls180.v:2908.15-2908.124" - cell $or $or$ls180.v:2908$595 + attribute \src "ls180.v:2899.15-2899.124" + cell $or $or$ls180.v:2899$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2908$593_Y - connect \B $and$ls180.v:2908$594_Y - connect \Y $or$ls180.v:2908$595_Y + connect \A $and$ls180.v:2899$593_Y + connect \B $and$ls180.v:2899$594_Y + connect \Y $or$ls180.v:2899$595_Y end - attribute \src "ls180.v:2923.60-2923.92" - cell $or $or$ls180.v:2923$597 + attribute \src "ls180.v:2914.60-2914.92" + cell $or $or$ls180.v:2914$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2923$596_Y + connect \A $not$ls180.v:2914$596_Y connect \B \tx_fifo_re - connect \Y $or$ls180.v:2923$597_Y + connect \Y $or$ls180.v:2914$597_Y end - attribute \src "ls180.v:2934.52-2934.95" - cell $or $or$ls180.v:2934$602 + attribute \src "ls180.v:2925.52-2925.95" + cell $or $or$ls180.v:2925$602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259282,21 +259074,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_writable connect \B \tx_fifo_replace - connect \Y $or$ls180.v:2934$602_Y + connect \Y $or$ls180.v:2925$602_Y end - attribute \src "ls180.v:2953.60-2953.92" - cell $or $or$ls180.v:2953$608 + attribute \src "ls180.v:2944.60-2944.92" + cell $or $or$ls180.v:2944$608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2953$607_Y + connect \A $not$ls180.v:2944$607_Y connect \B \rx_fifo_re - connect \Y $or$ls180.v:2953$608_Y + connect \Y $or$ls180.v:2944$608_Y end - attribute \src "ls180.v:2964.52-2964.95" - cell $or $or$ls180.v:2964$613 + attribute \src "ls180.v:2955.52-2955.95" + cell $or $or$ls180.v:2955$613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259304,10 +259096,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_writable connect \B \rx_fifo_replace - connect \Y $or$ls180.v:2964$613_Y + connect \Y $or$ls180.v:2955$613_Y end - attribute \src "ls180.v:3147.38-3147.83" - cell $or $or$ls180.v:3147$651 + attribute \src "ls180.v:3138.38-3138.83" + cell $or $or$ls180.v:3138$651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259315,54 +259107,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_err connect \B \ram_bus_ram_bus_err - connect \Y $or$ls180.v:3147$651_Y + connect \Y $or$ls180.v:3138$651_Y end - attribute \src "ls180.v:3147.37-3147.120" - cell $or $or$ls180.v:3147$652 + attribute \src "ls180.v:3138.37-3138.120" + cell $or $or$ls180.v:3138$652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3147$651_Y + connect \A $or$ls180.v:3138$651_Y connect \B \libresocsim_libresoc_xics_icp_err - connect \Y $or$ls180.v:3147$652_Y + connect \Y $or$ls180.v:3138$652_Y end - attribute \src "ls180.v:3147.36-3147.157" - cell $or $or$ls180.v:3147$653 + attribute \src "ls180.v:3138.36-3138.157" + cell $or $or$ls180.v:3138$653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3147$652_Y + connect \A $or$ls180.v:3138$652_Y connect \B \libresocsim_libresoc_xics_ics_err - connect \Y $or$ls180.v:3147$653_Y + connect \Y $or$ls180.v:3138$653_Y end - attribute \src "ls180.v:3147.35-3147.173" - cell $or $or$ls180.v:3147$654 + attribute \src "ls180.v:3138.35-3138.173" + cell $or $or$ls180.v:3138$654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3147$653_Y + connect \A $or$ls180.v:3138$653_Y connect \B \wb_sdram_err - connect \Y $or$ls180.v:3147$654_Y + connect \Y $or$ls180.v:3138$654_Y end - attribute \src "ls180.v:3147.34-3147.213" - cell $or $or$ls180.v:3147$655 + attribute \src "ls180.v:3138.34-3138.213" + cell $or $or$ls180.v:3138$655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3147$654_Y + connect \A $or$ls180.v:3138$654_Y connect \B \libresocsim_libresocsim_wishbone_err - connect \Y $or$ls180.v:3147$655_Y + connect \Y $or$ls180.v:3138$655_Y end - attribute \src "ls180.v:3153.33-3153.78" - cell $or $or$ls180.v:3153$660 + attribute \src "ls180.v:3144.33-3144.78" + cell $or $or$ls180.v:3144$660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259370,109 +259162,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_ack connect \B \ram_bus_ram_bus_ack - connect \Y $or$ls180.v:3153$660_Y + connect \Y $or$ls180.v:3144$660_Y end - attribute \src "ls180.v:3153.32-3153.115" - cell $or $or$ls180.v:3153$661 + attribute \src "ls180.v:3144.32-3144.115" + cell $or $or$ls180.v:3144$661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3153$660_Y + connect \A $or$ls180.v:3144$660_Y connect \B \libresocsim_libresoc_xics_icp_ack - connect \Y $or$ls180.v:3153$661_Y + connect \Y $or$ls180.v:3144$661_Y end - attribute \src "ls180.v:3153.31-3153.152" - cell $or $or$ls180.v:3153$662 + attribute \src "ls180.v:3144.31-3144.152" + cell $or $or$ls180.v:3144$662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3153$661_Y + connect \A $or$ls180.v:3144$661_Y connect \B \libresocsim_libresoc_xics_ics_ack - connect \Y $or$ls180.v:3153$662_Y + connect \Y $or$ls180.v:3144$662_Y end - attribute \src "ls180.v:3153.30-3153.168" - cell $or $or$ls180.v:3153$663 + attribute \src "ls180.v:3144.30-3144.168" + cell $or $or$ls180.v:3144$663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3153$662_Y + connect \A $or$ls180.v:3144$662_Y connect \B \wb_sdram_ack - connect \Y $or$ls180.v:3153$663_Y + connect \Y $or$ls180.v:3144$663_Y end - attribute \src "ls180.v:3153.29-3153.208" - cell $or $or$ls180.v:3153$664 + attribute \src "ls180.v:3144.29-3144.208" + cell $or $or$ls180.v:3144$664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3153$663_Y + connect \A $or$ls180.v:3144$663_Y connect \B \libresocsim_libresocsim_wishbone_ack - connect \Y $or$ls180.v:3153$664_Y + connect \Y $or$ls180.v:3144$664_Y end - attribute \src "ls180.v:3154.35-3154.158" - cell $or $or$ls180.v:3154$667 + attribute \src "ls180.v:3145.35-3145.158" + cell $or $or$ls180.v:3145$667 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $and$ls180.v:3154$665_Y - connect \B $and$ls180.v:3154$666_Y - connect \Y $or$ls180.v:3154$667_Y + connect \A $and$ls180.v:3145$665_Y + connect \B $and$ls180.v:3145$666_Y + connect \Y $or$ls180.v:3145$667_Y end - attribute \src "ls180.v:3154.34-3154.234" - cell $or $or$ls180.v:3154$669 + attribute \src "ls180.v:3145.34-3145.234" + cell $or $or$ls180.v:3145$669 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $or$ls180.v:3154$667_Y - connect \B $and$ls180.v:3154$668_Y - connect \Y $or$ls180.v:3154$669_Y + connect \A $or$ls180.v:3145$667_Y + connect \B $and$ls180.v:3145$668_Y + connect \Y $or$ls180.v:3145$669_Y end - attribute \src "ls180.v:3154.33-3154.310" - cell $or $or$ls180.v:3154$671 + attribute \src "ls180.v:3145.33-3145.310" + cell $or $or$ls180.v:3145$671 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $or$ls180.v:3154$669_Y - connect \B $and$ls180.v:3154$670_Y - connect \Y $or$ls180.v:3154$671_Y + connect \A $or$ls180.v:3145$669_Y + connect \B $and$ls180.v:3145$670_Y + connect \Y $or$ls180.v:3145$671_Y end - attribute \src "ls180.v:3154.32-3154.365" - cell $or $or$ls180.v:3154$673 + attribute \src "ls180.v:3145.32-3145.365" + cell $or $or$ls180.v:3145$673 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $or$ls180.v:3154$671_Y - connect \B $and$ls180.v:3154$672_Y - connect \Y $or$ls180.v:3154$673_Y + connect \A $or$ls180.v:3145$671_Y + connect \B $and$ls180.v:3145$672_Y + connect \Y $or$ls180.v:3145$673_Y end - attribute \src "ls180.v:3154.31-3154.444" - cell $or $or$ls180.v:3154$675 + attribute \src "ls180.v:3145.31-3145.444" + cell $or $or$ls180.v:3145$675 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $or$ls180.v:3154$673_Y - connect \B $and$ls180.v:3154$674_Y - connect \Y $or$ls180.v:3154$675_Y + connect \A $or$ls180.v:3145$673_Y + connect \B $and$ls180.v:3145$674_Y + connect \Y $or$ls180.v:3145$675_Y end - attribute \src "ls180.v:3434.52-3434.129" - cell $or $or$ls180.v:3434$1077 + attribute \src "ls180.v:3425.52-3425.129" + cell $or $or$ls180.v:3425$1077 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -259480,208 +259272,208 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \libresocsim_interface0_bank_bus_dat_r connect \B \libresocsim_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:3434$1077_Y + connect \Y $or$ls180.v:3425$1077_Y end - attribute \src "ls180.v:3434.51-3434.170" - cell $or $or$ls180.v:3434$1078 + attribute \src "ls180.v:3425.51-3425.170" + cell $or $or$ls180.v:3425$1078 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:3434$1077_Y + connect \A $or$ls180.v:3425$1077_Y connect \B \libresocsim_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:3434$1078_Y + connect \Y $or$ls180.v:3425$1078_Y end - attribute \src "ls180.v:3434.50-3434.211" - cell $or $or$ls180.v:3434$1079 + attribute \src "ls180.v:3425.50-3425.211" + cell $or $or$ls180.v:3425$1079 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:3434$1078_Y + connect \A $or$ls180.v:3425$1078_Y connect \B \libresocsim_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:3434$1079_Y + connect \Y $or$ls180.v:3425$1079_Y end - attribute \src "ls180.v:3434.49-3434.252" - cell $or $or$ls180.v:3434$1080 + attribute \src "ls180.v:3425.49-3425.252" + cell $or $or$ls180.v:3425$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:3434$1079_Y + connect \A $or$ls180.v:3425$1079_Y connect \B \libresocsim_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:3434$1080_Y + connect \Y $or$ls180.v:3425$1080_Y end - attribute \src "ls180.v:3434.48-3434.293" - cell $or $or$ls180.v:3434$1081 + attribute \src "ls180.v:3425.48-3425.293" + cell $or $or$ls180.v:3425$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:3434$1080_Y + connect \A $or$ls180.v:3425$1080_Y connect \B \libresocsim_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:3434$1081_Y + connect \Y $or$ls180.v:3425$1081_Y end - attribute \src "ls180.v:3434.47-3434.334" - cell $or $or$ls180.v:3434$1082 + attribute \src "ls180.v:3425.47-3425.334" + cell $or $or$ls180.v:3425$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:3434$1081_Y + connect \A $or$ls180.v:3425$1081_Y connect \B \libresocsim_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:3434$1082_Y + connect \Y $or$ls180.v:3425$1082_Y end - attribute \src "ls180.v:3434.46-3434.375" - cell $or $or$ls180.v:3434$1083 + attribute \src "ls180.v:3425.46-3425.375" + cell $or $or$ls180.v:3425$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:3434$1082_Y + connect \A $or$ls180.v:3425$1082_Y connect \B \libresocsim_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:3434$1083_Y + connect \Y $or$ls180.v:3425$1083_Y end - attribute \src "ls180.v:3761.72-3761.166" - cell $or $or$ls180.v:3761$1108 + attribute \src "ls180.v:3752.72-3752.166" + cell $or $or$ls180.v:3752$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked0 - connect \B $and$ls180.v:3761$1107_Y - connect \Y $or$ls180.v:3761$1108_Y + connect \B $and$ls180.v:3752$1107_Y + connect \Y $or$ls180.v:3752$1108_Y end - attribute \src "ls180.v:3761.71-3761.241" - cell $or $or$ls180.v:3761$1111 + attribute \src "ls180.v:3752.71-3752.241" + cell $or $or$ls180.v:3752$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3761$1108_Y - connect \B $and$ls180.v:3761$1110_Y - connect \Y $or$ls180.v:3761$1111_Y + connect \A $or$ls180.v:3752$1108_Y + connect \B $and$ls180.v:3752$1110_Y + connect \Y $or$ls180.v:3752$1111_Y end - attribute \src "ls180.v:3761.70-3761.316" - cell $or $or$ls180.v:3761$1114 + attribute \src "ls180.v:3752.70-3752.316" + cell $or $or$ls180.v:3752$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3761$1111_Y - connect \B $and$ls180.v:3761$1113_Y - connect \Y $or$ls180.v:3761$1114_Y + connect \A $or$ls180.v:3752$1111_Y + connect \B $and$ls180.v:3752$1113_Y + connect \Y $or$ls180.v:3752$1114_Y end - attribute \src "ls180.v:3785.72-3785.166" - cell $or $or$ls180.v:3785$1124 + attribute \src "ls180.v:3776.72-3776.166" + cell $or $or$ls180.v:3776$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked1 - connect \B $and$ls180.v:3785$1123_Y - connect \Y $or$ls180.v:3785$1124_Y + connect \B $and$ls180.v:3776$1123_Y + connect \Y $or$ls180.v:3776$1124_Y end - attribute \src "ls180.v:3785.71-3785.241" - cell $or $or$ls180.v:3785$1127 + attribute \src "ls180.v:3776.71-3776.241" + cell $or $or$ls180.v:3776$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3785$1124_Y - connect \B $and$ls180.v:3785$1126_Y - connect \Y $or$ls180.v:3785$1127_Y + connect \A $or$ls180.v:3776$1124_Y + connect \B $and$ls180.v:3776$1126_Y + connect \Y $or$ls180.v:3776$1127_Y end - attribute \src "ls180.v:3785.70-3785.316" - cell $or $or$ls180.v:3785$1130 + attribute \src "ls180.v:3776.70-3776.316" + cell $or $or$ls180.v:3776$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3785$1127_Y - connect \B $and$ls180.v:3785$1129_Y - connect \Y $or$ls180.v:3785$1130_Y + connect \A $or$ls180.v:3776$1127_Y + connect \B $and$ls180.v:3776$1129_Y + connect \Y $or$ls180.v:3776$1130_Y end - attribute \src "ls180.v:3809.72-3809.166" - cell $or $or$ls180.v:3809$1140 + attribute \src "ls180.v:3800.72-3800.166" + cell $or $or$ls180.v:3800$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked2 - connect \B $and$ls180.v:3809$1139_Y - connect \Y $or$ls180.v:3809$1140_Y + connect \B $and$ls180.v:3800$1139_Y + connect \Y $or$ls180.v:3800$1140_Y end - attribute \src "ls180.v:3809.71-3809.241" - cell $or $or$ls180.v:3809$1143 + attribute \src "ls180.v:3800.71-3800.241" + cell $or $or$ls180.v:3800$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3809$1140_Y - connect \B $and$ls180.v:3809$1142_Y - connect \Y $or$ls180.v:3809$1143_Y + connect \A $or$ls180.v:3800$1140_Y + connect \B $and$ls180.v:3800$1142_Y + connect \Y $or$ls180.v:3800$1143_Y end - attribute \src "ls180.v:3809.70-3809.316" - cell $or $or$ls180.v:3809$1146 + attribute \src "ls180.v:3800.70-3800.316" + cell $or $or$ls180.v:3800$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3809$1143_Y - connect \B $and$ls180.v:3809$1145_Y - connect \Y $or$ls180.v:3809$1146_Y + connect \A $or$ls180.v:3800$1143_Y + connect \B $and$ls180.v:3800$1145_Y + connect \Y $or$ls180.v:3800$1146_Y end - attribute \src "ls180.v:3833.72-3833.166" - cell $or $or$ls180.v:3833$1156 + attribute \src "ls180.v:3824.72-3824.166" + cell $or $or$ls180.v:3824$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked3 - connect \B $and$ls180.v:3833$1155_Y - connect \Y $or$ls180.v:3833$1156_Y + connect \B $and$ls180.v:3824$1155_Y + connect \Y $or$ls180.v:3824$1156_Y end - attribute \src "ls180.v:3833.71-3833.241" - cell $or $or$ls180.v:3833$1159 + attribute \src "ls180.v:3824.71-3824.241" + cell $or $or$ls180.v:3824$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3833$1156_Y - connect \B $and$ls180.v:3833$1158_Y - connect \Y $or$ls180.v:3833$1159_Y + connect \A $or$ls180.v:3824$1156_Y + connect \B $and$ls180.v:3824$1158_Y + connect \Y $or$ls180.v:3824$1159_Y end - attribute \src "ls180.v:3833.70-3833.316" - cell $or $or$ls180.v:3833$1162 + attribute \src "ls180.v:3824.70-3824.316" + cell $or $or$ls180.v:3824$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3833$1159_Y - connect \B $and$ls180.v:3833$1161_Y - connect \Y $or$ls180.v:3833$1162_Y + connect \A $or$ls180.v:3824$1159_Y + connect \B $and$ls180.v:3824$1161_Y + connect \Y $or$ls180.v:3824$1162_Y end - attribute \src "ls180.v:4286.15-4286.58" - cell $or $or$ls180.v:4286$1216 + attribute \src "ls180.v:4277.15-4277.58" + cell $or $or$ls180.v:4277$1216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259689,10 +259481,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [0] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4286$1216_Y + connect \Y $or$ls180.v:4277$1216_Y end - attribute \src "ls180.v:4287.15-4287.58" - cell $or $or$ls180.v:4287$1217 + attribute \src "ls180.v:4278.15-4278.58" + cell $or $or$ls180.v:4278$1217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259700,10 +259492,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [1] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4287$1217_Y + connect \Y $or$ls180.v:4278$1217_Y end - attribute \src "ls180.v:4288.15-4288.58" - cell $or $or$ls180.v:4288$1218 + attribute \src "ls180.v:4279.15-4279.58" + cell $or $or$ls180.v:4279$1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259711,10 +259503,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [2] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4288$1218_Y + connect \Y $or$ls180.v:4279$1218_Y end - attribute \src "ls180.v:4289.15-4289.58" - cell $or $or$ls180.v:4289$1219 + attribute \src "ls180.v:4280.15-4280.58" + cell $or $or$ls180.v:4280$1219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259722,10 +259514,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [3] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4289$1219_Y + connect \Y $or$ls180.v:4280$1219_Y end - attribute \src "ls180.v:4290.15-4290.58" - cell $or $or$ls180.v:4290$1220 + attribute \src "ls180.v:4281.15-4281.58" + cell $or $or$ls180.v:4281$1220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259733,10 +259525,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [4] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4290$1220_Y + connect \Y $or$ls180.v:4281$1220_Y end - attribute \src "ls180.v:4291.15-4291.58" - cell $or $or$ls180.v:4291$1221 + attribute \src "ls180.v:4282.15-4282.58" + cell $or $or$ls180.v:4282$1221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259744,10 +259536,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [5] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4291$1221_Y + connect \Y $or$ls180.v:4282$1221_Y end - attribute \src "ls180.v:4292.15-4292.58" - cell $or $or$ls180.v:4292$1222 + attribute \src "ls180.v:4283.15-4283.58" + cell $or $or$ls180.v:4283$1222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259755,10 +259547,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [6] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4292$1222_Y + connect \Y $or$ls180.v:4283$1222_Y end - attribute \src "ls180.v:4293.15-4293.58" - cell $or $or$ls180.v:4293$1223 + attribute \src "ls180.v:4284.15-4284.58" + cell $or $or$ls180.v:4284$1223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259766,10 +259558,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [7] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4293$1223_Y + connect \Y $or$ls180.v:4284$1223_Y end - attribute \src "ls180.v:4294.15-4294.58" - cell $or $or$ls180.v:4294$1224 + attribute \src "ls180.v:4285.15-4285.58" + cell $or $or$ls180.v:4285$1224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259777,10 +259569,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [8] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4294$1224_Y + connect \Y $or$ls180.v:4285$1224_Y end - attribute \src "ls180.v:4295.15-4295.58" - cell $or $or$ls180.v:4295$1225 + attribute \src "ls180.v:4286.15-4286.58" + cell $or $or$ls180.v:4286$1225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259788,10 +259580,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [9] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4295$1225_Y + connect \Y $or$ls180.v:4286$1225_Y end - attribute \src "ls180.v:4296.16-4296.60" - cell $or $or$ls180.v:4296$1226 + attribute \src "ls180.v:4287.16-4287.60" + cell $or $or$ls180.v:4287$1226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259799,10 +259591,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [10] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4296$1226_Y + connect \Y $or$ls180.v:4287$1226_Y end - attribute \src "ls180.v:4297.16-4297.60" - cell $or $or$ls180.v:4297$1227 + attribute \src "ls180.v:4288.16-4288.60" + cell $or $or$ls180.v:4288$1227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259810,10 +259602,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [11] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4297$1227_Y + connect \Y $or$ls180.v:4288$1227_Y end - attribute \src "ls180.v:4298.16-4298.60" - cell $or $or$ls180.v:4298$1228 + attribute \src "ls180.v:4289.16-4289.60" + cell $or $or$ls180.v:4289$1228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259821,10 +259613,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [12] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4298$1228_Y + connect \Y $or$ls180.v:4289$1228_Y end - attribute \src "ls180.v:4299.16-4299.60" - cell $or $or$ls180.v:4299$1229 + attribute \src "ls180.v:4290.16-4290.60" + cell $or $or$ls180.v:4290$1229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259832,10 +259624,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [13] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4299$1229_Y + connect \Y $or$ls180.v:4290$1229_Y end - attribute \src "ls180.v:4300.16-4300.60" - cell $or $or$ls180.v:4300$1230 + attribute \src "ls180.v:4291.16-4291.60" + cell $or $or$ls180.v:4291$1230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259843,10 +259635,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [14] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4300$1230_Y + connect \Y $or$ls180.v:4291$1230_Y end - attribute \src "ls180.v:4301.16-4301.60" - cell $or $or$ls180.v:4301$1231 + attribute \src "ls180.v:4292.16-4292.60" + cell $or $or$ls180.v:4292$1231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259854,10 +259646,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [15] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4301$1231_Y + connect \Y $or$ls180.v:4292$1231_Y end - attribute \src "ls180.v:4302.16-4302.60" - cell $or $or$ls180.v:4302$1232 + attribute \src "ls180.v:4293.16-4293.60" + cell $or $or$ls180.v:4293$1232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259865,10 +259657,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [16] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4302$1232_Y + connect \Y $or$ls180.v:4293$1232_Y end - attribute \src "ls180.v:4303.16-4303.60" - cell $or $or$ls180.v:4303$1233 + attribute \src "ls180.v:4294.16-4294.60" + cell $or $or$ls180.v:4294$1233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259876,10 +259668,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [17] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4303$1233_Y + connect \Y $or$ls180.v:4294$1233_Y end - attribute \src "ls180.v:4304.16-4304.60" - cell $or $or$ls180.v:4304$1234 + attribute \src "ls180.v:4295.16-4295.60" + cell $or $or$ls180.v:4295$1234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259887,10 +259679,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [18] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4304$1234_Y + connect \Y $or$ls180.v:4295$1234_Y end - attribute \src "ls180.v:4305.16-4305.60" - cell $or $or$ls180.v:4305$1235 + attribute \src "ls180.v:4296.16-4296.60" + cell $or $or$ls180.v:4296$1235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259898,10 +259690,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [19] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4305$1235_Y + connect \Y $or$ls180.v:4296$1235_Y end - attribute \src "ls180.v:4306.16-4306.60" - cell $or $or$ls180.v:4306$1236 + attribute \src "ls180.v:4297.16-4297.60" + cell $or $or$ls180.v:4297$1236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259909,10 +259701,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [20] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4306$1236_Y + connect \Y $or$ls180.v:4297$1236_Y end - attribute \src "ls180.v:4307.16-4307.60" - cell $or $or$ls180.v:4307$1237 + attribute \src "ls180.v:4298.16-4298.60" + cell $or $or$ls180.v:4298$1237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259920,10 +259712,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [21] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4307$1237_Y + connect \Y $or$ls180.v:4298$1237_Y end - attribute \src "ls180.v:4308.16-4308.60" - cell $or $or$ls180.v:4308$1238 + attribute \src "ls180.v:4299.16-4299.60" + cell $or $or$ls180.v:4299$1238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259931,10 +259723,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [22] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4308$1238_Y + connect \Y $or$ls180.v:4299$1238_Y end - attribute \src "ls180.v:4309.16-4309.60" - cell $or $or$ls180.v:4309$1239 + attribute \src "ls180.v:4300.16-4300.60" + cell $or $or$ls180.v:4300$1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259942,10 +259734,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [23] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4309$1239_Y + connect \Y $or$ls180.v:4300$1239_Y end - attribute \src "ls180.v:4310.16-4310.60" - cell $or $or$ls180.v:4310$1240 + attribute \src "ls180.v:4301.16-4301.60" + cell $or $or$ls180.v:4301$1240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259953,10 +259745,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [24] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4310$1240_Y + connect \Y $or$ls180.v:4301$1240_Y end - attribute \src "ls180.v:4311.16-4311.60" - cell $or $or$ls180.v:4311$1241 + attribute \src "ls180.v:4302.16-4302.60" + cell $or $or$ls180.v:4302$1241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259964,10 +259756,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [25] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4311$1241_Y + connect \Y $or$ls180.v:4302$1241_Y end - attribute \src "ls180.v:4312.16-4312.60" - cell $or $or$ls180.v:4312$1242 + attribute \src "ls180.v:4303.16-4303.60" + cell $or $or$ls180.v:4303$1242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259975,10 +259767,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [26] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4312$1242_Y + connect \Y $or$ls180.v:4303$1242_Y end - attribute \src "ls180.v:4313.16-4313.60" - cell $or $or$ls180.v:4313$1243 + attribute \src "ls180.v:4304.16-4304.60" + cell $or $or$ls180.v:4304$1243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259986,10 +259778,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [27] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4313$1243_Y + connect \Y $or$ls180.v:4304$1243_Y end - attribute \src "ls180.v:4314.16-4314.60" - cell $or $or$ls180.v:4314$1244 + attribute \src "ls180.v:4305.16-4305.60" + cell $or $or$ls180.v:4305$1244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259997,10 +259789,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [28] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4314$1244_Y + connect \Y $or$ls180.v:4305$1244_Y end - attribute \src "ls180.v:4315.16-4315.60" - cell $or $or$ls180.v:4315$1245 + attribute \src "ls180.v:4306.16-4306.60" + cell $or $or$ls180.v:4306$1245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260008,10 +259800,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [29] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4315$1245_Y + connect \Y $or$ls180.v:4306$1245_Y end - attribute \src "ls180.v:4316.16-4316.60" - cell $or $or$ls180.v:4316$1246 + attribute \src "ls180.v:4307.16-4307.60" + cell $or $or$ls180.v:4307$1246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260019,10 +259811,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [30] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4316$1246_Y + connect \Y $or$ls180.v:4307$1246_Y end - attribute \src "ls180.v:4317.16-4317.60" - cell $or $or$ls180.v:4317$1247 + attribute \src "ls180.v:4308.16-4308.60" + cell $or $or$ls180.v:4308$1247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260030,10 +259822,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [31] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4317$1247_Y + connect \Y $or$ls180.v:4308$1247_Y end - attribute \src "ls180.v:4318.16-4318.60" - cell $or $or$ls180.v:4318$1248 + attribute \src "ls180.v:4309.16-4309.60" + cell $or $or$ls180.v:4309$1248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260041,10 +259833,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [32] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4318$1248_Y + connect \Y $or$ls180.v:4309$1248_Y end - attribute \src "ls180.v:4319.16-4319.60" - cell $or $or$ls180.v:4319$1249 + attribute \src "ls180.v:4310.16-4310.60" + cell $or $or$ls180.v:4310$1249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260052,10 +259844,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [33] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4319$1249_Y + connect \Y $or$ls180.v:4310$1249_Y end - attribute \src "ls180.v:4320.16-4320.60" - cell $or $or$ls180.v:4320$1250 + attribute \src "ls180.v:4311.16-4311.60" + cell $or $or$ls180.v:4311$1250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260063,10 +259855,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [34] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4320$1250_Y + connect \Y $or$ls180.v:4311$1250_Y end - attribute \src "ls180.v:4321.16-4321.60" - cell $or $or$ls180.v:4321$1251 + attribute \src "ls180.v:4312.16-4312.60" + cell $or $or$ls180.v:4312$1251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260074,10 +259866,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \nc_1 [35] connect \B \libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:4321$1251_Y + connect \Y $or$ls180.v:4312$1251_Y + end + attribute \src "ls180.v:4313.16-4313.60" + cell $or $or$ls180.v:4313$1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \nc_1 [36] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4313$1252_Y + end + attribute \src "ls180.v:4314.16-4314.60" + cell $or $or$ls180.v:4314$1253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \nc_1 [37] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4314$1253_Y + end + attribute \src "ls180.v:4315.16-4315.60" + cell $or $or$ls180.v:4315$1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \nc_1 [38] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4315$1254_Y + end + attribute \src "ls180.v:4316.16-4316.60" + cell $or $or$ls180.v:4316$1255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \nc_1 [39] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4316$1255_Y end - attribute \src "ls180.v:4322.7-4322.83" - cell $or $or$ls180.v:4322$1252 + attribute \src "ls180.v:4317.7-4317.83" + cell $or $or$ls180.v:4317$1256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260085,10 +259921,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_converted_interface_ack connect \B \libresocsim_converter0_skip - connect \Y $or$ls180.v:4322$1252_Y + connect \Y $or$ls180.v:4317$1256_Y end - attribute \src "ls180.v:4333.7-4333.83" - cell $or $or$ls180.v:4333$1253 + attribute \src "ls180.v:4328.7-4328.83" + cell $or $or$ls180.v:4328$1257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260096,10 +259932,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_converted_interface_ack connect \B \libresocsim_converter1_skip - connect \Y $or$ls180.v:4333$1253_Y + connect \Y $or$ls180.v:4328$1257_Y end - attribute \src "ls180.v:4344.7-4344.83" - cell $or $or$ls180.v:4344$1254 + attribute \src "ls180.v:4339.7-4339.83" + cell $or $or$ls180.v:4339$1258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260107,142 +259943,142 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_converted_interface_ack connect \B \libresocsim_converter2_skip - connect \Y $or$ls180.v:4344$1254_Y + connect \Y $or$ls180.v:4339$1258_Y end - attribute \src "ls180.v:4477.7-4477.97" - cell $or $or$ls180.v:4477$1293 + attribute \src "ls180.v:4472.7-4472.97" + cell $or $or$ls180.v:4472$1297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4477$1292_Y + connect \A $not$ls180.v:4472$1296_Y connect \B \sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:4477$1293_Y + connect \Y $or$ls180.v:4472$1297_Y end - attribute \src "ls180.v:4523.7-4523.97" - cell $or $or$ls180.v:4523$1309 + attribute \src "ls180.v:4518.7-4518.97" + cell $or $or$ls180.v:4518$1313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4523$1308_Y + connect \A $not$ls180.v:4518$1312_Y connect \B \sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:4523$1309_Y + connect \Y $or$ls180.v:4518$1313_Y end - attribute \src "ls180.v:4569.7-4569.97" - cell $or $or$ls180.v:4569$1325 + attribute \src "ls180.v:4564.7-4564.97" + cell $or $or$ls180.v:4564$1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4569$1324_Y + connect \A $not$ls180.v:4564$1328_Y connect \B \sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:4569$1325_Y + connect \Y $or$ls180.v:4564$1329_Y end - attribute \src "ls180.v:4615.7-4615.97" - cell $or $or$ls180.v:4615$1341 + attribute \src "ls180.v:4610.7-4610.97" + cell $or $or$ls180.v:4610$1345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4615$1340_Y + connect \A $not$ls180.v:4610$1344_Y connect \B \sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:4615$1341_Y + connect \Y $or$ls180.v:4610$1345_Y end - attribute \src "ls180.v:4803.45-4803.130" - cell $or $or$ls180.v:4803$1362 + attribute \src "ls180.v:4798.45-4798.130" + cell $or $or$ls180.v:4798$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:4803$1361_Y - connect \Y $or$ls180.v:4803$1362_Y + connect \B $and$ls180.v:4798$1365_Y + connect \Y $or$ls180.v:4798$1366_Y end - attribute \src "ls180.v:4803.44-4803.212" - cell $or $or$ls180.v:4803$1365 + attribute \src "ls180.v:4798.44-4798.212" + cell $or $or$ls180.v:4798$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4803$1362_Y - connect \B $and$ls180.v:4803$1364_Y - connect \Y $or$ls180.v:4803$1365_Y + connect \A $or$ls180.v:4798$1366_Y + connect \B $and$ls180.v:4798$1368_Y + connect \Y $or$ls180.v:4798$1369_Y end - attribute \src "ls180.v:4803.43-4803.294" - cell $or $or$ls180.v:4803$1368 + attribute \src "ls180.v:4798.43-4798.294" + cell $or $or$ls180.v:4798$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4803$1365_Y - connect \B $and$ls180.v:4803$1367_Y - connect \Y $or$ls180.v:4803$1368_Y + connect \A $or$ls180.v:4798$1369_Y + connect \B $and$ls180.v:4798$1371_Y + connect \Y $or$ls180.v:4798$1372_Y end - attribute \src "ls180.v:4803.42-4803.376" - cell $or $or$ls180.v:4803$1371 + attribute \src "ls180.v:4798.42-4798.376" + cell $or $or$ls180.v:4798$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4803$1368_Y - connect \B $and$ls180.v:4803$1370_Y - connect \Y $or$ls180.v:4803$1371_Y + connect \A $or$ls180.v:4798$1372_Y + connect \B $and$ls180.v:4798$1374_Y + connect \Y $or$ls180.v:4798$1375_Y end - attribute \src "ls180.v:4804.46-4804.131" - cell $or $or$ls180.v:4804$1374 + attribute \src "ls180.v:4799.46-4799.131" + cell $or $or$ls180.v:4799$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:4804$1373_Y - connect \Y $or$ls180.v:4804$1374_Y + connect \B $and$ls180.v:4799$1377_Y + connect \Y $or$ls180.v:4799$1378_Y end - attribute \src "ls180.v:4804.45-4804.213" - cell $or $or$ls180.v:4804$1377 + attribute \src "ls180.v:4799.45-4799.213" + cell $or $or$ls180.v:4799$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4804$1374_Y - connect \B $and$ls180.v:4804$1376_Y - connect \Y $or$ls180.v:4804$1377_Y + connect \A $or$ls180.v:4799$1378_Y + connect \B $and$ls180.v:4799$1380_Y + connect \Y $or$ls180.v:4799$1381_Y end - attribute \src "ls180.v:4804.44-4804.295" - cell $or $or$ls180.v:4804$1380 + attribute \src "ls180.v:4799.44-4799.295" + cell $or $or$ls180.v:4799$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4804$1377_Y - connect \B $and$ls180.v:4804$1379_Y - connect \Y $or$ls180.v:4804$1380_Y + connect \A $or$ls180.v:4799$1381_Y + connect \B $and$ls180.v:4799$1383_Y + connect \Y $or$ls180.v:4799$1384_Y end - attribute \src "ls180.v:4804.43-4804.377" - cell $or $or$ls180.v:4804$1383 + attribute \src "ls180.v:4799.43-4799.377" + cell $or $or$ls180.v:4799$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4804$1380_Y - connect \B $and$ls180.v:4804$1382_Y - connect \Y $or$ls180.v:4804$1383_Y + connect \A $or$ls180.v:4799$1384_Y + connect \B $and$ls180.v:4799$1386_Y + connect \Y $or$ls180.v:4799$1387_Y end - attribute \src "ls180.v:4808.7-4808.39" - cell $or $or$ls180.v:4808$1384 + attribute \src "ls180.v:4803.7-4803.39" + cell $or $or$ls180.v:4803$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260250,10 +260086,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \litedram_wb_ack connect \B \converter_skip - connect \Y $or$ls180.v:4808$1384_Y + connect \Y $or$ls180.v:4803$1388_Y end - attribute \src "ls180.v:5717.8-5717.46" - cell $or $or$ls180.v:5717$1546 + attribute \src "ls180.v:5711.8-5711.46" + cell $or $or$ls180.v:5711$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260261,10 +260097,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sys_rst_1 connect \B \libresocsim_libresoc_reset - connect \Y $or$ls180.v:5717$1546_Y + connect \Y $or$ls180.v:5711$1550_Y end - attribute \src "ls180.v:1934.41-1934.84" - cell $sshl $sshl$ls180.v:1934$99 + attribute \src "ls180.v:1925.41-1925.84" + cell $sshl $sshl$ls180.v:1925$99 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260272,10 +260108,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \sdram_bankmachine0_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:1934$99_Y + connect \Y $sshl$ls180.v:1925$99_Y end - attribute \src "ls180.v:2091.41-2091.84" - cell $sshl $sshl$ls180.v:2091$129 + attribute \src "ls180.v:2082.41-2082.84" + cell $sshl $sshl$ls180.v:2082$129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260283,10 +260119,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \sdram_bankmachine1_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:2091$129_Y + connect \Y $sshl$ls180.v:2082$129_Y end - attribute \src "ls180.v:2248.41-2248.84" - cell $sshl $sshl$ls180.v:2248$159 + attribute \src "ls180.v:2239.41-2239.84" + cell $sshl $sshl$ls180.v:2239$159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260294,10 +260130,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \sdram_bankmachine2_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:2248$159_Y + connect \Y $sshl$ls180.v:2239$159_Y end - attribute \src "ls180.v:2405.41-2405.84" - cell $sshl $sshl$ls180.v:2405$189 + attribute \src "ls180.v:2396.41-2396.84" + cell $sshl $sshl$ls180.v:2396$189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260305,10 +260141,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \sdram_bankmachine3_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:2405$189_Y + connect \Y $sshl$ls180.v:2396$189_Y end - attribute \src "ls180.v:1965.58-1965.112" - cell $sub $sub$ls180.v:1965$112 + attribute \src "ls180.v:1956.58-1956.112" + cell $sub $sub$ls180.v:1956$112 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260316,10 +260152,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:1965$112_Y + connect \Y $sub$ls180.v:1956$112_Y end - attribute \src "ls180.v:2122.58-2122.112" - cell $sub $sub$ls180.v:2122$142 + attribute \src "ls180.v:2113.58-2113.112" + cell $sub $sub$ls180.v:2113$142 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260327,10 +260163,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:2122$142_Y + connect \Y $sub$ls180.v:2113$142_Y end - attribute \src "ls180.v:2279.58-2279.112" - cell $sub $sub$ls180.v:2279$172 + attribute \src "ls180.v:2270.58-2270.112" + cell $sub $sub$ls180.v:2270$172 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260338,10 +260174,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:2279$172_Y + connect \Y $sub$ls180.v:2270$172_Y end - attribute \src "ls180.v:2436.58-2436.112" - cell $sub $sub$ls180.v:2436$202 + attribute \src "ls180.v:2427.58-2427.112" + cell $sub $sub$ls180.v:2427$202 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260349,10 +260185,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:2436$202_Y + connect \Y $sub$ls180.v:2427$202_Y end - attribute \src "ls180.v:2842.33-2842.65" - cell $sub $sub$ls180.v:2842$556 + attribute \src "ls180.v:2833.33-2833.65" + cell $sub $sub$ls180.v:2833$556 parameter \A_SIGNED 0 parameter \A_WIDTH 30 parameter \B_SIGNED 0 @@ -260360,10 +260196,10 @@ module \ls180 parameter \Y_WIDTH 31 connect \A \litedram_wb_adr connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:2842$556_Y + connect \Y $sub$ls180.v:2833$556_Y end - attribute \src "ls180.v:2928.26-2928.48" - cell $sub $sub$ls180.v:2928$601 + attribute \src "ls180.v:2919.26-2919.48" + cell $sub $sub$ls180.v:2919$601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -260371,10 +260207,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \tx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:2928$601_Y + connect \Y $sub$ls180.v:2919$601_Y end - attribute \src "ls180.v:2958.26-2958.48" - cell $sub $sub$ls180.v:2958$612 + attribute \src "ls180.v:2949.26-2949.48" + cell $sub $sub$ls180.v:2949$612 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -260382,10 +260218,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \rx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:2958$612_Y + connect \Y $sub$ls180.v:2949$612_Y end - attribute \src "ls180.v:4368.26-4368.50" - cell $sub $sub$ls180.v:4368$1261 + attribute \src "ls180.v:4363.26-4363.50" + cell $sub $sub$ls180.v:4363$1265 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -260393,10 +260229,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \libresocsim_value connect \B 1'1 - connect \Y $sub$ls180.v:4368$1261_Y + connect \Y $sub$ls180.v:4363$1265_Y end - attribute \src "ls180.v:4393.26-4393.51" - cell $sub $sub$ls180.v:4393$1269 + attribute \src "ls180.v:4388.26-4388.51" + cell $sub $sub$ls180.v:4388$1273 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -260404,10 +260240,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \sdram_timer_count1 connect \B 1'1 - connect \Y $sub$ls180.v:4393$1269_Y + connect \Y $sub$ls180.v:4388$1273_Y end - attribute \src "ls180.v:4399.29-4399.57" - cell $sub $sub$ls180.v:4399$1270 + attribute \src "ls180.v:4394.29-4394.57" + cell $sub $sub$ls180.v:4394$1274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260415,10 +260251,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_postponer_count connect \B 1'1 - connect \Y $sub$ls180.v:4399$1270_Y + connect \Y $sub$ls180.v:4394$1274_Y end - attribute \src "ls180.v:4410.31-4410.59" - cell $sub $sub$ls180.v:4410$1273 + attribute \src "ls180.v:4405.31-4405.59" + cell $sub $sub$ls180.v:4405$1277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260426,10 +260262,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_count connect \B 1'1 - connect \Y $sub$ls180.v:4410$1273_Y + connect \Y $sub$ls180.v:4405$1277_Y end - attribute \src "ls180.v:4474.54-4474.106" - cell $sub $sub$ls180.v:4474$1291 + attribute \src "ls180.v:4469.54-4469.106" + cell $sub $sub$ls180.v:4469$1295 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -260437,10 +260273,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:4474$1291_Y + connect \Y $sub$ls180.v:4469$1295_Y end - attribute \src "ls180.v:4493.41-4493.80" - cell $sub $sub$ls180.v:4493$1295 + attribute \src "ls180.v:4488.41-4488.80" + cell $sub $sub$ls180.v:4488$1299 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260448,10 +260284,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:4493$1295_Y + connect \Y $sub$ls180.v:4488$1299_Y end - attribute \src "ls180.v:4520.54-4520.106" - cell $sub $sub$ls180.v:4520$1307 + attribute \src "ls180.v:4515.54-4515.106" + cell $sub $sub$ls180.v:4515$1311 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -260459,10 +260295,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:4520$1307_Y + connect \Y $sub$ls180.v:4515$1311_Y end - attribute \src "ls180.v:4539.41-4539.80" - cell $sub $sub$ls180.v:4539$1311 + attribute \src "ls180.v:4534.41-4534.80" + cell $sub $sub$ls180.v:4534$1315 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260470,10 +260306,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:4539$1311_Y + connect \Y $sub$ls180.v:4534$1315_Y end - attribute \src "ls180.v:4566.54-4566.106" - cell $sub $sub$ls180.v:4566$1323 + attribute \src "ls180.v:4561.54-4561.106" + cell $sub $sub$ls180.v:4561$1327 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -260481,10 +260317,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:4566$1323_Y + connect \Y $sub$ls180.v:4561$1327_Y end - attribute \src "ls180.v:4585.41-4585.80" - cell $sub $sub$ls180.v:4585$1327 + attribute \src "ls180.v:4580.41-4580.80" + cell $sub $sub$ls180.v:4580$1331 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260492,10 +260328,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:4585$1327_Y + connect \Y $sub$ls180.v:4580$1331_Y end - attribute \src "ls180.v:4612.54-4612.106" - cell $sub $sub$ls180.v:4612$1339 + attribute \src "ls180.v:4607.54-4607.106" + cell $sub $sub$ls180.v:4607$1343 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -260503,10 +260339,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:4612$1339_Y + connect \Y $sub$ls180.v:4607$1343_Y end - attribute \src "ls180.v:4631.41-4631.80" - cell $sub $sub$ls180.v:4631$1343 + attribute \src "ls180.v:4626.41-4626.80" + cell $sub $sub$ls180.v:4626$1347 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260514,10 +260350,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:4631$1343_Y + connect \Y $sub$ls180.v:4626$1347_Y end - attribute \src "ls180.v:4642.20-4642.38" - cell $sub $sub$ls180.v:4642$1347 + attribute \src "ls180.v:4637.20-4637.38" + cell $sub $sub$ls180.v:4637$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -260525,10 +260361,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \sdram_time0 connect \B 1'1 - connect \Y $sub$ls180.v:4642$1347_Y + connect \Y $sub$ls180.v:4637$1351_Y end - attribute \src "ls180.v:4649.20-4649.38" - cell $sub $sub$ls180.v:4649$1350 + attribute \src "ls180.v:4644.20-4644.38" + cell $sub $sub$ls180.v:4644$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -260536,10 +260372,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \sdram_time1 connect \B 1'1 - connect \Y $sub$ls180.v:4649$1350_Y + connect \Y $sub$ls180.v:4644$1354_Y end - attribute \src "ls180.v:4781.28-4781.54" - cell $sub $sub$ls180.v:4781$1355 + attribute \src "ls180.v:4776.28-4776.54" + cell $sub $sub$ls180.v:4776$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260547,10 +260383,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sdram_tccdcon_count connect \B 1'1 - connect \Y $sub$ls180.v:4781$1355_Y + connect \Y $sub$ls180.v:4776$1359_Y end - attribute \src "ls180.v:4796.28-4796.54" - cell $sub $sub$ls180.v:4796$1358 + attribute \src "ls180.v:4791.28-4791.54" + cell $sub $sub$ls180.v:4791$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260558,10 +260394,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \sdram_twtrcon_count connect \B 1'1 - connect \Y $sub$ls180.v:4796$1358_Y + connect \Y $sub$ls180.v:4791$1362_Y end - attribute \src "ls180.v:4923.23-4923.44" - cell $sub $sub$ls180.v:4923$1417 + attribute \src "ls180.v:4918.23-4918.44" + cell $sub $sub$ls180.v:4918$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -260569,10 +260405,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \tx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:4923$1417_Y + connect \Y $sub$ls180.v:4918$1421_Y end - attribute \src "ls180.v:4945.23-4945.44" - cell $sub $sub$ls180.v:4945$1428 + attribute \src "ls180.v:4940.23-4940.44" + cell $sub $sub$ls180.v:4940$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -260580,10 +260416,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \rx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:4945$1428_Y + connect \Y $sub$ls180.v:4940$1432_Y end - attribute \src "ls180.v:5010.26-5010.50" - cell $sub $sub$ls180.v:5010$1433 + attribute \src "ls180.v:5005.26-5005.50" + cell $sub $sub$ls180.v:5005$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -260591,10 +260427,10 @@ module \ls180 parameter \Y_WIDTH 20 connect \A \libresocsim_count connect \B 1'1 - connect \Y $sub$ls180.v:5010$1433_Y + connect \Y $sub$ls180.v:5005$1437_Y end attribute \module_not_derived 1 - attribute \src "ls180.v:5623.13-5949.2" + attribute \src "ls180.v:5618.13-5941.2" cell \test_issuer \test_issuer connect \TAP_bus__tck \libresocsim_libresoc_jtag_tck connect \TAP_bus__tdi \libresocsim_libresoc_jtag_tdi @@ -260602,7 +260438,6 @@ module \ls180 connect \TAP_bus__tms \libresocsim_libresoc_jtag_tms connect \busy_o \libresocsim_libresoc0 connect \clk \sys_clk_1 - connect \clk_sel_i \libresocsim_libresoc_clk_sel connect \core_bigendian_i 1'0 connect \dbus__ack \libresocsim_libresoc_dbus_ack connect \dbus__adr \libresocsim_libresoc_dbus_adr @@ -260776,9 +260611,7 @@ module \ls180 connect \pc_i 1'0 connect \pc_i_ok 1'0 connect \pc_o \libresocsim_libresoc2 - connect \pll_18_o \libresocsim_libresoc_pll_18_o - connect \pll_lck_o \libresocsim_libresoc_pll_lck_o - connect \rst $or$ls180.v:5717$1546_Y + connect \rst $or$ls180.v:5711$1550_Y connect \sdr_a_0__core__o \libresocsim_libresoc_constraintmanager_sdram_a [0] connect \sdr_a_0__pad__o \sdram_a [0] connect \sdr_a_10__core__o \libresocsim_libresoc_constraintmanager_sdram_a [10] @@ -260923,473 +260756,441 @@ module \ls180 connect \sdr_we_n__pad__o \sdram_we_n end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$2057 + process $proc$ls180.v:0$2061 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$2058 - sync always - sync init - end - attribute \src "ls180.v:1003.11-1003.29" - process $proc$ls180.v:1003$1942 - assign { } { } - assign $1\i2c_storage[2:0] 3'000 - sync always - sync init - update \i2c_storage $1\i2c_storage[2:0] - end - attribute \src "ls180.v:1004.5-1004.18" - process $proc$ls180.v:1004$1943 - assign { } { } - assign $1\i2c_re[0:0] 1'0 + process $proc$ls180.v:0$2062 sync always sync init - update \i2c_re $1\i2c_re[0:0] end - attribute \src "ls180.v:1008.5-1008.41" - process $proc$ls180.v:1008$1944 + attribute \src "ls180.v:1002.5-1002.41" + process $proc$ls180.v:1002$1948 assign { } { } assign $1\subfragments_converter0_state[0:0] 1'0 sync always sync init update \subfragments_converter0_state $1\subfragments_converter0_state[0:0] end - attribute \src "ls180.v:1009.5-1009.46" - process $proc$ls180.v:1009$1945 + attribute \src "ls180.v:1003.5-1003.46" + process $proc$ls180.v:1003$1949 assign { } { } assign $1\subfragments_converter0_next_state[0:0] 1'0 sync always sync init update \subfragments_converter0_next_state $1\subfragments_converter0_next_state[0:0] end - attribute \src "ls180.v:1010.5-1010.77" - process $proc$ls180.v:1010$1946 + attribute \src "ls180.v:1004.5-1004.77" + process $proc$ls180.v:1004$1950 assign { } { } assign $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0 sync always sync init update \libresocsim_converter0_counter_subfragments_converter0_next_value $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] end - attribute \src "ls180.v:1011.5-1011.80" - process $proc$ls180.v:1011$1947 + attribute \src "ls180.v:1005.5-1005.80" + process $proc$ls180.v:1005$1951 assign { } { } assign $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0 sync always sync init update \libresocsim_converter0_counter_subfragments_converter0_next_value_ce $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:1012.5-1012.41" - process $proc$ls180.v:1012$1948 + attribute \src "ls180.v:1006.5-1006.41" + process $proc$ls180.v:1006$1952 assign { } { } assign $1\subfragments_converter1_state[0:0] 1'0 sync always sync init update \subfragments_converter1_state $1\subfragments_converter1_state[0:0] end - attribute \src "ls180.v:1013.5-1013.46" - process $proc$ls180.v:1013$1949 + attribute \src "ls180.v:1007.5-1007.46" + process $proc$ls180.v:1007$1953 assign { } { } assign $1\subfragments_converter1_next_state[0:0] 1'0 sync always sync init update \subfragments_converter1_next_state $1\subfragments_converter1_next_state[0:0] end - attribute \src "ls180.v:1014.5-1014.77" - process $proc$ls180.v:1014$1950 + attribute \src "ls180.v:1008.5-1008.77" + process $proc$ls180.v:1008$1954 assign { } { } assign $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0 sync always sync init update \libresocsim_converter1_counter_subfragments_converter1_next_value $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] end - attribute \src "ls180.v:1015.5-1015.80" - process $proc$ls180.v:1015$1951 + attribute \src "ls180.v:1009.5-1009.80" + process $proc$ls180.v:1009$1955 assign { } { } assign $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0 sync always sync init update \libresocsim_converter1_counter_subfragments_converter1_next_value_ce $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:1016.5-1016.41" - process $proc$ls180.v:1016$1952 + attribute \src "ls180.v:101.5-101.44" + process $proc$ls180.v:101$1562 + assign { } { } + assign $0\libresocsim_libresoc_jtag_wb_err[0:0] 1'0 + sync always + update \libresocsim_libresoc_jtag_wb_err $0\libresocsim_libresoc_jtag_wb_err[0:0] + sync init + end + attribute \src "ls180.v:1010.5-1010.41" + process $proc$ls180.v:1010$1956 assign { } { } assign $1\subfragments_converter2_state[0:0] 1'0 sync always sync init update \subfragments_converter2_state $1\subfragments_converter2_state[0:0] end - attribute \src "ls180.v:1017.5-1017.46" - process $proc$ls180.v:1017$1953 + attribute \src "ls180.v:1011.5-1011.46" + process $proc$ls180.v:1011$1957 assign { } { } assign $1\subfragments_converter2_next_state[0:0] 1'0 sync always sync init update \subfragments_converter2_next_state $1\subfragments_converter2_next_state[0:0] end - attribute \src "ls180.v:1018.5-1018.77" - process $proc$ls180.v:1018$1954 + attribute \src "ls180.v:1012.5-1012.77" + process $proc$ls180.v:1012$1958 assign { } { } assign $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0 sync always sync init update \libresocsim_converter2_counter_subfragments_converter2_next_value $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] end - attribute \src "ls180.v:1019.5-1019.80" - process $proc$ls180.v:1019$1955 + attribute \src "ls180.v:1013.5-1013.80" + process $proc$ls180.v:1013$1959 assign { } { } assign $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'0 sync always sync init update \libresocsim_converter2_counter_subfragments_converter2_next_value_ce $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:102.5-102.44" - process $proc$ls180.v:102$1557 - assign { } { } - assign $1\libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 - sync always - sync init - update \libresocsim_libresoc_jtag_wb_ack $1\libresocsim_libresoc_jtag_wb_ack[0:0] - end - attribute \src "ls180.v:1020.11-1020.46" - process $proc$ls180.v:1020$1956 + attribute \src "ls180.v:1014.11-1014.46" + process $proc$ls180.v:1014$1960 assign { } { } assign $1\subfragments_refresher_state[1:0] 2'00 sync always sync init update \subfragments_refresher_state $1\subfragments_refresher_state[1:0] end - attribute \src "ls180.v:1021.11-1021.51" - process $proc$ls180.v:1021$1957 + attribute \src "ls180.v:1015.11-1015.51" + process $proc$ls180.v:1015$1961 assign { } { } assign $1\subfragments_refresher_next_state[1:0] 2'00 sync always sync init update \subfragments_refresher_next_state $1\subfragments_refresher_next_state[1:0] end - attribute \src "ls180.v:1022.11-1022.49" - process $proc$ls180.v:1022$1958 + attribute \src "ls180.v:1016.11-1016.49" + process $proc$ls180.v:1016$1962 assign { } { } assign $1\subfragments_bankmachine0_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine0_state $1\subfragments_bankmachine0_state[2:0] end - attribute \src "ls180.v:1023.11-1023.54" - process $proc$ls180.v:1023$1959 + attribute \src "ls180.v:1017.11-1017.54" + process $proc$ls180.v:1017$1963 assign { } { } assign $1\subfragments_bankmachine0_next_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine0_next_state $1\subfragments_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:1024.11-1024.49" - process $proc$ls180.v:1024$1960 + attribute \src "ls180.v:1018.11-1018.49" + process $proc$ls180.v:1018$1964 assign { } { } assign $1\subfragments_bankmachine1_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine1_state $1\subfragments_bankmachine1_state[2:0] end - attribute \src "ls180.v:1025.11-1025.54" - process $proc$ls180.v:1025$1961 + attribute \src "ls180.v:1019.11-1019.54" + process $proc$ls180.v:1019$1965 assign { } { } assign $1\subfragments_bankmachine1_next_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine1_next_state $1\subfragments_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:1026.11-1026.49" - process $proc$ls180.v:1026$1962 + attribute \src "ls180.v:1020.11-1020.49" + process $proc$ls180.v:1020$1966 assign { } { } assign $1\subfragments_bankmachine2_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine2_state $1\subfragments_bankmachine2_state[2:0] end - attribute \src "ls180.v:1027.11-1027.54" - process $proc$ls180.v:1027$1963 + attribute \src "ls180.v:1021.11-1021.54" + process $proc$ls180.v:1021$1967 assign { } { } assign $1\subfragments_bankmachine2_next_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine2_next_state $1\subfragments_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:1028.11-1028.49" - process $proc$ls180.v:1028$1964 + attribute \src "ls180.v:1022.11-1022.49" + process $proc$ls180.v:1022$1968 assign { } { } assign $1\subfragments_bankmachine3_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine3_state $1\subfragments_bankmachine3_state[2:0] end - attribute \src "ls180.v:1029.11-1029.54" - process $proc$ls180.v:1029$1965 + attribute \src "ls180.v:1023.11-1023.54" + process $proc$ls180.v:1023$1969 assign { } { } assign $1\subfragments_bankmachine3_next_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine3_next_state $1\subfragments_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:1030.11-1030.48" - process $proc$ls180.v:1030$1966 + attribute \src "ls180.v:1024.11-1024.48" + process $proc$ls180.v:1024$1970 assign { } { } assign $1\subfragments_multiplexer_state[2:0] 3'000 sync always sync init update \subfragments_multiplexer_state $1\subfragments_multiplexer_state[2:0] end - attribute \src "ls180.v:1031.11-1031.53" - process $proc$ls180.v:1031$1967 + attribute \src "ls180.v:1025.11-1025.53" + process $proc$ls180.v:1025$1971 assign { } { } assign $1\subfragments_multiplexer_next_state[2:0] 3'000 sync always sync init update \subfragments_multiplexer_next_state $1\subfragments_multiplexer_next_state[2:0] end - attribute \src "ls180.v:104.5-104.44" - process $proc$ls180.v:104$1558 - assign { } { } - assign $0\libresocsim_libresoc_jtag_wb_err[0:0] 1'0 - sync always - update \libresocsim_libresoc_jtag_wb_err $0\libresocsim_libresoc_jtag_wb_err[0:0] - sync init - end - attribute \src "ls180.v:1044.5-1044.32" - process $proc$ls180.v:1044$1968 + attribute \src "ls180.v:1038.5-1038.32" + process $proc$ls180.v:1038$1972 assign { } { } assign $0\subfragments_locked0[0:0] 1'0 sync always update \subfragments_locked0 $0\subfragments_locked0[0:0] sync init end - attribute \src "ls180.v:1045.5-1045.32" - process $proc$ls180.v:1045$1969 + attribute \src "ls180.v:1039.5-1039.32" + process $proc$ls180.v:1039$1973 assign { } { } assign $0\subfragments_locked1[0:0] 1'0 sync always update \subfragments_locked1 $0\subfragments_locked1[0:0] sync init end - attribute \src "ls180.v:1046.5-1046.32" - process $proc$ls180.v:1046$1970 + attribute \src "ls180.v:1040.5-1040.32" + process $proc$ls180.v:1040$1974 assign { } { } assign $0\subfragments_locked2[0:0] 1'0 sync always update \subfragments_locked2 $0\subfragments_locked2[0:0] sync init end - attribute \src "ls180.v:1047.5-1047.32" - process $proc$ls180.v:1047$1971 + attribute \src "ls180.v:1041.5-1041.32" + process $proc$ls180.v:1041$1975 assign { } { } assign $0\subfragments_locked3[0:0] 1'0 sync always update \subfragments_locked3 $0\subfragments_locked3[0:0] sync init end - attribute \src "ls180.v:1048.5-1048.47" - process $proc$ls180.v:1048$1972 + attribute \src "ls180.v:1042.5-1042.47" + process $proc$ls180.v:1042$1976 assign { } { } assign $1\subfragments_new_master_wdata_ready[0:0] 1'0 sync always sync init update \subfragments_new_master_wdata_ready $1\subfragments_new_master_wdata_ready[0:0] end - attribute \src "ls180.v:1049.5-1049.48" - process $proc$ls180.v:1049$1973 + attribute \src "ls180.v:1043.5-1043.48" + process $proc$ls180.v:1043$1977 assign { } { } assign $1\subfragments_new_master_rdata_valid0[0:0] 1'0 sync always sync init update \subfragments_new_master_rdata_valid0 $1\subfragments_new_master_rdata_valid0[0:0] end - attribute \src "ls180.v:1050.5-1050.48" - process $proc$ls180.v:1050$1974 + attribute \src "ls180.v:1044.5-1044.48" + process $proc$ls180.v:1044$1978 assign { } { } assign $1\subfragments_new_master_rdata_valid1[0:0] 1'0 sync always sync init update \subfragments_new_master_rdata_valid1 $1\subfragments_new_master_rdata_valid1[0:0] end - attribute \src "ls180.v:1051.5-1051.48" - process $proc$ls180.v:1051$1975 + attribute \src "ls180.v:1045.5-1045.48" + process $proc$ls180.v:1045$1979 assign { } { } assign $1\subfragments_new_master_rdata_valid2[0:0] 1'0 sync always sync init update \subfragments_new_master_rdata_valid2 $1\subfragments_new_master_rdata_valid2[0:0] end - attribute \src "ls180.v:1052.5-1052.48" - process $proc$ls180.v:1052$1976 + attribute \src "ls180.v:1046.5-1046.48" + process $proc$ls180.v:1046$1980 assign { } { } assign $1\subfragments_new_master_rdata_valid3[0:0] 1'0 sync always sync init update \subfragments_new_master_rdata_valid3 $1\subfragments_new_master_rdata_valid3[0:0] end - attribute \src "ls180.v:1053.5-1053.30" - process $proc$ls180.v:1053$1977 + attribute \src "ls180.v:1047.5-1047.30" + process $proc$ls180.v:1047$1981 assign { } { } assign $1\subfragments_state[0:0] 1'0 sync always sync init update \subfragments_state $1\subfragments_state[0:0] end - attribute \src "ls180.v:1054.5-1054.35" - process $proc$ls180.v:1054$1978 + attribute \src "ls180.v:1048.5-1048.35" + process $proc$ls180.v:1048$1982 assign { } { } assign $1\subfragments_next_state[0:0] 1'0 sync always sync init update \subfragments_next_state $1\subfragments_next_state[0:0] end - attribute \src "ls180.v:1055.5-1055.53" - process $proc$ls180.v:1055$1979 + attribute \src "ls180.v:1049.5-1049.53" + process $proc$ls180.v:1049$1983 assign { } { } assign $1\converter_counter_subfragments_next_value[0:0] 1'0 sync always sync init update \converter_counter_subfragments_next_value $1\converter_counter_subfragments_next_value[0:0] end - attribute \src "ls180.v:1056.5-1056.56" - process $proc$ls180.v:1056$1980 + attribute \src "ls180.v:1050.5-1050.56" + process $proc$ls180.v:1050$1984 assign { } { } assign $1\converter_counter_subfragments_next_value_ce[0:0] 1'0 sync always sync init update \converter_counter_subfragments_next_value_ce $1\converter_counter_subfragments_next_value_ce[0:0] end - attribute \src "ls180.v:1057.12-1057.47" - process $proc$ls180.v:1057$1981 + attribute \src "ls180.v:1051.12-1051.47" + process $proc$ls180.v:1051$1985 assign { } { } assign $1\libresocsim_libresocsim_adr[13:0] 14'00000000000000 sync always sync init update \libresocsim_libresocsim_adr $1\libresocsim_libresocsim_adr[13:0] end - attribute \src "ls180.v:1058.5-1058.38" - process $proc$ls180.v:1058$1982 + attribute \src "ls180.v:1052.5-1052.38" + process $proc$ls180.v:1052$1986 assign { } { } assign $1\libresocsim_libresocsim_we[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_we $1\libresocsim_libresocsim_we[0:0] end - attribute \src "ls180.v:1059.11-1059.47" - process $proc$ls180.v:1059$1983 + attribute \src "ls180.v:1053.11-1053.47" + process $proc$ls180.v:1053$1987 assign { } { } assign $1\libresocsim_libresocsim_dat_w[7:0] 8'00000000 sync always sync init update \libresocsim_libresocsim_dat_w $1\libresocsim_libresocsim_dat_w[7:0] end - attribute \src "ls180.v:1063.12-1063.58" - process $proc$ls180.v:1063$1984 + attribute \src "ls180.v:1057.12-1057.58" + process $proc$ls180.v:1057$1988 assign { } { } assign $1\libresocsim_libresocsim_wishbone_dat_r[31:0] 0 sync always sync init update \libresocsim_libresocsim_wishbone_dat_r $1\libresocsim_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:1067.5-1067.48" - process $proc$ls180.v:1067$1985 + attribute \src "ls180.v:1061.5-1061.48" + process $proc$ls180.v:1061$1989 assign { } { } assign $1\libresocsim_libresocsim_wishbone_ack[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_wishbone_ack $1\libresocsim_libresocsim_wishbone_ack[0:0] end - attribute \src "ls180.v:1071.5-1071.48" - process $proc$ls180.v:1071$1986 + attribute \src "ls180.v:1065.5-1065.48" + process $proc$ls180.v:1065$1990 assign { } { } assign $0\libresocsim_libresocsim_wishbone_err[0:0] 1'0 sync always update \libresocsim_libresocsim_wishbone_err $0\libresocsim_libresocsim_wishbone_err[0:0] sync init end - attribute \src "ls180.v:1074.12-1074.44" - process $proc$ls180.v:1074$1987 + attribute \src "ls180.v:1068.12-1068.44" + process $proc$ls180.v:1068$1991 assign { } { } assign $1\libresocsim_shared_dat_r[31:0] 0 sync always sync init update \libresocsim_shared_dat_r $1\libresocsim_shared_dat_r[31:0] end - attribute \src "ls180.v:1078.5-1078.34" - process $proc$ls180.v:1078$1988 + attribute \src "ls180.v:1072.5-1072.34" + process $proc$ls180.v:1072$1992 assign { } { } assign $1\libresocsim_shared_ack[0:0] 1'0 sync always sync init update \libresocsim_shared_ack $1\libresocsim_shared_ack[0:0] end - attribute \src "ls180.v:1084.11-1084.35" - process $proc$ls180.v:1084$1989 + attribute \src "ls180.v:1078.11-1078.35" + process $proc$ls180.v:1078$1993 assign { } { } assign $1\libresocsim_grant[1:0] 2'00 sync always sync init update \libresocsim_grant $1\libresocsim_grant[1:0] end - attribute \src "ls180.v:1085.11-1085.39" - process $proc$ls180.v:1085$1990 + attribute \src "ls180.v:1079.11-1079.39" + process $proc$ls180.v:1079$1994 assign { } { } assign $1\libresocsim_slave_sel[5:0] 6'000000 sync always sync init update \libresocsim_slave_sel $1\libresocsim_slave_sel[5:0] end - attribute \src "ls180.v:1086.11-1086.41" - process $proc$ls180.v:1086$1991 + attribute \src "ls180.v:1080.11-1080.41" + process $proc$ls180.v:1080$1995 assign { } { } assign $1\libresocsim_slave_sel_r[5:0] 6'000000 sync always sync init update \libresocsim_slave_sel_r $1\libresocsim_slave_sel_r[5:0] end - attribute \src "ls180.v:1087.5-1087.29" - process $proc$ls180.v:1087$1992 + attribute \src "ls180.v:1081.5-1081.29" + process $proc$ls180.v:1081$1996 assign { } { } assign $1\libresocsim_error[0:0] 1'0 sync always sync init update \libresocsim_error $1\libresocsim_error[0:0] end - attribute \src "ls180.v:1090.12-1090.43" - process $proc$ls180.v:1090$1993 + attribute \src "ls180.v:1084.12-1084.43" + process $proc$ls180.v:1084$1997 assign { } { } assign $1\libresocsim_count[19:0] 20'11110100001001000000 sync always sync init update \libresocsim_count $1\libresocsim_count[19:0] end - attribute \src "ls180.v:1094.11-1094.55" - process $proc$ls180.v:1094$1994 + attribute \src "ls180.v:1088.11-1088.55" + process $proc$ls180.v:1088$1998 assign { } { } assign $1\libresocsim_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface0_bank_bus_dat_r $1\libresocsim_interface0_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:1135.11-1135.55" - process $proc$ls180.v:1135$1995 + attribute \src "ls180.v:1129.11-1129.55" + process $proc$ls180.v:1129$1999 assign { } { } assign $1\libresocsim_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface1_bank_bus_dat_r $1\libresocsim_interface1_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:115.5-115.58" - process $proc$ls180.v:115$1559 - assign { } { } - assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 - sync always - sync init - update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] - end - attribute \src "ls180.v:1152.11-1152.55" - process $proc$ls180.v:1152$1996 + attribute \src "ls180.v:1146.11-1146.55" + process $proc$ls180.v:1146$2000 assign { } { } assign $1\libresocsim_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -261397,689 +261198,721 @@ module \ls180 update \libresocsim_interface2_bank_bus_dat_r $1\libresocsim_interface2_bank_bus_dat_r[7:0] end attribute \src "ls180.v:116.5-116.58" - process $proc$ls180.v:116$1560 + process $proc$ls180.v:116$1563 assign { } { } - assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 sync always - update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] sync init + update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] end - attribute \src "ls180.v:1169.11-1169.55" - process $proc$ls180.v:1169$1997 + attribute \src "ls180.v:1163.11-1163.55" + process $proc$ls180.v:1163$2001 assign { } { } assign $1\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface3_bank_bus_dat_r $1\libresocsim_interface3_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:1182.11-1182.55" - process $proc$ls180.v:1182$1998 + attribute \src "ls180.v:117.5-117.58" + process $proc$ls180.v:117$1564 + assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0 + sync always + update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] + sync init + end + attribute \src "ls180.v:1176.11-1176.55" + process $proc$ls180.v:1176$2002 assign { } { } assign $1\libresocsim_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface4_bank_bus_dat_r $1\libresocsim_interface4_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:120.12-120.66" - process $proc$ls180.v:120$1561 + attribute \src "ls180.v:118.12-118.66" + process $proc$ls180.v:118$1565 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] 13'0000000000000 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_a $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] end - attribute \src "ls180.v:122.12-122.69" - process $proc$ls180.v:122$1562 + attribute \src "ls180.v:120.12-120.69" + process $proc$ls180.v:120$1566 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] 16'0000000000000000 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] end - attribute \src "ls180.v:1223.11-1223.55" - process $proc$ls180.v:1223$1999 + attribute \src "ls180.v:121.5-121.62" + process $proc$ls180.v:121$1567 assign { } { } - assign $1\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] 1'0 sync always sync init - update \libresocsim_interface5_bank_bus_dat_r $1\libresocsim_interface5_bank_bus_dat_r[7:0] + update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] end - attribute \src "ls180.v:123.5-123.62" - process $proc$ls180.v:123$1563 + attribute \src "ls180.v:1217.11-1217.55" + process $proc$ls180.v:1217$2003 assign { } { } - assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] 1'0 + assign $1\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] + update \libresocsim_interface5_bank_bus_dat_r $1\libresocsim_interface5_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:124.5-124.61" - process $proc$ls180.v:124$1564 + attribute \src "ls180.v:122.5-122.61" + process $proc$ls180.v:122$1568 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_we_n $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] end - attribute \src "ls180.v:125.5-125.62" - process $proc$ls180.v:125$1565 + attribute \src "ls180.v:123.5-123.62" + process $proc$ls180.v:123$1569 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_ras_n $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] end - attribute \src "ls180.v:126.5-126.62" - process $proc$ls180.v:126$1566 + attribute \src "ls180.v:124.5-124.62" + process $proc$ls180.v:124$1570 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_cas_n $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] end - attribute \src "ls180.v:127.5-127.61" - process $proc$ls180.v:127$1567 + attribute \src "ls180.v:125.5-125.61" + process $proc$ls180.v:125$1571 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_cs_n $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] end - attribute \src "ls180.v:128.5-128.60" - process $proc$ls180.v:128$1568 + attribute \src "ls180.v:126.5-126.60" + process $proc$ls180.v:126$1572 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_cke $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] end - attribute \src "ls180.v:1288.11-1288.55" - process $proc$ls180.v:1288$2000 - assign { } { } - assign $1\libresocsim_interface6_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \libresocsim_interface6_bank_bus_dat_r $1\libresocsim_interface6_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:129.11-129.65" - process $proc$ls180.v:129$1569 + attribute \src "ls180.v:127.11-127.65" + process $proc$ls180.v:127$1573 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] 2'00 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_ba $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] end - attribute \src "ls180.v:130.11-130.65" - process $proc$ls180.v:130$1570 + attribute \src "ls180.v:128.11-128.65" + process $proc$ls180.v:128$1574 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] 2'00 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_dm $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] end - attribute \src "ls180.v:131.5-131.62" - process $proc$ls180.v:131$1571 + attribute \src "ls180.v:1282.11-1282.55" + process $proc$ls180.v:1282$2004 + assign { } { } + assign $1\libresocsim_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \libresocsim_interface6_bank_bus_dat_r $1\libresocsim_interface6_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:129.5-129.62" + process $proc$ls180.v:129$1575 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_clock $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] end - attribute \src "ls180.v:1313.11-1313.55" - process $proc$ls180.v:1313$2001 + attribute \src "ls180.v:1307.11-1307.55" + process $proc$ls180.v:1307$2005 assign { } { } assign $1\libresocsim_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface7_bank_bus_dat_r $1\libresocsim_interface7_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:1335.11-1335.35" - process $proc$ls180.v:1335$2002 + attribute \src "ls180.v:131.12-131.65" + process $proc$ls180.v:131$1576 + assign { } { } + assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] + end + attribute \src "ls180.v:132.12-132.66" + process $proc$ls180.v:132$1577 + assign { } { } + assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] + end + attribute \src "ls180.v:1329.11-1329.35" + process $proc$ls180.v:1329$2006 assign { } { } assign $1\libresocsim_state[1:0] 2'00 sync always sync init update \libresocsim_state $1\libresocsim_state[1:0] end - attribute \src "ls180.v:1336.11-1336.40" - process $proc$ls180.v:1336$2003 + attribute \src "ls180.v:133.5-133.64" + process $proc$ls180.v:133$1578 + assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0 + sync always + update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] + sync init + end + attribute \src "ls180.v:1330.11-1330.40" + process $proc$ls180.v:1330$2007 assign { } { } assign $1\libresocsim_next_state[1:0] 2'00 sync always sync init update \libresocsim_next_state $1\libresocsim_next_state[1:0] end - attribute \src "ls180.v:1337.11-1337.71" - process $proc$ls180.v:1337$2004 + attribute \src "ls180.v:1331.11-1331.71" + process $proc$ls180.v:1331$2008 assign { } { } assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] 8'00000000 sync always sync init update \libresocsim_libresocsim_dat_w_libresocsim_next_value0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] end - attribute \src "ls180.v:1338.5-1338.68" - process $proc$ls180.v:1338$2005 + attribute \src "ls180.v:1332.5-1332.68" + process $proc$ls180.v:1332$2009 assign { } { } assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] end - attribute \src "ls180.v:1339.12-1339.71" - process $proc$ls180.v:1339$2006 + attribute \src "ls180.v:1333.12-1333.71" + process $proc$ls180.v:1333$2010 assign { } { } assign $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 sync always sync init update \libresocsim_libresocsim_adr_libresocsim_next_value1 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] end - attribute \src "ls180.v:1340.5-1340.66" - process $proc$ls180.v:1340$2007 + attribute \src "ls180.v:1334.5-1334.66" + process $proc$ls180.v:1334$2011 assign { } { } assign $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] end - attribute \src "ls180.v:1341.5-1341.62" - process $proc$ls180.v:1341$2008 + attribute \src "ls180.v:1335.5-1335.62" + process $proc$ls180.v:1335$2012 assign { } { } assign $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_we_libresocsim_next_value2 $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] end - attribute \src "ls180.v:1342.5-1342.65" - process $proc$ls180.v:1342$2009 + attribute \src "ls180.v:1336.5-1336.65" + process $proc$ls180.v:1336$2013 assign { } { } assign $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] end - attribute \src "ls180.v:1343.5-1343.28" - process $proc$ls180.v:1343$2010 + attribute \src "ls180.v:1337.5-1337.28" + process $proc$ls180.v:1337$2014 assign { } { } assign $1\rhs_array_muxed0[0:0] 1'0 sync always sync init update \rhs_array_muxed0 $1\rhs_array_muxed0[0:0] end - attribute \src "ls180.v:1344.12-1344.36" - process $proc$ls180.v:1344$2011 + attribute \src "ls180.v:1338.12-1338.36" + process $proc$ls180.v:1338$2015 assign { } { } assign $1\rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \rhs_array_muxed1 $1\rhs_array_muxed1[12:0] end - attribute \src "ls180.v:1345.11-1345.34" - process $proc$ls180.v:1345$2012 + attribute \src "ls180.v:1339.11-1339.34" + process $proc$ls180.v:1339$2016 assign { } { } assign $1\rhs_array_muxed2[1:0] 2'00 sync always sync init update \rhs_array_muxed2 $1\rhs_array_muxed2[1:0] end - attribute \src "ls180.v:1346.5-1346.28" - process $proc$ls180.v:1346$2013 + attribute \src "ls180.v:134.5-134.65" + process $proc$ls180.v:134$1579 + assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0 + sync always + update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] + sync init + end + attribute \src "ls180.v:1340.5-1340.28" + process $proc$ls180.v:1340$2017 assign { } { } assign $1\rhs_array_muxed3[0:0] 1'0 sync always sync init update \rhs_array_muxed3 $1\rhs_array_muxed3[0:0] end - attribute \src "ls180.v:1347.5-1347.28" - process $proc$ls180.v:1347$2014 + attribute \src "ls180.v:1341.5-1341.28" + process $proc$ls180.v:1341$2018 assign { } { } assign $1\rhs_array_muxed4[0:0] 1'0 sync always sync init update \rhs_array_muxed4 $1\rhs_array_muxed4[0:0] end - attribute \src "ls180.v:1348.5-1348.28" - process $proc$ls180.v:1348$2015 + attribute \src "ls180.v:1342.5-1342.28" + process $proc$ls180.v:1342$2019 assign { } { } assign $1\rhs_array_muxed5[0:0] 1'0 sync always sync init update \rhs_array_muxed5 $1\rhs_array_muxed5[0:0] end - attribute \src "ls180.v:1349.5-1349.26" - process $proc$ls180.v:1349$2016 + attribute \src "ls180.v:1343.5-1343.26" + process $proc$ls180.v:1343$2020 assign { } { } assign $1\t_array_muxed0[0:0] 1'0 sync always sync init update \t_array_muxed0 $1\t_array_muxed0[0:0] end - attribute \src "ls180.v:1350.5-1350.26" - process $proc$ls180.v:1350$2017 + attribute \src "ls180.v:1344.5-1344.26" + process $proc$ls180.v:1344$2021 assign { } { } assign $1\t_array_muxed1[0:0] 1'0 sync always sync init update \t_array_muxed1 $1\t_array_muxed1[0:0] end - attribute \src "ls180.v:1351.5-1351.26" - process $proc$ls180.v:1351$2018 + attribute \src "ls180.v:1345.5-1345.26" + process $proc$ls180.v:1345$2022 assign { } { } assign $1\t_array_muxed2[0:0] 1'0 sync always sync init update \t_array_muxed2 $1\t_array_muxed2[0:0] end - attribute \src "ls180.v:1352.5-1352.28" - process $proc$ls180.v:1352$2019 + attribute \src "ls180.v:1346.5-1346.28" + process $proc$ls180.v:1346$2023 assign { } { } assign $1\rhs_array_muxed6[0:0] 1'0 sync always sync init update \rhs_array_muxed6 $1\rhs_array_muxed6[0:0] end - attribute \src "ls180.v:1353.12-1353.36" - process $proc$ls180.v:1353$2020 + attribute \src "ls180.v:1347.12-1347.36" + process $proc$ls180.v:1347$2024 assign { } { } assign $1\rhs_array_muxed7[12:0] 13'0000000000000 sync always sync init update \rhs_array_muxed7 $1\rhs_array_muxed7[12:0] end - attribute \src "ls180.v:1354.11-1354.34" - process $proc$ls180.v:1354$2021 + attribute \src "ls180.v:1348.11-1348.34" + process $proc$ls180.v:1348$2025 assign { } { } assign $1\rhs_array_muxed8[1:0] 2'00 sync always sync init update \rhs_array_muxed8 $1\rhs_array_muxed8[1:0] end - attribute \src "ls180.v:1355.5-1355.28" - process $proc$ls180.v:1355$2022 + attribute \src "ls180.v:1349.5-1349.28" + process $proc$ls180.v:1349$2026 assign { } { } assign $1\rhs_array_muxed9[0:0] 1'0 sync always sync init update \rhs_array_muxed9 $1\rhs_array_muxed9[0:0] end - attribute \src "ls180.v:1356.5-1356.29" - process $proc$ls180.v:1356$2023 + attribute \src "ls180.v:135.5-135.65" + process $proc$ls180.v:135$1580 + assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0 + sync always + update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] + sync init + end + attribute \src "ls180.v:1350.5-1350.29" + process $proc$ls180.v:1350$2027 assign { } { } assign $1\rhs_array_muxed10[0:0] 1'0 sync always sync init update \rhs_array_muxed10 $1\rhs_array_muxed10[0:0] end - attribute \src "ls180.v:1357.5-1357.29" - process $proc$ls180.v:1357$2024 + attribute \src "ls180.v:1351.5-1351.29" + process $proc$ls180.v:1351$2028 assign { } { } assign $1\rhs_array_muxed11[0:0] 1'0 sync always sync init update \rhs_array_muxed11 $1\rhs_array_muxed11[0:0] end - attribute \src "ls180.v:1358.5-1358.26" - process $proc$ls180.v:1358$2025 + attribute \src "ls180.v:1352.5-1352.26" + process $proc$ls180.v:1352$2029 assign { } { } assign $1\t_array_muxed3[0:0] 1'0 sync always sync init update \t_array_muxed3 $1\t_array_muxed3[0:0] end - attribute \src "ls180.v:1359.5-1359.26" - process $proc$ls180.v:1359$2026 + attribute \src "ls180.v:1353.5-1353.26" + process $proc$ls180.v:1353$2030 assign { } { } assign $1\t_array_muxed4[0:0] 1'0 sync always sync init update \t_array_muxed4 $1\t_array_muxed4[0:0] end - attribute \src "ls180.v:136.5-136.64" - process $proc$ls180.v:136$1572 - assign { } { } - assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0 - sync always - update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] - sync init - end - attribute \src "ls180.v:1360.5-1360.26" - process $proc$ls180.v:1360$2027 + attribute \src "ls180.v:1354.5-1354.26" + process $proc$ls180.v:1354$2031 assign { } { } assign $1\t_array_muxed5[0:0] 1'0 sync always sync init update \t_array_muxed5 $1\t_array_muxed5[0:0] end - attribute \src "ls180.v:1361.12-1361.37" - process $proc$ls180.v:1361$2028 + attribute \src "ls180.v:1355.12-1355.37" + process $proc$ls180.v:1355$2032 assign { } { } assign $1\rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always sync init update \rhs_array_muxed12 $1\rhs_array_muxed12[21:0] end - attribute \src "ls180.v:1362.5-1362.29" - process $proc$ls180.v:1362$2029 + attribute \src "ls180.v:1356.5-1356.29" + process $proc$ls180.v:1356$2033 assign { } { } assign $1\rhs_array_muxed13[0:0] 1'0 sync always sync init update \rhs_array_muxed13 $1\rhs_array_muxed13[0:0] end - attribute \src "ls180.v:1363.5-1363.29" - process $proc$ls180.v:1363$2030 + attribute \src "ls180.v:1357.5-1357.29" + process $proc$ls180.v:1357$2034 assign { } { } assign $1\rhs_array_muxed14[0:0] 1'0 sync always sync init update \rhs_array_muxed14 $1\rhs_array_muxed14[0:0] end - attribute \src "ls180.v:1364.12-1364.37" - process $proc$ls180.v:1364$2031 + attribute \src "ls180.v:1358.12-1358.37" + process $proc$ls180.v:1358$2035 assign { } { } assign $1\rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always sync init update \rhs_array_muxed15 $1\rhs_array_muxed15[21:0] end - attribute \src "ls180.v:1365.5-1365.29" - process $proc$ls180.v:1365$2032 + attribute \src "ls180.v:1359.5-1359.29" + process $proc$ls180.v:1359$2036 assign { } { } assign $1\rhs_array_muxed16[0:0] 1'0 sync always sync init update \rhs_array_muxed16 $1\rhs_array_muxed16[0:0] end - attribute \src "ls180.v:1366.5-1366.29" - process $proc$ls180.v:1366$2033 + attribute \src "ls180.v:1360.5-1360.29" + process $proc$ls180.v:1360$2037 assign { } { } assign $1\rhs_array_muxed17[0:0] 1'0 sync always sync init update \rhs_array_muxed17 $1\rhs_array_muxed17[0:0] end - attribute \src "ls180.v:1367.12-1367.37" - process $proc$ls180.v:1367$2034 + attribute \src "ls180.v:1361.12-1361.37" + process $proc$ls180.v:1361$2038 assign { } { } assign $1\rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always sync init update \rhs_array_muxed18 $1\rhs_array_muxed18[21:0] end - attribute \src "ls180.v:1368.5-1368.29" - process $proc$ls180.v:1368$2035 + attribute \src "ls180.v:1362.5-1362.29" + process $proc$ls180.v:1362$2039 assign { } { } assign $1\rhs_array_muxed19[0:0] 1'0 sync always sync init update \rhs_array_muxed19 $1\rhs_array_muxed19[0:0] end - attribute \src "ls180.v:1369.5-1369.29" - process $proc$ls180.v:1369$2036 + attribute \src "ls180.v:1363.5-1363.29" + process $proc$ls180.v:1363$2040 assign { } { } assign $1\rhs_array_muxed20[0:0] 1'0 sync always sync init update \rhs_array_muxed20 $1\rhs_array_muxed20[0:0] end - attribute \src "ls180.v:137.5-137.65" - process $proc$ls180.v:137$1573 - assign { } { } - assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0 - sync always - update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] - sync init - end - attribute \src "ls180.v:1370.12-1370.37" - process $proc$ls180.v:1370$2037 + attribute \src "ls180.v:1364.12-1364.37" + process $proc$ls180.v:1364$2041 assign { } { } assign $1\rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always sync init update \rhs_array_muxed21 $1\rhs_array_muxed21[21:0] end - attribute \src "ls180.v:1371.5-1371.29" - process $proc$ls180.v:1371$2038 + attribute \src "ls180.v:1365.5-1365.29" + process $proc$ls180.v:1365$2042 assign { } { } assign $1\rhs_array_muxed22[0:0] 1'0 sync always sync init update \rhs_array_muxed22 $1\rhs_array_muxed22[0:0] end - attribute \src "ls180.v:1372.5-1372.29" - process $proc$ls180.v:1372$2039 + attribute \src "ls180.v:1366.5-1366.29" + process $proc$ls180.v:1366$2043 assign { } { } assign $1\rhs_array_muxed23[0:0] 1'0 sync always sync init update \rhs_array_muxed23 $1\rhs_array_muxed23[0:0] end - attribute \src "ls180.v:1373.12-1373.37" - process $proc$ls180.v:1373$2040 + attribute \src "ls180.v:1367.12-1367.37" + process $proc$ls180.v:1367$2044 assign { } { } assign $1\rhs_array_muxed24[29:0] 30'000000000000000000000000000000 sync always sync init update \rhs_array_muxed24 $1\rhs_array_muxed24[29:0] end - attribute \src "ls180.v:1374.12-1374.37" - process $proc$ls180.v:1374$2041 + attribute \src "ls180.v:1368.12-1368.37" + process $proc$ls180.v:1368$2045 assign { } { } assign $1\rhs_array_muxed25[31:0] 0 sync always sync init update \rhs_array_muxed25 $1\rhs_array_muxed25[31:0] end - attribute \src "ls180.v:1375.11-1375.35" - process $proc$ls180.v:1375$2042 + attribute \src "ls180.v:1369.11-1369.35" + process $proc$ls180.v:1369$2046 assign { } { } assign $1\rhs_array_muxed26[3:0] 4'0000 sync always sync init update \rhs_array_muxed26 $1\rhs_array_muxed26[3:0] end - attribute \src "ls180.v:1376.5-1376.29" - process $proc$ls180.v:1376$2043 + attribute \src "ls180.v:137.12-137.66" + process $proc$ls180.v:137$1581 + assign { } { } + assign $1\libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \libresocsim_interface0_converted_interface_adr $1\libresocsim_interface0_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1370.5-1370.29" + process $proc$ls180.v:1370$2047 assign { } { } assign $1\rhs_array_muxed27[0:0] 1'0 sync always sync init update \rhs_array_muxed27 $1\rhs_array_muxed27[0:0] end - attribute \src "ls180.v:1377.5-1377.29" - process $proc$ls180.v:1377$2044 + attribute \src "ls180.v:1371.5-1371.29" + process $proc$ls180.v:1371$2048 assign { } { } assign $1\rhs_array_muxed28[0:0] 1'0 sync always sync init update \rhs_array_muxed28 $1\rhs_array_muxed28[0:0] end - attribute \src "ls180.v:1378.5-1378.29" - process $proc$ls180.v:1378$2045 + attribute \src "ls180.v:1372.5-1372.29" + process $proc$ls180.v:1372$2049 assign { } { } assign $1\rhs_array_muxed29[0:0] 1'0 sync always sync init update \rhs_array_muxed29 $1\rhs_array_muxed29[0:0] end - attribute \src "ls180.v:1379.11-1379.35" - process $proc$ls180.v:1379$2046 + attribute \src "ls180.v:1373.11-1373.35" + process $proc$ls180.v:1373$2050 assign { } { } assign $1\rhs_array_muxed30[2:0] 3'000 sync always sync init update \rhs_array_muxed30 $1\rhs_array_muxed30[2:0] end - attribute \src "ls180.v:138.5-138.65" - process $proc$ls180.v:138$1574 - assign { } { } - assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0 - sync always - update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] - sync init - end - attribute \src "ls180.v:1380.11-1380.35" - process $proc$ls180.v:1380$2047 + attribute \src "ls180.v:1374.11-1374.35" + process $proc$ls180.v:1374$2051 assign { } { } assign $1\rhs_array_muxed31[1:0] 2'00 sync always sync init update \rhs_array_muxed31 $1\rhs_array_muxed31[1:0] end - attribute \src "ls180.v:1381.11-1381.30" - process $proc$ls180.v:1381$2048 + attribute \src "ls180.v:1375.11-1375.30" + process $proc$ls180.v:1375$2052 assign { } { } assign $1\array_muxed0[1:0] 2'00 sync always sync init update \array_muxed0 $1\array_muxed0[1:0] end - attribute \src "ls180.v:1382.12-1382.32" - process $proc$ls180.v:1382$2049 + attribute \src "ls180.v:1376.12-1376.32" + process $proc$ls180.v:1376$2053 assign { } { } assign $1\array_muxed1[12:0] 13'0000000000000 sync always sync init update \array_muxed1 $1\array_muxed1[12:0] end - attribute \src "ls180.v:1383.5-1383.24" - process $proc$ls180.v:1383$2050 + attribute \src "ls180.v:1377.5-1377.24" + process $proc$ls180.v:1377$2054 assign { } { } assign $1\array_muxed2[0:0] 1'0 sync always sync init update \array_muxed2 $1\array_muxed2[0:0] end - attribute \src "ls180.v:1384.5-1384.24" - process $proc$ls180.v:1384$2051 + attribute \src "ls180.v:1378.5-1378.24" + process $proc$ls180.v:1378$2055 assign { } { } assign $1\array_muxed3[0:0] 1'0 sync always sync init update \array_muxed3 $1\array_muxed3[0:0] end - attribute \src "ls180.v:1385.5-1385.24" - process $proc$ls180.v:1385$2052 + attribute \src "ls180.v:1379.5-1379.24" + process $proc$ls180.v:1379$2056 assign { } { } assign $1\array_muxed4[0:0] 1'0 sync always sync init update \array_muxed4 $1\array_muxed4[0:0] end - attribute \src "ls180.v:1386.5-1386.24" - process $proc$ls180.v:1386$2053 + attribute \src "ls180.v:138.12-138.68" + process $proc$ls180.v:138$1582 assign { } { } - assign $1\array_muxed5[0:0] 1'0 + assign $1\libresocsim_interface0_converted_interface_dat_w[31:0] 0 sync always sync init - update \array_muxed5 $1\array_muxed5[0:0] + update \libresocsim_interface0_converted_interface_dat_w $1\libresocsim_interface0_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:1387.5-1387.24" - process $proc$ls180.v:1387$2054 + attribute \src "ls180.v:1380.5-1380.24" + process $proc$ls180.v:1380$2057 assign { } { } - assign $1\array_muxed6[0:0] 1'0 + assign $1\array_muxed5[0:0] 1'0 sync always sync init - update \array_muxed6 $1\array_muxed6[0:0] + update \array_muxed5 $1\array_muxed5[0:0] end - attribute \src "ls180.v:141.12-141.65" - process $proc$ls180.v:141$1575 + attribute \src "ls180.v:1381.5-1381.24" + process $proc$ls180.v:1381$2058 assign { } { } - assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000 + assign $1\array_muxed6[0:0] 1'0 sync always sync init - update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] + update \array_muxed6 $1\array_muxed6[0:0] end - attribute \src "ls180.v:142.12-142.66" - process $proc$ls180.v:142$1576 + attribute \src "ls180.v:140.11-140.64" + process $proc$ls180.v:140$1583 assign { } { } - assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000 + assign $1\libresocsim_interface0_converted_interface_sel[3:0] 4'0000 sync always sync init - update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] + update \libresocsim_interface0_converted_interface_sel $1\libresocsim_interface0_converted_interface_sel[3:0] end - attribute \src "ls180.v:143.12-143.66" - process $proc$ls180.v:143$1577 + attribute \src "ls180.v:141.5-141.58" + process $proc$ls180.v:141$1584 assign { } { } - assign $1\libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $1\libresocsim_interface0_converted_interface_cyc[0:0] 1'0 sync always sync init - update \libresocsim_interface0_converted_interface_adr $1\libresocsim_interface0_converted_interface_adr[29:0] + update \libresocsim_interface0_converted_interface_cyc $1\libresocsim_interface0_converted_interface_cyc[0:0] end - attribute \src "ls180.v:144.12-144.68" - process $proc$ls180.v:144$1578 + attribute \src "ls180.v:142.5-142.58" + process $proc$ls180.v:142$1585 assign { } { } - assign $1\libresocsim_interface0_converted_interface_dat_w[31:0] 0 + assign $1\libresocsim_interface0_converted_interface_stb[0:0] 1'0 sync always sync init - update \libresocsim_interface0_converted_interface_dat_w $1\libresocsim_interface0_converted_interface_dat_w[31:0] + update \libresocsim_interface0_converted_interface_stb $1\libresocsim_interface0_converted_interface_stb[0:0] end - attribute \src "ls180.v:1444.32-1444.44" - process $proc$ls180.v:1444$2055 + attribute \src "ls180.v:1438.32-1438.44" + process $proc$ls180.v:1438$2059 assign { } { } assign $1\regs0[0:0] 1'0 sync always sync init update \regs0 $1\regs0[0:0] end - attribute \src "ls180.v:1445.32-1445.44" - process $proc$ls180.v:1445$2056 + attribute \src "ls180.v:1439.32-1439.44" + process $proc$ls180.v:1439$2060 assign { } { } assign $1\regs1[0:0] 1'0 sync always sync init update \regs1 $1\regs1[0:0] end - attribute \src "ls180.v:146.11-146.64" - process $proc$ls180.v:146$1579 + attribute \src "ls180.v:144.5-144.57" + process $proc$ls180.v:144$1586 assign { } { } - assign $1\libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + assign $1\libresocsim_interface0_converted_interface_we[0:0] 1'0 sync always sync init - update \libresocsim_interface0_converted_interface_sel $1\libresocsim_interface0_converted_interface_sel[3:0] + update \libresocsim_interface0_converted_interface_we $1\libresocsim_interface0_converted_interface_we[0:0] end - attribute \src "ls180.v:147.5-147.58" - process $proc$ls180.v:147$1580 + attribute \src "ls180.v:145.11-145.64" + process $proc$ls180.v:145$1587 assign { } { } - assign $1\libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + assign $0\libresocsim_interface0_converted_interface_cti[2:0] 3'000 sync always + update \libresocsim_interface0_converted_interface_cti $0\libresocsim_interface0_converted_interface_cti[2:0] sync init - update \libresocsim_interface0_converted_interface_cyc $1\libresocsim_interface0_converted_interface_cyc[0:0] end - attribute \src "ls180.v:148.5-148.58" - process $proc$ls180.v:148$1581 + attribute \src "ls180.v:146.11-146.64" + process $proc$ls180.v:146$1588 assign { } { } - assign $1\libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign $0\libresocsim_interface0_converted_interface_bte[1:0] 2'00 sync always + update \libresocsim_interface0_converted_interface_bte $0\libresocsim_interface0_converted_interface_bte[1:0] sync init - update \libresocsim_interface0_converted_interface_stb $1\libresocsim_interface0_converted_interface_stb[0:0] end - attribute \src "ls180.v:1499.1-1504.4" - process $proc$ls180.v:1499$15 + attribute \src "ls180.v:148.5-148.39" + process $proc$ls180.v:148$1589 assign { } { } - assign { } { } - assign $0\eint_tmp[2:0] [0] \libresocsim_libresoc_constraintmanager_eint_0 - assign $0\eint_tmp[2:0] [1] \libresocsim_libresoc_constraintmanager_eint_1 - assign $0\eint_tmp[2:0] [2] \libresocsim_libresoc_constraintmanager_eint_2 + assign $1\libresocsim_converter0_skip[0:0] 1'0 sync always - update \eint_tmp $0\eint_tmp[2:0] + sync init + update \libresocsim_converter0_skip $1\libresocsim_converter0_skip[0:0] end - attribute \src "ls180.v:150.5-150.57" - process $proc$ls180.v:150$1582 + attribute \src "ls180.v:149.5-149.42" + process $proc$ls180.v:149$1590 assign { } { } - assign $1\libresocsim_interface0_converted_interface_we[0:0] 1'0 + assign $1\libresocsim_converter0_counter[0:0] 1'0 sync always sync init - update \libresocsim_interface0_converted_interface_we $1\libresocsim_interface0_converted_interface_we[0:0] + update \libresocsim_converter0_counter $1\libresocsim_converter0_counter[0:0] end - attribute \src "ls180.v:151.11-151.64" - process $proc$ls180.v:151$1583 + attribute \src "ls180.v:1490.1-1495.4" + process $proc$ls180.v:1490$15 assign { } { } - assign $0\libresocsim_interface0_converted_interface_cti[2:0] 3'000 + assign { } { } + assign $0\eint_tmp[2:0] [0] \libresocsim_libresoc_constraintmanager_eint_0 + assign $0\eint_tmp[2:0] [1] \libresocsim_libresoc_constraintmanager_eint_1 + assign $0\eint_tmp[2:0] [2] \libresocsim_libresoc_constraintmanager_eint_2 sync always - update \libresocsim_interface0_converted_interface_cti $0\libresocsim_interface0_converted_interface_cti[2:0] - sync init + update \eint_tmp $0\eint_tmp[2:0] end - attribute \src "ls180.v:1511.1-1518.4" - process $proc$ls180.v:1511$16 + attribute \src "ls180.v:1502.1-1509.4" + process $proc$ls180.v:1502$16 assign { } { } assign $0\libresocsim_libresoc_interrupt[15:0] [12:2] 11'00000000000 assign $0\libresocsim_libresoc_interrupt[15:0] [13] \eint_tmp [0] @@ -262090,19 +261923,19 @@ module \ls180 sync always update \libresocsim_libresoc_interrupt $0\libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:152.11-152.64" - process $proc$ls180.v:152$1584 + attribute \src "ls180.v:151.12-151.48" + process $proc$ls180.v:151$1591 assign { } { } - assign $0\libresocsim_interface0_converted_interface_bte[1:0] 2'00 + assign $1\libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \libresocsim_interface0_converted_interface_bte $0\libresocsim_interface0_converted_interface_bte[1:0] sync init + update \libresocsim_converter0_dat_r $1\libresocsim_converter0_dat_r[63:0] end - attribute \src "ls180.v:1520.1-1530.4" - process $proc$ls180.v:1520$18 + attribute \src "ls180.v:1511.1-1521.4" + process $proc$ls180.v:1511$18 assign { } { } assign $0\libresocsim_interface0_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:1522.2-1529.9" + attribute \src "ls180.v:1513.2-1520.9" switch \libresocsim_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -262115,8 +261948,16 @@ module \ls180 sync always update \libresocsim_interface0_converted_interface_dat_w $0\libresocsim_interface0_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:1532.1-1578.4" - process $proc$ls180.v:1532$19 + attribute \src "ls180.v:152.12-152.66" + process $proc$ls180.v:152$1592 + assign { } { } + assign $1\libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \libresocsim_interface1_converted_interface_adr $1\libresocsim_interface1_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1523.1-1569.4" + process $proc$ls180.v:1523$19 assign { } { } assign { } { } assign { } { } @@ -262127,23 +261968,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\libresocsim_libresoc_ibus_ack[0:0] 1'0 - assign $0\libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0 + assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0 assign $0\libresocsim_interface0_converted_interface_cyc[0:0] 1'0 assign $0\libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign $0\libresocsim_libresoc_ibus_ack[0:0] 1'0 assign $0\libresocsim_interface0_converted_interface_we[0:0] 1'0 assign $0\libresocsim_converter0_skip[0:0] 1'0 - assign { } { } - assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0 - assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0 assign $0\libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign { } { } + assign $0\libresocsim_interface0_converted_interface_sel[3:0] 4'0000 assign $0\subfragments_converter0_next_state[0:0] \subfragments_converter0_state - attribute \src "ls180.v:1544.2-1577.9" + attribute \src "ls180.v:1535.2-1568.9" switch \subfragments_converter0_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface0_converted_interface_adr[29:0] { \libresocsim_libresoc_ibus_adr \libresocsim_converter0_counter } - attribute \src "ls180.v:1547.4-1554.11" + attribute \src "ls180.v:1538.4-1545.11" switch \libresocsim_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -262153,23 +261994,23 @@ module \ls180 assign $0\libresocsim_interface0_converted_interface_sel[3:0] \libresocsim_libresoc_ibus_sel [7:4] case end - attribute \src "ls180.v:1555.4-1568.7" - switch $and$ls180.v:1555$20_Y - attribute \src "ls180.v:1555.8-1555.71" + attribute \src "ls180.v:1546.4-1559.7" + switch $and$ls180.v:1546$20_Y + attribute \src "ls180.v:1546.8-1546.71" case 1'1 - assign $0\libresocsim_converter0_skip[0:0] $eq$ls180.v:1556$21_Y + assign $0\libresocsim_converter0_skip[0:0] $eq$ls180.v:1547$21_Y assign $0\libresocsim_interface0_converted_interface_we[0:0] \libresocsim_libresoc_ibus_we - assign $0\libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:1558$22_Y - assign $0\libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:1559$23_Y - attribute \src "ls180.v:1560.5-1567.8" - switch $or$ls180.v:1560$24_Y - attribute \src "ls180.v:1560.9-1560.87" + assign $0\libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:1549$22_Y + assign $0\libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:1550$23_Y + attribute \src "ls180.v:1551.5-1558.8" + switch $or$ls180.v:1551$24_Y + attribute \src "ls180.v:1551.9-1551.87" case 1'1 - assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] $add$ls180.v:1561$25_Y + assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] $add$ls180.v:1552$25_Y assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:1563.6-1566.9" - switch $eq$ls180.v:1563$26_Y - attribute \src "ls180.v:1563.10-1563.50" + attribute \src "ls180.v:1554.6-1557.9" + switch $eq$ls180.v:1554$26_Y + attribute \src "ls180.v:1554.10-1554.50" case 1'1 assign $0\libresocsim_libresoc_ibus_ack[0:0] 1'1 assign $0\subfragments_converter0_next_state[0:0] 1'0 @@ -262183,9 +262024,9 @@ module \ls180 case assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0 assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:1573.4-1575.7" - switch $and$ls180.v:1573$27_Y - attribute \src "ls180.v:1573.8-1573.71" + attribute \src "ls180.v:1564.4-1566.7" + switch $and$ls180.v:1564$27_Y + attribute \src "ls180.v:1564.8-1564.71" case 1'1 assign $0\subfragments_converter0_next_state[0:0] 1'1 case @@ -262203,43 +262044,43 @@ module \ls180 update \libresocsim_converter0_counter_subfragments_converter0_next_value $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] update \libresocsim_converter0_counter_subfragments_converter0_next_value_ce $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:154.5-154.39" - process $proc$ls180.v:154$1585 + attribute \src "ls180.v:153.12-153.68" + process $proc$ls180.v:153$1593 assign { } { } - assign $1\libresocsim_converter0_skip[0:0] 1'0 + assign $1\libresocsim_interface1_converted_interface_dat_w[31:0] 0 sync always sync init - update \libresocsim_converter0_skip $1\libresocsim_converter0_skip[0:0] + update \libresocsim_interface1_converted_interface_dat_w $1\libresocsim_interface1_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:155.5-155.42" - process $proc$ls180.v:155$1586 + attribute \src "ls180.v:155.11-155.64" + process $proc$ls180.v:155$1594 assign { } { } - assign $1\libresocsim_converter0_counter[0:0] 1'0 + assign $1\libresocsim_interface1_converted_interface_sel[3:0] 4'0000 sync always sync init - update \libresocsim_converter0_counter $1\libresocsim_converter0_counter[0:0] + update \libresocsim_interface1_converted_interface_sel $1\libresocsim_interface1_converted_interface_sel[3:0] end - attribute \src "ls180.v:157.12-157.48" - process $proc$ls180.v:157$1587 + attribute \src "ls180.v:156.5-156.58" + process $proc$ls180.v:156$1595 assign { } { } - assign $1\libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\libresocsim_interface1_converted_interface_cyc[0:0] 1'0 sync always sync init - update \libresocsim_converter0_dat_r $1\libresocsim_converter0_dat_r[63:0] + update \libresocsim_interface1_converted_interface_cyc $1\libresocsim_interface1_converted_interface_cyc[0:0] end - attribute \src "ls180.v:158.12-158.66" - process $proc$ls180.v:158$1588 + attribute \src "ls180.v:157.5-157.58" + process $proc$ls180.v:157$1596 assign { } { } - assign $1\libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $1\libresocsim_interface1_converted_interface_stb[0:0] 1'0 sync always sync init - update \libresocsim_interface1_converted_interface_adr $1\libresocsim_interface1_converted_interface_adr[29:0] + update \libresocsim_interface1_converted_interface_stb $1\libresocsim_interface1_converted_interface_stb[0:0] end - attribute \src "ls180.v:1580.1-1590.4" - process $proc$ls180.v:1580$29 + attribute \src "ls180.v:1571.1-1581.4" + process $proc$ls180.v:1571$29 assign { } { } assign $0\libresocsim_interface1_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:1582.2-1589.9" + attribute \src "ls180.v:1573.2-1580.9" switch \libresocsim_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -262252,16 +262093,8 @@ module \ls180 sync always update \libresocsim_interface1_converted_interface_dat_w $0\libresocsim_interface1_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:159.12-159.68" - process $proc$ls180.v:159$1589 - assign { } { } - assign $1\libresocsim_interface1_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \libresocsim_interface1_converted_interface_dat_w $1\libresocsim_interface1_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1592.1-1638.4" - process $proc$ls180.v:1592$30 + attribute \src "ls180.v:1583.1-1629.4" + process $proc$ls180.v:1583$30 assign { } { } assign { } { } assign { } { } @@ -262272,23 +262105,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\libresocsim_interface1_converted_interface_stb[0:0] 1'0 - assign $0\libresocsim_interface1_converted_interface_we[0:0] 1'0 assign $0\libresocsim_converter1_skip[0:0] 1'0 assign $0\libresocsim_libresoc_dbus_ack[0:0] 1'0 - assign { } { } assign $0\libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0 - assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0 assign $0\libresocsim_interface1_converted_interface_sel[3:0] 4'0000 assign $0\libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + assign { } { } + assign $0\libresocsim_interface1_converted_interface_stb[0:0] 1'0 + assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0 + assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0 + assign $0\libresocsim_interface1_converted_interface_we[0:0] 1'0 assign $0\subfragments_converter1_next_state[0:0] \subfragments_converter1_state - attribute \src "ls180.v:1604.2-1637.9" + attribute \src "ls180.v:1595.2-1628.9" switch \subfragments_converter1_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface1_converted_interface_adr[29:0] { \libresocsim_libresoc_dbus_adr \libresocsim_converter1_counter } - attribute \src "ls180.v:1607.4-1614.11" + attribute \src "ls180.v:1598.4-1605.11" switch \libresocsim_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -262298,23 +262131,23 @@ module \ls180 assign $0\libresocsim_interface1_converted_interface_sel[3:0] \libresocsim_libresoc_dbus_sel [7:4] case end - attribute \src "ls180.v:1615.4-1628.7" - switch $and$ls180.v:1615$31_Y - attribute \src "ls180.v:1615.8-1615.71" + attribute \src "ls180.v:1606.4-1619.7" + switch $and$ls180.v:1606$31_Y + attribute \src "ls180.v:1606.8-1606.71" case 1'1 - assign $0\libresocsim_converter1_skip[0:0] $eq$ls180.v:1616$32_Y + assign $0\libresocsim_converter1_skip[0:0] $eq$ls180.v:1607$32_Y assign $0\libresocsim_interface1_converted_interface_we[0:0] \libresocsim_libresoc_dbus_we - assign $0\libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:1618$33_Y - assign $0\libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:1619$34_Y - attribute \src "ls180.v:1620.5-1627.8" - switch $or$ls180.v:1620$35_Y - attribute \src "ls180.v:1620.9-1620.87" + assign $0\libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:1609$33_Y + assign $0\libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:1610$34_Y + attribute \src "ls180.v:1611.5-1618.8" + switch $or$ls180.v:1611$35_Y + attribute \src "ls180.v:1611.9-1611.87" case 1'1 - assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] $add$ls180.v:1621$36_Y + assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] $add$ls180.v:1612$36_Y assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:1623.6-1626.9" - switch $eq$ls180.v:1623$37_Y - attribute \src "ls180.v:1623.10-1623.50" + attribute \src "ls180.v:1614.6-1617.9" + switch $eq$ls180.v:1614$37_Y + attribute \src "ls180.v:1614.10-1614.50" case 1'1 assign $0\libresocsim_libresoc_dbus_ack[0:0] 1'1 assign $0\subfragments_converter1_next_state[0:0] 1'0 @@ -262328,9 +262161,9 @@ module \ls180 case assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0 assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:1633.4-1635.7" - switch $and$ls180.v:1633$38_Y - attribute \src "ls180.v:1633.8-1633.71" + attribute \src "ls180.v:1624.4-1626.7" + switch $and$ls180.v:1624$38_Y + attribute \src "ls180.v:1624.8-1624.71" case 1'1 assign $0\subfragments_converter1_next_state[0:0] 1'1 case @@ -262348,35 +262181,43 @@ module \ls180 update \libresocsim_converter1_counter_subfragments_converter1_next_value $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] update \libresocsim_converter1_counter_subfragments_converter1_next_value_ce $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:161.11-161.64" - process $proc$ls180.v:161$1590 + attribute \src "ls180.v:159.5-159.57" + process $proc$ls180.v:159$1597 assign { } { } - assign $1\libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $1\libresocsim_interface1_converted_interface_we[0:0] 1'0 sync always sync init - update \libresocsim_interface1_converted_interface_sel $1\libresocsim_interface1_converted_interface_sel[3:0] + update \libresocsim_interface1_converted_interface_we $1\libresocsim_interface1_converted_interface_we[0:0] end - attribute \src "ls180.v:162.5-162.58" - process $proc$ls180.v:162$1591 + attribute \src "ls180.v:160.11-160.64" + process $proc$ls180.v:160$1598 assign { } { } - assign $1\libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + assign $0\libresocsim_interface1_converted_interface_cti[2:0] 3'000 sync always + update \libresocsim_interface1_converted_interface_cti $0\libresocsim_interface1_converted_interface_cti[2:0] sync init - update \libresocsim_interface1_converted_interface_cyc $1\libresocsim_interface1_converted_interface_cyc[0:0] end - attribute \src "ls180.v:163.5-163.58" - process $proc$ls180.v:163$1592 + attribute \src "ls180.v:161.11-161.64" + process $proc$ls180.v:161$1599 assign { } { } - assign $1\libresocsim_interface1_converted_interface_stb[0:0] 1'0 + assign $0\libresocsim_interface1_converted_interface_bte[1:0] 2'00 sync always + update \libresocsim_interface1_converted_interface_bte $0\libresocsim_interface1_converted_interface_bte[1:0] sync init - update \libresocsim_interface1_converted_interface_stb $1\libresocsim_interface1_converted_interface_stb[0:0] end - attribute \src "ls180.v:1640.1-1650.4" - process $proc$ls180.v:1640$40 + attribute \src "ls180.v:163.5-163.39" + process $proc$ls180.v:163$1600 + assign { } { } + assign $1\libresocsim_converter1_skip[0:0] 1'0 + sync always + sync init + update \libresocsim_converter1_skip $1\libresocsim_converter1_skip[0:0] + end + attribute \src "ls180.v:1631.1-1641.4" + process $proc$ls180.v:1631$40 assign { } { } assign $0\libresocsim_interface2_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:1642.2-1649.9" + attribute \src "ls180.v:1633.2-1640.9" switch \libresocsim_converter2_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -262389,16 +262230,16 @@ module \ls180 sync always update \libresocsim_interface2_converted_interface_dat_w $0\libresocsim_interface2_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:165.5-165.57" - process $proc$ls180.v:165$1593 + attribute \src "ls180.v:164.5-164.42" + process $proc$ls180.v:164$1601 assign { } { } - assign $1\libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign $1\libresocsim_converter1_counter[0:0] 1'0 sync always sync init - update \libresocsim_interface1_converted_interface_we $1\libresocsim_interface1_converted_interface_we[0:0] + update \libresocsim_converter1_counter $1\libresocsim_converter1_counter[0:0] end - attribute \src "ls180.v:1652.1-1698.4" - process $proc$ls180.v:1652$41 + attribute \src "ls180.v:1643.1-1689.4" + process $proc$ls180.v:1643$41 assign { } { } assign { } { } assign { } { } @@ -262409,23 +262250,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\libresocsim_converter2_skip[0:0] 1'0 assign $0\libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 assign $0\libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign { } { } assign $0\libresocsim_interface2_converted_interface_sel[3:0] 4'0000 - assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0 - assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'0 assign $0\libresocsim_interface2_converted_interface_cyc[0:0] 1'0 assign $0\libresocsim_interface2_converted_interface_stb[0:0] 1'0 + assign { } { } assign $0\libresocsim_interface2_converted_interface_we[0:0] 1'0 + assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0 + assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'0 + assign $0\libresocsim_converter2_skip[0:0] 1'0 assign $0\subfragments_converter2_next_state[0:0] \subfragments_converter2_state - attribute \src "ls180.v:1664.2-1697.9" + attribute \src "ls180.v:1655.2-1688.9" switch \subfragments_converter2_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface2_converted_interface_adr[29:0] { \libresocsim_libresoc_jtag_wb_adr \libresocsim_converter2_counter } - attribute \src "ls180.v:1667.4-1674.11" + attribute \src "ls180.v:1658.4-1665.11" switch \libresocsim_converter2_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -262435,23 +262276,23 @@ module \ls180 assign $0\libresocsim_interface2_converted_interface_sel[3:0] \libresocsim_libresoc_jtag_wb_sel [7:4] case end - attribute \src "ls180.v:1675.4-1688.7" - switch $and$ls180.v:1675$42_Y - attribute \src "ls180.v:1675.8-1675.77" + attribute \src "ls180.v:1666.4-1679.7" + switch $and$ls180.v:1666$42_Y + attribute \src "ls180.v:1666.8-1666.77" case 1'1 - assign $0\libresocsim_converter2_skip[0:0] $eq$ls180.v:1676$43_Y + assign $0\libresocsim_converter2_skip[0:0] $eq$ls180.v:1667$43_Y assign $0\libresocsim_interface2_converted_interface_we[0:0] \libresocsim_libresoc_jtag_wb_we - assign $0\libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:1678$44_Y - assign $0\libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:1679$45_Y - attribute \src "ls180.v:1680.5-1687.8" - switch $or$ls180.v:1680$46_Y - attribute \src "ls180.v:1680.9-1680.87" + assign $0\libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:1669$44_Y + assign $0\libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:1670$45_Y + attribute \src "ls180.v:1671.5-1678.8" + switch $or$ls180.v:1671$46_Y + attribute \src "ls180.v:1671.9-1671.87" case 1'1 - assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] $add$ls180.v:1681$47_Y + assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] $add$ls180.v:1672$47_Y assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:1683.6-1686.9" - switch $eq$ls180.v:1683$48_Y - attribute \src "ls180.v:1683.10-1683.50" + attribute \src "ls180.v:1674.6-1677.9" + switch $eq$ls180.v:1674$48_Y + attribute \src "ls180.v:1674.10-1674.50" case 1'1 assign $0\libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 assign $0\subfragments_converter2_next_state[0:0] 1'0 @@ -262465,9 +262306,9 @@ module \ls180 case assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0 assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:1693.4-1695.7" - switch $and$ls180.v:1693$49_Y - attribute \src "ls180.v:1693.8-1693.77" + attribute \src "ls180.v:1684.4-1686.7" + switch $and$ls180.v:1684$49_Y + attribute \src "ls180.v:1684.8-1684.77" case 1'1 assign $0\subfragments_converter2_next_state[0:0] 1'1 case @@ -262485,56 +262326,56 @@ module \ls180 update \libresocsim_converter2_counter_subfragments_converter2_next_value $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] update \libresocsim_converter2_counter_subfragments_converter2_next_value_ce $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:166.11-166.64" - process $proc$ls180.v:166$1594 + attribute \src "ls180.v:166.12-166.48" + process $proc$ls180.v:166$1602 assign { } { } - assign $0\libresocsim_interface1_converted_interface_cti[2:0] 3'000 + assign $1\libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \libresocsim_interface1_converted_interface_cti $0\libresocsim_interface1_converted_interface_cti[2:0] sync init + update \libresocsim_converter1_dat_r $1\libresocsim_converter1_dat_r[63:0] end - attribute \src "ls180.v:167.11-167.64" - process $proc$ls180.v:167$1595 + attribute \src "ls180.v:167.12-167.66" + process $proc$ls180.v:167$1603 assign { } { } - assign $0\libresocsim_interface1_converted_interface_bte[1:0] 2'00 + assign $1\libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 sync always - update \libresocsim_interface1_converted_interface_bte $0\libresocsim_interface1_converted_interface_bte[1:0] sync init + update \libresocsim_interface2_converted_interface_adr $1\libresocsim_interface2_converted_interface_adr[29:0] end - attribute \src "ls180.v:169.5-169.39" - process $proc$ls180.v:169$1596 + attribute \src "ls180.v:168.12-168.68" + process $proc$ls180.v:168$1604 assign { } { } - assign $1\libresocsim_converter1_skip[0:0] 1'0 + assign $1\libresocsim_interface2_converted_interface_dat_w[31:0] 0 sync always sync init - update \libresocsim_converter1_skip $1\libresocsim_converter1_skip[0:0] + update \libresocsim_interface2_converted_interface_dat_w $1\libresocsim_interface2_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:170.5-170.42" - process $proc$ls180.v:170$1597 + attribute \src "ls180.v:1692.1-1698.4" + process $proc$ls180.v:1692$50 assign { } { } - assign $1\libresocsim_converter1_counter[0:0] 1'0 + assign { } { } + assign $0\libresocsim_we[3:0] [0] $and$ls180.v:1694$53_Y + assign $0\libresocsim_we[3:0] [1] $and$ls180.v:1695$56_Y + assign $0\libresocsim_we[3:0] [2] $and$ls180.v:1696$59_Y + assign $0\libresocsim_we[3:0] [3] $and$ls180.v:1697$62_Y sync always - sync init - update \libresocsim_converter1_counter $1\libresocsim_converter1_counter[0:0] + update \libresocsim_we $0\libresocsim_we[3:0] end - attribute \src "ls180.v:1701.1-1707.4" - process $proc$ls180.v:1701$50 + attribute \src "ls180.v:170.11-170.64" + process $proc$ls180.v:170$1605 assign { } { } - assign { } { } - assign $0\libresocsim_we[3:0] [0] $and$ls180.v:1703$53_Y - assign $0\libresocsim_we[3:0] [1] $and$ls180.v:1704$56_Y - assign $0\libresocsim_we[3:0] [2] $and$ls180.v:1705$59_Y - assign $0\libresocsim_we[3:0] [3] $and$ls180.v:1706$62_Y + assign $1\libresocsim_interface2_converted_interface_sel[3:0] 4'0000 sync always - update \libresocsim_we $0\libresocsim_we[3:0] + sync init + update \libresocsim_interface2_converted_interface_sel $1\libresocsim_interface2_converted_interface_sel[3:0] end - attribute \src "ls180.v:1713.1-1718.4" - process $proc$ls180.v:1713$64 + attribute \src "ls180.v:1704.1-1709.4" + process $proc$ls180.v:1704$64 assign { } { } assign $0\libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:1715.2-1717.5" - switch $and$ls180.v:1715$65_Y - attribute \src "ls180.v:1715.6-1715.80" + attribute \src "ls180.v:1706.2-1708.5" + switch $and$ls180.v:1706$65_Y + attribute \src "ls180.v:1706.6-1706.80" case 1'1 assign $0\libresocsim_zero_clear[0:0] 1'1 case @@ -262542,51 +262383,51 @@ module \ls180 sync always update \libresocsim_zero_clear $0\libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:172.12-172.48" - process $proc$ls180.v:172$1598 + attribute \src "ls180.v:171.5-171.58" + process $proc$ls180.v:171$1606 assign { } { } - assign $1\libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\libresocsim_interface2_converted_interface_cyc[0:0] 1'0 sync always sync init - update \libresocsim_converter1_dat_r $1\libresocsim_converter1_dat_r[63:0] + update \libresocsim_interface2_converted_interface_cyc $1\libresocsim_interface2_converted_interface_cyc[0:0] end - attribute \src "ls180.v:1722.1-1728.4" - process $proc$ls180.v:1722$67 + attribute \src "ls180.v:1713.1-1719.4" + process $proc$ls180.v:1713$67 assign { } { } assign { } { } - assign $0\ram_we[3:0] [0] $and$ls180.v:1724$70_Y - assign $0\ram_we[3:0] [1] $and$ls180.v:1725$73_Y - assign $0\ram_we[3:0] [2] $and$ls180.v:1726$76_Y - assign $0\ram_we[3:0] [3] $and$ls180.v:1727$79_Y + assign $0\ram_we[3:0] [0] $and$ls180.v:1715$70_Y + assign $0\ram_we[3:0] [1] $and$ls180.v:1716$73_Y + assign $0\ram_we[3:0] [2] $and$ls180.v:1717$76_Y + assign $0\ram_we[3:0] [3] $and$ls180.v:1718$79_Y sync always update \ram_we $0\ram_we[3:0] end - attribute \src "ls180.v:173.12-173.66" - process $proc$ls180.v:173$1599 + attribute \src "ls180.v:172.5-172.58" + process $proc$ls180.v:172$1607 assign { } { } - assign $1\libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $1\libresocsim_interface2_converted_interface_stb[0:0] 1'0 sync always sync init - update \libresocsim_interface2_converted_interface_adr $1\libresocsim_interface2_converted_interface_adr[29:0] + update \libresocsim_interface2_converted_interface_stb $1\libresocsim_interface2_converted_interface_stb[0:0] end - attribute \src "ls180.v:174.12-174.68" - process $proc$ls180.v:174$1600 + attribute \src "ls180.v:174.5-174.57" + process $proc$ls180.v:174$1608 assign { } { } - assign $1\libresocsim_interface2_converted_interface_dat_w[31:0] 0 + assign $1\libresocsim_interface2_converted_interface_we[0:0] 1'0 sync always sync init - update \libresocsim_interface2_converted_interface_dat_w $1\libresocsim_interface2_converted_interface_dat_w[31:0] + update \libresocsim_interface2_converted_interface_we $1\libresocsim_interface2_converted_interface_we[0:0] end - attribute \src "ls180.v:176.11-176.64" - process $proc$ls180.v:176$1601 + attribute \src "ls180.v:175.11-175.64" + process $proc$ls180.v:175$1609 assign { } { } - assign $1\libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + assign $0\libresocsim_interface2_converted_interface_cti[2:0] 3'000 sync always + update \libresocsim_interface2_converted_interface_cti $0\libresocsim_interface2_converted_interface_cti[2:0] sync init - update \libresocsim_interface2_converted_interface_sel $1\libresocsim_interface2_converted_interface_sel[3:0] end - attribute \src "ls180.v:1767.1-1821.4" - process $proc$ls180.v:1767$80 + attribute \src "ls180.v:1758.1-1812.4" + process $proc$ls180.v:1758$80 assign { } { } assign { } { } assign { } { } @@ -262623,9 +262464,9 @@ module \ls180 assign $0\sdram_master_p0_wrdata_en[0:0] 1'0 assign $0\sdram_master_p0_wrdata_mask[1:0] 2'00 assign $0\sdram_master_p0_rddata_en[0:0] 1'0 - attribute \src "ls180.v:1786.2-1820.5" + attribute \src "ls180.v:1777.2-1811.5" switch \sdram_sel - attribute \src "ls180.v:1786.6-1786.15" + attribute \src "ls180.v:1777.6-1777.15" case 1'1 assign $0\sdram_master_p0_address[12:0] \sdram_slave_p0_address assign $0\sdram_master_p0_bank[1:0] \sdram_slave_p0_bank @@ -262643,7 +262484,7 @@ module \ls180 assign $0\sdram_master_p0_rddata_en[0:0] \sdram_slave_p0_rddata_en assign $0\sdram_slave_p0_rddata[15:0] \sdram_master_p0_rddata assign $0\sdram_slave_p0_rddata_valid[0:0] \sdram_master_p0_rddata_valid - attribute \src "ls180.v:1803.6-1803.10" + attribute \src "ls180.v:1794.6-1794.10" case assign $0\sdram_master_p0_address[12:0] \sdram_inti_p0_address assign $0\sdram_master_p0_bank[1:0] \sdram_inti_p0_bank @@ -262682,65 +262523,57 @@ module \ls180 update \sdram_master_p0_wrdata_mask $0\sdram_master_p0_wrdata_mask[1:0] update \sdram_master_p0_rddata_en $0\sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:177.5-177.58" - process $proc$ls180.v:177$1602 + attribute \src "ls180.v:176.11-176.64" + process $proc$ls180.v:176$1610 assign { } { } - assign $1\libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $0\libresocsim_interface2_converted_interface_bte[1:0] 2'00 sync always + update \libresocsim_interface2_converted_interface_bte $0\libresocsim_interface2_converted_interface_bte[1:0] sync init - update \libresocsim_interface2_converted_interface_cyc $1\libresocsim_interface2_converted_interface_cyc[0:0] end - attribute \src "ls180.v:178.5-178.58" - process $proc$ls180.v:178$1603 + attribute \src "ls180.v:178.5-178.39" + process $proc$ls180.v:178$1611 assign { } { } - assign $1\libresocsim_interface2_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \libresocsim_interface2_converted_interface_stb $1\libresocsim_interface2_converted_interface_stb[0:0] - end - attribute \src "ls180.v:180.5-180.57" - process $proc$ls180.v:180$1604 - assign { } { } - assign $1\libresocsim_interface2_converted_interface_we[0:0] 1'0 + assign $1\libresocsim_converter2_skip[0:0] 1'0 sync always sync init - update \libresocsim_interface2_converted_interface_we $1\libresocsim_interface2_converted_interface_we[0:0] + update \libresocsim_converter2_skip $1\libresocsim_converter2_skip[0:0] end - attribute \src "ls180.v:181.11-181.64" - process $proc$ls180.v:181$1605 + attribute \src "ls180.v:179.5-179.42" + process $proc$ls180.v:179$1612 assign { } { } - assign $0\libresocsim_interface2_converted_interface_cti[2:0] 3'000 + assign $1\libresocsim_converter2_counter[0:0] 1'0 sync always - update \libresocsim_interface2_converted_interface_cti $0\libresocsim_interface2_converted_interface_cti[2:0] sync init + update \libresocsim_converter2_counter $1\libresocsim_converter2_counter[0:0] end - attribute \src "ls180.v:182.11-182.64" - process $proc$ls180.v:182$1606 + attribute \src "ls180.v:181.12-181.48" + process $proc$ls180.v:181$1613 assign { } { } - assign $0\libresocsim_interface2_converted_interface_bte[1:0] 2'00 + assign $1\libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \libresocsim_interface2_converted_interface_bte $0\libresocsim_interface2_converted_interface_bte[1:0] sync init + update \libresocsim_converter2_dat_r $1\libresocsim_converter2_dat_r[63:0] end - attribute \src "ls180.v:1825.1-1841.4" - process $proc$ls180.v:1825$81 + attribute \src "ls180.v:1816.1-1832.4" + process $proc$ls180.v:1816$81 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sdram_inti_p0_ras_n[0:0] 1'1 - assign $0\sdram_inti_p0_we_n[0:0] 1'1 assign $0\sdram_inti_p0_cas_n[0:0] 1'1 assign $0\sdram_inti_p0_cs_n[0:0] 1'1 - attribute \src "ls180.v:1830.2-1840.5" + assign $0\sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\sdram_inti_p0_we_n[0:0] 1'1 + attribute \src "ls180.v:1821.2-1831.5" switch \sdram_command_issue_re - attribute \src "ls180.v:1830.6-1830.28" + attribute \src "ls180.v:1821.6-1821.28" case 1'1 - assign $0\sdram_inti_p0_cs_n[0:0] $not$ls180.v:1831$82_Y - assign $0\sdram_inti_p0_we_n[0:0] $not$ls180.v:1832$83_Y - assign $0\sdram_inti_p0_cas_n[0:0] $not$ls180.v:1833$84_Y - assign $0\sdram_inti_p0_ras_n[0:0] $not$ls180.v:1834$85_Y - attribute \src "ls180.v:1835.6-1835.10" + assign $0\sdram_inti_p0_cs_n[0:0] $not$ls180.v:1822$82_Y + assign $0\sdram_inti_p0_we_n[0:0] $not$ls180.v:1823$83_Y + assign $0\sdram_inti_p0_cas_n[0:0] $not$ls180.v:1824$84_Y + assign $0\sdram_inti_p0_ras_n[0:0] $not$ls180.v:1825$85_Y + attribute \src "ls180.v:1826.6-1826.10" case assign $0\sdram_inti_p0_cs_n[0:0] 1'1 assign $0\sdram_inti_p0_we_n[0:0] 1'1 @@ -262753,32 +262586,8 @@ module \ls180 update \sdram_inti_p0_ras_n $0\sdram_inti_p0_ras_n[0:0] update \sdram_inti_p0_we_n $0\sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:184.5-184.39" - process $proc$ls180.v:184$1607 - assign { } { } - assign $1\libresocsim_converter2_skip[0:0] 1'0 - sync always - sync init - update \libresocsim_converter2_skip $1\libresocsim_converter2_skip[0:0] - end - attribute \src "ls180.v:185.5-185.42" - process $proc$ls180.v:185$1608 - assign { } { } - assign $1\libresocsim_converter2_counter[0:0] 1'0 - sync always - sync init - update \libresocsim_converter2_counter $1\libresocsim_converter2_counter[0:0] - end - attribute \src "ls180.v:187.12-187.48" - process $proc$ls180.v:187$1609 - assign { } { } - assign $1\libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \libresocsim_converter2_dat_r $1\libresocsim_converter2_dat_r[63:0] - end - attribute \src "ls180.v:1884.1-1914.4" - process $proc$ls180.v:1884$94 + attribute \src "ls180.v:1875.1-1905.4" + process $proc$ls180.v:1875$94 assign { } { } assign { } { } assign { } { } @@ -262788,14 +262597,14 @@ module \ls180 assign { } { } assign $0\sdram_cmd_valid[0:0] 1'0 assign $0\subfragments_refresher_next_state[1:0] \subfragments_refresher_state - attribute \src "ls180.v:1890.2-1913.9" + attribute \src "ls180.v:1881.2-1904.9" switch \subfragments_refresher_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:1893.4-1896.7" + attribute \src "ls180.v:1884.4-1887.7" switch \sdram_cmd_ready - attribute \src "ls180.v:1893.8-1893.23" + attribute \src "ls180.v:1884.8-1884.23" case 1'1 assign $0\sdram_sequencer_start0[0:0] 1'1 assign $0\subfragments_refresher_next_state[1:0] 2'10 @@ -262804,9 +262613,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:1900.4-1904.7" + attribute \src "ls180.v:1891.4-1895.7" switch \sdram_sequencer_done0 - attribute \src "ls180.v:1900.8-1900.29" + attribute \src "ls180.v:1891.8-1891.29" case 1'1 assign $0\sdram_cmd_valid[0:0] 1'0 assign $0\sdram_cmd_last[0:0] 1'1 @@ -262815,13 +262624,13 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:1907.4-1911.7" + attribute \src "ls180.v:1898.4-1902.7" switch 1'1 - attribute \src "ls180.v:1907.8-1907.12" + attribute \src "ls180.v:1898.8-1898.12" case 1'1 - attribute \src "ls180.v:1908.5-1910.8" + attribute \src "ls180.v:1899.5-1901.8" switch \sdram_wants_refresh - attribute \src "ls180.v:1908.9-1908.28" + attribute \src "ls180.v:1899.9-1899.28" case 1'1 assign $0\subfragments_refresher_next_state[1:0] 2'01 case @@ -262835,43 +262644,51 @@ module \ls180 update \sdram_sequencer_start0 $0\sdram_sequencer_start0[0:0] update \subfragments_refresher_next_state $0\subfragments_refresher_next_state[1:0] end - attribute \src "ls180.v:1929.1-1936.4" - process $proc$ls180.v:1929$98 + attribute \src "ls180.v:188.5-188.35" + process $proc$ls180.v:188$1614 + assign { } { } + assign $1\libresocsim_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \libresocsim_ram_bus_ack $1\libresocsim_ram_bus_ack[0:0] + end + attribute \src "ls180.v:192.5-192.35" + process $proc$ls180.v:192$1615 + assign { } { } + assign $0\libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \libresocsim_ram_bus_err $0\libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:1920.1-1927.4" + process $proc$ls180.v:1920$98 assign { } { } assign $0\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:1931.2-1935.5" + attribute \src "ls180.v:1922.2-1926.5" switch \sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:1931.6-1931.43" + attribute \src "ls180.v:1922.6-1922.43" case 1'1 assign $0\sdram_bankmachine0_cmd_payload_a[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:1933.6-1933.10" + attribute \src "ls180.v:1924.6-1924.10" case - assign $0\sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:1934$100_Y + assign $0\sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:1925$100_Y end sync always update \sdram_bankmachine0_cmd_payload_a $0\sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:194.5-194.35" - process $proc$ls180.v:194$1610 - assign { } { } - assign $1\libresocsim_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \libresocsim_ram_bus_ack $1\libresocsim_ram_bus_ack[0:0] - end - attribute \src "ls180.v:1940.1-1947.4" - process $proc$ls180.v:1940$107 + attribute \src "ls180.v:1931.1-1938.4" + process $proc$ls180.v:1931$107 assign { } { } assign $0\sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:1942.2-1946.5" - switch $and$ls180.v:1942$108_Y - attribute \src "ls180.v:1942.6-1942.105" + attribute \src "ls180.v:1933.2-1937.5" + switch $and$ls180.v:1933$108_Y + attribute \src "ls180.v:1933.6-1933.105" case 1'1 - attribute \src "ls180.v:1943.3-1945.6" - switch $ne$ls180.v:1943$109_Y - attribute \src "ls180.v:1943.7-1943.133" + attribute \src "ls180.v:1934.3-1936.6" + switch $ne$ls180.v:1934$109_Y + attribute \src "ls180.v:1934.7-1934.133" case 1'1 - assign $0\sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:1944$110_Y + assign $0\sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:1935$110_Y case end case @@ -262879,24 +262696,32 @@ module \ls180 sync always update \sdram_bankmachine0_auto_precharge $0\sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:1962.1-1969.4" - process $proc$ls180.v:1962$111 + attribute \src "ls180.v:195.11-195.32" + process $proc$ls180.v:195$1616 + assign { } { } + assign $1\libresocsim_we[3:0] 4'0000 + sync always + sync init + update \libresocsim_we $1\libresocsim_we[3:0] + end + attribute \src "ls180.v:1953.1-1960.4" + process $proc$ls180.v:1953$111 assign { } { } assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:1964.2-1968.5" + attribute \src "ls180.v:1955.2-1959.5" switch \sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:1964.6-1964.53" + attribute \src "ls180.v:1955.6-1955.53" case 1'1 - assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:1965$112_Y - attribute \src "ls180.v:1966.6-1966.10" + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:1956$112_Y + attribute \src "ls180.v:1957.6-1957.10" case assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_produce end sync always update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:1978.1-2071.4" - process $proc$ls180.v:1978$120 + attribute \src "ls180.v:1969.1-2062.4" + process $proc$ls180.v:1969$120 assign { } { } assign { } { } assign { } { } @@ -262911,37 +262736,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 assign $0\sdram_bankmachine0_req_wdata_ready[0:0] 1'0 assign $0\sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign { } { } assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'0 assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'0 assign $0\sdram_bankmachine0_row_open[0:0] 1'0 assign $0\sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 assign $0\subfragments_bankmachine0_next_state[2:0] \subfragments_bankmachine0_state - attribute \src "ls180.v:1994.2-2070.9" + attribute \src "ls180.v:1985.2-2061.9" switch \subfragments_bankmachine0_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:1996.4-2004.7" - switch $and$ls180.v:1996$121_Y - attribute \src "ls180.v:1996.8-1996.77" + attribute \src "ls180.v:1987.4-1995.7" + switch $and$ls180.v:1987$121_Y + attribute \src "ls180.v:1987.8-1987.77" case 1'1 assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:1998.5-2000.8" + attribute \src "ls180.v:1989.5-1991.8" switch \sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:1998.9-1998.37" + attribute \src "ls180.v:1989.9-1989.37" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'101 case @@ -262951,27 +262776,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:2008.4-2010.7" - switch $and$ls180.v:2008$122_Y - attribute \src "ls180.v:2008.8-2008.77" + attribute \src "ls180.v:1999.4-2001.7" + switch $and$ls180.v:1999$122_Y + attribute \src "ls180.v:1999.8-1999.77" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:2014.4-2023.7" + attribute \src "ls180.v:2005.4-2014.7" switch \sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:2014.8-2014.39" + attribute \src "ls180.v:2005.8-2005.39" case 1'1 assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 assign $0\sdram_bankmachine0_row_open[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:2019.5-2021.8" + attribute \src "ls180.v:2010.5-2012.8" switch \sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:2019.9-2019.37" + attribute \src "ls180.v:2010.9-2010.37" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'110 case @@ -262982,16 +262807,16 @@ module \ls180 case 3'100 assign $0\sdram_bankmachine0_row_close[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:2026.4-2028.7" + attribute \src "ls180.v:2017.4-2019.7" switch \sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:2026.8-2026.40" + attribute \src "ls180.v:2017.8-2017.40" case 1'1 assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:2031.4-2033.7" - switch $not$ls180.v:2031$123_Y - attribute \src "ls180.v:2031.8-2031.41" + attribute \src "ls180.v:2022.4-2024.7" + switch $not$ls180.v:2022$123_Y + attribute \src "ls180.v:2022.8-2022.41" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'000 case @@ -263004,51 +262829,51 @@ module \ls180 assign $0\subfragments_bankmachine0_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:2042.4-2068.7" + attribute \src "ls180.v:2033.4-2059.7" switch \sdram_bankmachine0_refresh_req - attribute \src "ls180.v:2042.8-2042.38" + attribute \src "ls180.v:2033.8-2033.38" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:2044.8-2044.12" + attribute \src "ls180.v:2035.8-2035.12" case - attribute \src "ls180.v:2045.5-2067.8" + attribute \src "ls180.v:2036.5-2058.8" switch \sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:2045.9-2045.51" + attribute \src "ls180.v:2036.9-2036.51" case 1'1 - attribute \src "ls180.v:2046.6-2066.9" + attribute \src "ls180.v:2037.6-2057.9" switch \sdram_bankmachine0_row_opened - attribute \src "ls180.v:2046.10-2046.39" + attribute \src "ls180.v:2037.10-2037.39" case 1'1 - attribute \src "ls180.v:2047.7-2063.10" + attribute \src "ls180.v:2038.7-2054.10" switch \sdram_bankmachine0_row_hit - attribute \src "ls180.v:2047.11-2047.37" + attribute \src "ls180.v:2038.11-2038.37" case 1'1 assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:2049.8-2056.11" + attribute \src "ls180.v:2040.8-2047.11" switch \sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:2049.12-2049.59" + attribute \src "ls180.v:2040.12-2040.59" case 1'1 assign $0\sdram_bankmachine0_req_wdata_ready[0:0] \sdram_bankmachine0_cmd_ready assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:2053.12-2053.16" + attribute \src "ls180.v:2044.12-2044.16" case assign $0\sdram_bankmachine0_req_rdata_valid[0:0] \sdram_bankmachine0_cmd_ready assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:2058.8-2060.11" - switch $and$ls180.v:2058$124_Y - attribute \src "ls180.v:2058.12-2058.78" + attribute \src "ls180.v:2049.8-2051.11" + switch $and$ls180.v:2049$124_Y + attribute \src "ls180.v:2049.12-2049.78" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'010 case end - attribute \src "ls180.v:2061.11-2061.15" + attribute \src "ls180.v:2052.11-2052.15" case assign $0\subfragments_bankmachine0_next_state[2:0] 3'001 end - attribute \src "ls180.v:2064.10-2064.14" + attribute \src "ls180.v:2055.10-2055.14" case assign $0\subfragments_bankmachine0_next_state[2:0] 3'011 end @@ -263072,107 +262897,107 @@ module \ls180 update \sdram_bankmachine0_row_col_n_addr_sel $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] update \subfragments_bankmachine0_next_state $0\subfragments_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:198.5-198.35" - process $proc$ls180.v:198$1611 - assign { } { } - assign $0\libresocsim_ram_bus_err[0:0] 1'0 - sync always - update \libresocsim_ram_bus_err $0\libresocsim_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:201.11-201.32" - process $proc$ls180.v:201$1612 - assign { } { } - assign $1\libresocsim_we[3:0] 4'0000 - sync always - sync init - update \libresocsim_we $1\libresocsim_we[3:0] - end - attribute \src "ls180.v:203.12-203.44" - process $proc$ls180.v:203$1613 + attribute \src "ls180.v:197.12-197.44" + process $proc$ls180.v:197$1617 assign { } { } assign $1\libresocsim_load_storage[31:0] 0 sync always sync init update \libresocsim_load_storage $1\libresocsim_load_storage[31:0] end - attribute \src "ls180.v:204.5-204.31" - process $proc$ls180.v:204$1614 + attribute \src "ls180.v:198.5-198.31" + process $proc$ls180.v:198$1618 assign { } { } assign $1\libresocsim_load_re[0:0] 1'0 sync always sync init update \libresocsim_load_re $1\libresocsim_load_re[0:0] end - attribute \src "ls180.v:205.12-205.46" - process $proc$ls180.v:205$1615 + attribute \src "ls180.v:199.12-199.46" + process $proc$ls180.v:199$1619 assign { } { } assign $1\libresocsim_reload_storage[31:0] 0 sync always sync init update \libresocsim_reload_storage $1\libresocsim_reload_storage[31:0] end - attribute \src "ls180.v:206.5-206.33" - process $proc$ls180.v:206$1616 + attribute \src "ls180.v:200.5-200.33" + process $proc$ls180.v:200$1620 assign { } { } assign $1\libresocsim_reload_re[0:0] 1'0 sync always sync init update \libresocsim_reload_re $1\libresocsim_reload_re[0:0] end - attribute \src "ls180.v:207.5-207.34" - process $proc$ls180.v:207$1617 + attribute \src "ls180.v:201.5-201.34" + process $proc$ls180.v:201$1621 assign { } { } assign $1\libresocsim_en_storage[0:0] 1'0 sync always sync init update \libresocsim_en_storage $1\libresocsim_en_storage[0:0] end - attribute \src "ls180.v:208.5-208.29" - process $proc$ls180.v:208$1618 + attribute \src "ls180.v:202.5-202.29" + process $proc$ls180.v:202$1622 assign { } { } assign $1\libresocsim_en_re[0:0] 1'0 sync always sync init update \libresocsim_en_re $1\libresocsim_en_re[0:0] end - attribute \src "ls180.v:2086.1-2093.4" - process $proc$ls180.v:2086$128 + attribute \src "ls180.v:203.5-203.44" + process $proc$ls180.v:203$1623 + assign { } { } + assign $1\libresocsim_update_value_storage[0:0] 1'0 + sync always + sync init + update \libresocsim_update_value_storage $1\libresocsim_update_value_storage[0:0] + end + attribute \src "ls180.v:204.5-204.39" + process $proc$ls180.v:204$1624 + assign { } { } + assign $1\libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \libresocsim_update_value_re $1\libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:205.12-205.44" + process $proc$ls180.v:205$1625 + assign { } { } + assign $1\libresocsim_value_status[31:0] 0 + sync always + sync init + update \libresocsim_value_status $1\libresocsim_value_status[31:0] + end + attribute \src "ls180.v:2077.1-2084.4" + process $proc$ls180.v:2077$128 assign { } { } assign $0\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:2088.2-2092.5" + attribute \src "ls180.v:2079.2-2083.5" switch \sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:2088.6-2088.43" + attribute \src "ls180.v:2079.6-2079.43" case 1'1 assign $0\sdram_bankmachine1_cmd_payload_a[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:2090.6-2090.10" + attribute \src "ls180.v:2081.6-2081.10" case - assign $0\sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:2091$130_Y + assign $0\sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:2082$130_Y end sync always update \sdram_bankmachine1_cmd_payload_a $0\sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:209.5-209.44" - process $proc$ls180.v:209$1619 - assign { } { } - assign $1\libresocsim_update_value_storage[0:0] 1'0 - sync always - sync init - update \libresocsim_update_value_storage $1\libresocsim_update_value_storage[0:0] - end - attribute \src "ls180.v:2097.1-2104.4" - process $proc$ls180.v:2097$137 + attribute \src "ls180.v:2088.1-2095.4" + process $proc$ls180.v:2088$137 assign { } { } assign $0\sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:2099.2-2103.5" - switch $and$ls180.v:2099$138_Y - attribute \src "ls180.v:2099.6-2099.105" + attribute \src "ls180.v:2090.2-2094.5" + switch $and$ls180.v:2090$138_Y + attribute \src "ls180.v:2090.6-2090.105" case 1'1 - attribute \src "ls180.v:2100.3-2102.6" - switch $ne$ls180.v:2100$139_Y - attribute \src "ls180.v:2100.7-2100.133" + attribute \src "ls180.v:2091.3-2093.6" + switch $ne$ls180.v:2091$139_Y + attribute \src "ls180.v:2091.7-2091.133" case 1'1 - assign $0\sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:2101$140_Y + assign $0\sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:2092$140_Y case end case @@ -263180,40 +263005,48 @@ module \ls180 sync always update \sdram_bankmachine1_auto_precharge $0\sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:210.5-210.39" - process $proc$ls180.v:210$1620 + attribute \src "ls180.v:209.5-209.36" + process $proc$ls180.v:209$1626 assign { } { } - assign $1\libresocsim_update_value_re[0:0] 1'0 + assign $1\libresocsim_zero_pending[0:0] 1'0 sync always sync init - update \libresocsim_update_value_re $1\libresocsim_update_value_re[0:0] + update \libresocsim_zero_pending $1\libresocsim_zero_pending[0:0] end - attribute \src "ls180.v:211.12-211.44" - process $proc$ls180.v:211$1621 + attribute \src "ls180.v:211.5-211.34" + process $proc$ls180.v:211$1627 assign { } { } - assign $1\libresocsim_value_status[31:0] 0 + assign $1\libresocsim_zero_clear[0:0] 1'0 sync always sync init - update \libresocsim_value_status $1\libresocsim_value_status[31:0] + update \libresocsim_zero_clear $1\libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:2119.1-2126.4" - process $proc$ls180.v:2119$141 + attribute \src "ls180.v:2110.1-2117.4" + process $proc$ls180.v:2110$141 assign { } { } assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:2121.2-2125.5" + attribute \src "ls180.v:2112.2-2116.5" switch \sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:2121.6-2121.53" + attribute \src "ls180.v:2112.6-2112.53" case 1'1 - assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2122$142_Y - attribute \src "ls180.v:2123.6-2123.10" + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2113$142_Y + attribute \src "ls180.v:2114.6-2114.10" case assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_produce end sync always update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:2135.1-2228.4" - process $proc$ls180.v:2135$150 + attribute \src "ls180.v:212.5-212.40" + process $proc$ls180.v:212$1628 + assign { } { } + assign $1\libresocsim_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \libresocsim_zero_old_trigger $1\libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:2126.1-2219.4" + process $proc$ls180.v:2126$150 assign { } { } assign { } { } assign { } { } @@ -263228,37 +263061,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\sdram_bankmachine1_row_open[0:0] 1'0 - assign $0\sdram_bankmachine1_row_close[0:0] 1'0 - assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign { } { } assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 assign $0\sdram_bankmachine1_req_wdata_ready[0:0] 1'0 assign $0\sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - assign { } { } assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'0 assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $0\sdram_bankmachine1_row_open[0:0] 1'0 + assign $0\sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 assign $0\subfragments_bankmachine1_next_state[2:0] \subfragments_bankmachine1_state - attribute \src "ls180.v:2151.2-2227.9" + attribute \src "ls180.v:2142.2-2218.9" switch \subfragments_bankmachine1_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:2153.4-2161.7" - switch $and$ls180.v:2153$151_Y - attribute \src "ls180.v:2153.8-2153.77" + attribute \src "ls180.v:2144.4-2152.7" + switch $and$ls180.v:2144$151_Y + attribute \src "ls180.v:2144.8-2144.77" case 1'1 assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:2155.5-2157.8" + attribute \src "ls180.v:2146.5-2148.8" switch \sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:2155.9-2155.37" + attribute \src "ls180.v:2146.9-2146.37" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'101 case @@ -263268,27 +263101,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:2165.4-2167.7" - switch $and$ls180.v:2165$152_Y - attribute \src "ls180.v:2165.8-2165.77" + attribute \src "ls180.v:2156.4-2158.7" + switch $and$ls180.v:2156$152_Y + attribute \src "ls180.v:2156.8-2156.77" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:2171.4-2180.7" + attribute \src "ls180.v:2162.4-2171.7" switch \sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:2171.8-2171.39" + attribute \src "ls180.v:2162.8-2162.39" case 1'1 assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 assign $0\sdram_bankmachine1_row_open[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:2176.5-2178.8" + attribute \src "ls180.v:2167.5-2169.8" switch \sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:2176.9-2176.37" + attribute \src "ls180.v:2167.9-2167.37" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'110 case @@ -263299,16 +263132,16 @@ module \ls180 case 3'100 assign $0\sdram_bankmachine1_row_close[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:2183.4-2185.7" + attribute \src "ls180.v:2174.4-2176.7" switch \sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:2183.8-2183.40" + attribute \src "ls180.v:2174.8-2174.40" case 1'1 assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:2188.4-2190.7" - switch $not$ls180.v:2188$153_Y - attribute \src "ls180.v:2188.8-2188.41" + attribute \src "ls180.v:2179.4-2181.7" + switch $not$ls180.v:2179$153_Y + attribute \src "ls180.v:2179.8-2179.41" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'000 case @@ -263321,51 +263154,51 @@ module \ls180 assign $0\subfragments_bankmachine1_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:2199.4-2225.7" + attribute \src "ls180.v:2190.4-2216.7" switch \sdram_bankmachine1_refresh_req - attribute \src "ls180.v:2199.8-2199.38" + attribute \src "ls180.v:2190.8-2190.38" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:2201.8-2201.12" + attribute \src "ls180.v:2192.8-2192.12" case - attribute \src "ls180.v:2202.5-2224.8" + attribute \src "ls180.v:2193.5-2215.8" switch \sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:2202.9-2202.51" + attribute \src "ls180.v:2193.9-2193.51" case 1'1 - attribute \src "ls180.v:2203.6-2223.9" + attribute \src "ls180.v:2194.6-2214.9" switch \sdram_bankmachine1_row_opened - attribute \src "ls180.v:2203.10-2203.39" + attribute \src "ls180.v:2194.10-2194.39" case 1'1 - attribute \src "ls180.v:2204.7-2220.10" + attribute \src "ls180.v:2195.7-2211.10" switch \sdram_bankmachine1_row_hit - attribute \src "ls180.v:2204.11-2204.37" + attribute \src "ls180.v:2195.11-2195.37" case 1'1 assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:2206.8-2213.11" + attribute \src "ls180.v:2197.8-2204.11" switch \sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:2206.12-2206.59" + attribute \src "ls180.v:2197.12-2197.59" case 1'1 assign $0\sdram_bankmachine1_req_wdata_ready[0:0] \sdram_bankmachine1_cmd_ready assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:2210.12-2210.16" + attribute \src "ls180.v:2201.12-2201.16" case assign $0\sdram_bankmachine1_req_rdata_valid[0:0] \sdram_bankmachine1_cmd_ready assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:2215.8-2217.11" - switch $and$ls180.v:2215$154_Y - attribute \src "ls180.v:2215.12-2215.78" + attribute \src "ls180.v:2206.8-2208.11" + switch $and$ls180.v:2206$154_Y + attribute \src "ls180.v:2206.12-2206.78" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'010 case end - attribute \src "ls180.v:2218.11-2218.15" + attribute \src "ls180.v:2209.11-2209.15" case assign $0\subfragments_bankmachine1_next_state[2:0] 3'001 end - attribute \src "ls180.v:2221.10-2221.14" + attribute \src "ls180.v:2212.10-2212.14" case assign $0\subfragments_bankmachine1_next_state[2:0] 3'011 end @@ -263389,59 +263222,59 @@ module \ls180 update \sdram_bankmachine1_row_col_n_addr_sel $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] update \subfragments_bankmachine1_next_state $0\subfragments_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:215.5-215.36" - process $proc$ls180.v:215$1622 + attribute \src "ls180.v:221.5-221.44" + process $proc$ls180.v:221$1629 assign { } { } - assign $1\libresocsim_zero_pending[0:0] 1'0 + assign $1\libresocsim_eventmanager_storage[0:0] 1'0 sync always sync init - update \libresocsim_zero_pending $1\libresocsim_zero_pending[0:0] + update \libresocsim_eventmanager_storage $1\libresocsim_eventmanager_storage[0:0] end - attribute \src "ls180.v:217.5-217.34" - process $proc$ls180.v:217$1623 + attribute \src "ls180.v:222.5-222.39" + process $proc$ls180.v:222$1630 assign { } { } - assign $1\libresocsim_zero_clear[0:0] 1'0 + assign $1\libresocsim_eventmanager_re[0:0] 1'0 sync always sync init - update \libresocsim_zero_clear $1\libresocsim_zero_clear[0:0] + update \libresocsim_eventmanager_re $1\libresocsim_eventmanager_re[0:0] end - attribute \src "ls180.v:218.5-218.40" - process $proc$ls180.v:218$1624 + attribute \src "ls180.v:223.12-223.37" + process $proc$ls180.v:223$1631 assign { } { } - assign $1\libresocsim_zero_old_trigger[0:0] 1'0 + assign $1\libresocsim_value[31:0] 0 sync always sync init - update \libresocsim_zero_old_trigger $1\libresocsim_zero_old_trigger[0:0] + update \libresocsim_value $1\libresocsim_value[31:0] end - attribute \src "ls180.v:2243.1-2250.4" - process $proc$ls180.v:2243$158 + attribute \src "ls180.v:2234.1-2241.4" + process $proc$ls180.v:2234$158 assign { } { } assign $0\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:2245.2-2249.5" + attribute \src "ls180.v:2236.2-2240.5" switch \sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:2245.6-2245.43" + attribute \src "ls180.v:2236.6-2236.43" case 1'1 assign $0\sdram_bankmachine2_cmd_payload_a[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:2247.6-2247.10" + attribute \src "ls180.v:2238.6-2238.10" case - assign $0\sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:2248$160_Y + assign $0\sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:2239$160_Y end sync always update \sdram_bankmachine2_cmd_payload_a $0\sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:2254.1-2261.4" - process $proc$ls180.v:2254$167 + attribute \src "ls180.v:2245.1-2252.4" + process $proc$ls180.v:2245$167 assign { } { } assign $0\sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:2256.2-2260.5" - switch $and$ls180.v:2256$168_Y - attribute \src "ls180.v:2256.6-2256.105" + attribute \src "ls180.v:2247.2-2251.5" + switch $and$ls180.v:2247$168_Y + attribute \src "ls180.v:2247.6-2247.105" case 1'1 - attribute \src "ls180.v:2257.3-2259.6" - switch $ne$ls180.v:2257$169_Y - attribute \src "ls180.v:2257.7-2257.133" + attribute \src "ls180.v:2248.3-2250.6" + switch $ne$ls180.v:2248$169_Y + attribute \src "ls180.v:2248.7-2248.133" case 1'1 - assign $0\sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:2258$170_Y + assign $0\sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:2249$170_Y case end case @@ -263449,48 +263282,25 @@ module \ls180 sync always update \sdram_bankmachine2_auto_precharge $0\sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:227.5-227.44" - process $proc$ls180.v:227$1625 - assign { } { } - assign $1\libresocsim_eventmanager_storage[0:0] 1'0 - sync always - sync init - update \libresocsim_eventmanager_storage $1\libresocsim_eventmanager_storage[0:0] - end - attribute \src "ls180.v:2276.1-2283.4" - process $proc$ls180.v:2276$171 + attribute \src "ls180.v:2267.1-2274.4" + process $proc$ls180.v:2267$171 assign { } { } assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:2278.2-2282.5" + attribute \src "ls180.v:2269.2-2273.5" switch \sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:2278.6-2278.53" + attribute \src "ls180.v:2269.6-2269.53" case 1'1 - assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2279$172_Y - attribute \src "ls180.v:2280.6-2280.10" + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2270$172_Y + attribute \src "ls180.v:2271.6-2271.10" case assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_produce end sync always update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:228.5-228.39" - process $proc$ls180.v:228$1626 + attribute \src "ls180.v:2283.1-2376.4" + process $proc$ls180.v:2283$180 assign { } { } - assign $1\libresocsim_eventmanager_re[0:0] 1'0 - sync always - sync init - update \libresocsim_eventmanager_re $1\libresocsim_eventmanager_re[0:0] - end - attribute \src "ls180.v:229.12-229.37" - process $proc$ls180.v:229$1627 - assign { } { } - assign $1\libresocsim_value[31:0] 0 - sync always - sync init - update \libresocsim_value $1\libresocsim_value[31:0] - end - attribute \src "ls180.v:2292.1-2385.4" - process $proc$ls180.v:2292$180 assign { } { } assign { } { } assign { } { } @@ -263504,11 +263314,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'0 - assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'0 assign $0\sdram_bankmachine2_row_open[0:0] 1'0 assign $0\sdram_bankmachine2_row_close[0:0] 1'0 assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 @@ -263516,26 +263321,30 @@ module \ls180 assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'0 assign $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - assign { } { } + assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 assign $0\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 assign $0\sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign { } { } assign $0\subfragments_bankmachine2_next_state[2:0] \subfragments_bankmachine2_state - attribute \src "ls180.v:2308.2-2384.9" + attribute \src "ls180.v:2299.2-2375.9" switch \subfragments_bankmachine2_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:2310.4-2318.7" - switch $and$ls180.v:2310$181_Y - attribute \src "ls180.v:2310.8-2310.77" + attribute \src "ls180.v:2301.4-2309.7" + switch $and$ls180.v:2301$181_Y + attribute \src "ls180.v:2301.8-2301.77" case 1'1 assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:2312.5-2314.8" + attribute \src "ls180.v:2303.5-2305.8" switch \sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:2312.9-2312.37" + attribute \src "ls180.v:2303.9-2303.37" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'101 case @@ -263545,27 +263354,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:2322.4-2324.7" - switch $and$ls180.v:2322$182_Y - attribute \src "ls180.v:2322.8-2322.77" + attribute \src "ls180.v:2313.4-2315.7" + switch $and$ls180.v:2313$182_Y + attribute \src "ls180.v:2313.8-2313.77" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:2328.4-2337.7" + attribute \src "ls180.v:2319.4-2328.7" switch \sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:2328.8-2328.39" + attribute \src "ls180.v:2319.8-2319.39" case 1'1 assign $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 assign $0\sdram_bankmachine2_row_open[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:2333.5-2335.8" + attribute \src "ls180.v:2324.5-2326.8" switch \sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:2333.9-2333.37" + attribute \src "ls180.v:2324.9-2324.37" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'110 case @@ -263576,16 +263385,16 @@ module \ls180 case 3'100 assign $0\sdram_bankmachine2_row_close[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:2340.4-2342.7" + attribute \src "ls180.v:2331.4-2333.7" switch \sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:2340.8-2340.40" + attribute \src "ls180.v:2331.8-2331.40" case 1'1 assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:2345.4-2347.7" - switch $not$ls180.v:2345$183_Y - attribute \src "ls180.v:2345.8-2345.41" + attribute \src "ls180.v:2336.4-2338.7" + switch $not$ls180.v:2336$183_Y + attribute \src "ls180.v:2336.8-2336.41" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'000 case @@ -263598,51 +263407,51 @@ module \ls180 assign $0\subfragments_bankmachine2_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:2356.4-2382.7" + attribute \src "ls180.v:2347.4-2373.7" switch \sdram_bankmachine2_refresh_req - attribute \src "ls180.v:2356.8-2356.38" + attribute \src "ls180.v:2347.8-2347.38" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:2358.8-2358.12" + attribute \src "ls180.v:2349.8-2349.12" case - attribute \src "ls180.v:2359.5-2381.8" + attribute \src "ls180.v:2350.5-2372.8" switch \sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:2359.9-2359.51" + attribute \src "ls180.v:2350.9-2350.51" case 1'1 - attribute \src "ls180.v:2360.6-2380.9" + attribute \src "ls180.v:2351.6-2371.9" switch \sdram_bankmachine2_row_opened - attribute \src "ls180.v:2360.10-2360.39" + attribute \src "ls180.v:2351.10-2351.39" case 1'1 - attribute \src "ls180.v:2361.7-2377.10" + attribute \src "ls180.v:2352.7-2368.10" switch \sdram_bankmachine2_row_hit - attribute \src "ls180.v:2361.11-2361.37" + attribute \src "ls180.v:2352.11-2352.37" case 1'1 assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:2363.8-2370.11" + attribute \src "ls180.v:2354.8-2361.11" switch \sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:2363.12-2363.59" + attribute \src "ls180.v:2354.12-2354.59" case 1'1 assign $0\sdram_bankmachine2_req_wdata_ready[0:0] \sdram_bankmachine2_cmd_ready assign $0\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:2367.12-2367.16" + attribute \src "ls180.v:2358.12-2358.16" case assign $0\sdram_bankmachine2_req_rdata_valid[0:0] \sdram_bankmachine2_cmd_ready assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:2372.8-2374.11" - switch $and$ls180.v:2372$184_Y - attribute \src "ls180.v:2372.12-2372.78" + attribute \src "ls180.v:2363.8-2365.11" + switch $and$ls180.v:2363$184_Y + attribute \src "ls180.v:2363.12-2363.78" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'010 case end - attribute \src "ls180.v:2375.11-2375.15" + attribute \src "ls180.v:2366.11-2366.15" case assign $0\subfragments_bankmachine2_next_state[2:0] 3'001 end - attribute \src "ls180.v:2378.10-2378.14" + attribute \src "ls180.v:2369.10-2369.14" case assign $0\subfragments_bankmachine2_next_state[2:0] 3'011 end @@ -263666,51 +263475,59 @@ module \ls180 update \sdram_bankmachine2_row_col_n_addr_sel $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] update \subfragments_bankmachine2_next_state $0\subfragments_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:236.5-236.31" - process $proc$ls180.v:236$1628 + attribute \src "ls180.v:230.5-230.31" + process $proc$ls180.v:230$1632 assign { } { } assign $1\ram_bus_ram_bus_ack[0:0] 1'0 sync always sync init update \ram_bus_ram_bus_ack $1\ram_bus_ram_bus_ack[0:0] end - attribute \src "ls180.v:240.5-240.31" - process $proc$ls180.v:240$1629 + attribute \src "ls180.v:234.5-234.31" + process $proc$ls180.v:234$1633 assign { } { } assign $0\ram_bus_ram_bus_err[0:0] 1'0 sync always update \ram_bus_ram_bus_err $0\ram_bus_ram_bus_err[0:0] sync init end - attribute \src "ls180.v:2400.1-2407.4" - process $proc$ls180.v:2400$188 + attribute \src "ls180.v:237.11-237.24" + process $proc$ls180.v:237$1634 + assign { } { } + assign $1\ram_we[3:0] 4'0000 + sync always + sync init + update \ram_we $1\ram_we[3:0] + end + attribute \src "ls180.v:2391.1-2398.4" + process $proc$ls180.v:2391$188 assign { } { } assign $0\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:2402.2-2406.5" + attribute \src "ls180.v:2393.2-2397.5" switch \sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:2402.6-2402.43" + attribute \src "ls180.v:2393.6-2393.43" case 1'1 assign $0\sdram_bankmachine3_cmd_payload_a[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:2404.6-2404.10" + attribute \src "ls180.v:2395.6-2395.10" case - assign $0\sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:2405$190_Y + assign $0\sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:2396$190_Y end sync always update \sdram_bankmachine3_cmd_payload_a $0\sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:2411.1-2418.4" - process $proc$ls180.v:2411$197 + attribute \src "ls180.v:2402.1-2409.4" + process $proc$ls180.v:2402$197 assign { } { } assign $0\sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:2413.2-2417.5" - switch $and$ls180.v:2413$198_Y - attribute \src "ls180.v:2413.6-2413.105" + attribute \src "ls180.v:2404.2-2408.5" + switch $and$ls180.v:2404$198_Y + attribute \src "ls180.v:2404.6-2404.105" case 1'1 - attribute \src "ls180.v:2414.3-2416.6" - switch $ne$ls180.v:2414$199_Y - attribute \src "ls180.v:2414.7-2414.133" + attribute \src "ls180.v:2405.3-2407.6" + switch $ne$ls180.v:2405$199_Y + attribute \src "ls180.v:2405.7-2405.133" case 1'1 - assign $0\sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:2415$200_Y + assign $0\sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:2406$200_Y case end case @@ -263718,32 +263535,32 @@ module \ls180 sync always update \sdram_bankmachine3_auto_precharge $0\sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:243.11-243.24" - process $proc$ls180.v:243$1630 + attribute \src "ls180.v:242.5-242.19" + process $proc$ls180.v:242$1635 assign { } { } - assign $1\ram_we[3:0] 4'0000 + assign $1\int_rst[0:0] 1'1 sync always sync init - update \ram_we $1\ram_we[3:0] + update \int_rst $1\int_rst[0:0] end - attribute \src "ls180.v:2433.1-2440.4" - process $proc$ls180.v:2433$201 + attribute \src "ls180.v:2424.1-2431.4" + process $proc$ls180.v:2424$201 assign { } { } assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:2435.2-2439.5" + attribute \src "ls180.v:2426.2-2430.5" switch \sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:2435.6-2435.53" + attribute \src "ls180.v:2426.6-2426.53" case 1'1 - assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2436$202_Y - attribute \src "ls180.v:2437.6-2437.10" + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2427$202_Y + attribute \src "ls180.v:2428.6-2428.10" case assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_produce end sync always update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:2449.1-2542.4" - process $proc$ls180.v:2449$210 + attribute \src "ls180.v:2440.1-2533.4" + process $proc$ls180.v:2440$210 assign { } { } assign { } { } assign { } { } @@ -263758,37 +263575,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - assign $0\sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - assign $0\sdram_bankmachine3_req_rdata_valid[0:0] 1'0 assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'0 assign $0\sdram_bankmachine3_row_open[0:0] 1'0 - assign { } { } + assign $0\sdram_bankmachine3_req_wdata_ready[0:0] 1'0 assign $0\sdram_bankmachine3_row_close[0:0] 1'0 assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign { } { } + assign $0\sdram_bankmachine3_req_rdata_valid[0:0] 1'0 assign $0\subfragments_bankmachine3_next_state[2:0] \subfragments_bankmachine3_state - attribute \src "ls180.v:2465.2-2541.9" + attribute \src "ls180.v:2456.2-2532.9" switch \subfragments_bankmachine3_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:2467.4-2475.7" - switch $and$ls180.v:2467$211_Y - attribute \src "ls180.v:2467.8-2467.77" + attribute \src "ls180.v:2458.4-2466.7" + switch $and$ls180.v:2458$211_Y + attribute \src "ls180.v:2458.8-2458.77" case 1'1 assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:2469.5-2471.8" + attribute \src "ls180.v:2460.5-2462.8" switch \sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:2469.9-2469.37" + attribute \src "ls180.v:2460.9-2460.37" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'101 case @@ -263798,27 +263615,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:2479.4-2481.7" - switch $and$ls180.v:2479$212_Y - attribute \src "ls180.v:2479.8-2479.77" + attribute \src "ls180.v:2470.4-2472.7" + switch $and$ls180.v:2470$212_Y + attribute \src "ls180.v:2470.8-2470.77" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:2485.4-2494.7" + attribute \src "ls180.v:2476.4-2485.7" switch \sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:2485.8-2485.39" + attribute \src "ls180.v:2476.8-2476.39" case 1'1 assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 assign $0\sdram_bankmachine3_row_open[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:2490.5-2492.8" + attribute \src "ls180.v:2481.5-2483.8" switch \sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:2490.9-2490.37" + attribute \src "ls180.v:2481.9-2481.37" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'110 case @@ -263829,16 +263646,16 @@ module \ls180 case 3'100 assign $0\sdram_bankmachine3_row_close[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:2497.4-2499.7" + attribute \src "ls180.v:2488.4-2490.7" switch \sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:2497.8-2497.40" + attribute \src "ls180.v:2488.8-2488.40" case 1'1 assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:2502.4-2504.7" - switch $not$ls180.v:2502$213_Y - attribute \src "ls180.v:2502.8-2502.41" + attribute \src "ls180.v:2493.4-2495.7" + switch $not$ls180.v:2493$213_Y + attribute \src "ls180.v:2493.8-2493.41" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'000 case @@ -263851,51 +263668,51 @@ module \ls180 assign $0\subfragments_bankmachine3_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:2513.4-2539.7" + attribute \src "ls180.v:2504.4-2530.7" switch \sdram_bankmachine3_refresh_req - attribute \src "ls180.v:2513.8-2513.38" + attribute \src "ls180.v:2504.8-2504.38" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:2515.8-2515.12" + attribute \src "ls180.v:2506.8-2506.12" case - attribute \src "ls180.v:2516.5-2538.8" + attribute \src "ls180.v:2507.5-2529.8" switch \sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:2516.9-2516.51" + attribute \src "ls180.v:2507.9-2507.51" case 1'1 - attribute \src "ls180.v:2517.6-2537.9" + attribute \src "ls180.v:2508.6-2528.9" switch \sdram_bankmachine3_row_opened - attribute \src "ls180.v:2517.10-2517.39" + attribute \src "ls180.v:2508.10-2508.39" case 1'1 - attribute \src "ls180.v:2518.7-2534.10" + attribute \src "ls180.v:2509.7-2525.10" switch \sdram_bankmachine3_row_hit - attribute \src "ls180.v:2518.11-2518.37" + attribute \src "ls180.v:2509.11-2509.37" case 1'1 assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:2520.8-2527.11" + attribute \src "ls180.v:2511.8-2518.11" switch \sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:2520.12-2520.59" + attribute \src "ls180.v:2511.12-2511.59" case 1'1 assign $0\sdram_bankmachine3_req_wdata_ready[0:0] \sdram_bankmachine3_cmd_ready assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:2524.12-2524.16" + attribute \src "ls180.v:2515.12-2515.16" case assign $0\sdram_bankmachine3_req_rdata_valid[0:0] \sdram_bankmachine3_cmd_ready assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:2529.8-2531.11" - switch $and$ls180.v:2529$214_Y - attribute \src "ls180.v:2529.12-2529.78" + attribute \src "ls180.v:2520.8-2522.11" + switch $and$ls180.v:2520$214_Y + attribute \src "ls180.v:2520.12-2520.78" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'010 case end - attribute \src "ls180.v:2532.11-2532.15" + attribute \src "ls180.v:2523.11-2523.15" case assign $0\subfragments_bankmachine3_next_state[2:0] 3'001 end - attribute \src "ls180.v:2535.10-2535.14" + attribute \src "ls180.v:2526.10-2526.14" case assign $0\subfragments_bankmachine3_next_state[2:0] 3'011 end @@ -263919,32 +263736,24 @@ module \ls180 update \sdram_bankmachine3_row_col_n_addr_sel $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] update \subfragments_bankmachine3_next_state $0\subfragments_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:248.5-248.19" - process $proc$ls180.v:248$1631 - assign { } { } - assign $1\int_rst[0:0] 1'1 - sync always - sync init - update \int_rst $1\int_rst[0:0] - end - attribute \src "ls180.v:2562.1-2568.4" - process $proc$ls180.v:2562$253 + attribute \src "ls180.v:2553.1-2559.4" + process $proc$ls180.v:2553$253 assign { } { } assign { } { } - assign $0\sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:2564$266_Y - assign $0\sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:2565$279_Y - assign $0\sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:2566$292_Y - assign $0\sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:2567$305_Y + assign $0\sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:2555$266_Y + assign $0\sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:2556$279_Y + assign $0\sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:2557$292_Y + assign $0\sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:2558$305_Y sync always update \sdram_choose_cmd_valids $0\sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:2576.1-2581.4" - process $proc$ls180.v:2576$306 + attribute \src "ls180.v:2567.1-2572.4" + process $proc$ls180.v:2567$306 assign { } { } assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:2578.2-2580.5" + attribute \src "ls180.v:2569.2-2571.5" switch \sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:2578.6-2578.32" + attribute \src "ls180.v:2569.6-2569.32" case 1'1 assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] \t_array_muxed0 case @@ -263952,13 +263761,21 @@ module \ls180 sync always update \sdram_choose_cmd_cmd_payload_cas $0\sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:2582.1-2587.4" - process $proc$ls180.v:2582$307 + attribute \src "ls180.v:257.12-257.33" + process $proc$ls180.v:257$1636 + assign { } { } + assign $1\dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \dfi_p0_rddata $1\dfi_p0_rddata[15:0] + end + attribute \src "ls180.v:2573.1-2578.4" + process $proc$ls180.v:2573$307 assign { } { } assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:2584.2-2586.5" + attribute \src "ls180.v:2575.2-2577.5" switch \sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:2584.6-2584.32" + attribute \src "ls180.v:2575.6-2575.32" case 1'1 assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] \t_array_muxed1 case @@ -263966,13 +263783,13 @@ module \ls180 sync always update \sdram_choose_cmd_cmd_payload_ras $0\sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:2588.1-2593.4" - process $proc$ls180.v:2588$308 + attribute \src "ls180.v:2579.1-2584.4" + process $proc$ls180.v:2579$308 assign { } { } assign $0\sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:2590.2-2592.5" + attribute \src "ls180.v:2581.2-2583.5" switch \sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:2590.6-2590.32" + attribute \src "ls180.v:2581.6-2581.32" case 1'1 assign $0\sdram_choose_cmd_cmd_payload_we[0:0] \t_array_muxed2 case @@ -263980,24 +263797,40 @@ module \ls180 sync always update \sdram_choose_cmd_cmd_payload_we $0\sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:2595.1-2601.4" - process $proc$ls180.v:2595$311 + attribute \src "ls180.v:258.5-258.31" + process $proc$ls180.v:258$1637 assign { } { } + assign $1\dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \dfi_p0_rddata_valid $1\dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:2586.1-2592.4" + process $proc$ls180.v:2586$311 assign { } { } - assign $0\sdram_choose_req_valids[3:0] [0] $and$ls180.v:2597$324_Y - assign $0\sdram_choose_req_valids[3:0] [1] $and$ls180.v:2598$337_Y - assign $0\sdram_choose_req_valids[3:0] [2] $and$ls180.v:2599$350_Y - assign $0\sdram_choose_req_valids[3:0] [3] $and$ls180.v:2600$363_Y + assign { } { } + assign $0\sdram_choose_req_valids[3:0] [0] $and$ls180.v:2588$324_Y + assign $0\sdram_choose_req_valids[3:0] [1] $and$ls180.v:2589$337_Y + assign $0\sdram_choose_req_valids[3:0] [2] $and$ls180.v:2590$350_Y + assign $0\sdram_choose_req_valids[3:0] [3] $and$ls180.v:2591$363_Y sync always update \sdram_choose_req_valids $0\sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:2609.1-2614.4" - process $proc$ls180.v:2609$364 + attribute \src "ls180.v:259.11-259.27" + process $proc$ls180.v:259$1638 + assign { } { } + assign $1\rddata_en[2:0] 3'000 + sync always + sync init + update \rddata_en $1\rddata_en[2:0] + end + attribute \src "ls180.v:2600.1-2605.4" + process $proc$ls180.v:2600$364 assign { } { } assign $0\sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:2611.2-2613.5" + attribute \src "ls180.v:2602.2-2604.5" switch \sdram_choose_req_cmd_valid - attribute \src "ls180.v:2611.6-2611.32" + attribute \src "ls180.v:2602.6-2602.32" case 1'1 assign $0\sdram_choose_req_cmd_payload_cas[0:0] \t_array_muxed3 case @@ -264005,13 +263838,13 @@ module \ls180 sync always update \sdram_choose_req_cmd_payload_cas $0\sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:2615.1-2620.4" - process $proc$ls180.v:2615$365 + attribute \src "ls180.v:2606.1-2611.4" + process $proc$ls180.v:2606$365 assign { } { } assign $0\sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:2617.2-2619.5" + attribute \src "ls180.v:2608.2-2610.5" switch \sdram_choose_req_cmd_valid - attribute \src "ls180.v:2617.6-2617.32" + attribute \src "ls180.v:2608.6-2608.32" case 1'1 assign $0\sdram_choose_req_cmd_payload_ras[0:0] \t_array_muxed4 case @@ -264019,13 +263852,13 @@ module \ls180 sync always update \sdram_choose_req_cmd_payload_ras $0\sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:2621.1-2626.4" - process $proc$ls180.v:2621$366 + attribute \src "ls180.v:2612.1-2617.4" + process $proc$ls180.v:2612$366 assign { } { } assign $0\sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:2623.2-2625.5" + attribute \src "ls180.v:2614.2-2616.5" switch \sdram_choose_req_cmd_valid - attribute \src "ls180.v:2623.6-2623.32" + attribute \src "ls180.v:2614.6-2614.32" case 1'1 assign $0\sdram_choose_req_cmd_payload_we[0:0] \t_array_muxed5 case @@ -264033,20 +263866,20 @@ module \ls180 sync always update \sdram_choose_req_cmd_payload_we $0\sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:2627.1-2635.4" - process $proc$ls180.v:2627$367 + attribute \src "ls180.v:2618.1-2626.4" + process $proc$ls180.v:2618$367 assign { } { } assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:2629.2-2631.5" - switch $and$ls180.v:2629$370_Y - attribute \src "ls180.v:2629.6-2629.100" + attribute \src "ls180.v:2620.2-2622.5" + switch $and$ls180.v:2620$370_Y + attribute \src "ls180.v:2620.6-2620.100" case 1'1 assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:2632.2-2634.5" - switch $and$ls180.v:2632$373_Y - attribute \src "ls180.v:2632.6-2632.100" + attribute \src "ls180.v:2623.2-2625.5" + switch $and$ls180.v:2623$373_Y + attribute \src "ls180.v:2623.6-2623.100" case 1'1 assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1 case @@ -264054,28 +263887,28 @@ module \ls180 sync always update \sdram_bankmachine0_cmd_ready $0\sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:263.12-263.33" - process $proc$ls180.v:263$1632 + attribute \src "ls180.v:262.5-262.31" + process $proc$ls180.v:262$1639 assign { } { } - assign $1\dfi_p0_rddata[15:0] 16'0000000000000000 + assign $1\sdram_inti_p0_cas_n[0:0] 1'1 sync always sync init - update \dfi_p0_rddata $1\dfi_p0_rddata[15:0] + update \sdram_inti_p0_cas_n $1\sdram_inti_p0_cas_n[0:0] end - attribute \src "ls180.v:2636.1-2644.4" - process $proc$ls180.v:2636$374 + attribute \src "ls180.v:2627.1-2635.4" + process $proc$ls180.v:2627$374 assign { } { } assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:2638.2-2640.5" - switch $and$ls180.v:2638$377_Y - attribute \src "ls180.v:2638.6-2638.100" + attribute \src "ls180.v:2629.2-2631.5" + switch $and$ls180.v:2629$377_Y + attribute \src "ls180.v:2629.6-2629.100" case 1'1 assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:2641.2-2643.5" - switch $and$ls180.v:2641$380_Y - attribute \src "ls180.v:2641.6-2641.100" + attribute \src "ls180.v:2632.2-2634.5" + switch $and$ls180.v:2632$380_Y + attribute \src "ls180.v:2632.6-2632.100" case 1'1 assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1 case @@ -264083,28 +263916,28 @@ module \ls180 sync always update \sdram_bankmachine1_cmd_ready $0\sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:264.5-264.31" - process $proc$ls180.v:264$1633 + attribute \src "ls180.v:263.5-263.30" + process $proc$ls180.v:263$1640 assign { } { } - assign $1\dfi_p0_rddata_valid[0:0] 1'0 + assign $1\sdram_inti_p0_cs_n[0:0] 1'1 sync always sync init - update \dfi_p0_rddata_valid $1\dfi_p0_rddata_valid[0:0] + update \sdram_inti_p0_cs_n $1\sdram_inti_p0_cs_n[0:0] end - attribute \src "ls180.v:2645.1-2653.4" - process $proc$ls180.v:2645$381 + attribute \src "ls180.v:2636.1-2644.4" + process $proc$ls180.v:2636$381 assign { } { } assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:2647.2-2649.5" - switch $and$ls180.v:2647$384_Y - attribute \src "ls180.v:2647.6-2647.100" + attribute \src "ls180.v:2638.2-2640.5" + switch $and$ls180.v:2638$384_Y + attribute \src "ls180.v:2638.6-2638.100" case 1'1 assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:2650.2-2652.5" - switch $and$ls180.v:2650$387_Y - attribute \src "ls180.v:2650.6-2650.100" + attribute \src "ls180.v:2641.2-2643.5" + switch $and$ls180.v:2641$387_Y + attribute \src "ls180.v:2641.6-2641.100" case 1'1 assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1 case @@ -264112,28 +263945,28 @@ module \ls180 sync always update \sdram_bankmachine2_cmd_ready $0\sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:265.11-265.27" - process $proc$ls180.v:265$1634 + attribute \src "ls180.v:264.5-264.31" + process $proc$ls180.v:264$1641 assign { } { } - assign $1\rddata_en[2:0] 3'000 + assign $1\sdram_inti_p0_ras_n[0:0] 1'1 sync always sync init - update \rddata_en $1\rddata_en[2:0] + update \sdram_inti_p0_ras_n $1\sdram_inti_p0_ras_n[0:0] end - attribute \src "ls180.v:2654.1-2662.4" - process $proc$ls180.v:2654$388 + attribute \src "ls180.v:2645.1-2653.4" + process $proc$ls180.v:2645$388 assign { } { } assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:2656.2-2658.5" - switch $and$ls180.v:2656$391_Y - attribute \src "ls180.v:2656.6-2656.100" + attribute \src "ls180.v:2647.2-2649.5" + switch $and$ls180.v:2647$391_Y + attribute \src "ls180.v:2647.6-2647.100" case 1'1 assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:2659.2-2661.5" - switch $and$ls180.v:2659$394_Y - attribute \src "ls180.v:2659.6-2659.100" + attribute \src "ls180.v:2650.2-2652.5" + switch $and$ls180.v:2650$394_Y + attribute \src "ls180.v:2650.6-2650.100" case 1'1 assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1 case @@ -264141,8 +263974,16 @@ module \ls180 sync always update \sdram_bankmachine3_cmd_ready $0\sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:2667.1-2739.4" - process $proc$ls180.v:2667$397 + attribute \src "ls180.v:265.5-265.30" + process $proc$ls180.v:265$1642 + assign { } { } + assign $1\sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \sdram_inti_p0_we_n $1\sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:2658.1-2730.4" + process $proc$ls180.v:2658$397 assign { } { } assign { } { } assign { } { } @@ -264152,47 +263993,47 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\sdram_en1[0:0] 1'0 - assign $0\sdram_choose_req_want_reads[0:0] 1'0 - assign $0\sdram_choose_req_want_writes[0:0] 1'0 assign $0\sdram_cmd_ready[0:0] 1'0 assign { } { } assign $0\sdram_choose_req_cmd_ready[0:0] 1'0 assign $0\sdram_steerer_sel[1:0] 2'00 - assign { } { } assign $0\sdram_en0[0:0] 1'0 + assign { } { } + assign $0\sdram_en1[0:0] 1'0 + assign $0\sdram_choose_req_want_reads[0:0] 1'0 + assign $0\sdram_choose_req_want_writes[0:0] 1'0 assign $0\sdram_choose_req_want_activates[0:0] \sdram_ras_allowed assign $0\subfragments_multiplexer_next_state[2:0] \subfragments_multiplexer_state - attribute \src "ls180.v:2679.2-2738.9" + attribute \src "ls180.v:2670.2-2729.9" switch \subfragments_multiplexer_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\sdram_en1[0:0] 1'1 assign $0\sdram_choose_req_want_writes[0:0] 1'1 assign $0\sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:2683.4-2689.7" + attribute \src "ls180.v:2674.4-2680.7" switch 1'1 - attribute \src "ls180.v:2683.8-2683.12" + attribute \src "ls180.v:2674.8-2674.12" case 1'1 - assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2684$404_Y + assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2675$404_Y case end - attribute \src "ls180.v:2691.4-2695.7" + attribute \src "ls180.v:2682.4-2686.7" switch \sdram_read_available - attribute \src "ls180.v:2691.8-2691.28" + attribute \src "ls180.v:2682.8-2682.28" case 1'1 - attribute \src "ls180.v:2692.5-2694.8" - switch $or$ls180.v:2692$406_Y - attribute \src "ls180.v:2692.9-2692.53" + attribute \src "ls180.v:2683.5-2685.8" + switch $or$ls180.v:2683$406_Y + attribute \src "ls180.v:2683.9-2683.53" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'011 case end case end - attribute \src "ls180.v:2696.4-2698.7" + attribute \src "ls180.v:2687.4-2689.7" switch \sdram_go_to_refresh - attribute \src "ls180.v:2696.8-2696.27" + attribute \src "ls180.v:2687.8-2687.27" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'010 case @@ -264201,18 +264042,18 @@ module \ls180 case 3'010 assign $0\sdram_steerer_sel[1:0] 2'11 assign $0\sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:2703.4-2705.7" + attribute \src "ls180.v:2694.4-2696.7" switch \sdram_cmd_last - attribute \src "ls180.v:2703.8-2703.22" + attribute \src "ls180.v:2694.8-2694.22" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:2708.4-2710.7" + attribute \src "ls180.v:2699.4-2701.7" switch \sdram_twtrcon_ready - attribute \src "ls180.v:2708.8-2708.27" + attribute \src "ls180.v:2699.8-2699.27" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'000 case @@ -264228,29 +264069,29 @@ module \ls180 assign $0\sdram_en0[0:0] 1'1 assign $0\sdram_choose_req_want_reads[0:0] 1'1 assign $0\sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:2721.4-2727.7" + attribute \src "ls180.v:2712.4-2718.7" switch 1'1 - attribute \src "ls180.v:2721.8-2721.12" + attribute \src "ls180.v:2712.8-2712.12" case 1'1 - assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2722$413_Y + assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2713$413_Y case end - attribute \src "ls180.v:2729.4-2733.7" + attribute \src "ls180.v:2720.4-2724.7" switch \sdram_write_available - attribute \src "ls180.v:2729.8-2729.29" + attribute \src "ls180.v:2720.8-2720.29" case 1'1 - attribute \src "ls180.v:2730.5-2732.8" - switch $or$ls180.v:2730$415_Y - attribute \src "ls180.v:2730.9-2730.52" + attribute \src "ls180.v:2721.5-2723.8" + switch $or$ls180.v:2721$415_Y + attribute \src "ls180.v:2721.9-2721.52" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'100 case end case end - attribute \src "ls180.v:2734.4-2736.7" + attribute \src "ls180.v:2725.4-2727.7" switch \sdram_go_to_refresh - attribute \src "ls180.v:2734.8-2734.27" + attribute \src "ls180.v:2725.8-2725.27" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'010 case @@ -264267,53 +264108,37 @@ module \ls180 update \sdram_en1 $0\sdram_en1[0:0] update \subfragments_multiplexer_next_state $0\subfragments_multiplexer_next_state[2:0] end - attribute \src "ls180.v:268.5-268.31" - process $proc$ls180.v:268$1635 + attribute \src "ls180.v:269.5-269.31" + process $proc$ls180.v:269$1643 assign { } { } - assign $1\sdram_inti_p0_cas_n[0:0] 1'1 - sync always - sync init - update \sdram_inti_p0_cas_n $1\sdram_inti_p0_cas_n[0:0] - end - attribute \src "ls180.v:269.5-269.30" - process $proc$ls180.v:269$1636 - assign { } { } - assign $1\sdram_inti_p0_cs_n[0:0] 1'1 - sync always - sync init - update \sdram_inti_p0_cs_n $1\sdram_inti_p0_cs_n[0:0] - end - attribute \src "ls180.v:270.5-270.31" - process $proc$ls180.v:270$1637 - assign { } { } - assign $1\sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\sdram_inti_p0_act_n[0:0] 1'1 sync always + update \sdram_inti_p0_act_n $0\sdram_inti_p0_act_n[0:0] sync init - update \sdram_inti_p0_ras_n $1\sdram_inti_p0_ras_n[0:0] end - attribute \src "ls180.v:271.5-271.30" - process $proc$ls180.v:271$1638 + attribute \src "ls180.v:274.12-274.40" + process $proc$ls180.v:274$1644 assign { } { } - assign $1\sdram_inti_p0_we_n[0:0] 1'1 + assign $1\sdram_inti_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \sdram_inti_p0_we_n $1\sdram_inti_p0_we_n[0:0] + update \sdram_inti_p0_rddata $1\sdram_inti_p0_rddata[15:0] end - attribute \src "ls180.v:275.5-275.31" - process $proc$ls180.v:275$1639 + attribute \src "ls180.v:275.5-275.38" + process $proc$ls180.v:275$1645 assign { } { } - assign $0\sdram_inti_p0_act_n[0:0] 1'1 + assign $1\sdram_inti_p0_rddata_valid[0:0] 1'0 sync always - update \sdram_inti_p0_act_n $0\sdram_inti_p0_act_n[0:0] sync init + update \sdram_inti_p0_rddata_valid $1\sdram_inti_p0_rddata_valid[0:0] end - attribute \src "ls180.v:2763.1-2776.4" - process $proc$ls180.v:2763$544 + attribute \src "ls180.v:2754.1-2767.4" + process $proc$ls180.v:2754$544 assign { } { } assign { } { } - assign $0\sdram_interface_wdata_we[1:0] 2'00 assign $0\sdram_interface_wdata[15:0] 16'0000000000000000 - attribute \src "ls180.v:2766.2-2775.9" + assign $0\sdram_interface_wdata_we[1:0] 2'00 + attribute \src "ls180.v:2757.2-2766.9" switch \subfragments_new_master_wdata_ready attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -264328,11 +264153,11 @@ module \ls180 update \sdram_interface_wdata $0\sdram_interface_wdata[15:0] update \sdram_interface_wdata_we $0\sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:2783.1-2793.4" - process $proc$ls180.v:2783$546 + attribute \src "ls180.v:2774.1-2784.4" + process $proc$ls180.v:2774$546 assign { } { } assign $0\litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:2785.2-2792.9" + attribute \src "ls180.v:2776.2-2783.9" switch \converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -264345,8 +264170,8 @@ module \ls180 sync always update \litedram_wb_dat_w $0\litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:2795.1-2841.4" - process $proc$ls180.v:2795$547 + attribute \src "ls180.v:2786.1-2832.4" + process $proc$ls180.v:2786$547 assign { } { } assign { } { } assign { } { } @@ -264357,23 +264182,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\converter_counter_subfragments_next_value[0:0] 1'0 + assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'0 + assign $0\litedram_wb_we[0:0] 1'0 + assign $0\converter_skip[0:0] 1'0 + assign $0\wb_sdram_ack[0:0] 1'0 assign $0\litedram_wb_adr[29:0] 30'000000000000000000000000000000 assign $0\litedram_wb_sel[1:0] 2'00 assign $0\litedram_wb_cyc[0:0] 1'0 - assign $0\litedram_wb_stb[0:0] 1'0 - assign $0\litedram_wb_we[0:0] 1'0 - assign $0\wb_sdram_ack[0:0] 1'0 - assign $0\converter_skip[0:0] 1'0 assign { } { } - assign $0\converter_counter_subfragments_next_value[0:0] 1'0 - assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'0 + assign $0\litedram_wb_stb[0:0] 1'0 assign $0\subfragments_next_state[0:0] \subfragments_state - attribute \src "ls180.v:2807.2-2840.9" + attribute \src "ls180.v:2798.2-2831.9" switch \subfragments_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\litedram_wb_adr[29:0] { \wb_sdram_adr [28:0] \converter_counter } - attribute \src "ls180.v:2810.4-2817.11" + attribute \src "ls180.v:2801.4-2808.11" switch \converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -264383,23 +264208,23 @@ module \ls180 assign $0\litedram_wb_sel[1:0] \wb_sdram_sel [3:2] case end - attribute \src "ls180.v:2818.4-2831.7" - switch $and$ls180.v:2818$548_Y - attribute \src "ls180.v:2818.8-2818.37" + attribute \src "ls180.v:2809.4-2822.7" + switch $and$ls180.v:2809$548_Y + attribute \src "ls180.v:2809.8-2809.37" case 1'1 - assign $0\converter_skip[0:0] $eq$ls180.v:2819$549_Y + assign $0\converter_skip[0:0] $eq$ls180.v:2810$549_Y assign $0\litedram_wb_we[0:0] \wb_sdram_we - assign $0\litedram_wb_cyc[0:0] $not$ls180.v:2821$550_Y - assign $0\litedram_wb_stb[0:0] $not$ls180.v:2822$551_Y - attribute \src "ls180.v:2823.5-2830.8" - switch $or$ls180.v:2823$552_Y - attribute \src "ls180.v:2823.9-2823.43" + assign $0\litedram_wb_cyc[0:0] $not$ls180.v:2812$550_Y + assign $0\litedram_wb_stb[0:0] $not$ls180.v:2813$551_Y + attribute \src "ls180.v:2814.5-2821.8" + switch $or$ls180.v:2814$552_Y + attribute \src "ls180.v:2814.9-2814.43" case 1'1 - assign $0\converter_counter_subfragments_next_value[0:0] $add$ls180.v:2824$553_Y + assign $0\converter_counter_subfragments_next_value[0:0] $add$ls180.v:2815$553_Y assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2826.6-2829.9" - switch $eq$ls180.v:2826$554_Y - attribute \src "ls180.v:2826.10-2826.37" + attribute \src "ls180.v:2817.6-2820.9" + switch $eq$ls180.v:2817$554_Y + attribute \src "ls180.v:2817.10-2817.37" case 1'1 assign $0\wb_sdram_ack[0:0] 1'1 assign $0\subfragments_next_state[0:0] 1'0 @@ -264413,9 +264238,9 @@ module \ls180 case assign $0\converter_counter_subfragments_next_value[0:0] 1'0 assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2836.4-2838.7" - switch $and$ls180.v:2836$555_Y - attribute \src "ls180.v:2836.8-2836.37" + attribute \src "ls180.v:2827.4-2829.7" + switch $and$ls180.v:2827$555_Y + attribute \src "ls180.v:2827.8-2827.37" case 1'1 assign $0\subfragments_next_state[0:0] 1'1 case @@ -264433,29 +264258,13 @@ module \ls180 update \converter_counter_subfragments_next_value $0\converter_counter_subfragments_next_value[0:0] update \converter_counter_subfragments_next_value_ce $0\converter_counter_subfragments_next_value_ce[0:0] end - attribute \src "ls180.v:280.12-280.40" - process $proc$ls180.v:280$1640 - assign { } { } - assign $1\sdram_inti_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \sdram_inti_p0_rddata $1\sdram_inti_p0_rddata[15:0] - end - attribute \src "ls180.v:281.5-281.38" - process $proc$ls180.v:281$1641 - assign { } { } - assign $1\sdram_inti_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \sdram_inti_p0_rddata_valid $1\sdram_inti_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:2886.1-2891.4" - process $proc$ls180.v:2886$587 + attribute \src "ls180.v:2877.1-2882.4" + process $proc$ls180.v:2877$587 assign { } { } assign $0\tx_clear[0:0] 1'0 - attribute \src "ls180.v:2888.2-2890.5" - switch $and$ls180.v:2888$588_Y - attribute \src "ls180.v:2888.6-2888.59" + attribute \src "ls180.v:2879.2-2881.5" + switch $and$ls180.v:2879$588_Y + attribute \src "ls180.v:2879.6-2879.59" case 1'1 assign $0\tx_clear[0:0] 1'1 case @@ -264463,8 +264272,8 @@ module \ls180 sync always update \tx_clear $0\tx_clear[0:0] end - attribute \src "ls180.v:2892.1-2896.4" - process $proc$ls180.v:2892$589 + attribute \src "ls180.v:2883.1-2887.4" + process $proc$ls180.v:2883$589 assign { } { } assign { } { } assign $0\eventmanager_status_w[1:0] [0] \tx_status @@ -264472,13 +264281,13 @@ module \ls180 sync always update \eventmanager_status_w $0\eventmanager_status_w[1:0] end - attribute \src "ls180.v:2897.1-2902.4" - process $proc$ls180.v:2897$590 + attribute \src "ls180.v:2888.1-2893.4" + process $proc$ls180.v:2888$590 assign { } { } assign $0\rx_clear[0:0] 1'0 - attribute \src "ls180.v:2899.2-2901.5" - switch $and$ls180.v:2899$591_Y - attribute \src "ls180.v:2899.6-2899.59" + attribute \src "ls180.v:2890.2-2892.5" + switch $and$ls180.v:2890$591_Y + attribute \src "ls180.v:2890.6-2890.59" case 1'1 assign $0\rx_clear[0:0] 1'1 case @@ -264486,8 +264295,8 @@ module \ls180 sync always update \rx_clear $0\rx_clear[0:0] end - attribute \src "ls180.v:2903.1-2907.4" - process $proc$ls180.v:2903$592 + attribute \src "ls180.v:2894.1-2898.4" + process $proc$ls180.v:2894$592 assign { } { } assign { } { } assign $0\eventmanager_pending_w[1:0] [0] \tx_pending @@ -264495,56 +264304,96 @@ module \ls180 sync always update \eventmanager_pending_w $0\eventmanager_pending_w[1:0] end - attribute \src "ls180.v:2925.1-2932.4" - process $proc$ls180.v:2925$600 + attribute \src "ls180.v:290.12-290.41" + process $proc$ls180.v:290$1646 + assign { } { } + assign $1\sdram_slave_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \sdram_slave_p0_rddata $1\sdram_slave_p0_rddata[15:0] + end + attribute \src "ls180.v:291.5-291.39" + process $proc$ls180.v:291$1647 + assign { } { } + assign $1\sdram_slave_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \sdram_slave_p0_rddata_valid $1\sdram_slave_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:2916.1-2923.4" + process $proc$ls180.v:2916$600 assign { } { } assign $0\tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:2927.2-2931.5" + attribute \src "ls180.v:2918.2-2922.5" switch \tx_fifo_replace - attribute \src "ls180.v:2927.6-2927.21" + attribute \src "ls180.v:2918.6-2918.21" case 1'1 - assign $0\tx_fifo_wrport_adr[3:0] $sub$ls180.v:2928$601_Y - attribute \src "ls180.v:2929.6-2929.10" + assign $0\tx_fifo_wrport_adr[3:0] $sub$ls180.v:2919$601_Y + attribute \src "ls180.v:2920.6-2920.10" case assign $0\tx_fifo_wrport_adr[3:0] \tx_fifo_produce end sync always update \tx_fifo_wrport_adr $0\tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:2955.1-2962.4" - process $proc$ls180.v:2955$611 + attribute \src "ls180.v:292.12-292.43" + process $proc$ls180.v:292$1648 + assign { } { } + assign $1\sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \sdram_master_p0_address $1\sdram_master_p0_address[12:0] + end + attribute \src "ls180.v:293.11-293.38" + process $proc$ls180.v:293$1649 + assign { } { } + assign $1\sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \sdram_master_p0_bank $1\sdram_master_p0_bank[1:0] + end + attribute \src "ls180.v:294.5-294.33" + process $proc$ls180.v:294$1650 + assign { } { } + assign $1\sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \sdram_master_p0_cas_n $1\sdram_master_p0_cas_n[0:0] + end + attribute \src "ls180.v:2946.1-2953.4" + process $proc$ls180.v:2946$611 assign { } { } assign $0\rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:2957.2-2961.5" + attribute \src "ls180.v:2948.2-2952.5" switch \rx_fifo_replace - attribute \src "ls180.v:2957.6-2957.21" + attribute \src "ls180.v:2948.6-2948.21" case 1'1 - assign $0\rx_fifo_wrport_adr[3:0] $sub$ls180.v:2958$612_Y - attribute \src "ls180.v:2959.6-2959.10" + assign $0\rx_fifo_wrport_adr[3:0] $sub$ls180.v:2949$612_Y + attribute \src "ls180.v:2950.6-2950.10" case assign $0\rx_fifo_wrport_adr[3:0] \rx_fifo_produce end sync always update \rx_fifo_wrport_adr $0\rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:296.12-296.41" - process $proc$ls180.v:296$1642 + attribute \src "ls180.v:295.5-295.32" + process $proc$ls180.v:295$1651 assign { } { } - assign $1\sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $1\sdram_master_p0_cs_n[0:0] 1'1 sync always sync init - update \sdram_slave_p0_rddata $1\sdram_slave_p0_rddata[15:0] + update \sdram_master_p0_cs_n $1\sdram_master_p0_cs_n[0:0] end - attribute \src "ls180.v:297.5-297.39" - process $proc$ls180.v:297$1643 + attribute \src "ls180.v:296.5-296.33" + process $proc$ls180.v:296$1652 assign { } { } - assign $1\sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $1\sdram_master_p0_ras_n[0:0] 1'1 sync always sync init - update \sdram_slave_p0_rddata_valid $1\sdram_slave_p0_rddata_valid[0:0] + update \sdram_master_p0_ras_n $1\sdram_master_p0_ras_n[0:0] end - attribute \src "ls180.v:2971.1-2981.4" - process $proc$ls180.v:2971$618 + attribute \src "ls180.v:2962.1-2972.4" + process $proc$ls180.v:2962$618 assign { } { } assign { } { } assign $0\gpio0_pads_gpio0i[7:0] [0] \libresocsim_libresoc_constraintmanager_gpio_i [0] @@ -264558,16 +264407,16 @@ module \ls180 sync always update \gpio0_pads_gpio0i $0\gpio0_pads_gpio0i[7:0] end - attribute \src "ls180.v:298.12-298.43" - process $proc$ls180.v:298$1644 + attribute \src "ls180.v:297.5-297.32" + process $proc$ls180.v:297$1653 assign { } { } - assign $1\sdram_master_p0_address[12:0] 13'0000000000000 + assign $1\sdram_master_p0_we_n[0:0] 1'1 sync always sync init - update \sdram_master_p0_address $1\sdram_master_p0_address[12:0] + update \sdram_master_p0_we_n $1\sdram_master_p0_we_n[0:0] end - attribute \src "ls180.v:2982.1-2992.4" - process $proc$ls180.v:2982$619 + attribute \src "ls180.v:2973.1-2983.4" + process $proc$ls180.v:2973$619 assign { } { } assign { } { } assign $0\gpio1_pads_gpio1i[7:0] [0] \libresocsim_libresoc_constraintmanager_gpio_i [8] @@ -264581,16 +264430,16 @@ module \ls180 sync always update \gpio1_pads_gpio1i $0\gpio1_pads_gpio1i[7:0] end - attribute \src "ls180.v:299.11-299.38" - process $proc$ls180.v:299$1645 + attribute \src "ls180.v:298.5-298.31" + process $proc$ls180.v:298$1654 assign { } { } - assign $1\sdram_master_p0_bank[1:0] 2'00 + assign $1\sdram_master_p0_cke[0:0] 1'0 sync always sync init - update \sdram_master_p0_bank $1\sdram_master_p0_bank[1:0] + update \sdram_master_p0_cke $1\sdram_master_p0_cke[0:0] end - attribute \src "ls180.v:2993.1-3011.4" - process $proc$ls180.v:2993$620 + attribute \src "ls180.v:2984.1-3002.4" + process $proc$ls180.v:2984$620 assign { } { } assign { } { } assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [0] \gpio0_pads_gpio0o [0] @@ -264612,24 +264461,24 @@ module \ls180 sync always update \libresocsim_libresoc_constraintmanager_gpio_o $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] end - attribute \src "ls180.v:300.5-300.33" - process $proc$ls180.v:300$1646 + attribute \src "ls180.v:299.5-299.31" + process $proc$ls180.v:299$1655 assign { } { } - assign $1\sdram_master_p0_cas_n[0:0] 1'1 + assign $1\sdram_master_p0_odt[0:0] 1'0 sync always sync init - update \sdram_master_p0_cas_n $1\sdram_master_p0_cas_n[0:0] + update \sdram_master_p0_odt $1\sdram_master_p0_odt[0:0] end - attribute \src "ls180.v:301.5-301.32" - process $proc$ls180.v:301$1647 + attribute \src "ls180.v:300.5-300.35" + process $proc$ls180.v:300$1656 assign { } { } - assign $1\sdram_master_p0_cs_n[0:0] 1'1 + assign $1\sdram_master_p0_reset_n[0:0] 1'0 sync always sync init - update \sdram_master_p0_cs_n $1\sdram_master_p0_cs_n[0:0] + update \sdram_master_p0_reset_n $1\sdram_master_p0_reset_n[0:0] end - attribute \src "ls180.v:3012.1-3030.4" - process $proc$ls180.v:3012$621 + attribute \src "ls180.v:3003.1-3021.4" + process $proc$ls180.v:3003$621 assign { } { } assign { } { } assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [0] \gpio0_pads_gpio0oe [0] @@ -264651,24 +264500,24 @@ module \ls180 sync always update \libresocsim_libresoc_constraintmanager_gpio_oe $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] end - attribute \src "ls180.v:302.5-302.33" - process $proc$ls180.v:302$1648 + attribute \src "ls180.v:301.5-301.33" + process $proc$ls180.v:301$1657 assign { } { } - assign $1\sdram_master_p0_ras_n[0:0] 1'1 + assign $1\sdram_master_p0_act_n[0:0] 1'1 sync always sync init - update \sdram_master_p0_ras_n $1\sdram_master_p0_ras_n[0:0] + update \sdram_master_p0_act_n $1\sdram_master_p0_act_n[0:0] end - attribute \src "ls180.v:303.5-303.32" - process $proc$ls180.v:303$1649 + attribute \src "ls180.v:302.12-302.42" + process $proc$ls180.v:302$1658 assign { } { } - assign $1\sdram_master_p0_we_n[0:0] 1'1 + assign $1\sdram_master_p0_wrdata[15:0] 16'0000000000000000 sync always sync init - update \sdram_master_p0_we_n $1\sdram_master_p0_we_n[0:0] + update \sdram_master_p0_wrdata $1\sdram_master_p0_wrdata[15:0] end - attribute \src "ls180.v:3035.1-3071.4" - process $proc$ls180.v:3035$622 + attribute \src "ls180.v:3026.1-3062.4" + process $proc$ls180.v:3026$622 assign { } { } assign { } { } assign { } { } @@ -264678,6 +264527,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0 assign $0\libresocsim_libresocsim_wishbone_dat_r[31:0] 0 assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0 assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0 @@ -264685,10 +264536,8 @@ module \ls180 assign { } { } assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] 8'00000000 assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'0 - assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 - assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0 assign $0\libresocsim_next_state[1:0] \libresocsim_state - attribute \src "ls180.v:3046.2-3070.9" + attribute \src "ls180.v:3037.2-3061.9" switch \libresocsim_state attribute \src "ls180.v:0.0-0.0" case 2'01 @@ -264706,13 +264555,13 @@ module \ls180 case assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] \libresocsim_libresocsim_wishbone_dat_w [7:0] assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:3062.4-3068.7" - switch $and$ls180.v:3062$623_Y - attribute \src "ls180.v:3062.8-3062.85" + attribute \src "ls180.v:3053.4-3059.7" + switch $and$ls180.v:3053$623_Y + attribute \src "ls180.v:3053.8-3053.85" case 1'1 assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] \libresocsim_libresocsim_wishbone_adr [13:0] assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'1 - assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] $and$ls180.v:3065$625_Y + assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] $and$ls180.v:3056$625_Y assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'1 assign $0\libresocsim_next_state[1:0] 2'01 case @@ -264729,96 +264578,80 @@ module \ls180 update \libresocsim_libresocsim_we_libresocsim_next_value2 $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] end - attribute \src "ls180.v:304.5-304.31" - process $proc$ls180.v:304$1650 + attribute \src "ls180.v:303.5-303.37" + process $proc$ls180.v:303$1659 assign { } { } - assign $1\sdram_master_p0_cke[0:0] 1'0 + assign $1\sdram_master_p0_wrdata_en[0:0] 1'0 sync always sync init - update \sdram_master_p0_cke $1\sdram_master_p0_cke[0:0] + update \sdram_master_p0_wrdata_en $1\sdram_master_p0_wrdata_en[0:0] end - attribute \src "ls180.v:305.5-305.31" - process $proc$ls180.v:305$1651 + attribute \src "ls180.v:304.11-304.45" + process $proc$ls180.v:304$1660 assign { } { } - assign $1\sdram_master_p0_odt[0:0] 1'0 + assign $1\sdram_master_p0_wrdata_mask[1:0] 2'00 sync always sync init - update \sdram_master_p0_odt $1\sdram_master_p0_odt[0:0] + update \sdram_master_p0_wrdata_mask $1\sdram_master_p0_wrdata_mask[1:0] end - attribute \src "ls180.v:306.5-306.35" - process $proc$ls180.v:306$1652 + attribute \src "ls180.v:305.5-305.37" + process $proc$ls180.v:305$1661 assign { } { } - assign $1\sdram_master_p0_reset_n[0:0] 1'0 + assign $1\sdram_master_p0_rddata_en[0:0] 1'0 sync always sync init - update \sdram_master_p0_reset_n $1\sdram_master_p0_reset_n[0:0] + update \sdram_master_p0_rddata_en $1\sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:307.5-307.33" - process $proc$ls180.v:307$1653 + attribute \src "ls180.v:3081.1-3089.4" + process $proc$ls180.v:3081$638 assign { } { } - assign $1\sdram_master_p0_act_n[0:0] 1'1 - sync always - sync init - update \sdram_master_p0_act_n $1\sdram_master_p0_act_n[0:0] - end - attribute \src "ls180.v:308.12-308.42" - process $proc$ls180.v:308$1654 assign { } { } - assign $1\sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\libresocsim_slave_sel[5:0] [0] $eq$ls180.v:3083$639_Y + assign $0\libresocsim_slave_sel[5:0] [1] $eq$ls180.v:3084$640_Y + assign $0\libresocsim_slave_sel[5:0] [2] $eq$ls180.v:3085$641_Y + assign $0\libresocsim_slave_sel[5:0] [3] $eq$ls180.v:3086$642_Y + assign $0\libresocsim_slave_sel[5:0] [4] $eq$ls180.v:3087$643_Y + assign $0\libresocsim_slave_sel[5:0] [5] $eq$ls180.v:3088$644_Y sync always - sync init - update \sdram_master_p0_wrdata $1\sdram_master_p0_wrdata[15:0] + update \libresocsim_slave_sel $0\libresocsim_slave_sel[5:0] end - attribute \src "ls180.v:309.5-309.37" - process $proc$ls180.v:309$1655 + attribute \src "ls180.v:312.11-312.31" + process $proc$ls180.v:312$1662 assign { } { } - assign $1\sdram_master_p0_wrdata_en[0:0] 1'0 + assign $1\sdram_storage[3:0] 4'0001 sync always sync init - update \sdram_master_p0_wrdata_en $1\sdram_master_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:3090.1-3098.4" - process $proc$ls180.v:3090$638 - assign { } { } - assign { } { } - assign $0\libresocsim_slave_sel[5:0] [0] $eq$ls180.v:3092$639_Y - assign $0\libresocsim_slave_sel[5:0] [1] $eq$ls180.v:3093$640_Y - assign $0\libresocsim_slave_sel[5:0] [2] $eq$ls180.v:3094$641_Y - assign $0\libresocsim_slave_sel[5:0] [3] $eq$ls180.v:3095$642_Y - assign $0\libresocsim_slave_sel[5:0] [4] $eq$ls180.v:3096$643_Y - assign $0\libresocsim_slave_sel[5:0] [5] $eq$ls180.v:3097$644_Y - sync always - update \libresocsim_slave_sel $0\libresocsim_slave_sel[5:0] + update \sdram_storage $1\sdram_storage[3:0] end - attribute \src "ls180.v:310.11-310.45" - process $proc$ls180.v:310$1656 + attribute \src "ls180.v:313.5-313.20" + process $proc$ls180.v:313$1663 assign { } { } - assign $1\sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $1\sdram_re[0:0] 1'0 sync always sync init - update \sdram_master_p0_wrdata_mask $1\sdram_master_p0_wrdata_mask[1:0] + update \sdram_re $1\sdram_re[0:0] end - attribute \src "ls180.v:311.5-311.37" - process $proc$ls180.v:311$1657 + attribute \src "ls180.v:314.11-314.39" + process $proc$ls180.v:314$1664 assign { } { } - assign $1\sdram_master_p0_rddata_en[0:0] 1'0 + assign $1\sdram_command_storage[5:0] 6'000000 sync always sync init - update \sdram_master_p0_rddata_en $1\sdram_master_p0_rddata_en[0:0] + update \sdram_command_storage $1\sdram_command_storage[5:0] end - attribute \src "ls180.v:3149.1-3160.4" - process $proc$ls180.v:3149$659 + attribute \src "ls180.v:3140.1-3151.4" + process $proc$ls180.v:3140$659 assign { } { } assign { } { } assign { } { } - assign $0\libresocsim_error[0:0] 1'0 assign { } { } + assign $0\libresocsim_error[0:0] 1'0 assign { } { } - assign $0\libresocsim_shared_ack[0:0] $or$ls180.v:3153$664_Y - assign $0\libresocsim_shared_dat_r[31:0] $or$ls180.v:3154$675_Y - attribute \src "ls180.v:3155.2-3159.5" + assign $0\libresocsim_shared_ack[0:0] $or$ls180.v:3144$664_Y + assign $0\libresocsim_shared_dat_r[31:0] $or$ls180.v:3145$675_Y + attribute \src "ls180.v:3146.2-3150.5" switch \libresocsim_done - attribute \src "ls180.v:3155.6-3155.22" + attribute \src "ls180.v:3146.6-3146.22" case 1'1 assign $0\libresocsim_shared_dat_r[31:0] 32'11111111111111111111111111111111 assign $0\libresocsim_shared_ack[0:0] 1'1 @@ -264830,107 +264663,83 @@ module \ls180 update \libresocsim_shared_ack $0\libresocsim_shared_ack[0:0] update \libresocsim_error $0\libresocsim_error[0:0] end - attribute \src "ls180.v:318.11-318.31" - process $proc$ls180.v:318$1658 - assign { } { } - assign $1\sdram_storage[3:0] 4'0001 - sync always - sync init - update \sdram_storage $1\sdram_storage[3:0] - end - attribute \src "ls180.v:319.5-319.20" - process $proc$ls180.v:319$1659 - assign { } { } - assign $1\sdram_re[0:0] 1'0 - sync always - sync init - update \sdram_re $1\sdram_re[0:0] - end - attribute \src "ls180.v:320.11-320.39" - process $proc$ls180.v:320$1660 - assign { } { } - assign $1\sdram_command_storage[5:0] 6'000000 - sync always - sync init - update \sdram_command_storage $1\sdram_command_storage[5:0] - end - attribute \src "ls180.v:321.5-321.28" - process $proc$ls180.v:321$1661 + attribute \src "ls180.v:315.5-315.28" + process $proc$ls180.v:315$1665 assign { } { } assign $1\sdram_command_re[0:0] 1'0 sync always sync init update \sdram_command_re $1\sdram_command_re[0:0] end - attribute \src "ls180.v:325.5-325.33" - process $proc$ls180.v:325$1662 + attribute \src "ls180.v:319.5-319.33" + process $proc$ls180.v:319$1666 assign { } { } assign $0\sdram_command_issue_w[0:0] 1'0 sync always update \sdram_command_issue_w $0\sdram_command_issue_w[0:0] sync init end - attribute \src "ls180.v:326.12-326.41" - process $proc$ls180.v:326$1663 + attribute \src "ls180.v:320.12-320.41" + process $proc$ls180.v:320$1667 assign { } { } assign $1\sdram_address_storage[12:0] 13'0000000000000 sync always sync init update \sdram_address_storage $1\sdram_address_storage[12:0] end - attribute \src "ls180.v:327.5-327.28" - process $proc$ls180.v:327$1664 + attribute \src "ls180.v:321.5-321.28" + process $proc$ls180.v:321$1668 assign { } { } assign $1\sdram_address_re[0:0] 1'0 sync always sync init update \sdram_address_re $1\sdram_address_re[0:0] end - attribute \src "ls180.v:328.11-328.40" - process $proc$ls180.v:328$1665 + attribute \src "ls180.v:322.11-322.40" + process $proc$ls180.v:322$1669 assign { } { } assign $1\sdram_baddress_storage[1:0] 2'00 sync always sync init update \sdram_baddress_storage $1\sdram_baddress_storage[1:0] end - attribute \src "ls180.v:329.5-329.29" - process $proc$ls180.v:329$1666 + attribute \src "ls180.v:323.5-323.29" + process $proc$ls180.v:323$1670 assign { } { } assign $1\sdram_baddress_re[0:0] 1'0 sync always sync init update \sdram_baddress_re $1\sdram_baddress_re[0:0] end - attribute \src "ls180.v:330.12-330.40" - process $proc$ls180.v:330$1667 + attribute \src "ls180.v:324.12-324.40" + process $proc$ls180.v:324$1671 assign { } { } assign $1\sdram_wrdata_storage[15:0] 16'0000000000000000 sync always sync init update \sdram_wrdata_storage $1\sdram_wrdata_storage[15:0] end - attribute \src "ls180.v:331.5-331.27" - process $proc$ls180.v:331$1668 + attribute \src "ls180.v:325.5-325.27" + process $proc$ls180.v:325$1672 assign { } { } assign $1\sdram_wrdata_re[0:0] 1'0 sync always sync init update \sdram_wrdata_re $1\sdram_wrdata_re[0:0] end - attribute \src "ls180.v:332.12-332.32" - process $proc$ls180.v:332$1669 + attribute \src "ls180.v:326.12-326.32" + process $proc$ls180.v:326$1673 assign { } { } assign $1\sdram_status[15:0] 16'0000000000000000 sync always sync init update \sdram_status $1\sdram_status[15:0] end - attribute \src "ls180.v:3435.1-3451.4" - process $proc$ls180.v:3435$1084 + attribute \src "ls180.v:3426.1-3442.4" + process $proc$ls180.v:3426$1084 assign { } { } assign $0\rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:3437.2-3450.9" + attribute \src "ls180.v:3428.2-3441.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -264948,11 +264757,11 @@ module \ls180 sync always update \rhs_array_muxed0 $0\rhs_array_muxed0[0:0] end - attribute \src "ls180.v:3452.1-3468.4" - process $proc$ls180.v:3452$1085 + attribute \src "ls180.v:3443.1-3459.4" + process $proc$ls180.v:3443$1085 assign { } { } assign $0\rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:3454.2-3467.9" + attribute \src "ls180.v:3445.2-3458.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -264970,11 +264779,11 @@ module \ls180 sync always update \rhs_array_muxed1 $0\rhs_array_muxed1[12:0] end - attribute \src "ls180.v:3469.1-3485.4" - process $proc$ls180.v:3469$1086 + attribute \src "ls180.v:3460.1-3476.4" + process $proc$ls180.v:3460$1086 assign { } { } assign $0\rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:3471.2-3484.9" + attribute \src "ls180.v:3462.2-3475.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -264992,11 +264801,11 @@ module \ls180 sync always update \rhs_array_muxed2 $0\rhs_array_muxed2[1:0] end - attribute \src "ls180.v:3486.1-3502.4" - process $proc$ls180.v:3486$1087 + attribute \src "ls180.v:3477.1-3493.4" + process $proc$ls180.v:3477$1087 assign { } { } assign $0\rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:3488.2-3501.9" + attribute \src "ls180.v:3479.2-3492.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265014,11 +264823,11 @@ module \ls180 sync always update \rhs_array_muxed3 $0\rhs_array_muxed3[0:0] end - attribute \src "ls180.v:3503.1-3519.4" - process $proc$ls180.v:3503$1088 + attribute \src "ls180.v:3494.1-3510.4" + process $proc$ls180.v:3494$1088 assign { } { } assign $0\rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:3505.2-3518.9" + attribute \src "ls180.v:3496.2-3509.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265036,11 +264845,11 @@ module \ls180 sync always update \rhs_array_muxed4 $0\rhs_array_muxed4[0:0] end - attribute \src "ls180.v:3520.1-3536.4" - process $proc$ls180.v:3520$1089 + attribute \src "ls180.v:3511.1-3527.4" + process $proc$ls180.v:3511$1089 assign { } { } assign $0\rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:3522.2-3535.9" + attribute \src "ls180.v:3513.2-3526.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265058,11 +264867,11 @@ module \ls180 sync always update \rhs_array_muxed5 $0\rhs_array_muxed5[0:0] end - attribute \src "ls180.v:3537.1-3553.4" - process $proc$ls180.v:3537$1090 + attribute \src "ls180.v:3528.1-3544.4" + process $proc$ls180.v:3528$1090 assign { } { } assign $0\t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:3539.2-3552.9" + attribute \src "ls180.v:3530.2-3543.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265080,11 +264889,11 @@ module \ls180 sync always update \t_array_muxed0 $0\t_array_muxed0[0:0] end - attribute \src "ls180.v:3554.1-3570.4" - process $proc$ls180.v:3554$1091 + attribute \src "ls180.v:3545.1-3561.4" + process $proc$ls180.v:3545$1091 assign { } { } assign $0\t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:3556.2-3569.9" + attribute \src "ls180.v:3547.2-3560.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265102,11 +264911,19 @@ module \ls180 sync always update \t_array_muxed1 $0\t_array_muxed1[0:0] end - attribute \src "ls180.v:3571.1-3587.4" - process $proc$ls180.v:3571$1092 + attribute \src "ls180.v:356.12-356.41" + process $proc$ls180.v:356$1674 + assign { } { } + assign $1\sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \sdram_interface_wdata $1\sdram_interface_wdata[15:0] + end + attribute \src "ls180.v:3562.1-3578.4" + process $proc$ls180.v:3562$1092 assign { } { } assign $0\t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:3573.2-3586.9" + attribute \src "ls180.v:3564.2-3577.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265124,11 +264941,19 @@ module \ls180 sync always update \t_array_muxed2 $0\t_array_muxed2[0:0] end - attribute \src "ls180.v:3588.1-3604.4" - process $proc$ls180.v:3588$1093 + attribute \src "ls180.v:357.11-357.42" + process $proc$ls180.v:357$1675 + assign { } { } + assign $1\sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \sdram_interface_wdata_we $1\sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:3579.1-3595.4" + process $proc$ls180.v:3579$1093 assign { } { } assign $0\rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:3590.2-3603.9" + attribute \src "ls180.v:3581.2-3594.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265146,11 +264971,19 @@ module \ls180 sync always update \rhs_array_muxed6 $0\rhs_array_muxed6[0:0] end - attribute \src "ls180.v:3605.1-3621.4" - process $proc$ls180.v:3605$1094 + attribute \src "ls180.v:359.12-359.40" + process $proc$ls180.v:359$1676 + assign { } { } + assign $1\sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \sdram_dfi_p0_address $1\sdram_dfi_p0_address[12:0] + end + attribute \src "ls180.v:3596.1-3612.4" + process $proc$ls180.v:3596$1094 assign { } { } assign $0\rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:3607.2-3620.9" + attribute \src "ls180.v:3598.2-3611.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265168,19 +265001,27 @@ module \ls180 sync always update \rhs_array_muxed7 $0\rhs_array_muxed7[12:0] end - attribute \src "ls180.v:362.12-362.41" - process $proc$ls180.v:362$1670 + attribute \src "ls180.v:360.11-360.35" + process $proc$ls180.v:360$1677 assign { } { } - assign $1\sdram_interface_wdata[15:0] 16'0000000000000000 + assign $1\sdram_dfi_p0_bank[1:0] 2'00 sync always sync init - update \sdram_interface_wdata $1\sdram_interface_wdata[15:0] + update \sdram_dfi_p0_bank $1\sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:361.5-361.30" + process $proc$ls180.v:361$1678 + assign { } { } + assign $1\sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \sdram_dfi_p0_cas_n $1\sdram_dfi_p0_cas_n[0:0] end - attribute \src "ls180.v:3622.1-3638.4" - process $proc$ls180.v:3622$1095 + attribute \src "ls180.v:3613.1-3629.4" + process $proc$ls180.v:3613$1095 assign { } { } assign $0\rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:3624.2-3637.9" + attribute \src "ls180.v:3615.2-3628.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265198,19 +265039,27 @@ module \ls180 sync always update \rhs_array_muxed8 $0\rhs_array_muxed8[1:0] end - attribute \src "ls180.v:363.11-363.42" - process $proc$ls180.v:363$1671 + attribute \src "ls180.v:362.5-362.29" + process $proc$ls180.v:362$1679 assign { } { } - assign $1\sdram_interface_wdata_we[1:0] 2'00 + assign $1\sdram_dfi_p0_cs_n[0:0] 1'1 sync always sync init - update \sdram_interface_wdata_we $1\sdram_interface_wdata_we[1:0] + update \sdram_dfi_p0_cs_n $1\sdram_dfi_p0_cs_n[0:0] end - attribute \src "ls180.v:3639.1-3655.4" - process $proc$ls180.v:3639$1096 + attribute \src "ls180.v:363.5-363.30" + process $proc$ls180.v:363$1680 + assign { } { } + assign $1\sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \sdram_dfi_p0_ras_n $1\sdram_dfi_p0_ras_n[0:0] + end + attribute \src "ls180.v:3630.1-3646.4" + process $proc$ls180.v:3630$1096 assign { } { } assign $0\rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:3641.2-3654.9" + attribute \src "ls180.v:3632.2-3645.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265228,19 +265077,19 @@ module \ls180 sync always update \rhs_array_muxed9 $0\rhs_array_muxed9[0:0] end - attribute \src "ls180.v:365.12-365.40" - process $proc$ls180.v:365$1672 + attribute \src "ls180.v:364.5-364.29" + process $proc$ls180.v:364$1681 assign { } { } - assign $1\sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $1\sdram_dfi_p0_we_n[0:0] 1'1 sync always sync init - update \sdram_dfi_p0_address $1\sdram_dfi_p0_address[12:0] + update \sdram_dfi_p0_we_n $1\sdram_dfi_p0_we_n[0:0] end - attribute \src "ls180.v:3656.1-3672.4" - process $proc$ls180.v:3656$1097 + attribute \src "ls180.v:3647.1-3663.4" + process $proc$ls180.v:3647$1097 assign { } { } assign $0\rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:3658.2-3671.9" + attribute \src "ls180.v:3649.2-3662.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265258,27 +265107,11 @@ module \ls180 sync always update \rhs_array_muxed10 $0\rhs_array_muxed10[0:0] end - attribute \src "ls180.v:366.11-366.35" - process $proc$ls180.v:366$1673 - assign { } { } - assign $1\sdram_dfi_p0_bank[1:0] 2'00 - sync always - sync init - update \sdram_dfi_p0_bank $1\sdram_dfi_p0_bank[1:0] - end - attribute \src "ls180.v:367.5-367.30" - process $proc$ls180.v:367$1674 - assign { } { } - assign $1\sdram_dfi_p0_cas_n[0:0] 1'1 - sync always - sync init - update \sdram_dfi_p0_cas_n $1\sdram_dfi_p0_cas_n[0:0] - end - attribute \src "ls180.v:3673.1-3689.4" - process $proc$ls180.v:3673$1098 + attribute \src "ls180.v:3664.1-3680.4" + process $proc$ls180.v:3664$1098 assign { } { } assign $0\rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:3675.2-3688.9" + attribute \src "ls180.v:3666.2-3679.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265296,27 +265129,19 @@ module \ls180 sync always update \rhs_array_muxed11 $0\rhs_array_muxed11[0:0] end - attribute \src "ls180.v:368.5-368.29" - process $proc$ls180.v:368$1675 - assign { } { } - assign $1\sdram_dfi_p0_cs_n[0:0] 1'1 - sync always - sync init - update \sdram_dfi_p0_cs_n $1\sdram_dfi_p0_cs_n[0:0] - end - attribute \src "ls180.v:369.5-369.30" - process $proc$ls180.v:369$1676 + attribute \src "ls180.v:368.5-368.30" + process $proc$ls180.v:368$1682 assign { } { } - assign $1\sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\sdram_dfi_p0_act_n[0:0] 1'1 sync always + update \sdram_dfi_p0_act_n $0\sdram_dfi_p0_act_n[0:0] sync init - update \sdram_dfi_p0_ras_n $1\sdram_dfi_p0_ras_n[0:0] end - attribute \src "ls180.v:3690.1-3706.4" - process $proc$ls180.v:3690$1099 + attribute \src "ls180.v:3681.1-3697.4" + process $proc$ls180.v:3681$1099 assign { } { } assign $0\t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:3692.2-3705.9" + attribute \src "ls180.v:3683.2-3696.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265334,19 +265159,11 @@ module \ls180 sync always update \t_array_muxed3 $0\t_array_muxed3[0:0] end - attribute \src "ls180.v:370.5-370.29" - process $proc$ls180.v:370$1677 - assign { } { } - assign $1\sdram_dfi_p0_we_n[0:0] 1'1 - sync always - sync init - update \sdram_dfi_p0_we_n $1\sdram_dfi_p0_we_n[0:0] - end - attribute \src "ls180.v:3707.1-3723.4" - process $proc$ls180.v:3707$1100 + attribute \src "ls180.v:3698.1-3714.4" + process $proc$ls180.v:3698$1100 assign { } { } assign $0\t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:3709.2-3722.9" + attribute \src "ls180.v:3700.2-3713.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265364,11 +265181,19 @@ module \ls180 sync always update \t_array_muxed4 $0\t_array_muxed4[0:0] end - attribute \src "ls180.v:3724.1-3740.4" - process $proc$ls180.v:3724$1101 + attribute \src "ls180.v:370.5-370.34" + process $proc$ls180.v:370$1683 + assign { } { } + assign $1\sdram_dfi_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \sdram_dfi_p0_wrdata_en $1\sdram_dfi_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:3715.1-3731.4" + process $proc$ls180.v:3715$1101 assign { } { } assign $0\t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:3726.2-3739.9" + attribute \src "ls180.v:3717.2-3730.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265386,19 +265211,19 @@ module \ls180 sync always update \t_array_muxed5 $0\t_array_muxed5[0:0] end - attribute \src "ls180.v:374.5-374.30" - process $proc$ls180.v:374$1678 + attribute \src "ls180.v:372.5-372.34" + process $proc$ls180.v:372$1684 assign { } { } - assign $0\sdram_dfi_p0_act_n[0:0] 1'1 + assign $1\sdram_dfi_p0_rddata_en[0:0] 1'0 sync always - update \sdram_dfi_p0_act_n $0\sdram_dfi_p0_act_n[0:0] sync init + update \sdram_dfi_p0_rddata_en $1\sdram_dfi_p0_rddata_en[0:0] end - attribute \src "ls180.v:3741.1-3748.4" - process $proc$ls180.v:3741$1102 + attribute \src "ls180.v:3732.1-3739.4" + process $proc$ls180.v:3732$1102 assign { } { } assign $0\rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:3743.2-3747.9" + attribute \src "ls180.v:3734.2-3738.9" switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -265407,11 +265232,11 @@ module \ls180 sync always update \rhs_array_muxed12 $0\rhs_array_muxed12[21:0] end - attribute \src "ls180.v:3749.1-3756.4" - process $proc$ls180.v:3749$1103 + attribute \src "ls180.v:3740.1-3747.4" + process $proc$ls180.v:3740$1103 assign { } { } assign $0\rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:3751.2-3755.9" + attribute \src "ls180.v:3742.2-3746.9" switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -265420,32 +265245,32 @@ module \ls180 sync always update \rhs_array_muxed13 $0\rhs_array_muxed13[0:0] end - attribute \src "ls180.v:3757.1-3764.4" - process $proc$ls180.v:3757$1104 + attribute \src "ls180.v:3748.1-3755.4" + process $proc$ls180.v:3748$1104 assign { } { } assign $0\rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:3759.2-3763.9" + attribute \src "ls180.v:3750.2-3754.9" switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\rhs_array_muxed14[0:0] $and$ls180.v:3761$1117_Y + assign $0\rhs_array_muxed14[0:0] $and$ls180.v:3752$1117_Y end sync always update \rhs_array_muxed14 $0\rhs_array_muxed14[0:0] end - attribute \src "ls180.v:376.5-376.34" - process $proc$ls180.v:376$1679 + attribute \src "ls180.v:375.5-375.27" + process $proc$ls180.v:375$1685 assign { } { } - assign $1\sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $1\sdram_cmd_valid[0:0] 1'0 sync always sync init - update \sdram_dfi_p0_wrdata_en $1\sdram_dfi_p0_wrdata_en[0:0] + update \sdram_cmd_valid $1\sdram_cmd_valid[0:0] end - attribute \src "ls180.v:3765.1-3772.4" - process $proc$ls180.v:3765$1118 + attribute \src "ls180.v:3756.1-3763.4" + process $proc$ls180.v:3756$1118 assign { } { } assign $0\rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:3767.2-3771.9" + attribute \src "ls180.v:3758.2-3762.9" switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -265454,11 +265279,19 @@ module \ls180 sync always update \rhs_array_muxed15 $0\rhs_array_muxed15[21:0] end - attribute \src "ls180.v:3773.1-3780.4" - process $proc$ls180.v:3773$1119 + attribute \src "ls180.v:376.5-376.27" + process $proc$ls180.v:376$1686 + assign { } { } + assign $1\sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \sdram_cmd_ready $1\sdram_cmd_ready[0:0] + end + attribute \src "ls180.v:3764.1-3771.4" + process $proc$ls180.v:3764$1119 assign { } { } assign $0\rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:3775.2-3779.9" + attribute \src "ls180.v:3766.2-3770.9" switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -265467,32 +265300,40 @@ module \ls180 sync always update \rhs_array_muxed16 $0\rhs_array_muxed16[0:0] end - attribute \src "ls180.v:378.5-378.34" - process $proc$ls180.v:378$1680 + attribute \src "ls180.v:377.5-377.26" + process $proc$ls180.v:377$1687 assign { } { } - assign $1\sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $1\sdram_cmd_last[0:0] 1'0 sync always sync init - update \sdram_dfi_p0_rddata_en $1\sdram_dfi_p0_rddata_en[0:0] + update \sdram_cmd_last $1\sdram_cmd_last[0:0] end - attribute \src "ls180.v:3781.1-3788.4" - process $proc$ls180.v:3781$1120 + attribute \src "ls180.v:3772.1-3779.4" + process $proc$ls180.v:3772$1120 assign { } { } assign $0\rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:3783.2-3787.9" + attribute \src "ls180.v:3774.2-3778.9" switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\rhs_array_muxed17[0:0] $and$ls180.v:3785$1133_Y + assign $0\rhs_array_muxed17[0:0] $and$ls180.v:3776$1133_Y end sync always update \rhs_array_muxed17 $0\rhs_array_muxed17[0:0] end - attribute \src "ls180.v:3789.1-3796.4" - process $proc$ls180.v:3789$1134 + attribute \src "ls180.v:378.12-378.39" + process $proc$ls180.v:378$1688 + assign { } { } + assign $1\sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \sdram_cmd_payload_a $1\sdram_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3780.1-3787.4" + process $proc$ls180.v:3780$1134 assign { } { } assign $0\rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:3791.2-3795.9" + attribute \src "ls180.v:3782.2-3786.9" switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -265501,11 +265342,11 @@ module \ls180 sync always update \rhs_array_muxed18 $0\rhs_array_muxed18[21:0] end - attribute \src "ls180.v:3797.1-3804.4" - process $proc$ls180.v:3797$1135 + attribute \src "ls180.v:3788.1-3795.4" + process $proc$ls180.v:3788$1135 assign { } { } assign $0\rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:3799.2-3803.9" + attribute \src "ls180.v:3790.2-3794.9" switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -265514,32 +265355,40 @@ module \ls180 sync always update \rhs_array_muxed19 $0\rhs_array_muxed19[0:0] end - attribute \src "ls180.v:3805.1-3812.4" - process $proc$ls180.v:3805$1136 + attribute \src "ls180.v:379.11-379.38" + process $proc$ls180.v:379$1689 + assign { } { } + assign $1\sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \sdram_cmd_payload_ba $1\sdram_cmd_payload_ba[1:0] + end + attribute \src "ls180.v:3796.1-3803.4" + process $proc$ls180.v:3796$1136 assign { } { } assign $0\rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:3807.2-3811.9" + attribute \src "ls180.v:3798.2-3802.9" switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\rhs_array_muxed20[0:0] $and$ls180.v:3809$1149_Y + assign $0\rhs_array_muxed20[0:0] $and$ls180.v:3800$1149_Y end sync always update \rhs_array_muxed20 $0\rhs_array_muxed20[0:0] end - attribute \src "ls180.v:381.5-381.27" - process $proc$ls180.v:381$1681 + attribute \src "ls180.v:380.5-380.33" + process $proc$ls180.v:380$1690 assign { } { } - assign $1\sdram_cmd_valid[0:0] 1'0 + assign $1\sdram_cmd_payload_cas[0:0] 1'0 sync always sync init - update \sdram_cmd_valid $1\sdram_cmd_valid[0:0] + update \sdram_cmd_payload_cas $1\sdram_cmd_payload_cas[0:0] end - attribute \src "ls180.v:3813.1-3820.4" - process $proc$ls180.v:3813$1150 + attribute \src "ls180.v:3804.1-3811.4" + process $proc$ls180.v:3804$1150 assign { } { } assign $0\rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:3815.2-3819.9" + attribute \src "ls180.v:3806.2-3810.9" switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -265548,19 +265397,19 @@ module \ls180 sync always update \rhs_array_muxed21 $0\rhs_array_muxed21[21:0] end - attribute \src "ls180.v:382.5-382.27" - process $proc$ls180.v:382$1682 + attribute \src "ls180.v:381.5-381.33" + process $proc$ls180.v:381$1691 assign { } { } - assign $1\sdram_cmd_ready[0:0] 1'0 + assign $1\sdram_cmd_payload_ras[0:0] 1'0 sync always sync init - update \sdram_cmd_ready $1\sdram_cmd_ready[0:0] + update \sdram_cmd_payload_ras $1\sdram_cmd_payload_ras[0:0] end - attribute \src "ls180.v:3821.1-3828.4" - process $proc$ls180.v:3821$1151 + attribute \src "ls180.v:3812.1-3819.4" + process $proc$ls180.v:3812$1151 assign { } { } assign $0\rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:3823.2-3827.9" + attribute \src "ls180.v:3814.2-3818.9" switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -265569,32 +265418,32 @@ module \ls180 sync always update \rhs_array_muxed22 $0\rhs_array_muxed22[0:0] end - attribute \src "ls180.v:3829.1-3836.4" - process $proc$ls180.v:3829$1152 + attribute \src "ls180.v:382.5-382.32" + process $proc$ls180.v:382$1692 + assign { } { } + assign $1\sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_cmd_payload_we $1\sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3820.1-3827.4" + process $proc$ls180.v:3820$1152 assign { } { } assign $0\rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:3831.2-3835.9" + attribute \src "ls180.v:3822.2-3826.9" switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\rhs_array_muxed23[0:0] $and$ls180.v:3833$1165_Y + assign $0\rhs_array_muxed23[0:0] $and$ls180.v:3824$1165_Y end sync always update \rhs_array_muxed23 $0\rhs_array_muxed23[0:0] end - attribute \src "ls180.v:383.5-383.26" - process $proc$ls180.v:383$1683 - assign { } { } - assign $1\sdram_cmd_last[0:0] 1'0 - sync always - sync init - update \sdram_cmd_last $1\sdram_cmd_last[0:0] - end - attribute \src "ls180.v:3837.1-3850.4" - process $proc$ls180.v:3837$1166 + attribute \src "ls180.v:3828.1-3841.4" + process $proc$ls180.v:3828$1166 assign { } { } assign $0\rhs_array_muxed24[29:0] 30'000000000000000000000000000000 - attribute \src "ls180.v:3839.2-3849.9" + attribute \src "ls180.v:3830.2-3840.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265609,27 +265458,27 @@ module \ls180 sync always update \rhs_array_muxed24 $0\rhs_array_muxed24[29:0] end - attribute \src "ls180.v:384.12-384.39" - process $proc$ls180.v:384$1684 + attribute \src "ls180.v:383.5-383.37" + process $proc$ls180.v:383$1693 assign { } { } - assign $1\sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\sdram_cmd_payload_is_read[0:0] 1'0 sync always + update \sdram_cmd_payload_is_read $0\sdram_cmd_payload_is_read[0:0] sync init - update \sdram_cmd_payload_a $1\sdram_cmd_payload_a[12:0] end - attribute \src "ls180.v:385.11-385.38" - process $proc$ls180.v:385$1685 + attribute \src "ls180.v:384.5-384.38" + process $proc$ls180.v:384$1694 assign { } { } - assign $1\sdram_cmd_payload_ba[1:0] 2'00 + assign $0\sdram_cmd_payload_is_write[0:0] 1'0 sync always + update \sdram_cmd_payload_is_write $0\sdram_cmd_payload_is_write[0:0] sync init - update \sdram_cmd_payload_ba $1\sdram_cmd_payload_ba[1:0] end - attribute \src "ls180.v:3851.1-3864.4" - process $proc$ls180.v:3851$1167 + attribute \src "ls180.v:3842.1-3855.4" + process $proc$ls180.v:3842$1167 assign { } { } assign $0\rhs_array_muxed25[31:0] 0 - attribute \src "ls180.v:3853.2-3863.9" + attribute \src "ls180.v:3844.2-3854.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265644,19 +265493,11 @@ module \ls180 sync always update \rhs_array_muxed25 $0\rhs_array_muxed25[31:0] end - attribute \src "ls180.v:386.5-386.33" - process $proc$ls180.v:386$1686 - assign { } { } - assign $1\sdram_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \sdram_cmd_payload_cas $1\sdram_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:3865.1-3878.4" - process $proc$ls180.v:3865$1168 + attribute \src "ls180.v:3856.1-3869.4" + process $proc$ls180.v:3856$1168 assign { } { } assign $0\rhs_array_muxed26[3:0] 4'0000 - attribute \src "ls180.v:3867.2-3877.9" + attribute \src "ls180.v:3858.2-3868.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265671,19 +265512,11 @@ module \ls180 sync always update \rhs_array_muxed26 $0\rhs_array_muxed26[3:0] end - attribute \src "ls180.v:387.5-387.33" - process $proc$ls180.v:387$1687 - assign { } { } - assign $1\sdram_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \sdram_cmd_payload_ras $1\sdram_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:3879.1-3892.4" - process $proc$ls180.v:3879$1169 + attribute \src "ls180.v:3870.1-3883.4" + process $proc$ls180.v:3870$1169 assign { } { } assign $0\rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:3881.2-3891.9" + attribute \src "ls180.v:3872.2-3882.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265698,27 +265531,11 @@ module \ls180 sync always update \rhs_array_muxed27 $0\rhs_array_muxed27[0:0] end - attribute \src "ls180.v:388.5-388.32" - process $proc$ls180.v:388$1688 - assign { } { } - assign $1\sdram_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \sdram_cmd_payload_we $1\sdram_cmd_payload_we[0:0] - end - attribute \src "ls180.v:389.5-389.37" - process $proc$ls180.v:389$1689 - assign { } { } - assign $0\sdram_cmd_payload_is_read[0:0] 1'0 - sync always - update \sdram_cmd_payload_is_read $0\sdram_cmd_payload_is_read[0:0] - sync init - end - attribute \src "ls180.v:3893.1-3906.4" - process $proc$ls180.v:3893$1170 + attribute \src "ls180.v:3884.1-3897.4" + process $proc$ls180.v:3884$1170 assign { } { } assign $0\rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:3895.2-3905.9" + attribute \src "ls180.v:3886.2-3896.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265733,19 +265550,11 @@ module \ls180 sync always update \rhs_array_muxed28 $0\rhs_array_muxed28[0:0] end - attribute \src "ls180.v:390.5-390.38" - process $proc$ls180.v:390$1690 - assign { } { } - assign $0\sdram_cmd_payload_is_write[0:0] 1'0 - sync always - update \sdram_cmd_payload_is_write $0\sdram_cmd_payload_is_write[0:0] - sync init - end - attribute \src "ls180.v:3907.1-3920.4" - process $proc$ls180.v:3907$1171 + attribute \src "ls180.v:3898.1-3911.4" + process $proc$ls180.v:3898$1171 assign { } { } assign $0\rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:3909.2-3919.9" + attribute \src "ls180.v:3900.2-3910.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265760,11 +265569,19 @@ module \ls180 sync always update \rhs_array_muxed29 $0\rhs_array_muxed29[0:0] end - attribute \src "ls180.v:3921.1-3934.4" - process $proc$ls180.v:3921$1172 + attribute \src "ls180.v:390.11-390.39" + process $proc$ls180.v:390$1695 + assign { } { } + assign $1\sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \sdram_timer_count1 $1\sdram_timer_count1[9:0] + end + attribute \src "ls180.v:3912.1-3925.4" + process $proc$ls180.v:3912$1172 assign { } { } assign $0\rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:3923.2-3933.9" + attribute \src "ls180.v:3914.2-3924.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265779,11 +265596,19 @@ module \ls180 sync always update \rhs_array_muxed30 $0\rhs_array_muxed30[2:0] end - attribute \src "ls180.v:3935.1-3948.4" - process $proc$ls180.v:3935$1173 + attribute \src "ls180.v:392.5-392.33" + process $proc$ls180.v:392$1696 + assign { } { } + assign $1\sdram_postponer_req_o[0:0] 1'0 + sync always + sync init + update \sdram_postponer_req_o $1\sdram_postponer_req_o[0:0] + end + attribute \src "ls180.v:3926.1-3939.4" + process $proc$ls180.v:3926$1173 assign { } { } assign $0\rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:3937.2-3947.9" + attribute \src "ls180.v:3928.2-3938.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265798,11 +265623,27 @@ module \ls180 sync always update \rhs_array_muxed31 $0\rhs_array_muxed31[1:0] end - attribute \src "ls180.v:3949.1-3965.4" - process $proc$ls180.v:3949$1174 + attribute \src "ls180.v:393.5-393.33" + process $proc$ls180.v:393$1697 + assign { } { } + assign $1\sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \sdram_postponer_count $1\sdram_postponer_count[0:0] + end + attribute \src "ls180.v:394.5-394.34" + process $proc$ls180.v:394$1698 + assign { } { } + assign $1\sdram_sequencer_start0[0:0] 1'0 + sync always + sync init + update \sdram_sequencer_start0 $1\sdram_sequencer_start0[0:0] + end + attribute \src "ls180.v:3940.1-3956.4" + process $proc$ls180.v:3940$1174 assign { } { } assign $0\array_muxed0[1:0] 2'00 - attribute \src "ls180.v:3951.2-3964.9" + attribute \src "ls180.v:3942.2-3955.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265820,19 +265661,11 @@ module \ls180 sync always update \array_muxed0 $0\array_muxed0[1:0] end - attribute \src "ls180.v:396.11-396.39" - process $proc$ls180.v:396$1691 - assign { } { } - assign $1\sdram_timer_count1[9:0] 10'1100001101 - sync always - sync init - update \sdram_timer_count1 $1\sdram_timer_count1[9:0] - end - attribute \src "ls180.v:3966.1-3982.4" - process $proc$ls180.v:3966$1175 + attribute \src "ls180.v:3957.1-3973.4" + process $proc$ls180.v:3957$1175 assign { } { } assign $0\array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:3968.2-3981.9" + attribute \src "ls180.v:3959.2-3972.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -265850,221 +265683,229 @@ module \ls180 sync always update \array_muxed1 $0\array_muxed1[12:0] end - attribute \src "ls180.v:398.5-398.33" - process $proc$ls180.v:398$1692 + attribute \src "ls180.v:397.5-397.33" + process $proc$ls180.v:397$1699 assign { } { } - assign $1\sdram_postponer_req_o[0:0] 1'0 + assign $1\sdram_sequencer_done1[0:0] 1'0 sync always sync init - update \sdram_postponer_req_o $1\sdram_postponer_req_o[0:0] + update \sdram_sequencer_done1 $1\sdram_sequencer_done1[0:0] end - attribute \src "ls180.v:3983.1-3999.4" - process $proc$ls180.v:3983$1176 + attribute \src "ls180.v:3974.1-3990.4" + process $proc$ls180.v:3974$1176 assign { } { } assign $0\array_muxed2[0:0] 1'0 - attribute \src "ls180.v:3985.2-3998.9" + attribute \src "ls180.v:3976.2-3989.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed2[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\array_muxed2[0:0] $and$ls180.v:3990$1178_Y + assign $0\array_muxed2[0:0] $and$ls180.v:3981$1178_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\array_muxed2[0:0] $and$ls180.v:3993$1180_Y + assign $0\array_muxed2[0:0] $and$ls180.v:3984$1180_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\array_muxed2[0:0] $and$ls180.v:3996$1182_Y + assign $0\array_muxed2[0:0] $and$ls180.v:3987$1182_Y end sync always update \array_muxed2 $0\array_muxed2[0:0] end - attribute \src "ls180.v:399.5-399.33" - process $proc$ls180.v:399$1693 + attribute \src "ls180.v:398.11-398.41" + process $proc$ls180.v:398$1700 assign { } { } - assign $1\sdram_postponer_count[0:0] 1'0 + assign $1\sdram_sequencer_counter[3:0] 4'0000 sync always sync init - update \sdram_postponer_count $1\sdram_postponer_count[0:0] + update \sdram_sequencer_counter $1\sdram_sequencer_counter[3:0] end - attribute \src "ls180.v:400.5-400.34" - process $proc$ls180.v:400$1694 + attribute \src "ls180.v:399.5-399.33" + process $proc$ls180.v:399$1701 assign { } { } - assign $1\sdram_sequencer_start0[0:0] 1'0 + assign $1\sdram_sequencer_count[0:0] 1'0 sync always sync init - update \sdram_sequencer_start0 $1\sdram_sequencer_start0[0:0] + update \sdram_sequencer_count $1\sdram_sequencer_count[0:0] end - attribute \src "ls180.v:4000.1-4016.4" - process $proc$ls180.v:4000$1183 + attribute \src "ls180.v:3991.1-4007.4" + process $proc$ls180.v:3991$1183 assign { } { } assign $0\array_muxed3[0:0] 1'0 - attribute \src "ls180.v:4002.2-4015.9" + attribute \src "ls180.v:3993.2-4006.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed3[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\array_muxed3[0:0] $and$ls180.v:4007$1185_Y + assign $0\array_muxed3[0:0] $and$ls180.v:3998$1185_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\array_muxed3[0:0] $and$ls180.v:4010$1187_Y + assign $0\array_muxed3[0:0] $and$ls180.v:4001$1187_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\array_muxed3[0:0] $and$ls180.v:4013$1189_Y + assign $0\array_muxed3[0:0] $and$ls180.v:4004$1189_Y end sync always update \array_muxed3 $0\array_muxed3[0:0] end - attribute \src "ls180.v:4017.1-4033.4" - process $proc$ls180.v:4017$1190 + attribute \src "ls180.v:4008.1-4024.4" + process $proc$ls180.v:4008$1190 assign { } { } assign $0\array_muxed4[0:0] 1'0 - attribute \src "ls180.v:4019.2-4032.9" + attribute \src "ls180.v:4010.2-4023.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed4[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\array_muxed4[0:0] $and$ls180.v:4024$1192_Y + assign $0\array_muxed4[0:0] $and$ls180.v:4015$1192_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\array_muxed4[0:0] $and$ls180.v:4027$1194_Y + assign $0\array_muxed4[0:0] $and$ls180.v:4018$1194_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\array_muxed4[0:0] $and$ls180.v:4030$1196_Y + assign $0\array_muxed4[0:0] $and$ls180.v:4021$1196_Y end sync always update \array_muxed4 $0\array_muxed4[0:0] end - attribute \src "ls180.v:403.5-403.33" - process $proc$ls180.v:403$1695 - assign { } { } - assign $1\sdram_sequencer_done1[0:0] 1'0 - sync always - sync init - update \sdram_sequencer_done1 $1\sdram_sequencer_done1[0:0] - end - attribute \src "ls180.v:4034.1-4050.4" - process $proc$ls180.v:4034$1197 + attribute \src "ls180.v:4025.1-4041.4" + process $proc$ls180.v:4025$1197 assign { } { } assign $0\array_muxed5[0:0] 1'0 - attribute \src "ls180.v:4036.2-4049.9" + attribute \src "ls180.v:4027.2-4040.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed5[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\array_muxed5[0:0] $and$ls180.v:4041$1199_Y + assign $0\array_muxed5[0:0] $and$ls180.v:4032$1199_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\array_muxed5[0:0] $and$ls180.v:4044$1201_Y + assign $0\array_muxed5[0:0] $and$ls180.v:4035$1201_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\array_muxed5[0:0] $and$ls180.v:4047$1203_Y + assign $0\array_muxed5[0:0] $and$ls180.v:4038$1203_Y end sync always update \array_muxed5 $0\array_muxed5[0:0] end - attribute \src "ls180.v:404.11-404.41" - process $proc$ls180.v:404$1696 - assign { } { } - assign $1\sdram_sequencer_counter[3:0] 4'0000 - sync always - sync init - update \sdram_sequencer_counter $1\sdram_sequencer_counter[3:0] - end - attribute \src "ls180.v:405.5-405.33" - process $proc$ls180.v:405$1697 - assign { } { } - assign $1\sdram_sequencer_count[0:0] 1'0 - sync always - sync init - update \sdram_sequencer_count $1\sdram_sequencer_count[0:0] - end - attribute \src "ls180.v:4051.1-4067.4" - process $proc$ls180.v:4051$1204 + attribute \src "ls180.v:4042.1-4058.4" + process $proc$ls180.v:4042$1204 assign { } { } assign $0\array_muxed6[0:0] 1'0 - attribute \src "ls180.v:4053.2-4066.9" + attribute \src "ls180.v:4044.2-4057.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed6[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\array_muxed6[0:0] $and$ls180.v:4058$1206_Y + assign $0\array_muxed6[0:0] $and$ls180.v:4049$1206_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\array_muxed6[0:0] $and$ls180.v:4061$1208_Y + assign $0\array_muxed6[0:0] $and$ls180.v:4052$1208_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\array_muxed6[0:0] $and$ls180.v:4064$1210_Y + assign $0\array_muxed6[0:0] $and$ls180.v:4055$1210_Y end sync always update \array_muxed6 $0\array_muxed6[0:0] end - attribute \src "ls180.v:411.5-411.46" - process $proc$ls180.v:411$1698 + attribute \src "ls180.v:405.5-405.46" + process $proc$ls180.v:405$1702 assign { } { } assign $1\sdram_bankmachine0_req_wdata_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine0_req_wdata_ready $1\sdram_bankmachine0_req_wdata_ready[0:0] end - attribute \src "ls180.v:412.5-412.46" - process $proc$ls180.v:412$1699 + attribute \src "ls180.v:406.5-406.46" + process $proc$ls180.v:406$1703 assign { } { } assign $1\sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine0_req_rdata_valid $1\sdram_bankmachine0_req_rdata_valid[0:0] end - attribute \src "ls180.v:414.5-414.42" - process $proc$ls180.v:414$1700 + attribute \src "ls180.v:408.5-408.42" + process $proc$ls180.v:408$1704 assign { } { } assign $1\sdram_bankmachine0_refresh_gnt[0:0] 1'0 sync always sync init update \sdram_bankmachine0_refresh_gnt $1\sdram_bankmachine0_refresh_gnt[0:0] end - attribute \src "ls180.v:415.5-415.40" - process $proc$ls180.v:415$1701 + attribute \src "ls180.v:409.5-409.40" + process $proc$ls180.v:409$1705 assign { } { } assign $1\sdram_bankmachine0_cmd_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_valid $1\sdram_bankmachine0_cmd_valid[0:0] end - attribute \src "ls180.v:416.5-416.40" - process $proc$ls180.v:416$1702 + attribute \src "ls180.v:410.5-410.40" + process $proc$ls180.v:410$1706 assign { } { } assign $1\sdram_bankmachine0_cmd_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_ready $1\sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:417.12-417.52" - process $proc$ls180.v:417$1703 + attribute \src "ls180.v:411.12-411.52" + process $proc$ls180.v:411$1707 assign { } { } assign $1\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine0_cmd_payload_a $1\sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:4174.1-4176.4" - process $proc$ls180.v:4174$1211 + attribute \src "ls180.v:413.5-413.46" + process $proc$ls180.v:413$1708 + assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_cas $1\sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:414.5-414.46" + process $proc$ls180.v:414$1709 + assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_ras $1\sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:415.5-415.45" + process $proc$ls180.v:415$1710 + assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_we $1\sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:416.5-416.49" + process $proc$ls180.v:416$1711 + assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_is_cmd $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:4165.1-4167.4" + process $proc$ls180.v:4165$1211 assign { } { } assign $0\int_rst[0:0] \sys_rst sync posedge \por_clk update \int_rst $0\int_rst[0:0] end - attribute \src "ls180.v:4178.1-4283.4" - process $proc$ls180.v:4178$1212 + attribute \src "ls180.v:4169.1-4274.4" + process $proc$ls180.v:4169$1212 assign { } { } assign { } { } assign { } { } @@ -266136,8 +265977,8 @@ module \ls180 assign $0\dfi_p0_rddata[15:0] [14] \libresocsim_libresoc_constraintmanager_sdram_dq_i [14] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [15] \dfi_p0_wrdata [15] assign $0\dfi_p0_rddata[15:0] [15] \libresocsim_libresoc_constraintmanager_sdram_dq_i [15] - assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [0] $and$ls180.v:4232$1213_Y - assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [1] $and$ls180.v:4233$1214_Y + assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [0] $and$ls180.v:4223$1213_Y + assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [1] $and$ls180.v:4224$1214_Y assign $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] \sys_clk_1 assign $0\gpio0_pads_gpio0oe[7:0] [0] \gpio0_oe_storage [0] assign $0\gpio0_pads_gpio0o[7:0] [0] \gpio0_out_storage [0] @@ -266207,72 +266048,56 @@ module \ls180 update \gpio1_pads_gpio1o $0\gpio1_pads_gpio1o[7:0] update \gpio1_pads_gpio1oe $0\gpio1_pads_gpio1oe[7:0] end - attribute \src "ls180.v:419.5-419.46" - process $proc$ls180.v:419$1704 - assign { } { } - assign $1\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \sdram_bankmachine0_cmd_payload_cas $1\sdram_bankmachine0_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:420.5-420.46" - process $proc$ls180.v:420$1705 - assign { } { } - assign $1\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \sdram_bankmachine0_cmd_payload_ras $1\sdram_bankmachine0_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:421.5-421.45" - process $proc$ls180.v:421$1706 - assign { } { } - assign $1\sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \sdram_bankmachine0_cmd_payload_we $1\sdram_bankmachine0_cmd_payload_we[0:0] - end - attribute \src "ls180.v:422.5-422.49" - process $proc$ls180.v:422$1707 - assign { } { } - assign $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \sdram_bankmachine0_cmd_payload_is_cmd $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:423.5-423.50" - process $proc$ls180.v:423$1708 + attribute \src "ls180.v:417.5-417.50" + process $proc$ls180.v:417$1712 assign { } { } assign $1\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_payload_is_read $1\sdram_bankmachine0_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:424.5-424.51" - process $proc$ls180.v:424$1709 + attribute \src "ls180.v:418.5-418.51" + process $proc$ls180.v:418$1713 assign { } { } assign $1\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_payload_is_write $1\sdram_bankmachine0_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:425.5-425.45" - process $proc$ls180.v:425$1710 + attribute \src "ls180.v:419.5-419.45" + process $proc$ls180.v:419$1714 assign { } { } assign $1\sdram_bankmachine0_auto_precharge[0:0] 1'0 sync always sync init update \sdram_bankmachine0_auto_precharge $1\sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:428.5-428.62" - process $proc$ls180.v:428$1711 + attribute \src "ls180.v:42.5-42.37" + process $proc$ls180.v:42$1551 + assign { } { } + assign $1\libresocsim_reset_storage[0:0] 1'0 + sync always + sync init + update \libresocsim_reset_storage $1\libresocsim_reset_storage[0:0] + end + attribute \src "ls180.v:422.5-422.62" + process $proc$ls180.v:422$1715 assign { } { } assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init end - attribute \src "ls180.v:4285.1-5491.4" - process $proc$ls180.v:4285$1215 + attribute \src "ls180.v:423.5-423.61" + process $proc$ls180.v:423$1716 + assign { } { } + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4276.1-5486.4" + process $proc$ls180.v:4276$1215 assign $0\libresocsim_reset_storage[0:0] \libresocsim_reset_storage assign { } { } assign $0\libresocsim_scratch_storage[31:0] \libresocsim_scratch_storage @@ -266466,42 +266291,46 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\dummy[35:0] [0] $or$ls180.v:4286$1216_Y - assign $0\dummy[35:0] [1] $or$ls180.v:4287$1217_Y - assign $0\dummy[35:0] [2] $or$ls180.v:4288$1218_Y - assign $0\dummy[35:0] [3] $or$ls180.v:4289$1219_Y - assign $0\dummy[35:0] [4] $or$ls180.v:4290$1220_Y - assign $0\dummy[35:0] [5] $or$ls180.v:4291$1221_Y - assign $0\dummy[35:0] [6] $or$ls180.v:4292$1222_Y - assign $0\dummy[35:0] [7] $or$ls180.v:4293$1223_Y - assign $0\dummy[35:0] [8] $or$ls180.v:4294$1224_Y - assign $0\dummy[35:0] [9] $or$ls180.v:4295$1225_Y - assign $0\dummy[35:0] [10] $or$ls180.v:4296$1226_Y - assign $0\dummy[35:0] [11] $or$ls180.v:4297$1227_Y - assign $0\dummy[35:0] [12] $or$ls180.v:4298$1228_Y - assign $0\dummy[35:0] [13] $or$ls180.v:4299$1229_Y - assign $0\dummy[35:0] [14] $or$ls180.v:4300$1230_Y - assign $0\dummy[35:0] [15] $or$ls180.v:4301$1231_Y - assign $0\dummy[35:0] [16] $or$ls180.v:4302$1232_Y - assign $0\dummy[35:0] [17] $or$ls180.v:4303$1233_Y - assign $0\dummy[35:0] [18] $or$ls180.v:4304$1234_Y - assign $0\dummy[35:0] [19] $or$ls180.v:4305$1235_Y - assign $0\dummy[35:0] [20] $or$ls180.v:4306$1236_Y - assign $0\dummy[35:0] [21] $or$ls180.v:4307$1237_Y - assign $0\dummy[35:0] [22] $or$ls180.v:4308$1238_Y - assign $0\dummy[35:0] [23] $or$ls180.v:4309$1239_Y - assign $0\dummy[35:0] [24] $or$ls180.v:4310$1240_Y - assign $0\dummy[35:0] [25] $or$ls180.v:4311$1241_Y - assign $0\dummy[35:0] [26] $or$ls180.v:4312$1242_Y - assign $0\dummy[35:0] [27] $or$ls180.v:4313$1243_Y - assign $0\dummy[35:0] [28] $or$ls180.v:4314$1244_Y - assign $0\dummy[35:0] [29] $or$ls180.v:4315$1245_Y - assign $0\dummy[35:0] [30] $or$ls180.v:4316$1246_Y - assign $0\dummy[35:0] [31] $or$ls180.v:4317$1247_Y - assign $0\dummy[35:0] [32] $or$ls180.v:4318$1248_Y - assign $0\dummy[35:0] [33] $or$ls180.v:4319$1249_Y - assign $0\dummy[35:0] [34] $or$ls180.v:4320$1250_Y - assign $0\dummy[35:0] [35] $or$ls180.v:4321$1251_Y + assign $0\dummy[39:0] [0] $or$ls180.v:4277$1216_Y + assign $0\dummy[39:0] [1] $or$ls180.v:4278$1217_Y + assign $0\dummy[39:0] [2] $or$ls180.v:4279$1218_Y + assign $0\dummy[39:0] [3] $or$ls180.v:4280$1219_Y + assign $0\dummy[39:0] [4] $or$ls180.v:4281$1220_Y + assign $0\dummy[39:0] [5] $or$ls180.v:4282$1221_Y + assign $0\dummy[39:0] [6] $or$ls180.v:4283$1222_Y + assign $0\dummy[39:0] [7] $or$ls180.v:4284$1223_Y + assign $0\dummy[39:0] [8] $or$ls180.v:4285$1224_Y + assign $0\dummy[39:0] [9] $or$ls180.v:4286$1225_Y + assign $0\dummy[39:0] [10] $or$ls180.v:4287$1226_Y + assign $0\dummy[39:0] [11] $or$ls180.v:4288$1227_Y + assign $0\dummy[39:0] [12] $or$ls180.v:4289$1228_Y + assign $0\dummy[39:0] [13] $or$ls180.v:4290$1229_Y + assign $0\dummy[39:0] [14] $or$ls180.v:4291$1230_Y + assign $0\dummy[39:0] [15] $or$ls180.v:4292$1231_Y + assign $0\dummy[39:0] [16] $or$ls180.v:4293$1232_Y + assign $0\dummy[39:0] [17] $or$ls180.v:4294$1233_Y + assign $0\dummy[39:0] [18] $or$ls180.v:4295$1234_Y + assign $0\dummy[39:0] [19] $or$ls180.v:4296$1235_Y + assign $0\dummy[39:0] [20] $or$ls180.v:4297$1236_Y + assign $0\dummy[39:0] [21] $or$ls180.v:4298$1237_Y + assign $0\dummy[39:0] [22] $or$ls180.v:4299$1238_Y + assign $0\dummy[39:0] [23] $or$ls180.v:4300$1239_Y + assign $0\dummy[39:0] [24] $or$ls180.v:4301$1240_Y + assign $0\dummy[39:0] [25] $or$ls180.v:4302$1241_Y + assign $0\dummy[39:0] [26] $or$ls180.v:4303$1242_Y + assign $0\dummy[39:0] [27] $or$ls180.v:4304$1243_Y + assign $0\dummy[39:0] [28] $or$ls180.v:4305$1244_Y + assign $0\dummy[39:0] [29] $or$ls180.v:4306$1245_Y + assign $0\dummy[39:0] [30] $or$ls180.v:4307$1246_Y + assign $0\dummy[39:0] [31] $or$ls180.v:4308$1247_Y + assign $0\dummy[39:0] [32] $or$ls180.v:4309$1248_Y + assign $0\dummy[39:0] [33] $or$ls180.v:4310$1249_Y + assign $0\dummy[39:0] [34] $or$ls180.v:4311$1250_Y + assign $0\dummy[39:0] [35] $or$ls180.v:4312$1251_Y + assign $0\dummy[39:0] [36] $or$ls180.v:4313$1252_Y + assign $0\dummy[39:0] [37] $or$ls180.v:4314$1253_Y + assign $0\dummy[39:0] [38] $or$ls180.v:4315$1254_Y + assign $0\dummy[39:0] [39] $or$ls180.v:4316$1255_Y assign $0\subfragments_converter0_state[0:0] \subfragments_converter0_next_state assign $0\subfragments_converter1_state[0:0] \subfragments_converter1_next_state assign $0\subfragments_converter2_state[0:0] \subfragments_converter2_next_state @@ -266525,14 +266354,14 @@ module \ls180 assign $0\sdram_dfi_p0_cs_n[0:0] 1'0 assign $0\sdram_dfi_p0_bank[1:0] \array_muxed0 assign $0\sdram_dfi_p0_address[12:0] \array_muxed1 - assign $0\sdram_dfi_p0_cas_n[0:0] $not$ls180.v:4767$1351_Y - assign $0\sdram_dfi_p0_ras_n[0:0] $not$ls180.v:4768$1352_Y - assign $0\sdram_dfi_p0_we_n[0:0] $not$ls180.v:4769$1353_Y + assign $0\sdram_dfi_p0_cas_n[0:0] $not$ls180.v:4762$1355_Y + assign $0\sdram_dfi_p0_ras_n[0:0] $not$ls180.v:4763$1356_Y + assign $0\sdram_dfi_p0_we_n[0:0] $not$ls180.v:4764$1357_Y assign $0\sdram_dfi_p0_rddata_en[0:0] \array_muxed5 assign $0\sdram_dfi_p0_wrdata_en[0:0] \array_muxed6 assign $0\subfragments_multiplexer_state[2:0] \subfragments_multiplexer_next_state - assign $0\subfragments_new_master_wdata_ready[0:0] $or$ls180.v:4803$1371_Y - assign $0\subfragments_new_master_rdata_valid0[0:0] $or$ls180.v:4804$1383_Y + assign $0\subfragments_new_master_wdata_ready[0:0] $or$ls180.v:4798$1375_Y + assign $0\subfragments_new_master_rdata_valid0[0:0] $or$ls180.v:4799$1387_Y assign $0\subfragments_new_master_rdata_valid1[0:0] \subfragments_new_master_rdata_valid0 assign $0\subfragments_new_master_rdata_valid2[0:0] \subfragments_new_master_rdata_valid1 assign $0\subfragments_new_master_rdata_valid3[0:0] \subfragments_new_master_rdata_valid2 @@ -266573,161 +266402,161 @@ module \ls180 assign $0\uart_phy_re[0:0] \libresocsim_csrbank7_tuning_word0_re assign $0\regs0[0:0] \libresocsim_libresoc_constraintmanager_uart_rx assign $0\regs1[0:0] \regs0 - attribute \src "ls180.v:4322.2-4324.5" - switch $or$ls180.v:4322$1252_Y - attribute \src "ls180.v:4322.6-4322.84" + attribute \src "ls180.v:4317.2-4319.5" + switch $or$ls180.v:4317$1256_Y + attribute \src "ls180.v:4317.6-4317.84" case 1'1 assign $0\libresocsim_converter0_dat_r[63:0] \libresocsim_libresoc_ibus_dat_r case end - attribute \src "ls180.v:4326.2-4328.5" + attribute \src "ls180.v:4321.2-4323.5" switch \libresocsim_converter0_counter_subfragments_converter0_next_value_ce - attribute \src "ls180.v:4326.6-4326.74" + attribute \src "ls180.v:4321.6-4321.74" case 1'1 assign $0\libresocsim_converter0_counter[0:0] \libresocsim_converter0_counter_subfragments_converter0_next_value case end - attribute \src "ls180.v:4329.2-4332.5" + attribute \src "ls180.v:4324.2-4327.5" switch \libresocsim_converter0_reset - attribute \src "ls180.v:4329.6-4329.34" + attribute \src "ls180.v:4324.6-4324.34" case 1'1 assign $0\libresocsim_converter0_counter[0:0] 1'0 assign $0\subfragments_converter0_state[0:0] 1'0 case end - attribute \src "ls180.v:4333.2-4335.5" - switch $or$ls180.v:4333$1253_Y - attribute \src "ls180.v:4333.6-4333.84" + attribute \src "ls180.v:4328.2-4330.5" + switch $or$ls180.v:4328$1257_Y + attribute \src "ls180.v:4328.6-4328.84" case 1'1 assign $0\libresocsim_converter1_dat_r[63:0] \libresocsim_libresoc_dbus_dat_r case end - attribute \src "ls180.v:4337.2-4339.5" + attribute \src "ls180.v:4332.2-4334.5" switch \libresocsim_converter1_counter_subfragments_converter1_next_value_ce - attribute \src "ls180.v:4337.6-4337.74" + attribute \src "ls180.v:4332.6-4332.74" case 1'1 assign $0\libresocsim_converter1_counter[0:0] \libresocsim_converter1_counter_subfragments_converter1_next_value case end - attribute \src "ls180.v:4340.2-4343.5" + attribute \src "ls180.v:4335.2-4338.5" switch \libresocsim_converter1_reset - attribute \src "ls180.v:4340.6-4340.34" + attribute \src "ls180.v:4335.6-4335.34" case 1'1 assign $0\libresocsim_converter1_counter[0:0] 1'0 assign $0\subfragments_converter1_state[0:0] 1'0 case end - attribute \src "ls180.v:4344.2-4346.5" - switch $or$ls180.v:4344$1254_Y - attribute \src "ls180.v:4344.6-4344.84" + attribute \src "ls180.v:4339.2-4341.5" + switch $or$ls180.v:4339$1258_Y + attribute \src "ls180.v:4339.6-4339.84" case 1'1 assign $0\libresocsim_converter2_dat_r[63:0] \libresocsim_libresoc_jtag_wb_dat_r case end - attribute \src "ls180.v:4348.2-4350.5" + attribute \src "ls180.v:4343.2-4345.5" switch \libresocsim_converter2_counter_subfragments_converter2_next_value_ce - attribute \src "ls180.v:4348.6-4348.74" + attribute \src "ls180.v:4343.6-4343.74" case 1'1 assign $0\libresocsim_converter2_counter[0:0] \libresocsim_converter2_counter_subfragments_converter2_next_value case end - attribute \src "ls180.v:4351.2-4354.5" + attribute \src "ls180.v:4346.2-4349.5" switch \libresocsim_converter2_reset - attribute \src "ls180.v:4351.6-4351.34" + attribute \src "ls180.v:4346.6-4346.34" case 1'1 assign $0\libresocsim_converter2_counter[0:0] 1'0 assign $0\subfragments_converter2_state[0:0] 1'0 case end - attribute \src "ls180.v:4355.2-4359.5" - switch $ne$ls180.v:4355$1255_Y - attribute \src "ls180.v:4355.6-4355.48" + attribute \src "ls180.v:4350.2-4354.5" + switch $ne$ls180.v:4350$1259_Y + attribute \src "ls180.v:4350.6-4350.48" case 1'1 - attribute \src "ls180.v:4356.3-4358.6" + attribute \src "ls180.v:4351.3-4353.6" switch \libresocsim_bus_error - attribute \src "ls180.v:4356.7-4356.28" + attribute \src "ls180.v:4351.7-4351.28" case 1'1 - assign $0\libresocsim_bus_errors[31:0] $add$ls180.v:4357$1256_Y + assign $0\libresocsim_bus_errors[31:0] $add$ls180.v:4352$1260_Y case end case end - attribute \src "ls180.v:4361.2-4363.5" - switch $and$ls180.v:4361$1259_Y - attribute \src "ls180.v:4361.6-4361.88" + attribute \src "ls180.v:4356.2-4358.5" + switch $and$ls180.v:4356$1263_Y + attribute \src "ls180.v:4356.6-4356.88" case 1'1 assign $0\libresocsim_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:4364.2-4372.5" + attribute \src "ls180.v:4359.2-4367.5" switch \libresocsim_en_storage - attribute \src "ls180.v:4364.6-4364.28" + attribute \src "ls180.v:4359.6-4359.28" case 1'1 - attribute \src "ls180.v:4365.3-4369.6" - switch $eq$ls180.v:4365$1260_Y - attribute \src "ls180.v:4365.7-4365.34" + attribute \src "ls180.v:4360.3-4364.6" + switch $eq$ls180.v:4360$1264_Y + attribute \src "ls180.v:4360.7-4360.34" case 1'1 assign $0\libresocsim_value[31:0] \libresocsim_reload_storage - attribute \src "ls180.v:4367.7-4367.11" + attribute \src "ls180.v:4362.7-4362.11" case - assign $0\libresocsim_value[31:0] $sub$ls180.v:4368$1261_Y + assign $0\libresocsim_value[31:0] $sub$ls180.v:4363$1265_Y end - attribute \src "ls180.v:4370.6-4370.10" + attribute \src "ls180.v:4365.6-4365.10" case assign $0\libresocsim_value[31:0] \libresocsim_load_storage end - attribute \src "ls180.v:4373.2-4375.5" + attribute \src "ls180.v:4368.2-4370.5" switch \libresocsim_update_value_re - attribute \src "ls180.v:4373.6-4373.33" + attribute \src "ls180.v:4368.6-4368.33" case 1'1 assign $0\libresocsim_value_status[31:0] \libresocsim_value case end - attribute \src "ls180.v:4376.2-4378.5" + attribute \src "ls180.v:4371.2-4373.5" switch \libresocsim_zero_clear - attribute \src "ls180.v:4376.6-4376.28" + attribute \src "ls180.v:4371.6-4371.28" case 1'1 assign $0\libresocsim_zero_pending[0:0] 1'0 case end - attribute \src "ls180.v:4380.2-4382.5" - switch $and$ls180.v:4380$1263_Y - attribute \src "ls180.v:4380.6-4380.66" + attribute \src "ls180.v:4375.2-4377.5" + switch $and$ls180.v:4375$1267_Y + attribute \src "ls180.v:4375.6-4375.66" case 1'1 assign $0\libresocsim_zero_pending[0:0] 1'1 case end - attribute \src "ls180.v:4384.2-4386.5" - switch $and$ls180.v:4384$1266_Y - attribute \src "ls180.v:4384.6-4384.76" + attribute \src "ls180.v:4379.2-4381.5" + switch $and$ls180.v:4379$1270_Y + attribute \src "ls180.v:4379.6-4379.76" case 1'1 assign $0\ram_bus_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:4389.2-4391.5" + attribute \src "ls180.v:4384.2-4386.5" switch \sdram_inti_p0_rddata_valid - attribute \src "ls180.v:4389.6-4389.32" + attribute \src "ls180.v:4384.6-4384.32" case 1'1 assign $0\sdram_status[15:0] \sdram_inti_p0_rddata case end - attribute \src "ls180.v:4392.2-4396.5" - switch $and$ls180.v:4392$1268_Y - attribute \src "ls180.v:4392.6-4392.47" + attribute \src "ls180.v:4387.2-4391.5" + switch $and$ls180.v:4387$1272_Y + attribute \src "ls180.v:4387.6-4387.47" case 1'1 - assign $0\sdram_timer_count1[9:0] $sub$ls180.v:4393$1269_Y - attribute \src "ls180.v:4394.6-4394.10" + assign $0\sdram_timer_count1[9:0] $sub$ls180.v:4388$1273_Y + attribute \src "ls180.v:4389.6-4389.10" case assign $0\sdram_timer_count1[9:0] 10'1100001101 end - attribute \src "ls180.v:4398.2-4404.5" + attribute \src "ls180.v:4393.2-4399.5" switch \sdram_postponer_req_i - attribute \src "ls180.v:4398.6-4398.27" + attribute \src "ls180.v:4393.6-4393.27" case 1'1 - assign $0\sdram_postponer_count[0:0] $sub$ls180.v:4399$1270_Y - attribute \src "ls180.v:4400.3-4403.6" - switch $eq$ls180.v:4400$1271_Y - attribute \src "ls180.v:4400.7-4400.38" + assign $0\sdram_postponer_count[0:0] $sub$ls180.v:4394$1274_Y + attribute \src "ls180.v:4395.3-4398.6" + switch $eq$ls180.v:4395$1275_Y + attribute \src "ls180.v:4395.7-4395.38" case 1'1 assign $0\sdram_postponer_count[0:0] 1'0 assign $0\sdram_postponer_req_o[0:0] 1'1 @@ -266735,30 +266564,30 @@ module \ls180 end case end - attribute \src "ls180.v:4405.2-4413.5" + attribute \src "ls180.v:4400.2-4408.5" switch \sdram_sequencer_start0 - attribute \src "ls180.v:4405.6-4405.28" + attribute \src "ls180.v:4400.6-4400.28" case 1'1 assign $0\sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:4407.6-4407.10" + attribute \src "ls180.v:4402.6-4402.10" case - attribute \src "ls180.v:4408.3-4412.6" + attribute \src "ls180.v:4403.3-4407.6" switch \sdram_sequencer_done1 - attribute \src "ls180.v:4408.7-4408.28" + attribute \src "ls180.v:4403.7-4403.28" case 1'1 - attribute \src "ls180.v:4409.4-4411.7" - switch $ne$ls180.v:4409$1272_Y - attribute \src "ls180.v:4409.8-4409.39" + attribute \src "ls180.v:4404.4-4406.7" + switch $ne$ls180.v:4404$1276_Y + attribute \src "ls180.v:4404.8-4404.39" case 1'1 - assign $0\sdram_sequencer_count[0:0] $sub$ls180.v:4410$1273_Y + assign $0\sdram_sequencer_count[0:0] $sub$ls180.v:4405$1277_Y case end case end end - attribute \src "ls180.v:4420.2-4426.5" - switch $and$ls180.v:4420$1275_Y - attribute \src "ls180.v:4420.6-4420.66" + attribute \src "ls180.v:4415.2-4421.5" + switch $and$ls180.v:4415$1279_Y + attribute \src "ls180.v:4415.6-4415.66" case 1'1 assign $0\sdram_cmd_payload_a[12:0] 13'0010000000000 assign $0\sdram_cmd_payload_ba[1:0] 2'00 @@ -266767,9 +266596,9 @@ module \ls180 assign $0\sdram_cmd_payload_we[0:0] 1'1 case end - attribute \src "ls180.v:4427.2-4433.5" - switch $eq$ls180.v:4427$1276_Y - attribute \src "ls180.v:4427.6-4427.39" + attribute \src "ls180.v:4422.2-4428.5" + switch $eq$ls180.v:4422$1280_Y + attribute \src "ls180.v:4422.6-4422.39" case 1'1 assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\sdram_cmd_payload_ba[1:0] 2'00 @@ -266778,9 +266607,9 @@ module \ls180 assign $0\sdram_cmd_payload_we[0:0] 1'0 case end - attribute \src "ls180.v:4434.2-4441.5" - switch $eq$ls180.v:4434$1277_Y - attribute \src "ls180.v:4434.6-4434.39" + attribute \src "ls180.v:4429.2-4436.5" + switch $eq$ls180.v:4429$1281_Y + attribute \src "ls180.v:4429.6-4429.39" case 1'1 assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\sdram_cmd_payload_ba[1:0] 2'00 @@ -266790,83 +266619,83 @@ module \ls180 assign $0\sdram_sequencer_done1[0:0] 1'1 case end - attribute \src "ls180.v:4442.2-4452.5" - switch $eq$ls180.v:4442$1278_Y - attribute \src "ls180.v:4442.6-4442.39" + attribute \src "ls180.v:4437.2-4447.5" + switch $eq$ls180.v:4437$1282_Y + attribute \src "ls180.v:4437.6-4437.39" case 1'1 assign $0\sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:4444.6-4444.10" + attribute \src "ls180.v:4439.6-4439.10" case - attribute \src "ls180.v:4445.3-4451.6" - switch $ne$ls180.v:4445$1279_Y - attribute \src "ls180.v:4445.7-4445.40" + attribute \src "ls180.v:4440.3-4446.6" + switch $ne$ls180.v:4440$1283_Y + attribute \src "ls180.v:4440.7-4440.40" case 1'1 - assign $0\sdram_sequencer_counter[3:0] $add$ls180.v:4446$1280_Y - attribute \src "ls180.v:4447.7-4447.11" + assign $0\sdram_sequencer_counter[3:0] $add$ls180.v:4441$1284_Y + attribute \src "ls180.v:4442.7-4442.11" case - attribute \src "ls180.v:4448.4-4450.7" + attribute \src "ls180.v:4443.4-4445.7" switch \sdram_sequencer_start1 - attribute \src "ls180.v:4448.8-4448.30" + attribute \src "ls180.v:4443.8-4443.30" case 1'1 assign $0\sdram_sequencer_counter[3:0] 4'0001 case end end end - attribute \src "ls180.v:4454.2-4461.5" + attribute \src "ls180.v:4449.2-4456.5" switch \sdram_bankmachine0_row_close - attribute \src "ls180.v:4454.6-4454.34" + attribute \src "ls180.v:4449.6-4449.34" case 1'1 assign $0\sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:4456.6-4456.10" + attribute \src "ls180.v:4451.6-4451.10" case - attribute \src "ls180.v:4457.3-4460.6" + attribute \src "ls180.v:4452.3-4455.6" switch \sdram_bankmachine0_row_open - attribute \src "ls180.v:4457.7-4457.34" + attribute \src "ls180.v:4452.7-4452.34" case 1'1 assign $0\sdram_bankmachine0_row_opened[0:0] 1'1 assign $0\sdram_bankmachine0_row[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:4462.2-4464.5" - switch $and$ls180.v:4462$1283_Y - attribute \src "ls180.v:4462.6-4462.176" + attribute \src "ls180.v:4457.2-4459.5" + switch $and$ls180.v:4457$1287_Y + attribute \src "ls180.v:4457.6-4457.176" case 1'1 - assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4463$1284_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4458$1288_Y case end - attribute \src "ls180.v:4465.2-4467.5" + attribute \src "ls180.v:4460.2-4462.5" switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:4465.6-4465.53" + attribute \src "ls180.v:4460.6-4460.53" case 1'1 - assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4466$1285_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4461$1289_Y case end - attribute \src "ls180.v:4468.2-4476.5" - switch $and$ls180.v:4468$1288_Y - attribute \src "ls180.v:4468.6-4468.176" + attribute \src "ls180.v:4463.2-4471.5" + switch $and$ls180.v:4463$1292_Y + attribute \src "ls180.v:4463.6-4463.176" case 1'1 - attribute \src "ls180.v:4469.3-4471.6" - switch $not$ls180.v:4469$1289_Y - attribute \src "ls180.v:4469.7-4469.57" + attribute \src "ls180.v:4464.3-4466.6" + switch $not$ls180.v:4464$1293_Y + attribute \src "ls180.v:4464.7-4464.57" case 1'1 - assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4470$1290_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4465$1294_Y case end - attribute \src "ls180.v:4472.6-4472.10" + attribute \src "ls180.v:4467.6-4467.10" case - attribute \src "ls180.v:4473.3-4475.6" + attribute \src "ls180.v:4468.3-4470.6" switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:4473.7-4473.54" + attribute \src "ls180.v:4468.7-4468.54" case 1'1 - assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4474$1291_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4469$1295_Y case end end - attribute \src "ls180.v:4477.2-4483.5" - switch $or$ls180.v:4477$1293_Y - attribute \src "ls180.v:4477.6-4477.98" + attribute \src "ls180.v:4472.2-4478.5" + switch $or$ls180.v:4472$1297_Y + attribute \src "ls180.v:4472.6-4472.98" case 1'1 assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] \sdram_bankmachine0_cmd_buffer_sink_valid assign $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] \sdram_bankmachine0_cmd_buffer_sink_first @@ -266875,27 +266704,27 @@ module \ls180 assign $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine0_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:4484.2-4498.5" + attribute \src "ls180.v:4479.2-4493.5" switch \sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:4484.6-4484.38" + attribute \src "ls180.v:4479.6-4479.38" case 1'1 assign $0\sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:4486.3-4490.6" + attribute \src "ls180.v:4481.3-4485.6" switch 1'0 - attribute \src "ls180.v:4488.7-4488.11" + attribute \src "ls180.v:4483.7-4483.11" case assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:4491.6-4491.10" + attribute \src "ls180.v:4486.6-4486.10" case - attribute \src "ls180.v:4492.3-4497.6" - switch $not$ls180.v:4492$1294_Y - attribute \src "ls180.v:4492.7-4492.42" + attribute \src "ls180.v:4487.3-4492.6" + switch $not$ls180.v:4487$1298_Y + attribute \src "ls180.v:4487.7-4487.42" case 1'1 - assign $0\sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:4493$1295_Y - attribute \src "ls180.v:4494.4-4496.7" - switch $eq$ls180.v:4494$1296_Y - attribute \src "ls180.v:4494.8-4494.50" + assign $0\sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:4488$1299_Y + attribute \src "ls180.v:4489.4-4491.7" + switch $eq$ls180.v:4489$1300_Y + attribute \src "ls180.v:4489.8-4489.50" case 1'1 assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'1 case @@ -266903,60 +266732,60 @@ module \ls180 case end end - attribute \src "ls180.v:4500.2-4507.5" + attribute \src "ls180.v:4495.2-4502.5" switch \sdram_bankmachine1_row_close - attribute \src "ls180.v:4500.6-4500.34" + attribute \src "ls180.v:4495.6-4495.34" case 1'1 assign $0\sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:4502.6-4502.10" + attribute \src "ls180.v:4497.6-4497.10" case - attribute \src "ls180.v:4503.3-4506.6" + attribute \src "ls180.v:4498.3-4501.6" switch \sdram_bankmachine1_row_open - attribute \src "ls180.v:4503.7-4503.34" + attribute \src "ls180.v:4498.7-4498.34" case 1'1 assign $0\sdram_bankmachine1_row_opened[0:0] 1'1 assign $0\sdram_bankmachine1_row[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:4508.2-4510.5" - switch $and$ls180.v:4508$1299_Y - attribute \src "ls180.v:4508.6-4508.176" + attribute \src "ls180.v:4503.2-4505.5" + switch $and$ls180.v:4503$1303_Y + attribute \src "ls180.v:4503.6-4503.176" case 1'1 - assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4509$1300_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4504$1304_Y case end - attribute \src "ls180.v:4511.2-4513.5" + attribute \src "ls180.v:4506.2-4508.5" switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:4511.6-4511.53" + attribute \src "ls180.v:4506.6-4506.53" case 1'1 - assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4512$1301_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4507$1305_Y case end - attribute \src "ls180.v:4514.2-4522.5" - switch $and$ls180.v:4514$1304_Y - attribute \src "ls180.v:4514.6-4514.176" + attribute \src "ls180.v:4509.2-4517.5" + switch $and$ls180.v:4509$1308_Y + attribute \src "ls180.v:4509.6-4509.176" case 1'1 - attribute \src "ls180.v:4515.3-4517.6" - switch $not$ls180.v:4515$1305_Y - attribute \src "ls180.v:4515.7-4515.57" + attribute \src "ls180.v:4510.3-4512.6" + switch $not$ls180.v:4510$1309_Y + attribute \src "ls180.v:4510.7-4510.57" case 1'1 - assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4516$1306_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4511$1310_Y case end - attribute \src "ls180.v:4518.6-4518.10" + attribute \src "ls180.v:4513.6-4513.10" case - attribute \src "ls180.v:4519.3-4521.6" + attribute \src "ls180.v:4514.3-4516.6" switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:4519.7-4519.54" + attribute \src "ls180.v:4514.7-4514.54" case 1'1 - assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4520$1307_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4515$1311_Y case end end - attribute \src "ls180.v:4523.2-4529.5" - switch $or$ls180.v:4523$1309_Y - attribute \src "ls180.v:4523.6-4523.98" + attribute \src "ls180.v:4518.2-4524.5" + switch $or$ls180.v:4518$1313_Y + attribute \src "ls180.v:4518.6-4518.98" case 1'1 assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] \sdram_bankmachine1_cmd_buffer_sink_valid assign $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] \sdram_bankmachine1_cmd_buffer_sink_first @@ -266965,27 +266794,27 @@ module \ls180 assign $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine1_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:4530.2-4544.5" + attribute \src "ls180.v:4525.2-4539.5" switch \sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:4530.6-4530.38" + attribute \src "ls180.v:4525.6-4525.38" case 1'1 assign $0\sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:4532.3-4536.6" + attribute \src "ls180.v:4527.3-4531.6" switch 1'0 - attribute \src "ls180.v:4534.7-4534.11" + attribute \src "ls180.v:4529.7-4529.11" case assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:4537.6-4537.10" + attribute \src "ls180.v:4532.6-4532.10" case - attribute \src "ls180.v:4538.3-4543.6" - switch $not$ls180.v:4538$1310_Y - attribute \src "ls180.v:4538.7-4538.42" + attribute \src "ls180.v:4533.3-4538.6" + switch $not$ls180.v:4533$1314_Y + attribute \src "ls180.v:4533.7-4533.42" case 1'1 - assign $0\sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:4539$1311_Y - attribute \src "ls180.v:4540.4-4542.7" - switch $eq$ls180.v:4540$1312_Y - attribute \src "ls180.v:4540.8-4540.50" + assign $0\sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:4534$1315_Y + attribute \src "ls180.v:4535.4-4537.7" + switch $eq$ls180.v:4535$1316_Y + attribute \src "ls180.v:4535.8-4535.50" case 1'1 assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'1 case @@ -266993,60 +266822,60 @@ module \ls180 case end end - attribute \src "ls180.v:4546.2-4553.5" + attribute \src "ls180.v:4541.2-4548.5" switch \sdram_bankmachine2_row_close - attribute \src "ls180.v:4546.6-4546.34" + attribute \src "ls180.v:4541.6-4541.34" case 1'1 assign $0\sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:4548.6-4548.10" + attribute \src "ls180.v:4543.6-4543.10" case - attribute \src "ls180.v:4549.3-4552.6" + attribute \src "ls180.v:4544.3-4547.6" switch \sdram_bankmachine2_row_open - attribute \src "ls180.v:4549.7-4549.34" + attribute \src "ls180.v:4544.7-4544.34" case 1'1 assign $0\sdram_bankmachine2_row_opened[0:0] 1'1 assign $0\sdram_bankmachine2_row[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:4554.2-4556.5" - switch $and$ls180.v:4554$1315_Y - attribute \src "ls180.v:4554.6-4554.176" + attribute \src "ls180.v:4549.2-4551.5" + switch $and$ls180.v:4549$1319_Y + attribute \src "ls180.v:4549.6-4549.176" case 1'1 - assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4555$1316_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4550$1320_Y case end - attribute \src "ls180.v:4557.2-4559.5" + attribute \src "ls180.v:4552.2-4554.5" switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:4557.6-4557.53" + attribute \src "ls180.v:4552.6-4552.53" case 1'1 - assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4558$1317_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4553$1321_Y case end - attribute \src "ls180.v:4560.2-4568.5" - switch $and$ls180.v:4560$1320_Y - attribute \src "ls180.v:4560.6-4560.176" + attribute \src "ls180.v:4555.2-4563.5" + switch $and$ls180.v:4555$1324_Y + attribute \src "ls180.v:4555.6-4555.176" case 1'1 - attribute \src "ls180.v:4561.3-4563.6" - switch $not$ls180.v:4561$1321_Y - attribute \src "ls180.v:4561.7-4561.57" + attribute \src "ls180.v:4556.3-4558.6" + switch $not$ls180.v:4556$1325_Y + attribute \src "ls180.v:4556.7-4556.57" case 1'1 - assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4562$1322_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4557$1326_Y case end - attribute \src "ls180.v:4564.6-4564.10" + attribute \src "ls180.v:4559.6-4559.10" case - attribute \src "ls180.v:4565.3-4567.6" + attribute \src "ls180.v:4560.3-4562.6" switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:4565.7-4565.54" + attribute \src "ls180.v:4560.7-4560.54" case 1'1 - assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4566$1323_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4561$1327_Y case end end - attribute \src "ls180.v:4569.2-4575.5" - switch $or$ls180.v:4569$1325_Y - attribute \src "ls180.v:4569.6-4569.98" + attribute \src "ls180.v:4564.2-4570.5" + switch $or$ls180.v:4564$1329_Y + attribute \src "ls180.v:4564.6-4564.98" case 1'1 assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] \sdram_bankmachine2_cmd_buffer_sink_valid assign $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] \sdram_bankmachine2_cmd_buffer_sink_first @@ -267055,27 +266884,27 @@ module \ls180 assign $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine2_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:4576.2-4590.5" + attribute \src "ls180.v:4571.2-4585.5" switch \sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:4576.6-4576.38" + attribute \src "ls180.v:4571.6-4571.38" case 1'1 assign $0\sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:4578.3-4582.6" + attribute \src "ls180.v:4573.3-4577.6" switch 1'0 - attribute \src "ls180.v:4580.7-4580.11" + attribute \src "ls180.v:4575.7-4575.11" case assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:4583.6-4583.10" + attribute \src "ls180.v:4578.6-4578.10" case - attribute \src "ls180.v:4584.3-4589.6" - switch $not$ls180.v:4584$1326_Y - attribute \src "ls180.v:4584.7-4584.42" + attribute \src "ls180.v:4579.3-4584.6" + switch $not$ls180.v:4579$1330_Y + attribute \src "ls180.v:4579.7-4579.42" case 1'1 - assign $0\sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:4585$1327_Y - attribute \src "ls180.v:4586.4-4588.7" - switch $eq$ls180.v:4586$1328_Y - attribute \src "ls180.v:4586.8-4586.50" + assign $0\sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:4580$1331_Y + attribute \src "ls180.v:4581.4-4583.7" + switch $eq$ls180.v:4581$1332_Y + attribute \src "ls180.v:4581.8-4581.50" case 1'1 assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'1 case @@ -267083,60 +266912,60 @@ module \ls180 case end end - attribute \src "ls180.v:4592.2-4599.5" + attribute \src "ls180.v:4587.2-4594.5" switch \sdram_bankmachine3_row_close - attribute \src "ls180.v:4592.6-4592.34" + attribute \src "ls180.v:4587.6-4587.34" case 1'1 assign $0\sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:4594.6-4594.10" + attribute \src "ls180.v:4589.6-4589.10" case - attribute \src "ls180.v:4595.3-4598.6" + attribute \src "ls180.v:4590.3-4593.6" switch \sdram_bankmachine3_row_open - attribute \src "ls180.v:4595.7-4595.34" + attribute \src "ls180.v:4590.7-4590.34" case 1'1 assign $0\sdram_bankmachine3_row_opened[0:0] 1'1 assign $0\sdram_bankmachine3_row[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:4600.2-4602.5" - switch $and$ls180.v:4600$1331_Y - attribute \src "ls180.v:4600.6-4600.176" + attribute \src "ls180.v:4595.2-4597.5" + switch $and$ls180.v:4595$1335_Y + attribute \src "ls180.v:4595.6-4595.176" case 1'1 - assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4601$1332_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4596$1336_Y case end - attribute \src "ls180.v:4603.2-4605.5" + attribute \src "ls180.v:4598.2-4600.5" switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:4603.6-4603.53" + attribute \src "ls180.v:4598.6-4598.53" case 1'1 - assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4604$1333_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4599$1337_Y case end - attribute \src "ls180.v:4606.2-4614.5" - switch $and$ls180.v:4606$1336_Y - attribute \src "ls180.v:4606.6-4606.176" + attribute \src "ls180.v:4601.2-4609.5" + switch $and$ls180.v:4601$1340_Y + attribute \src "ls180.v:4601.6-4601.176" case 1'1 - attribute \src "ls180.v:4607.3-4609.6" - switch $not$ls180.v:4607$1337_Y - attribute \src "ls180.v:4607.7-4607.57" + attribute \src "ls180.v:4602.3-4604.6" + switch $not$ls180.v:4602$1341_Y + attribute \src "ls180.v:4602.7-4602.57" case 1'1 - assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4608$1338_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4603$1342_Y case end - attribute \src "ls180.v:4610.6-4610.10" + attribute \src "ls180.v:4605.6-4605.10" case - attribute \src "ls180.v:4611.3-4613.6" + attribute \src "ls180.v:4606.3-4608.6" switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:4611.7-4611.54" + attribute \src "ls180.v:4606.7-4606.54" case 1'1 - assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4612$1339_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4607$1343_Y case end end - attribute \src "ls180.v:4615.2-4621.5" - switch $or$ls180.v:4615$1341_Y - attribute \src "ls180.v:4615.6-4615.98" + attribute \src "ls180.v:4610.2-4616.5" + switch $or$ls180.v:4610$1345_Y + attribute \src "ls180.v:4610.6-4610.98" case 1'1 assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] \sdram_bankmachine3_cmd_buffer_sink_valid assign $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] \sdram_bankmachine3_cmd_buffer_sink_first @@ -267145,27 +266974,27 @@ module \ls180 assign $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine3_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:4622.2-4636.5" + attribute \src "ls180.v:4617.2-4631.5" switch \sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:4622.6-4622.38" + attribute \src "ls180.v:4617.6-4617.38" case 1'1 assign $0\sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:4624.3-4628.6" + attribute \src "ls180.v:4619.3-4623.6" switch 1'0 - attribute \src "ls180.v:4626.7-4626.11" + attribute \src "ls180.v:4621.7-4621.11" case assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:4629.6-4629.10" + attribute \src "ls180.v:4624.6-4624.10" case - attribute \src "ls180.v:4630.3-4635.6" - switch $not$ls180.v:4630$1342_Y - attribute \src "ls180.v:4630.7-4630.42" + attribute \src "ls180.v:4625.3-4630.6" + switch $not$ls180.v:4625$1346_Y + attribute \src "ls180.v:4625.7-4625.42" case 1'1 - assign $0\sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:4631$1343_Y - attribute \src "ls180.v:4632.4-4634.7" - switch $eq$ls180.v:4632$1344_Y - attribute \src "ls180.v:4632.8-4632.50" + assign $0\sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:4626$1347_Y + attribute \src "ls180.v:4627.4-4629.7" + switch $eq$ls180.v:4627$1348_Y + attribute \src "ls180.v:4627.8-4627.50" case 1'1 assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'1 case @@ -267173,61 +267002,61 @@ module \ls180 case end end - attribute \src "ls180.v:4638.2-4644.5" - switch $not$ls180.v:4638$1345_Y - attribute \src "ls180.v:4638.6-4638.18" + attribute \src "ls180.v:4633.2-4639.5" + switch $not$ls180.v:4633$1349_Y + attribute \src "ls180.v:4633.6-4633.18" case 1'1 assign $0\sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:4640.6-4640.10" + attribute \src "ls180.v:4635.6-4635.10" case - attribute \src "ls180.v:4641.3-4643.6" - switch $not$ls180.v:4641$1346_Y - attribute \src "ls180.v:4641.7-4641.25" + attribute \src "ls180.v:4636.3-4638.6" + switch $not$ls180.v:4636$1350_Y + attribute \src "ls180.v:4636.7-4636.25" case 1'1 - assign $0\sdram_time0[4:0] $sub$ls180.v:4642$1347_Y + assign $0\sdram_time0[4:0] $sub$ls180.v:4637$1351_Y case end end - attribute \src "ls180.v:4645.2-4651.5" - switch $not$ls180.v:4645$1348_Y - attribute \src "ls180.v:4645.6-4645.18" + attribute \src "ls180.v:4640.2-4646.5" + switch $not$ls180.v:4640$1352_Y + attribute \src "ls180.v:4640.6-4640.18" case 1'1 assign $0\sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:4647.6-4647.10" + attribute \src "ls180.v:4642.6-4642.10" case - attribute \src "ls180.v:4648.3-4650.6" - switch $not$ls180.v:4648$1349_Y - attribute \src "ls180.v:4648.7-4648.25" + attribute \src "ls180.v:4643.3-4645.6" + switch $not$ls180.v:4643$1353_Y + attribute \src "ls180.v:4643.7-4643.25" case 1'1 - assign $0\sdram_time1[3:0] $sub$ls180.v:4649$1350_Y + assign $0\sdram_time1[3:0] $sub$ls180.v:4644$1354_Y case end end - attribute \src "ls180.v:4652.2-4707.5" + attribute \src "ls180.v:4647.2-4702.5" switch \sdram_choose_cmd_ce - attribute \src "ls180.v:4652.6-4652.25" + attribute \src "ls180.v:4647.6-4647.25" case 1'1 - attribute \src "ls180.v:4653.3-4706.10" + attribute \src "ls180.v:4648.3-4701.10" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:4655.5-4665.8" + attribute \src "ls180.v:4650.5-4660.8" switch \sdram_choose_cmd_request [1] - attribute \src "ls180.v:4655.9-4655.36" + attribute \src "ls180.v:4650.9-4650.36" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:4657.9-4657.13" + attribute \src "ls180.v:4652.9-4652.13" case - attribute \src "ls180.v:4658.6-4664.9" + attribute \src "ls180.v:4653.6-4659.9" switch \sdram_choose_cmd_request [2] - attribute \src "ls180.v:4658.10-4658.37" + attribute \src "ls180.v:4653.10-4653.37" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:4660.10-4660.14" + attribute \src "ls180.v:4655.10-4655.14" case - attribute \src "ls180.v:4661.7-4663.10" + attribute \src "ls180.v:4656.7-4658.10" switch \sdram_choose_cmd_request [3] - attribute \src "ls180.v:4661.11-4661.38" + attribute \src "ls180.v:4656.11-4656.38" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'11 case @@ -267236,23 +267065,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:4668.5-4678.8" + attribute \src "ls180.v:4663.5-4673.8" switch \sdram_choose_cmd_request [2] - attribute \src "ls180.v:4668.9-4668.36" + attribute \src "ls180.v:4663.9-4663.36" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:4670.9-4670.13" + attribute \src "ls180.v:4665.9-4665.13" case - attribute \src "ls180.v:4671.6-4677.9" + attribute \src "ls180.v:4666.6-4672.9" switch \sdram_choose_cmd_request [3] - attribute \src "ls180.v:4671.10-4671.37" + attribute \src "ls180.v:4666.10-4666.37" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:4673.10-4673.14" + attribute \src "ls180.v:4668.10-4668.14" case - attribute \src "ls180.v:4674.7-4676.10" + attribute \src "ls180.v:4669.7-4671.10" switch \sdram_choose_cmd_request [0] - attribute \src "ls180.v:4674.11-4674.38" + attribute \src "ls180.v:4669.11-4669.38" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'00 case @@ -267261,23 +267090,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:4681.5-4691.8" + attribute \src "ls180.v:4676.5-4686.8" switch \sdram_choose_cmd_request [3] - attribute \src "ls180.v:4681.9-4681.36" + attribute \src "ls180.v:4676.9-4676.36" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:4683.9-4683.13" + attribute \src "ls180.v:4678.9-4678.13" case - attribute \src "ls180.v:4684.6-4690.9" + attribute \src "ls180.v:4679.6-4685.9" switch \sdram_choose_cmd_request [0] - attribute \src "ls180.v:4684.10-4684.37" + attribute \src "ls180.v:4679.10-4679.37" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:4686.10-4686.14" + attribute \src "ls180.v:4681.10-4681.14" case - attribute \src "ls180.v:4687.7-4689.10" + attribute \src "ls180.v:4682.7-4684.10" switch \sdram_choose_cmd_request [1] - attribute \src "ls180.v:4687.11-4687.38" + attribute \src "ls180.v:4682.11-4682.38" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'01 case @@ -267286,23 +267115,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:4694.5-4704.8" + attribute \src "ls180.v:4689.5-4699.8" switch \sdram_choose_cmd_request [0] - attribute \src "ls180.v:4694.9-4694.36" + attribute \src "ls180.v:4689.9-4689.36" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:4696.9-4696.13" + attribute \src "ls180.v:4691.9-4691.13" case - attribute \src "ls180.v:4697.6-4703.9" + attribute \src "ls180.v:4692.6-4698.9" switch \sdram_choose_cmd_request [1] - attribute \src "ls180.v:4697.10-4697.37" + attribute \src "ls180.v:4692.10-4692.37" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:4699.10-4699.14" + attribute \src "ls180.v:4694.10-4694.14" case - attribute \src "ls180.v:4700.7-4702.10" + attribute \src "ls180.v:4695.7-4697.10" switch \sdram_choose_cmd_request [2] - attribute \src "ls180.v:4700.11-4700.38" + attribute \src "ls180.v:4695.11-4695.38" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'10 case @@ -267313,31 +267142,31 @@ module \ls180 end case end - attribute \src "ls180.v:4708.2-4763.5" + attribute \src "ls180.v:4703.2-4758.5" switch \sdram_choose_req_ce - attribute \src "ls180.v:4708.6-4708.25" + attribute \src "ls180.v:4703.6-4703.25" case 1'1 - attribute \src "ls180.v:4709.3-4762.10" + attribute \src "ls180.v:4704.3-4757.10" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:4711.5-4721.8" + attribute \src "ls180.v:4706.5-4716.8" switch \sdram_choose_req_request [1] - attribute \src "ls180.v:4711.9-4711.36" + attribute \src "ls180.v:4706.9-4706.36" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:4713.9-4713.13" + attribute \src "ls180.v:4708.9-4708.13" case - attribute \src "ls180.v:4714.6-4720.9" + attribute \src "ls180.v:4709.6-4715.9" switch \sdram_choose_req_request [2] - attribute \src "ls180.v:4714.10-4714.37" + attribute \src "ls180.v:4709.10-4709.37" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:4716.10-4716.14" + attribute \src "ls180.v:4711.10-4711.14" case - attribute \src "ls180.v:4717.7-4719.10" + attribute \src "ls180.v:4712.7-4714.10" switch \sdram_choose_req_request [3] - attribute \src "ls180.v:4717.11-4717.38" + attribute \src "ls180.v:4712.11-4712.38" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'11 case @@ -267346,23 +267175,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:4724.5-4734.8" + attribute \src "ls180.v:4719.5-4729.8" switch \sdram_choose_req_request [2] - attribute \src "ls180.v:4724.9-4724.36" + attribute \src "ls180.v:4719.9-4719.36" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:4726.9-4726.13" + attribute \src "ls180.v:4721.9-4721.13" case - attribute \src "ls180.v:4727.6-4733.9" + attribute \src "ls180.v:4722.6-4728.9" switch \sdram_choose_req_request [3] - attribute \src "ls180.v:4727.10-4727.37" + attribute \src "ls180.v:4722.10-4722.37" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:4729.10-4729.14" + attribute \src "ls180.v:4724.10-4724.14" case - attribute \src "ls180.v:4730.7-4732.10" + attribute \src "ls180.v:4725.7-4727.10" switch \sdram_choose_req_request [0] - attribute \src "ls180.v:4730.11-4730.38" + attribute \src "ls180.v:4725.11-4725.38" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'00 case @@ -267371,23 +267200,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:4737.5-4747.8" + attribute \src "ls180.v:4732.5-4742.8" switch \sdram_choose_req_request [3] - attribute \src "ls180.v:4737.9-4737.36" + attribute \src "ls180.v:4732.9-4732.36" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:4739.9-4739.13" + attribute \src "ls180.v:4734.9-4734.13" case - attribute \src "ls180.v:4740.6-4746.9" + attribute \src "ls180.v:4735.6-4741.9" switch \sdram_choose_req_request [0] - attribute \src "ls180.v:4740.10-4740.37" + attribute \src "ls180.v:4735.10-4735.37" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:4742.10-4742.14" + attribute \src "ls180.v:4737.10-4737.14" case - attribute \src "ls180.v:4743.7-4745.10" + attribute \src "ls180.v:4738.7-4740.10" switch \sdram_choose_req_request [1] - attribute \src "ls180.v:4743.11-4743.38" + attribute \src "ls180.v:4738.11-4738.38" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'01 case @@ -267396,23 +267225,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:4750.5-4760.8" + attribute \src "ls180.v:4745.5-4755.8" switch \sdram_choose_req_request [0] - attribute \src "ls180.v:4750.9-4750.36" + attribute \src "ls180.v:4745.9-4745.36" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:4752.9-4752.13" + attribute \src "ls180.v:4747.9-4747.13" case - attribute \src "ls180.v:4753.6-4759.9" + attribute \src "ls180.v:4748.6-4754.9" switch \sdram_choose_req_request [1] - attribute \src "ls180.v:4753.10-4753.37" + attribute \src "ls180.v:4748.10-4748.37" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:4755.10-4755.14" + attribute \src "ls180.v:4750.10-4750.14" case - attribute \src "ls180.v:4756.7-4758.10" + attribute \src "ls180.v:4751.7-4753.10" switch \sdram_choose_req_request [2] - attribute \src "ls180.v:4756.11-4756.38" + attribute \src "ls180.v:4751.11-4751.38" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'10 case @@ -267423,28 +267252,28 @@ module \ls180 end case end - attribute \src "ls180.v:4772.2-4786.5" + attribute \src "ls180.v:4767.2-4781.5" switch \sdram_tccdcon_valid - attribute \src "ls180.v:4772.6-4772.25" + attribute \src "ls180.v:4767.6-4767.25" case 1'1 assign $0\sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:4774.3-4778.6" + attribute \src "ls180.v:4769.3-4773.6" switch 1'1 - attribute \src "ls180.v:4774.7-4774.11" + attribute \src "ls180.v:4769.7-4769.11" case 1'1 assign $0\sdram_tccdcon_ready[0:0] 1'1 case end - attribute \src "ls180.v:4779.6-4779.10" + attribute \src "ls180.v:4774.6-4774.10" case - attribute \src "ls180.v:4780.3-4785.6" - switch $not$ls180.v:4780$1354_Y - attribute \src "ls180.v:4780.7-4780.29" + attribute \src "ls180.v:4775.3-4780.6" + switch $not$ls180.v:4775$1358_Y + attribute \src "ls180.v:4775.7-4775.29" case 1'1 - assign $0\sdram_tccdcon_count[0:0] $sub$ls180.v:4781$1355_Y - attribute \src "ls180.v:4782.4-4784.7" - switch $eq$ls180.v:4782$1356_Y - attribute \src "ls180.v:4782.8-4782.37" + assign $0\sdram_tccdcon_count[0:0] $sub$ls180.v:4776$1359_Y + attribute \src "ls180.v:4777.4-4779.7" + switch $eq$ls180.v:4777$1360_Y + attribute \src "ls180.v:4777.8-4777.37" case 1'1 assign $0\sdram_tccdcon_ready[0:0] 1'1 case @@ -267452,27 +267281,27 @@ module \ls180 case end end - attribute \src "ls180.v:4787.2-4801.5" + attribute \src "ls180.v:4782.2-4796.5" switch \sdram_twtrcon_valid - attribute \src "ls180.v:4787.6-4787.25" + attribute \src "ls180.v:4782.6-4782.25" case 1'1 assign $0\sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:4789.3-4793.6" + attribute \src "ls180.v:4784.3-4788.6" switch 1'0 - attribute \src "ls180.v:4791.7-4791.11" + attribute \src "ls180.v:4786.7-4786.11" case assign $0\sdram_twtrcon_ready[0:0] 1'0 end - attribute \src "ls180.v:4794.6-4794.10" + attribute \src "ls180.v:4789.6-4789.10" case - attribute \src "ls180.v:4795.3-4800.6" - switch $not$ls180.v:4795$1357_Y - attribute \src "ls180.v:4795.7-4795.29" + attribute \src "ls180.v:4790.3-4795.6" + switch $not$ls180.v:4790$1361_Y + attribute \src "ls180.v:4790.7-4790.29" case 1'1 - assign $0\sdram_twtrcon_count[2:0] $sub$ls180.v:4796$1358_Y - attribute \src "ls180.v:4797.4-4799.7" - switch $eq$ls180.v:4797$1359_Y - attribute \src "ls180.v:4797.8-4797.37" + assign $0\sdram_twtrcon_count[2:0] $sub$ls180.v:4791$1362_Y + attribute \src "ls180.v:4792.4-4794.7" + switch $eq$ls180.v:4792$1363_Y + attribute \src "ls180.v:4792.8-4792.37" case 1'1 assign $0\sdram_twtrcon_ready[0:0] 1'1 case @@ -267480,81 +267309,81 @@ module \ls180 case end end - attribute \src "ls180.v:4808.2-4810.5" - switch $or$ls180.v:4808$1384_Y - attribute \src "ls180.v:4808.6-4808.40" + attribute \src "ls180.v:4803.2-4805.5" + switch $or$ls180.v:4803$1388_Y + attribute \src "ls180.v:4803.6-4803.40" case 1'1 assign $0\converter_dat_r[31:0] \wb_sdram_dat_r case end - attribute \src "ls180.v:4812.2-4814.5" + attribute \src "ls180.v:4807.2-4809.5" switch \converter_counter_subfragments_next_value_ce - attribute \src "ls180.v:4812.6-4812.50" + attribute \src "ls180.v:4807.6-4807.50" case 1'1 assign $0\converter_counter[0:0] \converter_counter_subfragments_next_value case end - attribute \src "ls180.v:4815.2-4818.5" + attribute \src "ls180.v:4810.2-4813.5" switch \converter_reset - attribute \src "ls180.v:4815.6-4815.21" + attribute \src "ls180.v:4810.6-4810.21" case 1'1 assign $0\converter_counter[0:0] 1'0 assign $0\subfragments_state[0:0] 1'0 case end - attribute \src "ls180.v:4819.2-4829.5" + attribute \src "ls180.v:4814.2-4824.5" switch \litedram_wb_ack - attribute \src "ls180.v:4819.6-4819.21" + attribute \src "ls180.v:4814.6-4814.21" case 1'1 assign $0\cmd_consumed[0:0] 1'0 assign $0\wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:4822.6-4822.10" + attribute \src "ls180.v:4817.6-4817.10" case - attribute \src "ls180.v:4823.3-4825.6" - switch $and$ls180.v:4823$1385_Y - attribute \src "ls180.v:4823.7-4823.40" + attribute \src "ls180.v:4818.3-4820.6" + switch $and$ls180.v:4818$1389_Y + attribute \src "ls180.v:4818.7-4818.40" case 1'1 assign $0\cmd_consumed[0:0] 1'1 case end - attribute \src "ls180.v:4826.3-4828.6" - switch $and$ls180.v:4826$1386_Y - attribute \src "ls180.v:4826.7-4826.44" + attribute \src "ls180.v:4821.3-4823.6" + switch $and$ls180.v:4821$1390_Y + attribute \src "ls180.v:4821.7-4821.44" case 1'1 assign $0\wdata_consumed[0:0] 1'1 case end end - attribute \src "ls180.v:4831.2-4852.5" - switch $and$ls180.v:4831$1390_Y - attribute \src "ls180.v:4831.6-4831.76" + attribute \src "ls180.v:4826.2-4847.5" + switch $and$ls180.v:4826$1394_Y + attribute \src "ls180.v:4826.6-4826.76" case 1'1 assign $0\uart_phy_tx_reg[7:0] \uart_phy_sink_payload_data assign $0\uart_phy_tx_bitcount[3:0] 4'0000 assign $0\uart_phy_tx_busy[0:0] 1'1 assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'0 - attribute \src "ls180.v:4836.6-4836.10" + attribute \src "ls180.v:4831.6-4831.10" case - attribute \src "ls180.v:4837.3-4851.6" - switch $and$ls180.v:4837$1391_Y - attribute \src "ls180.v:4837.7-4837.50" + attribute \src "ls180.v:4832.3-4846.6" + switch $and$ls180.v:4832$1395_Y + attribute \src "ls180.v:4832.7-4832.50" case 1'1 - assign $0\uart_phy_tx_bitcount[3:0] $add$ls180.v:4838$1392_Y - attribute \src "ls180.v:4839.4-4850.7" - switch $eq$ls180.v:4839$1393_Y - attribute \src "ls180.v:4839.8-4839.38" + assign $0\uart_phy_tx_bitcount[3:0] $add$ls180.v:4833$1396_Y + attribute \src "ls180.v:4834.4-4845.7" + switch $eq$ls180.v:4834$1397_Y + attribute \src "ls180.v:4834.8-4834.38" case 1'1 assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 - attribute \src "ls180.v:4841.8-4841.12" + attribute \src "ls180.v:4836.8-4836.12" case - attribute \src "ls180.v:4842.5-4849.8" - switch $eq$ls180.v:4842$1394_Y - attribute \src "ls180.v:4842.9-4842.39" + attribute \src "ls180.v:4837.5-4844.8" + switch $eq$ls180.v:4837$1398_Y + attribute \src "ls180.v:4837.9-4837.39" case 1'1 assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 assign $0\uart_phy_tx_busy[0:0] 1'0 assign $0\uart_phy_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4846.9-4846.13" + attribute \src "ls180.v:4841.9-4841.13" case assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] \uart_phy_tx_reg [0] assign $0\uart_phy_tx_reg[7:0] { 1'0 \uart_phy_tx_reg [7:1] } @@ -267563,61 +267392,61 @@ module \ls180 case end end - attribute \src "ls180.v:4853.2-4857.5" + attribute \src "ls180.v:4848.2-4852.5" switch \uart_phy_tx_busy - attribute \src "ls180.v:4853.6-4853.22" + attribute \src "ls180.v:4848.6-4848.22" case 1'1 - assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:4854$1395_Y - attribute \src "ls180.v:4855.6-4855.10" + assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:4849$1399_Y + attribute \src "ls180.v:4850.6-4850.10" case assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } { 1'0 \uart_phy_storage } end - attribute \src "ls180.v:4860.2-4884.5" - switch $not$ls180.v:4860$1396_Y - attribute \src "ls180.v:4860.6-4860.25" + attribute \src "ls180.v:4855.2-4879.5" + switch $not$ls180.v:4855$1400_Y + attribute \src "ls180.v:4855.6-4855.25" case 1'1 - attribute \src "ls180.v:4861.3-4864.6" - switch $and$ls180.v:4861$1398_Y - attribute \src "ls180.v:4861.7-4861.39" + attribute \src "ls180.v:4856.3-4859.6" + switch $and$ls180.v:4856$1402_Y + attribute \src "ls180.v:4856.7-4856.39" case 1'1 assign $0\uart_phy_rx_busy[0:0] 1'1 assign $0\uart_phy_rx_bitcount[3:0] 4'0000 case end - attribute \src "ls180.v:4865.6-4865.10" + attribute \src "ls180.v:4860.6-4860.10" case - attribute \src "ls180.v:4866.3-4883.6" + attribute \src "ls180.v:4861.3-4878.6" switch \uart_phy_uart_clk_rxen - attribute \src "ls180.v:4866.7-4866.29" + attribute \src "ls180.v:4861.7-4861.29" case 1'1 - assign $0\uart_phy_rx_bitcount[3:0] $add$ls180.v:4867$1399_Y - attribute \src "ls180.v:4868.4-4882.7" - switch $eq$ls180.v:4868$1400_Y - attribute \src "ls180.v:4868.8-4868.38" + assign $0\uart_phy_rx_bitcount[3:0] $add$ls180.v:4862$1403_Y + attribute \src "ls180.v:4863.4-4877.7" + switch $eq$ls180.v:4863$1404_Y + attribute \src "ls180.v:4863.8-4863.38" case 1'1 - attribute \src "ls180.v:4869.5-4871.8" + attribute \src "ls180.v:4864.5-4866.8" switch \uart_phy_rx - attribute \src "ls180.v:4869.9-4869.20" + attribute \src "ls180.v:4864.9-4864.20" case 1'1 assign $0\uart_phy_rx_busy[0:0] 1'0 case end - attribute \src "ls180.v:4872.8-4872.12" + attribute \src "ls180.v:4867.8-4867.12" case - attribute \src "ls180.v:4873.5-4881.8" - switch $eq$ls180.v:4873$1401_Y - attribute \src "ls180.v:4873.9-4873.39" + attribute \src "ls180.v:4868.5-4876.8" + switch $eq$ls180.v:4868$1405_Y + attribute \src "ls180.v:4868.9-4868.39" case 1'1 assign $0\uart_phy_rx_busy[0:0] 1'0 - attribute \src "ls180.v:4875.6-4878.9" + attribute \src "ls180.v:4870.6-4873.9" switch \uart_phy_rx - attribute \src "ls180.v:4875.10-4875.21" + attribute \src "ls180.v:4870.10-4870.21" case 1'1 assign $0\uart_phy_source_payload_data[7:0] \uart_phy_rx_reg assign $0\uart_phy_source_valid[0:0] 1'1 case end - attribute \src "ls180.v:4879.9-4879.13" + attribute \src "ls180.v:4874.9-4874.13" case assign $0\uart_phy_rx_reg[7:0] { \uart_phy_rx \uart_phy_rx_reg [7:1] } end @@ -267625,146 +267454,146 @@ module \ls180 case end end - attribute \src "ls180.v:4885.2-4889.5" + attribute \src "ls180.v:4880.2-4884.5" switch \uart_phy_rx_busy - attribute \src "ls180.v:4885.6-4885.22" + attribute \src "ls180.v:4880.6-4880.22" case 1'1 - assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:4886$1402_Y - attribute \src "ls180.v:4887.6-4887.10" + assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:4881$1406_Y + attribute \src "ls180.v:4882.6-4882.10" case assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 end - attribute \src "ls180.v:4890.2-4892.5" + attribute \src "ls180.v:4885.2-4887.5" switch \tx_clear - attribute \src "ls180.v:4890.6-4890.14" + attribute \src "ls180.v:4885.6-4885.14" case 1'1 assign $0\tx_pending[0:0] 1'0 case end - attribute \src "ls180.v:4894.2-4896.5" - switch $and$ls180.v:4894$1404_Y - attribute \src "ls180.v:4894.6-4894.38" + attribute \src "ls180.v:4889.2-4891.5" + switch $and$ls180.v:4889$1408_Y + attribute \src "ls180.v:4889.6-4889.38" case 1'1 assign $0\tx_pending[0:0] 1'1 case end - attribute \src "ls180.v:4897.2-4899.5" + attribute \src "ls180.v:4892.2-4894.5" switch \rx_clear - attribute \src "ls180.v:4897.6-4897.14" + attribute \src "ls180.v:4892.6-4892.14" case 1'1 assign $0\rx_pending[0:0] 1'0 case end - attribute \src "ls180.v:4901.2-4903.5" - switch $and$ls180.v:4901$1406_Y - attribute \src "ls180.v:4901.6-4901.38" + attribute \src "ls180.v:4896.2-4898.5" + switch $and$ls180.v:4896$1410_Y + attribute \src "ls180.v:4896.6-4896.38" case 1'1 assign $0\rx_pending[0:0] 1'1 case end - attribute \src "ls180.v:4904.2-4910.5" + attribute \src "ls180.v:4899.2-4905.5" switch \tx_fifo_syncfifo_re - attribute \src "ls180.v:4904.6-4904.25" + attribute \src "ls180.v:4899.6-4899.25" case 1'1 assign $0\tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:4906.6-4906.10" + attribute \src "ls180.v:4901.6-4901.10" case - attribute \src "ls180.v:4907.3-4909.6" + attribute \src "ls180.v:4902.3-4904.6" switch \tx_fifo_re - attribute \src "ls180.v:4907.7-4907.17" + attribute \src "ls180.v:4902.7-4902.17" case 1'1 assign $0\tx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:4911.2-4913.5" - switch $and$ls180.v:4911$1409_Y - attribute \src "ls180.v:4911.6-4911.78" + attribute \src "ls180.v:4906.2-4908.5" + switch $and$ls180.v:4906$1413_Y + attribute \src "ls180.v:4906.6-4906.78" case 1'1 - assign $0\tx_fifo_produce[3:0] $add$ls180.v:4912$1410_Y + assign $0\tx_fifo_produce[3:0] $add$ls180.v:4907$1414_Y case end - attribute \src "ls180.v:4914.2-4916.5" + attribute \src "ls180.v:4909.2-4911.5" switch \tx_fifo_do_read - attribute \src "ls180.v:4914.6-4914.21" + attribute \src "ls180.v:4909.6-4909.21" case 1'1 - assign $0\tx_fifo_consume[3:0] $add$ls180.v:4915$1411_Y + assign $0\tx_fifo_consume[3:0] $add$ls180.v:4910$1415_Y case end - attribute \src "ls180.v:4917.2-4925.5" - switch $and$ls180.v:4917$1414_Y - attribute \src "ls180.v:4917.6-4917.78" + attribute \src "ls180.v:4912.2-4920.5" + switch $and$ls180.v:4912$1418_Y + attribute \src "ls180.v:4912.6-4912.78" case 1'1 - attribute \src "ls180.v:4918.3-4920.6" - switch $not$ls180.v:4918$1415_Y - attribute \src "ls180.v:4918.7-4918.25" + attribute \src "ls180.v:4913.3-4915.6" + switch $not$ls180.v:4913$1419_Y + attribute \src "ls180.v:4913.7-4913.25" case 1'1 - assign $0\tx_fifo_level0[4:0] $add$ls180.v:4919$1416_Y + assign $0\tx_fifo_level0[4:0] $add$ls180.v:4914$1420_Y case end - attribute \src "ls180.v:4921.6-4921.10" + attribute \src "ls180.v:4916.6-4916.10" case - attribute \src "ls180.v:4922.3-4924.6" + attribute \src "ls180.v:4917.3-4919.6" switch \tx_fifo_do_read - attribute \src "ls180.v:4922.7-4922.22" + attribute \src "ls180.v:4917.7-4917.22" case 1'1 - assign $0\tx_fifo_level0[4:0] $sub$ls180.v:4923$1417_Y + assign $0\tx_fifo_level0[4:0] $sub$ls180.v:4918$1421_Y case end end - attribute \src "ls180.v:4926.2-4932.5" + attribute \src "ls180.v:4921.2-4927.5" switch \rx_fifo_syncfifo_re - attribute \src "ls180.v:4926.6-4926.25" + attribute \src "ls180.v:4921.6-4921.25" case 1'1 assign $0\rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:4928.6-4928.10" + attribute \src "ls180.v:4923.6-4923.10" case - attribute \src "ls180.v:4929.3-4931.6" + attribute \src "ls180.v:4924.3-4926.6" switch \rx_fifo_re - attribute \src "ls180.v:4929.7-4929.17" + attribute \src "ls180.v:4924.7-4924.17" case 1'1 assign $0\rx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:4933.2-4935.5" - switch $and$ls180.v:4933$1420_Y - attribute \src "ls180.v:4933.6-4933.78" + attribute \src "ls180.v:4928.2-4930.5" + switch $and$ls180.v:4928$1424_Y + attribute \src "ls180.v:4928.6-4928.78" case 1'1 - assign $0\rx_fifo_produce[3:0] $add$ls180.v:4934$1421_Y + assign $0\rx_fifo_produce[3:0] $add$ls180.v:4929$1425_Y case end - attribute \src "ls180.v:4936.2-4938.5" + attribute \src "ls180.v:4931.2-4933.5" switch \rx_fifo_do_read - attribute \src "ls180.v:4936.6-4936.21" + attribute \src "ls180.v:4931.6-4931.21" case 1'1 - assign $0\rx_fifo_consume[3:0] $add$ls180.v:4937$1422_Y + assign $0\rx_fifo_consume[3:0] $add$ls180.v:4932$1426_Y case end - attribute \src "ls180.v:4939.2-4947.5" - switch $and$ls180.v:4939$1425_Y - attribute \src "ls180.v:4939.6-4939.78" + attribute \src "ls180.v:4934.2-4942.5" + switch $and$ls180.v:4934$1429_Y + attribute \src "ls180.v:4934.6-4934.78" case 1'1 - attribute \src "ls180.v:4940.3-4942.6" - switch $not$ls180.v:4940$1426_Y - attribute \src "ls180.v:4940.7-4940.25" + attribute \src "ls180.v:4935.3-4937.6" + switch $not$ls180.v:4935$1430_Y + attribute \src "ls180.v:4935.7-4935.25" case 1'1 - assign $0\rx_fifo_level0[4:0] $add$ls180.v:4941$1427_Y + assign $0\rx_fifo_level0[4:0] $add$ls180.v:4936$1431_Y case end - attribute \src "ls180.v:4943.6-4943.10" + attribute \src "ls180.v:4938.6-4938.10" case - attribute \src "ls180.v:4944.3-4946.6" + attribute \src "ls180.v:4939.3-4941.6" switch \rx_fifo_do_read - attribute \src "ls180.v:4944.7-4944.22" + attribute \src "ls180.v:4939.7-4939.22" case 1'1 - assign $0\rx_fifo_level0[4:0] $sub$ls180.v:4945$1428_Y + assign $0\rx_fifo_level0[4:0] $sub$ls180.v:4940$1432_Y case end end - attribute \src "ls180.v:4948.2-4961.5" + attribute \src "ls180.v:4943.2-4956.5" switch \reset - attribute \src "ls180.v:4948.6-4948.11" + attribute \src "ls180.v:4943.6-4943.11" case 1'1 assign $0\tx_pending[0:0] 1'0 assign $0\tx_old_trigger[0:0] 1'0 @@ -267780,45 +267609,45 @@ module \ls180 assign $0\rx_fifo_consume[3:0] 4'0000 case end - attribute \src "ls180.v:4963.2-4965.5" + attribute \src "ls180.v:4958.2-4960.5" switch \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 - attribute \src "ls180.v:4963.6-4963.62" + attribute \src "ls180.v:4958.6-4958.62" case 1'1 assign $0\libresocsim_libresocsim_dat_w[7:0] \libresocsim_libresocsim_dat_w_libresocsim_next_value0 case end - attribute \src "ls180.v:4966.2-4968.5" + attribute \src "ls180.v:4961.2-4963.5" switch \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 - attribute \src "ls180.v:4966.6-4966.60" + attribute \src "ls180.v:4961.6-4961.60" case 1'1 assign $0\libresocsim_libresocsim_adr[13:0] \libresocsim_libresocsim_adr_libresocsim_next_value1 case end - attribute \src "ls180.v:4969.2-4971.5" + attribute \src "ls180.v:4964.2-4966.5" switch \libresocsim_libresocsim_we_libresocsim_next_value_ce2 - attribute \src "ls180.v:4969.6-4969.59" + attribute \src "ls180.v:4964.6-4964.59" case 1'1 assign $0\libresocsim_libresocsim_we[0:0] \libresocsim_libresocsim_we_libresocsim_next_value2 case end - attribute \src "ls180.v:4972.2-5006.9" + attribute \src "ls180.v:4967.2-5001.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:4974.4-4982.7" - switch $not$ls180.v:4974$1429_Y - attribute \src "ls180.v:4974.8-4974.33" + attribute \src "ls180.v:4969.4-4977.7" + switch $not$ls180.v:4969$1433_Y + attribute \src "ls180.v:4969.8-4969.33" case 1'1 - attribute \src "ls180.v:4975.5-4981.8" + attribute \src "ls180.v:4970.5-4976.8" switch \libresocsim_request [1] - attribute \src "ls180.v:4975.9-4975.31" + attribute \src "ls180.v:4970.9-4970.31" case 1'1 assign $0\libresocsim_grant[1:0] 2'01 - attribute \src "ls180.v:4977.9-4977.13" + attribute \src "ls180.v:4972.9-4972.13" case - attribute \src "ls180.v:4978.6-4980.9" + attribute \src "ls180.v:4973.6-4975.9" switch \libresocsim_request [2] - attribute \src "ls180.v:4978.10-4978.32" + attribute \src "ls180.v:4973.10-4973.32" case 1'1 assign $0\libresocsim_grant[1:0] 2'10 case @@ -267828,20 +267657,20 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:4985.4-4993.7" - switch $not$ls180.v:4985$1430_Y - attribute \src "ls180.v:4985.8-4985.33" + attribute \src "ls180.v:4980.4-4988.7" + switch $not$ls180.v:4980$1434_Y + attribute \src "ls180.v:4980.8-4980.33" case 1'1 - attribute \src "ls180.v:4986.5-4992.8" + attribute \src "ls180.v:4981.5-4987.8" switch \libresocsim_request [2] - attribute \src "ls180.v:4986.9-4986.31" + attribute \src "ls180.v:4981.9-4981.31" case 1'1 assign $0\libresocsim_grant[1:0] 2'10 - attribute \src "ls180.v:4988.9-4988.13" + attribute \src "ls180.v:4983.9-4983.13" case - attribute \src "ls180.v:4989.6-4991.9" + attribute \src "ls180.v:4984.6-4986.9" switch \libresocsim_request [0] - attribute \src "ls180.v:4989.10-4989.32" + attribute \src "ls180.v:4984.10-4984.32" case 1'1 assign $0\libresocsim_grant[1:0] 2'00 case @@ -267851,20 +267680,20 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:4996.4-5004.7" - switch $not$ls180.v:4996$1431_Y - attribute \src "ls180.v:4996.8-4996.33" + attribute \src "ls180.v:4991.4-4999.7" + switch $not$ls180.v:4991$1435_Y + attribute \src "ls180.v:4991.8-4991.33" case 1'1 - attribute \src "ls180.v:4997.5-5003.8" + attribute \src "ls180.v:4992.5-4998.8" switch \libresocsim_request [0] - attribute \src "ls180.v:4997.9-4997.31" + attribute \src "ls180.v:4992.9-4992.31" case 1'1 assign $0\libresocsim_grant[1:0] 2'00 - attribute \src "ls180.v:4999.9-4999.13" + attribute \src "ls180.v:4994.9-4994.13" case - attribute \src "ls180.v:5000.6-5002.9" + attribute \src "ls180.v:4995.6-4997.9" switch \libresocsim_request [1] - attribute \src "ls180.v:5000.10-5000.32" + attribute \src "ls180.v:4995.10-4995.32" case 1'1 assign $0\libresocsim_grant[1:0] 2'01 case @@ -267874,26 +267703,26 @@ module \ls180 end case end - attribute \src "ls180.v:5008.2-5014.5" + attribute \src "ls180.v:5003.2-5009.5" switch \libresocsim_wait - attribute \src "ls180.v:5008.6-5008.22" + attribute \src "ls180.v:5003.6-5003.22" case 1'1 - attribute \src "ls180.v:5009.3-5011.6" - switch $not$ls180.v:5009$1432_Y - attribute \src "ls180.v:5009.7-5009.26" + attribute \src "ls180.v:5004.3-5006.6" + switch $not$ls180.v:5004$1436_Y + attribute \src "ls180.v:5004.7-5004.26" case 1'1 - assign $0\libresocsim_count[19:0] $sub$ls180.v:5010$1433_Y + assign $0\libresocsim_count[19:0] $sub$ls180.v:5005$1437_Y case end - attribute \src "ls180.v:5012.6-5012.10" + attribute \src "ls180.v:5007.6-5007.10" case assign $0\libresocsim_count[19:0] 20'11110100001001000000 end - attribute \src "ls180.v:5016.2-5046.5" + attribute \src "ls180.v:5011.2-5041.5" switch \libresocsim_csrbank0_sel - attribute \src "ls180.v:5016.6-5016.30" + attribute \src "ls180.v:5011.6-5011.30" case 1'1 - attribute \src "ls180.v:5017.3-5045.10" + attribute \src "ls180.v:5012.3-5040.10" switch \libresocsim_interface0_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -267926,46 +267755,46 @@ module \ls180 end case end - attribute \src "ls180.v:5047.2-5049.5" + attribute \src "ls180.v:5042.2-5044.5" switch \libresocsim_csrbank0_reset0_re - attribute \src "ls180.v:5047.6-5047.36" + attribute \src "ls180.v:5042.6-5042.36" case 1'1 assign $0\libresocsim_reset_storage[0:0] \libresocsim_csrbank0_reset0_r case end - attribute \src "ls180.v:5051.2-5053.5" + attribute \src "ls180.v:5046.2-5048.5" switch \libresocsim_csrbank0_scratch3_re - attribute \src "ls180.v:5051.6-5051.38" + attribute \src "ls180.v:5046.6-5046.38" case 1'1 assign $0\libresocsim_scratch_storage[31:0] [31:24] \libresocsim_csrbank0_scratch3_r case end - attribute \src "ls180.v:5054.2-5056.5" + attribute \src "ls180.v:5049.2-5051.5" switch \libresocsim_csrbank0_scratch2_re - attribute \src "ls180.v:5054.6-5054.38" + attribute \src "ls180.v:5049.6-5049.38" case 1'1 assign $0\libresocsim_scratch_storage[31:0] [23:16] \libresocsim_csrbank0_scratch2_r case end - attribute \src "ls180.v:5057.2-5059.5" + attribute \src "ls180.v:5052.2-5054.5" switch \libresocsim_csrbank0_scratch1_re - attribute \src "ls180.v:5057.6-5057.38" + attribute \src "ls180.v:5052.6-5052.38" case 1'1 assign $0\libresocsim_scratch_storage[31:0] [15:8] \libresocsim_csrbank0_scratch1_r case end - attribute \src "ls180.v:5060.2-5062.5" + attribute \src "ls180.v:5055.2-5057.5" switch \libresocsim_csrbank0_scratch0_re - attribute \src "ls180.v:5060.6-5060.38" + attribute \src "ls180.v:5055.6-5055.38" case 1'1 assign $0\libresocsim_scratch_storage[31:0] [7:0] \libresocsim_csrbank0_scratch0_r case end - attribute \src "ls180.v:5065.2-5077.5" + attribute \src "ls180.v:5060.2-5072.5" switch \libresocsim_csrbank1_sel - attribute \src "ls180.v:5065.6-5065.30" + attribute \src "ls180.v:5060.6-5060.30" case 1'1 - attribute \src "ls180.v:5066.3-5076.10" + attribute \src "ls180.v:5061.3-5071.10" switch \libresocsim_interface1_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -267980,25 +267809,25 @@ module \ls180 end case end - attribute \src "ls180.v:5078.2-5080.5" + attribute \src "ls180.v:5073.2-5075.5" switch \libresocsim_csrbank1_oe0_re - attribute \src "ls180.v:5078.6-5078.33" + attribute \src "ls180.v:5073.6-5073.33" case 1'1 assign $0\gpio0_oe_storage[7:0] \libresocsim_csrbank1_oe0_r case end - attribute \src "ls180.v:5082.2-5084.5" + attribute \src "ls180.v:5077.2-5079.5" switch \libresocsim_csrbank1_out0_re - attribute \src "ls180.v:5082.6-5082.34" + attribute \src "ls180.v:5077.6-5077.34" case 1'1 assign $0\gpio0_out_storage[7:0] \libresocsim_csrbank1_out0_r case end - attribute \src "ls180.v:5087.2-5099.5" + attribute \src "ls180.v:5082.2-5094.5" switch \libresocsim_csrbank2_sel - attribute \src "ls180.v:5087.6-5087.30" + attribute \src "ls180.v:5082.6-5082.30" case 1'1 - attribute \src "ls180.v:5088.3-5098.10" + attribute \src "ls180.v:5083.3-5093.10" switch \libresocsim_interface2_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268013,25 +267842,25 @@ module \ls180 end case end - attribute \src "ls180.v:5100.2-5102.5" + attribute \src "ls180.v:5095.2-5097.5" switch \libresocsim_csrbank2_oe0_re - attribute \src "ls180.v:5100.6-5100.33" + attribute \src "ls180.v:5095.6-5095.33" case 1'1 assign $0\gpio1_oe_storage[7:0] \libresocsim_csrbank2_oe0_r case end - attribute \src "ls180.v:5104.2-5106.5" + attribute \src "ls180.v:5099.2-5101.5" switch \libresocsim_csrbank2_out0_re - attribute \src "ls180.v:5104.6-5104.34" + attribute \src "ls180.v:5099.6-5099.34" case 1'1 assign $0\gpio1_out_storage[7:0] \libresocsim_csrbank2_out0_r case end - attribute \src "ls180.v:5109.2-5118.5" + attribute \src "ls180.v:5104.2-5113.5" switch \libresocsim_csrbank3_sel - attribute \src "ls180.v:5109.6-5109.30" + attribute \src "ls180.v:5104.6-5104.30" case 1'1 - attribute \src "ls180.v:5110.3-5117.10" + attribute \src "ls180.v:5105.3-5112.10" switch \libresocsim_interface3_bank_bus_adr [0] attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -268043,18 +267872,18 @@ module \ls180 end case end - attribute \src "ls180.v:5119.2-5121.5" + attribute \src "ls180.v:5114.2-5116.5" switch \libresocsim_csrbank3_w0_re - attribute \src "ls180.v:5119.6-5119.32" + attribute \src "ls180.v:5114.6-5114.32" case 1'1 assign $0\i2c_storage[2:0] \libresocsim_csrbank3_w0_r case end - attribute \src "ls180.v:5124.2-5157.5" + attribute \src "ls180.v:5119.2-5152.5" switch \libresocsim_csrbank4_sel - attribute \src "ls180.v:5124.6-5124.30" + attribute \src "ls180.v:5119.6-5119.30" case 1'1 - attribute \src "ls180.v:5125.3-5156.10" + attribute \src "ls180.v:5120.3-5151.10" switch \libresocsim_interface4_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -268090,60 +267919,60 @@ module \ls180 end case end - attribute \src "ls180.v:5158.2-5160.5" + attribute \src "ls180.v:5153.2-5155.5" switch \libresocsim_csrbank4_dfii_control0_re - attribute \src "ls180.v:5158.6-5158.43" + attribute \src "ls180.v:5153.6-5153.43" case 1'1 assign $0\sdram_storage[3:0] \libresocsim_csrbank4_dfii_control0_r case end - attribute \src "ls180.v:5162.2-5164.5" + attribute \src "ls180.v:5157.2-5159.5" switch \libresocsim_csrbank4_dfii_pi0_command0_re - attribute \src "ls180.v:5162.6-5162.47" + attribute \src "ls180.v:5157.6-5157.47" case 1'1 assign $0\sdram_command_storage[5:0] \libresocsim_csrbank4_dfii_pi0_command0_r case end - attribute \src "ls180.v:5166.2-5168.5" + attribute \src "ls180.v:5161.2-5163.5" switch \libresocsim_csrbank4_dfii_pi0_address1_re - attribute \src "ls180.v:5166.6-5166.47" + attribute \src "ls180.v:5161.6-5161.47" case 1'1 assign $0\sdram_address_storage[12:0] [12:8] \libresocsim_csrbank4_dfii_pi0_address1_r case end - attribute \src "ls180.v:5169.2-5171.5" + attribute \src "ls180.v:5164.2-5166.5" switch \libresocsim_csrbank4_dfii_pi0_address0_re - attribute \src "ls180.v:5169.6-5169.47" + attribute \src "ls180.v:5164.6-5164.47" case 1'1 assign $0\sdram_address_storage[12:0] [7:0] \libresocsim_csrbank4_dfii_pi0_address0_r case end - attribute \src "ls180.v:5173.2-5175.5" + attribute \src "ls180.v:5168.2-5170.5" switch \libresocsim_csrbank4_dfii_pi0_baddress0_re - attribute \src "ls180.v:5173.6-5173.48" + attribute \src "ls180.v:5168.6-5168.48" case 1'1 assign $0\sdram_baddress_storage[1:0] \libresocsim_csrbank4_dfii_pi0_baddress0_r case end - attribute \src "ls180.v:5177.2-5179.5" + attribute \src "ls180.v:5172.2-5174.5" switch \libresocsim_csrbank4_dfii_pi0_wrdata1_re - attribute \src "ls180.v:5177.6-5177.46" + attribute \src "ls180.v:5172.6-5172.46" case 1'1 assign $0\sdram_wrdata_storage[15:0] [15:8] \libresocsim_csrbank4_dfii_pi0_wrdata1_r case end - attribute \src "ls180.v:5180.2-5182.5" + attribute \src "ls180.v:5175.2-5177.5" switch \libresocsim_csrbank4_dfii_pi0_wrdata0_re - attribute \src "ls180.v:5180.6-5180.46" + attribute \src "ls180.v:5175.6-5175.46" case 1'1 assign $0\sdram_wrdata_storage[15:0] [7:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_r case end - attribute \src "ls180.v:5185.2-5239.5" + attribute \src "ls180.v:5180.2-5234.5" switch \libresocsim_csrbank5_sel - attribute \src "ls180.v:5185.6-5185.30" + attribute \src "ls180.v:5180.6-5180.30" case 1'1 - attribute \src "ls180.v:5186.3-5238.10" + attribute \src "ls180.v:5181.3-5233.10" switch \libresocsim_interface5_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -268200,88 +268029,88 @@ module \ls180 end case end - attribute \src "ls180.v:5240.2-5242.5" + attribute \src "ls180.v:5235.2-5237.5" switch \libresocsim_csrbank5_load3_re - attribute \src "ls180.v:5240.6-5240.35" + attribute \src "ls180.v:5235.6-5235.35" case 1'1 assign $0\libresocsim_load_storage[31:0] [31:24] \libresocsim_csrbank5_load3_r case end - attribute \src "ls180.v:5243.2-5245.5" + attribute \src "ls180.v:5238.2-5240.5" switch \libresocsim_csrbank5_load2_re - attribute \src "ls180.v:5243.6-5243.35" + attribute \src "ls180.v:5238.6-5238.35" case 1'1 assign $0\libresocsim_load_storage[31:0] [23:16] \libresocsim_csrbank5_load2_r case end - attribute \src "ls180.v:5246.2-5248.5" + attribute \src "ls180.v:5241.2-5243.5" switch \libresocsim_csrbank5_load1_re - attribute \src "ls180.v:5246.6-5246.35" + attribute \src "ls180.v:5241.6-5241.35" case 1'1 assign $0\libresocsim_load_storage[31:0] [15:8] \libresocsim_csrbank5_load1_r case end - attribute \src "ls180.v:5249.2-5251.5" + attribute \src "ls180.v:5244.2-5246.5" switch \libresocsim_csrbank5_load0_re - attribute \src "ls180.v:5249.6-5249.35" + attribute \src "ls180.v:5244.6-5244.35" case 1'1 assign $0\libresocsim_load_storage[31:0] [7:0] \libresocsim_csrbank5_load0_r case end - attribute \src "ls180.v:5253.2-5255.5" + attribute \src "ls180.v:5248.2-5250.5" switch \libresocsim_csrbank5_reload3_re - attribute \src "ls180.v:5253.6-5253.37" + attribute \src "ls180.v:5248.6-5248.37" case 1'1 assign $0\libresocsim_reload_storage[31:0] [31:24] \libresocsim_csrbank5_reload3_r case end - attribute \src "ls180.v:5256.2-5258.5" + attribute \src "ls180.v:5251.2-5253.5" switch \libresocsim_csrbank5_reload2_re - attribute \src "ls180.v:5256.6-5256.37" + attribute \src "ls180.v:5251.6-5251.37" case 1'1 assign $0\libresocsim_reload_storage[31:0] [23:16] \libresocsim_csrbank5_reload2_r case end - attribute \src "ls180.v:5259.2-5261.5" + attribute \src "ls180.v:5254.2-5256.5" switch \libresocsim_csrbank5_reload1_re - attribute \src "ls180.v:5259.6-5259.37" + attribute \src "ls180.v:5254.6-5254.37" case 1'1 assign $0\libresocsim_reload_storage[31:0] [15:8] \libresocsim_csrbank5_reload1_r case end - attribute \src "ls180.v:5262.2-5264.5" + attribute \src "ls180.v:5257.2-5259.5" switch \libresocsim_csrbank5_reload0_re - attribute \src "ls180.v:5262.6-5262.37" + attribute \src "ls180.v:5257.6-5257.37" case 1'1 assign $0\libresocsim_reload_storage[31:0] [7:0] \libresocsim_csrbank5_reload0_r case end - attribute \src "ls180.v:5266.2-5268.5" + attribute \src "ls180.v:5261.2-5263.5" switch \libresocsim_csrbank5_en0_re - attribute \src "ls180.v:5266.6-5266.33" + attribute \src "ls180.v:5261.6-5261.33" case 1'1 assign $0\libresocsim_en_storage[0:0] \libresocsim_csrbank5_en0_r case end - attribute \src "ls180.v:5270.2-5272.5" + attribute \src "ls180.v:5265.2-5267.5" switch \libresocsim_csrbank5_update_value0_re - attribute \src "ls180.v:5270.6-5270.43" + attribute \src "ls180.v:5265.6-5265.43" case 1'1 assign $0\libresocsim_update_value_storage[0:0] \libresocsim_csrbank5_update_value0_r case end - attribute \src "ls180.v:5274.2-5276.5" + attribute \src "ls180.v:5269.2-5271.5" switch \libresocsim_csrbank5_ev_enable0_re - attribute \src "ls180.v:5274.6-5274.40" + attribute \src "ls180.v:5269.6-5269.40" case 1'1 assign $0\libresocsim_eventmanager_storage[0:0] \libresocsim_csrbank5_ev_enable0_r case end - attribute \src "ls180.v:5279.2-5306.5" + attribute \src "ls180.v:5274.2-5301.5" switch \libresocsim_csrbank6_sel - attribute \src "ls180.v:5279.6-5279.30" + attribute \src "ls180.v:5274.6-5274.30" case 1'1 - attribute \src "ls180.v:5280.3-5305.10" + attribute \src "ls180.v:5275.3-5300.10" switch \libresocsim_interface6_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -268311,18 +268140,18 @@ module \ls180 end case end - attribute \src "ls180.v:5307.2-5309.5" + attribute \src "ls180.v:5302.2-5304.5" switch \libresocsim_csrbank6_ev_enable0_re - attribute \src "ls180.v:5307.6-5307.40" + attribute \src "ls180.v:5302.6-5302.40" case 1'1 assign $0\eventmanager_storage[1:0] \libresocsim_csrbank6_ev_enable0_r case end - attribute \src "ls180.v:5312.2-5327.5" + attribute \src "ls180.v:5307.2-5322.5" switch \libresocsim_csrbank7_sel - attribute \src "ls180.v:5312.6-5312.30" + attribute \src "ls180.v:5307.6-5307.30" case 1'1 - attribute \src "ls180.v:5313.3-5326.10" + attribute \src "ls180.v:5308.3-5321.10" switch \libresocsim_interface7_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268340,37 +268169,37 @@ module \ls180 end case end - attribute \src "ls180.v:5328.2-5330.5" + attribute \src "ls180.v:5323.2-5325.5" switch \libresocsim_csrbank7_tuning_word3_re - attribute \src "ls180.v:5328.6-5328.42" + attribute \src "ls180.v:5323.6-5323.42" case 1'1 assign $0\uart_phy_storage[31:0] [31:24] \libresocsim_csrbank7_tuning_word3_r case end - attribute \src "ls180.v:5331.2-5333.5" + attribute \src "ls180.v:5326.2-5328.5" switch \libresocsim_csrbank7_tuning_word2_re - attribute \src "ls180.v:5331.6-5331.42" + attribute \src "ls180.v:5326.6-5326.42" case 1'1 assign $0\uart_phy_storage[31:0] [23:16] \libresocsim_csrbank7_tuning_word2_r case end - attribute \src "ls180.v:5334.2-5336.5" + attribute \src "ls180.v:5329.2-5331.5" switch \libresocsim_csrbank7_tuning_word1_re - attribute \src "ls180.v:5334.6-5334.42" + attribute \src "ls180.v:5329.6-5329.42" case 1'1 assign $0\uart_phy_storage[31:0] [15:8] \libresocsim_csrbank7_tuning_word1_r case end - attribute \src "ls180.v:5337.2-5339.5" + attribute \src "ls180.v:5332.2-5334.5" switch \libresocsim_csrbank7_tuning_word0_re - attribute \src "ls180.v:5337.6-5337.42" + attribute \src "ls180.v:5332.6-5332.42" case 1'1 assign $0\uart_phy_storage[31:0] [7:0] \libresocsim_csrbank7_tuning_word0_r case end - attribute \src "ls180.v:5341.2-5488.5" + attribute \src "ls180.v:5336.2-5483.5" switch \sys_rst_1 - attribute \src "ls180.v:5341.6-5341.15" + attribute \src "ls180.v:5336.6-5336.15" case 1'1 assign $0\libresocsim_reset_storage[0:0] 1'0 assign $0\libresocsim_reset_re[0:0] 1'0 @@ -268495,7 +268324,7 @@ module \ls180 assign $0\gpio1_oe_re[0:0] 1'0 assign $0\gpio1_out_storage[7:0] 8'00000000 assign $0\gpio1_out_re[0:0] 1'0 - assign $0\dummy[35:0] 36'000000000000000000000000000000000000 + assign $0\dummy[39:0] 40'0000000000000000000000000000000000000000 assign $0\i2c_storage[2:0] 3'000 assign $0\i2c_re[0:0] 1'0 assign $0\subfragments_converter0_state[0:0] 1'0 @@ -268679,7 +268508,7 @@ module \ls180 update \gpio1_oe_re $0\gpio1_oe_re[0:0] update \gpio1_out_storage $0\gpio1_out_storage[7:0] update \gpio1_out_re $0\gpio1_out_re[0:0] - update \dummy $0\dummy[35:0] + update \dummy $0\dummy[39:0] update \i2c_storage $0\i2c_storage[2:0] update \i2c_re $0\i2c_re[0:0] update \subfragments_converter0_state $0\subfragments_converter0_state[0:0] @@ -268715,368 +268544,392 @@ module \ls180 update \regs0 $0\regs0[0:0] update \regs1 $0\regs1[0:0] end - attribute \src "ls180.v:429.5-429.61" - process $proc$ls180.v:429$1712 + attribute \src "ls180.v:43.5-43.32" + process $proc$ls180.v:43$1552 assign { } { } - assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\libresocsim_reset_re[0:0] 1'0 sync always - update \sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] sync init + update \libresocsim_reset_re $1\libresocsim_reset_re[0:0] end - attribute \src "ls180.v:444.11-444.63" - process $proc$ls180.v:444$1713 + attribute \src "ls180.v:438.11-438.63" + process $proc$ls180.v:438$1717 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \sdram_bankmachine0_cmd_buffer_lookahead_level $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:445.5-445.59" - process $proc$ls180.v:445$1714 + attribute \src "ls180.v:439.5-439.59" + process $proc$ls180.v:439$1718 assign { } { } assign $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \sdram_bankmachine0_cmd_buffer_lookahead_replace $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init end - attribute \src "ls180.v:446.11-446.65" - process $proc$ls180.v:446$1715 + attribute \src "ls180.v:44.12-44.55" + process $proc$ls180.v:44$1553 + assign { } { } + assign $1\libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \libresocsim_scratch_storage $1\libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:440.11-440.65" + process $proc$ls180.v:440$1719 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \sdram_bankmachine0_cmd_buffer_lookahead_produce $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:447.11-447.65" - process $proc$ls180.v:447$1716 + attribute \src "ls180.v:441.11-441.65" + process $proc$ls180.v:441$1720 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \sdram_bankmachine0_cmd_buffer_lookahead_consume $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:448.11-448.68" - process $proc$ls180.v:448$1717 + attribute \src "ls180.v:442.11-442.68" + process $proc$ls180.v:442$1721 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:45.5-45.37" - process $proc$ls180.v:45$1547 - assign { } { } - assign $1\libresocsim_reset_storage[0:0] 1'0 - sync always - sync init - update \libresocsim_reset_storage $1\libresocsim_reset_storage[0:0] - end - attribute \src "ls180.v:46.5-46.32" - process $proc$ls180.v:46$1548 + attribute \src "ls180.v:45.5-45.34" + process $proc$ls180.v:45$1554 assign { } { } - assign $1\libresocsim_reset_re[0:0] 1'0 + assign $1\libresocsim_scratch_re[0:0] 1'0 sync always sync init - update \libresocsim_reset_re $1\libresocsim_reset_re[0:0] + update \libresocsim_scratch_re $1\libresocsim_scratch_re[0:0] end - attribute \src "ls180.v:469.5-469.54" - process $proc$ls180.v:469$1718 + attribute \src "ls180.v:463.5-463.54" + process $proc$ls180.v:463$1722 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_buffer_source_valid $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:47.12-47.55" - process $proc$ls180.v:47$1549 - assign { } { } - assign $1\libresocsim_scratch_storage[31:0] 305419896 - sync always - sync init - update \libresocsim_scratch_storage $1\libresocsim_scratch_storage[31:0] - end - attribute \src "ls180.v:471.5-471.54" - process $proc$ls180.v:471$1719 + attribute \src "ls180.v:465.5-465.54" + process $proc$ls180.v:465$1723 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_buffer_source_first $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:472.5-472.53" - process $proc$ls180.v:472$1720 + attribute \src "ls180.v:466.5-466.53" + process $proc$ls180.v:466$1724 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_buffer_source_last $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:473.5-473.59" - process $proc$ls180.v:473$1721 + attribute \src "ls180.v:467.5-467.59" + process $proc$ls180.v:467$1725 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_buffer_source_payload_we $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:474.12-474.69" - process $proc$ls180.v:474$1722 + attribute \src "ls180.v:468.12-468.69" + process $proc$ls180.v:468$1726 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \sdram_bankmachine0_cmd_buffer_source_payload_addr $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:475.12-475.42" - process $proc$ls180.v:475$1723 + attribute \src "ls180.v:469.12-469.42" + process $proc$ls180.v:469$1727 assign { } { } assign $1\sdram_bankmachine0_row[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine0_row $1\sdram_bankmachine0_row[12:0] end - attribute \src "ls180.v:476.5-476.41" - process $proc$ls180.v:476$1724 + attribute \src "ls180.v:470.5-470.41" + process $proc$ls180.v:470$1728 assign { } { } assign $1\sdram_bankmachine0_row_opened[0:0] 1'0 sync always sync init update \sdram_bankmachine0_row_opened $1\sdram_bankmachine0_row_opened[0:0] end - attribute \src "ls180.v:478.5-478.39" - process $proc$ls180.v:478$1725 + attribute \src "ls180.v:472.5-472.39" + process $proc$ls180.v:472$1729 assign { } { } assign $1\sdram_bankmachine0_row_open[0:0] 1'0 sync always sync init update \sdram_bankmachine0_row_open $1\sdram_bankmachine0_row_open[0:0] end - attribute \src "ls180.v:479.5-479.40" - process $proc$ls180.v:479$1726 + attribute \src "ls180.v:473.5-473.40" + process $proc$ls180.v:473$1730 assign { } { } assign $1\sdram_bankmachine0_row_close[0:0] 1'0 sync always sync init update \sdram_bankmachine0_row_close $1\sdram_bankmachine0_row_close[0:0] end - attribute \src "ls180.v:48.5-48.34" - process $proc$ls180.v:48$1550 - assign { } { } - assign $1\libresocsim_scratch_re[0:0] 1'0 - sync always - sync init - update \libresocsim_scratch_re $1\libresocsim_scratch_re[0:0] - end - attribute \src "ls180.v:480.5-480.49" - process $proc$ls180.v:480$1727 + attribute \src "ls180.v:474.5-474.49" + process $proc$ls180.v:474$1731 assign { } { } assign $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \sdram_bankmachine0_row_col_n_addr_sel $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:482.32-482.71" - process $proc$ls180.v:482$1728 + attribute \src "ls180.v:476.32-476.71" + process $proc$ls180.v:476$1732 assign { } { } assign $1\sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine0_twtpcon_ready $1\sdram_bankmachine0_twtpcon_ready[0:0] end - attribute \src "ls180.v:483.11-483.50" - process $proc$ls180.v:483$1729 + attribute \src "ls180.v:477.11-477.50" + process $proc$ls180.v:477$1733 assign { } { } assign $1\sdram_bankmachine0_twtpcon_count[2:0] 3'000 sync always sync init update \sdram_bankmachine0_twtpcon_count $1\sdram_bankmachine0_twtpcon_count[2:0] end - attribute \src "ls180.v:485.32-485.70" - process $proc$ls180.v:485$1730 + attribute \src "ls180.v:479.32-479.70" + process $proc$ls180.v:479$1734 assign { } { } assign $0\sdram_bankmachine0_trccon_ready[0:0] 1'1 sync always update \sdram_bankmachine0_trccon_ready $0\sdram_bankmachine0_trccon_ready[0:0] sync init end - attribute \src "ls180.v:487.32-487.71" - process $proc$ls180.v:487$1731 + attribute \src "ls180.v:481.32-481.71" + process $proc$ls180.v:481$1735 assign { } { } assign $0\sdram_bankmachine0_trascon_ready[0:0] 1'1 sync always update \sdram_bankmachine0_trascon_ready $0\sdram_bankmachine0_trascon_ready[0:0] sync init end - attribute \src "ls180.v:493.5-493.46" - process $proc$ls180.v:493$1732 + attribute \src "ls180.v:487.5-487.46" + process $proc$ls180.v:487$1736 assign { } { } assign $1\sdram_bankmachine1_req_wdata_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine1_req_wdata_ready $1\sdram_bankmachine1_req_wdata_ready[0:0] end - attribute \src "ls180.v:494.5-494.46" - process $proc$ls180.v:494$1733 + attribute \src "ls180.v:488.5-488.46" + process $proc$ls180.v:488$1737 assign { } { } assign $1\sdram_bankmachine1_req_rdata_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine1_req_rdata_valid $1\sdram_bankmachine1_req_rdata_valid[0:0] end - attribute \src "ls180.v:496.5-496.42" - process $proc$ls180.v:496$1734 + attribute \src "ls180.v:490.5-490.42" + process $proc$ls180.v:490$1738 assign { } { } assign $1\sdram_bankmachine1_refresh_gnt[0:0] 1'0 sync always sync init update \sdram_bankmachine1_refresh_gnt $1\sdram_bankmachine1_refresh_gnt[0:0] end - attribute \src "ls180.v:497.5-497.40" - process $proc$ls180.v:497$1735 + attribute \src "ls180.v:491.5-491.40" + process $proc$ls180.v:491$1739 assign { } { } assign $1\sdram_bankmachine1_cmd_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_valid $1\sdram_bankmachine1_cmd_valid[0:0] end - attribute \src "ls180.v:498.5-498.40" - process $proc$ls180.v:498$1736 + attribute \src "ls180.v:492.5-492.40" + process $proc$ls180.v:492$1740 assign { } { } assign $1\sdram_bankmachine1_cmd_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_ready $1\sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:499.12-499.52" - process $proc$ls180.v:499$1737 + attribute \src "ls180.v:493.12-493.52" + process $proc$ls180.v:493$1741 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine1_cmd_payload_a $1\sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:501.5-501.46" - process $proc$ls180.v:501$1738 + attribute \src "ls180.v:495.5-495.46" + process $proc$ls180.v:495$1742 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_cas $1\sdram_bankmachine1_cmd_payload_cas[0:0] end - attribute \src "ls180.v:502.5-502.46" - process $proc$ls180.v:502$1739 + attribute \src "ls180.v:496.5-496.46" + process $proc$ls180.v:496$1743 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_ras $1\sdram_bankmachine1_cmd_payload_ras[0:0] end - attribute \src "ls180.v:503.5-503.45" - process $proc$ls180.v:503$1740 + attribute \src "ls180.v:497.5-497.45" + process $proc$ls180.v:497$1744 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_we $1\sdram_bankmachine1_cmd_payload_we[0:0] end - attribute \src "ls180.v:504.5-504.49" - process $proc$ls180.v:504$1741 + attribute \src "ls180.v:498.5-498.49" + process $proc$ls180.v:498$1745 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_is_cmd $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:505.5-505.50" - process $proc$ls180.v:505$1742 + attribute \src "ls180.v:499.5-499.50" + process $proc$ls180.v:499$1746 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_is_read $1\sdram_bankmachine1_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:506.5-506.51" - process $proc$ls180.v:506$1743 + attribute \src "ls180.v:50.12-50.42" + process $proc$ls180.v:50$1555 + assign { } { } + assign $1\libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \libresocsim_bus_errors $1\libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:500.5-500.51" + process $proc$ls180.v:500$1747 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_is_write $1\sdram_bankmachine1_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:507.5-507.45" - process $proc$ls180.v:507$1744 + attribute \src "ls180.v:501.5-501.45" + process $proc$ls180.v:501$1748 assign { } { } assign $1\sdram_bankmachine1_auto_precharge[0:0] 1'0 sync always sync init update \sdram_bankmachine1_auto_precharge $1\sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:510.5-510.62" - process $proc$ls180.v:510$1745 + attribute \src "ls180.v:504.5-504.62" + process $proc$ls180.v:504$1749 assign { } { } assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] sync init end - attribute \src "ls180.v:511.5-511.61" - process $proc$ls180.v:511$1746 + attribute \src "ls180.v:505.5-505.61" + process $proc$ls180.v:505$1750 assign { } { } assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] sync init end - attribute \src "ls180.v:526.11-526.63" - process $proc$ls180.v:526$1747 + attribute \src "ls180.v:52.12-52.50" + process $proc$ls180.v:52$1556 + assign { } { } + assign $1\libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_libresoc_interrupt $1\libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:520.11-520.63" + process $proc$ls180.v:520$1751 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \sdram_bankmachine1_cmd_buffer_lookahead_level $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:527.5-527.59" - process $proc$ls180.v:527$1748 + attribute \src "ls180.v:521.5-521.59" + process $proc$ls180.v:521$1752 assign { } { } assign $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \sdram_bankmachine1_cmd_buffer_lookahead_replace $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] sync init end - attribute \src "ls180.v:528.11-528.65" - process $proc$ls180.v:528$1749 + attribute \src "ls180.v:522.11-522.65" + process $proc$ls180.v:522$1753 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \sdram_bankmachine1_cmd_buffer_lookahead_produce $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:529.11-529.65" - process $proc$ls180.v:529$1750 + attribute \src "ls180.v:523.11-523.65" + process $proc$ls180.v:523$1754 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \sdram_bankmachine1_cmd_buffer_lookahead_consume $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:53.12-53.42" - process $proc$ls180.v:53$1551 + attribute \src "ls180.v:524.11-524.68" + process $proc$ls180.v:524$1755 assign { } { } - assign $1\libresocsim_bus_errors[31:0] 0 + assign $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \libresocsim_bus_errors $1\libresocsim_bus_errors[31:0] + update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:530.11-530.68" - process $proc$ls180.v:530$1751 + attribute \src "ls180.v:545.5-545.54" + process $proc$ls180.v:545$1756 assign { } { } - assign $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + update \sdram_bankmachine1_cmd_buffer_source_valid $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:5495.1-5505.4" - process $proc$ls180.v:5495$1434 + attribute \src "ls180.v:547.5-547.54" + process $proc$ls180.v:547$1757 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_first $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:548.5-548.53" + process $proc$ls180.v:548$1758 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_last $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:549.5-549.59" + process $proc$ls180.v:549$1759 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_payload_we $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:5490.1-5500.4" + process $proc$ls180.v:5490$1438 assign { } { } assign { } { } assign { } { } @@ -269102,120 +268955,120 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1435 $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 - assign $0$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1436 $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 - assign $0$memwr$\mem$ls180.v:5497$1_EN[31:0]$1437 $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 - assign $0$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1438 $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 - assign $0$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1439 $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 - assign $0$memwr$\mem$ls180.v:5499$2_EN[31:0]$1440 $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 - assign $0$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1441 $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 - assign $0$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1442 $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 - assign $0$memwr$\mem$ls180.v:5501$3_EN[31:0]$1443 $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 - assign $0$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1444 $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 - assign $0$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1445 $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 - assign $0$memwr$\mem$ls180.v:5503$4_EN[31:0]$1446 $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 + assign $0$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1439 $1$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1451 + assign $0$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1440 $1$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1452 + assign $0$memwr$\mem$ls180.v:5492$1_EN[31:0]$1441 $1$memwr$\mem$ls180.v:5492$1_EN[31:0]$1453 + assign $0$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1442 $1$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1454 + assign $0$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1443 $1$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1455 + assign $0$memwr$\mem$ls180.v:5494$2_EN[31:0]$1444 $1$memwr$\mem$ls180.v:5494$2_EN[31:0]$1456 + assign $0$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1445 $1$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1457 + assign $0$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1446 $1$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1458 + assign $0$memwr$\mem$ls180.v:5496$3_EN[31:0]$1447 $1$memwr$\mem$ls180.v:5496$3_EN[31:0]$1459 + assign $0$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1448 $1$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1460 + assign $0$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1449 $1$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1461 + assign $0$memwr$\mem$ls180.v:5498$4_EN[31:0]$1450 $1$memwr$\mem$ls180.v:5498$4_EN[31:0]$1462 assign $0\memadr[6:0] \libresocsim_adr - attribute \src "ls180.v:5496.2-5497.55" + attribute \src "ls180.v:5491.2-5492.55" switch \libresocsim_we [0] - attribute \src "ls180.v:5496.6-5496.23" + attribute \src "ls180.v:5491.6-5491.23" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 \libresocsim_adr - assign $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 { 24'000000000000000000000000 \libresocsim_dat_w [7:0] } - assign $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 255 + assign $1$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1451 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1452 { 24'000000000000000000000000 \libresocsim_dat_w [7:0] } + assign $1$memwr$\mem$ls180.v:5492$1_EN[31:0]$1453 255 case - assign $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 7'xxxxxxx - assign $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 0 + assign $1$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1451 7'xxxxxxx + assign $1$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1452 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5492$1_EN[31:0]$1453 0 end - attribute \src "ls180.v:5498.2-5499.57" + attribute \src "ls180.v:5493.2-5494.57" switch \libresocsim_we [1] - attribute \src "ls180.v:5498.6-5498.23" + attribute \src "ls180.v:5493.6-5493.23" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 \libresocsim_adr - assign $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 { 16'0000000000000000 \libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 65280 + assign $1$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1454 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1455 { 16'0000000000000000 \libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $1$memwr$\mem$ls180.v:5494$2_EN[31:0]$1456 65280 case - assign $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 7'xxxxxxx - assign $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 0 + assign $1$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1454 7'xxxxxxx + assign $1$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1455 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5494$2_EN[31:0]$1456 0 end - attribute \src "ls180.v:5500.2-5501.59" + attribute \src "ls180.v:5495.2-5496.59" switch \libresocsim_we [2] - attribute \src "ls180.v:5500.6-5500.23" + attribute \src "ls180.v:5495.6-5495.23" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 \libresocsim_adr - assign $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 { 8'00000000 \libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 16711680 + assign $1$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1457 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1458 { 8'00000000 \libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $1$memwr$\mem$ls180.v:5496$3_EN[31:0]$1459 16711680 case - assign $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 7'xxxxxxx - assign $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 0 + assign $1$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1457 7'xxxxxxx + assign $1$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1458 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5496$3_EN[31:0]$1459 0 end - attribute \src "ls180.v:5502.2-5503.59" + attribute \src "ls180.v:5497.2-5498.59" switch \libresocsim_we [3] - attribute \src "ls180.v:5502.6-5502.23" + attribute \src "ls180.v:5497.6-5497.23" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 \libresocsim_adr - assign $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 { \libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 32'11111111000000000000000000000000 + assign $1$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1460 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1461 { \libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem$ls180.v:5498$4_EN[31:0]$1462 32'11111111000000000000000000000000 case - assign $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 7'xxxxxxx - assign $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 0 + assign $1$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1460 7'xxxxxxx + assign $1$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1461 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5498$4_EN[31:0]$1462 0 end sync posedge \sys_clk_1 update \memadr $0\memadr[6:0] - update $memwr$\mem$ls180.v:5497$1_ADDR $0$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1435 - update $memwr$\mem$ls180.v:5497$1_DATA $0$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1436 - update $memwr$\mem$ls180.v:5497$1_EN $0$memwr$\mem$ls180.v:5497$1_EN[31:0]$1437 - update $memwr$\mem$ls180.v:5499$2_ADDR $0$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1438 - update $memwr$\mem$ls180.v:5499$2_DATA $0$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1439 - update $memwr$\mem$ls180.v:5499$2_EN $0$memwr$\mem$ls180.v:5499$2_EN[31:0]$1440 - update $memwr$\mem$ls180.v:5501$3_ADDR $0$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1441 - update $memwr$\mem$ls180.v:5501$3_DATA $0$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1442 - update $memwr$\mem$ls180.v:5501$3_EN $0$memwr$\mem$ls180.v:5501$3_EN[31:0]$1443 - update $memwr$\mem$ls180.v:5503$4_ADDR $0$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1444 - update $memwr$\mem$ls180.v:5503$4_DATA $0$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1445 - update $memwr$\mem$ls180.v:5503$4_EN $0$memwr$\mem$ls180.v:5503$4_EN[31:0]$1446 - attribute \src "ls180.v:5497.3-5497.54" - memwr \mem $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 0' - attribute \src "ls180.v:5499.3-5499.56" - memwr \mem $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 1'1 - attribute \src "ls180.v:5501.3-5501.58" - memwr \mem $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 2'11 - attribute \src "ls180.v:5503.3-5503.58" - memwr \mem $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 3'111 - end - attribute \src "ls180.v:55.12-55.50" - process $proc$ls180.v:55$1552 + update $memwr$\mem$ls180.v:5492$1_ADDR $0$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1439 + update $memwr$\mem$ls180.v:5492$1_DATA $0$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1440 + update $memwr$\mem$ls180.v:5492$1_EN $0$memwr$\mem$ls180.v:5492$1_EN[31:0]$1441 + update $memwr$\mem$ls180.v:5494$2_ADDR $0$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1442 + update $memwr$\mem$ls180.v:5494$2_DATA $0$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1443 + update $memwr$\mem$ls180.v:5494$2_EN $0$memwr$\mem$ls180.v:5494$2_EN[31:0]$1444 + update $memwr$\mem$ls180.v:5496$3_ADDR $0$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1445 + update $memwr$\mem$ls180.v:5496$3_DATA $0$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1446 + update $memwr$\mem$ls180.v:5496$3_EN $0$memwr$\mem$ls180.v:5496$3_EN[31:0]$1447 + update $memwr$\mem$ls180.v:5498$4_ADDR $0$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1448 + update $memwr$\mem$ls180.v:5498$4_DATA $0$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1449 + update $memwr$\mem$ls180.v:5498$4_EN $0$memwr$\mem$ls180.v:5498$4_EN[31:0]$1450 + attribute \src "ls180.v:5492.3-5492.54" + memwr \mem $1$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1451 $1$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1452 $1$memwr$\mem$ls180.v:5492$1_EN[31:0]$1453 0' + attribute \src "ls180.v:5494.3-5494.56" + memwr \mem $1$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1454 $1$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1455 $1$memwr$\mem$ls180.v:5494$2_EN[31:0]$1456 1'1 + attribute \src "ls180.v:5496.3-5496.58" + memwr \mem $1$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1457 $1$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1458 $1$memwr$\mem$ls180.v:5496$3_EN[31:0]$1459 2'11 + attribute \src "ls180.v:5498.3-5498.58" + memwr \mem $1$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1460 $1$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1461 $1$memwr$\mem$ls180.v:5498$4_EN[31:0]$1462 3'111 + end + attribute \src "ls180.v:550.12-550.69" + process $proc$ls180.v:550$1760 assign { } { } - assign $1\libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + assign $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \libresocsim_libresoc_interrupt $1\libresocsim_libresoc_interrupt[15:0] + update \sdram_bankmachine1_cmd_buffer_source_payload_addr $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:551.5-551.54" - process $proc$ls180.v:551$1752 + attribute \src "ls180.v:551.12-551.42" + process $proc$ls180.v:551$1761 assign { } { } - assign $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $1\sdram_bankmachine1_row[12:0] 13'0000000000000 sync always sync init - update \sdram_bankmachine1_cmd_buffer_source_valid $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \sdram_bankmachine1_row $1\sdram_bankmachine1_row[12:0] end - attribute \src "ls180.v:5515.1-5525.4" - process $proc$ls180.v:5515$1460 + attribute \src "ls180.v:5510.1-5520.4" + process $proc$ls180.v:5510$1464 assign { } { } assign { } { } assign { } { } @@ -269241,112 +269094,112 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1461 $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 - assign $0$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1462 $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 - assign $0$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1463 $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 - assign $0$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1464 $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 - assign $0$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1465 $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 - assign $0$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1466 $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 - assign $0$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1467 $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 - assign $0$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1468 $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 - assign $0$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1469 $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 - assign $0$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1470 $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 - assign $0$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1471 $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 - assign $0$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1472 $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 + assign $0$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1465 $1$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1477 + assign $0$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1466 $1$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1478 + assign $0$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1467 $1$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1479 + assign $0$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1468 $1$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1480 + assign $0$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1469 $1$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1481 + assign $0$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1470 $1$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1482 + assign $0$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1471 $1$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1483 + assign $0$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1472 $1$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1484 + assign $0$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1473 $1$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1485 + assign $0$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1474 $1$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1486 + assign $0$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1475 $1$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1487 + assign $0$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1476 $1$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1488 assign $0\memadr_1[4:0] \ram_adr - attribute \src "ls180.v:5516.2-5517.41" + attribute \src "ls180.v:5511.2-5512.41" switch \ram_we [0] - attribute \src "ls180.v:5516.6-5516.15" + attribute \src "ls180.v:5511.6-5511.15" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 \ram_adr - assign $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 { 24'000000000000000000000000 \ram_dat_w [7:0] } - assign $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 255 + assign $1$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1477 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1478 { 24'000000000000000000000000 \ram_dat_w [7:0] } + assign $1$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1479 255 case - assign $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 5'xxxxx - assign $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 0 + assign $1$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1477 5'xxxxx + assign $1$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1478 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1479 0 end - attribute \src "ls180.v:5518.2-5519.43" + attribute \src "ls180.v:5513.2-5514.43" switch \ram_we [1] - attribute \src "ls180.v:5518.6-5518.15" + attribute \src "ls180.v:5513.6-5513.15" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 \ram_adr - assign $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 { 16'0000000000000000 \ram_dat_w [15:8] 8'xxxxxxxx } - assign $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 65280 + assign $1$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1480 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1481 { 16'0000000000000000 \ram_dat_w [15:8] 8'xxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1482 65280 case - assign $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 5'xxxxx - assign $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 0 + assign $1$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1480 5'xxxxx + assign $1$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1481 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1482 0 end - attribute \src "ls180.v:5520.2-5521.45" + attribute \src "ls180.v:5515.2-5516.45" switch \ram_we [2] - attribute \src "ls180.v:5520.6-5520.15" + attribute \src "ls180.v:5515.6-5515.15" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 \ram_adr - assign $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 { 8'00000000 \ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 16711680 + assign $1$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1483 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1484 { 8'00000000 \ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1485 16711680 case - assign $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 5'xxxxx - assign $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 0 + assign $1$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1483 5'xxxxx + assign $1$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1484 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1485 0 end - attribute \src "ls180.v:5522.2-5523.45" + attribute \src "ls180.v:5517.2-5518.45" switch \ram_we [3] - attribute \src "ls180.v:5522.6-5522.15" + attribute \src "ls180.v:5517.6-5517.15" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 \ram_adr - assign $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 { \ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 32'11111111000000000000000000000000 + assign $1$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1486 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1487 { \ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1488 32'11111111000000000000000000000000 case - assign $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 5'xxxxx - assign $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 0 + assign $1$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1486 5'xxxxx + assign $1$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1487 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1488 0 end sync posedge \sys_clk_1 update \memadr_1 $0\memadr_1[4:0] - update $memwr$\mem_1$ls180.v:5517$5_ADDR $0$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1461 - update $memwr$\mem_1$ls180.v:5517$5_DATA $0$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1462 - update $memwr$\mem_1$ls180.v:5517$5_EN $0$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1463 - update $memwr$\mem_1$ls180.v:5519$6_ADDR $0$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1464 - update $memwr$\mem_1$ls180.v:5519$6_DATA $0$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1465 - update $memwr$\mem_1$ls180.v:5519$6_EN $0$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1466 - update $memwr$\mem_1$ls180.v:5521$7_ADDR $0$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1467 - update $memwr$\mem_1$ls180.v:5521$7_DATA $0$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1468 - update $memwr$\mem_1$ls180.v:5521$7_EN $0$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1469 - update $memwr$\mem_1$ls180.v:5523$8_ADDR $0$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1470 - update $memwr$\mem_1$ls180.v:5523$8_DATA $0$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1471 - update $memwr$\mem_1$ls180.v:5523$8_EN $0$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1472 - attribute \src "ls180.v:5517.3-5517.40" - memwr \mem_1 $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 0' - attribute \src "ls180.v:5519.3-5519.42" - memwr \mem_1 $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 1'1 - attribute \src "ls180.v:5521.3-5521.44" - memwr \mem_1 $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 2'11 - attribute \src "ls180.v:5523.3-5523.44" - memwr \mem_1 $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 3'111 - end - attribute \src "ls180.v:553.5-553.54" - process $proc$ls180.v:553$1753 + update $memwr$\mem_1$ls180.v:5512$5_ADDR $0$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1465 + update $memwr$\mem_1$ls180.v:5512$5_DATA $0$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1466 + update $memwr$\mem_1$ls180.v:5512$5_EN $0$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1467 + update $memwr$\mem_1$ls180.v:5514$6_ADDR $0$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1468 + update $memwr$\mem_1$ls180.v:5514$6_DATA $0$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1469 + update $memwr$\mem_1$ls180.v:5514$6_EN $0$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1470 + update $memwr$\mem_1$ls180.v:5516$7_ADDR $0$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1471 + update $memwr$\mem_1$ls180.v:5516$7_DATA $0$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1472 + update $memwr$\mem_1$ls180.v:5516$7_EN $0$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1473 + update $memwr$\mem_1$ls180.v:5518$8_ADDR $0$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1474 + update $memwr$\mem_1$ls180.v:5518$8_DATA $0$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1475 + update $memwr$\mem_1$ls180.v:5518$8_EN $0$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1476 + attribute \src "ls180.v:5512.3-5512.40" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1477 $1$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1478 $1$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1479 0' + attribute \src "ls180.v:5514.3-5514.42" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1480 $1$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1481 $1$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1482 1'1 + attribute \src "ls180.v:5516.3-5516.44" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1483 $1$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1484 $1$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1485 2'11 + attribute \src "ls180.v:5518.3-5518.44" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1486 $1$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1487 $1$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1488 3'111 + end + attribute \src "ls180.v:552.5-552.41" + process $proc$ls180.v:552$1762 assign { } { } - assign $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + assign $1\sdram_bankmachine1_row_opened[0:0] 1'0 sync always sync init - update \sdram_bankmachine1_cmd_buffer_source_first $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \sdram_bankmachine1_row_opened $1\sdram_bankmachine1_row_opened[0:0] end - attribute \src "ls180.v:5535.1-5539.4" - process $proc$ls180.v:5535$1486 + attribute \src "ls180.v:5530.1-5534.4" + process $proc$ls180.v:5530$1490 assign { } { } assign { } { } assign { } { } @@ -269354,47 +269207,47 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1487 $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 - assign $0$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1488 $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 - assign $0$memwr$\storage$ls180.v:5537$9_EN[24:0]$1489 $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:5538$1493_DATA - attribute \src "ls180.v:5536.2-5537.119" + assign $0$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1491 $1$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1494 + assign $0$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1492 $1$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1495 + assign $0$memwr$\storage$ls180.v:5532$9_EN[24:0]$1493 $1$memwr$\storage$ls180.v:5532$9_EN[24:0]$1496 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:5533$1497_DATA + attribute \src "ls180.v:5531.2-5532.119" switch \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:5536.6-5536.55" + attribute \src "ls180.v:5531.6-5531.55" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 25'1111111111111111111111111 + assign $1$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1494 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1495 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage$ls180.v:5532$9_EN[24:0]$1496 25'1111111111111111111111111 case - assign $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 3'xxx - assign $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 25'0000000000000000000000000 + assign $1$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1494 3'xxx + assign $1$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1495 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage$ls180.v:5532$9_EN[24:0]$1496 25'0000000000000000000000000 end sync posedge \sys_clk_1 update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:5537$9_ADDR $0$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1487 - update $memwr$\storage$ls180.v:5537$9_DATA $0$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1488 - update $memwr$\storage$ls180.v:5537$9_EN $0$memwr$\storage$ls180.v:5537$9_EN[24:0]$1489 - attribute \src "ls180.v:5537.3-5537.118" - memwr \storage $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 0' + update $memwr$\storage$ls180.v:5532$9_ADDR $0$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1491 + update $memwr$\storage$ls180.v:5532$9_DATA $0$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1492 + update $memwr$\storage$ls180.v:5532$9_EN $0$memwr$\storage$ls180.v:5532$9_EN[24:0]$1493 + attribute \src "ls180.v:5532.3-5532.118" + memwr \storage $1$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1494 $1$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1495 $1$memwr$\storage$ls180.v:5532$9_EN[24:0]$1496 0' + end + attribute \src "ls180.v:5536.1-5537.4" + process $proc$ls180.v:5536$1498 + sync posedge \sys_clk_1 end - attribute \src "ls180.v:554.5-554.53" - process $proc$ls180.v:554$1754 + attribute \src "ls180.v:554.5-554.39" + process $proc$ls180.v:554$1763 assign { } { } - assign $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + assign $1\sdram_bankmachine1_row_open[0:0] 1'0 sync always sync init - update \sdram_bankmachine1_cmd_buffer_source_last $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:5541.1-5542.4" - process $proc$ls180.v:5541$1494 - sync posedge \sys_clk_1 + update \sdram_bankmachine1_row_open $1\sdram_bankmachine1_row_open[0:0] end - attribute \src "ls180.v:5549.1-5553.4" - process $proc$ls180.v:5549$1496 + attribute \src "ls180.v:5544.1-5548.4" + process $proc$ls180.v:5544$1500 assign { } { } assign { } { } assign { } { } @@ -269402,55 +269255,47 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1497 $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 - assign $0$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1498 $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 - assign $0$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1499 $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:5552$1503_DATA - attribute \src "ls180.v:5550.2-5551.121" + assign $0$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1501 $1$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1504 + assign $0$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1502 $1$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1505 + assign $0$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1503 $1$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1506 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:5547$1507_DATA + attribute \src "ls180.v:5545.2-5546.121" switch \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:5550.6-5550.55" + attribute \src "ls180.v:5545.6-5545.55" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 25'1111111111111111111111111 + assign $1$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1504 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1505 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1506 25'1111111111111111111111111 case - assign $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 3'xxx - assign $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 25'0000000000000000000000000 + assign $1$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1504 3'xxx + assign $1$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1505 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1506 25'0000000000000000000000000 end sync posedge \sys_clk_1 update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:5551$10_ADDR $0$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1497 - update $memwr$\storage_1$ls180.v:5551$10_DATA $0$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1498 - update $memwr$\storage_1$ls180.v:5551$10_EN $0$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1499 - attribute \src "ls180.v:5551.3-5551.120" - memwr \storage_1 $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 0' + update $memwr$\storage_1$ls180.v:5546$10_ADDR $0$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1501 + update $memwr$\storage_1$ls180.v:5546$10_DATA $0$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1502 + update $memwr$\storage_1$ls180.v:5546$10_EN $0$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1503 + attribute \src "ls180.v:5546.3-5546.120" + memwr \storage_1 $1$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1504 $1$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1505 $1$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1506 0' end - attribute \src "ls180.v:555.5-555.59" - process $proc$ls180.v:555$1755 + attribute \src "ls180.v:555.5-555.40" + process $proc$ls180.v:555$1764 assign { } { } - assign $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + assign $1\sdram_bankmachine1_row_close[0:0] 1'0 sync always sync init - update \sdram_bankmachine1_cmd_buffer_source_payload_we $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \sdram_bankmachine1_row_close $1\sdram_bankmachine1_row_close[0:0] end - attribute \src "ls180.v:5555.1-5556.4" - process $proc$ls180.v:5555$1504 + attribute \src "ls180.v:5550.1-5551.4" + process $proc$ls180.v:5550$1508 sync posedge \sys_clk_1 end - attribute \src "ls180.v:556.12-556.69" - process $proc$ls180.v:556$1756 - assign { } { } - assign $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \sdram_bankmachine1_cmd_buffer_source_payload_addr $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:5563.1-5567.4" - process $proc$ls180.v:5563$1506 + attribute \src "ls180.v:5558.1-5562.4" + process $proc$ls180.v:5558$1510 assign { } { } assign { } { } assign { } { } @@ -269458,47 +269303,47 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1507 $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 - assign $0$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1508 $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 - assign $0$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1509 $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:5566$1513_DATA - attribute \src "ls180.v:5564.2-5565.121" + assign $0$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1511 $1$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1514 + assign $0$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1512 $1$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1515 + assign $0$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1513 $1$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1516 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:5561$1517_DATA + attribute \src "ls180.v:5559.2-5560.121" switch \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:5564.6-5564.55" + attribute \src "ls180.v:5559.6-5559.55" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 25'1111111111111111111111111 + assign $1$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1514 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1515 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1516 25'1111111111111111111111111 case - assign $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 3'xxx - assign $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 25'0000000000000000000000000 + assign $1$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1514 3'xxx + assign $1$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1515 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1516 25'0000000000000000000000000 end sync posedge \sys_clk_1 update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:5565$11_ADDR $0$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1507 - update $memwr$\storage_2$ls180.v:5565$11_DATA $0$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1508 - update $memwr$\storage_2$ls180.v:5565$11_EN $0$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1509 - attribute \src "ls180.v:5565.3-5565.120" - memwr \storage_2 $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 0' - end - attribute \src "ls180.v:5569.1-5570.4" - process $proc$ls180.v:5569$1514 - sync posedge \sys_clk_1 + update $memwr$\storage_2$ls180.v:5560$11_ADDR $0$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1511 + update $memwr$\storage_2$ls180.v:5560$11_DATA $0$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1512 + update $memwr$\storage_2$ls180.v:5560$11_EN $0$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1513 + attribute \src "ls180.v:5560.3-5560.120" + memwr \storage_2 $1$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1514 $1$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1515 $1$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1516 0' end - attribute \src "ls180.v:557.12-557.42" - process $proc$ls180.v:557$1757 + attribute \src "ls180.v:556.5-556.49" + process $proc$ls180.v:556$1765 assign { } { } - assign $1\sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \sdram_bankmachine1_row $1\sdram_bankmachine1_row[12:0] + update \sdram_bankmachine1_row_col_n_addr_sel $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:5577.1-5581.4" - process $proc$ls180.v:5577$1516 + attribute \src "ls180.v:5564.1-5565.4" + process $proc$ls180.v:5564$1518 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:5572.1-5576.4" + process $proc$ls180.v:5572$1520 assign { } { } assign { } { } assign { } { } @@ -269506,47 +269351,47 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1517 $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 - assign $0$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1518 $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 - assign $0$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1519 $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:5580$1523_DATA - attribute \src "ls180.v:5578.2-5579.121" + assign $0$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1521 $1$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1524 + assign $0$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1522 $1$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1525 + assign $0$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1523 $1$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1526 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:5575$1527_DATA + attribute \src "ls180.v:5573.2-5574.121" switch \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:5578.6-5578.55" + attribute \src "ls180.v:5573.6-5573.55" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 25'1111111111111111111111111 + assign $1$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1524 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1525 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1526 25'1111111111111111111111111 case - assign $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 3'xxx - assign $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 25'0000000000000000000000000 + assign $1$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1524 3'xxx + assign $1$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1525 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1526 25'0000000000000000000000000 end sync posedge \sys_clk_1 update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:5579$12_ADDR $0$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1517 - update $memwr$\storage_3$ls180.v:5579$12_DATA $0$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1518 - update $memwr$\storage_3$ls180.v:5579$12_EN $0$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1519 - attribute \src "ls180.v:5579.3-5579.120" - memwr \storage_3 $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 0' + update $memwr$\storage_3$ls180.v:5574$12_ADDR $0$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1521 + update $memwr$\storage_3$ls180.v:5574$12_DATA $0$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1522 + update $memwr$\storage_3$ls180.v:5574$12_EN $0$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1523 + attribute \src "ls180.v:5574.3-5574.120" + memwr \storage_3 $1$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1524 $1$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1525 $1$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1526 0' + end + attribute \src "ls180.v:5578.1-5579.4" + process $proc$ls180.v:5578$1528 + sync posedge \sys_clk_1 end - attribute \src "ls180.v:558.5-558.41" - process $proc$ls180.v:558$1758 + attribute \src "ls180.v:558.32-558.71" + process $proc$ls180.v:558$1766 assign { } { } - assign $1\sdram_bankmachine1_row_opened[0:0] 1'0 + assign $1\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 sync always sync init - update \sdram_bankmachine1_row_opened $1\sdram_bankmachine1_row_opened[0:0] - end - attribute \src "ls180.v:5583.1-5584.4" - process $proc$ls180.v:5583$1524 - sync posedge \sys_clk_1 + update \sdram_bankmachine1_twtpcon_ready $1\sdram_bankmachine1_twtpcon_ready[0:0] end - attribute \src "ls180.v:5592.1-5596.4" - process $proc$ls180.v:5592$1526 + attribute \src "ls180.v:5587.1-5591.4" + process $proc$ls180.v:5587$1530 assign { } { } assign { } { } assign { } { } @@ -269554,56 +269399,56 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1527 $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 - assign $0$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1528 $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 - assign $0$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1529 $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:5595$1533_DATA - attribute \src "ls180.v:5593.2-5594.57" + assign $0$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1531 $1$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1534 + assign $0$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1532 $1$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1535 + assign $0$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1533 $1$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1536 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:5590$1537_DATA + attribute \src "ls180.v:5588.2-5589.57" switch \tx_fifo_wrport_we - attribute \src "ls180.v:5593.6-5593.23" + attribute \src "ls180.v:5588.6-5588.23" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 \tx_fifo_wrport_adr - assign $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 \tx_fifo_wrport_dat_w - assign $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 10'1111111111 + assign $1$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1534 \tx_fifo_wrport_adr + assign $1$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1535 \tx_fifo_wrport_dat_w + assign $1$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1536 10'1111111111 case - assign $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 4'xxxx - assign $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 10'xxxxxxxxxx - assign $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 10'0000000000 + assign $1$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1534 4'xxxx + assign $1$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1535 10'xxxxxxxxxx + assign $1$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1536 10'0000000000 end sync posedge \sys_clk_1 update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:5594$13_ADDR $0$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1527 - update $memwr$\storage_4$ls180.v:5594$13_DATA $0$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1528 - update $memwr$\storage_4$ls180.v:5594$13_EN $0$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1529 - attribute \src "ls180.v:5594.3-5594.56" - memwr \storage_4 $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 0' - end - attribute \src "ls180.v:5598.1-5601.4" - process $proc$ls180.v:5598$1534 + update $memwr$\storage_4$ls180.v:5589$13_ADDR $0$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1531 + update $memwr$\storage_4$ls180.v:5589$13_DATA $0$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1532 + update $memwr$\storage_4$ls180.v:5589$13_EN $0$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1533 + attribute \src "ls180.v:5589.3-5589.56" + memwr \storage_4 $1$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1534 $1$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1535 $1$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1536 0' + end + attribute \src "ls180.v:559.11-559.50" + process $proc$ls180.v:559$1767 + assign { } { } + assign $1\sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine1_twtpcon_count $1\sdram_bankmachine1_twtpcon_count[2:0] + end + attribute \src "ls180.v:5593.1-5596.4" + process $proc$ls180.v:5593$1538 assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:5599.2-5600.45" + attribute \src "ls180.v:5594.2-5595.45" switch \tx_fifo_rdport_re - attribute \src "ls180.v:5599.6-5599.23" + attribute \src "ls180.v:5594.6-5594.23" case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:5600$1535_DATA + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:5595$1539_DATA case end sync posedge \sys_clk_1 update \memdat_5 $0\memdat_5[9:0] end - attribute \src "ls180.v:560.5-560.39" - process $proc$ls180.v:560$1759 - assign { } { } - assign $1\sdram_bankmachine1_row_open[0:0] 1'0 - sync always - sync init - update \sdram_bankmachine1_row_open $1\sdram_bankmachine1_row_open[0:0] - end - attribute \src "ls180.v:5609.1-5613.4" - process $proc$ls180.v:5609$1536 + attribute \src "ls180.v:5604.1-5608.4" + process $proc$ls180.v:5604$1540 assign { } { } assign { } { } assign { } { } @@ -269611,1559 +269456,1548 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1537 $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 - assign $0$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1538 $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 - assign $0$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1539 $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:5612$1543_DATA - attribute \src "ls180.v:5610.2-5611.57" + assign $0$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1541 $1$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1544 + assign $0$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1542 $1$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1545 + assign $0$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1543 $1$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1546 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:5607$1547_DATA + attribute \src "ls180.v:5605.2-5606.57" switch \rx_fifo_wrport_we - attribute \src "ls180.v:5610.6-5610.23" + attribute \src "ls180.v:5605.6-5605.23" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 \rx_fifo_wrport_adr - assign $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 \rx_fifo_wrport_dat_w - assign $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 10'1111111111 + assign $1$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1544 \rx_fifo_wrport_adr + assign $1$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1545 \rx_fifo_wrport_dat_w + assign $1$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1546 10'1111111111 case - assign $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 4'xxxx - assign $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 10'xxxxxxxxxx - assign $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 10'0000000000 + assign $1$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1544 4'xxxx + assign $1$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1545 10'xxxxxxxxxx + assign $1$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1546 10'0000000000 end sync posedge \sys_clk_1 update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:5611$14_ADDR $0$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1537 - update $memwr$\storage_5$ls180.v:5611$14_DATA $0$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1538 - update $memwr$\storage_5$ls180.v:5611$14_EN $0$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1539 - attribute \src "ls180.v:5611.3-5611.56" - memwr \storage_5 $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 0' + update $memwr$\storage_5$ls180.v:5606$14_ADDR $0$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1541 + update $memwr$\storage_5$ls180.v:5606$14_DATA $0$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1542 + update $memwr$\storage_5$ls180.v:5606$14_EN $0$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1543 + attribute \src "ls180.v:5606.3-5606.56" + memwr \storage_5 $1$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1544 $1$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1545 $1$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1546 0' end - attribute \src "ls180.v:561.5-561.40" - process $proc$ls180.v:561$1760 + attribute \src "ls180.v:561.32-561.70" + process $proc$ls180.v:561$1768 assign { } { } - assign $1\sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\sdram_bankmachine1_trccon_ready[0:0] 1'1 sync always + update \sdram_bankmachine1_trccon_ready $0\sdram_bankmachine1_trccon_ready[0:0] sync init - update \sdram_bankmachine1_row_close $1\sdram_bankmachine1_row_close[0:0] end - attribute \src "ls180.v:5615.1-5618.4" - process $proc$ls180.v:5615$1544 + attribute \src "ls180.v:5610.1-5613.4" + process $proc$ls180.v:5610$1548 assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:5616.2-5617.45" + attribute \src "ls180.v:5611.2-5612.45" switch \rx_fifo_rdport_re - attribute \src "ls180.v:5616.6-5616.23" + attribute \src "ls180.v:5611.6-5611.23" case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:5617$1545_DATA + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:5612$1549_DATA case end sync posedge \sys_clk_1 update \memdat_7 $0\memdat_7[9:0] end - attribute \src "ls180.v:562.5-562.49" - process $proc$ls180.v:562$1761 - assign { } { } - assign $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \sdram_bankmachine1_row_col_n_addr_sel $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:564.32-564.71" - process $proc$ls180.v:564$1762 - assign { } { } - assign $1\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \sdram_bankmachine1_twtpcon_ready $1\sdram_bankmachine1_twtpcon_ready[0:0] - end - attribute \src "ls180.v:565.11-565.50" - process $proc$ls180.v:565$1763 - assign { } { } - assign $1\sdram_bankmachine1_twtpcon_count[2:0] 3'000 - sync always - sync init - update \sdram_bankmachine1_twtpcon_count $1\sdram_bankmachine1_twtpcon_count[2:0] - end - attribute \src "ls180.v:567.32-567.70" - process $proc$ls180.v:567$1764 - assign { } { } - assign $0\sdram_bankmachine1_trccon_ready[0:0] 1'1 - sync always - update \sdram_bankmachine1_trccon_ready $0\sdram_bankmachine1_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:569.32-569.71" - process $proc$ls180.v:569$1765 + attribute \src "ls180.v:563.32-563.71" + process $proc$ls180.v:563$1769 assign { } { } assign $0\sdram_bankmachine1_trascon_ready[0:0] 1'1 sync always update \sdram_bankmachine1_trascon_ready $0\sdram_bankmachine1_trascon_ready[0:0] sync init end - attribute \src "ls180.v:575.5-575.46" - process $proc$ls180.v:575$1766 + attribute \src "ls180.v:569.5-569.46" + process $proc$ls180.v:569$1770 assign { } { } assign $1\sdram_bankmachine2_req_wdata_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine2_req_wdata_ready $1\sdram_bankmachine2_req_wdata_ready[0:0] end - attribute \src "ls180.v:576.5-576.46" - process $proc$ls180.v:576$1767 + attribute \src "ls180.v:570.5-570.46" + process $proc$ls180.v:570$1771 assign { } { } assign $1\sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine2_req_rdata_valid $1\sdram_bankmachine2_req_rdata_valid[0:0] end - attribute \src "ls180.v:578.5-578.42" - process $proc$ls180.v:578$1768 + attribute \src "ls180.v:572.5-572.42" + process $proc$ls180.v:572$1772 assign { } { } assign $1\sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always sync init update \sdram_bankmachine2_refresh_gnt $1\sdram_bankmachine2_refresh_gnt[0:0] end - attribute \src "ls180.v:579.5-579.40" - process $proc$ls180.v:579$1769 + attribute \src "ls180.v:573.5-573.40" + process $proc$ls180.v:573$1773 assign { } { } assign $1\sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_valid $1\sdram_bankmachine2_cmd_valid[0:0] end - attribute \src "ls180.v:580.5-580.40" - process $proc$ls180.v:580$1770 + attribute \src "ls180.v:574.5-574.40" + process $proc$ls180.v:574$1774 assign { } { } assign $1\sdram_bankmachine2_cmd_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_ready $1\sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:581.12-581.52" - process $proc$ls180.v:581$1771 + attribute \src "ls180.v:575.12-575.52" + process $proc$ls180.v:575$1775 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine2_cmd_payload_a $1\sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:583.5-583.46" - process $proc$ls180.v:583$1772 + attribute \src "ls180.v:577.5-577.46" + process $proc$ls180.v:577$1776 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_cas $1\sdram_bankmachine2_cmd_payload_cas[0:0] end - attribute \src "ls180.v:584.5-584.46" - process $proc$ls180.v:584$1773 + attribute \src "ls180.v:578.5-578.46" + process $proc$ls180.v:578$1777 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_ras $1\sdram_bankmachine2_cmd_payload_ras[0:0] end - attribute \src "ls180.v:585.5-585.45" - process $proc$ls180.v:585$1774 + attribute \src "ls180.v:579.5-579.45" + process $proc$ls180.v:579$1778 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_we $1\sdram_bankmachine2_cmd_payload_we[0:0] end - attribute \src "ls180.v:586.5-586.49" - process $proc$ls180.v:586$1775 + attribute \src "ls180.v:580.5-580.49" + process $proc$ls180.v:580$1779 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_is_cmd $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:587.5-587.50" - process $proc$ls180.v:587$1776 + attribute \src "ls180.v:581.5-581.50" + process $proc$ls180.v:581$1780 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_is_read $1\sdram_bankmachine2_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:588.5-588.51" - process $proc$ls180.v:588$1777 + attribute \src "ls180.v:582.5-582.51" + process $proc$ls180.v:582$1781 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_is_write $1\sdram_bankmachine2_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:589.5-589.45" - process $proc$ls180.v:589$1778 + attribute \src "ls180.v:583.5-583.45" + process $proc$ls180.v:583$1782 assign { } { } assign $1\sdram_bankmachine2_auto_precharge[0:0] 1'0 sync always sync init update \sdram_bankmachine2_auto_precharge $1\sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:592.5-592.62" - process $proc$ls180.v:592$1779 + attribute \src "ls180.v:586.5-586.62" + process $proc$ls180.v:586$1783 assign { } { } assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] sync init end - attribute \src "ls180.v:593.5-593.61" - process $proc$ls180.v:593$1780 + attribute \src "ls180.v:587.5-587.61" + process $proc$ls180.v:587$1784 assign { } { } assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] sync init end - attribute \src "ls180.v:608.11-608.63" - process $proc$ls180.v:608$1781 + attribute \src "ls180.v:59.5-59.41" + process $proc$ls180.v:59$1557 + assign { } { } + assign $1\libresocsim_libresoc_dbus_ack[0:0] 1'0 + sync always + sync init + update \libresocsim_libresoc_dbus_ack $1\libresocsim_libresoc_dbus_ack[0:0] + end + attribute \src "ls180.v:602.11-602.63" + process $proc$ls180.v:602$1785 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \sdram_bankmachine2_cmd_buffer_lookahead_level $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:609.5-609.59" - process $proc$ls180.v:609$1782 + attribute \src "ls180.v:603.5-603.59" + process $proc$ls180.v:603$1786 assign { } { } assign $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \sdram_bankmachine2_cmd_buffer_lookahead_replace $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init end - attribute \src "ls180.v:610.11-610.65" - process $proc$ls180.v:610$1783 + attribute \src "ls180.v:604.11-604.65" + process $proc$ls180.v:604$1787 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \sdram_bankmachine2_cmd_buffer_lookahead_produce $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:611.11-611.65" - process $proc$ls180.v:611$1784 + attribute \src "ls180.v:605.11-605.65" + process $proc$ls180.v:605$1788 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \sdram_bankmachine2_cmd_buffer_lookahead_consume $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:612.11-612.68" - process $proc$ls180.v:612$1785 + attribute \src "ls180.v:606.11-606.68" + process $proc$ls180.v:606$1789 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:62.5-62.41" - process $proc$ls180.v:62$1553 + attribute \src "ls180.v:61.5-61.41" + process $proc$ls180.v:61$1558 assign { } { } - assign $1\libresocsim_libresoc_dbus_ack[0:0] 1'0 + assign $0\libresocsim_libresoc_dbus_err[0:0] 1'0 sync always + update \libresocsim_libresoc_dbus_err $0\libresocsim_libresoc_dbus_err[0:0] sync init - update \libresocsim_libresoc_dbus_ack $1\libresocsim_libresoc_dbus_ack[0:0] end - attribute \src "ls180.v:633.5-633.54" - process $proc$ls180.v:633$1786 + attribute \src "ls180.v:627.5-627.54" + process $proc$ls180.v:627$1790 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_buffer_source_valid $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:635.5-635.54" - process $proc$ls180.v:635$1787 + attribute \src "ls180.v:629.5-629.54" + process $proc$ls180.v:629$1791 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_buffer_source_first $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:636.5-636.53" - process $proc$ls180.v:636$1788 + attribute \src "ls180.v:630.5-630.53" + process $proc$ls180.v:630$1792 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_buffer_source_last $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:637.5-637.59" - process $proc$ls180.v:637$1789 + attribute \src "ls180.v:631.5-631.59" + process $proc$ls180.v:631$1793 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_buffer_source_payload_we $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:638.12-638.69" - process $proc$ls180.v:638$1790 + attribute \src "ls180.v:632.12-632.69" + process $proc$ls180.v:632$1794 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \sdram_bankmachine2_cmd_buffer_source_payload_addr $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:639.12-639.42" - process $proc$ls180.v:639$1791 + attribute \src "ls180.v:633.12-633.42" + process $proc$ls180.v:633$1795 assign { } { } assign $1\sdram_bankmachine2_row[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine2_row $1\sdram_bankmachine2_row[12:0] end - attribute \src "ls180.v:64.5-64.41" - process $proc$ls180.v:64$1554 - assign { } { } - assign $0\libresocsim_libresoc_dbus_err[0:0] 1'0 - sync always - update \libresocsim_libresoc_dbus_err $0\libresocsim_libresoc_dbus_err[0:0] - sync init - end - attribute \src "ls180.v:640.5-640.41" - process $proc$ls180.v:640$1792 + attribute \src "ls180.v:634.5-634.41" + process $proc$ls180.v:634$1796 assign { } { } assign $1\sdram_bankmachine2_row_opened[0:0] 1'0 sync always sync init update \sdram_bankmachine2_row_opened $1\sdram_bankmachine2_row_opened[0:0] end - attribute \src "ls180.v:642.5-642.39" - process $proc$ls180.v:642$1793 + attribute \src "ls180.v:636.5-636.39" + process $proc$ls180.v:636$1797 assign { } { } assign $1\sdram_bankmachine2_row_open[0:0] 1'0 sync always sync init update \sdram_bankmachine2_row_open $1\sdram_bankmachine2_row_open[0:0] end - attribute \src "ls180.v:643.5-643.40" - process $proc$ls180.v:643$1794 + attribute \src "ls180.v:637.5-637.40" + process $proc$ls180.v:637$1798 assign { } { } assign $1\sdram_bankmachine2_row_close[0:0] 1'0 sync always sync init update \sdram_bankmachine2_row_close $1\sdram_bankmachine2_row_close[0:0] end - attribute \src "ls180.v:644.5-644.49" - process $proc$ls180.v:644$1795 + attribute \src "ls180.v:638.5-638.49" + process $proc$ls180.v:638$1799 assign { } { } assign $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \sdram_bankmachine2_row_col_n_addr_sel $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:646.32-646.71" - process $proc$ls180.v:646$1796 + attribute \src "ls180.v:640.32-640.71" + process $proc$ls180.v:640$1800 assign { } { } assign $1\sdram_bankmachine2_twtpcon_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine2_twtpcon_ready $1\sdram_bankmachine2_twtpcon_ready[0:0] end - attribute \src "ls180.v:647.11-647.50" - process $proc$ls180.v:647$1797 + attribute \src "ls180.v:641.11-641.50" + process $proc$ls180.v:641$1801 assign { } { } assign $1\sdram_bankmachine2_twtpcon_count[2:0] 3'000 sync always sync init update \sdram_bankmachine2_twtpcon_count $1\sdram_bankmachine2_twtpcon_count[2:0] end - attribute \src "ls180.v:649.32-649.70" - process $proc$ls180.v:649$1798 + attribute \src "ls180.v:643.32-643.70" + process $proc$ls180.v:643$1802 assign { } { } assign $0\sdram_bankmachine2_trccon_ready[0:0] 1'1 sync always update \sdram_bankmachine2_trccon_ready $0\sdram_bankmachine2_trccon_ready[0:0] sync init end - attribute \src "ls180.v:651.32-651.71" - process $proc$ls180.v:651$1799 + attribute \src "ls180.v:645.32-645.71" + process $proc$ls180.v:645$1803 assign { } { } assign $0\sdram_bankmachine2_trascon_ready[0:0] 1'1 sync always update \sdram_bankmachine2_trascon_ready $0\sdram_bankmachine2_trascon_ready[0:0] sync init end - attribute \src "ls180.v:657.5-657.46" - process $proc$ls180.v:657$1800 + attribute \src "ls180.v:651.5-651.46" + process $proc$ls180.v:651$1804 assign { } { } assign $1\sdram_bankmachine3_req_wdata_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine3_req_wdata_ready $1\sdram_bankmachine3_req_wdata_ready[0:0] end - attribute \src "ls180.v:658.5-658.46" - process $proc$ls180.v:658$1801 + attribute \src "ls180.v:652.5-652.46" + process $proc$ls180.v:652$1805 assign { } { } assign $1\sdram_bankmachine3_req_rdata_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine3_req_rdata_valid $1\sdram_bankmachine3_req_rdata_valid[0:0] end - attribute \src "ls180.v:660.5-660.42" - process $proc$ls180.v:660$1802 + attribute \src "ls180.v:654.5-654.42" + process $proc$ls180.v:654$1806 assign { } { } assign $1\sdram_bankmachine3_refresh_gnt[0:0] 1'0 sync always sync init update \sdram_bankmachine3_refresh_gnt $1\sdram_bankmachine3_refresh_gnt[0:0] end - attribute \src "ls180.v:661.5-661.40" - process $proc$ls180.v:661$1803 + attribute \src "ls180.v:655.5-655.40" + process $proc$ls180.v:655$1807 assign { } { } assign $1\sdram_bankmachine3_cmd_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_valid $1\sdram_bankmachine3_cmd_valid[0:0] end - attribute \src "ls180.v:662.5-662.40" - process $proc$ls180.v:662$1804 + attribute \src "ls180.v:656.5-656.40" + process $proc$ls180.v:656$1808 assign { } { } assign $1\sdram_bankmachine3_cmd_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_ready $1\sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:663.12-663.52" - process $proc$ls180.v:663$1805 + attribute \src "ls180.v:657.12-657.52" + process $proc$ls180.v:657$1809 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine3_cmd_payload_a $1\sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:665.5-665.46" - process $proc$ls180.v:665$1806 + attribute \src "ls180.v:659.5-659.46" + process $proc$ls180.v:659$1810 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_cas $1\sdram_bankmachine3_cmd_payload_cas[0:0] end - attribute \src "ls180.v:666.5-666.46" - process $proc$ls180.v:666$1807 + attribute \src "ls180.v:660.5-660.46" + process $proc$ls180.v:660$1811 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_ras $1\sdram_bankmachine3_cmd_payload_ras[0:0] end - attribute \src "ls180.v:667.5-667.45" - process $proc$ls180.v:667$1808 + attribute \src "ls180.v:661.5-661.45" + process $proc$ls180.v:661$1812 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_we $1\sdram_bankmachine3_cmd_payload_we[0:0] end - attribute \src "ls180.v:668.5-668.49" - process $proc$ls180.v:668$1809 + attribute \src "ls180.v:662.5-662.49" + process $proc$ls180.v:662$1813 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_is_cmd $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:669.5-669.50" - process $proc$ls180.v:669$1810 + attribute \src "ls180.v:663.5-663.50" + process $proc$ls180.v:663$1814 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_is_read $1\sdram_bankmachine3_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:670.5-670.51" - process $proc$ls180.v:670$1811 + attribute \src "ls180.v:664.5-664.51" + process $proc$ls180.v:664$1815 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_is_write $1\sdram_bankmachine3_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:671.5-671.45" - process $proc$ls180.v:671$1812 + attribute \src "ls180.v:665.5-665.45" + process $proc$ls180.v:665$1816 assign { } { } assign $1\sdram_bankmachine3_auto_precharge[0:0] 1'0 sync always sync init update \sdram_bankmachine3_auto_precharge $1\sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:674.5-674.62" - process $proc$ls180.v:674$1813 + attribute \src "ls180.v:668.5-668.62" + process $proc$ls180.v:668$1817 assign { } { } assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] sync init end - attribute \src "ls180.v:675.5-675.61" - process $proc$ls180.v:675$1814 + attribute \src "ls180.v:669.5-669.61" + process $proc$ls180.v:669$1818 assign { } { } assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init end - attribute \src "ls180.v:690.11-690.63" - process $proc$ls180.v:690$1815 + attribute \src "ls180.v:68.5-68.41" + process $proc$ls180.v:68$1559 + assign { } { } + assign $1\libresocsim_libresoc_ibus_ack[0:0] 1'0 + sync always + sync init + update \libresocsim_libresoc_ibus_ack $1\libresocsim_libresoc_ibus_ack[0:0] + end + attribute \src "ls180.v:684.11-684.63" + process $proc$ls180.v:684$1819 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \sdram_bankmachine3_cmd_buffer_lookahead_level $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:691.5-691.59" - process $proc$ls180.v:691$1816 + attribute \src "ls180.v:685.5-685.59" + process $proc$ls180.v:685$1820 assign { } { } assign $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \sdram_bankmachine3_cmd_buffer_lookahead_replace $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] sync init end - attribute \src "ls180.v:692.11-692.65" - process $proc$ls180.v:692$1817 + attribute \src "ls180.v:686.11-686.65" + process $proc$ls180.v:686$1821 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \sdram_bankmachine3_cmd_buffer_lookahead_produce $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:693.11-693.65" - process $proc$ls180.v:693$1818 + attribute \src "ls180.v:687.11-687.65" + process $proc$ls180.v:687$1822 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \sdram_bankmachine3_cmd_buffer_lookahead_consume $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:694.11-694.68" - process $proc$ls180.v:694$1819 + attribute \src "ls180.v:688.11-688.68" + process $proc$ls180.v:688$1823 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:71.5-71.41" - process $proc$ls180.v:71$1555 + attribute \src "ls180.v:70.5-70.41" + process $proc$ls180.v:70$1560 assign { } { } - assign $1\libresocsim_libresoc_ibus_ack[0:0] 1'0 + assign $0\libresocsim_libresoc_ibus_err[0:0] 1'0 sync always + update \libresocsim_libresoc_ibus_err $0\libresocsim_libresoc_ibus_err[0:0] sync init - update \libresocsim_libresoc_ibus_ack $1\libresocsim_libresoc_ibus_ack[0:0] end - attribute \src "ls180.v:715.5-715.54" - process $proc$ls180.v:715$1820 + attribute \src "ls180.v:709.5-709.54" + process $proc$ls180.v:709$1824 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_buffer_source_valid $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:717.5-717.54" - process $proc$ls180.v:717$1821 + attribute \src "ls180.v:711.5-711.54" + process $proc$ls180.v:711$1825 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_buffer_source_first $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:718.5-718.53" - process $proc$ls180.v:718$1822 + attribute \src "ls180.v:712.5-712.53" + process $proc$ls180.v:712$1826 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_buffer_source_last $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:719.5-719.59" - process $proc$ls180.v:719$1823 + attribute \src "ls180.v:713.5-713.59" + process $proc$ls180.v:713$1827 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_buffer_source_payload_we $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:720.12-720.69" - process $proc$ls180.v:720$1824 + attribute \src "ls180.v:714.12-714.69" + process $proc$ls180.v:714$1828 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \sdram_bankmachine3_cmd_buffer_source_payload_addr $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:721.12-721.42" - process $proc$ls180.v:721$1825 + attribute \src "ls180.v:715.12-715.42" + process $proc$ls180.v:715$1829 assign { } { } assign $1\sdram_bankmachine3_row[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine3_row $1\sdram_bankmachine3_row[12:0] end - attribute \src "ls180.v:722.5-722.41" - process $proc$ls180.v:722$1826 + attribute \src "ls180.v:716.5-716.41" + process $proc$ls180.v:716$1830 assign { } { } assign $1\sdram_bankmachine3_row_opened[0:0] 1'0 sync always sync init update \sdram_bankmachine3_row_opened $1\sdram_bankmachine3_row_opened[0:0] end - attribute \src "ls180.v:724.5-724.39" - process $proc$ls180.v:724$1827 + attribute \src "ls180.v:718.5-718.39" + process $proc$ls180.v:718$1831 assign { } { } assign $1\sdram_bankmachine3_row_open[0:0] 1'0 sync always sync init update \sdram_bankmachine3_row_open $1\sdram_bankmachine3_row_open[0:0] end - attribute \src "ls180.v:725.5-725.40" - process $proc$ls180.v:725$1828 + attribute \src "ls180.v:719.5-719.40" + process $proc$ls180.v:719$1832 assign { } { } assign $1\sdram_bankmachine3_row_close[0:0] 1'0 sync always sync init update \sdram_bankmachine3_row_close $1\sdram_bankmachine3_row_close[0:0] end - attribute \src "ls180.v:726.5-726.49" - process $proc$ls180.v:726$1829 + attribute \src "ls180.v:720.5-720.49" + process $proc$ls180.v:720$1833 assign { } { } assign $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \sdram_bankmachine3_row_col_n_addr_sel $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:728.32-728.71" - process $proc$ls180.v:728$1830 + attribute \src "ls180.v:722.32-722.71" + process $proc$ls180.v:722$1834 assign { } { } assign $1\sdram_bankmachine3_twtpcon_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine3_twtpcon_ready $1\sdram_bankmachine3_twtpcon_ready[0:0] end - attribute \src "ls180.v:729.11-729.50" - process $proc$ls180.v:729$1831 + attribute \src "ls180.v:723.11-723.50" + process $proc$ls180.v:723$1835 assign { } { } assign $1\sdram_bankmachine3_twtpcon_count[2:0] 3'000 sync always sync init update \sdram_bankmachine3_twtpcon_count $1\sdram_bankmachine3_twtpcon_count[2:0] end - attribute \src "ls180.v:73.5-73.41" - process $proc$ls180.v:73$1556 - assign { } { } - assign $0\libresocsim_libresoc_ibus_err[0:0] 1'0 - sync always - update \libresocsim_libresoc_ibus_err $0\libresocsim_libresoc_ibus_err[0:0] - sync init - end - attribute \src "ls180.v:731.32-731.70" - process $proc$ls180.v:731$1832 + attribute \src "ls180.v:725.32-725.70" + process $proc$ls180.v:725$1836 assign { } { } assign $0\sdram_bankmachine3_trccon_ready[0:0] 1'1 sync always update \sdram_bankmachine3_trccon_ready $0\sdram_bankmachine3_trccon_ready[0:0] sync init end - attribute \src "ls180.v:733.32-733.71" - process $proc$ls180.v:733$1833 + attribute \src "ls180.v:727.32-727.71" + process $proc$ls180.v:727$1837 assign { } { } assign $0\sdram_bankmachine3_trascon_ready[0:0] 1'1 sync always update \sdram_bankmachine3_trascon_ready $0\sdram_bankmachine3_trascon_ready[0:0] sync init end - attribute \src "ls180.v:736.5-736.39" - process $proc$ls180.v:736$1834 + attribute \src "ls180.v:730.5-730.39" + process $proc$ls180.v:730$1838 assign { } { } assign $0\sdram_choose_cmd_want_reads[0:0] 1'0 sync always update \sdram_choose_cmd_want_reads $0\sdram_choose_cmd_want_reads[0:0] sync init end - attribute \src "ls180.v:737.5-737.40" - process $proc$ls180.v:737$1835 + attribute \src "ls180.v:731.5-731.40" + process $proc$ls180.v:731$1839 assign { } { } assign $0\sdram_choose_cmd_want_writes[0:0] 1'0 sync always update \sdram_choose_cmd_want_writes $0\sdram_choose_cmd_want_writes[0:0] sync init end - attribute \src "ls180.v:738.5-738.38" - process $proc$ls180.v:738$1836 + attribute \src "ls180.v:732.5-732.38" + process $proc$ls180.v:732$1840 assign { } { } assign $0\sdram_choose_cmd_want_cmds[0:0] 1'0 sync always update \sdram_choose_cmd_want_cmds $0\sdram_choose_cmd_want_cmds[0:0] sync init end - attribute \src "ls180.v:739.5-739.43" - process $proc$ls180.v:739$1837 + attribute \src "ls180.v:733.5-733.43" + process $proc$ls180.v:733$1841 assign { } { } assign $0\sdram_choose_cmd_want_activates[0:0] 1'0 sync always update \sdram_choose_cmd_want_activates $0\sdram_choose_cmd_want_activates[0:0] sync init end - attribute \src "ls180.v:741.5-741.38" - process $proc$ls180.v:741$1838 + attribute \src "ls180.v:735.5-735.38" + process $proc$ls180.v:735$1842 assign { } { } assign $0\sdram_choose_cmd_cmd_ready[0:0] 1'0 sync always update \sdram_choose_cmd_cmd_ready $0\sdram_choose_cmd_cmd_ready[0:0] sync init end - attribute \src "ls180.v:744.5-744.44" - process $proc$ls180.v:744$1839 + attribute \src "ls180.v:738.5-738.44" + process $proc$ls180.v:738$1843 assign { } { } assign $1\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_choose_cmd_cmd_payload_cas $1\sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:745.5-745.44" - process $proc$ls180.v:745$1840 + attribute \src "ls180.v:739.5-739.44" + process $proc$ls180.v:739$1844 assign { } { } assign $1\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_choose_cmd_cmd_payload_ras $1\sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:746.5-746.43" - process $proc$ls180.v:746$1841 + attribute \src "ls180.v:740.5-740.43" + process $proc$ls180.v:740$1845 assign { } { } assign $1\sdram_choose_cmd_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_choose_cmd_cmd_payload_we $1\sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:750.11-750.41" - process $proc$ls180.v:750$1842 + attribute \src "ls180.v:744.11-744.41" + process $proc$ls180.v:744$1846 assign { } { } assign $1\sdram_choose_cmd_valids[3:0] 4'0000 sync always sync init update \sdram_choose_cmd_valids $1\sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:752.11-752.40" - process $proc$ls180.v:752$1843 + attribute \src "ls180.v:746.11-746.40" + process $proc$ls180.v:746$1847 assign { } { } assign $1\sdram_choose_cmd_grant[1:0] 2'00 sync always sync init update \sdram_choose_cmd_grant $1\sdram_choose_cmd_grant[1:0] end - attribute \src "ls180.v:754.5-754.39" - process $proc$ls180.v:754$1844 + attribute \src "ls180.v:748.5-748.39" + process $proc$ls180.v:748$1848 assign { } { } assign $1\sdram_choose_req_want_reads[0:0] 1'0 sync always sync init update \sdram_choose_req_want_reads $1\sdram_choose_req_want_reads[0:0] end - attribute \src "ls180.v:755.5-755.40" - process $proc$ls180.v:755$1845 + attribute \src "ls180.v:749.5-749.40" + process $proc$ls180.v:749$1849 assign { } { } assign $1\sdram_choose_req_want_writes[0:0] 1'0 sync always sync init update \sdram_choose_req_want_writes $1\sdram_choose_req_want_writes[0:0] end - attribute \src "ls180.v:757.5-757.43" - process $proc$ls180.v:757$1846 + attribute \src "ls180.v:751.5-751.43" + process $proc$ls180.v:751$1850 assign { } { } assign $1\sdram_choose_req_want_activates[0:0] 1'0 sync always sync init update \sdram_choose_req_want_activates $1\sdram_choose_req_want_activates[0:0] end - attribute \src "ls180.v:759.5-759.38" - process $proc$ls180.v:759$1847 + attribute \src "ls180.v:753.5-753.38" + process $proc$ls180.v:753$1851 assign { } { } assign $1\sdram_choose_req_cmd_ready[0:0] 1'0 sync always sync init update \sdram_choose_req_cmd_ready $1\sdram_choose_req_cmd_ready[0:0] end - attribute \src "ls180.v:762.5-762.44" - process $proc$ls180.v:762$1848 + attribute \src "ls180.v:756.5-756.44" + process $proc$ls180.v:756$1852 assign { } { } assign $1\sdram_choose_req_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_choose_req_cmd_payload_cas $1\sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:763.5-763.44" - process $proc$ls180.v:763$1849 + attribute \src "ls180.v:757.5-757.44" + process $proc$ls180.v:757$1853 assign { } { } assign $1\sdram_choose_req_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_choose_req_cmd_payload_ras $1\sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:764.5-764.43" - process $proc$ls180.v:764$1850 + attribute \src "ls180.v:758.5-758.43" + process $proc$ls180.v:758$1854 assign { } { } assign $1\sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_choose_req_cmd_payload_we $1\sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:768.11-768.41" - process $proc$ls180.v:768$1851 + attribute \src "ls180.v:762.11-762.41" + process $proc$ls180.v:762$1855 assign { } { } assign $1\sdram_choose_req_valids[3:0] 4'0000 sync always sync init update \sdram_choose_req_valids $1\sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:770.11-770.40" - process $proc$ls180.v:770$1852 + attribute \src "ls180.v:764.11-764.40" + process $proc$ls180.v:764$1856 assign { } { } assign $1\sdram_choose_req_grant[1:0] 2'00 sync always sync init update \sdram_choose_req_grant $1\sdram_choose_req_grant[1:0] end - attribute \src "ls180.v:772.12-772.31" - process $proc$ls180.v:772$1853 + attribute \src "ls180.v:766.12-766.31" + process $proc$ls180.v:766$1857 assign { } { } assign $0\sdram_nop_a[12:0] 13'0000000000000 sync always update \sdram_nop_a $0\sdram_nop_a[12:0] sync init end - attribute \src "ls180.v:773.11-773.30" - process $proc$ls180.v:773$1854 + attribute \src "ls180.v:767.11-767.30" + process $proc$ls180.v:767$1858 assign { } { } assign $0\sdram_nop_ba[1:0] 2'00 sync always update \sdram_nop_ba $0\sdram_nop_ba[1:0] sync init end - attribute \src "ls180.v:774.11-774.35" - process $proc$ls180.v:774$1855 + attribute \src "ls180.v:768.11-768.35" + process $proc$ls180.v:768$1859 assign { } { } assign $1\sdram_steerer_sel[1:0] 2'00 sync always sync init update \sdram_steerer_sel $1\sdram_steerer_sel[1:0] end - attribute \src "ls180.v:775.5-775.26" - process $proc$ls180.v:775$1856 + attribute \src "ls180.v:769.5-769.26" + process $proc$ls180.v:769$1860 assign { } { } assign $0\sdram_steerer0[0:0] 1'1 sync always update \sdram_steerer0 $0\sdram_steerer0[0:0] sync init end - attribute \src "ls180.v:776.5-776.26" - process $proc$ls180.v:776$1857 + attribute \src "ls180.v:770.5-770.26" + process $proc$ls180.v:770$1861 assign { } { } assign $0\sdram_steerer1[0:0] 1'1 sync always update \sdram_steerer1 $0\sdram_steerer1[0:0] sync init end - attribute \src "ls180.v:778.32-778.58" - process $proc$ls180.v:778$1858 + attribute \src "ls180.v:772.32-772.58" + process $proc$ls180.v:772$1862 assign { } { } assign $0\sdram_trrdcon_ready[0:0] 1'1 sync always update \sdram_trrdcon_ready $0\sdram_trrdcon_ready[0:0] sync init end - attribute \src "ls180.v:780.32-780.58" - process $proc$ls180.v:780$1859 + attribute \src "ls180.v:774.32-774.58" + process $proc$ls180.v:774$1863 assign { } { } assign $0\sdram_tfawcon_ready[0:0] 1'1 sync always update \sdram_tfawcon_ready $0\sdram_tfawcon_ready[0:0] sync init end - attribute \src "ls180.v:782.32-782.58" - process $proc$ls180.v:782$1860 + attribute \src "ls180.v:776.32-776.58" + process $proc$ls180.v:776$1864 assign { } { } assign $1\sdram_tccdcon_ready[0:0] 1'0 sync always sync init update \sdram_tccdcon_ready $1\sdram_tccdcon_ready[0:0] end - attribute \src "ls180.v:783.5-783.31" - process $proc$ls180.v:783$1861 + attribute \src "ls180.v:777.5-777.31" + process $proc$ls180.v:777$1865 assign { } { } assign $1\sdram_tccdcon_count[0:0] 1'0 sync always sync init update \sdram_tccdcon_count $1\sdram_tccdcon_count[0:0] end - attribute \src "ls180.v:785.32-785.58" - process $proc$ls180.v:785$1862 + attribute \src "ls180.v:779.32-779.58" + process $proc$ls180.v:779$1866 assign { } { } assign $1\sdram_twtrcon_ready[0:0] 1'0 sync always sync init update \sdram_twtrcon_ready $1\sdram_twtrcon_ready[0:0] end - attribute \src "ls180.v:786.11-786.37" - process $proc$ls180.v:786$1863 + attribute \src "ls180.v:780.11-780.37" + process $proc$ls180.v:780$1867 assign { } { } assign $1\sdram_twtrcon_count[2:0] 3'000 sync always sync init update \sdram_twtrcon_count $1\sdram_twtrcon_count[2:0] end - attribute \src "ls180.v:789.5-789.21" - process $proc$ls180.v:789$1864 + attribute \src "ls180.v:783.5-783.21" + process $proc$ls180.v:783$1868 assign { } { } assign $1\sdram_en0[0:0] 1'0 sync always sync init update \sdram_en0 $1\sdram_en0[0:0] end - attribute \src "ls180.v:791.11-791.29" - process $proc$ls180.v:791$1865 + attribute \src "ls180.v:785.11-785.29" + process $proc$ls180.v:785$1869 assign { } { } assign $1\sdram_time0[4:0] 5'00000 sync always sync init update \sdram_time0 $1\sdram_time0[4:0] end - attribute \src "ls180.v:792.5-792.21" - process $proc$ls180.v:792$1866 + attribute \src "ls180.v:786.5-786.21" + process $proc$ls180.v:786$1870 assign { } { } assign $1\sdram_en1[0:0] 1'0 sync always sync init update \sdram_en1 $1\sdram_en1[0:0] end - attribute \src "ls180.v:794.11-794.29" - process $proc$ls180.v:794$1867 + attribute \src "ls180.v:788.11-788.29" + process $proc$ls180.v:788$1871 assign { } { } assign $1\sdram_time1[3:0] 4'0000 sync always sync init update \sdram_time1 $1\sdram_time1[3:0] end - attribute \src "ls180.v:815.5-815.24" - process $proc$ls180.v:815$1868 + attribute \src "ls180.v:809.5-809.24" + process $proc$ls180.v:809$1872 assign { } { } assign $1\wb_sdram_ack[0:0] 1'0 sync always sync init update \wb_sdram_ack $1\wb_sdram_ack[0:0] end - attribute \src "ls180.v:819.5-819.24" - process $proc$ls180.v:819$1869 + attribute \src "ls180.v:813.5-813.24" + process $proc$ls180.v:813$1873 assign { } { } assign $0\wb_sdram_err[0:0] 1'0 sync always update \wb_sdram_err $0\wb_sdram_err[0:0] sync init end - attribute \src "ls180.v:820.12-820.35" - process $proc$ls180.v:820$1870 + attribute \src "ls180.v:814.12-814.35" + process $proc$ls180.v:814$1874 assign { } { } assign $1\litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \litedram_wb_adr $1\litedram_wb_adr[29:0] end - attribute \src "ls180.v:821.12-821.37" - process $proc$ls180.v:821$1871 + attribute \src "ls180.v:815.12-815.37" + process $proc$ls180.v:815$1875 assign { } { } assign $1\litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init update \litedram_wb_dat_w $1\litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:823.11-823.33" - process $proc$ls180.v:823$1872 + attribute \src "ls180.v:817.11-817.33" + process $proc$ls180.v:817$1876 assign { } { } assign $1\litedram_wb_sel[1:0] 2'00 sync always sync init update \litedram_wb_sel $1\litedram_wb_sel[1:0] end - attribute \src "ls180.v:824.5-824.27" - process $proc$ls180.v:824$1873 + attribute \src "ls180.v:818.5-818.27" + process $proc$ls180.v:818$1877 assign { } { } assign $1\litedram_wb_cyc[0:0] 1'0 sync always sync init update \litedram_wb_cyc $1\litedram_wb_cyc[0:0] end - attribute \src "ls180.v:825.5-825.27" - process $proc$ls180.v:825$1874 + attribute \src "ls180.v:819.5-819.27" + process $proc$ls180.v:819$1878 assign { } { } assign $1\litedram_wb_stb[0:0] 1'0 sync always sync init update \litedram_wb_stb $1\litedram_wb_stb[0:0] end - attribute \src "ls180.v:827.5-827.26" - process $proc$ls180.v:827$1875 + attribute \src "ls180.v:821.5-821.26" + process $proc$ls180.v:821$1879 assign { } { } assign $1\litedram_wb_we[0:0] 1'0 sync always sync init update \litedram_wb_we $1\litedram_wb_we[0:0] end - attribute \src "ls180.v:828.5-828.26" - process $proc$ls180.v:828$1876 + attribute \src "ls180.v:822.5-822.26" + process $proc$ls180.v:822$1880 assign { } { } assign $1\converter_skip[0:0] 1'0 sync always sync init update \converter_skip $1\converter_skip[0:0] end - attribute \src "ls180.v:829.5-829.29" - process $proc$ls180.v:829$1877 + attribute \src "ls180.v:823.5-823.29" + process $proc$ls180.v:823$1881 assign { } { } assign $1\converter_counter[0:0] 1'0 sync always sync init update \converter_counter $1\converter_counter[0:0] end - attribute \src "ls180.v:831.12-831.35" - process $proc$ls180.v:831$1878 + attribute \src "ls180.v:825.12-825.35" + process $proc$ls180.v:825$1882 assign { } { } assign $1\converter_dat_r[31:0] 0 sync always sync init update \converter_dat_r $1\converter_dat_r[31:0] end - attribute \src "ls180.v:832.5-832.24" - process $proc$ls180.v:832$1879 + attribute \src "ls180.v:826.5-826.24" + process $proc$ls180.v:826$1883 assign { } { } assign $1\cmd_consumed[0:0] 1'0 sync always sync init update \cmd_consumed $1\cmd_consumed[0:0] end - attribute \src "ls180.v:833.5-833.26" - process $proc$ls180.v:833$1880 + attribute \src "ls180.v:827.5-827.26" + process $proc$ls180.v:827$1884 assign { } { } assign $1\wdata_consumed[0:0] 1'0 sync always sync init update \wdata_consumed $1\wdata_consumed[0:0] end - attribute \src "ls180.v:837.12-837.42" - process $proc$ls180.v:837$1881 + attribute \src "ls180.v:831.12-831.42" + process $proc$ls180.v:831$1885 assign { } { } assign $1\uart_phy_storage[31:0] 9895604 sync always sync init update \uart_phy_storage $1\uart_phy_storage[31:0] end - attribute \src "ls180.v:838.5-838.23" - process $proc$ls180.v:838$1882 + attribute \src "ls180.v:832.5-832.23" + process $proc$ls180.v:832$1886 assign { } { } assign $1\uart_phy_re[0:0] 1'0 sync always sync init update \uart_phy_re $1\uart_phy_re[0:0] end - attribute \src "ls180.v:840.5-840.31" - process $proc$ls180.v:840$1883 + attribute \src "ls180.v:834.5-834.31" + process $proc$ls180.v:834$1887 assign { } { } assign $1\uart_phy_sink_ready[0:0] 1'0 sync always sync init update \uart_phy_sink_ready $1\uart_phy_sink_ready[0:0] end - attribute \src "ls180.v:844.5-844.34" - process $proc$ls180.v:844$1884 + attribute \src "ls180.v:838.5-838.34" + process $proc$ls180.v:838$1888 assign { } { } assign $1\uart_phy_uart_clk_txen[0:0] 1'0 sync always sync init update \uart_phy_uart_clk_txen $1\uart_phy_uart_clk_txen[0:0] end - attribute \src "ls180.v:845.12-845.49" - process $proc$ls180.v:845$1885 + attribute \src "ls180.v:839.12-839.49" + process $proc$ls180.v:839$1889 assign { } { } assign $1\uart_phy_phase_accumulator_tx[31:0] 0 sync always sync init update \uart_phy_phase_accumulator_tx $1\uart_phy_phase_accumulator_tx[31:0] end - attribute \src "ls180.v:846.11-846.33" - process $proc$ls180.v:846$1886 + attribute \src "ls180.v:840.11-840.33" + process $proc$ls180.v:840$1890 assign { } { } assign $1\uart_phy_tx_reg[7:0] 8'00000000 sync always sync init update \uart_phy_tx_reg $1\uart_phy_tx_reg[7:0] end - attribute \src "ls180.v:847.11-847.38" - process $proc$ls180.v:847$1887 + attribute \src "ls180.v:841.11-841.38" + process $proc$ls180.v:841$1891 assign { } { } assign $1\uart_phy_tx_bitcount[3:0] 4'0000 sync always sync init update \uart_phy_tx_bitcount $1\uart_phy_tx_bitcount[3:0] end - attribute \src "ls180.v:848.5-848.28" - process $proc$ls180.v:848$1888 + attribute \src "ls180.v:842.5-842.28" + process $proc$ls180.v:842$1892 assign { } { } assign $1\uart_phy_tx_busy[0:0] 1'0 sync always sync init update \uart_phy_tx_busy $1\uart_phy_tx_busy[0:0] end - attribute \src "ls180.v:849.5-849.33" - process $proc$ls180.v:849$1889 + attribute \src "ls180.v:843.5-843.33" + process $proc$ls180.v:843$1893 assign { } { } assign $1\uart_phy_source_valid[0:0] 1'0 sync always sync init update \uart_phy_source_valid $1\uart_phy_source_valid[0:0] end - attribute \src "ls180.v:851.5-851.33" - process $proc$ls180.v:851$1890 + attribute \src "ls180.v:845.5-845.33" + process $proc$ls180.v:845$1894 assign { } { } assign $0\uart_phy_source_first[0:0] 1'0 sync always update \uart_phy_source_first $0\uart_phy_source_first[0:0] sync init end - attribute \src "ls180.v:852.5-852.32" - process $proc$ls180.v:852$1891 + attribute \src "ls180.v:846.5-846.32" + process $proc$ls180.v:846$1895 assign { } { } assign $0\uart_phy_source_last[0:0] 1'0 sync always update \uart_phy_source_last $0\uart_phy_source_last[0:0] sync init end - attribute \src "ls180.v:853.11-853.46" - process $proc$ls180.v:853$1892 + attribute \src "ls180.v:847.11-847.46" + process $proc$ls180.v:847$1896 assign { } { } assign $1\uart_phy_source_payload_data[7:0] 8'00000000 sync always sync init update \uart_phy_source_payload_data $1\uart_phy_source_payload_data[7:0] end - attribute \src "ls180.v:854.5-854.34" - process $proc$ls180.v:854$1893 + attribute \src "ls180.v:848.5-848.34" + process $proc$ls180.v:848$1897 assign { } { } assign $1\uart_phy_uart_clk_rxen[0:0] 1'0 sync always sync init update \uart_phy_uart_clk_rxen $1\uart_phy_uart_clk_rxen[0:0] end - attribute \src "ls180.v:855.12-855.49" - process $proc$ls180.v:855$1894 + attribute \src "ls180.v:849.12-849.49" + process $proc$ls180.v:849$1898 assign { } { } assign $1\uart_phy_phase_accumulator_rx[31:0] 0 sync always sync init update \uart_phy_phase_accumulator_rx $1\uart_phy_phase_accumulator_rx[31:0] end - attribute \src "ls180.v:857.5-857.25" - process $proc$ls180.v:857$1895 + attribute \src "ls180.v:851.5-851.25" + process $proc$ls180.v:851$1899 assign { } { } assign $1\uart_phy_rx_r[0:0] 1'0 sync always sync init update \uart_phy_rx_r $1\uart_phy_rx_r[0:0] end - attribute \src "ls180.v:858.11-858.33" - process $proc$ls180.v:858$1896 + attribute \src "ls180.v:852.11-852.33" + process $proc$ls180.v:852$1900 assign { } { } assign $1\uart_phy_rx_reg[7:0] 8'00000000 sync always sync init update \uart_phy_rx_reg $1\uart_phy_rx_reg[7:0] end - attribute \src "ls180.v:859.11-859.38" - process $proc$ls180.v:859$1897 + attribute \src "ls180.v:853.11-853.38" + process $proc$ls180.v:853$1901 assign { } { } assign $1\uart_phy_rx_bitcount[3:0] 4'0000 sync always sync init update \uart_phy_rx_bitcount $1\uart_phy_rx_bitcount[3:0] end - attribute \src "ls180.v:860.5-860.28" - process $proc$ls180.v:860$1898 + attribute \src "ls180.v:854.5-854.28" + process $proc$ls180.v:854$1902 assign { } { } assign $1\uart_phy_rx_busy[0:0] 1'0 sync always sync init update \uart_phy_rx_busy $1\uart_phy_rx_busy[0:0] end - attribute \src "ls180.v:871.5-871.22" - process $proc$ls180.v:871$1899 + attribute \src "ls180.v:865.5-865.22" + process $proc$ls180.v:865$1903 assign { } { } assign $1\tx_pending[0:0] 1'0 sync always sync init update \tx_pending $1\tx_pending[0:0] end - attribute \src "ls180.v:873.5-873.20" - process $proc$ls180.v:873$1900 + attribute \src "ls180.v:867.5-867.20" + process $proc$ls180.v:867$1904 assign { } { } assign $1\tx_clear[0:0] 1'0 sync always sync init update \tx_clear $1\tx_clear[0:0] end - attribute \src "ls180.v:874.5-874.26" - process $proc$ls180.v:874$1901 + attribute \src "ls180.v:868.5-868.26" + process $proc$ls180.v:868$1905 assign { } { } assign $1\tx_old_trigger[0:0] 1'0 sync always sync init update \tx_old_trigger $1\tx_old_trigger[0:0] end - attribute \src "ls180.v:876.5-876.22" - process $proc$ls180.v:876$1902 + attribute \src "ls180.v:870.5-870.22" + process $proc$ls180.v:870$1906 assign { } { } assign $1\rx_pending[0:0] 1'0 sync always sync init update \rx_pending $1\rx_pending[0:0] end - attribute \src "ls180.v:878.5-878.20" - process $proc$ls180.v:878$1903 + attribute \src "ls180.v:872.5-872.20" + process $proc$ls180.v:872$1907 assign { } { } assign $1\rx_clear[0:0] 1'0 sync always sync init update \rx_clear $1\rx_clear[0:0] end - attribute \src "ls180.v:879.5-879.26" - process $proc$ls180.v:879$1904 + attribute \src "ls180.v:873.5-873.26" + process $proc$ls180.v:873$1908 assign { } { } assign $1\rx_old_trigger[0:0] 1'0 sync always sync init update \rx_old_trigger $1\rx_old_trigger[0:0] end - attribute \src "ls180.v:883.11-883.39" - process $proc$ls180.v:883$1905 + attribute \src "ls180.v:877.11-877.39" + process $proc$ls180.v:877$1909 assign { } { } assign $1\eventmanager_status_w[1:0] 2'00 sync always sync init update \eventmanager_status_w $1\eventmanager_status_w[1:0] end - attribute \src "ls180.v:887.11-887.40" - process $proc$ls180.v:887$1906 + attribute \src "ls180.v:881.11-881.40" + process $proc$ls180.v:881$1910 assign { } { } assign $1\eventmanager_pending_w[1:0] 2'00 sync always sync init update \eventmanager_pending_w $1\eventmanager_pending_w[1:0] end - attribute \src "ls180.v:888.11-888.38" - process $proc$ls180.v:888$1907 + attribute \src "ls180.v:882.11-882.38" + process $proc$ls180.v:882$1911 assign { } { } assign $1\eventmanager_storage[1:0] 2'00 sync always sync init update \eventmanager_storage $1\eventmanager_storage[1:0] end - attribute \src "ls180.v:889.5-889.27" - process $proc$ls180.v:889$1908 + attribute \src "ls180.v:883.5-883.27" + process $proc$ls180.v:883$1912 assign { } { } assign $1\eventmanager_re[0:0] 1'0 sync always sync init update \eventmanager_re $1\eventmanager_re[0:0] end - attribute \src "ls180.v:906.5-906.30" - process $proc$ls180.v:906$1909 + attribute \src "ls180.v:900.5-900.30" + process $proc$ls180.v:900$1913 assign { } { } assign $0\tx_fifo_sink_first[0:0] 1'0 sync always update \tx_fifo_sink_first $0\tx_fifo_sink_first[0:0] sync init end - attribute \src "ls180.v:907.5-907.29" - process $proc$ls180.v:907$1910 + attribute \src "ls180.v:901.5-901.29" + process $proc$ls180.v:901$1914 assign { } { } assign $0\tx_fifo_sink_last[0:0] 1'0 sync always update \tx_fifo_sink_last $0\tx_fifo_sink_last[0:0] sync init end - attribute \src "ls180.v:915.5-915.28" - process $proc$ls180.v:915$1911 + attribute \src "ls180.v:909.5-909.28" + process $proc$ls180.v:909$1915 assign { } { } assign $1\tx_fifo_readable[0:0] 1'0 sync always sync init update \tx_fifo_readable $1\tx_fifo_readable[0:0] end - attribute \src "ls180.v:922.11-922.32" - process $proc$ls180.v:922$1912 + attribute \src "ls180.v:916.11-916.32" + process $proc$ls180.v:916$1916 assign { } { } assign $1\tx_fifo_level0[4:0] 5'00000 sync always sync init update \tx_fifo_level0 $1\tx_fifo_level0[4:0] end - attribute \src "ls180.v:923.5-923.27" - process $proc$ls180.v:923$1913 + attribute \src "ls180.v:917.5-917.27" + process $proc$ls180.v:917$1917 assign { } { } assign $0\tx_fifo_replace[0:0] 1'0 sync always update \tx_fifo_replace $0\tx_fifo_replace[0:0] sync init end - attribute \src "ls180.v:924.11-924.33" - process $proc$ls180.v:924$1914 + attribute \src "ls180.v:918.11-918.33" + process $proc$ls180.v:918$1918 assign { } { } assign $1\tx_fifo_produce[3:0] 4'0000 sync always sync init update \tx_fifo_produce $1\tx_fifo_produce[3:0] end - attribute \src "ls180.v:925.11-925.33" - process $proc$ls180.v:925$1915 + attribute \src "ls180.v:919.11-919.33" + process $proc$ls180.v:919$1919 assign { } { } assign $1\tx_fifo_consume[3:0] 4'0000 sync always sync init update \tx_fifo_consume $1\tx_fifo_consume[3:0] end - attribute \src "ls180.v:926.11-926.36" - process $proc$ls180.v:926$1916 + attribute \src "ls180.v:920.11-920.36" + process $proc$ls180.v:920$1920 assign { } { } assign $1\tx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \tx_fifo_wrport_adr $1\tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:952.5-952.28" - process $proc$ls180.v:952$1917 + attribute \src "ls180.v:946.5-946.28" + process $proc$ls180.v:946$1921 assign { } { } assign $1\rx_fifo_readable[0:0] 1'0 sync always sync init update \rx_fifo_readable $1\rx_fifo_readable[0:0] end - attribute \src "ls180.v:959.11-959.32" - process $proc$ls180.v:959$1918 + attribute \src "ls180.v:953.11-953.32" + process $proc$ls180.v:953$1922 assign { } { } assign $1\rx_fifo_level0[4:0] 5'00000 sync always sync init update \rx_fifo_level0 $1\rx_fifo_level0[4:0] end - attribute \src "ls180.v:960.5-960.27" - process $proc$ls180.v:960$1919 + attribute \src "ls180.v:954.5-954.27" + process $proc$ls180.v:954$1923 assign { } { } assign $0\rx_fifo_replace[0:0] 1'0 sync always update \rx_fifo_replace $0\rx_fifo_replace[0:0] sync init end - attribute \src "ls180.v:961.11-961.33" - process $proc$ls180.v:961$1920 + attribute \src "ls180.v:955.11-955.33" + process $proc$ls180.v:955$1924 assign { } { } assign $1\rx_fifo_produce[3:0] 4'0000 sync always sync init update \rx_fifo_produce $1\rx_fifo_produce[3:0] end - attribute \src "ls180.v:962.11-962.33" - process $proc$ls180.v:962$1921 + attribute \src "ls180.v:956.11-956.33" + process $proc$ls180.v:956$1925 assign { } { } assign $1\rx_fifo_consume[3:0] 4'0000 sync always sync init update \rx_fifo_consume $1\rx_fifo_consume[3:0] end - attribute \src "ls180.v:963.11-963.36" - process $proc$ls180.v:963$1922 + attribute \src "ls180.v:957.11-957.36" + process $proc$ls180.v:957$1926 assign { } { } assign $1\rx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \rx_fifo_wrport_adr $1\rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:978.5-978.17" - process $proc$ls180.v:978$1923 + attribute \src "ls180.v:972.5-972.17" + process $proc$ls180.v:972$1927 assign { } { } assign $0\reset[0:0] 1'0 sync always update \reset $0\reset[0:0] sync init end - attribute \src "ls180.v:979.11-979.34" - process $proc$ls180.v:979$1924 + attribute \src "ls180.v:973.11-973.34" + process $proc$ls180.v:973$1928 assign { } { } assign $1\gpio0_oe_storage[7:0] 8'00000000 sync always sync init update \gpio0_oe_storage $1\gpio0_oe_storage[7:0] end - attribute \src "ls180.v:980.5-980.23" - process $proc$ls180.v:980$1925 + attribute \src "ls180.v:974.5-974.23" + process $proc$ls180.v:974$1929 assign { } { } assign $1\gpio0_oe_re[0:0] 1'0 sync always sync init update \gpio0_oe_re $1\gpio0_oe_re[0:0] end - attribute \src "ls180.v:981.11-981.30" - process $proc$ls180.v:981$1926 + attribute \src "ls180.v:975.11-975.30" + process $proc$ls180.v:975$1930 assign { } { } assign $1\gpio0_status[7:0] 8'00000000 sync always sync init update \gpio0_status $1\gpio0_status[7:0] end - attribute \src "ls180.v:983.11-983.35" - process $proc$ls180.v:983$1927 + attribute \src "ls180.v:977.11-977.35" + process $proc$ls180.v:977$1931 assign { } { } assign $1\gpio0_out_storage[7:0] 8'00000000 sync always sync init update \gpio0_out_storage $1\gpio0_out_storage[7:0] end - attribute \src "ls180.v:984.5-984.24" - process $proc$ls180.v:984$1928 + attribute \src "ls180.v:978.5-978.24" + process $proc$ls180.v:978$1932 assign { } { } assign $1\gpio0_out_re[0:0] 1'0 sync always sync init update \gpio0_out_re $1\gpio0_out_re[0:0] end - attribute \src "ls180.v:985.11-985.35" - process $proc$ls180.v:985$1929 + attribute \src "ls180.v:979.11-979.35" + process $proc$ls180.v:979$1933 assign { } { } assign $1\gpio0_pads_gpio0i[7:0] 8'00000000 sync always sync init update \gpio0_pads_gpio0i $1\gpio0_pads_gpio0i[7:0] end - attribute \src "ls180.v:986.11-986.35" - process $proc$ls180.v:986$1930 + attribute \src "ls180.v:980.11-980.35" + process $proc$ls180.v:980$1934 assign { } { } assign $1\gpio0_pads_gpio0o[7:0] 8'00000000 sync always sync init update \gpio0_pads_gpio0o $1\gpio0_pads_gpio0o[7:0] end - attribute \src "ls180.v:987.11-987.36" - process $proc$ls180.v:987$1931 + attribute \src "ls180.v:981.11-981.36" + process $proc$ls180.v:981$1935 assign { } { } assign $1\gpio0_pads_gpio0oe[7:0] 8'00000000 sync always sync init update \gpio0_pads_gpio0oe $1\gpio0_pads_gpio0oe[7:0] end - attribute \src "ls180.v:988.11-988.34" - process $proc$ls180.v:988$1932 + attribute \src "ls180.v:982.11-982.34" + process $proc$ls180.v:982$1936 assign { } { } assign $1\gpio1_oe_storage[7:0] 8'00000000 sync always sync init update \gpio1_oe_storage $1\gpio1_oe_storage[7:0] end - attribute \src "ls180.v:989.5-989.23" - process $proc$ls180.v:989$1933 + attribute \src "ls180.v:983.5-983.23" + process $proc$ls180.v:983$1937 assign { } { } assign $1\gpio1_oe_re[0:0] 1'0 sync always sync init update \gpio1_oe_re $1\gpio1_oe_re[0:0] end - attribute \src "ls180.v:990.11-990.30" - process $proc$ls180.v:990$1934 + attribute \src "ls180.v:984.11-984.30" + process $proc$ls180.v:984$1938 assign { } { } assign $1\gpio1_status[7:0] 8'00000000 sync always sync init update \gpio1_status $1\gpio1_status[7:0] end - attribute \src "ls180.v:992.11-992.35" - process $proc$ls180.v:992$1935 + attribute \src "ls180.v:986.11-986.35" + process $proc$ls180.v:986$1939 assign { } { } assign $1\gpio1_out_storage[7:0] 8'00000000 sync always sync init update \gpio1_out_storage $1\gpio1_out_storage[7:0] end - attribute \src "ls180.v:993.5-993.24" - process $proc$ls180.v:993$1936 + attribute \src "ls180.v:987.5-987.24" + process $proc$ls180.v:987$1940 assign { } { } assign $1\gpio1_out_re[0:0] 1'0 sync always sync init update \gpio1_out_re $1\gpio1_out_re[0:0] end - attribute \src "ls180.v:994.11-994.35" - process $proc$ls180.v:994$1937 + attribute \src "ls180.v:988.11-988.35" + process $proc$ls180.v:988$1941 assign { } { } assign $1\gpio1_pads_gpio1i[7:0] 8'00000000 sync always sync init update \gpio1_pads_gpio1i $1\gpio1_pads_gpio1i[7:0] end - attribute \src "ls180.v:995.11-995.35" - process $proc$ls180.v:995$1938 + attribute \src "ls180.v:989.11-989.35" + process $proc$ls180.v:989$1942 assign { } { } assign $1\gpio1_pads_gpio1o[7:0] 8'00000000 sync always sync init update \gpio1_pads_gpio1o $1\gpio1_pads_gpio1o[7:0] end - attribute \src "ls180.v:996.11-996.36" - process $proc$ls180.v:996$1939 + attribute \src "ls180.v:99.5-99.44" + process $proc$ls180.v:99$1561 + assign { } { } + assign $1\libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + sync always + sync init + update \libresocsim_libresoc_jtag_wb_ack $1\libresocsim_libresoc_jtag_wb_ack[0:0] + end + attribute \src "ls180.v:990.11-990.36" + process $proc$ls180.v:990$1943 assign { } { } assign $1\gpio1_pads_gpio1oe[7:0] 8'00000000 sync always sync init update \gpio1_pads_gpio1oe $1\gpio1_pads_gpio1oe[7:0] end - attribute \src "ls180.v:997.11-997.26" - process $proc$ls180.v:997$1940 + attribute \src "ls180.v:991.11-991.26" + process $proc$ls180.v:991$1944 assign { } { } assign $1\eint_tmp[2:0] 3'000 sync always sync init update \eint_tmp $1\eint_tmp[2:0] end - attribute \src "ls180.v:999.12-999.25" - process $proc$ls180.v:999$1941 + attribute \src "ls180.v:993.12-993.25" + process $proc$ls180.v:993$1945 assign { } { } - assign $1\dummy[35:0] 36'000000000000000000000000000000000000 + assign $1\dummy[39:0] 40'0000000000000000000000000000000000000000 sync always sync init - update \dummy $1\dummy[35:0] + update \dummy $1\dummy[39:0] + end + attribute \src "ls180.v:997.11-997.29" + process $proc$ls180.v:997$1946 + assign { } { } + assign $1\i2c_storage[2:0] 3'000 + sync always + sync init + update \i2c_storage $1\i2c_storage[2:0] + end + attribute \src "ls180.v:998.5-998.18" + process $proc$ls180.v:998$1947 + assign { } { } + assign $1\i2c_re[0:0] 1'0 + sync always + sync init + update \i2c_re $1\i2c_re[0:0] end connect \libresocsim_libresoc_reset \libresocsim_reset - connect \libresocsim_libresoc_clk_sel \sys_clksel_i - connect \sys_pll_18_o \libresocsim_libresoc_pll_18_o - connect \sys_pll_lck_o \libresocsim_libresoc_pll_lck_o connect \libresocsim_libresoc_jtag_tck \jtag_tck connect \libresocsim_libresoc_jtag_tms \jtag_tms connect \libresocsim_libresoc_jtag_tdi \jtag_tdi connect \jtag_tdo \libresocsim_libresoc_jtag_tdo connect \nc_1 \nc connect \libresocsim_bus_error \libresocsim_error - connect \libresocsim_converter0_reset $not$ls180.v:1519$17_Y + connect \libresocsim_converter0_reset $not$ls180.v:1510$17_Y connect \libresocsim_libresoc_ibus_dat_r { \libresocsim_interface0_converted_interface_dat_r \libresocsim_converter0_dat_r [63:32] } - connect \libresocsim_converter1_reset $not$ls180.v:1579$28_Y + connect \libresocsim_converter1_reset $not$ls180.v:1570$28_Y connect \libresocsim_libresoc_dbus_dat_r { \libresocsim_interface1_converted_interface_dat_r \libresocsim_converter1_dat_r [63:32] } - connect \libresocsim_converter2_reset $not$ls180.v:1639$39_Y + connect \libresocsim_converter2_reset $not$ls180.v:1630$39_Y connect \libresocsim_libresoc_jtag_wb_dat_r { \libresocsim_interface2_converted_interface_dat_r \libresocsim_converter2_dat_r [63:32] } connect \libresocsim_reset \libresocsim_reset_re connect \libresocsim_bus_errors_status \libresocsim_bus_errors connect \libresocsim_adr \libresocsim_ram_bus_adr [6:0] connect \libresocsim_ram_bus_dat_r \libresocsim_dat_r connect \libresocsim_dat_w \libresocsim_ram_bus_dat_w - connect \libresocsim_zero_trigger $ne$ls180.v:1711$63_Y + connect \libresocsim_zero_trigger $ne$ls180.v:1702$63_Y connect \libresocsim_eventmanager_status_w \libresocsim_zero_status connect \libresocsim_eventmanager_pending_w \libresocsim_zero_pending - connect \libresocsim_irq $and$ls180.v:1720$66_Y + connect \libresocsim_irq $and$ls180.v:1711$66_Y connect \libresocsim_zero_status \libresocsim_zero_trigger connect \ram_adr \ram_bus_ram_bus_adr [4:0] connect \ram_bus_ram_bus_dat_r \ram_dat_r @@ -271208,8 +271042,8 @@ module \ls180 connect \sdram_inti_p0_reset_n \sdram_reset_n connect \sdram_inti_p0_address \sdram_address_storage connect \sdram_inti_p0_bank \sdram_baddress_storage - connect \sdram_inti_p0_wrdata_en $and$ls180.v:1844$86_Y - connect \sdram_inti_p0_rddata_en $and$ls180.v:1845$87_Y + connect \sdram_inti_p0_wrdata_en $and$ls180.v:1835$86_Y + connect \sdram_inti_p0_rddata_en $and$ls180.v:1836$87_Y connect \sdram_inti_p0_wrdata \sdram_wrdata_storage connect \sdram_inti_p0_wrdata_mask 2'00 connect \sdram_bankmachine0_req_valid \sdram_interface_bank0_valid @@ -271240,14 +271074,14 @@ module \ls180 connect \sdram_interface_bank3_lock \sdram_bankmachine3_req_lock connect \sdram_interface_bank3_wdata_ready \sdram_bankmachine3_req_wdata_ready connect \sdram_interface_bank3_rdata_valid \sdram_bankmachine3_req_rdata_valid - connect \sdram_timer_wait $not$ls180.v:1876$88_Y + connect \sdram_timer_wait $not$ls180.v:1867$88_Y connect \sdram_postponer_req_i \sdram_timer_done0 connect \sdram_wants_refresh \sdram_postponer_req_o - connect \sdram_timer_done1 $eq$ls180.v:1879$89_Y + connect \sdram_timer_done1 $eq$ls180.v:1870$89_Y connect \sdram_timer_done0 \sdram_timer_done1 connect \sdram_timer_count0 \sdram_timer_count1 - connect \sdram_sequencer_start1 $or$ls180.v:1882$91_Y - connect \sdram_sequencer_done0 $and$ls180.v:1883$93_Y + connect \sdram_sequencer_start1 $or$ls180.v:1873$91_Y + connect \sdram_sequencer_done0 $and$ls180.v:1874$93_Y connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \sdram_bankmachine0_req_valid connect \sdram_bankmachine0_req_ready \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine0_req_we @@ -271258,13 +271092,13 @@ module \ls180 connect \sdram_bankmachine0_cmd_buffer_sink_last \sdram_bankmachine0_cmd_buffer_lookahead_source_last connect \sdram_bankmachine0_cmd_buffer_sink_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we connect \sdram_bankmachine0_cmd_buffer_sink_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:1925$95_Y - connect \sdram_bankmachine0_req_lock $or$ls180.v:1926$96_Y - connect \sdram_bankmachine0_row_hit $eq$ls180.v:1927$97_Y + connect \sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:1916$95_Y + connect \sdram_bankmachine0_req_lock $or$ls180.v:1917$96_Y + connect \sdram_bankmachine0_row_hit $eq$ls180.v:1918$97_Y connect \sdram_bankmachine0_cmd_payload_ba 2'00 - connect \sdram_bankmachine0_twtpcon_valid $and$ls180.v:1937$102_Y - connect \sdram_bankmachine0_trccon_valid $and$ls180.v:1938$104_Y - connect \sdram_bankmachine0_trascon_valid $and$ls180.v:1939$106_Y + connect \sdram_bankmachine0_twtpcon_valid $and$ls180.v:1928$102_Y + connect \sdram_bankmachine0_trccon_valid $and$ls180.v:1929$104_Y + connect \sdram_bankmachine0_trascon_valid $and$ls180.v:1930$106_Y connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } connect { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable @@ -271280,13 +271114,13 @@ module \ls180 connect \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \sdram_bankmachine0_cmd_buffer_lookahead_source_ready connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:1971$114_Y - connect \sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:1972$115_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:1962$114_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:1963$115_Y connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine0_cmd_buffer_lookahead_consume connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:1975$116_Y - connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:1976$117_Y - connect \sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:1977$119_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:1966$116_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:1967$117_Y + connect \sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:1968$119_Y connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \sdram_bankmachine1_req_valid connect \sdram_bankmachine1_req_ready \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine1_req_we @@ -271297,13 +271131,13 @@ module \ls180 connect \sdram_bankmachine1_cmd_buffer_sink_last \sdram_bankmachine1_cmd_buffer_lookahead_source_last connect \sdram_bankmachine1_cmd_buffer_sink_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we connect \sdram_bankmachine1_cmd_buffer_sink_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:2082$125_Y - connect \sdram_bankmachine1_req_lock $or$ls180.v:2083$126_Y - connect \sdram_bankmachine1_row_hit $eq$ls180.v:2084$127_Y + connect \sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:2073$125_Y + connect \sdram_bankmachine1_req_lock $or$ls180.v:2074$126_Y + connect \sdram_bankmachine1_row_hit $eq$ls180.v:2075$127_Y connect \sdram_bankmachine1_cmd_payload_ba 2'01 - connect \sdram_bankmachine1_twtpcon_valid $and$ls180.v:2094$132_Y - connect \sdram_bankmachine1_trccon_valid $and$ls180.v:2095$134_Y - connect \sdram_bankmachine1_trascon_valid $and$ls180.v:2096$136_Y + connect \sdram_bankmachine1_twtpcon_valid $and$ls180.v:2085$132_Y + connect \sdram_bankmachine1_trccon_valid $and$ls180.v:2086$134_Y + connect \sdram_bankmachine1_trascon_valid $and$ls180.v:2087$136_Y connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } connect { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable @@ -271319,13 +271153,13 @@ module \ls180 connect \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \sdram_bankmachine1_cmd_buffer_lookahead_source_ready connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:2128$144_Y - connect \sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:2129$145_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:2119$144_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:2120$145_Y connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine1_cmd_buffer_lookahead_consume connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:2132$146_Y - connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:2133$147_Y - connect \sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:2134$149_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:2123$146_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:2124$147_Y + connect \sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:2125$149_Y connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \sdram_bankmachine2_req_valid connect \sdram_bankmachine2_req_ready \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine2_req_we @@ -271336,13 +271170,13 @@ module \ls180 connect \sdram_bankmachine2_cmd_buffer_sink_last \sdram_bankmachine2_cmd_buffer_lookahead_source_last connect \sdram_bankmachine2_cmd_buffer_sink_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we connect \sdram_bankmachine2_cmd_buffer_sink_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:2239$155_Y - connect \sdram_bankmachine2_req_lock $or$ls180.v:2240$156_Y - connect \sdram_bankmachine2_row_hit $eq$ls180.v:2241$157_Y + connect \sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:2230$155_Y + connect \sdram_bankmachine2_req_lock $or$ls180.v:2231$156_Y + connect \sdram_bankmachine2_row_hit $eq$ls180.v:2232$157_Y connect \sdram_bankmachine2_cmd_payload_ba 2'10 - connect \sdram_bankmachine2_twtpcon_valid $and$ls180.v:2251$162_Y - connect \sdram_bankmachine2_trccon_valid $and$ls180.v:2252$164_Y - connect \sdram_bankmachine2_trascon_valid $and$ls180.v:2253$166_Y + connect \sdram_bankmachine2_twtpcon_valid $and$ls180.v:2242$162_Y + connect \sdram_bankmachine2_trccon_valid $and$ls180.v:2243$164_Y + connect \sdram_bankmachine2_trascon_valid $and$ls180.v:2244$166_Y connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } connect { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable @@ -271358,13 +271192,13 @@ module \ls180 connect \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \sdram_bankmachine2_cmd_buffer_lookahead_source_ready connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:2285$174_Y - connect \sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:2286$175_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:2276$174_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:2277$175_Y connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine2_cmd_buffer_lookahead_consume connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:2289$176_Y - connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:2290$177_Y - connect \sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:2291$179_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:2280$176_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:2281$177_Y + connect \sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:2282$179_Y connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \sdram_bankmachine3_req_valid connect \sdram_bankmachine3_req_ready \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine3_req_we @@ -271375,13 +271209,13 @@ module \ls180 connect \sdram_bankmachine3_cmd_buffer_sink_last \sdram_bankmachine3_cmd_buffer_lookahead_source_last connect \sdram_bankmachine3_cmd_buffer_sink_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we connect \sdram_bankmachine3_cmd_buffer_sink_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:2396$185_Y - connect \sdram_bankmachine3_req_lock $or$ls180.v:2397$186_Y - connect \sdram_bankmachine3_row_hit $eq$ls180.v:2398$187_Y + connect \sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:2387$185_Y + connect \sdram_bankmachine3_req_lock $or$ls180.v:2388$186_Y + connect \sdram_bankmachine3_row_hit $eq$ls180.v:2389$187_Y connect \sdram_bankmachine3_cmd_payload_ba 2'11 - connect \sdram_bankmachine3_twtpcon_valid $and$ls180.v:2408$192_Y - connect \sdram_bankmachine3_trccon_valid $and$ls180.v:2409$194_Y - connect \sdram_bankmachine3_trascon_valid $and$ls180.v:2410$196_Y + connect \sdram_bankmachine3_twtpcon_valid $and$ls180.v:2399$192_Y + connect \sdram_bankmachine3_trccon_valid $and$ls180.v:2400$194_Y + connect \sdram_bankmachine3_trascon_valid $and$ls180.v:2401$196_Y connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } connect { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable @@ -271397,32 +271231,32 @@ module \ls180 connect \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \sdram_bankmachine3_cmd_buffer_lookahead_source_ready connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:2442$204_Y - connect \sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:2443$205_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:2433$204_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:2434$205_Y connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine3_cmd_buffer_lookahead_consume connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:2446$206_Y - connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:2447$207_Y - connect \sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:2448$209_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:2437$206_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:2438$207_Y + connect \sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:2439$209_Y connect \sdram_choose_req_want_cmds 1'1 - connect \sdram_trrdcon_valid $and$ls180.v:2544$220_Y - connect \sdram_tfawcon_valid $and$ls180.v:2545$226_Y - connect \sdram_ras_allowed $and$ls180.v:2546$227_Y - connect \sdram_tccdcon_valid $and$ls180.v:2547$230_Y + connect \sdram_trrdcon_valid $and$ls180.v:2535$220_Y + connect \sdram_tfawcon_valid $and$ls180.v:2536$226_Y + connect \sdram_ras_allowed $and$ls180.v:2537$227_Y + connect \sdram_tccdcon_valid $and$ls180.v:2538$230_Y connect \sdram_cas_allowed \sdram_tccdcon_ready - connect \sdram_twtrcon_valid $and$ls180.v:2549$232_Y - connect \sdram_read_available $or$ls180.v:2550$239_Y - connect \sdram_write_available $or$ls180.v:2551$246_Y - connect \sdram_max_time0 $eq$ls180.v:2552$247_Y - connect \sdram_max_time1 $eq$ls180.v:2553$248_Y + connect \sdram_twtrcon_valid $and$ls180.v:2540$232_Y + connect \sdram_read_available $or$ls180.v:2541$239_Y + connect \sdram_write_available $or$ls180.v:2542$246_Y + connect \sdram_max_time0 $eq$ls180.v:2543$247_Y + connect \sdram_max_time1 $eq$ls180.v:2544$248_Y connect \sdram_bankmachine0_refresh_req \sdram_cmd_valid connect \sdram_bankmachine1_refresh_req \sdram_cmd_valid connect \sdram_bankmachine2_refresh_req \sdram_cmd_valid connect \sdram_bankmachine3_refresh_req \sdram_cmd_valid - connect \sdram_go_to_refresh $and$ls180.v:2558$251_Y + connect \sdram_go_to_refresh $and$ls180.v:2549$251_Y connect \sdram_interface_rdata \sdram_dfi_p0_rddata connect \sdram_dfi_p0_wrdata \sdram_interface_wdata - connect \sdram_dfi_p0_wrdata_mask $not$ls180.v:2561$252_Y + connect \sdram_dfi_p0_wrdata_mask $not$ls180.v:2552$252_Y connect \sdram_choose_cmd_request \sdram_choose_cmd_valids connect \sdram_choose_cmd_cmd_valid \rhs_array_muxed0 connect \sdram_choose_cmd_cmd_payload_a \rhs_array_muxed1 @@ -271430,7 +271264,7 @@ module \ls180 connect \sdram_choose_cmd_cmd_payload_is_read \rhs_array_muxed3 connect \sdram_choose_cmd_cmd_payload_is_write \rhs_array_muxed4 connect \sdram_choose_cmd_cmd_payload_is_cmd \rhs_array_muxed5 - connect \sdram_choose_cmd_ce $or$ls180.v:2594$310_Y + connect \sdram_choose_cmd_ce $or$ls180.v:2585$310_Y connect \sdram_choose_req_request \sdram_choose_req_valids connect \sdram_choose_req_cmd_valid \rhs_array_muxed6 connect \sdram_choose_req_cmd_payload_a \rhs_array_muxed7 @@ -271438,31 +271272,31 @@ module \ls180 connect \sdram_choose_req_cmd_payload_is_read \rhs_array_muxed9 connect \sdram_choose_req_cmd_payload_is_write \rhs_array_muxed10 connect \sdram_choose_req_cmd_payload_is_cmd \rhs_array_muxed11 - connect \sdram_choose_req_ce $or$ls180.v:2663$396_Y + connect \sdram_choose_req_ce $or$ls180.v:2654$396_Y connect \sdram_dfi_p0_reset_n 1'1 connect \sdram_dfi_p0_cke \sdram_steerer0 connect \sdram_dfi_p0_odt \sdram_steerer1 - connect \subfragments_roundrobin0_request $and$ls180.v:2740$428_Y - connect \subfragments_roundrobin0_ce $and$ls180.v:2741$431_Y + connect \subfragments_roundrobin0_request $and$ls180.v:2731$428_Y + connect \subfragments_roundrobin0_ce $and$ls180.v:2732$431_Y connect \sdram_interface_bank0_addr \rhs_array_muxed12 connect \sdram_interface_bank0_we \rhs_array_muxed13 connect \sdram_interface_bank0_valid \rhs_array_muxed14 - connect \subfragments_roundrobin1_request $and$ls180.v:2745$444_Y - connect \subfragments_roundrobin1_ce $and$ls180.v:2746$447_Y + connect \subfragments_roundrobin1_request $and$ls180.v:2736$444_Y + connect \subfragments_roundrobin1_ce $and$ls180.v:2737$447_Y connect \sdram_interface_bank1_addr \rhs_array_muxed15 connect \sdram_interface_bank1_we \rhs_array_muxed16 connect \sdram_interface_bank1_valid \rhs_array_muxed17 - connect \subfragments_roundrobin2_request $and$ls180.v:2750$460_Y - connect \subfragments_roundrobin2_ce $and$ls180.v:2751$463_Y + connect \subfragments_roundrobin2_request $and$ls180.v:2741$460_Y + connect \subfragments_roundrobin2_ce $and$ls180.v:2742$463_Y connect \sdram_interface_bank2_addr \rhs_array_muxed18 connect \sdram_interface_bank2_we \rhs_array_muxed19 connect \sdram_interface_bank2_valid \rhs_array_muxed20 - connect \subfragments_roundrobin3_request $and$ls180.v:2755$476_Y - connect \subfragments_roundrobin3_ce $and$ls180.v:2756$479_Y + connect \subfragments_roundrobin3_request $and$ls180.v:2746$476_Y + connect \subfragments_roundrobin3_ce $and$ls180.v:2747$479_Y connect \sdram_interface_bank3_addr \rhs_array_muxed21 connect \sdram_interface_bank3_we \rhs_array_muxed22 connect \sdram_interface_bank3_valid \rhs_array_muxed23 - connect \port_cmd_ready $or$ls180.v:2760$543_Y + connect \port_cmd_ready $or$ls180.v:2751$543_Y connect \port_wdata_ready \subfragments_new_master_wdata_ready connect \port_rdata_valid \subfragments_new_master_rdata_valid3 connect \port_rdata_payload_data \sdram_interface_rdata @@ -271470,22 +271304,22 @@ module \ls180 connect \subfragments_roundrobin1_grant 1'0 connect \subfragments_roundrobin2_grant 1'0 connect \subfragments_roundrobin3_grant 1'0 - connect \converter_reset $not$ls180.v:2782$545_Y + connect \converter_reset $not$ls180.v:2773$545_Y connect \wb_sdram_dat_r { \litedram_wb_dat_r \converter_dat_r [31:16] } - connect \port_cmd_payload_addr $sub$ls180.v:2842$556_Y [23:0] + connect \port_cmd_payload_addr $sub$ls180.v:2833$556_Y [23:0] connect \port_cmd_payload_we \litedram_wb_we connect \port_wdata_payload_data \litedram_wb_dat_w connect \port_wdata_payload_we \litedram_wb_sel connect \litedram_wb_dat_r \port_rdata_payload_data - connect \port_flush $not$ls180.v:2847$557_Y - connect \port_cmd_last $not$ls180.v:2848$558_Y - connect \port_cmd_valid $and$ls180.v:2849$561_Y - connect \port_wdata_valid $and$ls180.v:2850$565_Y - connect \port_rdata_ready $and$ls180.v:2851$568_Y - connect \litedram_wb_ack $and$ls180.v:2852$573_Y - connect \ack_cmd $or$ls180.v:2853$575_Y - connect \ack_wdata $or$ls180.v:2854$577_Y - connect \ack_rdata $and$ls180.v:2855$578_Y + connect \port_flush $not$ls180.v:2838$557_Y + connect \port_cmd_last $not$ls180.v:2839$558_Y + connect \port_cmd_valid $and$ls180.v:2840$561_Y + connect \port_wdata_valid $and$ls180.v:2841$565_Y + connect \port_rdata_ready $and$ls180.v:2842$568_Y + connect \litedram_wb_ack $and$ls180.v:2843$573_Y + connect \ack_cmd $or$ls180.v:2844$575_Y + connect \ack_wdata $or$ls180.v:2845$577_Y + connect \ack_rdata $and$ls180.v:2846$578_Y connect \uart_sink_valid \uart_phy_source_valid connect \uart_phy_source_ready \uart_sink_ready connect \uart_sink_first \uart_phy_source_first @@ -271498,25 +271332,25 @@ module \ls180 connect \uart_phy_sink_payload_data \uart_source_payload_data connect \tx_fifo_sink_valid \rxtx_re connect \tx_fifo_sink_payload_data \rxtx_r - connect \txfull_status $not$ls180.v:2868$579_Y - connect \txempty_status $not$ls180.v:2869$580_Y + connect \txfull_status $not$ls180.v:2859$579_Y + connect \txempty_status $not$ls180.v:2860$580_Y connect \uart_source_valid \tx_fifo_source_valid connect \tx_fifo_source_ready \uart_source_ready connect \uart_source_first \tx_fifo_source_first connect \uart_source_last \tx_fifo_source_last connect \uart_source_payload_data \tx_fifo_source_payload_data - connect \tx_trigger $not$ls180.v:2875$581_Y + connect \tx_trigger $not$ls180.v:2866$581_Y connect \rx_fifo_sink_valid \uart_sink_valid connect \uart_sink_ready \rx_fifo_sink_ready connect \rx_fifo_sink_first \uart_sink_first connect \rx_fifo_sink_last \uart_sink_last connect \rx_fifo_sink_payload_data \uart_sink_payload_data - connect \rxempty_status $not$ls180.v:2881$582_Y - connect \rxfull_status $not$ls180.v:2882$583_Y + connect \rxempty_status $not$ls180.v:2872$582_Y + connect \rxfull_status $not$ls180.v:2873$583_Y connect \rxtx_w \rx_fifo_source_payload_data - connect \rx_fifo_source_ready $or$ls180.v:2884$585_Y - connect \rx_trigger $not$ls180.v:2885$586_Y - connect \irq $or$ls180.v:2908$595_Y + connect \rx_fifo_source_ready $or$ls180.v:2875$585_Y + connect \rx_trigger $not$ls180.v:2876$586_Y + connect \irq $or$ls180.v:2899$595_Y connect \tx_status \tx_trigger connect \rx_status \rx_trigger connect \tx_fifo_syncfifo_din { \tx_fifo_fifo_in_last \tx_fifo_fifo_in_first \tx_fifo_fifo_in_payload_data } @@ -271531,16 +271365,16 @@ module \ls180 connect \tx_fifo_source_last \tx_fifo_fifo_out_last connect \tx_fifo_source_payload_data \tx_fifo_fifo_out_payload_data connect \tx_fifo_re \tx_fifo_source_ready - connect \tx_fifo_syncfifo_re $and$ls180.v:2923$598_Y - connect \tx_fifo_level1 $add$ls180.v:2924$599_Y + connect \tx_fifo_syncfifo_re $and$ls180.v:2914$598_Y + connect \tx_fifo_level1 $add$ls180.v:2915$599_Y connect \tx_fifo_wrport_dat_w \tx_fifo_syncfifo_din - connect \tx_fifo_wrport_we $and$ls180.v:2934$603_Y - connect \tx_fifo_do_read $and$ls180.v:2935$604_Y + connect \tx_fifo_wrport_we $and$ls180.v:2925$603_Y + connect \tx_fifo_do_read $and$ls180.v:2926$604_Y connect \tx_fifo_rdport_adr \tx_fifo_consume connect \tx_fifo_syncfifo_dout \tx_fifo_rdport_dat_r connect \tx_fifo_rdport_re \tx_fifo_do_read - connect \tx_fifo_syncfifo_writable $ne$ls180.v:2939$605_Y - connect \tx_fifo_syncfifo_readable $ne$ls180.v:2940$606_Y + connect \tx_fifo_syncfifo_writable $ne$ls180.v:2930$605_Y + connect \tx_fifo_syncfifo_readable $ne$ls180.v:2931$606_Y connect \rx_fifo_syncfifo_din { \rx_fifo_fifo_in_last \rx_fifo_fifo_in_first \rx_fifo_fifo_in_payload_data } connect { \rx_fifo_fifo_out_last \rx_fifo_fifo_out_first \rx_fifo_fifo_out_payload_data } \rx_fifo_syncfifo_dout connect \rx_fifo_sink_ready \rx_fifo_syncfifo_writable @@ -271553,16 +271387,16 @@ module \ls180 connect \rx_fifo_source_last \rx_fifo_fifo_out_last connect \rx_fifo_source_payload_data \rx_fifo_fifo_out_payload_data connect \rx_fifo_re \rx_fifo_source_ready - connect \rx_fifo_syncfifo_re $and$ls180.v:2953$609_Y - connect \rx_fifo_level1 $add$ls180.v:2954$610_Y + connect \rx_fifo_syncfifo_re $and$ls180.v:2944$609_Y + connect \rx_fifo_level1 $add$ls180.v:2945$610_Y connect \rx_fifo_wrport_dat_w \rx_fifo_syncfifo_din - connect \rx_fifo_wrport_we $and$ls180.v:2964$614_Y - connect \rx_fifo_do_read $and$ls180.v:2965$615_Y + connect \rx_fifo_wrport_we $and$ls180.v:2955$614_Y + connect \rx_fifo_do_read $and$ls180.v:2956$615_Y connect \rx_fifo_rdport_adr \rx_fifo_consume connect \rx_fifo_syncfifo_dout \rx_fifo_rdport_dat_r connect \rx_fifo_rdport_re \rx_fifo_do_read - connect \rx_fifo_syncfifo_writable $ne$ls180.v:2969$616_Y - connect \rx_fifo_syncfifo_readable $ne$ls180.v:2970$617_Y + connect \rx_fifo_syncfifo_writable $ne$ls180.v:2960$616_Y + connect \rx_fifo_syncfifo_readable $ne$ls180.v:2961$617_Y connect \libresocsim_libresoc_constraintmanager_i2c_scl \i2c_scl_1 connect \libresocsim_libresoc_constraintmanager_i2c_sda_oe \i2c_oe connect \libresocsim_libresoc_constraintmanager_i2c_sda_o \i2c_sda0 @@ -271578,12 +271412,12 @@ module \ls180 connect \libresocsim_interface0_converted_interface_dat_r \libresocsim_shared_dat_r connect \libresocsim_interface1_converted_interface_dat_r \libresocsim_shared_dat_r connect \libresocsim_interface2_converted_interface_dat_r \libresocsim_shared_dat_r - connect \libresocsim_interface0_converted_interface_ack $and$ls180.v:3083$627_Y - connect \libresocsim_interface1_converted_interface_ack $and$ls180.v:3084$629_Y - connect \libresocsim_interface2_converted_interface_ack $and$ls180.v:3085$631_Y - connect \libresocsim_interface0_converted_interface_err $and$ls180.v:3086$633_Y - connect \libresocsim_interface1_converted_interface_err $and$ls180.v:3087$635_Y - connect \libresocsim_interface2_converted_interface_err $and$ls180.v:3088$637_Y + connect \libresocsim_interface0_converted_interface_ack $and$ls180.v:3074$627_Y + connect \libresocsim_interface1_converted_interface_ack $and$ls180.v:3075$629_Y + connect \libresocsim_interface2_converted_interface_ack $and$ls180.v:3076$631_Y + connect \libresocsim_interface0_converted_interface_err $and$ls180.v:3077$633_Y + connect \libresocsim_interface1_converted_interface_err $and$ls180.v:3078$635_Y + connect \libresocsim_interface2_converted_interface_err $and$ls180.v:3079$637_Y connect \libresocsim_request { \libresocsim_interface2_converted_interface_cyc \libresocsim_interface1_converted_interface_cyc \libresocsim_interface0_converted_interface_cyc } connect \libresocsim_ram_bus_adr \libresocsim_shared_adr connect \libresocsim_ram_bus_dat_w \libresocsim_shared_dat_w @@ -271627,43 +271461,43 @@ module \ls180 connect \libresocsim_libresocsim_wishbone_we \libresocsim_shared_we connect \libresocsim_libresocsim_wishbone_cti \libresocsim_shared_cti connect \libresocsim_libresocsim_wishbone_bte \libresocsim_shared_bte - connect \libresocsim_ram_bus_cyc $and$ls180.v:3141$645_Y - connect \ram_bus_ram_bus_cyc $and$ls180.v:3142$646_Y - connect \libresocsim_libresoc_xics_icp_cyc $and$ls180.v:3143$647_Y - connect \libresocsim_libresoc_xics_ics_cyc $and$ls180.v:3144$648_Y - connect \wb_sdram_cyc $and$ls180.v:3145$649_Y - connect \libresocsim_libresocsim_wishbone_cyc $and$ls180.v:3146$650_Y - connect \libresocsim_shared_err $or$ls180.v:3147$655_Y - connect \libresocsim_wait $and$ls180.v:3148$658_Y - connect \libresocsim_done $eq$ls180.v:3161$676_Y - connect \libresocsim_csrbank0_sel $eq$ls180.v:3162$677_Y + connect \libresocsim_ram_bus_cyc $and$ls180.v:3132$645_Y + connect \ram_bus_ram_bus_cyc $and$ls180.v:3133$646_Y + connect \libresocsim_libresoc_xics_icp_cyc $and$ls180.v:3134$647_Y + connect \libresocsim_libresoc_xics_ics_cyc $and$ls180.v:3135$648_Y + connect \wb_sdram_cyc $and$ls180.v:3136$649_Y + connect \libresocsim_libresocsim_wishbone_cyc $and$ls180.v:3137$650_Y + connect \libresocsim_shared_err $or$ls180.v:3138$655_Y + connect \libresocsim_wait $and$ls180.v:3139$658_Y + connect \libresocsim_done $eq$ls180.v:3152$676_Y + connect \libresocsim_csrbank0_sel $eq$ls180.v:3153$677_Y connect \libresocsim_csrbank0_reset0_r \libresocsim_interface0_bank_bus_dat_w [0] - connect \libresocsim_csrbank0_reset0_re $and$ls180.v:3164$680_Y - connect \libresocsim_csrbank0_reset0_we $and$ls180.v:3165$684_Y + connect \libresocsim_csrbank0_reset0_re $and$ls180.v:3155$680_Y + connect \libresocsim_csrbank0_reset0_we $and$ls180.v:3156$684_Y connect \libresocsim_csrbank0_scratch3_r \libresocsim_interface0_bank_bus_dat_w - connect \libresocsim_csrbank0_scratch3_re $and$ls180.v:3167$687_Y - connect \libresocsim_csrbank0_scratch3_we $and$ls180.v:3168$691_Y + connect \libresocsim_csrbank0_scratch3_re $and$ls180.v:3158$687_Y + connect \libresocsim_csrbank0_scratch3_we $and$ls180.v:3159$691_Y connect \libresocsim_csrbank0_scratch2_r \libresocsim_interface0_bank_bus_dat_w - connect \libresocsim_csrbank0_scratch2_re $and$ls180.v:3170$694_Y - connect \libresocsim_csrbank0_scratch2_we $and$ls180.v:3171$698_Y + connect \libresocsim_csrbank0_scratch2_re $and$ls180.v:3161$694_Y + connect \libresocsim_csrbank0_scratch2_we $and$ls180.v:3162$698_Y connect \libresocsim_csrbank0_scratch1_r \libresocsim_interface0_bank_bus_dat_w - connect \libresocsim_csrbank0_scratch1_re $and$ls180.v:3173$701_Y - connect \libresocsim_csrbank0_scratch1_we $and$ls180.v:3174$705_Y + connect \libresocsim_csrbank0_scratch1_re $and$ls180.v:3164$701_Y + connect \libresocsim_csrbank0_scratch1_we $and$ls180.v:3165$705_Y connect \libresocsim_csrbank0_scratch0_r \libresocsim_interface0_bank_bus_dat_w - connect \libresocsim_csrbank0_scratch0_re $and$ls180.v:3176$708_Y - connect \libresocsim_csrbank0_scratch0_we $and$ls180.v:3177$712_Y + connect \libresocsim_csrbank0_scratch0_re $and$ls180.v:3167$708_Y + connect \libresocsim_csrbank0_scratch0_we $and$ls180.v:3168$712_Y connect \libresocsim_csrbank0_bus_errors3_r \libresocsim_interface0_bank_bus_dat_w - connect \libresocsim_csrbank0_bus_errors3_re $and$ls180.v:3179$715_Y - connect \libresocsim_csrbank0_bus_errors3_we $and$ls180.v:3180$719_Y + connect \libresocsim_csrbank0_bus_errors3_re $and$ls180.v:3170$715_Y + connect \libresocsim_csrbank0_bus_errors3_we $and$ls180.v:3171$719_Y connect \libresocsim_csrbank0_bus_errors2_r \libresocsim_interface0_bank_bus_dat_w - connect \libresocsim_csrbank0_bus_errors2_re $and$ls180.v:3182$722_Y - connect \libresocsim_csrbank0_bus_errors2_we $and$ls180.v:3183$726_Y + connect \libresocsim_csrbank0_bus_errors2_re $and$ls180.v:3173$722_Y + connect \libresocsim_csrbank0_bus_errors2_we $and$ls180.v:3174$726_Y connect \libresocsim_csrbank0_bus_errors1_r \libresocsim_interface0_bank_bus_dat_w - connect \libresocsim_csrbank0_bus_errors1_re $and$ls180.v:3185$729_Y - connect \libresocsim_csrbank0_bus_errors1_we $and$ls180.v:3186$733_Y + connect \libresocsim_csrbank0_bus_errors1_re $and$ls180.v:3176$729_Y + connect \libresocsim_csrbank0_bus_errors1_we $and$ls180.v:3177$733_Y connect \libresocsim_csrbank0_bus_errors0_r \libresocsim_interface0_bank_bus_dat_w - connect \libresocsim_csrbank0_bus_errors0_re $and$ls180.v:3188$736_Y - connect \libresocsim_csrbank0_bus_errors0_we $and$ls180.v:3189$740_Y + connect \libresocsim_csrbank0_bus_errors0_re $and$ls180.v:3179$736_Y + connect \libresocsim_csrbank0_bus_errors0_we $and$ls180.v:3180$740_Y connect \libresocsim_csrbank0_reset0_w \libresocsim_reset_storage connect \libresocsim_csrbank0_scratch3_w \libresocsim_scratch_storage [31:24] connect \libresocsim_csrbank0_scratch2_w \libresocsim_scratch_storage [23:16] @@ -271674,41 +271508,41 @@ module \ls180 connect \libresocsim_csrbank0_bus_errors1_w \libresocsim_bus_errors_status [15:8] connect \libresocsim_csrbank0_bus_errors0_w \libresocsim_bus_errors_status [7:0] connect \libresocsim_bus_errors_we \libresocsim_csrbank0_bus_errors0_we - connect \libresocsim_csrbank1_sel $eq$ls180.v:3200$741_Y + connect \libresocsim_csrbank1_sel $eq$ls180.v:3191$741_Y connect \libresocsim_csrbank1_oe0_r \libresocsim_interface1_bank_bus_dat_w - connect \libresocsim_csrbank1_oe0_re $and$ls180.v:3202$744_Y - connect \libresocsim_csrbank1_oe0_we $and$ls180.v:3203$748_Y + connect \libresocsim_csrbank1_oe0_re $and$ls180.v:3193$744_Y + connect \libresocsim_csrbank1_oe0_we $and$ls180.v:3194$748_Y connect \libresocsim_csrbank1_in_r \libresocsim_interface1_bank_bus_dat_w - connect \libresocsim_csrbank1_in_re $and$ls180.v:3205$751_Y - connect \libresocsim_csrbank1_in_we $and$ls180.v:3206$755_Y + connect \libresocsim_csrbank1_in_re $and$ls180.v:3196$751_Y + connect \libresocsim_csrbank1_in_we $and$ls180.v:3197$755_Y connect \libresocsim_csrbank1_out0_r \libresocsim_interface1_bank_bus_dat_w - connect \libresocsim_csrbank1_out0_re $and$ls180.v:3208$758_Y - connect \libresocsim_csrbank1_out0_we $and$ls180.v:3209$762_Y + connect \libresocsim_csrbank1_out0_re $and$ls180.v:3199$758_Y + connect \libresocsim_csrbank1_out0_we $and$ls180.v:3200$762_Y connect \libresocsim_csrbank1_oe0_w \gpio0_oe_storage connect \libresocsim_csrbank1_in_w \gpio0_status connect \gpio0_we \libresocsim_csrbank1_in_we connect \libresocsim_csrbank1_out0_w \gpio0_out_storage - connect \libresocsim_csrbank2_sel $eq$ls180.v:3214$763_Y + connect \libresocsim_csrbank2_sel $eq$ls180.v:3205$763_Y connect \libresocsim_csrbank2_oe0_r \libresocsim_interface2_bank_bus_dat_w - connect \libresocsim_csrbank2_oe0_re $and$ls180.v:3216$766_Y - connect \libresocsim_csrbank2_oe0_we $and$ls180.v:3217$770_Y + connect \libresocsim_csrbank2_oe0_re $and$ls180.v:3207$766_Y + connect \libresocsim_csrbank2_oe0_we $and$ls180.v:3208$770_Y connect \libresocsim_csrbank2_in_r \libresocsim_interface2_bank_bus_dat_w - connect \libresocsim_csrbank2_in_re $and$ls180.v:3219$773_Y - connect \libresocsim_csrbank2_in_we $and$ls180.v:3220$777_Y + connect \libresocsim_csrbank2_in_re $and$ls180.v:3210$773_Y + connect \libresocsim_csrbank2_in_we $and$ls180.v:3211$777_Y connect \libresocsim_csrbank2_out0_r \libresocsim_interface2_bank_bus_dat_w - connect \libresocsim_csrbank2_out0_re $and$ls180.v:3222$780_Y - connect \libresocsim_csrbank2_out0_we $and$ls180.v:3223$784_Y + connect \libresocsim_csrbank2_out0_re $and$ls180.v:3213$780_Y + connect \libresocsim_csrbank2_out0_we $and$ls180.v:3214$784_Y connect \libresocsim_csrbank2_oe0_w \gpio1_oe_storage connect \libresocsim_csrbank2_in_w \gpio1_status connect \gpio1_we \libresocsim_csrbank2_in_we connect \libresocsim_csrbank2_out0_w \gpio1_out_storage - connect \libresocsim_csrbank3_sel $eq$ls180.v:3228$785_Y + connect \libresocsim_csrbank3_sel $eq$ls180.v:3219$785_Y connect \libresocsim_csrbank3_w0_r \libresocsim_interface3_bank_bus_dat_w [2:0] - connect \libresocsim_csrbank3_w0_re $and$ls180.v:3230$788_Y - connect \libresocsim_csrbank3_w0_we $and$ls180.v:3231$792_Y + connect \libresocsim_csrbank3_w0_re $and$ls180.v:3221$788_Y + connect \libresocsim_csrbank3_w0_we $and$ls180.v:3222$792_Y connect \libresocsim_csrbank3_r_r \libresocsim_interface3_bank_bus_dat_w [0] - connect \libresocsim_csrbank3_r_re $and$ls180.v:3233$795_Y - connect \libresocsim_csrbank3_r_we $and$ls180.v:3234$799_Y + connect \libresocsim_csrbank3_r_re $and$ls180.v:3224$795_Y + connect \libresocsim_csrbank3_r_we $and$ls180.v:3225$799_Y connect \i2c_scl_1 \i2c_storage [0] connect \i2c_oe \i2c_storage [1] connect \i2c_sda0 \i2c_storage [2] @@ -271716,37 +271550,37 @@ module \ls180 connect \i2c_status \i2c_sda1 connect \libresocsim_csrbank3_r_w \i2c_status connect \i2c_we \libresocsim_csrbank3_r_we - connect \libresocsim_csrbank4_sel $eq$ls180.v:3242$800_Y + connect \libresocsim_csrbank4_sel $eq$ls180.v:3233$800_Y connect \libresocsim_csrbank4_dfii_control0_r \libresocsim_interface4_bank_bus_dat_w [3:0] - connect \libresocsim_csrbank4_dfii_control0_re $and$ls180.v:3244$803_Y - connect \libresocsim_csrbank4_dfii_control0_we $and$ls180.v:3245$807_Y + connect \libresocsim_csrbank4_dfii_control0_re $and$ls180.v:3235$803_Y + connect \libresocsim_csrbank4_dfii_control0_we $and$ls180.v:3236$807_Y connect \libresocsim_csrbank4_dfii_pi0_command0_r \libresocsim_interface4_bank_bus_dat_w [5:0] - connect \libresocsim_csrbank4_dfii_pi0_command0_re $and$ls180.v:3247$810_Y - connect \libresocsim_csrbank4_dfii_pi0_command0_we $and$ls180.v:3248$814_Y + connect \libresocsim_csrbank4_dfii_pi0_command0_re $and$ls180.v:3238$810_Y + connect \libresocsim_csrbank4_dfii_pi0_command0_we $and$ls180.v:3239$814_Y connect \sdram_command_issue_r \libresocsim_interface4_bank_bus_dat_w [0] - connect \sdram_command_issue_re $and$ls180.v:3250$817_Y - connect \sdram_command_issue_we $and$ls180.v:3251$821_Y + connect \sdram_command_issue_re $and$ls180.v:3241$817_Y + connect \sdram_command_issue_we $and$ls180.v:3242$821_Y connect \libresocsim_csrbank4_dfii_pi0_address1_r \libresocsim_interface4_bank_bus_dat_w [4:0] - connect \libresocsim_csrbank4_dfii_pi0_address1_re $and$ls180.v:3253$824_Y - connect \libresocsim_csrbank4_dfii_pi0_address1_we $and$ls180.v:3254$828_Y + connect \libresocsim_csrbank4_dfii_pi0_address1_re $and$ls180.v:3244$824_Y + connect \libresocsim_csrbank4_dfii_pi0_address1_we $and$ls180.v:3245$828_Y connect \libresocsim_csrbank4_dfii_pi0_address0_r \libresocsim_interface4_bank_bus_dat_w - connect \libresocsim_csrbank4_dfii_pi0_address0_re $and$ls180.v:3256$831_Y - connect \libresocsim_csrbank4_dfii_pi0_address0_we $and$ls180.v:3257$835_Y + connect \libresocsim_csrbank4_dfii_pi0_address0_re $and$ls180.v:3247$831_Y + connect \libresocsim_csrbank4_dfii_pi0_address0_we $and$ls180.v:3248$835_Y connect \libresocsim_csrbank4_dfii_pi0_baddress0_r \libresocsim_interface4_bank_bus_dat_w [1:0] - connect \libresocsim_csrbank4_dfii_pi0_baddress0_re $and$ls180.v:3259$838_Y - connect \libresocsim_csrbank4_dfii_pi0_baddress0_we $and$ls180.v:3260$842_Y + connect \libresocsim_csrbank4_dfii_pi0_baddress0_re $and$ls180.v:3250$838_Y + connect \libresocsim_csrbank4_dfii_pi0_baddress0_we $and$ls180.v:3251$842_Y connect \libresocsim_csrbank4_dfii_pi0_wrdata1_r \libresocsim_interface4_bank_bus_dat_w - connect \libresocsim_csrbank4_dfii_pi0_wrdata1_re $and$ls180.v:3262$845_Y - connect \libresocsim_csrbank4_dfii_pi0_wrdata1_we $and$ls180.v:3263$849_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata1_re $and$ls180.v:3253$845_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata1_we $and$ls180.v:3254$849_Y connect \libresocsim_csrbank4_dfii_pi0_wrdata0_r \libresocsim_interface4_bank_bus_dat_w - connect \libresocsim_csrbank4_dfii_pi0_wrdata0_re $and$ls180.v:3265$852_Y - connect \libresocsim_csrbank4_dfii_pi0_wrdata0_we $and$ls180.v:3266$856_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata0_re $and$ls180.v:3256$852_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata0_we $and$ls180.v:3257$856_Y connect \libresocsim_csrbank4_dfii_pi0_rddata1_r \libresocsim_interface4_bank_bus_dat_w - connect \libresocsim_csrbank4_dfii_pi0_rddata1_re $and$ls180.v:3268$859_Y - connect \libresocsim_csrbank4_dfii_pi0_rddata1_we $and$ls180.v:3269$863_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata1_re $and$ls180.v:3259$859_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata1_we $and$ls180.v:3260$863_Y connect \libresocsim_csrbank4_dfii_pi0_rddata0_r \libresocsim_interface4_bank_bus_dat_w - connect \libresocsim_csrbank4_dfii_pi0_rddata0_re $and$ls180.v:3271$866_Y - connect \libresocsim_csrbank4_dfii_pi0_rddata0_we $and$ls180.v:3272$870_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata0_re $and$ls180.v:3262$866_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata0_we $and$ls180.v:3263$870_Y connect \sdram_sel \sdram_storage [0] connect \sdram_cke_1 \sdram_storage [1] connect \sdram_odt \sdram_storage [2] @@ -271761,58 +271595,58 @@ module \ls180 connect \libresocsim_csrbank4_dfii_pi0_rddata1_w \sdram_status [15:8] connect \libresocsim_csrbank4_dfii_pi0_rddata0_w \sdram_status [7:0] connect \sdram_we \libresocsim_csrbank4_dfii_pi0_rddata0_we - connect \libresocsim_csrbank5_sel $eq$ls180.v:3287$871_Y + connect \libresocsim_csrbank5_sel $eq$ls180.v:3278$871_Y connect \libresocsim_csrbank5_load3_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_load3_re $and$ls180.v:3289$874_Y - connect \libresocsim_csrbank5_load3_we $and$ls180.v:3290$878_Y + connect \libresocsim_csrbank5_load3_re $and$ls180.v:3280$874_Y + connect \libresocsim_csrbank5_load3_we $and$ls180.v:3281$878_Y connect \libresocsim_csrbank5_load2_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_load2_re $and$ls180.v:3292$881_Y - connect \libresocsim_csrbank5_load2_we $and$ls180.v:3293$885_Y + connect \libresocsim_csrbank5_load2_re $and$ls180.v:3283$881_Y + connect \libresocsim_csrbank5_load2_we $and$ls180.v:3284$885_Y connect \libresocsim_csrbank5_load1_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_load1_re $and$ls180.v:3295$888_Y - connect \libresocsim_csrbank5_load1_we $and$ls180.v:3296$892_Y + connect \libresocsim_csrbank5_load1_re $and$ls180.v:3286$888_Y + connect \libresocsim_csrbank5_load1_we $and$ls180.v:3287$892_Y connect \libresocsim_csrbank5_load0_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_load0_re $and$ls180.v:3298$895_Y - connect \libresocsim_csrbank5_load0_we $and$ls180.v:3299$899_Y + connect \libresocsim_csrbank5_load0_re $and$ls180.v:3289$895_Y + connect \libresocsim_csrbank5_load0_we $and$ls180.v:3290$899_Y connect \libresocsim_csrbank5_reload3_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_reload3_re $and$ls180.v:3301$902_Y - connect \libresocsim_csrbank5_reload3_we $and$ls180.v:3302$906_Y + connect \libresocsim_csrbank5_reload3_re $and$ls180.v:3292$902_Y + connect \libresocsim_csrbank5_reload3_we $and$ls180.v:3293$906_Y connect \libresocsim_csrbank5_reload2_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_reload2_re $and$ls180.v:3304$909_Y - connect \libresocsim_csrbank5_reload2_we $and$ls180.v:3305$913_Y + connect \libresocsim_csrbank5_reload2_re $and$ls180.v:3295$909_Y + connect \libresocsim_csrbank5_reload2_we $and$ls180.v:3296$913_Y connect \libresocsim_csrbank5_reload1_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_reload1_re $and$ls180.v:3307$916_Y - connect \libresocsim_csrbank5_reload1_we $and$ls180.v:3308$920_Y + connect \libresocsim_csrbank5_reload1_re $and$ls180.v:3298$916_Y + connect \libresocsim_csrbank5_reload1_we $and$ls180.v:3299$920_Y connect \libresocsim_csrbank5_reload0_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_reload0_re $and$ls180.v:3310$923_Y - connect \libresocsim_csrbank5_reload0_we $and$ls180.v:3311$927_Y + connect \libresocsim_csrbank5_reload0_re $and$ls180.v:3301$923_Y + connect \libresocsim_csrbank5_reload0_we $and$ls180.v:3302$927_Y connect \libresocsim_csrbank5_en0_r \libresocsim_interface5_bank_bus_dat_w [0] - connect \libresocsim_csrbank5_en0_re $and$ls180.v:3313$930_Y - connect \libresocsim_csrbank5_en0_we $and$ls180.v:3314$934_Y + connect \libresocsim_csrbank5_en0_re $and$ls180.v:3304$930_Y + connect \libresocsim_csrbank5_en0_we $and$ls180.v:3305$934_Y connect \libresocsim_csrbank5_update_value0_r \libresocsim_interface5_bank_bus_dat_w [0] - connect \libresocsim_csrbank5_update_value0_re $and$ls180.v:3316$937_Y - connect \libresocsim_csrbank5_update_value0_we $and$ls180.v:3317$941_Y + connect \libresocsim_csrbank5_update_value0_re $and$ls180.v:3307$937_Y + connect \libresocsim_csrbank5_update_value0_we $and$ls180.v:3308$941_Y connect \libresocsim_csrbank5_value3_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_value3_re $and$ls180.v:3319$944_Y - connect \libresocsim_csrbank5_value3_we $and$ls180.v:3320$948_Y + connect \libresocsim_csrbank5_value3_re $and$ls180.v:3310$944_Y + connect \libresocsim_csrbank5_value3_we $and$ls180.v:3311$948_Y connect \libresocsim_csrbank5_value2_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_value2_re $and$ls180.v:3322$951_Y - connect \libresocsim_csrbank5_value2_we $and$ls180.v:3323$955_Y + connect \libresocsim_csrbank5_value2_re $and$ls180.v:3313$951_Y + connect \libresocsim_csrbank5_value2_we $and$ls180.v:3314$955_Y connect \libresocsim_csrbank5_value1_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_value1_re $and$ls180.v:3325$958_Y - connect \libresocsim_csrbank5_value1_we $and$ls180.v:3326$962_Y + connect \libresocsim_csrbank5_value1_re $and$ls180.v:3316$958_Y + connect \libresocsim_csrbank5_value1_we $and$ls180.v:3317$962_Y connect \libresocsim_csrbank5_value0_r \libresocsim_interface5_bank_bus_dat_w - connect \libresocsim_csrbank5_value0_re $and$ls180.v:3328$965_Y - connect \libresocsim_csrbank5_value0_we $and$ls180.v:3329$969_Y + connect \libresocsim_csrbank5_value0_re $and$ls180.v:3319$965_Y + connect \libresocsim_csrbank5_value0_we $and$ls180.v:3320$969_Y connect \libresocsim_eventmanager_status_r \libresocsim_interface5_bank_bus_dat_w [0] - connect \libresocsim_eventmanager_status_re $and$ls180.v:3331$972_Y - connect \libresocsim_eventmanager_status_we $and$ls180.v:3332$976_Y + connect \libresocsim_eventmanager_status_re $and$ls180.v:3322$972_Y + connect \libresocsim_eventmanager_status_we $and$ls180.v:3323$976_Y connect \libresocsim_eventmanager_pending_r \libresocsim_interface5_bank_bus_dat_w [0] - connect \libresocsim_eventmanager_pending_re $and$ls180.v:3334$979_Y - connect \libresocsim_eventmanager_pending_we $and$ls180.v:3335$983_Y + connect \libresocsim_eventmanager_pending_re $and$ls180.v:3325$979_Y + connect \libresocsim_eventmanager_pending_we $and$ls180.v:3326$983_Y connect \libresocsim_csrbank5_ev_enable0_r \libresocsim_interface5_bank_bus_dat_w [0] - connect \libresocsim_csrbank5_ev_enable0_re $and$ls180.v:3337$986_Y - connect \libresocsim_csrbank5_ev_enable0_we $and$ls180.v:3338$990_Y + connect \libresocsim_csrbank5_ev_enable0_re $and$ls180.v:3328$986_Y + connect \libresocsim_csrbank5_ev_enable0_we $and$ls180.v:3329$990_Y connect \libresocsim_csrbank5_load3_w \libresocsim_load_storage [31:24] connect \libresocsim_csrbank5_load2_w \libresocsim_load_storage [23:16] connect \libresocsim_csrbank5_load1_w \libresocsim_load_storage [15:8] @@ -271829,31 +271663,31 @@ module \ls180 connect \libresocsim_csrbank5_value0_w \libresocsim_value_status [7:0] connect \libresocsim_value_we \libresocsim_csrbank5_value0_we connect \libresocsim_csrbank5_ev_enable0_w \libresocsim_eventmanager_storage - connect \libresocsim_csrbank6_sel $eq$ls180.v:3355$991_Y + connect \libresocsim_csrbank6_sel $eq$ls180.v:3346$991_Y connect \rxtx_r \libresocsim_interface6_bank_bus_dat_w - connect \rxtx_re $and$ls180.v:3357$994_Y - connect \rxtx_we $and$ls180.v:3358$998_Y + connect \rxtx_re $and$ls180.v:3348$994_Y + connect \rxtx_we $and$ls180.v:3349$998_Y connect \libresocsim_csrbank6_txfull_r \libresocsim_interface6_bank_bus_dat_w [0] - connect \libresocsim_csrbank6_txfull_re $and$ls180.v:3360$1001_Y - connect \libresocsim_csrbank6_txfull_we $and$ls180.v:3361$1005_Y + connect \libresocsim_csrbank6_txfull_re $and$ls180.v:3351$1001_Y + connect \libresocsim_csrbank6_txfull_we $and$ls180.v:3352$1005_Y connect \libresocsim_csrbank6_rxempty_r \libresocsim_interface6_bank_bus_dat_w [0] - connect \libresocsim_csrbank6_rxempty_re $and$ls180.v:3363$1008_Y - connect \libresocsim_csrbank6_rxempty_we $and$ls180.v:3364$1012_Y + connect \libresocsim_csrbank6_rxempty_re $and$ls180.v:3354$1008_Y + connect \libresocsim_csrbank6_rxempty_we $and$ls180.v:3355$1012_Y connect \eventmanager_status_r \libresocsim_interface6_bank_bus_dat_w [1:0] - connect \eventmanager_status_re $and$ls180.v:3366$1015_Y - connect \eventmanager_status_we $and$ls180.v:3367$1019_Y + connect \eventmanager_status_re $and$ls180.v:3357$1015_Y + connect \eventmanager_status_we $and$ls180.v:3358$1019_Y connect \eventmanager_pending_r \libresocsim_interface6_bank_bus_dat_w [1:0] - connect \eventmanager_pending_re $and$ls180.v:3369$1022_Y - connect \eventmanager_pending_we $and$ls180.v:3370$1026_Y + connect \eventmanager_pending_re $and$ls180.v:3360$1022_Y + connect \eventmanager_pending_we $and$ls180.v:3361$1026_Y connect \libresocsim_csrbank6_ev_enable0_r \libresocsim_interface6_bank_bus_dat_w [1:0] - connect \libresocsim_csrbank6_ev_enable0_re $and$ls180.v:3372$1029_Y - connect \libresocsim_csrbank6_ev_enable0_we $and$ls180.v:3373$1033_Y + connect \libresocsim_csrbank6_ev_enable0_re $and$ls180.v:3363$1029_Y + connect \libresocsim_csrbank6_ev_enable0_we $and$ls180.v:3364$1033_Y connect \libresocsim_csrbank6_txempty_r \libresocsim_interface6_bank_bus_dat_w [0] - connect \libresocsim_csrbank6_txempty_re $and$ls180.v:3375$1036_Y - connect \libresocsim_csrbank6_txempty_we $and$ls180.v:3376$1040_Y + connect \libresocsim_csrbank6_txempty_re $and$ls180.v:3366$1036_Y + connect \libresocsim_csrbank6_txempty_we $and$ls180.v:3367$1040_Y connect \libresocsim_csrbank6_rxfull_r \libresocsim_interface6_bank_bus_dat_w [0] - connect \libresocsim_csrbank6_rxfull_re $and$ls180.v:3378$1043_Y - connect \libresocsim_csrbank6_rxfull_we $and$ls180.v:3379$1047_Y + connect \libresocsim_csrbank6_rxfull_re $and$ls180.v:3369$1043_Y + connect \libresocsim_csrbank6_rxfull_we $and$ls180.v:3370$1047_Y connect \libresocsim_csrbank6_txfull_w \txfull_status connect \txfull_we \libresocsim_csrbank6_txfull_we connect \libresocsim_csrbank6_rxempty_w \rxempty_status @@ -271863,19 +271697,19 @@ module \ls180 connect \txempty_we \libresocsim_csrbank6_txempty_we connect \libresocsim_csrbank6_rxfull_w \rxfull_status connect \rxfull_we \libresocsim_csrbank6_rxfull_we - connect \libresocsim_csrbank7_sel $eq$ls180.v:3389$1048_Y + connect \libresocsim_csrbank7_sel $eq$ls180.v:3380$1048_Y connect \libresocsim_csrbank7_tuning_word3_r \libresocsim_interface7_bank_bus_dat_w - connect \libresocsim_csrbank7_tuning_word3_re $and$ls180.v:3391$1051_Y - connect \libresocsim_csrbank7_tuning_word3_we $and$ls180.v:3392$1055_Y + connect \libresocsim_csrbank7_tuning_word3_re $and$ls180.v:3382$1051_Y + connect \libresocsim_csrbank7_tuning_word3_we $and$ls180.v:3383$1055_Y connect \libresocsim_csrbank7_tuning_word2_r \libresocsim_interface7_bank_bus_dat_w - connect \libresocsim_csrbank7_tuning_word2_re $and$ls180.v:3394$1058_Y - connect \libresocsim_csrbank7_tuning_word2_we $and$ls180.v:3395$1062_Y + connect \libresocsim_csrbank7_tuning_word2_re $and$ls180.v:3385$1058_Y + connect \libresocsim_csrbank7_tuning_word2_we $and$ls180.v:3386$1062_Y connect \libresocsim_csrbank7_tuning_word1_r \libresocsim_interface7_bank_bus_dat_w - connect \libresocsim_csrbank7_tuning_word1_re $and$ls180.v:3397$1065_Y - connect \libresocsim_csrbank7_tuning_word1_we $and$ls180.v:3398$1069_Y + connect \libresocsim_csrbank7_tuning_word1_re $and$ls180.v:3388$1065_Y + connect \libresocsim_csrbank7_tuning_word1_we $and$ls180.v:3389$1069_Y connect \libresocsim_csrbank7_tuning_word0_r \libresocsim_interface7_bank_bus_dat_w - connect \libresocsim_csrbank7_tuning_word0_re $and$ls180.v:3400$1072_Y - connect \libresocsim_csrbank7_tuning_word0_we $and$ls180.v:3401$1076_Y + connect \libresocsim_csrbank7_tuning_word0_re $and$ls180.v:3391$1072_Y + connect \libresocsim_csrbank7_tuning_word0_we $and$ls180.v:3392$1076_Y connect \libresocsim_csrbank7_tuning_word3_w \uart_phy_storage [31:24] connect \libresocsim_csrbank7_tuning_word2_w \uart_phy_storage [23:16] connect \libresocsim_csrbank7_tuning_word1_w \uart_phy_storage [15:8] @@ -271908,7 +271742,7 @@ module \ls180 connect \libresocsim_interface5_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w connect \libresocsim_interface6_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w connect \libresocsim_interface7_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w - connect \libresocsim_csr_interconnect_dat_r $or$ls180.v:3434$1083_Y + connect \libresocsim_csr_interconnect_dat_r $or$ls180.v:3425$1083_Y connect \sdrio_clk \sys_clk_1 connect \sdrio_clk_1 \sys_clk_1 connect \sdrio_clk_2 \sys_clk_1 @@ -272014,52 +271848,52 @@ module \ls180 connect \sdrio_clk_101 \sys_clk_1 connect \sdrio_clk_102 \sys_clk_1 connect \sdrio_clk_103 \sys_clk_1 - connect \libresocsim_dat_r $memrd$\mem$ls180.v:5507$1459_DATA - connect \ram_dat_r $memrd$\mem_1$ls180.v:5527$1485_DATA + connect \libresocsim_dat_r $memrd$\mem$ls180.v:5502$1463_DATA + connect \ram_dat_r $memrd$\mem_1$ls180.v:5522$1489_DATA connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:5545$1495_DATA + connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:5540$1499_DATA connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:5559$1505_DATA + connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:5554$1509_DATA connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:5573$1515_DATA + connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:5568$1519_DATA connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:5587$1525_DATA + connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:5582$1529_DATA connect \tx_fifo_wrport_dat_r \memdat_4 connect \tx_fifo_rdport_dat_r \memdat_5 connect \rx_fifo_wrport_dat_r \memdat_6 connect \rx_fifo_rdport_dat_r \memdat_7 end -attribute \src "libresoc.v:147105.1-147163.10" +attribute \src "libresoc.v:146901.1-146959.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" attribute \generator "nMigen" module \lsd_l - attribute \src "libresoc.v:147106.7-147106.20" + attribute \src "libresoc.v:146902.7-146902.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147151.3-147159.6" + attribute \src "libresoc.v:146947.3-146955.6" wire $0\q_int$next[0:0]$7081 - attribute \src "libresoc.v:147149.3-147150.27" + attribute \src "libresoc.v:146945.3-146946.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:147151.3-147159.6" + attribute \src "libresoc.v:146947.3-146955.6" wire $1\q_int$next[0:0]$7082 - attribute \src "libresoc.v:147128.7-147128.19" + attribute \src "libresoc.v:146924.7-146924.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:147141.17-147141.96" - wire $and$libresoc.v:147141$7071_Y - attribute \src "libresoc.v:147146.17-147146.96" - wire $and$libresoc.v:147146$7076_Y - attribute \src "libresoc.v:147143.18-147143.93" - wire $not$libresoc.v:147143$7073_Y - attribute \src "libresoc.v:147145.17-147145.92" - wire $not$libresoc.v:147145$7075_Y - attribute \src "libresoc.v:147148.17-147148.92" - wire $not$libresoc.v:147148$7078_Y - attribute \src "libresoc.v:147142.18-147142.98" - wire $or$libresoc.v:147142$7072_Y - attribute \src "libresoc.v:147144.18-147144.99" - wire $or$libresoc.v:147144$7074_Y - attribute \src "libresoc.v:147147.17-147147.97" - wire $or$libresoc.v:147147$7077_Y + attribute \src "libresoc.v:146937.17-146937.96" + wire $and$libresoc.v:146937$7071_Y + attribute \src "libresoc.v:146942.17-146942.96" + wire $and$libresoc.v:146942$7076_Y + attribute \src "libresoc.v:146939.18-146939.93" + wire $not$libresoc.v:146939$7073_Y + attribute \src "libresoc.v:146941.17-146941.92" + wire $not$libresoc.v:146941$7075_Y + attribute \src "libresoc.v:146944.17-146944.92" + wire $not$libresoc.v:146944$7078_Y + attribute \src "libresoc.v:146938.18-146938.98" + wire $or$libresoc.v:146938$7072_Y + attribute \src "libresoc.v:146940.18-146940.99" + wire $or$libresoc.v:146940$7074_Y + attribute \src "libresoc.v:146943.17-146943.97" + wire $or$libresoc.v:146943$7077_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -272076,11 +271910,11 @@ module \lsd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:147106.7-147106.15" + attribute \src "libresoc.v:146902.7-146902.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -272097,7 +271931,7 @@ module \lsd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:147141$7071 + cell $and $and$libresoc.v:146937$7071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272105,10 +271939,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:147141$7071_Y + connect \Y $and$libresoc.v:146937$7071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:147146$7076 + cell $and $and$libresoc.v:146942$7076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272116,34 +271950,34 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:147146$7076_Y + connect \Y $and$libresoc.v:146942$7076_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:147143$7073 + cell $not $not$libresoc.v:146939$7073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lsd - connect \Y $not$libresoc.v:147143$7073_Y + connect \Y $not$libresoc.v:146939$7073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:147145$7075 + cell $not $not$libresoc.v:146941$7075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:147145$7075_Y + connect \Y $not$libresoc.v:146941$7075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:147148$7078 + cell $not $not$libresoc.v:146944$7078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:147148$7078_Y + connect \Y $not$libresoc.v:146944$7078_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:147142$7072 + cell $or $or$libresoc.v:146938$7072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272151,10 +271985,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lsd - connect \Y $or$libresoc.v:147142$7072_Y + connect \Y $or$libresoc.v:146938$7072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:147144$7074 + cell $or $or$libresoc.v:146940$7074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272162,10 +271996,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_lsd connect \B \q_int - connect \Y $or$libresoc.v:147144$7074_Y + connect \Y $or$libresoc.v:146940$7074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:147147$7077 + cell $or $or$libresoc.v:146943$7077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272173,39 +272007,39 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lsd - connect \Y $or$libresoc.v:147147$7077_Y + connect \Y $or$libresoc.v:146943$7077_Y end - attribute \src "libresoc.v:147106.7-147106.20" - process $proc$libresoc.v:147106$7083 + attribute \src "libresoc.v:146902.7-146902.20" + process $proc$libresoc.v:146902$7083 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147128.7-147128.19" - process $proc$libresoc.v:147128$7084 + attribute \src "libresoc.v:146924.7-146924.19" + process $proc$libresoc.v:146924$7084 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:147149.3-147150.27" - process $proc$libresoc.v:147149$7079 + attribute \src "libresoc.v:146945.3-146946.27" + process $proc$libresoc.v:146945$7079 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:147151.3-147159.6" - process $proc$libresoc.v:147151$7080 + attribute \src "libresoc.v:146947.3-146955.6" + process $proc$libresoc.v:146947$7080 assign { } { } assign { } { } assign $0\q_int$next[0:0]$7081 $1\q_int$next[0:0]$7082 - attribute \src "libresoc.v:147152.5-147152.29" + attribute \src "libresoc.v:146948.5-146948.29" switch \initial - attribute \src "libresoc.v:147152.9-147152.17" + attribute \src "libresoc.v:146948.9-146948.17" case 1'1 case end @@ -272221,259 +272055,259 @@ module \lsd_l sync always update \q_int$next $0\q_int$next[0:0]$7081 end - connect \$9 $and$libresoc.v:147141$7071_Y - connect \$11 $or$libresoc.v:147142$7072_Y - connect \$13 $not$libresoc.v:147143$7073_Y - connect \$15 $or$libresoc.v:147144$7074_Y - connect \$1 $not$libresoc.v:147145$7075_Y - connect \$3 $and$libresoc.v:147146$7076_Y - connect \$5 $or$libresoc.v:147147$7077_Y - connect \$7 $not$libresoc.v:147148$7078_Y + connect \$9 $and$libresoc.v:146937$7071_Y + connect \$11 $or$libresoc.v:146938$7072_Y + connect \$13 $not$libresoc.v:146939$7073_Y + connect \$15 $or$libresoc.v:146940$7074_Y + connect \$1 $not$libresoc.v:146941$7075_Y + connect \$3 $and$libresoc.v:146942$7076_Y + connect \$5 $or$libresoc.v:146943$7077_Y + connect \$7 $not$libresoc.v:146944$7078_Y connect \qlq_lsd \$15 connect \qn_lsd \$13 connect \q_lsd \$11 end -attribute \src "libresoc.v:147167.1-147701.10" +attribute \src "libresoc.v:146963.1-147497.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" attribute \generator "nMigen" module \lsmem - attribute \src "libresoc.v:147555.3-147580.6" + attribute \src "libresoc.v:147351.3-147376.6" wire width 45 $0\dbus__adr$next[44:0]$7170 - attribute \src "libresoc.v:147405.3-147406.35" + attribute \src "libresoc.v:147201.3-147202.35" wire width 45 $0\dbus__adr[44:0] - attribute \src "libresoc.v:147415.3-147442.6" + attribute \src "libresoc.v:147211.3-147238.6" wire $0\dbus__cyc$next[0:0]$7144 - attribute \src "libresoc.v:147413.3-147414.35" + attribute \src "libresoc.v:147209.3-147210.35" wire $0\dbus__cyc[0:0] - attribute \src "libresoc.v:147607.3-147632.6" + attribute \src "libresoc.v:147403.3-147428.6" wire width 64 $0\dbus__dat_w$next[63:0]$7180 - attribute \src "libresoc.v:147401.3-147402.39" + attribute \src "libresoc.v:147197.3-147198.39" wire width 64 $0\dbus__dat_w[63:0] - attribute \src "libresoc.v:147499.3-147529.6" + attribute \src "libresoc.v:147295.3-147325.6" wire width 8 $0\dbus__sel$next[7:0]$7158 - attribute \src "libresoc.v:147409.3-147410.35" + attribute \src "libresoc.v:147205.3-147206.35" wire width 8 $0\dbus__sel[7:0] - attribute \src "libresoc.v:147443.3-147470.6" + attribute \src "libresoc.v:147239.3-147266.6" wire $0\dbus__stb$next[0:0]$7150 - attribute \src "libresoc.v:147411.3-147412.35" + attribute \src "libresoc.v:147207.3-147208.35" wire $0\dbus__stb[0:0] - attribute \src "libresoc.v:147581.3-147606.6" + attribute \src "libresoc.v:147377.3-147402.6" wire $0\dbus__we$next[0:0]$7175 - attribute \src "libresoc.v:147403.3-147404.33" + attribute \src "libresoc.v:147199.3-147200.33" wire $0\dbus__we[0:0] - attribute \src "libresoc.v:147168.7-147168.20" + attribute \src "libresoc.v:146964.7-146964.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147679.3-147698.6" + attribute \src "libresoc.v:147475.3-147494.6" wire width 45 $0\m_badaddr_o$next[44:0]$7195 - attribute \src "libresoc.v:147395.3-147396.39" + attribute \src "libresoc.v:147191.3-147192.39" wire width 45 $0\m_badaddr_o[44:0] - attribute \src "libresoc.v:147481.3-147498.6" + attribute \src "libresoc.v:147277.3-147294.6" wire $0\m_busy_o[0:0] - attribute \src "libresoc.v:147530.3-147554.6" + attribute \src "libresoc.v:147326.3-147350.6" wire width 64 $0\m_ld_data_o$next[63:0]$7164 - attribute \src "libresoc.v:147407.3-147408.39" + attribute \src "libresoc.v:147203.3-147204.39" wire width 64 $0\m_ld_data_o[63:0] - attribute \src "libresoc.v:147633.3-147655.6" + attribute \src "libresoc.v:147429.3-147451.6" wire $0\m_load_err_o$next[0:0]$7185 - attribute \src "libresoc.v:147399.3-147400.41" + attribute \src "libresoc.v:147195.3-147196.41" wire $0\m_load_err_o[0:0] - attribute \src "libresoc.v:147656.3-147678.6" + attribute \src "libresoc.v:147452.3-147474.6" wire $0\m_store_err_o$next[0:0]$7190 - attribute \src "libresoc.v:147397.3-147398.43" + attribute \src "libresoc.v:147193.3-147194.43" wire $0\m_store_err_o[0:0] - attribute \src "libresoc.v:147471.3-147480.6" + attribute \src "libresoc.v:147267.3-147276.6" wire $0\x_busy_o[0:0] - attribute \src "libresoc.v:147555.3-147580.6" + attribute \src "libresoc.v:147351.3-147376.6" wire width 45 $1\dbus__adr$next[44:0]$7171 - attribute \src "libresoc.v:147273.14-147273.42" + attribute \src "libresoc.v:147069.14-147069.42" wire width 45 $1\dbus__adr[44:0] - attribute \src "libresoc.v:147415.3-147442.6" + attribute \src "libresoc.v:147211.3-147238.6" wire $1\dbus__cyc$next[0:0]$7145 - attribute \src "libresoc.v:147278.7-147278.23" + attribute \src "libresoc.v:147074.7-147074.23" wire $1\dbus__cyc[0:0] - attribute \src "libresoc.v:147607.3-147632.6" + attribute \src "libresoc.v:147403.3-147428.6" wire width 64 $1\dbus__dat_w$next[63:0]$7181 - attribute \src "libresoc.v:147285.14-147285.48" + attribute \src "libresoc.v:147081.14-147081.48" wire width 64 $1\dbus__dat_w[63:0] - attribute \src "libresoc.v:147499.3-147529.6" + attribute \src "libresoc.v:147295.3-147325.6" wire width 8 $1\dbus__sel$next[7:0]$7159 - attribute \src "libresoc.v:147292.13-147292.30" + attribute \src "libresoc.v:147088.13-147088.30" wire width 8 $1\dbus__sel[7:0] - attribute \src "libresoc.v:147443.3-147470.6" + attribute \src "libresoc.v:147239.3-147266.6" wire $1\dbus__stb$next[0:0]$7151 - attribute \src "libresoc.v:147297.7-147297.23" + attribute \src "libresoc.v:147093.7-147093.23" wire $1\dbus__stb[0:0] - attribute \src "libresoc.v:147581.3-147606.6" + attribute \src "libresoc.v:147377.3-147402.6" wire $1\dbus__we$next[0:0]$7176 - attribute \src "libresoc.v:147302.7-147302.22" + attribute \src "libresoc.v:147098.7-147098.22" wire $1\dbus__we[0:0] - attribute \src "libresoc.v:147679.3-147698.6" + attribute \src "libresoc.v:147475.3-147494.6" wire width 45 $1\m_badaddr_o$next[44:0]$7196 - attribute \src "libresoc.v:147306.14-147306.44" + attribute \src "libresoc.v:147102.14-147102.44" wire width 45 $1\m_badaddr_o[44:0] - attribute \src "libresoc.v:147481.3-147498.6" + attribute \src "libresoc.v:147277.3-147294.6" wire $1\m_busy_o[0:0] - attribute \src "libresoc.v:147530.3-147554.6" + attribute \src "libresoc.v:147326.3-147350.6" wire width 64 $1\m_ld_data_o$next[63:0]$7165 - attribute \src "libresoc.v:147313.14-147313.48" + attribute \src "libresoc.v:147109.14-147109.48" wire width 64 $1\m_ld_data_o[63:0] - attribute \src "libresoc.v:147633.3-147655.6" + attribute \src "libresoc.v:147429.3-147451.6" wire $1\m_load_err_o$next[0:0]$7186 - attribute \src "libresoc.v:147317.7-147317.26" + attribute \src "libresoc.v:147113.7-147113.26" wire $1\m_load_err_o[0:0] - attribute \src "libresoc.v:147656.3-147678.6" + attribute \src "libresoc.v:147452.3-147474.6" wire $1\m_store_err_o$next[0:0]$7191 - attribute \src "libresoc.v:147323.7-147323.27" + attribute \src "libresoc.v:147119.7-147119.27" wire $1\m_store_err_o[0:0] - attribute \src "libresoc.v:147471.3-147480.6" + attribute \src "libresoc.v:147267.3-147276.6" wire $1\x_busy_o[0:0] - attribute \src "libresoc.v:147555.3-147580.6" + attribute \src "libresoc.v:147351.3-147376.6" wire width 45 $2\dbus__adr$next[44:0]$7172 - attribute \src "libresoc.v:147415.3-147442.6" + attribute \src "libresoc.v:147211.3-147238.6" wire $2\dbus__cyc$next[0:0]$7146 - attribute \src "libresoc.v:147607.3-147632.6" + attribute \src "libresoc.v:147403.3-147428.6" wire width 64 $2\dbus__dat_w$next[63:0]$7182 - attribute \src "libresoc.v:147499.3-147529.6" + attribute \src "libresoc.v:147295.3-147325.6" wire width 8 $2\dbus__sel$next[7:0]$7160 - attribute \src "libresoc.v:147443.3-147470.6" + attribute \src "libresoc.v:147239.3-147266.6" wire $2\dbus__stb$next[0:0]$7152 - attribute \src "libresoc.v:147581.3-147606.6" + attribute \src "libresoc.v:147377.3-147402.6" wire $2\dbus__we$next[0:0]$7177 - attribute \src "libresoc.v:147679.3-147698.6" + attribute \src "libresoc.v:147475.3-147494.6" wire width 45 $2\m_badaddr_o$next[44:0]$7197 - attribute \src "libresoc.v:147481.3-147498.6" + attribute \src "libresoc.v:147277.3-147294.6" wire $2\m_busy_o[0:0] - attribute \src "libresoc.v:147530.3-147554.6" + attribute \src "libresoc.v:147326.3-147350.6" wire width 64 $2\m_ld_data_o$next[63:0]$7166 - attribute \src "libresoc.v:147633.3-147655.6" + attribute \src "libresoc.v:147429.3-147451.6" wire $2\m_load_err_o$next[0:0]$7187 - attribute \src "libresoc.v:147656.3-147678.6" + attribute \src "libresoc.v:147452.3-147474.6" wire $2\m_store_err_o$next[0:0]$7192 - attribute \src "libresoc.v:147555.3-147580.6" + attribute \src "libresoc.v:147351.3-147376.6" wire width 45 $3\dbus__adr$next[44:0]$7173 - attribute \src "libresoc.v:147415.3-147442.6" + attribute \src "libresoc.v:147211.3-147238.6" wire $3\dbus__cyc$next[0:0]$7147 - attribute \src "libresoc.v:147607.3-147632.6" + attribute \src "libresoc.v:147403.3-147428.6" wire width 64 $3\dbus__dat_w$next[63:0]$7183 - attribute \src "libresoc.v:147499.3-147529.6" + attribute \src "libresoc.v:147295.3-147325.6" wire width 8 $3\dbus__sel$next[7:0]$7161 - attribute \src "libresoc.v:147443.3-147470.6" + attribute \src "libresoc.v:147239.3-147266.6" wire $3\dbus__stb$next[0:0]$7153 - attribute \src "libresoc.v:147581.3-147606.6" + attribute \src "libresoc.v:147377.3-147402.6" wire $3\dbus__we$next[0:0]$7178 - attribute \src "libresoc.v:147679.3-147698.6" + attribute \src "libresoc.v:147475.3-147494.6" wire width 45 $3\m_badaddr_o$next[44:0]$7198 - attribute \src "libresoc.v:147530.3-147554.6" + attribute \src "libresoc.v:147326.3-147350.6" wire width 64 $3\m_ld_data_o$next[63:0]$7167 - attribute \src "libresoc.v:147633.3-147655.6" + attribute \src "libresoc.v:147429.3-147451.6" wire $3\m_load_err_o$next[0:0]$7188 - attribute \src "libresoc.v:147656.3-147678.6" + attribute \src "libresoc.v:147452.3-147474.6" wire $3\m_store_err_o$next[0:0]$7193 - attribute \src "libresoc.v:147415.3-147442.6" + attribute \src "libresoc.v:147211.3-147238.6" wire $4\dbus__cyc$next[0:0]$7148 - attribute \src "libresoc.v:147499.3-147529.6" + attribute \src "libresoc.v:147295.3-147325.6" wire width 8 $4\dbus__sel$next[7:0]$7162 - attribute \src "libresoc.v:147443.3-147470.6" + attribute \src "libresoc.v:147239.3-147266.6" wire $4\dbus__stb$next[0:0]$7154 - attribute \src "libresoc.v:147530.3-147554.6" + attribute \src "libresoc.v:147326.3-147350.6" wire width 64 $4\m_ld_data_o$next[63:0]$7168 - attribute \src "libresoc.v:147351.18-147351.116" - wire $and$libresoc.v:147351$7089_Y - attribute \src "libresoc.v:147354.18-147354.111" - wire $and$libresoc.v:147354$7092_Y - attribute \src "libresoc.v:147359.18-147359.116" - wire $and$libresoc.v:147359$7097_Y - attribute \src "libresoc.v:147361.18-147361.111" - wire $and$libresoc.v:147361$7099_Y - attribute \src "libresoc.v:147363.17-147363.114" - wire $and$libresoc.v:147363$7101_Y - attribute \src "libresoc.v:147367.18-147367.116" - wire $and$libresoc.v:147367$7105_Y - attribute \src "libresoc.v:147369.18-147369.111" - wire $and$libresoc.v:147369$7107_Y - attribute \src "libresoc.v:147375.18-147375.116" - wire $and$libresoc.v:147375$7113_Y - attribute \src "libresoc.v:147377.18-147377.111" - wire $and$libresoc.v:147377$7115_Y - attribute \src "libresoc.v:147379.18-147379.116" - wire $and$libresoc.v:147379$7117_Y - attribute \src "libresoc.v:147381.18-147381.111" - wire $and$libresoc.v:147381$7119_Y - attribute \src "libresoc.v:147383.18-147383.116" - wire $and$libresoc.v:147383$7121_Y - attribute \src "libresoc.v:147385.17-147385.108" - wire $and$libresoc.v:147385$7123_Y - attribute \src "libresoc.v:147386.18-147386.111" - wire $and$libresoc.v:147386$7124_Y - attribute \src "libresoc.v:147387.18-147387.120" - wire $and$libresoc.v:147387$7125_Y - attribute \src "libresoc.v:147390.18-147390.120" - wire $and$libresoc.v:147390$7128_Y - attribute \src "libresoc.v:147392.18-147392.120" - wire $and$libresoc.v:147392$7130_Y - attribute \src "libresoc.v:147348.18-147348.110" - wire $not$libresoc.v:147348$7086_Y - attribute \src "libresoc.v:147353.18-147353.110" - wire $not$libresoc.v:147353$7091_Y - attribute \src "libresoc.v:147356.18-147356.110" - wire $not$libresoc.v:147356$7094_Y - attribute \src "libresoc.v:147360.18-147360.110" - wire $not$libresoc.v:147360$7098_Y - attribute \src "libresoc.v:147364.18-147364.110" - wire $not$libresoc.v:147364$7102_Y - attribute \src "libresoc.v:147368.18-147368.110" - wire $not$libresoc.v:147368$7106_Y - attribute \src "libresoc.v:147371.18-147371.110" - wire $not$libresoc.v:147371$7109_Y - attribute \src "libresoc.v:147374.17-147374.109" - wire $not$libresoc.v:147374$7112_Y - attribute \src "libresoc.v:147376.18-147376.110" - wire $not$libresoc.v:147376$7114_Y - attribute \src "libresoc.v:147380.18-147380.110" - wire $not$libresoc.v:147380$7118_Y - attribute \src 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wire $or$libresoc.v:147358$7096_Y - attribute \src "libresoc.v:147362.18-147362.120" - wire $or$libresoc.v:147362$7100_Y - attribute \src "libresoc.v:147365.18-147365.111" - wire $or$libresoc.v:147365$7103_Y - attribute \src "libresoc.v:147366.18-147366.114" - wire $or$libresoc.v:147366$7104_Y - attribute \src "libresoc.v:147370.18-147370.120" - wire $or$libresoc.v:147370$7108_Y - attribute \src "libresoc.v:147372.18-147372.111" - wire $or$libresoc.v:147372$7110_Y - attribute \src "libresoc.v:147373.18-147373.114" - wire $or$libresoc.v:147373$7111_Y - attribute \src "libresoc.v:147378.18-147378.114" - wire $or$libresoc.v:147378$7116_Y - attribute \src "libresoc.v:147382.18-147382.114" - wire $or$libresoc.v:147382$7120_Y - attribute \src "libresoc.v:147394.18-147394.127" - wire $or$libresoc.v:147394$7132_Y + attribute \src "libresoc.v:147147.18-147147.116" + wire $and$libresoc.v:147147$7089_Y + attribute \src "libresoc.v:147150.18-147150.111" + wire $and$libresoc.v:147150$7092_Y + attribute \src "libresoc.v:147155.18-147155.116" + wire $and$libresoc.v:147155$7097_Y + attribute \src "libresoc.v:147157.18-147157.111" + wire $and$libresoc.v:147157$7099_Y + attribute \src "libresoc.v:147159.17-147159.114" + wire $and$libresoc.v:147159$7101_Y + attribute \src "libresoc.v:147163.18-147163.116" + wire $and$libresoc.v:147163$7105_Y + attribute \src "libresoc.v:147165.18-147165.111" + wire $and$libresoc.v:147165$7107_Y + attribute \src "libresoc.v:147171.18-147171.116" + wire $and$libresoc.v:147171$7113_Y + attribute \src "libresoc.v:147173.18-147173.111" + wire $and$libresoc.v:147173$7115_Y + attribute \src "libresoc.v:147175.18-147175.116" + wire $and$libresoc.v:147175$7117_Y + attribute \src "libresoc.v:147177.18-147177.111" + wire $and$libresoc.v:147177$7119_Y + attribute \src "libresoc.v:147179.18-147179.116" + wire $and$libresoc.v:147179$7121_Y + attribute \src "libresoc.v:147181.17-147181.108" + wire $and$libresoc.v:147181$7123_Y + attribute \src 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"libresoc.v:147170.17-147170.109" + wire $not$libresoc.v:147170$7112_Y + attribute \src "libresoc.v:147172.18-147172.110" + wire $not$libresoc.v:147172$7114_Y + attribute \src "libresoc.v:147176.18-147176.110" + wire $not$libresoc.v:147176$7118_Y + attribute \src "libresoc.v:147180.18-147180.110" + wire $not$libresoc.v:147180$7122_Y + attribute \src "libresoc.v:147184.18-147184.110" + wire $not$libresoc.v:147184$7126_Y + attribute \src "libresoc.v:147185.18-147185.109" + wire $not$libresoc.v:147185$7127_Y + attribute \src "libresoc.v:147187.18-147187.110" + wire $not$libresoc.v:147187$7129_Y + attribute \src "libresoc.v:147189.18-147189.110" + wire $not$libresoc.v:147189$7131_Y + attribute \src "libresoc.v:147143.17-147143.119" + wire $or$libresoc.v:147143$7085_Y + attribute \src "libresoc.v:147145.18-147145.110" + wire $or$libresoc.v:147145$7087_Y + attribute \src "libresoc.v:147146.18-147146.114" + wire $or$libresoc.v:147146$7088_Y + attribute \src "libresoc.v:147148.17-147148.113" + wire $or$libresoc.v:147148$7090_Y + attribute \src "libresoc.v:147151.18-147151.120" + wire $or$libresoc.v:147151$7093_Y + attribute \src "libresoc.v:147153.18-147153.111" + wire $or$libresoc.v:147153$7095_Y + attribute \src "libresoc.v:147154.18-147154.114" + wire $or$libresoc.v:147154$7096_Y + attribute \src "libresoc.v:147158.18-147158.120" + wire $or$libresoc.v:147158$7100_Y + attribute \src "libresoc.v:147161.18-147161.111" + wire $or$libresoc.v:147161$7103_Y + attribute \src "libresoc.v:147162.18-147162.114" + wire $or$libresoc.v:147162$7104_Y + attribute \src "libresoc.v:147166.18-147166.120" + wire $or$libresoc.v:147166$7108_Y + attribute \src "libresoc.v:147168.18-147168.111" + wire $or$libresoc.v:147168$7110_Y + attribute \src "libresoc.v:147169.18-147169.114" + wire $or$libresoc.v:147169$7111_Y + attribute \src "libresoc.v:147174.18-147174.114" + wire $or$libresoc.v:147174$7116_Y + attribute \src "libresoc.v:147178.18-147178.114" + wire $or$libresoc.v:147178$7120_Y + attribute \src "libresoc.v:147190.18-147190.127" + wire $or$libresoc.v:147190$7132_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" @@ -272570,9 +272404,9 @@ module \lsmem wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 13 \dbus__ack @@ -272604,7 +272438,7 @@ module \lsmem wire output 19 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__we$next - attribute \src "libresoc.v:147168.7-147168.15" + attribute \src "libresoc.v:146964.7-146964.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o @@ -272647,7 +272481,7 @@ module \lsmem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire input 10 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147351$7089 + cell $and $and$libresoc.v:147147$7089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272655,10 +272489,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$15 connect \B \x_valid_i - connect \Y $and$libresoc.v:147351$7089_Y + connect \Y $and$libresoc.v:147147$7089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147354$7092 + cell $and $and$libresoc.v:147150$7092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272666,10 +272500,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$17 connect \B \$19 - connect \Y $and$libresoc.v:147354$7092_Y + connect \Y $and$libresoc.v:147150$7092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147359$7097 + cell $and $and$libresoc.v:147155$7097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272677,10 +272511,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$29 connect \B \x_valid_i - connect \Y $and$libresoc.v:147359$7097_Y + connect \Y $and$libresoc.v:147155$7097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147361$7099 + cell $and $and$libresoc.v:147157$7099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272688,10 +272522,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:147361$7099_Y + connect \Y $and$libresoc.v:147157$7099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147363$7101 + cell $and $and$libresoc.v:147159$7101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272699,10 +272533,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$1 connect \B \x_valid_i - connect \Y $and$libresoc.v:147363$7101_Y + connect \Y $and$libresoc.v:147159$7101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147367$7105 + cell $and $and$libresoc.v:147163$7105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272710,10 +272544,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$43 connect \B \x_valid_i - connect \Y $and$libresoc.v:147367$7105_Y + connect \Y $and$libresoc.v:147163$7105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147369$7107 + cell $and $and$libresoc.v:147165$7107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272721,10 +272555,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:147369$7107_Y + connect \Y $and$libresoc.v:147165$7107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147375$7113 + cell $and $and$libresoc.v:147171$7113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272732,10 +272566,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$57 connect \B \x_valid_i - connect \Y $and$libresoc.v:147375$7113_Y + connect \Y $and$libresoc.v:147171$7113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147377$7115 + cell $and $and$libresoc.v:147173$7115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272743,10 +272577,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:147377$7115_Y + connect \Y $and$libresoc.v:147173$7115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147379$7117 + cell $and $and$libresoc.v:147175$7117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272754,10 +272588,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$65 connect \B \x_valid_i - connect \Y $and$libresoc.v:147379$7117_Y + connect \Y $and$libresoc.v:147175$7117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147381$7119 + cell $and $and$libresoc.v:147177$7119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272765,10 +272599,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$67 connect \B \$69 - connect \Y $and$libresoc.v:147381$7119_Y + connect \Y $and$libresoc.v:147177$7119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147383$7121 + cell $and $and$libresoc.v:147179$7121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272776,10 +272610,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$73 connect \B \x_valid_i - connect \Y $and$libresoc.v:147383$7121_Y + connect \Y $and$libresoc.v:147179$7121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147385$7123 + cell $and $and$libresoc.v:147181$7123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272787,10 +272621,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:147385$7123_Y + connect \Y $and$libresoc.v:147181$7123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:147386$7124 + cell $and $and$libresoc.v:147182$7124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272798,10 +272632,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$75 connect \B \$77 - connect \Y $and$libresoc.v:147386$7124_Y + connect \Y $and$libresoc.v:147182$7124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:147387$7125 + cell $and $and$libresoc.v:147183$7125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272809,10 +272643,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:147387$7125_Y + connect \Y $and$libresoc.v:147183$7125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:147390$7128 + cell $and $and$libresoc.v:147186$7128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272820,10 +272654,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:147390$7128_Y + connect \Y $and$libresoc.v:147186$7128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:147392$7130 + cell $and $and$libresoc.v:147188$7130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272831,130 +272665,130 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:147392$7130_Y + connect \Y $and$libresoc.v:147188$7130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:147348$7086 + cell $not $not$libresoc.v:147144$7086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:147348$7086_Y + connect \Y $not$libresoc.v:147144$7086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:147353$7091 + cell $not $not$libresoc.v:147149$7091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:147353$7091_Y + connect \Y $not$libresoc.v:147149$7091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:147356$7094 + cell $not $not$libresoc.v:147152$7094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:147356$7094_Y + connect \Y $not$libresoc.v:147152$7094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:147360$7098 + cell $not $not$libresoc.v:147156$7098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:147360$7098_Y + connect \Y $not$libresoc.v:147156$7098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:147364$7102 + cell $not $not$libresoc.v:147160$7102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:147364$7102_Y + connect \Y $not$libresoc.v:147160$7102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:147368$7106 + cell $not $not$libresoc.v:147164$7106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:147368$7106_Y + connect \Y $not$libresoc.v:147164$7106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:147371$7109 + cell $not $not$libresoc.v:147167$7109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:147371$7109_Y + connect \Y $not$libresoc.v:147167$7109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:147374$7112 + cell $not $not$libresoc.v:147170$7112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:147374$7112_Y + connect \Y $not$libresoc.v:147170$7112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:147376$7114 + cell $not $not$libresoc.v:147172$7114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:147376$7114_Y + connect \Y $not$libresoc.v:147172$7114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:147380$7118 + cell $not $not$libresoc.v:147176$7118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:147380$7118_Y + connect \Y $not$libresoc.v:147176$7118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:147384$7122 + cell $not $not$libresoc.v:147180$7122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:147384$7122_Y + connect \Y $not$libresoc.v:147180$7122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:147388$7126 + cell $not $not$libresoc.v:147184$7126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:147388$7126_Y + connect \Y $not$libresoc.v:147184$7126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" - cell $not $not$libresoc.v:147389$7127 + cell $not $not$libresoc.v:147185$7127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__we - connect \Y $not$libresoc.v:147389$7127_Y + connect \Y $not$libresoc.v:147185$7127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:147391$7129 + cell $not $not$libresoc.v:147187$7129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:147391$7129_Y + connect \Y $not$libresoc.v:147187$7129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:147393$7131 + cell $not $not$libresoc.v:147189$7131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:147393$7131_Y + connect \Y $not$libresoc.v:147189$7131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:147347$7085 + cell $or $or$libresoc.v:147143$7085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272962,10 +272796,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:147347$7085_Y + connect \Y $or$libresoc.v:147143$7085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:147349$7087 + cell $or $or$libresoc.v:147145$7087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272973,10 +272807,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:147349$7087_Y + connect \Y $or$libresoc.v:147145$7087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:147350$7088 + cell $or $or$libresoc.v:147146$7088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272984,10 +272818,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:147350$7088_Y + connect \Y $or$libresoc.v:147146$7088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:147352$7090 + cell $or $or$libresoc.v:147148$7090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -272995,10 +272829,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:147352$7090_Y + connect \Y $or$libresoc.v:147148$7090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:147355$7093 + cell $or $or$libresoc.v:147151$7093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273006,10 +272840,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:147355$7093_Y + connect \Y $or$libresoc.v:147151$7093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:147357$7095 + cell $or $or$libresoc.v:147153$7095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273017,10 +272851,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:147357$7095_Y + connect \Y $or$libresoc.v:147153$7095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:147358$7096 + cell $or $or$libresoc.v:147154$7096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273028,10 +272862,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:147358$7096_Y + connect \Y $or$libresoc.v:147154$7096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:147362$7100 + cell $or $or$libresoc.v:147158$7100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273039,10 +272873,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:147362$7100_Y + connect \Y $or$libresoc.v:147158$7100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:147365$7103 + cell $or $or$libresoc.v:147161$7103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273050,10 +272884,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:147365$7103_Y + connect \Y $or$libresoc.v:147161$7103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:147366$7104 + cell $or $or$libresoc.v:147162$7104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273061,10 +272895,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:147366$7104_Y + connect \Y $or$libresoc.v:147162$7104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:147370$7108 + cell $or $or$libresoc.v:147166$7108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273072,10 +272906,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:147370$7108_Y + connect \Y $or$libresoc.v:147166$7108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:147372$7110 + cell $or $or$libresoc.v:147168$7110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273083,10 +272917,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:147372$7110_Y + connect \Y $or$libresoc.v:147168$7110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:147373$7111 + cell $or $or$libresoc.v:147169$7111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273094,10 +272928,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:147373$7111_Y + connect \Y $or$libresoc.v:147169$7111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:147378$7116 + cell $or $or$libresoc.v:147174$7116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273105,10 +272939,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:147378$7116_Y + connect \Y $or$libresoc.v:147174$7116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:147382$7120 + cell $or $or$libresoc.v:147178$7120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273116,10 +272950,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:147382$7120_Y + connect \Y $or$libresoc.v:147178$7120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - cell $or $or$libresoc.v:147394$7132 + cell $or $or$libresoc.v:147190$7132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273127,175 +272961,175 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \m_load_err_o connect \B \m_store_err_o - connect \Y $or$libresoc.v:147394$7132_Y + connect \Y $or$libresoc.v:147190$7132_Y end - attribute \src "libresoc.v:147168.7-147168.20" - process $proc$libresoc.v:147168$7199 + attribute \src "libresoc.v:146964.7-146964.20" + process $proc$libresoc.v:146964$7199 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147273.14-147273.42" - process $proc$libresoc.v:147273$7200 + attribute \src "libresoc.v:147069.14-147069.42" + process $proc$libresoc.v:147069$7200 assign { } { } assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \dbus__adr $1\dbus__adr[44:0] end - attribute \src "libresoc.v:147278.7-147278.23" - process $proc$libresoc.v:147278$7201 + attribute \src "libresoc.v:147074.7-147074.23" + process $proc$libresoc.v:147074$7201 assign { } { } assign $1\dbus__cyc[0:0] 1'0 sync always sync init update \dbus__cyc $1\dbus__cyc[0:0] end - attribute \src "libresoc.v:147285.14-147285.48" - process $proc$libresoc.v:147285$7202 + attribute \src "libresoc.v:147081.14-147081.48" + process $proc$libresoc.v:147081$7202 assign { } { } assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbus__dat_w $1\dbus__dat_w[63:0] end - attribute \src "libresoc.v:147292.13-147292.30" - process $proc$libresoc.v:147292$7203 + attribute \src "libresoc.v:147088.13-147088.30" + process $proc$libresoc.v:147088$7203 assign { } { } assign $1\dbus__sel[7:0] 8'00000000 sync always sync init update \dbus__sel $1\dbus__sel[7:0] end - attribute \src "libresoc.v:147297.7-147297.23" - process $proc$libresoc.v:147297$7204 + attribute \src "libresoc.v:147093.7-147093.23" + process $proc$libresoc.v:147093$7204 assign { } { } assign $1\dbus__stb[0:0] 1'0 sync always sync init update \dbus__stb $1\dbus__stb[0:0] end - attribute \src "libresoc.v:147302.7-147302.22" - process $proc$libresoc.v:147302$7205 + attribute \src "libresoc.v:147098.7-147098.22" + process $proc$libresoc.v:147098$7205 assign { } { } assign $1\dbus__we[0:0] 1'0 sync always sync init update \dbus__we $1\dbus__we[0:0] end - attribute \src "libresoc.v:147306.14-147306.44" - process $proc$libresoc.v:147306$7206 + attribute \src "libresoc.v:147102.14-147102.44" + process $proc$libresoc.v:147102$7206 assign { } { } assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \m_badaddr_o $1\m_badaddr_o[44:0] end - attribute \src "libresoc.v:147313.14-147313.48" - process $proc$libresoc.v:147313$7207 + attribute \src "libresoc.v:147109.14-147109.48" + process $proc$libresoc.v:147109$7207 assign { } { } assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \m_ld_data_o $1\m_ld_data_o[63:0] end - attribute \src "libresoc.v:147317.7-147317.26" - process $proc$libresoc.v:147317$7208 + attribute \src "libresoc.v:147113.7-147113.26" + process $proc$libresoc.v:147113$7208 assign { } { } assign $1\m_load_err_o[0:0] 1'0 sync always sync init update \m_load_err_o $1\m_load_err_o[0:0] end - attribute \src "libresoc.v:147323.7-147323.27" - process $proc$libresoc.v:147323$7209 + attribute \src "libresoc.v:147119.7-147119.27" + process $proc$libresoc.v:147119$7209 assign { } { } assign $1\m_store_err_o[0:0] 1'0 sync always sync init update \m_store_err_o $1\m_store_err_o[0:0] end - attribute \src "libresoc.v:147395.3-147396.39" - process $proc$libresoc.v:147395$7133 + attribute \src "libresoc.v:147191.3-147192.39" + process $proc$libresoc.v:147191$7133 assign { } { } assign $0\m_badaddr_o[44:0] \m_badaddr_o$next sync posedge \coresync_clk update \m_badaddr_o $0\m_badaddr_o[44:0] end - attribute \src "libresoc.v:147397.3-147398.43" - process $proc$libresoc.v:147397$7134 + attribute \src "libresoc.v:147193.3-147194.43" + process $proc$libresoc.v:147193$7134 assign { } { } assign $0\m_store_err_o[0:0] \m_store_err_o$next sync posedge \coresync_clk update \m_store_err_o $0\m_store_err_o[0:0] end - attribute \src "libresoc.v:147399.3-147400.41" - process $proc$libresoc.v:147399$7135 + attribute \src "libresoc.v:147195.3-147196.41" + process $proc$libresoc.v:147195$7135 assign { } { } assign $0\m_load_err_o[0:0] \m_load_err_o$next sync posedge \coresync_clk update \m_load_err_o $0\m_load_err_o[0:0] end - attribute \src "libresoc.v:147401.3-147402.39" - process $proc$libresoc.v:147401$7136 + attribute \src "libresoc.v:147197.3-147198.39" + process $proc$libresoc.v:147197$7136 assign { } { } assign $0\dbus__dat_w[63:0] \dbus__dat_w$next sync posedge \coresync_clk update \dbus__dat_w $0\dbus__dat_w[63:0] end - attribute \src "libresoc.v:147403.3-147404.33" - process $proc$libresoc.v:147403$7137 + attribute \src "libresoc.v:147199.3-147200.33" + process $proc$libresoc.v:147199$7137 assign { } { } assign $0\dbus__we[0:0] \dbus__we$next sync posedge \coresync_clk update \dbus__we $0\dbus__we[0:0] end - attribute \src "libresoc.v:147405.3-147406.35" - process $proc$libresoc.v:147405$7138 + attribute \src "libresoc.v:147201.3-147202.35" + process $proc$libresoc.v:147201$7138 assign { } { } assign $0\dbus__adr[44:0] \dbus__adr$next sync posedge \coresync_clk update \dbus__adr $0\dbus__adr[44:0] end - attribute \src "libresoc.v:147407.3-147408.39" - process $proc$libresoc.v:147407$7139 + attribute \src "libresoc.v:147203.3-147204.39" + process $proc$libresoc.v:147203$7139 assign { } { } assign $0\m_ld_data_o[63:0] \m_ld_data_o$next sync posedge \coresync_clk update \m_ld_data_o $0\m_ld_data_o[63:0] end - attribute \src "libresoc.v:147409.3-147410.35" - process $proc$libresoc.v:147409$7140 + attribute \src "libresoc.v:147205.3-147206.35" + process $proc$libresoc.v:147205$7140 assign { } { } assign $0\dbus__sel[7:0] \dbus__sel$next sync posedge \coresync_clk update \dbus__sel $0\dbus__sel[7:0] end - attribute \src "libresoc.v:147411.3-147412.35" - process $proc$libresoc.v:147411$7141 + attribute \src "libresoc.v:147207.3-147208.35" + process $proc$libresoc.v:147207$7141 assign { } { } assign $0\dbus__stb[0:0] \dbus__stb$next sync posedge \coresync_clk update \dbus__stb $0\dbus__stb[0:0] end - attribute \src "libresoc.v:147413.3-147414.35" - process $proc$libresoc.v:147413$7142 + attribute \src "libresoc.v:147209.3-147210.35" + process $proc$libresoc.v:147209$7142 assign { } { } assign $0\dbus__cyc[0:0] \dbus__cyc$next sync posedge \coresync_clk update \dbus__cyc $0\dbus__cyc[0:0] end - attribute \src "libresoc.v:147415.3-147442.6" - process $proc$libresoc.v:147415$7143 + attribute \src "libresoc.v:147211.3-147238.6" + process $proc$libresoc.v:147211$7143 assign { } { } assign { } { } assign { } { } assign $0\dbus__cyc$next[0:0]$7144 $4\dbus__cyc$next[0:0]$7148 - attribute \src "libresoc.v:147416.5-147416.29" + attribute \src "libresoc.v:147212.5-147212.29" switch \initial - attribute \src "libresoc.v:147416.9-147416.17" + attribute \src "libresoc.v:147212.9-147212.17" case 1'1 case end @@ -273342,15 +273176,15 @@ module \lsmem sync always update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7144 end - attribute \src "libresoc.v:147443.3-147470.6" - process $proc$libresoc.v:147443$7149 + attribute \src "libresoc.v:147239.3-147266.6" + process $proc$libresoc.v:147239$7149 assign { } { } assign { } { } assign { } { } assign $0\dbus__stb$next[0:0]$7150 $4\dbus__stb$next[0:0]$7154 - attribute \src "libresoc.v:147444.5-147444.29" + attribute \src "libresoc.v:147240.5-147240.29" switch \initial - attribute \src "libresoc.v:147444.9-147444.17" + attribute \src "libresoc.v:147240.9-147240.17" case 1'1 case end @@ -273397,14 +273231,14 @@ module \lsmem sync always update \dbus__stb$next $0\dbus__stb$next[0:0]$7150 end - attribute \src "libresoc.v:147471.3-147480.6" - process $proc$libresoc.v:147471$7155 + attribute \src "libresoc.v:147267.3-147276.6" + process $proc$libresoc.v:147267$7155 assign { } { } assign { } { } assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] - attribute \src "libresoc.v:147472.5-147472.29" + attribute \src "libresoc.v:147268.5-147268.29" switch \initial - attribute \src "libresoc.v:147472.9-147472.17" + attribute \src "libresoc.v:147268.9-147268.17" case 1'1 case end @@ -273420,14 +273254,14 @@ module \lsmem sync always update \x_busy_o $0\x_busy_o[0:0] end - attribute \src "libresoc.v:147481.3-147498.6" - process $proc$libresoc.v:147481$7156 + attribute \src "libresoc.v:147277.3-147294.6" + process $proc$libresoc.v:147277$7156 assign { } { } assign { } { } assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "libresoc.v:147482.5-147482.29" + attribute \src "libresoc.v:147278.5-147278.29" switch \initial - attribute \src "libresoc.v:147482.9-147482.17" + attribute \src "libresoc.v:147278.9-147278.17" case 1'1 case end @@ -273454,15 +273288,15 @@ module \lsmem sync always update \m_busy_o $0\m_busy_o[0:0] end - attribute \src "libresoc.v:147499.3-147529.6" - process $proc$libresoc.v:147499$7157 + attribute \src "libresoc.v:147295.3-147325.6" + process $proc$libresoc.v:147295$7157 assign { } { } assign { } { } assign { } { } assign $0\dbus__sel$next[7:0]$7158 $4\dbus__sel$next[7:0]$7162 - attribute \src "libresoc.v:147500.5-147500.29" + attribute \src "libresoc.v:147296.5-147296.29" switch \initial - attribute \src "libresoc.v:147500.9-147500.17" + attribute \src "libresoc.v:147296.9-147296.17" case 1'1 case end @@ -273511,15 +273345,15 @@ module \lsmem sync always update \dbus__sel$next $0\dbus__sel$next[7:0]$7158 end - attribute \src "libresoc.v:147530.3-147554.6" - process $proc$libresoc.v:147530$7163 + attribute \src "libresoc.v:147326.3-147350.6" + process $proc$libresoc.v:147326$7163 assign { } { } assign { } { } assign { } { } assign $0\m_ld_data_o$next[63:0]$7164 $4\m_ld_data_o$next[63:0]$7168 - attribute \src "libresoc.v:147531.5-147531.29" + attribute \src "libresoc.v:147327.5-147327.29" switch \initial - attribute \src "libresoc.v:147531.9-147531.17" + attribute \src "libresoc.v:147327.9-147327.17" case 1'1 case end @@ -273562,15 +273396,15 @@ module \lsmem sync always update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7164 end - attribute \src "libresoc.v:147555.3-147580.6" - process $proc$libresoc.v:147555$7169 + attribute \src "libresoc.v:147351.3-147376.6" + process $proc$libresoc.v:147351$7169 assign { } { } assign { } { } assign { } { } assign $0\dbus__adr$next[44:0]$7170 $3\dbus__adr$next[44:0]$7173 - attribute \src "libresoc.v:147556.5-147556.29" + attribute \src "libresoc.v:147352.5-147352.29" switch \initial - attribute \src "libresoc.v:147556.9-147556.17" + attribute \src "libresoc.v:147352.9-147352.17" case 1'1 case end @@ -273609,15 +273443,15 @@ module \lsmem sync always update \dbus__adr$next $0\dbus__adr$next[44:0]$7170 end - attribute \src "libresoc.v:147581.3-147606.6" - process $proc$libresoc.v:147581$7174 + attribute \src "libresoc.v:147377.3-147402.6" + process $proc$libresoc.v:147377$7174 assign { } { } assign { } { } assign { } { } assign $0\dbus__we$next[0:0]$7175 $3\dbus__we$next[0:0]$7178 - attribute \src "libresoc.v:147582.5-147582.29" + attribute \src "libresoc.v:147378.5-147378.29" switch \initial - attribute \src "libresoc.v:147582.9-147582.17" + attribute \src "libresoc.v:147378.9-147378.17" case 1'1 case end @@ -273656,15 +273490,15 @@ module \lsmem sync always update \dbus__we$next $0\dbus__we$next[0:0]$7175 end - attribute \src "libresoc.v:147607.3-147632.6" - process $proc$libresoc.v:147607$7179 + attribute \src "libresoc.v:147403.3-147428.6" + process $proc$libresoc.v:147403$7179 assign { } { } assign { } { } assign { } { } assign $0\dbus__dat_w$next[63:0]$7180 $3\dbus__dat_w$next[63:0]$7183 - attribute \src "libresoc.v:147608.5-147608.29" + attribute \src "libresoc.v:147404.5-147404.29" switch \initial - attribute \src "libresoc.v:147608.9-147608.17" + attribute \src "libresoc.v:147404.9-147404.17" case 1'1 case end @@ -273703,15 +273537,15 @@ module \lsmem sync always update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7180 end - attribute \src "libresoc.v:147633.3-147655.6" - process $proc$libresoc.v:147633$7184 + attribute \src "libresoc.v:147429.3-147451.6" + process $proc$libresoc.v:147429$7184 assign { } { } assign { } { } assign { } { } assign $0\m_load_err_o$next[0:0]$7185 $3\m_load_err_o$next[0:0]$7188 - attribute \src "libresoc.v:147634.5-147634.29" + attribute \src "libresoc.v:147430.5-147430.29" switch \initial - attribute \src "libresoc.v:147634.9-147634.17" + attribute \src "libresoc.v:147430.9-147430.17" case 1'1 case end @@ -273749,15 +273583,15 @@ module \lsmem sync always update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7185 end - attribute \src "libresoc.v:147656.3-147678.6" - process $proc$libresoc.v:147656$7189 + attribute \src "libresoc.v:147452.3-147474.6" + process $proc$libresoc.v:147452$7189 assign { } { } assign { } { } assign { } { } assign $0\m_store_err_o$next[0:0]$7190 $3\m_store_err_o$next[0:0]$7193 - attribute \src "libresoc.v:147657.5-147657.29" + attribute \src "libresoc.v:147453.5-147453.29" switch \initial - attribute \src "libresoc.v:147657.9-147657.17" + attribute \src "libresoc.v:147453.9-147453.17" case 1'1 case end @@ -273795,15 +273629,15 @@ module \lsmem sync always update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7190 end - attribute \src "libresoc.v:147679.3-147698.6" - process $proc$libresoc.v:147679$7194 + attribute \src "libresoc.v:147475.3-147494.6" + process $proc$libresoc.v:147475$7194 assign { } { } assign { } { } assign { } { } assign $0\m_badaddr_o$next[44:0]$7195 $3\m_badaddr_o$next[44:0]$7198 - attribute \src "libresoc.v:147680.5-147680.29" + attribute \src "libresoc.v:147476.5-147476.29" switch \initial - attribute \src "libresoc.v:147680.9-147680.17" + attribute \src "libresoc.v:147476.9-147476.17" case 1'1 case end @@ -273837,318 +273671,318 @@ module \lsmem sync always update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7195 end - connect \$9 $or$libresoc.v:147347$7085_Y - connect \$11 $not$libresoc.v:147348$7086_Y - connect \$13 $or$libresoc.v:147349$7087_Y - connect \$15 $or$libresoc.v:147350$7088_Y - connect \$17 $and$libresoc.v:147351$7089_Y - connect \$1 $or$libresoc.v:147352$7090_Y - connect \$19 $not$libresoc.v:147353$7091_Y - connect \$21 $and$libresoc.v:147354$7092_Y - connect \$23 $or$libresoc.v:147355$7093_Y - connect \$25 $not$libresoc.v:147356$7094_Y - connect \$27 $or$libresoc.v:147357$7095_Y - connect \$29 $or$libresoc.v:147358$7096_Y - connect \$31 $and$libresoc.v:147359$7097_Y - connect \$33 $not$libresoc.v:147360$7098_Y - connect \$35 $and$libresoc.v:147361$7099_Y - connect \$37 $or$libresoc.v:147362$7100_Y - connect \$3 $and$libresoc.v:147363$7101_Y - connect \$39 $not$libresoc.v:147364$7102_Y - connect \$41 $or$libresoc.v:147365$7103_Y - connect \$43 $or$libresoc.v:147366$7104_Y - connect \$45 $and$libresoc.v:147367$7105_Y - connect \$47 $not$libresoc.v:147368$7106_Y - connect \$49 $and$libresoc.v:147369$7107_Y - connect \$51 $or$libresoc.v:147370$7108_Y - connect \$53 $not$libresoc.v:147371$7109_Y - connect \$55 $or$libresoc.v:147372$7110_Y - connect \$57 $or$libresoc.v:147373$7111_Y - connect \$5 $not$libresoc.v:147374$7112_Y - connect \$59 $and$libresoc.v:147375$7113_Y - connect \$61 $not$libresoc.v:147376$7114_Y - connect \$63 $and$libresoc.v:147377$7115_Y - connect \$65 $or$libresoc.v:147378$7116_Y - connect \$67 $and$libresoc.v:147379$7117_Y - connect \$69 $not$libresoc.v:147380$7118_Y - connect \$71 $and$libresoc.v:147381$7119_Y - connect \$73 $or$libresoc.v:147382$7120_Y - connect \$75 $and$libresoc.v:147383$7121_Y - connect \$77 $not$libresoc.v:147384$7122_Y - connect \$7 $and$libresoc.v:147385$7123_Y - connect \$79 $and$libresoc.v:147386$7124_Y - connect \$81 $and$libresoc.v:147387$7125_Y - connect \$83 $not$libresoc.v:147388$7126_Y - connect \$85 $not$libresoc.v:147389$7127_Y - connect \$87 $and$libresoc.v:147390$7128_Y - connect \$89 $not$libresoc.v:147391$7129_Y - connect \$91 $and$libresoc.v:147392$7130_Y - connect \$93 $not$libresoc.v:147393$7131_Y - connect \$95 $or$libresoc.v:147394$7132_Y + connect \$9 $or$libresoc.v:147143$7085_Y + connect \$11 $not$libresoc.v:147144$7086_Y + connect \$13 $or$libresoc.v:147145$7087_Y + connect \$15 $or$libresoc.v:147146$7088_Y + connect \$17 $and$libresoc.v:147147$7089_Y + connect \$1 $or$libresoc.v:147148$7090_Y + connect \$19 $not$libresoc.v:147149$7091_Y + connect \$21 $and$libresoc.v:147150$7092_Y + connect \$23 $or$libresoc.v:147151$7093_Y + connect \$25 $not$libresoc.v:147152$7094_Y + connect \$27 $or$libresoc.v:147153$7095_Y + connect \$29 $or$libresoc.v:147154$7096_Y + connect \$31 $and$libresoc.v:147155$7097_Y + connect \$33 $not$libresoc.v:147156$7098_Y + connect \$35 $and$libresoc.v:147157$7099_Y + connect \$37 $or$libresoc.v:147158$7100_Y + connect \$3 $and$libresoc.v:147159$7101_Y + connect \$39 $not$libresoc.v:147160$7102_Y + connect \$41 $or$libresoc.v:147161$7103_Y + connect \$43 $or$libresoc.v:147162$7104_Y + connect \$45 $and$libresoc.v:147163$7105_Y + connect \$47 $not$libresoc.v:147164$7106_Y + connect \$49 $and$libresoc.v:147165$7107_Y + connect \$51 $or$libresoc.v:147166$7108_Y + connect \$53 $not$libresoc.v:147167$7109_Y + connect \$55 $or$libresoc.v:147168$7110_Y + connect \$57 $or$libresoc.v:147169$7111_Y + connect \$5 $not$libresoc.v:147170$7112_Y + connect \$59 $and$libresoc.v:147171$7113_Y + connect \$61 $not$libresoc.v:147172$7114_Y + connect \$63 $and$libresoc.v:147173$7115_Y + connect \$65 $or$libresoc.v:147174$7116_Y + connect \$67 $and$libresoc.v:147175$7117_Y + connect \$69 $not$libresoc.v:147176$7118_Y + connect \$71 $and$libresoc.v:147177$7119_Y + connect \$73 $or$libresoc.v:147178$7120_Y + connect \$75 $and$libresoc.v:147179$7121_Y + connect \$77 $not$libresoc.v:147180$7122_Y + connect \$7 $and$libresoc.v:147181$7123_Y + connect \$79 $and$libresoc.v:147182$7124_Y + connect \$81 $and$libresoc.v:147183$7125_Y + connect \$83 $not$libresoc.v:147184$7126_Y + connect \$85 $not$libresoc.v:147185$7127_Y + connect \$87 $and$libresoc.v:147186$7128_Y + connect \$89 $not$libresoc.v:147187$7129_Y + connect \$91 $and$libresoc.v:147188$7130_Y + connect \$93 $not$libresoc.v:147189$7131_Y + connect \$95 $or$libresoc.v:147190$7132_Y connect \x_stall_i 1'0 connect \m_stall_i 1'0 end -attribute \src "libresoc.v:147705.1-148738.10" +attribute \src "libresoc.v:147501.1-148534.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" attribute \generator "nMigen" module \main - attribute \src "libresoc.v:148238.3-148260.6" + attribute \src "libresoc.v:148034.3-148056.6" wire width 64 $0\a_i[63:0] - attribute \src "libresoc.v:148337.3-148363.6" + attribute \src "libresoc.v:148133.3-148159.6" wire $0\a_lt[0:0] - attribute \src "libresoc.v:148690.3-148700.6" + attribute \src "libresoc.v:148486.3-148496.6" wire width 64 $0\a_n[63:0] - attribute \src "libresoc.v:148660.3-148669.6" + attribute \src "libresoc.v:148456.3-148465.6" wire width 66 $0\add_a[65:0] - attribute \src "libresoc.v:148670.3-148679.6" + attribute \src "libresoc.v:148466.3-148475.6" wire width 66 $0\add_b[65:0] - attribute \src "libresoc.v:148680.3-148689.6" + attribute \src "libresoc.v:148476.3-148485.6" wire width 66 $0\add_o[65:0] - attribute \src "libresoc.v:148504.3-148526.6" + attribute \src "libresoc.v:148300.3-148322.6" wire width 64 $0\b_i[63:0] - attribute \src "libresoc.v:148486.3-148503.6" + attribute \src "libresoc.v:148282.3-148299.6" wire width 2 $0\ca[1:0] - attribute \src "libresoc.v:148701.3-148711.6" + attribute \src "libresoc.v:148497.3-148507.6" wire $0\carry_32[0:0] - attribute \src "libresoc.v:148712.3-148722.6" + attribute \src "libresoc.v:148508.3-148518.6" wire $0\carry_64[0:0] - attribute \src "libresoc.v:148364.3-148397.6" + attribute \src "libresoc.v:148160.3-148193.6" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:148398.3-148420.6" + attribute \src "libresoc.v:148194.3-148216.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:148628.3-148659.6" + attribute \src "libresoc.v:148424.3-148455.6" wire width 8 $0\eqs[7:0] - attribute \src "libresoc.v:147706.7-147706.20" + attribute \src "libresoc.v:147502.7-147502.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148228.3-148237.6" + attribute \src "libresoc.v:148024.3-148033.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:148299.3-148317.6" + attribute \src "libresoc.v:148095.3-148113.6" wire $0\msb_a[0:0] - attribute \src "libresoc.v:148318.3-148336.6" + attribute \src "libresoc.v:148114.3-148132.6" wire $0\msb_b[0:0] - attribute \src "libresoc.v:148421.3-148462.6" + attribute \src "libresoc.v:148217.3-148258.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:148463.3-148485.6" + attribute \src "libresoc.v:148259.3-148281.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:148557.3-148574.6" + attribute \src "libresoc.v:148353.3-148370.6" wire width 2 $0\ov[1:0] - attribute \src "libresoc.v:148605.3-148627.6" + attribute \src "libresoc.v:148401.3-148423.6" wire width 8 $0\src1[7:0] - attribute \src "libresoc.v:148272.3-148298.6" + attribute \src "libresoc.v:148068.3-148094.6" wire width 5 $0\tval[4:0] - attribute \src "libresoc.v:148527.3-148541.6" + attribute \src "libresoc.v:148323.3-148337.6" wire width 2 $0\xer_ca$20[1:0]$7285 - attribute \src "libresoc.v:148542.3-148556.6" + attribute \src "libresoc.v:148338.3-148352.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:148575.3-148589.6" + attribute \src "libresoc.v:148371.3-148385.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:148590.3-148604.6" + attribute \src "libresoc.v:148386.3-148400.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:148261.3-148271.6" + attribute \src "libresoc.v:148057.3-148067.6" wire $0\zerohi[0:0] - attribute \src "libresoc.v:148723.3-148733.6" + attribute \src "libresoc.v:148519.3-148529.6" wire $0\zerolo[0:0] - attribute \src "libresoc.v:148238.3-148260.6" + attribute \src "libresoc.v:148034.3-148056.6" wire width 64 $1\a_i[63:0] - attribute \src "libresoc.v:148337.3-148363.6" + attribute \src "libresoc.v:148133.3-148159.6" wire $1\a_lt[0:0] - attribute \src "libresoc.v:148690.3-148700.6" + attribute \src "libresoc.v:148486.3-148496.6" wire width 64 $1\a_n[63:0] - attribute \src "libresoc.v:148660.3-148669.6" + attribute \src "libresoc.v:148456.3-148465.6" wire width 66 $1\add_a[65:0] - attribute \src "libresoc.v:148670.3-148679.6" + attribute \src "libresoc.v:148466.3-148475.6" wire width 66 $1\add_b[65:0] - attribute \src "libresoc.v:148680.3-148689.6" + attribute \src "libresoc.v:148476.3-148485.6" wire width 66 $1\add_o[65:0] - attribute \src "libresoc.v:148504.3-148526.6" + attribute \src "libresoc.v:148300.3-148322.6" wire width 64 $1\b_i[63:0] - attribute \src "libresoc.v:148486.3-148503.6" + attribute \src "libresoc.v:148282.3-148299.6" wire width 2 $1\ca[1:0] - attribute \src "libresoc.v:148701.3-148711.6" + attribute \src "libresoc.v:148497.3-148507.6" wire $1\carry_32[0:0] - attribute \src "libresoc.v:148712.3-148722.6" + attribute \src "libresoc.v:148508.3-148518.6" wire $1\carry_64[0:0] - attribute \src "libresoc.v:148364.3-148397.6" + attribute \src "libresoc.v:148160.3-148193.6" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:148398.3-148420.6" + attribute \src "libresoc.v:148194.3-148216.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:148628.3-148659.6" + attribute \src "libresoc.v:148424.3-148455.6" wire width 8 $1\eqs[7:0] - attribute \src "libresoc.v:148228.3-148237.6" + attribute \src "libresoc.v:148024.3-148033.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:148299.3-148317.6" + attribute \src "libresoc.v:148095.3-148113.6" wire $1\msb_a[0:0] - attribute \src "libresoc.v:148318.3-148336.6" + attribute \src "libresoc.v:148114.3-148132.6" wire $1\msb_b[0:0] - attribute \src "libresoc.v:148421.3-148462.6" + attribute \src "libresoc.v:148217.3-148258.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:148463.3-148485.6" + attribute \src "libresoc.v:148259.3-148281.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:148557.3-148574.6" + attribute \src "libresoc.v:148353.3-148370.6" wire width 2 $1\ov[1:0] - attribute \src "libresoc.v:148605.3-148627.6" + attribute \src "libresoc.v:148401.3-148423.6" wire width 8 $1\src1[7:0] - attribute \src "libresoc.v:148272.3-148298.6" + attribute \src "libresoc.v:148068.3-148094.6" wire width 5 $1\tval[4:0] - attribute \src "libresoc.v:148527.3-148541.6" + attribute \src "libresoc.v:148323.3-148337.6" wire width 2 $1\xer_ca$20[1:0]$7286 - attribute \src "libresoc.v:148542.3-148556.6" + attribute \src "libresoc.v:148338.3-148352.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:148575.3-148589.6" + attribute \src "libresoc.v:148371.3-148385.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:148590.3-148604.6" + attribute \src "libresoc.v:148386.3-148400.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:148261.3-148271.6" + attribute \src "libresoc.v:148057.3-148067.6" wire $1\zerohi[0:0] - attribute \src "libresoc.v:148723.3-148733.6" + attribute \src "libresoc.v:148519.3-148529.6" wire $1\zerolo[0:0] - attribute \src "libresoc.v:148238.3-148260.6" + attribute \src "libresoc.v:148034.3-148056.6" wire width 64 $2\a_i[63:0] - attribute \src "libresoc.v:148337.3-148363.6" + attribute \src "libresoc.v:148133.3-148159.6" wire $2\a_lt[0:0] - attribute \src "libresoc.v:148504.3-148526.6" + attribute \src "libresoc.v:148300.3-148322.6" wire width 64 $2\b_i[63:0] - attribute \src "libresoc.v:148364.3-148397.6" + attribute \src "libresoc.v:148160.3-148193.6" wire width 2 $2\cr_a[3:2] - attribute \src "libresoc.v:148299.3-148317.6" + attribute \src "libresoc.v:148095.3-148113.6" wire $2\msb_a[0:0] - attribute \src "libresoc.v:148318.3-148336.6" + attribute \src "libresoc.v:148114.3-148132.6" wire $2\msb_b[0:0] - attribute \src "libresoc.v:148421.3-148462.6" + attribute \src "libresoc.v:148217.3-148258.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:148272.3-148298.6" + attribute \src "libresoc.v:148068.3-148094.6" wire width 5 $2\tval[4:0] - attribute \src "libresoc.v:148337.3-148363.6" + attribute \src "libresoc.v:148133.3-148159.6" wire $3\a_lt[0:0] - attribute \src "libresoc.v:148421.3-148462.6" + attribute \src "libresoc.v:148217.3-148258.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:148272.3-148298.6" + attribute \src "libresoc.v:148068.3-148094.6" wire width 5 $3\tval[4:0] - attribute \src "libresoc.v:148421.3-148462.6" + attribute \src "libresoc.v:148217.3-148258.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:148203.18-148203.105" - wire width 67 $add$libresoc.v:148203$7246_Y - attribute \src "libresoc.v:148177.19-148177.107" - wire $and$libresoc.v:148177$7220_Y - attribute \src "libresoc.v:148181.19-148181.107" - wire $and$libresoc.v:148181$7224_Y - attribute \src "libresoc.v:148214.18-148214.106" - wire $and$libresoc.v:148214$7257_Y - attribute \src "libresoc.v:148219.18-148219.106" - wire $and$libresoc.v:148219$7262_Y - attribute \src "libresoc.v:148222.18-148222.106" - wire $and$libresoc.v:148222$7265_Y - attribute \src "libresoc.v:148225.18-148225.106" - wire $and$libresoc.v:148225$7268_Y - attribute \src "libresoc.v:148168.19-148168.118" - wire $eq$libresoc.v:148168$7211_Y - attribute \src "libresoc.v:148169.19-148169.118" - wire $eq$libresoc.v:148169$7212_Y - attribute \src "libresoc.v:148170.19-148170.118" - wire $eq$libresoc.v:148170$7213_Y - attribute \src "libresoc.v:148182.19-148182.109" - wire $eq$libresoc.v:148182$7225_Y - attribute \src "libresoc.v:148183.19-148183.110" - wire $eq$libresoc.v:148183$7226_Y - attribute \src "libresoc.v:148184.19-148184.111" - wire $eq$libresoc.v:148184$7227_Y - attribute \src "libresoc.v:148185.19-148185.111" - wire $eq$libresoc.v:148185$7228_Y - attribute \src "libresoc.v:148186.19-148186.111" - wire $eq$libresoc.v:148186$7229_Y - attribute \src "libresoc.v:148187.19-148187.111" - wire $eq$libresoc.v:148187$7230_Y - attribute \src "libresoc.v:148188.19-148188.111" - wire $eq$libresoc.v:148188$7231_Y - attribute \src "libresoc.v:148189.19-148189.111" - wire $eq$libresoc.v:148189$7232_Y - attribute \src "libresoc.v:148190.18-148190.118" - wire $eq$libresoc.v:148190$7233_Y - attribute \src "libresoc.v:148192.18-148192.118" - wire $eq$libresoc.v:148192$7235_Y - attribute \src "libresoc.v:148193.18-148193.118" - wire $eq$libresoc.v:148193$7236_Y - attribute \src "libresoc.v:148194.18-148194.118" - wire $eq$libresoc.v:148194$7237_Y - attribute \src "libresoc.v:148195.18-148195.118" - wire $eq$libresoc.v:148195$7238_Y - attribute \src "libresoc.v:148197.18-148197.118" - wire $eq$libresoc.v:148197$7240_Y - attribute \src "libresoc.v:148198.18-148198.118" - wire $eq$libresoc.v:148198$7241_Y - attribute \src "libresoc.v:148200.18-148200.118" - wire $eq$libresoc.v:148200$7243_Y - attribute \src "libresoc.v:148201.18-148201.118" - wire $eq$libresoc.v:148201$7244_Y - attribute \src "libresoc.v:148215.18-148215.107" - wire $ne$libresoc.v:148215$7258_Y - attribute \src "libresoc.v:148226.18-148226.107" - wire $ne$libresoc.v:148226$7269_Y - attribute \src "libresoc.v:148176.19-148176.100" - wire $not$libresoc.v:148176$7219_Y - attribute \src "libresoc.v:148180.19-148180.100" - wire $not$libresoc.v:148180$7223_Y - attribute \src "libresoc.v:148191.18-148191.110" - wire $not$libresoc.v:148191$7234_Y - attribute \src "libresoc.v:148204.18-148204.97" - wire width 64 $not$libresoc.v:148204$7247_Y - attribute \src "libresoc.v:148209.18-148209.99" - wire $not$libresoc.v:148209$7252_Y - attribute \src "libresoc.v:148212.18-148212.99" - wire $not$libresoc.v:148212$7255_Y - attribute \src "libresoc.v:148216.18-148216.99" - wire $not$libresoc.v:148216$7259_Y - attribute \src "libresoc.v:148217.18-148217.99" - wire $not$libresoc.v:148217$7260_Y - attribute \src "libresoc.v:148196.18-148196.104" - wire $or$libresoc.v:148196$7239_Y - attribute \src "libresoc.v:148199.18-148199.104" - wire $or$libresoc.v:148199$7242_Y - attribute \src "libresoc.v:148202.18-148202.104" - wire $or$libresoc.v:148202$7245_Y - attribute \src "libresoc.v:148213.18-148213.110" - wire $or$libresoc.v:148213$7256_Y - attribute \src "libresoc.v:148218.18-148218.110" - wire $or$libresoc.v:148218$7261_Y - attribute \src "libresoc.v:148221.18-148221.110" - wire $or$libresoc.v:148221$7264_Y - attribute \src "libresoc.v:148224.18-148224.110" - wire $or$libresoc.v:148224$7267_Y - attribute \src "libresoc.v:148167.18-148167.98" - wire $reduce_or$libresoc.v:148167$7210_Y - attribute \src "libresoc.v:148171.19-148171.99" - wire $reduce_or$libresoc.v:148171$7214_Y - attribute \src "libresoc.v:148208.18-148208.99" - wire $reduce_or$libresoc.v:148208$7251_Y - attribute \src "libresoc.v:148211.18-148211.99" - wire $reduce_or$libresoc.v:148211$7254_Y - attribute \src "libresoc.v:148220.18-148220.121" - wire $ternary$libresoc.v:148220$7263_Y - attribute \src "libresoc.v:148223.18-148223.119" - wire $ternary$libresoc.v:148223$7266_Y - attribute \src "libresoc.v:148227.18-148227.123" - wire $ternary$libresoc.v:148227$7270_Y - attribute \src "libresoc.v:148172.19-148172.111" - wire $xor$libresoc.v:148172$7215_Y - attribute \src "libresoc.v:148173.19-148173.111" - wire $xor$libresoc.v:148173$7216_Y - attribute \src "libresoc.v:148174.19-148174.110" - wire $xor$libresoc.v:148174$7217_Y - attribute \src "libresoc.v:148175.19-148175.110" - wire $xor$libresoc.v:148175$7218_Y - attribute \src "libresoc.v:148178.19-148178.110" - wire $xor$libresoc.v:148178$7221_Y - attribute \src "libresoc.v:148179.19-148179.110" - wire $xor$libresoc.v:148179$7222_Y - attribute \src "libresoc.v:148205.18-148205.111" - wire $xor$libresoc.v:148205$7248_Y - attribute \src "libresoc.v:148206.18-148206.107" - wire $xor$libresoc.v:148206$7249_Y - attribute \src "libresoc.v:148207.18-148207.113" - wire width 32 $xor$libresoc.v:148207$7250_Y - attribute \src "libresoc.v:148210.18-148210.115" - wire width 32 $xor$libresoc.v:148210$7253_Y + attribute \src "libresoc.v:147999.18-147999.105" + wire width 67 $add$libresoc.v:147999$7246_Y + attribute \src "libresoc.v:147973.19-147973.107" + wire $and$libresoc.v:147973$7220_Y + attribute \src "libresoc.v:147977.19-147977.107" + wire $and$libresoc.v:147977$7224_Y + attribute \src "libresoc.v:148010.18-148010.106" + wire $and$libresoc.v:148010$7257_Y + attribute \src "libresoc.v:148015.18-148015.106" + wire $and$libresoc.v:148015$7262_Y + attribute \src "libresoc.v:148018.18-148018.106" + wire $and$libresoc.v:148018$7265_Y + attribute \src "libresoc.v:148021.18-148021.106" + wire $and$libresoc.v:148021$7268_Y + attribute \src "libresoc.v:147964.19-147964.118" + wire $eq$libresoc.v:147964$7211_Y + attribute \src "libresoc.v:147965.19-147965.118" + wire $eq$libresoc.v:147965$7212_Y + attribute \src "libresoc.v:147966.19-147966.118" + wire $eq$libresoc.v:147966$7213_Y + attribute \src "libresoc.v:147978.19-147978.109" + wire $eq$libresoc.v:147978$7225_Y + attribute \src "libresoc.v:147979.19-147979.110" + wire $eq$libresoc.v:147979$7226_Y + attribute \src "libresoc.v:147980.19-147980.111" + wire $eq$libresoc.v:147980$7227_Y + attribute \src "libresoc.v:147981.19-147981.111" + wire $eq$libresoc.v:147981$7228_Y + attribute \src "libresoc.v:147982.19-147982.111" + wire $eq$libresoc.v:147982$7229_Y + attribute \src "libresoc.v:147983.19-147983.111" + wire $eq$libresoc.v:147983$7230_Y + attribute \src "libresoc.v:147984.19-147984.111" + wire $eq$libresoc.v:147984$7231_Y + attribute \src "libresoc.v:147985.19-147985.111" + wire $eq$libresoc.v:147985$7232_Y + attribute \src "libresoc.v:147986.18-147986.118" + wire $eq$libresoc.v:147986$7233_Y + attribute \src "libresoc.v:147988.18-147988.118" + wire $eq$libresoc.v:147988$7235_Y + attribute \src "libresoc.v:147989.18-147989.118" + wire $eq$libresoc.v:147989$7236_Y + attribute \src "libresoc.v:147990.18-147990.118" + wire $eq$libresoc.v:147990$7237_Y + attribute \src "libresoc.v:147991.18-147991.118" + wire $eq$libresoc.v:147991$7238_Y + attribute \src "libresoc.v:147993.18-147993.118" + wire $eq$libresoc.v:147993$7240_Y + attribute \src "libresoc.v:147994.18-147994.118" + wire $eq$libresoc.v:147994$7241_Y + attribute \src "libresoc.v:147996.18-147996.118" + wire $eq$libresoc.v:147996$7243_Y + attribute \src "libresoc.v:147997.18-147997.118" + wire $eq$libresoc.v:147997$7244_Y + attribute \src "libresoc.v:148011.18-148011.107" + wire $ne$libresoc.v:148011$7258_Y + attribute \src "libresoc.v:148022.18-148022.107" + wire $ne$libresoc.v:148022$7269_Y + attribute \src "libresoc.v:147972.19-147972.100" + wire $not$libresoc.v:147972$7219_Y + attribute \src "libresoc.v:147976.19-147976.100" + wire $not$libresoc.v:147976$7223_Y + attribute \src "libresoc.v:147987.18-147987.110" + wire $not$libresoc.v:147987$7234_Y + attribute \src "libresoc.v:148000.18-148000.97" + wire width 64 $not$libresoc.v:148000$7247_Y + attribute \src "libresoc.v:148005.18-148005.99" + wire $not$libresoc.v:148005$7252_Y + attribute \src "libresoc.v:148008.18-148008.99" + wire $not$libresoc.v:148008$7255_Y + attribute \src "libresoc.v:148012.18-148012.99" + wire $not$libresoc.v:148012$7259_Y + attribute \src "libresoc.v:148013.18-148013.99" + wire $not$libresoc.v:148013$7260_Y + attribute \src "libresoc.v:147992.18-147992.104" + wire $or$libresoc.v:147992$7239_Y + attribute \src "libresoc.v:147995.18-147995.104" + wire $or$libresoc.v:147995$7242_Y + attribute \src "libresoc.v:147998.18-147998.104" + wire $or$libresoc.v:147998$7245_Y + attribute \src "libresoc.v:148009.18-148009.110" + wire $or$libresoc.v:148009$7256_Y + attribute \src "libresoc.v:148014.18-148014.110" + wire $or$libresoc.v:148014$7261_Y + attribute \src "libresoc.v:148017.18-148017.110" + wire $or$libresoc.v:148017$7264_Y + attribute \src "libresoc.v:148020.18-148020.110" + wire $or$libresoc.v:148020$7267_Y + attribute \src "libresoc.v:147963.18-147963.98" + wire $reduce_or$libresoc.v:147963$7210_Y + attribute \src "libresoc.v:147967.19-147967.99" + wire $reduce_or$libresoc.v:147967$7214_Y + attribute \src "libresoc.v:148004.18-148004.99" + wire $reduce_or$libresoc.v:148004$7251_Y + attribute \src "libresoc.v:148007.18-148007.99" + wire $reduce_or$libresoc.v:148007$7254_Y + attribute \src "libresoc.v:148016.18-148016.121" + wire $ternary$libresoc.v:148016$7263_Y + attribute \src "libresoc.v:148019.18-148019.119" + wire $ternary$libresoc.v:148019$7266_Y + attribute \src "libresoc.v:148023.18-148023.123" + wire $ternary$libresoc.v:148023$7270_Y + attribute \src "libresoc.v:147968.19-147968.111" + wire $xor$libresoc.v:147968$7215_Y + attribute \src "libresoc.v:147969.19-147969.111" + wire $xor$libresoc.v:147969$7216_Y + attribute \src "libresoc.v:147970.19-147970.110" + wire $xor$libresoc.v:147970$7217_Y + attribute \src "libresoc.v:147971.19-147971.110" + wire $xor$libresoc.v:147971$7218_Y + attribute \src "libresoc.v:147974.19-147974.110" + wire $xor$libresoc.v:147974$7221_Y + attribute \src "libresoc.v:147975.19-147975.110" + wire $xor$libresoc.v:147975$7222_Y + attribute \src "libresoc.v:148001.18-148001.111" + wire $xor$libresoc.v:148001$7248_Y + attribute \src "libresoc.v:148002.18-148002.107" + wire $xor$libresoc.v:148002$7249_Y + attribute \src "libresoc.v:148003.18-148003.113" + wire width 32 $xor$libresoc.v:148003$7250_Y + attribute \src "libresoc.v:148006.18-148006.115" + wire width 32 $xor$libresoc.v:148006$7253_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" @@ -274559,7 +274393,7 @@ module \main wire output 45 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" wire width 8 \eqs - attribute \src "libresoc.v:147706.7-147706.15" + attribute \src "libresoc.v:147502.7-147502.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" wire \is_32bit @@ -274604,7 +274438,7 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" wire \zerolo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" - cell $add $add$libresoc.v:148203$7246 + cell $add $add$libresoc.v:147999$7246 parameter \A_SIGNED 0 parameter \A_WIDTH 66 parameter \B_SIGNED 0 @@ -274612,10 +274446,10 @@ module \main parameter \Y_WIDTH 67 connect \A \add_a connect \B \add_b - connect \Y $add$libresoc.v:148203$7246_Y + connect \Y $add$libresoc.v:147999$7246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:148177$7220 + cell $and $and$libresoc.v:147973$7220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274623,10 +274457,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$113 connect \B \$115 - connect \Y $and$libresoc.v:148177$7220_Y + connect \Y $and$libresoc.v:147973$7220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:148181$7224 + cell $and $and$libresoc.v:147977$7224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274634,10 +274468,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$121 connect \B \$123 - connect \Y $and$libresoc.v:148181$7224_Y + connect \Y $and$libresoc.v:147977$7224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:148214$7257 + cell $and $and$libresoc.v:148010$7257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274645,10 +274479,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$69 - connect \Y $and$libresoc.v:148214$7257_Y + connect \Y $and$libresoc.v:148010$7257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:148219$7262 + cell $and $and$libresoc.v:148015$7262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274656,10 +274490,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$79 - connect \Y $and$libresoc.v:148219$7262_Y + connect \Y $and$libresoc.v:148015$7262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:148222$7265 + cell $and $and$libresoc.v:148018$7265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274667,10 +274501,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$85 - connect \Y $and$libresoc.v:148222$7265_Y + connect \Y $and$libresoc.v:148018$7265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:148225$7268 + cell $and $and$libresoc.v:148021$7268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274678,10 +274512,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$91 - connect \Y $and$libresoc.v:148225$7268_Y + connect \Y $and$libresoc.v:148021$7268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$libresoc.v:148168$7211 + cell $eq $eq$libresoc.v:147964$7211 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274689,10 +274523,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 1'1 - connect \Y $eq$libresoc.v:148168$7211_Y + connect \Y $eq$libresoc.v:147964$7211_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - cell $eq $eq$libresoc.v:148169$7212 + cell $eq $eq$libresoc.v:147965$7212 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274700,10 +274534,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:148169$7212_Y + connect \Y $eq$libresoc.v:147965$7212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - cell $eq $eq$libresoc.v:148170$7213 + cell $eq $eq$libresoc.v:147966$7213 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274711,10 +274545,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 3'100 - connect \Y $eq$libresoc.v:148170$7213_Y + connect \Y $eq$libresoc.v:147966$7213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:148182$7225 + cell $eq $eq$libresoc.v:147978$7225 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -274722,10 +274556,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148182$7225_Y + connect \Y $eq$libresoc.v:147978$7225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:148183$7226 + cell $eq $eq$libresoc.v:147979$7226 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -274733,10 +274567,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148183$7226_Y + connect \Y $eq$libresoc.v:147979$7226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:148184$7227 + cell $eq $eq$libresoc.v:147980$7227 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -274744,10 +274578,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148184$7227_Y + connect \Y $eq$libresoc.v:147980$7227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:148185$7228 + cell $eq $eq$libresoc.v:147981$7228 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -274755,10 +274589,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148185$7228_Y + connect \Y $eq$libresoc.v:147981$7228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:148186$7229 + cell $eq $eq$libresoc.v:147982$7229 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -274766,10 +274600,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148186$7229_Y + connect \Y $eq$libresoc.v:147982$7229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:148187$7230 + cell $eq $eq$libresoc.v:147983$7230 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -274777,10 +274611,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148187$7230_Y + connect \Y $eq$libresoc.v:147983$7230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:148188$7231 + cell $eq $eq$libresoc.v:147984$7231 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -274788,10 +274622,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148188$7231_Y + connect \Y $eq$libresoc.v:147984$7231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:148189$7232 + cell $eq $eq$libresoc.v:147985$7232 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -274799,10 +274633,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148189$7232_Y + connect \Y $eq$libresoc.v:147985$7232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - cell $eq $eq$libresoc.v:148190$7233 + cell $eq $eq$libresoc.v:147986$7233 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -274810,10 +274644,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:148190$7233_Y + connect \Y $eq$libresoc.v:147986$7233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:148192$7235 + cell $eq $eq$libresoc.v:147988$7235 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -274821,10 +274655,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:148192$7235_Y + connect \Y $eq$libresoc.v:147988$7235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:148193$7236 + cell $eq $eq$libresoc.v:147989$7236 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -274832,10 +274666,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:148193$7236_Y + connect \Y $eq$libresoc.v:147989$7236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:148194$7237 + cell $eq $eq$libresoc.v:147990$7237 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -274843,10 +274677,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:148194$7237_Y + connect \Y $eq$libresoc.v:147990$7237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:148195$7238 + cell $eq $eq$libresoc.v:147991$7238 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -274854,10 +274688,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:148195$7238_Y + connect \Y $eq$libresoc.v:147991$7238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:148197$7240 + cell $eq $eq$libresoc.v:147993$7240 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -274865,10 +274699,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:148197$7240_Y + connect \Y $eq$libresoc.v:147993$7240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:148198$7241 + cell $eq $eq$libresoc.v:147994$7241 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -274876,10 +274710,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:148198$7241_Y + connect \Y $eq$libresoc.v:147994$7241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:148200$7243 + cell $eq $eq$libresoc.v:147996$7243 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -274887,10 +274721,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:148200$7243_Y + connect \Y $eq$libresoc.v:147996$7243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:148201$7244 + cell $eq $eq$libresoc.v:147997$7244 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -274898,10 +274732,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:148201$7244_Y + connect \Y $eq$libresoc.v:147997$7244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:148215$7258 + cell $ne $ne$libresoc.v:148011$7258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274909,10 +274743,10 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:148215$7258_Y + connect \Y $ne$libresoc.v:148011$7258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:148226$7269 + cell $ne $ne$libresoc.v:148022$7269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274920,74 +274754,74 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:148226$7269_Y + connect \Y $ne$libresoc.v:148022$7269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:148176$7219 + cell $not $not$libresoc.v:147972$7219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$116 - connect \Y $not$libresoc.v:148176$7219_Y + connect \Y $not$libresoc.v:147972$7219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:148180$7223 + cell $not $not$libresoc.v:147976$7223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$124 - connect \Y $not$libresoc.v:148180$7223_Y + connect \Y $not$libresoc.v:147976$7223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" - cell $not $not$libresoc.v:148191$7234 + cell $not $not$libresoc.v:147987$7234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__insn [21] - connect \Y $not$libresoc.v:148191$7234_Y + connect \Y $not$libresoc.v:147987$7234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $not$libresoc.v:148204$7247 + cell $not $not$libresoc.v:148000$7247 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:148204$7247_Y + connect \Y $not$libresoc.v:148000$7247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $not $not$libresoc.v:148209$7252 + cell $not $not$libresoc.v:148005$7252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$58 - connect \Y $not$libresoc.v:148209$7252_Y + connect \Y $not$libresoc.v:148005$7252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $not $not$libresoc.v:148212$7255 + cell $not $not$libresoc.v:148008$7255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $not$libresoc.v:148212$7255_Y + connect \Y $not$libresoc.v:148008$7255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:148216$7259 + cell $not $not$libresoc.v:148012$7259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:148216$7259_Y + connect \Y $not$libresoc.v:148012$7259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:148217$7260 + cell $not $not$libresoc.v:148013$7260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:148217$7260_Y + connect \Y $not$libresoc.v:148013$7260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:148196$7239 + cell $or $or$libresoc.v:147992$7239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274995,10 +274829,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:148196$7239_Y + connect \Y $or$libresoc.v:147992$7239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:148199$7242 + cell $or $or$libresoc.v:147995$7242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275006,10 +274840,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:148199$7242_Y + connect \Y $or$libresoc.v:147995$7242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:148202$7245 + cell $or $or$libresoc.v:147998$7245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275017,10 +274851,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$42 connect \B \$44 - connect \Y $or$libresoc.v:148202$7245_Y + connect \Y $or$libresoc.v:147998$7245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:148213$7256 + cell $or $or$libresoc.v:148009$7256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275028,10 +274862,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:148213$7256_Y + connect \Y $or$libresoc.v:148009$7256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:148218$7261 + cell $or $or$libresoc.v:148014$7261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275039,10 +274873,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:148218$7261_Y + connect \Y $or$libresoc.v:148014$7261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:148221$7264 + cell $or $or$libresoc.v:148017$7264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275050,10 +274884,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:148221$7264_Y + connect \Y $or$libresoc.v:148017$7264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:148224$7267 + cell $or $or$libresoc.v:148020$7267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275061,66 +274895,66 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:148224$7267_Y + connect \Y $or$libresoc.v:148020$7267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" - cell $reduce_or $reduce_or$libresoc.v:148167$7210 + cell $reduce_or $reduce_or$libresoc.v:147963$7210 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:148167$7210_Y + connect \Y $reduce_or$libresoc.v:147963$7210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" - cell $reduce_or $reduce_or$libresoc.v:148171$7214 + cell $reduce_or $reduce_or$libresoc.v:147967$7214 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:148171$7214_Y + connect \Y $reduce_or$libresoc.v:147967$7214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $reduce_or $reduce_or$libresoc.v:148208$7251 + cell $reduce_or $reduce_or$libresoc.v:148004$7251 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$59 - connect \Y $reduce_or$libresoc.v:148208$7251_Y + connect \Y $reduce_or$libresoc.v:148004$7251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $reduce_or $reduce_or$libresoc.v:148211$7254 + cell $reduce_or $reduce_or$libresoc.v:148007$7254 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$65 - connect \Y $reduce_or$libresoc.v:148211$7254_Y + connect \Y $reduce_or$libresoc.v:148007$7254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" - cell $mux $ternary$libresoc.v:148220$7263 + cell $mux $ternary$libresoc.v:148016$7263 parameter \WIDTH 1 connect \A \a_n [63] connect \B \a_n [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:148220$7263_Y + connect \Y $ternary$libresoc.v:148016$7263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - cell $mux $ternary$libresoc.v:148223$7266 + cell $mux $ternary$libresoc.v:148019$7266 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:148223$7266_Y + connect \Y $ternary$libresoc.v:148019$7266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" - cell $mux $ternary$libresoc.v:148227$7270 + cell $mux $ternary$libresoc.v:148023$7270 parameter \WIDTH 1 connect \A \carry_64 connect \B \carry_32 connect \S \is_32bit - connect \Y $ternary$libresoc.v:148227$7270_Y + connect \Y $ternary$libresoc.v:148023$7270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:148172$7215 + cell $xor $xor$libresoc.v:147968$7215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275128,10 +274962,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [32] connect \B \b_i [32] - connect \Y $xor$libresoc.v:148172$7215_Y + connect \Y $xor$libresoc.v:147968$7215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:148173$7216 + cell $xor $xor$libresoc.v:147969$7216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275139,10 +274973,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \$109 - connect \Y $xor$libresoc.v:148173$7216_Y + connect \Y $xor$libresoc.v:147969$7216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:148174$7217 + cell $xor $xor$libresoc.v:147970$7217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275150,10 +274984,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [0] connect \B \add_o [64] - connect \Y $xor$libresoc.v:148174$7217_Y + connect \Y $xor$libresoc.v:147970$7217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:148175$7218 + cell $xor $xor$libresoc.v:147971$7218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275161,10 +274995,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [63] connect \B \b_i [63] - connect \Y $xor$libresoc.v:148175$7218_Y + connect \Y $xor$libresoc.v:147971$7218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:148178$7221 + cell $xor $xor$libresoc.v:147974$7221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275172,10 +275006,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [1] connect \B \add_o [32] - connect \Y $xor$libresoc.v:148178$7221_Y + connect \Y $xor$libresoc.v:147974$7221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:148179$7222 + cell $xor $xor$libresoc.v:147975$7222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275183,10 +275017,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [31] connect \B \b_i [31] - connect \Y $xor$libresoc.v:148179$7222_Y + connect \Y $xor$libresoc.v:147975$7222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:148205$7248 + cell $xor $xor$libresoc.v:148001$7248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275194,10 +275028,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \ra [32] - connect \Y $xor$libresoc.v:148205$7248_Y + connect \Y $xor$libresoc.v:148001$7248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:148206$7249 + cell $xor $xor$libresoc.v:148002$7249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275205,10 +275039,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$53 connect \B \rb [32] - connect \Y $xor$libresoc.v:148206$7249_Y + connect \Y $xor$libresoc.v:148002$7249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $xor $xor$libresoc.v:148207$7250 + cell $xor $xor$libresoc.v:148003$7250 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -275216,10 +275050,10 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [31:0] connect \B \rb [31:0] - connect \Y $xor$libresoc.v:148207$7250_Y + connect \Y $xor$libresoc.v:148003$7250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $xor $xor$libresoc.v:148210$7253 + cell $xor $xor$libresoc.v:148006$7253 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -275227,24 +275061,24 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [63:32] connect \B \rb [63:32] - connect \Y $xor$libresoc.v:148210$7253_Y + connect \Y $xor$libresoc.v:148006$7253_Y end - attribute \src "libresoc.v:147706.7-147706.20" - process $proc$libresoc.v:147706$7300 + attribute \src "libresoc.v:147502.7-147502.20" + process $proc$libresoc.v:147502$7300 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148228.3-148237.6" - process $proc$libresoc.v:148228$7271 + attribute \src "libresoc.v:148024.3-148033.6" + process $proc$libresoc.v:148024$7271 assign { } { } assign { } { } assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "libresoc.v:148229.5-148229.29" + attribute \src "libresoc.v:148025.5-148025.29" switch \initial - attribute \src "libresoc.v:148229.9-148229.17" + attribute \src "libresoc.v:148025.9-148025.17" case 1'1 case end @@ -275260,13 +275094,13 @@ module \main sync always update \is_32bit $0\is_32bit[0:0] end - attribute \src "libresoc.v:148238.3-148260.6" - process $proc$libresoc.v:148238$7272 + attribute \src "libresoc.v:148034.3-148056.6" + process $proc$libresoc.v:148034$7272 assign { } { } assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "libresoc.v:148239.5-148239.29" + attribute \src "libresoc.v:148035.5-148035.29" switch \initial - attribute \src "libresoc.v:148239.9-148239.17" + attribute \src "libresoc.v:148035.9-148035.17" case 1'1 case end @@ -275299,14 +275133,14 @@ module \main sync always update \a_i $0\a_i[63:0] end - attribute \src "libresoc.v:148261.3-148271.6" - process $proc$libresoc.v:148261$7273 + attribute \src "libresoc.v:148057.3-148067.6" + process $proc$libresoc.v:148057$7273 assign { } { } assign { } { } assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "libresoc.v:148262.5-148262.29" + attribute \src "libresoc.v:148058.5-148058.29" switch \initial - attribute \src "libresoc.v:148262.9-148262.17" + attribute \src "libresoc.v:148058.9-148058.17" case 1'1 case end @@ -275322,14 +275156,14 @@ module \main sync always update \zerohi $0\zerohi[0:0] end - attribute \src "libresoc.v:148272.3-148298.6" - process $proc$libresoc.v:148272$7274 + attribute \src "libresoc.v:148068.3-148094.6" + process $proc$libresoc.v:148068$7274 assign { } { } assign { } { } assign $0\tval[4:0] $1\tval[4:0] - attribute \src "libresoc.v:148273.5-148273.29" + attribute \src "libresoc.v:148069.5-148069.29" switch \initial - attribute \src "libresoc.v:148273.9-148273.17" + attribute \src "libresoc.v:148069.9-148069.17" case 1'1 case end @@ -275367,14 +275201,14 @@ module \main sync always update \tval $0\tval[4:0] end - attribute \src "libresoc.v:148299.3-148317.6" - process $proc$libresoc.v:148299$7275 + attribute \src "libresoc.v:148095.3-148113.6" + process $proc$libresoc.v:148095$7275 assign { } { } assign { } { } assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "libresoc.v:148300.5-148300.29" + attribute \src "libresoc.v:148096.5-148096.29" switch \initial - attribute \src "libresoc.v:148300.9-148300.17" + attribute \src "libresoc.v:148096.9-148096.17" case 1'1 case end @@ -275400,14 +275234,14 @@ module \main sync always update \msb_a $0\msb_a[0:0] end - attribute \src "libresoc.v:148318.3-148336.6" - process $proc$libresoc.v:148318$7276 + attribute \src "libresoc.v:148114.3-148132.6" + process $proc$libresoc.v:148114$7276 assign { } { } assign { } { } assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "libresoc.v:148319.5-148319.29" + attribute \src "libresoc.v:148115.5-148115.29" switch \initial - attribute \src "libresoc.v:148319.9-148319.17" + attribute \src "libresoc.v:148115.9-148115.17" case 1'1 case end @@ -275433,14 +275267,14 @@ module \main sync always update \msb_b $0\msb_b[0:0] end - attribute \src "libresoc.v:148337.3-148363.6" - process $proc$libresoc.v:148337$7277 + attribute \src "libresoc.v:148133.3-148159.6" + process $proc$libresoc.v:148133$7277 assign { } { } assign { } { } assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "libresoc.v:148338.5-148338.29" + attribute \src "libresoc.v:148134.5-148134.29" switch \initial - attribute \src "libresoc.v:148338.9-148338.17" + attribute \src "libresoc.v:148134.9-148134.17" case 1'1 case end @@ -275476,14 +275310,14 @@ module \main sync always update \a_lt $0\a_lt[0:0] end - attribute \src "libresoc.v:148364.3-148397.6" - process $proc$libresoc.v:148364$7278 + attribute \src "libresoc.v:148160.3-148193.6" + process $proc$libresoc.v:148160$7278 assign { } { } assign { } { } assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "libresoc.v:148365.5-148365.29" + attribute \src "libresoc.v:148161.5-148161.29" switch \initial - attribute \src "libresoc.v:148365.9-148365.17" + attribute \src "libresoc.v:148161.9-148161.17" case 1'1 case end @@ -275521,14 +275355,14 @@ module \main sync always update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:148398.3-148420.6" - process $proc$libresoc.v:148398$7279 + attribute \src "libresoc.v:148194.3-148216.6" + process $proc$libresoc.v:148194$7279 assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "libresoc.v:148399.5-148399.29" + attribute \src "libresoc.v:148195.5-148195.29" switch \initial - attribute \src "libresoc.v:148399.9-148399.17" + attribute \src "libresoc.v:148195.9-148195.17" case 1'1 case end @@ -275554,14 +275388,14 @@ module \main sync always update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:148421.3-148462.6" - process $proc$libresoc.v:148421$7280 + attribute \src "libresoc.v:148217.3-148258.6" + process $proc$libresoc.v:148217$7280 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:148422.5-148422.29" + attribute \src "libresoc.v:148218.5-148218.29" switch \initial - attribute \src "libresoc.v:148422.9-148422.17" + attribute \src "libresoc.v:148218.9-148218.17" case 1'1 case end @@ -275617,14 +275451,14 @@ module \main sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:148463.3-148485.6" - process $proc$libresoc.v:148463$7281 + attribute \src "libresoc.v:148259.3-148281.6" + process $proc$libresoc.v:148259$7281 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:148464.5-148464.29" + attribute \src "libresoc.v:148260.5-148260.29" switch \initial - attribute \src "libresoc.v:148464.9-148464.17" + attribute \src "libresoc.v:148260.9-148260.17" case 1'1 case end @@ -275651,14 +275485,14 @@ module \main sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:148486.3-148503.6" - process $proc$libresoc.v:148486$7282 + attribute \src "libresoc.v:148282.3-148299.6" + process $proc$libresoc.v:148282$7282 assign { } { } assign { } { } assign $0\ca[1:0] $1\ca[1:0] - attribute \src "libresoc.v:148487.5-148487.29" + attribute \src "libresoc.v:148283.5-148283.29" switch \initial - attribute \src "libresoc.v:148487.9-148487.17" + attribute \src "libresoc.v:148283.9-148283.17" case 1'1 case end @@ -275678,13 +275512,13 @@ module \main sync always update \ca $0\ca[1:0] end - attribute \src "libresoc.v:148504.3-148526.6" - process $proc$libresoc.v:148504$7283 + attribute \src "libresoc.v:148300.3-148322.6" + process $proc$libresoc.v:148300$7283 assign { } { } assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "libresoc.v:148505.5-148505.29" + attribute \src "libresoc.v:148301.5-148301.29" switch \initial - attribute \src "libresoc.v:148505.9-148505.17" + attribute \src "libresoc.v:148301.9-148301.17" case 1'1 case end @@ -275717,14 +275551,14 @@ module \main sync always update \b_i $0\b_i[63:0] end - attribute \src "libresoc.v:148527.3-148541.6" - process $proc$libresoc.v:148527$7284 + attribute \src "libresoc.v:148323.3-148337.6" + process $proc$libresoc.v:148323$7284 assign { } { } assign { } { } assign $0\xer_ca$20[1:0]$7285 $1\xer_ca$20[1:0]$7286 - attribute \src "libresoc.v:148528.5-148528.29" + attribute \src "libresoc.v:148324.5-148324.29" switch \initial - attribute \src "libresoc.v:148528.9-148528.17" + attribute \src "libresoc.v:148324.9-148324.17" case 1'1 case end @@ -275743,14 +275577,14 @@ module \main sync always update \xer_ca$20 $0\xer_ca$20[1:0]$7285 end - attribute \src "libresoc.v:148542.3-148556.6" - process $proc$libresoc.v:148542$7287 + attribute \src "libresoc.v:148338.3-148352.6" + process $proc$libresoc.v:148338$7287 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:148543.5-148543.29" + attribute \src "libresoc.v:148339.5-148339.29" switch \initial - attribute \src "libresoc.v:148543.9-148543.17" + attribute \src "libresoc.v:148339.9-148339.17" case 1'1 case end @@ -275769,14 +275603,14 @@ module \main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:148557.3-148574.6" - process $proc$libresoc.v:148557$7288 + attribute \src "libresoc.v:148353.3-148370.6" + process $proc$libresoc.v:148353$7288 assign { } { } assign { } { } assign $0\ov[1:0] $1\ov[1:0] - attribute \src "libresoc.v:148558.5-148558.29" + attribute \src "libresoc.v:148354.5-148354.29" switch \initial - attribute \src "libresoc.v:148558.9-148558.17" + attribute \src "libresoc.v:148354.9-148354.17" case 1'1 case end @@ -275796,14 +275630,14 @@ module \main sync always update \ov $0\ov[1:0] end - attribute \src "libresoc.v:148575.3-148589.6" - process $proc$libresoc.v:148575$7289 + attribute \src "libresoc.v:148371.3-148385.6" + process $proc$libresoc.v:148371$7289 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:148576.5-148576.29" + attribute \src "libresoc.v:148372.5-148372.29" switch \initial - attribute \src "libresoc.v:148576.9-148576.17" + attribute \src "libresoc.v:148372.9-148372.17" case 1'1 case end @@ -275822,14 +275656,14 @@ module \main sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:148590.3-148604.6" - process $proc$libresoc.v:148590$7290 + attribute \src "libresoc.v:148386.3-148400.6" + process $proc$libresoc.v:148386$7290 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:148591.5-148591.29" + attribute \src "libresoc.v:148387.5-148387.29" switch \initial - attribute \src "libresoc.v:148591.9-148591.17" + attribute \src "libresoc.v:148387.9-148387.17" case 1'1 case end @@ -275848,14 +275682,14 @@ module \main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:148605.3-148627.6" - process $proc$libresoc.v:148605$7291 + attribute \src "libresoc.v:148401.3-148423.6" + process $proc$libresoc.v:148401$7291 assign { } { } assign { } { } assign $0\src1[7:0] $1\src1[7:0] - attribute \src "libresoc.v:148606.5-148606.29" + attribute \src "libresoc.v:148402.5-148402.29" switch \initial - attribute \src "libresoc.v:148606.9-148606.17" + attribute \src "libresoc.v:148402.9-148402.17" case 1'1 case end @@ -275880,14 +275714,14 @@ module \main sync always update \src1 $0\src1[7:0] end - attribute \src "libresoc.v:148628.3-148659.6" - process $proc$libresoc.v:148628$7292 + attribute \src "libresoc.v:148424.3-148455.6" + process $proc$libresoc.v:148424$7292 assign { } { } assign { } { } assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "libresoc.v:148629.5-148629.29" + attribute \src "libresoc.v:148425.5-148425.29" switch \initial - attribute \src "libresoc.v:148629.9-148629.17" + attribute \src "libresoc.v:148425.9-148425.17" case 1'1 case end @@ -275919,14 +275753,14 @@ module \main sync always update \eqs $0\eqs[7:0] end - attribute \src "libresoc.v:148660.3-148669.6" - process $proc$libresoc.v:148660$7293 + attribute \src "libresoc.v:148456.3-148465.6" + process $proc$libresoc.v:148456$7293 assign { } { } assign { } { } assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "libresoc.v:148661.5-148661.29" + attribute \src "libresoc.v:148457.5-148457.29" switch \initial - attribute \src "libresoc.v:148661.9-148661.17" + attribute \src "libresoc.v:148457.9-148457.17" case 1'1 case end @@ -275942,14 +275776,14 @@ module \main sync always update \add_a $0\add_a[65:0] end - attribute \src "libresoc.v:148670.3-148679.6" - process $proc$libresoc.v:148670$7294 + attribute \src "libresoc.v:148466.3-148475.6" + process $proc$libresoc.v:148466$7294 assign { } { } assign { } { } assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "libresoc.v:148671.5-148671.29" + attribute \src "libresoc.v:148467.5-148467.29" switch \initial - attribute \src "libresoc.v:148671.9-148671.17" + attribute \src "libresoc.v:148467.9-148467.17" case 1'1 case end @@ -275965,14 +275799,14 @@ module \main sync always update \add_b $0\add_b[65:0] end - attribute \src "libresoc.v:148680.3-148689.6" - process $proc$libresoc.v:148680$7295 + attribute \src "libresoc.v:148476.3-148485.6" + process $proc$libresoc.v:148476$7295 assign { } { } assign { } { } assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "libresoc.v:148681.5-148681.29" + attribute \src "libresoc.v:148477.5-148477.29" switch \initial - attribute \src "libresoc.v:148681.9-148681.17" + attribute \src "libresoc.v:148477.9-148477.17" case 1'1 case end @@ -275988,14 +275822,14 @@ module \main sync always update \add_o $0\add_o[65:0] end - attribute \src "libresoc.v:148690.3-148700.6" - process $proc$libresoc.v:148690$7296 + attribute \src "libresoc.v:148486.3-148496.6" + process $proc$libresoc.v:148486$7296 assign { } { } assign { } { } assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "libresoc.v:148691.5-148691.29" + attribute \src "libresoc.v:148487.5-148487.29" switch \initial - attribute \src "libresoc.v:148691.9-148691.17" + attribute \src "libresoc.v:148487.9-148487.17" case 1'1 case end @@ -276011,14 +275845,14 @@ module \main sync always update \a_n $0\a_n[63:0] end - attribute \src "libresoc.v:148701.3-148711.6" - process $proc$libresoc.v:148701$7297 + attribute \src "libresoc.v:148497.3-148507.6" + process $proc$libresoc.v:148497$7297 assign { } { } assign { } { } assign $0\carry_32[0:0] $1\carry_32[0:0] - attribute \src "libresoc.v:148702.5-148702.29" + attribute \src "libresoc.v:148498.5-148498.29" switch \initial - attribute \src "libresoc.v:148702.9-148702.17" + attribute \src "libresoc.v:148498.9-148498.17" case 1'1 case end @@ -276034,14 +275868,14 @@ module \main sync always update \carry_32 $0\carry_32[0:0] end - attribute \src "libresoc.v:148712.3-148722.6" - process $proc$libresoc.v:148712$7298 + attribute \src "libresoc.v:148508.3-148518.6" + process $proc$libresoc.v:148508$7298 assign { } { } assign { } { } assign $0\carry_64[0:0] $1\carry_64[0:0] - attribute \src "libresoc.v:148713.5-148713.29" + attribute \src "libresoc.v:148509.5-148509.29" switch \initial - attribute \src "libresoc.v:148713.9-148713.17" + attribute \src "libresoc.v:148509.9-148509.17" case 1'1 case end @@ -276057,14 +275891,14 @@ module \main sync always update \carry_64 $0\carry_64[0:0] end - attribute \src "libresoc.v:148723.3-148733.6" - process $proc$libresoc.v:148723$7299 + attribute \src "libresoc.v:148519.3-148529.6" + process $proc$libresoc.v:148519$7299 assign { } { } assign { } { } assign $0\zerolo[0:0] $1\zerolo[0:0] - attribute \src "libresoc.v:148724.5-148724.29" + attribute \src "libresoc.v:148520.5-148520.29" switch \initial - attribute \src "libresoc.v:148724.9-148724.17" + attribute \src "libresoc.v:148520.9-148520.17" case 1'1 case end @@ -276080,88 +275914,88 @@ module \main sync always update \zerolo $0\zerolo[0:0] end - connect \$99 $reduce_or$libresoc.v:148167$7210_Y - connect \$101 $eq$libresoc.v:148168$7211_Y - connect \$103 $eq$libresoc.v:148169$7212_Y - connect \$105 $eq$libresoc.v:148170$7213_Y - connect \$107 $reduce_or$libresoc.v:148171$7214_Y - connect \$109 $xor$libresoc.v:148172$7215_Y - connect \$111 $xor$libresoc.v:148173$7216_Y - connect \$113 $xor$libresoc.v:148174$7217_Y - connect \$116 $xor$libresoc.v:148175$7218_Y - connect \$115 $not$libresoc.v:148176$7219_Y - connect \$119 $and$libresoc.v:148177$7220_Y - connect \$121 $xor$libresoc.v:148178$7221_Y - connect \$124 $xor$libresoc.v:148179$7222_Y - connect \$123 $not$libresoc.v:148180$7223_Y - connect \$127 $and$libresoc.v:148181$7224_Y - connect \$129 $eq$libresoc.v:148182$7225_Y - connect \$131 $eq$libresoc.v:148183$7226_Y - connect \$133 $eq$libresoc.v:148184$7227_Y - connect \$135 $eq$libresoc.v:148185$7228_Y - connect \$137 $eq$libresoc.v:148186$7229_Y - connect \$139 $eq$libresoc.v:148187$7230_Y - connect \$141 $eq$libresoc.v:148188$7231_Y - connect \$143 $eq$libresoc.v:148189$7232_Y - connect \$22 $eq$libresoc.v:148190$7233_Y - connect \$24 $not$libresoc.v:148191$7234_Y - connect \$26 $eq$libresoc.v:148192$7235_Y - connect \$28 $eq$libresoc.v:148193$7236_Y - connect \$30 $eq$libresoc.v:148194$7237_Y - connect \$32 $eq$libresoc.v:148195$7238_Y - connect \$34 $or$libresoc.v:148196$7239_Y - connect \$36 $eq$libresoc.v:148197$7240_Y - connect \$38 $eq$libresoc.v:148198$7241_Y - connect \$40 $or$libresoc.v:148199$7242_Y - connect \$42 $eq$libresoc.v:148200$7243_Y - connect \$44 $eq$libresoc.v:148201$7244_Y - connect \$46 $or$libresoc.v:148202$7245_Y - connect \$49 $add$libresoc.v:148203$7246_Y - connect \$51 $not$libresoc.v:148204$7247_Y - connect \$53 $xor$libresoc.v:148205$7248_Y - connect \$55 $xor$libresoc.v:148206$7249_Y - connect \$59 $xor$libresoc.v:148207$7250_Y - connect \$58 $reduce_or$libresoc.v:148208$7251_Y - connect \$57 $not$libresoc.v:148209$7252_Y - connect \$65 $xor$libresoc.v:148210$7253_Y - connect \$64 $reduce_or$libresoc.v:148211$7254_Y - connect \$63 $not$libresoc.v:148212$7255_Y - connect \$69 $or$libresoc.v:148213$7256_Y - connect \$71 $and$libresoc.v:148214$7257_Y - connect \$73 $ne$libresoc.v:148215$7258_Y - connect \$75 $not$libresoc.v:148216$7259_Y - connect \$77 $not$libresoc.v:148217$7260_Y - connect \$79 $or$libresoc.v:148218$7261_Y - connect \$81 $and$libresoc.v:148219$7262_Y - connect \$83 $ternary$libresoc.v:148220$7263_Y - connect \$85 $or$libresoc.v:148221$7264_Y - connect \$87 $and$libresoc.v:148222$7265_Y - connect \$89 $ternary$libresoc.v:148223$7266_Y - connect \$91 $or$libresoc.v:148224$7267_Y - connect \$93 $and$libresoc.v:148225$7268_Y - connect \$95 $ne$libresoc.v:148226$7269_Y - connect \$97 $ternary$libresoc.v:148227$7270_Y + connect \$99 $reduce_or$libresoc.v:147963$7210_Y + connect \$101 $eq$libresoc.v:147964$7211_Y + connect \$103 $eq$libresoc.v:147965$7212_Y + connect \$105 $eq$libresoc.v:147966$7213_Y + connect \$107 $reduce_or$libresoc.v:147967$7214_Y + connect \$109 $xor$libresoc.v:147968$7215_Y + connect \$111 $xor$libresoc.v:147969$7216_Y + connect \$113 $xor$libresoc.v:147970$7217_Y + connect \$116 $xor$libresoc.v:147971$7218_Y + connect \$115 $not$libresoc.v:147972$7219_Y + connect \$119 $and$libresoc.v:147973$7220_Y + connect \$121 $xor$libresoc.v:147974$7221_Y + connect \$124 $xor$libresoc.v:147975$7222_Y + connect \$123 $not$libresoc.v:147976$7223_Y + connect \$127 $and$libresoc.v:147977$7224_Y + connect \$129 $eq$libresoc.v:147978$7225_Y + connect \$131 $eq$libresoc.v:147979$7226_Y + connect \$133 $eq$libresoc.v:147980$7227_Y + connect \$135 $eq$libresoc.v:147981$7228_Y + connect \$137 $eq$libresoc.v:147982$7229_Y + connect \$139 $eq$libresoc.v:147983$7230_Y + connect \$141 $eq$libresoc.v:147984$7231_Y + connect \$143 $eq$libresoc.v:147985$7232_Y + connect \$22 $eq$libresoc.v:147986$7233_Y + connect \$24 $not$libresoc.v:147987$7234_Y + connect \$26 $eq$libresoc.v:147988$7235_Y + connect \$28 $eq$libresoc.v:147989$7236_Y + connect \$30 $eq$libresoc.v:147990$7237_Y + connect \$32 $eq$libresoc.v:147991$7238_Y + connect \$34 $or$libresoc.v:147992$7239_Y + connect \$36 $eq$libresoc.v:147993$7240_Y + connect \$38 $eq$libresoc.v:147994$7241_Y + connect \$40 $or$libresoc.v:147995$7242_Y + connect \$42 $eq$libresoc.v:147996$7243_Y + connect \$44 $eq$libresoc.v:147997$7244_Y + connect \$46 $or$libresoc.v:147998$7245_Y + connect \$49 $add$libresoc.v:147999$7246_Y + connect \$51 $not$libresoc.v:148000$7247_Y + connect \$53 $xor$libresoc.v:148001$7248_Y + connect \$55 $xor$libresoc.v:148002$7249_Y + connect \$59 $xor$libresoc.v:148003$7250_Y + connect \$58 $reduce_or$libresoc.v:148004$7251_Y + connect \$57 $not$libresoc.v:148005$7252_Y + connect \$65 $xor$libresoc.v:148006$7253_Y + connect \$64 $reduce_or$libresoc.v:148007$7254_Y + connect \$63 $not$libresoc.v:148008$7255_Y + connect \$69 $or$libresoc.v:148009$7256_Y + connect \$71 $and$libresoc.v:148010$7257_Y + connect \$73 $ne$libresoc.v:148011$7258_Y + connect \$75 $not$libresoc.v:148012$7259_Y + connect \$77 $not$libresoc.v:148013$7260_Y + connect \$79 $or$libresoc.v:148014$7261_Y + connect \$81 $and$libresoc.v:148015$7262_Y + connect \$83 $ternary$libresoc.v:148016$7263_Y + connect \$85 $or$libresoc.v:148017$7264_Y + connect \$87 $and$libresoc.v:148018$7265_Y + connect \$89 $ternary$libresoc.v:148019$7266_Y + connect \$91 $or$libresoc.v:148020$7267_Y + connect \$93 $and$libresoc.v:148021$7268_Y + connect \$95 $ne$libresoc.v:148022$7269_Y + connect \$97 $ternary$libresoc.v:148023$7270_Y connect \$48 \$49 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$21 \xer_so end -attribute \src "libresoc.v:148742.1-149156.10" +attribute \src "libresoc.v:148538.1-148952.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" attribute \generator "nMigen" module \main$114 - attribute \src "libresoc.v:148743.7-148743.20" + attribute \src "libresoc.v:148539.7-148539.20" wire $0\initial[0:0] - attribute \src "libresoc.v:149108.3-149138.6" + attribute \src "libresoc.v:148904.3-148934.6" wire width 4 $0\mode[3:0] - attribute \src "libresoc.v:149073.3-149107.6" + attribute \src "libresoc.v:148869.3-148903.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:149108.3-149138.6" + attribute \src "libresoc.v:148904.3-148934.6" wire width 4 $1\mode[3:0] - attribute \src "libresoc.v:149073.3-149107.6" + attribute \src "libresoc.v:148869.3-148903.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:148743.7-148743.15" + attribute \src "libresoc.v:148539.7-148539.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" wire width 5 \mb @@ -276476,7 +276310,7 @@ module \main$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 42 \xer_so$19 attribute \module_not_derived 1 - attribute \src "libresoc.v:149057.11-149072.4" + attribute \src "libresoc.v:148853.11-148868.4" cell \rotator \rotator connect \arith \rotator_arith connect \carry_out_o \rotator_carry_out_o @@ -276493,22 +276327,22 @@ module \main$114 connect \shift \rotator_shift connect \sign_ext_rs \rotator_sign_ext_rs end - attribute \src "libresoc.v:148743.7-148743.20" - process $proc$libresoc.v:148743$7303 + attribute \src "libresoc.v:148539.7-148539.20" + process $proc$libresoc.v:148539$7303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149073.3-149107.6" - process $proc$libresoc.v:149073$7301 + attribute \src "libresoc.v:148869.3-148903.6" + process $proc$libresoc.v:148869$7301 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:149074.5-149074.29" + attribute \src "libresoc.v:148870.5-148870.29" switch \initial - attribute \src "libresoc.v:149074.9-149074.17" + attribute \src "libresoc.v:148870.9-148870.17" case 1'1 case end @@ -276540,14 +276374,14 @@ module \main$114 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:149108.3-149138.6" - process $proc$libresoc.v:149108$7302 + attribute \src "libresoc.v:148904.3-148934.6" + process $proc$libresoc.v:148904$7302 assign { } { } assign { } { } assign $0\mode[3:0] $1\mode[3:0] - attribute \src "libresoc.v:149109.5-149109.29" + attribute \src "libresoc.v:148905.5-148905.29" switch \initial - attribute \src "libresoc.v:149109.9-149109.17" + attribute \src "libresoc.v:148905.9-148905.17" case 1'1 case end @@ -276601,109 +276435,109 @@ module \main$114 connect \me \sr_op__insn [5:1] connect \mb \sr_op__insn [10:6] end -attribute \src "libresoc.v:149160.1-149700.10" +attribute \src "libresoc.v:148956.1-149496.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" attribute \generator "nMigen" module \main$22 - attribute \src "libresoc.v:149607.3-149630.6" + attribute \src "libresoc.v:149403.3-149426.6" wire $0\bc_taken[0:0] - attribute \src "libresoc.v:149482.3-149493.6" + attribute \src "libresoc.v:149278.3-149289.6" wire width 64 $0\br_addr[63:0] - attribute \src "libresoc.v:149494.3-149520.6" + attribute \src "libresoc.v:149290.3-149316.6" wire width 64 $0\br_imm_addr[63:0] - attribute \src "libresoc.v:149521.3-149539.6" + attribute \src "libresoc.v:149317.3-149335.6" wire $0\br_taken[0:0] - attribute \src "libresoc.v:149579.3-149593.6" + attribute \src "libresoc.v:149375.3-149389.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:149657.3-149677.6" + attribute \src "libresoc.v:149453.3-149473.6" wire width 64 $0\ctr_m[63:0] - attribute \src "libresoc.v:149631.3-149643.6" + attribute \src "libresoc.v:149427.3-149439.6" wire width 64 $0\ctr_n[63:0] - attribute \src "libresoc.v:149594.3-149606.6" + attribute \src "libresoc.v:149390.3-149402.6" wire $0\ctr_write[0:0] - attribute \src "libresoc.v:149678.3-149690.6" + attribute \src "libresoc.v:149474.3-149486.6" wire $0\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149644.3-149656.6" + attribute \src "libresoc.v:149440.3-149452.6" wire width 64 $0\fast1$10[63:0]$7336 - attribute \src "libresoc.v:149540.3-149558.6" + attribute \src "libresoc.v:149336.3-149354.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:149559.3-149568.6" + attribute \src "libresoc.v:149355.3-149364.6" wire width 64 $0\fast2$11[63:0]$7328 - attribute \src "libresoc.v:149569.3-149578.6" + attribute \src "libresoc.v:149365.3-149374.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:149161.7-149161.20" + attribute \src "libresoc.v:148957.7-148957.20" wire $0\initial[0:0] - attribute \src "libresoc.v:149607.3-149630.6" + attribute \src "libresoc.v:149403.3-149426.6" wire $1\bc_taken[0:0] - attribute \src "libresoc.v:149482.3-149493.6" + attribute \src "libresoc.v:149278.3-149289.6" wire width 64 $1\br_addr[63:0] - attribute \src "libresoc.v:149494.3-149520.6" + attribute \src "libresoc.v:149290.3-149316.6" wire width 64 $1\br_imm_addr[63:0] - attribute \src "libresoc.v:149521.3-149539.6" + attribute \src "libresoc.v:149317.3-149335.6" wire $1\br_taken[0:0] - attribute \src "libresoc.v:149579.3-149593.6" + attribute \src "libresoc.v:149375.3-149389.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:149657.3-149677.6" + attribute \src "libresoc.v:149453.3-149473.6" wire width 64 $1\ctr_m[63:0] - attribute \src "libresoc.v:149631.3-149643.6" + attribute \src "libresoc.v:149427.3-149439.6" wire width 64 $1\ctr_n[63:0] - attribute \src "libresoc.v:149594.3-149606.6" + attribute \src "libresoc.v:149390.3-149402.6" wire $1\ctr_write[0:0] - attribute \src "libresoc.v:149678.3-149690.6" + attribute \src "libresoc.v:149474.3-149486.6" wire $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149644.3-149656.6" + attribute \src "libresoc.v:149440.3-149452.6" wire width 64 $1\fast1$10[63:0]$7337 - attribute \src "libresoc.v:149540.3-149558.6" + attribute \src "libresoc.v:149336.3-149354.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:149559.3-149568.6" + attribute \src "libresoc.v:149355.3-149364.6" wire width 64 $1\fast2$11[63:0]$7329 - attribute \src "libresoc.v:149569.3-149578.6" + attribute \src "libresoc.v:149365.3-149374.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:149607.3-149630.6" + attribute \src "libresoc.v:149403.3-149426.6" wire $2\bc_taken[0:0] - attribute \src "libresoc.v:149494.3-149520.6" + attribute \src "libresoc.v:149290.3-149316.6" wire width 64 $2\br_imm_addr[63:0] - attribute \src "libresoc.v:149657.3-149677.6" + attribute \src "libresoc.v:149453.3-149473.6" wire width 64 $2\ctr_m[63:0] - attribute \src "libresoc.v:149466.18-149466.119" - wire width 65 $add$libresoc.v:149466$7306_Y - attribute \src "libresoc.v:149481.18-149481.113" - wire width 65 $add$libresoc.v:149481$7322_Y - attribute \src "libresoc.v:149473.18-149473.115" - wire $and$libresoc.v:149473$7313_Y - attribute \src "libresoc.v:149474.18-149474.117" - wire $and$libresoc.v:149474$7314_Y - attribute \src "libresoc.v:149480.18-149480.118" - wire $and$libresoc.v:149480$7321_Y - attribute \src "libresoc.v:149464.18-149464.120" - wire $eq$libresoc.v:149464$7304_Y - attribute \src "libresoc.v:149467.18-149467.111" - wire $eq$libresoc.v:149467$7307_Y - attribute \src "libresoc.v:149469.18-149469.111" - wire $eq$libresoc.v:149469$7309_Y - attribute \src "libresoc.v:149470.18-149470.111" - wire $eq$libresoc.v:149470$7310_Y - attribute \src "libresoc.v:149471.18-149471.109" - wire $eq$libresoc.v:149471$7311_Y - attribute \src "libresoc.v:149476.18-149476.98" - wire width 64 $extend$libresoc.v:149476$7316_Y - attribute \src "libresoc.v:149472.18-149472.104" - wire $not$libresoc.v:149472$7312_Y - attribute \src "libresoc.v:149479.18-149479.112" - wire $not$libresoc.v:149479$7320_Y - attribute \src "libresoc.v:149465.18-149465.116" - wire $or$libresoc.v:149465$7305_Y - attribute \src "libresoc.v:149468.18-149468.109" - wire $or$libresoc.v:149468$7308_Y - attribute \src "libresoc.v:149476.18-149476.98" - wire width 64 $pos$libresoc.v:149476$7317_Y - attribute \src "libresoc.v:149477.18-149477.103" - wire $reduce_or$libresoc.v:149477$7318_Y - attribute \src "libresoc.v:149475.18-149475.108" - wire width 65 $sub$libresoc.v:149475$7315_Y - attribute \src "libresoc.v:149478.18-149478.108" - wire $xor$libresoc.v:149478$7319_Y + attribute \src "libresoc.v:149262.18-149262.119" + wire width 65 $add$libresoc.v:149262$7306_Y + attribute \src "libresoc.v:149277.18-149277.113" + wire width 65 $add$libresoc.v:149277$7322_Y + attribute \src "libresoc.v:149269.18-149269.115" + wire $and$libresoc.v:149269$7313_Y + attribute \src "libresoc.v:149270.18-149270.117" + wire $and$libresoc.v:149270$7314_Y + attribute \src "libresoc.v:149276.18-149276.118" + wire $and$libresoc.v:149276$7321_Y + attribute \src "libresoc.v:149260.18-149260.120" + wire $eq$libresoc.v:149260$7304_Y + attribute \src "libresoc.v:149263.18-149263.111" + wire $eq$libresoc.v:149263$7307_Y + attribute \src "libresoc.v:149265.18-149265.111" + wire $eq$libresoc.v:149265$7309_Y + attribute \src "libresoc.v:149266.18-149266.111" + wire $eq$libresoc.v:149266$7310_Y + attribute \src "libresoc.v:149267.18-149267.109" + wire $eq$libresoc.v:149267$7311_Y + attribute \src "libresoc.v:149272.18-149272.98" + wire width 64 $extend$libresoc.v:149272$7316_Y + attribute \src "libresoc.v:149268.18-149268.104" + wire $not$libresoc.v:149268$7312_Y + attribute \src "libresoc.v:149275.18-149275.112" + wire $not$libresoc.v:149275$7320_Y + attribute \src "libresoc.v:149261.18-149261.116" + wire $or$libresoc.v:149261$7305_Y + attribute \src "libresoc.v:149264.18-149264.109" + wire $or$libresoc.v:149264$7308_Y + attribute \src "libresoc.v:149272.18-149272.98" + wire width 64 $pos$libresoc.v:149272$7317_Y + attribute \src "libresoc.v:149273.18-149273.103" + wire $reduce_or$libresoc.v:149273$7318_Y + attribute \src "libresoc.v:149271.18-149271.108" + wire width 65 $sub$libresoc.v:149271$7315_Y + attribute \src "libresoc.v:149274.18-149274.108" + wire $xor$libresoc.v:149274$7319_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" @@ -276994,7 +276828,7 @@ module \main$22 wire width 64 output 23 \fast2$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 24 \fast2_ok - attribute \src "libresoc.v:149161.7-149161.15" + attribute \src "libresoc.v:148957.7-148957.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 27 \muxid @@ -277005,7 +276839,7 @@ module \main$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$libresoc.v:149466$7306 + cell $add $add$libresoc.v:149262$7306 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -277013,10 +276847,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_imm_addr connect \B \br_op__cia - connect \Y $add$libresoc.v:149466$7306_Y + connect \Y $add$libresoc.v:149262$7306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$libresoc.v:149481$7322 + cell $add $add$libresoc.v:149277$7322 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -277024,10 +276858,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:149481$7322_Y + connect \Y $add$libresoc.v:149277$7322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$libresoc.v:149473$7313 + cell $and $and$libresoc.v:149269$7313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277035,10 +276869,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \$29 - connect \Y $and$libresoc.v:149473$7313_Y + connect \Y $and$libresoc.v:149269$7313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$libresoc.v:149474$7314 + cell $and $and$libresoc.v:149270$7314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277046,10 +276880,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \cr_bit - connect \Y $and$libresoc.v:149474$7314_Y + connect \Y $and$libresoc.v:149270$7314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$libresoc.v:149480$7321 + cell $and $and$libresoc.v:149276$7321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277057,10 +276891,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [10] connect \B \$44 - connect \Y $and$libresoc.v:149480$7321_Y + connect \Y $and$libresoc.v:149276$7321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$libresoc.v:149464$7304 + cell $eq $eq$libresoc.v:149260$7304 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -277068,10 +276902,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn_type connect \B 7'0001000 - connect \Y $eq$libresoc.v:149464$7304_Y + connect \Y $eq$libresoc.v:149260$7304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$libresoc.v:149467$7307 + cell $eq $eq$libresoc.v:149263$7307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277079,10 +276913,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \cr_bit connect \B \bo [3] - connect \Y $eq$libresoc.v:149467$7307_Y + connect \Y $eq$libresoc.v:149263$7307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$libresoc.v:149469$7309 + cell $eq $eq$libresoc.v:149265$7309 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -277090,10 +276924,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'0 - connect \Y $eq$libresoc.v:149469$7309_Y + connect \Y $eq$libresoc.v:149265$7309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$libresoc.v:149470$7310 + cell $eq $eq$libresoc.v:149266$7310 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -277101,10 +276935,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'1 - connect \Y $eq$libresoc.v:149470$7310_Y + connect \Y $eq$libresoc.v:149266$7310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$libresoc.v:149471$7311 + cell $eq $eq$libresoc.v:149267$7311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277112,34 +276946,34 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4] connect \B 1'1 - connect \Y $eq$libresoc.v:149471$7311_Y + connect \Y $eq$libresoc.v:149267$7311_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:149476$7316 + cell $pos $extend$libresoc.v:149272$7316 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \fast1 [31:0] - connect \Y $extend$libresoc.v:149476$7316_Y + connect \Y $extend$libresoc.v:149272$7316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$libresoc.v:149472$7312 + cell $not $not$libresoc.v:149268$7312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit - connect \Y $not$libresoc.v:149472$7312_Y + connect \Y $not$libresoc.v:149268$7312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$libresoc.v:149479$7320 + cell $not $not$libresoc.v:149275$7320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [6] - connect \Y $not$libresoc.v:149479$7320_Y + connect \Y $not$libresoc.v:149275$7320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$libresoc.v:149465$7305 + cell $or $or$libresoc.v:149261$7305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277147,10 +276981,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [1] connect \B \$12 - connect \Y $or$libresoc.v:149465$7305_Y + connect \Y $or$libresoc.v:149261$7305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$libresoc.v:149468$7308 + cell $or $or$libresoc.v:149264$7308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277158,26 +276992,26 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \$19 connect \B \bo [4] - connect \Y $or$libresoc.v:149468$7308_Y + connect \Y $or$libresoc.v:149264$7308_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:149476$7317 + cell $pos $pos$libresoc.v:149272$7317 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149476$7316_Y - connect \Y $pos$libresoc.v:149476$7317_Y + connect \A $extend$libresoc.v:149272$7316_Y + connect \Y $pos$libresoc.v:149272$7317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$libresoc.v:149477$7318 + cell $reduce_or $reduce_or$libresoc.v:149273$7318 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \ctr_n - connect \Y $reduce_or$libresoc.v:149477$7318_Y + connect \Y $reduce_or$libresoc.v:149273$7318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$libresoc.v:149475$7315 + cell $sub $sub$libresoc.v:149271$7315 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -277185,10 +277019,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \fast1 connect \B 1'1 - connect \Y $sub$libresoc.v:149475$7315_Y + connect \Y $sub$libresoc.v:149271$7315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$libresoc.v:149478$7319 + cell $xor $xor$libresoc.v:149274$7319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277196,23 +277030,23 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [1] connect \B \$40 - connect \Y $xor$libresoc.v:149478$7319_Y + connect \Y $xor$libresoc.v:149274$7319_Y end - attribute \src "libresoc.v:149161.7-149161.20" - process $proc$libresoc.v:149161$7340 + attribute \src "libresoc.v:148957.7-148957.20" + process $proc$libresoc.v:148957$7340 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149482.3-149493.6" - process $proc$libresoc.v:149482$7323 + attribute \src "libresoc.v:149278.3-149289.6" + process $proc$libresoc.v:149278$7323 assign { } { } assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "libresoc.v:149483.5-149483.29" + attribute \src "libresoc.v:149279.5-149279.29" switch \initial - attribute \src "libresoc.v:149483.9-149483.17" + attribute \src "libresoc.v:149279.9-149279.17" case 1'1 case end @@ -277230,14 +277064,14 @@ module \main$22 sync always update \br_addr $0\br_addr[63:0] end - attribute \src "libresoc.v:149494.3-149520.6" - process $proc$libresoc.v:149494$7324 + attribute \src "libresoc.v:149290.3-149316.6" + process $proc$libresoc.v:149290$7324 assign { } { } assign { } { } assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "libresoc.v:149495.5-149495.29" + attribute \src "libresoc.v:149291.5-149291.29" switch \initial - attribute \src "libresoc.v:149495.9-149495.17" + attribute \src "libresoc.v:149291.9-149291.17" case 1'1 case end @@ -277272,14 +277106,14 @@ module \main$22 sync always update \br_imm_addr $0\br_imm_addr[63:0] end - attribute \src "libresoc.v:149521.3-149539.6" - process $proc$libresoc.v:149521$7325 + attribute \src "libresoc.v:149317.3-149335.6" + process $proc$libresoc.v:149317$7325 assign { } { } assign { } { } assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "libresoc.v:149522.5-149522.29" + attribute \src "libresoc.v:149318.5-149318.29" switch \initial - attribute \src "libresoc.v:149522.9-149522.17" + attribute \src "libresoc.v:149318.9-149318.17" case 1'1 case end @@ -277303,14 +277137,14 @@ module \main$22 sync always update \br_taken $0\br_taken[0:0] end - attribute \src "libresoc.v:149540.3-149558.6" - process $proc$libresoc.v:149540$7326 + attribute \src "libresoc.v:149336.3-149354.6" + process $proc$libresoc.v:149336$7326 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:149541.5-149541.29" + attribute \src "libresoc.v:149337.5-149337.29" switch \initial - attribute \src "libresoc.v:149541.9-149541.17" + attribute \src "libresoc.v:149337.9-149337.17" case 1'1 case end @@ -277333,14 +277167,14 @@ module \main$22 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:149559.3-149568.6" - process $proc$libresoc.v:149559$7327 + attribute \src "libresoc.v:149355.3-149364.6" + process $proc$libresoc.v:149355$7327 assign { } { } assign { } { } assign $0\fast2$11[63:0]$7328 $1\fast2$11[63:0]$7329 - attribute \src "libresoc.v:149560.5-149560.29" + attribute \src "libresoc.v:149356.5-149356.29" switch \initial - attribute \src "libresoc.v:149560.9-149560.17" + attribute \src "libresoc.v:149356.9-149356.17" case 1'1 case end @@ -277356,14 +277190,14 @@ module \main$22 sync always update \fast2$11 $0\fast2$11[63:0]$7328 end - attribute \src "libresoc.v:149569.3-149578.6" - process $proc$libresoc.v:149569$7330 + attribute \src "libresoc.v:149365.3-149374.6" + process $proc$libresoc.v:149365$7330 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:149570.5-149570.29" + attribute \src "libresoc.v:149366.5-149366.29" switch \initial - attribute \src "libresoc.v:149570.9-149570.17" + attribute \src "libresoc.v:149366.9-149366.17" case 1'1 case end @@ -277379,14 +277213,14 @@ module \main$22 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:149579.3-149593.6" - process $proc$libresoc.v:149579$7331 + attribute \src "libresoc.v:149375.3-149389.6" + process $proc$libresoc.v:149375$7331 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:149580.5-149580.29" + attribute \src "libresoc.v:149376.5-149376.29" switch \initial - attribute \src "libresoc.v:149580.9-149580.17" + attribute \src "libresoc.v:149376.9-149376.17" case 1'1 case end @@ -277414,14 +277248,14 @@ module \main$22 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:149594.3-149606.6" - process $proc$libresoc.v:149594$7332 + attribute \src "libresoc.v:149390.3-149402.6" + process $proc$libresoc.v:149390$7332 assign { } { } assign { } { } assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "libresoc.v:149595.5-149595.29" + attribute \src "libresoc.v:149391.5-149391.29" switch \initial - attribute \src "libresoc.v:149595.9-149595.17" + attribute \src "libresoc.v:149391.9-149391.17" case 1'1 case end @@ -277438,14 +277272,14 @@ module \main$22 sync always update \ctr_write $0\ctr_write[0:0] end - attribute \src "libresoc.v:149607.3-149630.6" - process $proc$libresoc.v:149607$7333 + attribute \src "libresoc.v:149403.3-149426.6" + process $proc$libresoc.v:149403$7333 assign { } { } assign { } { } assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "libresoc.v:149608.5-149608.29" + attribute \src "libresoc.v:149404.5-149404.29" switch \initial - attribute \src "libresoc.v:149608.9-149608.17" + attribute \src "libresoc.v:149404.9-149404.17" case 1'1 case end @@ -277480,14 +277314,14 @@ module \main$22 sync always update \bc_taken $0\bc_taken[0:0] end - attribute \src "libresoc.v:149631.3-149643.6" - process $proc$libresoc.v:149631$7334 + attribute \src "libresoc.v:149427.3-149439.6" + process $proc$libresoc.v:149427$7334 assign { } { } assign { } { } assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "libresoc.v:149632.5-149632.29" + attribute \src "libresoc.v:149428.5-149428.29" switch \initial - attribute \src "libresoc.v:149632.9-149632.17" + attribute \src "libresoc.v:149428.9-149428.17" case 1'1 case end @@ -277504,14 +277338,14 @@ module \main$22 sync always update \ctr_n $0\ctr_n[63:0] end - attribute \src "libresoc.v:149644.3-149656.6" - process $proc$libresoc.v:149644$7335 + attribute \src "libresoc.v:149440.3-149452.6" + process $proc$libresoc.v:149440$7335 assign { } { } assign { } { } assign $0\fast1$10[63:0]$7336 $1\fast1$10[63:0]$7337 - attribute \src "libresoc.v:149645.5-149645.29" + attribute \src "libresoc.v:149441.5-149441.29" switch \initial - attribute \src "libresoc.v:149645.9-149645.17" + attribute \src "libresoc.v:149441.9-149441.17" case 1'1 case end @@ -277528,14 +277362,14 @@ module \main$22 sync always update \fast1$10 $0\fast1$10[63:0]$7336 end - attribute \src "libresoc.v:149657.3-149677.6" - process $proc$libresoc.v:149657$7338 + attribute \src "libresoc.v:149453.3-149473.6" + process $proc$libresoc.v:149453$7338 assign { } { } assign { } { } assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "libresoc.v:149658.5-149658.29" + attribute \src "libresoc.v:149454.5-149454.29" switch \initial - attribute \src "libresoc.v:149658.9-149658.17" + attribute \src "libresoc.v:149454.9-149454.17" case 1'1 case end @@ -277563,14 +277397,14 @@ module \main$22 sync always update \ctr_m $0\ctr_m[63:0] end - attribute \src "libresoc.v:149678.3-149690.6" - process $proc$libresoc.v:149678$7339 + attribute \src "libresoc.v:149474.3-149486.6" + process $proc$libresoc.v:149474$7339 assign { } { } assign { } { } assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149679.5-149679.29" + attribute \src "libresoc.v:149475.5-149475.29" switch \initial - attribute \src "libresoc.v:149679.9-149679.17" + attribute \src "libresoc.v:149475.9-149475.17" case 1'1 case end @@ -277587,24 +277421,24 @@ module \main$22 sync always update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] end - connect \$12 $eq$libresoc.v:149464$7304_Y - connect \$14 $or$libresoc.v:149465$7305_Y - connect \$17 $add$libresoc.v:149466$7306_Y - connect \$19 $eq$libresoc.v:149467$7307_Y - connect \$21 $or$libresoc.v:149468$7308_Y - connect \$23 $eq$libresoc.v:149469$7309_Y - connect \$25 $eq$libresoc.v:149470$7310_Y - connect \$27 $eq$libresoc.v:149471$7311_Y - connect \$29 $not$libresoc.v:149472$7312_Y - connect \$31 $and$libresoc.v:149473$7313_Y - connect \$33 $and$libresoc.v:149474$7314_Y - connect \$36 $sub$libresoc.v:149475$7315_Y - connect \$38 $pos$libresoc.v:149476$7317_Y - connect \$40 $reduce_or$libresoc.v:149477$7318_Y - connect \$42 $xor$libresoc.v:149478$7319_Y - connect \$44 $not$libresoc.v:149479$7320_Y - connect \$46 $and$libresoc.v:149480$7321_Y - connect \$49 $add$libresoc.v:149481$7322_Y + connect \$12 $eq$libresoc.v:149260$7304_Y + connect \$14 $or$libresoc.v:149261$7305_Y + connect \$17 $add$libresoc.v:149262$7306_Y + connect \$19 $eq$libresoc.v:149263$7307_Y + connect \$21 $or$libresoc.v:149264$7308_Y + connect \$23 $eq$libresoc.v:149265$7309_Y + connect \$25 $eq$libresoc.v:149266$7310_Y + connect \$27 $eq$libresoc.v:149267$7311_Y + connect \$29 $not$libresoc.v:149268$7312_Y + connect \$31 $and$libresoc.v:149269$7313_Y + connect \$33 $and$libresoc.v:149270$7314_Y + connect \$36 $sub$libresoc.v:149271$7315_Y + connect \$38 $pos$libresoc.v:149272$7317_Y + connect \$40 $reduce_or$libresoc.v:149273$7318_Y + connect \$42 $xor$libresoc.v:149274$7319_Y + connect \$44 $not$libresoc.v:149275$7320_Y + connect \$46 $and$libresoc.v:149276$7321_Y + connect \$49 $add$libresoc.v:149277$7322_Y connect \$16 \$17 connect \$35 \$36 connect \$48 \$49 @@ -277615,279 +277449,279 @@ module \main$22 connect \bi \br_op__insn [17:16] connect \bo \br_op__insn [25:21] end -attribute \src "libresoc.v:149704.1-150654.10" +attribute \src "libresoc.v:149500.1-150450.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" attribute \generator "nMigen" module \main$38 - attribute \src "libresoc.v:150619.3-150630.6" + attribute \src "libresoc.v:150415.3-150426.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:150117.3-150128.6" + attribute \src "libresoc.v:149913.3-149924.6" wire width 64 $0\a_s[63:0] - attribute \src "libresoc.v:150631.3-150642.6" + attribute \src "libresoc.v:150427.3-150438.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:150400.3-150411.6" + attribute \src "libresoc.v:150196.3-150207.6" wire width 64 $0\b_s[63:0] - attribute \src "libresoc.v:150193.3-150224.6" + attribute \src "libresoc.v:149989.3-150020.6" wire width 64 $0\fast1$11[63:0]$7386 - attribute \src "libresoc.v:150225.3-150256.6" + attribute \src "libresoc.v:150021.3-150052.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:150257.3-150339.6" + attribute \src "libresoc.v:150053.3-150135.6" wire width 64 $0\fast2$12[63:0]$7391 - attribute \src "libresoc.v:150340.3-150371.6" + attribute \src "libresoc.v:150136.3-150167.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:149705.7-149705.20" + attribute \src "libresoc.v:149501.7-149501.20" wire $0\initial[0:0] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:150129.3-150160.6" + attribute \src "libresoc.v:149925.3-149956.6" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:150161.3-150192.6" + attribute \src "libresoc.v:149957.3-149988.6" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:150581.3-150599.6" + attribute \src "libresoc.v:150377.3-150395.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:150600.3-150618.6" + attribute \src "libresoc.v:150396.3-150414.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$60[0:0]$7405 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$61[0:0]$7406 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$62[0:0]$7407 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$67[0:0]$7408 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$68[0:0]$7409 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$69[0:0]$7410 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$70[0:0]$7411 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal[0:0]$7404 - attribute \src "libresoc.v:150257.3-150339.6" + attribute \src "libresoc.v:150053.3-150135.6" wire $10\fast2$12[19:19]$7401 - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 2 $10\msr[5:4] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire $11\msr[15:15] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire $12\msr[12:12] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire $13\msr[60:60] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire $14\msr[12:12] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire $15\msr[12:12] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 2 $16\msr[5:4] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire $17\msr[15:15] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 3 $18\msr[34:32] - attribute \src "libresoc.v:150619.3-150630.6" + attribute \src "libresoc.v:150415.3-150426.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:150117.3-150128.6" + attribute \src "libresoc.v:149913.3-149924.6" wire width 64 $1\a_s[63:0] - attribute \src "libresoc.v:150631.3-150642.6" + attribute \src "libresoc.v:150427.3-150438.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:150400.3-150411.6" + attribute \src "libresoc.v:150196.3-150207.6" wire width 64 $1\b_s[63:0] - attribute \src "libresoc.v:150193.3-150224.6" + attribute \src "libresoc.v:149989.3-150020.6" wire width 64 $1\fast1$11[63:0]$7387 - attribute \src "libresoc.v:150225.3-150256.6" + attribute \src "libresoc.v:150021.3-150052.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:150257.3-150339.6" + attribute \src "libresoc.v:150053.3-150135.6" wire width 64 $1\fast2$12[63:0]$7392 - attribute \src "libresoc.v:150340.3-150371.6" + attribute \src "libresoc.v:150136.3-150167.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:150129.3-150160.6" + attribute \src "libresoc.v:149925.3-149956.6" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:150161.3-150192.6" + attribute \src "libresoc.v:149957.3-149988.6" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:150581.3-150599.6" + attribute \src "libresoc.v:150377.3-150395.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:150600.3-150618.6" + attribute \src "libresoc.v:150396.3-150414.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$60[0:0]$7413 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$61[0:0]$7414 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$62[0:0]$7415 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$67[0:0]$7416 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$68[0:0]$7417 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$69[0:0]$7418 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$70[0:0]$7419 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal[0:0]$7412 - attribute \src "libresoc.v:150193.3-150224.6" + attribute \src "libresoc.v:149989.3-150020.6" wire width 64 $2\fast1$11[63:0]$7388 - attribute \src "libresoc.v:150225.3-150256.6" + attribute \src "libresoc.v:150021.3-150052.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:150257.3-150339.6" + attribute \src "libresoc.v:150053.3-150135.6" wire width 64 $2\fast2$12[63:0]$7393 - attribute \src "libresoc.v:150340.3-150371.6" + attribute \src "libresoc.v:150136.3-150167.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire $2\msr_ok[0:0] - attribute \src "libresoc.v:150129.3-150160.6" + attribute \src "libresoc.v:149925.3-149956.6" wire width 64 $2\nia[63:0] - attribute \src "libresoc.v:150161.3-150192.6" + attribute \src "libresoc.v:149957.3-149988.6" wire $2\nia_ok[0:0] - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$60[0:0]$7421 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$61[0:0]$7422 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$62[0:0]$7423 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$67[0:0]$7424 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$68[0:0]$7425 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$69[0:0]$7426 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$70[0:0]$7427 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal[0:0]$7420 - attribute \src "libresoc.v:150257.3-150339.6" + attribute \src "libresoc.v:150053.3-150135.6" wire $3\fast2$12[17:17]$7394 - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 11 $3\msr[11:1] - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$60[0:0]$7429 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$61[0:0]$7430 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$62[0:0]$7431 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$67[0:0]$7432 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$68[0:0]$7433 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$69[0:0]$7434 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$70[0:0]$7435 - attribute \src "libresoc.v:150372.3-150399.6" + attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal[0:0]$7428 - attribute \src "libresoc.v:150257.3-150339.6" + attribute \src "libresoc.v:150053.3-150135.6" wire $4\fast2$12[18:18]$7395 - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 47 $4\msr[59:13] - attribute \src "libresoc.v:150257.3-150339.6" + attribute \src "libresoc.v:150053.3-150135.6" wire $5\fast2$12[20:20]$7396 - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 3 $5\msr[63:61] - attribute \src "libresoc.v:150257.3-150339.6" + attribute \src "libresoc.v:150053.3-150135.6" wire $6\fast2$12[16:16]$7397 - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 11 $6\msr[11:1] - attribute \src "libresoc.v:150257.3-150339.6" + attribute \src "libresoc.v:150053.3-150135.6" wire width 2 $7\fast2$12[19:18]$7398 - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 47 $7\msr[59:13] - attribute \src "libresoc.v:150257.3-150339.6" + attribute \src "libresoc.v:150053.3-150135.6" wire $8\fast2$12[28:28]$7399 - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 3 $8\msr[63:61] - attribute \src "libresoc.v:150257.3-150339.6" + attribute \src "libresoc.v:150053.3-150135.6" wire $9\fast2$12[30:30]$7400 - attribute \src "libresoc.v:150412.3-150580.6" + attribute \src "libresoc.v:150208.3-150376.6" wire width 3 $9\msr[34:32] - attribute \src "libresoc.v:150093.18-150093.113" - wire width 65 $add$libresoc.v:150093$7357_Y - attribute \src "libresoc.v:150087.18-150087.108" - wire width 5 $and$libresoc.v:150087$7350_Y - attribute \src "libresoc.v:150095.18-150095.118" - wire width 8 $and$libresoc.v:150095$7359_Y - attribute \src "libresoc.v:150097.18-150097.118" - wire width 8 $and$libresoc.v:150097$7361_Y - attribute \src "libresoc.v:150099.18-150099.118" - wire width 8 $and$libresoc.v:150099$7363_Y - attribute \src "libresoc.v:150101.18-150101.119" - wire width 8 $and$libresoc.v:150101$7365_Y - attribute \src "libresoc.v:150103.18-150103.119" - wire width 8 $and$libresoc.v:150103$7367_Y - attribute \src "libresoc.v:150105.18-150105.119" - wire width 8 $and$libresoc.v:150105$7369_Y - attribute \src "libresoc.v:150111.18-150111.106" - wire $and$libresoc.v:150111$7376_Y - attribute \src "libresoc.v:150116.18-150116.106" - wire $and$libresoc.v:150116$7381_Y - attribute \src "libresoc.v:150086.18-150086.100" - wire $eq$libresoc.v:150086$7349_Y - attribute \src "libresoc.v:150094.18-150094.119" - wire $eq$libresoc.v:150094$7358_Y - attribute \src "libresoc.v:150108.18-150108.121" - wire $eq$libresoc.v:150108$7373_Y - attribute \src "libresoc.v:150109.18-150109.121" - wire $eq$libresoc.v:150109$7374_Y - attribute \src "libresoc.v:150110.18-150110.111" - wire $eq$libresoc.v:150110$7375_Y - attribute \src "libresoc.v:150114.18-150114.121" - wire $eq$libresoc.v:150114$7379_Y - attribute \src "libresoc.v:150115.18-150115.114" - wire $eq$libresoc.v:150115$7380_Y - attribute \src "libresoc.v:150080.18-150080.95" - wire width 64 $extend$libresoc.v:150080$7341_Y - attribute \src "libresoc.v:150081.18-150081.95" - wire width 64 $extend$libresoc.v:150081$7343_Y - attribute \src "libresoc.v:150092.18-150092.100" - wire width 64 $extend$libresoc.v:150092$7355_Y - attribute \src "libresoc.v:150107.18-150107.109" - wire width 65 $extend$libresoc.v:150107$7371_Y - attribute \src "libresoc.v:150083.18-150083.121" - wire $gt$libresoc.v:150083$7346_Y - attribute \src "libresoc.v:150085.18-150085.99" - wire $gt$libresoc.v:150085$7348_Y - attribute \src "libresoc.v:150082.18-150082.121" - wire $lt$libresoc.v:150082$7345_Y - attribute \src "libresoc.v:150084.18-150084.99" - wire $lt$libresoc.v:150084$7347_Y - attribute \src "libresoc.v:150112.18-150112.112" - wire $not$libresoc.v:150112$7377_Y - attribute \src "libresoc.v:150113.18-150113.112" - wire $not$libresoc.v:150113$7378_Y - attribute \src "libresoc.v:150090.18-150090.106" - wire $or$libresoc.v:150090$7353_Y - attribute \src "libresoc.v:150080.18-150080.95" - wire width 64 $pos$libresoc.v:150080$7342_Y - attribute \src "libresoc.v:150081.18-150081.95" - wire width 64 $pos$libresoc.v:150081$7344_Y - attribute \src "libresoc.v:150092.18-150092.100" - wire width 64 $pos$libresoc.v:150092$7356_Y - attribute \src "libresoc.v:150107.18-150107.109" - wire width 65 $pos$libresoc.v:150107$7372_Y - attribute \src "libresoc.v:150088.18-150088.100" - wire $reduce_or$libresoc.v:150088$7351_Y - attribute \src "libresoc.v:150089.18-150089.113" - wire $reduce_or$libresoc.v:150089$7352_Y - attribute \src "libresoc.v:150096.18-150096.91" - wire $reduce_or$libresoc.v:150096$7360_Y - attribute \src "libresoc.v:150098.18-150098.91" - wire $reduce_or$libresoc.v:150098$7362_Y - attribute \src "libresoc.v:150100.18-150100.91" - wire $reduce_or$libresoc.v:150100$7364_Y - attribute \src "libresoc.v:150102.18-150102.91" - wire $reduce_or$libresoc.v:150102$7366_Y - attribute \src "libresoc.v:150104.18-150104.91" - wire $reduce_or$libresoc.v:150104$7368_Y - attribute \src "libresoc.v:150106.18-150106.91" - wire $reduce_or$libresoc.v:150106$7370_Y - attribute \src "libresoc.v:150091.18-150091.120" - wire width 20 $sshl$libresoc.v:150091$7354_Y + attribute \src "libresoc.v:149889.18-149889.113" + wire width 65 $add$libresoc.v:149889$7357_Y + attribute \src "libresoc.v:149883.18-149883.108" + wire width 5 $and$libresoc.v:149883$7350_Y + attribute \src "libresoc.v:149891.18-149891.118" + wire width 8 $and$libresoc.v:149891$7359_Y + attribute \src "libresoc.v:149893.18-149893.118" + wire width 8 $and$libresoc.v:149893$7361_Y + attribute \src "libresoc.v:149895.18-149895.118" + wire width 8 $and$libresoc.v:149895$7363_Y + attribute \src "libresoc.v:149897.18-149897.119" + wire width 8 $and$libresoc.v:149897$7365_Y + attribute \src "libresoc.v:149899.18-149899.119" + wire width 8 $and$libresoc.v:149899$7367_Y + attribute \src "libresoc.v:149901.18-149901.119" + wire width 8 $and$libresoc.v:149901$7369_Y + attribute \src "libresoc.v:149907.18-149907.106" + wire $and$libresoc.v:149907$7376_Y + attribute \src "libresoc.v:149912.18-149912.106" + wire $and$libresoc.v:149912$7381_Y + attribute \src "libresoc.v:149882.18-149882.100" + wire $eq$libresoc.v:149882$7349_Y + attribute \src "libresoc.v:149890.18-149890.119" + wire $eq$libresoc.v:149890$7358_Y + attribute \src "libresoc.v:149904.18-149904.121" + wire $eq$libresoc.v:149904$7373_Y + attribute \src "libresoc.v:149905.18-149905.121" + wire $eq$libresoc.v:149905$7374_Y + attribute \src "libresoc.v:149906.18-149906.111" + wire $eq$libresoc.v:149906$7375_Y + attribute \src "libresoc.v:149910.18-149910.121" + wire $eq$libresoc.v:149910$7379_Y + attribute \src "libresoc.v:149911.18-149911.114" + wire $eq$libresoc.v:149911$7380_Y + attribute \src "libresoc.v:149876.18-149876.95" + wire width 64 $extend$libresoc.v:149876$7341_Y + attribute \src "libresoc.v:149877.18-149877.95" + wire width 64 $extend$libresoc.v:149877$7343_Y + attribute \src "libresoc.v:149888.18-149888.100" + wire width 64 $extend$libresoc.v:149888$7355_Y + attribute \src "libresoc.v:149903.18-149903.109" + wire width 65 $extend$libresoc.v:149903$7371_Y + attribute \src "libresoc.v:149879.18-149879.121" + wire $gt$libresoc.v:149879$7346_Y + attribute \src "libresoc.v:149881.18-149881.99" + wire $gt$libresoc.v:149881$7348_Y + attribute \src "libresoc.v:149878.18-149878.121" + wire $lt$libresoc.v:149878$7345_Y + attribute \src "libresoc.v:149880.18-149880.99" + wire $lt$libresoc.v:149880$7347_Y + attribute \src "libresoc.v:149908.18-149908.112" + wire $not$libresoc.v:149908$7377_Y + attribute \src "libresoc.v:149909.18-149909.112" + wire $not$libresoc.v:149909$7378_Y + attribute \src "libresoc.v:149886.18-149886.106" + wire $or$libresoc.v:149886$7353_Y + attribute \src "libresoc.v:149876.18-149876.95" + wire width 64 $pos$libresoc.v:149876$7342_Y + attribute \src "libresoc.v:149877.18-149877.95" + wire width 64 $pos$libresoc.v:149877$7344_Y + attribute \src "libresoc.v:149888.18-149888.100" + wire width 64 $pos$libresoc.v:149888$7356_Y + attribute \src "libresoc.v:149903.18-149903.109" + wire width 65 $pos$libresoc.v:149903$7372_Y + attribute \src "libresoc.v:149884.18-149884.100" + wire $reduce_or$libresoc.v:149884$7351_Y + attribute \src "libresoc.v:149885.18-149885.113" + wire $reduce_or$libresoc.v:149885$7352_Y + attribute \src "libresoc.v:149892.18-149892.91" + wire $reduce_or$libresoc.v:149892$7360_Y + attribute \src "libresoc.v:149894.18-149894.91" + wire $reduce_or$libresoc.v:149894$7362_Y + attribute \src "libresoc.v:149896.18-149896.91" + wire $reduce_or$libresoc.v:149896$7364_Y + attribute \src "libresoc.v:149898.18-149898.91" + wire $reduce_or$libresoc.v:149898$7366_Y + attribute \src "libresoc.v:149900.18-149900.91" + wire $reduce_or$libresoc.v:149900$7368_Y + attribute \src "libresoc.v:149902.18-149902.91" + wire $reduce_or$libresoc.v:149902$7370_Y + attribute \src "libresoc.v:149887.18-149887.120" + wire width 20 $sshl$libresoc.v:149887$7354_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 \$13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" @@ -277990,7 +277824,7 @@ module \main$38 wire \gt_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" wire \gt_u - attribute \src "libresoc.v:149705.7-149705.15" + attribute \src "libresoc.v:149501.7-149501.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" wire \lt_s @@ -278255,7 +278089,7 @@ module \main$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" - cell $add $add$libresoc.v:150093$7357 + cell $add $add$libresoc.v:149889$7357 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -278263,10 +278097,10 @@ module \main$38 parameter \Y_WIDTH 65 connect \A \trap_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:150093$7357_Y + connect \Y $add$libresoc.v:149889$7357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $and $and$libresoc.v:150087$7350 + cell $and $and$libresoc.v:149883$7350 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -278274,10 +278108,10 @@ module \main$38 parameter \Y_WIDTH 5 connect \A \trap_bits connect \B \to - connect \Y $and$libresoc.v:150087$7350_Y + connect \Y $and$libresoc.v:149883$7350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" - cell $and $and$libresoc.v:150095$7359 + cell $and $and$libresoc.v:149891$7359 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -278285,10 +278119,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 2'10 - connect \Y $and$libresoc.v:150095$7359_Y + connect \Y $and$libresoc.v:149891$7359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" - cell $and $and$libresoc.v:150097$7361 + cell $and $and$libresoc.v:149893$7361 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -278296,10 +278130,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 1'1 - connect \Y $and$libresoc.v:150097$7361_Y + connect \Y $and$libresoc.v:149893$7361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" - cell $and $and$libresoc.v:150099$7363 + cell $and $and$libresoc.v:149895$7363 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -278307,10 +278141,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 4'1000 - connect \Y $and$libresoc.v:150099$7363_Y + connect \Y $and$libresoc.v:149895$7363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:150101$7365 + cell $and $and$libresoc.v:149897$7365 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -278318,10 +278152,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:150101$7365_Y + connect \Y $and$libresoc.v:149897$7365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" - cell $and $and$libresoc.v:150103$7367 + cell $and $and$libresoc.v:149899$7367 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -278329,10 +278163,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 8'10000000 - connect \Y $and$libresoc.v:150103$7367_Y + connect \Y $and$libresoc.v:149899$7367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:150105$7369 + cell $and $and$libresoc.v:149901$7369 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -278340,10 +278174,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:150105$7369_Y + connect \Y $and$libresoc.v:149901$7369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $and $and$libresoc.v:150111$7376 + cell $and $and$libresoc.v:149907$7376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278351,10 +278185,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:150111$7376_Y + connect \Y $and$libresoc.v:149907$7376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $and $and$libresoc.v:150116$7381 + cell $and $and$libresoc.v:149912$7381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278362,10 +278196,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$89 connect \B \$91 - connect \Y $and$libresoc.v:150116$7381_Y + connect \Y $and$libresoc.v:149912$7381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" - cell $eq $eq$libresoc.v:150086$7349 + cell $eq $eq$libresoc.v:149882$7349 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -278373,10 +278207,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $eq$libresoc.v:150086$7349_Y + connect \Y $eq$libresoc.v:149882$7349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" - cell $eq $eq$libresoc.v:150094$7358 + cell $eq $eq$libresoc.v:149890$7358 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -278384,10 +278218,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \B 1'0 - connect \Y $eq$libresoc.v:150094$7358_Y + connect \Y $eq$libresoc.v:149890$7358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - cell $eq $eq$libresoc.v:150108$7373 + cell $eq $eq$libresoc.v:149904$7373 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -278395,10 +278229,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__insn_type connect \B 7'1001000 - connect \Y $eq$libresoc.v:150108$7373_Y + connect \Y $eq$libresoc.v:149904$7373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" - cell $eq $eq$libresoc.v:150109$7374 + cell $eq $eq$libresoc.v:149905$7374 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -278406,10 +278240,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:150109$7374_Y + connect \Y $eq$libresoc.v:149905$7374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $eq $eq$libresoc.v:150110$7375 + cell $eq $eq$libresoc.v:149906$7375 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -278417,10 +278251,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \ra [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:150110$7375_Y + connect \Y $eq$libresoc.v:149906$7375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - cell $eq $eq$libresoc.v:150114$7379 + cell $eq $eq$libresoc.v:149910$7379 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -278428,10 +278262,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:150114$7379_Y + connect \Y $eq$libresoc.v:149910$7379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $eq $eq$libresoc.v:150115$7380 + cell $eq $eq$libresoc.v:149911$7380 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -278439,42 +278273,42 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \fast2 [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:150115$7380_Y + connect \Y $eq$libresoc.v:149911$7380_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:150080$7341 + cell $pos $extend$libresoc.v:149876$7341 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \ra [31:0] - connect \Y $extend$libresoc.v:150080$7341_Y + connect \Y $extend$libresoc.v:149876$7341_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:150081$7343 + cell $pos $extend$libresoc.v:149877$7343 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \rb [31:0] - connect \Y $extend$libresoc.v:150081$7343_Y + connect \Y $extend$libresoc.v:149877$7343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $extend$libresoc.v:150092$7355 + cell $pos $extend$libresoc.v:149888$7355 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \Y_WIDTH 64 connect \A \$36 - connect \Y $extend$libresoc.v:150092$7355_Y + connect \Y $extend$libresoc.v:149888$7355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:150107$7371 + cell $pos $extend$libresoc.v:149903$7371 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \trap_op__msr - connect \Y $extend$libresoc.v:150107$7371_Y + connect \Y $extend$libresoc.v:149903$7371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $gt $gt$libresoc.v:150083$7346 + cell $gt $gt$libresoc.v:149879$7346 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -278482,10 +278316,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $gt$libresoc.v:150083$7346_Y + connect \Y $gt$libresoc.v:149879$7346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $gt $gt$libresoc.v:150085$7348 + cell $gt $gt$libresoc.v:149881$7348 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -278493,10 +278327,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $gt$libresoc.v:150085$7348_Y + connect \Y $gt$libresoc.v:149881$7348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $lt $lt$libresoc.v:150082$7345 + cell $lt $lt$libresoc.v:149878$7345 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -278504,10 +278338,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $lt$libresoc.v:150082$7345_Y + connect \Y $lt$libresoc.v:149878$7345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $lt $lt$libresoc.v:150084$7347 + cell $lt $lt$libresoc.v:149880$7347 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -278515,26 +278349,26 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $lt$libresoc.v:150084$7347_Y + connect \Y $lt$libresoc.v:149880$7347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - cell $not $not$libresoc.v:150112$7377 + cell $not $not$libresoc.v:149908$7377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__msr [60] - connect \Y $not$libresoc.v:150112$7377_Y + connect \Y $not$libresoc.v:149908$7377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - cell $not $not$libresoc.v:150113$7378 + cell $not $not$libresoc.v:149909$7378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__insn [9] - connect \Y $not$libresoc.v:150113$7378_Y + connect \Y $not$libresoc.v:149909$7378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $or $or$libresoc.v:150090$7353 + cell $or $or$libresoc.v:149886$7353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278542,106 +278376,106 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$27 connect \B \$31 - connect \Y $or$libresoc.v:150090$7353_Y + connect \Y $or$libresoc.v:149886$7353_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:150080$7342 + cell $pos $pos$libresoc.v:149876$7342 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150080$7341_Y - connect \Y $pos$libresoc.v:150080$7342_Y + connect \A $extend$libresoc.v:149876$7341_Y + connect \Y $pos$libresoc.v:149876$7342_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:150081$7344 + cell $pos $pos$libresoc.v:149877$7344 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150081$7343_Y - connect \Y $pos$libresoc.v:150081$7344_Y + connect \A $extend$libresoc.v:149877$7343_Y + connect \Y $pos$libresoc.v:149877$7344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $pos$libresoc.v:150092$7356 + cell $pos $pos$libresoc.v:149888$7356 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150092$7355_Y - connect \Y $pos$libresoc.v:150092$7356_Y + connect \A $extend$libresoc.v:149888$7355_Y + connect \Y $pos$libresoc.v:149888$7356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:150107$7372 + cell $pos $pos$libresoc.v:149903$7372 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:150107$7371_Y - connect \Y $pos$libresoc.v:150107$7372_Y + connect \A $extend$libresoc.v:149903$7371_Y + connect \Y $pos$libresoc.v:149903$7372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:150088$7351 + cell $reduce_or $reduce_or$libresoc.v:149884$7351 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $reduce_or$libresoc.v:150088$7351_Y + connect \Y $reduce_or$libresoc.v:149884$7351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:150089$7352 + cell $reduce_or $reduce_or$libresoc.v:149885$7352 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \trap_op__traptype - connect \Y $reduce_or$libresoc.v:150089$7352_Y + connect \Y $reduce_or$libresoc.v:149885$7352_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:150096$7360 + cell $reduce_or $reduce_or$libresoc.v:149892$7360 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$45 - connect \Y $reduce_or$libresoc.v:150096$7360_Y + connect \Y $reduce_or$libresoc.v:149892$7360_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:150098$7362 + cell $reduce_or $reduce_or$libresoc.v:149894$7362 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$49 - connect \Y $reduce_or$libresoc.v:150098$7362_Y + connect \Y $reduce_or$libresoc.v:149894$7362_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:150100$7364 + cell $reduce_or $reduce_or$libresoc.v:149896$7364 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$53 - connect \Y $reduce_or$libresoc.v:150100$7364_Y + connect \Y $reduce_or$libresoc.v:149896$7364_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:150102$7366 + cell $reduce_or $reduce_or$libresoc.v:149898$7366 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$57 - connect \Y $reduce_or$libresoc.v:150102$7366_Y + connect \Y $reduce_or$libresoc.v:149898$7366_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:150104$7368 + cell $reduce_or $reduce_or$libresoc.v:149900$7368 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $reduce_or$libresoc.v:150104$7368_Y + connect \Y $reduce_or$libresoc.v:149900$7368_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:150106$7370 + cell $reduce_or $reduce_or$libresoc.v:149902$7370 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$72 - connect \Y $reduce_or$libresoc.v:150106$7370_Y + connect \Y $reduce_or$libresoc.v:149902$7370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $sshl $sshl$libresoc.v:150091$7354 + cell $sshl $sshl$libresoc.v:149887$7354 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -278649,23 +278483,23 @@ module \main$38 parameter \Y_WIDTH 20 connect \A \trap_op__trapaddr connect \B 3'100 - connect \Y $sshl$libresoc.v:150091$7354_Y + connect \Y $sshl$libresoc.v:149887$7354_Y end - attribute \src "libresoc.v:149705.7-149705.20" - process $proc$libresoc.v:149705$7442 + attribute \src "libresoc.v:149501.7-149501.20" + process $proc$libresoc.v:149501$7442 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:150117.3-150128.6" - process $proc$libresoc.v:150117$7382 + attribute \src "libresoc.v:149913.3-149924.6" + process $proc$libresoc.v:149913$7382 assign { } { } assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "libresoc.v:150118.5-150118.29" + attribute \src "libresoc.v:149914.5-149914.29" switch \initial - attribute \src "libresoc.v:150118.9-150118.17" + attribute \src "libresoc.v:149914.9-149914.17" case 1'1 case end @@ -278683,14 +278517,14 @@ module \main$38 sync always update \a_s $0\a_s[63:0] end - attribute \src "libresoc.v:150129.3-150160.6" - process $proc$libresoc.v:150129$7383 + attribute \src "libresoc.v:149925.3-149956.6" + process $proc$libresoc.v:149925$7383 assign { } { } assign { } { } assign $0\nia[63:0] $1\nia[63:0] - attribute \src "libresoc.v:150130.5-150130.29" + attribute \src "libresoc.v:149926.5-149926.29" switch \initial - attribute \src "libresoc.v:150130.9-150130.17" + attribute \src "libresoc.v:149926.9-149926.17" case 1'1 case end @@ -278729,14 +278563,14 @@ module \main$38 sync always update \nia $0\nia[63:0] end - attribute \src "libresoc.v:150161.3-150192.6" - process $proc$libresoc.v:150161$7384 + attribute \src "libresoc.v:149957.3-149988.6" + process $proc$libresoc.v:149957$7384 assign { } { } assign { } { } assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "libresoc.v:150162.5-150162.29" + attribute \src "libresoc.v:149958.5-149958.29" switch \initial - attribute \src "libresoc.v:150162.9-150162.17" + attribute \src "libresoc.v:149958.9-149958.17" case 1'1 case end @@ -278775,14 +278609,14 @@ module \main$38 sync always update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:150193.3-150224.6" - process $proc$libresoc.v:150193$7385 + attribute \src "libresoc.v:149989.3-150020.6" + process $proc$libresoc.v:149989$7385 assign { } { } assign { } { } assign $0\fast1$11[63:0]$7386 $1\fast1$11[63:0]$7387 - attribute \src "libresoc.v:150194.5-150194.29" + attribute \src "libresoc.v:149990.5-149990.29" switch \initial - attribute \src "libresoc.v:150194.9-150194.17" + attribute \src "libresoc.v:149990.9-149990.17" case 1'1 case end @@ -278820,14 +278654,14 @@ module \main$38 sync always update \fast1$11 $0\fast1$11[63:0]$7386 end - attribute \src "libresoc.v:150225.3-150256.6" - process $proc$libresoc.v:150225$7389 + attribute \src "libresoc.v:150021.3-150052.6" + process $proc$libresoc.v:150021$7389 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:150226.5-150226.29" + attribute \src "libresoc.v:150022.5-150022.29" switch \initial - attribute \src "libresoc.v:150226.9-150226.17" + attribute \src "libresoc.v:150022.9-150022.17" case 1'1 case end @@ -278865,14 +278699,14 @@ module \main$38 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:150257.3-150339.6" - process $proc$libresoc.v:150257$7390 + attribute \src "libresoc.v:150053.3-150135.6" + process $proc$libresoc.v:150053$7390 assign { } { } assign { } { } assign $0\fast2$12[63:0]$7391 $1\fast2$12[63:0]$7392 - attribute \src "libresoc.v:150258.5-150258.29" + attribute \src "libresoc.v:150054.5-150054.29" switch \initial - attribute \src "libresoc.v:150258.9-150258.17" + attribute \src "libresoc.v:150054.9-150054.17" case 1'1 case end @@ -278985,14 +278819,14 @@ module \main$38 sync always update \fast2$12 $0\fast2$12[63:0]$7391 end - attribute \src "libresoc.v:150340.3-150371.6" - process $proc$libresoc.v:150340$7402 + attribute \src "libresoc.v:150136.3-150167.6" + process $proc$libresoc.v:150136$7402 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:150341.5-150341.29" + attribute \src "libresoc.v:150137.5-150137.29" switch \initial - attribute \src "libresoc.v:150341.9-150341.17" + attribute \src "libresoc.v:150137.9-150137.17" case 1'1 case end @@ -279030,8 +278864,8 @@ module \main$38 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:150372.3-150399.6" - process $proc$libresoc.v:150372$7403 + attribute \src "libresoc.v:150168.3-150195.6" + process $proc$libresoc.v:150168$7403 assign { } { } assign { } { } assign { } { } @@ -279056,9 +278890,9 @@ module \main$38 assign $0\trapexc_$signal$68[0:0]$7409 $1\trapexc_$signal$68[0:0]$7417 assign $0\trapexc_$signal$69[0:0]$7410 $1\trapexc_$signal$69[0:0]$7418 assign $0\trapexc_$signal$70[0:0]$7411 $1\trapexc_$signal$70[0:0]$7419 - attribute \src "libresoc.v:150373.5-150373.29" + attribute \src "libresoc.v:150169.5-150169.29" switch \initial - attribute \src "libresoc.v:150373.9-150373.17" + attribute \src "libresoc.v:150169.9-150169.17" case 1'1 case end @@ -279155,13 +278989,13 @@ module \main$38 update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7410 update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7411 end - attribute \src "libresoc.v:150400.3-150411.6" - process $proc$libresoc.v:150400$7436 + attribute \src "libresoc.v:150196.3-150207.6" + process $proc$libresoc.v:150196$7436 assign { } { } assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "libresoc.v:150401.5-150401.29" + attribute \src "libresoc.v:150197.5-150197.29" switch \initial - attribute \src "libresoc.v:150401.9-150401.17" + attribute \src "libresoc.v:150197.9-150197.17" case 1'1 case end @@ -279179,17 +279013,17 @@ module \main$38 sync always update \b_s $0\b_s[63:0] end - attribute \src "libresoc.v:150412.3-150580.6" - process $proc$libresoc.v:150412$7437 + attribute \src "libresoc.v:150208.3-150376.6" + process $proc$libresoc.v:150208$7437 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\msr[63:0] $1\msr[63:0] assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "libresoc.v:150413.5-150413.29" + attribute \src "libresoc.v:150209.5-150209.29" switch \initial - attribute \src "libresoc.v:150413.9-150413.17" + attribute \src "libresoc.v:150209.9-150209.17" case 1'1 case end @@ -279403,14 +279237,14 @@ module \main$38 update \msr $0\msr[63:0] update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:150581.3-150599.6" - process $proc$libresoc.v:150581$7438 + attribute \src "libresoc.v:150377.3-150395.6" + process $proc$libresoc.v:150377$7438 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:150582.5-150582.29" + attribute \src "libresoc.v:150378.5-150378.29" switch \initial - attribute \src "libresoc.v:150582.9-150582.17" + attribute \src "libresoc.v:150378.9-150378.17" case 1'1 case end @@ -279432,14 +279266,14 @@ module \main$38 sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:150600.3-150618.6" - process $proc$libresoc.v:150600$7439 + attribute \src "libresoc.v:150396.3-150414.6" + process $proc$libresoc.v:150396$7439 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:150601.5-150601.29" + attribute \src "libresoc.v:150397.5-150397.29" switch \initial - attribute \src "libresoc.v:150601.9-150601.17" + attribute \src "libresoc.v:150397.9-150397.17" case 1'1 case end @@ -279461,13 +279295,13 @@ module \main$38 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:150619.3-150630.6" - process $proc$libresoc.v:150619$7440 + attribute \src "libresoc.v:150415.3-150426.6" + process $proc$libresoc.v:150415$7440 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:150620.5-150620.29" + attribute \src "libresoc.v:150416.5-150416.29" switch \initial - attribute \src "libresoc.v:150620.9-150620.17" + attribute \src "libresoc.v:150416.9-150416.17" case 1'1 case end @@ -279485,13 +279319,13 @@ module \main$38 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:150631.3-150642.6" - process $proc$libresoc.v:150631$7441 + attribute \src "libresoc.v:150427.3-150438.6" + process $proc$libresoc.v:150427$7441 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:150632.5-150632.29" + attribute \src "libresoc.v:150428.5-150428.29" switch \initial - attribute \src "libresoc.v:150632.9-150632.17" + attribute \src "libresoc.v:150428.9-150428.17" case 1'1 case end @@ -279509,43 +279343,43 @@ module \main$38 sync always update \b $0\b[63:0] end - connect \$13 $pos$libresoc.v:150080$7342_Y - connect \$15 $pos$libresoc.v:150081$7344_Y - connect \$17 $lt$libresoc.v:150082$7345_Y - connect \$19 $gt$libresoc.v:150083$7346_Y - connect \$21 $lt$libresoc.v:150084$7347_Y - connect \$23 $gt$libresoc.v:150085$7348_Y - connect \$25 $eq$libresoc.v:150086$7349_Y - connect \$28 $and$libresoc.v:150087$7350_Y - connect \$27 $reduce_or$libresoc.v:150088$7351_Y - connect \$31 $reduce_or$libresoc.v:150089$7352_Y - connect \$33 $or$libresoc.v:150090$7353_Y - connect \$36 $sshl$libresoc.v:150091$7354_Y - connect \$35 $pos$libresoc.v:150092$7356_Y - connect \$40 $add$libresoc.v:150093$7357_Y - connect \$42 $eq$libresoc.v:150094$7358_Y - connect \$45 $and$libresoc.v:150095$7359_Y - connect \$44 $reduce_or$libresoc.v:150096$7360_Y - connect \$49 $and$libresoc.v:150097$7361_Y - connect \$48 $reduce_or$libresoc.v:150098$7362_Y - connect \$53 $and$libresoc.v:150099$7363_Y - connect \$52 $reduce_or$libresoc.v:150100$7364_Y - connect \$57 $and$libresoc.v:150101$7365_Y - connect \$56 $reduce_or$libresoc.v:150102$7366_Y - connect \$64 $and$libresoc.v:150103$7367_Y - connect \$63 $reduce_or$libresoc.v:150104$7368_Y - connect \$72 $and$libresoc.v:150105$7369_Y - connect \$71 $reduce_or$libresoc.v:150106$7370_Y - connect \$75 $pos$libresoc.v:150107$7372_Y - connect \$77 $eq$libresoc.v:150108$7373_Y - connect \$79 $eq$libresoc.v:150109$7374_Y - connect \$81 $eq$libresoc.v:150110$7375_Y - connect \$83 $and$libresoc.v:150111$7376_Y - connect \$85 $not$libresoc.v:150112$7377_Y - connect \$87 $not$libresoc.v:150113$7378_Y - connect \$89 $eq$libresoc.v:150114$7379_Y - connect \$91 $eq$libresoc.v:150115$7380_Y - connect \$93 $and$libresoc.v:150116$7381_Y + connect \$13 $pos$libresoc.v:149876$7342_Y + connect \$15 $pos$libresoc.v:149877$7344_Y + connect \$17 $lt$libresoc.v:149878$7345_Y + connect \$19 $gt$libresoc.v:149879$7346_Y + connect \$21 $lt$libresoc.v:149880$7347_Y + connect \$23 $gt$libresoc.v:149881$7348_Y + connect \$25 $eq$libresoc.v:149882$7349_Y + connect \$28 $and$libresoc.v:149883$7350_Y + connect \$27 $reduce_or$libresoc.v:149884$7351_Y + connect \$31 $reduce_or$libresoc.v:149885$7352_Y + connect \$33 $or$libresoc.v:149886$7353_Y + connect \$36 $sshl$libresoc.v:149887$7354_Y + connect \$35 $pos$libresoc.v:149888$7356_Y + connect \$40 $add$libresoc.v:149889$7357_Y + connect \$42 $eq$libresoc.v:149890$7358_Y + connect \$45 $and$libresoc.v:149891$7359_Y + connect \$44 $reduce_or$libresoc.v:149892$7360_Y + connect \$49 $and$libresoc.v:149893$7361_Y + connect \$48 $reduce_or$libresoc.v:149894$7362_Y + connect \$53 $and$libresoc.v:149895$7363_Y + connect \$52 $reduce_or$libresoc.v:149896$7364_Y + connect \$57 $and$libresoc.v:149897$7365_Y + connect \$56 $reduce_or$libresoc.v:149898$7366_Y + connect \$64 $and$libresoc.v:149899$7367_Y + connect \$63 $reduce_or$libresoc.v:149900$7368_Y + connect \$72 $and$libresoc.v:149901$7369_Y + connect \$71 $reduce_or$libresoc.v:149902$7370_Y + connect \$75 $pos$libresoc.v:149903$7372_Y + connect \$77 $eq$libresoc.v:149904$7373_Y + connect \$79 $eq$libresoc.v:149905$7374_Y + connect \$81 $eq$libresoc.v:149906$7375_Y + connect \$83 $and$libresoc.v:149907$7376_Y + connect \$85 $not$libresoc.v:149908$7377_Y + connect \$87 $not$libresoc.v:149909$7378_Y + connect \$89 $eq$libresoc.v:149910$7379_Y + connect \$91 $eq$libresoc.v:149911$7380_Y + connect \$93 $and$libresoc.v:149912$7381_Y connect \$39 \$40 connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid @@ -279558,239 +279392,239 @@ module \main$38 connect \lt_s \$17 connect \to \trap_op__insn [25:21] end -attribute \src "libresoc.v:150658.1-151647.10" +attribute \src "libresoc.v:150454.1-151443.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" attribute \generator "nMigen" module \main$51 - attribute \src "libresoc.v:151566.3-151600.6" + attribute \src "libresoc.v:151362.3-151396.6" wire width 32 $0\a32[31:0] - attribute \src "libresoc.v:151415.3-151441.6" + attribute \src "libresoc.v:151211.3-151237.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:151349.3-151387.6" + attribute \src "libresoc.v:151145.3-151183.6" wire width 64 $0\bpermd_rb[63:0] - attribute \src "libresoc.v:151310.3-151348.6" + attribute \src "libresoc.v:151106.3-151144.6" wire width 64 $0\bpermd_rs[63:0] - attribute \src "libresoc.v:151275.3-151309.6" + attribute \src "libresoc.v:151071.3-151105.6" wire width 64 $0\clz_sig_in[63:0] - attribute \src "libresoc.v:151601.3-151643.6" + attribute \src "libresoc.v:151397.3-151439.6" wire width 64 $0\cntz_i[63:0] - attribute \src "libresoc.v:151531.3-151565.6" + attribute \src "libresoc.v:151327.3-151361.6" wire $0\count_right[0:0] - attribute \src "libresoc.v:150659.7-150659.20" + attribute \src "libresoc.v:150455.7-150455.20" wire $0\initial[0:0] - attribute \src "libresoc.v:151220.3-151274.6" + attribute \src "libresoc.v:151016.3-151070.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:151220.3-151274.6" + attribute \src "libresoc.v:151016.3-151070.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:151469.3-151499.6" + attribute \src "libresoc.v:151265.3-151295.6" wire $0\par0[0:0] - attribute \src "libresoc.v:151500.3-151530.6" + attribute \src "libresoc.v:151296.3-151326.6" wire $0\par1[0:0] - attribute \src "libresoc.v:151388.3-151414.6" + attribute \src "libresoc.v:151184.3-151210.6" wire width 64 $0\popcount_a[63:0] - attribute \src "libresoc.v:151442.3-151468.6" + attribute \src "libresoc.v:151238.3-151264.6" wire width 64 $0\popcount_data_len[63:0] - attribute \src "libresoc.v:151566.3-151600.6" + attribute \src "libresoc.v:151362.3-151396.6" wire width 32 $1\a32[31:0] - attribute \src "libresoc.v:151415.3-151441.6" + attribute \src "libresoc.v:151211.3-151237.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:151349.3-151387.6" + attribute \src "libresoc.v:151145.3-151183.6" wire width 64 $1\bpermd_rb[63:0] - attribute \src "libresoc.v:151310.3-151348.6" + attribute \src "libresoc.v:151106.3-151144.6" wire width 64 $1\bpermd_rs[63:0] - attribute \src "libresoc.v:151275.3-151309.6" + attribute \src "libresoc.v:151071.3-151105.6" wire width 64 $1\clz_sig_in[63:0] - attribute \src "libresoc.v:151601.3-151643.6" + attribute \src "libresoc.v:151397.3-151439.6" wire width 64 $1\cntz_i[63:0] - attribute \src "libresoc.v:151531.3-151565.6" + attribute \src "libresoc.v:151327.3-151361.6" wire $1\count_right[0:0] - attribute \src "libresoc.v:151220.3-151274.6" + attribute \src "libresoc.v:151016.3-151070.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:151220.3-151274.6" + attribute \src "libresoc.v:151016.3-151070.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:151469.3-151499.6" + attribute \src "libresoc.v:151265.3-151295.6" wire $1\par0[0:0] - attribute \src "libresoc.v:151500.3-151530.6" + attribute \src "libresoc.v:151296.3-151326.6" wire $1\par1[0:0] - attribute \src "libresoc.v:151388.3-151414.6" + attribute \src "libresoc.v:151184.3-151210.6" wire width 64 $1\popcount_a[63:0] - attribute \src "libresoc.v:151442.3-151468.6" + attribute \src "libresoc.v:151238.3-151264.6" wire width 64 $1\popcount_data_len[63:0] - attribute \src "libresoc.v:151601.3-151643.6" + attribute \src "libresoc.v:151397.3-151439.6" wire width 64 $2\cntz_i[63:0] - attribute \src "libresoc.v:151220.3-151274.6" + attribute \src "libresoc.v:151016.3-151070.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:151167.18-151167.103" - wire width 64 $and$libresoc.v:151167$7489_Y - attribute \src "libresoc.v:151126.18-151126.118" - wire $eq$libresoc.v:151126$7443_Y - attribute \src "libresoc.v:151127.19-151127.119" - wire $eq$libresoc.v:151127$7444_Y - attribute \src "libresoc.v:151128.19-151128.119" - wire $eq$libresoc.v:151128$7445_Y - attribute \src "libresoc.v:151129.19-151129.119" - wire $eq$libresoc.v:151129$7446_Y - attribute \src "libresoc.v:151130.19-151130.119" - wire $eq$libresoc.v:151130$7447_Y - attribute \src "libresoc.v:151131.19-151131.119" - wire $eq$libresoc.v:151131$7448_Y - attribute \src "libresoc.v:151132.19-151132.119" - wire $eq$libresoc.v:151132$7449_Y - attribute \src "libresoc.v:151133.19-151133.119" - wire $eq$libresoc.v:151133$7450_Y - attribute \src "libresoc.v:151134.19-151134.119" - wire $eq$libresoc.v:151134$7451_Y - attribute \src "libresoc.v:151135.19-151135.119" - wire $eq$libresoc.v:151135$7452_Y - attribute \src "libresoc.v:151136.19-151136.119" - wire $eq$libresoc.v:151136$7453_Y - attribute \src "libresoc.v:151137.19-151137.119" - wire $eq$libresoc.v:151137$7454_Y - attribute \src "libresoc.v:151138.19-151138.119" - wire $eq$libresoc.v:151138$7455_Y - attribute \src "libresoc.v:151139.19-151139.119" - wire $eq$libresoc.v:151139$7456_Y - attribute \src "libresoc.v:151140.19-151140.119" - wire $eq$libresoc.v:151140$7457_Y - attribute \src "libresoc.v:151141.19-151141.119" - wire $eq$libresoc.v:151141$7458_Y - attribute \src "libresoc.v:151142.19-151142.119" - wire $eq$libresoc.v:151142$7459_Y - attribute \src "libresoc.v:151143.19-151143.119" - wire $eq$libresoc.v:151143$7460_Y - attribute \src "libresoc.v:151144.19-151144.119" - wire $eq$libresoc.v:151144$7461_Y - attribute \src "libresoc.v:151145.19-151145.119" - wire $eq$libresoc.v:151145$7462_Y - attribute \src "libresoc.v:151146.19-151146.119" - wire $eq$libresoc.v:151146$7463_Y - attribute \src "libresoc.v:151147.19-151147.119" - wire $eq$libresoc.v:151147$7464_Y - attribute \src "libresoc.v:151148.19-151148.119" - wire $eq$libresoc.v:151148$7465_Y - attribute \src "libresoc.v:151149.19-151149.119" - wire $eq$libresoc.v:151149$7466_Y - attribute \src "libresoc.v:151150.19-151150.119" - wire $eq$libresoc.v:151150$7467_Y - attribute \src "libresoc.v:151151.19-151151.119" - wire $eq$libresoc.v:151151$7468_Y - attribute \src "libresoc.v:151152.19-151152.119" - wire $eq$libresoc.v:151152$7469_Y - attribute \src "libresoc.v:151153.19-151153.119" - wire $eq$libresoc.v:151153$7470_Y - attribute \src "libresoc.v:151154.19-151154.128" - wire $eq$libresoc.v:151154$7471_Y - attribute \src "libresoc.v:151170.18-151170.114" - wire $eq$libresoc.v:151170$7492_Y - attribute \src "libresoc.v:151171.18-151171.114" - wire $eq$libresoc.v:151171$7493_Y - attribute \src "libresoc.v:151172.18-151172.114" - wire $eq$libresoc.v:151172$7494_Y - attribute \src "libresoc.v:151173.18-151173.114" - wire $eq$libresoc.v:151173$7495_Y - attribute \src "libresoc.v:151174.18-151174.114" - wire $eq$libresoc.v:151174$7496_Y - attribute \src "libresoc.v:151175.18-151175.114" - wire $eq$libresoc.v:151175$7497_Y - attribute \src "libresoc.v:151176.18-151176.114" - wire $eq$libresoc.v:151176$7498_Y - attribute \src "libresoc.v:151177.18-151177.114" - wire $eq$libresoc.v:151177$7499_Y - attribute \src "libresoc.v:151178.18-151178.116" - wire $eq$libresoc.v:151178$7500_Y - attribute \src "libresoc.v:151179.18-151179.116" - wire $eq$libresoc.v:151179$7501_Y - attribute \src "libresoc.v:151180.18-151180.116" - wire $eq$libresoc.v:151180$7502_Y - attribute \src "libresoc.v:151181.18-151181.116" - wire $eq$libresoc.v:151181$7503_Y - attribute \src "libresoc.v:151182.18-151182.116" - wire $eq$libresoc.v:151182$7504_Y - attribute \src "libresoc.v:151183.18-151183.116" - wire $eq$libresoc.v:151183$7505_Y - attribute \src "libresoc.v:151184.18-151184.116" - wire $eq$libresoc.v:151184$7506_Y - attribute \src "libresoc.v:151185.18-151185.116" - wire $eq$libresoc.v:151185$7507_Y - attribute \src "libresoc.v:151186.18-151186.118" - wire $eq$libresoc.v:151186$7508_Y - attribute \src "libresoc.v:151187.18-151187.118" - wire $eq$libresoc.v:151187$7509_Y - attribute \src "libresoc.v:151188.18-151188.118" - wire $eq$libresoc.v:151188$7510_Y - attribute \src "libresoc.v:151189.18-151189.118" - wire $eq$libresoc.v:151189$7511_Y - attribute \src "libresoc.v:151190.18-151190.118" - wire $eq$libresoc.v:151190$7512_Y - attribute \src "libresoc.v:151191.18-151191.118" - wire $eq$libresoc.v:151191$7513_Y - attribute \src "libresoc.v:151192.18-151192.118" - wire $eq$libresoc.v:151192$7514_Y - attribute \src "libresoc.v:151193.18-151193.118" - wire $eq$libresoc.v:151193$7515_Y - attribute \src "libresoc.v:151194.18-151194.118" - wire $eq$libresoc.v:151194$7516_Y - attribute \src "libresoc.v:151195.18-151195.118" - wire $eq$libresoc.v:151195$7517_Y - attribute \src "libresoc.v:151196.18-151196.118" - wire $eq$libresoc.v:151196$7518_Y - attribute \src "libresoc.v:151197.18-151197.118" - wire $eq$libresoc.v:151197$7519_Y - attribute \src "libresoc.v:151198.18-151198.118" - wire $eq$libresoc.v:151198$7520_Y - attribute \src "libresoc.v:151199.18-151199.118" - wire $eq$libresoc.v:151199$7521_Y - attribute \src "libresoc.v:151200.18-151200.118" - wire $eq$libresoc.v:151200$7522_Y - attribute \src "libresoc.v:151201.18-151201.118" - wire $eq$libresoc.v:151201$7523_Y - attribute \src "libresoc.v:151202.18-151202.118" - wire $eq$libresoc.v:151202$7524_Y - attribute \src "libresoc.v:151203.18-151203.118" - wire $eq$libresoc.v:151203$7525_Y - attribute \src "libresoc.v:151204.18-151204.118" - wire $eq$libresoc.v:151204$7526_Y - attribute \src "libresoc.v:151205.18-151205.118" - wire $eq$libresoc.v:151205$7527_Y - attribute \src "libresoc.v:151156.19-151156.104" - wire width 64 $extend$libresoc.v:151156$7473_Y - attribute \src "libresoc.v:151158.19-151158.93" - wire width 8 $extend$libresoc.v:151158$7476_Y - attribute \src "libresoc.v:151160.19-151160.105" - wire width 64 $extend$libresoc.v:151160$7479_Y - attribute \src "libresoc.v:151161.19-151161.118" - wire width 64 $extend$libresoc.v:151161$7481_Y - attribute \src "libresoc.v:151165.19-151165.105" - wire width 64 $extend$libresoc.v:151165$7486_Y - attribute \src "libresoc.v:151168.18-151168.103" - wire width 64 $or$libresoc.v:151168$7490_Y - attribute \src "libresoc.v:151156.19-151156.104" - wire width 64 $pos$libresoc.v:151156$7474_Y - attribute \src "libresoc.v:151158.19-151158.93" - wire width 8 $pos$libresoc.v:151158$7477_Y - attribute \src "libresoc.v:151160.19-151160.105" - wire width 64 $pos$libresoc.v:151160$7480_Y - attribute \src "libresoc.v:151161.19-151161.118" - wire width 64 $pos$libresoc.v:151161$7482_Y - attribute \src "libresoc.v:151165.19-151165.105" - wire width 64 $pos$libresoc.v:151165$7487_Y - attribute \src "libresoc.v:151162.19-151162.131" - wire $reduce_xor$libresoc.v:151162$7483_Y - attribute \src "libresoc.v:151163.19-151163.133" - wire $reduce_xor$libresoc.v:151163$7484_Y - attribute \src "libresoc.v:151157.19-151157.112" - wire width 8 $sub$libresoc.v:151157$7475_Y - attribute \src "libresoc.v:151159.19-151159.135" - wire width 8 $ternary$libresoc.v:151159$7478_Y - attribute \src "libresoc.v:151164.19-151164.398" - wire width 32 $ternary$libresoc.v:151164$7485_Y - attribute \src "libresoc.v:151166.19-151166.621" - wire width 64 $ternary$libresoc.v:151166$7488_Y - attribute \src "libresoc.v:151155.19-151155.108" - wire $xor$libresoc.v:151155$7472_Y - attribute \src "libresoc.v:151169.18-151169.103" - wire width 64 $xor$libresoc.v:151169$7491_Y + attribute \src "libresoc.v:150963.18-150963.103" + wire width 64 $and$libresoc.v:150963$7489_Y + attribute \src "libresoc.v:150922.18-150922.118" + wire $eq$libresoc.v:150922$7443_Y + attribute \src "libresoc.v:150923.19-150923.119" + wire $eq$libresoc.v:150923$7444_Y + attribute \src "libresoc.v:150924.19-150924.119" + wire $eq$libresoc.v:150924$7445_Y + attribute \src "libresoc.v:150925.19-150925.119" + wire $eq$libresoc.v:150925$7446_Y + attribute \src "libresoc.v:150926.19-150926.119" + wire $eq$libresoc.v:150926$7447_Y + attribute \src "libresoc.v:150927.19-150927.119" + wire $eq$libresoc.v:150927$7448_Y + attribute \src "libresoc.v:150928.19-150928.119" + wire $eq$libresoc.v:150928$7449_Y + attribute \src "libresoc.v:150929.19-150929.119" + wire $eq$libresoc.v:150929$7450_Y + attribute \src "libresoc.v:150930.19-150930.119" + wire $eq$libresoc.v:150930$7451_Y + attribute \src "libresoc.v:150931.19-150931.119" + wire $eq$libresoc.v:150931$7452_Y + attribute \src "libresoc.v:150932.19-150932.119" + wire $eq$libresoc.v:150932$7453_Y + attribute \src "libresoc.v:150933.19-150933.119" + wire $eq$libresoc.v:150933$7454_Y + attribute \src "libresoc.v:150934.19-150934.119" + wire $eq$libresoc.v:150934$7455_Y + attribute \src "libresoc.v:150935.19-150935.119" + wire $eq$libresoc.v:150935$7456_Y + attribute \src "libresoc.v:150936.19-150936.119" + wire $eq$libresoc.v:150936$7457_Y + attribute \src "libresoc.v:150937.19-150937.119" + wire $eq$libresoc.v:150937$7458_Y + attribute \src "libresoc.v:150938.19-150938.119" + wire $eq$libresoc.v:150938$7459_Y + attribute \src "libresoc.v:150939.19-150939.119" + wire $eq$libresoc.v:150939$7460_Y + attribute \src "libresoc.v:150940.19-150940.119" + wire $eq$libresoc.v:150940$7461_Y + attribute \src "libresoc.v:150941.19-150941.119" + wire $eq$libresoc.v:150941$7462_Y + attribute \src "libresoc.v:150942.19-150942.119" + wire $eq$libresoc.v:150942$7463_Y + attribute \src "libresoc.v:150943.19-150943.119" + wire $eq$libresoc.v:150943$7464_Y + attribute \src "libresoc.v:150944.19-150944.119" + wire $eq$libresoc.v:150944$7465_Y + attribute \src "libresoc.v:150945.19-150945.119" + wire $eq$libresoc.v:150945$7466_Y + attribute \src "libresoc.v:150946.19-150946.119" + wire $eq$libresoc.v:150946$7467_Y + attribute \src "libresoc.v:150947.19-150947.119" + wire $eq$libresoc.v:150947$7468_Y + attribute \src "libresoc.v:150948.19-150948.119" + wire $eq$libresoc.v:150948$7469_Y + attribute \src "libresoc.v:150949.19-150949.119" + wire $eq$libresoc.v:150949$7470_Y + attribute \src "libresoc.v:150950.19-150950.128" + wire $eq$libresoc.v:150950$7471_Y + attribute \src "libresoc.v:150966.18-150966.114" + wire $eq$libresoc.v:150966$7492_Y + attribute \src "libresoc.v:150967.18-150967.114" + wire $eq$libresoc.v:150967$7493_Y + attribute \src "libresoc.v:150968.18-150968.114" + wire $eq$libresoc.v:150968$7494_Y + attribute \src "libresoc.v:150969.18-150969.114" + wire $eq$libresoc.v:150969$7495_Y + attribute \src "libresoc.v:150970.18-150970.114" + wire $eq$libresoc.v:150970$7496_Y + attribute \src "libresoc.v:150971.18-150971.114" + wire $eq$libresoc.v:150971$7497_Y + attribute \src "libresoc.v:150972.18-150972.114" + wire $eq$libresoc.v:150972$7498_Y + attribute \src "libresoc.v:150973.18-150973.114" + wire $eq$libresoc.v:150973$7499_Y + attribute \src "libresoc.v:150974.18-150974.116" + wire $eq$libresoc.v:150974$7500_Y + attribute \src "libresoc.v:150975.18-150975.116" + wire $eq$libresoc.v:150975$7501_Y + attribute \src "libresoc.v:150976.18-150976.116" + wire $eq$libresoc.v:150976$7502_Y + attribute \src "libresoc.v:150977.18-150977.116" + wire $eq$libresoc.v:150977$7503_Y + attribute \src "libresoc.v:150978.18-150978.116" + wire $eq$libresoc.v:150978$7504_Y + attribute \src "libresoc.v:150979.18-150979.116" + wire $eq$libresoc.v:150979$7505_Y + attribute \src "libresoc.v:150980.18-150980.116" + wire $eq$libresoc.v:150980$7506_Y + attribute \src "libresoc.v:150981.18-150981.116" + wire $eq$libresoc.v:150981$7507_Y + attribute \src "libresoc.v:150982.18-150982.118" + wire $eq$libresoc.v:150982$7508_Y + attribute \src "libresoc.v:150983.18-150983.118" + wire $eq$libresoc.v:150983$7509_Y + attribute \src "libresoc.v:150984.18-150984.118" + wire $eq$libresoc.v:150984$7510_Y + attribute \src "libresoc.v:150985.18-150985.118" + wire $eq$libresoc.v:150985$7511_Y + attribute \src "libresoc.v:150986.18-150986.118" + wire $eq$libresoc.v:150986$7512_Y + attribute \src "libresoc.v:150987.18-150987.118" + wire $eq$libresoc.v:150987$7513_Y + attribute \src "libresoc.v:150988.18-150988.118" + wire $eq$libresoc.v:150988$7514_Y + attribute \src "libresoc.v:150989.18-150989.118" + wire $eq$libresoc.v:150989$7515_Y + attribute \src "libresoc.v:150990.18-150990.118" + wire $eq$libresoc.v:150990$7516_Y + attribute \src "libresoc.v:150991.18-150991.118" + wire $eq$libresoc.v:150991$7517_Y + attribute \src "libresoc.v:150992.18-150992.118" + wire $eq$libresoc.v:150992$7518_Y + attribute \src "libresoc.v:150993.18-150993.118" + wire $eq$libresoc.v:150993$7519_Y + attribute \src "libresoc.v:150994.18-150994.118" + wire $eq$libresoc.v:150994$7520_Y + attribute \src "libresoc.v:150995.18-150995.118" + wire $eq$libresoc.v:150995$7521_Y + attribute \src "libresoc.v:150996.18-150996.118" + wire $eq$libresoc.v:150996$7522_Y + attribute \src "libresoc.v:150997.18-150997.118" + wire $eq$libresoc.v:150997$7523_Y + attribute \src "libresoc.v:150998.18-150998.118" + wire $eq$libresoc.v:150998$7524_Y + attribute \src "libresoc.v:150999.18-150999.118" + wire $eq$libresoc.v:150999$7525_Y + attribute \src "libresoc.v:151000.18-151000.118" + wire $eq$libresoc.v:151000$7526_Y + attribute \src "libresoc.v:151001.18-151001.118" + wire $eq$libresoc.v:151001$7527_Y + attribute \src "libresoc.v:150952.19-150952.104" + wire width 64 $extend$libresoc.v:150952$7473_Y + attribute \src "libresoc.v:150954.19-150954.93" + wire width 8 $extend$libresoc.v:150954$7476_Y + attribute \src "libresoc.v:150956.19-150956.105" + wire width 64 $extend$libresoc.v:150956$7479_Y + attribute \src "libresoc.v:150957.19-150957.118" + wire width 64 $extend$libresoc.v:150957$7481_Y + attribute \src "libresoc.v:150961.19-150961.105" + wire width 64 $extend$libresoc.v:150961$7486_Y + attribute \src "libresoc.v:150964.18-150964.103" + wire width 64 $or$libresoc.v:150964$7490_Y + attribute \src "libresoc.v:150952.19-150952.104" + wire width 64 $pos$libresoc.v:150952$7474_Y + attribute \src "libresoc.v:150954.19-150954.93" + wire width 8 $pos$libresoc.v:150954$7477_Y + attribute \src "libresoc.v:150956.19-150956.105" + wire width 64 $pos$libresoc.v:150956$7480_Y + attribute \src "libresoc.v:150957.19-150957.118" + wire width 64 $pos$libresoc.v:150957$7482_Y + attribute \src "libresoc.v:150961.19-150961.105" + wire width 64 $pos$libresoc.v:150961$7487_Y + attribute \src "libresoc.v:150958.19-150958.131" + wire $reduce_xor$libresoc.v:150958$7483_Y + attribute \src "libresoc.v:150959.19-150959.133" + wire $reduce_xor$libresoc.v:150959$7484_Y + attribute \src "libresoc.v:150953.19-150953.112" + wire width 8 $sub$libresoc.v:150953$7475_Y + attribute \src "libresoc.v:150955.19-150955.135" + wire width 8 $ternary$libresoc.v:150955$7478_Y + attribute \src "libresoc.v:150960.19-150960.398" + wire width 32 $ternary$libresoc.v:150960$7485_Y + attribute \src "libresoc.v:150962.19-150962.621" + wire width 64 $ternary$libresoc.v:150962$7488_Y + attribute \src "libresoc.v:150951.19-150951.108" + wire $xor$libresoc.v:150951$7472_Y + attribute \src "libresoc.v:150965.18-150965.103" + wire width 64 $xor$libresoc.v:150965$7491_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" @@ -279969,7 +279803,7 @@ module \main$51 wire width 64 \cntz_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" wire \count_right - attribute \src "libresoc.v:150659.7-150659.15" + attribute \src "libresoc.v:150455.7-150455.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -280258,7 +280092,7 @@ module \main$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 43 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$libresoc.v:151167$7489 + cell $and $and$libresoc.v:150963$7489 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -280266,10 +280100,10 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $and$libresoc.v:151167$7489_Y + connect \Y $and$libresoc.v:150963$7489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151126$7443 + cell $eq $eq$libresoc.v:150922$7443 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280277,10 +280111,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:151126$7443_Y + connect \Y $eq$libresoc.v:150922$7443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151127$7444 + cell $eq $eq$libresoc.v:150923$7444 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280288,10 +280122,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:151127$7444_Y + connect \Y $eq$libresoc.v:150923$7444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151128$7445 + cell $eq $eq$libresoc.v:150924$7445 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280299,10 +280133,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:151128$7445_Y + connect \Y $eq$libresoc.v:150924$7445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151129$7446 + cell $eq $eq$libresoc.v:150925$7446 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280310,10 +280144,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:151129$7446_Y + connect \Y $eq$libresoc.v:150925$7446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151130$7447 + cell $eq $eq$libresoc.v:150926$7447 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280321,10 +280155,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:151130$7447_Y + connect \Y $eq$libresoc.v:150926$7447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151131$7448 + cell $eq $eq$libresoc.v:150927$7448 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280332,10 +280166,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:151131$7448_Y + connect \Y $eq$libresoc.v:150927$7448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151132$7449 + cell $eq $eq$libresoc.v:150928$7449 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280343,10 +280177,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:151132$7449_Y + connect \Y $eq$libresoc.v:150928$7449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151133$7450 + cell $eq $eq$libresoc.v:150929$7450 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280354,10 +280188,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:151133$7450_Y + connect \Y $eq$libresoc.v:150929$7450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151134$7451 + cell $eq $eq$libresoc.v:150930$7451 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280365,10 +280199,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:151134$7451_Y + connect \Y $eq$libresoc.v:150930$7451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151135$7452 + cell $eq $eq$libresoc.v:150931$7452 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280376,10 +280210,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:151135$7452_Y + connect \Y $eq$libresoc.v:150931$7452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151136$7453 + cell $eq $eq$libresoc.v:150932$7453 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280387,10 +280221,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:151136$7453_Y + connect \Y $eq$libresoc.v:150932$7453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151137$7454 + cell $eq $eq$libresoc.v:150933$7454 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280398,10 +280232,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:151137$7454_Y + connect \Y $eq$libresoc.v:150933$7454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151138$7455 + cell $eq $eq$libresoc.v:150934$7455 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280409,10 +280243,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:151138$7455_Y + connect \Y $eq$libresoc.v:150934$7455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151139$7456 + cell $eq $eq$libresoc.v:150935$7456 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280420,10 +280254,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:151139$7456_Y + connect \Y $eq$libresoc.v:150935$7456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151140$7457 + cell $eq $eq$libresoc.v:150936$7457 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280431,10 +280265,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:151140$7457_Y + connect \Y $eq$libresoc.v:150936$7457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151141$7458 + cell $eq $eq$libresoc.v:150937$7458 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280442,10 +280276,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:151141$7458_Y + connect \Y $eq$libresoc.v:150937$7458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151142$7459 + cell $eq $eq$libresoc.v:150938$7459 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280453,10 +280287,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:151142$7459_Y + connect \Y $eq$libresoc.v:150938$7459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151143$7460 + cell $eq $eq$libresoc.v:150939$7460 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280464,10 +280298,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:151143$7460_Y + connect \Y $eq$libresoc.v:150939$7460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151144$7461 + cell $eq $eq$libresoc.v:150940$7461 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280475,10 +280309,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:151144$7461_Y + connect \Y $eq$libresoc.v:150940$7461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151145$7462 + cell $eq $eq$libresoc.v:150941$7462 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280486,10 +280320,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:151145$7462_Y + connect \Y $eq$libresoc.v:150941$7462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151146$7463 + cell $eq $eq$libresoc.v:150942$7463 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280497,10 +280331,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:151146$7463_Y + connect \Y $eq$libresoc.v:150942$7463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151147$7464 + cell $eq $eq$libresoc.v:150943$7464 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280508,10 +280342,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:151147$7464_Y + connect \Y $eq$libresoc.v:150943$7464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151148$7465 + cell $eq $eq$libresoc.v:150944$7465 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280519,10 +280353,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:151148$7465_Y + connect \Y $eq$libresoc.v:150944$7465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151149$7466 + cell $eq $eq$libresoc.v:150945$7466 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280530,10 +280364,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:151149$7466_Y + connect \Y $eq$libresoc.v:150945$7466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151150$7467 + cell $eq $eq$libresoc.v:150946$7467 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280541,10 +280375,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:151150$7467_Y + connect \Y $eq$libresoc.v:150946$7467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151151$7468 + cell $eq $eq$libresoc.v:150947$7468 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280552,10 +280386,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:151151$7468_Y + connect \Y $eq$libresoc.v:150947$7468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151152$7469 + cell $eq $eq$libresoc.v:150948$7469 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280563,10 +280397,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:151152$7469_Y + connect \Y $eq$libresoc.v:150948$7469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151153$7470 + cell $eq $eq$libresoc.v:150949$7470 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280574,10 +280408,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:151153$7470_Y + connect \Y $eq$libresoc.v:150949$7470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$libresoc.v:151154$7471 + cell $eq $eq$libresoc.v:150950$7471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280585,10 +280419,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \logical_op__data_len [3] connect \B 1'1 - connect \Y $eq$libresoc.v:151154$7471_Y + connect \Y $eq$libresoc.v:150950$7471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151170$7492 + cell $eq $eq$libresoc.v:150966$7492 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280596,10 +280430,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:151170$7492_Y + connect \Y $eq$libresoc.v:150966$7492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151171$7493 + cell $eq $eq$libresoc.v:150967$7493 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280607,10 +280441,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:151171$7493_Y + connect \Y $eq$libresoc.v:150967$7493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151172$7494 + cell $eq $eq$libresoc.v:150968$7494 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280618,10 +280452,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:151172$7494_Y + connect \Y $eq$libresoc.v:150968$7494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151173$7495 + cell $eq $eq$libresoc.v:150969$7495 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280629,10 +280463,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:151173$7495_Y + connect \Y $eq$libresoc.v:150969$7495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151174$7496 + cell $eq $eq$libresoc.v:150970$7496 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280640,10 +280474,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:151174$7496_Y + connect \Y $eq$libresoc.v:150970$7496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151175$7497 + cell $eq $eq$libresoc.v:150971$7497 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280651,10 +280485,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:151175$7497_Y + connect \Y $eq$libresoc.v:150971$7497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151176$7498 + cell $eq $eq$libresoc.v:150972$7498 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280662,10 +280496,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:151176$7498_Y + connect \Y $eq$libresoc.v:150972$7498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151177$7499 + cell $eq $eq$libresoc.v:150973$7499 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280673,10 +280507,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:151177$7499_Y + connect \Y $eq$libresoc.v:150973$7499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151178$7500 + cell $eq $eq$libresoc.v:150974$7500 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280684,10 +280518,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:151178$7500_Y + connect \Y $eq$libresoc.v:150974$7500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151179$7501 + cell $eq $eq$libresoc.v:150975$7501 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280695,10 +280529,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:151179$7501_Y + connect \Y $eq$libresoc.v:150975$7501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151180$7502 + cell $eq $eq$libresoc.v:150976$7502 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280706,10 +280540,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:151180$7502_Y + connect \Y $eq$libresoc.v:150976$7502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151181$7503 + cell $eq $eq$libresoc.v:150977$7503 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280717,10 +280551,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:151181$7503_Y + connect \Y $eq$libresoc.v:150977$7503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151182$7504 + cell $eq $eq$libresoc.v:150978$7504 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280728,10 +280562,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:151182$7504_Y + connect \Y $eq$libresoc.v:150978$7504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151183$7505 + cell $eq $eq$libresoc.v:150979$7505 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280739,10 +280573,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:151183$7505_Y + connect \Y $eq$libresoc.v:150979$7505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151184$7506 + cell $eq $eq$libresoc.v:150980$7506 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280750,10 +280584,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:151184$7506_Y + connect \Y $eq$libresoc.v:150980$7506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151185$7507 + cell $eq $eq$libresoc.v:150981$7507 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280761,10 +280595,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:151185$7507_Y + connect \Y $eq$libresoc.v:150981$7507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151186$7508 + cell $eq $eq$libresoc.v:150982$7508 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280772,10 +280606,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:151186$7508_Y + connect \Y $eq$libresoc.v:150982$7508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151187$7509 + cell $eq $eq$libresoc.v:150983$7509 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280783,10 +280617,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:151187$7509_Y + connect \Y $eq$libresoc.v:150983$7509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151188$7510 + cell $eq $eq$libresoc.v:150984$7510 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280794,10 +280628,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:151188$7510_Y + connect \Y $eq$libresoc.v:150984$7510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151189$7511 + cell $eq $eq$libresoc.v:150985$7511 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280805,10 +280639,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:151189$7511_Y + connect \Y $eq$libresoc.v:150985$7511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151190$7512 + cell $eq $eq$libresoc.v:150986$7512 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280816,10 +280650,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:151190$7512_Y + connect \Y $eq$libresoc.v:150986$7512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151191$7513 + cell $eq $eq$libresoc.v:150987$7513 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280827,10 +280661,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:151191$7513_Y + connect \Y $eq$libresoc.v:150987$7513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151192$7514 + cell $eq $eq$libresoc.v:150988$7514 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280838,10 +280672,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:151192$7514_Y + connect \Y $eq$libresoc.v:150988$7514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151193$7515 + cell $eq $eq$libresoc.v:150989$7515 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280849,10 +280683,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:151193$7515_Y + connect \Y $eq$libresoc.v:150989$7515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151194$7516 + cell $eq $eq$libresoc.v:150990$7516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280860,10 +280694,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:151194$7516_Y + connect \Y $eq$libresoc.v:150990$7516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151195$7517 + cell $eq $eq$libresoc.v:150991$7517 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280871,10 +280705,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:151195$7517_Y + connect \Y $eq$libresoc.v:150991$7517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151196$7518 + cell $eq $eq$libresoc.v:150992$7518 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280882,10 +280716,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:151196$7518_Y + connect \Y $eq$libresoc.v:150992$7518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151197$7519 + cell $eq $eq$libresoc.v:150993$7519 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280893,10 +280727,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:151197$7519_Y + connect \Y $eq$libresoc.v:150993$7519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151198$7520 + cell $eq $eq$libresoc.v:150994$7520 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280904,10 +280738,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:151198$7520_Y + connect \Y $eq$libresoc.v:150994$7520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151199$7521 + cell $eq $eq$libresoc.v:150995$7521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280915,10 +280749,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:151199$7521_Y + connect \Y $eq$libresoc.v:150995$7521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151200$7522 + cell $eq $eq$libresoc.v:150996$7522 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280926,10 +280760,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:151200$7522_Y + connect \Y $eq$libresoc.v:150996$7522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151201$7523 + cell $eq $eq$libresoc.v:150997$7523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280937,10 +280771,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:151201$7523_Y + connect \Y $eq$libresoc.v:150997$7523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151202$7524 + cell $eq $eq$libresoc.v:150998$7524 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280948,10 +280782,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:151202$7524_Y + connect \Y $eq$libresoc.v:150998$7524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151203$7525 + cell $eq $eq$libresoc.v:150999$7525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280959,10 +280793,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:151203$7525_Y + connect \Y $eq$libresoc.v:150999$7525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151204$7526 + cell $eq $eq$libresoc.v:151000$7526 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280970,10 +280804,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:151204$7526_Y + connect \Y $eq$libresoc.v:151000$7526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:151205$7527 + cell $eq $eq$libresoc.v:151001$7527 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280981,50 +280815,50 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:151205$7527_Y + connect \Y $eq$libresoc.v:151001$7527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$libresoc.v:151156$7473 + cell $pos $extend$libresoc.v:150952$7473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 64 connect \A \$158 - connect \Y $extend$libresoc.v:151156$7473_Y + connect \Y $extend$libresoc.v:150952$7473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $extend$libresoc.v:151158$7476 + cell $pos $extend$libresoc.v:150954$7476 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 8 connect \A \clz_lz - connect \Y $extend$libresoc.v:151158$7476_Y + connect \Y $extend$libresoc.v:150954$7476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$libresoc.v:151160$7479 + cell $pos $extend$libresoc.v:150956$7479 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \$166 - connect \Y $extend$libresoc.v:151160$7479_Y + connect \Y $extend$libresoc.v:150956$7479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:151161$7481 + cell $pos $extend$libresoc.v:150957$7481 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 64 connect \A \logical_op__data_len - connect \Y $extend$libresoc.v:151161$7481_Y + connect \Y $extend$libresoc.v:150957$7481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$libresoc.v:151165$7486 + cell $pos $extend$libresoc.v:150961$7486 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$176 - connect \Y $extend$libresoc.v:151165$7486_Y + connect \Y $extend$libresoc.v:150961$7486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$libresoc.v:151168$7490 + cell $or $or$libresoc.v:150964$7490 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -281032,66 +280866,66 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $or$libresoc.v:151168$7490_Y + connect \Y $or$libresoc.v:150964$7490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$libresoc.v:151156$7474 + cell $pos $pos$libresoc.v:150952$7474 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:151156$7473_Y - connect \Y $pos$libresoc.v:151156$7474_Y + connect \A $extend$libresoc.v:150952$7473_Y + connect \Y $pos$libresoc.v:150952$7474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $pos$libresoc.v:151158$7477 + cell $pos $pos$libresoc.v:150954$7477 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:151158$7476_Y - connect \Y $pos$libresoc.v:151158$7477_Y + connect \A $extend$libresoc.v:150954$7476_Y + connect \Y $pos$libresoc.v:150954$7477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$libresoc.v:151160$7480 + cell $pos $pos$libresoc.v:150956$7480 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:151160$7479_Y - connect \Y $pos$libresoc.v:151160$7480_Y + connect \A $extend$libresoc.v:150956$7479_Y + connect \Y $pos$libresoc.v:150956$7480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:151161$7482 + cell $pos $pos$libresoc.v:150957$7482 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:151161$7481_Y - connect \Y $pos$libresoc.v:151161$7482_Y + connect \A $extend$libresoc.v:150957$7481_Y + connect \Y $pos$libresoc.v:150957$7482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$libresoc.v:151165$7487 + cell $pos $pos$libresoc.v:150961$7487 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:151165$7486_Y - connect \Y $pos$libresoc.v:151165$7487_Y + connect \A $extend$libresoc.v:150961$7486_Y + connect \Y $pos$libresoc.v:150961$7487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$libresoc.v:151162$7483 + cell $reduce_xor $reduce_xor$libresoc.v:150958$7483 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$libresoc.v:151162$7483_Y + connect \Y $reduce_xor$libresoc.v:150958$7483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$libresoc.v:151163$7484 + cell $reduce_xor $reduce_xor$libresoc.v:150959$7484 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$libresoc.v:151163$7484_Y + connect \Y $reduce_xor$libresoc.v:150959$7484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$libresoc.v:151157$7475 + cell $sub $sub$libresoc.v:150953$7475 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -281099,34 +280933,34 @@ module \main$51 parameter \Y_WIDTH 8 connect \A \clz_lz connect \B 6'100000 - connect \Y $sub$libresoc.v:151157$7475_Y + connect \Y $sub$libresoc.v:150953$7475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$libresoc.v:151159$7478 + cell $mux $ternary$libresoc.v:150955$7478 parameter \WIDTH 8 connect \A \$164 connect \B \$162 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:151159$7478_Y + connect \Y $ternary$libresoc.v:150955$7478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$libresoc.v:151164$7485 + cell $mux $ternary$libresoc.v:150960$7485 parameter \WIDTH 32 connect \A \a32 connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } connect \S \count_right - connect \Y $ternary$libresoc.v:151164$7485_Y + connect \Y $ternary$libresoc.v:150960$7485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$libresoc.v:151166$7488 + cell $mux $ternary$libresoc.v:150962$7488 parameter \WIDTH 64 connect \A \ra connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } connect \S \count_right - connect \Y $ternary$libresoc.v:151166$7488_Y + connect \Y $ternary$libresoc.v:150962$7488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$libresoc.v:151155$7472 + cell $xor $xor$libresoc.v:150951$7472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281134,10 +280968,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \par0 connect \B \par1 - connect \Y $xor$libresoc.v:151155$7472_Y + connect \Y $xor$libresoc.v:150951$7472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$libresoc.v:151169$7491 + cell $xor $xor$libresoc.v:150965$7491 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -281145,47 +280979,47 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $xor$libresoc.v:151169$7491_Y + connect \Y $xor$libresoc.v:150965$7491_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:151206.10-151210.4" + attribute \src "libresoc.v:151002.10-151006.4" cell \bpermd \bpermd connect \ra \bpermd_ra connect \rb \bpermd_rb connect \rs \bpermd_rs end attribute \module_not_derived 1 - attribute \src "libresoc.v:151211.7-151214.4" + attribute \src "libresoc.v:151007.7-151010.4" cell \clz \clz connect \lz \clz_lz connect \sig_in \clz_sig_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:151215.12-151219.4" + attribute \src "libresoc.v:151011.12-151015.4" cell \popcount \popcount connect \a \popcount_a connect \data_len \popcount_data_len connect \o \popcount_o end - attribute \src "libresoc.v:150659.7-150659.20" - process $proc$libresoc.v:150659$7540 + attribute \src "libresoc.v:150455.7-150455.20" + process $proc$libresoc.v:150455$7540 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151220.3-151274.6" - process $proc$libresoc.v:151220$7528 + attribute \src "libresoc.v:151016.3-151070.6" + process $proc$libresoc.v:151016$7528 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:151221.5-151221.29" + attribute \src "libresoc.v:151017.5-151017.29" switch \initial - attribute \src "libresoc.v:151221.9-151221.17" + attribute \src "libresoc.v:151017.9-151017.17" case 1'1 case end @@ -281253,14 +281087,14 @@ module \main$51 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:151275.3-151309.6" - process $proc$libresoc.v:151275$7529 + attribute \src "libresoc.v:151071.3-151105.6" + process $proc$libresoc.v:151071$7529 assign { } { } assign { } { } assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "libresoc.v:151276.5-151276.29" + attribute \src "libresoc.v:151072.5-151072.29" switch \initial - attribute \src "libresoc.v:151276.9-151276.17" + attribute \src "libresoc.v:151072.9-151072.17" case 1'1 case end @@ -281294,14 +281128,14 @@ module \main$51 sync always update \clz_sig_in $0\clz_sig_in[63:0] end - attribute \src "libresoc.v:151310.3-151348.6" - process $proc$libresoc.v:151310$7530 + attribute \src "libresoc.v:151106.3-151144.6" + process $proc$libresoc.v:151106$7530 assign { } { } assign { } { } assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "libresoc.v:151311.5-151311.29" + attribute \src "libresoc.v:151107.5-151107.29" switch \initial - attribute \src "libresoc.v:151311.9-151311.17" + attribute \src "libresoc.v:151107.9-151107.17" case 1'1 case end @@ -281338,14 +281172,14 @@ module \main$51 sync always update \bpermd_rs $0\bpermd_rs[63:0] end - attribute \src "libresoc.v:151349.3-151387.6" - process $proc$libresoc.v:151349$7531 + attribute \src "libresoc.v:151145.3-151183.6" + process $proc$libresoc.v:151145$7531 assign { } { } assign { } { } assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "libresoc.v:151350.5-151350.29" + attribute \src "libresoc.v:151146.5-151146.29" switch \initial - attribute \src "libresoc.v:151350.9-151350.17" + attribute \src "libresoc.v:151146.9-151146.17" case 1'1 case end @@ -281382,14 +281216,14 @@ module \main$51 sync always update \bpermd_rb $0\bpermd_rb[63:0] end - attribute \src "libresoc.v:151388.3-151414.6" - process $proc$libresoc.v:151388$7532 + attribute \src "libresoc.v:151184.3-151210.6" + process $proc$libresoc.v:151184$7532 assign { } { } assign { } { } assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "libresoc.v:151389.5-151389.29" + attribute \src "libresoc.v:151185.5-151185.29" switch \initial - attribute \src "libresoc.v:151389.9-151389.17" + attribute \src "libresoc.v:151185.9-151185.17" case 1'1 case end @@ -281417,14 +281251,14 @@ module \main$51 sync always update \popcount_a $0\popcount_a[63:0] end - attribute \src "libresoc.v:151415.3-151441.6" - process $proc$libresoc.v:151415$7533 + attribute \src "libresoc.v:151211.3-151237.6" + process $proc$libresoc.v:151211$7533 assign { } { } assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:151416.5-151416.29" + attribute \src "libresoc.v:151212.5-151212.29" switch \initial - attribute \src "libresoc.v:151416.9-151416.17" + attribute \src "libresoc.v:151212.9-151212.17" case 1'1 case end @@ -281452,14 +281286,14 @@ module \main$51 sync always update \b $0\b[63:0] end - attribute \src "libresoc.v:151442.3-151468.6" - process $proc$libresoc.v:151442$7534 + attribute \src "libresoc.v:151238.3-151264.6" + process $proc$libresoc.v:151238$7534 assign { } { } assign { } { } assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] - attribute \src "libresoc.v:151443.5-151443.29" + attribute \src "libresoc.v:151239.5-151239.29" switch \initial - attribute \src "libresoc.v:151443.9-151443.17" + attribute \src "libresoc.v:151239.9-151239.17" case 1'1 case end @@ -281487,14 +281321,14 @@ module \main$51 sync always update \popcount_data_len $0\popcount_data_len[63:0] end - attribute \src "libresoc.v:151469.3-151499.6" - process $proc$libresoc.v:151469$7535 + attribute \src "libresoc.v:151265.3-151295.6" + process $proc$libresoc.v:151265$7535 assign { } { } assign { } { } assign $0\par0[0:0] $1\par0[0:0] - attribute \src "libresoc.v:151470.5-151470.29" + attribute \src "libresoc.v:151266.5-151266.29" switch \initial - attribute \src "libresoc.v:151470.9-151470.17" + attribute \src "libresoc.v:151266.9-151266.17" case 1'1 case end @@ -281525,14 +281359,14 @@ module \main$51 sync always update \par0 $0\par0[0:0] end - attribute \src "libresoc.v:151500.3-151530.6" - process $proc$libresoc.v:151500$7536 + attribute \src "libresoc.v:151296.3-151326.6" + process $proc$libresoc.v:151296$7536 assign { } { } assign { } { } assign $0\par1[0:0] $1\par1[0:0] - attribute \src "libresoc.v:151501.5-151501.29" + attribute \src "libresoc.v:151297.5-151297.29" switch \initial - attribute \src "libresoc.v:151501.9-151501.17" + attribute \src "libresoc.v:151297.9-151297.17" case 1'1 case end @@ -281563,14 +281397,14 @@ module \main$51 sync always update \par1 $0\par1[0:0] end - attribute \src "libresoc.v:151531.3-151565.6" - process $proc$libresoc.v:151531$7537 + attribute \src "libresoc.v:151327.3-151361.6" + process $proc$libresoc.v:151327$7537 assign { } { } assign { } { } assign $0\count_right[0:0] $1\count_right[0:0] - attribute \src "libresoc.v:151532.5-151532.29" + attribute \src "libresoc.v:151328.5-151328.29" switch \initial - attribute \src "libresoc.v:151532.9-151532.17" + attribute \src "libresoc.v:151328.9-151328.17" case 1'1 case end @@ -281604,14 +281438,14 @@ module \main$51 sync always update \count_right $0\count_right[0:0] end - attribute \src "libresoc.v:151566.3-151600.6" - process $proc$libresoc.v:151566$7538 + attribute \src "libresoc.v:151362.3-151396.6" + process $proc$libresoc.v:151362$7538 assign { } { } assign { } { } assign $0\a32[31:0] $1\a32[31:0] - attribute \src "libresoc.v:151567.5-151567.29" + attribute \src "libresoc.v:151363.5-151363.29" switch \initial - attribute \src "libresoc.v:151567.9-151567.17" + attribute \src "libresoc.v:151363.9-151363.17" case 1'1 case end @@ -281645,14 +281479,14 @@ module \main$51 sync always update \a32 $0\a32[31:0] end - attribute \src "libresoc.v:151601.3-151643.6" - process $proc$libresoc.v:151601$7539 + attribute \src "libresoc.v:151397.3-151439.6" + process $proc$libresoc.v:151397$7539 assign { } { } assign { } { } assign $0\cntz_i[63:0] $1\cntz_i[63:0] - attribute \src "libresoc.v:151602.5-151602.29" + attribute \src "libresoc.v:151398.5-151398.29" switch \initial - attribute \src "libresoc.v:151602.9-151602.17" + attribute \src "libresoc.v:151398.9-151398.17" case 1'1 case end @@ -281697,193 +281531,193 @@ module \main$51 sync always update \cntz_i $0\cntz_i[63:0] end - connect \$99 $eq$libresoc.v:151126$7443_Y - connect \$101 $eq$libresoc.v:151127$7444_Y - connect \$103 $eq$libresoc.v:151128$7445_Y - connect \$105 $eq$libresoc.v:151129$7446_Y - connect \$107 $eq$libresoc.v:151130$7447_Y - connect \$109 $eq$libresoc.v:151131$7448_Y - connect \$111 $eq$libresoc.v:151132$7449_Y - connect \$113 $eq$libresoc.v:151133$7450_Y - connect \$115 $eq$libresoc.v:151134$7451_Y - connect \$117 $eq$libresoc.v:151135$7452_Y - connect \$119 $eq$libresoc.v:151136$7453_Y - connect \$121 $eq$libresoc.v:151137$7454_Y - connect \$123 $eq$libresoc.v:151138$7455_Y - connect \$125 $eq$libresoc.v:151139$7456_Y - connect \$127 $eq$libresoc.v:151140$7457_Y - connect \$129 $eq$libresoc.v:151141$7458_Y - connect \$131 $eq$libresoc.v:151142$7459_Y - connect \$133 $eq$libresoc.v:151143$7460_Y - connect \$135 $eq$libresoc.v:151144$7461_Y - connect \$137 $eq$libresoc.v:151145$7462_Y - connect \$139 $eq$libresoc.v:151146$7463_Y - connect \$141 $eq$libresoc.v:151147$7464_Y - connect \$143 $eq$libresoc.v:151148$7465_Y - connect \$145 $eq$libresoc.v:151149$7466_Y - connect \$147 $eq$libresoc.v:151150$7467_Y - connect \$149 $eq$libresoc.v:151151$7468_Y - connect \$151 $eq$libresoc.v:151152$7469_Y - connect \$153 $eq$libresoc.v:151153$7470_Y - connect \$155 $eq$libresoc.v:151154$7471_Y - connect \$158 $xor$libresoc.v:151155$7472_Y - connect \$157 $pos$libresoc.v:151156$7474_Y - connect \$162 $sub$libresoc.v:151157$7475_Y - connect \$164 $pos$libresoc.v:151158$7477_Y - connect \$166 $ternary$libresoc.v:151159$7478_Y - connect \$161 $pos$libresoc.v:151160$7480_Y - connect \$169 $pos$libresoc.v:151161$7482_Y - connect \$171 $reduce_xor$libresoc.v:151162$7483_Y - connect \$173 $reduce_xor$libresoc.v:151163$7484_Y - connect \$176 $ternary$libresoc.v:151164$7485_Y - connect \$175 $pos$libresoc.v:151165$7487_Y - connect \$179 $ternary$libresoc.v:151166$7488_Y - connect \$21 $and$libresoc.v:151167$7489_Y - connect \$23 $or$libresoc.v:151168$7490_Y - connect \$25 $xor$libresoc.v:151169$7491_Y - connect \$27 $eq$libresoc.v:151170$7492_Y - connect \$29 $eq$libresoc.v:151171$7493_Y - connect \$31 $eq$libresoc.v:151172$7494_Y - connect \$33 $eq$libresoc.v:151173$7495_Y - connect \$35 $eq$libresoc.v:151174$7496_Y - connect \$37 $eq$libresoc.v:151175$7497_Y - connect \$39 $eq$libresoc.v:151176$7498_Y - connect \$41 $eq$libresoc.v:151177$7499_Y - connect \$43 $eq$libresoc.v:151178$7500_Y - connect \$45 $eq$libresoc.v:151179$7501_Y - connect \$47 $eq$libresoc.v:151180$7502_Y - connect \$49 $eq$libresoc.v:151181$7503_Y - connect \$51 $eq$libresoc.v:151182$7504_Y - connect \$53 $eq$libresoc.v:151183$7505_Y - connect \$55 $eq$libresoc.v:151184$7506_Y - connect \$57 $eq$libresoc.v:151185$7507_Y - connect \$59 $eq$libresoc.v:151186$7508_Y - connect \$61 $eq$libresoc.v:151187$7509_Y - connect \$63 $eq$libresoc.v:151188$7510_Y - connect \$65 $eq$libresoc.v:151189$7511_Y - connect \$67 $eq$libresoc.v:151190$7512_Y - connect \$69 $eq$libresoc.v:151191$7513_Y - connect \$71 $eq$libresoc.v:151192$7514_Y - connect \$73 $eq$libresoc.v:151193$7515_Y - connect \$75 $eq$libresoc.v:151194$7516_Y - connect \$77 $eq$libresoc.v:151195$7517_Y - connect \$79 $eq$libresoc.v:151196$7518_Y - connect \$81 $eq$libresoc.v:151197$7519_Y - connect \$83 $eq$libresoc.v:151198$7520_Y - connect \$85 $eq$libresoc.v:151199$7521_Y - connect \$87 $eq$libresoc.v:151200$7522_Y - connect \$89 $eq$libresoc.v:151201$7523_Y - connect \$91 $eq$libresoc.v:151202$7524_Y - connect \$93 $eq$libresoc.v:151203$7525_Y - connect \$95 $eq$libresoc.v:151204$7526_Y - connect \$97 $eq$libresoc.v:151205$7527_Y + connect \$99 $eq$libresoc.v:150922$7443_Y + connect \$101 $eq$libresoc.v:150923$7444_Y + connect \$103 $eq$libresoc.v:150924$7445_Y + connect \$105 $eq$libresoc.v:150925$7446_Y + connect \$107 $eq$libresoc.v:150926$7447_Y + connect \$109 $eq$libresoc.v:150927$7448_Y + connect \$111 $eq$libresoc.v:150928$7449_Y + connect \$113 $eq$libresoc.v:150929$7450_Y + connect \$115 $eq$libresoc.v:150930$7451_Y + connect \$117 $eq$libresoc.v:150931$7452_Y + connect \$119 $eq$libresoc.v:150932$7453_Y + connect \$121 $eq$libresoc.v:150933$7454_Y + connect \$123 $eq$libresoc.v:150934$7455_Y + connect \$125 $eq$libresoc.v:150935$7456_Y + connect \$127 $eq$libresoc.v:150936$7457_Y + connect \$129 $eq$libresoc.v:150937$7458_Y + connect \$131 $eq$libresoc.v:150938$7459_Y + connect \$133 $eq$libresoc.v:150939$7460_Y + connect \$135 $eq$libresoc.v:150940$7461_Y + connect \$137 $eq$libresoc.v:150941$7462_Y + connect \$139 $eq$libresoc.v:150942$7463_Y + connect \$141 $eq$libresoc.v:150943$7464_Y + connect \$143 $eq$libresoc.v:150944$7465_Y + connect \$145 $eq$libresoc.v:150945$7466_Y + connect \$147 $eq$libresoc.v:150946$7467_Y + connect \$149 $eq$libresoc.v:150947$7468_Y + connect \$151 $eq$libresoc.v:150948$7469_Y + connect \$153 $eq$libresoc.v:150949$7470_Y + connect \$155 $eq$libresoc.v:150950$7471_Y + connect \$158 $xor$libresoc.v:150951$7472_Y + connect \$157 $pos$libresoc.v:150952$7474_Y + connect \$162 $sub$libresoc.v:150953$7475_Y + connect \$164 $pos$libresoc.v:150954$7477_Y + connect \$166 $ternary$libresoc.v:150955$7478_Y + connect \$161 $pos$libresoc.v:150956$7480_Y + connect \$169 $pos$libresoc.v:150957$7482_Y + connect \$171 $reduce_xor$libresoc.v:150958$7483_Y + connect \$173 $reduce_xor$libresoc.v:150959$7484_Y + connect \$176 $ternary$libresoc.v:150960$7485_Y + connect \$175 $pos$libresoc.v:150961$7487_Y + connect \$179 $ternary$libresoc.v:150962$7488_Y + connect \$21 $and$libresoc.v:150963$7489_Y + connect \$23 $or$libresoc.v:150964$7490_Y + connect \$25 $xor$libresoc.v:150965$7491_Y + connect \$27 $eq$libresoc.v:150966$7492_Y + connect \$29 $eq$libresoc.v:150967$7493_Y + connect \$31 $eq$libresoc.v:150968$7494_Y + connect \$33 $eq$libresoc.v:150969$7495_Y + connect \$35 $eq$libresoc.v:150970$7496_Y + connect \$37 $eq$libresoc.v:150971$7497_Y + connect \$39 $eq$libresoc.v:150972$7498_Y + connect \$41 $eq$libresoc.v:150973$7499_Y + connect \$43 $eq$libresoc.v:150974$7500_Y + connect \$45 $eq$libresoc.v:150975$7501_Y + connect \$47 $eq$libresoc.v:150976$7502_Y + connect \$49 $eq$libresoc.v:150977$7503_Y + connect \$51 $eq$libresoc.v:150978$7504_Y + connect \$53 $eq$libresoc.v:150979$7505_Y + connect \$55 $eq$libresoc.v:150980$7506_Y + connect \$57 $eq$libresoc.v:150981$7507_Y + connect \$59 $eq$libresoc.v:150982$7508_Y + connect \$61 $eq$libresoc.v:150983$7509_Y + connect \$63 $eq$libresoc.v:150984$7510_Y + connect \$65 $eq$libresoc.v:150985$7511_Y + connect \$67 $eq$libresoc.v:150986$7512_Y + connect \$69 $eq$libresoc.v:150987$7513_Y + connect \$71 $eq$libresoc.v:150988$7514_Y + connect \$73 $eq$libresoc.v:150989$7515_Y + connect \$75 $eq$libresoc.v:150990$7516_Y + connect \$77 $eq$libresoc.v:150991$7517_Y + connect \$79 $eq$libresoc.v:150992$7518_Y + connect \$81 $eq$libresoc.v:150993$7519_Y + connect \$83 $eq$libresoc.v:150994$7520_Y + connect \$85 $eq$libresoc.v:150995$7521_Y + connect \$87 $eq$libresoc.v:150996$7522_Y + connect \$89 $eq$libresoc.v:150997$7523_Y + connect \$91 $eq$libresoc.v:150998$7524_Y + connect \$93 $eq$libresoc.v:150999$7525_Y + connect \$95 $eq$libresoc.v:151000$7526_Y + connect \$97 $eq$libresoc.v:151001$7527_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so end -attribute \src "libresoc.v:151651.1-152254.10" +attribute \src "libresoc.v:151447.1-152050.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" attribute \generator "nMigen" module \main$9 - attribute \src "libresoc.v:152041.3-152067.6" + attribute \src "libresoc.v:151837.3-151863.6" wire width 2 $0\BC[1:0] - attribute \src "libresoc.v:152135.3-152149.6" + attribute \src "libresoc.v:151931.3-151945.6" wire width 2 $0\ba[1:0] - attribute \src "libresoc.v:152150.3-152164.6" + attribute \src "libresoc.v:151946.3-151960.6" wire width 2 $0\bb[1:0] - attribute \src "libresoc.v:152165.3-152189.6" + attribute \src "libresoc.v:151961.3-151985.6" wire $0\bit_a[0:0] - attribute \src "libresoc.v:152190.3-152214.6" + attribute \src "libresoc.v:151986.3-152010.6" wire $0\bit_b[0:0] - attribute \src "libresoc.v:152215.3-152229.6" + attribute \src "libresoc.v:152011.3-152025.6" wire $0\bit_o[0:0] - attribute \src "libresoc.v:152120.3-152134.6" + attribute \src "libresoc.v:151916.3-151930.6" wire width 2 $0\bt[1:0] - attribute \src "libresoc.v:151933.3-151967.6" + attribute \src "libresoc.v:151729.3-151763.6" wire width 4 $0\cr_a$6[3:0]$7555 - attribute \src "libresoc.v:151933.3-151967.6" + attribute \src "libresoc.v:151729.3-151763.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:152068.3-152104.6" + attribute \src "libresoc.v:151864.3-151900.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:152230.3-152248.6" + attribute \src "libresoc.v:152026.3-152044.6" wire width 32 $0\full_cr$5[31:0]$7570 - attribute \src "libresoc.v:151968.3-151986.6" + attribute \src "libresoc.v:151764.3-151782.6" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:151652.7-151652.20" + attribute \src "libresoc.v:151448.7-151448.20" wire $0\initial[0:0] - attribute \src "libresoc.v:152105.3-152119.6" + attribute \src "libresoc.v:151901.3-151915.6" wire width 4 $0\lut[3:0] - attribute \src "libresoc.v:151987.3-152040.6" + attribute \src "libresoc.v:151783.3-151836.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:151987.3-152040.6" + attribute \src "libresoc.v:151783.3-151836.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:152041.3-152067.6" + attribute \src "libresoc.v:151837.3-151863.6" wire width 2 $1\BC[1:0] - attribute \src "libresoc.v:152135.3-152149.6" + attribute \src "libresoc.v:151931.3-151945.6" wire width 2 $1\ba[1:0] - attribute \src "libresoc.v:152150.3-152164.6" + attribute \src "libresoc.v:151946.3-151960.6" wire width 2 $1\bb[1:0] - attribute \src "libresoc.v:152165.3-152189.6" + attribute \src "libresoc.v:151961.3-151985.6" wire $1\bit_a[0:0] - attribute \src "libresoc.v:152190.3-152214.6" + attribute \src "libresoc.v:151986.3-152010.6" wire $1\bit_b[0:0] - attribute \src "libresoc.v:152215.3-152229.6" + attribute \src "libresoc.v:152011.3-152025.6" wire $1\bit_o[0:0] - attribute \src "libresoc.v:152120.3-152134.6" + attribute \src "libresoc.v:151916.3-151930.6" wire width 2 $1\bt[1:0] - attribute \src "libresoc.v:151933.3-151967.6" + attribute \src "libresoc.v:151729.3-151763.6" wire width 4 $1\cr_a$6[3:0]$7556 - attribute \src "libresoc.v:151933.3-151967.6" + attribute \src "libresoc.v:151729.3-151763.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:152068.3-152104.6" + attribute \src "libresoc.v:151864.3-151900.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:152230.3-152248.6" + attribute \src "libresoc.v:152026.3-152044.6" wire width 32 $1\full_cr$5[31:0]$7571 - attribute \src "libresoc.v:151968.3-151986.6" + attribute \src "libresoc.v:151764.3-151782.6" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:152105.3-152119.6" + attribute \src "libresoc.v:151901.3-151915.6" wire width 4 $1\lut[3:0] - attribute \src "libresoc.v:151987.3-152040.6" + attribute \src "libresoc.v:151783.3-151836.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:151987.3-152040.6" + attribute \src "libresoc.v:151783.3-151836.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:152165.3-152189.6" + attribute \src "libresoc.v:151961.3-151985.6" wire $2\bit_a[0:0] - attribute \src "libresoc.v:152190.3-152214.6" + attribute \src "libresoc.v:151986.3-152010.6" wire $2\bit_b[0:0] - attribute \src "libresoc.v:151933.3-151967.6" + attribute \src "libresoc.v:151729.3-151763.6" wire width 4 $2\cr_a$6[3:0]$7557 - attribute \src "libresoc.v:152068.3-152104.6" + attribute \src "libresoc.v:151864.3-151900.6" wire $2\cr_bit[0:0] - attribute \src "libresoc.v:151987.3-152040.6" + attribute \src "libresoc.v:151783.3-151836.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:151929.18-151929.96" - wire width 64 $extend$libresoc.v:151929$7547_Y - attribute \src "libresoc.v:151931.18-151931.98" - wire width 65 $extend$libresoc.v:151931$7550_Y - attribute \src "libresoc.v:151932.17-151932.92" - wire width 5 $extend$libresoc.v:151932$7552_Y - attribute \src "libresoc.v:151929.18-151929.96" - wire width 64 $pos$libresoc.v:151929$7548_Y - attribute \src "libresoc.v:151931.18-151931.98" - wire width 65 $pos$libresoc.v:151931$7551_Y - attribute \src "libresoc.v:151932.17-151932.92" - wire width 5 $pos$libresoc.v:151932$7553_Y - attribute \src "libresoc.v:151923.18-151923.116" - wire width 3 $sub$libresoc.v:151923$7541_Y - attribute \src "libresoc.v:151924.18-151924.116" - wire width 3 $sub$libresoc.v:151924$7542_Y - attribute \src "libresoc.v:151925.18-151925.116" - wire width 3 $sub$libresoc.v:151925$7543_Y - attribute \src "libresoc.v:151926.18-151926.114" - wire $ternary$libresoc.v:151926$7544_Y - attribute \src "libresoc.v:151927.18-151927.115" - wire $ternary$libresoc.v:151927$7545_Y - attribute \src "libresoc.v:151928.18-151928.112" - wire $ternary$libresoc.v:151928$7546_Y - attribute \src "libresoc.v:151930.18-151930.108" - wire width 64 $ternary$libresoc.v:151930$7549_Y + attribute \src "libresoc.v:151725.18-151725.96" + wire width 64 $extend$libresoc.v:151725$7547_Y + attribute \src "libresoc.v:151727.18-151727.98" + wire width 65 $extend$libresoc.v:151727$7550_Y + attribute \src "libresoc.v:151728.17-151728.92" + wire width 5 $extend$libresoc.v:151728$7552_Y + attribute \src "libresoc.v:151725.18-151725.96" + wire width 64 $pos$libresoc.v:151725$7548_Y + attribute \src "libresoc.v:151727.18-151727.98" + wire width 65 $pos$libresoc.v:151727$7551_Y + attribute \src "libresoc.v:151728.17-151728.92" + wire width 5 $pos$libresoc.v:151728$7553_Y + attribute \src "libresoc.v:151719.18-151719.116" + wire width 3 $sub$libresoc.v:151719$7541_Y + attribute \src "libresoc.v:151720.18-151720.116" + wire width 3 $sub$libresoc.v:151720$7542_Y + attribute \src "libresoc.v:151721.18-151721.116" + wire width 3 $sub$libresoc.v:151721$7543_Y + attribute \src "libresoc.v:151722.18-151722.114" + wire $ternary$libresoc.v:151722$7544_Y + attribute \src "libresoc.v:151723.18-151723.115" + wire $ternary$libresoc.v:151723$7545_Y + attribute \src "libresoc.v:151724.18-151724.112" + wire $ternary$libresoc.v:151724$7546_Y + attribute \src "libresoc.v:151726.18-151726.108" + wire width 64 $ternary$libresoc.v:151726$7549_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" wire width 3 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" @@ -282134,7 +281968,7 @@ module \main$9 wire width 32 output 16 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \full_cr_ok - attribute \src "libresoc.v:151652.7-151652.15" + attribute \src "libresoc.v:151448.7-151448.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" wire width 4 \lut @@ -282151,55 +281985,55 @@ module \main$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151929$7547 + cell $pos $extend$libresoc.v:151725$7547 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \full_cr - connect \Y $extend$libresoc.v:151929$7547_Y + connect \Y $extend$libresoc.v:151725$7547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$libresoc.v:151931$7550 + cell $pos $extend$libresoc.v:151727$7550 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$27 - connect \Y $extend$libresoc.v:151931$7550_Y + connect \Y $extend$libresoc.v:151727$7550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151932$7552 + cell $pos $extend$libresoc.v:151728$7552 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 5 connect \A \cr_a - connect \Y $extend$libresoc.v:151932$7552_Y + connect \Y $extend$libresoc.v:151728$7552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151929$7548 + cell $pos $pos$libresoc.v:151725$7548 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:151929$7547_Y - connect \Y $pos$libresoc.v:151929$7548_Y + connect \A $extend$libresoc.v:151725$7547_Y + connect \Y $pos$libresoc.v:151725$7548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$libresoc.v:151931$7551 + cell $pos $pos$libresoc.v:151727$7551 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151931$7550_Y - connect \Y $pos$libresoc.v:151931$7551_Y + connect \A $extend$libresoc.v:151727$7550_Y + connect \Y $pos$libresoc.v:151727$7551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151932$7553 + cell $pos $pos$libresoc.v:151728$7553 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $extend$libresoc.v:151932$7552_Y - connect \Y $pos$libresoc.v:151932$7553_Y + connect \A $extend$libresoc.v:151728$7552_Y + connect \Y $pos$libresoc.v:151728$7553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$libresoc.v:151923$7541 + cell $sub $sub$libresoc.v:151719$7541 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -282207,10 +282041,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [22:21] - connect \Y $sub$libresoc.v:151923$7541_Y + connect \Y $sub$libresoc.v:151719$7541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$libresoc.v:151924$7542 + cell $sub $sub$libresoc.v:151720$7542 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -282218,10 +282052,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [17:16] - connect \Y $sub$libresoc.v:151924$7542_Y + connect \Y $sub$libresoc.v:151720$7542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$libresoc.v:151925$7543 + cell $sub $sub$libresoc.v:151721$7543 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -282229,59 +282063,59 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [12:11] - connect \Y $sub$libresoc.v:151925$7543_Y + connect \Y $sub$libresoc.v:151721$7543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$libresoc.v:151926$7544 + cell $mux $ternary$libresoc.v:151722$7544 parameter \WIDTH 1 connect \A \lut [1] connect \B \lut [3] connect \S \bit_a - connect \Y $ternary$libresoc.v:151926$7544_Y + connect \Y $ternary$libresoc.v:151722$7544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:151927$7545 + cell $mux $ternary$libresoc.v:151723$7545 parameter \WIDTH 1 connect \A \lut [0] connect \B \lut [2] connect \S \bit_a - connect \Y $ternary$libresoc.v:151927$7545_Y + connect \Y $ternary$libresoc.v:151723$7545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:151928$7546 + cell $mux $ternary$libresoc.v:151724$7546 parameter \WIDTH 1 connect \A \$20 connect \B \$18 connect \S \bit_b - connect \Y $ternary$libresoc.v:151928$7546_Y + connect \Y $ternary$libresoc.v:151724$7546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$libresoc.v:151930$7549 + cell $mux $ternary$libresoc.v:151726$7549 parameter \WIDTH 64 connect \A \rb connect \B \ra connect \S \cr_bit - connect \Y $ternary$libresoc.v:151930$7549_Y + connect \Y $ternary$libresoc.v:151726$7549_Y end - attribute \src "libresoc.v:151652.7-151652.20" - process $proc$libresoc.v:151652$7572 + attribute \src "libresoc.v:151448.7-151448.20" + process $proc$libresoc.v:151448$7572 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151933.3-151967.6" - process $proc$libresoc.v:151933$7554 + attribute \src "libresoc.v:151729.3-151763.6" + process $proc$libresoc.v:151729$7554 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] assign $0\cr_a$6[3:0]$7555 $1\cr_a$6[3:0]$7556 - attribute \src "libresoc.v:151934.5-151934.29" + attribute \src "libresoc.v:151730.5-151730.29" switch \initial - attribute \src "libresoc.v:151934.9-151934.17" + attribute \src "libresoc.v:151730.9-151730.17" case 1'1 case end @@ -282329,14 +282163,14 @@ module \main$9 update \cr_a_ok $0\cr_a_ok[0:0] update \cr_a$6 $0\cr_a$6[3:0]$7555 end - attribute \src "libresoc.v:151968.3-151986.6" - process $proc$libresoc.v:151968$7558 + attribute \src "libresoc.v:151764.3-151782.6" + process $proc$libresoc.v:151764$7558 assign { } { } assign { } { } assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "libresoc.v:151969.5-151969.29" + attribute \src "libresoc.v:151765.5-151765.29" switch \initial - attribute \src "libresoc.v:151969.9-151969.17" + attribute \src "libresoc.v:151765.9-151765.17" case 1'1 case end @@ -282358,17 +282192,17 @@ module \main$9 sync always update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:151987.3-152040.6" - process $proc$libresoc.v:151987$7559 + attribute \src "libresoc.v:151783.3-151836.6" + process $proc$libresoc.v:151783$7559 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:151988.5-151988.29" + attribute \src "libresoc.v:151784.5-151784.29" switch \initial - attribute \src "libresoc.v:151988.9-151988.17" + attribute \src "libresoc.v:151784.9-151784.17" case 1'1 case end @@ -282427,14 +282261,14 @@ module \main$9 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:152041.3-152067.6" - process $proc$libresoc.v:152041$7560 + attribute \src "libresoc.v:151837.3-151863.6" + process $proc$libresoc.v:151837$7560 assign { } { } assign { } { } assign $0\BC[1:0] $1\BC[1:0] - attribute \src "libresoc.v:152042.5-152042.29" + attribute \src "libresoc.v:151838.5-151838.29" switch \initial - attribute \src "libresoc.v:152042.9-152042.17" + attribute \src "libresoc.v:151838.9-151838.17" case 1'1 case end @@ -282462,14 +282296,14 @@ module \main$9 sync always update \BC $0\BC[1:0] end - attribute \src "libresoc.v:152068.3-152104.6" - process $proc$libresoc.v:152068$7561 + attribute \src "libresoc.v:151864.3-151900.6" + process $proc$libresoc.v:151864$7561 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:152069.5-152069.29" + attribute \src "libresoc.v:151865.5-151865.29" switch \initial - attribute \src "libresoc.v:152069.9-152069.17" + attribute \src "libresoc.v:151865.9-151865.17" case 1'1 case end @@ -282518,14 +282352,14 @@ module \main$9 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:152105.3-152119.6" - process $proc$libresoc.v:152105$7562 + attribute \src "libresoc.v:151901.3-151915.6" + process $proc$libresoc.v:151901$7562 assign { } { } assign { } { } assign $0\lut[3:0] $1\lut[3:0] - attribute \src "libresoc.v:152106.5-152106.29" + attribute \src "libresoc.v:151902.5-151902.29" switch \initial - attribute \src "libresoc.v:152106.9-152106.17" + attribute \src "libresoc.v:151902.9-151902.17" case 1'1 case end @@ -282544,14 +282378,14 @@ module \main$9 sync always update \lut $0\lut[3:0] end - attribute \src "libresoc.v:152120.3-152134.6" - process $proc$libresoc.v:152120$7563 + attribute \src "libresoc.v:151916.3-151930.6" + process $proc$libresoc.v:151916$7563 assign { } { } assign { } { } assign $0\bt[1:0] $1\bt[1:0] - attribute \src "libresoc.v:152121.5-152121.29" + attribute \src "libresoc.v:151917.5-151917.29" switch \initial - attribute \src "libresoc.v:152121.9-152121.17" + attribute \src "libresoc.v:151917.9-151917.17" case 1'1 case end @@ -282570,14 +282404,14 @@ module \main$9 sync always update \bt $0\bt[1:0] end - attribute \src "libresoc.v:152135.3-152149.6" - process $proc$libresoc.v:152135$7564 + attribute \src "libresoc.v:151931.3-151945.6" + process $proc$libresoc.v:151931$7564 assign { } { } assign { } { } assign $0\ba[1:0] $1\ba[1:0] - attribute \src "libresoc.v:152136.5-152136.29" + attribute \src "libresoc.v:151932.5-151932.29" switch \initial - attribute \src "libresoc.v:152136.9-152136.17" + attribute \src "libresoc.v:151932.9-151932.17" case 1'1 case end @@ -282596,14 +282430,14 @@ module \main$9 sync always update \ba $0\ba[1:0] end - attribute \src "libresoc.v:152150.3-152164.6" - process $proc$libresoc.v:152150$7565 + attribute \src "libresoc.v:151946.3-151960.6" + process $proc$libresoc.v:151946$7565 assign { } { } assign { } { } assign $0\bb[1:0] $1\bb[1:0] - attribute \src "libresoc.v:152151.5-152151.29" + attribute \src "libresoc.v:151947.5-151947.29" switch \initial - attribute \src "libresoc.v:152151.9-152151.17" + attribute \src "libresoc.v:151947.9-151947.17" case 1'1 case end @@ -282622,14 +282456,14 @@ module \main$9 sync always update \bb $0\bb[1:0] end - attribute \src "libresoc.v:152165.3-152189.6" - process $proc$libresoc.v:152165$7566 + attribute \src "libresoc.v:151961.3-151985.6" + process $proc$libresoc.v:151961$7566 assign { } { } assign { } { } assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "libresoc.v:152166.5-152166.29" + attribute \src "libresoc.v:151962.5-151962.29" switch \initial - attribute \src "libresoc.v:152166.9-152166.17" + attribute \src "libresoc.v:151962.9-151962.17" case 1'1 case end @@ -282669,14 +282503,14 @@ module \main$9 sync always update \bit_a $0\bit_a[0:0] end - attribute \src "libresoc.v:152190.3-152214.6" - process $proc$libresoc.v:152190$7567 + attribute \src "libresoc.v:151986.3-152010.6" + process $proc$libresoc.v:151986$7567 assign { } { } assign { } { } assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "libresoc.v:152191.5-152191.29" + attribute \src "libresoc.v:151987.5-151987.29" switch \initial - attribute \src "libresoc.v:152191.9-152191.17" + attribute \src "libresoc.v:151987.9-151987.17" case 1'1 case end @@ -282716,14 +282550,14 @@ module \main$9 sync always update \bit_b $0\bit_b[0:0] end - attribute \src "libresoc.v:152215.3-152229.6" - process $proc$libresoc.v:152215$7568 + attribute \src "libresoc.v:152011.3-152025.6" + process $proc$libresoc.v:152011$7568 assign { } { } assign { } { } assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "libresoc.v:152216.5-152216.29" + attribute \src "libresoc.v:152012.5-152012.29" switch \initial - attribute \src "libresoc.v:152216.9-152216.17" + attribute \src "libresoc.v:152012.9-152012.17" case 1'1 case end @@ -282742,14 +282576,14 @@ module \main$9 sync always update \bit_o $0\bit_o[0:0] end - attribute \src "libresoc.v:152230.3-152248.6" - process $proc$libresoc.v:152230$7569 + attribute \src "libresoc.v:152026.3-152044.6" + process $proc$libresoc.v:152026$7569 assign { } { } assign { } { } assign $0\full_cr$5[31:0]$7570 $1\full_cr$5[31:0]$7571 - attribute \src "libresoc.v:152231.5-152231.29" + attribute \src "libresoc.v:152027.5-152027.29" switch \initial - attribute \src "libresoc.v:152231.9-152231.17" + attribute \src "libresoc.v:152027.9-152027.17" case 1'1 case end @@ -282771,501 +282605,501 @@ module \main$9 sync always update \full_cr$5 $0\full_cr$5[31:0]$7570 end - connect \$10 $sub$libresoc.v:151923$7541_Y - connect \$13 $sub$libresoc.v:151924$7542_Y - connect \$16 $sub$libresoc.v:151925$7543_Y - connect \$18 $ternary$libresoc.v:151926$7544_Y - connect \$20 $ternary$libresoc.v:151927$7545_Y - connect \$22 $ternary$libresoc.v:151928$7546_Y - connect \$24 $pos$libresoc.v:151929$7548_Y - connect \$27 $ternary$libresoc.v:151930$7549_Y - connect \$26 $pos$libresoc.v:151931$7551_Y - connect \$7 $pos$libresoc.v:151932$7553_Y + connect \$10 $sub$libresoc.v:151719$7541_Y + connect \$13 $sub$libresoc.v:151720$7542_Y + connect \$16 $sub$libresoc.v:151721$7543_Y + connect \$18 $ternary$libresoc.v:151722$7544_Y + connect \$20 $ternary$libresoc.v:151723$7545_Y + connect \$22 $ternary$libresoc.v:151724$7546_Y + connect \$24 $pos$libresoc.v:151725$7548_Y + connect \$27 $ternary$libresoc.v:151726$7549_Y + connect \$26 $pos$libresoc.v:151727$7551_Y + connect \$7 $pos$libresoc.v:151728$7553_Y connect \$9 \$10 connect \$12 \$13 connect \$15 \$16 connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:152258.1-153419.10" +attribute \src "libresoc.v:152054.1-153215.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" attribute \generator "nMigen" module \mul0 - attribute \src "libresoc.v:152990.3-152991.25" + attribute \src "libresoc.v:152786.3-152787.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:152988.3-152989.40" + attribute \src "libresoc.v:152784.3-152785.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:153331.3-153339.6" + attribute \src "libresoc.v:153127.3-153135.6" wire $0\alu_l_r_alu$next[0:0]$7778 - attribute \src "libresoc.v:152916.3-152917.39" + attribute \src "libresoc.v:152712.3-152713.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7703 - attribute \src "libresoc.v:152944.3-152945.65" + attribute \src "libresoc.v:152740.3-152741.65" wire width 14 $0\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7704 - attribute \src "libresoc.v:152946.3-152947.79" + attribute \src "libresoc.v:152742.3-152743.79" wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7705 - attribute \src "libresoc.v:152948.3-152949.75" + attribute \src "libresoc.v:152744.3-152745.75" wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7706 - attribute \src "libresoc.v:152964.3-152965.59" + attribute \src "libresoc.v:152760.3-152761.59" wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7707 - attribute \src "libresoc.v:152942.3-152943.69" + attribute \src "libresoc.v:152738.3-152739.69" wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7708 - attribute \src "libresoc.v:152960.3-152961.67" + attribute \src "libresoc.v:152756.3-152757.67" wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7709 - attribute \src "libresoc.v:152962.3-152963.69" + attribute \src "libresoc.v:152758.3-152759.69" wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7710 - attribute \src "libresoc.v:152954.3-152955.63" + attribute \src "libresoc.v:152750.3-152751.63" wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7711 - attribute \src "libresoc.v:152956.3-152957.63" + attribute \src "libresoc.v:152752.3-152753.63" wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7712 - attribute \src "libresoc.v:152952.3-152953.63" + attribute \src "libresoc.v:152748.3-152749.63" wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713 - attribute \src "libresoc.v:152950.3-152951.63" + attribute \src "libresoc.v:152746.3-152747.63" wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7714 - attribute \src "libresoc.v:152958.3-152959.69" + attribute \src "libresoc.v:152754.3-152755.69" wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:153322.3-153330.6" + attribute \src "libresoc.v:153118.3-153126.6" wire $0\alui_l_r_alui$next[0:0]$7775 - attribute \src "libresoc.v:152918.3-152919.43" + attribute \src "libresoc.v:152714.3-152715.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:153204.3-153225.6" + attribute \src "libresoc.v:153000.3-153021.6" wire width 64 $0\data_r0__o$next[63:0]$7734 - attribute \src "libresoc.v:152938.3-152939.37" + attribute \src "libresoc.v:152734.3-152735.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:153204.3-153225.6" + attribute \src "libresoc.v:153000.3-153021.6" wire $0\data_r0__o_ok$next[0:0]$7735 - attribute \src "libresoc.v:152940.3-152941.43" + attribute \src "libresoc.v:152736.3-152737.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:153226.3-153247.6" + attribute \src "libresoc.v:153022.3-153043.6" wire width 4 $0\data_r1__cr_a$next[3:0]$7742 - attribute \src "libresoc.v:152934.3-152935.43" + attribute \src "libresoc.v:152730.3-152731.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:153226.3-153247.6" + attribute \src "libresoc.v:153022.3-153043.6" wire $0\data_r1__cr_a_ok$next[0:0]$7743 - attribute \src "libresoc.v:152936.3-152937.49" + attribute \src "libresoc.v:152732.3-152733.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:153248.3-153269.6" + attribute \src "libresoc.v:153044.3-153065.6" wire width 2 $0\data_r2__xer_ov$next[1:0]$7750 - attribute \src "libresoc.v:152930.3-152931.47" + attribute \src "libresoc.v:152726.3-152727.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:153248.3-153269.6" + attribute \src "libresoc.v:153044.3-153065.6" wire $0\data_r2__xer_ov_ok$next[0:0]$7751 - attribute \src "libresoc.v:152932.3-152933.53" + attribute \src "libresoc.v:152728.3-152729.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:153270.3-153291.6" + attribute \src "libresoc.v:153066.3-153087.6" wire $0\data_r3__xer_so$next[0:0]$7758 - attribute \src "libresoc.v:152926.3-152927.47" + attribute \src "libresoc.v:152722.3-152723.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:153270.3-153291.6" + attribute \src "libresoc.v:153066.3-153087.6" wire $0\data_r3__xer_so_ok$next[0:0]$7759 - attribute \src "libresoc.v:152928.3-152929.53" + attribute \src "libresoc.v:152724.3-152725.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:153340.3-153349.6" + attribute \src "libresoc.v:153136.3-153145.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:153350.3-153359.6" + attribute \src "libresoc.v:153146.3-153155.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:153360.3-153369.6" + attribute \src "libresoc.v:153156.3-153165.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:153370.3-153379.6" + attribute \src "libresoc.v:153166.3-153175.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:152259.7-152259.20" + attribute \src "libresoc.v:152055.7-152055.20" wire $0\initial[0:0] - attribute \src "libresoc.v:153126.3-153134.6" + attribute \src "libresoc.v:152922.3-152930.6" wire $0\opc_l_r_opc$next[0:0]$7688 - attribute \src "libresoc.v:152974.3-152975.39" + attribute \src "libresoc.v:152770.3-152771.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:153117.3-153125.6" + attribute \src "libresoc.v:152913.3-152921.6" wire $0\opc_l_s_opc$next[0:0]$7685 - attribute \src "libresoc.v:152976.3-152977.39" + attribute \src "libresoc.v:152772.3-152773.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:153380.3-153388.6" + attribute \src "libresoc.v:153176.3-153184.6" wire width 4 $0\prev_wr_go$next[3:0]$7785 - attribute \src "libresoc.v:152986.3-152987.37" + attribute \src "libresoc.v:152782.3-152783.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:153071.3-153080.6" + attribute \src "libresoc.v:152867.3-152876.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:153162.3-153170.6" + attribute \src "libresoc.v:152958.3-152966.6" wire width 4 $0\req_l_r_req$next[3:0]$7700 - attribute \src "libresoc.v:152966.3-152967.39" + attribute \src "libresoc.v:152762.3-152763.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:153153.3-153161.6" + attribute \src "libresoc.v:152949.3-152957.6" wire width 4 $0\req_l_s_req$next[3:0]$7697 - attribute \src "libresoc.v:152968.3-152969.39" + attribute \src "libresoc.v:152764.3-152765.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:153090.3-153098.6" + attribute \src "libresoc.v:152886.3-152894.6" wire $0\rok_l_r_rdok$next[0:0]$7676 - attribute \src "libresoc.v:152982.3-152983.41" + attribute \src "libresoc.v:152778.3-152779.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:153081.3-153089.6" + attribute \src "libresoc.v:152877.3-152885.6" wire $0\rok_l_s_rdok$next[0:0]$7673 - attribute \src "libresoc.v:152984.3-152985.41" + attribute \src "libresoc.v:152780.3-152781.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:153108.3-153116.6" + attribute \src "libresoc.v:152904.3-152912.6" wire $0\rst_l_r_rst$next[0:0]$7682 - attribute \src "libresoc.v:152978.3-152979.39" + attribute \src "libresoc.v:152774.3-152775.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:153099.3-153107.6" + attribute \src "libresoc.v:152895.3-152903.6" wire $0\rst_l_s_rst$next[0:0]$7679 - attribute \src "libresoc.v:152980.3-152981.39" + attribute \src "libresoc.v:152776.3-152777.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:153144.3-153152.6" + attribute \src "libresoc.v:152940.3-152948.6" wire width 3 $0\src_l_r_src$next[2:0]$7694 - attribute \src "libresoc.v:152970.3-152971.39" + attribute \src "libresoc.v:152766.3-152767.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:153135.3-153143.6" + attribute \src "libresoc.v:152931.3-152939.6" wire width 3 $0\src_l_s_src$next[2:0]$7691 - attribute \src "libresoc.v:152972.3-152973.39" + attribute \src "libresoc.v:152768.3-152769.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:153292.3-153301.6" + attribute \src "libresoc.v:153088.3-153097.6" wire width 64 $0\src_r0$next[63:0]$7766 - attribute \src "libresoc.v:152924.3-152925.29" + attribute \src "libresoc.v:152720.3-152721.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:153302.3-153311.6" + attribute \src "libresoc.v:153098.3-153107.6" wire width 64 $0\src_r1$next[63:0]$7769 - attribute \src "libresoc.v:152922.3-152923.29" + attribute \src "libresoc.v:152718.3-152719.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:153312.3-153321.6" + attribute \src "libresoc.v:153108.3-153117.6" wire $0\src_r2$next[0:0]$7772 - attribute \src "libresoc.v:152920.3-152921.29" + attribute \src "libresoc.v:152716.3-152717.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:152383.7-152383.24" + attribute \src "libresoc.v:152179.7-152179.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:152393.7-152393.26" + attribute \src "libresoc.v:152189.7-152189.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:153331.3-153339.6" + attribute \src "libresoc.v:153127.3-153135.6" wire $1\alu_l_r_alu$next[0:0]$7779 - attribute \src "libresoc.v:152401.7-152401.25" + attribute \src "libresoc.v:152197.7-152197.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715 - attribute \src "libresoc.v:152424.14-152424.49" + attribute \src "libresoc.v:152220.14-152220.49" wire width 14 $1\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716 - attribute \src "libresoc.v:152428.14-152428.68" + attribute \src "libresoc.v:152224.14-152224.68" wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717 - attribute \src "libresoc.v:152432.7-152432.43" + attribute \src "libresoc.v:152228.7-152228.43" wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7718 - attribute \src "libresoc.v:152436.14-152436.43" + attribute \src "libresoc.v:152232.14-152232.43" wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7719 - attribute \src "libresoc.v:152515.13-152515.47" + attribute \src "libresoc.v:152311.13-152311.47" wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720 - attribute \src "libresoc.v:152519.7-152519.39" + attribute \src "libresoc.v:152315.7-152315.39" wire $1\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7721 - attribute \src "libresoc.v:152523.7-152523.40" + attribute \src "libresoc.v:152319.7-152319.40" wire $1\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722 - attribute \src "libresoc.v:152527.7-152527.37" + attribute \src "libresoc.v:152323.7-152323.37" wire $1\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723 - attribute \src "libresoc.v:152531.7-152531.37" + attribute \src "libresoc.v:152327.7-152327.37" wire $1\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724 - attribute \src "libresoc.v:152535.7-152535.37" + attribute \src "libresoc.v:152331.7-152331.37" wire $1\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725 - attribute \src "libresoc.v:152539.7-152539.37" + attribute \src "libresoc.v:152335.7-152335.37" wire $1\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726 - attribute \src "libresoc.v:152543.7-152543.40" + attribute \src "libresoc.v:152339.7-152339.40" wire $1\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:153322.3-153330.6" + attribute \src "libresoc.v:153118.3-153126.6" wire $1\alui_l_r_alui$next[0:0]$7776 - attribute \src "libresoc.v:152573.7-152573.27" + attribute \src "libresoc.v:152369.7-152369.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:153204.3-153225.6" + attribute \src "libresoc.v:153000.3-153021.6" wire width 64 $1\data_r0__o$next[63:0]$7736 - attribute \src "libresoc.v:152607.14-152607.47" + attribute \src "libresoc.v:152403.14-152403.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:153204.3-153225.6" + attribute \src "libresoc.v:153000.3-153021.6" wire $1\data_r0__o_ok$next[0:0]$7737 - attribute \src "libresoc.v:152611.7-152611.27" + attribute \src "libresoc.v:152407.7-152407.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:153226.3-153247.6" + attribute \src "libresoc.v:153022.3-153043.6" wire width 4 $1\data_r1__cr_a$next[3:0]$7744 - attribute \src "libresoc.v:152615.13-152615.33" + attribute \src "libresoc.v:152411.13-152411.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:153226.3-153247.6" + attribute \src "libresoc.v:153022.3-153043.6" wire $1\data_r1__cr_a_ok$next[0:0]$7745 - attribute \src "libresoc.v:152619.7-152619.30" + attribute \src "libresoc.v:152415.7-152415.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:153248.3-153269.6" + attribute \src "libresoc.v:153044.3-153065.6" wire width 2 $1\data_r2__xer_ov$next[1:0]$7752 - attribute \src "libresoc.v:152623.13-152623.35" + attribute \src "libresoc.v:152419.13-152419.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:153248.3-153269.6" + attribute \src "libresoc.v:153044.3-153065.6" wire $1\data_r2__xer_ov_ok$next[0:0]$7753 - attribute \src "libresoc.v:152627.7-152627.32" + attribute \src "libresoc.v:152423.7-152423.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:153270.3-153291.6" + attribute \src "libresoc.v:153066.3-153087.6" wire $1\data_r3__xer_so$next[0:0]$7760 - attribute \src "libresoc.v:152631.7-152631.29" + attribute \src "libresoc.v:152427.7-152427.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:153270.3-153291.6" + attribute \src "libresoc.v:153066.3-153087.6" wire $1\data_r3__xer_so_ok$next[0:0]$7761 - attribute \src "libresoc.v:152635.7-152635.32" + attribute \src "libresoc.v:152431.7-152431.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:153340.3-153349.6" + attribute \src "libresoc.v:153136.3-153145.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:153350.3-153359.6" + attribute \src "libresoc.v:153146.3-153155.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:153360.3-153369.6" + attribute \src "libresoc.v:153156.3-153165.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:153370.3-153379.6" + attribute \src "libresoc.v:153166.3-153175.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:153126.3-153134.6" + attribute \src "libresoc.v:152922.3-152930.6" wire $1\opc_l_r_opc$next[0:0]$7689 - attribute \src "libresoc.v:152655.7-152655.25" + attribute \src "libresoc.v:152451.7-152451.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:153117.3-153125.6" + attribute \src "libresoc.v:152913.3-152921.6" wire $1\opc_l_s_opc$next[0:0]$7686 - attribute \src "libresoc.v:152659.7-152659.25" + attribute \src "libresoc.v:152455.7-152455.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:153380.3-153388.6" + attribute \src "libresoc.v:153176.3-153184.6" wire width 4 $1\prev_wr_go$next[3:0]$7786 - attribute \src "libresoc.v:152777.13-152777.30" + attribute \src "libresoc.v:152573.13-152573.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:153071.3-153080.6" + attribute \src "libresoc.v:152867.3-152876.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:153162.3-153170.6" + attribute \src "libresoc.v:152958.3-152966.6" wire width 4 $1\req_l_r_req$next[3:0]$7701 - attribute \src "libresoc.v:152785.13-152785.31" + attribute \src "libresoc.v:152581.13-152581.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:153153.3-153161.6" + attribute \src "libresoc.v:152949.3-152957.6" wire width 4 $1\req_l_s_req$next[3:0]$7698 - attribute \src "libresoc.v:152789.13-152789.31" + attribute \src "libresoc.v:152585.13-152585.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:153090.3-153098.6" + attribute \src "libresoc.v:152886.3-152894.6" wire $1\rok_l_r_rdok$next[0:0]$7677 - attribute \src "libresoc.v:152801.7-152801.26" + attribute \src "libresoc.v:152597.7-152597.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:153081.3-153089.6" + attribute \src "libresoc.v:152877.3-152885.6" wire $1\rok_l_s_rdok$next[0:0]$7674 - attribute \src "libresoc.v:152805.7-152805.26" + attribute \src "libresoc.v:152601.7-152601.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:153108.3-153116.6" + attribute \src "libresoc.v:152904.3-152912.6" wire $1\rst_l_r_rst$next[0:0]$7683 - attribute \src "libresoc.v:152809.7-152809.25" + attribute \src "libresoc.v:152605.7-152605.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:153099.3-153107.6" + attribute \src "libresoc.v:152895.3-152903.6" wire $1\rst_l_s_rst$next[0:0]$7680 - attribute \src "libresoc.v:152813.7-152813.25" + attribute \src "libresoc.v:152609.7-152609.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:153144.3-153152.6" + attribute \src "libresoc.v:152940.3-152948.6" wire width 3 $1\src_l_r_src$next[2:0]$7695 - attribute \src "libresoc.v:152827.13-152827.31" + attribute \src "libresoc.v:152623.13-152623.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:153135.3-153143.6" + attribute \src "libresoc.v:152931.3-152939.6" wire width 3 $1\src_l_s_src$next[2:0]$7692 - attribute \src "libresoc.v:152831.13-152831.31" + attribute \src "libresoc.v:152627.13-152627.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:153292.3-153301.6" + attribute \src "libresoc.v:153088.3-153097.6" wire width 64 $1\src_r0$next[63:0]$7767 - attribute \src "libresoc.v:152837.14-152837.43" + attribute \src "libresoc.v:152633.14-152633.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:153302.3-153311.6" + attribute \src "libresoc.v:153098.3-153107.6" wire width 64 $1\src_r1$next[63:0]$7770 - attribute \src "libresoc.v:152841.14-152841.43" + attribute \src "libresoc.v:152637.14-152637.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:153312.3-153321.6" + attribute \src "libresoc.v:153108.3-153117.6" wire $1\src_r2$next[0:0]$7773 - attribute \src "libresoc.v:152845.7-152845.20" + attribute \src "libresoc.v:152641.7-152641.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727 - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728 - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729 - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 - attribute \src "libresoc.v:153171.3-153203.6" + attribute \src "libresoc.v:152967.3-152999.6" wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 - attribute \src "libresoc.v:153204.3-153225.6" + attribute \src "libresoc.v:153000.3-153021.6" wire width 64 $2\data_r0__o$next[63:0]$7738 - attribute \src "libresoc.v:153204.3-153225.6" + attribute \src "libresoc.v:153000.3-153021.6" wire $2\data_r0__o_ok$next[0:0]$7739 - attribute \src "libresoc.v:153226.3-153247.6" + attribute \src "libresoc.v:153022.3-153043.6" wire width 4 $2\data_r1__cr_a$next[3:0]$7746 - attribute \src "libresoc.v:153226.3-153247.6" + attribute \src "libresoc.v:153022.3-153043.6" wire $2\data_r1__cr_a_ok$next[0:0]$7747 - attribute \src "libresoc.v:153248.3-153269.6" + attribute \src "libresoc.v:153044.3-153065.6" wire width 2 $2\data_r2__xer_ov$next[1:0]$7754 - attribute \src "libresoc.v:153248.3-153269.6" + attribute \src "libresoc.v:153044.3-153065.6" wire $2\data_r2__xer_ov_ok$next[0:0]$7755 - attribute \src "libresoc.v:153270.3-153291.6" + attribute \src "libresoc.v:153066.3-153087.6" wire $2\data_r3__xer_so$next[0:0]$7762 - attribute \src "libresoc.v:153270.3-153291.6" + attribute \src "libresoc.v:153066.3-153087.6" wire $2\data_r3__xer_so_ok$next[0:0]$7763 - attribute \src "libresoc.v:153204.3-153225.6" + attribute \src "libresoc.v:153000.3-153021.6" wire $3\data_r0__o_ok$next[0:0]$7740 - attribute \src "libresoc.v:153226.3-153247.6" + attribute \src "libresoc.v:153022.3-153043.6" wire $3\data_r1__cr_a_ok$next[0:0]$7748 - attribute \src "libresoc.v:153248.3-153269.6" + attribute \src "libresoc.v:153044.3-153065.6" wire $3\data_r2__xer_ov_ok$next[0:0]$7756 - attribute \src "libresoc.v:153270.3-153291.6" + attribute \src "libresoc.v:153066.3-153087.6" wire $3\data_r3__xer_so_ok$next[0:0]$7764 - attribute \src "libresoc.v:152856.19-152856.113" - wire width 3 $and$libresoc.v:152856$7573_Y - attribute \src "libresoc.v:152857.19-152857.125" - wire $and$libresoc.v:152857$7574_Y - attribute \src "libresoc.v:152858.19-152858.125" - wire $and$libresoc.v:152858$7575_Y - attribute \src "libresoc.v:152859.19-152859.125" - wire $and$libresoc.v:152859$7576_Y - attribute \src "libresoc.v:152860.19-152860.125" - wire $and$libresoc.v:152860$7577_Y - attribute \src "libresoc.v:152861.18-152861.110" - wire $and$libresoc.v:152861$7578_Y - attribute \src "libresoc.v:152862.19-152862.149" - wire width 4 $and$libresoc.v:152862$7579_Y - attribute \src "libresoc.v:152863.19-152863.121" - wire width 4 $and$libresoc.v:152863$7580_Y - attribute \src "libresoc.v:152864.19-152864.127" - wire $and$libresoc.v:152864$7581_Y - attribute \src "libresoc.v:152865.19-152865.127" - wire $and$libresoc.v:152865$7582_Y - attribute \src "libresoc.v:152866.19-152866.127" - wire $and$libresoc.v:152866$7583_Y - attribute \src "libresoc.v:152867.19-152867.127" - wire $and$libresoc.v:152867$7584_Y - attribute \src "libresoc.v:152869.18-152869.98" - wire $and$libresoc.v:152869$7586_Y - attribute \src "libresoc.v:152871.18-152871.100" - wire $and$libresoc.v:152871$7588_Y - attribute \src "libresoc.v:152872.18-152872.160" - wire width 4 $and$libresoc.v:152872$7589_Y - attribute \src "libresoc.v:152874.18-152874.119" - wire width 4 $and$libresoc.v:152874$7591_Y - attribute \src "libresoc.v:152877.17-152877.123" - wire $and$libresoc.v:152877$7594_Y - attribute \src "libresoc.v:152878.18-152878.116" - wire $and$libresoc.v:152878$7595_Y - attribute \src "libresoc.v:152883.18-152883.113" - wire $and$libresoc.v:152883$7600_Y - attribute \src "libresoc.v:152884.18-152884.125" - wire width 4 $and$libresoc.v:152884$7601_Y - attribute \src "libresoc.v:152886.18-152886.112" - wire $and$libresoc.v:152886$7603_Y - attribute \src "libresoc.v:152888.18-152888.126" - wire $and$libresoc.v:152888$7605_Y - attribute \src "libresoc.v:152889.18-152889.126" - wire $and$libresoc.v:152889$7606_Y - attribute \src "libresoc.v:152890.18-152890.117" - wire $and$libresoc.v:152890$7607_Y - attribute \src "libresoc.v:152896.18-152896.130" - wire $and$libresoc.v:152896$7613_Y - attribute \src "libresoc.v:152897.18-152897.124" - wire width 4 $and$libresoc.v:152897$7614_Y - attribute \src "libresoc.v:152899.18-152899.116" - wire $and$libresoc.v:152899$7616_Y - attribute \src "libresoc.v:152900.18-152900.119" - wire $and$libresoc.v:152900$7617_Y - attribute \src "libresoc.v:152901.18-152901.121" - wire $and$libresoc.v:152901$7618_Y - attribute \src "libresoc.v:152902.18-152902.121" - wire $and$libresoc.v:152902$7619_Y - attribute \src "libresoc.v:152909.18-152909.134" - wire $and$libresoc.v:152909$7626_Y - attribute \src "libresoc.v:152911.18-152911.132" - wire $and$libresoc.v:152911$7628_Y - attribute \src "libresoc.v:152912.18-152912.149" - wire width 3 $and$libresoc.v:152912$7629_Y - attribute \src "libresoc.v:152914.18-152914.129" - wire width 3 $and$libresoc.v:152914$7631_Y - attribute \src "libresoc.v:152885.18-152885.113" - wire $eq$libresoc.v:152885$7602_Y - attribute \src "libresoc.v:152887.18-152887.119" - wire $eq$libresoc.v:152887$7604_Y - attribute \src "libresoc.v:152868.18-152868.97" - wire $not$libresoc.v:152868$7585_Y - attribute \src "libresoc.v:152870.18-152870.99" - wire $not$libresoc.v:152870$7587_Y - attribute \src "libresoc.v:152873.18-152873.113" - wire width 4 $not$libresoc.v:152873$7590_Y - attribute \src "libresoc.v:152876.18-152876.106" - wire $not$libresoc.v:152876$7593_Y - attribute \src "libresoc.v:152882.18-152882.120" - wire $not$libresoc.v:152882$7599_Y - attribute \src "libresoc.v:152893.17-152893.113" - wire width 3 $not$libresoc.v:152893$7610_Y - attribute \src "libresoc.v:152913.18-152913.131" - wire $not$libresoc.v:152913$7630_Y - attribute \src "libresoc.v:152915.18-152915.114" - wire width 3 $not$libresoc.v:152915$7632_Y - attribute \src "libresoc.v:152881.18-152881.112" - wire $or$libresoc.v:152881$7598_Y - attribute \src "libresoc.v:152891.18-152891.122" - wire $or$libresoc.v:152891$7608_Y - attribute \src "libresoc.v:152892.18-152892.124" - wire $or$libresoc.v:152892$7609_Y - attribute \src "libresoc.v:152894.18-152894.168" - wire width 4 $or$libresoc.v:152894$7611_Y - attribute \src "libresoc.v:152895.18-152895.155" - wire width 3 $or$libresoc.v:152895$7612_Y - attribute \src "libresoc.v:152898.18-152898.120" - wire width 4 $or$libresoc.v:152898$7615_Y - attribute \src "libresoc.v:152904.17-152904.117" - wire width 3 $or$libresoc.v:152904$7621_Y - attribute \src "libresoc.v:152910.17-152910.104" - wire $reduce_and$libresoc.v:152910$7627_Y - attribute \src "libresoc.v:152875.18-152875.106" - wire $reduce_or$libresoc.v:152875$7592_Y - attribute \src "libresoc.v:152879.18-152879.113" - wire $reduce_or$libresoc.v:152879$7596_Y - attribute \src "libresoc.v:152880.18-152880.112" - wire $reduce_or$libresoc.v:152880$7597_Y - attribute \src "libresoc.v:152903.18-152903.160" - wire $ternary$libresoc.v:152903$7620_Y - attribute \src "libresoc.v:152905.18-152905.172" - wire width 64 $ternary$libresoc.v:152905$7622_Y - attribute \src "libresoc.v:152906.18-152906.118" - wire width 64 $ternary$libresoc.v:152906$7623_Y - attribute \src "libresoc.v:152907.18-152907.115" - wire width 64 $ternary$libresoc.v:152907$7624_Y - attribute \src "libresoc.v:152908.18-152908.118" - wire $ternary$libresoc.v:152908$7625_Y + attribute \src "libresoc.v:152652.19-152652.113" + wire width 3 $and$libresoc.v:152652$7573_Y + attribute \src "libresoc.v:152653.19-152653.125" + wire $and$libresoc.v:152653$7574_Y + attribute \src "libresoc.v:152654.19-152654.125" + wire $and$libresoc.v:152654$7575_Y + attribute \src "libresoc.v:152655.19-152655.125" + wire $and$libresoc.v:152655$7576_Y + attribute \src "libresoc.v:152656.19-152656.125" + wire $and$libresoc.v:152656$7577_Y + attribute \src "libresoc.v:152657.18-152657.110" + wire $and$libresoc.v:152657$7578_Y + attribute \src "libresoc.v:152658.19-152658.149" + wire width 4 $and$libresoc.v:152658$7579_Y + attribute \src "libresoc.v:152659.19-152659.121" + wire width 4 $and$libresoc.v:152659$7580_Y + attribute \src "libresoc.v:152660.19-152660.127" + wire $and$libresoc.v:152660$7581_Y + attribute \src "libresoc.v:152661.19-152661.127" + wire $and$libresoc.v:152661$7582_Y + attribute \src "libresoc.v:152662.19-152662.127" + wire $and$libresoc.v:152662$7583_Y + attribute \src "libresoc.v:152663.19-152663.127" + wire $and$libresoc.v:152663$7584_Y + attribute \src "libresoc.v:152665.18-152665.98" + wire $and$libresoc.v:152665$7586_Y + attribute \src "libresoc.v:152667.18-152667.100" + wire $and$libresoc.v:152667$7588_Y + attribute \src "libresoc.v:152668.18-152668.160" + wire width 4 $and$libresoc.v:152668$7589_Y + attribute \src "libresoc.v:152670.18-152670.119" + wire width 4 $and$libresoc.v:152670$7591_Y + attribute \src "libresoc.v:152673.17-152673.123" + wire $and$libresoc.v:152673$7594_Y + attribute \src "libresoc.v:152674.18-152674.116" + wire $and$libresoc.v:152674$7595_Y + attribute \src "libresoc.v:152679.18-152679.113" + wire $and$libresoc.v:152679$7600_Y + attribute \src "libresoc.v:152680.18-152680.125" + wire width 4 $and$libresoc.v:152680$7601_Y + attribute \src "libresoc.v:152682.18-152682.112" + wire $and$libresoc.v:152682$7603_Y + attribute \src "libresoc.v:152684.18-152684.126" + wire $and$libresoc.v:152684$7605_Y + attribute \src "libresoc.v:152685.18-152685.126" + wire $and$libresoc.v:152685$7606_Y + attribute \src "libresoc.v:152686.18-152686.117" + wire $and$libresoc.v:152686$7607_Y + attribute \src "libresoc.v:152692.18-152692.130" + wire $and$libresoc.v:152692$7613_Y + attribute \src "libresoc.v:152693.18-152693.124" + wire width 4 $and$libresoc.v:152693$7614_Y + attribute \src "libresoc.v:152695.18-152695.116" + wire $and$libresoc.v:152695$7616_Y + attribute \src "libresoc.v:152696.18-152696.119" + wire $and$libresoc.v:152696$7617_Y + attribute \src "libresoc.v:152697.18-152697.121" + wire $and$libresoc.v:152697$7618_Y + attribute \src "libresoc.v:152698.18-152698.121" + wire $and$libresoc.v:152698$7619_Y + attribute \src "libresoc.v:152705.18-152705.134" + wire $and$libresoc.v:152705$7626_Y + attribute \src "libresoc.v:152707.18-152707.132" + wire $and$libresoc.v:152707$7628_Y + attribute \src "libresoc.v:152708.18-152708.149" + wire width 3 $and$libresoc.v:152708$7629_Y + attribute \src "libresoc.v:152710.18-152710.129" + wire width 3 $and$libresoc.v:152710$7631_Y + attribute \src "libresoc.v:152681.18-152681.113" + wire $eq$libresoc.v:152681$7602_Y + attribute \src "libresoc.v:152683.18-152683.119" + wire $eq$libresoc.v:152683$7604_Y + attribute \src "libresoc.v:152664.18-152664.97" + wire $not$libresoc.v:152664$7585_Y + attribute \src "libresoc.v:152666.18-152666.99" + wire $not$libresoc.v:152666$7587_Y + attribute \src "libresoc.v:152669.18-152669.113" + wire width 4 $not$libresoc.v:152669$7590_Y + attribute \src "libresoc.v:152672.18-152672.106" + wire $not$libresoc.v:152672$7593_Y + attribute \src "libresoc.v:152678.18-152678.120" + wire $not$libresoc.v:152678$7599_Y + attribute \src "libresoc.v:152689.17-152689.113" + wire width 3 $not$libresoc.v:152689$7610_Y + attribute \src "libresoc.v:152709.18-152709.131" + wire $not$libresoc.v:152709$7630_Y + attribute \src "libresoc.v:152711.18-152711.114" + wire width 3 $not$libresoc.v:152711$7632_Y + attribute \src "libresoc.v:152677.18-152677.112" + wire $or$libresoc.v:152677$7598_Y + attribute \src "libresoc.v:152687.18-152687.122" + wire $or$libresoc.v:152687$7608_Y + attribute \src "libresoc.v:152688.18-152688.124" + wire $or$libresoc.v:152688$7609_Y + attribute \src "libresoc.v:152690.18-152690.168" + wire width 4 $or$libresoc.v:152690$7611_Y + attribute \src "libresoc.v:152691.18-152691.155" + wire width 3 $or$libresoc.v:152691$7612_Y + attribute \src "libresoc.v:152694.18-152694.120" + wire width 4 $or$libresoc.v:152694$7615_Y + attribute \src "libresoc.v:152700.17-152700.117" + wire width 3 $or$libresoc.v:152700$7621_Y + attribute \src "libresoc.v:152706.17-152706.104" + wire $reduce_and$libresoc.v:152706$7627_Y + attribute \src "libresoc.v:152671.18-152671.106" + wire $reduce_or$libresoc.v:152671$7592_Y + attribute \src "libresoc.v:152675.18-152675.113" + wire $reduce_or$libresoc.v:152675$7596_Y + attribute \src "libresoc.v:152676.18-152676.112" + wire $reduce_or$libresoc.v:152676$7597_Y + attribute \src "libresoc.v:152699.18-152699.160" + wire $ternary$libresoc.v:152699$7620_Y + attribute \src "libresoc.v:152701.18-152701.172" + wire width 64 $ternary$libresoc.v:152701$7622_Y + attribute \src "libresoc.v:152702.18-152702.118" + wire width 64 $ternary$libresoc.v:152702$7623_Y + attribute \src "libresoc.v:152703.18-152703.115" + wire width 64 $ternary$libresoc.v:152703$7624_Y + attribute \src "libresoc.v:152704.18-152704.118" + wire $ternary$libresoc.v:152704$7625_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -283584,9 +283418,9 @@ module \mul0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \cr_a_ok @@ -283652,7 +283486,7 @@ module \mul0 wire width 2 output 29 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 31 \dest4_o - attribute \src "libresoc.v:152259.7-152259.15" + attribute \src "libresoc.v:152055.7-152055.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 22 \o_ok @@ -283861,7 +283695,7 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:152856$7573 + cell $and $and$libresoc.v:152652$7573 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -283869,10 +283703,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$96 connect \B \$98 - connect \Y $and$libresoc.v:152856$7573_Y + connect \Y $and$libresoc.v:152652$7573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:152857$7574 + cell $and $and$libresoc.v:152653$7574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283880,10 +283714,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:152857$7574_Y + connect \Y $and$libresoc.v:152653$7574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:152858$7575 + cell $and $and$libresoc.v:152654$7575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283891,10 +283725,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:152858$7575_Y + connect \Y $and$libresoc.v:152654$7575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:152859$7576 + cell $and $and$libresoc.v:152655$7576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283902,10 +283736,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:152859$7576_Y + connect \Y $and$libresoc.v:152655$7576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:152860$7577 + cell $and $and$libresoc.v:152656$7577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283913,10 +283747,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:152860$7577_Y + connect \Y $and$libresoc.v:152656$7577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:152861$7578 + cell $and $and$libresoc.v:152657$7578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283924,10 +283758,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:152861$7578_Y + connect \Y $and$libresoc.v:152657$7578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:152862$7579 + cell $and $and$libresoc.v:152658$7579 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -283935,10 +283769,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$102 \$104 \$106 \$108 } - connect \Y $and$libresoc.v:152862$7579_Y + connect \Y $and$libresoc.v:152658$7579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:152863$7580 + cell $and $and$libresoc.v:152659$7580 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -283946,10 +283780,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:152863$7580_Y + connect \Y $and$libresoc.v:152659$7580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:152864$7581 + cell $and $and$libresoc.v:152660$7581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283957,10 +283791,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:152864$7581_Y + connect \Y $and$libresoc.v:152660$7581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:152865$7582 + cell $and $and$libresoc.v:152661$7582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283968,10 +283802,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:152865$7582_Y + connect \Y $and$libresoc.v:152661$7582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:152866$7583 + cell $and $and$libresoc.v:152662$7583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283979,10 +283813,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:152866$7583_Y + connect \Y $and$libresoc.v:152662$7583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:152867$7584 + cell $and $and$libresoc.v:152663$7584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283990,10 +283824,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:152867$7584_Y + connect \Y $and$libresoc.v:152663$7584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:152869$7586 + cell $and $and$libresoc.v:152665$7586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284001,10 +283835,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:152869$7586_Y + connect \Y $and$libresoc.v:152665$7586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:152871$7588 + cell $and $and$libresoc.v:152667$7588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284012,10 +283846,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:152871$7588_Y + connect \Y $and$libresoc.v:152667$7588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:152872$7589 + cell $and $and$libresoc.v:152668$7589 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -284023,10 +283857,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:152872$7589_Y + connect \Y $and$libresoc.v:152668$7589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:152874$7591 + cell $and $and$libresoc.v:152670$7591 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -284034,10 +283868,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:152874$7591_Y + connect \Y $and$libresoc.v:152670$7591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:152877$7594 + cell $and $and$libresoc.v:152673$7594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284045,10 +283879,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:152877$7594_Y + connect \Y $and$libresoc.v:152673$7594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:152878$7595 + cell $and $and$libresoc.v:152674$7595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284056,10 +283890,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:152878$7595_Y + connect \Y $and$libresoc.v:152674$7595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:152883$7600 + cell $and $and$libresoc.v:152679$7600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284067,10 +283901,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:152883$7600_Y + connect \Y $and$libresoc.v:152679$7600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:152884$7601 + cell $and $and$libresoc.v:152680$7601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -284078,10 +283912,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:152884$7601_Y + connect \Y $and$libresoc.v:152680$7601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:152886$7603 + cell $and $and$libresoc.v:152682$7603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284089,10 +283923,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:152886$7603_Y + connect \Y $and$libresoc.v:152682$7603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:152888$7605 + cell $and $and$libresoc.v:152684$7605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284100,10 +283934,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_mul0_n_ready_i - connect \Y $and$libresoc.v:152888$7605_Y + connect \Y $and$libresoc.v:152684$7605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:152889$7606 + cell $and $and$libresoc.v:152685$7606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284111,10 +283945,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_mul0_n_valid_o - connect \Y $and$libresoc.v:152889$7606_Y + connect \Y $and$libresoc.v:152685$7606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:152890$7607 + cell $and $and$libresoc.v:152686$7607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284122,10 +283956,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:152890$7607_Y + connect \Y $and$libresoc.v:152686$7607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:152896$7613 + cell $and $and$libresoc.v:152692$7613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284133,10 +283967,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:152896$7613_Y + connect \Y $and$libresoc.v:152692$7613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:152897$7614 + cell $and $and$libresoc.v:152693$7614 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -284144,10 +283978,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:152897$7614_Y + connect \Y $and$libresoc.v:152693$7614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:152899$7616 + cell $and $and$libresoc.v:152695$7616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284155,10 +283989,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:152899$7616_Y + connect \Y $and$libresoc.v:152695$7616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:152900$7617 + cell $and $and$libresoc.v:152696$7617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284166,10 +284000,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:152900$7617_Y + connect \Y $and$libresoc.v:152696$7617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:152901$7618 + cell $and $and$libresoc.v:152697$7618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284177,10 +284011,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:152901$7618_Y + connect \Y $and$libresoc.v:152697$7618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:152902$7619 + cell $and $and$libresoc.v:152698$7619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284188,10 +284022,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:152902$7619_Y + connect \Y $and$libresoc.v:152698$7619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:152909$7626 + cell $and $and$libresoc.v:152705$7626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284199,10 +284033,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:152909$7626_Y + connect \Y $and$libresoc.v:152705$7626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:152911$7628 + cell $and $and$libresoc.v:152707$7628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284210,10 +284044,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:152911$7628_Y + connect \Y $and$libresoc.v:152707$7628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:152912$7629 + cell $and $and$libresoc.v:152708$7629 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -284221,10 +284055,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:152912$7629_Y + connect \Y $and$libresoc.v:152708$7629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:152914$7631 + cell $and $and$libresoc.v:152710$7631 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -284232,10 +284066,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$92 connect \B { 1'1 \$94 1'1 } - connect \Y $and$libresoc.v:152914$7631_Y + connect \Y $and$libresoc.v:152710$7631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:152885$7602 + cell $eq $eq$libresoc.v:152681$7602 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -284243,10 +284077,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:152885$7602_Y + connect \Y $eq$libresoc.v:152681$7602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:152887$7604 + cell $eq $eq$libresoc.v:152683$7604 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -284254,74 +284088,74 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:152887$7604_Y + connect \Y $eq$libresoc.v:152683$7604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:152868$7585 + cell $not $not$libresoc.v:152664$7585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:152868$7585_Y + connect \Y $not$libresoc.v:152664$7585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:152870$7587 + cell $not $not$libresoc.v:152666$7587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:152870$7587_Y + connect \Y $not$libresoc.v:152666$7587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:152873$7590 + cell $not $not$libresoc.v:152669$7590 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:152873$7590_Y + connect \Y $not$libresoc.v:152669$7590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:152876$7593 + cell $not $not$libresoc.v:152672$7593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:152876$7593_Y + connect \Y $not$libresoc.v:152672$7593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:152882$7599 + cell $not $not$libresoc.v:152678$7599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_ready_i - connect \Y $not$libresoc.v:152882$7599_Y + connect \Y $not$libresoc.v:152678$7599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:152893$7610 + cell $not $not$libresoc.v:152689$7610 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:152893$7610_Y + connect \Y $not$libresoc.v:152689$7610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:152913$7630 + cell $not $not$libresoc.v:152709$7630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $not$libresoc.v:152913$7630_Y + connect \Y $not$libresoc.v:152709$7630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:152915$7632 + cell $not $not$libresoc.v:152711$7632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:152915$7632_Y + connect \Y $not$libresoc.v:152711$7632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:152881$7598 + cell $or $or$libresoc.v:152677$7598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284329,10 +284163,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:152881$7598_Y + connect \Y $or$libresoc.v:152677$7598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:152891$7608 + cell $or $or$libresoc.v:152687$7608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284340,10 +284174,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:152891$7608_Y + connect \Y $or$libresoc.v:152687$7608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:152892$7609 + cell $or $or$libresoc.v:152688$7609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284351,10 +284185,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:152892$7609_Y + connect \Y $or$libresoc.v:152688$7609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:152894$7611 + cell $or $or$libresoc.v:152690$7611 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -284362,10 +284196,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:152894$7611_Y + connect \Y $or$libresoc.v:152690$7611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:152895$7612 + cell $or $or$libresoc.v:152691$7612 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -284373,10 +284207,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:152895$7612_Y + connect \Y $or$libresoc.v:152691$7612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:152898$7615 + cell $or $or$libresoc.v:152694$7615 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -284384,10 +284218,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:152898$7615_Y + connect \Y $or$libresoc.v:152694$7615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:152904$7621 + cell $or $or$libresoc.v:152700$7621 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -284395,82 +284229,82 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:152904$7621_Y + connect \Y $or$libresoc.v:152700$7621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:152910$7627 + cell $reduce_and $reduce_and$libresoc.v:152706$7627 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:152910$7627_Y + connect \Y $reduce_and$libresoc.v:152706$7627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:152875$7592 + cell $reduce_or $reduce_or$libresoc.v:152671$7592 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:152875$7592_Y + connect \Y $reduce_or$libresoc.v:152671$7592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:152879$7596 + cell $reduce_or $reduce_or$libresoc.v:152675$7596 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:152879$7596_Y + connect \Y $reduce_or$libresoc.v:152675$7596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:152880$7597 + cell $reduce_or $reduce_or$libresoc.v:152676$7597 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:152880$7597_Y + connect \Y $reduce_or$libresoc.v:152676$7597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:152903$7620 + cell $mux $ternary$libresoc.v:152699$7620 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:152903$7620_Y + connect \Y $ternary$libresoc.v:152699$7620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:152905$7622 + cell $mux $ternary$libresoc.v:152701$7622 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_mul0_mul_op__imm_data__data connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:152905$7622_Y + connect \Y $ternary$libresoc.v:152701$7622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:152906$7623 + cell $mux $ternary$libresoc.v:152702$7623 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:152906$7623_Y + connect \Y $ternary$libresoc.v:152702$7623_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:152907$7624 + cell $mux $ternary$libresoc.v:152703$7624 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:152907$7624_Y + connect \Y $ternary$libresoc.v:152703$7624_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:152908$7625 + cell $mux $ternary$libresoc.v:152704$7625 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:152908$7625_Y + connect \Y $ternary$libresoc.v:152704$7625_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:152992.15-152998.4" + attribute \src "libresoc.v:152788.15-152794.4" cell \alu_l$107 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -284479,7 +284313,7 @@ module \mul0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:152999.12-153029.4" + attribute \src "libresoc.v:152795.12-152825.4" cell \alu_mul0 \alu_mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -284512,7 +284346,7 @@ module \mul0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:153030.16-153036.4" + attribute \src "libresoc.v:152826.16-152832.4" cell \alui_l$106 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -284521,7 +284355,7 @@ module \mul0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:153037.15-153043.4" + attribute \src "libresoc.v:152833.15-152839.4" cell \opc_l$102 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -284530,7 +284364,7 @@ module \mul0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:153044.15-153050.4" + attribute \src "libresoc.v:152840.15-152846.4" cell \req_l$103 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -284539,7 +284373,7 @@ module \mul0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:153051.15-153057.4" + attribute \src "libresoc.v:152847.15-152853.4" cell \rok_l$105 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -284548,7 +284382,7 @@ module \mul0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:153058.15-153063.4" + attribute \src "libresoc.v:152854.15-152859.4" cell \rst_l$104 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -284556,7 +284390,7 @@ module \mul0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:153064.15-153070.4" + attribute \src "libresoc.v:152860.15-152866.4" cell \src_l$101 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -284564,592 +284398,592 @@ module \mul0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:152259.7-152259.20" - process $proc$libresoc.v:152259$7787 + attribute \src "libresoc.v:152055.7-152055.20" + process $proc$libresoc.v:152055$7787 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:152383.7-152383.24" - process $proc$libresoc.v:152383$7788 + attribute \src "libresoc.v:152179.7-152179.24" + process $proc$libresoc.v:152179$7788 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:152393.7-152393.26" - process $proc$libresoc.v:152393$7789 + attribute \src "libresoc.v:152189.7-152189.26" + process $proc$libresoc.v:152189$7789 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:152401.7-152401.25" - process $proc$libresoc.v:152401$7790 + attribute \src "libresoc.v:152197.7-152197.25" + process $proc$libresoc.v:152197$7790 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:152424.14-152424.49" - process $proc$libresoc.v:152424$7791 + attribute \src "libresoc.v:152220.14-152220.49" + process $proc$libresoc.v:152220$7791 assign { } { } assign $1\alu_mul0_mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:152428.14-152428.68" - process $proc$libresoc.v:152428$7792 + attribute \src "libresoc.v:152224.14-152224.68" + process $proc$libresoc.v:152224$7792 assign { } { } assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:152432.7-152432.43" - process $proc$libresoc.v:152432$7793 + attribute \src "libresoc.v:152228.7-152228.43" + process $proc$libresoc.v:152228$7793 assign { } { } assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:152436.14-152436.43" - process $proc$libresoc.v:152436$7794 + attribute \src "libresoc.v:152232.14-152232.43" + process $proc$libresoc.v:152232$7794 assign { } { } assign $1\alu_mul0_mul_op__insn[31:0] 0 sync always sync init update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:152515.13-152515.47" - process $proc$libresoc.v:152515$7795 + attribute \src "libresoc.v:152311.13-152311.47" + process $proc$libresoc.v:152311$7795 assign { } { } assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:152519.7-152519.39" - process $proc$libresoc.v:152519$7796 + attribute \src "libresoc.v:152315.7-152315.39" + process $proc$libresoc.v:152315$7796 assign { } { } assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:152523.7-152523.40" - process $proc$libresoc.v:152523$7797 + attribute \src "libresoc.v:152319.7-152319.40" + process $proc$libresoc.v:152319$7797 assign { } { } assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:152527.7-152527.37" - process $proc$libresoc.v:152527$7798 + attribute \src "libresoc.v:152323.7-152323.37" + process $proc$libresoc.v:152323$7798 assign { } { } assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:152531.7-152531.37" - process $proc$libresoc.v:152531$7799 + attribute \src "libresoc.v:152327.7-152327.37" + process $proc$libresoc.v:152327$7799 assign { } { } assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:152535.7-152535.37" - process $proc$libresoc.v:152535$7800 + attribute \src "libresoc.v:152331.7-152331.37" + process $proc$libresoc.v:152331$7800 assign { } { } assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:152539.7-152539.37" - process $proc$libresoc.v:152539$7801 + attribute \src "libresoc.v:152335.7-152335.37" + process $proc$libresoc.v:152335$7801 assign { } { } assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:152543.7-152543.40" - process $proc$libresoc.v:152543$7802 + attribute \src "libresoc.v:152339.7-152339.40" + process $proc$libresoc.v:152339$7802 assign { } { } assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:152573.7-152573.27" - process $proc$libresoc.v:152573$7803 + attribute \src "libresoc.v:152369.7-152369.27" + process $proc$libresoc.v:152369$7803 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:152607.14-152607.47" - process $proc$libresoc.v:152607$7804 + attribute \src "libresoc.v:152403.14-152403.47" + process $proc$libresoc.v:152403$7804 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:152611.7-152611.27" - process $proc$libresoc.v:152611$7805 + attribute \src "libresoc.v:152407.7-152407.27" + process $proc$libresoc.v:152407$7805 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:152615.13-152615.33" - process $proc$libresoc.v:152615$7806 + attribute \src "libresoc.v:152411.13-152411.33" + process $proc$libresoc.v:152411$7806 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:152619.7-152619.30" - process $proc$libresoc.v:152619$7807 + attribute \src "libresoc.v:152415.7-152415.30" + process $proc$libresoc.v:152415$7807 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:152623.13-152623.35" - process $proc$libresoc.v:152623$7808 + attribute \src "libresoc.v:152419.13-152419.35" + process $proc$libresoc.v:152419$7808 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:152627.7-152627.32" - process $proc$libresoc.v:152627$7809 + attribute \src "libresoc.v:152423.7-152423.32" + process $proc$libresoc.v:152423$7809 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:152631.7-152631.29" - process $proc$libresoc.v:152631$7810 + attribute \src "libresoc.v:152427.7-152427.29" + process $proc$libresoc.v:152427$7810 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:152635.7-152635.32" - process $proc$libresoc.v:152635$7811 + attribute \src "libresoc.v:152431.7-152431.32" + process $proc$libresoc.v:152431$7811 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:152655.7-152655.25" - process $proc$libresoc.v:152655$7812 + attribute \src "libresoc.v:152451.7-152451.25" + process $proc$libresoc.v:152451$7812 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:152659.7-152659.25" - process $proc$libresoc.v:152659$7813 + attribute \src "libresoc.v:152455.7-152455.25" + process $proc$libresoc.v:152455$7813 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:152777.13-152777.30" - process $proc$libresoc.v:152777$7814 + attribute \src "libresoc.v:152573.13-152573.30" + process $proc$libresoc.v:152573$7814 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:152785.13-152785.31" - process $proc$libresoc.v:152785$7815 + attribute \src "libresoc.v:152581.13-152581.31" + process $proc$libresoc.v:152581$7815 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:152789.13-152789.31" - process $proc$libresoc.v:152789$7816 + attribute \src "libresoc.v:152585.13-152585.31" + process $proc$libresoc.v:152585$7816 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:152801.7-152801.26" - process $proc$libresoc.v:152801$7817 + attribute \src "libresoc.v:152597.7-152597.26" + process $proc$libresoc.v:152597$7817 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:152805.7-152805.26" - process $proc$libresoc.v:152805$7818 + attribute \src "libresoc.v:152601.7-152601.26" + process $proc$libresoc.v:152601$7818 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:152809.7-152809.25" - process $proc$libresoc.v:152809$7819 + attribute \src "libresoc.v:152605.7-152605.25" + process $proc$libresoc.v:152605$7819 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:152813.7-152813.25" - process $proc$libresoc.v:152813$7820 + attribute \src "libresoc.v:152609.7-152609.25" + process $proc$libresoc.v:152609$7820 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:152827.13-152827.31" - process $proc$libresoc.v:152827$7821 + attribute \src "libresoc.v:152623.13-152623.31" + process $proc$libresoc.v:152623$7821 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:152831.13-152831.31" - process $proc$libresoc.v:152831$7822 + attribute \src "libresoc.v:152627.13-152627.31" + process $proc$libresoc.v:152627$7822 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:152837.14-152837.43" - process $proc$libresoc.v:152837$7823 + attribute \src "libresoc.v:152633.14-152633.43" + process $proc$libresoc.v:152633$7823 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:152841.14-152841.43" - process $proc$libresoc.v:152841$7824 + attribute \src "libresoc.v:152637.14-152637.43" + process $proc$libresoc.v:152637$7824 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:152845.7-152845.20" - process $proc$libresoc.v:152845$7825 + attribute \src "libresoc.v:152641.7-152641.20" + process $proc$libresoc.v:152641$7825 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:152916.3-152917.39" - process $proc$libresoc.v:152916$7633 + attribute \src "libresoc.v:152712.3-152713.39" + process $proc$libresoc.v:152712$7633 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:152918.3-152919.43" - process $proc$libresoc.v:152918$7634 + attribute \src "libresoc.v:152714.3-152715.43" + process $proc$libresoc.v:152714$7634 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:152920.3-152921.29" - process $proc$libresoc.v:152920$7635 + attribute \src "libresoc.v:152716.3-152717.29" + process $proc$libresoc.v:152716$7635 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:152922.3-152923.29" - process $proc$libresoc.v:152922$7636 + attribute \src "libresoc.v:152718.3-152719.29" + process $proc$libresoc.v:152718$7636 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:152924.3-152925.29" - process $proc$libresoc.v:152924$7637 + attribute \src "libresoc.v:152720.3-152721.29" + process $proc$libresoc.v:152720$7637 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:152926.3-152927.47" - process $proc$libresoc.v:152926$7638 + attribute \src "libresoc.v:152722.3-152723.47" + process $proc$libresoc.v:152722$7638 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:152928.3-152929.53" - process $proc$libresoc.v:152928$7639 + attribute \src "libresoc.v:152724.3-152725.53" + process $proc$libresoc.v:152724$7639 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:152930.3-152931.47" - process $proc$libresoc.v:152930$7640 + attribute \src "libresoc.v:152726.3-152727.47" + process $proc$libresoc.v:152726$7640 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:152932.3-152933.53" - process $proc$libresoc.v:152932$7641 + attribute \src "libresoc.v:152728.3-152729.53" + process $proc$libresoc.v:152728$7641 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:152934.3-152935.43" - process $proc$libresoc.v:152934$7642 + attribute \src "libresoc.v:152730.3-152731.43" + process $proc$libresoc.v:152730$7642 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:152936.3-152937.49" - process $proc$libresoc.v:152936$7643 + attribute \src "libresoc.v:152732.3-152733.49" + process $proc$libresoc.v:152732$7643 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:152938.3-152939.37" - process $proc$libresoc.v:152938$7644 + attribute \src "libresoc.v:152734.3-152735.37" + process $proc$libresoc.v:152734$7644 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:152940.3-152941.43" - process $proc$libresoc.v:152940$7645 + attribute \src "libresoc.v:152736.3-152737.43" + process $proc$libresoc.v:152736$7645 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:152942.3-152943.69" - process $proc$libresoc.v:152942$7646 + attribute \src "libresoc.v:152738.3-152739.69" + process $proc$libresoc.v:152738$7646 assign { } { } assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:152944.3-152945.65" - process $proc$libresoc.v:152944$7647 + attribute \src "libresoc.v:152740.3-152741.65" + process $proc$libresoc.v:152740$7647 assign { } { } assign $0\alu_mul0_mul_op__fn_unit[13:0] \alu_mul0_mul_op__fn_unit$next sync posedge \coresync_clk update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:152946.3-152947.79" - process $proc$libresoc.v:152946$7648 + attribute \src "libresoc.v:152742.3-152743.79" + process $proc$libresoc.v:152742$7648 assign { } { } assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:152948.3-152949.75" - process $proc$libresoc.v:152948$7649 + attribute \src "libresoc.v:152744.3-152745.75" + process $proc$libresoc.v:152744$7649 assign { } { } assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:152950.3-152951.63" - process $proc$libresoc.v:152950$7650 + attribute \src "libresoc.v:152746.3-152747.63" + process $proc$libresoc.v:152746$7650 assign { } { } assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:152952.3-152953.63" - process $proc$libresoc.v:152952$7651 + attribute \src "libresoc.v:152748.3-152749.63" + process $proc$libresoc.v:152748$7651 assign { } { } assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:152954.3-152955.63" - process $proc$libresoc.v:152954$7652 + attribute \src "libresoc.v:152750.3-152751.63" + process $proc$libresoc.v:152750$7652 assign { } { } assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:152956.3-152957.63" - process $proc$libresoc.v:152956$7653 + attribute \src "libresoc.v:152752.3-152753.63" + process $proc$libresoc.v:152752$7653 assign { } { } assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:152958.3-152959.69" - process $proc$libresoc.v:152958$7654 + attribute \src "libresoc.v:152754.3-152755.69" + process $proc$libresoc.v:152754$7654 assign { } { } assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next sync posedge \coresync_clk update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:152960.3-152961.67" - process $proc$libresoc.v:152960$7655 + attribute \src "libresoc.v:152756.3-152757.67" + process $proc$libresoc.v:152756$7655 assign { } { } assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:152962.3-152963.69" - process $proc$libresoc.v:152962$7656 + attribute \src "libresoc.v:152758.3-152759.69" + process $proc$libresoc.v:152758$7656 assign { } { } assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:152964.3-152965.59" - process $proc$libresoc.v:152964$7657 + attribute \src "libresoc.v:152760.3-152761.59" + process $proc$libresoc.v:152760$7657 assign { } { } assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:152966.3-152967.39" - process $proc$libresoc.v:152966$7658 + attribute \src "libresoc.v:152762.3-152763.39" + process $proc$libresoc.v:152762$7658 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:152968.3-152969.39" - process $proc$libresoc.v:152968$7659 + attribute \src "libresoc.v:152764.3-152765.39" + process $proc$libresoc.v:152764$7659 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:152970.3-152971.39" - process $proc$libresoc.v:152970$7660 + attribute \src "libresoc.v:152766.3-152767.39" + process $proc$libresoc.v:152766$7660 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:152972.3-152973.39" - process $proc$libresoc.v:152972$7661 + attribute \src "libresoc.v:152768.3-152769.39" + process $proc$libresoc.v:152768$7661 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:152974.3-152975.39" - process $proc$libresoc.v:152974$7662 + attribute \src "libresoc.v:152770.3-152771.39" + process $proc$libresoc.v:152770$7662 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:152976.3-152977.39" - process $proc$libresoc.v:152976$7663 + attribute \src "libresoc.v:152772.3-152773.39" + process $proc$libresoc.v:152772$7663 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:152978.3-152979.39" - process $proc$libresoc.v:152978$7664 + attribute \src "libresoc.v:152774.3-152775.39" + process $proc$libresoc.v:152774$7664 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:152980.3-152981.39" - process $proc$libresoc.v:152980$7665 + attribute \src "libresoc.v:152776.3-152777.39" + process $proc$libresoc.v:152776$7665 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:152982.3-152983.41" - process $proc$libresoc.v:152982$7666 + attribute \src "libresoc.v:152778.3-152779.41" + process $proc$libresoc.v:152778$7666 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:152984.3-152985.41" - process $proc$libresoc.v:152984$7667 + attribute \src "libresoc.v:152780.3-152781.41" + process $proc$libresoc.v:152780$7667 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:152986.3-152987.37" - process $proc$libresoc.v:152986$7668 + attribute \src "libresoc.v:152782.3-152783.37" + process $proc$libresoc.v:152782$7668 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:152988.3-152989.40" - process $proc$libresoc.v:152988$7669 + attribute \src "libresoc.v:152784.3-152785.40" + process $proc$libresoc.v:152784$7669 assign { } { } assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:152990.3-152991.25" - process $proc$libresoc.v:152990$7670 + attribute \src "libresoc.v:152786.3-152787.25" + process $proc$libresoc.v:152786$7670 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:153071.3-153080.6" - process $proc$libresoc.v:153071$7671 + attribute \src "libresoc.v:152867.3-152876.6" + process $proc$libresoc.v:152867$7671 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:153072.5-153072.29" + attribute \src "libresoc.v:152868.5-152868.29" switch \initial - attribute \src "libresoc.v:153072.9-153072.17" + attribute \src "libresoc.v:152868.9-152868.17" case 1'1 case end @@ -285165,14 +284999,14 @@ module \mul0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:153081.3-153089.6" - process $proc$libresoc.v:153081$7672 + attribute \src "libresoc.v:152877.3-152885.6" + process $proc$libresoc.v:152877$7672 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$7673 $1\rok_l_s_rdok$next[0:0]$7674 - attribute \src "libresoc.v:153082.5-153082.29" + attribute \src "libresoc.v:152878.5-152878.29" switch \initial - attribute \src "libresoc.v:153082.9-153082.17" + attribute \src "libresoc.v:152878.9-152878.17" case 1'1 case end @@ -285188,14 +285022,14 @@ module \mul0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7673 end - attribute \src "libresoc.v:153090.3-153098.6" - process $proc$libresoc.v:153090$7675 + attribute \src "libresoc.v:152886.3-152894.6" + process $proc$libresoc.v:152886$7675 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$7676 $1\rok_l_r_rdok$next[0:0]$7677 - attribute \src "libresoc.v:153091.5-153091.29" + attribute \src "libresoc.v:152887.5-152887.29" switch \initial - attribute \src "libresoc.v:153091.9-153091.17" + attribute \src "libresoc.v:152887.9-152887.17" case 1'1 case end @@ -285211,14 +285045,14 @@ module \mul0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7676 end - attribute \src "libresoc.v:153099.3-153107.6" - process $proc$libresoc.v:153099$7678 + attribute \src "libresoc.v:152895.3-152903.6" + process $proc$libresoc.v:152895$7678 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$7679 $1\rst_l_s_rst$next[0:0]$7680 - attribute \src "libresoc.v:153100.5-153100.29" + attribute \src "libresoc.v:152896.5-152896.29" switch \initial - attribute \src "libresoc.v:153100.9-153100.17" + attribute \src "libresoc.v:152896.9-152896.17" case 1'1 case end @@ -285234,14 +285068,14 @@ module \mul0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7679 end - attribute \src "libresoc.v:153108.3-153116.6" - process $proc$libresoc.v:153108$7681 + attribute \src "libresoc.v:152904.3-152912.6" + process $proc$libresoc.v:152904$7681 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$7682 $1\rst_l_r_rst$next[0:0]$7683 - attribute \src "libresoc.v:153109.5-153109.29" + attribute \src "libresoc.v:152905.5-152905.29" switch \initial - attribute \src "libresoc.v:153109.9-153109.17" + attribute \src "libresoc.v:152905.9-152905.17" case 1'1 case end @@ -285257,14 +285091,14 @@ module \mul0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7682 end - attribute \src "libresoc.v:153117.3-153125.6" - process $proc$libresoc.v:153117$7684 + attribute \src "libresoc.v:152913.3-152921.6" + process $proc$libresoc.v:152913$7684 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$7685 $1\opc_l_s_opc$next[0:0]$7686 - attribute \src "libresoc.v:153118.5-153118.29" + attribute \src "libresoc.v:152914.5-152914.29" switch \initial - attribute \src "libresoc.v:153118.9-153118.17" + attribute \src "libresoc.v:152914.9-152914.17" case 1'1 case end @@ -285280,14 +285114,14 @@ module \mul0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7685 end - attribute \src "libresoc.v:153126.3-153134.6" - process $proc$libresoc.v:153126$7687 + attribute \src "libresoc.v:152922.3-152930.6" + process $proc$libresoc.v:152922$7687 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$7688 $1\opc_l_r_opc$next[0:0]$7689 - attribute \src "libresoc.v:153127.5-153127.29" + attribute \src "libresoc.v:152923.5-152923.29" switch \initial - attribute \src "libresoc.v:153127.9-153127.17" + attribute \src "libresoc.v:152923.9-152923.17" case 1'1 case end @@ -285303,14 +285137,14 @@ module \mul0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7688 end - attribute \src "libresoc.v:153135.3-153143.6" - process $proc$libresoc.v:153135$7690 + attribute \src "libresoc.v:152931.3-152939.6" + process $proc$libresoc.v:152931$7690 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$7691 $1\src_l_s_src$next[2:0]$7692 - attribute \src "libresoc.v:153136.5-153136.29" + attribute \src "libresoc.v:152932.5-152932.29" switch \initial - attribute \src "libresoc.v:153136.9-153136.17" + attribute \src "libresoc.v:152932.9-152932.17" case 1'1 case end @@ -285326,14 +285160,14 @@ module \mul0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7691 end - attribute \src "libresoc.v:153144.3-153152.6" - process $proc$libresoc.v:153144$7693 + attribute \src "libresoc.v:152940.3-152948.6" + process $proc$libresoc.v:152940$7693 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$7694 $1\src_l_r_src$next[2:0]$7695 - attribute \src "libresoc.v:153145.5-153145.29" + attribute \src "libresoc.v:152941.5-152941.29" switch \initial - attribute \src "libresoc.v:153145.9-153145.17" + attribute \src "libresoc.v:152941.9-152941.17" case 1'1 case end @@ -285349,14 +285183,14 @@ module \mul0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7694 end - attribute \src "libresoc.v:153153.3-153161.6" - process $proc$libresoc.v:153153$7696 + attribute \src "libresoc.v:152949.3-152957.6" + process $proc$libresoc.v:152949$7696 assign { } { } assign { } { } assign $0\req_l_s_req$next[3:0]$7697 $1\req_l_s_req$next[3:0]$7698 - attribute \src "libresoc.v:153154.5-153154.29" + attribute \src "libresoc.v:152950.5-152950.29" switch \initial - attribute \src "libresoc.v:153154.9-153154.17" + attribute \src "libresoc.v:152950.9-152950.17" case 1'1 case end @@ -285372,14 +285206,14 @@ module \mul0 sync always update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7697 end - attribute \src "libresoc.v:153162.3-153170.6" - process $proc$libresoc.v:153162$7699 + attribute \src "libresoc.v:152958.3-152966.6" + process $proc$libresoc.v:152958$7699 assign { } { } assign { } { } assign $0\req_l_r_req$next[3:0]$7700 $1\req_l_r_req$next[3:0]$7701 - attribute \src "libresoc.v:153163.5-153163.29" + attribute \src "libresoc.v:152959.5-152959.29" switch \initial - attribute \src "libresoc.v:153163.9-153163.17" + attribute \src "libresoc.v:152959.9-152959.17" case 1'1 case end @@ -285395,8 +285229,8 @@ module \mul0 sync always update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7700 end - attribute \src "libresoc.v:153171.3-153203.6" - process $proc$libresoc.v:153171$7702 + attribute \src "libresoc.v:152967.3-152999.6" + process $proc$libresoc.v:152967$7702 assign { } { } assign { } { } assign { } { } @@ -285439,9 +285273,9 @@ module \mul0 assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7711 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7712 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 - attribute \src "libresoc.v:153172.5-153172.29" + attribute \src "libresoc.v:152968.5-152968.29" switch \initial - attribute \src "libresoc.v:153172.9-153172.17" + attribute \src "libresoc.v:152968.9-152968.17" case 1'1 case end @@ -285514,8 +285348,8 @@ module \mul0 update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713 update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7714 end - attribute \src "libresoc.v:153204.3-153225.6" - process $proc$libresoc.v:153204$7733 + attribute \src "libresoc.v:153000.3-153021.6" + process $proc$libresoc.v:153000$7733 assign { } { } assign { } { } assign { } { } @@ -285525,9 +285359,9 @@ module \mul0 assign $0\data_r0__o$next[63:0]$7734 $2\data_r0__o$next[63:0]$7738 assign { } { } assign $0\data_r0__o_ok$next[0:0]$7735 $3\data_r0__o_ok$next[0:0]$7740 - attribute \src "libresoc.v:153205.5-153205.29" + attribute \src "libresoc.v:153001.5-153001.29" switch \initial - attribute \src "libresoc.v:153205.9-153205.17" + attribute \src "libresoc.v:153001.9-153001.17" case 1'1 case end @@ -285566,8 +285400,8 @@ module \mul0 update \data_r0__o$next $0\data_r0__o$next[63:0]$7734 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7735 end - attribute \src "libresoc.v:153226.3-153247.6" - process $proc$libresoc.v:153226$7741 + attribute \src "libresoc.v:153022.3-153043.6" + process $proc$libresoc.v:153022$7741 assign { } { } assign { } { } assign { } { } @@ -285577,9 +285411,9 @@ module \mul0 assign $0\data_r1__cr_a$next[3:0]$7742 $2\data_r1__cr_a$next[3:0]$7746 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$7743 $3\data_r1__cr_a_ok$next[0:0]$7748 - attribute \src "libresoc.v:153227.5-153227.29" + attribute \src "libresoc.v:153023.5-153023.29" switch \initial - attribute \src "libresoc.v:153227.9-153227.17" + attribute \src "libresoc.v:153023.9-153023.17" case 1'1 case end @@ -285618,8 +285452,8 @@ module \mul0 update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7742 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7743 end - attribute \src "libresoc.v:153248.3-153269.6" - process $proc$libresoc.v:153248$7749 + attribute \src "libresoc.v:153044.3-153065.6" + process $proc$libresoc.v:153044$7749 assign { } { } assign { } { } assign { } { } @@ -285629,9 +285463,9 @@ module \mul0 assign $0\data_r2__xer_ov$next[1:0]$7750 $2\data_r2__xer_ov$next[1:0]$7754 assign { } { } assign $0\data_r2__xer_ov_ok$next[0:0]$7751 $3\data_r2__xer_ov_ok$next[0:0]$7756 - attribute \src "libresoc.v:153249.5-153249.29" + attribute \src "libresoc.v:153045.5-153045.29" switch \initial - attribute \src "libresoc.v:153249.9-153249.17" + attribute \src "libresoc.v:153045.9-153045.17" case 1'1 case end @@ -285670,8 +285504,8 @@ module \mul0 update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7750 update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7751 end - attribute \src "libresoc.v:153270.3-153291.6" - process $proc$libresoc.v:153270$7757 + attribute \src "libresoc.v:153066.3-153087.6" + process $proc$libresoc.v:153066$7757 assign { } { } assign { } { } assign { } { } @@ -285681,9 +285515,9 @@ module \mul0 assign $0\data_r3__xer_so$next[0:0]$7758 $2\data_r3__xer_so$next[0:0]$7762 assign { } { } assign $0\data_r3__xer_so_ok$next[0:0]$7759 $3\data_r3__xer_so_ok$next[0:0]$7764 - attribute \src "libresoc.v:153271.5-153271.29" + attribute \src "libresoc.v:153067.5-153067.29" switch \initial - attribute \src "libresoc.v:153271.9-153271.17" + attribute \src "libresoc.v:153067.9-153067.17" case 1'1 case end @@ -285722,14 +285556,14 @@ module \mul0 update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7758 update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7759 end - attribute \src "libresoc.v:153292.3-153301.6" - process $proc$libresoc.v:153292$7765 + attribute \src "libresoc.v:153088.3-153097.6" + process $proc$libresoc.v:153088$7765 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$7766 $1\src_r0$next[63:0]$7767 - attribute \src "libresoc.v:153293.5-153293.29" + attribute \src "libresoc.v:153089.5-153089.29" switch \initial - attribute \src "libresoc.v:153293.9-153293.17" + attribute \src "libresoc.v:153089.9-153089.17" case 1'1 case end @@ -285745,14 +285579,14 @@ module \mul0 sync always update \src_r0$next $0\src_r0$next[63:0]$7766 end - attribute \src "libresoc.v:153302.3-153311.6" - process $proc$libresoc.v:153302$7768 + attribute \src "libresoc.v:153098.3-153107.6" + process $proc$libresoc.v:153098$7768 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$7769 $1\src_r1$next[63:0]$7770 - attribute \src "libresoc.v:153303.5-153303.29" + attribute \src "libresoc.v:153099.5-153099.29" switch \initial - attribute \src "libresoc.v:153303.9-153303.17" + attribute \src "libresoc.v:153099.9-153099.17" case 1'1 case end @@ -285768,14 +285602,14 @@ module \mul0 sync always update \src_r1$next $0\src_r1$next[63:0]$7769 end - attribute \src "libresoc.v:153312.3-153321.6" - process $proc$libresoc.v:153312$7771 + attribute \src "libresoc.v:153108.3-153117.6" + process $proc$libresoc.v:153108$7771 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$7772 $1\src_r2$next[0:0]$7773 - attribute \src "libresoc.v:153313.5-153313.29" + attribute \src "libresoc.v:153109.5-153109.29" switch \initial - attribute \src "libresoc.v:153313.9-153313.17" + attribute \src "libresoc.v:153109.9-153109.17" case 1'1 case end @@ -285791,14 +285625,14 @@ module \mul0 sync always update \src_r2$next $0\src_r2$next[0:0]$7772 end - attribute \src "libresoc.v:153322.3-153330.6" - process $proc$libresoc.v:153322$7774 + attribute \src "libresoc.v:153118.3-153126.6" + process $proc$libresoc.v:153118$7774 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$7775 $1\alui_l_r_alui$next[0:0]$7776 - attribute \src "libresoc.v:153323.5-153323.29" + attribute \src "libresoc.v:153119.5-153119.29" switch \initial - attribute \src "libresoc.v:153323.9-153323.17" + attribute \src "libresoc.v:153119.9-153119.17" case 1'1 case end @@ -285814,14 +285648,14 @@ module \mul0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7775 end - attribute \src "libresoc.v:153331.3-153339.6" - process $proc$libresoc.v:153331$7777 + attribute \src "libresoc.v:153127.3-153135.6" + process $proc$libresoc.v:153127$7777 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$7778 $1\alu_l_r_alu$next[0:0]$7779 - attribute \src "libresoc.v:153332.5-153332.29" + attribute \src "libresoc.v:153128.5-153128.29" switch \initial - attribute \src "libresoc.v:153332.9-153332.17" + attribute \src "libresoc.v:153128.9-153128.17" case 1'1 case end @@ -285837,14 +285671,14 @@ module \mul0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7778 end - attribute \src "libresoc.v:153340.3-153349.6" - process $proc$libresoc.v:153340$7780 + attribute \src "libresoc.v:153136.3-153145.6" + process $proc$libresoc.v:153136$7780 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:153341.5-153341.29" + attribute \src "libresoc.v:153137.5-153137.29" switch \initial - attribute \src "libresoc.v:153341.9-153341.17" + attribute \src "libresoc.v:153137.9-153137.17" case 1'1 case end @@ -285860,14 +285694,14 @@ module \mul0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:153350.3-153359.6" - process $proc$libresoc.v:153350$7781 + attribute \src "libresoc.v:153146.3-153155.6" + process $proc$libresoc.v:153146$7781 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:153351.5-153351.29" + attribute \src "libresoc.v:153147.5-153147.29" switch \initial - attribute \src "libresoc.v:153351.9-153351.17" + attribute \src "libresoc.v:153147.9-153147.17" case 1'1 case end @@ -285883,14 +285717,14 @@ module \mul0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:153360.3-153369.6" - process $proc$libresoc.v:153360$7782 + attribute \src "libresoc.v:153156.3-153165.6" + process $proc$libresoc.v:153156$7782 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:153361.5-153361.29" + attribute \src "libresoc.v:153157.5-153157.29" switch \initial - attribute \src "libresoc.v:153361.9-153361.17" + attribute \src "libresoc.v:153157.9-153157.17" case 1'1 case end @@ -285906,14 +285740,14 @@ module \mul0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:153370.3-153379.6" - process $proc$libresoc.v:153370$7783 + attribute \src "libresoc.v:153166.3-153175.6" + process $proc$libresoc.v:153166$7783 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:153371.5-153371.29" + attribute \src "libresoc.v:153167.5-153167.29" switch \initial - attribute \src "libresoc.v:153371.9-153371.17" + attribute \src "libresoc.v:153167.9-153167.17" case 1'1 case end @@ -285929,14 +285763,14 @@ module \mul0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:153380.3-153388.6" - process $proc$libresoc.v:153380$7784 + attribute \src "libresoc.v:153176.3-153184.6" + process $proc$libresoc.v:153176$7784 assign { } { } assign { } { } assign $0\prev_wr_go$next[3:0]$7785 $1\prev_wr_go$next[3:0]$7786 - attribute \src "libresoc.v:153381.5-153381.29" + attribute \src "libresoc.v:153177.5-153177.29" switch \initial - attribute \src "libresoc.v:153381.9-153381.17" + attribute \src "libresoc.v:153177.9-153177.17" case 1'1 case end @@ -285952,66 +285786,66 @@ module \mul0 sync always update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7785 end - connect \$100 $and$libresoc.v:152856$7573_Y - connect \$102 $and$libresoc.v:152857$7574_Y - connect \$104 $and$libresoc.v:152858$7575_Y - connect \$106 $and$libresoc.v:152859$7576_Y - connect \$108 $and$libresoc.v:152860$7577_Y - connect \$10 $and$libresoc.v:152861$7578_Y - connect \$110 $and$libresoc.v:152862$7579_Y - connect \$112 $and$libresoc.v:152863$7580_Y - connect \$114 $and$libresoc.v:152864$7581_Y - connect \$116 $and$libresoc.v:152865$7582_Y - connect \$118 $and$libresoc.v:152866$7583_Y - connect \$120 $and$libresoc.v:152867$7584_Y - connect \$12 $not$libresoc.v:152868$7585_Y - connect \$14 $and$libresoc.v:152869$7586_Y - connect \$16 $not$libresoc.v:152870$7587_Y - connect \$18 $and$libresoc.v:152871$7588_Y - connect \$20 $and$libresoc.v:152872$7589_Y - connect \$24 $not$libresoc.v:152873$7590_Y - connect \$26 $and$libresoc.v:152874$7591_Y - connect \$23 $reduce_or$libresoc.v:152875$7592_Y - connect \$22 $not$libresoc.v:152876$7593_Y - connect \$2 $and$libresoc.v:152877$7594_Y - connect \$30 $and$libresoc.v:152878$7595_Y - connect \$32 $reduce_or$libresoc.v:152879$7596_Y - connect \$34 $reduce_or$libresoc.v:152880$7597_Y - connect \$36 $or$libresoc.v:152881$7598_Y - connect \$38 $not$libresoc.v:152882$7599_Y - connect \$40 $and$libresoc.v:152883$7600_Y - connect \$42 $and$libresoc.v:152884$7601_Y - connect \$44 $eq$libresoc.v:152885$7602_Y - connect \$46 $and$libresoc.v:152886$7603_Y - connect \$48 $eq$libresoc.v:152887$7604_Y - connect \$50 $and$libresoc.v:152888$7605_Y - connect \$52 $and$libresoc.v:152889$7606_Y - connect \$54 $and$libresoc.v:152890$7607_Y - connect \$56 $or$libresoc.v:152891$7608_Y - connect \$58 $or$libresoc.v:152892$7609_Y - connect \$5 $not$libresoc.v:152893$7610_Y - connect \$60 $or$libresoc.v:152894$7611_Y - connect \$62 $or$libresoc.v:152895$7612_Y - connect \$64 $and$libresoc.v:152896$7613_Y - connect \$66 $and$libresoc.v:152897$7614_Y - connect \$68 $or$libresoc.v:152898$7615_Y - connect \$70 $and$libresoc.v:152899$7616_Y - connect \$72 $and$libresoc.v:152900$7617_Y - connect \$74 $and$libresoc.v:152901$7618_Y - connect \$76 $and$libresoc.v:152902$7619_Y - connect \$78 $ternary$libresoc.v:152903$7620_Y - connect \$7 $or$libresoc.v:152904$7621_Y - connect \$80 $ternary$libresoc.v:152905$7622_Y - connect \$82 $ternary$libresoc.v:152906$7623_Y - connect \$84 $ternary$libresoc.v:152907$7624_Y - connect \$86 $ternary$libresoc.v:152908$7625_Y - connect \$88 $and$libresoc.v:152909$7626_Y - connect \$4 $reduce_and$libresoc.v:152910$7627_Y - connect \$90 $and$libresoc.v:152911$7628_Y - connect \$92 $and$libresoc.v:152912$7629_Y - connect \$94 $not$libresoc.v:152913$7630_Y - connect \$96 $and$libresoc.v:152914$7631_Y - connect \$98 $not$libresoc.v:152915$7632_Y + connect \$100 $and$libresoc.v:152652$7573_Y + connect \$102 $and$libresoc.v:152653$7574_Y + connect \$104 $and$libresoc.v:152654$7575_Y + connect \$106 $and$libresoc.v:152655$7576_Y + connect \$108 $and$libresoc.v:152656$7577_Y + connect \$10 $and$libresoc.v:152657$7578_Y + connect \$110 $and$libresoc.v:152658$7579_Y + connect \$112 $and$libresoc.v:152659$7580_Y + connect \$114 $and$libresoc.v:152660$7581_Y + connect \$116 $and$libresoc.v:152661$7582_Y + connect \$118 $and$libresoc.v:152662$7583_Y + connect \$120 $and$libresoc.v:152663$7584_Y + connect \$12 $not$libresoc.v:152664$7585_Y + connect \$14 $and$libresoc.v:152665$7586_Y + connect \$16 $not$libresoc.v:152666$7587_Y + connect \$18 $and$libresoc.v:152667$7588_Y + connect \$20 $and$libresoc.v:152668$7589_Y + connect \$24 $not$libresoc.v:152669$7590_Y + connect \$26 $and$libresoc.v:152670$7591_Y + connect \$23 $reduce_or$libresoc.v:152671$7592_Y + connect \$22 $not$libresoc.v:152672$7593_Y + connect \$2 $and$libresoc.v:152673$7594_Y + connect \$30 $and$libresoc.v:152674$7595_Y + connect \$32 $reduce_or$libresoc.v:152675$7596_Y + connect \$34 $reduce_or$libresoc.v:152676$7597_Y + connect \$36 $or$libresoc.v:152677$7598_Y + connect \$38 $not$libresoc.v:152678$7599_Y + connect \$40 $and$libresoc.v:152679$7600_Y + connect \$42 $and$libresoc.v:152680$7601_Y + connect \$44 $eq$libresoc.v:152681$7602_Y + connect \$46 $and$libresoc.v:152682$7603_Y + connect \$48 $eq$libresoc.v:152683$7604_Y + connect \$50 $and$libresoc.v:152684$7605_Y + connect \$52 $and$libresoc.v:152685$7606_Y + connect \$54 $and$libresoc.v:152686$7607_Y + connect \$56 $or$libresoc.v:152687$7608_Y + connect \$58 $or$libresoc.v:152688$7609_Y + connect \$5 $not$libresoc.v:152689$7610_Y + connect \$60 $or$libresoc.v:152690$7611_Y + connect \$62 $or$libresoc.v:152691$7612_Y + connect \$64 $and$libresoc.v:152692$7613_Y + connect \$66 $and$libresoc.v:152693$7614_Y + connect \$68 $or$libresoc.v:152694$7615_Y + connect \$70 $and$libresoc.v:152695$7616_Y + connect \$72 $and$libresoc.v:152696$7617_Y + connect \$74 $and$libresoc.v:152697$7618_Y + connect \$76 $and$libresoc.v:152698$7619_Y + connect \$78 $ternary$libresoc.v:152699$7620_Y + connect \$7 $or$libresoc.v:152700$7621_Y + connect \$80 $ternary$libresoc.v:152701$7622_Y + connect \$82 $ternary$libresoc.v:152702$7623_Y + connect \$84 $ternary$libresoc.v:152703$7624_Y + connect \$86 $ternary$libresoc.v:152704$7625_Y + connect \$88 $and$libresoc.v:152705$7626_Y + connect \$4 $reduce_and$libresoc.v:152706$7627_Y + connect \$90 $and$libresoc.v:152707$7628_Y + connect \$92 $and$libresoc.v:152708$7629_Y + connect \$94 $not$libresoc.v:152709$7630_Y + connect \$96 $and$libresoc.v:152710$7631_Y + connect \$98 $not$libresoc.v:152711$7632_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -286043,51 +285877,51 @@ module \mul0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:153423.1-153756.10" +attribute \src "libresoc.v:153219.1-153552.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" attribute \generator "nMigen" module \mul1 - attribute \src "libresoc.v:153723.18-153723.116" - wire $and$libresoc.v:153723$7827_Y - attribute \src "libresoc.v:153725.18-153725.116" - wire $and$libresoc.v:153725$7829_Y - attribute \src "libresoc.v:153726.18-153726.117" - wire $and$libresoc.v:153726$7830_Y - attribute \src "libresoc.v:153727.18-153727.117" - wire $and$libresoc.v:153727$7831_Y - attribute \src "libresoc.v:153730.18-153730.95" - wire width 65 $extend$libresoc.v:153730$7834_Y - attribute \src "libresoc.v:153731.18-153731.91" - wire width 65 $extend$libresoc.v:153731$7836_Y - attribute \src "libresoc.v:153733.18-153733.95" - wire width 65 $extend$libresoc.v:153733$7839_Y - attribute \src "libresoc.v:153734.18-153734.91" - wire width 65 $extend$libresoc.v:153734$7841_Y - attribute \src "libresoc.v:153730.18-153730.95" - wire width 65 $neg$libresoc.v:153730$7835_Y - attribute \src "libresoc.v:153733.18-153733.95" - wire width 65 $neg$libresoc.v:153733$7840_Y - attribute \src "libresoc.v:153731.18-153731.91" - wire width 65 $pos$libresoc.v:153731$7837_Y - attribute \src "libresoc.v:153734.18-153734.91" - wire width 65 $pos$libresoc.v:153734$7842_Y - attribute \src "libresoc.v:153722.18-153722.125" - wire $ternary$libresoc.v:153722$7826_Y - attribute \src "libresoc.v:153724.18-153724.125" - wire $ternary$libresoc.v:153724$7828_Y - attribute \src "libresoc.v:153732.18-153732.112" - wire width 65 $ternary$libresoc.v:153732$7838_Y - attribute \src "libresoc.v:153735.18-153735.112" - wire width 65 $ternary$libresoc.v:153735$7843_Y - attribute \src "libresoc.v:153736.18-153736.116" - wire width 32 $ternary$libresoc.v:153736$7844_Y - attribute \src "libresoc.v:153737.18-153737.116" - wire width 32 $ternary$libresoc.v:153737$7845_Y - attribute \src "libresoc.v:153728.18-153728.106" - wire $xor$libresoc.v:153728$7832_Y - attribute \src "libresoc.v:153729.18-153729.110" - wire $xor$libresoc.v:153729$7833_Y + attribute \src "libresoc.v:153519.18-153519.116" + wire $and$libresoc.v:153519$7827_Y + attribute \src "libresoc.v:153521.18-153521.116" + wire $and$libresoc.v:153521$7829_Y + attribute \src "libresoc.v:153522.18-153522.117" + wire $and$libresoc.v:153522$7830_Y + attribute \src "libresoc.v:153523.18-153523.117" + wire $and$libresoc.v:153523$7831_Y + attribute \src "libresoc.v:153526.18-153526.95" + wire width 65 $extend$libresoc.v:153526$7834_Y + attribute \src "libresoc.v:153527.18-153527.91" + wire width 65 $extend$libresoc.v:153527$7836_Y + attribute \src "libresoc.v:153529.18-153529.95" + wire width 65 $extend$libresoc.v:153529$7839_Y + attribute \src "libresoc.v:153530.18-153530.91" + wire width 65 $extend$libresoc.v:153530$7841_Y + attribute \src "libresoc.v:153526.18-153526.95" + wire width 65 $neg$libresoc.v:153526$7835_Y + attribute \src "libresoc.v:153529.18-153529.95" + wire width 65 $neg$libresoc.v:153529$7840_Y + attribute \src "libresoc.v:153527.18-153527.91" + wire width 65 $pos$libresoc.v:153527$7837_Y + attribute \src "libresoc.v:153530.18-153530.91" + wire width 65 $pos$libresoc.v:153530$7842_Y + attribute \src "libresoc.v:153518.18-153518.125" + wire $ternary$libresoc.v:153518$7826_Y + attribute \src "libresoc.v:153520.18-153520.125" + wire $ternary$libresoc.v:153520$7828_Y + attribute \src "libresoc.v:153528.18-153528.112" + wire width 65 $ternary$libresoc.v:153528$7838_Y + attribute \src "libresoc.v:153531.18-153531.112" + wire width 65 $ternary$libresoc.v:153531$7843_Y + attribute \src "libresoc.v:153532.18-153532.116" + wire width 32 $ternary$libresoc.v:153532$7844_Y + attribute \src "libresoc.v:153533.18-153533.116" + wire width 32 $ternary$libresoc.v:153533$7845_Y + attribute \src "libresoc.v:153524.18-153524.106" + wire $xor$libresoc.v:153524$7832_Y + attribute \src "libresoc.v:153525.18-153525.110" + wire $xor$libresoc.v:153525$7833_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" @@ -286387,7 +286221,7 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 31 \xer_so$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $and$libresoc.v:153723$7827 + cell $and $and$libresoc.v:153519$7827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286395,10 +286229,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:153723$7827_Y + connect \Y $and$libresoc.v:153519$7827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $and$libresoc.v:153725$7829 + cell $and $and$libresoc.v:153521$7829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286406,10 +286240,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:153725$7829_Y + connect \Y $and$libresoc.v:153521$7829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $and$libresoc.v:153726$7830 + cell $and $and$libresoc.v:153522$7830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286417,10 +286251,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \ra [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:153726$7830_Y + connect \Y $and$libresoc.v:153522$7830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $and$libresoc.v:153727$7831 + cell $and $and$libresoc.v:153523$7831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286428,122 +286262,122 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \rb [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:153727$7831_Y + connect \Y $and$libresoc.v:153523$7831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $pos $extend$libresoc.v:153730$7834 + cell $pos $extend$libresoc.v:153526$7834 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:153730$7834_Y + connect \Y $extend$libresoc.v:153526$7834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:153731$7836 + cell $pos $extend$libresoc.v:153527$7836 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:153731$7836_Y + connect \Y $extend$libresoc.v:153527$7836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $pos $extend$libresoc.v:153733$7839 + cell $pos $extend$libresoc.v:153529$7839 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:153733$7839_Y + connect \Y $extend$libresoc.v:153529$7839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:153734$7841 + cell $pos $extend$libresoc.v:153530$7841 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:153734$7841_Y + connect \Y $extend$libresoc.v:153530$7841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $neg$libresoc.v:153730$7835 + cell $neg $neg$libresoc.v:153526$7835 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:153730$7834_Y - connect \Y $neg$libresoc.v:153730$7835_Y + connect \A $extend$libresoc.v:153526$7834_Y + connect \Y $neg$libresoc.v:153526$7835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $neg $neg$libresoc.v:153733$7840 + cell $neg $neg$libresoc.v:153529$7840 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:153733$7839_Y - connect \Y $neg$libresoc.v:153733$7840_Y + connect \A $extend$libresoc.v:153529$7839_Y + connect \Y $neg$libresoc.v:153529$7840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:153731$7837 + cell $pos $pos$libresoc.v:153527$7837 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:153731$7836_Y - connect \Y $pos$libresoc.v:153731$7837_Y + connect \A $extend$libresoc.v:153527$7836_Y + connect \Y $pos$libresoc.v:153527$7837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:153734$7842 + cell $pos $pos$libresoc.v:153530$7842 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:153734$7841_Y - connect \Y $pos$libresoc.v:153734$7842_Y + connect \A $extend$libresoc.v:153530$7841_Y + connect \Y $pos$libresoc.v:153530$7842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $ternary$libresoc.v:153722$7826 + cell $mux $ternary$libresoc.v:153518$7826 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:153722$7826_Y + connect \Y $ternary$libresoc.v:153518$7826_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $ternary$libresoc.v:153724$7828 + cell $mux $ternary$libresoc.v:153520$7828 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:153724$7828_Y + connect \Y $ternary$libresoc.v:153520$7828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $mux $ternary$libresoc.v:153732$7838 + cell $mux $ternary$libresoc.v:153528$7838 parameter \WIDTH 65 connect \A \$36 connect \B \$34 connect \S \sign_a - connect \Y $ternary$libresoc.v:153732$7838_Y + connect \Y $ternary$libresoc.v:153528$7838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $mux $ternary$libresoc.v:153735$7843 + cell $mux $ternary$libresoc.v:153531$7843 parameter \WIDTH 65 connect \A \$43 connect \B \$41 connect \S \sign_b - connect \Y $ternary$libresoc.v:153735$7843_Y + connect \Y $ternary$libresoc.v:153531$7843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:153736$7844 + cell $mux $ternary$libresoc.v:153532$7844 parameter \WIDTH 32 connect \A \abs_a [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:153736$7844_Y + connect \Y $ternary$libresoc.v:153532$7844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:153737$7845 + cell $mux $ternary$libresoc.v:153533$7845 parameter \WIDTH 32 connect \A \abs_b [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:153737$7845_Y + connect \Y $ternary$libresoc.v:153533$7845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $xor$libresoc.v:153728$7832 + cell $xor $xor$libresoc.v:153524$7832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286551,10 +286385,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign_a connect \B \sign_b - connect \Y $xor$libresoc.v:153728$7832_Y + connect \Y $xor$libresoc.v:153524$7832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $xor$libresoc.v:153729$7833 + cell $xor $xor$libresoc.v:153525$7833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -286562,24 +286396,24 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign32_a connect \B \sign32_b - connect \Y $xor$libresoc.v:153729$7833_Y - end - connect \$17 $ternary$libresoc.v:153722$7826_Y - connect \$19 $and$libresoc.v:153723$7827_Y - connect \$21 $ternary$libresoc.v:153724$7828_Y - connect \$23 $and$libresoc.v:153725$7829_Y - connect \$25 $and$libresoc.v:153726$7830_Y - connect \$27 $and$libresoc.v:153727$7831_Y - connect \$29 $xor$libresoc.v:153728$7832_Y - connect \$31 $xor$libresoc.v:153729$7833_Y - connect \$34 $neg$libresoc.v:153730$7835_Y - connect \$36 $pos$libresoc.v:153731$7837_Y - connect \$38 $ternary$libresoc.v:153732$7838_Y - connect \$41 $neg$libresoc.v:153733$7840_Y - connect \$43 $pos$libresoc.v:153734$7842_Y - connect \$45 $ternary$libresoc.v:153735$7843_Y - connect \$47 $ternary$libresoc.v:153736$7844_Y - connect \$49 $ternary$libresoc.v:153737$7845_Y + connect \Y $xor$libresoc.v:153525$7833_Y + end + connect \$17 $ternary$libresoc.v:153518$7826_Y + connect \$19 $and$libresoc.v:153519$7827_Y + connect \$21 $ternary$libresoc.v:153520$7828_Y + connect \$23 $and$libresoc.v:153521$7829_Y + connect \$25 $and$libresoc.v:153522$7830_Y + connect \$27 $and$libresoc.v:153523$7831_Y + connect \$29 $xor$libresoc.v:153524$7832_Y + connect \$31 $xor$libresoc.v:153525$7833_Y + connect \$34 $neg$libresoc.v:153526$7835_Y + connect \$36 $pos$libresoc.v:153527$7837_Y + connect \$38 $ternary$libresoc.v:153528$7838_Y + connect \$41 $neg$libresoc.v:153529$7840_Y + connect \$43 $pos$libresoc.v:153530$7842_Y + connect \$45 $ternary$libresoc.v:153531$7843_Y + connect \$47 $ternary$libresoc.v:153532$7844_Y + connect \$49 $ternary$libresoc.v:153533$7845_Y connect \$33 \$38 connect \$40 \$45 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } @@ -286599,17 +286433,17 @@ module \mul1 connect \sign_a \$19 connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:153760.1-154023.10" +attribute \src "libresoc.v:153556.1-153819.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" attribute \generator "nMigen" module \mul2 - attribute \src "libresoc.v:154016.18-154016.98" - wire width 129 $extend$libresoc.v:154016$7847_Y - attribute \src "libresoc.v:154015.18-154015.99" - wire width 128 $mul$libresoc.v:154015$7846_Y - attribute \src "libresoc.v:154016.18-154016.98" - wire width 129 $pos$libresoc.v:154016$7848_Y + attribute \src "libresoc.v:153812.18-153812.98" + wire width 129 $extend$libresoc.v:153812$7847_Y + attribute \src "libresoc.v:153811.18-153811.99" + wire width 128 $mul$libresoc.v:153811$7846_Y + attribute \src "libresoc.v:153812.18-153812.98" + wire width 129 $pos$libresoc.v:153812$7848_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 129 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" @@ -286865,15 +286699,15 @@ module \mul2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 32 \xer_so$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $extend$libresoc.v:154016$7847 + cell $pos $extend$libresoc.v:153812$7847 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 129 connect \A \$18 - connect \Y $extend$libresoc.v:154016$7847_Y + connect \Y $extend$libresoc.v:153812$7847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $mul$libresoc.v:154015$7846 + cell $mul $mul$libresoc.v:153811$7846 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -286881,18 +286715,18 @@ module \mul2 parameter \Y_WIDTH 128 connect \A \ra connect \B \rb - connect \Y $mul$libresoc.v:154015$7846_Y + connect \Y $mul$libresoc.v:153811$7846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $pos$libresoc.v:154016$7848 + cell $pos $pos$libresoc.v:153812$7848 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 129 - connect \A $extend$libresoc.v:154016$7847_Y - connect \Y $pos$libresoc.v:154016$7848_Y + connect \A $extend$libresoc.v:153812$7847_Y + connect \Y $pos$libresoc.v:153812$7848_Y end - connect \$18 $mul$libresoc.v:154015$7846_Y - connect \$17 $pos$libresoc.v:154016$7848_Y + connect \$18 $mul$libresoc.v:153811$7846_Y + connect \$17 $pos$libresoc.v:153812$7848_Y connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$14 \xer_so @@ -286900,65 +286734,65 @@ module \mul2 connect \neg_res$15 \neg_res connect \o \$17 end -attribute \src "libresoc.v:154027.1-154436.10" +attribute \src "libresoc.v:153823.1-154232.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" attribute \generator "nMigen" module \mul3 - attribute \src "libresoc.v:154028.7-154028.20" + attribute \src "libresoc.v:153824.7-153824.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154365.3-154391.6" + attribute \src "libresoc.v:154161.3-154187.6" wire $0\mul_ov[0:0] - attribute \src "libresoc.v:154327.3-154345.6" + attribute \src "libresoc.v:154123.3-154141.6" wire width 64 $0\o$14[63:0]$7865 - attribute \src "libresoc.v:154346.3-154364.6" + attribute \src "libresoc.v:154142.3-154160.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:154392.3-154410.6" + attribute \src "libresoc.v:154188.3-154206.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:154411.3-154429.6" + attribute \src "libresoc.v:154207.3-154225.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:154365.3-154391.6" + attribute \src "libresoc.v:154161.3-154187.6" wire $1\mul_ov[0:0] - attribute \src "libresoc.v:154327.3-154345.6" + attribute \src "libresoc.v:154123.3-154141.6" wire width 64 $1\o$14[63:0]$7866 - attribute \src "libresoc.v:154346.3-154364.6" + attribute \src "libresoc.v:154142.3-154160.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:154392.3-154410.6" + attribute \src "libresoc.v:154188.3-154206.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:154411.3-154429.6" + attribute \src "libresoc.v:154207.3-154225.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:154365.3-154391.6" + attribute \src "libresoc.v:154161.3-154187.6" wire $2\mul_ov[0:0] - attribute \src "libresoc.v:154321.18-154321.104" - wire $and$libresoc.v:154321$7857_Y - attribute \src "libresoc.v:154325.18-154325.104" - wire $and$libresoc.v:154325$7861_Y - attribute \src "libresoc.v:154315.18-154315.95" - wire width 130 $extend$libresoc.v:154315$7849_Y - attribute \src "libresoc.v:154316.18-154316.90" - wire width 130 $extend$libresoc.v:154316$7851_Y - attribute \src "libresoc.v:154326.18-154326.95" - wire width 2 $extend$libresoc.v:154326$7862_Y - attribute \src "libresoc.v:154315.18-154315.95" - wire width 130 $neg$libresoc.v:154315$7850_Y - attribute \src "libresoc.v:154320.18-154320.98" - wire $not$libresoc.v:154320$7856_Y - attribute \src "libresoc.v:154324.18-154324.98" - wire $not$libresoc.v:154324$7860_Y - attribute \src "libresoc.v:154316.18-154316.90" - wire width 130 $pos$libresoc.v:154316$7852_Y - attribute \src "libresoc.v:154326.18-154326.95" - wire width 2 $pos$libresoc.v:154326$7863_Y - attribute \src "libresoc.v:154319.18-154319.106" - wire $reduce_and$libresoc.v:154319$7855_Y - attribute \src "libresoc.v:154323.18-154323.107" - wire $reduce_and$libresoc.v:154323$7859_Y - attribute \src "libresoc.v:154318.18-154318.106" - wire $reduce_or$libresoc.v:154318$7854_Y - attribute \src "libresoc.v:154322.18-154322.107" - wire $reduce_or$libresoc.v:154322$7858_Y - attribute \src "libresoc.v:154317.18-154317.114" - wire width 130 $ternary$libresoc.v:154317$7853_Y + attribute \src "libresoc.v:154117.18-154117.104" + wire $and$libresoc.v:154117$7857_Y + attribute \src "libresoc.v:154121.18-154121.104" + wire $and$libresoc.v:154121$7861_Y + attribute \src "libresoc.v:154111.18-154111.95" + wire width 130 $extend$libresoc.v:154111$7849_Y + attribute \src "libresoc.v:154112.18-154112.90" + wire width 130 $extend$libresoc.v:154112$7851_Y + attribute \src "libresoc.v:154122.18-154122.95" + wire width 2 $extend$libresoc.v:154122$7862_Y + attribute \src "libresoc.v:154111.18-154111.95" + wire width 130 $neg$libresoc.v:154111$7850_Y + attribute \src "libresoc.v:154116.18-154116.98" + wire $not$libresoc.v:154116$7856_Y + attribute \src "libresoc.v:154120.18-154120.98" + wire $not$libresoc.v:154120$7860_Y + attribute \src "libresoc.v:154112.18-154112.90" + wire width 130 $pos$libresoc.v:154112$7852_Y + attribute \src "libresoc.v:154122.18-154122.95" + wire width 2 $pos$libresoc.v:154122$7863_Y + attribute \src "libresoc.v:154115.18-154115.106" + wire $reduce_and$libresoc.v:154115$7855_Y + attribute \src "libresoc.v:154119.18-154119.107" + wire $reduce_and$libresoc.v:154119$7859_Y + attribute \src "libresoc.v:154114.18-154114.106" + wire $reduce_or$libresoc.v:154114$7854_Y + attribute \src "libresoc.v:154118.18-154118.107" + wire $reduce_or$libresoc.v:154118$7858_Y + attribute \src "libresoc.v:154113.18-154113.114" + wire width 130 $ternary$libresoc.v:154113$7853_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" @@ -286985,7 +286819,7 @@ module \mul3 wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \$39 - attribute \src "libresoc.v:154028.7-154028.15" + attribute \src "libresoc.v:153824.7-153824.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" wire \is_32bit @@ -287244,7 +287078,7 @@ module \mul3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 34 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$libresoc.v:154321$7857 + cell $and $and$libresoc.v:154117$7857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287252,10 +287086,10 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $and$libresoc.v:154321$7857_Y + connect \Y $and$libresoc.v:154117$7857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$libresoc.v:154325$7861 + cell $and $and$libresoc.v:154121$7861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -287263,128 +287097,128 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:154325$7861_Y + connect \Y $and$libresoc.v:154121$7861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$libresoc.v:154315$7849 + cell $pos $extend$libresoc.v:154111$7849 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:154315$7849_Y + connect \Y $extend$libresoc.v:154111$7849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:154316$7851 + cell $pos $extend$libresoc.v:154112$7851 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:154316$7851_Y + connect \Y $extend$libresoc.v:154112$7851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:154326$7862 + cell $pos $extend$libresoc.v:154122$7862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \xer_so - connect \Y $extend$libresoc.v:154326$7862_Y + connect \Y $extend$libresoc.v:154122$7862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$libresoc.v:154315$7850 + cell $neg $neg$libresoc.v:154111$7850 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:154315$7849_Y - connect \Y $neg$libresoc.v:154315$7850_Y + connect \A $extend$libresoc.v:154111$7849_Y + connect \Y $neg$libresoc.v:154111$7850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$libresoc.v:154320$7856 + cell $not $not$libresoc.v:154116$7856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $not$libresoc.v:154320$7856_Y + connect \Y $not$libresoc.v:154116$7856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$libresoc.v:154324$7860 + cell $not $not$libresoc.v:154120$7860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$34 - connect \Y $not$libresoc.v:154324$7860_Y + connect \Y $not$libresoc.v:154120$7860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:154316$7852 + cell $pos $pos$libresoc.v:154112$7852 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:154316$7851_Y - connect \Y $pos$libresoc.v:154316$7852_Y + connect \A $extend$libresoc.v:154112$7851_Y + connect \Y $pos$libresoc.v:154112$7852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:154326$7863 + cell $pos $pos$libresoc.v:154122$7863 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:154326$7862_Y - connect \Y $pos$libresoc.v:154326$7863_Y + connect \A $extend$libresoc.v:154122$7862_Y + connect \Y $pos$libresoc.v:154122$7863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$libresoc.v:154319$7855 + cell $reduce_and $reduce_and$libresoc.v:154115$7855 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_and$libresoc.v:154319$7855_Y + connect \Y $reduce_and$libresoc.v:154115$7855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$libresoc.v:154323$7859 + cell $reduce_and $reduce_and$libresoc.v:154119$7859 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_and$libresoc.v:154323$7859_Y + connect \Y $reduce_and$libresoc.v:154119$7859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$libresoc.v:154318$7854 + cell $reduce_or $reduce_or$libresoc.v:154114$7854 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_or$libresoc.v:154318$7854_Y + connect \Y $reduce_or$libresoc.v:154114$7854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$libresoc.v:154322$7858 + cell $reduce_or $reduce_or$libresoc.v:154118$7858 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_or$libresoc.v:154322$7858_Y + connect \Y $reduce_or$libresoc.v:154118$7858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$libresoc.v:154317$7853 + cell $mux $ternary$libresoc.v:154113$7853 parameter \WIDTH 130 connect \A \$19 connect \B \$17 connect \S \neg_res - connect \Y $ternary$libresoc.v:154317$7853_Y + connect \Y $ternary$libresoc.v:154113$7853_Y end - attribute \src "libresoc.v:154028.7-154028.20" - process $proc$libresoc.v:154028$7871 + attribute \src "libresoc.v:153824.7-153824.20" + process $proc$libresoc.v:153824$7871 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154327.3-154345.6" - process $proc$libresoc.v:154327$7864 + attribute \src "libresoc.v:154123.3-154141.6" + process $proc$libresoc.v:154123$7864 assign { } { } assign { } { } assign $0\o$14[63:0]$7865 $1\o$14[63:0]$7866 - attribute \src "libresoc.v:154328.5-154328.29" + attribute \src "libresoc.v:154124.5-154124.29" switch \initial - attribute \src "libresoc.v:154328.9-154328.17" + attribute \src "libresoc.v:154124.9-154124.17" case 1'1 case end @@ -287408,14 +287242,14 @@ module \mul3 sync always update \o$14 $0\o$14[63:0]$7865 end - attribute \src "libresoc.v:154346.3-154364.6" - process $proc$libresoc.v:154346$7867 + attribute \src "libresoc.v:154142.3-154160.6" + process $proc$libresoc.v:154142$7867 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:154347.5-154347.29" + attribute \src "libresoc.v:154143.5-154143.29" switch \initial - attribute \src "libresoc.v:154347.9-154347.17" + attribute \src "libresoc.v:154143.9-154143.17" case 1'1 case end @@ -287439,14 +287273,14 @@ module \mul3 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:154365.3-154391.6" - process $proc$libresoc.v:154365$7868 + attribute \src "libresoc.v:154161.3-154187.6" + process $proc$libresoc.v:154161$7868 assign { } { } assign { } { } assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "libresoc.v:154366.5-154366.29" + attribute \src "libresoc.v:154162.5-154162.29" switch \initial - attribute \src "libresoc.v:154366.9-154366.17" + attribute \src "libresoc.v:154162.9-154162.17" case 1'1 case end @@ -287479,14 +287313,14 @@ module \mul3 sync always update \mul_ov $0\mul_ov[0:0] end - attribute \src "libresoc.v:154392.3-154410.6" - process $proc$libresoc.v:154392$7869 + attribute \src "libresoc.v:154188.3-154206.6" + process $proc$libresoc.v:154188$7869 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:154393.5-154393.29" + attribute \src "libresoc.v:154189.5-154189.29" switch \initial - attribute \src "libresoc.v:154393.9-154393.17" + attribute \src "libresoc.v:154189.9-154189.17" case 1'1 case end @@ -287508,14 +287342,14 @@ module \mul3 sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:154411.3-154429.6" - process $proc$libresoc.v:154411$7870 + attribute \src "libresoc.v:154207.3-154225.6" + process $proc$libresoc.v:154207$7870 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:154412.5-154412.29" + attribute \src "libresoc.v:154208.5-154208.29" switch \initial - attribute \src "libresoc.v:154412.9-154412.17" + attribute \src "libresoc.v:154208.9-154208.17" case 1'1 case end @@ -287537,18 +287371,18 @@ module \mul3 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$17 $neg$libresoc.v:154315$7850_Y - connect \$19 $pos$libresoc.v:154316$7852_Y - connect \$21 $ternary$libresoc.v:154317$7853_Y - connect \$23 $reduce_or$libresoc.v:154318$7854_Y - connect \$26 $reduce_and$libresoc.v:154319$7855_Y - connect \$25 $not$libresoc.v:154320$7856_Y - connect \$29 $and$libresoc.v:154321$7857_Y - connect \$31 $reduce_or$libresoc.v:154322$7858_Y - connect \$34 $reduce_and$libresoc.v:154323$7859_Y - connect \$33 $not$libresoc.v:154324$7860_Y - connect \$37 $and$libresoc.v:154325$7861_Y - connect \$39 $pos$libresoc.v:154326$7863_Y + connect \$17 $neg$libresoc.v:154111$7850_Y + connect \$19 $pos$libresoc.v:154112$7852_Y + connect \$21 $ternary$libresoc.v:154113$7853_Y + connect \$23 $reduce_or$libresoc.v:154114$7854_Y + connect \$26 $reduce_and$libresoc.v:154115$7855_Y + connect \$25 $not$libresoc.v:154116$7856_Y + connect \$29 $and$libresoc.v:154117$7857_Y + connect \$31 $reduce_or$libresoc.v:154118$7858_Y + connect \$34 $reduce_and$libresoc.v:154119$7859_Y + connect \$33 $not$libresoc.v:154120$7860_Y + connect \$37 $and$libresoc.v:154121$7861_Y + connect \$39 $pos$libresoc.v:154122$7863_Y connect \$16 \$21 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -287556,188 +287390,188 @@ module \mul3 connect \mul_o \$21 [128:0] connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:154440.1-155657.10" +attribute \src "libresoc.v:154236.1-155453.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" attribute \generator "nMigen" module \mul_pipe1 - attribute \src "libresoc.v:154441.7-154441.20" + attribute \src "libresoc.v:154237.7-154237.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire width 14 $0\mul_op__fn_unit$next[13:0]$7900 - attribute \src "libresoc.v:155399.3-155400.47" + attribute \src "libresoc.v:155195.3-155196.47" wire width 14 $0\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire width 64 $0\mul_op__imm_data__data$next[63:0]$7901 - attribute \src "libresoc.v:155401.3-155402.61" + attribute \src "libresoc.v:155197.3-155198.61" wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__imm_data__ok$next[0:0]$7902 - attribute \src "libresoc.v:155403.3-155404.57" + attribute \src "libresoc.v:155199.3-155200.57" wire $0\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire width 32 $0\mul_op__insn$next[31:0]$7903 - attribute \src "libresoc.v:155419.3-155420.41" + attribute \src "libresoc.v:155215.3-155216.41" wire width 32 $0\mul_op__insn[31:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire width 7 $0\mul_op__insn_type$next[6:0]$7904 - attribute \src "libresoc.v:155397.3-155398.51" + attribute \src "libresoc.v:155193.3-155194.51" wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__is_32bit$next[0:0]$7905 - attribute \src "libresoc.v:155415.3-155416.49" + attribute \src "libresoc.v:155211.3-155212.49" wire $0\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__is_signed$next[0:0]$7906 - attribute \src "libresoc.v:155417.3-155418.51" + attribute \src "libresoc.v:155213.3-155214.51" wire $0\mul_op__is_signed[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__oe__oe$next[0:0]$7907 - attribute \src "libresoc.v:155409.3-155410.45" + attribute \src "libresoc.v:155205.3-155206.45" wire $0\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__oe__ok$next[0:0]$7908 - attribute \src "libresoc.v:155411.3-155412.45" + attribute \src "libresoc.v:155207.3-155208.45" wire $0\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__rc__ok$next[0:0]$7909 - attribute \src "libresoc.v:155407.3-155408.45" + attribute \src "libresoc.v:155203.3-155204.45" wire $0\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__rc__rc$next[0:0]$7910 - attribute \src "libresoc.v:155405.3-155406.45" + attribute \src "libresoc.v:155201.3-155202.45" wire $0\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__write_cr0$next[0:0]$7911 - attribute \src "libresoc.v:155413.3-155414.51" + attribute \src "libresoc.v:155209.3-155210.51" wire $0\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:155521.3-155533.6" + attribute \src "libresoc.v:155317.3-155329.6" wire width 2 $0\muxid$next[1:0]$7897 - attribute \src "libresoc.v:155421.3-155422.27" + attribute \src "libresoc.v:155217.3-155218.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:155609.3-155621.6" + attribute \src "libresoc.v:155405.3-155417.6" wire $0\neg_res$next[0:0]$7940 - attribute \src "libresoc.v:155622.3-155634.6" + attribute \src "libresoc.v:155418.3-155430.6" wire $0\neg_res32$next[0:0]$7943 - attribute \src "libresoc.v:155387.3-155388.35" + attribute \src "libresoc.v:155183.3-155184.35" wire $0\neg_res32[0:0] - attribute \src "libresoc.v:155389.3-155390.31" + attribute \src "libresoc.v:155185.3-155186.31" wire $0\neg_res[0:0] - attribute \src "libresoc.v:155503.3-155520.6" + attribute \src "libresoc.v:155299.3-155316.6" wire $0\r_busy$next[0:0]$7893 - attribute \src "libresoc.v:155423.3-155424.29" + attribute \src "libresoc.v:155219.3-155220.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:155570.3-155582.6" + attribute \src "libresoc.v:155366.3-155378.6" wire width 64 $0\ra$next[63:0]$7931 - attribute \src "libresoc.v:155395.3-155396.21" + attribute \src "libresoc.v:155191.3-155192.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:155583.3-155595.6" + attribute \src "libresoc.v:155379.3-155391.6" wire width 64 $0\rb$next[63:0]$7934 - attribute \src "libresoc.v:155393.3-155394.21" + attribute \src "libresoc.v:155189.3-155190.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:155596.3-155608.6" + attribute \src "libresoc.v:155392.3-155404.6" wire $0\xer_so$next[0:0]$7937 - attribute \src "libresoc.v:155391.3-155392.29" + attribute \src "libresoc.v:155187.3-155188.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire width 14 $1\mul_op__fn_unit$next[13:0]$7912 - attribute \src "libresoc.v:154957.14-154957.40" + attribute \src "libresoc.v:154753.14-154753.40" wire width 14 $1\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire width 64 $1\mul_op__imm_data__data$next[63:0]$7913 - attribute \src "libresoc.v:154996.14-154996.59" + attribute \src "libresoc.v:154792.14-154792.59" wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__imm_data__ok$next[0:0]$7914 - attribute \src "libresoc.v:155005.7-155005.34" + attribute \src "libresoc.v:154801.7-154801.34" wire $1\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire width 32 $1\mul_op__insn$next[31:0]$7915 - attribute \src "libresoc.v:155014.14-155014.34" + attribute \src "libresoc.v:154810.14-154810.34" wire width 32 $1\mul_op__insn[31:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire width 7 $1\mul_op__insn_type$next[6:0]$7916 - attribute \src "libresoc.v:155098.13-155098.38" + attribute \src "libresoc.v:154894.13-154894.38" wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__is_32bit$next[0:0]$7917 - attribute \src "libresoc.v:155257.7-155257.30" + attribute \src "libresoc.v:155053.7-155053.30" wire $1\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__is_signed$next[0:0]$7918 - attribute \src "libresoc.v:155266.7-155266.31" + attribute \src "libresoc.v:155062.7-155062.31" wire $1\mul_op__is_signed[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__oe__oe$next[0:0]$7919 - attribute \src "libresoc.v:155275.7-155275.28" + attribute \src "libresoc.v:155071.7-155071.28" wire $1\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__oe__ok$next[0:0]$7920 - attribute \src "libresoc.v:155284.7-155284.28" + attribute \src "libresoc.v:155080.7-155080.28" wire $1\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__rc__ok$next[0:0]$7921 - attribute \src "libresoc.v:155293.7-155293.28" + attribute \src "libresoc.v:155089.7-155089.28" wire $1\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__rc__rc$next[0:0]$7922 - attribute \src "libresoc.v:155302.7-155302.28" + attribute \src "libresoc.v:155098.7-155098.28" wire $1\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__write_cr0$next[0:0]$7923 - attribute \src "libresoc.v:155311.7-155311.31" + attribute \src "libresoc.v:155107.7-155107.31" wire $1\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:155521.3-155533.6" + attribute \src "libresoc.v:155317.3-155329.6" wire width 2 $1\muxid$next[1:0]$7898 - attribute \src "libresoc.v:155320.13-155320.25" + attribute \src "libresoc.v:155116.13-155116.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:155609.3-155621.6" + attribute \src "libresoc.v:155405.3-155417.6" wire $1\neg_res$next[0:0]$7941 - attribute \src "libresoc.v:155622.3-155634.6" + attribute \src "libresoc.v:155418.3-155430.6" wire $1\neg_res32$next[0:0]$7944 - attribute \src "libresoc.v:155342.7-155342.23" + attribute \src "libresoc.v:155138.7-155138.23" wire $1\neg_res32[0:0] - attribute \src "libresoc.v:155335.7-155335.21" + attribute \src "libresoc.v:155131.7-155131.21" wire $1\neg_res[0:0] - attribute \src "libresoc.v:155503.3-155520.6" + attribute \src "libresoc.v:155299.3-155316.6" wire $1\r_busy$next[0:0]$7894 - attribute \src "libresoc.v:155356.7-155356.20" + attribute \src "libresoc.v:155152.7-155152.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:155570.3-155582.6" + attribute \src "libresoc.v:155366.3-155378.6" wire width 64 $1\ra$next[63:0]$7932 - attribute \src "libresoc.v:155361.14-155361.39" + attribute \src "libresoc.v:155157.14-155157.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:155583.3-155595.6" + attribute \src "libresoc.v:155379.3-155391.6" wire width 64 $1\rb$next[63:0]$7935 - attribute \src "libresoc.v:155370.14-155370.39" + attribute \src "libresoc.v:155166.14-155166.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:155596.3-155608.6" + attribute \src "libresoc.v:155392.3-155404.6" wire $1\xer_so$next[0:0]$7938 - attribute \src "libresoc.v:155379.7-155379.20" + attribute \src "libresoc.v:155175.7-155175.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire width 64 $2\mul_op__imm_data__data$next[63:0]$7924 - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $2\mul_op__imm_data__ok$next[0:0]$7925 - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $2\mul_op__oe__oe$next[0:0]$7926 - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $2\mul_op__oe__ok$next[0:0]$7927 - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $2\mul_op__rc__ok$next[0:0]$7928 - attribute \src "libresoc.v:155534.3-155569.6" + attribute \src "libresoc.v:155330.3-155365.6" wire $2\mul_op__rc__rc$next[0:0]$7929 - attribute \src "libresoc.v:155503.3-155520.6" + attribute \src "libresoc.v:155299.3-155316.6" wire $2\r_busy$next[0:0]$7895 - attribute \src "libresoc.v:155386.18-155386.118" - wire $and$libresoc.v:155386$7872_Y + attribute \src "libresoc.v:155182.18-155182.118" + wire $and$libresoc.v:155182$7872_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:154441.7-154441.15" + attribute \src "libresoc.v:154237.7-154237.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -288660,7 +288494,7 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:155386$7872 + cell $and $and$libresoc.v:155182$7872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288668,10 +288502,10 @@ module \mul_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$49 connect \B \p_ready_o - connect \Y $and$libresoc.v:155386$7872_Y + connect \Y $and$libresoc.v:155182$7872_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:155425.14-155458.4" + attribute \src "libresoc.v:155221.14-155254.4" cell \input$95 \input connect \mul_op__fn_unit \input_mul_op__fn_unit connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 @@ -288707,7 +288541,7 @@ module \mul_pipe1 connect \xer_so$16 \input_xer_so$32 end attribute \module_not_derived 1 - attribute \src "libresoc.v:155459.8-155494.4" + attribute \src "libresoc.v:155255.8-155290.4" cell \mul1 \mul1 connect \mul_op__fn_unit \mul1_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 @@ -288745,319 +288579,319 @@ module \mul_pipe1 connect \xer_so$16 \mul1_xer_so$48 end attribute \module_not_derived 1 - attribute \src "libresoc.v:155495.10-155498.4" + attribute \src "libresoc.v:155291.10-155294.4" cell \n$94 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:155499.10-155502.4" + attribute \src "libresoc.v:155295.10-155298.4" cell \p$93 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:154441.7-154441.20" - process $proc$libresoc.v:154441$7945 + attribute \src "libresoc.v:154237.7-154237.20" + process $proc$libresoc.v:154237$7945 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154957.14-154957.40" - process $proc$libresoc.v:154957$7946 + attribute \src "libresoc.v:154753.14-154753.40" + process $proc$libresoc.v:154753$7946 assign { } { } assign $1\mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \mul_op__fn_unit $1\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:154996.14-154996.59" - process $proc$libresoc.v:154996$7947 + attribute \src "libresoc.v:154792.14-154792.59" + process $proc$libresoc.v:154792$7947 assign { } { } assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:155005.7-155005.34" - process $proc$libresoc.v:155005$7948 + attribute \src "libresoc.v:154801.7-154801.34" + process $proc$libresoc.v:154801$7948 assign { } { } assign $1\mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:155014.14-155014.34" - process $proc$libresoc.v:155014$7949 + attribute \src "libresoc.v:154810.14-154810.34" + process $proc$libresoc.v:154810$7949 assign { } { } assign $1\mul_op__insn[31:0] 0 sync always sync init update \mul_op__insn $1\mul_op__insn[31:0] end - attribute \src "libresoc.v:155098.13-155098.38" - process $proc$libresoc.v:155098$7950 + attribute \src "libresoc.v:154894.13-154894.38" + process $proc$libresoc.v:154894$7950 assign { } { } assign $1\mul_op__insn_type[6:0] 7'0000000 sync always sync init update \mul_op__insn_type $1\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:155257.7-155257.30" - process $proc$libresoc.v:155257$7951 + attribute \src "libresoc.v:155053.7-155053.30" + process $proc$libresoc.v:155053$7951 assign { } { } assign $1\mul_op__is_32bit[0:0] 1'0 sync always sync init update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:155266.7-155266.31" - process $proc$libresoc.v:155266$7952 + attribute \src "libresoc.v:155062.7-155062.31" + process $proc$libresoc.v:155062$7952 assign { } { } assign $1\mul_op__is_signed[0:0] 1'0 sync always sync init update \mul_op__is_signed $1\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:155275.7-155275.28" - process $proc$libresoc.v:155275$7953 + attribute \src "libresoc.v:155071.7-155071.28" + process $proc$libresoc.v:155071$7953 assign { } { } assign $1\mul_op__oe__oe[0:0] 1'0 sync always sync init update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:155284.7-155284.28" - process $proc$libresoc.v:155284$7954 + attribute \src "libresoc.v:155080.7-155080.28" + process $proc$libresoc.v:155080$7954 assign { } { } assign $1\mul_op__oe__ok[0:0] 1'0 sync always sync init update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:155293.7-155293.28" - process $proc$libresoc.v:155293$7955 + attribute \src "libresoc.v:155089.7-155089.28" + process $proc$libresoc.v:155089$7955 assign { } { } assign $1\mul_op__rc__ok[0:0] 1'0 sync always sync init update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:155302.7-155302.28" - process $proc$libresoc.v:155302$7956 + attribute \src "libresoc.v:155098.7-155098.28" + process $proc$libresoc.v:155098$7956 assign { } { } assign $1\mul_op__rc__rc[0:0] 1'0 sync always sync init update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:155311.7-155311.31" - process $proc$libresoc.v:155311$7957 + attribute \src "libresoc.v:155107.7-155107.31" + process $proc$libresoc.v:155107$7957 assign { } { } assign $1\mul_op__write_cr0[0:0] 1'0 sync always sync init update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:155320.13-155320.25" - process $proc$libresoc.v:155320$7958 + attribute \src "libresoc.v:155116.13-155116.25" + process $proc$libresoc.v:155116$7958 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:155335.7-155335.21" - process $proc$libresoc.v:155335$7959 + attribute \src "libresoc.v:155131.7-155131.21" + process $proc$libresoc.v:155131$7959 assign { } { } assign $1\neg_res[0:0] 1'0 sync always sync init update \neg_res $1\neg_res[0:0] end - attribute \src "libresoc.v:155342.7-155342.23" - process $proc$libresoc.v:155342$7960 + attribute \src "libresoc.v:155138.7-155138.23" + process $proc$libresoc.v:155138$7960 assign { } { } assign $1\neg_res32[0:0] 1'0 sync always sync init update \neg_res32 $1\neg_res32[0:0] end - attribute \src "libresoc.v:155356.7-155356.20" - process $proc$libresoc.v:155356$7961 + attribute \src "libresoc.v:155152.7-155152.20" + process $proc$libresoc.v:155152$7961 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:155361.14-155361.39" - process $proc$libresoc.v:155361$7962 + attribute \src "libresoc.v:155157.14-155157.39" + process $proc$libresoc.v:155157$7962 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:155370.14-155370.39" - process $proc$libresoc.v:155370$7963 + attribute \src "libresoc.v:155166.14-155166.39" + process $proc$libresoc.v:155166$7963 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:155379.7-155379.20" - process $proc$libresoc.v:155379$7964 + attribute \src "libresoc.v:155175.7-155175.20" + process $proc$libresoc.v:155175$7964 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:155387.3-155388.35" - process $proc$libresoc.v:155387$7873 + attribute \src "libresoc.v:155183.3-155184.35" + process $proc$libresoc.v:155183$7873 assign { } { } assign $0\neg_res32[0:0] \neg_res32$next sync posedge \coresync_clk update \neg_res32 $0\neg_res32[0:0] end - attribute \src "libresoc.v:155389.3-155390.31" - process $proc$libresoc.v:155389$7874 + attribute \src "libresoc.v:155185.3-155186.31" + process $proc$libresoc.v:155185$7874 assign { } { } assign $0\neg_res[0:0] \neg_res$next sync posedge \coresync_clk update \neg_res $0\neg_res[0:0] end - attribute \src "libresoc.v:155391.3-155392.29" - process $proc$libresoc.v:155391$7875 + attribute \src "libresoc.v:155187.3-155188.29" + process $proc$libresoc.v:155187$7875 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:155393.3-155394.21" - process $proc$libresoc.v:155393$7876 + attribute \src "libresoc.v:155189.3-155190.21" + process $proc$libresoc.v:155189$7876 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:155395.3-155396.21" - process $proc$libresoc.v:155395$7877 + attribute \src "libresoc.v:155191.3-155192.21" + process $proc$libresoc.v:155191$7877 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:155397.3-155398.51" - process $proc$libresoc.v:155397$7878 + attribute \src "libresoc.v:155193.3-155194.51" + process $proc$libresoc.v:155193$7878 assign { } { } assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next sync posedge \coresync_clk update \mul_op__insn_type $0\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:155399.3-155400.47" - process $proc$libresoc.v:155399$7879 + attribute \src "libresoc.v:155195.3-155196.47" + process $proc$libresoc.v:155195$7879 assign { } { } assign $0\mul_op__fn_unit[13:0] \mul_op__fn_unit$next sync posedge \coresync_clk update \mul_op__fn_unit $0\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:155401.3-155402.61" - process $proc$libresoc.v:155401$7880 + attribute \src "libresoc.v:155197.3-155198.61" + process $proc$libresoc.v:155197$7880 assign { } { } assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next sync posedge \coresync_clk update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:155403.3-155404.57" - process $proc$libresoc.v:155403$7881 + attribute \src "libresoc.v:155199.3-155200.57" + process $proc$libresoc.v:155199$7881 assign { } { } assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next sync posedge \coresync_clk update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:155405.3-155406.45" - process $proc$libresoc.v:155405$7882 + attribute \src "libresoc.v:155201.3-155202.45" + process $proc$libresoc.v:155201$7882 assign { } { } assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next sync posedge \coresync_clk update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:155407.3-155408.45" - process $proc$libresoc.v:155407$7883 + attribute \src "libresoc.v:155203.3-155204.45" + process $proc$libresoc.v:155203$7883 assign { } { } assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next sync posedge \coresync_clk update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:155409.3-155410.45" - process $proc$libresoc.v:155409$7884 + attribute \src "libresoc.v:155205.3-155206.45" + process $proc$libresoc.v:155205$7884 assign { } { } assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next sync posedge \coresync_clk update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:155411.3-155412.45" - process $proc$libresoc.v:155411$7885 + attribute \src "libresoc.v:155207.3-155208.45" + process $proc$libresoc.v:155207$7885 assign { } { } assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next sync posedge \coresync_clk update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:155413.3-155414.51" - process $proc$libresoc.v:155413$7886 + attribute \src "libresoc.v:155209.3-155210.51" + process $proc$libresoc.v:155209$7886 assign { } { } assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next sync posedge \coresync_clk update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:155415.3-155416.49" - process $proc$libresoc.v:155415$7887 + attribute \src "libresoc.v:155211.3-155212.49" + process $proc$libresoc.v:155211$7887 assign { } { } assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next sync posedge \coresync_clk update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:155417.3-155418.51" - process $proc$libresoc.v:155417$7888 + attribute \src "libresoc.v:155213.3-155214.51" + process $proc$libresoc.v:155213$7888 assign { } { } assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next sync posedge \coresync_clk update \mul_op__is_signed $0\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:155419.3-155420.41" - process $proc$libresoc.v:155419$7889 + attribute \src "libresoc.v:155215.3-155216.41" + process $proc$libresoc.v:155215$7889 assign { } { } assign $0\mul_op__insn[31:0] \mul_op__insn$next sync posedge \coresync_clk update \mul_op__insn $0\mul_op__insn[31:0] end - attribute \src "libresoc.v:155421.3-155422.27" - process $proc$libresoc.v:155421$7890 + attribute \src "libresoc.v:155217.3-155218.27" + process $proc$libresoc.v:155217$7890 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:155423.3-155424.29" - process $proc$libresoc.v:155423$7891 + attribute \src "libresoc.v:155219.3-155220.29" + process $proc$libresoc.v:155219$7891 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:155503.3-155520.6" - process $proc$libresoc.v:155503$7892 + attribute \src "libresoc.v:155299.3-155316.6" + process $proc$libresoc.v:155299$7892 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$7893 $2\r_busy$next[0:0]$7895 - attribute \src "libresoc.v:155504.5-155504.29" + attribute \src "libresoc.v:155300.5-155300.29" switch \initial - attribute \src "libresoc.v:155504.9-155504.17" + attribute \src "libresoc.v:155300.9-155300.17" case 1'1 case end @@ -289086,14 +288920,14 @@ module \mul_pipe1 sync always update \r_busy$next $0\r_busy$next[0:0]$7893 end - attribute \src "libresoc.v:155521.3-155533.6" - process $proc$libresoc.v:155521$7896 + attribute \src "libresoc.v:155317.3-155329.6" + process $proc$libresoc.v:155317$7896 assign { } { } assign { } { } assign $0\muxid$next[1:0]$7897 $1\muxid$next[1:0]$7898 - attribute \src "libresoc.v:155522.5-155522.29" + attribute \src "libresoc.v:155318.5-155318.29" switch \initial - attribute \src "libresoc.v:155522.9-155522.17" + attribute \src "libresoc.v:155318.9-155318.17" case 1'1 case end @@ -289113,8 +288947,8 @@ module \mul_pipe1 sync always update \muxid$next $0\muxid$next[1:0]$7897 end - attribute \src "libresoc.v:155534.3-155569.6" - process $proc$libresoc.v:155534$7899 + attribute \src "libresoc.v:155330.3-155365.6" + process $proc$libresoc.v:155330$7899 assign { } { } assign { } { } assign { } { } @@ -289157,9 +288991,9 @@ module \mul_pipe1 assign $0\mul_op__oe__ok$next[0:0]$7908 $2\mul_op__oe__ok$next[0:0]$7927 assign $0\mul_op__rc__ok$next[0:0]$7909 $2\mul_op__rc__ok$next[0:0]$7928 assign $0\mul_op__rc__rc$next[0:0]$7910 $2\mul_op__rc__rc$next[0:0]$7929 - attribute \src "libresoc.v:155535.5-155535.29" + attribute \src "libresoc.v:155331.5-155331.29" switch \initial - attribute \src "libresoc.v:155535.9-155535.17" + attribute \src "libresoc.v:155331.9-155331.17" case 1'1 case end @@ -289247,14 +289081,14 @@ module \mul_pipe1 update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7910 update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7911 end - attribute \src "libresoc.v:155570.3-155582.6" - process $proc$libresoc.v:155570$7930 + attribute \src "libresoc.v:155366.3-155378.6" + process $proc$libresoc.v:155366$7930 assign { } { } assign { } { } assign $0\ra$next[63:0]$7931 $1\ra$next[63:0]$7932 - attribute \src "libresoc.v:155571.5-155571.29" + attribute \src "libresoc.v:155367.5-155367.29" switch \initial - attribute \src "libresoc.v:155571.9-155571.17" + attribute \src "libresoc.v:155367.9-155367.17" case 1'1 case end @@ -289274,14 +289108,14 @@ module \mul_pipe1 sync always update \ra$next $0\ra$next[63:0]$7931 end - attribute \src "libresoc.v:155583.3-155595.6" - process $proc$libresoc.v:155583$7933 + attribute \src "libresoc.v:155379.3-155391.6" + process $proc$libresoc.v:155379$7933 assign { } { } assign { } { } assign $0\rb$next[63:0]$7934 $1\rb$next[63:0]$7935 - attribute \src "libresoc.v:155584.5-155584.29" + attribute \src "libresoc.v:155380.5-155380.29" switch \initial - attribute \src "libresoc.v:155584.9-155584.17" + attribute \src "libresoc.v:155380.9-155380.17" case 1'1 case end @@ -289301,14 +289135,14 @@ module \mul_pipe1 sync always update \rb$next $0\rb$next[63:0]$7934 end - attribute \src "libresoc.v:155596.3-155608.6" - process $proc$libresoc.v:155596$7936 + attribute \src "libresoc.v:155392.3-155404.6" + process $proc$libresoc.v:155392$7936 assign { } { } assign { } { } assign $0\xer_so$next[0:0]$7937 $1\xer_so$next[0:0]$7938 - attribute \src "libresoc.v:155597.5-155597.29" + attribute \src "libresoc.v:155393.5-155393.29" switch \initial - attribute \src "libresoc.v:155597.9-155597.17" + attribute \src "libresoc.v:155393.9-155393.17" case 1'1 case end @@ -289328,14 +289162,14 @@ module \mul_pipe1 sync always update \xer_so$next $0\xer_so$next[0:0]$7937 end - attribute \src "libresoc.v:155609.3-155621.6" - process $proc$libresoc.v:155609$7939 + attribute \src "libresoc.v:155405.3-155417.6" + process $proc$libresoc.v:155405$7939 assign { } { } assign { } { } assign $0\neg_res$next[0:0]$7940 $1\neg_res$next[0:0]$7941 - attribute \src "libresoc.v:155610.5-155610.29" + attribute \src "libresoc.v:155406.5-155406.29" switch \initial - attribute \src "libresoc.v:155610.9-155610.17" + attribute \src "libresoc.v:155406.9-155406.17" case 1'1 case end @@ -289355,14 +289189,14 @@ module \mul_pipe1 sync always update \neg_res$next $0\neg_res$next[0:0]$7940 end - attribute \src "libresoc.v:155622.3-155634.6" - process $proc$libresoc.v:155622$7942 + attribute \src "libresoc.v:155418.3-155430.6" + process $proc$libresoc.v:155418$7942 assign { } { } assign { } { } assign $0\neg_res32$next[0:0]$7943 $1\neg_res32$next[0:0]$7944 - attribute \src "libresoc.v:155623.5-155623.29" + attribute \src "libresoc.v:155419.5-155419.29" switch \initial - attribute \src "libresoc.v:155623.9-155623.17" + attribute \src "libresoc.v:155419.9-155419.17" case 1'1 case end @@ -289382,7 +289216,7 @@ module \mul_pipe1 sync always update \neg_res32$next $0\neg_res32$next[0:0]$7943 end - connect \$50 $and$libresoc.v:155386$7872_Y + connect \$50 $and$libresoc.v:155182$7872_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$69 \mul1_neg_res32 @@ -289406,180 +289240,180 @@ module \mul_pipe1 connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:155661.1-156581.10" +attribute \src "libresoc.v:155457.1-156377.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" attribute \generator "nMigen" module \mul_pipe2 - attribute \src "libresoc.v:155662.7-155662.20" + attribute \src "libresoc.v:155458.7-155458.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8008 - attribute \src "libresoc.v:156373.3-156374.53" + attribute \src "libresoc.v:156169.3-156170.53" wire width 14 $0\mul_op__fn_unit$3[13:0]$7976 - attribute \src "libresoc.v:155953.14-155953.44" + attribute \src "libresoc.v:155749.14-155749.44" wire width 14 $0\mul_op__fn_unit$3[13:0]$8052 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8009 - attribute \src "libresoc.v:156375.3-156376.67" + attribute \src "libresoc.v:156171.3-156172.67" wire width 64 $0\mul_op__imm_data__data$4[63:0]$7978 - attribute \src "libresoc.v:155979.14-155979.63" + attribute \src "libresoc.v:155775.14-155775.63" wire width 64 $0\mul_op__imm_data__data$4[63:0]$8054 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__imm_data__ok$5$next[0:0]$8010 - attribute \src "libresoc.v:156377.3-156378.63" + attribute \src "libresoc.v:156173.3-156174.63" wire $0\mul_op__imm_data__ok$5[0:0]$7980 - attribute \src "libresoc.v:155988.7-155988.38" + attribute \src "libresoc.v:155784.7-155784.38" wire $0\mul_op__imm_data__ok$5[0:0]$8056 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire width 32 $0\mul_op__insn$13$next[31:0]$8011 - attribute \src "libresoc.v:156393.3-156394.49" + attribute \src "libresoc.v:156189.3-156190.49" wire width 32 $0\mul_op__insn$13[31:0]$7996 - attribute \src "libresoc.v:155995.14-155995.39" + attribute \src "libresoc.v:155791.14-155791.39" wire width 32 $0\mul_op__insn$13[31:0]$8058 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire width 7 $0\mul_op__insn_type$2$next[6:0]$8012 - attribute \src "libresoc.v:156371.3-156372.57" + attribute \src "libresoc.v:156167.3-156168.57" wire width 7 $0\mul_op__insn_type$2[6:0]$7974 - attribute \src "libresoc.v:156154.13-156154.42" + attribute \src "libresoc.v:155950.13-155950.42" wire width 7 $0\mul_op__insn_type$2[6:0]$8060 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__is_32bit$11$next[0:0]$8013 - attribute \src "libresoc.v:156389.3-156390.57" + attribute \src "libresoc.v:156185.3-156186.57" wire $0\mul_op__is_32bit$11[0:0]$7992 - attribute \src "libresoc.v:156238.7-156238.35" + attribute \src "libresoc.v:156034.7-156034.35" wire $0\mul_op__is_32bit$11[0:0]$8062 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__is_signed$12$next[0:0]$8014 - attribute \src "libresoc.v:156391.3-156392.59" + attribute \src "libresoc.v:156187.3-156188.59" wire $0\mul_op__is_signed$12[0:0]$7994 - attribute \src "libresoc.v:156247.7-156247.36" + attribute \src "libresoc.v:156043.7-156043.36" wire $0\mul_op__is_signed$12[0:0]$8064 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__oe__oe$8$next[0:0]$8015 - attribute \src "libresoc.v:156383.3-156384.51" + attribute \src "libresoc.v:156179.3-156180.51" wire $0\mul_op__oe__oe$8[0:0]$7986 - attribute \src "libresoc.v:156258.7-156258.32" + attribute \src "libresoc.v:156054.7-156054.32" wire $0\mul_op__oe__oe$8[0:0]$8066 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__oe__ok$9$next[0:0]$8016 - attribute \src "libresoc.v:156385.3-156386.51" + attribute \src "libresoc.v:156181.3-156182.51" wire $0\mul_op__oe__ok$9[0:0]$7988 - attribute \src "libresoc.v:156267.7-156267.32" + attribute \src "libresoc.v:156063.7-156063.32" wire $0\mul_op__oe__ok$9[0:0]$8068 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__rc__ok$7$next[0:0]$8017 - attribute \src "libresoc.v:156381.3-156382.51" + attribute \src "libresoc.v:156177.3-156178.51" wire $0\mul_op__rc__ok$7[0:0]$7984 - attribute \src "libresoc.v:156276.7-156276.32" + attribute \src "libresoc.v:156072.7-156072.32" wire $0\mul_op__rc__ok$7[0:0]$8070 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__rc__rc$6$next[0:0]$8018 - attribute \src "libresoc.v:156379.3-156380.51" + attribute \src "libresoc.v:156175.3-156176.51" wire $0\mul_op__rc__rc$6[0:0]$7982 - attribute \src "libresoc.v:156285.7-156285.32" + attribute \src "libresoc.v:156081.7-156081.32" wire $0\mul_op__rc__rc$6[0:0]$8072 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__write_cr0$10$next[0:0]$8019 - attribute \src "libresoc.v:156387.3-156388.59" + attribute \src "libresoc.v:156183.3-156184.59" wire $0\mul_op__write_cr0$10[0:0]$7990 - attribute \src "libresoc.v:156292.7-156292.36" + attribute \src "libresoc.v:156088.7-156088.36" wire $0\mul_op__write_cr0$10[0:0]$8074 - attribute \src "libresoc.v:156462.3-156474.6" + attribute \src "libresoc.v:156258.3-156270.6" wire width 2 $0\muxid$1$next[1:0]$8005 - attribute \src "libresoc.v:156395.3-156396.33" + attribute \src "libresoc.v:156191.3-156192.33" wire width 2 $0\muxid$1[1:0]$7998 - attribute \src "libresoc.v:156301.13-156301.29" + attribute \src "libresoc.v:156097.13-156097.29" wire width 2 $0\muxid$1[1:0]$8076 - attribute \src "libresoc.v:156537.3-156549.6" + attribute \src "libresoc.v:156333.3-156345.6" wire $0\neg_res$15$next[0:0]$8045 - attribute \src "libresoc.v:156365.3-156366.39" + attribute \src "libresoc.v:156161.3-156162.39" wire $0\neg_res$15[0:0]$7969 - attribute \src "libresoc.v:156316.7-156316.26" + attribute \src "libresoc.v:156112.7-156112.26" wire $0\neg_res$15[0:0]$8078 - attribute \src "libresoc.v:156550.3-156562.6" + attribute \src "libresoc.v:156346.3-156358.6" wire $0\neg_res32$16$next[0:0]$8048 - attribute \src "libresoc.v:156363.3-156364.43" + attribute \src "libresoc.v:156159.3-156160.43" wire $0\neg_res32$16[0:0]$7967 - attribute \src "libresoc.v:156325.7-156325.28" + attribute \src "libresoc.v:156121.7-156121.28" wire $0\neg_res32$16[0:0]$8080 - attribute \src "libresoc.v:156511.3-156523.6" + attribute \src "libresoc.v:156307.3-156319.6" wire width 129 $0\o$next[128:0]$8039 - attribute \src "libresoc.v:156369.3-156370.19" + attribute \src "libresoc.v:156165.3-156166.19" wire width 129 $0\o[128:0] - attribute \src "libresoc.v:156444.3-156461.6" + attribute \src "libresoc.v:156240.3-156257.6" wire $0\r_busy$next[0:0]$8001 - attribute \src "libresoc.v:156397.3-156398.29" + attribute \src "libresoc.v:156193.3-156194.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:156524.3-156536.6" + attribute \src "libresoc.v:156320.3-156332.6" wire $0\xer_so$14$next[0:0]$8042 - attribute \src "libresoc.v:156367.3-156368.37" + attribute \src "libresoc.v:156163.3-156164.37" wire $0\xer_so$14[0:0]$7971 - attribute \src "libresoc.v:156357.7-156357.25" + attribute \src "libresoc.v:156153.7-156153.25" wire $0\xer_so$14[0:0]$8084 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8020 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8021 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__imm_data__ok$5$next[0:0]$8022 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire width 32 $1\mul_op__insn$13$next[31:0]$8023 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire width 7 $1\mul_op__insn_type$2$next[6:0]$8024 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__is_32bit$11$next[0:0]$8025 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__is_signed$12$next[0:0]$8026 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__oe__oe$8$next[0:0]$8027 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__oe__ok$9$next[0:0]$8028 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__rc__ok$7$next[0:0]$8029 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__rc__rc$6$next[0:0]$8030 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__write_cr0$10$next[0:0]$8031 - attribute \src "libresoc.v:156462.3-156474.6" + attribute \src "libresoc.v:156258.3-156270.6" wire width 2 $1\muxid$1$next[1:0]$8006 - attribute \src "libresoc.v:156537.3-156549.6" + attribute \src "libresoc.v:156333.3-156345.6" wire $1\neg_res$15$next[0:0]$8046 - attribute \src "libresoc.v:156550.3-156562.6" + attribute \src "libresoc.v:156346.3-156358.6" wire $1\neg_res32$16$next[0:0]$8049 - attribute \src "libresoc.v:156511.3-156523.6" + attribute \src "libresoc.v:156307.3-156319.6" wire width 129 $1\o$next[128:0]$8040 - attribute \src "libresoc.v:156332.15-156332.57" + attribute \src "libresoc.v:156128.15-156128.57" wire width 129 $1\o[128:0] - attribute \src "libresoc.v:156444.3-156461.6" + attribute \src "libresoc.v:156240.3-156257.6" wire $1\r_busy$next[0:0]$8002 - attribute \src "libresoc.v:156346.7-156346.20" + attribute \src "libresoc.v:156142.7-156142.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:156524.3-156536.6" + attribute \src "libresoc.v:156320.3-156332.6" wire $1\xer_so$14$next[0:0]$8043 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8032 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $2\mul_op__imm_data__ok$5$next[0:0]$8033 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $2\mul_op__oe__oe$8$next[0:0]$8034 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $2\mul_op__oe__ok$9$next[0:0]$8035 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $2\mul_op__rc__ok$7$next[0:0]$8036 - attribute \src "libresoc.v:156475.3-156510.6" + attribute \src "libresoc.v:156271.3-156306.6" wire $2\mul_op__rc__rc$6$next[0:0]$8037 - attribute \src "libresoc.v:156444.3-156461.6" + attribute \src "libresoc.v:156240.3-156257.6" wire $2\r_busy$next[0:0]$8003 - attribute \src "libresoc.v:156362.18-156362.118" - wire $and$libresoc.v:156362$7965_Y + attribute \src "libresoc.v:156158.18-156158.118" + wire $and$libresoc.v:156158$7965_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:155662.7-155662.15" + attribute \src "libresoc.v:155458.7-155458.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -290258,7 +290092,7 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:156362$7965 + cell $and $and$libresoc.v:156158$7965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -290266,10 +290100,10 @@ module \mul_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$33 connect \B \p_ready_o - connect \Y $and$libresoc.v:156362$7965_Y + connect \Y $and$libresoc.v:156158$7965_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:156399.8-156435.4" + attribute \src "libresoc.v:156195.8-156231.4" cell \mul2 \mul2 connect \mul_op__fn_unit \mul2_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 @@ -290308,304 +290142,304 @@ module \mul_pipe2 connect \xer_so$14 \mul2_xer_so$30 end attribute \module_not_derived 1 - attribute \src "libresoc.v:156436.10-156439.4" + attribute \src "libresoc.v:156232.10-156235.4" cell \n$97 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:156440.10-156443.4" + attribute \src "libresoc.v:156236.10-156239.4" cell \p$96 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:155662.7-155662.20" - process $proc$libresoc.v:155662$8050 + attribute \src "libresoc.v:155458.7-155458.20" + process $proc$libresoc.v:155458$8050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155953.14-155953.44" - process $proc$libresoc.v:155953$8051 + attribute \src "libresoc.v:155749.14-155749.44" + process $proc$libresoc.v:155749$8051 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$8052 14'00000000000000 sync always sync init update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8052 end - attribute \src "libresoc.v:155979.14-155979.63" - process $proc$libresoc.v:155979$8053 + attribute \src "libresoc.v:155775.14-155775.63" + process $proc$libresoc.v:155775$8053 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$8054 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8054 end - attribute \src "libresoc.v:155988.7-155988.38" - process $proc$libresoc.v:155988$8055 + attribute \src "libresoc.v:155784.7-155784.38" + process $proc$libresoc.v:155784$8055 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$8056 1'0 sync always sync init update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8056 end - attribute \src "libresoc.v:155995.14-155995.39" - process $proc$libresoc.v:155995$8057 + attribute \src "libresoc.v:155791.14-155791.39" + process $proc$libresoc.v:155791$8057 assign { } { } assign $0\mul_op__insn$13[31:0]$8058 0 sync always sync init update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8058 end - attribute \src "libresoc.v:156154.13-156154.42" - process $proc$libresoc.v:156154$8059 + attribute \src "libresoc.v:155950.13-155950.42" + process $proc$libresoc.v:155950$8059 assign { } { } assign $0\mul_op__insn_type$2[6:0]$8060 7'0000000 sync always sync init update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8060 end - attribute \src "libresoc.v:156238.7-156238.35" - process $proc$libresoc.v:156238$8061 + attribute \src "libresoc.v:156034.7-156034.35" + process $proc$libresoc.v:156034$8061 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$8062 1'0 sync always sync init update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8062 end - attribute \src "libresoc.v:156247.7-156247.36" - process $proc$libresoc.v:156247$8063 + attribute \src "libresoc.v:156043.7-156043.36" + process $proc$libresoc.v:156043$8063 assign { } { } assign $0\mul_op__is_signed$12[0:0]$8064 1'0 sync always sync init update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8064 end - attribute \src "libresoc.v:156258.7-156258.32" - process $proc$libresoc.v:156258$8065 + attribute \src "libresoc.v:156054.7-156054.32" + process $proc$libresoc.v:156054$8065 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$8066 1'0 sync always sync init update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8066 end - attribute \src "libresoc.v:156267.7-156267.32" - process $proc$libresoc.v:156267$8067 + attribute \src "libresoc.v:156063.7-156063.32" + process $proc$libresoc.v:156063$8067 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$8068 1'0 sync always sync init update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8068 end - attribute \src "libresoc.v:156276.7-156276.32" - process $proc$libresoc.v:156276$8069 + attribute \src "libresoc.v:156072.7-156072.32" + process $proc$libresoc.v:156072$8069 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$8070 1'0 sync always sync init update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8070 end - attribute \src "libresoc.v:156285.7-156285.32" - process $proc$libresoc.v:156285$8071 + attribute \src "libresoc.v:156081.7-156081.32" + process $proc$libresoc.v:156081$8071 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$8072 1'0 sync always sync init update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8072 end - attribute \src "libresoc.v:156292.7-156292.36" - process $proc$libresoc.v:156292$8073 + attribute \src "libresoc.v:156088.7-156088.36" + process $proc$libresoc.v:156088$8073 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$8074 1'0 sync always sync init update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8074 end - attribute \src "libresoc.v:156301.13-156301.29" - process $proc$libresoc.v:156301$8075 + attribute \src "libresoc.v:156097.13-156097.29" + process $proc$libresoc.v:156097$8075 assign { } { } assign $0\muxid$1[1:0]$8076 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8076 end - attribute \src "libresoc.v:156316.7-156316.26" - process $proc$libresoc.v:156316$8077 + attribute \src "libresoc.v:156112.7-156112.26" + process $proc$libresoc.v:156112$8077 assign { } { } assign $0\neg_res$15[0:0]$8078 1'0 sync always sync init update \neg_res$15 $0\neg_res$15[0:0]$8078 end - attribute \src "libresoc.v:156325.7-156325.28" - process $proc$libresoc.v:156325$8079 + attribute \src "libresoc.v:156121.7-156121.28" + process $proc$libresoc.v:156121$8079 assign { } { } assign $0\neg_res32$16[0:0]$8080 1'0 sync always sync init update \neg_res32$16 $0\neg_res32$16[0:0]$8080 end - attribute \src "libresoc.v:156332.15-156332.57" - process $proc$libresoc.v:156332$8081 + attribute \src "libresoc.v:156128.15-156128.57" + process $proc$libresoc.v:156128$8081 assign { } { } assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[128:0] end - attribute \src "libresoc.v:156346.7-156346.20" - process $proc$libresoc.v:156346$8082 + attribute \src "libresoc.v:156142.7-156142.20" + process $proc$libresoc.v:156142$8082 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:156357.7-156357.25" - process $proc$libresoc.v:156357$8083 + attribute \src "libresoc.v:156153.7-156153.25" + process $proc$libresoc.v:156153$8083 assign { } { } assign $0\xer_so$14[0:0]$8084 1'0 sync always sync init update \xer_so$14 $0\xer_so$14[0:0]$8084 end - attribute \src "libresoc.v:156363.3-156364.43" - process $proc$libresoc.v:156363$7966 + attribute \src "libresoc.v:156159.3-156160.43" + process $proc$libresoc.v:156159$7966 assign { } { } assign $0\neg_res32$16[0:0]$7967 \neg_res32$16$next sync posedge \coresync_clk update \neg_res32$16 $0\neg_res32$16[0:0]$7967 end - attribute \src "libresoc.v:156365.3-156366.39" - process $proc$libresoc.v:156365$7968 + attribute \src "libresoc.v:156161.3-156162.39" + process $proc$libresoc.v:156161$7968 assign { } { } assign $0\neg_res$15[0:0]$7969 \neg_res$15$next sync posedge \coresync_clk update \neg_res$15 $0\neg_res$15[0:0]$7969 end - attribute \src "libresoc.v:156367.3-156368.37" - process $proc$libresoc.v:156367$7970 + attribute \src "libresoc.v:156163.3-156164.37" + process $proc$libresoc.v:156163$7970 assign { } { } assign $0\xer_so$14[0:0]$7971 \xer_so$14$next sync posedge \coresync_clk update \xer_so$14 $0\xer_so$14[0:0]$7971 end - attribute \src "libresoc.v:156369.3-156370.19" - process $proc$libresoc.v:156369$7972 + attribute \src "libresoc.v:156165.3-156166.19" + process $proc$libresoc.v:156165$7972 assign { } { } assign $0\o[128:0] \o$next sync posedge \coresync_clk update \o $0\o[128:0] end - attribute \src "libresoc.v:156371.3-156372.57" - process $proc$libresoc.v:156371$7973 + attribute \src "libresoc.v:156167.3-156168.57" + process $proc$libresoc.v:156167$7973 assign { } { } assign $0\mul_op__insn_type$2[6:0]$7974 \mul_op__insn_type$2$next sync posedge \coresync_clk update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7974 end - attribute \src "libresoc.v:156373.3-156374.53" - process $proc$libresoc.v:156373$7975 + attribute \src "libresoc.v:156169.3-156170.53" + process $proc$libresoc.v:156169$7975 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$7976 \mul_op__fn_unit$3$next sync posedge \coresync_clk update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$7976 end - attribute \src "libresoc.v:156375.3-156376.67" - process $proc$libresoc.v:156375$7977 + attribute \src "libresoc.v:156171.3-156172.67" + process $proc$libresoc.v:156171$7977 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$7978 \mul_op__imm_data__data$4$next sync posedge \coresync_clk update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7978 end - attribute \src "libresoc.v:156377.3-156378.63" - process $proc$libresoc.v:156377$7979 + attribute \src "libresoc.v:156173.3-156174.63" + process $proc$libresoc.v:156173$7979 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$7980 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7980 end - attribute \src "libresoc.v:156379.3-156380.51" - process $proc$libresoc.v:156379$7981 + attribute \src "libresoc.v:156175.3-156176.51" + process $proc$libresoc.v:156175$7981 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$7982 \mul_op__rc__rc$6$next sync posedge \coresync_clk update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7982 end - attribute \src "libresoc.v:156381.3-156382.51" - process $proc$libresoc.v:156381$7983 + attribute \src "libresoc.v:156177.3-156178.51" + process $proc$libresoc.v:156177$7983 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$7984 \mul_op__rc__ok$7$next sync posedge \coresync_clk update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7984 end - attribute \src "libresoc.v:156383.3-156384.51" - process $proc$libresoc.v:156383$7985 + attribute \src "libresoc.v:156179.3-156180.51" + process $proc$libresoc.v:156179$7985 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$7986 \mul_op__oe__oe$8$next sync posedge \coresync_clk update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7986 end - attribute \src "libresoc.v:156385.3-156386.51" - process $proc$libresoc.v:156385$7987 + attribute \src "libresoc.v:156181.3-156182.51" + process $proc$libresoc.v:156181$7987 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$7988 \mul_op__oe__ok$9$next sync posedge \coresync_clk update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7988 end - attribute \src "libresoc.v:156387.3-156388.59" - process $proc$libresoc.v:156387$7989 + attribute \src "libresoc.v:156183.3-156184.59" + process $proc$libresoc.v:156183$7989 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$7990 \mul_op__write_cr0$10$next sync posedge \coresync_clk update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7990 end - attribute \src "libresoc.v:156389.3-156390.57" - process $proc$libresoc.v:156389$7991 + attribute \src "libresoc.v:156185.3-156186.57" + process $proc$libresoc.v:156185$7991 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$7992 \mul_op__is_32bit$11$next sync posedge \coresync_clk update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7992 end - attribute \src "libresoc.v:156391.3-156392.59" - process $proc$libresoc.v:156391$7993 + attribute \src "libresoc.v:156187.3-156188.59" + process $proc$libresoc.v:156187$7993 assign { } { } assign $0\mul_op__is_signed$12[0:0]$7994 \mul_op__is_signed$12$next sync posedge \coresync_clk update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7994 end - attribute \src "libresoc.v:156393.3-156394.49" - process $proc$libresoc.v:156393$7995 + attribute \src "libresoc.v:156189.3-156190.49" + process $proc$libresoc.v:156189$7995 assign { } { } assign $0\mul_op__insn$13[31:0]$7996 \mul_op__insn$13$next sync posedge \coresync_clk update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7996 end - attribute \src "libresoc.v:156395.3-156396.33" - process $proc$libresoc.v:156395$7997 + attribute \src "libresoc.v:156191.3-156192.33" + process $proc$libresoc.v:156191$7997 assign { } { } assign $0\muxid$1[1:0]$7998 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$7998 end - attribute \src "libresoc.v:156397.3-156398.29" - process $proc$libresoc.v:156397$7999 + attribute \src "libresoc.v:156193.3-156194.29" + process $proc$libresoc.v:156193$7999 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:156444.3-156461.6" - process $proc$libresoc.v:156444$8000 + attribute \src "libresoc.v:156240.3-156257.6" + process $proc$libresoc.v:156240$8000 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8001 $2\r_busy$next[0:0]$8003 - attribute \src "libresoc.v:156445.5-156445.29" + attribute \src "libresoc.v:156241.5-156241.29" switch \initial - attribute \src "libresoc.v:156445.9-156445.17" + attribute \src "libresoc.v:156241.9-156241.17" case 1'1 case end @@ -290634,14 +290468,14 @@ module \mul_pipe2 sync always update \r_busy$next $0\r_busy$next[0:0]$8001 end - attribute \src "libresoc.v:156462.3-156474.6" - process $proc$libresoc.v:156462$8004 + attribute \src "libresoc.v:156258.3-156270.6" + process $proc$libresoc.v:156258$8004 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8005 $1\muxid$1$next[1:0]$8006 - attribute \src "libresoc.v:156463.5-156463.29" + attribute \src "libresoc.v:156259.5-156259.29" switch \initial - attribute \src "libresoc.v:156463.9-156463.17" + attribute \src "libresoc.v:156259.9-156259.17" case 1'1 case end @@ -290661,8 +290495,8 @@ module \mul_pipe2 sync always update \muxid$1$next $0\muxid$1$next[1:0]$8005 end - attribute \src "libresoc.v:156475.3-156510.6" - process $proc$libresoc.v:156475$8007 + attribute \src "libresoc.v:156271.3-156306.6" + process $proc$libresoc.v:156271$8007 assign { } { } assign { } { } assign { } { } @@ -290705,9 +290539,9 @@ module \mul_pipe2 assign $0\mul_op__oe__ok$9$next[0:0]$8016 $2\mul_op__oe__ok$9$next[0:0]$8035 assign $0\mul_op__rc__ok$7$next[0:0]$8017 $2\mul_op__rc__ok$7$next[0:0]$8036 assign $0\mul_op__rc__rc$6$next[0:0]$8018 $2\mul_op__rc__rc$6$next[0:0]$8037 - attribute \src "libresoc.v:156476.5-156476.29" + attribute \src "libresoc.v:156272.5-156272.29" switch \initial - attribute \src "libresoc.v:156476.9-156476.17" + attribute \src "libresoc.v:156272.9-156272.17" case 1'1 case end @@ -290795,14 +290629,14 @@ module \mul_pipe2 update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8018 update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8019 end - attribute \src "libresoc.v:156511.3-156523.6" - process $proc$libresoc.v:156511$8038 + attribute \src "libresoc.v:156307.3-156319.6" + process $proc$libresoc.v:156307$8038 assign { } { } assign { } { } assign $0\o$next[128:0]$8039 $1\o$next[128:0]$8040 - attribute \src "libresoc.v:156512.5-156512.29" + attribute \src "libresoc.v:156308.5-156308.29" switch \initial - attribute \src "libresoc.v:156512.9-156512.17" + attribute \src "libresoc.v:156308.9-156308.17" case 1'1 case end @@ -290822,14 +290656,14 @@ module \mul_pipe2 sync always update \o$next $0\o$next[128:0]$8039 end - attribute \src "libresoc.v:156524.3-156536.6" - process $proc$libresoc.v:156524$8041 + attribute \src "libresoc.v:156320.3-156332.6" + process $proc$libresoc.v:156320$8041 assign { } { } assign { } { } assign $0\xer_so$14$next[0:0]$8042 $1\xer_so$14$next[0:0]$8043 - attribute \src "libresoc.v:156525.5-156525.29" + attribute \src "libresoc.v:156321.5-156321.29" switch \initial - attribute \src "libresoc.v:156525.9-156525.17" + attribute \src "libresoc.v:156321.9-156321.17" case 1'1 case end @@ -290849,14 +290683,14 @@ module \mul_pipe2 sync always update \xer_so$14$next $0\xer_so$14$next[0:0]$8042 end - attribute \src "libresoc.v:156537.3-156549.6" - process $proc$libresoc.v:156537$8044 + attribute \src "libresoc.v:156333.3-156345.6" + process $proc$libresoc.v:156333$8044 assign { } { } assign { } { } assign $0\neg_res$15$next[0:0]$8045 $1\neg_res$15$next[0:0]$8046 - attribute \src "libresoc.v:156538.5-156538.29" + attribute \src "libresoc.v:156334.5-156334.29" switch \initial - attribute \src "libresoc.v:156538.9-156538.17" + attribute \src "libresoc.v:156334.9-156334.17" case 1'1 case end @@ -290876,14 +290710,14 @@ module \mul_pipe2 sync always update \neg_res$15$next $0\neg_res$15$next[0:0]$8045 end - attribute \src "libresoc.v:156550.3-156562.6" - process $proc$libresoc.v:156550$8047 + attribute \src "libresoc.v:156346.3-156358.6" + process $proc$libresoc.v:156346$8047 assign { } { } assign { } { } assign $0\neg_res32$16$next[0:0]$8048 $1\neg_res32$16$next[0:0]$8049 - attribute \src "libresoc.v:156551.5-156551.29" + attribute \src "libresoc.v:156347.5-156347.29" switch \initial - attribute \src "libresoc.v:156551.9-156551.17" + attribute \src "libresoc.v:156347.9-156347.17" case 1'1 case end @@ -290903,7 +290737,7 @@ module \mul_pipe2 sync always update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8048 end - connect \$34 $and$libresoc.v:156362$7965_Y + connect \$34 $and$libresoc.v:156158$7965_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$52 \mul2_neg_res32$32 @@ -290923,218 +290757,218 @@ module \mul_pipe2 connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul2_muxid \muxid end -attribute \src "libresoc.v:156585.1-157881.10" +attribute \src "libresoc.v:156381.1-157677.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" attribute \generator "nMigen" module \mul_pipe3 - attribute \src "libresoc.v:157799.3-157817.6" + attribute \src "libresoc.v:157595.3-157613.6" wire width 4 $0\cr_a$next[3:0]$8168 - attribute \src "libresoc.v:157591.3-157592.25" + attribute \src "libresoc.v:157387.3-157388.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:157799.3-157817.6" + attribute \src "libresoc.v:157595.3-157613.6" wire $0\cr_a_ok$next[0:0]$8169 - attribute \src "libresoc.v:157593.3-157594.31" + attribute \src "libresoc.v:157389.3-157390.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:156586.7-156586.20" + attribute \src "libresoc.v:156382.7-156382.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8131 - attribute \src "libresoc.v:157601.3-157602.53" + attribute \src "libresoc.v:157397.3-157398.53" wire width 14 $0\mul_op__fn_unit$3[13:0]$8099 - attribute \src "libresoc.v:156897.14-156897.44" + attribute \src "libresoc.v:156693.14-156693.44" wire width 14 $0\mul_op__fn_unit$3[13:0]$8189 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8132 - attribute \src "libresoc.v:157603.3-157604.67" + attribute \src "libresoc.v:157399.3-157400.67" wire width 64 $0\mul_op__imm_data__data$4[63:0]$8101 - attribute \src "libresoc.v:156921.14-156921.63" + attribute \src "libresoc.v:156717.14-156717.63" wire width 64 $0\mul_op__imm_data__data$4[63:0]$8191 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__imm_data__ok$5$next[0:0]$8133 - attribute \src "libresoc.v:157605.3-157606.63" + attribute \src "libresoc.v:157401.3-157402.63" wire $0\mul_op__imm_data__ok$5[0:0]$8103 - attribute \src "libresoc.v:156930.7-156930.38" + attribute \src "libresoc.v:156726.7-156726.38" wire $0\mul_op__imm_data__ok$5[0:0]$8193 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire width 32 $0\mul_op__insn$13$next[31:0]$8134 - attribute \src "libresoc.v:157621.3-157622.49" + attribute \src "libresoc.v:157417.3-157418.49" wire width 32 $0\mul_op__insn$13[31:0]$8119 - attribute \src "libresoc.v:156939.14-156939.39" + attribute \src "libresoc.v:156735.14-156735.39" wire width 32 $0\mul_op__insn$13[31:0]$8195 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire width 7 $0\mul_op__insn_type$2$next[6:0]$8135 - attribute \src "libresoc.v:157599.3-157600.57" + attribute \src "libresoc.v:157395.3-157396.57" wire width 7 $0\mul_op__insn_type$2[6:0]$8097 - attribute \src "libresoc.v:157098.13-157098.42" + attribute \src "libresoc.v:156894.13-156894.42" wire width 7 $0\mul_op__insn_type$2[6:0]$8197 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__is_32bit$11$next[0:0]$8136 - attribute \src "libresoc.v:157617.3-157618.57" + attribute \src "libresoc.v:157413.3-157414.57" wire $0\mul_op__is_32bit$11[0:0]$8115 - attribute \src "libresoc.v:157182.7-157182.35" + attribute \src "libresoc.v:156978.7-156978.35" wire $0\mul_op__is_32bit$11[0:0]$8199 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__is_signed$12$next[0:0]$8137 - attribute \src "libresoc.v:157619.3-157620.59" + attribute \src "libresoc.v:157415.3-157416.59" wire $0\mul_op__is_signed$12[0:0]$8117 - attribute \src "libresoc.v:157191.7-157191.36" + attribute \src "libresoc.v:156987.7-156987.36" wire $0\mul_op__is_signed$12[0:0]$8201 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__oe__oe$8$next[0:0]$8138 - attribute \src "libresoc.v:157611.3-157612.51" + attribute \src "libresoc.v:157407.3-157408.51" wire $0\mul_op__oe__oe$8[0:0]$8109 - attribute \src "libresoc.v:157202.7-157202.32" + attribute \src "libresoc.v:156998.7-156998.32" wire $0\mul_op__oe__oe$8[0:0]$8203 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__oe__ok$9$next[0:0]$8139 - attribute \src "libresoc.v:157613.3-157614.51" + attribute \src "libresoc.v:157409.3-157410.51" wire $0\mul_op__oe__ok$9[0:0]$8111 - attribute \src "libresoc.v:157211.7-157211.32" + attribute \src "libresoc.v:157007.7-157007.32" wire $0\mul_op__oe__ok$9[0:0]$8205 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__rc__ok$7$next[0:0]$8140 - attribute \src "libresoc.v:157609.3-157610.51" + attribute \src "libresoc.v:157405.3-157406.51" wire $0\mul_op__rc__ok$7[0:0]$8107 - attribute \src "libresoc.v:157220.7-157220.32" + attribute \src "libresoc.v:157016.7-157016.32" wire $0\mul_op__rc__ok$7[0:0]$8207 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__rc__rc$6$next[0:0]$8141 - attribute \src "libresoc.v:157607.3-157608.51" + attribute \src "libresoc.v:157403.3-157404.51" wire $0\mul_op__rc__rc$6[0:0]$8105 - attribute \src "libresoc.v:157227.7-157227.32" + attribute \src "libresoc.v:157023.7-157023.32" wire $0\mul_op__rc__rc$6[0:0]$8209 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__write_cr0$10$next[0:0]$8142 - attribute \src "libresoc.v:157615.3-157616.59" + attribute \src "libresoc.v:157411.3-157412.59" wire $0\mul_op__write_cr0$10[0:0]$8113 - attribute \src "libresoc.v:157236.7-157236.36" + attribute \src "libresoc.v:157032.7-157032.36" wire $0\mul_op__write_cr0$10[0:0]$8211 - attribute \src "libresoc.v:157731.3-157743.6" + attribute \src "libresoc.v:157527.3-157539.6" wire width 2 $0\muxid$1$next[1:0]$8128 - attribute \src "libresoc.v:157623.3-157624.33" + attribute \src "libresoc.v:157419.3-157420.33" wire width 2 $0\muxid$1[1:0]$8121 - attribute \src "libresoc.v:157245.13-157245.29" + attribute \src "libresoc.v:157041.13-157041.29" wire width 2 $0\muxid$1[1:0]$8213 - attribute \src "libresoc.v:157780.3-157798.6" + attribute \src "libresoc.v:157576.3-157594.6" wire width 64 $0\o$14$next[63:0]$8163 - attribute \src "libresoc.v:157595.3-157596.27" + attribute \src "libresoc.v:157391.3-157392.27" wire width 64 $0\o$14[63:0]$8094 - attribute \src "libresoc.v:157266.14-157266.43" + attribute \src "libresoc.v:157062.14-157062.43" wire width 64 $0\o$14[63:0]$8215 - attribute \src "libresoc.v:157780.3-157798.6" + attribute \src "libresoc.v:157576.3-157594.6" wire $0\o_ok$next[0:0]$8162 - attribute \src "libresoc.v:157597.3-157598.25" + attribute \src "libresoc.v:157393.3-157394.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:157713.3-157730.6" + attribute \src "libresoc.v:157509.3-157526.6" wire $0\r_busy$next[0:0]$8124 - attribute \src "libresoc.v:157625.3-157626.29" + attribute \src "libresoc.v:157421.3-157422.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:157818.3-157836.6" + attribute \src "libresoc.v:157614.3-157632.6" wire width 2 $0\xer_ov$next[1:0]$8174 - attribute \src "libresoc.v:157587.3-157588.29" + attribute \src "libresoc.v:157383.3-157384.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:157818.3-157836.6" + attribute \src "libresoc.v:157614.3-157632.6" wire $0\xer_ov_ok$next[0:0]$8175 - attribute \src "libresoc.v:157589.3-157590.35" + attribute \src "libresoc.v:157385.3-157386.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:157837.3-157855.6" + attribute \src "libresoc.v:157633.3-157651.6" wire $0\xer_so$15$next[0:0]$8181 - attribute \src "libresoc.v:157583.3-157584.37" + attribute \src "libresoc.v:157379.3-157380.37" wire $0\xer_so$15[0:0]$8087 - attribute \src "libresoc.v:157568.7-157568.25" + attribute \src "libresoc.v:157364.7-157364.25" wire $0\xer_so$15[0:0]$8221 - attribute \src "libresoc.v:157837.3-157855.6" + attribute \src "libresoc.v:157633.3-157651.6" wire $0\xer_so_ok$next[0:0]$8180 - attribute \src "libresoc.v:157585.3-157586.35" + attribute \src "libresoc.v:157381.3-157382.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:157799.3-157817.6" + attribute \src "libresoc.v:157595.3-157613.6" wire width 4 $1\cr_a$next[3:0]$8170 - attribute \src "libresoc.v:156595.13-156595.24" + attribute \src "libresoc.v:156391.13-156391.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:157799.3-157817.6" + attribute \src "libresoc.v:157595.3-157613.6" wire $1\cr_a_ok$next[0:0]$8171 - attribute \src "libresoc.v:156604.7-156604.21" + attribute \src "libresoc.v:156400.7-156400.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8143 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8144 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__imm_data__ok$5$next[0:0]$8145 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire width 32 $1\mul_op__insn$13$next[31:0]$8146 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire width 7 $1\mul_op__insn_type$2$next[6:0]$8147 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__is_32bit$11$next[0:0]$8148 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__is_signed$12$next[0:0]$8149 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__oe__oe$8$next[0:0]$8150 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__oe__ok$9$next[0:0]$8151 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__rc__ok$7$next[0:0]$8152 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__rc__rc$6$next[0:0]$8153 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__write_cr0$10$next[0:0]$8154 - attribute \src "libresoc.v:157731.3-157743.6" + attribute \src "libresoc.v:157527.3-157539.6" wire width 2 $1\muxid$1$next[1:0]$8129 - attribute \src "libresoc.v:157780.3-157798.6" + attribute \src "libresoc.v:157576.3-157594.6" wire width 64 $1\o$14$next[63:0]$8165 - attribute \src "libresoc.v:157780.3-157798.6" + attribute \src "libresoc.v:157576.3-157594.6" wire $1\o_ok$next[0:0]$8164 - attribute \src "libresoc.v:157273.7-157273.18" + attribute \src "libresoc.v:157069.7-157069.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:157713.3-157730.6" + attribute \src "libresoc.v:157509.3-157526.6" wire $1\r_busy$next[0:0]$8125 - attribute \src "libresoc.v:157545.7-157545.20" + attribute \src "libresoc.v:157341.7-157341.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:157818.3-157836.6" + attribute \src "libresoc.v:157614.3-157632.6" wire width 2 $1\xer_ov$next[1:0]$8176 - attribute \src "libresoc.v:157550.13-157550.26" + attribute \src "libresoc.v:157346.13-157346.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:157818.3-157836.6" + attribute \src "libresoc.v:157614.3-157632.6" wire $1\xer_ov_ok$next[0:0]$8177 - attribute \src "libresoc.v:157557.7-157557.23" + attribute \src "libresoc.v:157353.7-157353.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:157837.3-157855.6" + attribute \src "libresoc.v:157633.3-157651.6" wire $1\xer_so$15$next[0:0]$8183 - attribute \src "libresoc.v:157837.3-157855.6" + attribute \src "libresoc.v:157633.3-157651.6" wire $1\xer_so_ok$next[0:0]$8182 - attribute \src "libresoc.v:157575.7-157575.23" + attribute \src "libresoc.v:157371.7-157371.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:157799.3-157817.6" + attribute \src "libresoc.v:157595.3-157613.6" wire $2\cr_a_ok$next[0:0]$8172 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8155 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $2\mul_op__imm_data__ok$5$next[0:0]$8156 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $2\mul_op__oe__oe$8$next[0:0]$8157 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $2\mul_op__oe__ok$9$next[0:0]$8158 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $2\mul_op__rc__ok$7$next[0:0]$8159 - attribute \src "libresoc.v:157744.3-157779.6" + attribute \src "libresoc.v:157540.3-157575.6" wire $2\mul_op__rc__rc$6$next[0:0]$8160 - attribute \src "libresoc.v:157780.3-157798.6" + attribute \src "libresoc.v:157576.3-157594.6" wire $2\o_ok$next[0:0]$8166 - attribute \src "libresoc.v:157713.3-157730.6" + attribute \src "libresoc.v:157509.3-157526.6" wire $2\r_busy$next[0:0]$8126 - attribute \src "libresoc.v:157818.3-157836.6" + attribute \src "libresoc.v:157614.3-157632.6" wire $2\xer_ov_ok$next[0:0]$8178 - attribute \src "libresoc.v:157837.3-157855.6" + attribute \src "libresoc.v:157633.3-157651.6" wire $2\xer_so_ok$next[0:0]$8184 - attribute \src "libresoc.v:157582.18-157582.118" - wire $and$libresoc.v:157582$8085_Y + attribute \src "libresoc.v:157378.18-157378.118" + wire $and$libresoc.v:157378$8085_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 44 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 38 \cr_a @@ -291154,7 +290988,7 @@ module \mul_pipe3 wire \cr_a_ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next - attribute \src "libresoc.v:156586.7-156586.15" + attribute \src "libresoc.v:156382.7-156382.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -292107,7 +291941,7 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:157582$8085 + cell $and $and$libresoc.v:157378$8085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -292115,10 +291949,10 @@ module \mul_pipe3 parameter \Y_WIDTH 1 connect \A \p_valid_i$55 connect \B \p_ready_o - connect \Y $and$libresoc.v:157582$8085_Y + connect \Y $and$libresoc.v:157378$8085_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:157627.8-157663.4" + attribute \src "libresoc.v:157423.8-157459.4" cell \mul3 \mul3 connect \mul_op__fn_unit \mul3_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 @@ -292157,13 +291991,13 @@ module \mul_pipe3 connect \xer_so_ok \mul3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:157664.10-157667.4" + attribute \src "libresoc.v:157460.10-157463.4" cell \n$99 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:157668.16-157708.4" + attribute \src "libresoc.v:157464.16-157504.4" cell \output$100 \output connect \cr_a \output_cr_a connect \cr_a$16 \output_cr_a$46 @@ -292206,358 +292040,358 @@ module \mul_pipe3 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:157709.10-157712.4" + attribute \src "libresoc.v:157505.10-157508.4" cell \p$98 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:156586.7-156586.20" - process $proc$libresoc.v:156586$8185 + attribute \src "libresoc.v:156382.7-156382.20" + process $proc$libresoc.v:156382$8185 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156595.13-156595.24" - process $proc$libresoc.v:156595$8186 + attribute \src "libresoc.v:156391.13-156391.24" + process $proc$libresoc.v:156391$8186 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:156604.7-156604.21" - process $proc$libresoc.v:156604$8187 + attribute \src "libresoc.v:156400.7-156400.21" + process $proc$libresoc.v:156400$8187 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:156897.14-156897.44" - process $proc$libresoc.v:156897$8188 + attribute \src "libresoc.v:156693.14-156693.44" + process $proc$libresoc.v:156693$8188 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$8189 14'00000000000000 sync always sync init update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8189 end - attribute \src "libresoc.v:156921.14-156921.63" - process $proc$libresoc.v:156921$8190 + attribute \src "libresoc.v:156717.14-156717.63" + process $proc$libresoc.v:156717$8190 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$8191 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8191 end - attribute \src "libresoc.v:156930.7-156930.38" - process $proc$libresoc.v:156930$8192 + attribute \src "libresoc.v:156726.7-156726.38" + process $proc$libresoc.v:156726$8192 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$8193 1'0 sync always sync init update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8193 end - attribute \src "libresoc.v:156939.14-156939.39" - process $proc$libresoc.v:156939$8194 + attribute \src "libresoc.v:156735.14-156735.39" + process $proc$libresoc.v:156735$8194 assign { } { } assign $0\mul_op__insn$13[31:0]$8195 0 sync always sync init update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8195 end - attribute \src "libresoc.v:157098.13-157098.42" - process $proc$libresoc.v:157098$8196 + attribute \src "libresoc.v:156894.13-156894.42" + process $proc$libresoc.v:156894$8196 assign { } { } assign $0\mul_op__insn_type$2[6:0]$8197 7'0000000 sync always sync init update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8197 end - attribute \src "libresoc.v:157182.7-157182.35" - process $proc$libresoc.v:157182$8198 + attribute \src "libresoc.v:156978.7-156978.35" + process $proc$libresoc.v:156978$8198 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$8199 1'0 sync always sync init update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8199 end - attribute \src "libresoc.v:157191.7-157191.36" - process $proc$libresoc.v:157191$8200 + attribute \src "libresoc.v:156987.7-156987.36" + process $proc$libresoc.v:156987$8200 assign { } { } assign $0\mul_op__is_signed$12[0:0]$8201 1'0 sync always sync init update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8201 end - attribute \src "libresoc.v:157202.7-157202.32" - process $proc$libresoc.v:157202$8202 + attribute \src "libresoc.v:156998.7-156998.32" + process $proc$libresoc.v:156998$8202 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$8203 1'0 sync always sync init update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8203 end - attribute \src "libresoc.v:157211.7-157211.32" - process $proc$libresoc.v:157211$8204 + attribute \src "libresoc.v:157007.7-157007.32" + process $proc$libresoc.v:157007$8204 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$8205 1'0 sync always sync init update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8205 end - attribute \src "libresoc.v:157220.7-157220.32" - process $proc$libresoc.v:157220$8206 + attribute \src "libresoc.v:157016.7-157016.32" + process $proc$libresoc.v:157016$8206 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$8207 1'0 sync always sync init update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8207 end - attribute \src "libresoc.v:157227.7-157227.32" - process $proc$libresoc.v:157227$8208 + attribute \src "libresoc.v:157023.7-157023.32" + process $proc$libresoc.v:157023$8208 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$8209 1'0 sync always sync init update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8209 end - attribute \src "libresoc.v:157236.7-157236.36" - process $proc$libresoc.v:157236$8210 + attribute \src "libresoc.v:157032.7-157032.36" + process $proc$libresoc.v:157032$8210 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$8211 1'0 sync always sync init update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8211 end - attribute \src "libresoc.v:157245.13-157245.29" - process $proc$libresoc.v:157245$8212 + attribute \src "libresoc.v:157041.13-157041.29" + process $proc$libresoc.v:157041$8212 assign { } { } assign $0\muxid$1[1:0]$8213 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8213 end - attribute \src "libresoc.v:157266.14-157266.43" - process $proc$libresoc.v:157266$8214 + attribute \src "libresoc.v:157062.14-157062.43" + process $proc$libresoc.v:157062$8214 assign { } { } assign $0\o$14[63:0]$8215 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$14 $0\o$14[63:0]$8215 end - attribute \src "libresoc.v:157273.7-157273.18" - process $proc$libresoc.v:157273$8216 + attribute \src "libresoc.v:157069.7-157069.18" + process $proc$libresoc.v:157069$8216 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:157545.7-157545.20" - process $proc$libresoc.v:157545$8217 + attribute \src "libresoc.v:157341.7-157341.20" + process $proc$libresoc.v:157341$8217 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:157550.13-157550.26" - process $proc$libresoc.v:157550$8218 + attribute \src "libresoc.v:157346.13-157346.26" + process $proc$libresoc.v:157346$8218 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:157557.7-157557.23" - process $proc$libresoc.v:157557$8219 + attribute \src "libresoc.v:157353.7-157353.23" + process $proc$libresoc.v:157353$8219 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:157568.7-157568.25" - process $proc$libresoc.v:157568$8220 + attribute \src "libresoc.v:157364.7-157364.25" + process $proc$libresoc.v:157364$8220 assign { } { } assign $0\xer_so$15[0:0]$8221 1'0 sync always sync init update \xer_so$15 $0\xer_so$15[0:0]$8221 end - attribute \src "libresoc.v:157575.7-157575.23" - process $proc$libresoc.v:157575$8222 + attribute \src "libresoc.v:157371.7-157371.23" + process $proc$libresoc.v:157371$8222 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:157583.3-157584.37" - process $proc$libresoc.v:157583$8086 + attribute \src "libresoc.v:157379.3-157380.37" + process $proc$libresoc.v:157379$8086 assign { } { } assign $0\xer_so$15[0:0]$8087 \xer_so$15$next sync posedge \coresync_clk update \xer_so$15 $0\xer_so$15[0:0]$8087 end - attribute \src "libresoc.v:157585.3-157586.35" - process $proc$libresoc.v:157585$8088 + attribute \src "libresoc.v:157381.3-157382.35" + process $proc$libresoc.v:157381$8088 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:157587.3-157588.29" - process $proc$libresoc.v:157587$8089 + attribute \src "libresoc.v:157383.3-157384.29" + process $proc$libresoc.v:157383$8089 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:157589.3-157590.35" - process $proc$libresoc.v:157589$8090 + attribute \src "libresoc.v:157385.3-157386.35" + process $proc$libresoc.v:157385$8090 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:157591.3-157592.25" - process $proc$libresoc.v:157591$8091 + attribute \src "libresoc.v:157387.3-157388.25" + process $proc$libresoc.v:157387$8091 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:157593.3-157594.31" - process $proc$libresoc.v:157593$8092 + attribute \src "libresoc.v:157389.3-157390.31" + process $proc$libresoc.v:157389$8092 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:157595.3-157596.27" - process $proc$libresoc.v:157595$8093 + attribute \src "libresoc.v:157391.3-157392.27" + process $proc$libresoc.v:157391$8093 assign { } { } assign $0\o$14[63:0]$8094 \o$14$next sync posedge \coresync_clk update \o$14 $0\o$14[63:0]$8094 end - attribute \src "libresoc.v:157597.3-157598.25" - process $proc$libresoc.v:157597$8095 + attribute \src "libresoc.v:157393.3-157394.25" + process $proc$libresoc.v:157393$8095 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:157599.3-157600.57" - process $proc$libresoc.v:157599$8096 + attribute \src "libresoc.v:157395.3-157396.57" + process $proc$libresoc.v:157395$8096 assign { } { } assign $0\mul_op__insn_type$2[6:0]$8097 \mul_op__insn_type$2$next sync posedge \coresync_clk update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8097 end - attribute \src "libresoc.v:157601.3-157602.53" - process $proc$libresoc.v:157601$8098 + attribute \src "libresoc.v:157397.3-157398.53" + process $proc$libresoc.v:157397$8098 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$8099 \mul_op__fn_unit$3$next sync posedge \coresync_clk update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8099 end - attribute \src "libresoc.v:157603.3-157604.67" - process $proc$libresoc.v:157603$8100 + attribute \src "libresoc.v:157399.3-157400.67" + process $proc$libresoc.v:157399$8100 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$8101 \mul_op__imm_data__data$4$next sync posedge \coresync_clk update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8101 end - attribute \src "libresoc.v:157605.3-157606.63" - process $proc$libresoc.v:157605$8102 + attribute \src "libresoc.v:157401.3-157402.63" + process $proc$libresoc.v:157401$8102 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$8103 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8103 end - attribute \src "libresoc.v:157607.3-157608.51" - process $proc$libresoc.v:157607$8104 + attribute \src "libresoc.v:157403.3-157404.51" + process $proc$libresoc.v:157403$8104 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$8105 \mul_op__rc__rc$6$next sync posedge \coresync_clk update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8105 end - attribute \src "libresoc.v:157609.3-157610.51" - process $proc$libresoc.v:157609$8106 + attribute \src "libresoc.v:157405.3-157406.51" + process $proc$libresoc.v:157405$8106 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$8107 \mul_op__rc__ok$7$next sync posedge \coresync_clk update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8107 end - attribute \src "libresoc.v:157611.3-157612.51" - process $proc$libresoc.v:157611$8108 + attribute \src "libresoc.v:157407.3-157408.51" + process $proc$libresoc.v:157407$8108 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$8109 \mul_op__oe__oe$8$next sync posedge \coresync_clk update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8109 end - attribute \src "libresoc.v:157613.3-157614.51" - process $proc$libresoc.v:157613$8110 + attribute \src "libresoc.v:157409.3-157410.51" + process $proc$libresoc.v:157409$8110 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$8111 \mul_op__oe__ok$9$next sync posedge \coresync_clk update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8111 end - attribute \src "libresoc.v:157615.3-157616.59" - process $proc$libresoc.v:157615$8112 + attribute \src "libresoc.v:157411.3-157412.59" + process $proc$libresoc.v:157411$8112 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$8113 \mul_op__write_cr0$10$next sync posedge \coresync_clk update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8113 end - attribute \src "libresoc.v:157617.3-157618.57" - process $proc$libresoc.v:157617$8114 + attribute \src "libresoc.v:157413.3-157414.57" + process $proc$libresoc.v:157413$8114 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$8115 \mul_op__is_32bit$11$next sync posedge \coresync_clk update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8115 end - attribute \src "libresoc.v:157619.3-157620.59" - process $proc$libresoc.v:157619$8116 + attribute \src "libresoc.v:157415.3-157416.59" + process $proc$libresoc.v:157415$8116 assign { } { } assign $0\mul_op__is_signed$12[0:0]$8117 \mul_op__is_signed$12$next sync posedge \coresync_clk update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8117 end - attribute \src "libresoc.v:157621.3-157622.49" - process $proc$libresoc.v:157621$8118 + attribute \src "libresoc.v:157417.3-157418.49" + process $proc$libresoc.v:157417$8118 assign { } { } assign $0\mul_op__insn$13[31:0]$8119 \mul_op__insn$13$next sync posedge \coresync_clk update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8119 end - attribute \src "libresoc.v:157623.3-157624.33" - process $proc$libresoc.v:157623$8120 + attribute \src "libresoc.v:157419.3-157420.33" + process $proc$libresoc.v:157419$8120 assign { } { } assign $0\muxid$1[1:0]$8121 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8121 end - attribute \src "libresoc.v:157625.3-157626.29" - process $proc$libresoc.v:157625$8122 + attribute \src "libresoc.v:157421.3-157422.29" + process $proc$libresoc.v:157421$8122 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:157713.3-157730.6" - process $proc$libresoc.v:157713$8123 + attribute \src "libresoc.v:157509.3-157526.6" + process $proc$libresoc.v:157509$8123 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8124 $2\r_busy$next[0:0]$8126 - attribute \src "libresoc.v:157714.5-157714.29" + attribute \src "libresoc.v:157510.5-157510.29" switch \initial - attribute \src "libresoc.v:157714.9-157714.17" + attribute \src "libresoc.v:157510.9-157510.17" case 1'1 case end @@ -292586,14 +292420,14 @@ module \mul_pipe3 sync always update \r_busy$next $0\r_busy$next[0:0]$8124 end - attribute \src "libresoc.v:157731.3-157743.6" - process $proc$libresoc.v:157731$8127 + attribute \src "libresoc.v:157527.3-157539.6" + process $proc$libresoc.v:157527$8127 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8128 $1\muxid$1$next[1:0]$8129 - attribute \src "libresoc.v:157732.5-157732.29" + attribute \src "libresoc.v:157528.5-157528.29" switch \initial - attribute \src "libresoc.v:157732.9-157732.17" + attribute \src "libresoc.v:157528.9-157528.17" case 1'1 case end @@ -292613,8 +292447,8 @@ module \mul_pipe3 sync always update \muxid$1$next $0\muxid$1$next[1:0]$8128 end - attribute \src "libresoc.v:157744.3-157779.6" - process $proc$libresoc.v:157744$8130 + attribute \src "libresoc.v:157540.3-157575.6" + process $proc$libresoc.v:157540$8130 assign { } { } assign { } { } assign { } { } @@ -292657,9 +292491,9 @@ module \mul_pipe3 assign $0\mul_op__oe__ok$9$next[0:0]$8139 $2\mul_op__oe__ok$9$next[0:0]$8158 assign $0\mul_op__rc__ok$7$next[0:0]$8140 $2\mul_op__rc__ok$7$next[0:0]$8159 assign $0\mul_op__rc__rc$6$next[0:0]$8141 $2\mul_op__rc__rc$6$next[0:0]$8160 - attribute \src "libresoc.v:157745.5-157745.29" + attribute \src "libresoc.v:157541.5-157541.29" switch \initial - attribute \src "libresoc.v:157745.9-157745.17" + attribute \src "libresoc.v:157541.9-157541.17" case 1'1 case end @@ -292747,8 +292581,8 @@ module \mul_pipe3 update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8141 update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8142 end - attribute \src "libresoc.v:157780.3-157798.6" - process $proc$libresoc.v:157780$8161 + attribute \src "libresoc.v:157576.3-157594.6" + process $proc$libresoc.v:157576$8161 assign { } { } assign { } { } assign { } { } @@ -292756,9 +292590,9 @@ module \mul_pipe3 assign { } { } assign $0\o$14$next[63:0]$8163 $1\o$14$next[63:0]$8165 assign $0\o_ok$next[0:0]$8162 $2\o_ok$next[0:0]$8166 - attribute \src "libresoc.v:157781.5-157781.29" + attribute \src "libresoc.v:157577.5-157577.29" switch \initial - attribute \src "libresoc.v:157781.9-157781.17" + attribute \src "libresoc.v:157577.9-157577.17" case 1'1 case end @@ -292791,8 +292625,8 @@ module \mul_pipe3 update \o_ok$next $0\o_ok$next[0:0]$8162 update \o$14$next $0\o$14$next[63:0]$8163 end - attribute \src "libresoc.v:157799.3-157817.6" - process $proc$libresoc.v:157799$8167 + attribute \src "libresoc.v:157595.3-157613.6" + process $proc$libresoc.v:157595$8167 assign { } { } assign { } { } assign { } { } @@ -292800,9 +292634,9 @@ module \mul_pipe3 assign $0\cr_a$next[3:0]$8168 $1\cr_a$next[3:0]$8170 assign { } { } assign $0\cr_a_ok$next[0:0]$8169 $2\cr_a_ok$next[0:0]$8172 - attribute \src "libresoc.v:157800.5-157800.29" + attribute \src "libresoc.v:157596.5-157596.29" switch \initial - attribute \src "libresoc.v:157800.9-157800.17" + attribute \src "libresoc.v:157596.9-157596.17" case 1'1 case end @@ -292835,8 +292669,8 @@ module \mul_pipe3 update \cr_a$next $0\cr_a$next[3:0]$8168 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8169 end - attribute \src "libresoc.v:157818.3-157836.6" - process $proc$libresoc.v:157818$8173 + attribute \src "libresoc.v:157614.3-157632.6" + process $proc$libresoc.v:157614$8173 assign { } { } assign { } { } assign { } { } @@ -292844,9 +292678,9 @@ module \mul_pipe3 assign $0\xer_ov$next[1:0]$8174 $1\xer_ov$next[1:0]$8176 assign { } { } assign $0\xer_ov_ok$next[0:0]$8175 $2\xer_ov_ok$next[0:0]$8178 - attribute \src "libresoc.v:157819.5-157819.29" + attribute \src "libresoc.v:157615.5-157615.29" switch \initial - attribute \src "libresoc.v:157819.9-157819.17" + attribute \src "libresoc.v:157615.9-157615.17" case 1'1 case end @@ -292879,8 +292713,8 @@ module \mul_pipe3 update \xer_ov$next $0\xer_ov$next[1:0]$8174 update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8175 end - attribute \src "libresoc.v:157837.3-157855.6" - process $proc$libresoc.v:157837$8179 + attribute \src "libresoc.v:157633.3-157651.6" + process $proc$libresoc.v:157633$8179 assign { } { } assign { } { } assign { } { } @@ -292888,9 +292722,9 @@ module \mul_pipe3 assign { } { } assign $0\xer_so$15$next[0:0]$8181 $1\xer_so$15$next[0:0]$8183 assign $0\xer_so_ok$next[0:0]$8180 $2\xer_so_ok$next[0:0]$8184 - attribute \src "libresoc.v:157838.5-157838.29" + attribute \src "libresoc.v:157634.5-157634.29" switch \initial - attribute \src "libresoc.v:157838.9-157838.17" + attribute \src "libresoc.v:157634.9-157634.17" case 1'1 case end @@ -292923,7 +292757,7 @@ module \mul_pipe3 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8180 update \xer_so$15$next $0\xer_so$15$next[0:0]$8181 end - connect \$56 $and$libresoc.v:157582$8085_Y + connect \$56 $and$libresoc.v:157378$8085_Y connect \cr_a$51 4'0000 connect \cr_a_ok$52 1'0 connect \p_ready_o \n_i_rdy_data @@ -292950,13 +292784,13 @@ module \mul_pipe3 connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul3_muxid \muxid end -attribute \src "libresoc.v:157885.1-157896.10" +attribute \src "libresoc.v:157681.1-157692.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" attribute \generator "nMigen" module \n - attribute \src "libresoc.v:157894.17-157894.111" - wire $and$libresoc.v:157894$8223_Y + attribute \src "libresoc.v:157690.17-157690.111" + wire $and$libresoc.v:157690$8223_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -292966,7 +292800,7 @@ module \n attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157894$8223 + cell $and $and$libresoc.v:157690$8223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -292974,18 +292808,18 @@ module \n parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157894$8223_Y + connect \Y $and$libresoc.v:157690$8223_Y end - connect \$1 $and$libresoc.v:157894$8223_Y + connect \$1 $and$libresoc.v:157690$8223_Y connect \trigger \$1 end -attribute \src "libresoc.v:157900.1-157911.10" +attribute \src "libresoc.v:157696.1-157707.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" attribute \generator "nMigen" module \n$109 - attribute \src "libresoc.v:157909.17-157909.111" - wire $and$libresoc.v:157909$8224_Y + attribute \src "libresoc.v:157705.17-157705.111" + wire $and$libresoc.v:157705$8224_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -292995,7 +292829,7 @@ module \n$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157909$8224 + cell $and $and$libresoc.v:157705$8224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293003,18 +292837,18 @@ module \n$109 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157909$8224_Y + connect \Y $and$libresoc.v:157705$8224_Y end - connect \$1 $and$libresoc.v:157909$8224_Y + connect \$1 $and$libresoc.v:157705$8224_Y connect \trigger \$1 end -attribute \src "libresoc.v:157915.1-157926.10" +attribute \src "libresoc.v:157711.1-157722.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" attribute \generator "nMigen" module \n$112 - attribute \src "libresoc.v:157924.17-157924.111" - wire $and$libresoc.v:157924$8225_Y + attribute \src "libresoc.v:157720.17-157720.111" + wire $and$libresoc.v:157720$8225_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293024,7 +292858,7 @@ module \n$112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157924$8225 + cell $and $and$libresoc.v:157720$8225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293032,18 +292866,18 @@ module \n$112 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157924$8225_Y + connect \Y $and$libresoc.v:157720$8225_Y end - connect \$1 $and$libresoc.v:157924$8225_Y + connect \$1 $and$libresoc.v:157720$8225_Y connect \trigger \$1 end -attribute \src "libresoc.v:157930.1-157941.10" +attribute \src "libresoc.v:157726.1-157737.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" attribute \generator "nMigen" module \n$117 - attribute \src "libresoc.v:157939.17-157939.111" - wire $and$libresoc.v:157939$8226_Y + attribute \src "libresoc.v:157735.17-157735.111" + wire $and$libresoc.v:157735$8226_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293053,7 +292887,7 @@ module \n$117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157939$8226 + cell $and $and$libresoc.v:157735$8226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293061,18 +292895,18 @@ module \n$117 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157939$8226_Y + connect \Y $and$libresoc.v:157735$8226_Y end - connect \$1 $and$libresoc.v:157939$8226_Y + connect \$1 $and$libresoc.v:157735$8226_Y connect \trigger \$1 end -attribute \src "libresoc.v:157945.1-157956.10" +attribute \src "libresoc.v:157741.1-157752.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" attribute \generator "nMigen" module \n$18 - attribute \src "libresoc.v:157954.17-157954.111" - wire $and$libresoc.v:157954$8227_Y + attribute \src "libresoc.v:157750.17-157750.111" + wire $and$libresoc.v:157750$8227_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293082,7 +292916,7 @@ module \n$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157954$8227 + cell $and $and$libresoc.v:157750$8227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293090,18 +292924,18 @@ module \n$18 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157954$8227_Y + connect \Y $and$libresoc.v:157750$8227_Y end - connect \$1 $and$libresoc.v:157954$8227_Y + connect \$1 $and$libresoc.v:157750$8227_Y connect \trigger \$1 end -attribute \src "libresoc.v:157960.1-157971.10" +attribute \src "libresoc.v:157756.1-157767.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" attribute \generator "nMigen" module \n$2 - attribute \src "libresoc.v:157969.17-157969.111" - wire $and$libresoc.v:157969$8228_Y + attribute \src "libresoc.v:157765.17-157765.111" + wire $and$libresoc.v:157765$8228_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293111,7 +292945,7 @@ module \n$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157969$8228 + cell $and $and$libresoc.v:157765$8228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293119,18 +292953,18 @@ module \n$2 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157969$8228_Y + connect \Y $and$libresoc.v:157765$8228_Y end - connect \$1 $and$libresoc.v:157969$8228_Y + connect \$1 $and$libresoc.v:157765$8228_Y connect \trigger \$1 end -attribute \src "libresoc.v:157975.1-157986.10" +attribute \src "libresoc.v:157771.1-157782.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" attribute \generator "nMigen" module \n$21 - attribute \src "libresoc.v:157984.17-157984.111" - wire $and$libresoc.v:157984$8229_Y + attribute \src "libresoc.v:157780.17-157780.111" + wire $and$libresoc.v:157780$8229_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293140,7 +292974,7 @@ module \n$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157984$8229 + cell $and $and$libresoc.v:157780$8229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293148,18 +292982,18 @@ module \n$21 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157984$8229_Y + connect \Y $and$libresoc.v:157780$8229_Y end - connect \$1 $and$libresoc.v:157984$8229_Y + connect \$1 $and$libresoc.v:157780$8229_Y connect \trigger \$1 end -attribute \src "libresoc.v:157990.1-158001.10" +attribute \src "libresoc.v:157786.1-157797.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" attribute \generator "nMigen" module \n$31 - attribute \src "libresoc.v:157999.17-157999.111" - wire $and$libresoc.v:157999$8230_Y + attribute \src "libresoc.v:157795.17-157795.111" + wire $and$libresoc.v:157795$8230_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293169,7 +293003,7 @@ module \n$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157999$8230 + cell $and $and$libresoc.v:157795$8230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293177,18 +293011,18 @@ module \n$31 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157999$8230_Y + connect \Y $and$libresoc.v:157795$8230_Y end - connect \$1 $and$libresoc.v:157999$8230_Y + connect \$1 $and$libresoc.v:157795$8230_Y connect \trigger \$1 end -attribute \src "libresoc.v:158005.1-158016.10" +attribute \src "libresoc.v:157801.1-157812.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" attribute \generator "nMigen" module \n$34 - attribute \src "libresoc.v:158014.17-158014.111" - wire $and$libresoc.v:158014$8231_Y + attribute \src "libresoc.v:157810.17-157810.111" + wire $and$libresoc.v:157810$8231_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293198,7 +293032,7 @@ module \n$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158014$8231 + cell $and $and$libresoc.v:157810$8231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293206,18 +293040,18 @@ module \n$34 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158014$8231_Y + connect \Y $and$libresoc.v:157810$8231_Y end - connect \$1 $and$libresoc.v:158014$8231_Y + connect \$1 $and$libresoc.v:157810$8231_Y connect \trigger \$1 end -attribute \src "libresoc.v:158020.1-158031.10" +attribute \src "libresoc.v:157816.1-157827.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" attribute \generator "nMigen" module \n$37 - attribute \src "libresoc.v:158029.17-158029.111" - wire $and$libresoc.v:158029$8232_Y + attribute \src "libresoc.v:157825.17-157825.111" + wire $and$libresoc.v:157825$8232_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293227,7 +293061,7 @@ module \n$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158029$8232 + cell $and $and$libresoc.v:157825$8232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293235,18 +293069,18 @@ module \n$37 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158029$8232_Y + connect \Y $and$libresoc.v:157825$8232_Y end - connect \$1 $and$libresoc.v:158029$8232_Y + connect \$1 $and$libresoc.v:157825$8232_Y connect \trigger \$1 end -attribute \src "libresoc.v:158035.1-158046.10" +attribute \src "libresoc.v:157831.1-157842.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" attribute \generator "nMigen" module \n$4 - attribute \src "libresoc.v:158044.17-158044.111" - wire $and$libresoc.v:158044$8233_Y + attribute \src "libresoc.v:157840.17-157840.111" + wire $and$libresoc.v:157840$8233_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293256,7 +293090,7 @@ module \n$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158044$8233 + cell $and $and$libresoc.v:157840$8233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293264,18 +293098,18 @@ module \n$4 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158044$8233_Y + connect \Y $and$libresoc.v:157840$8233_Y end - connect \$1 $and$libresoc.v:158044$8233_Y + connect \$1 $and$libresoc.v:157840$8233_Y connect \trigger \$1 end -attribute \src "libresoc.v:158050.1-158061.10" +attribute \src "libresoc.v:157846.1-157857.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" attribute \generator "nMigen" module \n$47 - attribute \src "libresoc.v:158059.17-158059.111" - wire $and$libresoc.v:158059$8234_Y + attribute \src "libresoc.v:157855.17-157855.111" + wire $and$libresoc.v:157855$8234_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293285,7 +293119,7 @@ module \n$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158059$8234 + cell $and $and$libresoc.v:157855$8234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293293,18 +293127,18 @@ module \n$47 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158059$8234_Y + connect \Y $and$libresoc.v:157855$8234_Y end - connect \$1 $and$libresoc.v:158059$8234_Y + connect \$1 $and$libresoc.v:157855$8234_Y connect \trigger \$1 end -attribute \src "libresoc.v:158065.1-158076.10" +attribute \src "libresoc.v:157861.1-157872.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" attribute \generator "nMigen" module \n$49 - attribute \src "libresoc.v:158074.17-158074.111" - wire $and$libresoc.v:158074$8235_Y + attribute \src "libresoc.v:157870.17-157870.111" + wire $and$libresoc.v:157870$8235_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293314,7 +293148,7 @@ module \n$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158074$8235 + cell $and $and$libresoc.v:157870$8235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293322,18 +293156,18 @@ module \n$49 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158074$8235_Y + connect \Y $and$libresoc.v:157870$8235_Y end - connect \$1 $and$libresoc.v:158074$8235_Y + connect \$1 $and$libresoc.v:157870$8235_Y connect \trigger \$1 end -attribute \src "libresoc.v:158080.1-158091.10" +attribute \src "libresoc.v:157876.1-157887.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" attribute \generator "nMigen" module \n$53 - attribute \src "libresoc.v:158089.17-158089.111" - wire $and$libresoc.v:158089$8236_Y + attribute \src "libresoc.v:157885.17-157885.111" + wire $and$libresoc.v:157885$8236_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293343,7 +293177,7 @@ module \n$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158089$8236 + cell $and $and$libresoc.v:157885$8236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293351,18 +293185,18 @@ module \n$53 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158089$8236_Y + connect \Y $and$libresoc.v:157885$8236_Y end - connect \$1 $and$libresoc.v:158089$8236_Y + connect \$1 $and$libresoc.v:157885$8236_Y connect \trigger \$1 end -attribute \src "libresoc.v:158095.1-158106.10" +attribute \src "libresoc.v:157891.1-157902.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" attribute \generator "nMigen" module \n$6 - attribute \src "libresoc.v:158104.17-158104.111" - wire $and$libresoc.v:158104$8237_Y + attribute \src "libresoc.v:157900.17-157900.111" + wire $and$libresoc.v:157900$8237_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293372,7 +293206,7 @@ module \n$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158104$8237 + cell $and $and$libresoc.v:157900$8237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293380,18 +293214,18 @@ module \n$6 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158104$8237_Y + connect \Y $and$libresoc.v:157900$8237_Y end - connect \$1 $and$libresoc.v:158104$8237_Y + connect \$1 $and$libresoc.v:157900$8237_Y connect \trigger \$1 end -attribute \src "libresoc.v:158110.1-158121.10" +attribute \src "libresoc.v:157906.1-157917.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" attribute \generator "nMigen" module \n$63 - attribute \src "libresoc.v:158119.17-158119.111" - wire $and$libresoc.v:158119$8238_Y + attribute \src "libresoc.v:157915.17-157915.111" + wire $and$libresoc.v:157915$8238_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293401,7 +293235,7 @@ module \n$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158119$8238 + cell $and $and$libresoc.v:157915$8238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293409,18 +293243,18 @@ module \n$63 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158119$8238_Y + connect \Y $and$libresoc.v:157915$8238_Y end - connect \$1 $and$libresoc.v:158119$8238_Y + connect \$1 $and$libresoc.v:157915$8238_Y connect \trigger \$1 end -attribute \src "libresoc.v:158125.1-158136.10" +attribute \src "libresoc.v:157921.1-157932.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" attribute \generator "nMigen" module \n$66 - attribute \src "libresoc.v:158134.17-158134.111" - wire $and$libresoc.v:158134$8239_Y + attribute \src "libresoc.v:157930.17-157930.111" + wire $and$libresoc.v:157930$8239_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293430,7 +293264,7 @@ module \n$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158134$8239 + cell $and $and$libresoc.v:157930$8239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293438,18 +293272,18 @@ module \n$66 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158134$8239_Y + connect \Y $and$libresoc.v:157930$8239_Y end - connect \$1 $and$libresoc.v:158134$8239_Y + connect \$1 $and$libresoc.v:157930$8239_Y connect \trigger \$1 end -attribute \src "libresoc.v:158140.1-158151.10" +attribute \src "libresoc.v:157936.1-157947.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" attribute \generator "nMigen" module \n$75 - attribute \src "libresoc.v:158149.17-158149.111" - wire $and$libresoc.v:158149$8240_Y + attribute \src "libresoc.v:157945.17-157945.111" + wire $and$libresoc.v:157945$8240_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293459,7 +293293,7 @@ module \n$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158149$8240 + cell $and $and$libresoc.v:157945$8240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293467,18 +293301,18 @@ module \n$75 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158149$8240_Y + connect \Y $and$libresoc.v:157945$8240_Y end - connect \$1 $and$libresoc.v:158149$8240_Y + connect \$1 $and$libresoc.v:157945$8240_Y connect \trigger \$1 end -attribute \src "libresoc.v:158155.1-158166.10" +attribute \src "libresoc.v:157951.1-157962.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" attribute \generator "nMigen" module \n$77 - attribute \src "libresoc.v:158164.17-158164.111" - wire $and$libresoc.v:158164$8241_Y + attribute \src "libresoc.v:157960.17-157960.111" + wire $and$libresoc.v:157960$8241_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293488,7 +293322,7 @@ module \n$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158164$8241 + cell $and $and$libresoc.v:157960$8241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293496,18 +293330,18 @@ module \n$77 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158164$8241_Y + connect \Y $and$libresoc.v:157960$8241_Y end - connect \$1 $and$libresoc.v:158164$8241_Y + connect \$1 $and$libresoc.v:157960$8241_Y connect \trigger \$1 end -attribute \src "libresoc.v:158170.1-158181.10" +attribute \src "libresoc.v:157966.1-157977.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" attribute \generator "nMigen" module \n$8 - attribute \src "libresoc.v:158179.17-158179.111" - wire $and$libresoc.v:158179$8242_Y + attribute \src "libresoc.v:157975.17-157975.111" + wire $and$libresoc.v:157975$8242_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293517,7 +293351,7 @@ module \n$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158179$8242 + cell $and $and$libresoc.v:157975$8242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293525,18 +293359,18 @@ module \n$8 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158179$8242_Y + connect \Y $and$libresoc.v:157975$8242_Y end - connect \$1 $and$libresoc.v:158179$8242_Y + connect \$1 $and$libresoc.v:157975$8242_Y connect \trigger \$1 end -attribute \src "libresoc.v:158185.1-158196.10" +attribute \src "libresoc.v:157981.1-157992.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" attribute \generator "nMigen" module \n$80 - attribute \src "libresoc.v:158194.17-158194.111" - wire $and$libresoc.v:158194$8243_Y + attribute \src "libresoc.v:157990.17-157990.111" + wire $and$libresoc.v:157990$8243_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293546,7 +293380,7 @@ module \n$80 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158194$8243 + cell $and $and$libresoc.v:157990$8243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293554,18 +293388,18 @@ module \n$80 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158194$8243_Y + connect \Y $and$libresoc.v:157990$8243_Y end - connect \$1 $and$libresoc.v:158194$8243_Y + connect \$1 $and$libresoc.v:157990$8243_Y connect \trigger \$1 end -attribute \src "libresoc.v:158200.1-158211.10" +attribute \src "libresoc.v:157996.1-158007.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" attribute \generator "nMigen" module \n$82 - attribute \src "libresoc.v:158209.17-158209.111" - wire $and$libresoc.v:158209$8244_Y + attribute \src "libresoc.v:158005.17-158005.111" + wire $and$libresoc.v:158005$8244_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293575,7 +293409,7 @@ module \n$82 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158209$8244 + cell $and $and$libresoc.v:158005$8244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293583,18 +293417,18 @@ module \n$82 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158209$8244_Y + connect \Y $and$libresoc.v:158005$8244_Y end - connect \$1 $and$libresoc.v:158209$8244_Y + connect \$1 $and$libresoc.v:158005$8244_Y connect \trigger \$1 end -attribute \src "libresoc.v:158215.1-158226.10" +attribute \src "libresoc.v:158011.1-158022.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" attribute \generator "nMigen" module \n$92 - attribute \src "libresoc.v:158224.17-158224.111" - wire $and$libresoc.v:158224$8245_Y + attribute \src "libresoc.v:158020.17-158020.111" + wire $and$libresoc.v:158020$8245_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293604,7 +293438,7 @@ module \n$92 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158224$8245 + cell $and $and$libresoc.v:158020$8245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293612,18 +293446,18 @@ module \n$92 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158224$8245_Y + connect \Y $and$libresoc.v:158020$8245_Y end - connect \$1 $and$libresoc.v:158224$8245_Y + connect \$1 $and$libresoc.v:158020$8245_Y connect \trigger \$1 end -attribute \src "libresoc.v:158230.1-158241.10" +attribute \src "libresoc.v:158026.1-158037.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" attribute \generator "nMigen" module \n$94 - attribute \src "libresoc.v:158239.17-158239.111" - wire $and$libresoc.v:158239$8246_Y + attribute \src "libresoc.v:158035.17-158035.111" + wire $and$libresoc.v:158035$8246_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293633,7 +293467,7 @@ module \n$94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158239$8246 + cell $and $and$libresoc.v:158035$8246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293641,18 +293475,18 @@ module \n$94 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158239$8246_Y + connect \Y $and$libresoc.v:158035$8246_Y end - connect \$1 $and$libresoc.v:158239$8246_Y + connect \$1 $and$libresoc.v:158035$8246_Y connect \trigger \$1 end -attribute \src "libresoc.v:158245.1-158256.10" +attribute \src "libresoc.v:158041.1-158052.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" attribute \generator "nMigen" module \n$97 - attribute \src "libresoc.v:158254.17-158254.111" - wire $and$libresoc.v:158254$8247_Y + attribute \src "libresoc.v:158050.17-158050.111" + wire $and$libresoc.v:158050$8247_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293662,7 +293496,7 @@ module \n$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158254$8247 + cell $and $and$libresoc.v:158050$8247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293670,18 +293504,18 @@ module \n$97 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158254$8247_Y + connect \Y $and$libresoc.v:158050$8247_Y end - connect \$1 $and$libresoc.v:158254$8247_Y + connect \$1 $and$libresoc.v:158050$8247_Y connect \trigger \$1 end -attribute \src "libresoc.v:158260.1-158271.10" +attribute \src "libresoc.v:158056.1-158067.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" attribute \generator "nMigen" module \n$99 - attribute \src "libresoc.v:158269.17-158269.111" - wire $and$libresoc.v:158269$8248_Y + attribute \src "libresoc.v:158065.17-158065.111" + wire $and$libresoc.v:158065$8248_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -293691,7 +293525,7 @@ module \n$99 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:158269$8248 + cell $and $and$libresoc.v:158065$8248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293699,42 +293533,42 @@ module \n$99 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158269$8248_Y + connect \Y $and$libresoc.v:158065$8248_Y end - connect \$1 $and$libresoc.v:158269$8248_Y + connect \$1 $and$libresoc.v:158065$8248_Y connect \trigger \$1 end -attribute \src "libresoc.v:158275.1-158333.10" +attribute \src "libresoc.v:158071.1-158129.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" attribute \generator "nMigen" module \opc_l - attribute \src "libresoc.v:158276.7-158276.20" + attribute \src "libresoc.v:158072.7-158072.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158321.3-158329.6" + attribute \src "libresoc.v:158117.3-158125.6" wire $0\q_int$next[0:0]$8259 - attribute \src "libresoc.v:158319.3-158320.27" + attribute \src "libresoc.v:158115.3-158116.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:158321.3-158329.6" + attribute \src "libresoc.v:158117.3-158125.6" wire $1\q_int$next[0:0]$8260 - attribute \src "libresoc.v:158298.7-158298.19" + attribute \src "libresoc.v:158094.7-158094.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:158311.17-158311.96" - wire $and$libresoc.v:158311$8249_Y - attribute \src "libresoc.v:158316.17-158316.96" - wire $and$libresoc.v:158316$8254_Y - attribute \src "libresoc.v:158313.18-158313.93" - wire $not$libresoc.v:158313$8251_Y - attribute \src "libresoc.v:158315.17-158315.92" - wire $not$libresoc.v:158315$8253_Y - attribute \src "libresoc.v:158318.17-158318.92" - wire $not$libresoc.v:158318$8256_Y - attribute \src "libresoc.v:158312.18-158312.98" - wire $or$libresoc.v:158312$8250_Y - attribute \src "libresoc.v:158314.18-158314.99" - wire $or$libresoc.v:158314$8252_Y - attribute \src "libresoc.v:158317.17-158317.97" - wire $or$libresoc.v:158317$8255_Y + attribute \src "libresoc.v:158107.17-158107.96" + wire $and$libresoc.v:158107$8249_Y + attribute \src "libresoc.v:158112.17-158112.96" + wire $and$libresoc.v:158112$8254_Y + attribute \src "libresoc.v:158109.18-158109.93" + wire $not$libresoc.v:158109$8251_Y + attribute \src "libresoc.v:158111.17-158111.92" + wire $not$libresoc.v:158111$8253_Y + attribute \src "libresoc.v:158114.17-158114.92" + wire $not$libresoc.v:158114$8256_Y + attribute \src "libresoc.v:158108.18-158108.98" + wire $or$libresoc.v:158108$8250_Y + attribute \src "libresoc.v:158110.18-158110.99" + wire $or$libresoc.v:158110$8252_Y + attribute \src "libresoc.v:158113.17-158113.97" + wire $or$libresoc.v:158113$8255_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -293751,11 +293585,11 @@ module \opc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:158276.7-158276.15" + attribute \src "libresoc.v:158072.7-158072.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -293772,7 +293606,7 @@ module \opc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:158311$8249 + cell $and $and$libresoc.v:158107$8249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293780,10 +293614,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:158311$8249_Y + connect \Y $and$libresoc.v:158107$8249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:158316$8254 + cell $and $and$libresoc.v:158112$8254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293791,34 +293625,34 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:158316$8254_Y + connect \Y $and$libresoc.v:158112$8254_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:158313$8251 + cell $not $not$libresoc.v:158109$8251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:158313$8251_Y + connect \Y $not$libresoc.v:158109$8251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:158315$8253 + cell $not $not$libresoc.v:158111$8253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158315$8253_Y + connect \Y $not$libresoc.v:158111$8253_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:158318$8256 + cell $not $not$libresoc.v:158114$8256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158318$8256_Y + connect \Y $not$libresoc.v:158114$8256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:158312$8250 + cell $or $or$libresoc.v:158108$8250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293826,10 +293660,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:158312$8250_Y + connect \Y $or$libresoc.v:158108$8250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:158314$8252 + cell $or $or$libresoc.v:158110$8252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293837,10 +293671,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:158314$8252_Y + connect \Y $or$libresoc.v:158110$8252_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:158317$8255 + cell $or $or$libresoc.v:158113$8255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293848,39 +293682,39 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:158317$8255_Y + connect \Y $or$libresoc.v:158113$8255_Y end - attribute \src "libresoc.v:158276.7-158276.20" - process $proc$libresoc.v:158276$8261 + attribute \src "libresoc.v:158072.7-158072.20" + process $proc$libresoc.v:158072$8261 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158298.7-158298.19" - process $proc$libresoc.v:158298$8262 + attribute \src "libresoc.v:158094.7-158094.19" + process $proc$libresoc.v:158094$8262 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:158319.3-158320.27" - process $proc$libresoc.v:158319$8257 + attribute \src "libresoc.v:158115.3-158116.27" + process $proc$libresoc.v:158115$8257 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:158321.3-158329.6" - process $proc$libresoc.v:158321$8258 + attribute \src "libresoc.v:158117.3-158125.6" + process $proc$libresoc.v:158117$8258 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8259 $1\q_int$next[0:0]$8260 - attribute \src "libresoc.v:158322.5-158322.29" + attribute \src "libresoc.v:158118.5-158118.29" switch \initial - attribute \src "libresoc.v:158322.9-158322.17" + attribute \src "libresoc.v:158118.9-158118.17" case 1'1 case end @@ -293896,49 +293730,49 @@ module \opc_l sync always update \q_int$next $0\q_int$next[0:0]$8259 end - connect \$9 $and$libresoc.v:158311$8249_Y - connect \$11 $or$libresoc.v:158312$8250_Y - connect \$13 $not$libresoc.v:158313$8251_Y - connect \$15 $or$libresoc.v:158314$8252_Y - connect \$1 $not$libresoc.v:158315$8253_Y - connect \$3 $and$libresoc.v:158316$8254_Y - connect \$5 $or$libresoc.v:158317$8255_Y - connect \$7 $not$libresoc.v:158318$8256_Y + connect \$9 $and$libresoc.v:158107$8249_Y + connect \$11 $or$libresoc.v:158108$8250_Y + connect \$13 $not$libresoc.v:158109$8251_Y + connect \$15 $or$libresoc.v:158110$8252_Y + connect \$1 $not$libresoc.v:158111$8253_Y + connect \$3 $and$libresoc.v:158112$8254_Y + connect \$5 $or$libresoc.v:158113$8255_Y + connect \$7 $not$libresoc.v:158114$8256_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:158337.1-158395.10" +attribute \src "libresoc.v:158133.1-158191.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l" attribute \generator "nMigen" module \opc_l$102 - attribute \src "libresoc.v:158338.7-158338.20" + attribute \src "libresoc.v:158134.7-158134.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158383.3-158391.6" + attribute \src "libresoc.v:158179.3-158187.6" wire $0\q_int$next[0:0]$8273 - attribute \src "libresoc.v:158381.3-158382.27" + attribute \src "libresoc.v:158177.3-158178.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:158383.3-158391.6" + attribute \src "libresoc.v:158179.3-158187.6" wire $1\q_int$next[0:0]$8274 - attribute \src "libresoc.v:158360.7-158360.19" + attribute \src "libresoc.v:158156.7-158156.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:158373.17-158373.96" - wire $and$libresoc.v:158373$8263_Y - attribute \src "libresoc.v:158378.17-158378.96" - wire $and$libresoc.v:158378$8268_Y - attribute \src "libresoc.v:158375.18-158375.93" - wire $not$libresoc.v:158375$8265_Y - attribute \src "libresoc.v:158377.17-158377.92" - wire $not$libresoc.v:158377$8267_Y - attribute \src "libresoc.v:158380.17-158380.92" - wire $not$libresoc.v:158380$8270_Y - attribute \src "libresoc.v:158374.18-158374.98" - wire $or$libresoc.v:158374$8264_Y - attribute \src "libresoc.v:158376.18-158376.99" - wire $or$libresoc.v:158376$8266_Y - attribute \src "libresoc.v:158379.17-158379.97" - wire $or$libresoc.v:158379$8269_Y + attribute \src "libresoc.v:158169.17-158169.96" + wire $and$libresoc.v:158169$8263_Y + attribute \src "libresoc.v:158174.17-158174.96" + wire $and$libresoc.v:158174$8268_Y + attribute \src "libresoc.v:158171.18-158171.93" + wire $not$libresoc.v:158171$8265_Y + attribute \src "libresoc.v:158173.17-158173.92" + wire $not$libresoc.v:158173$8267_Y + attribute \src "libresoc.v:158176.17-158176.92" + wire $not$libresoc.v:158176$8270_Y + attribute \src "libresoc.v:158170.18-158170.98" + wire $or$libresoc.v:158170$8264_Y + attribute \src "libresoc.v:158172.18-158172.99" + wire $or$libresoc.v:158172$8266_Y + attribute \src "libresoc.v:158175.17-158175.97" + wire $or$libresoc.v:158175$8269_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -293955,11 +293789,11 @@ module \opc_l$102 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:158338.7-158338.15" + attribute \src "libresoc.v:158134.7-158134.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -293976,7 +293810,7 @@ module \opc_l$102 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:158373$8263 + cell $and $and$libresoc.v:158169$8263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293984,10 +293818,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:158373$8263_Y + connect \Y $and$libresoc.v:158169$8263_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:158378$8268 + cell $and $and$libresoc.v:158174$8268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293995,34 +293829,34 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:158378$8268_Y + connect \Y $and$libresoc.v:158174$8268_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:158375$8265 + cell $not $not$libresoc.v:158171$8265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:158375$8265_Y + connect \Y $not$libresoc.v:158171$8265_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:158377$8267 + cell $not $not$libresoc.v:158173$8267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158377$8267_Y + connect \Y $not$libresoc.v:158173$8267_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:158380$8270 + cell $not $not$libresoc.v:158176$8270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158380$8270_Y + connect \Y $not$libresoc.v:158176$8270_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:158374$8264 + cell $or $or$libresoc.v:158170$8264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294030,10 +293864,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:158374$8264_Y + connect \Y $or$libresoc.v:158170$8264_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:158376$8266 + cell $or $or$libresoc.v:158172$8266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294041,10 +293875,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:158376$8266_Y + connect \Y $or$libresoc.v:158172$8266_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:158379$8269 + cell $or $or$libresoc.v:158175$8269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294052,39 +293886,39 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:158379$8269_Y + connect \Y $or$libresoc.v:158175$8269_Y end - attribute \src "libresoc.v:158338.7-158338.20" - process $proc$libresoc.v:158338$8275 + attribute \src "libresoc.v:158134.7-158134.20" + process $proc$libresoc.v:158134$8275 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158360.7-158360.19" - process $proc$libresoc.v:158360$8276 + attribute \src "libresoc.v:158156.7-158156.19" + process $proc$libresoc.v:158156$8276 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:158381.3-158382.27" - process $proc$libresoc.v:158381$8271 + attribute \src "libresoc.v:158177.3-158178.27" + process $proc$libresoc.v:158177$8271 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:158383.3-158391.6" - process $proc$libresoc.v:158383$8272 + attribute \src "libresoc.v:158179.3-158187.6" + process $proc$libresoc.v:158179$8272 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8273 $1\q_int$next[0:0]$8274 - attribute \src "libresoc.v:158384.5-158384.29" + attribute \src "libresoc.v:158180.5-158180.29" switch \initial - attribute \src "libresoc.v:158384.9-158384.17" + attribute \src "libresoc.v:158180.9-158180.17" case 1'1 case end @@ -294100,49 +293934,49 @@ module \opc_l$102 sync always update \q_int$next $0\q_int$next[0:0]$8273 end - connect \$9 $and$libresoc.v:158373$8263_Y - connect \$11 $or$libresoc.v:158374$8264_Y - connect \$13 $not$libresoc.v:158375$8265_Y - connect \$15 $or$libresoc.v:158376$8266_Y - connect \$1 $not$libresoc.v:158377$8267_Y - connect \$3 $and$libresoc.v:158378$8268_Y - connect \$5 $or$libresoc.v:158379$8269_Y - connect \$7 $not$libresoc.v:158380$8270_Y + connect \$9 $and$libresoc.v:158169$8263_Y + connect \$11 $or$libresoc.v:158170$8264_Y + connect \$13 $not$libresoc.v:158171$8265_Y + connect \$15 $or$libresoc.v:158172$8266_Y + connect \$1 $not$libresoc.v:158173$8267_Y + connect \$3 $and$libresoc.v:158174$8268_Y + connect \$5 $or$libresoc.v:158175$8269_Y + connect \$7 $not$libresoc.v:158176$8270_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:158399.1-158457.10" +attribute \src "libresoc.v:158195.1-158253.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" attribute \generator "nMigen" module \opc_l$11 - attribute \src "libresoc.v:158400.7-158400.20" + attribute \src "libresoc.v:158196.7-158196.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158445.3-158453.6" + attribute \src "libresoc.v:158241.3-158249.6" wire $0\q_int$next[0:0]$8287 - attribute \src "libresoc.v:158443.3-158444.27" + attribute \src "libresoc.v:158239.3-158240.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:158445.3-158453.6" + attribute \src "libresoc.v:158241.3-158249.6" wire $1\q_int$next[0:0]$8288 - attribute \src "libresoc.v:158422.7-158422.19" + attribute \src "libresoc.v:158218.7-158218.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:158435.17-158435.96" - wire $and$libresoc.v:158435$8277_Y - attribute \src "libresoc.v:158440.17-158440.96" - wire $and$libresoc.v:158440$8282_Y - attribute \src "libresoc.v:158437.18-158437.93" - wire $not$libresoc.v:158437$8279_Y - attribute \src "libresoc.v:158439.17-158439.92" - wire $not$libresoc.v:158439$8281_Y - attribute \src "libresoc.v:158442.17-158442.92" - wire $not$libresoc.v:158442$8284_Y - attribute \src "libresoc.v:158436.18-158436.98" - wire $or$libresoc.v:158436$8278_Y - attribute \src "libresoc.v:158438.18-158438.99" - wire $or$libresoc.v:158438$8280_Y - attribute \src "libresoc.v:158441.17-158441.97" - wire $or$libresoc.v:158441$8283_Y + attribute \src "libresoc.v:158231.17-158231.96" + wire $and$libresoc.v:158231$8277_Y + attribute \src "libresoc.v:158236.17-158236.96" + wire $and$libresoc.v:158236$8282_Y + attribute \src "libresoc.v:158233.18-158233.93" + wire $not$libresoc.v:158233$8279_Y + attribute \src "libresoc.v:158235.17-158235.92" + wire $not$libresoc.v:158235$8281_Y + attribute \src "libresoc.v:158238.17-158238.92" + wire $not$libresoc.v:158238$8284_Y + attribute \src "libresoc.v:158232.18-158232.98" + wire $or$libresoc.v:158232$8278_Y + attribute \src "libresoc.v:158234.18-158234.99" + wire $or$libresoc.v:158234$8280_Y + attribute \src "libresoc.v:158237.17-158237.97" + wire $or$libresoc.v:158237$8283_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -294159,11 +293993,11 @@ module \opc_l$11 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:158400.7-158400.15" + attribute \src "libresoc.v:158196.7-158196.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -294180,7 +294014,7 @@ module \opc_l$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:158435$8277 + cell $and $and$libresoc.v:158231$8277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294188,10 +294022,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:158435$8277_Y + connect \Y $and$libresoc.v:158231$8277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:158440$8282 + cell $and $and$libresoc.v:158236$8282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294199,34 +294033,34 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:158440$8282_Y + connect \Y $and$libresoc.v:158236$8282_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:158437$8279 + cell $not $not$libresoc.v:158233$8279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:158437$8279_Y + connect \Y $not$libresoc.v:158233$8279_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:158439$8281 + cell $not $not$libresoc.v:158235$8281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158439$8281_Y + connect \Y $not$libresoc.v:158235$8281_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:158442$8284 + cell $not $not$libresoc.v:158238$8284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158442$8284_Y + connect \Y $not$libresoc.v:158238$8284_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:158436$8278 + cell $or $or$libresoc.v:158232$8278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294234,10 +294068,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:158436$8278_Y + connect \Y $or$libresoc.v:158232$8278_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:158438$8280 + cell $or $or$libresoc.v:158234$8280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294245,10 +294079,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:158438$8280_Y + connect \Y $or$libresoc.v:158234$8280_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:158441$8283 + cell $or $or$libresoc.v:158237$8283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294256,39 +294090,39 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:158441$8283_Y + connect \Y $or$libresoc.v:158237$8283_Y end - attribute \src "libresoc.v:158400.7-158400.20" - process $proc$libresoc.v:158400$8289 + attribute \src "libresoc.v:158196.7-158196.20" + process $proc$libresoc.v:158196$8289 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158422.7-158422.19" - process $proc$libresoc.v:158422$8290 + attribute \src "libresoc.v:158218.7-158218.19" + process $proc$libresoc.v:158218$8290 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:158443.3-158444.27" - process $proc$libresoc.v:158443$8285 + attribute \src "libresoc.v:158239.3-158240.27" + process $proc$libresoc.v:158239$8285 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:158445.3-158453.6" - process $proc$libresoc.v:158445$8286 + attribute \src "libresoc.v:158241.3-158249.6" + process $proc$libresoc.v:158241$8286 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8287 $1\q_int$next[0:0]$8288 - attribute \src "libresoc.v:158446.5-158446.29" + attribute \src "libresoc.v:158242.5-158242.29" switch \initial - attribute \src "libresoc.v:158446.9-158446.17" + attribute \src "libresoc.v:158242.9-158242.17" case 1'1 case end @@ -294304,49 +294138,49 @@ module \opc_l$11 sync always update \q_int$next $0\q_int$next[0:0]$8287 end - connect \$9 $and$libresoc.v:158435$8277_Y - connect \$11 $or$libresoc.v:158436$8278_Y - connect \$13 $not$libresoc.v:158437$8279_Y - connect \$15 $or$libresoc.v:158438$8280_Y - connect \$1 $not$libresoc.v:158439$8281_Y - connect \$3 $and$libresoc.v:158440$8282_Y - connect \$5 $or$libresoc.v:158441$8283_Y - connect \$7 $not$libresoc.v:158442$8284_Y + connect \$9 $and$libresoc.v:158231$8277_Y + connect \$11 $or$libresoc.v:158232$8278_Y + connect \$13 $not$libresoc.v:158233$8279_Y + connect \$15 $or$libresoc.v:158234$8280_Y + connect \$1 $not$libresoc.v:158235$8281_Y + connect \$3 $and$libresoc.v:158236$8282_Y + connect \$5 $or$libresoc.v:158237$8283_Y + connect \$7 $not$libresoc.v:158238$8284_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:158461.1-158519.10" +attribute \src "libresoc.v:158257.1-158315.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" attribute \generator "nMigen" module \opc_l$120 - attribute \src "libresoc.v:158462.7-158462.20" + attribute \src "libresoc.v:158258.7-158258.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158507.3-158515.6" + attribute \src "libresoc.v:158303.3-158311.6" wire $0\q_int$next[0:0]$8301 - attribute \src "libresoc.v:158505.3-158506.27" + attribute \src "libresoc.v:158301.3-158302.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:158507.3-158515.6" + attribute \src "libresoc.v:158303.3-158311.6" wire $1\q_int$next[0:0]$8302 - attribute \src "libresoc.v:158484.7-158484.19" + attribute \src "libresoc.v:158280.7-158280.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:158497.17-158497.96" - wire $and$libresoc.v:158497$8291_Y - attribute \src "libresoc.v:158502.17-158502.96" - wire $and$libresoc.v:158502$8296_Y - attribute \src "libresoc.v:158499.18-158499.93" - wire $not$libresoc.v:158499$8293_Y - attribute \src "libresoc.v:158501.17-158501.92" - wire $not$libresoc.v:158501$8295_Y - attribute \src "libresoc.v:158504.17-158504.92" - wire $not$libresoc.v:158504$8298_Y - attribute \src "libresoc.v:158498.18-158498.98" - wire $or$libresoc.v:158498$8292_Y - attribute \src "libresoc.v:158500.18-158500.99" - wire $or$libresoc.v:158500$8294_Y - attribute \src "libresoc.v:158503.17-158503.97" - wire $or$libresoc.v:158503$8297_Y + attribute \src "libresoc.v:158293.17-158293.96" + wire $and$libresoc.v:158293$8291_Y + attribute \src "libresoc.v:158298.17-158298.96" + wire $and$libresoc.v:158298$8296_Y + attribute \src "libresoc.v:158295.18-158295.93" + wire $not$libresoc.v:158295$8293_Y + attribute \src "libresoc.v:158297.17-158297.92" + wire $not$libresoc.v:158297$8295_Y + attribute \src "libresoc.v:158300.17-158300.92" + wire $not$libresoc.v:158300$8298_Y + attribute \src "libresoc.v:158294.18-158294.98" + wire $or$libresoc.v:158294$8292_Y + attribute \src "libresoc.v:158296.18-158296.99" + wire $or$libresoc.v:158296$8294_Y + attribute \src "libresoc.v:158299.17-158299.97" + wire $or$libresoc.v:158299$8297_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -294363,11 +294197,11 @@ module \opc_l$120 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:158462.7-158462.15" + attribute \src "libresoc.v:158258.7-158258.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -294384,7 +294218,7 @@ module \opc_l$120 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:158497$8291 + cell $and $and$libresoc.v:158293$8291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294392,10 +294226,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:158497$8291_Y + connect \Y $and$libresoc.v:158293$8291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:158502$8296 + cell $and $and$libresoc.v:158298$8296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294403,34 +294237,34 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:158502$8296_Y + connect \Y $and$libresoc.v:158298$8296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:158499$8293 + cell $not $not$libresoc.v:158295$8293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:158499$8293_Y + connect \Y $not$libresoc.v:158295$8293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:158501$8295 + cell $not $not$libresoc.v:158297$8295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158501$8295_Y + connect \Y $not$libresoc.v:158297$8295_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:158504$8298 + cell $not $not$libresoc.v:158300$8298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158504$8298_Y + connect \Y $not$libresoc.v:158300$8298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:158498$8292 + cell $or $or$libresoc.v:158294$8292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294438,10 +294272,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:158498$8292_Y + connect \Y $or$libresoc.v:158294$8292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:158500$8294 + cell $or $or$libresoc.v:158296$8294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294449,10 +294283,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:158500$8294_Y + connect \Y $or$libresoc.v:158296$8294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:158503$8297 + cell $or $or$libresoc.v:158299$8297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294460,39 +294294,39 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:158503$8297_Y + connect \Y $or$libresoc.v:158299$8297_Y end - attribute \src "libresoc.v:158462.7-158462.20" - process $proc$libresoc.v:158462$8303 + attribute \src "libresoc.v:158258.7-158258.20" + process $proc$libresoc.v:158258$8303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158484.7-158484.19" - process $proc$libresoc.v:158484$8304 + attribute \src "libresoc.v:158280.7-158280.19" + process $proc$libresoc.v:158280$8304 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:158505.3-158506.27" - process $proc$libresoc.v:158505$8299 + attribute \src "libresoc.v:158301.3-158302.27" + process $proc$libresoc.v:158301$8299 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:158507.3-158515.6" - process $proc$libresoc.v:158507$8300 + attribute \src "libresoc.v:158303.3-158311.6" + process $proc$libresoc.v:158303$8300 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8301 $1\q_int$next[0:0]$8302 - attribute \src "libresoc.v:158508.5-158508.29" + attribute \src "libresoc.v:158304.5-158304.29" switch \initial - attribute \src "libresoc.v:158508.9-158508.17" + attribute \src "libresoc.v:158304.9-158304.17" case 1'1 case end @@ -294508,49 +294342,49 @@ module \opc_l$120 sync always update \q_int$next $0\q_int$next[0:0]$8301 end - connect \$9 $and$libresoc.v:158497$8291_Y - connect \$11 $or$libresoc.v:158498$8292_Y - connect \$13 $not$libresoc.v:158499$8293_Y - connect \$15 $or$libresoc.v:158500$8294_Y - connect \$1 $not$libresoc.v:158501$8295_Y - connect \$3 $and$libresoc.v:158502$8296_Y - connect \$5 $or$libresoc.v:158503$8297_Y - connect \$7 $not$libresoc.v:158504$8298_Y + connect \$9 $and$libresoc.v:158293$8291_Y + connect \$11 $or$libresoc.v:158294$8292_Y + connect \$13 $not$libresoc.v:158295$8293_Y + connect \$15 $or$libresoc.v:158296$8294_Y + connect \$1 $not$libresoc.v:158297$8295_Y + connect \$3 $and$libresoc.v:158298$8296_Y + connect \$5 $or$libresoc.v:158299$8297_Y + connect \$7 $not$libresoc.v:158300$8298_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:158523.1-158581.10" +attribute \src "libresoc.v:158319.1-158377.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" attribute \generator "nMigen" module \opc_l$126 - attribute \src "libresoc.v:158524.7-158524.20" + attribute \src "libresoc.v:158320.7-158320.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158569.3-158577.6" + attribute \src "libresoc.v:158365.3-158373.6" wire $0\q_int$next[0:0]$8315 - attribute \src "libresoc.v:158567.3-158568.27" + attribute \src "libresoc.v:158363.3-158364.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:158569.3-158577.6" + attribute \src "libresoc.v:158365.3-158373.6" wire $1\q_int$next[0:0]$8316 - attribute \src "libresoc.v:158546.7-158546.19" + attribute \src "libresoc.v:158342.7-158342.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:158559.17-158559.96" - wire $and$libresoc.v:158559$8305_Y - attribute \src "libresoc.v:158564.17-158564.96" - wire $and$libresoc.v:158564$8310_Y - attribute \src "libresoc.v:158561.18-158561.93" - wire $not$libresoc.v:158561$8307_Y - attribute \src "libresoc.v:158563.17-158563.92" - wire $not$libresoc.v:158563$8309_Y - attribute \src "libresoc.v:158566.17-158566.92" - wire $not$libresoc.v:158566$8312_Y - attribute \src "libresoc.v:158560.18-158560.98" - wire $or$libresoc.v:158560$8306_Y - attribute \src "libresoc.v:158562.18-158562.99" - wire $or$libresoc.v:158562$8308_Y - attribute \src "libresoc.v:158565.17-158565.97" - wire $or$libresoc.v:158565$8311_Y + attribute \src "libresoc.v:158355.17-158355.96" + wire $and$libresoc.v:158355$8305_Y + attribute \src "libresoc.v:158360.17-158360.96" + wire $and$libresoc.v:158360$8310_Y + attribute \src "libresoc.v:158357.18-158357.93" + wire $not$libresoc.v:158357$8307_Y + attribute \src "libresoc.v:158359.17-158359.92" + wire $not$libresoc.v:158359$8309_Y + attribute \src "libresoc.v:158362.17-158362.92" + wire $not$libresoc.v:158362$8312_Y + attribute \src "libresoc.v:158356.18-158356.98" + wire $or$libresoc.v:158356$8306_Y + attribute \src "libresoc.v:158358.18-158358.99" + wire $or$libresoc.v:158358$8308_Y + attribute \src "libresoc.v:158361.17-158361.97" + wire $or$libresoc.v:158361$8311_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -294567,11 +294401,11 @@ module \opc_l$126 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:158524.7-158524.15" + attribute \src "libresoc.v:158320.7-158320.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -294588,7 +294422,7 @@ module \opc_l$126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:158559$8305 + cell $and $and$libresoc.v:158355$8305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294596,10 +294430,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:158559$8305_Y + connect \Y $and$libresoc.v:158355$8305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:158564$8310 + cell $and $and$libresoc.v:158360$8310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294607,34 +294441,34 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:158564$8310_Y + connect \Y $and$libresoc.v:158360$8310_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:158561$8307 + cell $not $not$libresoc.v:158357$8307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:158561$8307_Y + connect \Y $not$libresoc.v:158357$8307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:158563$8309 + cell $not $not$libresoc.v:158359$8309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158563$8309_Y + connect \Y $not$libresoc.v:158359$8309_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:158566$8312 + cell $not $not$libresoc.v:158362$8312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158566$8312_Y + connect \Y $not$libresoc.v:158362$8312_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:158560$8306 + cell $or $or$libresoc.v:158356$8306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294642,10 +294476,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:158560$8306_Y + connect \Y $or$libresoc.v:158356$8306_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:158562$8308 + cell $or $or$libresoc.v:158358$8308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294653,10 +294487,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:158562$8308_Y + connect \Y $or$libresoc.v:158358$8308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:158565$8311 + cell $or $or$libresoc.v:158361$8311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294664,39 +294498,39 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:158565$8311_Y + connect \Y $or$libresoc.v:158361$8311_Y end - attribute \src "libresoc.v:158524.7-158524.20" - process $proc$libresoc.v:158524$8317 + attribute \src "libresoc.v:158320.7-158320.20" + process $proc$libresoc.v:158320$8317 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158546.7-158546.19" - process $proc$libresoc.v:158546$8318 + attribute \src "libresoc.v:158342.7-158342.19" + process $proc$libresoc.v:158342$8318 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:158567.3-158568.27" - process $proc$libresoc.v:158567$8313 + attribute \src "libresoc.v:158363.3-158364.27" + process $proc$libresoc.v:158363$8313 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:158569.3-158577.6" - process $proc$libresoc.v:158569$8314 + attribute \src "libresoc.v:158365.3-158373.6" + process $proc$libresoc.v:158365$8314 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8315 $1\q_int$next[0:0]$8316 - attribute \src "libresoc.v:158570.5-158570.29" + attribute \src "libresoc.v:158366.5-158366.29" switch \initial - attribute \src "libresoc.v:158570.9-158570.17" + attribute \src "libresoc.v:158366.9-158366.17" case 1'1 case end @@ -294712,49 +294546,49 @@ module \opc_l$126 sync always update \q_int$next $0\q_int$next[0:0]$8315 end - connect \$9 $and$libresoc.v:158559$8305_Y - connect \$11 $or$libresoc.v:158560$8306_Y - connect \$13 $not$libresoc.v:158561$8307_Y - connect \$15 $or$libresoc.v:158562$8308_Y - connect \$1 $not$libresoc.v:158563$8309_Y - connect \$3 $and$libresoc.v:158564$8310_Y - connect \$5 $or$libresoc.v:158565$8311_Y - connect \$7 $not$libresoc.v:158566$8312_Y + connect \$9 $and$libresoc.v:158355$8305_Y + connect \$11 $or$libresoc.v:158356$8306_Y + connect \$13 $not$libresoc.v:158357$8307_Y + connect \$15 $or$libresoc.v:158358$8308_Y + connect \$1 $not$libresoc.v:158359$8309_Y + connect \$3 $and$libresoc.v:158360$8310_Y + connect \$5 $or$libresoc.v:158361$8311_Y + connect \$7 $not$libresoc.v:158362$8312_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:158585.1-158643.10" +attribute \src "libresoc.v:158381.1-158439.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" attribute \generator "nMigen" module \opc_l$24 - attribute \src "libresoc.v:158586.7-158586.20" + attribute \src "libresoc.v:158382.7-158382.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158631.3-158639.6" + attribute \src "libresoc.v:158427.3-158435.6" wire $0\q_int$next[0:0]$8329 - attribute \src "libresoc.v:158629.3-158630.27" + attribute \src "libresoc.v:158425.3-158426.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:158631.3-158639.6" + attribute \src "libresoc.v:158427.3-158435.6" wire $1\q_int$next[0:0]$8330 - attribute \src "libresoc.v:158608.7-158608.19" + attribute \src "libresoc.v:158404.7-158404.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:158621.17-158621.96" - wire $and$libresoc.v:158621$8319_Y - attribute \src "libresoc.v:158626.17-158626.96" - wire $and$libresoc.v:158626$8324_Y - attribute \src "libresoc.v:158623.18-158623.93" - wire $not$libresoc.v:158623$8321_Y - attribute \src "libresoc.v:158625.17-158625.92" - wire $not$libresoc.v:158625$8323_Y - attribute \src "libresoc.v:158628.17-158628.92" - wire $not$libresoc.v:158628$8326_Y - attribute \src "libresoc.v:158622.18-158622.98" - wire $or$libresoc.v:158622$8320_Y - attribute \src "libresoc.v:158624.18-158624.99" - wire $or$libresoc.v:158624$8322_Y - attribute \src "libresoc.v:158627.17-158627.97" - wire $or$libresoc.v:158627$8325_Y + attribute \src "libresoc.v:158417.17-158417.96" + wire $and$libresoc.v:158417$8319_Y + attribute \src "libresoc.v:158422.17-158422.96" + wire $and$libresoc.v:158422$8324_Y + attribute \src "libresoc.v:158419.18-158419.93" + wire $not$libresoc.v:158419$8321_Y + attribute \src "libresoc.v:158421.17-158421.92" + wire $not$libresoc.v:158421$8323_Y + attribute \src "libresoc.v:158424.17-158424.92" + wire $not$libresoc.v:158424$8326_Y + attribute \src "libresoc.v:158418.18-158418.98" + wire $or$libresoc.v:158418$8320_Y + attribute \src "libresoc.v:158420.18-158420.99" + wire $or$libresoc.v:158420$8322_Y + attribute \src "libresoc.v:158423.17-158423.97" + wire $or$libresoc.v:158423$8325_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -294771,11 +294605,11 @@ module \opc_l$24 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:158586.7-158586.15" + attribute \src "libresoc.v:158382.7-158382.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -294792,7 +294626,7 @@ module \opc_l$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:158621$8319 + cell $and $and$libresoc.v:158417$8319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294800,10 +294634,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:158621$8319_Y + connect \Y $and$libresoc.v:158417$8319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:158626$8324 + cell $and $and$libresoc.v:158422$8324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294811,34 +294645,34 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:158626$8324_Y + connect \Y $and$libresoc.v:158422$8324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:158623$8321 + cell $not $not$libresoc.v:158419$8321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:158623$8321_Y + connect \Y $not$libresoc.v:158419$8321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:158625$8323 + cell $not $not$libresoc.v:158421$8323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158625$8323_Y + connect \Y $not$libresoc.v:158421$8323_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:158628$8326 + cell $not $not$libresoc.v:158424$8326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158628$8326_Y + connect \Y $not$libresoc.v:158424$8326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:158622$8320 + cell $or $or$libresoc.v:158418$8320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294846,10 +294680,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:158622$8320_Y + connect \Y $or$libresoc.v:158418$8320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:158624$8322 + cell $or $or$libresoc.v:158420$8322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294857,10 +294691,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:158624$8322_Y + connect \Y $or$libresoc.v:158420$8322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:158627$8325 + cell $or $or$libresoc.v:158423$8325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294868,39 +294702,39 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:158627$8325_Y + connect \Y $or$libresoc.v:158423$8325_Y end - attribute \src "libresoc.v:158586.7-158586.20" - process $proc$libresoc.v:158586$8331 + attribute \src "libresoc.v:158382.7-158382.20" + process $proc$libresoc.v:158382$8331 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158608.7-158608.19" - process $proc$libresoc.v:158608$8332 + attribute \src "libresoc.v:158404.7-158404.19" + process $proc$libresoc.v:158404$8332 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:158629.3-158630.27" - process $proc$libresoc.v:158629$8327 + attribute \src "libresoc.v:158425.3-158426.27" + process $proc$libresoc.v:158425$8327 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:158631.3-158639.6" - process $proc$libresoc.v:158631$8328 + attribute \src "libresoc.v:158427.3-158435.6" + process $proc$libresoc.v:158427$8328 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8329 $1\q_int$next[0:0]$8330 - attribute \src "libresoc.v:158632.5-158632.29" + attribute \src "libresoc.v:158428.5-158428.29" switch \initial - attribute \src "libresoc.v:158632.9-158632.17" + attribute \src "libresoc.v:158428.9-158428.17" case 1'1 case end @@ -294916,49 +294750,49 @@ module \opc_l$24 sync always update \q_int$next $0\q_int$next[0:0]$8329 end - connect \$9 $and$libresoc.v:158621$8319_Y - connect \$11 $or$libresoc.v:158622$8320_Y - connect \$13 $not$libresoc.v:158623$8321_Y - connect \$15 $or$libresoc.v:158624$8322_Y - connect \$1 $not$libresoc.v:158625$8323_Y - connect \$3 $and$libresoc.v:158626$8324_Y - connect \$5 $or$libresoc.v:158627$8325_Y - connect \$7 $not$libresoc.v:158628$8326_Y + connect \$9 $and$libresoc.v:158417$8319_Y + connect \$11 $or$libresoc.v:158418$8320_Y + connect \$13 $not$libresoc.v:158419$8321_Y + connect \$15 $or$libresoc.v:158420$8322_Y + connect \$1 $not$libresoc.v:158421$8323_Y + connect \$3 $and$libresoc.v:158422$8324_Y + connect \$5 $or$libresoc.v:158423$8325_Y + connect \$7 $not$libresoc.v:158424$8326_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:158647.1-158705.10" +attribute \src "libresoc.v:158443.1-158501.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" attribute \generator "nMigen" module \opc_l$40 - attribute \src "libresoc.v:158648.7-158648.20" + attribute \src "libresoc.v:158444.7-158444.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158693.3-158701.6" + attribute \src "libresoc.v:158489.3-158497.6" wire $0\q_int$next[0:0]$8343 - attribute \src "libresoc.v:158691.3-158692.27" + attribute \src "libresoc.v:158487.3-158488.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:158693.3-158701.6" + attribute \src "libresoc.v:158489.3-158497.6" wire $1\q_int$next[0:0]$8344 - attribute \src "libresoc.v:158670.7-158670.19" + attribute \src "libresoc.v:158466.7-158466.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:158683.17-158683.96" - wire $and$libresoc.v:158683$8333_Y - attribute \src "libresoc.v:158688.17-158688.96" - wire $and$libresoc.v:158688$8338_Y - attribute \src "libresoc.v:158685.18-158685.93" - wire $not$libresoc.v:158685$8335_Y - attribute \src "libresoc.v:158687.17-158687.92" - wire $not$libresoc.v:158687$8337_Y - attribute \src "libresoc.v:158690.17-158690.92" - wire $not$libresoc.v:158690$8340_Y - attribute \src "libresoc.v:158684.18-158684.98" - wire $or$libresoc.v:158684$8334_Y - attribute \src "libresoc.v:158686.18-158686.99" - wire $or$libresoc.v:158686$8336_Y - attribute \src "libresoc.v:158689.17-158689.97" - wire $or$libresoc.v:158689$8339_Y + attribute \src "libresoc.v:158479.17-158479.96" + wire $and$libresoc.v:158479$8333_Y + attribute \src "libresoc.v:158484.17-158484.96" + wire $and$libresoc.v:158484$8338_Y + attribute \src "libresoc.v:158481.18-158481.93" + wire $not$libresoc.v:158481$8335_Y + attribute \src "libresoc.v:158483.17-158483.92" + wire $not$libresoc.v:158483$8337_Y + attribute \src "libresoc.v:158486.17-158486.92" + wire $not$libresoc.v:158486$8340_Y + attribute \src "libresoc.v:158480.18-158480.98" + wire $or$libresoc.v:158480$8334_Y + attribute \src "libresoc.v:158482.18-158482.99" + wire $or$libresoc.v:158482$8336_Y + attribute \src "libresoc.v:158485.17-158485.97" + wire $or$libresoc.v:158485$8339_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -294975,11 +294809,11 @@ module \opc_l$40 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:158648.7-158648.15" + attribute \src "libresoc.v:158444.7-158444.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -294996,7 +294830,7 @@ module \opc_l$40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:158683$8333 + cell $and $and$libresoc.v:158479$8333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295004,10 +294838,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:158683$8333_Y + connect \Y $and$libresoc.v:158479$8333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:158688$8338 + cell $and $and$libresoc.v:158484$8338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295015,34 +294849,34 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:158688$8338_Y + connect \Y $and$libresoc.v:158484$8338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:158685$8335 + cell $not $not$libresoc.v:158481$8335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:158685$8335_Y + connect \Y $not$libresoc.v:158481$8335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:158687$8337 + cell $not $not$libresoc.v:158483$8337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158687$8337_Y + connect \Y $not$libresoc.v:158483$8337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:158690$8340 + cell $not $not$libresoc.v:158486$8340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158690$8340_Y + connect \Y $not$libresoc.v:158486$8340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:158684$8334 + cell $or $or$libresoc.v:158480$8334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295050,10 +294884,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:158684$8334_Y + connect \Y $or$libresoc.v:158480$8334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:158686$8336 + cell $or $or$libresoc.v:158482$8336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295061,10 +294895,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:158686$8336_Y + connect \Y $or$libresoc.v:158482$8336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:158689$8339 + cell $or $or$libresoc.v:158485$8339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295072,39 +294906,39 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:158689$8339_Y + connect \Y $or$libresoc.v:158485$8339_Y end - attribute \src "libresoc.v:158648.7-158648.20" - process $proc$libresoc.v:158648$8345 + attribute \src "libresoc.v:158444.7-158444.20" + process $proc$libresoc.v:158444$8345 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158670.7-158670.19" - process $proc$libresoc.v:158670$8346 + attribute \src "libresoc.v:158466.7-158466.19" + process $proc$libresoc.v:158466$8346 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:158691.3-158692.27" - process $proc$libresoc.v:158691$8341 + attribute \src "libresoc.v:158487.3-158488.27" + process $proc$libresoc.v:158487$8341 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:158693.3-158701.6" - process $proc$libresoc.v:158693$8342 + attribute \src "libresoc.v:158489.3-158497.6" + process $proc$libresoc.v:158489$8342 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8343 $1\q_int$next[0:0]$8344 - attribute \src "libresoc.v:158694.5-158694.29" + attribute \src "libresoc.v:158490.5-158490.29" switch \initial - attribute \src "libresoc.v:158694.9-158694.17" + attribute \src "libresoc.v:158490.9-158490.17" case 1'1 case end @@ -295120,49 +294954,49 @@ module \opc_l$40 sync always update \q_int$next $0\q_int$next[0:0]$8343 end - connect \$9 $and$libresoc.v:158683$8333_Y - connect \$11 $or$libresoc.v:158684$8334_Y - connect \$13 $not$libresoc.v:158685$8335_Y - connect \$15 $or$libresoc.v:158686$8336_Y - connect \$1 $not$libresoc.v:158687$8337_Y - connect \$3 $and$libresoc.v:158688$8338_Y - connect \$5 $or$libresoc.v:158689$8339_Y - connect \$7 $not$libresoc.v:158690$8340_Y + connect \$9 $and$libresoc.v:158479$8333_Y + connect \$11 $or$libresoc.v:158480$8334_Y + connect \$13 $not$libresoc.v:158481$8335_Y + connect \$15 $or$libresoc.v:158482$8336_Y + connect \$1 $not$libresoc.v:158483$8337_Y + connect \$3 $and$libresoc.v:158484$8338_Y + connect \$5 $or$libresoc.v:158485$8339_Y + connect \$7 $not$libresoc.v:158486$8340_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:158709.1-158767.10" +attribute \src "libresoc.v:158505.1-158563.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" attribute \generator "nMigen" module \opc_l$56 - attribute \src "libresoc.v:158710.7-158710.20" + attribute \src "libresoc.v:158506.7-158506.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158755.3-158763.6" + attribute \src "libresoc.v:158551.3-158559.6" wire $0\q_int$next[0:0]$8357 - attribute \src "libresoc.v:158753.3-158754.27" + attribute \src "libresoc.v:158549.3-158550.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:158755.3-158763.6" + attribute \src "libresoc.v:158551.3-158559.6" wire $1\q_int$next[0:0]$8358 - attribute \src "libresoc.v:158732.7-158732.19" + attribute \src "libresoc.v:158528.7-158528.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:158745.17-158745.96" - wire $and$libresoc.v:158745$8347_Y - attribute \src "libresoc.v:158750.17-158750.96" - wire $and$libresoc.v:158750$8352_Y - attribute \src "libresoc.v:158747.18-158747.93" - wire $not$libresoc.v:158747$8349_Y - attribute \src "libresoc.v:158749.17-158749.92" - wire $not$libresoc.v:158749$8351_Y - attribute \src "libresoc.v:158752.17-158752.92" - wire $not$libresoc.v:158752$8354_Y - attribute \src "libresoc.v:158746.18-158746.98" - wire $or$libresoc.v:158746$8348_Y - attribute \src "libresoc.v:158748.18-158748.99" - wire $or$libresoc.v:158748$8350_Y - attribute \src "libresoc.v:158751.17-158751.97" - wire $or$libresoc.v:158751$8353_Y + attribute \src "libresoc.v:158541.17-158541.96" + wire $and$libresoc.v:158541$8347_Y + attribute \src "libresoc.v:158546.17-158546.96" + wire $and$libresoc.v:158546$8352_Y + attribute \src "libresoc.v:158543.18-158543.93" + wire $not$libresoc.v:158543$8349_Y + attribute \src "libresoc.v:158545.17-158545.92" + wire $not$libresoc.v:158545$8351_Y + attribute \src "libresoc.v:158548.17-158548.92" + wire $not$libresoc.v:158548$8354_Y + attribute \src "libresoc.v:158542.18-158542.98" + wire $or$libresoc.v:158542$8348_Y + attribute \src "libresoc.v:158544.18-158544.99" + wire $or$libresoc.v:158544$8350_Y + attribute \src "libresoc.v:158547.17-158547.97" + wire $or$libresoc.v:158547$8353_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -295179,11 +295013,11 @@ module \opc_l$56 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:158710.7-158710.15" + attribute \src "libresoc.v:158506.7-158506.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -295200,7 +295034,7 @@ module \opc_l$56 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:158745$8347 + cell $and $and$libresoc.v:158541$8347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295208,10 +295042,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:158745$8347_Y + connect \Y $and$libresoc.v:158541$8347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:158750$8352 + cell $and $and$libresoc.v:158546$8352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295219,34 +295053,34 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:158750$8352_Y + connect \Y $and$libresoc.v:158546$8352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:158747$8349 + cell $not $not$libresoc.v:158543$8349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:158747$8349_Y + connect \Y $not$libresoc.v:158543$8349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:158749$8351 + cell $not $not$libresoc.v:158545$8351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158749$8351_Y + connect \Y $not$libresoc.v:158545$8351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:158752$8354 + cell $not $not$libresoc.v:158548$8354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158752$8354_Y + connect \Y $not$libresoc.v:158548$8354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:158746$8348 + cell $or $or$libresoc.v:158542$8348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295254,10 +295088,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:158746$8348_Y + connect \Y $or$libresoc.v:158542$8348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:158748$8350 + cell $or $or$libresoc.v:158544$8350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295265,10 +295099,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:158748$8350_Y + connect \Y $or$libresoc.v:158544$8350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:158751$8353 + cell $or $or$libresoc.v:158547$8353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295276,39 +295110,39 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:158751$8353_Y + connect \Y $or$libresoc.v:158547$8353_Y end - attribute \src "libresoc.v:158710.7-158710.20" - process $proc$libresoc.v:158710$8359 + attribute \src "libresoc.v:158506.7-158506.20" + process $proc$libresoc.v:158506$8359 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158732.7-158732.19" - process $proc$libresoc.v:158732$8360 + attribute \src "libresoc.v:158528.7-158528.19" + process $proc$libresoc.v:158528$8360 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:158753.3-158754.27" - process $proc$libresoc.v:158753$8355 + attribute \src "libresoc.v:158549.3-158550.27" + process $proc$libresoc.v:158549$8355 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:158755.3-158763.6" - process $proc$libresoc.v:158755$8356 + attribute \src "libresoc.v:158551.3-158559.6" + process $proc$libresoc.v:158551$8356 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8357 $1\q_int$next[0:0]$8358 - attribute \src "libresoc.v:158756.5-158756.29" + attribute \src "libresoc.v:158552.5-158552.29" switch \initial - attribute \src "libresoc.v:158756.9-158756.17" + attribute \src "libresoc.v:158552.9-158552.17" case 1'1 case end @@ -295324,49 +295158,49 @@ module \opc_l$56 sync always update \q_int$next $0\q_int$next[0:0]$8357 end - connect \$9 $and$libresoc.v:158745$8347_Y - connect \$11 $or$libresoc.v:158746$8348_Y - connect \$13 $not$libresoc.v:158747$8349_Y - connect \$15 $or$libresoc.v:158748$8350_Y - connect \$1 $not$libresoc.v:158749$8351_Y - connect \$3 $and$libresoc.v:158750$8352_Y - connect \$5 $or$libresoc.v:158751$8353_Y - connect \$7 $not$libresoc.v:158752$8354_Y + connect \$9 $and$libresoc.v:158541$8347_Y + connect \$11 $or$libresoc.v:158542$8348_Y + connect \$13 $not$libresoc.v:158543$8349_Y + connect \$15 $or$libresoc.v:158544$8350_Y + connect \$1 $not$libresoc.v:158545$8351_Y + connect \$3 $and$libresoc.v:158546$8352_Y + connect \$5 $or$libresoc.v:158547$8353_Y + connect \$7 $not$libresoc.v:158548$8354_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:158771.1-158829.10" +attribute \src "libresoc.v:158567.1-158625.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" attribute \generator "nMigen" module \opc_l$68 - attribute \src "libresoc.v:158772.7-158772.20" + attribute \src "libresoc.v:158568.7-158568.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158817.3-158825.6" + attribute \src "libresoc.v:158613.3-158621.6" wire $0\q_int$next[0:0]$8371 - attribute \src "libresoc.v:158815.3-158816.27" + attribute \src "libresoc.v:158611.3-158612.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:158817.3-158825.6" + attribute \src "libresoc.v:158613.3-158621.6" wire $1\q_int$next[0:0]$8372 - attribute \src "libresoc.v:158794.7-158794.19" + attribute \src "libresoc.v:158590.7-158590.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:158807.17-158807.96" - wire $and$libresoc.v:158807$8361_Y - attribute \src "libresoc.v:158812.17-158812.96" - wire $and$libresoc.v:158812$8366_Y - attribute \src "libresoc.v:158809.18-158809.93" - wire $not$libresoc.v:158809$8363_Y - attribute \src "libresoc.v:158811.17-158811.92" - wire $not$libresoc.v:158811$8365_Y - attribute \src "libresoc.v:158814.17-158814.92" - wire $not$libresoc.v:158814$8368_Y - attribute \src "libresoc.v:158808.18-158808.98" - wire $or$libresoc.v:158808$8362_Y - attribute \src "libresoc.v:158810.18-158810.99" - wire $or$libresoc.v:158810$8364_Y - attribute \src "libresoc.v:158813.17-158813.97" - wire $or$libresoc.v:158813$8367_Y + attribute \src "libresoc.v:158603.17-158603.96" + wire $and$libresoc.v:158603$8361_Y + attribute \src "libresoc.v:158608.17-158608.96" + wire $and$libresoc.v:158608$8366_Y + attribute \src "libresoc.v:158605.18-158605.93" + wire $not$libresoc.v:158605$8363_Y + attribute \src "libresoc.v:158607.17-158607.92" + wire $not$libresoc.v:158607$8365_Y + attribute \src "libresoc.v:158610.17-158610.92" + wire $not$libresoc.v:158610$8368_Y + attribute \src "libresoc.v:158604.18-158604.98" + wire $or$libresoc.v:158604$8362_Y + attribute \src "libresoc.v:158606.18-158606.99" + wire $or$libresoc.v:158606$8364_Y + attribute \src "libresoc.v:158609.17-158609.97" + wire $or$libresoc.v:158609$8367_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -295383,11 +295217,11 @@ module \opc_l$68 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:158772.7-158772.15" + attribute \src "libresoc.v:158568.7-158568.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -295404,7 +295238,7 @@ module \opc_l$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:158807$8361 + cell $and $and$libresoc.v:158603$8361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295412,10 +295246,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:158807$8361_Y + connect \Y $and$libresoc.v:158603$8361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:158812$8366 + cell $and $and$libresoc.v:158608$8366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295423,34 +295257,34 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:158812$8366_Y + connect \Y $and$libresoc.v:158608$8366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:158809$8363 + cell $not $not$libresoc.v:158605$8363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:158809$8363_Y + connect \Y $not$libresoc.v:158605$8363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:158811$8365 + cell $not $not$libresoc.v:158607$8365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158811$8365_Y + connect \Y $not$libresoc.v:158607$8365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:158814$8368 + cell $not $not$libresoc.v:158610$8368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158814$8368_Y + connect \Y $not$libresoc.v:158610$8368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:158808$8362 + cell $or $or$libresoc.v:158604$8362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295458,10 +295292,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:158808$8362_Y + connect \Y $or$libresoc.v:158604$8362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:158810$8364 + cell $or $or$libresoc.v:158606$8364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295469,10 +295303,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:158810$8364_Y + connect \Y $or$libresoc.v:158606$8364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:158813$8367 + cell $or $or$libresoc.v:158609$8367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295480,39 +295314,39 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:158813$8367_Y + connect \Y $or$libresoc.v:158609$8367_Y end - attribute \src "libresoc.v:158772.7-158772.20" - process $proc$libresoc.v:158772$8373 + attribute \src "libresoc.v:158568.7-158568.20" + process $proc$libresoc.v:158568$8373 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158794.7-158794.19" - process $proc$libresoc.v:158794$8374 + attribute \src "libresoc.v:158590.7-158590.19" + process $proc$libresoc.v:158590$8374 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:158815.3-158816.27" - process $proc$libresoc.v:158815$8369 + attribute \src "libresoc.v:158611.3-158612.27" + process $proc$libresoc.v:158611$8369 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:158817.3-158825.6" - process $proc$libresoc.v:158817$8370 + attribute \src "libresoc.v:158613.3-158621.6" + process $proc$libresoc.v:158613$8370 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8371 $1\q_int$next[0:0]$8372 - attribute \src "libresoc.v:158818.5-158818.29" + attribute \src "libresoc.v:158614.5-158614.29" switch \initial - attribute \src "libresoc.v:158818.9-158818.17" + attribute \src "libresoc.v:158614.9-158614.17" case 1'1 case end @@ -295528,49 +295362,49 @@ module \opc_l$68 sync always update \q_int$next $0\q_int$next[0:0]$8371 end - connect \$9 $and$libresoc.v:158807$8361_Y - connect \$11 $or$libresoc.v:158808$8362_Y - connect \$13 $not$libresoc.v:158809$8363_Y - connect \$15 $or$libresoc.v:158810$8364_Y - connect \$1 $not$libresoc.v:158811$8365_Y - connect \$3 $and$libresoc.v:158812$8366_Y - connect \$5 $or$libresoc.v:158813$8367_Y - connect \$7 $not$libresoc.v:158814$8368_Y + connect \$9 $and$libresoc.v:158603$8361_Y + connect \$11 $or$libresoc.v:158604$8362_Y + connect \$13 $not$libresoc.v:158605$8363_Y + connect \$15 $or$libresoc.v:158606$8364_Y + connect \$1 $not$libresoc.v:158607$8365_Y + connect \$3 $and$libresoc.v:158608$8366_Y + connect \$5 $or$libresoc.v:158609$8367_Y + connect \$7 $not$libresoc.v:158610$8368_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:158833.1-158891.10" +attribute \src "libresoc.v:158629.1-158687.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" attribute \generator "nMigen" module \opc_l$85 - attribute \src "libresoc.v:158834.7-158834.20" + attribute \src "libresoc.v:158630.7-158630.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158879.3-158887.6" + attribute \src "libresoc.v:158675.3-158683.6" wire $0\q_int$next[0:0]$8385 - attribute \src "libresoc.v:158877.3-158878.27" + attribute \src "libresoc.v:158673.3-158674.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:158879.3-158887.6" + attribute \src "libresoc.v:158675.3-158683.6" wire $1\q_int$next[0:0]$8386 - attribute \src "libresoc.v:158856.7-158856.19" + attribute \src "libresoc.v:158652.7-158652.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:158869.17-158869.96" - wire $and$libresoc.v:158869$8375_Y - attribute \src "libresoc.v:158874.17-158874.96" - wire $and$libresoc.v:158874$8380_Y - attribute \src "libresoc.v:158871.18-158871.93" - wire $not$libresoc.v:158871$8377_Y - attribute \src "libresoc.v:158873.17-158873.92" - wire $not$libresoc.v:158873$8379_Y - attribute \src "libresoc.v:158876.17-158876.92" - wire $not$libresoc.v:158876$8382_Y - attribute \src "libresoc.v:158870.18-158870.98" - wire $or$libresoc.v:158870$8376_Y - attribute \src "libresoc.v:158872.18-158872.99" - wire $or$libresoc.v:158872$8378_Y - attribute \src "libresoc.v:158875.17-158875.97" - wire $or$libresoc.v:158875$8381_Y + attribute \src "libresoc.v:158665.17-158665.96" + wire $and$libresoc.v:158665$8375_Y + attribute \src "libresoc.v:158670.17-158670.96" + wire $and$libresoc.v:158670$8380_Y + attribute \src "libresoc.v:158667.18-158667.93" + wire $not$libresoc.v:158667$8377_Y + attribute \src "libresoc.v:158669.17-158669.92" + wire $not$libresoc.v:158669$8379_Y + attribute \src "libresoc.v:158672.17-158672.92" + wire $not$libresoc.v:158672$8382_Y + attribute \src "libresoc.v:158666.18-158666.98" + wire $or$libresoc.v:158666$8376_Y + attribute \src "libresoc.v:158668.18-158668.99" + wire $or$libresoc.v:158668$8378_Y + attribute \src "libresoc.v:158671.17-158671.97" + wire $or$libresoc.v:158671$8381_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -295587,11 +295421,11 @@ module \opc_l$85 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:158834.7-158834.15" + attribute \src "libresoc.v:158630.7-158630.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -295608,7 +295442,7 @@ module \opc_l$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:158869$8375 + cell $and $and$libresoc.v:158665$8375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295616,10 +295450,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:158869$8375_Y + connect \Y $and$libresoc.v:158665$8375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:158874$8380 + cell $and $and$libresoc.v:158670$8380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295627,34 +295461,34 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:158874$8380_Y + connect \Y $and$libresoc.v:158670$8380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:158871$8377 + cell $not $not$libresoc.v:158667$8377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:158871$8377_Y + connect \Y $not$libresoc.v:158667$8377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:158873$8379 + cell $not $not$libresoc.v:158669$8379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158873$8379_Y + connect \Y $not$libresoc.v:158669$8379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:158876$8382 + cell $not $not$libresoc.v:158672$8382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:158876$8382_Y + connect \Y $not$libresoc.v:158672$8382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:158870$8376 + cell $or $or$libresoc.v:158666$8376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295662,10 +295496,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:158870$8376_Y + connect \Y $or$libresoc.v:158666$8376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:158872$8378 + cell $or $or$libresoc.v:158668$8378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295673,10 +295507,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:158872$8378_Y + connect \Y $or$libresoc.v:158668$8378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:158875$8381 + cell $or $or$libresoc.v:158671$8381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -295684,39 +295518,39 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:158875$8381_Y + connect \Y $or$libresoc.v:158671$8381_Y end - attribute \src "libresoc.v:158834.7-158834.20" - process $proc$libresoc.v:158834$8387 + attribute \src "libresoc.v:158630.7-158630.20" + process $proc$libresoc.v:158630$8387 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158856.7-158856.19" - process $proc$libresoc.v:158856$8388 + attribute \src "libresoc.v:158652.7-158652.19" + process $proc$libresoc.v:158652$8388 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:158877.3-158878.27" - process $proc$libresoc.v:158877$8383 + attribute \src "libresoc.v:158673.3-158674.27" + process $proc$libresoc.v:158673$8383 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:158879.3-158887.6" - process $proc$libresoc.v:158879$8384 + attribute \src "libresoc.v:158675.3-158683.6" + process $proc$libresoc.v:158675$8384 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8385 $1\q_int$next[0:0]$8386 - attribute \src "libresoc.v:158880.5-158880.29" + attribute \src "libresoc.v:158676.5-158676.29" switch \initial - attribute \src "libresoc.v:158880.9-158880.17" + attribute \src "libresoc.v:158676.9-158676.17" case 1'1 case end @@ -295732,83 +295566,83 @@ module \opc_l$85 sync always update \q_int$next $0\q_int$next[0:0]$8385 end - connect \$9 $and$libresoc.v:158869$8375_Y - connect \$11 $or$libresoc.v:158870$8376_Y - connect \$13 $not$libresoc.v:158871$8377_Y - connect \$15 $or$libresoc.v:158872$8378_Y - connect \$1 $not$libresoc.v:158873$8379_Y - connect \$3 $and$libresoc.v:158874$8380_Y - connect \$5 $or$libresoc.v:158875$8381_Y - connect \$7 $not$libresoc.v:158876$8382_Y + connect \$9 $and$libresoc.v:158665$8375_Y + connect \$11 $or$libresoc.v:158666$8376_Y + connect \$13 $not$libresoc.v:158667$8377_Y + connect \$15 $or$libresoc.v:158668$8378_Y + connect \$1 $not$libresoc.v:158669$8379_Y + connect \$3 $and$libresoc.v:158670$8380_Y + connect \$5 $or$libresoc.v:158671$8381_Y + connect \$7 $not$libresoc.v:158672$8382_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:158895.1-159353.10" +attribute \src "libresoc.v:158691.1-159149.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" attribute \generator "nMigen" module \output - attribute \src "libresoc.v:159272.3-159283.6" + attribute \src "libresoc.v:159068.3-159079.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:158896.7-158896.20" + attribute \src "libresoc.v:158692.7-158692.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159284.3-159295.6" + attribute \src "libresoc.v:159080.3-159091.6" wire width 65 $0\o$28[64:0]$8407 - attribute \src "libresoc.v:159260.3-159271.6" + attribute \src "libresoc.v:159056.3-159067.6" wire $0\so[0:0] - attribute \src "libresoc.v:159316.3-159325.6" + attribute \src "libresoc.v:159112.3-159121.6" wire width 2 $0\xer_ov$24[1:0]$8414 - attribute \src "libresoc.v:159326.3-159335.6" + attribute \src "libresoc.v:159122.3-159131.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:159296.3-159305.6" + attribute \src "libresoc.v:159092.3-159101.6" wire $0\xer_so$25[0:0]$8410 - attribute \src "libresoc.v:159306.3-159315.6" + attribute \src "libresoc.v:159102.3-159111.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:159272.3-159283.6" + attribute \src "libresoc.v:159068.3-159079.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:159284.3-159295.6" + attribute \src "libresoc.v:159080.3-159091.6" wire width 65 $1\o$28[64:0]$8408 - attribute \src "libresoc.v:159260.3-159271.6" + attribute \src "libresoc.v:159056.3-159067.6" wire $1\so[0:0] - attribute \src "libresoc.v:159316.3-159325.6" + attribute \src "libresoc.v:159112.3-159121.6" wire width 2 $1\xer_ov$24[1:0]$8415 - attribute \src "libresoc.v:159326.3-159335.6" + attribute \src "libresoc.v:159122.3-159131.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:159296.3-159305.6" + attribute \src "libresoc.v:159092.3-159101.6" wire $1\xer_so$25[0:0]$8411 - attribute \src "libresoc.v:159306.3-159315.6" + attribute \src "libresoc.v:159102.3-159111.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:159247.18-159247.128" - wire $and$libresoc.v:159247$8389_Y - attribute \src "libresoc.v:159255.18-159255.112" - wire $and$libresoc.v:159255$8399_Y - attribute \src "libresoc.v:159258.18-159258.125" - wire $and$libresoc.v:159258$8402_Y - attribute \src "libresoc.v:159251.18-159251.123" - wire $eq$libresoc.v:159251$8395_Y - attribute \src "libresoc.v:159252.18-159252.123" - wire $eq$libresoc.v:159252$8396_Y - attribute \src "libresoc.v:159249.18-159249.103" - wire width 65 $extend$libresoc.v:159249$8391_Y - attribute \src "libresoc.v:159250.18-159250.101" - wire width 65 $extend$libresoc.v:159250$8393_Y - attribute \src "libresoc.v:159248.18-159248.100" - wire width 64 $not$libresoc.v:159248$8390_Y - attribute \src "libresoc.v:159254.18-159254.107" - wire $not$libresoc.v:159254$8398_Y - attribute \src "libresoc.v:159257.18-159257.107" - wire $not$libresoc.v:159257$8401_Y - attribute \src "libresoc.v:159256.18-159256.115" - wire $or$libresoc.v:159256$8400_Y - attribute \src "libresoc.v:159259.18-159259.112" - wire $or$libresoc.v:159259$8403_Y - attribute \src "libresoc.v:159249.18-159249.103" - wire width 65 $pos$libresoc.v:159249$8392_Y - attribute \src "libresoc.v:159250.18-159250.101" - wire width 65 $pos$libresoc.v:159250$8394_Y - attribute \src "libresoc.v:159253.18-159253.105" - wire $reduce_or$libresoc.v:159253$8397_Y + attribute \src "libresoc.v:159043.18-159043.128" + wire $and$libresoc.v:159043$8389_Y + attribute \src "libresoc.v:159051.18-159051.112" + wire $and$libresoc.v:159051$8399_Y + attribute \src "libresoc.v:159054.18-159054.125" + wire $and$libresoc.v:159054$8402_Y + attribute \src "libresoc.v:159047.18-159047.123" + wire $eq$libresoc.v:159047$8395_Y + attribute \src "libresoc.v:159048.18-159048.123" + wire $eq$libresoc.v:159048$8396_Y + attribute \src "libresoc.v:159045.18-159045.103" + wire width 65 $extend$libresoc.v:159045$8391_Y + attribute \src "libresoc.v:159046.18-159046.101" + wire width 65 $extend$libresoc.v:159046$8393_Y + attribute \src "libresoc.v:159044.18-159044.100" + wire width 64 $not$libresoc.v:159044$8390_Y + attribute \src "libresoc.v:159050.18-159050.107" + wire $not$libresoc.v:159050$8398_Y + attribute \src "libresoc.v:159053.18-159053.107" + wire $not$libresoc.v:159053$8401_Y + attribute \src "libresoc.v:159052.18-159052.115" + wire $or$libresoc.v:159052$8400_Y + attribute \src "libresoc.v:159055.18-159055.112" + wire $or$libresoc.v:159055$8403_Y + attribute \src "libresoc.v:159045.18-159045.103" + wire width 65 $pos$libresoc.v:159045$8392_Y + attribute \src "libresoc.v:159046.18-159046.101" + wire width 65 $pos$libresoc.v:159046$8394_Y + attribute \src "libresoc.v:159049.18-159049.105" + wire $reduce_or$libresoc.v:159049$8397_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -296103,7 +295937,7 @@ module \output wire width 4 output 46 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 47 \cr_a_ok - attribute \src "libresoc.v:158896.7-158896.15" + attribute \src "libresoc.v:158692.7-158692.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -296158,7 +295992,7 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 53 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:159247$8389 + cell $and $and$libresoc.v:159043$8389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296166,10 +296000,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:159247$8389_Y + connect \Y $and$libresoc.v:159043$8389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:159255$8399 + cell $and $and$libresoc.v:159051$8399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296177,10 +296011,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$41 - connect \Y $and$libresoc.v:159255$8399_Y + connect \Y $and$libresoc.v:159051$8399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:159258$8402 + cell $and $and$libresoc.v:159054$8402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296188,10 +296022,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:159258$8402_Y + connect \Y $and$libresoc.v:159054$8402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:159251$8395 + cell $eq $eq$libresoc.v:159047$8395 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -296199,10 +296033,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:159251$8395_Y + connect \Y $eq$libresoc.v:159047$8395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:159252$8396 + cell $eq $eq$libresoc.v:159048$8396 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -296210,50 +296044,50 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:159252$8396_Y + connect \Y $eq$libresoc.v:159048$8396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:159249$8391 + cell $pos $extend$libresoc.v:159045$8391 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$30 - connect \Y $extend$libresoc.v:159249$8391_Y + connect \Y $extend$libresoc.v:159045$8391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:159250$8393 + cell $pos $extend$libresoc.v:159046$8393 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:159250$8393_Y + connect \Y $extend$libresoc.v:159046$8393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:159248$8390 + cell $not $not$libresoc.v:159044$8390 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:159248$8390_Y + connect \Y $not$libresoc.v:159044$8390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:159254$8398 + cell $not $not$libresoc.v:159050$8398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:159254$8398_Y + connect \Y $not$libresoc.v:159050$8398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:159257$8401 + cell $not $not$libresoc.v:159053$8401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:159257$8401_Y + connect \Y $not$libresoc.v:159053$8401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:159256$8400 + cell $or $or$libresoc.v:159052$8400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296261,10 +296095,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:159256$8400_Y + connect \Y $or$libresoc.v:159052$8400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:159259$8403 + cell $or $or$libresoc.v:159055$8403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296272,47 +296106,47 @@ module \output parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:159259$8403_Y + connect \Y $or$libresoc.v:159055$8403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:159249$8392 + cell $pos $pos$libresoc.v:159045$8392 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159249$8391_Y - connect \Y $pos$libresoc.v:159249$8392_Y + connect \A $extend$libresoc.v:159045$8391_Y + connect \Y $pos$libresoc.v:159045$8392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:159250$8394 + cell $pos $pos$libresoc.v:159046$8394 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159250$8393_Y - connect \Y $pos$libresoc.v:159250$8394_Y + connect \A $extend$libresoc.v:159046$8393_Y + connect \Y $pos$libresoc.v:159046$8394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:159253$8397 + cell $reduce_or $reduce_or$libresoc.v:159049$8397 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:159253$8397_Y + connect \Y $reduce_or$libresoc.v:159049$8397_Y end - attribute \src "libresoc.v:158896.7-158896.20" - process $proc$libresoc.v:158896$8417 + attribute \src "libresoc.v:158692.7-158692.20" + process $proc$libresoc.v:158692$8417 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159260.3-159271.6" - process $proc$libresoc.v:159260$8404 + attribute \src "libresoc.v:159056.3-159067.6" + process $proc$libresoc.v:159056$8404 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:159261.5-159261.29" + attribute \src "libresoc.v:159057.5-159057.29" switch \initial - attribute \src "libresoc.v:159261.9-159261.17" + attribute \src "libresoc.v:159057.9-159057.17" case 1'1 case end @@ -296330,13 +296164,13 @@ module \output sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:159272.3-159283.6" - process $proc$libresoc.v:159272$8405 + attribute \src "libresoc.v:159068.3-159079.6" + process $proc$libresoc.v:159068$8405 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:159273.5-159273.29" + attribute \src "libresoc.v:159069.5-159069.29" switch \initial - attribute \src "libresoc.v:159273.9-159273.17" + attribute \src "libresoc.v:159069.9-159069.17" case 1'1 case end @@ -296354,13 +296188,13 @@ module \output sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:159284.3-159295.6" - process $proc$libresoc.v:159284$8406 + attribute \src "libresoc.v:159080.3-159091.6" + process $proc$libresoc.v:159080$8406 assign { } { } assign $0\o$28[64:0]$8407 $1\o$28[64:0]$8408 - attribute \src "libresoc.v:159285.5-159285.29" + attribute \src "libresoc.v:159081.5-159081.29" switch \initial - attribute \src "libresoc.v:159285.9-159285.17" + attribute \src "libresoc.v:159081.9-159081.17" case 1'1 case end @@ -296378,14 +296212,14 @@ module \output sync always update \o$28 $0\o$28[64:0]$8407 end - attribute \src "libresoc.v:159296.3-159305.6" - process $proc$libresoc.v:159296$8409 + attribute \src "libresoc.v:159092.3-159101.6" + process $proc$libresoc.v:159092$8409 assign { } { } assign { } { } assign $0\xer_so$25[0:0]$8410 $1\xer_so$25[0:0]$8411 - attribute \src "libresoc.v:159297.5-159297.29" + attribute \src "libresoc.v:159093.5-159093.29" switch \initial - attribute \src "libresoc.v:159297.9-159297.17" + attribute \src "libresoc.v:159093.9-159093.17" case 1'1 case end @@ -296401,14 +296235,14 @@ module \output sync always update \xer_so$25 $0\xer_so$25[0:0]$8410 end - attribute \src "libresoc.v:159306.3-159315.6" - process $proc$libresoc.v:159306$8412 + attribute \src "libresoc.v:159102.3-159111.6" + process $proc$libresoc.v:159102$8412 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:159307.5-159307.29" + attribute \src "libresoc.v:159103.5-159103.29" switch \initial - attribute \src "libresoc.v:159307.9-159307.17" + attribute \src "libresoc.v:159103.9-159103.17" case 1'1 case end @@ -296424,14 +296258,14 @@ module \output sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:159316.3-159325.6" - process $proc$libresoc.v:159316$8413 + attribute \src "libresoc.v:159112.3-159121.6" + process $proc$libresoc.v:159112$8413 assign { } { } assign { } { } assign $0\xer_ov$24[1:0]$8414 $1\xer_ov$24[1:0]$8415 - attribute \src "libresoc.v:159317.5-159317.29" + attribute \src "libresoc.v:159113.5-159113.29" switch \initial - attribute \src "libresoc.v:159317.9-159317.17" + attribute \src "libresoc.v:159113.9-159113.17" case 1'1 case end @@ -296447,14 +296281,14 @@ module \output sync always update \xer_ov$24 $0\xer_ov$24[1:0]$8414 end - attribute \src "libresoc.v:159326.3-159335.6" - process $proc$libresoc.v:159326$8416 + attribute \src "libresoc.v:159122.3-159131.6" + process $proc$libresoc.v:159122$8416 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:159327.5-159327.29" + attribute \src "libresoc.v:159123.5-159123.29" switch \initial - attribute \src "libresoc.v:159327.9-159327.17" + attribute \src "libresoc.v:159123.9-159123.17" case 1'1 case end @@ -296470,19 +296304,19 @@ module \output sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$26 $and$libresoc.v:159247$8389_Y - connect \$30 $not$libresoc.v:159248$8390_Y - connect \$29 $pos$libresoc.v:159249$8392_Y - connect \$33 $pos$libresoc.v:159250$8394_Y - connect \$35 $eq$libresoc.v:159251$8395_Y - connect \$37 $eq$libresoc.v:159252$8396_Y - connect \$39 $reduce_or$libresoc.v:159253$8397_Y - connect \$41 $not$libresoc.v:159254$8398_Y - connect \$43 $and$libresoc.v:159255$8399_Y - connect \$45 $or$libresoc.v:159256$8400_Y - connect \$47 $not$libresoc.v:159257$8401_Y - connect \$50 $and$libresoc.v:159258$8402_Y - connect \$52 $or$libresoc.v:159259$8403_Y + connect \$26 $and$libresoc.v:159043$8389_Y + connect \$30 $not$libresoc.v:159044$8390_Y + connect \$29 $pos$libresoc.v:159045$8392_Y + connect \$33 $pos$libresoc.v:159046$8394_Y + connect \$35 $eq$libresoc.v:159047$8395_Y + connect \$37 $eq$libresoc.v:159048$8396_Y + connect \$39 $reduce_or$libresoc.v:159049$8397_Y + connect \$41 $not$libresoc.v:159050$8398_Y + connect \$43 $and$libresoc.v:159051$8399_Y + connect \$45 $or$libresoc.v:159052$8400_Y + connect \$47 $not$libresoc.v:159053$8401_Y + connect \$50 $and$libresoc.v:159054$8402_Y + connect \$52 $or$libresoc.v:159055$8403_Y connect \oe$49 \$50 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid @@ -296501,61 +296335,61 @@ module \output connect \target \o$28 [63:0] connect \oe \$26 end -attribute \src "libresoc.v:159357.1-159758.10" +attribute \src "libresoc.v:159153.1-159554.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" attribute \generator "nMigen" module \output$100 - attribute \src "libresoc.v:159690.3-159701.6" + attribute \src "libresoc.v:159486.3-159497.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:159358.7-159358.20" + attribute \src "libresoc.v:159154.7-159154.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159678.3-159689.6" + attribute \src "libresoc.v:159474.3-159485.6" wire $0\so[0:0] - attribute \src "libresoc.v:159722.3-159731.6" + attribute \src "libresoc.v:159518.3-159527.6" wire width 2 $0\xer_ov$17[1:0]$8437 - attribute \src "libresoc.v:159732.3-159741.6" + attribute \src "libresoc.v:159528.3-159537.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:159702.3-159711.6" + attribute \src "libresoc.v:159498.3-159507.6" wire $0\xer_so$18[0:0]$8433 - attribute \src "libresoc.v:159712.3-159721.6" + attribute \src "libresoc.v:159508.3-159517.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:159690.3-159701.6" + attribute \src "libresoc.v:159486.3-159497.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:159678.3-159689.6" + attribute \src "libresoc.v:159474.3-159485.6" wire $1\so[0:0] - attribute \src "libresoc.v:159722.3-159731.6" + attribute \src "libresoc.v:159518.3-159527.6" wire width 2 $1\xer_ov$17[1:0]$8438 - attribute \src "libresoc.v:159732.3-159741.6" + attribute \src "libresoc.v:159528.3-159537.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:159702.3-159711.6" + attribute \src "libresoc.v:159498.3-159507.6" wire $1\xer_so$18[0:0]$8434 - attribute \src "libresoc.v:159712.3-159721.6" + attribute \src "libresoc.v:159508.3-159517.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:159667.18-159667.128" - wire $and$libresoc.v:159667$8418_Y - attribute \src "libresoc.v:159673.18-159673.112" - wire $and$libresoc.v:159673$8425_Y - attribute \src "libresoc.v:159676.18-159676.125" - wire $and$libresoc.v:159676$8428_Y - attribute \src "libresoc.v:159669.18-159669.123" - wire $eq$libresoc.v:159669$8421_Y - attribute \src "libresoc.v:159670.18-159670.123" - wire $eq$libresoc.v:159670$8422_Y - attribute \src "libresoc.v:159668.18-159668.101" - wire width 65 $extend$libresoc.v:159668$8419_Y - attribute \src "libresoc.v:159672.18-159672.107" - wire $not$libresoc.v:159672$8424_Y - attribute \src "libresoc.v:159675.18-159675.107" - wire $not$libresoc.v:159675$8427_Y - attribute \src "libresoc.v:159674.18-159674.115" - wire $or$libresoc.v:159674$8426_Y - attribute \src "libresoc.v:159677.18-159677.112" - wire $or$libresoc.v:159677$8429_Y - attribute \src "libresoc.v:159668.18-159668.101" - wire width 65 $pos$libresoc.v:159668$8420_Y - attribute \src "libresoc.v:159671.18-159671.105" - wire $reduce_or$libresoc.v:159671$8423_Y + attribute \src "libresoc.v:159463.18-159463.128" + wire $and$libresoc.v:159463$8418_Y + attribute \src "libresoc.v:159469.18-159469.112" + wire $and$libresoc.v:159469$8425_Y + attribute \src "libresoc.v:159472.18-159472.125" + wire $and$libresoc.v:159472$8428_Y + attribute \src "libresoc.v:159465.18-159465.123" + wire $eq$libresoc.v:159465$8421_Y + attribute \src "libresoc.v:159466.18-159466.123" + wire $eq$libresoc.v:159466$8422_Y + attribute \src "libresoc.v:159464.18-159464.101" + wire width 65 $extend$libresoc.v:159464$8419_Y + attribute \src "libresoc.v:159468.18-159468.107" + wire $not$libresoc.v:159468$8424_Y + attribute \src "libresoc.v:159471.18-159471.107" + wire $not$libresoc.v:159471$8427_Y + attribute \src "libresoc.v:159470.18-159470.115" + wire $or$libresoc.v:159470$8426_Y + attribute \src "libresoc.v:159473.18-159473.112" + wire $or$libresoc.v:159473$8429_Y + attribute \src "libresoc.v:159464.18-159464.101" + wire width 65 $pos$libresoc.v:159464$8420_Y + attribute \src "libresoc.v:159467.18-159467.105" + wire $reduce_or$libresoc.v:159467$8423_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" @@ -296586,7 +296420,7 @@ module \output$100 wire width 4 output 33 \cr_a$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 34 \cr_a_ok - attribute \src "libresoc.v:159358.7-159358.15" + attribute \src "libresoc.v:159154.7-159154.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -296863,7 +296697,7 @@ module \output$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 38 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:159667$8418 + cell $and $and$libresoc.v:159463$8418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296871,10 +296705,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:159667$8418_Y + connect \Y $and$libresoc.v:159463$8418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:159673$8425 + cell $and $and$libresoc.v:159469$8425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296882,10 +296716,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$30 - connect \Y $and$libresoc.v:159673$8425_Y + connect \Y $and$libresoc.v:159469$8425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:159676$8428 + cell $and $and$libresoc.v:159472$8428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296893,10 +296727,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:159676$8428_Y + connect \Y $and$libresoc.v:159472$8428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:159669$8421 + cell $eq $eq$libresoc.v:159465$8421 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -296904,10 +296738,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:159669$8421_Y + connect \Y $eq$libresoc.v:159465$8421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:159670$8422 + cell $eq $eq$libresoc.v:159466$8422 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -296915,34 +296749,34 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:159670$8422_Y + connect \Y $eq$libresoc.v:159466$8422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:159668$8419 + cell $pos $extend$libresoc.v:159464$8419 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:159668$8419_Y + connect \Y $extend$libresoc.v:159464$8419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:159672$8424 + cell $not $not$libresoc.v:159468$8424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:159672$8424_Y + connect \Y $not$libresoc.v:159468$8424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:159675$8427 + cell $not $not$libresoc.v:159471$8427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:159675$8427_Y + connect \Y $not$libresoc.v:159471$8427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:159674$8426 + cell $or $or$libresoc.v:159470$8426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296950,10 +296784,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:159674$8426_Y + connect \Y $or$libresoc.v:159470$8426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:159677$8429 + cell $or $or$libresoc.v:159473$8429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296961,39 +296795,39 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:159677$8429_Y + connect \Y $or$libresoc.v:159473$8429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:159668$8420 + cell $pos $pos$libresoc.v:159464$8420 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159668$8419_Y - connect \Y $pos$libresoc.v:159668$8420_Y + connect \A $extend$libresoc.v:159464$8419_Y + connect \Y $pos$libresoc.v:159464$8420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:159671$8423 + cell $reduce_or $reduce_or$libresoc.v:159467$8423 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:159671$8423_Y + connect \Y $reduce_or$libresoc.v:159467$8423_Y end - attribute \src "libresoc.v:159358.7-159358.20" - process $proc$libresoc.v:159358$8440 + attribute \src "libresoc.v:159154.7-159154.20" + process $proc$libresoc.v:159154$8440 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159678.3-159689.6" - process $proc$libresoc.v:159678$8430 + attribute \src "libresoc.v:159474.3-159485.6" + process $proc$libresoc.v:159474$8430 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:159679.5-159679.29" + attribute \src "libresoc.v:159475.5-159475.29" switch \initial - attribute \src "libresoc.v:159679.9-159679.17" + attribute \src "libresoc.v:159475.9-159475.17" case 1'1 case end @@ -297011,13 +296845,13 @@ module \output$100 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:159690.3-159701.6" - process $proc$libresoc.v:159690$8431 + attribute \src "libresoc.v:159486.3-159497.6" + process $proc$libresoc.v:159486$8431 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:159691.5-159691.29" + attribute \src "libresoc.v:159487.5-159487.29" switch \initial - attribute \src "libresoc.v:159691.9-159691.17" + attribute \src "libresoc.v:159487.9-159487.17" case 1'1 case end @@ -297035,14 +296869,14 @@ module \output$100 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:159702.3-159711.6" - process $proc$libresoc.v:159702$8432 + attribute \src "libresoc.v:159498.3-159507.6" + process $proc$libresoc.v:159498$8432 assign { } { } assign { } { } assign $0\xer_so$18[0:0]$8433 $1\xer_so$18[0:0]$8434 - attribute \src "libresoc.v:159703.5-159703.29" + attribute \src "libresoc.v:159499.5-159499.29" switch \initial - attribute \src "libresoc.v:159703.9-159703.17" + attribute \src "libresoc.v:159499.9-159499.17" case 1'1 case end @@ -297058,14 +296892,14 @@ module \output$100 sync always update \xer_so$18 $0\xer_so$18[0:0]$8433 end - attribute \src "libresoc.v:159712.3-159721.6" - process $proc$libresoc.v:159712$8435 + attribute \src "libresoc.v:159508.3-159517.6" + process $proc$libresoc.v:159508$8435 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:159713.5-159713.29" + attribute \src "libresoc.v:159509.5-159509.29" switch \initial - attribute \src "libresoc.v:159713.9-159713.17" + attribute \src "libresoc.v:159509.9-159509.17" case 1'1 case end @@ -297081,14 +296915,14 @@ module \output$100 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:159722.3-159731.6" - process $proc$libresoc.v:159722$8436 + attribute \src "libresoc.v:159518.3-159527.6" + process $proc$libresoc.v:159518$8436 assign { } { } assign { } { } assign $0\xer_ov$17[1:0]$8437 $1\xer_ov$17[1:0]$8438 - attribute \src "libresoc.v:159723.5-159723.29" + attribute \src "libresoc.v:159519.5-159519.29" switch \initial - attribute \src "libresoc.v:159723.9-159723.17" + attribute \src "libresoc.v:159519.9-159519.17" case 1'1 case end @@ -297104,14 +296938,14 @@ module \output$100 sync always update \xer_ov$17 $0\xer_ov$17[1:0]$8437 end - attribute \src "libresoc.v:159732.3-159741.6" - process $proc$libresoc.v:159732$8439 + attribute \src "libresoc.v:159528.3-159537.6" + process $proc$libresoc.v:159528$8439 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:159733.5-159733.29" + attribute \src "libresoc.v:159529.5-159529.29" switch \initial - attribute \src "libresoc.v:159733.9-159733.17" + attribute \src "libresoc.v:159529.9-159529.17" case 1'1 case end @@ -297127,17 +296961,17 @@ module \output$100 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$19 $and$libresoc.v:159667$8418_Y - connect \$22 $pos$libresoc.v:159668$8420_Y - connect \$24 $eq$libresoc.v:159669$8421_Y - connect \$26 $eq$libresoc.v:159670$8422_Y - connect \$28 $reduce_or$libresoc.v:159671$8423_Y - connect \$30 $not$libresoc.v:159672$8424_Y - connect \$32 $and$libresoc.v:159673$8425_Y - connect \$34 $or$libresoc.v:159674$8426_Y - connect \$36 $not$libresoc.v:159675$8427_Y - connect \$39 $and$libresoc.v:159676$8428_Y - connect \$41 $or$libresoc.v:159677$8429_Y + connect \$19 $and$libresoc.v:159463$8418_Y + connect \$22 $pos$libresoc.v:159464$8420_Y + connect \$24 $eq$libresoc.v:159465$8421_Y + connect \$26 $eq$libresoc.v:159466$8422_Y + connect \$28 $reduce_or$libresoc.v:159467$8423_Y + connect \$30 $not$libresoc.v:159468$8424_Y + connect \$32 $and$libresoc.v:159469$8425_Y + connect \$34 $or$libresoc.v:159470$8426_Y + connect \$36 $not$libresoc.v:159471$8427_Y + connect \$39 $and$libresoc.v:159472$8428_Y + connect \$41 $or$libresoc.v:159473$8429_Y connect \oe$38 \$39 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -297155,35 +296989,35 @@ module \output$100 connect \o$21 \$22 connect \oe \$19 end -attribute \src "libresoc.v:159762.1-160116.10" +attribute \src "libresoc.v:159558.1-159912.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" attribute \generator "nMigen" module \output$118 - attribute \src "libresoc.v:160088.3-160099.6" + attribute \src "libresoc.v:159884.3-159895.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:159763.7-159763.20" + attribute \src "libresoc.v:159559.7-159559.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160088.3-160099.6" + attribute \src "libresoc.v:159884.3-159895.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:160085.18-160085.112" - wire $and$libresoc.v:160085$8447_Y - attribute \src "libresoc.v:160081.18-160081.122" - wire $eq$libresoc.v:160081$8443_Y - attribute \src "libresoc.v:160082.18-160082.122" - wire $eq$libresoc.v:160082$8444_Y - attribute \src "libresoc.v:160080.18-160080.101" - wire width 65 $extend$libresoc.v:160080$8441_Y - attribute \src "libresoc.v:160084.18-160084.107" - wire $not$libresoc.v:160084$8446_Y - attribute \src "libresoc.v:160087.18-160087.107" - wire $not$libresoc.v:160087$8449_Y - attribute \src "libresoc.v:160086.18-160086.115" - wire $or$libresoc.v:160086$8448_Y - attribute \src "libresoc.v:160080.18-160080.101" - wire width 65 $pos$libresoc.v:160080$8442_Y - attribute \src "libresoc.v:160083.18-160083.105" - wire $reduce_or$libresoc.v:160083$8445_Y + attribute \src "libresoc.v:159881.18-159881.112" + wire $and$libresoc.v:159881$8447_Y + attribute \src "libresoc.v:159877.18-159877.122" + wire $eq$libresoc.v:159877$8443_Y + attribute \src "libresoc.v:159878.18-159878.122" + wire $eq$libresoc.v:159878$8444_Y + attribute \src "libresoc.v:159876.18-159876.101" + wire width 65 $extend$libresoc.v:159876$8441_Y + attribute \src "libresoc.v:159880.18-159880.107" + wire $not$libresoc.v:159880$8446_Y + attribute \src "libresoc.v:159883.18-159883.107" + wire $not$libresoc.v:159883$8449_Y + attribute \src "libresoc.v:159882.18-159882.115" + wire $or$libresoc.v:159882$8448_Y + attribute \src "libresoc.v:159876.18-159876.101" + wire width 65 $pos$libresoc.v:159876$8442_Y + attribute \src "libresoc.v:159879.18-159879.105" + wire $reduce_or$libresoc.v:159879$8445_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" @@ -297208,7 +297042,7 @@ module \output$118 wire width 4 output 43 \cr_a$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 44 \cr_a_ok - attribute \src "libresoc.v:159763.7-159763.15" + attribute \src "libresoc.v:159559.7-159559.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -297503,7 +297337,7 @@ module \output$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:160085$8447 + cell $and $and$libresoc.v:159881$8447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297511,10 +297345,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$32 - connect \Y $and$libresoc.v:160085$8447_Y + connect \Y $and$libresoc.v:159881$8447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:160081$8443 + cell $eq $eq$libresoc.v:159877$8443 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -297522,10 +297356,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:160081$8443_Y + connect \Y $eq$libresoc.v:159877$8443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:160082$8444 + cell $eq $eq$libresoc.v:159878$8444 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -297533,34 +297367,34 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:160082$8444_Y + connect \Y $eq$libresoc.v:159878$8444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:160080$8441 + cell $pos $extend$libresoc.v:159876$8441 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:160080$8441_Y + connect \Y $extend$libresoc.v:159876$8441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:160084$8446 + cell $not $not$libresoc.v:159880$8446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:160084$8446_Y + connect \Y $not$libresoc.v:159880$8446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:160087$8449 + cell $not $not$libresoc.v:159883$8449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:160087$8449_Y + connect \Y $not$libresoc.v:159883$8449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:160086$8448 + cell $or $or$libresoc.v:159882$8448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297568,39 +297402,39 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:160086$8448_Y + connect \Y $or$libresoc.v:159882$8448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:160080$8442 + cell $pos $pos$libresoc.v:159876$8442 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160080$8441_Y - connect \Y $pos$libresoc.v:160080$8442_Y + connect \A $extend$libresoc.v:159876$8441_Y + connect \Y $pos$libresoc.v:159876$8442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:160083$8445 + cell $reduce_or $reduce_or$libresoc.v:159879$8445 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:160083$8445_Y + connect \Y $reduce_or$libresoc.v:159879$8445_Y end - attribute \src "libresoc.v:159763.7-159763.20" - process $proc$libresoc.v:159763$8451 + attribute \src "libresoc.v:159559.7-159559.20" + process $proc$libresoc.v:159559$8451 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160088.3-160099.6" - process $proc$libresoc.v:160088$8450 + attribute \src "libresoc.v:159884.3-159895.6" + process $proc$libresoc.v:159884$8450 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:160089.5-160089.29" + attribute \src "libresoc.v:159885.5-159885.29" switch \initial - attribute \src "libresoc.v:160089.9-160089.17" + attribute \src "libresoc.v:159885.9-159885.17" case 1'1 case end @@ -297618,14 +297452,14 @@ module \output$118 sync always update \cr0 $0\cr0[3:0] end - connect \$24 $pos$libresoc.v:160080$8442_Y - connect \$26 $eq$libresoc.v:160081$8443_Y - connect \$28 $eq$libresoc.v:160082$8444_Y - connect \$30 $reduce_or$libresoc.v:160083$8445_Y - connect \$32 $not$libresoc.v:160084$8446_Y - connect \$34 $and$libresoc.v:160085$8447_Y - connect \$36 $or$libresoc.v:160086$8448_Y - connect \$38 $not$libresoc.v:160087$8449_Y + connect \$24 $pos$libresoc.v:159876$8442_Y + connect \$26 $eq$libresoc.v:159877$8443_Y + connect \$28 $eq$libresoc.v:159878$8444_Y + connect \$30 $reduce_or$libresoc.v:159879$8445_Y + connect \$32 $not$libresoc.v:159880$8446_Y + connect \$34 $and$libresoc.v:159881$8447_Y + connect \$36 $or$libresoc.v:159882$8448_Y + connect \$38 $not$libresoc.v:159883$8449_Y connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \sr_op__write_cr0 @@ -297643,45 +297477,45 @@ module \output$118 connect \target \o$23 [63:0] connect \o$23 \$24 end -attribute \src "libresoc.v:160120.1-160487.10" +attribute \src "libresoc.v:159916.1-160283.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" attribute \generator "nMigen" module \output$54 - attribute \src "libresoc.v:160462.3-160473.6" + attribute \src "libresoc.v:160258.3-160269.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:160121.7-160121.20" + attribute \src "libresoc.v:159917.7-159917.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160450.3-160461.6" + attribute \src "libresoc.v:160246.3-160257.6" wire width 65 $0\o$23[64:0]$8465 - attribute \src "libresoc.v:160462.3-160473.6" + attribute \src "libresoc.v:160258.3-160269.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:160450.3-160461.6" + attribute \src "libresoc.v:160246.3-160257.6" wire width 65 $1\o$23[64:0]$8466 - attribute \src "libresoc.v:160447.18-160447.112" - wire $and$libresoc.v:160447$8461_Y - attribute \src "libresoc.v:160443.18-160443.127" - wire $eq$libresoc.v:160443$8457_Y - attribute \src "libresoc.v:160444.18-160444.127" - wire $eq$libresoc.v:160444$8458_Y - attribute \src "libresoc.v:160441.18-160441.103" - wire width 65 $extend$libresoc.v:160441$8453_Y - attribute \src "libresoc.v:160442.18-160442.101" - wire width 65 $extend$libresoc.v:160442$8455_Y - attribute \src "libresoc.v:160440.18-160440.100" - wire width 64 $not$libresoc.v:160440$8452_Y - attribute \src "libresoc.v:160446.18-160446.107" - wire $not$libresoc.v:160446$8460_Y - attribute \src "libresoc.v:160449.18-160449.107" - wire $not$libresoc.v:160449$8463_Y - attribute \src "libresoc.v:160448.18-160448.115" - wire $or$libresoc.v:160448$8462_Y - attribute \src "libresoc.v:160441.18-160441.103" - wire width 65 $pos$libresoc.v:160441$8454_Y - attribute \src "libresoc.v:160442.18-160442.101" - wire width 65 $pos$libresoc.v:160442$8456_Y - attribute \src "libresoc.v:160445.18-160445.105" - wire $reduce_or$libresoc.v:160445$8459_Y + attribute \src "libresoc.v:160243.18-160243.112" + wire $and$libresoc.v:160243$8461_Y + attribute \src "libresoc.v:160239.18-160239.127" + wire $eq$libresoc.v:160239$8457_Y + attribute \src "libresoc.v:160240.18-160240.127" + wire $eq$libresoc.v:160240$8458_Y + attribute \src "libresoc.v:160237.18-160237.103" + wire width 65 $extend$libresoc.v:160237$8453_Y + attribute \src "libresoc.v:160238.18-160238.101" + wire width 65 $extend$libresoc.v:160238$8455_Y + attribute \src "libresoc.v:160236.18-160236.100" + wire width 64 $not$libresoc.v:160236$8452_Y + attribute \src "libresoc.v:160242.18-160242.107" + wire $not$libresoc.v:160242$8460_Y + attribute \src "libresoc.v:160245.18-160245.107" + wire $not$libresoc.v:160245$8463_Y + attribute \src "libresoc.v:160244.18-160244.115" + wire $or$libresoc.v:160244$8462_Y + attribute \src "libresoc.v:160237.18-160237.103" + wire width 65 $pos$libresoc.v:160237$8454_Y + attribute \src "libresoc.v:160238.18-160238.101" + wire width 65 $pos$libresoc.v:160238$8456_Y + attribute \src "libresoc.v:160241.18-160241.105" + wire $reduce_or$libresoc.v:160241$8459_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -297710,7 +297544,7 @@ module \output$54 wire width 4 output 44 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 45 \cr_a_ok - attribute \src "libresoc.v:160121.7-160121.15" + attribute \src "libresoc.v:159917.7-159917.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -298003,7 +297837,7 @@ module \output$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 22 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:160447$8461 + cell $and $and$libresoc.v:160243$8461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298011,10 +297845,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$36 - connect \Y $and$libresoc.v:160447$8461_Y + connect \Y $and$libresoc.v:160243$8461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:160443$8457 + cell $eq $eq$libresoc.v:160239$8457 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -298022,10 +297856,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:160443$8457_Y + connect \Y $eq$libresoc.v:160239$8457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:160444$8458 + cell $eq $eq$libresoc.v:160240$8458 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -298033,50 +297867,50 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:160444$8458_Y + connect \Y $eq$libresoc.v:160240$8458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:160441$8453 + cell $pos $extend$libresoc.v:160237$8453 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$25 - connect \Y $extend$libresoc.v:160441$8453_Y + connect \Y $extend$libresoc.v:160237$8453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:160442$8455 + cell $pos $extend$libresoc.v:160238$8455 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:160442$8455_Y + connect \Y $extend$libresoc.v:160238$8455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:160440$8452 + cell $not $not$libresoc.v:160236$8452 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:160440$8452_Y + connect \Y $not$libresoc.v:160236$8452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:160446$8460 + cell $not $not$libresoc.v:160242$8460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:160446$8460_Y + connect \Y $not$libresoc.v:160242$8460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:160449$8463 + cell $not $not$libresoc.v:160245$8463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:160449$8463_Y + connect \Y $not$libresoc.v:160245$8463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:160448$8462 + cell $or $or$libresoc.v:160244$8462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298084,47 +297918,47 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:160448$8462_Y + connect \Y $or$libresoc.v:160244$8462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:160441$8454 + cell $pos $pos$libresoc.v:160237$8454 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160441$8453_Y - connect \Y $pos$libresoc.v:160441$8454_Y + connect \A $extend$libresoc.v:160237$8453_Y + connect \Y $pos$libresoc.v:160237$8454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:160442$8456 + cell $pos $pos$libresoc.v:160238$8456 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160442$8455_Y - connect \Y $pos$libresoc.v:160442$8456_Y + connect \A $extend$libresoc.v:160238$8455_Y + connect \Y $pos$libresoc.v:160238$8456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:160445$8459 + cell $reduce_or $reduce_or$libresoc.v:160241$8459 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:160445$8459_Y + connect \Y $reduce_or$libresoc.v:160241$8459_Y end - attribute \src "libresoc.v:160121.7-160121.20" - process $proc$libresoc.v:160121$8468 + attribute \src "libresoc.v:159917.7-159917.20" + process $proc$libresoc.v:159917$8468 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160450.3-160461.6" - process $proc$libresoc.v:160450$8464 + attribute \src "libresoc.v:160246.3-160257.6" + process $proc$libresoc.v:160246$8464 assign { } { } assign $0\o$23[64:0]$8465 $1\o$23[64:0]$8466 - attribute \src "libresoc.v:160451.5-160451.29" + attribute \src "libresoc.v:160247.5-160247.29" switch \initial - attribute \src "libresoc.v:160451.9-160451.17" + attribute \src "libresoc.v:160247.9-160247.17" case 1'1 case end @@ -298142,13 +297976,13 @@ module \output$54 sync always update \o$23 $0\o$23[64:0]$8465 end - attribute \src "libresoc.v:160462.3-160473.6" - process $proc$libresoc.v:160462$8467 + attribute \src "libresoc.v:160258.3-160269.6" + process $proc$libresoc.v:160258$8467 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:160463.5-160463.29" + attribute \src "libresoc.v:160259.5-160259.29" switch \initial - attribute \src "libresoc.v:160463.9-160463.17" + attribute \src "libresoc.v:160259.9-160259.17" case 1'1 case end @@ -298166,16 +298000,16 @@ module \output$54 sync always update \cr0 $0\cr0[3:0] end - connect \$25 $not$libresoc.v:160440$8452_Y - connect \$24 $pos$libresoc.v:160441$8454_Y - connect \$28 $pos$libresoc.v:160442$8456_Y - connect \$30 $eq$libresoc.v:160443$8457_Y - connect \$32 $eq$libresoc.v:160444$8458_Y - connect \$34 $reduce_or$libresoc.v:160445$8459_Y - connect \$36 $not$libresoc.v:160446$8460_Y - connect \$38 $and$libresoc.v:160447$8461_Y - connect \$40 $or$libresoc.v:160448$8462_Y - connect \$42 $not$libresoc.v:160449$8463_Y + connect \$25 $not$libresoc.v:160236$8452_Y + connect \$24 $pos$libresoc.v:160237$8454_Y + connect \$28 $pos$libresoc.v:160238$8456_Y + connect \$30 $eq$libresoc.v:160239$8457_Y + connect \$32 $eq$libresoc.v:160240$8458_Y + connect \$34 $reduce_or$libresoc.v:160241$8459_Y + connect \$36 $not$libresoc.v:160242$8460_Y + connect \$38 $and$libresoc.v:160243$8461_Y + connect \$40 $or$libresoc.v:160244$8462_Y + connect \$42 $not$libresoc.v:160245$8463_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \logical_op__write_cr0 @@ -298190,71 +298024,71 @@ module \output$54 connect \is_cmp \$30 connect \target \o$23 [63:0] end -attribute \src "libresoc.v:160491.1-160941.10" +attribute \src "libresoc.v:160287.1-160737.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" attribute \generator "nMigen" module \output$83 - attribute \src "libresoc.v:160862.3-160873.6" + attribute \src "libresoc.v:160658.3-160669.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:160492.7-160492.20" + attribute \src "libresoc.v:160288.7-160288.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160874.3-160885.6" + attribute \src "libresoc.v:160670.3-160681.6" wire width 65 $0\o$27[64:0]$8487 - attribute \src "libresoc.v:160850.3-160861.6" + attribute \src "libresoc.v:160646.3-160657.6" wire $0\so[0:0] - attribute \src "libresoc.v:160906.3-160915.6" + attribute \src "libresoc.v:160702.3-160711.6" wire width 2 $0\xer_ov$23[1:0]$8494 - attribute \src "libresoc.v:160916.3-160925.6" + attribute \src "libresoc.v:160712.3-160721.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:160886.3-160895.6" + attribute \src "libresoc.v:160682.3-160691.6" wire $0\xer_so$24[0:0]$8490 - attribute \src "libresoc.v:160896.3-160905.6" + attribute \src "libresoc.v:160692.3-160701.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:160862.3-160873.6" + attribute \src "libresoc.v:160658.3-160669.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:160874.3-160885.6" + attribute \src "libresoc.v:160670.3-160681.6" wire width 65 $1\o$27[64:0]$8488 - attribute \src "libresoc.v:160850.3-160861.6" + attribute \src "libresoc.v:160646.3-160657.6" wire $1\so[0:0] - attribute \src "libresoc.v:160906.3-160915.6" + attribute \src "libresoc.v:160702.3-160711.6" wire width 2 $1\xer_ov$23[1:0]$8495 - attribute \src "libresoc.v:160916.3-160925.6" + attribute \src "libresoc.v:160712.3-160721.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:160886.3-160895.6" + attribute \src "libresoc.v:160682.3-160691.6" wire $1\xer_so$24[0:0]$8491 - attribute \src "libresoc.v:160896.3-160905.6" + attribute \src "libresoc.v:160692.3-160701.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:160837.18-160837.136" - wire $and$libresoc.v:160837$8469_Y - attribute \src "libresoc.v:160845.18-160845.112" - wire $and$libresoc.v:160845$8479_Y - attribute \src "libresoc.v:160848.18-160848.133" - wire $and$libresoc.v:160848$8482_Y - attribute \src "libresoc.v:160841.18-160841.127" - wire $eq$libresoc.v:160841$8475_Y - attribute \src "libresoc.v:160842.18-160842.127" - wire $eq$libresoc.v:160842$8476_Y - attribute \src "libresoc.v:160839.18-160839.103" - wire width 65 $extend$libresoc.v:160839$8471_Y - attribute \src "libresoc.v:160840.18-160840.101" - wire width 65 $extend$libresoc.v:160840$8473_Y - attribute \src "libresoc.v:160838.18-160838.100" - wire width 64 $not$libresoc.v:160838$8470_Y - attribute \src "libresoc.v:160844.18-160844.107" - wire $not$libresoc.v:160844$8478_Y - attribute \src "libresoc.v:160847.18-160847.107" - wire $not$libresoc.v:160847$8481_Y - attribute \src "libresoc.v:160846.18-160846.115" - wire $or$libresoc.v:160846$8480_Y - attribute \src "libresoc.v:160849.18-160849.112" - wire $or$libresoc.v:160849$8483_Y - attribute \src "libresoc.v:160839.18-160839.103" - wire width 65 $pos$libresoc.v:160839$8472_Y - attribute \src "libresoc.v:160840.18-160840.101" - wire width 65 $pos$libresoc.v:160840$8474_Y - attribute \src "libresoc.v:160843.18-160843.105" - wire $reduce_or$libresoc.v:160843$8477_Y + attribute \src "libresoc.v:160633.18-160633.136" + wire $and$libresoc.v:160633$8469_Y + attribute \src "libresoc.v:160641.18-160641.112" + wire $and$libresoc.v:160641$8479_Y + attribute \src "libresoc.v:160644.18-160644.133" + wire $and$libresoc.v:160644$8482_Y + attribute \src "libresoc.v:160637.18-160637.127" + wire $eq$libresoc.v:160637$8475_Y + attribute \src "libresoc.v:160638.18-160638.127" + wire $eq$libresoc.v:160638$8476_Y + attribute \src "libresoc.v:160635.18-160635.103" + wire width 65 $extend$libresoc.v:160635$8471_Y + attribute \src "libresoc.v:160636.18-160636.101" + wire width 65 $extend$libresoc.v:160636$8473_Y + attribute \src "libresoc.v:160634.18-160634.100" + wire width 64 $not$libresoc.v:160634$8470_Y + attribute \src "libresoc.v:160640.18-160640.107" + wire $not$libresoc.v:160640$8478_Y + attribute \src "libresoc.v:160643.18-160643.107" + wire $not$libresoc.v:160643$8481_Y + attribute \src "libresoc.v:160642.18-160642.115" + wire $or$libresoc.v:160642$8480_Y + attribute \src "libresoc.v:160645.18-160645.112" + wire $or$libresoc.v:160645$8483_Y + attribute \src "libresoc.v:160635.18-160635.103" + wire width 65 $pos$libresoc.v:160635$8472_Y + attribute \src "libresoc.v:160636.18-160636.101" + wire width 65 $pos$libresoc.v:160636$8474_Y + attribute \src "libresoc.v:160639.18-160639.105" + wire $reduce_or$libresoc.v:160639$8477_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -298289,7 +298123,7 @@ module \output$83 wire width 4 output 45 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 46 \cr_a_ok - attribute \src "libresoc.v:160492.7-160492.15" + attribute \src "libresoc.v:160288.7-160288.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -298598,7 +298432,7 @@ module \output$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 50 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:160837$8469 + cell $and $and$libresoc.v:160633$8469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298606,10 +298440,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:160837$8469_Y + connect \Y $and$libresoc.v:160633$8469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:160845$8479 + cell $and $and$libresoc.v:160641$8479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298617,10 +298451,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$40 - connect \Y $and$libresoc.v:160845$8479_Y + connect \Y $and$libresoc.v:160641$8479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:160848$8482 + cell $and $and$libresoc.v:160644$8482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298628,10 +298462,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:160848$8482_Y + connect \Y $and$libresoc.v:160644$8482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:160841$8475 + cell $eq $eq$libresoc.v:160637$8475 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -298639,10 +298473,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:160841$8475_Y + connect \Y $eq$libresoc.v:160637$8475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:160842$8476 + cell $eq $eq$libresoc.v:160638$8476 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -298650,50 +298484,50 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:160842$8476_Y + connect \Y $eq$libresoc.v:160638$8476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:160839$8471 + cell $pos $extend$libresoc.v:160635$8471 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$29 - connect \Y $extend$libresoc.v:160839$8471_Y + connect \Y $extend$libresoc.v:160635$8471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:160840$8473 + cell $pos $extend$libresoc.v:160636$8473 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:160840$8473_Y + connect \Y $extend$libresoc.v:160636$8473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:160838$8470 + cell $not $not$libresoc.v:160634$8470 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:160838$8470_Y + connect \Y $not$libresoc.v:160634$8470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:160844$8478 + cell $not $not$libresoc.v:160640$8478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:160844$8478_Y + connect \Y $not$libresoc.v:160640$8478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:160847$8481 + cell $not $not$libresoc.v:160643$8481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:160847$8481_Y + connect \Y $not$libresoc.v:160643$8481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:160846$8480 + cell $or $or$libresoc.v:160642$8480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298701,10 +298535,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:160846$8480_Y + connect \Y $or$libresoc.v:160642$8480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:160849$8483 + cell $or $or$libresoc.v:160645$8483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298712,47 +298546,47 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:160849$8483_Y + connect \Y $or$libresoc.v:160645$8483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:160839$8472 + cell $pos $pos$libresoc.v:160635$8472 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160839$8471_Y - connect \Y $pos$libresoc.v:160839$8472_Y + connect \A $extend$libresoc.v:160635$8471_Y + connect \Y $pos$libresoc.v:160635$8472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:160840$8474 + cell $pos $pos$libresoc.v:160636$8474 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160840$8473_Y - connect \Y $pos$libresoc.v:160840$8474_Y + connect \A $extend$libresoc.v:160636$8473_Y + connect \Y $pos$libresoc.v:160636$8474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:160843$8477 + cell $reduce_or $reduce_or$libresoc.v:160639$8477 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:160843$8477_Y + connect \Y $reduce_or$libresoc.v:160639$8477_Y end - attribute \src "libresoc.v:160492.7-160492.20" - process $proc$libresoc.v:160492$8497 + attribute \src "libresoc.v:160288.7-160288.20" + process $proc$libresoc.v:160288$8497 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160850.3-160861.6" - process $proc$libresoc.v:160850$8484 + attribute \src "libresoc.v:160646.3-160657.6" + process $proc$libresoc.v:160646$8484 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:160851.5-160851.29" + attribute \src "libresoc.v:160647.5-160647.29" switch \initial - attribute \src "libresoc.v:160851.9-160851.17" + attribute \src "libresoc.v:160647.9-160647.17" case 1'1 case end @@ -298770,13 +298604,13 @@ module \output$83 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:160862.3-160873.6" - process $proc$libresoc.v:160862$8485 + attribute \src "libresoc.v:160658.3-160669.6" + process $proc$libresoc.v:160658$8485 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:160863.5-160863.29" + attribute \src "libresoc.v:160659.5-160659.29" switch \initial - attribute \src "libresoc.v:160863.9-160863.17" + attribute \src "libresoc.v:160659.9-160659.17" case 1'1 case end @@ -298794,13 +298628,13 @@ module \output$83 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:160874.3-160885.6" - process $proc$libresoc.v:160874$8486 + attribute \src "libresoc.v:160670.3-160681.6" + process $proc$libresoc.v:160670$8486 assign { } { } assign $0\o$27[64:0]$8487 $1\o$27[64:0]$8488 - attribute \src "libresoc.v:160875.5-160875.29" + attribute \src "libresoc.v:160671.5-160671.29" switch \initial - attribute \src "libresoc.v:160875.9-160875.17" + attribute \src "libresoc.v:160671.9-160671.17" case 1'1 case end @@ -298818,14 +298652,14 @@ module \output$83 sync always update \o$27 $0\o$27[64:0]$8487 end - attribute \src "libresoc.v:160886.3-160895.6" - process $proc$libresoc.v:160886$8489 + attribute \src "libresoc.v:160682.3-160691.6" + process $proc$libresoc.v:160682$8489 assign { } { } assign { } { } assign $0\xer_so$24[0:0]$8490 $1\xer_so$24[0:0]$8491 - attribute \src "libresoc.v:160887.5-160887.29" + attribute \src "libresoc.v:160683.5-160683.29" switch \initial - attribute \src "libresoc.v:160887.9-160887.17" + attribute \src "libresoc.v:160683.9-160683.17" case 1'1 case end @@ -298841,14 +298675,14 @@ module \output$83 sync always update \xer_so$24 $0\xer_so$24[0:0]$8490 end - attribute \src "libresoc.v:160896.3-160905.6" - process $proc$libresoc.v:160896$8492 + attribute \src "libresoc.v:160692.3-160701.6" + process $proc$libresoc.v:160692$8492 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:160897.5-160897.29" + attribute \src "libresoc.v:160693.5-160693.29" switch \initial - attribute \src "libresoc.v:160897.9-160897.17" + attribute \src "libresoc.v:160693.9-160693.17" case 1'1 case end @@ -298864,14 +298698,14 @@ module \output$83 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:160906.3-160915.6" - process $proc$libresoc.v:160906$8493 + attribute \src "libresoc.v:160702.3-160711.6" + process $proc$libresoc.v:160702$8493 assign { } { } assign { } { } assign $0\xer_ov$23[1:0]$8494 $1\xer_ov$23[1:0]$8495 - attribute \src "libresoc.v:160907.5-160907.29" + attribute \src "libresoc.v:160703.5-160703.29" switch \initial - attribute \src "libresoc.v:160907.9-160907.17" + attribute \src "libresoc.v:160703.9-160703.17" case 1'1 case end @@ -298887,14 +298721,14 @@ module \output$83 sync always update \xer_ov$23 $0\xer_ov$23[1:0]$8494 end - attribute \src "libresoc.v:160916.3-160925.6" - process $proc$libresoc.v:160916$8496 + attribute \src "libresoc.v:160712.3-160721.6" + process $proc$libresoc.v:160712$8496 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:160917.5-160917.29" + attribute \src "libresoc.v:160713.5-160713.29" switch \initial - attribute \src "libresoc.v:160917.9-160917.17" + attribute \src "libresoc.v:160713.9-160713.17" case 1'1 case end @@ -298910,19 +298744,19 @@ module \output$83 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$25 $and$libresoc.v:160837$8469_Y - connect \$29 $not$libresoc.v:160838$8470_Y - connect \$28 $pos$libresoc.v:160839$8472_Y - connect \$32 $pos$libresoc.v:160840$8474_Y - connect \$34 $eq$libresoc.v:160841$8475_Y - connect \$36 $eq$libresoc.v:160842$8476_Y - connect \$38 $reduce_or$libresoc.v:160843$8477_Y - connect \$40 $not$libresoc.v:160844$8478_Y - connect \$42 $and$libresoc.v:160845$8479_Y - connect \$44 $or$libresoc.v:160846$8480_Y - connect \$46 $not$libresoc.v:160847$8481_Y - connect \$49 $and$libresoc.v:160848$8482_Y - connect \$51 $or$libresoc.v:160849$8483_Y + connect \$25 $and$libresoc.v:160633$8469_Y + connect \$29 $not$libresoc.v:160634$8470_Y + connect \$28 $pos$libresoc.v:160635$8472_Y + connect \$32 $pos$libresoc.v:160636$8474_Y + connect \$34 $eq$libresoc.v:160637$8475_Y + connect \$36 $eq$libresoc.v:160638$8476_Y + connect \$38 $reduce_or$libresoc.v:160639$8477_Y + connect \$40 $not$libresoc.v:160640$8478_Y + connect \$42 $and$libresoc.v:160641$8479_Y + connect \$44 $or$libresoc.v:160642$8480_Y + connect \$46 $not$libresoc.v:160643$8481_Y + connect \$49 $and$libresoc.v:160644$8482_Y + connect \$51 $or$libresoc.v:160645$8483_Y connect \oe$48 \$49 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -298939,93 +298773,93 @@ module \output$83 connect \target \o$27 [63:0] connect \oe \$25 end -attribute \src "libresoc.v:160945.1-161427.10" +attribute \src "libresoc.v:160741.1-161223.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" attribute \generator "nMigen" module \output_stage - attribute \src "libresoc.v:160946.7-160946.20" + attribute \src "libresoc.v:160742.7-160742.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161308.3-161379.6" + attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:161380.3-161413.6" + attribute \src "libresoc.v:161176.3-161209.6" wire $0\ov[0:0] - attribute \src "libresoc.v:161308.3-161379.6" + attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:161380.3-161413.6" + attribute \src "libresoc.v:161176.3-161209.6" wire $1\ov[0:0] - attribute \src "libresoc.v:161308.3-161379.6" + attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:161380.3-161413.6" + attribute \src "libresoc.v:161176.3-161209.6" wire $2\ov[0:0] - attribute \src "libresoc.v:161308.3-161379.6" + attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:161380.3-161413.6" + attribute \src "libresoc.v:161176.3-161209.6" wire $3\ov[0:0] - attribute \src "libresoc.v:161308.3-161379.6" + attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:161308.3-161379.6" + attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $5\o[63:0] - attribute \src "libresoc.v:161308.3-161379.6" + attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $6\o[63:0] - attribute \src "libresoc.v:161308.3-161379.6" + attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $7\o[63:0] - attribute \src "libresoc.v:161308.3-161379.6" + attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $8\o[63:0] - attribute \src "libresoc.v:161299.18-161299.122" - wire $and$libresoc.v:161299$8511_Y - attribute \src "libresoc.v:161291.18-161291.109" - wire width 65 $extend$libresoc.v:161291$8499_Y - attribute \src "libresoc.v:161292.18-161292.100" - wire width 65 $extend$libresoc.v:161292$8501_Y - attribute \src "libresoc.v:161294.18-161294.113" - wire width 65 $extend$libresoc.v:161294$8504_Y - attribute \src "libresoc.v:161295.18-161295.104" - wire width 65 $extend$libresoc.v:161295$8506_Y - attribute \src "libresoc.v:161303.18-161303.114" - wire width 64 $extend$libresoc.v:161303$8515_Y - attribute \src "libresoc.v:161304.18-161304.114" - wire width 64 $extend$libresoc.v:161304$8517_Y - attribute \src "libresoc.v:161305.18-161305.114" - wire width 64 $extend$libresoc.v:161305$8519_Y - attribute \src "libresoc.v:161306.18-161306.114" - wire width 64 $extend$libresoc.v:161306$8521_Y - attribute \src "libresoc.v:161307.18-161307.115" - wire width 64 $extend$libresoc.v:161307$8523_Y - attribute \src "libresoc.v:161300.18-161300.128" - wire $ne$libresoc.v:161300$8512_Y - attribute \src "libresoc.v:161291.18-161291.109" - wire width 65 $neg$libresoc.v:161291$8500_Y - attribute \src "libresoc.v:161294.18-161294.113" - wire width 65 $neg$libresoc.v:161294$8505_Y - attribute \src "libresoc.v:161297.18-161297.116" - wire $not$libresoc.v:161297$8509_Y - attribute \src "libresoc.v:161302.18-161302.99" - wire $not$libresoc.v:161302$8514_Y - attribute \src "libresoc.v:161292.18-161292.100" - wire width 65 $pos$libresoc.v:161292$8502_Y - attribute \src "libresoc.v:161295.18-161295.104" - wire width 65 $pos$libresoc.v:161295$8507_Y - attribute \src "libresoc.v:161301.18-161301.118" - wire width 64 signed $pos$libresoc.v:161301$8513_Y - attribute \src "libresoc.v:161303.18-161303.114" - wire width 64 $pos$libresoc.v:161303$8516_Y - attribute \src "libresoc.v:161304.18-161304.114" - wire width 64 $pos$libresoc.v:161304$8518_Y - attribute \src "libresoc.v:161305.18-161305.114" - wire width 64 $pos$libresoc.v:161305$8520_Y - attribute \src "libresoc.v:161306.18-161306.114" - wire width 64 $pos$libresoc.v:161306$8522_Y - attribute \src "libresoc.v:161307.18-161307.115" - wire width 64 $pos$libresoc.v:161307$8524_Y - attribute \src "libresoc.v:161293.18-161293.121" - wire width 65 $ternary$libresoc.v:161293$8503_Y - attribute \src "libresoc.v:161296.18-161296.122" - wire width 65 $ternary$libresoc.v:161296$8508_Y - attribute \src "libresoc.v:161290.18-161290.120" - wire $xor$libresoc.v:161290$8498_Y - attribute \src "libresoc.v:161298.18-161298.127" - wire $xor$libresoc.v:161298$8510_Y + attribute \src "libresoc.v:161095.18-161095.122" + wire $and$libresoc.v:161095$8511_Y + attribute \src "libresoc.v:161087.18-161087.109" + wire width 65 $extend$libresoc.v:161087$8499_Y + attribute \src "libresoc.v:161088.18-161088.100" + wire width 65 $extend$libresoc.v:161088$8501_Y + attribute \src "libresoc.v:161090.18-161090.113" + wire width 65 $extend$libresoc.v:161090$8504_Y + attribute \src "libresoc.v:161091.18-161091.104" + wire width 65 $extend$libresoc.v:161091$8506_Y + attribute \src "libresoc.v:161099.18-161099.114" + wire width 64 $extend$libresoc.v:161099$8515_Y + attribute \src "libresoc.v:161100.18-161100.114" + wire width 64 $extend$libresoc.v:161100$8517_Y + attribute \src "libresoc.v:161101.18-161101.114" + wire width 64 $extend$libresoc.v:161101$8519_Y + attribute \src "libresoc.v:161102.18-161102.114" + wire width 64 $extend$libresoc.v:161102$8521_Y + attribute \src "libresoc.v:161103.18-161103.115" + wire width 64 $extend$libresoc.v:161103$8523_Y + attribute \src "libresoc.v:161096.18-161096.128" + wire $ne$libresoc.v:161096$8512_Y + attribute \src "libresoc.v:161087.18-161087.109" + wire width 65 $neg$libresoc.v:161087$8500_Y + attribute \src "libresoc.v:161090.18-161090.113" + wire width 65 $neg$libresoc.v:161090$8505_Y + attribute \src "libresoc.v:161093.18-161093.116" + wire $not$libresoc.v:161093$8509_Y + attribute \src "libresoc.v:161098.18-161098.99" + wire $not$libresoc.v:161098$8514_Y + attribute \src "libresoc.v:161088.18-161088.100" + wire width 65 $pos$libresoc.v:161088$8502_Y + attribute \src "libresoc.v:161091.18-161091.104" + wire width 65 $pos$libresoc.v:161091$8507_Y + attribute \src "libresoc.v:161097.18-161097.118" + wire width 64 signed $pos$libresoc.v:161097$8513_Y + attribute \src "libresoc.v:161099.18-161099.114" + wire width 64 $pos$libresoc.v:161099$8516_Y + attribute \src "libresoc.v:161100.18-161100.114" + wire width 64 $pos$libresoc.v:161100$8518_Y + attribute \src "libresoc.v:161101.18-161101.114" + wire width 64 $pos$libresoc.v:161101$8520_Y + attribute \src "libresoc.v:161102.18-161102.114" + wire width 64 $pos$libresoc.v:161102$8522_Y + attribute \src "libresoc.v:161103.18-161103.115" + wire width 64 $pos$libresoc.v:161103$8524_Y + attribute \src "libresoc.v:161089.18-161089.121" + wire width 65 $ternary$libresoc.v:161089$8503_Y + attribute \src "libresoc.v:161092.18-161092.122" + wire width 65 $ternary$libresoc.v:161092$8508_Y + attribute \src "libresoc.v:161086.18-161086.120" + wire $xor$libresoc.v:161086$8498_Y + attribute \src "libresoc.v:161094.18-161094.127" + wire $xor$libresoc.v:161094$8510_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" @@ -299074,7 +298908,7 @@ module \output_stage wire input 21 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 20 \divisor_neg - attribute \src "libresoc.v:160946.7-160946.15" + attribute \src "libresoc.v:160742.7-160742.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -299371,7 +299205,7 @@ module \output_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 50 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $and$libresoc.v:161299$8511 + cell $and $and$libresoc.v:161095$8511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299379,82 +299213,82 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \logical_op__is_signed connect \B \$38 - connect \Y $and$libresoc.v:161299$8511_Y + connect \Y $and$libresoc.v:161095$8511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $pos $extend$libresoc.v:161291$8499 + cell $pos $extend$libresoc.v:161087$8499 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:161291$8499_Y + connect \Y $extend$libresoc.v:161087$8499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $extend$libresoc.v:161292$8501 + cell $pos $extend$libresoc.v:161088$8501 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:161292$8501_Y + connect \Y $extend$libresoc.v:161088$8501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $pos $extend$libresoc.v:161294$8504 + cell $pos $extend$libresoc.v:161090$8504 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:161294$8504_Y + connect \Y $extend$libresoc.v:161090$8504_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:161295$8506 + cell $pos $extend$libresoc.v:161091$8506 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:161295$8506_Y + connect \Y $extend$libresoc.v:161091$8506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $extend$libresoc.v:161303$8515 + cell $pos $extend$libresoc.v:161099$8515 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:161303$8515_Y + connect \Y $extend$libresoc.v:161099$8515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $extend$libresoc.v:161304$8517 + cell $pos $extend$libresoc.v:161100$8517 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:161304$8517_Y + connect \Y $extend$libresoc.v:161100$8517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $extend$libresoc.v:161305$8519 + cell $pos $extend$libresoc.v:161101$8519 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:161305$8519_Y + connect \Y $extend$libresoc.v:161101$8519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $extend$libresoc.v:161306$8521 + cell $pos $extend$libresoc.v:161102$8521 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:161306$8521_Y + connect \Y $extend$libresoc.v:161102$8521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $extend$libresoc.v:161307$8523 + cell $pos $extend$libresoc.v:161103$8523 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \remainder_64 [31:0] - connect \Y $extend$libresoc.v:161307$8523_Y + connect \Y $extend$libresoc.v:161103$8523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $ne$libresoc.v:161300$8512 + cell $ne $ne$libresoc.v:161096$8512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299462,122 +299296,122 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [32] connect \B \quotient_65 [31] - connect \Y $ne$libresoc.v:161300$8512_Y + connect \Y $ne$libresoc.v:161096$8512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $neg$libresoc.v:161291$8500 + cell $neg $neg$libresoc.v:161087$8500 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:161291$8499_Y - connect \Y $neg$libresoc.v:161291$8500_Y + connect \A $extend$libresoc.v:161087$8499_Y + connect \Y $neg$libresoc.v:161087$8500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $neg$libresoc.v:161294$8505 + cell $neg $neg$libresoc.v:161090$8505 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:161294$8504_Y - connect \Y $neg$libresoc.v:161294$8505_Y + connect \A $extend$libresoc.v:161090$8504_Y + connect \Y $neg$libresoc.v:161090$8505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $not$libresoc.v:161297$8509 + cell $not $not$libresoc.v:161093$8509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__is_32bit - connect \Y $not$libresoc.v:161297$8509_Y + connect \Y $not$libresoc.v:161093$8509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $not $not$libresoc.v:161302$8514 + cell $not $not$libresoc.v:161098$8514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ov - connect \Y $not$libresoc.v:161302$8514_Y + connect \Y $not$libresoc.v:161098$8514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $pos$libresoc.v:161292$8502 + cell $pos $pos$libresoc.v:161088$8502 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:161292$8501_Y - connect \Y $pos$libresoc.v:161292$8502_Y + connect \A $extend$libresoc.v:161088$8501_Y + connect \Y $pos$libresoc.v:161088$8502_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:161295$8507 + cell $pos $pos$libresoc.v:161091$8507 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:161295$8506_Y - connect \Y $pos$libresoc.v:161295$8507_Y + connect \A $extend$libresoc.v:161091$8506_Y + connect \Y $pos$libresoc.v:161091$8507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - cell $pos $pos$libresoc.v:161301$8513 + cell $pos $pos$libresoc.v:161097$8513 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } - connect \Y $pos$libresoc.v:161301$8513_Y + connect \Y $pos$libresoc.v:161097$8513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $pos$libresoc.v:161303$8516 + cell $pos $pos$libresoc.v:161099$8516 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:161303$8515_Y - connect \Y $pos$libresoc.v:161303$8516_Y + connect \A $extend$libresoc.v:161099$8515_Y + connect \Y $pos$libresoc.v:161099$8516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $pos$libresoc.v:161304$8518 + cell $pos $pos$libresoc.v:161100$8518 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:161304$8517_Y - connect \Y $pos$libresoc.v:161304$8518_Y + connect \A $extend$libresoc.v:161100$8517_Y + connect \Y $pos$libresoc.v:161100$8518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $pos$libresoc.v:161305$8520 + cell $pos $pos$libresoc.v:161101$8520 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:161305$8519_Y - connect \Y $pos$libresoc.v:161305$8520_Y + connect \A $extend$libresoc.v:161101$8519_Y + connect \Y $pos$libresoc.v:161101$8520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $pos$libresoc.v:161306$8522 + cell $pos $pos$libresoc.v:161102$8522 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:161306$8521_Y - connect \Y $pos$libresoc.v:161306$8522_Y + connect \A $extend$libresoc.v:161102$8521_Y + connect \Y $pos$libresoc.v:161102$8522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $pos$libresoc.v:161307$8524 + cell $pos $pos$libresoc.v:161103$8524 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:161307$8523_Y - connect \Y $pos$libresoc.v:161307$8524_Y + connect \A $extend$libresoc.v:161103$8523_Y + connect \Y $pos$libresoc.v:161103$8524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $ternary$libresoc.v:161293$8503 + cell $mux $ternary$libresoc.v:161089$8503 parameter \WIDTH 65 connect \A \$25 connect \B \$23 connect \S \quotient_neg - connect \Y $ternary$libresoc.v:161293$8503_Y + connect \Y $ternary$libresoc.v:161089$8503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $ternary$libresoc.v:161296$8508 + cell $mux $ternary$libresoc.v:161092$8508 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \remainder_neg - connect \Y $ternary$libresoc.v:161296$8508_Y + connect \Y $ternary$libresoc.v:161092$8508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $xor$libresoc.v:161290$8498 + cell $xor $xor$libresoc.v:161086$8498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299585,10 +299419,10 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \dividend_neg connect \B \divisor_neg - connect \Y $xor$libresoc.v:161290$8498_Y + connect \Y $xor$libresoc.v:161086$8498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $xor$libresoc.v:161298$8510 + cell $xor $xor$libresoc.v:161094$8510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299596,24 +299430,24 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [64] connect \B \quotient_65 [63] - connect \Y $xor$libresoc.v:161298$8510_Y + connect \Y $xor$libresoc.v:161094$8510_Y end - attribute \src "libresoc.v:160946.7-160946.20" - process $proc$libresoc.v:160946$8527 + attribute \src "libresoc.v:160742.7-160742.20" + process $proc$libresoc.v:160742$8527 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:161308.3-161379.6" - process $proc$libresoc.v:161308$8525 + attribute \src "libresoc.v:161104.3-161175.6" + process $proc$libresoc.v:161104$8525 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:161309.5-161309.29" + attribute \src "libresoc.v:161105.5-161105.29" switch \initial - attribute \src "libresoc.v:161309.9-161309.17" + attribute \src "libresoc.v:161105.9-161105.17" case 1'1 case end @@ -299712,13 +299546,13 @@ module \output_stage sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:161380.3-161413.6" - process $proc$libresoc.v:161380$8526 + attribute \src "libresoc.v:161176.3-161209.6" + process $proc$libresoc.v:161176$8526 assign { } { } assign $0\ov[0:0] $1\ov[0:0] - attribute \src "libresoc.v:161381.5-161381.29" + attribute \src "libresoc.v:161177.5-161177.29" switch \initial - attribute \src "libresoc.v:161381.9-161381.17" + attribute \src "libresoc.v:161177.9-161177.17" case 1'1 case end @@ -299764,24 +299598,24 @@ module \output_stage sync always update \ov $0\ov[0:0] end - connect \$21 $xor$libresoc.v:161290$8498_Y - connect \$23 $neg$libresoc.v:161291$8500_Y - connect \$25 $pos$libresoc.v:161292$8502_Y - connect \$27 $ternary$libresoc.v:161293$8503_Y - connect \$30 $neg$libresoc.v:161294$8505_Y - connect \$32 $pos$libresoc.v:161295$8507_Y - connect \$34 $ternary$libresoc.v:161296$8508_Y - connect \$36 $not$libresoc.v:161297$8509_Y - connect \$38 $xor$libresoc.v:161298$8510_Y - connect \$40 $and$libresoc.v:161299$8511_Y - connect \$42 $ne$libresoc.v:161300$8512_Y - connect \$44 $pos$libresoc.v:161301$8513_Y - connect \$46 $not$libresoc.v:161302$8514_Y - connect \$48 $pos$libresoc.v:161303$8516_Y - connect \$50 $pos$libresoc.v:161304$8518_Y - connect \$52 $pos$libresoc.v:161305$8520_Y - connect \$54 $pos$libresoc.v:161306$8522_Y - connect \$56 $pos$libresoc.v:161307$8524_Y + connect \$21 $xor$libresoc.v:161086$8498_Y + connect \$23 $neg$libresoc.v:161087$8500_Y + connect \$25 $pos$libresoc.v:161088$8502_Y + connect \$27 $ternary$libresoc.v:161089$8503_Y + connect \$30 $neg$libresoc.v:161090$8505_Y + connect \$32 $pos$libresoc.v:161091$8507_Y + connect \$34 $ternary$libresoc.v:161092$8508_Y + connect \$36 $not$libresoc.v:161093$8509_Y + connect \$38 $xor$libresoc.v:161094$8510_Y + connect \$40 $and$libresoc.v:161095$8511_Y + connect \$42 $ne$libresoc.v:161096$8512_Y + connect \$44 $pos$libresoc.v:161097$8513_Y + connect \$46 $not$libresoc.v:161098$8514_Y + connect \$48 $pos$libresoc.v:161099$8516_Y + connect \$50 $pos$libresoc.v:161100$8518_Y + connect \$52 $pos$libresoc.v:161101$8520_Y + connect \$54 $pos$libresoc.v:161102$8522_Y + connect \$56 $pos$libresoc.v:161103$8524_Y connect \$29 \$34 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -299796,13 +299630,13 @@ module \output_stage connect \remainder_neg \dividend_neg connect \quotient_neg \$21 end -attribute \src "libresoc.v:161431.1-161442.10" +attribute \src "libresoc.v:161227.1-161238.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" attribute \generator "nMigen" module \p - attribute \src "libresoc.v:161440.17-161440.111" - wire $and$libresoc.v:161440$8528_Y + attribute \src "libresoc.v:161236.17-161236.111" + wire $and$libresoc.v:161236$8528_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -299812,7 +299646,7 @@ module \p attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161440$8528 + cell $and $and$libresoc.v:161236$8528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299820,18 +299654,18 @@ module \p parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161440$8528_Y + connect \Y $and$libresoc.v:161236$8528_Y end - connect \$1 $and$libresoc.v:161440$8528_Y + connect \$1 $and$libresoc.v:161236$8528_Y connect \trigger \$1 end -attribute \src "libresoc.v:161446.1-161457.10" +attribute \src "libresoc.v:161242.1-161253.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" attribute \generator "nMigen" module \p$1 - attribute \src "libresoc.v:161455.17-161455.111" - wire $and$libresoc.v:161455$8529_Y + attribute \src "libresoc.v:161251.17-161251.111" + wire $and$libresoc.v:161251$8529_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -299841,7 +299675,7 @@ module \p$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161455$8529 + cell $and $and$libresoc.v:161251$8529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299849,18 +299683,18 @@ module \p$1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161455$8529_Y + connect \Y $and$libresoc.v:161251$8529_Y end - connect \$1 $and$libresoc.v:161455$8529_Y + connect \$1 $and$libresoc.v:161251$8529_Y connect \trigger \$1 end -attribute \src "libresoc.v:161461.1-161472.10" +attribute \src "libresoc.v:161257.1-161268.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" attribute \generator "nMigen" module \p$108 - attribute \src "libresoc.v:161470.17-161470.111" - wire $and$libresoc.v:161470$8530_Y + attribute \src "libresoc.v:161266.17-161266.111" + wire $and$libresoc.v:161266$8530_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -299870,7 +299704,7 @@ module \p$108 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161470$8530 + cell $and $and$libresoc.v:161266$8530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299878,18 +299712,18 @@ module \p$108 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161470$8530_Y + connect \Y $and$libresoc.v:161266$8530_Y end - connect \$1 $and$libresoc.v:161470$8530_Y + connect \$1 $and$libresoc.v:161266$8530_Y connect \trigger \$1 end -attribute \src "libresoc.v:161476.1-161487.10" +attribute \src "libresoc.v:161272.1-161283.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" attribute \generator "nMigen" module \p$111 - attribute \src "libresoc.v:161485.17-161485.111" - wire $and$libresoc.v:161485$8531_Y + attribute \src "libresoc.v:161281.17-161281.111" + wire $and$libresoc.v:161281$8531_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -299899,7 +299733,7 @@ module \p$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161485$8531 + cell $and $and$libresoc.v:161281$8531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299907,18 +299741,18 @@ module \p$111 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161485$8531_Y + connect \Y $and$libresoc.v:161281$8531_Y end - connect \$1 $and$libresoc.v:161485$8531_Y + connect \$1 $and$libresoc.v:161281$8531_Y connect \trigger \$1 end -attribute \src "libresoc.v:161491.1-161502.10" +attribute \src "libresoc.v:161287.1-161298.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" attribute \generator "nMigen" module \p$116 - attribute \src "libresoc.v:161500.17-161500.111" - wire $and$libresoc.v:161500$8532_Y + attribute \src "libresoc.v:161296.17-161296.111" + wire $and$libresoc.v:161296$8532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -299928,7 +299762,7 @@ module \p$116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161500$8532 + cell $and $and$libresoc.v:161296$8532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299936,18 +299770,18 @@ module \p$116 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161500$8532_Y + connect \Y $and$libresoc.v:161296$8532_Y end - connect \$1 $and$libresoc.v:161500$8532_Y + connect \$1 $and$libresoc.v:161296$8532_Y connect \trigger \$1 end -attribute \src "libresoc.v:161506.1-161517.10" +attribute \src "libresoc.v:161302.1-161313.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" attribute \generator "nMigen" module \p$17 - attribute \src "libresoc.v:161515.17-161515.111" - wire $and$libresoc.v:161515$8533_Y + attribute \src "libresoc.v:161311.17-161311.111" + wire $and$libresoc.v:161311$8533_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -299957,7 +299791,7 @@ module \p$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161515$8533 + cell $and $and$libresoc.v:161311$8533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299965,18 +299799,18 @@ module \p$17 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161515$8533_Y + connect \Y $and$libresoc.v:161311$8533_Y end - connect \$1 $and$libresoc.v:161515$8533_Y + connect \$1 $and$libresoc.v:161311$8533_Y connect \trigger \$1 end -attribute \src "libresoc.v:161521.1-161532.10" +attribute \src "libresoc.v:161317.1-161328.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" attribute \generator "nMigen" module \p$20 - attribute \src "libresoc.v:161530.17-161530.111" - wire $and$libresoc.v:161530$8534_Y + attribute \src "libresoc.v:161326.17-161326.111" + wire $and$libresoc.v:161326$8534_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -299986,7 +299820,7 @@ module \p$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161530$8534 + cell $and $and$libresoc.v:161326$8534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299994,18 +299828,18 @@ module \p$20 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161530$8534_Y + connect \Y $and$libresoc.v:161326$8534_Y end - connect \$1 $and$libresoc.v:161530$8534_Y + connect \$1 $and$libresoc.v:161326$8534_Y connect \trigger \$1 end -attribute \src "libresoc.v:161536.1-161547.10" +attribute \src "libresoc.v:161332.1-161343.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" attribute \generator "nMigen" module \p$3 - attribute \src "libresoc.v:161545.17-161545.111" - wire $and$libresoc.v:161545$8535_Y + attribute \src "libresoc.v:161341.17-161341.111" + wire $and$libresoc.v:161341$8535_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300015,7 +299849,7 @@ module \p$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161545$8535 + cell $and $and$libresoc.v:161341$8535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300023,18 +299857,18 @@ module \p$3 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161545$8535_Y + connect \Y $and$libresoc.v:161341$8535_Y end - connect \$1 $and$libresoc.v:161545$8535_Y + connect \$1 $and$libresoc.v:161341$8535_Y connect \trigger \$1 end -attribute \src "libresoc.v:161551.1-161562.10" +attribute \src "libresoc.v:161347.1-161358.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" attribute \generator "nMigen" module \p$30 - attribute \src "libresoc.v:161560.17-161560.111" - wire $and$libresoc.v:161560$8536_Y + attribute \src "libresoc.v:161356.17-161356.111" + wire $and$libresoc.v:161356$8536_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300044,7 +299878,7 @@ module \p$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161560$8536 + cell $and $and$libresoc.v:161356$8536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300052,18 +299886,18 @@ module \p$30 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161560$8536_Y + connect \Y $and$libresoc.v:161356$8536_Y end - connect \$1 $and$libresoc.v:161560$8536_Y + connect \$1 $and$libresoc.v:161356$8536_Y connect \trigger \$1 end -attribute \src "libresoc.v:161566.1-161577.10" +attribute \src "libresoc.v:161362.1-161373.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" attribute \generator "nMigen" module \p$33 - attribute \src "libresoc.v:161575.17-161575.111" - wire $and$libresoc.v:161575$8537_Y + attribute \src "libresoc.v:161371.17-161371.111" + wire $and$libresoc.v:161371$8537_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300073,7 +299907,7 @@ module \p$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161575$8537 + cell $and $and$libresoc.v:161371$8537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300081,18 +299915,18 @@ module \p$33 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161575$8537_Y + connect \Y $and$libresoc.v:161371$8537_Y end - connect \$1 $and$libresoc.v:161575$8537_Y + connect \$1 $and$libresoc.v:161371$8537_Y connect \trigger \$1 end -attribute \src "libresoc.v:161581.1-161592.10" +attribute \src "libresoc.v:161377.1-161388.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" attribute \generator "nMigen" module \p$36 - attribute \src "libresoc.v:161590.17-161590.111" - wire $and$libresoc.v:161590$8538_Y + attribute \src "libresoc.v:161386.17-161386.111" + wire $and$libresoc.v:161386$8538_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300102,7 +299936,7 @@ module \p$36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161590$8538 + cell $and $and$libresoc.v:161386$8538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300110,18 +299944,18 @@ module \p$36 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161590$8538_Y + connect \Y $and$libresoc.v:161386$8538_Y end - connect \$1 $and$libresoc.v:161590$8538_Y + connect \$1 $and$libresoc.v:161386$8538_Y connect \trigger \$1 end -attribute \src "libresoc.v:161596.1-161607.10" +attribute \src "libresoc.v:161392.1-161403.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" attribute \generator "nMigen" module \p$46 - attribute \src "libresoc.v:161605.17-161605.111" - wire $and$libresoc.v:161605$8539_Y + attribute \src "libresoc.v:161401.17-161401.111" + wire $and$libresoc.v:161401$8539_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300131,7 +299965,7 @@ module \p$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161605$8539 + cell $and $and$libresoc.v:161401$8539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300139,18 +299973,18 @@ module \p$46 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161605$8539_Y + connect \Y $and$libresoc.v:161401$8539_Y end - connect \$1 $and$libresoc.v:161605$8539_Y + connect \$1 $and$libresoc.v:161401$8539_Y connect \trigger \$1 end -attribute \src "libresoc.v:161611.1-161622.10" +attribute \src "libresoc.v:161407.1-161418.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" attribute \generator "nMigen" module \p$48 - attribute \src "libresoc.v:161620.17-161620.111" - wire $and$libresoc.v:161620$8540_Y + attribute \src "libresoc.v:161416.17-161416.111" + wire $and$libresoc.v:161416$8540_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300160,7 +299994,7 @@ module \p$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161620$8540 + cell $and $and$libresoc.v:161416$8540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300168,18 +300002,18 @@ module \p$48 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161620$8540_Y + connect \Y $and$libresoc.v:161416$8540_Y end - connect \$1 $and$libresoc.v:161620$8540_Y + connect \$1 $and$libresoc.v:161416$8540_Y connect \trigger \$1 end -attribute \src "libresoc.v:161626.1-161637.10" +attribute \src "libresoc.v:161422.1-161433.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" attribute \generator "nMigen" module \p$5 - attribute \src "libresoc.v:161635.17-161635.111" - wire $and$libresoc.v:161635$8541_Y + attribute \src "libresoc.v:161431.17-161431.111" + wire $and$libresoc.v:161431$8541_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300189,7 +300023,7 @@ module \p$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161635$8541 + cell $and $and$libresoc.v:161431$8541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300197,18 +300031,18 @@ module \p$5 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161635$8541_Y + connect \Y $and$libresoc.v:161431$8541_Y end - connect \$1 $and$libresoc.v:161635$8541_Y + connect \$1 $and$libresoc.v:161431$8541_Y connect \trigger \$1 end -attribute \src "libresoc.v:161641.1-161652.10" +attribute \src "libresoc.v:161437.1-161448.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" attribute \generator "nMigen" module \p$52 - attribute \src "libresoc.v:161650.17-161650.111" - wire $and$libresoc.v:161650$8542_Y + attribute \src "libresoc.v:161446.17-161446.111" + wire $and$libresoc.v:161446$8542_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300218,7 +300052,7 @@ module \p$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161650$8542 + cell $and $and$libresoc.v:161446$8542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300226,18 +300060,18 @@ module \p$52 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161650$8542_Y + connect \Y $and$libresoc.v:161446$8542_Y end - connect \$1 $and$libresoc.v:161650$8542_Y + connect \$1 $and$libresoc.v:161446$8542_Y connect \trigger \$1 end -attribute \src "libresoc.v:161656.1-161667.10" +attribute \src "libresoc.v:161452.1-161463.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" attribute \generator "nMigen" module \p$62 - attribute \src "libresoc.v:161665.17-161665.111" - wire $and$libresoc.v:161665$8543_Y + attribute \src "libresoc.v:161461.17-161461.111" + wire $and$libresoc.v:161461$8543_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300247,7 +300081,7 @@ module \p$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161665$8543 + cell $and $and$libresoc.v:161461$8543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300255,18 +300089,18 @@ module \p$62 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161665$8543_Y + connect \Y $and$libresoc.v:161461$8543_Y end - connect \$1 $and$libresoc.v:161665$8543_Y + connect \$1 $and$libresoc.v:161461$8543_Y connect \trigger \$1 end -attribute \src "libresoc.v:161671.1-161682.10" +attribute \src "libresoc.v:161467.1-161478.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" attribute \generator "nMigen" module \p$65 - attribute \src "libresoc.v:161680.17-161680.111" - wire $and$libresoc.v:161680$8544_Y + attribute \src "libresoc.v:161476.17-161476.111" + wire $and$libresoc.v:161476$8544_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300276,7 +300110,7 @@ module \p$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161680$8544 + cell $and $and$libresoc.v:161476$8544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300284,18 +300118,18 @@ module \p$65 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161680$8544_Y + connect \Y $and$libresoc.v:161476$8544_Y end - connect \$1 $and$libresoc.v:161680$8544_Y + connect \$1 $and$libresoc.v:161476$8544_Y connect \trigger \$1 end -attribute \src "libresoc.v:161686.1-161697.10" +attribute \src "libresoc.v:161482.1-161493.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" attribute \generator "nMigen" module \p$7 - attribute \src "libresoc.v:161695.17-161695.111" - wire $and$libresoc.v:161695$8545_Y + attribute \src "libresoc.v:161491.17-161491.111" + wire $and$libresoc.v:161491$8545_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300305,7 +300139,7 @@ module \p$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161695$8545 + cell $and $and$libresoc.v:161491$8545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300313,18 +300147,18 @@ module \p$7 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161695$8545_Y + connect \Y $and$libresoc.v:161491$8545_Y end - connect \$1 $and$libresoc.v:161695$8545_Y + connect \$1 $and$libresoc.v:161491$8545_Y connect \trigger \$1 end -attribute \src "libresoc.v:161701.1-161712.10" +attribute \src "libresoc.v:161497.1-161508.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" attribute \generator "nMigen" module \p$74 - attribute \src "libresoc.v:161710.17-161710.111" - wire $and$libresoc.v:161710$8546_Y + attribute \src "libresoc.v:161506.17-161506.111" + wire $and$libresoc.v:161506$8546_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300334,7 +300168,7 @@ module \p$74 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161710$8546 + cell $and $and$libresoc.v:161506$8546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300342,18 +300176,18 @@ module \p$74 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161710$8546_Y + connect \Y $and$libresoc.v:161506$8546_Y end - connect \$1 $and$libresoc.v:161710$8546_Y + connect \$1 $and$libresoc.v:161506$8546_Y connect \trigger \$1 end -attribute \src "libresoc.v:161716.1-161727.10" +attribute \src "libresoc.v:161512.1-161523.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" attribute \generator "nMigen" module \p$76 - attribute \src "libresoc.v:161725.17-161725.111" - wire $and$libresoc.v:161725$8547_Y + attribute \src "libresoc.v:161521.17-161521.111" + wire $and$libresoc.v:161521$8547_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300363,7 +300197,7 @@ module \p$76 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161725$8547 + cell $and $and$libresoc.v:161521$8547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300371,18 +300205,18 @@ module \p$76 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161725$8547_Y + connect \Y $and$libresoc.v:161521$8547_Y end - connect \$1 $and$libresoc.v:161725$8547_Y + connect \$1 $and$libresoc.v:161521$8547_Y connect \trigger \$1 end -attribute \src "libresoc.v:161731.1-161742.10" +attribute \src "libresoc.v:161527.1-161538.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" attribute \generator "nMigen" module \p$79 - attribute \src "libresoc.v:161740.17-161740.111" - wire $and$libresoc.v:161740$8548_Y + attribute \src "libresoc.v:161536.17-161536.111" + wire $and$libresoc.v:161536$8548_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300392,7 +300226,7 @@ module \p$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161740$8548 + cell $and $and$libresoc.v:161536$8548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300400,18 +300234,18 @@ module \p$79 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161740$8548_Y + connect \Y $and$libresoc.v:161536$8548_Y end - connect \$1 $and$libresoc.v:161740$8548_Y + connect \$1 $and$libresoc.v:161536$8548_Y connect \trigger \$1 end -attribute \src "libresoc.v:161746.1-161757.10" +attribute \src "libresoc.v:161542.1-161553.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" attribute \generator "nMigen" module \p$81 - attribute \src "libresoc.v:161755.17-161755.111" - wire $and$libresoc.v:161755$8549_Y + attribute \src "libresoc.v:161551.17-161551.111" + wire $and$libresoc.v:161551$8549_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300421,7 +300255,7 @@ module \p$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161755$8549 + cell $and $and$libresoc.v:161551$8549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300429,18 +300263,18 @@ module \p$81 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161755$8549_Y + connect \Y $and$libresoc.v:161551$8549_Y end - connect \$1 $and$libresoc.v:161755$8549_Y + connect \$1 $and$libresoc.v:161551$8549_Y connect \trigger \$1 end -attribute \src "libresoc.v:161761.1-161772.10" +attribute \src "libresoc.v:161557.1-161568.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" attribute \generator "nMigen" module \p$91 - attribute \src "libresoc.v:161770.17-161770.111" - wire $and$libresoc.v:161770$8550_Y + attribute \src "libresoc.v:161566.17-161566.111" + wire $and$libresoc.v:161566$8550_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300450,7 +300284,7 @@ module \p$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161770$8550 + cell $and $and$libresoc.v:161566$8550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300458,18 +300292,18 @@ module \p$91 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161770$8550_Y + connect \Y $and$libresoc.v:161566$8550_Y end - connect \$1 $and$libresoc.v:161770$8550_Y + connect \$1 $and$libresoc.v:161566$8550_Y connect \trigger \$1 end -attribute \src "libresoc.v:161776.1-161787.10" +attribute \src "libresoc.v:161572.1-161583.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" attribute \generator "nMigen" module \p$93 - attribute \src "libresoc.v:161785.17-161785.111" - wire $and$libresoc.v:161785$8551_Y + attribute \src "libresoc.v:161581.17-161581.111" + wire $and$libresoc.v:161581$8551_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300479,7 +300313,7 @@ module \p$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161785$8551 + cell $and $and$libresoc.v:161581$8551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300487,18 +300321,18 @@ module \p$93 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161785$8551_Y + connect \Y $and$libresoc.v:161581$8551_Y end - connect \$1 $and$libresoc.v:161785$8551_Y + connect \$1 $and$libresoc.v:161581$8551_Y connect \trigger \$1 end -attribute \src "libresoc.v:161791.1-161802.10" +attribute \src "libresoc.v:161587.1-161598.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" attribute \generator "nMigen" module \p$96 - attribute \src "libresoc.v:161800.17-161800.111" - wire $and$libresoc.v:161800$8552_Y + attribute \src "libresoc.v:161596.17-161596.111" + wire $and$libresoc.v:161596$8552_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300508,7 +300342,7 @@ module \p$96 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161800$8552 + cell $and $and$libresoc.v:161596$8552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300516,18 +300350,18 @@ module \p$96 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161800$8552_Y + connect \Y $and$libresoc.v:161596$8552_Y end - connect \$1 $and$libresoc.v:161800$8552_Y + connect \$1 $and$libresoc.v:161596$8552_Y connect \trigger \$1 end -attribute \src "libresoc.v:161806.1-161817.10" +attribute \src "libresoc.v:161602.1-161613.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" attribute \generator "nMigen" module \p$98 - attribute \src "libresoc.v:161815.17-161815.111" - wire $and$libresoc.v:161815$8553_Y + attribute \src "libresoc.v:161611.17-161611.111" + wire $and$libresoc.v:161611$8553_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -300537,7 +300371,7 @@ module \p$98 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:161815$8553 + cell $and $and$libresoc.v:161611$8553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300545,36 +300379,36 @@ module \p$98 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:161815$8553_Y + connect \Y $and$libresoc.v:161611$8553_Y end - connect \$1 $and$libresoc.v:161815$8553_Y + connect \$1 $and$libresoc.v:161611$8553_Y connect \trigger \$1 end -attribute \src "libresoc.v:161821.1-161844.10" +attribute \src "libresoc.v:161617.1-161640.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" attribute \generator "nMigen" module \pick - attribute \src "libresoc.v:161822.7-161822.20" + attribute \src "libresoc.v:161618.7-161618.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161833.3-161842.6" + attribute \src "libresoc.v:161629.3-161638.6" wire $0\o[0:0] - attribute \src "libresoc.v:161833.3-161842.6" + attribute \src "libresoc.v:161629.3-161638.6" wire $1\o[0:0] - attribute \src "libresoc.v:161832.17-161832.95" - wire $eq$libresoc.v:161832$8554_Y + attribute \src "libresoc.v:161628.17-161628.95" + wire $eq$libresoc.v:161628$8554_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire input 3 \i - attribute \src "libresoc.v:161822.7-161822.15" + attribute \src "libresoc.v:161618.7-161618.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" wire output 2 \n attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$libresoc.v:161832$8554 + cell $eq $eq$libresoc.v:161628$8554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300582,24 +300416,24 @@ module \pick parameter \Y_WIDTH 1 connect \A \i connect \B 1'0 - connect \Y $eq$libresoc.v:161832$8554_Y + connect \Y $eq$libresoc.v:161628$8554_Y end - attribute \src "libresoc.v:161822.7-161822.20" - process $proc$libresoc.v:161822$8556 + attribute \src "libresoc.v:161618.7-161618.20" + process $proc$libresoc.v:161618$8556 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:161833.3-161842.6" - process $proc$libresoc.v:161833$8555 + attribute \src "libresoc.v:161629.3-161638.6" + process $proc$libresoc.v:161629$8555 assign { } { } assign { } { } assign $0\o[0:0] $1\o[0:0] - attribute \src "libresoc.v:161834.5-161834.29" + attribute \src "libresoc.v:161630.5-161630.29" switch \initial - attribute \src "libresoc.v:161834.9-161834.17" + attribute \src "libresoc.v:161630.9-161630.17" case 1'1 case end @@ -300615,296 +300449,296 @@ module \pick sync always update \o $0\o[0:0] end - connect \$1 $eq$libresoc.v:161832$8554_Y + connect \$1 $eq$libresoc.v:161628$8554_Y connect \n \$1 end -attribute \src "libresoc.v:161848.1-162662.10" +attribute \src "libresoc.v:161644.1-162458.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" attribute \generator "nMigen" module \pimem - attribute \src "libresoc.v:162625.3-162640.6" + attribute \src "libresoc.v:162421.3-162436.6" wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:162589.3-162624.6" + attribute \src "libresoc.v:162385.3-162420.6" wire $0\adrok_l_s_addr_acked$next[0:0]$8646 - attribute \src "libresoc.v:162147.3-162148.57" + attribute \src "libresoc.v:161943.3-161944.57" wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:162239.3-162247.6" + attribute \src "libresoc.v:162035.3-162043.6" wire $0\busy_delay$next[0:0]$8614 - attribute \src "libresoc.v:162145.3-162146.37" + attribute \src "libresoc.v:161941.3-161942.37" wire $0\busy_delay[0:0] - attribute \src "libresoc.v:162573.3-162588.6" + attribute \src "libresoc.v:162369.3-162384.6" wire $0\busy_l_r_busy[0:0] - attribute \src "libresoc.v:162563.3-162572.6" + attribute \src "libresoc.v:162359.3-162368.6" wire $0\busy_l_s_busy[0:0] - attribute \src "libresoc.v:162553.3-162562.6" + attribute \src "libresoc.v:162349.3-162358.6" wire $0\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:162534.3-162543.6" + attribute \src "libresoc.v:162330.3-162339.6" wire $0\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:162495.3-162533.6" + attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $0\fsm_state$next[1:0]$8632 - attribute \src "libresoc.v:162137.3-162138.35" + attribute \src "libresoc.v:161933.3-161934.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:161849.7-161849.20" + attribute \src "libresoc.v:161645.7-161645.20" wire $0\initial[0:0] - attribute \src "libresoc.v:162435.3-162444.6" + attribute \src "libresoc.v:162231.3-162240.6" wire $0\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:162143.3-162144.35" + attribute \src "libresoc.v:161939.3-161940.35" wire $0\lds_dly[0:0] - attribute \src "libresoc.v:162368.3-162398.6" + attribute \src "libresoc.v:162164.3-162194.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:162425.3-162434.6" + attribute \src "libresoc.v:162221.3-162230.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:162445.3-162454.6" + attribute \src "libresoc.v:162241.3-162250.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:162274.3-162289.6" + attribute \src "libresoc.v:162070.3-162085.6" wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "libresoc.v:162258.3-162273.6" + attribute \src "libresoc.v:162054.3-162069.6" wire width 4 $0\lenexp_len_i[3:0] - attribute \src "libresoc.v:162544.3-162552.6" + attribute \src "libresoc.v:162340.3-162348.6" wire $0\lsui_active_dly$next[0:0]$8640 - attribute \src "libresoc.v:162135.3-162136.47" + attribute \src "libresoc.v:161931.3-161932.47" wire $0\lsui_active_dly[0:0] - attribute \src "libresoc.v:162475.3-162494.6" + attribute \src "libresoc.v:162271.3-162290.6" wire $0\lsui_busy[0:0] - attribute \src "libresoc.v:162139.3-162140.36" + attribute \src "libresoc.v:161935.3-161936.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:162415.3-162424.6" + attribute \src "libresoc.v:162211.3-162220.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:162399.3-162414.6" + attribute \src "libresoc.v:162195.3-162210.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:162248.3-162257.6" + attribute \src "libresoc.v:162044.3-162053.6" wire $0\st_active_r_st_active[0:0] - attribute \src "libresoc.v:162229.3-162238.6" + attribute \src "libresoc.v:162025.3-162034.6" wire $0\st_done_r_st_done[0:0] - attribute \src "libresoc.v:162214.3-162228.6" + attribute \src "libresoc.v:162010.3-162024.6" wire $0\st_done_s_st_done$next[0:0]$8609 - attribute \src "libresoc.v:162149.3-162150.51" + attribute \src "libresoc.v:161945.3-161946.51" wire $0\st_done_s_st_done[0:0] - attribute \src "libresoc.v:162455.3-162464.6" + attribute \src "libresoc.v:162251.3-162260.6" wire width 64 $0\stdata[63:0] - attribute \src "libresoc.v:162141.3-162142.35" + attribute \src "libresoc.v:161937.3-161938.35" wire $0\sts_dly[0:0] - attribute \src "libresoc.v:162290.3-162315.6" + attribute \src "libresoc.v:162086.3-162111.6" wire $0\valid_l_s_valid[0:0] - attribute \src "libresoc.v:162342.3-162367.6" + attribute \src "libresoc.v:162138.3-162163.6" wire width 48 $0\x_addr_i[47:0] - attribute \src "libresoc.v:162316.3-162341.6" + attribute \src "libresoc.v:162112.3-162137.6" wire width 8 $0\x_mask_i[7:0] - attribute \src "libresoc.v:162465.3-162474.6" + attribute \src "libresoc.v:162261.3-162270.6" wire width 64 $0\x_st_data_i[63:0] - attribute \src "libresoc.v:162625.3-162640.6" + attribute \src "libresoc.v:162421.3-162436.6" wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:162589.3-162624.6" + attribute \src "libresoc.v:162385.3-162420.6" wire $1\adrok_l_s_addr_acked$next[0:0]$8647 - attribute \src "libresoc.v:161943.7-161943.34" + attribute \src "libresoc.v:161739.7-161739.34" wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:162239.3-162247.6" + attribute \src "libresoc.v:162035.3-162043.6" wire $1\busy_delay$next[0:0]$8615 - attribute \src "libresoc.v:161947.7-161947.24" + attribute \src "libresoc.v:161743.7-161743.24" wire $1\busy_delay[0:0] - attribute \src "libresoc.v:162573.3-162588.6" + attribute \src "libresoc.v:162369.3-162384.6" wire $1\busy_l_r_busy[0:0] - attribute \src "libresoc.v:162563.3-162572.6" + attribute \src "libresoc.v:162359.3-162368.6" wire $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:162553.3-162562.6" + attribute \src "libresoc.v:162349.3-162358.6" wire $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:162534.3-162543.6" + attribute \src "libresoc.v:162330.3-162339.6" wire $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:162495.3-162533.6" + attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $1\fsm_state$next[1:0]$8633 - attribute \src "libresoc.v:161969.13-161969.29" + attribute \src "libresoc.v:161765.13-161765.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:162435.3-162444.6" + attribute \src "libresoc.v:162231.3-162240.6" wire $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:161983.7-161983.21" + attribute \src "libresoc.v:161779.7-161779.21" wire $1\lds_dly[0:0] - attribute \src "libresoc.v:162368.3-162398.6" + attribute \src "libresoc.v:162164.3-162194.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:162425.3-162434.6" + attribute \src "libresoc.v:162221.3-162230.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:162445.3-162454.6" + attribute \src "libresoc.v:162241.3-162250.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:162274.3-162289.6" + attribute \src "libresoc.v:162070.3-162085.6" wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "libresoc.v:162258.3-162273.6" + attribute \src "libresoc.v:162054.3-162069.6" wire width 4 $1\lenexp_len_i[3:0] - attribute \src "libresoc.v:162544.3-162552.6" + attribute \src "libresoc.v:162340.3-162348.6" wire $1\lsui_active_dly$next[0:0]$8641 - attribute \src "libresoc.v:162026.7-162026.29" + attribute \src "libresoc.v:161822.7-161822.29" wire $1\lsui_active_dly[0:0] - attribute \src "libresoc.v:162475.3-162494.6" + attribute \src "libresoc.v:162271.3-162290.6" wire $1\lsui_busy[0:0] - attribute \src "libresoc.v:162038.7-162038.25" + attribute \src "libresoc.v:161834.7-161834.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:162415.3-162424.6" + attribute \src "libresoc.v:162211.3-162220.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:162399.3-162414.6" + attribute \src "libresoc.v:162195.3-162210.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:162248.3-162257.6" + attribute \src "libresoc.v:162044.3-162053.6" wire $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:162229.3-162238.6" + attribute \src "libresoc.v:162025.3-162034.6" wire $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:162214.3-162228.6" + attribute \src "libresoc.v:162010.3-162024.6" wire $1\st_done_s_st_done$next[0:0]$8610 - attribute \src "libresoc.v:162058.7-162058.31" + attribute \src "libresoc.v:161854.7-161854.31" wire $1\st_done_s_st_done[0:0] - attribute \src "libresoc.v:162455.3-162464.6" + attribute \src "libresoc.v:162251.3-162260.6" wire width 64 $1\stdata[63:0] - attribute \src "libresoc.v:162066.7-162066.21" + attribute \src "libresoc.v:161862.7-161862.21" wire $1\sts_dly[0:0] - attribute \src "libresoc.v:162290.3-162315.6" + attribute \src "libresoc.v:162086.3-162111.6" wire $1\valid_l_s_valid[0:0] - attribute \src "libresoc.v:162342.3-162367.6" + attribute \src "libresoc.v:162138.3-162163.6" wire width 48 $1\x_addr_i[47:0] - attribute \src "libresoc.v:162316.3-162341.6" + attribute \src "libresoc.v:162112.3-162137.6" wire width 8 $1\x_mask_i[7:0] - attribute \src "libresoc.v:162465.3-162474.6" + attribute \src "libresoc.v:162261.3-162270.6" wire width 64 $1\x_st_data_i[63:0] - attribute \src "libresoc.v:162625.3-162640.6" + attribute \src "libresoc.v:162421.3-162436.6" wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:162589.3-162624.6" + attribute \src "libresoc.v:162385.3-162420.6" wire $2\adrok_l_s_addr_acked$next[0:0]$8648 - attribute \src "libresoc.v:162573.3-162588.6" + attribute \src "libresoc.v:162369.3-162384.6" wire $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:162495.3-162533.6" + attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $2\fsm_state$next[1:0]$8634 - attribute \src "libresoc.v:162368.3-162398.6" + attribute \src "libresoc.v:162164.3-162194.6" wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:162274.3-162289.6" + attribute \src "libresoc.v:162070.3-162085.6" wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:162258.3-162273.6" + attribute \src "libresoc.v:162054.3-162069.6" wire width 4 $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:162475.3-162494.6" + attribute \src "libresoc.v:162271.3-162290.6" wire $2\lsui_busy[0:0] - attribute \src "libresoc.v:162399.3-162414.6" + attribute \src "libresoc.v:162195.3-162210.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:162214.3-162228.6" + attribute \src "libresoc.v:162010.3-162024.6" wire $2\st_done_s_st_done$next[0:0]$8611 - attribute \src "libresoc.v:162290.3-162315.6" + attribute \src "libresoc.v:162086.3-162111.6" wire $2\valid_l_s_valid[0:0] - attribute \src "libresoc.v:162342.3-162367.6" + attribute \src "libresoc.v:162138.3-162163.6" wire width 48 $2\x_addr_i[47:0] - attribute \src "libresoc.v:162316.3-162341.6" + attribute \src "libresoc.v:162112.3-162137.6" wire width 8 $2\x_mask_i[7:0] - attribute \src "libresoc.v:162589.3-162624.6" + attribute \src "libresoc.v:162385.3-162420.6" wire $3\adrok_l_s_addr_acked$next[0:0]$8649 - attribute \src "libresoc.v:162495.3-162533.6" + attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $3\fsm_state$next[1:0]$8635 - attribute \src "libresoc.v:162368.3-162398.6" + attribute \src "libresoc.v:162164.3-162194.6" wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:162290.3-162315.6" + attribute \src "libresoc.v:162086.3-162111.6" wire $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:162342.3-162367.6" + attribute \src "libresoc.v:162138.3-162163.6" wire width 48 $3\x_addr_i[47:0] - attribute \src "libresoc.v:162316.3-162341.6" + attribute \src "libresoc.v:162112.3-162137.6" wire width 8 $3\x_mask_i[7:0] - attribute \src "libresoc.v:162589.3-162624.6" + attribute \src "libresoc.v:162385.3-162420.6" wire $4\adrok_l_s_addr_acked$next[0:0]$8650 - attribute \src "libresoc.v:162495.3-162533.6" + attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $4\fsm_state$next[1:0]$8636 - attribute \src "libresoc.v:162368.3-162398.6" + attribute \src "libresoc.v:162164.3-162194.6" wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:162290.3-162315.6" + attribute \src "libresoc.v:162086.3-162111.6" wire $4\valid_l_s_valid[0:0] - attribute \src "libresoc.v:162342.3-162367.6" + attribute \src "libresoc.v:162138.3-162163.6" wire width 48 $4\x_addr_i[47:0] - attribute \src "libresoc.v:162316.3-162341.6" + attribute \src "libresoc.v:162112.3-162137.6" wire width 8 $4\x_mask_i[7:0] - attribute \src "libresoc.v:162589.3-162624.6" + attribute \src "libresoc.v:162385.3-162420.6" wire $5\adrok_l_s_addr_acked$next[0:0]$8651 - attribute \src "libresoc.v:162495.3-162533.6" + attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $5\fsm_state$next[1:0]$8637 - attribute \src "libresoc.v:162368.3-162398.6" + attribute \src "libresoc.v:162164.3-162194.6" wire $5\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:162589.3-162624.6" + attribute \src "libresoc.v:162385.3-162420.6" wire $6\adrok_l_s_addr_acked$next[0:0]$8652 - attribute \src "libresoc.v:162095.18-162095.115" - wire $and$libresoc.v:162095$8558_Y - attribute \src "libresoc.v:162097.18-162097.95" - wire $and$libresoc.v:162097$8560_Y - attribute \src "libresoc.v:162099.17-162099.138" - wire $and$libresoc.v:162099$8562_Y - attribute \src "libresoc.v:162100.18-162100.95" - wire $and$libresoc.v:162100$8563_Y - attribute \src "libresoc.v:162103.18-162103.136" - wire $and$libresoc.v:162103$8568_Y - attribute \src "libresoc.v:162104.18-162104.136" - wire $and$libresoc.v:162104$8569_Y - attribute \src "libresoc.v:162105.18-162105.136" - wire $and$libresoc.v:162105$8570_Y - attribute \src "libresoc.v:162106.18-162106.136" - wire $and$libresoc.v:162106$8571_Y - attribute \src "libresoc.v:162107.18-162107.136" - wire $and$libresoc.v:162107$8572_Y - attribute \src "libresoc.v:162112.18-162112.119" - wire width 176 $and$libresoc.v:162112$8577_Y - attribute \src "libresoc.v:162115.18-162115.136" - wire $and$libresoc.v:162115$8580_Y - attribute \src "libresoc.v:162116.18-162116.136" - wire $and$libresoc.v:162116$8581_Y - attribute \src "libresoc.v:162118.18-162118.139" - wire $and$libresoc.v:162118$8583_Y - attribute \src "libresoc.v:162122.18-162122.139" - wire $and$libresoc.v:162122$8587_Y - attribute \src "libresoc.v:162124.18-162124.114" - wire $and$libresoc.v:162124$8589_Y - attribute \src "libresoc.v:162126.18-162126.114" - wire $and$libresoc.v:162126$8591_Y - attribute \src "libresoc.v:162130.18-162130.103" - wire $and$libresoc.v:162130$8595_Y - attribute \src "libresoc.v:162131.17-162131.135" - wire $and$libresoc.v:162131$8596_Y - attribute \src "libresoc.v:162134.18-162134.103" - wire $and$libresoc.v:162134$8599_Y - attribute \src "libresoc.v:162101.18-162101.109" - wire width 4 $extend$libresoc.v:162101$8564_Y - attribute \src "libresoc.v:162102.18-162102.109" - wire width 4 $extend$libresoc.v:162102$8566_Y - attribute \src "libresoc.v:162113.18-162113.112" - wire width 8 $mul$libresoc.v:162113$8578_Y - attribute \src "libresoc.v:162119.18-162119.112" - wire width 8 $mul$libresoc.v:162119$8584_Y - attribute \src "libresoc.v:162094.17-162094.103" - wire $not$libresoc.v:162094$8557_Y - attribute \src "libresoc.v:162096.18-162096.94" - wire $not$libresoc.v:162096$8559_Y - attribute \src "libresoc.v:162098.18-162098.94" - wire $not$libresoc.v:162098$8561_Y - attribute \src "libresoc.v:162108.18-162108.102" - wire $not$libresoc.v:162108$8573_Y - attribute \src "libresoc.v:162111.18-162111.97" - wire $not$libresoc.v:162111$8576_Y - attribute \src "libresoc.v:162117.18-162117.102" - wire $not$libresoc.v:162117$8582_Y - attribute \src "libresoc.v:162120.17-162120.103" - wire $not$libresoc.v:162120$8585_Y - attribute \src "libresoc.v:162127.18-162127.101" - wire $not$libresoc.v:162127$8592_Y - attribute \src "libresoc.v:162128.18-162128.111" - wire $not$libresoc.v:162128$8593_Y - attribute \src "libresoc.v:162129.18-162129.110" - wire $not$libresoc.v:162129$8594_Y - attribute \src "libresoc.v:162132.18-162132.102" - wire $not$libresoc.v:162132$8597_Y - attribute \src "libresoc.v:162133.18-162133.102" - wire $not$libresoc.v:162133$8598_Y - attribute \src "libresoc.v:162109.18-162109.111" - wire $or$libresoc.v:162109$8574_Y - attribute \src "libresoc.v:162110.17-162110.130" - wire $or$libresoc.v:162110$8575_Y - attribute \src "libresoc.v:162123.18-162123.130" - wire $or$libresoc.v:162123$8588_Y - attribute \src "libresoc.v:162125.18-162125.130" - wire $or$libresoc.v:162125$8590_Y - attribute \src "libresoc.v:162101.18-162101.109" - wire width 4 $pos$libresoc.v:162101$8565_Y - attribute \src "libresoc.v:162102.18-162102.109" - wire width 4 $pos$libresoc.v:162102$8567_Y - attribute \src "libresoc.v:162121.18-162121.121" - wire width 319 $sshl$libresoc.v:162121$8586_Y - attribute \src "libresoc.v:162114.18-162114.106" - wire width 176 $sshr$libresoc.v:162114$8579_Y + attribute \src "libresoc.v:161891.18-161891.115" + wire $and$libresoc.v:161891$8558_Y + attribute \src "libresoc.v:161893.18-161893.95" + wire $and$libresoc.v:161893$8560_Y + attribute \src "libresoc.v:161895.17-161895.138" + wire $and$libresoc.v:161895$8562_Y + attribute \src "libresoc.v:161896.18-161896.95" + wire $and$libresoc.v:161896$8563_Y + attribute \src "libresoc.v:161899.18-161899.136" + wire $and$libresoc.v:161899$8568_Y + attribute \src "libresoc.v:161900.18-161900.136" + wire $and$libresoc.v:161900$8569_Y + attribute \src "libresoc.v:161901.18-161901.136" + wire $and$libresoc.v:161901$8570_Y + attribute \src "libresoc.v:161902.18-161902.136" + wire $and$libresoc.v:161902$8571_Y + attribute \src "libresoc.v:161903.18-161903.136" + wire $and$libresoc.v:161903$8572_Y + attribute \src "libresoc.v:161908.18-161908.119" + wire width 176 $and$libresoc.v:161908$8577_Y + attribute \src "libresoc.v:161911.18-161911.136" + wire $and$libresoc.v:161911$8580_Y + attribute \src "libresoc.v:161912.18-161912.136" + wire $and$libresoc.v:161912$8581_Y + attribute \src "libresoc.v:161914.18-161914.139" + wire $and$libresoc.v:161914$8583_Y + attribute \src "libresoc.v:161918.18-161918.139" + wire $and$libresoc.v:161918$8587_Y + attribute \src "libresoc.v:161920.18-161920.114" + wire $and$libresoc.v:161920$8589_Y + attribute \src "libresoc.v:161922.18-161922.114" + wire $and$libresoc.v:161922$8591_Y + attribute \src "libresoc.v:161926.18-161926.103" + wire $and$libresoc.v:161926$8595_Y + attribute \src "libresoc.v:161927.17-161927.135" + wire $and$libresoc.v:161927$8596_Y + attribute \src "libresoc.v:161930.18-161930.103" + wire $and$libresoc.v:161930$8599_Y + attribute \src "libresoc.v:161897.18-161897.109" + wire width 4 $extend$libresoc.v:161897$8564_Y + attribute \src "libresoc.v:161898.18-161898.109" + wire width 4 $extend$libresoc.v:161898$8566_Y + attribute \src "libresoc.v:161909.18-161909.112" + wire width 8 $mul$libresoc.v:161909$8578_Y + attribute \src "libresoc.v:161915.18-161915.112" + wire width 8 $mul$libresoc.v:161915$8584_Y + attribute \src "libresoc.v:161890.17-161890.103" + wire $not$libresoc.v:161890$8557_Y + attribute \src "libresoc.v:161892.18-161892.94" + wire $not$libresoc.v:161892$8559_Y + attribute \src "libresoc.v:161894.18-161894.94" + wire $not$libresoc.v:161894$8561_Y + attribute \src "libresoc.v:161904.18-161904.102" + wire $not$libresoc.v:161904$8573_Y + attribute \src "libresoc.v:161907.18-161907.97" + wire $not$libresoc.v:161907$8576_Y + attribute \src "libresoc.v:161913.18-161913.102" + wire $not$libresoc.v:161913$8582_Y + attribute \src "libresoc.v:161916.17-161916.103" + wire $not$libresoc.v:161916$8585_Y + attribute \src "libresoc.v:161923.18-161923.101" + wire $not$libresoc.v:161923$8592_Y + attribute \src "libresoc.v:161924.18-161924.111" + wire $not$libresoc.v:161924$8593_Y + attribute \src "libresoc.v:161925.18-161925.110" + wire $not$libresoc.v:161925$8594_Y + attribute \src "libresoc.v:161928.18-161928.102" + wire $not$libresoc.v:161928$8597_Y + attribute \src "libresoc.v:161929.18-161929.102" + wire $not$libresoc.v:161929$8598_Y + attribute \src "libresoc.v:161905.18-161905.111" + wire $or$libresoc.v:161905$8574_Y + attribute \src "libresoc.v:161906.17-161906.130" + wire $or$libresoc.v:161906$8575_Y + attribute \src "libresoc.v:161919.18-161919.130" + wire $or$libresoc.v:161919$8588_Y + attribute \src "libresoc.v:161921.18-161921.130" + wire $or$libresoc.v:161921$8590_Y + attribute \src "libresoc.v:161897.18-161897.109" + wire width 4 $pos$libresoc.v:161897$8565_Y + attribute \src "libresoc.v:161898.18-161898.109" + wire width 4 $pos$libresoc.v:161898$8567_Y + attribute \src "libresoc.v:161917.18-161917.121" + wire width 319 $sshl$libresoc.v:161917$8586_Y + attribute \src "libresoc.v:161910.18-161910.106" + wire width 176 $sshr$libresoc.v:161910$8579_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" @@ -301013,9 +300847,9 @@ module \pimem wire \busy_l_r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \cyc_l_q_cyc @@ -301027,7 +300861,7 @@ module \pimem wire width 2 \fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state$next - attribute \src "libresoc.v:161849.7-161849.15" + attribute \src "libresoc.v:161645.7-161645.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \ld_active_q_ld_active @@ -301146,7 +300980,7 @@ module \pimem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire output 22 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $and$libresoc.v:162095$8558 + cell $and $and$libresoc.v:161891$8558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301154,10 +300988,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \B \$9 - connect \Y $and$libresoc.v:162095$8558_Y + connect \Y $and$libresoc.v:161891$8558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:162097$8560 + cell $and $and$libresoc.v:161893$8560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301165,10 +300999,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lds connect \B \$13 - connect \Y $and$libresoc.v:162097$8560_Y + connect \Y $and$libresoc.v:161893$8560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:162099$8562 + cell $and $and$libresoc.v:161895$8562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301176,10 +301010,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:162099$8562_Y + connect \Y $and$libresoc.v:161895$8562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:162100$8563 + cell $and $and$libresoc.v:161896$8563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301187,10 +301021,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \sts connect \B \$17 - connect \Y $and$libresoc.v:162100$8563_Y + connect \Y $and$libresoc.v:161896$8563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:162103$8568 + cell $and $and$libresoc.v:161899$8568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301198,10 +301032,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:162103$8568_Y + connect \Y $and$libresoc.v:161899$8568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:162104$8569 + cell $and $and$libresoc.v:161900$8569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301209,10 +301043,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:162104$8569_Y + connect \Y $and$libresoc.v:161900$8569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:162105$8570 + cell $and $and$libresoc.v:161901$8570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301220,10 +301054,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:162105$8570_Y + connect \Y $and$libresoc.v:161901$8570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:162106$8571 + cell $and $and$libresoc.v:161902$8571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301231,10 +301065,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:162106$8571_Y + connect \Y $and$libresoc.v:161902$8571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:162107$8572 + cell $and $and$libresoc.v:161903$8572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301242,10 +301076,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:162107$8572_Y + connect \Y $and$libresoc.v:161903$8572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - cell $and $and$libresoc.v:162112$8577 + cell $and $and$libresoc.v:161908$8577 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -301253,10 +301087,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \m_ld_data_o connect \B \lenexp_rexp_o - connect \Y $and$libresoc.v:162112$8577_Y + connect \Y $and$libresoc.v:161908$8577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:162115$8580 + cell $and $and$libresoc.v:161911$8580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301264,10 +301098,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:162115$8580_Y + connect \Y $and$libresoc.v:161911$8580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:162116$8581 + cell $and $and$libresoc.v:161912$8581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301275,10 +301109,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:162116$8581_Y + connect \Y $and$libresoc.v:161912$8581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:162118$8583 + cell $and $and$libresoc.v:161914$8583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301286,10 +301120,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:162118$8583_Y + connect \Y $and$libresoc.v:161914$8583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:162122$8587 + cell $and $and$libresoc.v:161918$8587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301297,10 +301131,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:162122$8587_Y + connect \Y $and$libresoc.v:161918$8587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:162124$8589 + cell $and $and$libresoc.v:161920$8589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301308,10 +301142,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$63 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:162124$8589_Y + connect \Y $and$libresoc.v:161920$8589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:162126$8591 + cell $and $and$libresoc.v:161922$8591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301319,10 +301153,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$67 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:162126$8591_Y + connect \Y $and$libresoc.v:161922$8591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$libresoc.v:162130$8595 + cell $and $and$libresoc.v:161926$8595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301330,10 +301164,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$73 connect \B \$75 - connect \Y $and$libresoc.v:162130$8595_Y + connect \Y $and$libresoc.v:161926$8595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:162131$8596 + cell $and $and$libresoc.v:161927$8596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301341,10 +301175,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:162131$8596_Y + connect \Y $and$libresoc.v:161927$8596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:162134$8599 + cell $and $and$libresoc.v:161930$8599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301352,26 +301186,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lsui_active connect \B \$81 - connect \Y $and$libresoc.v:162134$8599_Y + connect \Y $and$libresoc.v:161930$8599_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:162101$8564 + cell $pos $extend$libresoc.v:161897$8564 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:162101$8564_Y + connect \Y $extend$libresoc.v:161897$8564_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:162102$8566 + cell $pos $extend$libresoc.v:161898$8566 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:162102$8566_Y + connect \Y $extend$libresoc.v:161898$8566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $mul $mul$libresoc.v:162113$8578 + cell $mul $mul$libresoc.v:161909$8578 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -301379,10 +301213,10 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:162113$8578_Y + connect \Y $mul$libresoc.v:161909$8578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $mul $mul$libresoc.v:162119$8584 + cell $mul $mul$libresoc.v:161915$8584 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -301390,106 +301224,106 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:162119$8584_Y + connect \Y $mul$libresoc.v:161915$8584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $not $not$libresoc.v:162094$8557 + cell $not $not$libresoc.v:161890$8557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:162094$8557_Y + connect \Y $not$libresoc.v:161890$8557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:162096$8559 + cell $not $not$libresoc.v:161892$8559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lds_dly - connect \Y $not$libresoc.v:162096$8559_Y + connect \Y $not$libresoc.v:161892$8559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:162098$8561 + cell $not $not$libresoc.v:161894$8561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sts_dly - connect \Y $not$libresoc.v:162098$8561_Y + connect \Y $not$libresoc.v:161894$8561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:162108$8573 + cell $not $not$libresoc.v:161904$8573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:162108$8573_Y + connect \Y $not$libresoc.v:161904$8573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $not$libresoc.v:162111$8576 + cell $not $not$libresoc.v:161907$8576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 - connect \Y $not$libresoc.v:162111$8576_Y + connect \Y $not$libresoc.v:161907$8576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:162117$8582 + cell $not $not$libresoc.v:161913$8582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:162117$8582_Y + connect \Y $not$libresoc.v:161913$8582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - cell $not $not$libresoc.v:162120$8585 + cell $not $not$libresoc.v:161916$8585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:162120$8585_Y + connect \Y $not$libresoc.v:161916$8585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $not$libresoc.v:162127$8592 + cell $not $not$libresoc.v:161923$8592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:162127$8592_Y + connect \Y $not$libresoc.v:161923$8592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:162128$8593 + cell $not $not$libresoc.v:161924$8593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_st_i - connect \Y $not$libresoc.v:162128$8593_Y + connect \Y $not$libresoc.v:161924$8593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:162129$8594 + cell $not $not$libresoc.v:161925$8594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:162129$8594_Y + connect \Y $not$libresoc.v:161925$8594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $not$libresoc.v:162132$8597 + cell $not $not$libresoc.v:161928$8597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:162132$8597_Y + connect \Y $not$libresoc.v:161928$8597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:162133$8598 + cell $not $not$libresoc.v:161929$8598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_active_dly - connect \Y $not$libresoc.v:162133$8598_Y + connect \Y $not$libresoc.v:161929$8598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $or$libresoc.v:162109$8574 + cell $or $or$libresoc.v:161905$8574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301497,10 +301331,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \x_busy_o connect \B \lsui_busy - connect \Y $or$libresoc.v:162109$8574_Y + connect \Y $or$libresoc.v:161905$8574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - cell $or $or$libresoc.v:162110$8575 + cell $or $or$libresoc.v:161906$8575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301508,10 +301342,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:162110$8575_Y + connect \Y $or$libresoc.v:161906$8575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:162123$8588 + cell $or $or$libresoc.v:161919$8588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301519,10 +301353,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:162123$8588_Y + connect \Y $or$libresoc.v:161919$8588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:162125$8590 + cell $or $or$libresoc.v:161921$8590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301530,26 +301364,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:162125$8590_Y + connect \Y $or$libresoc.v:161921$8590_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:162101$8565 + cell $pos $pos$libresoc.v:161897$8565 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:162101$8564_Y - connect \Y $pos$libresoc.v:162101$8565_Y + connect \A $extend$libresoc.v:161897$8564_Y + connect \Y $pos$libresoc.v:161897$8565_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:162102$8567 + cell $pos $pos$libresoc.v:161898$8567 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:162102$8566_Y - connect \Y $pos$libresoc.v:162102$8567_Y + connect \A $extend$libresoc.v:161898$8566_Y + connect \Y $pos$libresoc.v:161898$8567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $sshl $sshl$libresoc.v:162121$8586 + cell $sshl $sshl$libresoc.v:161917$8586 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -301557,10 +301391,10 @@ module \pimem parameter \Y_WIDTH 319 connect \A \ldst_port0_st_data_i connect \B \$57 - connect \Y $sshl$libresoc.v:162121$8586_Y + connect \Y $sshl$libresoc.v:161917$8586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $sshr $sshr$libresoc.v:162114$8579 + cell $sshr $sshr$libresoc.v:161910$8579 parameter \A_SIGNED 0 parameter \A_WIDTH 176 parameter \B_SIGNED 0 @@ -301568,10 +301402,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \$42 connect \B \$44 - connect \Y $sshr$libresoc.v:162114$8579_Y + connect \Y $sshr$libresoc.v:161910$8579_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:162151.11-162158.4" + attribute \src "libresoc.v:161947.11-161954.4" cell \adrok_l \adrok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -301581,7 +301415,7 @@ module \pimem connect \s_addr_acked \adrok_l_s_addr_acked end attribute \module_not_derived 1 - attribute \src "libresoc.v:162159.10-162165.4" + attribute \src "libresoc.v:161955.10-161961.4" cell \busy_l \busy_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -301590,7 +301424,7 @@ module \pimem connect \s_busy \busy_l_s_busy end attribute \module_not_derived 1 - attribute \src "libresoc.v:162166.9-162172.4" + attribute \src "libresoc.v:161962.9-161968.4" cell \cyc_l \cyc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -301599,7 +301433,7 @@ module \pimem connect \s_cyc \cyc_l_s_cyc end attribute \module_not_derived 1 - attribute \src "libresoc.v:162173.13-162179.4" + attribute \src "libresoc.v:161969.13-161975.4" cell \ld_active \ld_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -301608,7 +301442,7 @@ module \pimem connect \s_ld_active \ld_active_s_ld_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:162180.10-162185.4" + attribute \src "libresoc.v:161976.10-161981.4" cell \lenexp \lenexp connect \addr_i \lenexp_addr_i connect \len_i \lenexp_len_i @@ -301616,7 +301450,7 @@ module \pimem connect \rexp_o \lenexp_rexp_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:162186.11-162192.4" + attribute \src "libresoc.v:161982.11-161988.4" cell \reset_l \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -301625,7 +301459,7 @@ module \pimem connect \s_reset \reset_l_s_reset end attribute \module_not_derived 1 - attribute \src "libresoc.v:162193.13-162199.4" + attribute \src "libresoc.v:161989.13-161995.4" cell \st_active \st_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -301634,7 +301468,7 @@ module \pimem connect \s_st_active \st_active_s_st_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:162200.11-162206.4" + attribute \src "libresoc.v:161996.11-162002.4" cell \st_done \st_done connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -301643,7 +301477,7 @@ module \pimem connect \s_st_done \st_done_s_st_done end attribute \module_not_derived 1 - attribute \src "libresoc.v:162207.11-162213.4" + attribute \src "libresoc.v:162003.11-162009.4" cell \valid_l \valid_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -301651,143 +301485,143 @@ module \pimem connect \r_valid \valid_l_r_valid connect \s_valid \valid_l_s_valid end - attribute \src "libresoc.v:161849.7-161849.20" - process $proc$libresoc.v:161849$8654 + attribute \src "libresoc.v:161645.7-161645.20" + process $proc$libresoc.v:161645$8654 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:161943.7-161943.34" - process $proc$libresoc.v:161943$8655 + attribute \src "libresoc.v:161739.7-161739.34" + process $proc$libresoc.v:161739$8655 assign { } { } assign $1\adrok_l_s_addr_acked[0:0] 1'0 sync always sync init update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:161947.7-161947.24" - process $proc$libresoc.v:161947$8656 + attribute \src "libresoc.v:161743.7-161743.24" + process $proc$libresoc.v:161743$8656 assign { } { } assign $1\busy_delay[0:0] 1'0 sync always sync init update \busy_delay $1\busy_delay[0:0] end - attribute \src "libresoc.v:161969.13-161969.29" - process $proc$libresoc.v:161969$8657 + attribute \src "libresoc.v:161765.13-161765.29" + process $proc$libresoc.v:161765$8657 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:161983.7-161983.21" - process $proc$libresoc.v:161983$8658 + attribute \src "libresoc.v:161779.7-161779.21" + process $proc$libresoc.v:161779$8658 assign { } { } assign $1\lds_dly[0:0] 1'0 sync always sync init update \lds_dly $1\lds_dly[0:0] end - attribute \src "libresoc.v:162026.7-162026.29" - process $proc$libresoc.v:162026$8659 + attribute \src "libresoc.v:161822.7-161822.29" + process $proc$libresoc.v:161822$8659 assign { } { } assign $1\lsui_active_dly[0:0] 1'0 sync always sync init update \lsui_active_dly $1\lsui_active_dly[0:0] end - attribute \src "libresoc.v:162038.7-162038.25" - process $proc$libresoc.v:162038$8660 + attribute \src "libresoc.v:161834.7-161834.25" + process $proc$libresoc.v:161834$8660 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:162058.7-162058.31" - process $proc$libresoc.v:162058$8661 + attribute \src "libresoc.v:161854.7-161854.31" + process $proc$libresoc.v:161854$8661 assign { } { } assign $1\st_done_s_st_done[0:0] 1'0 sync always sync init update \st_done_s_st_done $1\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:162066.7-162066.21" - process $proc$libresoc.v:162066$8662 + attribute \src "libresoc.v:161862.7-161862.21" + process $proc$libresoc.v:161862$8662 assign { } { } assign $1\sts_dly[0:0] 1'0 sync always sync init update \sts_dly $1\sts_dly[0:0] end - attribute \src "libresoc.v:162135.3-162136.47" - process $proc$libresoc.v:162135$8600 + attribute \src "libresoc.v:161931.3-161932.47" + process $proc$libresoc.v:161931$8600 assign { } { } assign $0\lsui_active_dly[0:0] \lsui_active_dly$next sync posedge \coresync_clk update \lsui_active_dly $0\lsui_active_dly[0:0] end - attribute \src "libresoc.v:162137.3-162138.35" - process $proc$libresoc.v:162137$8601 + attribute \src "libresoc.v:161933.3-161934.35" + process $proc$libresoc.v:161933$8601 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \coresync_clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:162139.3-162140.36" - process $proc$libresoc.v:162139$8602 + attribute \src "libresoc.v:161935.3-161936.36" + process $proc$libresoc.v:161935$8602 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:162141.3-162142.35" - process $proc$libresoc.v:162141$8603 + attribute \src "libresoc.v:161937.3-161938.35" + process $proc$libresoc.v:161937$8603 assign { } { } assign $0\sts_dly[0:0] \ldst_port0_is_st_i sync posedge \coresync_clk update \sts_dly $0\sts_dly[0:0] end - attribute \src "libresoc.v:162143.3-162144.35" - process $proc$libresoc.v:162143$8604 + attribute \src "libresoc.v:161939.3-161940.35" + process $proc$libresoc.v:161939$8604 assign { } { } assign $0\lds_dly[0:0] \ldst_port0_is_ld_i sync posedge \coresync_clk update \lds_dly $0\lds_dly[0:0] end - attribute \src "libresoc.v:162145.3-162146.37" - process $proc$libresoc.v:162145$8605 + attribute \src "libresoc.v:161941.3-161942.37" + process $proc$libresoc.v:161941$8605 assign { } { } assign $0\busy_delay[0:0] \busy_delay$next sync posedge \coresync_clk update \busy_delay $0\busy_delay[0:0] end - attribute \src "libresoc.v:162147.3-162148.57" - process $proc$libresoc.v:162147$8606 + attribute \src "libresoc.v:161943.3-161944.57" + process $proc$libresoc.v:161943$8606 assign { } { } assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next sync posedge \coresync_clk update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:162149.3-162150.51" - process $proc$libresoc.v:162149$8607 + attribute \src "libresoc.v:161945.3-161946.51" + process $proc$libresoc.v:161945$8607 assign { } { } assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next sync posedge \coresync_clk update \st_done_s_st_done $0\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:162214.3-162228.6" - process $proc$libresoc.v:162214$8608 + attribute \src "libresoc.v:162010.3-162024.6" + process $proc$libresoc.v:162010$8608 assign { } { } assign { } { } assign { } { } assign $0\st_done_s_st_done$next[0:0]$8609 $2\st_done_s_st_done$next[0:0]$8611 - attribute \src "libresoc.v:162215.5-162215.29" + attribute \src "libresoc.v:162011.5-162011.29" switch \initial - attribute \src "libresoc.v:162215.9-162215.17" + attribute \src "libresoc.v:162011.9-162011.17" case 1'1 case end @@ -301812,14 +301646,14 @@ module \pimem sync always update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8609 end - attribute \src "libresoc.v:162229.3-162238.6" - process $proc$libresoc.v:162229$8612 + attribute \src "libresoc.v:162025.3-162034.6" + process $proc$libresoc.v:162025$8612 assign { } { } assign { } { } assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:162230.5-162230.29" + attribute \src "libresoc.v:162026.5-162026.29" switch \initial - attribute \src "libresoc.v:162230.9-162230.17" + attribute \src "libresoc.v:162026.9-162026.17" case 1'1 case end @@ -301835,14 +301669,14 @@ module \pimem sync always update \st_done_r_st_done $0\st_done_r_st_done[0:0] end - attribute \src "libresoc.v:162239.3-162247.6" - process $proc$libresoc.v:162239$8613 + attribute \src "libresoc.v:162035.3-162043.6" + process $proc$libresoc.v:162035$8613 assign { } { } assign { } { } assign $0\busy_delay$next[0:0]$8614 $1\busy_delay$next[0:0]$8615 - attribute \src "libresoc.v:162240.5-162240.29" + attribute \src "libresoc.v:162036.5-162036.29" switch \initial - attribute \src "libresoc.v:162240.9-162240.17" + attribute \src "libresoc.v:162036.9-162036.17" case 1'1 case end @@ -301858,14 +301692,14 @@ module \pimem sync always update \busy_delay$next $0\busy_delay$next[0:0]$8614 end - attribute \src "libresoc.v:162248.3-162257.6" - process $proc$libresoc.v:162248$8616 + attribute \src "libresoc.v:162044.3-162053.6" + process $proc$libresoc.v:162044$8616 assign { } { } assign { } { } assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:162249.5-162249.29" + attribute \src "libresoc.v:162045.5-162045.29" switch \initial - attribute \src "libresoc.v:162249.9-162249.17" + attribute \src "libresoc.v:162045.9-162045.17" case 1'1 case end @@ -301881,15 +301715,15 @@ module \pimem sync always update \st_active_r_st_active $0\st_active_r_st_active[0:0] end - attribute \src "libresoc.v:162258.3-162273.6" - process $proc$libresoc.v:162258$8617 + attribute \src "libresoc.v:162054.3-162069.6" + process $proc$libresoc.v:162054$8617 assign { } { } assign { } { } assign { } { } assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:162259.5-162259.29" + attribute \src "libresoc.v:162055.5-162055.29" switch \initial - attribute \src "libresoc.v:162259.9-162259.17" + attribute \src "libresoc.v:162055.9-162055.17" case 1'1 case end @@ -301914,15 +301748,15 @@ module \pimem sync always update \lenexp_len_i $0\lenexp_len_i[3:0] end - attribute \src "libresoc.v:162274.3-162289.6" - process $proc$libresoc.v:162274$8618 + attribute \src "libresoc.v:162070.3-162085.6" + process $proc$libresoc.v:162070$8618 assign { } { } assign { } { } assign { } { } assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:162275.5-162275.29" + attribute \src "libresoc.v:162071.5-162071.29" switch \initial - attribute \src "libresoc.v:162275.9-162275.17" + attribute \src "libresoc.v:162071.9-162071.17" case 1'1 case end @@ -301947,15 +301781,15 @@ module \pimem sync always update \lenexp_addr_i $0\lenexp_addr_i[3:0] end - attribute \src "libresoc.v:162290.3-162315.6" - process $proc$libresoc.v:162290$8619 + attribute \src "libresoc.v:162086.3-162111.6" + process $proc$libresoc.v:162086$8619 assign { } { } assign { } { } assign { } { } assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:162291.5-162291.29" + attribute \src "libresoc.v:162087.5-162087.29" switch \initial - attribute \src "libresoc.v:162291.9-162291.17" + attribute \src "libresoc.v:162087.9-162087.17" case 1'1 case end @@ -301998,15 +301832,15 @@ module \pimem sync always update \valid_l_s_valid $0\valid_l_s_valid[0:0] end - attribute \src "libresoc.v:162316.3-162341.6" - process $proc$libresoc.v:162316$8620 + attribute \src "libresoc.v:162112.3-162137.6" + process $proc$libresoc.v:162112$8620 assign { } { } assign { } { } assign { } { } assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "libresoc.v:162317.5-162317.29" + attribute \src "libresoc.v:162113.5-162113.29" switch \initial - attribute \src "libresoc.v:162317.9-162317.17" + attribute \src "libresoc.v:162113.9-162113.17" case 1'1 case end @@ -302049,15 +301883,15 @@ module \pimem sync always update \x_mask_i $0\x_mask_i[7:0] end - attribute \src "libresoc.v:162342.3-162367.6" - process $proc$libresoc.v:162342$8621 + attribute \src "libresoc.v:162138.3-162163.6" + process $proc$libresoc.v:162138$8621 assign { } { } assign { } { } assign { } { } assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "libresoc.v:162343.5-162343.29" + attribute \src "libresoc.v:162139.5-162139.29" switch \initial - attribute \src "libresoc.v:162343.9-162343.17" + attribute \src "libresoc.v:162139.9-162139.17" case 1'1 case end @@ -302100,15 +301934,15 @@ module \pimem sync always update \x_addr_i $0\x_addr_i[47:0] end - attribute \src "libresoc.v:162368.3-162398.6" - process $proc$libresoc.v:162368$8622 + attribute \src "libresoc.v:162164.3-162194.6" + process $proc$libresoc.v:162164$8622 assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:162369.5-162369.29" + attribute \src "libresoc.v:162165.5-162165.29" switch \initial - attribute \src "libresoc.v:162369.9-162369.17" + attribute \src "libresoc.v:162165.9-162165.17" case 1'1 case end @@ -302160,15 +301994,15 @@ module \pimem sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:162399.3-162414.6" - process $proc$libresoc.v:162399$8623 + attribute \src "libresoc.v:162195.3-162210.6" + process $proc$libresoc.v:162195$8623 assign { } { } assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:162400.5-162400.29" + attribute \src "libresoc.v:162196.5-162196.29" switch \initial - attribute \src "libresoc.v:162400.9-162400.17" + attribute \src "libresoc.v:162196.9-162196.17" case 1'1 case end @@ -302193,14 +302027,14 @@ module \pimem sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:162415.3-162424.6" - process $proc$libresoc.v:162415$8624 + attribute \src "libresoc.v:162211.3-162220.6" + process $proc$libresoc.v:162211$8624 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:162416.5-162416.29" + attribute \src "libresoc.v:162212.5-162212.29" switch \initial - attribute \src "libresoc.v:162416.9-162416.17" + attribute \src "libresoc.v:162212.9-162212.17" case 1'1 case end @@ -302216,14 +302050,14 @@ module \pimem sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:162425.3-162434.6" - process $proc$libresoc.v:162425$8625 + attribute \src "libresoc.v:162221.3-162230.6" + process $proc$libresoc.v:162221$8625 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:162426.5-162426.29" + attribute \src "libresoc.v:162222.5-162222.29" switch \initial - attribute \src "libresoc.v:162426.9-162426.17" + attribute \src "libresoc.v:162222.9-162222.17" case 1'1 case end @@ -302239,14 +302073,14 @@ module \pimem sync always update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] end - attribute \src "libresoc.v:162435.3-162444.6" - process $proc$libresoc.v:162435$8626 + attribute \src "libresoc.v:162231.3-162240.6" + process $proc$libresoc.v:162231$8626 assign { } { } assign { } { } assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:162436.5-162436.29" + attribute \src "libresoc.v:162232.5-162232.29" switch \initial - attribute \src "libresoc.v:162436.9-162436.17" + attribute \src "libresoc.v:162232.9-162232.17" case 1'1 case end @@ -302262,14 +302096,14 @@ module \pimem sync always update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] end - attribute \src "libresoc.v:162445.3-162454.6" - process $proc$libresoc.v:162445$8627 + attribute \src "libresoc.v:162241.3-162250.6" + process $proc$libresoc.v:162241$8627 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:162446.5-162446.29" + attribute \src "libresoc.v:162242.5-162242.29" switch \initial - attribute \src "libresoc.v:162446.9-162446.17" + attribute \src "libresoc.v:162242.9-162242.17" case 1'1 case end @@ -302285,14 +302119,14 @@ module \pimem sync always update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:162455.3-162464.6" - process $proc$libresoc.v:162455$8628 + attribute \src "libresoc.v:162251.3-162260.6" + process $proc$libresoc.v:162251$8628 assign { } { } assign { } { } assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "libresoc.v:162456.5-162456.29" + attribute \src "libresoc.v:162252.5-162252.29" switch \initial - attribute \src "libresoc.v:162456.9-162456.17" + attribute \src "libresoc.v:162252.9-162252.17" case 1'1 case end @@ -302308,14 +302142,14 @@ module \pimem sync always update \stdata $0\stdata[63:0] end - attribute \src "libresoc.v:162465.3-162474.6" - process $proc$libresoc.v:162465$8629 + attribute \src "libresoc.v:162261.3-162270.6" + process $proc$libresoc.v:162261$8629 assign { } { } assign { } { } assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "libresoc.v:162466.5-162466.29" + attribute \src "libresoc.v:162262.5-162262.29" switch \initial - attribute \src "libresoc.v:162466.9-162466.17" + attribute \src "libresoc.v:162262.9-162262.17" case 1'1 case end @@ -302331,14 +302165,14 @@ module \pimem sync always update \x_st_data_i $0\x_st_data_i[63:0] end - attribute \src "libresoc.v:162475.3-162494.6" - process $proc$libresoc.v:162475$8630 + attribute \src "libresoc.v:162271.3-162290.6" + process $proc$libresoc.v:162271$8630 assign { } { } assign { } { } assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "libresoc.v:162476.5-162476.29" + attribute \src "libresoc.v:162272.5-162272.29" switch \initial - attribute \src "libresoc.v:162476.9-162476.17" + attribute \src "libresoc.v:162272.9-162272.17" case 1'1 case end @@ -302367,15 +302201,15 @@ module \pimem sync always update \lsui_busy $0\lsui_busy[0:0] end - attribute \src "libresoc.v:162495.3-162533.6" - process $proc$libresoc.v:162495$8631 + attribute \src "libresoc.v:162291.3-162329.6" + process $proc$libresoc.v:162291$8631 assign { } { } assign { } { } assign { } { } assign $0\fsm_state$next[1:0]$8632 $5\fsm_state$next[1:0]$8637 - attribute \src "libresoc.v:162496.5-162496.29" + attribute \src "libresoc.v:162292.5-162292.29" switch \initial - attribute \src "libresoc.v:162496.9-162496.17" + attribute \src "libresoc.v:162292.9-162292.17" case 1'1 case end @@ -302435,14 +302269,14 @@ module \pimem sync always update \fsm_state$next $0\fsm_state$next[1:0]$8632 end - attribute \src "libresoc.v:162534.3-162543.6" - process $proc$libresoc.v:162534$8638 + attribute \src "libresoc.v:162330.3-162339.6" + process $proc$libresoc.v:162330$8638 assign { } { } assign { } { } assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:162535.5-162535.29" + attribute \src "libresoc.v:162331.5-162331.29" switch \initial - attribute \src "libresoc.v:162535.9-162535.17" + attribute \src "libresoc.v:162331.9-162331.17" case 1'1 case end @@ -302458,14 +302292,14 @@ module \pimem sync always update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] end - attribute \src "libresoc.v:162544.3-162552.6" - process $proc$libresoc.v:162544$8639 + attribute \src "libresoc.v:162340.3-162348.6" + process $proc$libresoc.v:162340$8639 assign { } { } assign { } { } assign $0\lsui_active_dly$next[0:0]$8640 $1\lsui_active_dly$next[0:0]$8641 - attribute \src "libresoc.v:162545.5-162545.29" + attribute \src "libresoc.v:162341.5-162341.29" switch \initial - attribute \src "libresoc.v:162545.9-162545.17" + attribute \src "libresoc.v:162341.9-162341.17" case 1'1 case end @@ -302481,14 +302315,14 @@ module \pimem sync always update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8640 end - attribute \src "libresoc.v:162553.3-162562.6" - process $proc$libresoc.v:162553$8642 + attribute \src "libresoc.v:162349.3-162358.6" + process $proc$libresoc.v:162349$8642 assign { } { } assign { } { } assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:162554.5-162554.29" + attribute \src "libresoc.v:162350.5-162350.29" switch \initial - attribute \src "libresoc.v:162554.9-162554.17" + attribute \src "libresoc.v:162350.9-162350.17" case 1'1 case end @@ -302504,14 +302338,14 @@ module \pimem sync always update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] end - attribute \src "libresoc.v:162563.3-162572.6" - process $proc$libresoc.v:162563$8643 + attribute \src "libresoc.v:162359.3-162368.6" + process $proc$libresoc.v:162359$8643 assign { } { } assign { } { } assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:162564.5-162564.29" + attribute \src "libresoc.v:162360.5-162360.29" switch \initial - attribute \src "libresoc.v:162564.9-162564.17" + attribute \src "libresoc.v:162360.9-162360.17" case 1'1 case end @@ -302527,15 +302361,15 @@ module \pimem sync always update \busy_l_s_busy $0\busy_l_s_busy[0:0] end - attribute \src "libresoc.v:162573.3-162588.6" - process $proc$libresoc.v:162573$8644 + attribute \src "libresoc.v:162369.3-162384.6" + process $proc$libresoc.v:162369$8644 assign { } { } assign { } { } assign { } { } assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:162574.5-162574.29" + attribute \src "libresoc.v:162370.5-162370.29" switch \initial - attribute \src "libresoc.v:162574.9-162574.17" + attribute \src "libresoc.v:162370.9-162370.17" case 1'1 case end @@ -302560,16 +302394,16 @@ module \pimem sync always update \busy_l_r_busy $0\busy_l_r_busy[0:0] end - attribute \src "libresoc.v:162589.3-162624.6" - process $proc$libresoc.v:162589$8645 + attribute \src "libresoc.v:162385.3-162420.6" + process $proc$libresoc.v:162385$8645 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\adrok_l_s_addr_acked$next[0:0]$8646 $6\adrok_l_s_addr_acked$next[0:0]$8652 - attribute \src "libresoc.v:162590.5-162590.29" + attribute \src "libresoc.v:162386.5-162386.29" switch \initial - attribute \src "libresoc.v:162590.9-162590.17" + attribute \src "libresoc.v:162386.9-162386.17" case 1'1 case end @@ -302630,15 +302464,15 @@ module \pimem sync always update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8646 end - attribute \src "libresoc.v:162625.3-162640.6" - process $proc$libresoc.v:162625$8653 + attribute \src "libresoc.v:162421.3-162436.6" + process $proc$libresoc.v:162421$8653 assign { } { } assign { } { } assign { } { } assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:162626.5-162626.29" + attribute \src "libresoc.v:162422.5-162422.29" switch \initial - attribute \src "libresoc.v:162626.9-162626.17" + attribute \src "libresoc.v:162422.9-162422.17" case 1'1 case end @@ -302663,47 +302497,47 @@ module \pimem sync always update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] end - connect \$9 $not$libresoc.v:162094$8557_Y - connect \$11 $and$libresoc.v:162095$8558_Y - connect \$13 $not$libresoc.v:162096$8559_Y - connect \$15 $and$libresoc.v:162097$8560_Y - connect \$17 $not$libresoc.v:162098$8561_Y - connect \$1 $and$libresoc.v:162099$8562_Y - connect \$19 $and$libresoc.v:162100$8563_Y - connect \$21 $pos$libresoc.v:162101$8565_Y - connect \$23 $pos$libresoc.v:162102$8567_Y - connect \$25 $and$libresoc.v:162103$8568_Y - connect \$27 $and$libresoc.v:162104$8569_Y - connect \$29 $and$libresoc.v:162105$8570_Y - connect \$31 $and$libresoc.v:162106$8571_Y - connect \$33 $and$libresoc.v:162107$8572_Y - connect \$35 $not$libresoc.v:162108$8573_Y - connect \$38 $or$libresoc.v:162109$8574_Y - connect \$3 $or$libresoc.v:162110$8575_Y - connect \$37 $not$libresoc.v:162111$8576_Y - connect \$42 $and$libresoc.v:162112$8577_Y - connect \$44 $mul$libresoc.v:162113$8578_Y - connect \$46 $sshr$libresoc.v:162114$8579_Y - connect \$48 $and$libresoc.v:162115$8580_Y - connect \$50 $and$libresoc.v:162116$8581_Y - connect \$52 $not$libresoc.v:162117$8582_Y - connect \$54 $and$libresoc.v:162118$8583_Y - connect \$57 $mul$libresoc.v:162119$8584_Y - connect \$5 $not$libresoc.v:162120$8585_Y - connect \$59 $sshl$libresoc.v:162121$8586_Y - connect \$61 $and$libresoc.v:162122$8587_Y - connect \$63 $or$libresoc.v:162123$8588_Y - connect \$65 $and$libresoc.v:162124$8589_Y - connect \$67 $or$libresoc.v:162125$8590_Y - connect \$69 $and$libresoc.v:162126$8591_Y - connect \$71 $not$libresoc.v:162127$8592_Y - connect \$73 $not$libresoc.v:162128$8593_Y - connect \$75 $not$libresoc.v:162129$8594_Y - connect \$77 $and$libresoc.v:162130$8595_Y - connect \$7 $and$libresoc.v:162131$8596_Y - connect \$79 $not$libresoc.v:162132$8597_Y - connect \$81 $not$libresoc.v:162133$8598_Y - connect \$83 $and$libresoc.v:162134$8599_Y + connect \$9 $not$libresoc.v:161890$8557_Y + connect \$11 $and$libresoc.v:161891$8558_Y + connect \$13 $not$libresoc.v:161892$8559_Y + connect \$15 $and$libresoc.v:161893$8560_Y + connect \$17 $not$libresoc.v:161894$8561_Y + connect \$1 $and$libresoc.v:161895$8562_Y + connect \$19 $and$libresoc.v:161896$8563_Y + connect \$21 $pos$libresoc.v:161897$8565_Y + connect \$23 $pos$libresoc.v:161898$8567_Y + connect \$25 $and$libresoc.v:161899$8568_Y + connect \$27 $and$libresoc.v:161900$8569_Y + connect \$29 $and$libresoc.v:161901$8570_Y + connect \$31 $and$libresoc.v:161902$8571_Y + connect \$33 $and$libresoc.v:161903$8572_Y + connect \$35 $not$libresoc.v:161904$8573_Y + connect \$38 $or$libresoc.v:161905$8574_Y + connect \$3 $or$libresoc.v:161906$8575_Y + connect \$37 $not$libresoc.v:161907$8576_Y + connect \$42 $and$libresoc.v:161908$8577_Y + connect \$44 $mul$libresoc.v:161909$8578_Y + connect \$46 $sshr$libresoc.v:161910$8579_Y + connect \$48 $and$libresoc.v:161911$8580_Y + connect \$50 $and$libresoc.v:161912$8581_Y + connect \$52 $not$libresoc.v:161913$8582_Y + connect \$54 $and$libresoc.v:161914$8583_Y + connect \$57 $mul$libresoc.v:161915$8584_Y + connect \$5 $not$libresoc.v:161916$8585_Y + connect \$59 $sshl$libresoc.v:161917$8586_Y + connect \$61 $and$libresoc.v:161918$8587_Y + connect \$63 $or$libresoc.v:161919$8588_Y + connect \$65 $and$libresoc.v:161920$8589_Y + connect \$67 $or$libresoc.v:161921$8590_Y + connect \$69 $and$libresoc.v:161922$8591_Y + connect \$71 $not$libresoc.v:161923$8592_Y + connect \$73 $not$libresoc.v:161924$8593_Y + connect \$75 $not$libresoc.v:161925$8594_Y + connect \$77 $and$libresoc.v:161926$8595_Y + connect \$7 $and$libresoc.v:161927$8596_Y + connect \$79 $not$libresoc.v:161928$8597_Y + connect \$81 $not$libresoc.v:161929$8598_Y + connect \$83 $and$libresoc.v:161930$8599_Y connect \$41 \$46 connect \$56 \$59 connect \valid_l_r_valid \lsui_active_rise @@ -302726,116 +302560,116 @@ module \pimem connect \sts \ldst_port0_is_st_i connect \lds \ldst_port0_is_ld_i end -attribute \src "libresoc.v:162666.1-163446.10" +attribute \src "libresoc.v:162462.1-163242.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" attribute \generator "nMigen" module \pipe - attribute \src "libresoc.v:163409.3-163427.6" + attribute \src "libresoc.v:163205.3-163223.6" wire width 4 $0\cr_a$6$next[3:0]$8709 - attribute \src "libresoc.v:163273.3-163274.31" + attribute \src "libresoc.v:163069.3-163070.31" wire width 4 $0\cr_a$6[3:0]$8665 - attribute \src "libresoc.v:162680.13-162680.28" + attribute \src "libresoc.v:162476.13-162476.28" wire width 4 $0\cr_a$6[3:0]$8715 - attribute \src "libresoc.v:163409.3-163427.6" + attribute \src "libresoc.v:163205.3-163223.6" wire $0\cr_a_ok$next[0:0]$8708 - attribute \src "libresoc.v:163275.3-163276.31" + attribute \src "libresoc.v:163071.3-163072.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:163356.3-163370.6" + attribute \src "libresoc.v:163152.3-163166.6" wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8689 - attribute \src "libresoc.v:163287.3-163288.51" + attribute \src "libresoc.v:163083.3-163084.51" wire width 14 $0\cr_op__fn_unit$3[13:0]$8675 - attribute \src "libresoc.v:162745.14-162745.43" + attribute \src "libresoc.v:162541.14-162541.43" wire width 14 $0\cr_op__fn_unit$3[13:0]$8718 - attribute \src "libresoc.v:163356.3-163370.6" + attribute \src "libresoc.v:163152.3-163166.6" wire width 32 $0\cr_op__insn$4$next[31:0]$8690 - attribute \src "libresoc.v:163289.3-163290.45" + attribute \src "libresoc.v:163085.3-163086.45" wire width 32 $0\cr_op__insn$4[31:0]$8677 - attribute \src "libresoc.v:162754.14-162754.37" + attribute \src "libresoc.v:162550.14-162550.37" wire width 32 $0\cr_op__insn$4[31:0]$8720 - attribute \src "libresoc.v:163356.3-163370.6" + attribute \src "libresoc.v:163152.3-163166.6" wire width 7 $0\cr_op__insn_type$2$next[6:0]$8691 - attribute \src "libresoc.v:163285.3-163286.55" + attribute \src "libresoc.v:163081.3-163082.55" wire width 7 $0\cr_op__insn_type$2[6:0]$8673 - attribute \src "libresoc.v:162988.13-162988.41" + attribute \src "libresoc.v:162784.13-162784.41" wire width 7 $0\cr_op__insn_type$2[6:0]$8722 - attribute \src "libresoc.v:163390.3-163408.6" + attribute \src "libresoc.v:163186.3-163204.6" wire width 32 $0\full_cr$5$next[31:0]$8702 - attribute \src "libresoc.v:163277.3-163278.37" + attribute \src "libresoc.v:163073.3-163074.37" wire width 32 $0\full_cr$5[31:0]$8668 - attribute \src "libresoc.v:162997.14-162997.33" + attribute \src "libresoc.v:162793.14-162793.33" wire width 32 $0\full_cr$5[31:0]$8724 - attribute \src "libresoc.v:163390.3-163408.6" + attribute \src "libresoc.v:163186.3-163204.6" wire $0\full_cr_ok$next[0:0]$8703 - attribute \src "libresoc.v:163279.3-163280.37" + attribute \src "libresoc.v:163075.3-163076.37" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:162667.7-162667.20" + attribute \src "libresoc.v:162463.7-162463.20" wire $0\initial[0:0] - attribute \src "libresoc.v:163343.3-163355.6" + attribute \src "libresoc.v:163139.3-163151.6" wire width 2 $0\muxid$1$next[1:0]$8686 - attribute \src "libresoc.v:163291.3-163292.33" + attribute \src "libresoc.v:163087.3-163088.33" wire width 2 $0\muxid$1[1:0]$8679 - attribute \src "libresoc.v:163231.13-163231.29" + attribute \src "libresoc.v:163027.13-163027.29" wire width 2 $0\muxid$1[1:0]$8727 - attribute \src "libresoc.v:163371.3-163389.6" + attribute \src "libresoc.v:163167.3-163185.6" wire width 64 $0\o$next[63:0]$8696 - attribute \src "libresoc.v:163281.3-163282.19" + attribute \src "libresoc.v:163077.3-163078.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:163371.3-163389.6" + attribute \src "libresoc.v:163167.3-163185.6" wire $0\o_ok$next[0:0]$8697 - attribute \src "libresoc.v:163283.3-163284.25" + attribute \src "libresoc.v:163079.3-163080.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:163325.3-163342.6" + attribute \src "libresoc.v:163121.3-163138.6" wire $0\r_busy$next[0:0]$8682 - attribute \src "libresoc.v:163293.3-163294.29" + attribute \src "libresoc.v:163089.3-163090.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:163409.3-163427.6" + attribute \src "libresoc.v:163205.3-163223.6" wire width 4 $1\cr_a$6$next[3:0]$8711 - attribute \src "libresoc.v:163409.3-163427.6" + attribute \src "libresoc.v:163205.3-163223.6" wire $1\cr_a_ok$next[0:0]$8710 - attribute \src "libresoc.v:162685.7-162685.21" + attribute \src "libresoc.v:162481.7-162481.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:163356.3-163370.6" + attribute \src "libresoc.v:163152.3-163166.6" wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8692 - attribute \src "libresoc.v:163356.3-163370.6" + attribute \src "libresoc.v:163152.3-163166.6" wire width 32 $1\cr_op__insn$4$next[31:0]$8693 - attribute \src "libresoc.v:163356.3-163370.6" + attribute \src "libresoc.v:163152.3-163166.6" wire width 7 $1\cr_op__insn_type$2$next[6:0]$8694 - attribute \src "libresoc.v:163390.3-163408.6" + attribute \src "libresoc.v:163186.3-163204.6" wire width 32 $1\full_cr$5$next[31:0]$8704 - attribute \src "libresoc.v:163390.3-163408.6" + attribute \src "libresoc.v:163186.3-163204.6" wire $1\full_cr_ok$next[0:0]$8705 - attribute \src "libresoc.v:163002.7-163002.24" + attribute \src "libresoc.v:162798.7-162798.24" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:163343.3-163355.6" + attribute \src "libresoc.v:163139.3-163151.6" wire width 2 $1\muxid$1$next[1:0]$8687 - attribute \src "libresoc.v:163371.3-163389.6" + attribute \src "libresoc.v:163167.3-163185.6" wire width 64 $1\o$next[63:0]$8698 - attribute \src "libresoc.v:163244.14-163244.38" + attribute \src "libresoc.v:163040.14-163040.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:163371.3-163389.6" + attribute \src "libresoc.v:163167.3-163185.6" wire $1\o_ok$next[0:0]$8699 - attribute \src "libresoc.v:163251.7-163251.18" + attribute \src "libresoc.v:163047.7-163047.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:163325.3-163342.6" + attribute \src "libresoc.v:163121.3-163138.6" wire $1\r_busy$next[0:0]$8683 - attribute \src "libresoc.v:163265.7-163265.20" + attribute \src "libresoc.v:163061.7-163061.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:163409.3-163427.6" + attribute \src "libresoc.v:163205.3-163223.6" wire $2\cr_a_ok$next[0:0]$8712 - attribute \src "libresoc.v:163390.3-163408.6" + attribute \src "libresoc.v:163186.3-163204.6" wire $2\full_cr_ok$next[0:0]$8706 - attribute \src "libresoc.v:163371.3-163389.6" + attribute \src "libresoc.v:163167.3-163185.6" wire $2\o_ok$next[0:0]$8700 - attribute \src "libresoc.v:163325.3-163342.6" + attribute \src "libresoc.v:163121.3-163138.6" wire $2\r_busy$next[0:0]$8684 - attribute \src "libresoc.v:163272.18-163272.118" - wire $and$libresoc.v:163272$8663_Y + attribute \src "libresoc.v:163068.18-163068.118" + wire $and$libresoc.v:163068$8663_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 11 \cr_a @@ -303163,7 +302997,7 @@ module \pipe wire \full_cr_ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \full_cr_ok$next - attribute \src "libresoc.v:162667.7-162667.15" + attribute \src "libresoc.v:162463.7-162463.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_a @@ -303428,7 +303262,7 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:163272$8663 + cell $and $and$libresoc.v:163068$8663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303436,10 +303270,10 @@ module \pipe parameter \Y_WIDTH 1 connect \A \p_valid_i$13 connect \B \p_ready_o - connect \Y $and$libresoc.v:163272$8663_Y + connect \Y $and$libresoc.v:163068$8663_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:163295.12-163316.4" + attribute \src "libresoc.v:163091.12-163112.4" cell \main$9 \main connect \cr_a \main_cr_a connect \cr_a$6 \main_cr_a$12 @@ -303463,199 +303297,199 @@ module \pipe connect \rb \main_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:163317.9-163320.4" + attribute \src "libresoc.v:163113.9-163116.4" cell \n$8 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:163321.9-163324.4" + attribute \src "libresoc.v:163117.9-163120.4" cell \p$7 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:162667.7-162667.20" - process $proc$libresoc.v:162667$8713 + attribute \src "libresoc.v:162463.7-162463.20" + process $proc$libresoc.v:162463$8713 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:162680.13-162680.28" - process $proc$libresoc.v:162680$8714 + attribute \src "libresoc.v:162476.13-162476.28" + process $proc$libresoc.v:162476$8714 assign { } { } assign $0\cr_a$6[3:0]$8715 4'0000 sync always sync init update \cr_a$6 $0\cr_a$6[3:0]$8715 end - attribute \src "libresoc.v:162685.7-162685.21" - process $proc$libresoc.v:162685$8716 + attribute \src "libresoc.v:162481.7-162481.21" + process $proc$libresoc.v:162481$8716 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:162745.14-162745.43" - process $proc$libresoc.v:162745$8717 + attribute \src "libresoc.v:162541.14-162541.43" + process $proc$libresoc.v:162541$8717 assign { } { } assign $0\cr_op__fn_unit$3[13:0]$8718 14'00000000000000 sync always sync init update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8718 end - attribute \src "libresoc.v:162754.14-162754.37" - process $proc$libresoc.v:162754$8719 + attribute \src "libresoc.v:162550.14-162550.37" + process $proc$libresoc.v:162550$8719 assign { } { } assign $0\cr_op__insn$4[31:0]$8720 0 sync always sync init update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8720 end - attribute \src "libresoc.v:162988.13-162988.41" - process $proc$libresoc.v:162988$8721 + attribute \src "libresoc.v:162784.13-162784.41" + process $proc$libresoc.v:162784$8721 assign { } { } assign $0\cr_op__insn_type$2[6:0]$8722 7'0000000 sync always sync init update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8722 end - attribute \src "libresoc.v:162997.14-162997.33" - process $proc$libresoc.v:162997$8723 + attribute \src "libresoc.v:162793.14-162793.33" + process $proc$libresoc.v:162793$8723 assign { } { } assign $0\full_cr$5[31:0]$8724 0 sync always sync init update \full_cr$5 $0\full_cr$5[31:0]$8724 end - attribute \src "libresoc.v:163002.7-163002.24" - process $proc$libresoc.v:163002$8725 + attribute \src "libresoc.v:162798.7-162798.24" + process $proc$libresoc.v:162798$8725 assign { } { } assign $1\full_cr_ok[0:0] 1'0 sync always sync init update \full_cr_ok $1\full_cr_ok[0:0] end - attribute \src "libresoc.v:163231.13-163231.29" - process $proc$libresoc.v:163231$8726 + attribute \src "libresoc.v:163027.13-163027.29" + process $proc$libresoc.v:163027$8726 assign { } { } assign $0\muxid$1[1:0]$8727 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8727 end - attribute \src "libresoc.v:163244.14-163244.38" - process $proc$libresoc.v:163244$8728 + attribute \src "libresoc.v:163040.14-163040.38" + process $proc$libresoc.v:163040$8728 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:163251.7-163251.18" - process $proc$libresoc.v:163251$8729 + attribute \src "libresoc.v:163047.7-163047.18" + process $proc$libresoc.v:163047$8729 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:163265.7-163265.20" - process $proc$libresoc.v:163265$8730 + attribute \src "libresoc.v:163061.7-163061.20" + process $proc$libresoc.v:163061$8730 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:163273.3-163274.31" - process $proc$libresoc.v:163273$8664 + attribute \src "libresoc.v:163069.3-163070.31" + process $proc$libresoc.v:163069$8664 assign { } { } assign $0\cr_a$6[3:0]$8665 \cr_a$6$next sync posedge \coresync_clk update \cr_a$6 $0\cr_a$6[3:0]$8665 end - attribute \src "libresoc.v:163275.3-163276.31" - process $proc$libresoc.v:163275$8666 + attribute \src "libresoc.v:163071.3-163072.31" + process $proc$libresoc.v:163071$8666 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:163277.3-163278.37" - process $proc$libresoc.v:163277$8667 + attribute \src "libresoc.v:163073.3-163074.37" + process $proc$libresoc.v:163073$8667 assign { } { } assign $0\full_cr$5[31:0]$8668 \full_cr$5$next sync posedge \coresync_clk update \full_cr$5 $0\full_cr$5[31:0]$8668 end - attribute \src "libresoc.v:163279.3-163280.37" - process $proc$libresoc.v:163279$8669 + attribute \src "libresoc.v:163075.3-163076.37" + process $proc$libresoc.v:163075$8669 assign { } { } assign $0\full_cr_ok[0:0] \full_cr_ok$next sync posedge \coresync_clk update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:163281.3-163282.19" - process $proc$libresoc.v:163281$8670 + attribute \src "libresoc.v:163077.3-163078.19" + process $proc$libresoc.v:163077$8670 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:163283.3-163284.25" - process $proc$libresoc.v:163283$8671 + attribute \src "libresoc.v:163079.3-163080.25" + process $proc$libresoc.v:163079$8671 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:163285.3-163286.55" - process $proc$libresoc.v:163285$8672 + attribute \src "libresoc.v:163081.3-163082.55" + process $proc$libresoc.v:163081$8672 assign { } { } assign $0\cr_op__insn_type$2[6:0]$8673 \cr_op__insn_type$2$next sync posedge \coresync_clk update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8673 end - attribute \src "libresoc.v:163287.3-163288.51" - process $proc$libresoc.v:163287$8674 + attribute \src "libresoc.v:163083.3-163084.51" + process $proc$libresoc.v:163083$8674 assign { } { } assign $0\cr_op__fn_unit$3[13:0]$8675 \cr_op__fn_unit$3$next sync posedge \coresync_clk update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8675 end - attribute \src "libresoc.v:163289.3-163290.45" - process $proc$libresoc.v:163289$8676 + attribute \src "libresoc.v:163085.3-163086.45" + process $proc$libresoc.v:163085$8676 assign { } { } assign $0\cr_op__insn$4[31:0]$8677 \cr_op__insn$4$next sync posedge \coresync_clk update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8677 end - attribute \src "libresoc.v:163291.3-163292.33" - process $proc$libresoc.v:163291$8678 + attribute \src "libresoc.v:163087.3-163088.33" + process $proc$libresoc.v:163087$8678 assign { } { } assign $0\muxid$1[1:0]$8679 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8679 end - attribute \src "libresoc.v:163293.3-163294.29" - process $proc$libresoc.v:163293$8680 + attribute \src "libresoc.v:163089.3-163090.29" + process $proc$libresoc.v:163089$8680 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:163325.3-163342.6" - process $proc$libresoc.v:163325$8681 + attribute \src "libresoc.v:163121.3-163138.6" + process $proc$libresoc.v:163121$8681 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8682 $2\r_busy$next[0:0]$8684 - attribute \src "libresoc.v:163326.5-163326.29" + attribute \src "libresoc.v:163122.5-163122.29" switch \initial - attribute \src "libresoc.v:163326.9-163326.17" + attribute \src "libresoc.v:163122.9-163122.17" case 1'1 case end @@ -303684,14 +303518,14 @@ module \pipe sync always update \r_busy$next $0\r_busy$next[0:0]$8682 end - attribute \src "libresoc.v:163343.3-163355.6" - process $proc$libresoc.v:163343$8685 + attribute \src "libresoc.v:163139.3-163151.6" + process $proc$libresoc.v:163139$8685 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8686 $1\muxid$1$next[1:0]$8687 - attribute \src "libresoc.v:163344.5-163344.29" + attribute \src "libresoc.v:163140.5-163140.29" switch \initial - attribute \src "libresoc.v:163344.9-163344.17" + attribute \src "libresoc.v:163140.9-163140.17" case 1'1 case end @@ -303711,8 +303545,8 @@ module \pipe sync always update \muxid$1$next $0\muxid$1$next[1:0]$8686 end - attribute \src "libresoc.v:163356.3-163370.6" - process $proc$libresoc.v:163356$8688 + attribute \src "libresoc.v:163152.3-163166.6" + process $proc$libresoc.v:163152$8688 assign { } { } assign { } { } assign { } { } @@ -303722,9 +303556,9 @@ module \pipe assign $0\cr_op__fn_unit$3$next[13:0]$8689 $1\cr_op__fn_unit$3$next[13:0]$8692 assign $0\cr_op__insn$4$next[31:0]$8690 $1\cr_op__insn$4$next[31:0]$8693 assign $0\cr_op__insn_type$2$next[6:0]$8691 $1\cr_op__insn_type$2$next[6:0]$8694 - attribute \src "libresoc.v:163357.5-163357.29" + attribute \src "libresoc.v:163153.5-163153.29" switch \initial - attribute \src "libresoc.v:163357.9-163357.17" + attribute \src "libresoc.v:163153.9-163153.17" case 1'1 case end @@ -303752,8 +303586,8 @@ module \pipe update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8690 update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8691 end - attribute \src "libresoc.v:163371.3-163389.6" - process $proc$libresoc.v:163371$8695 + attribute \src "libresoc.v:163167.3-163185.6" + process $proc$libresoc.v:163167$8695 assign { } { } assign { } { } assign { } { } @@ -303761,9 +303595,9 @@ module \pipe assign $0\o$next[63:0]$8696 $1\o$next[63:0]$8698 assign { } { } assign $0\o_ok$next[0:0]$8697 $2\o_ok$next[0:0]$8700 - attribute \src "libresoc.v:163372.5-163372.29" + attribute \src "libresoc.v:163168.5-163168.29" switch \initial - attribute \src "libresoc.v:163372.9-163372.17" + attribute \src "libresoc.v:163168.9-163168.17" case 1'1 case end @@ -303796,8 +303630,8 @@ module \pipe update \o$next $0\o$next[63:0]$8696 update \o_ok$next $0\o_ok$next[0:0]$8697 end - attribute \src "libresoc.v:163390.3-163408.6" - process $proc$libresoc.v:163390$8701 + attribute \src "libresoc.v:163186.3-163204.6" + process $proc$libresoc.v:163186$8701 assign { } { } assign { } { } assign { } { } @@ -303805,9 +303639,9 @@ module \pipe assign $0\full_cr$5$next[31:0]$8702 $1\full_cr$5$next[31:0]$8704 assign { } { } assign $0\full_cr_ok$next[0:0]$8703 $2\full_cr_ok$next[0:0]$8706 - attribute \src "libresoc.v:163391.5-163391.29" + attribute \src "libresoc.v:163187.5-163187.29" switch \initial - attribute \src "libresoc.v:163391.9-163391.17" + attribute \src "libresoc.v:163187.9-163187.17" case 1'1 case end @@ -303840,8 +303674,8 @@ module \pipe update \full_cr$5$next $0\full_cr$5$next[31:0]$8702 update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8703 end - attribute \src "libresoc.v:163409.3-163427.6" - process $proc$libresoc.v:163409$8707 + attribute \src "libresoc.v:163205.3-163223.6" + process $proc$libresoc.v:163205$8707 assign { } { } assign { } { } assign { } { } @@ -303849,9 +303683,9 @@ module \pipe assign { } { } assign $0\cr_a$6$next[3:0]$8709 $1\cr_a$6$next[3:0]$8711 assign $0\cr_a_ok$next[0:0]$8708 $2\cr_a_ok$next[0:0]$8712 - attribute \src "libresoc.v:163410.5-163410.29" + attribute \src "libresoc.v:163206.5-163206.29" switch \initial - attribute \src "libresoc.v:163410.9-163410.17" + attribute \src "libresoc.v:163206.9-163206.17" case 1'1 case end @@ -303884,7 +303718,7 @@ module \pipe update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8708 update \cr_a$6$next $0\cr_a$6$next[3:0]$8709 end - connect \$14 $and$libresoc.v:163272$8663_Y + connect \$14 $and$libresoc.v:163068$8663_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } @@ -303904,155 +303738,155 @@ module \pipe connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:163450.1-164310.10" +attribute \src "libresoc.v:163246.1-164106.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" attribute \generator "nMigen" module \pipe$19 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire width 64 $0\br_op__cia$2$next[63:0]$8767 - attribute \src "libresoc.v:164122.3-164123.43" + attribute \src "libresoc.v:163918.3-163919.43" wire width 64 $0\br_op__cia$2[63:0]$8741 - attribute \src "libresoc.v:163458.14-163458.51" + attribute \src "libresoc.v:163254.14-163254.51" wire width 64 $0\br_op__cia$2[63:0]$8805 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire width 14 $0\br_op__fn_unit$4$next[13:0]$8768 - attribute \src "libresoc.v:164126.3-164127.51" + attribute \src "libresoc.v:163922.3-163923.51" wire width 14 $0\br_op__fn_unit$4[13:0]$8745 - attribute \src "libresoc.v:163514.14-163514.43" + attribute \src "libresoc.v:163310.14-163310.43" wire width 14 $0\br_op__fn_unit$4[13:0]$8807 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8769 - attribute \src "libresoc.v:164130.3-164131.65" + attribute \src "libresoc.v:163926.3-163927.65" wire width 64 $0\br_op__imm_data__data$6[63:0]$8749 - attribute \src "libresoc.v:163523.14-163523.62" + attribute \src "libresoc.v:163319.14-163319.62" wire width 64 $0\br_op__imm_data__data$6[63:0]$8809 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire $0\br_op__imm_data__ok$7$next[0:0]$8770 - attribute \src "libresoc.v:164132.3-164133.61" + attribute \src "libresoc.v:163928.3-163929.61" wire $0\br_op__imm_data__ok$7[0:0]$8751 - attribute \src "libresoc.v:163532.7-163532.37" + attribute \src "libresoc.v:163328.7-163328.37" wire $0\br_op__imm_data__ok$7[0:0]$8811 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire width 32 $0\br_op__insn$5$next[31:0]$8771 - attribute \src "libresoc.v:164128.3-164129.45" + attribute \src "libresoc.v:163924.3-163925.45" wire width 32 $0\br_op__insn$5[31:0]$8747 - attribute \src "libresoc.v:163541.14-163541.37" + attribute \src "libresoc.v:163337.14-163337.37" wire width 32 $0\br_op__insn$5[31:0]$8813 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire width 7 $0\br_op__insn_type$3$next[6:0]$8772 - attribute \src "libresoc.v:164124.3-164125.55" + attribute \src "libresoc.v:163920.3-163921.55" wire width 7 $0\br_op__insn_type$3[6:0]$8743 - attribute \src "libresoc.v:163775.13-163775.41" + attribute \src "libresoc.v:163571.13-163571.41" wire width 7 $0\br_op__insn_type$3[6:0]$8815 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire $0\br_op__is_32bit$9$next[0:0]$8773 - attribute \src "libresoc.v:164136.3-164137.53" + attribute \src "libresoc.v:163932.3-163933.53" wire $0\br_op__is_32bit$9[0:0]$8755 - attribute \src "libresoc.v:163784.7-163784.33" + attribute \src "libresoc.v:163580.7-163580.33" wire $0\br_op__is_32bit$9[0:0]$8817 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire $0\br_op__lk$8$next[0:0]$8774 - attribute \src "libresoc.v:164134.3-164135.41" + attribute \src "libresoc.v:163930.3-163931.41" wire $0\br_op__lk$8[0:0]$8753 - attribute \src "libresoc.v:163793.7-163793.27" + attribute \src "libresoc.v:163589.7-163589.27" wire $0\br_op__lk$8[0:0]$8819 - attribute \src "libresoc.v:164238.3-164256.6" + attribute \src "libresoc.v:164034.3-164052.6" wire width 64 $0\fast1$10$next[63:0]$8786 - attribute \src "libresoc.v:164118.3-164119.35" + attribute \src "libresoc.v:163914.3-163915.35" wire width 64 $0\fast1$10[63:0]$8738 - attribute \src "libresoc.v:163806.14-163806.47" + attribute \src "libresoc.v:163602.14-163602.47" wire width 64 $0\fast1$10[63:0]$8821 - attribute \src "libresoc.v:164238.3-164256.6" + attribute \src "libresoc.v:164034.3-164052.6" wire $0\fast1_ok$next[0:0]$8787 - attribute \src "libresoc.v:164120.3-164121.33" + attribute \src "libresoc.v:163916.3-163917.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:164257.3-164275.6" + attribute \src "libresoc.v:164053.3-164071.6" wire width 64 $0\fast2$11$next[63:0]$8792 - attribute \src "libresoc.v:164114.3-164115.35" + attribute \src "libresoc.v:163910.3-163911.35" wire width 64 $0\fast2$11[63:0]$8735 - attribute \src "libresoc.v:163822.14-163822.47" + attribute \src "libresoc.v:163618.14-163618.47" wire width 64 $0\fast2$11[63:0]$8824 - attribute \src "libresoc.v:164257.3-164275.6" + attribute \src "libresoc.v:164053.3-164071.6" wire $0\fast2_ok$next[0:0]$8793 - attribute \src "libresoc.v:164116.3-164117.33" + attribute \src "libresoc.v:163912.3-163913.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:163451.7-163451.20" + attribute \src "libresoc.v:163247.7-163247.20" wire $0\initial[0:0] - attribute \src "libresoc.v:164197.3-164209.6" + attribute \src "libresoc.v:163993.3-164005.6" wire width 2 $0\muxid$1$next[1:0]$8764 - attribute \src "libresoc.v:164138.3-164139.33" + attribute \src "libresoc.v:163934.3-163935.33" wire width 2 $0\muxid$1[1:0]$8757 - attribute \src "libresoc.v:164072.13-164072.29" + attribute \src "libresoc.v:163868.13-163868.29" wire width 2 $0\muxid$1[1:0]$8827 - attribute \src "libresoc.v:164276.3-164294.6" + attribute \src "libresoc.v:164072.3-164090.6" wire width 64 $0\nia$next[63:0]$8798 - attribute \src "libresoc.v:164110.3-164111.23" + attribute \src "libresoc.v:163906.3-163907.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:164276.3-164294.6" + attribute \src "libresoc.v:164072.3-164090.6" wire $0\nia_ok$next[0:0]$8799 - attribute \src "libresoc.v:164112.3-164113.29" + attribute \src "libresoc.v:163908.3-163909.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:164179.3-164196.6" + attribute \src "libresoc.v:163975.3-163992.6" wire $0\r_busy$next[0:0]$8760 - attribute \src "libresoc.v:164140.3-164141.29" + attribute \src "libresoc.v:163936.3-163937.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire width 64 $1\br_op__cia$2$next[63:0]$8775 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire width 14 $1\br_op__fn_unit$4$next[13:0]$8776 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8777 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire $1\br_op__imm_data__ok$7$next[0:0]$8778 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire width 32 $1\br_op__insn$5$next[31:0]$8779 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire width 7 $1\br_op__insn_type$3$next[6:0]$8780 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire $1\br_op__is_32bit$9$next[0:0]$8781 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire $1\br_op__lk$8$next[0:0]$8782 - attribute \src "libresoc.v:164238.3-164256.6" + attribute \src "libresoc.v:164034.3-164052.6" wire width 64 $1\fast1$10$next[63:0]$8788 - attribute \src "libresoc.v:164238.3-164256.6" + attribute \src "libresoc.v:164034.3-164052.6" wire $1\fast1_ok$next[0:0]$8789 - attribute \src "libresoc.v:163813.7-163813.22" + attribute \src "libresoc.v:163609.7-163609.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:164257.3-164275.6" + attribute \src "libresoc.v:164053.3-164071.6" wire width 64 $1\fast2$11$next[63:0]$8794 - attribute \src "libresoc.v:164257.3-164275.6" + attribute \src "libresoc.v:164053.3-164071.6" wire $1\fast2_ok$next[0:0]$8795 - attribute \src "libresoc.v:163829.7-163829.22" + attribute \src "libresoc.v:163625.7-163625.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:164197.3-164209.6" + attribute \src "libresoc.v:163993.3-164005.6" wire width 2 $1\muxid$1$next[1:0]$8765 - attribute \src "libresoc.v:164276.3-164294.6" + attribute \src "libresoc.v:164072.3-164090.6" wire width 64 $1\nia$next[63:0]$8800 - attribute \src "libresoc.v:164085.14-164085.40" + attribute \src "libresoc.v:163881.14-163881.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:164276.3-164294.6" + attribute \src "libresoc.v:164072.3-164090.6" wire $1\nia_ok$next[0:0]$8801 - attribute \src "libresoc.v:164092.7-164092.20" + attribute \src "libresoc.v:163888.7-163888.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:164179.3-164196.6" + attribute \src "libresoc.v:163975.3-163992.6" wire $1\r_busy$next[0:0]$8761 - attribute \src "libresoc.v:164106.7-164106.20" + attribute \src "libresoc.v:163902.7-163902.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8783 - attribute \src "libresoc.v:164210.3-164237.6" + attribute \src "libresoc.v:164006.3-164033.6" wire $2\br_op__imm_data__ok$7$next[0:0]$8784 - attribute \src "libresoc.v:164238.3-164256.6" + attribute \src "libresoc.v:164034.3-164052.6" wire $2\fast1_ok$next[0:0]$8790 - attribute \src "libresoc.v:164257.3-164275.6" + attribute \src "libresoc.v:164053.3-164071.6" wire $2\fast2_ok$next[0:0]$8796 - attribute \src "libresoc.v:164276.3-164294.6" + attribute \src "libresoc.v:164072.3-164090.6" wire $2\nia_ok$next[0:0]$8802 - attribute \src "libresoc.v:164179.3-164196.6" + attribute \src "libresoc.v:163975.3-163992.6" wire $2\r_busy$next[0:0]$8762 - attribute \src "libresoc.v:164109.18-164109.118" - wire $and$libresoc.v:164109$8731_Y + attribute \src "libresoc.v:163905.18-163905.118" + wire $and$libresoc.v:163905$8731_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -304389,9 +304223,9 @@ module \pipe$19 wire output 25 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 15 \cr_a @@ -304423,7 +304257,7 @@ module \pipe$19 wire \fast2_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast2_ok$next - attribute \src "libresoc.v:163451.7-163451.15" + attribute \src "libresoc.v:163247.7-163247.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__cia @@ -304698,7 +304532,7 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:164109$8731 + cell $and $and$libresoc.v:163905$8731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304706,10 +304540,10 @@ module \pipe$19 parameter \Y_WIDTH 1 connect \A \p_valid_i$23 connect \B \p_ready_o - connect \Y $and$libresoc.v:164109$8731_Y + connect \Y $and$libresoc.v:163905$8731_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:164142.13-164170.4" + attribute \src "libresoc.v:163938.13-163966.4" cell \main$22 \main connect \br_op__cia \main_br_op__cia connect \br_op__cia$2 \main_br_op__cia$13 @@ -304740,274 +304574,274 @@ module \pipe$19 connect \nia_ok \main_nia_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:164171.10-164174.4" + attribute \src "libresoc.v:163967.10-163970.4" cell \n$21 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:164175.10-164178.4" + attribute \src "libresoc.v:163971.10-163974.4" cell \p$20 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:163451.7-163451.20" - process $proc$libresoc.v:163451$8803 + attribute \src "libresoc.v:163247.7-163247.20" + process $proc$libresoc.v:163247$8803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:163458.14-163458.51" - process $proc$libresoc.v:163458$8804 + attribute \src "libresoc.v:163254.14-163254.51" + process $proc$libresoc.v:163254$8804 assign { } { } assign $0\br_op__cia$2[63:0]$8805 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \br_op__cia$2 $0\br_op__cia$2[63:0]$8805 end - attribute \src "libresoc.v:163514.14-163514.43" - process $proc$libresoc.v:163514$8806 + attribute \src "libresoc.v:163310.14-163310.43" + process $proc$libresoc.v:163310$8806 assign { } { } assign $0\br_op__fn_unit$4[13:0]$8807 14'00000000000000 sync always sync init update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8807 end - attribute \src "libresoc.v:163523.14-163523.62" - process $proc$libresoc.v:163523$8808 + attribute \src "libresoc.v:163319.14-163319.62" + process $proc$libresoc.v:163319$8808 assign { } { } assign $0\br_op__imm_data__data$6[63:0]$8809 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8809 end - attribute \src "libresoc.v:163532.7-163532.37" - process $proc$libresoc.v:163532$8810 + attribute \src "libresoc.v:163328.7-163328.37" + process $proc$libresoc.v:163328$8810 assign { } { } assign $0\br_op__imm_data__ok$7[0:0]$8811 1'0 sync always sync init update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8811 end - attribute \src "libresoc.v:163541.14-163541.37" - process $proc$libresoc.v:163541$8812 + attribute \src "libresoc.v:163337.14-163337.37" + process $proc$libresoc.v:163337$8812 assign { } { } assign $0\br_op__insn$5[31:0]$8813 0 sync always sync init update \br_op__insn$5 $0\br_op__insn$5[31:0]$8813 end - attribute \src "libresoc.v:163775.13-163775.41" - process $proc$libresoc.v:163775$8814 + attribute \src "libresoc.v:163571.13-163571.41" + process $proc$libresoc.v:163571$8814 assign { } { } assign $0\br_op__insn_type$3[6:0]$8815 7'0000000 sync always sync init update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8815 end - attribute \src "libresoc.v:163784.7-163784.33" - process $proc$libresoc.v:163784$8816 + attribute \src "libresoc.v:163580.7-163580.33" + process $proc$libresoc.v:163580$8816 assign { } { } assign $0\br_op__is_32bit$9[0:0]$8817 1'0 sync always sync init update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8817 end - attribute \src "libresoc.v:163793.7-163793.27" - process $proc$libresoc.v:163793$8818 + attribute \src "libresoc.v:163589.7-163589.27" + process $proc$libresoc.v:163589$8818 assign { } { } assign $0\br_op__lk$8[0:0]$8819 1'0 sync always sync init update \br_op__lk$8 $0\br_op__lk$8[0:0]$8819 end - attribute \src "libresoc.v:163806.14-163806.47" - process $proc$libresoc.v:163806$8820 + attribute \src "libresoc.v:163602.14-163602.47" + process $proc$libresoc.v:163602$8820 assign { } { } assign $0\fast1$10[63:0]$8821 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1$10 $0\fast1$10[63:0]$8821 end - attribute \src "libresoc.v:163813.7-163813.22" - process $proc$libresoc.v:163813$8822 + attribute \src "libresoc.v:163609.7-163609.22" + process $proc$libresoc.v:163609$8822 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:163822.14-163822.47" - process $proc$libresoc.v:163822$8823 + attribute \src "libresoc.v:163618.14-163618.47" + process $proc$libresoc.v:163618$8823 assign { } { } assign $0\fast2$11[63:0]$8824 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2$11 $0\fast2$11[63:0]$8824 end - attribute \src "libresoc.v:163829.7-163829.22" - process $proc$libresoc.v:163829$8825 + attribute \src "libresoc.v:163625.7-163625.22" + process $proc$libresoc.v:163625$8825 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:164072.13-164072.29" - process $proc$libresoc.v:164072$8826 + attribute \src "libresoc.v:163868.13-163868.29" + process $proc$libresoc.v:163868$8826 assign { } { } assign $0\muxid$1[1:0]$8827 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8827 end - attribute \src "libresoc.v:164085.14-164085.40" - process $proc$libresoc.v:164085$8828 + attribute \src "libresoc.v:163881.14-163881.40" + process $proc$libresoc.v:163881$8828 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:164092.7-164092.20" - process $proc$libresoc.v:164092$8829 + attribute \src "libresoc.v:163888.7-163888.20" + process $proc$libresoc.v:163888$8829 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:164106.7-164106.20" - process $proc$libresoc.v:164106$8830 + attribute \src "libresoc.v:163902.7-163902.20" + process $proc$libresoc.v:163902$8830 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:164110.3-164111.23" - process $proc$libresoc.v:164110$8732 + attribute \src "libresoc.v:163906.3-163907.23" + process $proc$libresoc.v:163906$8732 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:164112.3-164113.29" - process $proc$libresoc.v:164112$8733 + attribute \src "libresoc.v:163908.3-163909.29" + process $proc$libresoc.v:163908$8733 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:164114.3-164115.35" - process $proc$libresoc.v:164114$8734 + attribute \src "libresoc.v:163910.3-163911.35" + process $proc$libresoc.v:163910$8734 assign { } { } assign $0\fast2$11[63:0]$8735 \fast2$11$next sync posedge \coresync_clk update \fast2$11 $0\fast2$11[63:0]$8735 end - attribute \src "libresoc.v:164116.3-164117.33" - process $proc$libresoc.v:164116$8736 + attribute \src "libresoc.v:163912.3-163913.33" + process $proc$libresoc.v:163912$8736 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:164118.3-164119.35" - process $proc$libresoc.v:164118$8737 + attribute \src "libresoc.v:163914.3-163915.35" + process $proc$libresoc.v:163914$8737 assign { } { } assign $0\fast1$10[63:0]$8738 \fast1$10$next sync posedge \coresync_clk update \fast1$10 $0\fast1$10[63:0]$8738 end - attribute \src "libresoc.v:164120.3-164121.33" - process $proc$libresoc.v:164120$8739 + attribute \src "libresoc.v:163916.3-163917.33" + process $proc$libresoc.v:163916$8739 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:164122.3-164123.43" - process $proc$libresoc.v:164122$8740 + attribute \src "libresoc.v:163918.3-163919.43" + process $proc$libresoc.v:163918$8740 assign { } { } assign $0\br_op__cia$2[63:0]$8741 \br_op__cia$2$next sync posedge \coresync_clk update \br_op__cia$2 $0\br_op__cia$2[63:0]$8741 end - attribute \src "libresoc.v:164124.3-164125.55" - process $proc$libresoc.v:164124$8742 + attribute \src "libresoc.v:163920.3-163921.55" + process $proc$libresoc.v:163920$8742 assign { } { } assign $0\br_op__insn_type$3[6:0]$8743 \br_op__insn_type$3$next sync posedge \coresync_clk update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8743 end - attribute \src "libresoc.v:164126.3-164127.51" - process $proc$libresoc.v:164126$8744 + attribute \src "libresoc.v:163922.3-163923.51" + process $proc$libresoc.v:163922$8744 assign { } { } assign $0\br_op__fn_unit$4[13:0]$8745 \br_op__fn_unit$4$next sync posedge \coresync_clk update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8745 end - attribute \src "libresoc.v:164128.3-164129.45" - process $proc$libresoc.v:164128$8746 + attribute \src "libresoc.v:163924.3-163925.45" + process $proc$libresoc.v:163924$8746 assign { } { } assign $0\br_op__insn$5[31:0]$8747 \br_op__insn$5$next sync posedge \coresync_clk update \br_op__insn$5 $0\br_op__insn$5[31:0]$8747 end - attribute \src "libresoc.v:164130.3-164131.65" - process $proc$libresoc.v:164130$8748 + attribute \src "libresoc.v:163926.3-163927.65" + process $proc$libresoc.v:163926$8748 assign { } { } assign $0\br_op__imm_data__data$6[63:0]$8749 \br_op__imm_data__data$6$next sync posedge \coresync_clk update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8749 end - attribute \src "libresoc.v:164132.3-164133.61" - process $proc$libresoc.v:164132$8750 + attribute \src "libresoc.v:163928.3-163929.61" + process $proc$libresoc.v:163928$8750 assign { } { } assign $0\br_op__imm_data__ok$7[0:0]$8751 \br_op__imm_data__ok$7$next sync posedge \coresync_clk update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8751 end - attribute \src "libresoc.v:164134.3-164135.41" - process $proc$libresoc.v:164134$8752 + attribute \src "libresoc.v:163930.3-163931.41" + process $proc$libresoc.v:163930$8752 assign { } { } assign $0\br_op__lk$8[0:0]$8753 \br_op__lk$8$next sync posedge \coresync_clk update \br_op__lk$8 $0\br_op__lk$8[0:0]$8753 end - attribute \src "libresoc.v:164136.3-164137.53" - process $proc$libresoc.v:164136$8754 + attribute \src "libresoc.v:163932.3-163933.53" + process $proc$libresoc.v:163932$8754 assign { } { } assign $0\br_op__is_32bit$9[0:0]$8755 \br_op__is_32bit$9$next sync posedge \coresync_clk update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8755 end - attribute \src "libresoc.v:164138.3-164139.33" - process $proc$libresoc.v:164138$8756 + attribute \src "libresoc.v:163934.3-163935.33" + process $proc$libresoc.v:163934$8756 assign { } { } assign $0\muxid$1[1:0]$8757 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8757 end - attribute \src "libresoc.v:164140.3-164141.29" - process $proc$libresoc.v:164140$8758 + attribute \src "libresoc.v:163936.3-163937.29" + process $proc$libresoc.v:163936$8758 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:164179.3-164196.6" - process $proc$libresoc.v:164179$8759 + attribute \src "libresoc.v:163975.3-163992.6" + process $proc$libresoc.v:163975$8759 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8760 $2\r_busy$next[0:0]$8762 - attribute \src "libresoc.v:164180.5-164180.29" + attribute \src "libresoc.v:163976.5-163976.29" switch \initial - attribute \src "libresoc.v:164180.9-164180.17" + attribute \src "libresoc.v:163976.9-163976.17" case 1'1 case end @@ -305036,14 +304870,14 @@ module \pipe$19 sync always update \r_busy$next $0\r_busy$next[0:0]$8760 end - attribute \src "libresoc.v:164197.3-164209.6" - process $proc$libresoc.v:164197$8763 + attribute \src "libresoc.v:163993.3-164005.6" + process $proc$libresoc.v:163993$8763 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8764 $1\muxid$1$next[1:0]$8765 - attribute \src "libresoc.v:164198.5-164198.29" + attribute \src "libresoc.v:163994.5-163994.29" switch \initial - attribute \src "libresoc.v:164198.9-164198.17" + attribute \src "libresoc.v:163994.9-163994.17" case 1'1 case end @@ -305063,8 +304897,8 @@ module \pipe$19 sync always update \muxid$1$next $0\muxid$1$next[1:0]$8764 end - attribute \src "libresoc.v:164210.3-164237.6" - process $proc$libresoc.v:164210$8766 + attribute \src "libresoc.v:164006.3-164033.6" + process $proc$libresoc.v:164006$8766 assign { } { } assign { } { } assign { } { } @@ -305091,9 +304925,9 @@ module \pipe$19 assign $0\br_op__lk$8$next[0:0]$8774 $1\br_op__lk$8$next[0:0]$8782 assign $0\br_op__imm_data__data$6$next[63:0]$8769 $2\br_op__imm_data__data$6$next[63:0]$8783 assign $0\br_op__imm_data__ok$7$next[0:0]$8770 $2\br_op__imm_data__ok$7$next[0:0]$8784 - attribute \src "libresoc.v:164211.5-164211.29" + attribute \src "libresoc.v:164007.5-164007.29" switch \initial - attribute \src "libresoc.v:164211.9-164211.17" + attribute \src "libresoc.v:164007.9-164007.17" case 1'1 case end @@ -305153,8 +304987,8 @@ module \pipe$19 update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8773 update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8774 end - attribute \src "libresoc.v:164238.3-164256.6" - process $proc$libresoc.v:164238$8785 + attribute \src "libresoc.v:164034.3-164052.6" + process $proc$libresoc.v:164034$8785 assign { } { } assign { } { } assign { } { } @@ -305162,9 +304996,9 @@ module \pipe$19 assign $0\fast1$10$next[63:0]$8786 $1\fast1$10$next[63:0]$8788 assign { } { } assign $0\fast1_ok$next[0:0]$8787 $2\fast1_ok$next[0:0]$8790 - attribute \src "libresoc.v:164239.5-164239.29" + attribute \src "libresoc.v:164035.5-164035.29" switch \initial - attribute \src "libresoc.v:164239.9-164239.17" + attribute \src "libresoc.v:164035.9-164035.17" case 1'1 case end @@ -305197,8 +305031,8 @@ module \pipe$19 update \fast1$10$next $0\fast1$10$next[63:0]$8786 update \fast1_ok$next $0\fast1_ok$next[0:0]$8787 end - attribute \src "libresoc.v:164257.3-164275.6" - process $proc$libresoc.v:164257$8791 + attribute \src "libresoc.v:164053.3-164071.6" + process $proc$libresoc.v:164053$8791 assign { } { } assign { } { } assign { } { } @@ -305206,9 +305040,9 @@ module \pipe$19 assign $0\fast2$11$next[63:0]$8792 $1\fast2$11$next[63:0]$8794 assign { } { } assign $0\fast2_ok$next[0:0]$8793 $2\fast2_ok$next[0:0]$8796 - attribute \src "libresoc.v:164258.5-164258.29" + attribute \src "libresoc.v:164054.5-164054.29" switch \initial - attribute \src "libresoc.v:164258.9-164258.17" + attribute \src "libresoc.v:164054.9-164054.17" case 1'1 case end @@ -305241,8 +305075,8 @@ module \pipe$19 update \fast2$11$next $0\fast2$11$next[63:0]$8792 update \fast2_ok$next $0\fast2_ok$next[0:0]$8793 end - attribute \src "libresoc.v:164276.3-164294.6" - process $proc$libresoc.v:164276$8797 + attribute \src "libresoc.v:164072.3-164090.6" + process $proc$libresoc.v:164072$8797 assign { } { } assign { } { } assign { } { } @@ -305250,9 +305084,9 @@ module \pipe$19 assign $0\nia$next[63:0]$8798 $1\nia$next[63:0]$8800 assign { } { } assign $0\nia_ok$next[0:0]$8799 $2\nia_ok$next[0:0]$8802 - attribute \src "libresoc.v:164277.5-164277.29" + attribute \src "libresoc.v:164073.5-164073.29" switch \initial - attribute \src "libresoc.v:164277.9-164277.17" + attribute \src "libresoc.v:164073.9-164073.17" case 1'1 case end @@ -305285,7 +305119,7 @@ module \pipe$19 update \nia$next $0\nia$next[63:0]$8798 update \nia_ok$next $0\nia_ok$next[0:0]$8799 end - connect \$24 $and$libresoc.v:164109$8731_Y + connect \$24 $and$libresoc.v:163905$8731_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } @@ -305302,178 +305136,178 @@ module \pipe$19 connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } connect \main_muxid \muxid end -attribute \src "libresoc.v:164314.1-165244.10" +attribute \src "libresoc.v:164110.1-165040.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" attribute \generator "nMigen" module \pipe$64 - attribute \src "libresoc.v:165147.3-165165.6" + attribute \src "libresoc.v:164943.3-164961.6" wire width 64 $0\fast1$7$next[63:0]$8890 - attribute \src "libresoc.v:165000.3-165001.33" + attribute \src "libresoc.v:164796.3-164797.33" wire width 64 $0\fast1$7[63:0]$8842 - attribute \src "libresoc.v:164328.14-164328.46" + attribute \src "libresoc.v:164124.14-164124.46" wire width 64 $0\fast1$7[63:0]$8914 - attribute \src "libresoc.v:165147.3-165165.6" + attribute \src "libresoc.v:164943.3-164961.6" wire $0\fast1_ok$next[0:0]$8889 - attribute \src "libresoc.v:165002.3-165003.33" + attribute \src "libresoc.v:164798.3-164799.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:164315.7-164315.20" + attribute \src "libresoc.v:164111.7-164111.20" wire $0\initial[0:0] - attribute \src "libresoc.v:165080.3-165092.6" + attribute \src "libresoc.v:164876.3-164888.6" wire width 2 $0\muxid$1$next[1:0]$8865 - attribute \src "libresoc.v:165020.3-165021.33" + attribute \src "libresoc.v:164816.3-164817.33" wire width 2 $0\muxid$1[1:0]$8858 - attribute \src "libresoc.v:164342.13-164342.29" + attribute \src "libresoc.v:164138.13-164138.29" wire width 2 $0\muxid$1[1:0]$8917 - attribute \src "libresoc.v:165109.3-165127.6" + attribute \src "libresoc.v:164905.3-164923.6" wire width 64 $0\o$next[63:0]$8877 - attribute \src "libresoc.v:165008.3-165009.19" + attribute \src "libresoc.v:164804.3-164805.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:165109.3-165127.6" + attribute \src "libresoc.v:164905.3-164923.6" wire $0\o_ok$next[0:0]$8878 - attribute \src "libresoc.v:165010.3-165011.25" + attribute \src "libresoc.v:164806.3-164807.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:165062.3-165079.6" + attribute \src "libresoc.v:164858.3-164875.6" wire $0\r_busy$next[0:0]$8861 - attribute \src "libresoc.v:165022.3-165023.29" + attribute \src "libresoc.v:164818.3-164819.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:165128.3-165146.6" + attribute \src "libresoc.v:164924.3-164942.6" wire width 64 $0\spr1$6$next[63:0]$8883 - attribute \src "libresoc.v:165004.3-165005.31" + attribute \src "libresoc.v:164800.3-164801.31" wire width 64 $0\spr1$6[63:0]$8845 - attribute \src "libresoc.v:164387.14-164387.45" + attribute \src "libresoc.v:164183.14-164183.45" wire width 64 $0\spr1$6[63:0]$8922 - attribute \src "libresoc.v:165128.3-165146.6" + attribute \src "libresoc.v:164924.3-164942.6" wire $0\spr1_ok$next[0:0]$8884 - attribute \src "libresoc.v:165006.3-165007.31" + attribute \src "libresoc.v:164802.3-164803.31" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:165093.3-165108.6" + attribute \src "libresoc.v:164889.3-164904.6" wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8868 - attribute \src "libresoc.v:165014.3-165015.53" + attribute \src "libresoc.v:164810.3-164811.53" wire width 14 $0\spr_op__fn_unit$3[13:0]$8852 - attribute \src "libresoc.v:164684.14-164684.44" + attribute \src "libresoc.v:164480.14-164480.44" wire width 14 $0\spr_op__fn_unit$3[13:0]$8925 - attribute \src "libresoc.v:165093.3-165108.6" + attribute \src "libresoc.v:164889.3-164904.6" wire width 32 $0\spr_op__insn$4$next[31:0]$8869 - attribute \src "libresoc.v:165016.3-165017.47" + attribute \src "libresoc.v:164812.3-164813.47" wire width 32 $0\spr_op__insn$4[31:0]$8854 - attribute \src "libresoc.v:164693.14-164693.38" + attribute \src "libresoc.v:164489.14-164489.38" wire width 32 $0\spr_op__insn$4[31:0]$8927 - attribute \src "libresoc.v:165093.3-165108.6" + attribute \src "libresoc.v:164889.3-164904.6" wire width 7 $0\spr_op__insn_type$2$next[6:0]$8870 - attribute \src "libresoc.v:165012.3-165013.57" + attribute \src "libresoc.v:164808.3-164809.57" wire width 7 $0\spr_op__insn_type$2[6:0]$8850 - attribute \src "libresoc.v:164850.13-164850.42" + attribute \src "libresoc.v:164646.13-164646.42" wire width 7 $0\spr_op__insn_type$2[6:0]$8929 - attribute \src "libresoc.v:165093.3-165108.6" + attribute \src "libresoc.v:164889.3-164904.6" wire $0\spr_op__is_32bit$5$next[0:0]$8871 - attribute \src "libresoc.v:165018.3-165019.55" + attribute \src "libresoc.v:164814.3-164815.55" wire $0\spr_op__is_32bit$5[0:0]$8856 - attribute \src "libresoc.v:164936.7-164936.34" + attribute \src "libresoc.v:164732.7-164732.34" wire $0\spr_op__is_32bit$5[0:0]$8931 - attribute \src "libresoc.v:165204.3-165222.6" + attribute \src "libresoc.v:165000.3-165018.6" wire width 2 $0\xer_ca$10$next[1:0]$8907 - attribute \src "libresoc.v:164988.3-164989.37" + attribute \src "libresoc.v:164784.3-164785.37" wire width 2 $0\xer_ca$10[1:0]$8833 - attribute \src "libresoc.v:164943.13-164943.31" + attribute \src "libresoc.v:164739.13-164739.31" wire width 2 $0\xer_ca$10[1:0]$8933 - attribute \src "libresoc.v:165204.3-165222.6" + attribute \src "libresoc.v:165000.3-165018.6" wire $0\xer_ca_ok$next[0:0]$8908 - attribute \src "libresoc.v:164990.3-164991.35" + attribute \src "libresoc.v:164786.3-164787.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:165185.3-165203.6" + attribute \src "libresoc.v:164981.3-164999.6" wire width 2 $0\xer_ov$9$next[1:0]$8902 - attribute \src "libresoc.v:164992.3-164993.35" + attribute \src "libresoc.v:164788.3-164789.35" wire width 2 $0\xer_ov$9[1:0]$8836 - attribute \src "libresoc.v:164961.13-164961.30" + attribute \src "libresoc.v:164757.13-164757.30" wire width 2 $0\xer_ov$9[1:0]$8936 - attribute \src "libresoc.v:165185.3-165203.6" + attribute \src "libresoc.v:164981.3-164999.6" wire $0\xer_ov_ok$next[0:0]$8901 - attribute \src "libresoc.v:164994.3-164995.35" + attribute \src "libresoc.v:164790.3-164791.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:165166.3-165184.6" + attribute \src "libresoc.v:164962.3-164980.6" wire $0\xer_so$8$next[0:0]$8896 - attribute \src "libresoc.v:164996.3-164997.35" + attribute \src "libresoc.v:164792.3-164793.35" wire $0\xer_so$8[0:0]$8839 - attribute \src "libresoc.v:164977.7-164977.24" + attribute \src "libresoc.v:164773.7-164773.24" wire $0\xer_so$8[0:0]$8939 - attribute \src "libresoc.v:165166.3-165184.6" + attribute \src "libresoc.v:164962.3-164980.6" wire $0\xer_so_ok$next[0:0]$8895 - attribute \src "libresoc.v:164998.3-164999.35" + attribute \src "libresoc.v:164794.3-164795.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:165147.3-165165.6" + attribute \src "libresoc.v:164943.3-164961.6" wire width 64 $1\fast1$7$next[63:0]$8892 - attribute \src "libresoc.v:165147.3-165165.6" + attribute \src "libresoc.v:164943.3-164961.6" wire $1\fast1_ok$next[0:0]$8891 - attribute \src "libresoc.v:164333.7-164333.22" + attribute \src "libresoc.v:164129.7-164129.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:165080.3-165092.6" + attribute \src "libresoc.v:164876.3-164888.6" wire width 2 $1\muxid$1$next[1:0]$8866 - attribute \src "libresoc.v:165109.3-165127.6" + attribute \src "libresoc.v:164905.3-164923.6" wire width 64 $1\o$next[63:0]$8879 - attribute \src "libresoc.v:164355.14-164355.38" + attribute \src "libresoc.v:164151.14-164151.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:165109.3-165127.6" + attribute \src "libresoc.v:164905.3-164923.6" wire $1\o_ok$next[0:0]$8880 - attribute \src "libresoc.v:164362.7-164362.18" + attribute \src "libresoc.v:164158.7-164158.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:165062.3-165079.6" + attribute \src "libresoc.v:164858.3-164875.6" wire $1\r_busy$next[0:0]$8862 - attribute \src "libresoc.v:164376.7-164376.20" + attribute \src "libresoc.v:164172.7-164172.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:165128.3-165146.6" + attribute \src "libresoc.v:164924.3-164942.6" wire width 64 $1\spr1$6$next[63:0]$8885 - attribute \src "libresoc.v:165128.3-165146.6" + attribute \src "libresoc.v:164924.3-164942.6" wire $1\spr1_ok$next[0:0]$8886 - attribute \src "libresoc.v:164392.7-164392.21" + attribute \src "libresoc.v:164188.7-164188.21" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:165093.3-165108.6" + attribute \src "libresoc.v:164889.3-164904.6" wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8872 - attribute \src "libresoc.v:165093.3-165108.6" + attribute \src "libresoc.v:164889.3-164904.6" wire width 32 $1\spr_op__insn$4$next[31:0]$8873 - attribute \src "libresoc.v:165093.3-165108.6" + attribute \src "libresoc.v:164889.3-164904.6" wire width 7 $1\spr_op__insn_type$2$next[6:0]$8874 - attribute \src "libresoc.v:165093.3-165108.6" + attribute \src "libresoc.v:164889.3-164904.6" wire $1\spr_op__is_32bit$5$next[0:0]$8875 - attribute \src "libresoc.v:165204.3-165222.6" + attribute \src "libresoc.v:165000.3-165018.6" wire width 2 $1\xer_ca$10$next[1:0]$8909 - attribute \src "libresoc.v:165204.3-165222.6" + attribute \src "libresoc.v:165000.3-165018.6" wire $1\xer_ca_ok$next[0:0]$8910 - attribute \src "libresoc.v:164950.7-164950.23" + attribute \src "libresoc.v:164746.7-164746.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:165185.3-165203.6" + attribute \src "libresoc.v:164981.3-164999.6" wire width 2 $1\xer_ov$9$next[1:0]$8904 - attribute \src "libresoc.v:165185.3-165203.6" + attribute \src "libresoc.v:164981.3-164999.6" wire $1\xer_ov_ok$next[0:0]$8903 - attribute \src "libresoc.v:164966.7-164966.23" + attribute \src "libresoc.v:164762.7-164762.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:165166.3-165184.6" + attribute \src "libresoc.v:164962.3-164980.6" wire $1\xer_so$8$next[0:0]$8898 - attribute \src "libresoc.v:165166.3-165184.6" + attribute \src "libresoc.v:164962.3-164980.6" wire $1\xer_so_ok$next[0:0]$8897 - attribute \src "libresoc.v:164982.7-164982.23" + attribute \src "libresoc.v:164778.7-164778.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:165147.3-165165.6" + attribute \src "libresoc.v:164943.3-164961.6" wire $2\fast1_ok$next[0:0]$8893 - attribute \src "libresoc.v:165109.3-165127.6" + attribute \src "libresoc.v:164905.3-164923.6" wire $2\o_ok$next[0:0]$8881 - attribute \src "libresoc.v:165062.3-165079.6" + attribute \src "libresoc.v:164858.3-164875.6" wire $2\r_busy$next[0:0]$8863 - attribute \src "libresoc.v:165128.3-165146.6" + attribute \src "libresoc.v:164924.3-164942.6" wire $2\spr1_ok$next[0:0]$8887 - attribute \src "libresoc.v:165204.3-165222.6" + attribute \src "libresoc.v:165000.3-165018.6" wire $2\xer_ca_ok$next[0:0]$8911 - attribute \src "libresoc.v:165185.3-165203.6" + attribute \src "libresoc.v:164981.3-164999.6" wire $2\xer_ov_ok$next[0:0]$8905 - attribute \src "libresoc.v:165166.3-165184.6" + attribute \src "libresoc.v:164962.3-164980.6" wire $2\xer_so_ok$next[0:0]$8899 - attribute \src "libresoc.v:164987.18-164987.118" - wire $and$libresoc.v:164987$8831_Y + attribute \src "libresoc.v:164783.18-164783.118" + wire $and$libresoc.v:164783$8831_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 11 \fast1 @@ -305489,7 +305323,7 @@ module \pipe$64 wire \fast1_ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$next - attribute \src "libresoc.v:164315.7-164315.15" + attribute \src "libresoc.v:164111.7-164111.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -306126,7 +305960,7 @@ module \pipe$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:164987$8831 + cell $and $and$libresoc.v:164783$8831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306134,22 +305968,22 @@ module \pipe$64 parameter \Y_WIDTH 1 connect \A \p_valid_i$21 connect \B \p_ready_o - connect \Y $and$libresoc.v:164987$8831_Y + connect \Y $and$libresoc.v:164783$8831_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:165024.10-165027.4" + attribute \src "libresoc.v:164820.10-164823.4" cell \n$66 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:165028.10-165031.4" + attribute \src "libresoc.v:164824.10-164827.4" cell \p$65 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:165032.12-165061.4" + attribute \src "libresoc.v:164828.12-164857.4" cell \spr_main \spr_main connect \fast1 \spr_main_fast1 connect \fast1$7 \spr_main_fast1$17 @@ -306180,293 +306014,293 @@ module \pipe$64 connect \xer_so$8 \spr_main_xer_so$18 connect \xer_so_ok \spr_main_xer_so_ok end - attribute \src "libresoc.v:164315.7-164315.20" - process $proc$libresoc.v:164315$8912 + attribute \src "libresoc.v:164111.7-164111.20" + process $proc$libresoc.v:164111$8912 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:164328.14-164328.46" - process $proc$libresoc.v:164328$8913 + attribute \src "libresoc.v:164124.14-164124.46" + process $proc$libresoc.v:164124$8913 assign { } { } assign $0\fast1$7[63:0]$8914 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1$7 $0\fast1$7[63:0]$8914 end - attribute \src "libresoc.v:164333.7-164333.22" - process $proc$libresoc.v:164333$8915 + attribute \src "libresoc.v:164129.7-164129.22" + process $proc$libresoc.v:164129$8915 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:164342.13-164342.29" - process $proc$libresoc.v:164342$8916 + attribute \src "libresoc.v:164138.13-164138.29" + process $proc$libresoc.v:164138$8916 assign { } { } assign $0\muxid$1[1:0]$8917 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8917 end - attribute \src "libresoc.v:164355.14-164355.38" - process $proc$libresoc.v:164355$8918 + attribute \src "libresoc.v:164151.14-164151.38" + process $proc$libresoc.v:164151$8918 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:164362.7-164362.18" - process $proc$libresoc.v:164362$8919 + attribute \src "libresoc.v:164158.7-164158.18" + process $proc$libresoc.v:164158$8919 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:164376.7-164376.20" - process $proc$libresoc.v:164376$8920 + attribute \src "libresoc.v:164172.7-164172.20" + process $proc$libresoc.v:164172$8920 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:164387.14-164387.45" - process $proc$libresoc.v:164387$8921 + attribute \src "libresoc.v:164183.14-164183.45" + process $proc$libresoc.v:164183$8921 assign { } { } assign $0\spr1$6[63:0]$8922 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \spr1$6 $0\spr1$6[63:0]$8922 end - attribute \src "libresoc.v:164392.7-164392.21" - process $proc$libresoc.v:164392$8923 + attribute \src "libresoc.v:164188.7-164188.21" + process $proc$libresoc.v:164188$8923 assign { } { } assign $1\spr1_ok[0:0] 1'0 sync always sync init update \spr1_ok $1\spr1_ok[0:0] end - attribute \src "libresoc.v:164684.14-164684.44" - process $proc$libresoc.v:164684$8924 + attribute \src "libresoc.v:164480.14-164480.44" + process $proc$libresoc.v:164480$8924 assign { } { } assign $0\spr_op__fn_unit$3[13:0]$8925 14'00000000000000 sync always sync init update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8925 end - attribute \src "libresoc.v:164693.14-164693.38" - process $proc$libresoc.v:164693$8926 + attribute \src "libresoc.v:164489.14-164489.38" + process $proc$libresoc.v:164489$8926 assign { } { } assign $0\spr_op__insn$4[31:0]$8927 0 sync always sync init update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8927 end - attribute \src "libresoc.v:164850.13-164850.42" - process $proc$libresoc.v:164850$8928 + attribute \src "libresoc.v:164646.13-164646.42" + process $proc$libresoc.v:164646$8928 assign { } { } assign $0\spr_op__insn_type$2[6:0]$8929 7'0000000 sync always sync init update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8929 end - attribute \src "libresoc.v:164936.7-164936.34" - process $proc$libresoc.v:164936$8930 + attribute \src "libresoc.v:164732.7-164732.34" + process $proc$libresoc.v:164732$8930 assign { } { } assign $0\spr_op__is_32bit$5[0:0]$8931 1'0 sync always sync init update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8931 end - attribute \src "libresoc.v:164943.13-164943.31" - process $proc$libresoc.v:164943$8932 + attribute \src "libresoc.v:164739.13-164739.31" + process $proc$libresoc.v:164739$8932 assign { } { } assign $0\xer_ca$10[1:0]$8933 2'00 sync always sync init update \xer_ca$10 $0\xer_ca$10[1:0]$8933 end - attribute \src "libresoc.v:164950.7-164950.23" - process $proc$libresoc.v:164950$8934 + attribute \src "libresoc.v:164746.7-164746.23" + process $proc$libresoc.v:164746$8934 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:164961.13-164961.30" - process $proc$libresoc.v:164961$8935 + attribute \src "libresoc.v:164757.13-164757.30" + process $proc$libresoc.v:164757$8935 assign { } { } assign $0\xer_ov$9[1:0]$8936 2'00 sync always sync init update \xer_ov$9 $0\xer_ov$9[1:0]$8936 end - attribute \src "libresoc.v:164966.7-164966.23" - process $proc$libresoc.v:164966$8937 + attribute \src "libresoc.v:164762.7-164762.23" + process $proc$libresoc.v:164762$8937 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:164977.7-164977.24" - process $proc$libresoc.v:164977$8938 + attribute \src "libresoc.v:164773.7-164773.24" + process $proc$libresoc.v:164773$8938 assign { } { } assign $0\xer_so$8[0:0]$8939 1'0 sync always sync init update \xer_so$8 $0\xer_so$8[0:0]$8939 end - attribute \src "libresoc.v:164982.7-164982.23" - process $proc$libresoc.v:164982$8940 + attribute \src "libresoc.v:164778.7-164778.23" + process $proc$libresoc.v:164778$8940 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:164988.3-164989.37" - process $proc$libresoc.v:164988$8832 + attribute \src "libresoc.v:164784.3-164785.37" + process $proc$libresoc.v:164784$8832 assign { } { } assign $0\xer_ca$10[1:0]$8833 \xer_ca$10$next sync posedge \coresync_clk update \xer_ca$10 $0\xer_ca$10[1:0]$8833 end - attribute \src "libresoc.v:164990.3-164991.35" - process $proc$libresoc.v:164990$8834 + attribute \src "libresoc.v:164786.3-164787.35" + process $proc$libresoc.v:164786$8834 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:164992.3-164993.35" - process $proc$libresoc.v:164992$8835 + attribute \src "libresoc.v:164788.3-164789.35" + process $proc$libresoc.v:164788$8835 assign { } { } assign $0\xer_ov$9[1:0]$8836 \xer_ov$9$next sync posedge \coresync_clk update \xer_ov$9 $0\xer_ov$9[1:0]$8836 end - attribute \src "libresoc.v:164994.3-164995.35" - process $proc$libresoc.v:164994$8837 + attribute \src "libresoc.v:164790.3-164791.35" + process $proc$libresoc.v:164790$8837 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:164996.3-164997.35" - process $proc$libresoc.v:164996$8838 + attribute \src "libresoc.v:164792.3-164793.35" + process $proc$libresoc.v:164792$8838 assign { } { } assign $0\xer_so$8[0:0]$8839 \xer_so$8$next sync posedge \coresync_clk update \xer_so$8 $0\xer_so$8[0:0]$8839 end - attribute \src "libresoc.v:164998.3-164999.35" - process $proc$libresoc.v:164998$8840 + attribute \src "libresoc.v:164794.3-164795.35" + process $proc$libresoc.v:164794$8840 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:165000.3-165001.33" - process $proc$libresoc.v:165000$8841 + attribute \src "libresoc.v:164796.3-164797.33" + process $proc$libresoc.v:164796$8841 assign { } { } assign $0\fast1$7[63:0]$8842 \fast1$7$next sync posedge \coresync_clk update \fast1$7 $0\fast1$7[63:0]$8842 end - attribute \src "libresoc.v:165002.3-165003.33" - process $proc$libresoc.v:165002$8843 + attribute \src "libresoc.v:164798.3-164799.33" + process $proc$libresoc.v:164798$8843 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:165004.3-165005.31" - process $proc$libresoc.v:165004$8844 + attribute \src "libresoc.v:164800.3-164801.31" + process $proc$libresoc.v:164800$8844 assign { } { } assign $0\spr1$6[63:0]$8845 \spr1$6$next sync posedge \coresync_clk update \spr1$6 $0\spr1$6[63:0]$8845 end - attribute \src "libresoc.v:165006.3-165007.31" - process $proc$libresoc.v:165006$8846 + attribute \src "libresoc.v:164802.3-164803.31" + process $proc$libresoc.v:164802$8846 assign { } { } assign $0\spr1_ok[0:0] \spr1_ok$next sync posedge \coresync_clk update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:165008.3-165009.19" - process $proc$libresoc.v:165008$8847 + attribute \src "libresoc.v:164804.3-164805.19" + process $proc$libresoc.v:164804$8847 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:165010.3-165011.25" - process $proc$libresoc.v:165010$8848 + attribute \src "libresoc.v:164806.3-164807.25" + process $proc$libresoc.v:164806$8848 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:165012.3-165013.57" - process $proc$libresoc.v:165012$8849 + attribute \src "libresoc.v:164808.3-164809.57" + process $proc$libresoc.v:164808$8849 assign { } { } assign $0\spr_op__insn_type$2[6:0]$8850 \spr_op__insn_type$2$next sync posedge \coresync_clk update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8850 end - attribute \src "libresoc.v:165014.3-165015.53" - process $proc$libresoc.v:165014$8851 + attribute \src "libresoc.v:164810.3-164811.53" + process $proc$libresoc.v:164810$8851 assign { } { } assign $0\spr_op__fn_unit$3[13:0]$8852 \spr_op__fn_unit$3$next sync posedge \coresync_clk update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8852 end - attribute \src "libresoc.v:165016.3-165017.47" - process $proc$libresoc.v:165016$8853 + attribute \src "libresoc.v:164812.3-164813.47" + process $proc$libresoc.v:164812$8853 assign { } { } assign $0\spr_op__insn$4[31:0]$8854 \spr_op__insn$4$next sync posedge \coresync_clk update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8854 end - attribute \src "libresoc.v:165018.3-165019.55" - process $proc$libresoc.v:165018$8855 + attribute \src "libresoc.v:164814.3-164815.55" + process $proc$libresoc.v:164814$8855 assign { } { } assign $0\spr_op__is_32bit$5[0:0]$8856 \spr_op__is_32bit$5$next sync posedge \coresync_clk update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8856 end - attribute \src "libresoc.v:165020.3-165021.33" - process $proc$libresoc.v:165020$8857 + attribute \src "libresoc.v:164816.3-164817.33" + process $proc$libresoc.v:164816$8857 assign { } { } assign $0\muxid$1[1:0]$8858 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8858 end - attribute \src "libresoc.v:165022.3-165023.29" - process $proc$libresoc.v:165022$8859 + attribute \src "libresoc.v:164818.3-164819.29" + process $proc$libresoc.v:164818$8859 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:165062.3-165079.6" - process $proc$libresoc.v:165062$8860 + attribute \src "libresoc.v:164858.3-164875.6" + process $proc$libresoc.v:164858$8860 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8861 $2\r_busy$next[0:0]$8863 - attribute \src "libresoc.v:165063.5-165063.29" + attribute \src "libresoc.v:164859.5-164859.29" switch \initial - attribute \src "libresoc.v:165063.9-165063.17" + attribute \src "libresoc.v:164859.9-164859.17" case 1'1 case end @@ -306495,14 +306329,14 @@ module \pipe$64 sync always update \r_busy$next $0\r_busy$next[0:0]$8861 end - attribute \src "libresoc.v:165080.3-165092.6" - process $proc$libresoc.v:165080$8864 + attribute \src "libresoc.v:164876.3-164888.6" + process $proc$libresoc.v:164876$8864 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8865 $1\muxid$1$next[1:0]$8866 - attribute \src "libresoc.v:165081.5-165081.29" + attribute \src "libresoc.v:164877.5-164877.29" switch \initial - attribute \src "libresoc.v:165081.9-165081.17" + attribute \src "libresoc.v:164877.9-164877.17" case 1'1 case end @@ -306522,8 +306356,8 @@ module \pipe$64 sync always update \muxid$1$next $0\muxid$1$next[1:0]$8865 end - attribute \src "libresoc.v:165093.3-165108.6" - process $proc$libresoc.v:165093$8867 + attribute \src "libresoc.v:164889.3-164904.6" + process $proc$libresoc.v:164889$8867 assign { } { } assign { } { } assign { } { } @@ -306536,9 +306370,9 @@ module \pipe$64 assign $0\spr_op__insn$4$next[31:0]$8869 $1\spr_op__insn$4$next[31:0]$8873 assign $0\spr_op__insn_type$2$next[6:0]$8870 $1\spr_op__insn_type$2$next[6:0]$8874 assign $0\spr_op__is_32bit$5$next[0:0]$8871 $1\spr_op__is_32bit$5$next[0:0]$8875 - attribute \src "libresoc.v:165094.5-165094.29" + attribute \src "libresoc.v:164890.5-164890.29" switch \initial - attribute \src "libresoc.v:165094.9-165094.17" + attribute \src "libresoc.v:164890.9-164890.17" case 1'1 case end @@ -306570,8 +306404,8 @@ module \pipe$64 update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8870 update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8871 end - attribute \src "libresoc.v:165109.3-165127.6" - process $proc$libresoc.v:165109$8876 + attribute \src "libresoc.v:164905.3-164923.6" + process $proc$libresoc.v:164905$8876 assign { } { } assign { } { } assign { } { } @@ -306579,9 +306413,9 @@ module \pipe$64 assign $0\o$next[63:0]$8877 $1\o$next[63:0]$8879 assign { } { } assign $0\o_ok$next[0:0]$8878 $2\o_ok$next[0:0]$8881 - attribute \src "libresoc.v:165110.5-165110.29" + attribute \src "libresoc.v:164906.5-164906.29" switch \initial - attribute \src "libresoc.v:165110.9-165110.17" + attribute \src "libresoc.v:164906.9-164906.17" case 1'1 case end @@ -306614,8 +306448,8 @@ module \pipe$64 update \o$next $0\o$next[63:0]$8877 update \o_ok$next $0\o_ok$next[0:0]$8878 end - attribute \src "libresoc.v:165128.3-165146.6" - process $proc$libresoc.v:165128$8882 + attribute \src "libresoc.v:164924.3-164942.6" + process $proc$libresoc.v:164924$8882 assign { } { } assign { } { } assign { } { } @@ -306623,9 +306457,9 @@ module \pipe$64 assign $0\spr1$6$next[63:0]$8883 $1\spr1$6$next[63:0]$8885 assign { } { } assign $0\spr1_ok$next[0:0]$8884 $2\spr1_ok$next[0:0]$8887 - attribute \src "libresoc.v:165129.5-165129.29" + attribute \src "libresoc.v:164925.5-164925.29" switch \initial - attribute \src "libresoc.v:165129.9-165129.17" + attribute \src "libresoc.v:164925.9-164925.17" case 1'1 case end @@ -306658,8 +306492,8 @@ module \pipe$64 update \spr1$6$next $0\spr1$6$next[63:0]$8883 update \spr1_ok$next $0\spr1_ok$next[0:0]$8884 end - attribute \src "libresoc.v:165147.3-165165.6" - process $proc$libresoc.v:165147$8888 + attribute \src "libresoc.v:164943.3-164961.6" + process $proc$libresoc.v:164943$8888 assign { } { } assign { } { } assign { } { } @@ -306667,9 +306501,9 @@ module \pipe$64 assign { } { } assign $0\fast1$7$next[63:0]$8890 $1\fast1$7$next[63:0]$8892 assign $0\fast1_ok$next[0:0]$8889 $2\fast1_ok$next[0:0]$8893 - attribute \src "libresoc.v:165148.5-165148.29" + attribute \src "libresoc.v:164944.5-164944.29" switch \initial - attribute \src "libresoc.v:165148.9-165148.17" + attribute \src "libresoc.v:164944.9-164944.17" case 1'1 case end @@ -306702,8 +306536,8 @@ module \pipe$64 update \fast1_ok$next $0\fast1_ok$next[0:0]$8889 update \fast1$7$next $0\fast1$7$next[63:0]$8890 end - attribute \src "libresoc.v:165166.3-165184.6" - process $proc$libresoc.v:165166$8894 + attribute \src "libresoc.v:164962.3-164980.6" + process $proc$libresoc.v:164962$8894 assign { } { } assign { } { } assign { } { } @@ -306711,9 +306545,9 @@ module \pipe$64 assign { } { } assign $0\xer_so$8$next[0:0]$8896 $1\xer_so$8$next[0:0]$8898 assign $0\xer_so_ok$next[0:0]$8895 $2\xer_so_ok$next[0:0]$8899 - attribute \src "libresoc.v:165167.5-165167.29" + attribute \src "libresoc.v:164963.5-164963.29" switch \initial - attribute \src "libresoc.v:165167.9-165167.17" + attribute \src "libresoc.v:164963.9-164963.17" case 1'1 case end @@ -306746,8 +306580,8 @@ module \pipe$64 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8895 update \xer_so$8$next $0\xer_so$8$next[0:0]$8896 end - attribute \src "libresoc.v:165185.3-165203.6" - process $proc$libresoc.v:165185$8900 + attribute \src "libresoc.v:164981.3-164999.6" + process $proc$libresoc.v:164981$8900 assign { } { } assign { } { } assign { } { } @@ -306755,9 +306589,9 @@ module \pipe$64 assign { } { } assign $0\xer_ov$9$next[1:0]$8902 $1\xer_ov$9$next[1:0]$8904 assign $0\xer_ov_ok$next[0:0]$8901 $2\xer_ov_ok$next[0:0]$8905 - attribute \src "libresoc.v:165186.5-165186.29" + attribute \src "libresoc.v:164982.5-164982.29" switch \initial - attribute \src "libresoc.v:165186.9-165186.17" + attribute \src "libresoc.v:164982.9-164982.17" case 1'1 case end @@ -306790,8 +306624,8 @@ module \pipe$64 update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8901 update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8902 end - attribute \src "libresoc.v:165204.3-165222.6" - process $proc$libresoc.v:165204$8906 + attribute \src "libresoc.v:165000.3-165018.6" + process $proc$libresoc.v:165000$8906 assign { } { } assign { } { } assign { } { } @@ -306799,9 +306633,9 @@ module \pipe$64 assign $0\xer_ca$10$next[1:0]$8907 $1\xer_ca$10$next[1:0]$8909 assign { } { } assign $0\xer_ca_ok$next[0:0]$8908 $2\xer_ca_ok$next[0:0]$8911 - attribute \src "libresoc.v:165205.5-165205.29" + attribute \src "libresoc.v:165001.5-165001.29" switch \initial - attribute \src "libresoc.v:165205.9-165205.17" + attribute \src "libresoc.v:165001.9-165001.17" case 1'1 case end @@ -306834,7 +306668,7 @@ module \pipe$64 update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8907 update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8908 end - connect \$22 $and$libresoc.v:164987$8831_Y + connect \$22 $and$libresoc.v:164783$8831_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } @@ -306857,279 +306691,279 @@ module \pipe$64 connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \spr_main_muxid \muxid end -attribute \src "libresoc.v:165248.1-166740.10" +attribute \src "libresoc.v:165044.1-166536.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" attribute \generator "nMigen" module \pipe1 - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 4 $0\alu_op__data_len$next[3:0]$9004 - attribute \src "libresoc.v:166430.3-166431.49" + attribute \src "libresoc.v:166226.3-166227.49" wire width 4 $0\alu_op__data_len[3:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 14 $0\alu_op__fn_unit$next[13:0]$9005 - attribute \src "libresoc.v:166400.3-166401.47" + attribute \src "libresoc.v:166196.3-166197.47" wire width 14 $0\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 64 $0\alu_op__imm_data__data$next[63:0]$9006 - attribute \src "libresoc.v:166402.3-166403.61" + attribute \src "libresoc.v:166198.3-166199.61" wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__imm_data__ok$next[0:0]$9007 - attribute \src "libresoc.v:166404.3-166405.57" + attribute \src "libresoc.v:166200.3-166201.57" wire $0\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 2 $0\alu_op__input_carry$next[1:0]$9008 - attribute \src "libresoc.v:166422.3-166423.55" + attribute \src "libresoc.v:166218.3-166219.55" wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 32 $0\alu_op__insn$next[31:0]$9009 - attribute \src "libresoc.v:166432.3-166433.41" + attribute \src "libresoc.v:166228.3-166229.41" wire width 32 $0\alu_op__insn[31:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 7 $0\alu_op__insn_type$next[6:0]$9010 - attribute \src "libresoc.v:166398.3-166399.51" + attribute \src "libresoc.v:166194.3-166195.51" wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__invert_in$next[0:0]$9011 - attribute \src "libresoc.v:166414.3-166415.51" + attribute \src "libresoc.v:166210.3-166211.51" wire $0\alu_op__invert_in[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__invert_out$next[0:0]$9012 - attribute \src "libresoc.v:166418.3-166419.53" + attribute \src "libresoc.v:166214.3-166215.53" wire $0\alu_op__invert_out[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__is_32bit$next[0:0]$9013 - attribute \src "libresoc.v:166426.3-166427.49" + attribute \src "libresoc.v:166222.3-166223.49" wire $0\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__is_signed$next[0:0]$9014 - attribute \src "libresoc.v:166428.3-166429.51" + attribute \src "libresoc.v:166224.3-166225.51" wire $0\alu_op__is_signed[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__oe__oe$next[0:0]$9015 - attribute \src "libresoc.v:166410.3-166411.45" + attribute \src "libresoc.v:166206.3-166207.45" wire $0\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__oe__ok$next[0:0]$9016 - attribute \src "libresoc.v:166412.3-166413.45" + attribute \src "libresoc.v:166208.3-166209.45" wire $0\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__output_carry$next[0:0]$9017 - attribute \src "libresoc.v:166424.3-166425.57" + attribute \src "libresoc.v:166220.3-166221.57" wire $0\alu_op__output_carry[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__rc__ok$next[0:0]$9018 - attribute \src "libresoc.v:166408.3-166409.45" + attribute \src "libresoc.v:166204.3-166205.45" wire $0\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__rc__rc$next[0:0]$9019 - attribute \src "libresoc.v:166406.3-166407.45" + attribute \src "libresoc.v:166202.3-166203.45" wire $0\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__write_cr0$next[0:0]$9020 - attribute \src "libresoc.v:166420.3-166421.51" + attribute \src "libresoc.v:166216.3-166217.51" wire $0\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__zero_a$next[0:0]$9021 - attribute \src "libresoc.v:166416.3-166417.45" + attribute \src "libresoc.v:166212.3-166213.45" wire $0\alu_op__zero_a[0:0] - attribute \src "libresoc.v:166547.3-166565.6" + attribute \src "libresoc.v:166343.3-166361.6" wire width 4 $0\cr_a$next[3:0]$8973 - attribute \src "libresoc.v:166390.3-166391.25" + attribute \src "libresoc.v:166186.3-166187.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:166547.3-166565.6" + attribute \src "libresoc.v:166343.3-166361.6" wire $0\cr_a_ok$next[0:0]$8974 - attribute \src "libresoc.v:166392.3-166393.31" + attribute \src "libresoc.v:166188.3-166189.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:165249.7-165249.20" + attribute \src "libresoc.v:165045.7-165045.20" wire $0\initial[0:0] - attribute \src "libresoc.v:166641.3-166653.6" + attribute \src "libresoc.v:166437.3-166449.6" wire width 2 $0\muxid$next[1:0]$9001 - attribute \src "libresoc.v:166434.3-166435.27" + attribute \src "libresoc.v:166230.3-166231.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:166696.3-166714.6" + attribute \src "libresoc.v:166492.3-166510.6" wire width 64 $0\o$next[63:0]$9047 - attribute \src "libresoc.v:166394.3-166395.19" + attribute \src "libresoc.v:166190.3-166191.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:166696.3-166714.6" + attribute \src "libresoc.v:166492.3-166510.6" wire $0\o_ok$next[0:0]$9048 - attribute \src "libresoc.v:166396.3-166397.25" + attribute \src "libresoc.v:166192.3-166193.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:166623.3-166640.6" + attribute \src "libresoc.v:166419.3-166436.6" wire $0\r_busy$next[0:0]$8997 - attribute \src "libresoc.v:166436.3-166437.29" + attribute \src "libresoc.v:166232.3-166233.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:166566.3-166584.6" + attribute \src "libresoc.v:166362.3-166380.6" wire width 2 $0\xer_ca$next[1:0]$8980 - attribute \src "libresoc.v:166386.3-166387.29" + attribute \src "libresoc.v:166182.3-166183.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:166566.3-166584.6" + attribute \src "libresoc.v:166362.3-166380.6" wire $0\xer_ca_ok$next[0:0]$8979 - attribute \src "libresoc.v:166388.3-166389.35" + attribute \src "libresoc.v:166184.3-166185.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:166585.3-166603.6" + attribute \src "libresoc.v:166381.3-166399.6" wire width 2 $0\xer_ov$next[1:0]$8985 - attribute \src "libresoc.v:166382.3-166383.29" + attribute \src "libresoc.v:166178.3-166179.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:166585.3-166603.6" + attribute \src "libresoc.v:166381.3-166399.6" wire $0\xer_ov_ok$next[0:0]$8986 - attribute \src "libresoc.v:166384.3-166385.35" + attribute \src "libresoc.v:166180.3-166181.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:166604.3-166622.6" + attribute \src "libresoc.v:166400.3-166418.6" wire $0\xer_so$next[0:0]$8991 - attribute \src "libresoc.v:166378.3-166379.29" + attribute \src "libresoc.v:166174.3-166175.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:166604.3-166622.6" + attribute \src "libresoc.v:166400.3-166418.6" wire $0\xer_so_ok$next[0:0]$8992 - attribute \src "libresoc.v:166380.3-166381.35" + attribute \src "libresoc.v:166176.3-166177.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 4 $1\alu_op__data_len$next[3:0]$9022 - attribute \src "libresoc.v:165254.13-165254.36" + attribute \src "libresoc.v:165050.13-165050.36" wire width 4 $1\alu_op__data_len[3:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 14 $1\alu_op__fn_unit$next[13:0]$9023 - attribute \src "libresoc.v:165278.14-165278.40" + attribute \src "libresoc.v:165074.14-165074.40" wire width 14 $1\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 64 $1\alu_op__imm_data__data$next[63:0]$9024 - attribute \src "libresoc.v:165317.14-165317.59" + attribute \src "libresoc.v:165113.14-165113.59" wire width 64 $1\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__imm_data__ok$next[0:0]$9025 - attribute \src "libresoc.v:165326.7-165326.34" + attribute \src "libresoc.v:165122.7-165122.34" wire $1\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 2 $1\alu_op__input_carry$next[1:0]$9026 - attribute \src "libresoc.v:165339.13-165339.39" + attribute \src "libresoc.v:165135.13-165135.39" wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 32 $1\alu_op__insn$next[31:0]$9027 - attribute \src "libresoc.v:165356.14-165356.34" + attribute \src "libresoc.v:165152.14-165152.34" wire width 32 $1\alu_op__insn[31:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 7 $1\alu_op__insn_type$next[6:0]$9028 - attribute \src "libresoc.v:165440.13-165440.38" + attribute \src "libresoc.v:165236.13-165236.38" wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__invert_in$next[0:0]$9029 - attribute \src "libresoc.v:165599.7-165599.31" + attribute \src "libresoc.v:165395.7-165395.31" wire $1\alu_op__invert_in[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__invert_out$next[0:0]$9030 - attribute \src "libresoc.v:165608.7-165608.32" + attribute \src "libresoc.v:165404.7-165404.32" wire $1\alu_op__invert_out[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__is_32bit$next[0:0]$9031 - attribute \src "libresoc.v:165617.7-165617.30" + attribute \src "libresoc.v:165413.7-165413.30" wire $1\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__is_signed$next[0:0]$9032 - attribute \src "libresoc.v:165626.7-165626.31" + attribute \src "libresoc.v:165422.7-165422.31" wire $1\alu_op__is_signed[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__oe__oe$next[0:0]$9033 - attribute \src "libresoc.v:165635.7-165635.28" + attribute \src "libresoc.v:165431.7-165431.28" wire $1\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__oe__ok$next[0:0]$9034 - attribute \src "libresoc.v:165644.7-165644.28" + attribute \src "libresoc.v:165440.7-165440.28" wire $1\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__output_carry$next[0:0]$9035 - attribute \src "libresoc.v:165653.7-165653.34" + attribute \src "libresoc.v:165449.7-165449.34" wire $1\alu_op__output_carry[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__rc__ok$next[0:0]$9036 - attribute \src "libresoc.v:165662.7-165662.28" + attribute \src "libresoc.v:165458.7-165458.28" wire $1\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__rc__rc$next[0:0]$9037 - attribute \src "libresoc.v:165671.7-165671.28" + attribute \src "libresoc.v:165467.7-165467.28" wire $1\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__write_cr0$next[0:0]$9038 - attribute \src "libresoc.v:165680.7-165680.31" + attribute \src "libresoc.v:165476.7-165476.31" wire $1\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__zero_a$next[0:0]$9039 - attribute \src "libresoc.v:165689.7-165689.28" + attribute \src "libresoc.v:165485.7-165485.28" wire $1\alu_op__zero_a[0:0] - attribute \src "libresoc.v:166547.3-166565.6" + attribute \src "libresoc.v:166343.3-166361.6" wire width 4 $1\cr_a$next[3:0]$8975 - attribute \src "libresoc.v:165702.13-165702.24" + attribute \src "libresoc.v:165498.13-165498.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:166547.3-166565.6" + attribute \src "libresoc.v:166343.3-166361.6" wire $1\cr_a_ok$next[0:0]$8976 - attribute \src "libresoc.v:165709.7-165709.21" + attribute \src "libresoc.v:165505.7-165505.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:166641.3-166653.6" + attribute \src "libresoc.v:166437.3-166449.6" wire width 2 $1\muxid$next[1:0]$9002 - attribute \src "libresoc.v:166286.13-166286.25" + attribute \src "libresoc.v:166082.13-166082.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:166696.3-166714.6" + attribute \src "libresoc.v:166492.3-166510.6" wire width 64 $1\o$next[63:0]$9049 - attribute \src "libresoc.v:166301.14-166301.38" + attribute \src "libresoc.v:166097.14-166097.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:166696.3-166714.6" + attribute \src "libresoc.v:166492.3-166510.6" wire $1\o_ok$next[0:0]$9050 - attribute \src "libresoc.v:166308.7-166308.18" + attribute \src "libresoc.v:166104.7-166104.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:166623.3-166640.6" + attribute \src "libresoc.v:166419.3-166436.6" wire $1\r_busy$next[0:0]$8998 - attribute \src "libresoc.v:166322.7-166322.20" + attribute \src "libresoc.v:166118.7-166118.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:166566.3-166584.6" + attribute \src "libresoc.v:166362.3-166380.6" wire width 2 $1\xer_ca$next[1:0]$8982 - attribute \src "libresoc.v:166331.13-166331.26" + attribute \src "libresoc.v:166127.13-166127.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:166566.3-166584.6" + attribute \src "libresoc.v:166362.3-166380.6" wire $1\xer_ca_ok$next[0:0]$8981 - attribute \src "libresoc.v:166340.7-166340.23" + attribute \src "libresoc.v:166136.7-166136.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:166585.3-166603.6" + attribute \src "libresoc.v:166381.3-166399.6" wire width 2 $1\xer_ov$next[1:0]$8987 - attribute \src "libresoc.v:166347.13-166347.26" + attribute \src "libresoc.v:166143.13-166143.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:166585.3-166603.6" + attribute \src "libresoc.v:166381.3-166399.6" wire $1\xer_ov_ok$next[0:0]$8988 - attribute \src "libresoc.v:166354.7-166354.23" + attribute \src "libresoc.v:166150.7-166150.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:166604.3-166622.6" + attribute \src "libresoc.v:166400.3-166418.6" wire $1\xer_so$next[0:0]$8993 - attribute \src "libresoc.v:166361.7-166361.20" + attribute \src "libresoc.v:166157.7-166157.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:166604.3-166622.6" + attribute \src "libresoc.v:166400.3-166418.6" wire $1\xer_so_ok$next[0:0]$8994 - attribute \src "libresoc.v:166370.7-166370.23" + attribute \src "libresoc.v:166166.7-166166.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire width 64 $2\alu_op__imm_data__data$next[63:0]$9040 - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $2\alu_op__imm_data__ok$next[0:0]$9041 - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $2\alu_op__oe__oe$next[0:0]$9042 - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $2\alu_op__oe__ok$next[0:0]$9043 - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $2\alu_op__rc__ok$next[0:0]$9044 - attribute \src "libresoc.v:166654.3-166695.6" + attribute \src "libresoc.v:166450.3-166491.6" wire $2\alu_op__rc__rc$next[0:0]$9045 - attribute \src "libresoc.v:166547.3-166565.6" + attribute \src "libresoc.v:166343.3-166361.6" wire $2\cr_a_ok$next[0:0]$8977 - attribute \src "libresoc.v:166696.3-166714.6" + attribute \src "libresoc.v:166492.3-166510.6" wire $2\o_ok$next[0:0]$9051 - attribute \src "libresoc.v:166623.3-166640.6" + attribute \src "libresoc.v:166419.3-166436.6" wire $2\r_busy$next[0:0]$8999 - attribute \src "libresoc.v:166566.3-166584.6" + attribute \src "libresoc.v:166362.3-166380.6" wire $2\xer_ca_ok$next[0:0]$8983 - attribute \src "libresoc.v:166585.3-166603.6" + attribute \src "libresoc.v:166381.3-166399.6" wire $2\xer_ov_ok$next[0:0]$8989 - attribute \src "libresoc.v:166604.3-166622.6" + attribute \src "libresoc.v:166400.3-166418.6" wire $2\xer_so_ok$next[0:0]$8995 - attribute \src "libresoc.v:166377.18-166377.118" - wire $and$libresoc.v:166377$8941_Y + attribute \src "libresoc.v:166173.18-166173.118" + wire $and$libresoc.v:166173$8941_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -307558,9 +307392,9 @@ module \pipe1 wire \alu_op__zero_a$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a @@ -307574,7 +307408,7 @@ module \pipe1 wire \cr_a_ok$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next - attribute \src "libresoc.v:165249.7-165249.15" + attribute \src "libresoc.v:165045.7-165045.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_alu_op__data_len @@ -308231,7 +308065,7 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:166377$8941 + cell $and $and$libresoc.v:166173$8941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308239,10 +308073,10 @@ module \pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$66 connect \B \p_ready_o - connect \Y $and$libresoc.v:166377$8941_Y + connect \Y $and$libresoc.v:166173$8941_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:166438.11-166485.4" + attribute \src "libresoc.v:166234.11-166281.4" cell \input \input connect \alu_op__data_len \input_alu_op__data_len connect \alu_op__data_len$18 \input_alu_op__data_len$39 @@ -308292,7 +308126,7 @@ module \pipe1 connect \xer_so$22 \input_xer_so$43 end attribute \module_not_derived 1 - attribute \src "libresoc.v:166486.8-166538.4" + attribute \src "libresoc.v:166282.8-166334.4" cell \main \main connect \alu_op__data_len \main_alu_op__data_len connect \alu_op__data_len$18 \main_alu_op__data_len$62 @@ -308347,477 +308181,477 @@ module \pipe1 connect \xer_so$21 \main_xer_so$65 end attribute \module_not_derived 1 - attribute \src "libresoc.v:166539.9-166542.4" + attribute \src "libresoc.v:166335.9-166338.4" cell \n$2 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:166543.9-166546.4" + attribute \src "libresoc.v:166339.9-166342.4" cell \p$1 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:165249.7-165249.20" - process $proc$libresoc.v:165249$9052 + attribute \src "libresoc.v:165045.7-165045.20" + process $proc$libresoc.v:165045$9052 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:165254.13-165254.36" - process $proc$libresoc.v:165254$9053 + attribute \src "libresoc.v:165050.13-165050.36" + process $proc$libresoc.v:165050$9053 assign { } { } assign $1\alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_op__data_len $1\alu_op__data_len[3:0] end - attribute \src "libresoc.v:165278.14-165278.40" - process $proc$libresoc.v:165278$9054 + attribute \src "libresoc.v:165074.14-165074.40" + process $proc$libresoc.v:165074$9054 assign { } { } assign $1\alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_op__fn_unit $1\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:165317.14-165317.59" - process $proc$libresoc.v:165317$9055 + attribute \src "libresoc.v:165113.14-165113.59" + process $proc$libresoc.v:165113$9055 assign { } { } assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:165326.7-165326.34" - process $proc$libresoc.v:165326$9056 + attribute \src "libresoc.v:165122.7-165122.34" + process $proc$libresoc.v:165122$9056 assign { } { } assign $1\alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:165339.13-165339.39" - process $proc$libresoc.v:165339$9057 + attribute \src "libresoc.v:165135.13-165135.39" + process $proc$libresoc.v:165135$9057 assign { } { } assign $1\alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_op__input_carry $1\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:165356.14-165356.34" - process $proc$libresoc.v:165356$9058 + attribute \src "libresoc.v:165152.14-165152.34" + process $proc$libresoc.v:165152$9058 assign { } { } assign $1\alu_op__insn[31:0] 0 sync always sync init update \alu_op__insn $1\alu_op__insn[31:0] end - attribute \src "libresoc.v:165440.13-165440.38" - process $proc$libresoc.v:165440$9059 + attribute \src "libresoc.v:165236.13-165236.38" + process $proc$libresoc.v:165236$9059 assign { } { } assign $1\alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_op__insn_type $1\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:165599.7-165599.31" - process $proc$libresoc.v:165599$9060 + attribute \src "libresoc.v:165395.7-165395.31" + process $proc$libresoc.v:165395$9060 assign { } { } assign $1\alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_op__invert_in $1\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:165608.7-165608.32" - process $proc$libresoc.v:165608$9061 + attribute \src "libresoc.v:165404.7-165404.32" + process $proc$libresoc.v:165404$9061 assign { } { } assign $1\alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_op__invert_out $1\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:165617.7-165617.30" - process $proc$libresoc.v:165617$9062 + attribute \src "libresoc.v:165413.7-165413.30" + process $proc$libresoc.v:165413$9062 assign { } { } assign $1\alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:165626.7-165626.31" - process $proc$libresoc.v:165626$9063 + attribute \src "libresoc.v:165422.7-165422.31" + process $proc$libresoc.v:165422$9063 assign { } { } assign $1\alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_op__is_signed $1\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:165635.7-165635.28" - process $proc$libresoc.v:165635$9064 + attribute \src "libresoc.v:165431.7-165431.28" + process $proc$libresoc.v:165431$9064 assign { } { } assign $1\alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:165644.7-165644.28" - process $proc$libresoc.v:165644$9065 + attribute \src "libresoc.v:165440.7-165440.28" + process $proc$libresoc.v:165440$9065 assign { } { } assign $1\alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:165653.7-165653.34" - process $proc$libresoc.v:165653$9066 + attribute \src "libresoc.v:165449.7-165449.34" + process $proc$libresoc.v:165449$9066 assign { } { } assign $1\alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_op__output_carry $1\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:165662.7-165662.28" - process $proc$libresoc.v:165662$9067 + attribute \src "libresoc.v:165458.7-165458.28" + process $proc$libresoc.v:165458$9067 assign { } { } assign $1\alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:165671.7-165671.28" - process $proc$libresoc.v:165671$9068 + attribute \src "libresoc.v:165467.7-165467.28" + process $proc$libresoc.v:165467$9068 assign { } { } assign $1\alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:165680.7-165680.31" - process $proc$libresoc.v:165680$9069 + attribute \src "libresoc.v:165476.7-165476.31" + process $proc$libresoc.v:165476$9069 assign { } { } assign $1\alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:165689.7-165689.28" - process $proc$libresoc.v:165689$9070 + attribute \src "libresoc.v:165485.7-165485.28" + process $proc$libresoc.v:165485$9070 assign { } { } assign $1\alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_op__zero_a $1\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:165702.13-165702.24" - process $proc$libresoc.v:165702$9071 + attribute \src "libresoc.v:165498.13-165498.24" + process $proc$libresoc.v:165498$9071 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:165709.7-165709.21" - process $proc$libresoc.v:165709$9072 + attribute \src "libresoc.v:165505.7-165505.21" + process $proc$libresoc.v:165505$9072 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:166286.13-166286.25" - process $proc$libresoc.v:166286$9073 + attribute \src "libresoc.v:166082.13-166082.25" + process $proc$libresoc.v:166082$9073 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:166301.14-166301.38" - process $proc$libresoc.v:166301$9074 + attribute \src "libresoc.v:166097.14-166097.38" + process $proc$libresoc.v:166097$9074 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:166308.7-166308.18" - process $proc$libresoc.v:166308$9075 + attribute \src "libresoc.v:166104.7-166104.18" + process $proc$libresoc.v:166104$9075 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:166322.7-166322.20" - process $proc$libresoc.v:166322$9076 + attribute \src "libresoc.v:166118.7-166118.20" + process $proc$libresoc.v:166118$9076 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:166331.13-166331.26" - process $proc$libresoc.v:166331$9077 + attribute \src "libresoc.v:166127.13-166127.26" + process $proc$libresoc.v:166127$9077 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:166340.7-166340.23" - process $proc$libresoc.v:166340$9078 + attribute \src "libresoc.v:166136.7-166136.23" + process $proc$libresoc.v:166136$9078 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:166347.13-166347.26" - process $proc$libresoc.v:166347$9079 + attribute \src "libresoc.v:166143.13-166143.26" + process $proc$libresoc.v:166143$9079 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:166354.7-166354.23" - process $proc$libresoc.v:166354$9080 + attribute \src "libresoc.v:166150.7-166150.23" + process $proc$libresoc.v:166150$9080 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:166361.7-166361.20" - process $proc$libresoc.v:166361$9081 + attribute \src "libresoc.v:166157.7-166157.20" + process $proc$libresoc.v:166157$9081 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:166370.7-166370.23" - process $proc$libresoc.v:166370$9082 + attribute \src "libresoc.v:166166.7-166166.23" + process $proc$libresoc.v:166166$9082 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:166378.3-166379.29" - process $proc$libresoc.v:166378$8942 + attribute \src "libresoc.v:166174.3-166175.29" + process $proc$libresoc.v:166174$8942 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:166380.3-166381.35" - process $proc$libresoc.v:166380$8943 + attribute \src "libresoc.v:166176.3-166177.35" + process $proc$libresoc.v:166176$8943 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:166382.3-166383.29" - process $proc$libresoc.v:166382$8944 + attribute \src "libresoc.v:166178.3-166179.29" + process $proc$libresoc.v:166178$8944 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:166384.3-166385.35" - process $proc$libresoc.v:166384$8945 + attribute \src "libresoc.v:166180.3-166181.35" + process $proc$libresoc.v:166180$8945 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:166386.3-166387.29" - process $proc$libresoc.v:166386$8946 + attribute \src "libresoc.v:166182.3-166183.29" + process $proc$libresoc.v:166182$8946 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:166388.3-166389.35" - process $proc$libresoc.v:166388$8947 + attribute \src "libresoc.v:166184.3-166185.35" + process $proc$libresoc.v:166184$8947 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:166390.3-166391.25" - process $proc$libresoc.v:166390$8948 + attribute \src "libresoc.v:166186.3-166187.25" + process $proc$libresoc.v:166186$8948 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:166392.3-166393.31" - process $proc$libresoc.v:166392$8949 + attribute \src "libresoc.v:166188.3-166189.31" + process $proc$libresoc.v:166188$8949 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:166394.3-166395.19" - process $proc$libresoc.v:166394$8950 + attribute \src "libresoc.v:166190.3-166191.19" + process $proc$libresoc.v:166190$8950 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:166396.3-166397.25" - process $proc$libresoc.v:166396$8951 + attribute \src "libresoc.v:166192.3-166193.25" + process $proc$libresoc.v:166192$8951 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:166398.3-166399.51" - process $proc$libresoc.v:166398$8952 + attribute \src "libresoc.v:166194.3-166195.51" + process $proc$libresoc.v:166194$8952 assign { } { } assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next sync posedge \coresync_clk update \alu_op__insn_type $0\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:166400.3-166401.47" - process $proc$libresoc.v:166400$8953 + attribute \src "libresoc.v:166196.3-166197.47" + process $proc$libresoc.v:166196$8953 assign { } { } assign $0\alu_op__fn_unit[13:0] \alu_op__fn_unit$next sync posedge \coresync_clk update \alu_op__fn_unit $0\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:166402.3-166403.61" - process $proc$libresoc.v:166402$8954 + attribute \src "libresoc.v:166198.3-166199.61" + process $proc$libresoc.v:166198$8954 assign { } { } assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:166404.3-166405.57" - process $proc$libresoc.v:166404$8955 + attribute \src "libresoc.v:166200.3-166201.57" + process $proc$libresoc.v:166200$8955 assign { } { } assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:166406.3-166407.45" - process $proc$libresoc.v:166406$8956 + attribute \src "libresoc.v:166202.3-166203.45" + process $proc$libresoc.v:166202$8956 assign { } { } assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next sync posedge \coresync_clk update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:166408.3-166409.45" - process $proc$libresoc.v:166408$8957 + attribute \src "libresoc.v:166204.3-166205.45" + process $proc$libresoc.v:166204$8957 assign { } { } assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next sync posedge \coresync_clk update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:166410.3-166411.45" - process $proc$libresoc.v:166410$8958 + attribute \src "libresoc.v:166206.3-166207.45" + process $proc$libresoc.v:166206$8958 assign { } { } assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next sync posedge \coresync_clk update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:166412.3-166413.45" - process $proc$libresoc.v:166412$8959 + attribute \src "libresoc.v:166208.3-166209.45" + process $proc$libresoc.v:166208$8959 assign { } { } assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next sync posedge \coresync_clk update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:166414.3-166415.51" - process $proc$libresoc.v:166414$8960 + attribute \src "libresoc.v:166210.3-166211.51" + process $proc$libresoc.v:166210$8960 assign { } { } assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next sync posedge \coresync_clk update \alu_op__invert_in $0\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:166416.3-166417.45" - process $proc$libresoc.v:166416$8961 + attribute \src "libresoc.v:166212.3-166213.45" + process $proc$libresoc.v:166212$8961 assign { } { } assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next sync posedge \coresync_clk update \alu_op__zero_a $0\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:166418.3-166419.53" - process $proc$libresoc.v:166418$8962 + attribute \src "libresoc.v:166214.3-166215.53" + process $proc$libresoc.v:166214$8962 assign { } { } assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next sync posedge \coresync_clk update \alu_op__invert_out $0\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:166420.3-166421.51" - process $proc$libresoc.v:166420$8963 + attribute \src "libresoc.v:166216.3-166217.51" + process $proc$libresoc.v:166216$8963 assign { } { } assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next sync posedge \coresync_clk update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:166422.3-166423.55" - process $proc$libresoc.v:166422$8964 + attribute \src "libresoc.v:166218.3-166219.55" + process $proc$libresoc.v:166218$8964 assign { } { } assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next sync posedge \coresync_clk update \alu_op__input_carry $0\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:166424.3-166425.57" - process $proc$libresoc.v:166424$8965 + attribute \src "libresoc.v:166220.3-166221.57" + process $proc$libresoc.v:166220$8965 assign { } { } assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next sync posedge \coresync_clk update \alu_op__output_carry $0\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:166426.3-166427.49" - process $proc$libresoc.v:166426$8966 + attribute \src "libresoc.v:166222.3-166223.49" + process $proc$libresoc.v:166222$8966 assign { } { } assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next sync posedge \coresync_clk update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:166428.3-166429.51" - process $proc$libresoc.v:166428$8967 + attribute \src "libresoc.v:166224.3-166225.51" + process $proc$libresoc.v:166224$8967 assign { } { } assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next sync posedge \coresync_clk update \alu_op__is_signed $0\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:166430.3-166431.49" - process $proc$libresoc.v:166430$8968 + attribute \src "libresoc.v:166226.3-166227.49" + process $proc$libresoc.v:166226$8968 assign { } { } assign $0\alu_op__data_len[3:0] \alu_op__data_len$next sync posedge \coresync_clk update \alu_op__data_len $0\alu_op__data_len[3:0] end - attribute \src "libresoc.v:166432.3-166433.41" - process $proc$libresoc.v:166432$8969 + attribute \src "libresoc.v:166228.3-166229.41" + process $proc$libresoc.v:166228$8969 assign { } { } assign $0\alu_op__insn[31:0] \alu_op__insn$next sync posedge \coresync_clk update \alu_op__insn $0\alu_op__insn[31:0] end - attribute \src "libresoc.v:166434.3-166435.27" - process $proc$libresoc.v:166434$8970 + attribute \src "libresoc.v:166230.3-166231.27" + process $proc$libresoc.v:166230$8970 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:166436.3-166437.29" - process $proc$libresoc.v:166436$8971 + attribute \src "libresoc.v:166232.3-166233.29" + process $proc$libresoc.v:166232$8971 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:166547.3-166565.6" - process $proc$libresoc.v:166547$8972 + attribute \src "libresoc.v:166343.3-166361.6" + process $proc$libresoc.v:166343$8972 assign { } { } assign { } { } assign { } { } @@ -308825,9 +308659,9 @@ module \pipe1 assign $0\cr_a$next[3:0]$8973 $1\cr_a$next[3:0]$8975 assign { } { } assign $0\cr_a_ok$next[0:0]$8974 $2\cr_a_ok$next[0:0]$8977 - attribute \src "libresoc.v:166548.5-166548.29" + attribute \src "libresoc.v:166344.5-166344.29" switch \initial - attribute \src "libresoc.v:166548.9-166548.17" + attribute \src "libresoc.v:166344.9-166344.17" case 1'1 case end @@ -308860,8 +308694,8 @@ module \pipe1 update \cr_a$next $0\cr_a$next[3:0]$8973 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8974 end - attribute \src "libresoc.v:166566.3-166584.6" - process $proc$libresoc.v:166566$8978 + attribute \src "libresoc.v:166362.3-166380.6" + process $proc$libresoc.v:166362$8978 assign { } { } assign { } { } assign { } { } @@ -308869,9 +308703,9 @@ module \pipe1 assign { } { } assign $0\xer_ca$next[1:0]$8980 $1\xer_ca$next[1:0]$8982 assign $0\xer_ca_ok$next[0:0]$8979 $2\xer_ca_ok$next[0:0]$8983 - attribute \src "libresoc.v:166567.5-166567.29" + attribute \src "libresoc.v:166363.5-166363.29" switch \initial - attribute \src "libresoc.v:166567.9-166567.17" + attribute \src "libresoc.v:166363.9-166363.17" case 1'1 case end @@ -308904,8 +308738,8 @@ module \pipe1 update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8979 update \xer_ca$next $0\xer_ca$next[1:0]$8980 end - attribute \src "libresoc.v:166585.3-166603.6" - process $proc$libresoc.v:166585$8984 + attribute \src "libresoc.v:166381.3-166399.6" + process $proc$libresoc.v:166381$8984 assign { } { } assign { } { } assign { } { } @@ -308913,9 +308747,9 @@ module \pipe1 assign $0\xer_ov$next[1:0]$8985 $1\xer_ov$next[1:0]$8987 assign { } { } assign $0\xer_ov_ok$next[0:0]$8986 $2\xer_ov_ok$next[0:0]$8989 - attribute \src "libresoc.v:166586.5-166586.29" + attribute \src "libresoc.v:166382.5-166382.29" switch \initial - attribute \src "libresoc.v:166586.9-166586.17" + attribute \src "libresoc.v:166382.9-166382.17" case 1'1 case end @@ -308948,8 +308782,8 @@ module \pipe1 update \xer_ov$next $0\xer_ov$next[1:0]$8985 update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8986 end - attribute \src "libresoc.v:166604.3-166622.6" - process $proc$libresoc.v:166604$8990 + attribute \src "libresoc.v:166400.3-166418.6" + process $proc$libresoc.v:166400$8990 assign { } { } assign { } { } assign { } { } @@ -308957,9 +308791,9 @@ module \pipe1 assign $0\xer_so$next[0:0]$8991 $1\xer_so$next[0:0]$8993 assign { } { } assign $0\xer_so_ok$next[0:0]$8992 $2\xer_so_ok$next[0:0]$8995 - attribute \src "libresoc.v:166605.5-166605.29" + attribute \src "libresoc.v:166401.5-166401.29" switch \initial - attribute \src "libresoc.v:166605.9-166605.17" + attribute \src "libresoc.v:166401.9-166401.17" case 1'1 case end @@ -308992,15 +308826,15 @@ module \pipe1 update \xer_so$next $0\xer_so$next[0:0]$8991 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8992 end - attribute \src "libresoc.v:166623.3-166640.6" - process $proc$libresoc.v:166623$8996 + attribute \src "libresoc.v:166419.3-166436.6" + process $proc$libresoc.v:166419$8996 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8997 $2\r_busy$next[0:0]$8999 - attribute \src "libresoc.v:166624.5-166624.29" + attribute \src "libresoc.v:166420.5-166420.29" switch \initial - attribute \src "libresoc.v:166624.9-166624.17" + attribute \src "libresoc.v:166420.9-166420.17" case 1'1 case end @@ -309029,14 +308863,14 @@ module \pipe1 sync always update \r_busy$next $0\r_busy$next[0:0]$8997 end - attribute \src "libresoc.v:166641.3-166653.6" - process $proc$libresoc.v:166641$9000 + attribute \src "libresoc.v:166437.3-166449.6" + process $proc$libresoc.v:166437$9000 assign { } { } assign { } { } assign $0\muxid$next[1:0]$9001 $1\muxid$next[1:0]$9002 - attribute \src "libresoc.v:166642.5-166642.29" + attribute \src "libresoc.v:166438.5-166438.29" switch \initial - attribute \src "libresoc.v:166642.9-166642.17" + attribute \src "libresoc.v:166438.9-166438.17" case 1'1 case end @@ -309056,8 +308890,8 @@ module \pipe1 sync always update \muxid$next $0\muxid$next[1:0]$9001 end - attribute \src "libresoc.v:166654.3-166695.6" - process $proc$libresoc.v:166654$9003 + attribute \src "libresoc.v:166450.3-166491.6" + process $proc$libresoc.v:166450$9003 assign { } { } assign { } { } assign { } { } @@ -309118,9 +308952,9 @@ module \pipe1 assign $0\alu_op__oe__ok$next[0:0]$9016 $2\alu_op__oe__ok$next[0:0]$9043 assign $0\alu_op__rc__ok$next[0:0]$9018 $2\alu_op__rc__ok$next[0:0]$9044 assign $0\alu_op__rc__rc$next[0:0]$9019 $2\alu_op__rc__rc$next[0:0]$9045 - attribute \src "libresoc.v:166655.5-166655.29" + attribute \src "libresoc.v:166451.5-166451.29" switch \initial - attribute \src "libresoc.v:166655.9-166655.17" + attribute \src "libresoc.v:166451.9-166451.17" case 1'1 case end @@ -309232,8 +309066,8 @@ module \pipe1 update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9020 update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9021 end - attribute \src "libresoc.v:166696.3-166714.6" - process $proc$libresoc.v:166696$9046 + attribute \src "libresoc.v:166492.3-166510.6" + process $proc$libresoc.v:166492$9046 assign { } { } assign { } { } assign { } { } @@ -309241,9 +309075,9 @@ module \pipe1 assign $0\o$next[63:0]$9047 $1\o$next[63:0]$9049 assign { } { } assign $0\o_ok$next[0:0]$9048 $2\o_ok$next[0:0]$9051 - attribute \src "libresoc.v:166697.5-166697.29" + attribute \src "libresoc.v:166493.5-166493.29" switch \initial - attribute \src "libresoc.v:166697.9-166697.17" + attribute \src "libresoc.v:166493.9-166493.17" case 1'1 case end @@ -309276,7 +309110,7 @@ module \pipe1 update \o$next $0\o$next[63:0]$9047 update \o_ok$next $0\o_ok$next[0:0]$9048 end - connect \$67 $and$libresoc.v:166377$8941_Y + connect \$67 $and$libresoc.v:166173$8941_Y connect \xer_so_ok$98 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy @@ -309303,258 +309137,258 @@ module \pipe1 connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:166744.1-168180.10" +attribute \src "libresoc.v:166540.1-167976.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" attribute \generator "nMigen" module \pipe1$110 - attribute \src "libresoc.v:168113.3-168131.6" + attribute \src "libresoc.v:167909.3-167927.6" wire width 4 $0\cr_a$next[3:0]$9172 - attribute \src "libresoc.v:167855.3-167856.25" + attribute \src "libresoc.v:167651.3-167652.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:168113.3-168131.6" + attribute \src "libresoc.v:167909.3-167927.6" wire $0\cr_a_ok$next[0:0]$9173 - attribute \src "libresoc.v:167857.3-167858.31" + attribute \src "libresoc.v:167653.3-167654.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:166745.7-166745.20" + attribute \src "libresoc.v:166541.7-166541.20" wire $0\initial[0:0] - attribute \src "libresoc.v:168040.3-168052.6" + attribute \src "libresoc.v:167836.3-167848.6" wire width 2 $0\muxid$next[1:0]$9122 - attribute \src "libresoc.v:167897.3-167898.27" + attribute \src "libresoc.v:167693.3-167694.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:168094.3-168112.6" + attribute \src "libresoc.v:167890.3-167908.6" wire width 64 $0\o$next[63:0]$9166 - attribute \src "libresoc.v:167859.3-167860.19" + attribute \src "libresoc.v:167655.3-167656.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:168094.3-168112.6" + attribute \src "libresoc.v:167890.3-167908.6" wire $0\o_ok$next[0:0]$9167 - attribute \src "libresoc.v:167861.3-167862.25" + attribute \src "libresoc.v:167657.3-167658.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:168022.3-168039.6" + attribute \src "libresoc.v:167818.3-167835.6" wire $0\r_busy$next[0:0]$9118 - attribute \src "libresoc.v:167899.3-167900.29" + attribute \src "libresoc.v:167695.3-167696.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire width 14 $0\sr_op__fn_unit$next[13:0]$9125 - attribute \src "libresoc.v:167865.3-167866.45" + attribute \src "libresoc.v:167661.3-167662.45" wire width 14 $0\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire width 64 $0\sr_op__imm_data__data$next[63:0]$9126 - attribute \src "libresoc.v:167867.3-167868.59" + attribute \src "libresoc.v:167663.3-167664.59" wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__imm_data__ok$next[0:0]$9127 - attribute \src "libresoc.v:167869.3-167870.55" + attribute \src "libresoc.v:167665.3-167666.55" wire $0\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire width 2 $0\sr_op__input_carry$next[1:0]$9128 - attribute \src "libresoc.v:167883.3-167884.53" + attribute \src "libresoc.v:167679.3-167680.53" wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__input_cr$next[0:0]$9129 - attribute \src "libresoc.v:167887.3-167888.47" + attribute \src "libresoc.v:167683.3-167684.47" wire $0\sr_op__input_cr[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire width 32 $0\sr_op__insn$next[31:0]$9130 - attribute \src "libresoc.v:167895.3-167896.39" + attribute \src "libresoc.v:167691.3-167692.39" wire width 32 $0\sr_op__insn[31:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire width 7 $0\sr_op__insn_type$next[6:0]$9131 - attribute \src "libresoc.v:167863.3-167864.49" + attribute \src "libresoc.v:167659.3-167660.49" wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__invert_in$next[0:0]$9132 - attribute \src "libresoc.v:167881.3-167882.49" + attribute \src "libresoc.v:167677.3-167678.49" wire $0\sr_op__invert_in[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__is_32bit$next[0:0]$9133 - attribute \src "libresoc.v:167891.3-167892.47" + attribute \src "libresoc.v:167687.3-167688.47" wire $0\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__is_signed$next[0:0]$9134 - attribute \src "libresoc.v:167893.3-167894.49" + attribute \src "libresoc.v:167689.3-167690.49" wire $0\sr_op__is_signed[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__oe__oe$next[0:0]$9135 - attribute \src "libresoc.v:167875.3-167876.43" + attribute \src "libresoc.v:167671.3-167672.43" wire $0\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__oe__ok$next[0:0]$9136 - attribute \src "libresoc.v:167877.3-167878.43" + attribute \src "libresoc.v:167673.3-167674.43" wire $0\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__output_carry$next[0:0]$9137 - attribute \src "libresoc.v:167885.3-167886.55" + attribute \src "libresoc.v:167681.3-167682.55" wire $0\sr_op__output_carry[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__output_cr$next[0:0]$9138 - attribute \src "libresoc.v:167889.3-167890.49" + attribute \src "libresoc.v:167685.3-167686.49" wire $0\sr_op__output_cr[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__rc__ok$next[0:0]$9139 - attribute \src "libresoc.v:167873.3-167874.43" + attribute \src "libresoc.v:167669.3-167670.43" wire $0\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__rc__rc$next[0:0]$9140 - attribute \src "libresoc.v:167871.3-167872.43" + attribute \src "libresoc.v:167667.3-167668.43" wire $0\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__write_cr0$next[0:0]$9141 - attribute \src "libresoc.v:167879.3-167880.49" + attribute \src "libresoc.v:167675.3-167676.49" wire $0\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:168003.3-168021.6" + attribute \src "libresoc.v:167799.3-167817.6" wire width 2 $0\xer_ca$next[1:0]$9113 - attribute \src "libresoc.v:167847.3-167848.29" + attribute \src "libresoc.v:167643.3-167644.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:168003.3-168021.6" + attribute \src "libresoc.v:167799.3-167817.6" wire $0\xer_ca_ok$next[0:0]$9112 - attribute \src "libresoc.v:167849.3-167850.35" + attribute \src "libresoc.v:167645.3-167646.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:168132.3-168150.6" + attribute \src "libresoc.v:167928.3-167946.6" wire $0\xer_so$next[0:0]$9178 - attribute \src "libresoc.v:167851.3-167852.29" + attribute \src "libresoc.v:167647.3-167648.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:168132.3-168150.6" + attribute \src "libresoc.v:167928.3-167946.6" wire $0\xer_so_ok$next[0:0]$9179 - attribute \src "libresoc.v:167853.3-167854.35" + attribute \src "libresoc.v:167649.3-167650.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:168113.3-168131.6" + attribute \src "libresoc.v:167909.3-167927.6" wire width 4 $1\cr_a$next[3:0]$9174 - attribute \src "libresoc.v:166754.13-166754.24" + attribute \src "libresoc.v:166550.13-166550.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:168113.3-168131.6" + attribute \src "libresoc.v:167909.3-167927.6" wire $1\cr_a_ok$next[0:0]$9175 - attribute \src "libresoc.v:166763.7-166763.21" + attribute \src "libresoc.v:166559.7-166559.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:168040.3-168052.6" + attribute \src "libresoc.v:167836.3-167848.6" wire width 2 $1\muxid$next[1:0]$9123 - attribute \src "libresoc.v:167328.13-167328.25" + attribute \src "libresoc.v:167124.13-167124.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:168094.3-168112.6" + attribute \src "libresoc.v:167890.3-167908.6" wire width 64 $1\o$next[63:0]$9168 - attribute \src "libresoc.v:167343.14-167343.38" + attribute \src "libresoc.v:167139.14-167139.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:168094.3-168112.6" + attribute \src "libresoc.v:167890.3-167908.6" wire $1\o_ok$next[0:0]$9169 - attribute \src "libresoc.v:167350.7-167350.18" + attribute \src "libresoc.v:167146.7-167146.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:168022.3-168039.6" + attribute \src "libresoc.v:167818.3-167835.6" wire $1\r_busy$next[0:0]$9119 - attribute \src "libresoc.v:167364.7-167364.20" + attribute \src "libresoc.v:167160.7-167160.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire width 14 $1\sr_op__fn_unit$next[13:0]$9142 - attribute \src "libresoc.v:167390.14-167390.39" + attribute \src "libresoc.v:167186.14-167186.39" wire width 14 $1\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire width 64 $1\sr_op__imm_data__data$next[63:0]$9143 - attribute \src "libresoc.v:167429.14-167429.58" + attribute \src "libresoc.v:167225.14-167225.58" wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__imm_data__ok$next[0:0]$9144 - attribute \src "libresoc.v:167438.7-167438.33" + attribute \src "libresoc.v:167234.7-167234.33" wire $1\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire width 2 $1\sr_op__input_carry$next[1:0]$9145 - attribute \src "libresoc.v:167451.13-167451.38" + attribute \src "libresoc.v:167247.13-167247.38" wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__input_cr$next[0:0]$9146 - attribute \src "libresoc.v:167468.7-167468.29" + attribute \src "libresoc.v:167264.7-167264.29" wire $1\sr_op__input_cr[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire width 32 $1\sr_op__insn$next[31:0]$9147 - attribute \src "libresoc.v:167477.14-167477.33" + attribute \src "libresoc.v:167273.14-167273.33" wire width 32 $1\sr_op__insn[31:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire width 7 $1\sr_op__insn_type$next[6:0]$9148 - attribute \src "libresoc.v:167561.13-167561.37" + attribute \src "libresoc.v:167357.13-167357.37" wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__invert_in$next[0:0]$9149 - attribute \src "libresoc.v:167720.7-167720.30" + attribute \src "libresoc.v:167516.7-167516.30" wire $1\sr_op__invert_in[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__is_32bit$next[0:0]$9150 - attribute \src "libresoc.v:167729.7-167729.29" + attribute \src "libresoc.v:167525.7-167525.29" wire $1\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__is_signed$next[0:0]$9151 - attribute \src "libresoc.v:167738.7-167738.30" + attribute \src "libresoc.v:167534.7-167534.30" wire $1\sr_op__is_signed[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__oe__oe$next[0:0]$9152 - attribute \src "libresoc.v:167747.7-167747.27" + attribute \src "libresoc.v:167543.7-167543.27" wire $1\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__oe__ok$next[0:0]$9153 - attribute \src "libresoc.v:167756.7-167756.27" + attribute \src "libresoc.v:167552.7-167552.27" wire $1\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__output_carry$next[0:0]$9154 - attribute \src "libresoc.v:167765.7-167765.33" + attribute \src "libresoc.v:167561.7-167561.33" wire $1\sr_op__output_carry[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__output_cr$next[0:0]$9155 - attribute \src "libresoc.v:167774.7-167774.30" + attribute \src "libresoc.v:167570.7-167570.30" wire $1\sr_op__output_cr[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__rc__ok$next[0:0]$9156 - attribute \src "libresoc.v:167783.7-167783.27" + attribute \src "libresoc.v:167579.7-167579.27" wire $1\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__rc__rc$next[0:0]$9157 - attribute \src "libresoc.v:167792.7-167792.27" + attribute \src "libresoc.v:167588.7-167588.27" wire $1\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__write_cr0$next[0:0]$9158 - attribute \src "libresoc.v:167801.7-167801.30" + attribute \src "libresoc.v:167597.7-167597.30" wire $1\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:168003.3-168021.6" + attribute \src "libresoc.v:167799.3-167817.6" wire width 2 $1\xer_ca$next[1:0]$9115 - attribute \src "libresoc.v:167810.13-167810.26" + attribute \src "libresoc.v:167606.13-167606.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:168003.3-168021.6" + attribute \src "libresoc.v:167799.3-167817.6" wire $1\xer_ca_ok$next[0:0]$9114 - attribute \src "libresoc.v:167821.7-167821.23" + attribute \src "libresoc.v:167617.7-167617.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:168132.3-168150.6" + attribute \src "libresoc.v:167928.3-167946.6" wire $1\xer_so$next[0:0]$9180 - attribute \src "libresoc.v:167830.7-167830.20" + attribute \src "libresoc.v:167626.7-167626.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:168132.3-168150.6" + attribute \src "libresoc.v:167928.3-167946.6" wire $1\xer_so_ok$next[0:0]$9181 - attribute \src "libresoc.v:167839.7-167839.23" + attribute \src "libresoc.v:167635.7-167635.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:168113.3-168131.6" + attribute \src "libresoc.v:167909.3-167927.6" wire $2\cr_a_ok$next[0:0]$9176 - attribute \src "libresoc.v:168094.3-168112.6" + attribute \src "libresoc.v:167890.3-167908.6" wire $2\o_ok$next[0:0]$9170 - attribute \src "libresoc.v:168022.3-168039.6" + attribute \src "libresoc.v:167818.3-167835.6" wire $2\r_busy$next[0:0]$9120 - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire width 64 $2\sr_op__imm_data__data$next[63:0]$9159 - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $2\sr_op__imm_data__ok$next[0:0]$9160 - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $2\sr_op__oe__oe$next[0:0]$9161 - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $2\sr_op__oe__ok$next[0:0]$9162 - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $2\sr_op__rc__ok$next[0:0]$9163 - attribute \src "libresoc.v:168053.3-168093.6" + attribute \src "libresoc.v:167849.3-167889.6" wire $2\sr_op__rc__rc$next[0:0]$9164 - attribute \src "libresoc.v:168003.3-168021.6" + attribute \src "libresoc.v:167799.3-167817.6" wire $2\xer_ca_ok$next[0:0]$9116 - attribute \src "libresoc.v:168132.3-168150.6" + attribute \src "libresoc.v:167928.3-167946.6" wire $2\xer_so_ok$next[0:0]$9182 - attribute \src "libresoc.v:167846.18-167846.118" - wire $and$libresoc.v:167846$9083_Y + attribute \src "libresoc.v:167642.18-167642.118" + wire $and$libresoc.v:167642$9083_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 55 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 24 \cr_a @@ -309572,7 +309406,7 @@ module \pipe1$110 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next - attribute \src "libresoc.v:166745.7-166745.15" + attribute \src "libresoc.v:166541.7-166541.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid @@ -310627,7 +310461,7 @@ module \pipe1$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:167846$9083 + cell $and $and$libresoc.v:167642$9083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310635,10 +310469,10 @@ module \pipe1$110 parameter \Y_WIDTH 1 connect \A \p_valid_i$64 connect \B \p_ready_o - connect \Y $and$libresoc.v:167846$9083_Y + connect \Y $and$libresoc.v:167642$9083_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:167901.15-167948.4" + attribute \src "libresoc.v:167697.15-167744.4" cell \input$113 \input connect \muxid \input_muxid connect \muxid$1 \input_muxid$21 @@ -310688,7 +310522,7 @@ module \pipe1$110 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:167949.14-167994.4" + attribute \src "libresoc.v:167745.14-167790.4" cell \main$114 \main connect \muxid \main_muxid connect \muxid$1 \main_muxid$44 @@ -310736,432 +310570,432 @@ module \pipe1$110 connect \xer_so$19 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:167995.11-167998.4" + attribute \src "libresoc.v:167791.11-167794.4" cell \n$112 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:167999.11-168002.4" + attribute \src "libresoc.v:167795.11-167798.4" cell \p$111 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:166745.7-166745.20" - process $proc$libresoc.v:166745$9183 + attribute \src "libresoc.v:166541.7-166541.20" + process $proc$libresoc.v:166541$9183 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:166754.13-166754.24" - process $proc$libresoc.v:166754$9184 + attribute \src "libresoc.v:166550.13-166550.24" + process $proc$libresoc.v:166550$9184 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:166763.7-166763.21" - process $proc$libresoc.v:166763$9185 + attribute \src "libresoc.v:166559.7-166559.21" + process $proc$libresoc.v:166559$9185 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:167328.13-167328.25" - process $proc$libresoc.v:167328$9186 + attribute \src "libresoc.v:167124.13-167124.25" + process $proc$libresoc.v:167124$9186 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:167343.14-167343.38" - process $proc$libresoc.v:167343$9187 + attribute \src "libresoc.v:167139.14-167139.38" + process $proc$libresoc.v:167139$9187 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:167350.7-167350.18" - process $proc$libresoc.v:167350$9188 + attribute \src "libresoc.v:167146.7-167146.18" + process $proc$libresoc.v:167146$9188 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:167364.7-167364.20" - process $proc$libresoc.v:167364$9189 + attribute \src "libresoc.v:167160.7-167160.20" + process $proc$libresoc.v:167160$9189 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:167390.14-167390.39" - process $proc$libresoc.v:167390$9190 + attribute \src "libresoc.v:167186.14-167186.39" + process $proc$libresoc.v:167186$9190 assign { } { } assign $1\sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \sr_op__fn_unit $1\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:167429.14-167429.58" - process $proc$libresoc.v:167429$9191 + attribute \src "libresoc.v:167225.14-167225.58" + process $proc$libresoc.v:167225$9191 assign { } { } assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:167438.7-167438.33" - process $proc$libresoc.v:167438$9192 + attribute \src "libresoc.v:167234.7-167234.33" + process $proc$libresoc.v:167234$9192 assign { } { } assign $1\sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:167451.13-167451.38" - process $proc$libresoc.v:167451$9193 + attribute \src "libresoc.v:167247.13-167247.38" + process $proc$libresoc.v:167247$9193 assign { } { } assign $1\sr_op__input_carry[1:0] 2'00 sync always sync init update \sr_op__input_carry $1\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:167468.7-167468.29" - process $proc$libresoc.v:167468$9194 + attribute \src "libresoc.v:167264.7-167264.29" + process $proc$libresoc.v:167264$9194 assign { } { } assign $1\sr_op__input_cr[0:0] 1'0 sync always sync init update \sr_op__input_cr $1\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:167477.14-167477.33" - process $proc$libresoc.v:167477$9195 + attribute \src "libresoc.v:167273.14-167273.33" + process $proc$libresoc.v:167273$9195 assign { } { } assign $1\sr_op__insn[31:0] 0 sync always sync init update \sr_op__insn $1\sr_op__insn[31:0] end - attribute \src "libresoc.v:167561.13-167561.37" - process $proc$libresoc.v:167561$9196 + attribute \src "libresoc.v:167357.13-167357.37" + process $proc$libresoc.v:167357$9196 assign { } { } assign $1\sr_op__insn_type[6:0] 7'0000000 sync always sync init update \sr_op__insn_type $1\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:167720.7-167720.30" - process $proc$libresoc.v:167720$9197 + attribute \src "libresoc.v:167516.7-167516.30" + process $proc$libresoc.v:167516$9197 assign { } { } assign $1\sr_op__invert_in[0:0] 1'0 sync always sync init update \sr_op__invert_in $1\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:167729.7-167729.29" - process $proc$libresoc.v:167729$9198 + attribute \src "libresoc.v:167525.7-167525.29" + process $proc$libresoc.v:167525$9198 assign { } { } assign $1\sr_op__is_32bit[0:0] 1'0 sync always sync init update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:167738.7-167738.30" - process $proc$libresoc.v:167738$9199 + attribute \src "libresoc.v:167534.7-167534.30" + process $proc$libresoc.v:167534$9199 assign { } { } assign $1\sr_op__is_signed[0:0] 1'0 sync always sync init update \sr_op__is_signed $1\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:167747.7-167747.27" - process $proc$libresoc.v:167747$9200 + attribute \src "libresoc.v:167543.7-167543.27" + process $proc$libresoc.v:167543$9200 assign { } { } assign $1\sr_op__oe__oe[0:0] 1'0 sync always sync init update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:167756.7-167756.27" - process $proc$libresoc.v:167756$9201 + attribute \src "libresoc.v:167552.7-167552.27" + process $proc$libresoc.v:167552$9201 assign { } { } assign $1\sr_op__oe__ok[0:0] 1'0 sync always sync init update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:167765.7-167765.33" - process $proc$libresoc.v:167765$9202 + attribute \src "libresoc.v:167561.7-167561.33" + process $proc$libresoc.v:167561$9202 assign { } { } assign $1\sr_op__output_carry[0:0] 1'0 sync always sync init update \sr_op__output_carry $1\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:167774.7-167774.30" - process $proc$libresoc.v:167774$9203 + attribute \src "libresoc.v:167570.7-167570.30" + process $proc$libresoc.v:167570$9203 assign { } { } assign $1\sr_op__output_cr[0:0] 1'0 sync always sync init update \sr_op__output_cr $1\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:167783.7-167783.27" - process $proc$libresoc.v:167783$9204 + attribute \src "libresoc.v:167579.7-167579.27" + process $proc$libresoc.v:167579$9204 assign { } { } assign $1\sr_op__rc__ok[0:0] 1'0 sync always sync init update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:167792.7-167792.27" - process $proc$libresoc.v:167792$9205 + attribute \src "libresoc.v:167588.7-167588.27" + process $proc$libresoc.v:167588$9205 assign { } { } assign $1\sr_op__rc__rc[0:0] 1'0 sync always sync init update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:167801.7-167801.30" - process $proc$libresoc.v:167801$9206 + attribute \src "libresoc.v:167597.7-167597.30" + process $proc$libresoc.v:167597$9206 assign { } { } assign $1\sr_op__write_cr0[0:0] 1'0 sync always sync init update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:167810.13-167810.26" - process $proc$libresoc.v:167810$9207 + attribute \src "libresoc.v:167606.13-167606.26" + process $proc$libresoc.v:167606$9207 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:167821.7-167821.23" - process $proc$libresoc.v:167821$9208 + attribute \src "libresoc.v:167617.7-167617.23" + process $proc$libresoc.v:167617$9208 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:167830.7-167830.20" - process $proc$libresoc.v:167830$9209 + attribute \src "libresoc.v:167626.7-167626.20" + process $proc$libresoc.v:167626$9209 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:167839.7-167839.23" - process $proc$libresoc.v:167839$9210 + attribute \src "libresoc.v:167635.7-167635.23" + process $proc$libresoc.v:167635$9210 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:167847.3-167848.29" - process $proc$libresoc.v:167847$9084 + attribute \src "libresoc.v:167643.3-167644.29" + process $proc$libresoc.v:167643$9084 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:167849.3-167850.35" - process $proc$libresoc.v:167849$9085 + attribute \src "libresoc.v:167645.3-167646.35" + process $proc$libresoc.v:167645$9085 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:167851.3-167852.29" - process $proc$libresoc.v:167851$9086 + attribute \src "libresoc.v:167647.3-167648.29" + process $proc$libresoc.v:167647$9086 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:167853.3-167854.35" - process $proc$libresoc.v:167853$9087 + attribute \src "libresoc.v:167649.3-167650.35" + process $proc$libresoc.v:167649$9087 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:167855.3-167856.25" - process $proc$libresoc.v:167855$9088 + attribute \src "libresoc.v:167651.3-167652.25" + process $proc$libresoc.v:167651$9088 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:167857.3-167858.31" - process $proc$libresoc.v:167857$9089 + attribute \src "libresoc.v:167653.3-167654.31" + process $proc$libresoc.v:167653$9089 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:167859.3-167860.19" - process $proc$libresoc.v:167859$9090 + attribute \src "libresoc.v:167655.3-167656.19" + process $proc$libresoc.v:167655$9090 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:167861.3-167862.25" - process $proc$libresoc.v:167861$9091 + attribute \src "libresoc.v:167657.3-167658.25" + process $proc$libresoc.v:167657$9091 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:167863.3-167864.49" - process $proc$libresoc.v:167863$9092 + attribute \src "libresoc.v:167659.3-167660.49" + process $proc$libresoc.v:167659$9092 assign { } { } assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next sync posedge \coresync_clk update \sr_op__insn_type $0\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:167865.3-167866.45" - process $proc$libresoc.v:167865$9093 + attribute \src "libresoc.v:167661.3-167662.45" + process $proc$libresoc.v:167661$9093 assign { } { } assign $0\sr_op__fn_unit[13:0] \sr_op__fn_unit$next sync posedge \coresync_clk update \sr_op__fn_unit $0\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:167867.3-167868.59" - process $proc$libresoc.v:167867$9094 + attribute \src "libresoc.v:167663.3-167664.59" + process $proc$libresoc.v:167663$9094 assign { } { } assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next sync posedge \coresync_clk update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:167869.3-167870.55" - process $proc$libresoc.v:167869$9095 + attribute \src "libresoc.v:167665.3-167666.55" + process $proc$libresoc.v:167665$9095 assign { } { } assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next sync posedge \coresync_clk update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:167871.3-167872.43" - process $proc$libresoc.v:167871$9096 + attribute \src "libresoc.v:167667.3-167668.43" + process $proc$libresoc.v:167667$9096 assign { } { } assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next sync posedge \coresync_clk update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:167873.3-167874.43" - process $proc$libresoc.v:167873$9097 + attribute \src "libresoc.v:167669.3-167670.43" + process $proc$libresoc.v:167669$9097 assign { } { } assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next sync posedge \coresync_clk update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:167875.3-167876.43" - process $proc$libresoc.v:167875$9098 + attribute \src "libresoc.v:167671.3-167672.43" + process $proc$libresoc.v:167671$9098 assign { } { } assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next sync posedge \coresync_clk update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:167877.3-167878.43" - process $proc$libresoc.v:167877$9099 + attribute \src "libresoc.v:167673.3-167674.43" + process $proc$libresoc.v:167673$9099 assign { } { } assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next sync posedge \coresync_clk update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:167879.3-167880.49" - process $proc$libresoc.v:167879$9100 + attribute \src "libresoc.v:167675.3-167676.49" + process $proc$libresoc.v:167675$9100 assign { } { } assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next sync posedge \coresync_clk update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:167881.3-167882.49" - process $proc$libresoc.v:167881$9101 + attribute \src "libresoc.v:167677.3-167678.49" + process $proc$libresoc.v:167677$9101 assign { } { } assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next sync posedge \coresync_clk update \sr_op__invert_in $0\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:167883.3-167884.53" - process $proc$libresoc.v:167883$9102 + attribute \src "libresoc.v:167679.3-167680.53" + process $proc$libresoc.v:167679$9102 assign { } { } assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next sync posedge \coresync_clk update \sr_op__input_carry $0\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:167885.3-167886.55" - process $proc$libresoc.v:167885$9103 + attribute \src "libresoc.v:167681.3-167682.55" + process $proc$libresoc.v:167681$9103 assign { } { } assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next sync posedge \coresync_clk update \sr_op__output_carry $0\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:167887.3-167888.47" - process $proc$libresoc.v:167887$9104 + attribute \src "libresoc.v:167683.3-167684.47" + process $proc$libresoc.v:167683$9104 assign { } { } assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next sync posedge \coresync_clk update \sr_op__input_cr $0\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:167889.3-167890.49" - process $proc$libresoc.v:167889$9105 + attribute \src "libresoc.v:167685.3-167686.49" + process $proc$libresoc.v:167685$9105 assign { } { } assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next sync posedge \coresync_clk update \sr_op__output_cr $0\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:167891.3-167892.47" - process $proc$libresoc.v:167891$9106 + attribute \src "libresoc.v:167687.3-167688.47" + process $proc$libresoc.v:167687$9106 assign { } { } assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next sync posedge \coresync_clk update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:167893.3-167894.49" - process $proc$libresoc.v:167893$9107 + attribute \src "libresoc.v:167689.3-167690.49" + process $proc$libresoc.v:167689$9107 assign { } { } assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next sync posedge \coresync_clk update \sr_op__is_signed $0\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:167895.3-167896.39" - process $proc$libresoc.v:167895$9108 + attribute \src "libresoc.v:167691.3-167692.39" + process $proc$libresoc.v:167691$9108 assign { } { } assign $0\sr_op__insn[31:0] \sr_op__insn$next sync posedge \coresync_clk update \sr_op__insn $0\sr_op__insn[31:0] end - attribute \src "libresoc.v:167897.3-167898.27" - process $proc$libresoc.v:167897$9109 + attribute \src "libresoc.v:167693.3-167694.27" + process $proc$libresoc.v:167693$9109 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:167899.3-167900.29" - process $proc$libresoc.v:167899$9110 + attribute \src "libresoc.v:167695.3-167696.29" + process $proc$libresoc.v:167695$9110 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:168003.3-168021.6" - process $proc$libresoc.v:168003$9111 + attribute \src "libresoc.v:167799.3-167817.6" + process $proc$libresoc.v:167799$9111 assign { } { } assign { } { } assign { } { } @@ -311169,9 +311003,9 @@ module \pipe1$110 assign { } { } assign $0\xer_ca$next[1:0]$9113 $1\xer_ca$next[1:0]$9115 assign $0\xer_ca_ok$next[0:0]$9112 $2\xer_ca_ok$next[0:0]$9116 - attribute \src "libresoc.v:168004.5-168004.29" + attribute \src "libresoc.v:167800.5-167800.29" switch \initial - attribute \src "libresoc.v:168004.9-168004.17" + attribute \src "libresoc.v:167800.9-167800.17" case 1'1 case end @@ -311204,15 +311038,15 @@ module \pipe1$110 update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9112 update \xer_ca$next $0\xer_ca$next[1:0]$9113 end - attribute \src "libresoc.v:168022.3-168039.6" - process $proc$libresoc.v:168022$9117 + attribute \src "libresoc.v:167818.3-167835.6" + process $proc$libresoc.v:167818$9117 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9118 $2\r_busy$next[0:0]$9120 - attribute \src "libresoc.v:168023.5-168023.29" + attribute \src "libresoc.v:167819.5-167819.29" switch \initial - attribute \src "libresoc.v:168023.9-168023.17" + attribute \src "libresoc.v:167819.9-167819.17" case 1'1 case end @@ -311241,14 +311075,14 @@ module \pipe1$110 sync always update \r_busy$next $0\r_busy$next[0:0]$9118 end - attribute \src "libresoc.v:168040.3-168052.6" - process $proc$libresoc.v:168040$9121 + attribute \src "libresoc.v:167836.3-167848.6" + process $proc$libresoc.v:167836$9121 assign { } { } assign { } { } assign $0\muxid$next[1:0]$9122 $1\muxid$next[1:0]$9123 - attribute \src "libresoc.v:168041.5-168041.29" + attribute \src "libresoc.v:167837.5-167837.29" switch \initial - attribute \src "libresoc.v:168041.9-168041.17" + attribute \src "libresoc.v:167837.9-167837.17" case 1'1 case end @@ -311268,8 +311102,8 @@ module \pipe1$110 sync always update \muxid$next $0\muxid$next[1:0]$9122 end - attribute \src "libresoc.v:168053.3-168093.6" - process $proc$libresoc.v:168053$9124 + attribute \src "libresoc.v:167849.3-167889.6" + process $proc$libresoc.v:167849$9124 assign { } { } assign { } { } assign { } { } @@ -311327,9 +311161,9 @@ module \pipe1$110 assign $0\sr_op__oe__ok$next[0:0]$9136 $2\sr_op__oe__ok$next[0:0]$9162 assign $0\sr_op__rc__ok$next[0:0]$9139 $2\sr_op__rc__ok$next[0:0]$9163 assign $0\sr_op__rc__rc$next[0:0]$9140 $2\sr_op__rc__rc$next[0:0]$9164 - attribute \src "libresoc.v:168054.5-168054.29" + attribute \src "libresoc.v:167850.5-167850.29" switch \initial - attribute \src "libresoc.v:168054.9-168054.17" + attribute \src "libresoc.v:167850.9-167850.17" case 1'1 case end @@ -311437,8 +311271,8 @@ module \pipe1$110 update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9140 update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9141 end - attribute \src "libresoc.v:168094.3-168112.6" - process $proc$libresoc.v:168094$9165 + attribute \src "libresoc.v:167890.3-167908.6" + process $proc$libresoc.v:167890$9165 assign { } { } assign { } { } assign { } { } @@ -311446,9 +311280,9 @@ module \pipe1$110 assign $0\o$next[63:0]$9166 $1\o$next[63:0]$9168 assign { } { } assign $0\o_ok$next[0:0]$9167 $2\o_ok$next[0:0]$9170 - attribute \src "libresoc.v:168095.5-168095.29" + attribute \src "libresoc.v:167891.5-167891.29" switch \initial - attribute \src "libresoc.v:168095.9-168095.17" + attribute \src "libresoc.v:167891.9-167891.17" case 1'1 case end @@ -311481,8 +311315,8 @@ module \pipe1$110 update \o$next $0\o$next[63:0]$9166 update \o_ok$next $0\o_ok$next[0:0]$9167 end - attribute \src "libresoc.v:168113.3-168131.6" - process $proc$libresoc.v:168113$9171 + attribute \src "libresoc.v:167909.3-167927.6" + process $proc$libresoc.v:167909$9171 assign { } { } assign { } { } assign { } { } @@ -311490,9 +311324,9 @@ module \pipe1$110 assign $0\cr_a$next[3:0]$9172 $1\cr_a$next[3:0]$9174 assign { } { } assign $0\cr_a_ok$next[0:0]$9173 $2\cr_a_ok$next[0:0]$9176 - attribute \src "libresoc.v:168114.5-168114.29" + attribute \src "libresoc.v:167910.5-167910.29" switch \initial - attribute \src "libresoc.v:168114.9-168114.17" + attribute \src "libresoc.v:167910.9-167910.17" case 1'1 case end @@ -311525,8 +311359,8 @@ module \pipe1$110 update \cr_a$next $0\cr_a$next[3:0]$9172 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9173 end - attribute \src "libresoc.v:168132.3-168150.6" - process $proc$libresoc.v:168132$9177 + attribute \src "libresoc.v:167928.3-167946.6" + process $proc$libresoc.v:167928$9177 assign { } { } assign { } { } assign { } { } @@ -311534,9 +311368,9 @@ module \pipe1$110 assign $0\xer_so$next[0:0]$9178 $1\xer_so$next[0:0]$9180 assign { } { } assign $0\xer_so_ok$next[0:0]$9179 $2\xer_so_ok$next[0:0]$9182 - attribute \src "libresoc.v:168133.5-168133.29" + attribute \src "libresoc.v:167929.5-167929.29" switch \initial - attribute \src "libresoc.v:168133.9-168133.17" + attribute \src "libresoc.v:167929.9-167929.17" case 1'1 case end @@ -311569,7 +311403,7 @@ module \pipe1$110 update \xer_so$next $0\xer_so$next[0:0]$9178 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9179 end - connect \$65 $and$libresoc.v:167846$9083_Y + connect \$65 $and$libresoc.v:167642$9083_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -311600,142 +311434,142 @@ module \pipe1$110 connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:168184.1-169032.10" +attribute \src "libresoc.v:167980.1-168828.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" attribute \generator "nMigen" module \pipe1$32 - attribute \src "libresoc.v:168989.3-169001.6" + attribute \src "libresoc.v:168785.3-168797.6" wire width 64 $0\fast1$next[63:0]$9260 - attribute \src "libresoc.v:168845.3-168846.27" + attribute \src "libresoc.v:168641.3-168642.27" wire width 64 $0\fast1[63:0] - attribute \src "libresoc.v:169002.3-169014.6" + attribute \src "libresoc.v:168798.3-168810.6" wire width 64 $0\fast2$next[63:0]$9263 - attribute \src "libresoc.v:168843.3-168844.27" + attribute \src "libresoc.v:168639.3-168640.27" wire width 64 $0\fast2[63:0] - attribute \src "libresoc.v:168185.7-168185.20" + attribute \src "libresoc.v:167981.7-167981.20" wire $0\initial[0:0] - attribute \src "libresoc.v:168929.3-168941.6" + attribute \src "libresoc.v:168725.3-168737.6" wire width 2 $0\muxid$next[1:0]$9232 - attribute \src "libresoc.v:168869.3-168870.27" + attribute \src "libresoc.v:168665.3-168666.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:168911.3-168928.6" + attribute \src "libresoc.v:168707.3-168724.6" wire $0\r_busy$next[0:0]$9228 - attribute \src "libresoc.v:168871.3-168872.29" + attribute \src "libresoc.v:168667.3-168668.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:168963.3-168975.6" + attribute \src "libresoc.v:168759.3-168771.6" wire width 64 $0\ra$next[63:0]$9254 - attribute \src "libresoc.v:168849.3-168850.21" + attribute \src "libresoc.v:168645.3-168646.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:168976.3-168988.6" + attribute \src "libresoc.v:168772.3-168784.6" wire width 64 $0\rb$next[63:0]$9257 - attribute \src "libresoc.v:168847.3-168848.21" + attribute \src "libresoc.v:168643.3-168644.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 64 $0\trap_op__cia$next[63:0]$9235 - attribute \src "libresoc.v:168859.3-168860.41" + attribute \src "libresoc.v:168655.3-168656.41" wire width 64 $0\trap_op__cia[63:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 14 $0\trap_op__fn_unit$next[13:0]$9236 - attribute \src "libresoc.v:168853.3-168854.49" + attribute \src "libresoc.v:168649.3-168650.49" wire width 14 $0\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 32 $0\trap_op__insn$next[31:0]$9237 - attribute \src "libresoc.v:168855.3-168856.43" + attribute \src "libresoc.v:168651.3-168652.43" wire width 32 $0\trap_op__insn[31:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 7 $0\trap_op__insn_type$next[6:0]$9238 - attribute \src "libresoc.v:168851.3-168852.53" + attribute \src "libresoc.v:168647.3-168648.53" wire width 7 $0\trap_op__insn_type[6:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire $0\trap_op__is_32bit$next[0:0]$9239 - attribute \src "libresoc.v:168861.3-168862.51" + attribute \src "libresoc.v:168657.3-168658.51" wire $0\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 8 $0\trap_op__ldst_exc$next[7:0]$9240 - attribute \src "libresoc.v:168867.3-168868.51" + attribute \src "libresoc.v:168663.3-168664.51" wire width 8 $0\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 64 $0\trap_op__msr$next[63:0]$9241 - attribute \src "libresoc.v:168857.3-168858.41" + attribute \src "libresoc.v:168653.3-168654.41" wire width 64 $0\trap_op__msr[63:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 13 $0\trap_op__trapaddr$next[12:0]$9242 - attribute \src "libresoc.v:168865.3-168866.51" + attribute \src "libresoc.v:168661.3-168662.51" wire width 13 $0\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 8 $0\trap_op__traptype$next[7:0]$9243 - attribute \src "libresoc.v:168863.3-168864.51" + attribute \src "libresoc.v:168659.3-168660.51" wire width 8 $0\trap_op__traptype[7:0] - attribute \src "libresoc.v:168989.3-169001.6" + attribute \src "libresoc.v:168785.3-168797.6" wire width 64 $1\fast1$next[63:0]$9261 - attribute \src "libresoc.v:168430.14-168430.42" + attribute \src "libresoc.v:168226.14-168226.42" wire width 64 $1\fast1[63:0] - attribute \src "libresoc.v:169002.3-169014.6" + attribute \src "libresoc.v:168798.3-168810.6" wire width 64 $1\fast2$next[63:0]$9264 - attribute \src "libresoc.v:168439.14-168439.42" + attribute \src "libresoc.v:168235.14-168235.42" wire width 64 $1\fast2[63:0] - attribute \src "libresoc.v:168929.3-168941.6" + attribute \src "libresoc.v:168725.3-168737.6" wire width 2 $1\muxid$next[1:0]$9233 - attribute \src "libresoc.v:168448.13-168448.25" + attribute \src "libresoc.v:168244.13-168244.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:168911.3-168928.6" + attribute \src "libresoc.v:168707.3-168724.6" wire $1\r_busy$next[0:0]$9229 - attribute \src "libresoc.v:168470.7-168470.20" + attribute \src "libresoc.v:168266.7-168266.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:168963.3-168975.6" + attribute \src "libresoc.v:168759.3-168771.6" wire width 64 $1\ra$next[63:0]$9255 - attribute \src "libresoc.v:168475.14-168475.39" + attribute \src "libresoc.v:168271.14-168271.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:168976.3-168988.6" + attribute \src "libresoc.v:168772.3-168784.6" wire width 64 $1\rb$next[63:0]$9258 - attribute \src "libresoc.v:168484.14-168484.39" + attribute \src "libresoc.v:168280.14-168280.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 64 $1\trap_op__cia$next[63:0]$9244 - attribute \src "libresoc.v:168493.14-168493.49" + attribute \src "libresoc.v:168289.14-168289.49" wire width 64 $1\trap_op__cia[63:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 14 $1\trap_op__fn_unit$next[13:0]$9245 - attribute \src "libresoc.v:168517.14-168517.41" + attribute \src "libresoc.v:168313.14-168313.41" wire width 14 $1\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 32 $1\trap_op__insn$next[31:0]$9246 - attribute \src "libresoc.v:168556.14-168556.35" + attribute \src "libresoc.v:168352.14-168352.35" wire width 32 $1\trap_op__insn[31:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 7 $1\trap_op__insn_type$next[6:0]$9247 - attribute \src "libresoc.v:168640.13-168640.39" + attribute \src "libresoc.v:168436.13-168436.39" wire width 7 $1\trap_op__insn_type[6:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire $1\trap_op__is_32bit$next[0:0]$9248 - attribute \src "libresoc.v:168799.7-168799.31" + attribute \src "libresoc.v:168595.7-168595.31" wire $1\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 8 $1\trap_op__ldst_exc$next[7:0]$9249 - attribute \src "libresoc.v:168808.13-168808.38" + attribute \src "libresoc.v:168604.13-168604.38" wire width 8 $1\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 64 $1\trap_op__msr$next[63:0]$9250 - attribute \src "libresoc.v:168817.14-168817.49" + attribute \src "libresoc.v:168613.14-168613.49" wire width 64 $1\trap_op__msr[63:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 13 $1\trap_op__trapaddr$next[12:0]$9251 - attribute \src "libresoc.v:168826.14-168826.42" + attribute \src "libresoc.v:168622.14-168622.42" wire width 13 $1\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:168942.3-168962.6" + attribute \src "libresoc.v:168738.3-168758.6" wire width 8 $1\trap_op__traptype$next[7:0]$9252 - attribute \src "libresoc.v:168835.13-168835.38" + attribute \src "libresoc.v:168631.13-168631.38" wire width 8 $1\trap_op__traptype[7:0] - attribute \src "libresoc.v:168911.3-168928.6" + attribute \src "libresoc.v:168707.3-168724.6" wire $2\r_busy$next[0:0]$9230 - attribute \src "libresoc.v:168842.18-168842.118" - wire $and$libresoc.v:168842$9211_Y + attribute \src "libresoc.v:168638.18-168638.118" + wire $and$libresoc.v:168638$9211_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_fast1 @@ -311989,7 +311823,7 @@ module \pipe1$32 wire width 64 \fast2$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \fast2$next - attribute \src "libresoc.v:168185.7-168185.15" + attribute \src "libresoc.v:167981.7-167981.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid @@ -312376,7 +312210,7 @@ module \pipe1$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:168842$9211 + cell $and $and$libresoc.v:168638$9211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312384,10 +312218,10 @@ module \pipe1$32 parameter \Y_WIDTH 1 connect \A \p_valid_i$29 connect \B \p_ready_o - connect \Y $and$libresoc.v:168842$9211_Y + connect \Y $and$libresoc.v:168638$9211_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:168873.9-168902.4" + attribute \src "libresoc.v:168669.9-168698.4" cell \dummy \dummy connect \fast1 \dummy_fast1 connect \fast1$13 \dummy_fast1$27 @@ -312419,259 +312253,259 @@ module \pipe1$32 connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 end attribute \module_not_derived 1 - attribute \src "libresoc.v:168903.10-168906.4" + attribute \src "libresoc.v:168699.10-168702.4" cell \n$34 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:168907.10-168910.4" + attribute \src "libresoc.v:168703.10-168706.4" cell \p$33 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:168185.7-168185.20" - process $proc$libresoc.v:168185$9265 + attribute \src "libresoc.v:167981.7-167981.20" + process $proc$libresoc.v:167981$9265 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168430.14-168430.42" - process $proc$libresoc.v:168430$9266 + attribute \src "libresoc.v:168226.14-168226.42" + process $proc$libresoc.v:168226$9266 assign { } { } assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1 $1\fast1[63:0] end - attribute \src "libresoc.v:168439.14-168439.42" - process $proc$libresoc.v:168439$9267 + attribute \src "libresoc.v:168235.14-168235.42" + process $proc$libresoc.v:168235$9267 assign { } { } assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2 $1\fast2[63:0] end - attribute \src "libresoc.v:168448.13-168448.25" - process $proc$libresoc.v:168448$9268 + attribute \src "libresoc.v:168244.13-168244.25" + process $proc$libresoc.v:168244$9268 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:168470.7-168470.20" - process $proc$libresoc.v:168470$9269 + attribute \src "libresoc.v:168266.7-168266.20" + process $proc$libresoc.v:168266$9269 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:168475.14-168475.39" - process $proc$libresoc.v:168475$9270 + attribute \src "libresoc.v:168271.14-168271.39" + process $proc$libresoc.v:168271$9270 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:168484.14-168484.39" - process $proc$libresoc.v:168484$9271 + attribute \src "libresoc.v:168280.14-168280.39" + process $proc$libresoc.v:168280$9271 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:168493.14-168493.49" - process $proc$libresoc.v:168493$9272 + attribute \src "libresoc.v:168289.14-168289.49" + process $proc$libresoc.v:168289$9272 assign { } { } assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__cia $1\trap_op__cia[63:0] end - attribute \src "libresoc.v:168517.14-168517.41" - process $proc$libresoc.v:168517$9273 + attribute \src "libresoc.v:168313.14-168313.41" + process $proc$libresoc.v:168313$9273 assign { } { } assign $1\trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \trap_op__fn_unit $1\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:168556.14-168556.35" - process $proc$libresoc.v:168556$9274 + attribute \src "libresoc.v:168352.14-168352.35" + process $proc$libresoc.v:168352$9274 assign { } { } assign $1\trap_op__insn[31:0] 0 sync always sync init update \trap_op__insn $1\trap_op__insn[31:0] end - attribute \src "libresoc.v:168640.13-168640.39" - process $proc$libresoc.v:168640$9275 + attribute \src "libresoc.v:168436.13-168436.39" + process $proc$libresoc.v:168436$9275 assign { } { } assign $1\trap_op__insn_type[6:0] 7'0000000 sync always sync init update \trap_op__insn_type $1\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:168799.7-168799.31" - process $proc$libresoc.v:168799$9276 + attribute \src "libresoc.v:168595.7-168595.31" + process $proc$libresoc.v:168595$9276 assign { } { } assign $1\trap_op__is_32bit[0:0] 1'0 sync always sync init update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:168808.13-168808.38" - process $proc$libresoc.v:168808$9277 + attribute \src "libresoc.v:168604.13-168604.38" + process $proc$libresoc.v:168604$9277 assign { } { } assign $1\trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:168817.14-168817.49" - process $proc$libresoc.v:168817$9278 + attribute \src "libresoc.v:168613.14-168613.49" + process $proc$libresoc.v:168613$9278 assign { } { } assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__msr $1\trap_op__msr[63:0] end - attribute \src "libresoc.v:168826.14-168826.42" - process $proc$libresoc.v:168826$9279 + attribute \src "libresoc.v:168622.14-168622.42" + process $proc$libresoc.v:168622$9279 assign { } { } assign $1\trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:168835.13-168835.38" - process $proc$libresoc.v:168835$9280 + attribute \src "libresoc.v:168631.13-168631.38" + process $proc$libresoc.v:168631$9280 assign { } { } assign $1\trap_op__traptype[7:0] 8'00000000 sync always sync init update \trap_op__traptype $1\trap_op__traptype[7:0] end - attribute \src "libresoc.v:168843.3-168844.27" - process $proc$libresoc.v:168843$9212 + attribute \src "libresoc.v:168639.3-168640.27" + process $proc$libresoc.v:168639$9212 assign { } { } assign $0\fast2[63:0] \fast2$next sync posedge \coresync_clk update \fast2 $0\fast2[63:0] end - attribute \src "libresoc.v:168845.3-168846.27" - process $proc$libresoc.v:168845$9213 + attribute \src "libresoc.v:168641.3-168642.27" + process $proc$libresoc.v:168641$9213 assign { } { } assign $0\fast1[63:0] \fast1$next sync posedge \coresync_clk update \fast1 $0\fast1[63:0] end - attribute \src "libresoc.v:168847.3-168848.21" - process $proc$libresoc.v:168847$9214 + attribute \src "libresoc.v:168643.3-168644.21" + process $proc$libresoc.v:168643$9214 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:168849.3-168850.21" - process $proc$libresoc.v:168849$9215 + attribute \src "libresoc.v:168645.3-168646.21" + process $proc$libresoc.v:168645$9215 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:168851.3-168852.53" - process $proc$libresoc.v:168851$9216 + attribute \src "libresoc.v:168647.3-168648.53" + process $proc$libresoc.v:168647$9216 assign { } { } assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next sync posedge \coresync_clk update \trap_op__insn_type $0\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:168853.3-168854.49" - process $proc$libresoc.v:168853$9217 + attribute \src "libresoc.v:168649.3-168650.49" + process $proc$libresoc.v:168649$9217 assign { } { } assign $0\trap_op__fn_unit[13:0] \trap_op__fn_unit$next sync posedge \coresync_clk update \trap_op__fn_unit $0\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:168855.3-168856.43" - process $proc$libresoc.v:168855$9218 + attribute \src "libresoc.v:168651.3-168652.43" + process $proc$libresoc.v:168651$9218 assign { } { } assign $0\trap_op__insn[31:0] \trap_op__insn$next sync posedge \coresync_clk update \trap_op__insn $0\trap_op__insn[31:0] end - attribute \src "libresoc.v:168857.3-168858.41" - process $proc$libresoc.v:168857$9219 + attribute \src "libresoc.v:168653.3-168654.41" + process $proc$libresoc.v:168653$9219 assign { } { } assign $0\trap_op__msr[63:0] \trap_op__msr$next sync posedge \coresync_clk update \trap_op__msr $0\trap_op__msr[63:0] end - attribute \src "libresoc.v:168859.3-168860.41" - process $proc$libresoc.v:168859$9220 + attribute \src "libresoc.v:168655.3-168656.41" + process $proc$libresoc.v:168655$9220 assign { } { } assign $0\trap_op__cia[63:0] \trap_op__cia$next sync posedge \coresync_clk update \trap_op__cia $0\trap_op__cia[63:0] end - attribute \src "libresoc.v:168861.3-168862.51" - process $proc$libresoc.v:168861$9221 + attribute \src "libresoc.v:168657.3-168658.51" + process $proc$libresoc.v:168657$9221 assign { } { } assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next sync posedge \coresync_clk update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:168863.3-168864.51" - process $proc$libresoc.v:168863$9222 + attribute \src "libresoc.v:168659.3-168660.51" + process $proc$libresoc.v:168659$9222 assign { } { } assign $0\trap_op__traptype[7:0] \trap_op__traptype$next sync posedge \coresync_clk update \trap_op__traptype $0\trap_op__traptype[7:0] end - attribute \src "libresoc.v:168865.3-168866.51" - process $proc$libresoc.v:168865$9223 + attribute \src "libresoc.v:168661.3-168662.51" + process $proc$libresoc.v:168661$9223 assign { } { } assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next sync posedge \coresync_clk update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:168867.3-168868.51" - process $proc$libresoc.v:168867$9224 + attribute \src "libresoc.v:168663.3-168664.51" + process $proc$libresoc.v:168663$9224 assign { } { } assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next sync posedge \coresync_clk update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:168869.3-168870.27" - process $proc$libresoc.v:168869$9225 + attribute \src "libresoc.v:168665.3-168666.27" + process $proc$libresoc.v:168665$9225 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:168871.3-168872.29" - process $proc$libresoc.v:168871$9226 + attribute \src "libresoc.v:168667.3-168668.29" + process $proc$libresoc.v:168667$9226 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:168911.3-168928.6" - process $proc$libresoc.v:168911$9227 + attribute \src "libresoc.v:168707.3-168724.6" + process $proc$libresoc.v:168707$9227 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9228 $2\r_busy$next[0:0]$9230 - attribute \src "libresoc.v:168912.5-168912.29" + attribute \src "libresoc.v:168708.5-168708.29" switch \initial - attribute \src "libresoc.v:168912.9-168912.17" + attribute \src "libresoc.v:168708.9-168708.17" case 1'1 case end @@ -312700,14 +312534,14 @@ module \pipe1$32 sync always update \r_busy$next $0\r_busy$next[0:0]$9228 end - attribute \src "libresoc.v:168929.3-168941.6" - process $proc$libresoc.v:168929$9231 + attribute \src "libresoc.v:168725.3-168737.6" + process $proc$libresoc.v:168725$9231 assign { } { } assign { } { } assign $0\muxid$next[1:0]$9232 $1\muxid$next[1:0]$9233 - attribute \src "libresoc.v:168930.5-168930.29" + attribute \src "libresoc.v:168726.5-168726.29" switch \initial - attribute \src "libresoc.v:168930.9-168930.17" + attribute \src "libresoc.v:168726.9-168726.17" case 1'1 case end @@ -312727,8 +312561,8 @@ module \pipe1$32 sync always update \muxid$next $0\muxid$next[1:0]$9232 end - attribute \src "libresoc.v:168942.3-168962.6" - process $proc$libresoc.v:168942$9234 + attribute \src "libresoc.v:168738.3-168758.6" + process $proc$libresoc.v:168738$9234 assign { } { } assign { } { } assign { } { } @@ -312756,9 +312590,9 @@ module \pipe1$32 assign $0\trap_op__msr$next[63:0]$9241 $1\trap_op__msr$next[63:0]$9250 assign $0\trap_op__trapaddr$next[12:0]$9242 $1\trap_op__trapaddr$next[12:0]$9251 assign $0\trap_op__traptype$next[7:0]$9243 $1\trap_op__traptype$next[7:0]$9252 - attribute \src "libresoc.v:168943.5-168943.29" + attribute \src "libresoc.v:168739.5-168739.29" switch \initial - attribute \src "libresoc.v:168943.9-168943.17" + attribute \src "libresoc.v:168739.9-168739.17" case 1'1 case end @@ -312810,14 +312644,14 @@ module \pipe1$32 update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9242 update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9243 end - attribute \src "libresoc.v:168963.3-168975.6" - process $proc$libresoc.v:168963$9253 + attribute \src "libresoc.v:168759.3-168771.6" + process $proc$libresoc.v:168759$9253 assign { } { } assign { } { } assign $0\ra$next[63:0]$9254 $1\ra$next[63:0]$9255 - attribute \src "libresoc.v:168964.5-168964.29" + attribute \src "libresoc.v:168760.5-168760.29" switch \initial - attribute \src "libresoc.v:168964.9-168964.17" + attribute \src "libresoc.v:168760.9-168760.17" case 1'1 case end @@ -312837,14 +312671,14 @@ module \pipe1$32 sync always update \ra$next $0\ra$next[63:0]$9254 end - attribute \src "libresoc.v:168976.3-168988.6" - process $proc$libresoc.v:168976$9256 + attribute \src "libresoc.v:168772.3-168784.6" + process $proc$libresoc.v:168772$9256 assign { } { } assign { } { } assign $0\rb$next[63:0]$9257 $1\rb$next[63:0]$9258 - attribute \src "libresoc.v:168977.5-168977.29" + attribute \src "libresoc.v:168773.5-168773.29" switch \initial - attribute \src "libresoc.v:168977.9-168977.17" + attribute \src "libresoc.v:168773.9-168773.17" case 1'1 case end @@ -312864,14 +312698,14 @@ module \pipe1$32 sync always update \rb$next $0\rb$next[63:0]$9257 end - attribute \src "libresoc.v:168989.3-169001.6" - process $proc$libresoc.v:168989$9259 + attribute \src "libresoc.v:168785.3-168797.6" + process $proc$libresoc.v:168785$9259 assign { } { } assign { } { } assign $0\fast1$next[63:0]$9260 $1\fast1$next[63:0]$9261 - attribute \src "libresoc.v:168990.5-168990.29" + attribute \src "libresoc.v:168786.5-168786.29" switch \initial - attribute \src "libresoc.v:168990.9-168990.17" + attribute \src "libresoc.v:168786.9-168786.17" case 1'1 case end @@ -312891,14 +312725,14 @@ module \pipe1$32 sync always update \fast1$next $0\fast1$next[63:0]$9260 end - attribute \src "libresoc.v:169002.3-169014.6" - process $proc$libresoc.v:169002$9262 + attribute \src "libresoc.v:168798.3-168810.6" + process $proc$libresoc.v:168798$9262 assign { } { } assign { } { } assign $0\fast2$next[63:0]$9263 $1\fast2$next[63:0]$9264 - attribute \src "libresoc.v:169003.5-169003.29" + attribute \src "libresoc.v:168799.5-168799.29" switch \initial - attribute \src "libresoc.v:169003.9-169003.17" + attribute \src "libresoc.v:168799.9-168799.17" case 1'1 case end @@ -312918,7 +312752,7 @@ module \pipe1$32 sync always update \fast2$next $0\fast2$next[63:0]$9263 end - connect \$30 $and$libresoc.v:168842$9211_Y + connect \$30 $and$libresoc.v:168638$9211_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \fast2$45 \dummy_fast2$28 @@ -312937,279 +312771,279 @@ module \pipe1$32 connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } connect \dummy_muxid \muxid$1 end -attribute \src "libresoc.v:169036.1-170221.10" +attribute \src "libresoc.v:168832.1-170017.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" attribute \generator "nMigen" module \pipe2 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 4 $0\alu_op__data_len$18$next[3:0]$9349 - attribute \src "libresoc.v:169962.3-169963.57" + attribute \src "libresoc.v:169758.3-169759.57" wire width 4 $0\alu_op__data_len$18[3:0]$9335 - attribute \src "libresoc.v:169044.13-169044.41" + attribute \src "libresoc.v:168840.13-168840.41" wire width 4 $0\alu_op__data_len$18[3:0]$9423 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9350 - attribute \src "libresoc.v:169932.3-169933.53" + attribute \src "libresoc.v:169728.3-169729.53" wire width 14 $0\alu_op__fn_unit$3[13:0]$9305 - attribute \src "libresoc.v:169083.14-169083.44" + attribute \src "libresoc.v:168879.14-168879.44" wire width 14 $0\alu_op__fn_unit$3[13:0]$9425 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9351 - attribute \src "libresoc.v:169934.3-169935.67" + attribute \src "libresoc.v:169730.3-169731.67" wire width 64 $0\alu_op__imm_data__data$4[63:0]$9307 - attribute \src "libresoc.v:169107.14-169107.63" + attribute \src "libresoc.v:168903.14-168903.63" wire width 64 $0\alu_op__imm_data__data$4[63:0]$9427 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__imm_data__ok$5$next[0:0]$9352 - attribute \src "libresoc.v:169936.3-169937.63" + attribute \src "libresoc.v:169732.3-169733.63" wire $0\alu_op__imm_data__ok$5[0:0]$9309 - attribute \src "libresoc.v:169116.7-169116.38" + attribute \src "libresoc.v:168912.7-168912.38" wire $0\alu_op__imm_data__ok$5[0:0]$9429 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 2 $0\alu_op__input_carry$14$next[1:0]$9353 - attribute \src "libresoc.v:169954.3-169955.63" + attribute \src "libresoc.v:169750.3-169751.63" wire width 2 $0\alu_op__input_carry$14[1:0]$9327 - attribute \src "libresoc.v:169133.13-169133.44" + attribute \src "libresoc.v:168929.13-168929.44" wire width 2 $0\alu_op__input_carry$14[1:0]$9431 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 32 $0\alu_op__insn$19$next[31:0]$9354 - attribute \src "libresoc.v:169964.3-169965.49" + attribute \src "libresoc.v:169760.3-169761.49" wire width 32 $0\alu_op__insn$19[31:0]$9337 - attribute \src "libresoc.v:169146.14-169146.39" + attribute \src "libresoc.v:168942.14-168942.39" wire width 32 $0\alu_op__insn$19[31:0]$9433 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 7 $0\alu_op__insn_type$2$next[6:0]$9355 - attribute \src "libresoc.v:169930.3-169931.57" + attribute \src "libresoc.v:169726.3-169727.57" wire width 7 $0\alu_op__insn_type$2[6:0]$9303 - attribute \src "libresoc.v:169305.13-169305.42" + attribute \src "libresoc.v:169101.13-169101.42" wire width 7 $0\alu_op__insn_type$2[6:0]$9435 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__invert_in$10$next[0:0]$9356 - attribute \src "libresoc.v:169946.3-169947.59" + attribute \src "libresoc.v:169742.3-169743.59" wire $0\alu_op__invert_in$10[0:0]$9319 - attribute \src "libresoc.v:169389.7-169389.36" + attribute \src "libresoc.v:169185.7-169185.36" wire $0\alu_op__invert_in$10[0:0]$9437 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__invert_out$12$next[0:0]$9357 - attribute \src "libresoc.v:169950.3-169951.61" + attribute \src "libresoc.v:169746.3-169747.61" wire $0\alu_op__invert_out$12[0:0]$9323 - attribute \src "libresoc.v:169398.7-169398.37" + attribute \src "libresoc.v:169194.7-169194.37" wire $0\alu_op__invert_out$12[0:0]$9439 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__is_32bit$16$next[0:0]$9358 - attribute \src "libresoc.v:169958.3-169959.57" + attribute \src "libresoc.v:169754.3-169755.57" wire $0\alu_op__is_32bit$16[0:0]$9331 - attribute \src "libresoc.v:169407.7-169407.35" + attribute \src "libresoc.v:169203.7-169203.35" wire $0\alu_op__is_32bit$16[0:0]$9441 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__is_signed$17$next[0:0]$9359 - attribute \src "libresoc.v:169960.3-169961.59" + attribute \src "libresoc.v:169756.3-169757.59" wire $0\alu_op__is_signed$17[0:0]$9333 - attribute \src "libresoc.v:169416.7-169416.36" + attribute \src "libresoc.v:169212.7-169212.36" wire $0\alu_op__is_signed$17[0:0]$9443 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__oe__oe$8$next[0:0]$9360 - attribute \src "libresoc.v:169942.3-169943.51" + attribute \src "libresoc.v:169738.3-169739.51" wire $0\alu_op__oe__oe$8[0:0]$9315 - attribute \src "libresoc.v:169427.7-169427.32" + attribute \src "libresoc.v:169223.7-169223.32" wire $0\alu_op__oe__oe$8[0:0]$9445 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__oe__ok$9$next[0:0]$9361 - attribute \src "libresoc.v:169944.3-169945.51" + attribute \src "libresoc.v:169740.3-169741.51" wire $0\alu_op__oe__ok$9[0:0]$9317 - attribute \src "libresoc.v:169436.7-169436.32" + attribute \src "libresoc.v:169232.7-169232.32" wire $0\alu_op__oe__ok$9[0:0]$9447 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__output_carry$15$next[0:0]$9362 - attribute \src "libresoc.v:169956.3-169957.65" + attribute \src "libresoc.v:169752.3-169753.65" wire $0\alu_op__output_carry$15[0:0]$9329 - attribute \src "libresoc.v:169443.7-169443.39" + attribute \src "libresoc.v:169239.7-169239.39" wire $0\alu_op__output_carry$15[0:0]$9449 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__rc__ok$7$next[0:0]$9363 - attribute \src "libresoc.v:169940.3-169941.51" + attribute \src "libresoc.v:169736.3-169737.51" wire $0\alu_op__rc__ok$7[0:0]$9313 - attribute \src "libresoc.v:169454.7-169454.32" + attribute \src "libresoc.v:169250.7-169250.32" wire $0\alu_op__rc__ok$7[0:0]$9451 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__rc__rc$6$next[0:0]$9364 - attribute \src "libresoc.v:169938.3-169939.51" + attribute \src "libresoc.v:169734.3-169735.51" wire $0\alu_op__rc__rc$6[0:0]$9311 - attribute \src "libresoc.v:169461.7-169461.32" + attribute \src "libresoc.v:169257.7-169257.32" wire $0\alu_op__rc__rc$6[0:0]$9453 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__write_cr0$13$next[0:0]$9365 - attribute \src "libresoc.v:169952.3-169953.59" + attribute \src "libresoc.v:169748.3-169749.59" wire $0\alu_op__write_cr0$13[0:0]$9325 - attribute \src "libresoc.v:169470.7-169470.36" + attribute \src "libresoc.v:169266.7-169266.36" wire $0\alu_op__write_cr0$13[0:0]$9455 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__zero_a$11$next[0:0]$9366 - attribute \src "libresoc.v:169948.3-169949.53" + attribute \src "libresoc.v:169744.3-169745.53" wire $0\alu_op__zero_a$11[0:0]$9321 - attribute \src "libresoc.v:169479.7-169479.33" + attribute \src "libresoc.v:169275.7-169275.33" wire $0\alu_op__zero_a$11[0:0]$9457 - attribute \src "libresoc.v:170126.3-170144.6" + attribute \src "libresoc.v:169922.3-169940.6" wire width 4 $0\cr_a$22$next[3:0]$9398 - attribute \src "libresoc.v:169922.3-169923.33" + attribute \src "libresoc.v:169718.3-169719.33" wire width 4 $0\cr_a$22[3:0]$9295 - attribute \src "libresoc.v:169492.13-169492.29" + attribute \src "libresoc.v:169288.13-169288.29" wire width 4 $0\cr_a$22[3:0]$9459 - attribute \src "libresoc.v:170126.3-170144.6" + attribute \src "libresoc.v:169922.3-169940.6" wire $0\cr_a_ok$23$next[0:0]$9399 - attribute \src "libresoc.v:169924.3-169925.39" + attribute \src "libresoc.v:169720.3-169721.39" wire $0\cr_a_ok$23[0:0]$9297 - attribute \src "libresoc.v:169501.7-169501.26" + attribute \src "libresoc.v:169297.7-169297.26" wire $0\cr_a_ok$23[0:0]$9461 - attribute \src "libresoc.v:169037.7-169037.20" + attribute \src "libresoc.v:168833.7-168833.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170052.3-170064.6" + attribute \src "libresoc.v:169848.3-169860.6" wire width 2 $0\muxid$1$next[1:0]$9346 - attribute \src "libresoc.v:169966.3-169967.33" + attribute \src "libresoc.v:169762.3-169763.33" wire width 2 $0\muxid$1[1:0]$9339 - attribute \src "libresoc.v:169512.13-169512.29" + attribute \src "libresoc.v:169308.13-169308.29" wire width 2 $0\muxid$1[1:0]$9463 - attribute \src "libresoc.v:170107.3-170125.6" + attribute \src "libresoc.v:169903.3-169921.6" wire width 64 $0\o$20$next[63:0]$9392 - attribute \src "libresoc.v:169926.3-169927.27" + attribute \src "libresoc.v:169722.3-169723.27" wire width 64 $0\o$20[63:0]$9299 - attribute \src "libresoc.v:169527.14-169527.43" + attribute \src "libresoc.v:169323.14-169323.43" wire width 64 $0\o$20[63:0]$9465 - attribute \src "libresoc.v:170107.3-170125.6" + attribute \src "libresoc.v:169903.3-169921.6" wire $0\o_ok$21$next[0:0]$9393 - attribute \src "libresoc.v:169928.3-169929.33" + attribute \src "libresoc.v:169724.3-169725.33" wire $0\o_ok$21[0:0]$9301 - attribute \src "libresoc.v:169536.7-169536.23" + attribute \src "libresoc.v:169332.7-169332.23" wire $0\o_ok$21[0:0]$9467 - attribute \src "libresoc.v:170034.3-170051.6" + attribute \src "libresoc.v:169830.3-169847.6" wire $0\r_busy$next[0:0]$9342 - attribute \src "libresoc.v:169968.3-169969.29" + attribute \src "libresoc.v:169764.3-169765.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:170145.3-170163.6" + attribute \src "libresoc.v:169941.3-169959.6" wire width 2 $0\xer_ca$24$next[1:0]$9404 - attribute \src "libresoc.v:169918.3-169919.37" + attribute \src "libresoc.v:169714.3-169715.37" wire width 2 $0\xer_ca$24[1:0]$9291 - attribute \src "libresoc.v:169853.13-169853.31" + attribute \src "libresoc.v:169649.13-169649.31" wire width 2 $0\xer_ca$24[1:0]$9470 - attribute \src "libresoc.v:170145.3-170163.6" + attribute \src "libresoc.v:169941.3-169959.6" wire $0\xer_ca_ok$25$next[0:0]$9405 - attribute \src "libresoc.v:169920.3-169921.43" + attribute \src "libresoc.v:169716.3-169717.43" wire $0\xer_ca_ok$25[0:0]$9293 - attribute \src "libresoc.v:169862.7-169862.28" + attribute \src "libresoc.v:169658.7-169658.28" wire $0\xer_ca_ok$25[0:0]$9472 - attribute \src "libresoc.v:170164.3-170182.6" + attribute \src "libresoc.v:169960.3-169978.6" wire width 2 $0\xer_ov$26$next[1:0]$9410 - attribute \src "libresoc.v:169914.3-169915.37" + attribute \src "libresoc.v:169710.3-169711.37" wire width 2 $0\xer_ov$26[1:0]$9287 - attribute \src "libresoc.v:169873.13-169873.31" + attribute \src "libresoc.v:169669.13-169669.31" wire width 2 $0\xer_ov$26[1:0]$9474 - attribute \src "libresoc.v:170164.3-170182.6" + attribute \src "libresoc.v:169960.3-169978.6" wire $0\xer_ov_ok$27$next[0:0]$9411 - attribute \src "libresoc.v:169916.3-169917.43" + attribute \src "libresoc.v:169712.3-169713.43" wire $0\xer_ov_ok$27[0:0]$9289 - attribute \src "libresoc.v:169882.7-169882.28" + attribute \src "libresoc.v:169678.7-169678.28" wire $0\xer_ov_ok$27[0:0]$9476 - attribute \src "libresoc.v:170183.3-170201.6" + attribute \src "libresoc.v:169979.3-169997.6" wire $0\xer_so$28$next[0:0]$9416 - attribute \src "libresoc.v:169910.3-169911.37" + attribute \src "libresoc.v:169706.3-169707.37" wire $0\xer_so$28[0:0]$9283 - attribute \src "libresoc.v:169893.7-169893.25" + attribute \src "libresoc.v:169689.7-169689.25" wire $0\xer_so$28[0:0]$9478 - attribute \src "libresoc.v:170183.3-170201.6" + attribute \src "libresoc.v:169979.3-169997.6" wire $0\xer_so_ok$29$next[0:0]$9417 - attribute \src "libresoc.v:169912.3-169913.43" + attribute \src "libresoc.v:169708.3-169709.43" wire $0\xer_so_ok$29[0:0]$9285 - attribute \src "libresoc.v:169902.7-169902.28" + attribute \src "libresoc.v:169698.7-169698.28" wire $0\xer_so_ok$29[0:0]$9480 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 4 $1\alu_op__data_len$18$next[3:0]$9367 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9368 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9369 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__imm_data__ok$5$next[0:0]$9370 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 2 $1\alu_op__input_carry$14$next[1:0]$9371 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 32 $1\alu_op__insn$19$next[31:0]$9372 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 7 $1\alu_op__insn_type$2$next[6:0]$9373 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__invert_in$10$next[0:0]$9374 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__invert_out$12$next[0:0]$9375 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__is_32bit$16$next[0:0]$9376 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__is_signed$17$next[0:0]$9377 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__oe__oe$8$next[0:0]$9378 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__oe__ok$9$next[0:0]$9379 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__output_carry$15$next[0:0]$9380 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__rc__ok$7$next[0:0]$9381 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__rc__rc$6$next[0:0]$9382 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__write_cr0$13$next[0:0]$9383 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__zero_a$11$next[0:0]$9384 - attribute \src "libresoc.v:170126.3-170144.6" + attribute \src "libresoc.v:169922.3-169940.6" wire width 4 $1\cr_a$22$next[3:0]$9400 - attribute \src "libresoc.v:170126.3-170144.6" + attribute \src "libresoc.v:169922.3-169940.6" wire $1\cr_a_ok$23$next[0:0]$9401 - attribute \src "libresoc.v:170052.3-170064.6" + attribute \src "libresoc.v:169848.3-169860.6" wire width 2 $1\muxid$1$next[1:0]$9347 - attribute \src "libresoc.v:170107.3-170125.6" + attribute \src "libresoc.v:169903.3-169921.6" wire width 64 $1\o$20$next[63:0]$9394 - attribute \src "libresoc.v:170107.3-170125.6" + attribute \src "libresoc.v:169903.3-169921.6" wire $1\o_ok$21$next[0:0]$9395 - attribute \src "libresoc.v:170034.3-170051.6" + attribute \src "libresoc.v:169830.3-169847.6" wire $1\r_busy$next[0:0]$9343 - attribute \src "libresoc.v:169846.7-169846.20" + attribute \src "libresoc.v:169642.7-169642.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:170145.3-170163.6" + attribute \src "libresoc.v:169941.3-169959.6" wire width 2 $1\xer_ca$24$next[1:0]$9406 - attribute \src "libresoc.v:170145.3-170163.6" + attribute \src "libresoc.v:169941.3-169959.6" wire $1\xer_ca_ok$25$next[0:0]$9407 - attribute \src "libresoc.v:170164.3-170182.6" + attribute \src "libresoc.v:169960.3-169978.6" wire width 2 $1\xer_ov$26$next[1:0]$9412 - attribute \src "libresoc.v:170164.3-170182.6" + attribute \src "libresoc.v:169960.3-169978.6" wire $1\xer_ov_ok$27$next[0:0]$9413 - attribute \src "libresoc.v:170183.3-170201.6" + attribute \src "libresoc.v:169979.3-169997.6" wire $1\xer_so$28$next[0:0]$9418 - attribute \src "libresoc.v:170183.3-170201.6" + attribute \src "libresoc.v:169979.3-169997.6" wire $1\xer_so_ok$29$next[0:0]$9419 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9385 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $2\alu_op__imm_data__ok$5$next[0:0]$9386 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $2\alu_op__oe__oe$8$next[0:0]$9387 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $2\alu_op__oe__ok$9$next[0:0]$9388 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $2\alu_op__rc__ok$7$next[0:0]$9389 - attribute \src "libresoc.v:170065.3-170106.6" + attribute \src "libresoc.v:169861.3-169902.6" wire $2\alu_op__rc__rc$6$next[0:0]$9390 - attribute \src "libresoc.v:170126.3-170144.6" + attribute \src "libresoc.v:169922.3-169940.6" wire $2\cr_a_ok$23$next[0:0]$9402 - attribute \src "libresoc.v:170107.3-170125.6" + attribute \src "libresoc.v:169903.3-169921.6" wire $2\o_ok$21$next[0:0]$9396 - attribute \src "libresoc.v:170034.3-170051.6" + attribute \src "libresoc.v:169830.3-169847.6" wire $2\r_busy$next[0:0]$9344 - attribute \src "libresoc.v:170145.3-170163.6" + attribute \src "libresoc.v:169941.3-169959.6" wire $2\xer_ca_ok$25$next[0:0]$9408 - attribute \src "libresoc.v:170164.3-170182.6" + attribute \src "libresoc.v:169960.3-169978.6" wire $2\xer_ov_ok$27$next[0:0]$9414 - attribute \src "libresoc.v:170183.3-170201.6" + attribute \src "libresoc.v:169979.3-169997.6" wire $2\xer_so_ok$29$next[0:0]$9420 - attribute \src "libresoc.v:169909.18-169909.118" - wire $and$libresoc.v:169909$9281_Y + attribute \src "libresoc.v:169705.18-169705.118" + wire $and$libresoc.v:169705$9281_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -313638,9 +313472,9 @@ module \pipe2 wire \alu_op__zero_a$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 64 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 25 \cr_a @@ -313660,7 +313494,7 @@ module \pipe2 wire \cr_a_ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$84 - attribute \src "libresoc.v:169037.7-169037.15" + attribute \src "libresoc.v:168833.7-168833.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -314055,7 +313889,7 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:169909$9281 + cell $and $and$libresoc.v:169705$9281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314063,16 +313897,16 @@ module \pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$59 connect \B \p_ready_o - connect \Y $and$libresoc.v:169909$9281_Y + connect \Y $and$libresoc.v:169705$9281_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:169970.9-169973.4" + attribute \src "libresoc.v:169766.9-169769.4" cell \n$4 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:169974.12-170029.4" + attribute \src "libresoc.v:169770.12-169825.4" cell \output \output connect \alu_op__data_len \output_alu_op__data_len connect \alu_op__data_len$18 \output_alu_op__data_len$47 @@ -314130,478 +313964,478 @@ module \pipe2 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:170030.9-170033.4" + attribute \src "libresoc.v:169826.9-169829.4" cell \p$3 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:169037.7-169037.20" - process $proc$libresoc.v:169037$9421 + attribute \src "libresoc.v:168833.7-168833.20" + process $proc$libresoc.v:168833$9421 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169044.13-169044.41" - process $proc$libresoc.v:169044$9422 + attribute \src "libresoc.v:168840.13-168840.41" + process $proc$libresoc.v:168840$9422 assign { } { } assign $0\alu_op__data_len$18[3:0]$9423 4'0000 sync always sync init update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9423 end - attribute \src "libresoc.v:169083.14-169083.44" - process $proc$libresoc.v:169083$9424 + attribute \src "libresoc.v:168879.14-168879.44" + process $proc$libresoc.v:168879$9424 assign { } { } assign $0\alu_op__fn_unit$3[13:0]$9425 14'00000000000000 sync always sync init update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9425 end - attribute \src "libresoc.v:169107.14-169107.63" - process $proc$libresoc.v:169107$9426 + attribute \src "libresoc.v:168903.14-168903.63" + process $proc$libresoc.v:168903$9426 assign { } { } assign $0\alu_op__imm_data__data$4[63:0]$9427 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9427 end - attribute \src "libresoc.v:169116.7-169116.38" - process $proc$libresoc.v:169116$9428 + attribute \src "libresoc.v:168912.7-168912.38" + process $proc$libresoc.v:168912$9428 assign { } { } assign $0\alu_op__imm_data__ok$5[0:0]$9429 1'0 sync always sync init update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9429 end - attribute \src "libresoc.v:169133.13-169133.44" - process $proc$libresoc.v:169133$9430 + attribute \src "libresoc.v:168929.13-168929.44" + process $proc$libresoc.v:168929$9430 assign { } { } assign $0\alu_op__input_carry$14[1:0]$9431 2'00 sync always sync init update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9431 end - attribute \src "libresoc.v:169146.14-169146.39" - process $proc$libresoc.v:169146$9432 + attribute \src "libresoc.v:168942.14-168942.39" + process $proc$libresoc.v:168942$9432 assign { } { } assign $0\alu_op__insn$19[31:0]$9433 0 sync always sync init update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9433 end - attribute \src "libresoc.v:169305.13-169305.42" - process $proc$libresoc.v:169305$9434 + attribute \src "libresoc.v:169101.13-169101.42" + process $proc$libresoc.v:169101$9434 assign { } { } assign $0\alu_op__insn_type$2[6:0]$9435 7'0000000 sync always sync init update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9435 end - attribute \src "libresoc.v:169389.7-169389.36" - process $proc$libresoc.v:169389$9436 + attribute \src "libresoc.v:169185.7-169185.36" + process $proc$libresoc.v:169185$9436 assign { } { } assign $0\alu_op__invert_in$10[0:0]$9437 1'0 sync always sync init update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9437 end - attribute \src "libresoc.v:169398.7-169398.37" - process $proc$libresoc.v:169398$9438 + attribute \src "libresoc.v:169194.7-169194.37" + process $proc$libresoc.v:169194$9438 assign { } { } assign $0\alu_op__invert_out$12[0:0]$9439 1'0 sync always sync init update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9439 end - attribute \src "libresoc.v:169407.7-169407.35" - process $proc$libresoc.v:169407$9440 + attribute \src "libresoc.v:169203.7-169203.35" + process $proc$libresoc.v:169203$9440 assign { } { } assign $0\alu_op__is_32bit$16[0:0]$9441 1'0 sync always sync init update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9441 end - attribute \src "libresoc.v:169416.7-169416.36" - process $proc$libresoc.v:169416$9442 + attribute \src "libresoc.v:169212.7-169212.36" + process $proc$libresoc.v:169212$9442 assign { } { } assign $0\alu_op__is_signed$17[0:0]$9443 1'0 sync always sync init update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9443 end - attribute \src "libresoc.v:169427.7-169427.32" - process $proc$libresoc.v:169427$9444 + attribute \src "libresoc.v:169223.7-169223.32" + process $proc$libresoc.v:169223$9444 assign { } { } assign $0\alu_op__oe__oe$8[0:0]$9445 1'0 sync always sync init update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9445 end - attribute \src "libresoc.v:169436.7-169436.32" - process $proc$libresoc.v:169436$9446 + attribute \src "libresoc.v:169232.7-169232.32" + process $proc$libresoc.v:169232$9446 assign { } { } assign $0\alu_op__oe__ok$9[0:0]$9447 1'0 sync always sync init update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9447 end - attribute \src "libresoc.v:169443.7-169443.39" - process $proc$libresoc.v:169443$9448 + attribute \src "libresoc.v:169239.7-169239.39" + process $proc$libresoc.v:169239$9448 assign { } { } assign $0\alu_op__output_carry$15[0:0]$9449 1'0 sync always sync init update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9449 end - attribute \src "libresoc.v:169454.7-169454.32" - process $proc$libresoc.v:169454$9450 + attribute \src "libresoc.v:169250.7-169250.32" + process $proc$libresoc.v:169250$9450 assign { } { } assign $0\alu_op__rc__ok$7[0:0]$9451 1'0 sync always sync init update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9451 end - attribute \src "libresoc.v:169461.7-169461.32" - process $proc$libresoc.v:169461$9452 + attribute \src "libresoc.v:169257.7-169257.32" + process $proc$libresoc.v:169257$9452 assign { } { } assign $0\alu_op__rc__rc$6[0:0]$9453 1'0 sync always sync init update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9453 end - attribute \src "libresoc.v:169470.7-169470.36" - process $proc$libresoc.v:169470$9454 + attribute \src "libresoc.v:169266.7-169266.36" + process $proc$libresoc.v:169266$9454 assign { } { } assign $0\alu_op__write_cr0$13[0:0]$9455 1'0 sync always sync init update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9455 end - attribute \src "libresoc.v:169479.7-169479.33" - process $proc$libresoc.v:169479$9456 + attribute \src "libresoc.v:169275.7-169275.33" + process $proc$libresoc.v:169275$9456 assign { } { } assign $0\alu_op__zero_a$11[0:0]$9457 1'0 sync always sync init update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9457 end - attribute \src "libresoc.v:169492.13-169492.29" - process $proc$libresoc.v:169492$9458 + attribute \src "libresoc.v:169288.13-169288.29" + process $proc$libresoc.v:169288$9458 assign { } { } assign $0\cr_a$22[3:0]$9459 4'0000 sync always sync init update \cr_a$22 $0\cr_a$22[3:0]$9459 end - attribute \src "libresoc.v:169501.7-169501.26" - process $proc$libresoc.v:169501$9460 + attribute \src "libresoc.v:169297.7-169297.26" + process $proc$libresoc.v:169297$9460 assign { } { } assign $0\cr_a_ok$23[0:0]$9461 1'0 sync always sync init update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9461 end - attribute \src "libresoc.v:169512.13-169512.29" - process $proc$libresoc.v:169512$9462 + attribute \src "libresoc.v:169308.13-169308.29" + process $proc$libresoc.v:169308$9462 assign { } { } assign $0\muxid$1[1:0]$9463 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$9463 end - attribute \src "libresoc.v:169527.14-169527.43" - process $proc$libresoc.v:169527$9464 + attribute \src "libresoc.v:169323.14-169323.43" + process $proc$libresoc.v:169323$9464 assign { } { } assign $0\o$20[63:0]$9465 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$20 $0\o$20[63:0]$9465 end - attribute \src "libresoc.v:169536.7-169536.23" - process $proc$libresoc.v:169536$9466 + attribute \src "libresoc.v:169332.7-169332.23" + process $proc$libresoc.v:169332$9466 assign { } { } assign $0\o_ok$21[0:0]$9467 1'0 sync always sync init update \o_ok$21 $0\o_ok$21[0:0]$9467 end - attribute \src "libresoc.v:169846.7-169846.20" - process $proc$libresoc.v:169846$9468 + attribute \src "libresoc.v:169642.7-169642.20" + process $proc$libresoc.v:169642$9468 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:169853.13-169853.31" - process $proc$libresoc.v:169853$9469 + attribute \src "libresoc.v:169649.13-169649.31" + process $proc$libresoc.v:169649$9469 assign { } { } assign $0\xer_ca$24[1:0]$9470 2'00 sync always sync init update \xer_ca$24 $0\xer_ca$24[1:0]$9470 end - attribute \src "libresoc.v:169862.7-169862.28" - process $proc$libresoc.v:169862$9471 + attribute \src "libresoc.v:169658.7-169658.28" + process $proc$libresoc.v:169658$9471 assign { } { } assign $0\xer_ca_ok$25[0:0]$9472 1'0 sync always sync init update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9472 end - attribute \src "libresoc.v:169873.13-169873.31" - process $proc$libresoc.v:169873$9473 + attribute \src "libresoc.v:169669.13-169669.31" + process $proc$libresoc.v:169669$9473 assign { } { } assign $0\xer_ov$26[1:0]$9474 2'00 sync always sync init update \xer_ov$26 $0\xer_ov$26[1:0]$9474 end - attribute \src "libresoc.v:169882.7-169882.28" - process $proc$libresoc.v:169882$9475 + attribute \src "libresoc.v:169678.7-169678.28" + process $proc$libresoc.v:169678$9475 assign { } { } assign $0\xer_ov_ok$27[0:0]$9476 1'0 sync always sync init update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9476 end - attribute \src "libresoc.v:169893.7-169893.25" - process $proc$libresoc.v:169893$9477 + attribute \src "libresoc.v:169689.7-169689.25" + process $proc$libresoc.v:169689$9477 assign { } { } assign $0\xer_so$28[0:0]$9478 1'0 sync always sync init update \xer_so$28 $0\xer_so$28[0:0]$9478 end - attribute \src "libresoc.v:169902.7-169902.28" - process $proc$libresoc.v:169902$9479 + attribute \src "libresoc.v:169698.7-169698.28" + process $proc$libresoc.v:169698$9479 assign { } { } assign $0\xer_so_ok$29[0:0]$9480 1'0 sync always sync init update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9480 end - attribute \src "libresoc.v:169910.3-169911.37" - process $proc$libresoc.v:169910$9282 + attribute \src "libresoc.v:169706.3-169707.37" + process $proc$libresoc.v:169706$9282 assign { } { } assign $0\xer_so$28[0:0]$9283 \xer_so$28$next sync posedge \coresync_clk update \xer_so$28 $0\xer_so$28[0:0]$9283 end - attribute \src "libresoc.v:169912.3-169913.43" - process $proc$libresoc.v:169912$9284 + attribute \src "libresoc.v:169708.3-169709.43" + process $proc$libresoc.v:169708$9284 assign { } { } assign $0\xer_so_ok$29[0:0]$9285 \xer_so_ok$29$next sync posedge \coresync_clk update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9285 end - attribute \src "libresoc.v:169914.3-169915.37" - process $proc$libresoc.v:169914$9286 + attribute \src "libresoc.v:169710.3-169711.37" + process $proc$libresoc.v:169710$9286 assign { } { } assign $0\xer_ov$26[1:0]$9287 \xer_ov$26$next sync posedge \coresync_clk update \xer_ov$26 $0\xer_ov$26[1:0]$9287 end - attribute \src "libresoc.v:169916.3-169917.43" - process $proc$libresoc.v:169916$9288 + attribute \src "libresoc.v:169712.3-169713.43" + process $proc$libresoc.v:169712$9288 assign { } { } assign $0\xer_ov_ok$27[0:0]$9289 \xer_ov_ok$27$next sync posedge \coresync_clk update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9289 end - attribute \src "libresoc.v:169918.3-169919.37" - process $proc$libresoc.v:169918$9290 + attribute \src "libresoc.v:169714.3-169715.37" + process $proc$libresoc.v:169714$9290 assign { } { } assign $0\xer_ca$24[1:0]$9291 \xer_ca$24$next sync posedge \coresync_clk update \xer_ca$24 $0\xer_ca$24[1:0]$9291 end - attribute \src "libresoc.v:169920.3-169921.43" - process $proc$libresoc.v:169920$9292 + attribute \src "libresoc.v:169716.3-169717.43" + process $proc$libresoc.v:169716$9292 assign { } { } assign $0\xer_ca_ok$25[0:0]$9293 \xer_ca_ok$25$next sync posedge \coresync_clk update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9293 end - attribute \src "libresoc.v:169922.3-169923.33" - process $proc$libresoc.v:169922$9294 + attribute \src "libresoc.v:169718.3-169719.33" + process $proc$libresoc.v:169718$9294 assign { } { } assign $0\cr_a$22[3:0]$9295 \cr_a$22$next sync posedge \coresync_clk update \cr_a$22 $0\cr_a$22[3:0]$9295 end - attribute \src "libresoc.v:169924.3-169925.39" - process $proc$libresoc.v:169924$9296 + attribute \src "libresoc.v:169720.3-169721.39" + process $proc$libresoc.v:169720$9296 assign { } { } assign $0\cr_a_ok$23[0:0]$9297 \cr_a_ok$23$next sync posedge \coresync_clk update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9297 end - attribute \src "libresoc.v:169926.3-169927.27" - process $proc$libresoc.v:169926$9298 + attribute \src "libresoc.v:169722.3-169723.27" + process $proc$libresoc.v:169722$9298 assign { } { } assign $0\o$20[63:0]$9299 \o$20$next sync posedge \coresync_clk update \o$20 $0\o$20[63:0]$9299 end - attribute \src "libresoc.v:169928.3-169929.33" - process $proc$libresoc.v:169928$9300 + attribute \src "libresoc.v:169724.3-169725.33" + process $proc$libresoc.v:169724$9300 assign { } { } assign $0\o_ok$21[0:0]$9301 \o_ok$21$next sync posedge \coresync_clk update \o_ok$21 $0\o_ok$21[0:0]$9301 end - attribute \src "libresoc.v:169930.3-169931.57" - process $proc$libresoc.v:169930$9302 + attribute \src "libresoc.v:169726.3-169727.57" + process $proc$libresoc.v:169726$9302 assign { } { } assign $0\alu_op__insn_type$2[6:0]$9303 \alu_op__insn_type$2$next sync posedge \coresync_clk update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9303 end - attribute \src "libresoc.v:169932.3-169933.53" - process $proc$libresoc.v:169932$9304 + attribute \src "libresoc.v:169728.3-169729.53" + process $proc$libresoc.v:169728$9304 assign { } { } assign $0\alu_op__fn_unit$3[13:0]$9305 \alu_op__fn_unit$3$next sync posedge \coresync_clk update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9305 end - attribute \src "libresoc.v:169934.3-169935.67" - process $proc$libresoc.v:169934$9306 + attribute \src "libresoc.v:169730.3-169731.67" + process $proc$libresoc.v:169730$9306 assign { } { } assign $0\alu_op__imm_data__data$4[63:0]$9307 \alu_op__imm_data__data$4$next sync posedge \coresync_clk update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9307 end - attribute \src "libresoc.v:169936.3-169937.63" - process $proc$libresoc.v:169936$9308 + attribute \src "libresoc.v:169732.3-169733.63" + process $proc$libresoc.v:169732$9308 assign { } { } assign $0\alu_op__imm_data__ok$5[0:0]$9309 \alu_op__imm_data__ok$5$next sync posedge \coresync_clk update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9309 end - attribute \src "libresoc.v:169938.3-169939.51" - process $proc$libresoc.v:169938$9310 + attribute \src "libresoc.v:169734.3-169735.51" + process $proc$libresoc.v:169734$9310 assign { } { } assign $0\alu_op__rc__rc$6[0:0]$9311 \alu_op__rc__rc$6$next sync posedge \coresync_clk update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9311 end - attribute \src "libresoc.v:169940.3-169941.51" - process $proc$libresoc.v:169940$9312 + attribute \src "libresoc.v:169736.3-169737.51" + process $proc$libresoc.v:169736$9312 assign { } { } assign $0\alu_op__rc__ok$7[0:0]$9313 \alu_op__rc__ok$7$next sync posedge \coresync_clk update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9313 end - attribute \src "libresoc.v:169942.3-169943.51" - process $proc$libresoc.v:169942$9314 + attribute \src "libresoc.v:169738.3-169739.51" + process $proc$libresoc.v:169738$9314 assign { } { } assign $0\alu_op__oe__oe$8[0:0]$9315 \alu_op__oe__oe$8$next sync posedge \coresync_clk update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9315 end - attribute \src "libresoc.v:169944.3-169945.51" - process $proc$libresoc.v:169944$9316 + attribute \src "libresoc.v:169740.3-169741.51" + process $proc$libresoc.v:169740$9316 assign { } { } assign $0\alu_op__oe__ok$9[0:0]$9317 \alu_op__oe__ok$9$next sync posedge \coresync_clk update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9317 end - attribute \src "libresoc.v:169946.3-169947.59" - process $proc$libresoc.v:169946$9318 + attribute \src "libresoc.v:169742.3-169743.59" + process $proc$libresoc.v:169742$9318 assign { } { } assign $0\alu_op__invert_in$10[0:0]$9319 \alu_op__invert_in$10$next sync posedge \coresync_clk update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9319 end - attribute \src "libresoc.v:169948.3-169949.53" - process $proc$libresoc.v:169948$9320 + attribute \src "libresoc.v:169744.3-169745.53" + process $proc$libresoc.v:169744$9320 assign { } { } assign $0\alu_op__zero_a$11[0:0]$9321 \alu_op__zero_a$11$next sync posedge \coresync_clk update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9321 end - attribute \src "libresoc.v:169950.3-169951.61" - process $proc$libresoc.v:169950$9322 + attribute \src "libresoc.v:169746.3-169747.61" + process $proc$libresoc.v:169746$9322 assign { } { } assign $0\alu_op__invert_out$12[0:0]$9323 \alu_op__invert_out$12$next sync posedge \coresync_clk update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9323 end - attribute \src "libresoc.v:169952.3-169953.59" - process $proc$libresoc.v:169952$9324 + attribute \src "libresoc.v:169748.3-169749.59" + process $proc$libresoc.v:169748$9324 assign { } { } assign $0\alu_op__write_cr0$13[0:0]$9325 \alu_op__write_cr0$13$next sync posedge \coresync_clk update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9325 end - attribute \src "libresoc.v:169954.3-169955.63" - process $proc$libresoc.v:169954$9326 + attribute \src "libresoc.v:169750.3-169751.63" + process $proc$libresoc.v:169750$9326 assign { } { } assign $0\alu_op__input_carry$14[1:0]$9327 \alu_op__input_carry$14$next sync posedge \coresync_clk update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9327 end - attribute \src "libresoc.v:169956.3-169957.65" - process $proc$libresoc.v:169956$9328 + attribute \src "libresoc.v:169752.3-169753.65" + process $proc$libresoc.v:169752$9328 assign { } { } assign $0\alu_op__output_carry$15[0:0]$9329 \alu_op__output_carry$15$next sync posedge \coresync_clk update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9329 end - attribute \src "libresoc.v:169958.3-169959.57" - process $proc$libresoc.v:169958$9330 + attribute \src "libresoc.v:169754.3-169755.57" + process $proc$libresoc.v:169754$9330 assign { } { } assign $0\alu_op__is_32bit$16[0:0]$9331 \alu_op__is_32bit$16$next sync posedge \coresync_clk update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9331 end - attribute \src "libresoc.v:169960.3-169961.59" - process $proc$libresoc.v:169960$9332 + attribute \src "libresoc.v:169756.3-169757.59" + process $proc$libresoc.v:169756$9332 assign { } { } assign $0\alu_op__is_signed$17[0:0]$9333 \alu_op__is_signed$17$next sync posedge \coresync_clk update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9333 end - attribute \src "libresoc.v:169962.3-169963.57" - process $proc$libresoc.v:169962$9334 + attribute \src "libresoc.v:169758.3-169759.57" + process $proc$libresoc.v:169758$9334 assign { } { } assign $0\alu_op__data_len$18[3:0]$9335 \alu_op__data_len$18$next sync posedge \coresync_clk update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9335 end - attribute \src "libresoc.v:169964.3-169965.49" - process $proc$libresoc.v:169964$9336 + attribute \src "libresoc.v:169760.3-169761.49" + process $proc$libresoc.v:169760$9336 assign { } { } assign $0\alu_op__insn$19[31:0]$9337 \alu_op__insn$19$next sync posedge \coresync_clk update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9337 end - attribute \src "libresoc.v:169966.3-169967.33" - process $proc$libresoc.v:169966$9338 + attribute \src "libresoc.v:169762.3-169763.33" + process $proc$libresoc.v:169762$9338 assign { } { } assign $0\muxid$1[1:0]$9339 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9339 end - attribute \src "libresoc.v:169968.3-169969.29" - process $proc$libresoc.v:169968$9340 + attribute \src "libresoc.v:169764.3-169765.29" + process $proc$libresoc.v:169764$9340 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:170034.3-170051.6" - process $proc$libresoc.v:170034$9341 + attribute \src "libresoc.v:169830.3-169847.6" + process $proc$libresoc.v:169830$9341 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9342 $2\r_busy$next[0:0]$9344 - attribute \src "libresoc.v:170035.5-170035.29" + attribute \src "libresoc.v:169831.5-169831.29" switch \initial - attribute \src "libresoc.v:170035.9-170035.17" + attribute \src "libresoc.v:169831.9-169831.17" case 1'1 case end @@ -314630,14 +314464,14 @@ module \pipe2 sync always update \r_busy$next $0\r_busy$next[0:0]$9342 end - attribute \src "libresoc.v:170052.3-170064.6" - process $proc$libresoc.v:170052$9345 + attribute \src "libresoc.v:169848.3-169860.6" + process $proc$libresoc.v:169848$9345 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9346 $1\muxid$1$next[1:0]$9347 - attribute \src "libresoc.v:170053.5-170053.29" + attribute \src "libresoc.v:169849.5-169849.29" switch \initial - attribute \src "libresoc.v:170053.9-170053.17" + attribute \src "libresoc.v:169849.9-169849.17" case 1'1 case end @@ -314657,8 +314491,8 @@ module \pipe2 sync always update \muxid$1$next $0\muxid$1$next[1:0]$9346 end - attribute \src "libresoc.v:170065.3-170106.6" - process $proc$libresoc.v:170065$9348 + attribute \src "libresoc.v:169861.3-169902.6" + process $proc$libresoc.v:169861$9348 assign { } { } assign { } { } assign { } { } @@ -314719,9 +314553,9 @@ module \pipe2 assign $0\alu_op__oe__ok$9$next[0:0]$9361 $2\alu_op__oe__ok$9$next[0:0]$9388 assign $0\alu_op__rc__ok$7$next[0:0]$9363 $2\alu_op__rc__ok$7$next[0:0]$9389 assign $0\alu_op__rc__rc$6$next[0:0]$9364 $2\alu_op__rc__rc$6$next[0:0]$9390 - attribute \src "libresoc.v:170066.5-170066.29" + attribute \src "libresoc.v:169862.5-169862.29" switch \initial - attribute \src "libresoc.v:170066.9-170066.17" + attribute \src "libresoc.v:169862.9-169862.17" case 1'1 case end @@ -314833,8 +314667,8 @@ module \pipe2 update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9365 update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9366 end - attribute \src "libresoc.v:170107.3-170125.6" - process $proc$libresoc.v:170107$9391 + attribute \src "libresoc.v:169903.3-169921.6" + process $proc$libresoc.v:169903$9391 assign { } { } assign { } { } assign { } { } @@ -314842,9 +314676,9 @@ module \pipe2 assign $0\o$20$next[63:0]$9392 $1\o$20$next[63:0]$9394 assign { } { } assign $0\o_ok$21$next[0:0]$9393 $2\o_ok$21$next[0:0]$9396 - attribute \src "libresoc.v:170108.5-170108.29" + attribute \src "libresoc.v:169904.5-169904.29" switch \initial - attribute \src "libresoc.v:170108.9-170108.17" + attribute \src "libresoc.v:169904.9-169904.17" case 1'1 case end @@ -314877,8 +314711,8 @@ module \pipe2 update \o$20$next $0\o$20$next[63:0]$9392 update \o_ok$21$next $0\o_ok$21$next[0:0]$9393 end - attribute \src "libresoc.v:170126.3-170144.6" - process $proc$libresoc.v:170126$9397 + attribute \src "libresoc.v:169922.3-169940.6" + process $proc$libresoc.v:169922$9397 assign { } { } assign { } { } assign { } { } @@ -314886,9 +314720,9 @@ module \pipe2 assign $0\cr_a$22$next[3:0]$9398 $1\cr_a$22$next[3:0]$9400 assign { } { } assign $0\cr_a_ok$23$next[0:0]$9399 $2\cr_a_ok$23$next[0:0]$9402 - attribute \src "libresoc.v:170127.5-170127.29" + attribute \src "libresoc.v:169923.5-169923.29" switch \initial - attribute \src "libresoc.v:170127.9-170127.17" + attribute \src "libresoc.v:169923.9-169923.17" case 1'1 case end @@ -314921,8 +314755,8 @@ module \pipe2 update \cr_a$22$next $0\cr_a$22$next[3:0]$9398 update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9399 end - attribute \src "libresoc.v:170145.3-170163.6" - process $proc$libresoc.v:170145$9403 + attribute \src "libresoc.v:169941.3-169959.6" + process $proc$libresoc.v:169941$9403 assign { } { } assign { } { } assign { } { } @@ -314930,9 +314764,9 @@ module \pipe2 assign $0\xer_ca$24$next[1:0]$9404 $1\xer_ca$24$next[1:0]$9406 assign { } { } assign $0\xer_ca_ok$25$next[0:0]$9405 $2\xer_ca_ok$25$next[0:0]$9408 - attribute \src "libresoc.v:170146.5-170146.29" + attribute \src "libresoc.v:169942.5-169942.29" switch \initial - attribute \src "libresoc.v:170146.9-170146.17" + attribute \src "libresoc.v:169942.9-169942.17" case 1'1 case end @@ -314965,8 +314799,8 @@ module \pipe2 update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9404 update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9405 end - attribute \src "libresoc.v:170164.3-170182.6" - process $proc$libresoc.v:170164$9409 + attribute \src "libresoc.v:169960.3-169978.6" + process $proc$libresoc.v:169960$9409 assign { } { } assign { } { } assign { } { } @@ -314974,9 +314808,9 @@ module \pipe2 assign $0\xer_ov$26$next[1:0]$9410 $1\xer_ov$26$next[1:0]$9412 assign { } { } assign $0\xer_ov_ok$27$next[0:0]$9411 $2\xer_ov_ok$27$next[0:0]$9414 - attribute \src "libresoc.v:170165.5-170165.29" + attribute \src "libresoc.v:169961.5-169961.29" switch \initial - attribute \src "libresoc.v:170165.9-170165.17" + attribute \src "libresoc.v:169961.9-169961.17" case 1'1 case end @@ -315009,8 +314843,8 @@ module \pipe2 update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9410 update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9411 end - attribute \src "libresoc.v:170183.3-170201.6" - process $proc$libresoc.v:170183$9415 + attribute \src "libresoc.v:169979.3-169997.6" + process $proc$libresoc.v:169979$9415 assign { } { } assign { } { } assign { } { } @@ -315018,9 +314852,9 @@ module \pipe2 assign $0\xer_so$28$next[0:0]$9416 $1\xer_so$28$next[0:0]$9418 assign { } { } assign $0\xer_so_ok$29$next[0:0]$9417 $2\xer_so_ok$29$next[0:0]$9420 - attribute \src "libresoc.v:170184.5-170184.29" + attribute \src "libresoc.v:169980.5-169980.29" switch \initial - attribute \src "libresoc.v:170184.9-170184.17" + attribute \src "libresoc.v:169980.9-169980.17" case 1'1 case end @@ -315053,7 +314887,7 @@ module \pipe2 update \xer_so$28$next $0\xer_so$28$next[0:0]$9416 update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9417 end - connect \$60 $and$libresoc.v:169909$9281_Y + connect \$60 $and$libresoc.v:169705$9281_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } @@ -315074,240 +314908,240 @@ module \pipe2 connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:170225.1-171294.10" +attribute \src "libresoc.v:170021.1-171090.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" attribute \generator "nMigen" module \pipe2$115 - attribute \src "libresoc.v:171240.3-171258.6" + attribute \src "libresoc.v:171036.3-171054.6" wire width 4 $0\cr_a$21$next[3:0]$9586 - attribute \src "libresoc.v:171046.3-171047.33" + attribute \src "libresoc.v:170842.3-170843.33" wire width 4 $0\cr_a$21[3:0]$9487 - attribute \src "libresoc.v:170237.13-170237.29" + attribute \src "libresoc.v:170033.13-170033.29" wire width 4 $0\cr_a$21[3:0]$9599 - attribute \src "libresoc.v:171240.3-171258.6" + attribute \src "libresoc.v:171036.3-171054.6" wire $0\cr_a_ok$22$next[0:0]$9587 - attribute \src "libresoc.v:171048.3-171049.39" + attribute \src "libresoc.v:170844.3-170845.39" wire $0\cr_a_ok$22[0:0]$9489 - attribute \src "libresoc.v:170246.7-170246.26" + attribute \src "libresoc.v:170042.7-170042.26" wire $0\cr_a_ok$22[0:0]$9601 - attribute \src "libresoc.v:170226.7-170226.20" + attribute \src "libresoc.v:170022.7-170022.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171167.3-171179.6" + attribute \src "libresoc.v:170963.3-170975.6" wire width 2 $0\muxid$1$next[1:0]$9536 - attribute \src "libresoc.v:171088.3-171089.33" + attribute \src "libresoc.v:170884.3-170885.33" wire width 2 $0\muxid$1[1:0]$9529 - attribute \src "libresoc.v:170257.13-170257.29" + attribute \src "libresoc.v:170053.13-170053.29" wire width 2 $0\muxid$1[1:0]$9603 - attribute \src "libresoc.v:171221.3-171239.6" + attribute \src "libresoc.v:171017.3-171035.6" wire width 64 $0\o$19$next[63:0]$9580 - attribute \src "libresoc.v:171050.3-171051.27" + attribute \src "libresoc.v:170846.3-170847.27" wire width 64 $0\o$19[63:0]$9491 - attribute \src "libresoc.v:170272.14-170272.43" + attribute \src "libresoc.v:170068.14-170068.43" wire width 64 $0\o$19[63:0]$9605 - attribute \src "libresoc.v:171221.3-171239.6" + attribute \src "libresoc.v:171017.3-171035.6" wire $0\o_ok$20$next[0:0]$9581 - attribute \src "libresoc.v:171052.3-171053.33" + attribute \src "libresoc.v:170848.3-170849.33" wire $0\o_ok$20[0:0]$9493 - attribute \src "libresoc.v:170281.7-170281.23" + attribute \src "libresoc.v:170077.7-170077.23" wire $0\o_ok$20[0:0]$9607 - attribute \src "libresoc.v:171149.3-171166.6" + attribute \src "libresoc.v:170945.3-170962.6" wire $0\r_busy$next[0:0]$9532 - attribute \src "libresoc.v:171090.3-171091.29" + attribute \src "libresoc.v:170886.3-170887.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9539 - attribute \src "libresoc.v:171056.3-171057.51" + attribute \src "libresoc.v:170852.3-170853.51" wire width 14 $0\sr_op__fn_unit$3[13:0]$9497 - attribute \src "libresoc.v:170614.14-170614.43" + attribute \src "libresoc.v:170410.14-170410.43" wire width 14 $0\sr_op__fn_unit$3[13:0]$9610 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9540 - attribute \src "libresoc.v:171058.3-171059.65" + attribute \src "libresoc.v:170854.3-170855.65" wire width 64 $0\sr_op__imm_data__data$4[63:0]$9499 - attribute \src "libresoc.v:170638.14-170638.62" + attribute \src "libresoc.v:170434.14-170434.62" wire width 64 $0\sr_op__imm_data__data$4[63:0]$9612 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__imm_data__ok$5$next[0:0]$9541 - attribute \src "libresoc.v:171060.3-171061.61" + attribute \src "libresoc.v:170856.3-170857.61" wire $0\sr_op__imm_data__ok$5[0:0]$9501 - attribute \src "libresoc.v:170647.7-170647.37" + attribute \src "libresoc.v:170443.7-170443.37" wire $0\sr_op__imm_data__ok$5[0:0]$9614 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire width 2 $0\sr_op__input_carry$12$next[1:0]$9542 - attribute \src "libresoc.v:171074.3-171075.61" + attribute \src "libresoc.v:170870.3-170871.61" wire width 2 $0\sr_op__input_carry$12[1:0]$9515 - attribute \src "libresoc.v:170664.13-170664.43" + attribute \src "libresoc.v:170460.13-170460.43" wire width 2 $0\sr_op__input_carry$12[1:0]$9616 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__input_cr$14$next[0:0]$9543 - attribute \src "libresoc.v:171078.3-171079.55" + attribute \src "libresoc.v:170874.3-170875.55" wire $0\sr_op__input_cr$14[0:0]$9519 - attribute \src "libresoc.v:170677.7-170677.34" + attribute \src "libresoc.v:170473.7-170473.34" wire $0\sr_op__input_cr$14[0:0]$9618 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire width 32 $0\sr_op__insn$18$next[31:0]$9544 - attribute \src "libresoc.v:171086.3-171087.47" + attribute \src "libresoc.v:170882.3-170883.47" wire width 32 $0\sr_op__insn$18[31:0]$9527 - attribute \src "libresoc.v:170686.14-170686.38" + attribute \src "libresoc.v:170482.14-170482.38" wire width 32 $0\sr_op__insn$18[31:0]$9620 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire width 7 $0\sr_op__insn_type$2$next[6:0]$9545 - attribute \src "libresoc.v:171054.3-171055.55" + attribute \src "libresoc.v:170850.3-170851.55" wire width 7 $0\sr_op__insn_type$2[6:0]$9495 - attribute \src "libresoc.v:170845.13-170845.41" + attribute \src "libresoc.v:170641.13-170641.41" wire width 7 $0\sr_op__insn_type$2[6:0]$9622 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__invert_in$11$next[0:0]$9546 - attribute \src "libresoc.v:171072.3-171073.57" + attribute \src "libresoc.v:170868.3-170869.57" wire $0\sr_op__invert_in$11[0:0]$9513 - attribute \src "libresoc.v:170929.7-170929.35" + attribute \src "libresoc.v:170725.7-170725.35" wire $0\sr_op__invert_in$11[0:0]$9624 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__is_32bit$16$next[0:0]$9547 - attribute \src "libresoc.v:171082.3-171083.55" + attribute \src "libresoc.v:170878.3-170879.55" wire $0\sr_op__is_32bit$16[0:0]$9523 - attribute \src "libresoc.v:170938.7-170938.34" + attribute \src "libresoc.v:170734.7-170734.34" wire $0\sr_op__is_32bit$16[0:0]$9626 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__is_signed$17$next[0:0]$9548 - attribute \src "libresoc.v:171084.3-171085.57" + attribute \src "libresoc.v:170880.3-170881.57" wire $0\sr_op__is_signed$17[0:0]$9525 - attribute \src "libresoc.v:170947.7-170947.35" + attribute \src "libresoc.v:170743.7-170743.35" wire $0\sr_op__is_signed$17[0:0]$9628 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__oe__oe$8$next[0:0]$9549 - attribute \src "libresoc.v:171066.3-171067.49" + attribute \src "libresoc.v:170862.3-170863.49" wire $0\sr_op__oe__oe$8[0:0]$9507 - attribute \src "libresoc.v:170958.7-170958.31" + attribute \src "libresoc.v:170754.7-170754.31" wire $0\sr_op__oe__oe$8[0:0]$9630 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__oe__ok$9$next[0:0]$9550 - attribute \src "libresoc.v:171068.3-171069.49" + attribute \src "libresoc.v:170864.3-170865.49" wire $0\sr_op__oe__ok$9[0:0]$9509 - attribute \src "libresoc.v:170967.7-170967.31" + attribute \src "libresoc.v:170763.7-170763.31" wire $0\sr_op__oe__ok$9[0:0]$9632 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__output_carry$13$next[0:0]$9551 - attribute \src "libresoc.v:171076.3-171077.63" + attribute \src "libresoc.v:170872.3-170873.63" wire $0\sr_op__output_carry$13[0:0]$9517 - attribute \src "libresoc.v:170974.7-170974.38" + attribute \src "libresoc.v:170770.7-170770.38" wire $0\sr_op__output_carry$13[0:0]$9634 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__output_cr$15$next[0:0]$9552 - attribute \src "libresoc.v:171080.3-171081.57" + attribute \src "libresoc.v:170876.3-170877.57" wire $0\sr_op__output_cr$15[0:0]$9521 - attribute \src "libresoc.v:170983.7-170983.35" + attribute \src "libresoc.v:170779.7-170779.35" wire $0\sr_op__output_cr$15[0:0]$9636 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__rc__ok$7$next[0:0]$9553 - attribute \src "libresoc.v:171064.3-171065.49" + attribute \src "libresoc.v:170860.3-170861.49" wire $0\sr_op__rc__ok$7[0:0]$9505 - attribute \src "libresoc.v:170994.7-170994.31" + attribute \src "libresoc.v:170790.7-170790.31" wire $0\sr_op__rc__ok$7[0:0]$9638 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__rc__rc$6$next[0:0]$9554 - attribute \src "libresoc.v:171062.3-171063.49" + attribute \src "libresoc.v:170858.3-170859.49" wire $0\sr_op__rc__rc$6[0:0]$9503 - attribute \src "libresoc.v:171003.7-171003.31" + attribute \src "libresoc.v:170799.7-170799.31" wire $0\sr_op__rc__rc$6[0:0]$9640 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__write_cr0$10$next[0:0]$9555 - attribute \src "libresoc.v:171070.3-171071.57" + attribute \src "libresoc.v:170866.3-170867.57" wire $0\sr_op__write_cr0$10[0:0]$9511 - attribute \src "libresoc.v:171010.7-171010.35" + attribute \src "libresoc.v:170806.7-170806.35" wire $0\sr_op__write_cr0$10[0:0]$9642 - attribute \src "libresoc.v:171259.3-171277.6" + attribute \src "libresoc.v:171055.3-171073.6" wire width 2 $0\xer_ca$23$next[1:0]$9592 - attribute \src "libresoc.v:171042.3-171043.37" + attribute \src "libresoc.v:170838.3-170839.37" wire width 2 $0\xer_ca$23[1:0]$9483 - attribute \src "libresoc.v:171019.13-171019.31" + attribute \src "libresoc.v:170815.13-170815.31" wire width 2 $0\xer_ca$23[1:0]$9644 - attribute \src "libresoc.v:171259.3-171277.6" + attribute \src "libresoc.v:171055.3-171073.6" wire $0\xer_ca_ok$24$next[0:0]$9593 - attribute \src "libresoc.v:171044.3-171045.43" + attribute \src "libresoc.v:170840.3-170841.43" wire $0\xer_ca_ok$24[0:0]$9485 - attribute \src "libresoc.v:171028.7-171028.28" + attribute \src "libresoc.v:170824.7-170824.28" wire $0\xer_ca_ok$24[0:0]$9646 - attribute \src "libresoc.v:171240.3-171258.6" + attribute \src "libresoc.v:171036.3-171054.6" wire width 4 $1\cr_a$21$next[3:0]$9588 - attribute \src "libresoc.v:171240.3-171258.6" + attribute \src "libresoc.v:171036.3-171054.6" wire $1\cr_a_ok$22$next[0:0]$9589 - attribute \src "libresoc.v:171167.3-171179.6" + attribute \src "libresoc.v:170963.3-170975.6" wire width 2 $1\muxid$1$next[1:0]$9537 - attribute \src "libresoc.v:171221.3-171239.6" + attribute \src "libresoc.v:171017.3-171035.6" wire width 64 $1\o$19$next[63:0]$9582 - attribute \src "libresoc.v:171221.3-171239.6" + attribute \src "libresoc.v:171017.3-171035.6" wire $1\o_ok$20$next[0:0]$9583 - attribute \src "libresoc.v:171149.3-171166.6" + attribute \src "libresoc.v:170945.3-170962.6" wire $1\r_busy$next[0:0]$9533 - attribute \src "libresoc.v:170577.7-170577.20" + attribute \src "libresoc.v:170373.7-170373.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9556 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9557 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__imm_data__ok$5$next[0:0]$9558 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire width 2 $1\sr_op__input_carry$12$next[1:0]$9559 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__input_cr$14$next[0:0]$9560 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire width 32 $1\sr_op__insn$18$next[31:0]$9561 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire width 7 $1\sr_op__insn_type$2$next[6:0]$9562 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__invert_in$11$next[0:0]$9563 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__is_32bit$16$next[0:0]$9564 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__is_signed$17$next[0:0]$9565 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__oe__oe$8$next[0:0]$9566 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__oe__ok$9$next[0:0]$9567 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__output_carry$13$next[0:0]$9568 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__output_cr$15$next[0:0]$9569 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__rc__ok$7$next[0:0]$9570 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__rc__rc$6$next[0:0]$9571 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__write_cr0$10$next[0:0]$9572 - attribute \src "libresoc.v:171259.3-171277.6" + attribute \src "libresoc.v:171055.3-171073.6" wire width 2 $1\xer_ca$23$next[1:0]$9594 - attribute \src "libresoc.v:171259.3-171277.6" + attribute \src "libresoc.v:171055.3-171073.6" wire $1\xer_ca_ok$24$next[0:0]$9595 - attribute \src "libresoc.v:171240.3-171258.6" + attribute \src "libresoc.v:171036.3-171054.6" wire $2\cr_a_ok$22$next[0:0]$9590 - attribute \src "libresoc.v:171221.3-171239.6" + attribute \src "libresoc.v:171017.3-171035.6" wire $2\o_ok$20$next[0:0]$9584 - attribute \src "libresoc.v:171149.3-171166.6" + attribute \src "libresoc.v:170945.3-170962.6" wire $2\r_busy$next[0:0]$9534 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9573 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $2\sr_op__imm_data__ok$5$next[0:0]$9574 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $2\sr_op__oe__oe$8$next[0:0]$9575 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $2\sr_op__oe__ok$9$next[0:0]$9576 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $2\sr_op__rc__ok$7$next[0:0]$9577 - attribute \src "libresoc.v:171180.3-171220.6" + attribute \src "libresoc.v:170976.3-171016.6" wire $2\sr_op__rc__rc$6$next[0:0]$9578 - attribute \src "libresoc.v:171259.3-171277.6" + attribute \src "libresoc.v:171055.3-171073.6" wire $2\xer_ca_ok$24$next[0:0]$9596 - attribute \src "libresoc.v:171041.18-171041.118" - wire $and$libresoc.v:171041$9481_Y + attribute \src "libresoc.v:170837.18-170837.118" + wire $and$libresoc.v:170837$9481_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 56 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 24 \cr_a @@ -315327,7 +315161,7 @@ module \pipe2$115 wire \cr_a_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$74 - attribute \src "libresoc.v:170226.7-170226.15" + attribute \src "libresoc.v:170022.7-170022.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -316096,7 +315930,7 @@ module \pipe2$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:171041$9481 + cell $and $and$libresoc.v:170837$9481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -316104,16 +315938,16 @@ module \pipe2$115 parameter \Y_WIDTH 1 connect \A \p_valid_i$50 connect \B \p_ready_o - connect \Y $and$libresoc.v:171041$9481_Y + connect \Y $and$libresoc.v:170837$9481_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:171092.11-171095.4" + attribute \src "libresoc.v:170888.11-170891.4" cell \n$117 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:171096.16-171144.4" + attribute \src "libresoc.v:170892.16-170940.4" cell \output$118 \output connect \cr_a \output_cr_a connect \cr_a$21 \output_cr_a$45 @@ -316164,403 +315998,403 @@ module \pipe2$115 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:171145.11-171148.4" + attribute \src "libresoc.v:170941.11-170944.4" cell \p$116 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:170226.7-170226.20" - process $proc$libresoc.v:170226$9597 + attribute \src "libresoc.v:170022.7-170022.20" + process $proc$libresoc.v:170022$9597 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170237.13-170237.29" - process $proc$libresoc.v:170237$9598 + attribute \src "libresoc.v:170033.13-170033.29" + process $proc$libresoc.v:170033$9598 assign { } { } assign $0\cr_a$21[3:0]$9599 4'0000 sync always sync init update \cr_a$21 $0\cr_a$21[3:0]$9599 end - attribute \src "libresoc.v:170246.7-170246.26" - process $proc$libresoc.v:170246$9600 + attribute \src "libresoc.v:170042.7-170042.26" + process $proc$libresoc.v:170042$9600 assign { } { } assign $0\cr_a_ok$22[0:0]$9601 1'0 sync always sync init update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9601 end - attribute \src "libresoc.v:170257.13-170257.29" - process $proc$libresoc.v:170257$9602 + attribute \src "libresoc.v:170053.13-170053.29" + process $proc$libresoc.v:170053$9602 assign { } { } assign $0\muxid$1[1:0]$9603 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$9603 end - attribute \src "libresoc.v:170272.14-170272.43" - process $proc$libresoc.v:170272$9604 + attribute \src "libresoc.v:170068.14-170068.43" + process $proc$libresoc.v:170068$9604 assign { } { } assign $0\o$19[63:0]$9605 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$19 $0\o$19[63:0]$9605 end - attribute \src "libresoc.v:170281.7-170281.23" - process $proc$libresoc.v:170281$9606 + attribute \src "libresoc.v:170077.7-170077.23" + process $proc$libresoc.v:170077$9606 assign { } { } assign $0\o_ok$20[0:0]$9607 1'0 sync always sync init update \o_ok$20 $0\o_ok$20[0:0]$9607 end - attribute \src "libresoc.v:170577.7-170577.20" - process $proc$libresoc.v:170577$9608 + attribute \src "libresoc.v:170373.7-170373.20" + process $proc$libresoc.v:170373$9608 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:170614.14-170614.43" - process $proc$libresoc.v:170614$9609 + attribute \src "libresoc.v:170410.14-170410.43" + process $proc$libresoc.v:170410$9609 assign { } { } assign $0\sr_op__fn_unit$3[13:0]$9610 14'00000000000000 sync always sync init update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9610 end - attribute \src "libresoc.v:170638.14-170638.62" - process $proc$libresoc.v:170638$9611 + attribute \src "libresoc.v:170434.14-170434.62" + process $proc$libresoc.v:170434$9611 assign { } { } assign $0\sr_op__imm_data__data$4[63:0]$9612 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9612 end - attribute \src "libresoc.v:170647.7-170647.37" - process $proc$libresoc.v:170647$9613 + attribute \src "libresoc.v:170443.7-170443.37" + process $proc$libresoc.v:170443$9613 assign { } { } assign $0\sr_op__imm_data__ok$5[0:0]$9614 1'0 sync always sync init update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9614 end - attribute \src "libresoc.v:170664.13-170664.43" - process $proc$libresoc.v:170664$9615 + attribute \src "libresoc.v:170460.13-170460.43" + process $proc$libresoc.v:170460$9615 assign { } { } assign $0\sr_op__input_carry$12[1:0]$9616 2'00 sync always sync init update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9616 end - attribute \src "libresoc.v:170677.7-170677.34" - process $proc$libresoc.v:170677$9617 + attribute \src "libresoc.v:170473.7-170473.34" + process $proc$libresoc.v:170473$9617 assign { } { } assign $0\sr_op__input_cr$14[0:0]$9618 1'0 sync always sync init update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9618 end - attribute \src "libresoc.v:170686.14-170686.38" - process $proc$libresoc.v:170686$9619 + attribute \src "libresoc.v:170482.14-170482.38" + process $proc$libresoc.v:170482$9619 assign { } { } assign $0\sr_op__insn$18[31:0]$9620 0 sync always sync init update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9620 end - attribute \src "libresoc.v:170845.13-170845.41" - process $proc$libresoc.v:170845$9621 + attribute \src "libresoc.v:170641.13-170641.41" + process $proc$libresoc.v:170641$9621 assign { } { } assign $0\sr_op__insn_type$2[6:0]$9622 7'0000000 sync always sync init update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9622 end - attribute \src "libresoc.v:170929.7-170929.35" - process $proc$libresoc.v:170929$9623 + attribute \src "libresoc.v:170725.7-170725.35" + process $proc$libresoc.v:170725$9623 assign { } { } assign $0\sr_op__invert_in$11[0:0]$9624 1'0 sync always sync init update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9624 end - attribute \src "libresoc.v:170938.7-170938.34" - process $proc$libresoc.v:170938$9625 + attribute \src "libresoc.v:170734.7-170734.34" + process $proc$libresoc.v:170734$9625 assign { } { } assign $0\sr_op__is_32bit$16[0:0]$9626 1'0 sync always sync init update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9626 end - attribute \src "libresoc.v:170947.7-170947.35" - process $proc$libresoc.v:170947$9627 + attribute \src "libresoc.v:170743.7-170743.35" + process $proc$libresoc.v:170743$9627 assign { } { } assign $0\sr_op__is_signed$17[0:0]$9628 1'0 sync always sync init update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9628 end - attribute \src "libresoc.v:170958.7-170958.31" - process $proc$libresoc.v:170958$9629 + attribute \src "libresoc.v:170754.7-170754.31" + process $proc$libresoc.v:170754$9629 assign { } { } assign $0\sr_op__oe__oe$8[0:0]$9630 1'0 sync always sync init update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9630 end - attribute \src "libresoc.v:170967.7-170967.31" - process $proc$libresoc.v:170967$9631 + attribute \src "libresoc.v:170763.7-170763.31" + process $proc$libresoc.v:170763$9631 assign { } { } assign $0\sr_op__oe__ok$9[0:0]$9632 1'0 sync always sync init update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9632 end - attribute \src "libresoc.v:170974.7-170974.38" - process $proc$libresoc.v:170974$9633 + attribute \src "libresoc.v:170770.7-170770.38" + process $proc$libresoc.v:170770$9633 assign { } { } assign $0\sr_op__output_carry$13[0:0]$9634 1'0 sync always sync init update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9634 end - attribute \src "libresoc.v:170983.7-170983.35" - process $proc$libresoc.v:170983$9635 + attribute \src "libresoc.v:170779.7-170779.35" + process $proc$libresoc.v:170779$9635 assign { } { } assign $0\sr_op__output_cr$15[0:0]$9636 1'0 sync always sync init update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9636 end - attribute \src "libresoc.v:170994.7-170994.31" - process $proc$libresoc.v:170994$9637 + attribute \src "libresoc.v:170790.7-170790.31" + process $proc$libresoc.v:170790$9637 assign { } { } assign $0\sr_op__rc__ok$7[0:0]$9638 1'0 sync always sync init update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9638 end - attribute \src "libresoc.v:171003.7-171003.31" - process $proc$libresoc.v:171003$9639 + attribute \src "libresoc.v:170799.7-170799.31" + process $proc$libresoc.v:170799$9639 assign { } { } assign $0\sr_op__rc__rc$6[0:0]$9640 1'0 sync always sync init update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9640 end - attribute \src "libresoc.v:171010.7-171010.35" - process $proc$libresoc.v:171010$9641 + attribute \src "libresoc.v:170806.7-170806.35" + process $proc$libresoc.v:170806$9641 assign { } { } assign $0\sr_op__write_cr0$10[0:0]$9642 1'0 sync always sync init update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9642 end - attribute \src "libresoc.v:171019.13-171019.31" - process $proc$libresoc.v:171019$9643 + attribute \src "libresoc.v:170815.13-170815.31" + process $proc$libresoc.v:170815$9643 assign { } { } assign $0\xer_ca$23[1:0]$9644 2'00 sync always sync init update \xer_ca$23 $0\xer_ca$23[1:0]$9644 end - attribute \src "libresoc.v:171028.7-171028.28" - process $proc$libresoc.v:171028$9645 + attribute \src "libresoc.v:170824.7-170824.28" + process $proc$libresoc.v:170824$9645 assign { } { } assign $0\xer_ca_ok$24[0:0]$9646 1'0 sync always sync init update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9646 end - attribute \src "libresoc.v:171042.3-171043.37" - process $proc$libresoc.v:171042$9482 + attribute \src "libresoc.v:170838.3-170839.37" + process $proc$libresoc.v:170838$9482 assign { } { } assign $0\xer_ca$23[1:0]$9483 \xer_ca$23$next sync posedge \coresync_clk update \xer_ca$23 $0\xer_ca$23[1:0]$9483 end - attribute \src "libresoc.v:171044.3-171045.43" - process $proc$libresoc.v:171044$9484 + attribute \src "libresoc.v:170840.3-170841.43" + process $proc$libresoc.v:170840$9484 assign { } { } assign $0\xer_ca_ok$24[0:0]$9485 \xer_ca_ok$24$next sync posedge \coresync_clk update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9485 end - attribute \src "libresoc.v:171046.3-171047.33" - process $proc$libresoc.v:171046$9486 + attribute \src "libresoc.v:170842.3-170843.33" + process $proc$libresoc.v:170842$9486 assign { } { } assign $0\cr_a$21[3:0]$9487 \cr_a$21$next sync posedge \coresync_clk update \cr_a$21 $0\cr_a$21[3:0]$9487 end - attribute \src "libresoc.v:171048.3-171049.39" - process $proc$libresoc.v:171048$9488 + attribute \src "libresoc.v:170844.3-170845.39" + process $proc$libresoc.v:170844$9488 assign { } { } assign $0\cr_a_ok$22[0:0]$9489 \cr_a_ok$22$next sync posedge \coresync_clk update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9489 end - attribute \src "libresoc.v:171050.3-171051.27" - process $proc$libresoc.v:171050$9490 + attribute \src "libresoc.v:170846.3-170847.27" + process $proc$libresoc.v:170846$9490 assign { } { } assign $0\o$19[63:0]$9491 \o$19$next sync posedge \coresync_clk update \o$19 $0\o$19[63:0]$9491 end - attribute \src "libresoc.v:171052.3-171053.33" - process $proc$libresoc.v:171052$9492 + attribute \src "libresoc.v:170848.3-170849.33" + process $proc$libresoc.v:170848$9492 assign { } { } assign $0\o_ok$20[0:0]$9493 \o_ok$20$next sync posedge \coresync_clk update \o_ok$20 $0\o_ok$20[0:0]$9493 end - attribute \src "libresoc.v:171054.3-171055.55" - process $proc$libresoc.v:171054$9494 + attribute \src "libresoc.v:170850.3-170851.55" + process $proc$libresoc.v:170850$9494 assign { } { } assign $0\sr_op__insn_type$2[6:0]$9495 \sr_op__insn_type$2$next sync posedge \coresync_clk update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9495 end - attribute \src "libresoc.v:171056.3-171057.51" - process $proc$libresoc.v:171056$9496 + attribute \src "libresoc.v:170852.3-170853.51" + process $proc$libresoc.v:170852$9496 assign { } { } assign $0\sr_op__fn_unit$3[13:0]$9497 \sr_op__fn_unit$3$next sync posedge \coresync_clk update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9497 end - attribute \src "libresoc.v:171058.3-171059.65" - process $proc$libresoc.v:171058$9498 + attribute \src "libresoc.v:170854.3-170855.65" + process $proc$libresoc.v:170854$9498 assign { } { } assign $0\sr_op__imm_data__data$4[63:0]$9499 \sr_op__imm_data__data$4$next sync posedge \coresync_clk update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9499 end - attribute \src "libresoc.v:171060.3-171061.61" - process $proc$libresoc.v:171060$9500 + attribute \src "libresoc.v:170856.3-170857.61" + process $proc$libresoc.v:170856$9500 assign { } { } assign $0\sr_op__imm_data__ok$5[0:0]$9501 \sr_op__imm_data__ok$5$next sync posedge \coresync_clk update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9501 end - attribute \src "libresoc.v:171062.3-171063.49" - process $proc$libresoc.v:171062$9502 + attribute \src "libresoc.v:170858.3-170859.49" + process $proc$libresoc.v:170858$9502 assign { } { } assign $0\sr_op__rc__rc$6[0:0]$9503 \sr_op__rc__rc$6$next sync posedge \coresync_clk update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9503 end - attribute \src "libresoc.v:171064.3-171065.49" - process $proc$libresoc.v:171064$9504 + attribute \src "libresoc.v:170860.3-170861.49" + process $proc$libresoc.v:170860$9504 assign { } { } assign $0\sr_op__rc__ok$7[0:0]$9505 \sr_op__rc__ok$7$next sync posedge \coresync_clk update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9505 end - attribute \src "libresoc.v:171066.3-171067.49" - process $proc$libresoc.v:171066$9506 + attribute \src "libresoc.v:170862.3-170863.49" + process $proc$libresoc.v:170862$9506 assign { } { } assign $0\sr_op__oe__oe$8[0:0]$9507 \sr_op__oe__oe$8$next sync posedge \coresync_clk update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9507 end - attribute \src "libresoc.v:171068.3-171069.49" - process $proc$libresoc.v:171068$9508 + attribute \src "libresoc.v:170864.3-170865.49" + process $proc$libresoc.v:170864$9508 assign { } { } assign $0\sr_op__oe__ok$9[0:0]$9509 \sr_op__oe__ok$9$next sync posedge \coresync_clk update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9509 end - attribute \src "libresoc.v:171070.3-171071.57" - process $proc$libresoc.v:171070$9510 + attribute \src "libresoc.v:170866.3-170867.57" + process $proc$libresoc.v:170866$9510 assign { } { } assign $0\sr_op__write_cr0$10[0:0]$9511 \sr_op__write_cr0$10$next sync posedge \coresync_clk update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9511 end - attribute \src "libresoc.v:171072.3-171073.57" - process $proc$libresoc.v:171072$9512 + attribute \src "libresoc.v:170868.3-170869.57" + process $proc$libresoc.v:170868$9512 assign { } { } assign $0\sr_op__invert_in$11[0:0]$9513 \sr_op__invert_in$11$next sync posedge \coresync_clk update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9513 end - attribute \src "libresoc.v:171074.3-171075.61" - process $proc$libresoc.v:171074$9514 + attribute \src "libresoc.v:170870.3-170871.61" + process $proc$libresoc.v:170870$9514 assign { } { } assign $0\sr_op__input_carry$12[1:0]$9515 \sr_op__input_carry$12$next sync posedge \coresync_clk update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9515 end - attribute \src "libresoc.v:171076.3-171077.63" - process $proc$libresoc.v:171076$9516 + attribute \src "libresoc.v:170872.3-170873.63" + process $proc$libresoc.v:170872$9516 assign { } { } assign $0\sr_op__output_carry$13[0:0]$9517 \sr_op__output_carry$13$next sync posedge \coresync_clk update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9517 end - attribute \src "libresoc.v:171078.3-171079.55" - process $proc$libresoc.v:171078$9518 + attribute \src "libresoc.v:170874.3-170875.55" + process $proc$libresoc.v:170874$9518 assign { } { } assign $0\sr_op__input_cr$14[0:0]$9519 \sr_op__input_cr$14$next sync posedge \coresync_clk update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9519 end - attribute \src "libresoc.v:171080.3-171081.57" - process $proc$libresoc.v:171080$9520 + attribute \src "libresoc.v:170876.3-170877.57" + process $proc$libresoc.v:170876$9520 assign { } { } assign $0\sr_op__output_cr$15[0:0]$9521 \sr_op__output_cr$15$next sync posedge \coresync_clk update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9521 end - attribute \src "libresoc.v:171082.3-171083.55" - process $proc$libresoc.v:171082$9522 + attribute \src "libresoc.v:170878.3-170879.55" + process $proc$libresoc.v:170878$9522 assign { } { } assign $0\sr_op__is_32bit$16[0:0]$9523 \sr_op__is_32bit$16$next sync posedge \coresync_clk update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9523 end - attribute \src "libresoc.v:171084.3-171085.57" - process $proc$libresoc.v:171084$9524 + attribute \src "libresoc.v:170880.3-170881.57" + process $proc$libresoc.v:170880$9524 assign { } { } assign $0\sr_op__is_signed$17[0:0]$9525 \sr_op__is_signed$17$next sync posedge \coresync_clk update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9525 end - attribute \src "libresoc.v:171086.3-171087.47" - process $proc$libresoc.v:171086$9526 + attribute \src "libresoc.v:170882.3-170883.47" + process $proc$libresoc.v:170882$9526 assign { } { } assign $0\sr_op__insn$18[31:0]$9527 \sr_op__insn$18$next sync posedge \coresync_clk update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9527 end - attribute \src "libresoc.v:171088.3-171089.33" - process $proc$libresoc.v:171088$9528 + attribute \src "libresoc.v:170884.3-170885.33" + process $proc$libresoc.v:170884$9528 assign { } { } assign $0\muxid$1[1:0]$9529 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9529 end - attribute \src "libresoc.v:171090.3-171091.29" - process $proc$libresoc.v:171090$9530 + attribute \src "libresoc.v:170886.3-170887.29" + process $proc$libresoc.v:170886$9530 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:171149.3-171166.6" - process $proc$libresoc.v:171149$9531 + attribute \src "libresoc.v:170945.3-170962.6" + process $proc$libresoc.v:170945$9531 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9532 $2\r_busy$next[0:0]$9534 - attribute \src "libresoc.v:171150.5-171150.29" + attribute \src "libresoc.v:170946.5-170946.29" switch \initial - attribute \src "libresoc.v:171150.9-171150.17" + attribute \src "libresoc.v:170946.9-170946.17" case 1'1 case end @@ -316589,14 +316423,14 @@ module \pipe2$115 sync always update \r_busy$next $0\r_busy$next[0:0]$9532 end - attribute \src "libresoc.v:171167.3-171179.6" - process $proc$libresoc.v:171167$9535 + attribute \src "libresoc.v:170963.3-170975.6" + process $proc$libresoc.v:170963$9535 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9536 $1\muxid$1$next[1:0]$9537 - attribute \src "libresoc.v:171168.5-171168.29" + attribute \src "libresoc.v:170964.5-170964.29" switch \initial - attribute \src "libresoc.v:171168.9-171168.17" + attribute \src "libresoc.v:170964.9-170964.17" case 1'1 case end @@ -316616,8 +316450,8 @@ module \pipe2$115 sync always update \muxid$1$next $0\muxid$1$next[1:0]$9536 end - attribute \src "libresoc.v:171180.3-171220.6" - process $proc$libresoc.v:171180$9538 + attribute \src "libresoc.v:170976.3-171016.6" + process $proc$libresoc.v:170976$9538 assign { } { } assign { } { } assign { } { } @@ -316675,9 +316509,9 @@ module \pipe2$115 assign $0\sr_op__oe__ok$9$next[0:0]$9550 $2\sr_op__oe__ok$9$next[0:0]$9576 assign $0\sr_op__rc__ok$7$next[0:0]$9553 $2\sr_op__rc__ok$7$next[0:0]$9577 assign $0\sr_op__rc__rc$6$next[0:0]$9554 $2\sr_op__rc__rc$6$next[0:0]$9578 - attribute \src "libresoc.v:171181.5-171181.29" + attribute \src "libresoc.v:170977.5-170977.29" switch \initial - attribute \src "libresoc.v:171181.9-171181.17" + attribute \src "libresoc.v:170977.9-170977.17" case 1'1 case end @@ -316785,8 +316619,8 @@ module \pipe2$115 update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9554 update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9555 end - attribute \src "libresoc.v:171221.3-171239.6" - process $proc$libresoc.v:171221$9579 + attribute \src "libresoc.v:171017.3-171035.6" + process $proc$libresoc.v:171017$9579 assign { } { } assign { } { } assign { } { } @@ -316794,9 +316628,9 @@ module \pipe2$115 assign $0\o$19$next[63:0]$9580 $1\o$19$next[63:0]$9582 assign { } { } assign $0\o_ok$20$next[0:0]$9581 $2\o_ok$20$next[0:0]$9584 - attribute \src "libresoc.v:171222.5-171222.29" + attribute \src "libresoc.v:171018.5-171018.29" switch \initial - attribute \src "libresoc.v:171222.9-171222.17" + attribute \src "libresoc.v:171018.9-171018.17" case 1'1 case end @@ -316829,8 +316663,8 @@ module \pipe2$115 update \o$19$next $0\o$19$next[63:0]$9580 update \o_ok$20$next $0\o_ok$20$next[0:0]$9581 end - attribute \src "libresoc.v:171240.3-171258.6" - process $proc$libresoc.v:171240$9585 + attribute \src "libresoc.v:171036.3-171054.6" + process $proc$libresoc.v:171036$9585 assign { } { } assign { } { } assign { } { } @@ -316838,9 +316672,9 @@ module \pipe2$115 assign $0\cr_a$21$next[3:0]$9586 $1\cr_a$21$next[3:0]$9588 assign { } { } assign $0\cr_a_ok$22$next[0:0]$9587 $2\cr_a_ok$22$next[0:0]$9590 - attribute \src "libresoc.v:171241.5-171241.29" + attribute \src "libresoc.v:171037.5-171037.29" switch \initial - attribute \src "libresoc.v:171241.9-171241.17" + attribute \src "libresoc.v:171037.9-171037.17" case 1'1 case end @@ -316873,8 +316707,8 @@ module \pipe2$115 update \cr_a$21$next $0\cr_a$21$next[3:0]$9586 update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9587 end - attribute \src "libresoc.v:171259.3-171277.6" - process $proc$libresoc.v:171259$9591 + attribute \src "libresoc.v:171055.3-171073.6" + process $proc$libresoc.v:171055$9591 assign { } { } assign { } { } assign { } { } @@ -316882,9 +316716,9 @@ module \pipe2$115 assign $0\xer_ca$23$next[1:0]$9592 $1\xer_ca$23$next[1:0]$9594 assign { } { } assign $0\xer_ca_ok$24$next[0:0]$9593 $2\xer_ca_ok$24$next[0:0]$9596 - attribute \src "libresoc.v:171260.5-171260.29" + attribute \src "libresoc.v:171056.5-171056.29" switch \initial - attribute \src "libresoc.v:171260.9-171260.17" + attribute \src "libresoc.v:171056.9-171056.17" case 1'1 case end @@ -316917,7 +316751,7 @@ module \pipe2$115 update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9592 update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9593 end - connect \$51 $and$libresoc.v:171041$9481_Y + connect \$51 $and$libresoc.v:170837$9481_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } @@ -316935,200 +316769,200 @@ module \pipe2$115 connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:171298.1-172262.10" +attribute \src "libresoc.v:171094.1-172058.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" attribute \generator "nMigen" module \pipe2$35 - attribute \src "libresoc.v:172168.3-172186.6" + attribute \src "libresoc.v:171964.3-171982.6" wire width 64 $0\fast1$11$next[63:0]$9715 - attribute \src "libresoc.v:172045.3-172046.35" + attribute \src "libresoc.v:171841.3-171842.35" wire width 64 $0\fast1$11[63:0]$9677 - attribute \src "libresoc.v:171310.14-171310.47" + attribute \src "libresoc.v:171106.14-171106.47" wire width 64 $0\fast1$11[63:0]$9739 - attribute \src "libresoc.v:172168.3-172186.6" + attribute \src "libresoc.v:171964.3-171982.6" wire $0\fast1_ok$next[0:0]$9714 - attribute \src "libresoc.v:172047.3-172048.33" + attribute \src "libresoc.v:171843.3-171844.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:172187.3-172205.6" + attribute \src "libresoc.v:171983.3-172001.6" wire width 64 $0\fast2$12$next[63:0]$9721 - attribute \src "libresoc.v:172041.3-172042.35" + attribute \src "libresoc.v:171837.3-171838.35" wire width 64 $0\fast2$12[63:0]$9674 - attribute \src "libresoc.v:171326.14-171326.47" + attribute \src "libresoc.v:171122.14-171122.47" wire width 64 $0\fast2$12[63:0]$9742 - attribute \src "libresoc.v:172187.3-172205.6" + attribute \src "libresoc.v:171983.3-172001.6" wire $0\fast2_ok$next[0:0]$9720 - attribute \src "libresoc.v:172043.3-172044.33" + attribute \src "libresoc.v:171839.3-171840.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:171299.7-171299.20" + attribute \src "libresoc.v:171095.7-171095.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172225.3-172243.6" + attribute \src "libresoc.v:172021.3-172039.6" wire width 64 $0\msr$next[63:0]$9732 - attribute \src "libresoc.v:172033.3-172034.23" + attribute \src "libresoc.v:171829.3-171830.23" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:172225.3-172243.6" + attribute \src "libresoc.v:172021.3-172039.6" wire $0\msr_ok$next[0:0]$9733 - attribute \src "libresoc.v:172035.3-172036.29" + attribute \src "libresoc.v:171831.3-171832.29" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:172115.3-172127.6" + attribute \src "libresoc.v:171911.3-171923.6" wire width 2 $0\muxid$1$next[1:0]$9686 - attribute \src "libresoc.v:172029.3-172030.33" + attribute \src "libresoc.v:171825.3-171826.33" wire width 2 $0\muxid$1[1:0]$9667 - attribute \src "libresoc.v:171604.13-171604.29" + attribute \src "libresoc.v:171400.13-171400.29" wire width 2 $0\muxid$1[1:0]$9747 - attribute \src "libresoc.v:172206.3-172224.6" + attribute \src "libresoc.v:172002.3-172020.6" wire width 64 $0\nia$next[63:0]$9726 - attribute \src "libresoc.v:172037.3-172038.23" + attribute \src "libresoc.v:171833.3-171834.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:172206.3-172224.6" + attribute \src "libresoc.v:172002.3-172020.6" wire $0\nia_ok$next[0:0]$9727 - attribute \src "libresoc.v:172039.3-172040.29" + attribute \src "libresoc.v:171835.3-171836.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:172149.3-172167.6" + attribute \src "libresoc.v:171945.3-171963.6" wire width 64 $0\o$next[63:0]$9708 - attribute \src "libresoc.v:172049.3-172050.19" + attribute \src "libresoc.v:171845.3-171846.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:172149.3-172167.6" + attribute \src "libresoc.v:171945.3-171963.6" wire $0\o_ok$next[0:0]$9709 - attribute \src "libresoc.v:172051.3-172052.25" + attribute \src "libresoc.v:171847.3-171848.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:172097.3-172114.6" + attribute \src "libresoc.v:171893.3-171910.6" wire $0\r_busy$next[0:0]$9682 - attribute \src "libresoc.v:172031.3-172032.29" + attribute \src "libresoc.v:171827.3-171828.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 64 $0\trap_op__cia$6$next[63:0]$9689 - attribute \src "libresoc.v:172019.3-172020.47" + attribute \src "libresoc.v:171815.3-171816.47" wire width 64 $0\trap_op__cia$6[63:0]$9657 - attribute \src "libresoc.v:171665.14-171665.53" + attribute \src "libresoc.v:171461.14-171461.53" wire width 64 $0\trap_op__cia$6[63:0]$9754 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9690 - attribute \src "libresoc.v:172013.3-172014.55" + attribute \src "libresoc.v:171809.3-171810.55" wire width 14 $0\trap_op__fn_unit$3[13:0]$9651 - attribute \src "libresoc.v:171702.14-171702.45" + attribute \src "libresoc.v:171498.14-171498.45" wire width 14 $0\trap_op__fn_unit$3[13:0]$9756 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 32 $0\trap_op__insn$4$next[31:0]$9691 - attribute \src "libresoc.v:172015.3-172016.49" + attribute \src "libresoc.v:171811.3-171812.49" wire width 32 $0\trap_op__insn$4[31:0]$9653 - attribute \src "libresoc.v:171728.14-171728.39" + attribute \src "libresoc.v:171524.14-171524.39" wire width 32 $0\trap_op__insn$4[31:0]$9758 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 7 $0\trap_op__insn_type$2$next[6:0]$9692 - attribute \src "libresoc.v:172011.3-172012.59" + attribute \src "libresoc.v:171807.3-171808.59" wire width 7 $0\trap_op__insn_type$2[6:0]$9649 - attribute \src "libresoc.v:171885.13-171885.43" + attribute \src "libresoc.v:171681.13-171681.43" wire width 7 $0\trap_op__insn_type$2[6:0]$9760 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire $0\trap_op__is_32bit$7$next[0:0]$9693 - attribute \src "libresoc.v:172021.3-172022.57" + attribute \src "libresoc.v:171817.3-171818.57" wire $0\trap_op__is_32bit$7[0:0]$9659 - attribute \src "libresoc.v:171971.7-171971.35" + attribute \src "libresoc.v:171767.7-171767.35" wire $0\trap_op__is_32bit$7[0:0]$9762 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9694 - attribute \src "libresoc.v:172027.3-172028.59" + attribute \src "libresoc.v:171823.3-171824.59" wire width 8 $0\trap_op__ldst_exc$10[7:0]$9665 - attribute \src "libresoc.v:171978.13-171978.43" + attribute \src "libresoc.v:171774.13-171774.43" wire width 8 $0\trap_op__ldst_exc$10[7:0]$9764 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 64 $0\trap_op__msr$5$next[63:0]$9695 - attribute \src "libresoc.v:172017.3-172018.47" + attribute \src "libresoc.v:171813.3-171814.47" wire width 64 $0\trap_op__msr$5[63:0]$9655 - attribute \src "libresoc.v:171989.14-171989.53" + attribute \src "libresoc.v:171785.14-171785.53" wire width 64 $0\trap_op__msr$5[63:0]$9766 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9696 - attribute \src "libresoc.v:172025.3-172026.57" + attribute \src "libresoc.v:171821.3-171822.57" wire width 13 $0\trap_op__trapaddr$9[12:0]$9663 - attribute \src "libresoc.v:171998.14-171998.46" + attribute \src "libresoc.v:171794.14-171794.46" wire width 13 $0\trap_op__trapaddr$9[12:0]$9768 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 8 $0\trap_op__traptype$8$next[7:0]$9697 - attribute \src "libresoc.v:172023.3-172024.57" + attribute \src "libresoc.v:171819.3-171820.57" wire width 8 $0\trap_op__traptype$8[7:0]$9661 - attribute \src "libresoc.v:172007.13-172007.42" + attribute \src "libresoc.v:171803.13-171803.42" wire width 8 $0\trap_op__traptype$8[7:0]$9770 - attribute \src "libresoc.v:172168.3-172186.6" + attribute \src "libresoc.v:171964.3-171982.6" wire width 64 $1\fast1$11$next[63:0]$9717 - attribute \src "libresoc.v:172168.3-172186.6" + attribute \src "libresoc.v:171964.3-171982.6" wire $1\fast1_ok$next[0:0]$9716 - attribute \src "libresoc.v:171317.7-171317.22" + attribute \src "libresoc.v:171113.7-171113.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:172187.3-172205.6" + attribute \src "libresoc.v:171983.3-172001.6" wire width 64 $1\fast2$12$next[63:0]$9723 - attribute \src "libresoc.v:172187.3-172205.6" + attribute \src "libresoc.v:171983.3-172001.6" wire $1\fast2_ok$next[0:0]$9722 - attribute \src "libresoc.v:171333.7-171333.22" + attribute \src "libresoc.v:171129.7-171129.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:172225.3-172243.6" + attribute \src "libresoc.v:172021.3-172039.6" wire width 64 $1\msr$next[63:0]$9734 - attribute \src "libresoc.v:171588.14-171588.40" + attribute \src "libresoc.v:171384.14-171384.40" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:172225.3-172243.6" + attribute \src "libresoc.v:172021.3-172039.6" wire $1\msr_ok$next[0:0]$9735 - attribute \src "libresoc.v:171595.7-171595.20" + attribute \src "libresoc.v:171391.7-171391.20" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:172115.3-172127.6" + attribute \src "libresoc.v:171911.3-171923.6" wire width 2 $1\muxid$1$next[1:0]$9687 - attribute \src "libresoc.v:172206.3-172224.6" + attribute \src "libresoc.v:172002.3-172020.6" wire width 64 $1\nia$next[63:0]$9728 - attribute \src "libresoc.v:171617.14-171617.40" + attribute \src "libresoc.v:171413.14-171413.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:172206.3-172224.6" + attribute \src "libresoc.v:172002.3-172020.6" wire $1\nia_ok$next[0:0]$9729 - attribute \src "libresoc.v:171624.7-171624.20" + attribute \src "libresoc.v:171420.7-171420.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:172149.3-172167.6" + attribute \src "libresoc.v:171945.3-171963.6" wire width 64 $1\o$next[63:0]$9710 - attribute \src "libresoc.v:171631.14-171631.38" + attribute \src "libresoc.v:171427.14-171427.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:172149.3-172167.6" + attribute \src "libresoc.v:171945.3-171963.6" wire $1\o_ok$next[0:0]$9711 - attribute \src "libresoc.v:171638.7-171638.18" + attribute \src "libresoc.v:171434.7-171434.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:172097.3-172114.6" + attribute \src "libresoc.v:171893.3-171910.6" wire $1\r_busy$next[0:0]$9683 - attribute \src "libresoc.v:171652.7-171652.20" + attribute \src "libresoc.v:171448.7-171448.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 64 $1\trap_op__cia$6$next[63:0]$9698 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9699 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 32 $1\trap_op__insn$4$next[31:0]$9700 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 7 $1\trap_op__insn_type$2$next[6:0]$9701 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire $1\trap_op__is_32bit$7$next[0:0]$9702 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9703 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 64 $1\trap_op__msr$5$next[63:0]$9704 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9705 - attribute \src "libresoc.v:172128.3-172148.6" + attribute \src "libresoc.v:171924.3-171944.6" wire width 8 $1\trap_op__traptype$8$next[7:0]$9706 - attribute \src "libresoc.v:172168.3-172186.6" + attribute \src "libresoc.v:171964.3-171982.6" wire $2\fast1_ok$next[0:0]$9718 - attribute \src "libresoc.v:172187.3-172205.6" + attribute \src "libresoc.v:171983.3-172001.6" wire $2\fast2_ok$next[0:0]$9724 - attribute \src "libresoc.v:172225.3-172243.6" + attribute \src "libresoc.v:172021.3-172039.6" wire $2\msr_ok$next[0:0]$9736 - attribute \src "libresoc.v:172206.3-172224.6" + attribute \src "libresoc.v:172002.3-172020.6" wire $2\nia_ok$next[0:0]$9730 - attribute \src "libresoc.v:172149.3-172167.6" + attribute \src "libresoc.v:171945.3-171963.6" wire $2\o_ok$next[0:0]$9712 - attribute \src "libresoc.v:172097.3-172114.6" + attribute \src "libresoc.v:171893.3-171910.6" wire $2\r_busy$next[0:0]$9684 - attribute \src "libresoc.v:172010.18-172010.118" - wire $and$libresoc.v:172010$9647_Y + attribute \src "libresoc.v:171806.18-171806.118" + wire $and$libresoc.v:171806$9647_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 16 \fast1 @@ -317158,7 +316992,7 @@ module \pipe2$35 wire \fast2_ok$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast2_ok$next - attribute \src "libresoc.v:171299.7-171299.15" + attribute \src "libresoc.v:171095.7-171095.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast1 @@ -317817,7 +317651,7 @@ module \pipe2$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$8$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:172010$9647 + cell $and $and$libresoc.v:171806$9647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317825,10 +317659,10 @@ module \pipe2$35 parameter \Y_WIDTH 1 connect \A \p_valid_i$25 connect \B \p_ready_o - connect \Y $and$libresoc.v:172010$9647_Y + connect \Y $and$libresoc.v:171806$9647_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:172053.13-172088.4" + attribute \src "libresoc.v:171849.13-171884.4" cell \main$38 \main connect \fast1 \main_fast1 connect \fast1$11 \main_fast1$23 @@ -317866,349 +317700,349 @@ module \pipe2$35 connect \trap_op__traptype$8 \main_trap_op__traptype$20 end attribute \module_not_derived 1 - attribute \src "libresoc.v:172089.10-172092.4" + attribute \src "libresoc.v:171885.10-171888.4" cell \n$37 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:172093.10-172096.4" + attribute \src "libresoc.v:171889.10-171892.4" cell \p$36 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:171299.7-171299.20" - process $proc$libresoc.v:171299$9737 + attribute \src "libresoc.v:171095.7-171095.20" + process $proc$libresoc.v:171095$9737 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171310.14-171310.47" - process $proc$libresoc.v:171310$9738 + attribute \src "libresoc.v:171106.14-171106.47" + process $proc$libresoc.v:171106$9738 assign { } { } assign $0\fast1$11[63:0]$9739 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1$11 $0\fast1$11[63:0]$9739 end - attribute \src "libresoc.v:171317.7-171317.22" - process $proc$libresoc.v:171317$9740 + attribute \src "libresoc.v:171113.7-171113.22" + process $proc$libresoc.v:171113$9740 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:171326.14-171326.47" - process $proc$libresoc.v:171326$9741 + attribute \src "libresoc.v:171122.14-171122.47" + process $proc$libresoc.v:171122$9741 assign { } { } assign $0\fast2$12[63:0]$9742 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2$12 $0\fast2$12[63:0]$9742 end - attribute \src "libresoc.v:171333.7-171333.22" - process $proc$libresoc.v:171333$9743 + attribute \src "libresoc.v:171129.7-171129.22" + process $proc$libresoc.v:171129$9743 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:171588.14-171588.40" - process $proc$libresoc.v:171588$9744 + attribute \src "libresoc.v:171384.14-171384.40" + process $proc$libresoc.v:171384$9744 assign { } { } assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr $1\msr[63:0] end - attribute \src "libresoc.v:171595.7-171595.20" - process $proc$libresoc.v:171595$9745 + attribute \src "libresoc.v:171391.7-171391.20" + process $proc$libresoc.v:171391$9745 assign { } { } assign $1\msr_ok[0:0] 1'0 sync always sync init update \msr_ok $1\msr_ok[0:0] end - attribute \src "libresoc.v:171604.13-171604.29" - process $proc$libresoc.v:171604$9746 + attribute \src "libresoc.v:171400.13-171400.29" + process $proc$libresoc.v:171400$9746 assign { } { } assign $0\muxid$1[1:0]$9747 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$9747 end - attribute \src "libresoc.v:171617.14-171617.40" - process $proc$libresoc.v:171617$9748 + attribute \src "libresoc.v:171413.14-171413.40" + process $proc$libresoc.v:171413$9748 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:171624.7-171624.20" - process $proc$libresoc.v:171624$9749 + attribute \src "libresoc.v:171420.7-171420.20" + process $proc$libresoc.v:171420$9749 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:171631.14-171631.38" - process $proc$libresoc.v:171631$9750 + attribute \src "libresoc.v:171427.14-171427.38" + process $proc$libresoc.v:171427$9750 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:171638.7-171638.18" - process $proc$libresoc.v:171638$9751 + attribute \src "libresoc.v:171434.7-171434.18" + process $proc$libresoc.v:171434$9751 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:171652.7-171652.20" - process $proc$libresoc.v:171652$9752 + attribute \src "libresoc.v:171448.7-171448.20" + process $proc$libresoc.v:171448$9752 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:171665.14-171665.53" - process $proc$libresoc.v:171665$9753 + attribute \src "libresoc.v:171461.14-171461.53" + process $proc$libresoc.v:171461$9753 assign { } { } assign $0\trap_op__cia$6[63:0]$9754 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9754 end - attribute \src "libresoc.v:171702.14-171702.45" - process $proc$libresoc.v:171702$9755 + attribute \src "libresoc.v:171498.14-171498.45" + process $proc$libresoc.v:171498$9755 assign { } { } assign $0\trap_op__fn_unit$3[13:0]$9756 14'00000000000000 sync always sync init update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9756 end - attribute \src "libresoc.v:171728.14-171728.39" - process $proc$libresoc.v:171728$9757 + attribute \src "libresoc.v:171524.14-171524.39" + process $proc$libresoc.v:171524$9757 assign { } { } assign $0\trap_op__insn$4[31:0]$9758 0 sync always sync init update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9758 end - attribute \src "libresoc.v:171885.13-171885.43" - process $proc$libresoc.v:171885$9759 + attribute \src "libresoc.v:171681.13-171681.43" + process $proc$libresoc.v:171681$9759 assign { } { } assign $0\trap_op__insn_type$2[6:0]$9760 7'0000000 sync always sync init update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9760 end - attribute \src "libresoc.v:171971.7-171971.35" - process $proc$libresoc.v:171971$9761 + attribute \src "libresoc.v:171767.7-171767.35" + process $proc$libresoc.v:171767$9761 assign { } { } assign $0\trap_op__is_32bit$7[0:0]$9762 1'0 sync always sync init update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9762 end - attribute \src "libresoc.v:171978.13-171978.43" - process $proc$libresoc.v:171978$9763 + attribute \src "libresoc.v:171774.13-171774.43" + process $proc$libresoc.v:171774$9763 assign { } { } assign $0\trap_op__ldst_exc$10[7:0]$9764 8'00000000 sync always sync init update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9764 end - attribute \src "libresoc.v:171989.14-171989.53" - process $proc$libresoc.v:171989$9765 + attribute \src "libresoc.v:171785.14-171785.53" + process $proc$libresoc.v:171785$9765 assign { } { } assign $0\trap_op__msr$5[63:0]$9766 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9766 end - attribute \src "libresoc.v:171998.14-171998.46" - process $proc$libresoc.v:171998$9767 + attribute \src "libresoc.v:171794.14-171794.46" + process $proc$libresoc.v:171794$9767 assign { } { } assign $0\trap_op__trapaddr$9[12:0]$9768 13'0000000000000 sync always sync init update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9768 end - attribute \src "libresoc.v:172007.13-172007.42" - process $proc$libresoc.v:172007$9769 + attribute \src "libresoc.v:171803.13-171803.42" + process $proc$libresoc.v:171803$9769 assign { } { } assign $0\trap_op__traptype$8[7:0]$9770 8'00000000 sync always sync init update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9770 end - attribute \src "libresoc.v:172011.3-172012.59" - process $proc$libresoc.v:172011$9648 + attribute \src "libresoc.v:171807.3-171808.59" + process $proc$libresoc.v:171807$9648 assign { } { } assign $0\trap_op__insn_type$2[6:0]$9649 \trap_op__insn_type$2$next sync posedge \coresync_clk update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9649 end - attribute \src "libresoc.v:172013.3-172014.55" - process $proc$libresoc.v:172013$9650 + attribute \src "libresoc.v:171809.3-171810.55" + process $proc$libresoc.v:171809$9650 assign { } { } assign $0\trap_op__fn_unit$3[13:0]$9651 \trap_op__fn_unit$3$next sync posedge \coresync_clk update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9651 end - attribute \src "libresoc.v:172015.3-172016.49" - process $proc$libresoc.v:172015$9652 + attribute \src "libresoc.v:171811.3-171812.49" + process $proc$libresoc.v:171811$9652 assign { } { } assign $0\trap_op__insn$4[31:0]$9653 \trap_op__insn$4$next sync posedge \coresync_clk update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9653 end - attribute \src "libresoc.v:172017.3-172018.47" - process $proc$libresoc.v:172017$9654 + attribute \src "libresoc.v:171813.3-171814.47" + process $proc$libresoc.v:171813$9654 assign { } { } assign $0\trap_op__msr$5[63:0]$9655 \trap_op__msr$5$next sync posedge \coresync_clk update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9655 end - attribute \src "libresoc.v:172019.3-172020.47" - process $proc$libresoc.v:172019$9656 + attribute \src "libresoc.v:171815.3-171816.47" + process $proc$libresoc.v:171815$9656 assign { } { } assign $0\trap_op__cia$6[63:0]$9657 \trap_op__cia$6$next sync posedge \coresync_clk update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9657 end - attribute \src "libresoc.v:172021.3-172022.57" - process $proc$libresoc.v:172021$9658 + attribute \src "libresoc.v:171817.3-171818.57" + process $proc$libresoc.v:171817$9658 assign { } { } assign $0\trap_op__is_32bit$7[0:0]$9659 \trap_op__is_32bit$7$next sync posedge \coresync_clk update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9659 end - attribute \src "libresoc.v:172023.3-172024.57" - process $proc$libresoc.v:172023$9660 + attribute \src "libresoc.v:171819.3-171820.57" + process $proc$libresoc.v:171819$9660 assign { } { } assign $0\trap_op__traptype$8[7:0]$9661 \trap_op__traptype$8$next sync posedge \coresync_clk update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9661 end - attribute \src "libresoc.v:172025.3-172026.57" - process $proc$libresoc.v:172025$9662 + attribute \src "libresoc.v:171821.3-171822.57" + process $proc$libresoc.v:171821$9662 assign { } { } assign $0\trap_op__trapaddr$9[12:0]$9663 \trap_op__trapaddr$9$next sync posedge \coresync_clk update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9663 end - attribute \src "libresoc.v:172027.3-172028.59" - process $proc$libresoc.v:172027$9664 + attribute \src "libresoc.v:171823.3-171824.59" + process $proc$libresoc.v:171823$9664 assign { } { } assign $0\trap_op__ldst_exc$10[7:0]$9665 \trap_op__ldst_exc$10$next sync posedge \coresync_clk update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9665 end - attribute \src "libresoc.v:172029.3-172030.33" - process $proc$libresoc.v:172029$9666 + attribute \src "libresoc.v:171825.3-171826.33" + process $proc$libresoc.v:171825$9666 assign { } { } assign $0\muxid$1[1:0]$9667 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9667 end - attribute \src "libresoc.v:172031.3-172032.29" - process $proc$libresoc.v:172031$9668 + attribute \src "libresoc.v:171827.3-171828.29" + process $proc$libresoc.v:171827$9668 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:172033.3-172034.23" - process $proc$libresoc.v:172033$9669 + attribute \src "libresoc.v:171829.3-171830.23" + process $proc$libresoc.v:171829$9669 assign { } { } assign $0\msr[63:0] \msr$next sync posedge \coresync_clk update \msr $0\msr[63:0] end - attribute \src "libresoc.v:172035.3-172036.29" - process $proc$libresoc.v:172035$9670 + attribute \src "libresoc.v:171831.3-171832.29" + process $proc$libresoc.v:171831$9670 assign { } { } assign $0\msr_ok[0:0] \msr_ok$next sync posedge \coresync_clk update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:172037.3-172038.23" - process $proc$libresoc.v:172037$9671 + attribute \src "libresoc.v:171833.3-171834.23" + process $proc$libresoc.v:171833$9671 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:172039.3-172040.29" - process $proc$libresoc.v:172039$9672 + attribute \src "libresoc.v:171835.3-171836.29" + process $proc$libresoc.v:171835$9672 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:172041.3-172042.35" - process $proc$libresoc.v:172041$9673 + attribute \src "libresoc.v:171837.3-171838.35" + process $proc$libresoc.v:171837$9673 assign { } { } assign $0\fast2$12[63:0]$9674 \fast2$12$next sync posedge \coresync_clk update \fast2$12 $0\fast2$12[63:0]$9674 end - attribute \src "libresoc.v:172043.3-172044.33" - process $proc$libresoc.v:172043$9675 + attribute \src "libresoc.v:171839.3-171840.33" + process $proc$libresoc.v:171839$9675 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:172045.3-172046.35" - process $proc$libresoc.v:172045$9676 + attribute \src "libresoc.v:171841.3-171842.35" + process $proc$libresoc.v:171841$9676 assign { } { } assign $0\fast1$11[63:0]$9677 \fast1$11$next sync posedge \coresync_clk update \fast1$11 $0\fast1$11[63:0]$9677 end - attribute \src "libresoc.v:172047.3-172048.33" - process $proc$libresoc.v:172047$9678 + attribute \src "libresoc.v:171843.3-171844.33" + process $proc$libresoc.v:171843$9678 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:172049.3-172050.19" - process $proc$libresoc.v:172049$9679 + attribute \src "libresoc.v:171845.3-171846.19" + process $proc$libresoc.v:171845$9679 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:172051.3-172052.25" - process $proc$libresoc.v:172051$9680 + attribute \src "libresoc.v:171847.3-171848.25" + process $proc$libresoc.v:171847$9680 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:172097.3-172114.6" - process $proc$libresoc.v:172097$9681 + attribute \src "libresoc.v:171893.3-171910.6" + process $proc$libresoc.v:171893$9681 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9682 $2\r_busy$next[0:0]$9684 - attribute \src "libresoc.v:172098.5-172098.29" + attribute \src "libresoc.v:171894.5-171894.29" switch \initial - attribute \src "libresoc.v:172098.9-172098.17" + attribute \src "libresoc.v:171894.9-171894.17" case 1'1 case end @@ -318237,14 +318071,14 @@ module \pipe2$35 sync always update \r_busy$next $0\r_busy$next[0:0]$9682 end - attribute \src "libresoc.v:172115.3-172127.6" - process $proc$libresoc.v:172115$9685 + attribute \src "libresoc.v:171911.3-171923.6" + process $proc$libresoc.v:171911$9685 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9686 $1\muxid$1$next[1:0]$9687 - attribute \src "libresoc.v:172116.5-172116.29" + attribute \src "libresoc.v:171912.5-171912.29" switch \initial - attribute \src "libresoc.v:172116.9-172116.17" + attribute \src "libresoc.v:171912.9-171912.17" case 1'1 case end @@ -318264,8 +318098,8 @@ module \pipe2$35 sync always update \muxid$1$next $0\muxid$1$next[1:0]$9686 end - attribute \src "libresoc.v:172128.3-172148.6" - process $proc$libresoc.v:172128$9688 + attribute \src "libresoc.v:171924.3-171944.6" + process $proc$libresoc.v:171924$9688 assign { } { } assign { } { } assign { } { } @@ -318293,9 +318127,9 @@ module \pipe2$35 assign $0\trap_op__msr$5$next[63:0]$9695 $1\trap_op__msr$5$next[63:0]$9704 assign $0\trap_op__trapaddr$9$next[12:0]$9696 $1\trap_op__trapaddr$9$next[12:0]$9705 assign $0\trap_op__traptype$8$next[7:0]$9697 $1\trap_op__traptype$8$next[7:0]$9706 - attribute \src "libresoc.v:172129.5-172129.29" + attribute \src "libresoc.v:171925.5-171925.29" switch \initial - attribute \src "libresoc.v:172129.9-172129.17" + attribute \src "libresoc.v:171925.9-171925.17" case 1'1 case end @@ -318347,8 +318181,8 @@ module \pipe2$35 update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9696 update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9697 end - attribute \src "libresoc.v:172149.3-172167.6" - process $proc$libresoc.v:172149$9707 + attribute \src "libresoc.v:171945.3-171963.6" + process $proc$libresoc.v:171945$9707 assign { } { } assign { } { } assign { } { } @@ -318356,9 +318190,9 @@ module \pipe2$35 assign $0\o$next[63:0]$9708 $1\o$next[63:0]$9710 assign { } { } assign $0\o_ok$next[0:0]$9709 $2\o_ok$next[0:0]$9712 - attribute \src "libresoc.v:172150.5-172150.29" + attribute \src "libresoc.v:171946.5-171946.29" switch \initial - attribute \src "libresoc.v:172150.9-172150.17" + attribute \src "libresoc.v:171946.9-171946.17" case 1'1 case end @@ -318391,8 +318225,8 @@ module \pipe2$35 update \o$next $0\o$next[63:0]$9708 update \o_ok$next $0\o_ok$next[0:0]$9709 end - attribute \src "libresoc.v:172168.3-172186.6" - process $proc$libresoc.v:172168$9713 + attribute \src "libresoc.v:171964.3-171982.6" + process $proc$libresoc.v:171964$9713 assign { } { } assign { } { } assign { } { } @@ -318400,9 +318234,9 @@ module \pipe2$35 assign { } { } assign $0\fast1$11$next[63:0]$9715 $1\fast1$11$next[63:0]$9717 assign $0\fast1_ok$next[0:0]$9714 $2\fast1_ok$next[0:0]$9718 - attribute \src "libresoc.v:172169.5-172169.29" + attribute \src "libresoc.v:171965.5-171965.29" switch \initial - attribute \src "libresoc.v:172169.9-172169.17" + attribute \src "libresoc.v:171965.9-171965.17" case 1'1 case end @@ -318435,8 +318269,8 @@ module \pipe2$35 update \fast1_ok$next $0\fast1_ok$next[0:0]$9714 update \fast1$11$next $0\fast1$11$next[63:0]$9715 end - attribute \src "libresoc.v:172187.3-172205.6" - process $proc$libresoc.v:172187$9719 + attribute \src "libresoc.v:171983.3-172001.6" + process $proc$libresoc.v:171983$9719 assign { } { } assign { } { } assign { } { } @@ -318444,9 +318278,9 @@ module \pipe2$35 assign { } { } assign $0\fast2$12$next[63:0]$9721 $1\fast2$12$next[63:0]$9723 assign $0\fast2_ok$next[0:0]$9720 $2\fast2_ok$next[0:0]$9724 - attribute \src "libresoc.v:172188.5-172188.29" + attribute \src "libresoc.v:171984.5-171984.29" switch \initial - attribute \src "libresoc.v:172188.9-172188.17" + attribute \src "libresoc.v:171984.9-171984.17" case 1'1 case end @@ -318479,8 +318313,8 @@ module \pipe2$35 update \fast2_ok$next $0\fast2_ok$next[0:0]$9720 update \fast2$12$next $0\fast2$12$next[63:0]$9721 end - attribute \src "libresoc.v:172206.3-172224.6" - process $proc$libresoc.v:172206$9725 + attribute \src "libresoc.v:172002.3-172020.6" + process $proc$libresoc.v:172002$9725 assign { } { } assign { } { } assign { } { } @@ -318488,9 +318322,9 @@ module \pipe2$35 assign $0\nia$next[63:0]$9726 $1\nia$next[63:0]$9728 assign { } { } assign $0\nia_ok$next[0:0]$9727 $2\nia_ok$next[0:0]$9730 - attribute \src "libresoc.v:172207.5-172207.29" + attribute \src "libresoc.v:172003.5-172003.29" switch \initial - attribute \src "libresoc.v:172207.9-172207.17" + attribute \src "libresoc.v:172003.9-172003.17" case 1'1 case end @@ -318523,8 +318357,8 @@ module \pipe2$35 update \nia$next $0\nia$next[63:0]$9726 update \nia_ok$next $0\nia_ok$next[0:0]$9727 end - attribute \src "libresoc.v:172225.3-172243.6" - process $proc$libresoc.v:172225$9731 + attribute \src "libresoc.v:172021.3-172039.6" + process $proc$libresoc.v:172021$9731 assign { } { } assign { } { } assign { } { } @@ -318532,9 +318366,9 @@ module \pipe2$35 assign $0\msr$next[63:0]$9732 $1\msr$next[63:0]$9734 assign { } { } assign $0\msr_ok$next[0:0]$9733 $2\msr_ok$next[0:0]$9736 - attribute \src "libresoc.v:172226.5-172226.29" + attribute \src "libresoc.v:172022.5-172022.29" switch \initial - attribute \src "libresoc.v:172226.9-172226.17" + attribute \src "libresoc.v:172022.9-172022.17" case 1'1 case end @@ -318567,7 +318401,7 @@ module \pipe2$35 update \msr$next $0\msr$next[63:0]$9732 update \msr_ok$next $0\msr_ok$next[0:0]$9733 end - connect \$26 $and$libresoc.v:172010$9647_Y + connect \$26 $and$libresoc.v:171806$9647_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } @@ -318587,266 +318421,266 @@ module \pipe2$35 connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:172266.1-173769.10" +attribute \src "libresoc.v:172062.1-173565.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" attribute \generator "nMigen" module \pipe_end - attribute \src "libresoc.v:173607.3-173625.6" + attribute \src "libresoc.v:173403.3-173421.6" wire width 4 $0\cr_a$next[3:0]$9827 - attribute \src "libresoc.v:173426.3-173427.25" + attribute \src "libresoc.v:173222.3-173223.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:173607.3-173625.6" + attribute \src "libresoc.v:173403.3-173421.6" wire $0\cr_a_ok$next[0:0]$9828 - attribute \src "libresoc.v:173428.3-173429.31" + attribute \src "libresoc.v:173224.3-173225.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:172267.7-172267.20" + attribute \src "libresoc.v:172063.7-172063.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 4 $0\logical_op__data_len$18$next[3:0]$9852 - attribute \src "libresoc.v:173466.3-173467.65" + attribute \src "libresoc.v:173262.3-173263.65" wire width 4 $0\logical_op__data_len$18[3:0]$9814 - attribute \src "libresoc.v:172308.13-172308.45" + attribute \src "libresoc.v:172104.13-172104.45" wire width 4 $0\logical_op__data_len$18[3:0]$9898 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9853 - attribute \src "libresoc.v:173436.3-173437.61" + attribute \src "libresoc.v:173232.3-173233.61" wire width 14 $0\logical_op__fn_unit$3[13:0]$9784 - attribute \src "libresoc.v:172347.14-172347.48" + attribute \src "libresoc.v:172143.14-172143.48" wire width 14 $0\logical_op__fn_unit$3[13:0]$9900 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9854 - attribute \src "libresoc.v:173438.3-173439.75" + attribute \src "libresoc.v:173234.3-173235.75" wire width 64 $0\logical_op__imm_data__data$4[63:0]$9786 - attribute \src "libresoc.v:172371.14-172371.67" + attribute \src "libresoc.v:172167.14-172167.67" wire width 64 $0\logical_op__imm_data__data$4[63:0]$9902 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__imm_data__ok$5$next[0:0]$9855 - attribute \src "libresoc.v:173440.3-173441.71" + attribute \src "libresoc.v:173236.3-173237.71" wire $0\logical_op__imm_data__ok$5[0:0]$9788 - attribute \src "libresoc.v:172380.7-172380.42" + attribute \src "libresoc.v:172176.7-172176.42" wire $0\logical_op__imm_data__ok$5[0:0]$9904 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 2 $0\logical_op__input_carry$12$next[1:0]$9856 - attribute \src "libresoc.v:173454.3-173455.71" + attribute \src "libresoc.v:173250.3-173251.71" wire width 2 $0\logical_op__input_carry$12[1:0]$9802 - attribute \src "libresoc.v:172397.13-172397.48" + attribute \src "libresoc.v:172193.13-172193.48" wire width 2 $0\logical_op__input_carry$12[1:0]$9906 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 32 $0\logical_op__insn$19$next[31:0]$9857 - attribute \src "libresoc.v:173468.3-173469.57" + attribute \src "libresoc.v:173264.3-173265.57" wire width 32 $0\logical_op__insn$19[31:0]$9816 - attribute \src "libresoc.v:172410.14-172410.43" + attribute \src "libresoc.v:172206.14-172206.43" wire width 32 $0\logical_op__insn$19[31:0]$9908 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 7 $0\logical_op__insn_type$2$next[6:0]$9858 - attribute \src "libresoc.v:173434.3-173435.65" + attribute \src "libresoc.v:173230.3-173231.65" wire width 7 $0\logical_op__insn_type$2[6:0]$9782 - attribute \src "libresoc.v:172569.13-172569.46" + attribute \src "libresoc.v:172365.13-172365.46" wire width 7 $0\logical_op__insn_type$2[6:0]$9910 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__invert_in$10$next[0:0]$9859 - attribute \src "libresoc.v:173450.3-173451.67" + attribute \src "libresoc.v:173246.3-173247.67" wire $0\logical_op__invert_in$10[0:0]$9798 - attribute \src "libresoc.v:172653.7-172653.40" + attribute \src "libresoc.v:172449.7-172449.40" wire $0\logical_op__invert_in$10[0:0]$9912 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__invert_out$13$next[0:0]$9860 - attribute \src "libresoc.v:173456.3-173457.69" + attribute \src "libresoc.v:173252.3-173253.69" wire $0\logical_op__invert_out$13[0:0]$9804 - attribute \src "libresoc.v:172662.7-172662.41" + attribute \src "libresoc.v:172458.7-172458.41" wire $0\logical_op__invert_out$13[0:0]$9914 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__is_32bit$16$next[0:0]$9861 - attribute \src "libresoc.v:173462.3-173463.65" + attribute \src "libresoc.v:173258.3-173259.65" wire $0\logical_op__is_32bit$16[0:0]$9810 - attribute \src "libresoc.v:172671.7-172671.39" + attribute \src "libresoc.v:172467.7-172467.39" wire $0\logical_op__is_32bit$16[0:0]$9916 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__is_signed$17$next[0:0]$9862 - attribute \src "libresoc.v:173464.3-173465.67" + attribute \src "libresoc.v:173260.3-173261.67" wire $0\logical_op__is_signed$17[0:0]$9812 - attribute \src "libresoc.v:172680.7-172680.40" + attribute \src "libresoc.v:172476.7-172476.40" wire $0\logical_op__is_signed$17[0:0]$9918 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__oe__oe$8$next[0:0]$9863 - attribute \src "libresoc.v:173446.3-173447.59" + attribute \src "libresoc.v:173242.3-173243.59" wire $0\logical_op__oe__oe$8[0:0]$9794 - attribute \src "libresoc.v:172689.7-172689.36" + attribute \src "libresoc.v:172485.7-172485.36" wire $0\logical_op__oe__oe$8[0:0]$9920 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__oe__ok$9$next[0:0]$9864 - attribute \src "libresoc.v:173448.3-173449.59" + attribute \src "libresoc.v:173244.3-173245.59" wire $0\logical_op__oe__ok$9[0:0]$9796 - attribute \src "libresoc.v:172700.7-172700.36" + attribute \src "libresoc.v:172496.7-172496.36" wire $0\logical_op__oe__ok$9[0:0]$9922 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__output_carry$15$next[0:0]$9865 - attribute \src "libresoc.v:173460.3-173461.73" + attribute \src "libresoc.v:173256.3-173257.73" wire $0\logical_op__output_carry$15[0:0]$9808 - attribute \src "libresoc.v:172707.7-172707.43" + attribute \src "libresoc.v:172503.7-172503.43" wire $0\logical_op__output_carry$15[0:0]$9924 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__rc__ok$7$next[0:0]$9866 - attribute \src "libresoc.v:173444.3-173445.59" + attribute \src "libresoc.v:173240.3-173241.59" wire $0\logical_op__rc__ok$7[0:0]$9792 - attribute \src "libresoc.v:172716.7-172716.36" + attribute \src "libresoc.v:172512.7-172512.36" wire $0\logical_op__rc__ok$7[0:0]$9926 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__rc__rc$6$next[0:0]$9867 - attribute \src "libresoc.v:173442.3-173443.59" + attribute \src "libresoc.v:173238.3-173239.59" wire $0\logical_op__rc__rc$6[0:0]$9790 - attribute \src "libresoc.v:172725.7-172725.36" + attribute \src "libresoc.v:172521.7-172521.36" wire $0\logical_op__rc__rc$6[0:0]$9928 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__write_cr0$14$next[0:0]$9868 - attribute \src "libresoc.v:173458.3-173459.67" + attribute \src "libresoc.v:173254.3-173255.67" wire $0\logical_op__write_cr0$14[0:0]$9806 - attribute \src "libresoc.v:172734.7-172734.40" + attribute \src "libresoc.v:172530.7-172530.40" wire $0\logical_op__write_cr0$14[0:0]$9930 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__zero_a$11$next[0:0]$9869 - attribute \src "libresoc.v:173452.3-173453.61" + attribute \src "libresoc.v:173248.3-173249.61" wire $0\logical_op__zero_a$11[0:0]$9800 - attribute \src "libresoc.v:172743.7-172743.37" + attribute \src "libresoc.v:172539.7-172539.37" wire $0\logical_op__zero_a$11[0:0]$9932 - attribute \src "libresoc.v:173682.3-173694.6" + attribute \src "libresoc.v:173478.3-173490.6" wire width 2 $0\muxid$1$next[1:0]$9849 - attribute \src "libresoc.v:173470.3-173471.33" + attribute \src "libresoc.v:173266.3-173267.33" wire width 2 $0\muxid$1[1:0]$9818 - attribute \src "libresoc.v:172752.13-172752.29" + attribute \src "libresoc.v:172548.13-172548.29" wire width 2 $0\muxid$1[1:0]$9934 - attribute \src "libresoc.v:173588.3-173606.6" + attribute \src "libresoc.v:173384.3-173402.6" wire width 64 $0\o$next[63:0]$9821 - attribute \src "libresoc.v:173430.3-173431.19" + attribute \src "libresoc.v:173226.3-173227.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:173588.3-173606.6" + attribute \src "libresoc.v:173384.3-173402.6" wire $0\o_ok$next[0:0]$9822 - attribute \src "libresoc.v:173432.3-173433.25" + attribute \src "libresoc.v:173228.3-173229.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:173664.3-173681.6" + attribute \src "libresoc.v:173460.3-173477.6" wire $0\r_busy$next[0:0]$9845 - attribute \src "libresoc.v:173472.3-173473.29" + attribute \src "libresoc.v:173268.3-173269.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:173626.3-173644.6" + attribute \src "libresoc.v:173422.3-173440.6" wire width 2 $0\xer_ov$next[1:0]$9833 - attribute \src "libresoc.v:173422.3-173423.29" + attribute \src "libresoc.v:173218.3-173219.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:173626.3-173644.6" + attribute \src "libresoc.v:173422.3-173440.6" wire $0\xer_ov_ok$next[0:0]$9834 - attribute \src "libresoc.v:173424.3-173425.35" + attribute \src "libresoc.v:173220.3-173221.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:173645.3-173663.6" + attribute \src "libresoc.v:173441.3-173459.6" wire $0\xer_so$20$next[0:0]$9840 - attribute \src "libresoc.v:173418.3-173419.37" + attribute \src "libresoc.v:173214.3-173215.37" wire $0\xer_so$20[0:0]$9773 - attribute \src "libresoc.v:173403.7-173403.25" + attribute \src "libresoc.v:173199.7-173199.25" wire $0\xer_so$20[0:0]$9941 - attribute \src "libresoc.v:173645.3-173663.6" + attribute \src "libresoc.v:173441.3-173459.6" wire $0\xer_so_ok$next[0:0]$9839 - attribute \src "libresoc.v:173420.3-173421.35" + attribute \src "libresoc.v:173216.3-173217.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:173607.3-173625.6" + attribute \src "libresoc.v:173403.3-173421.6" wire width 4 $1\cr_a$next[3:0]$9829 - attribute \src "libresoc.v:172276.13-172276.24" + attribute \src "libresoc.v:172072.13-172072.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:173607.3-173625.6" + attribute \src "libresoc.v:173403.3-173421.6" wire $1\cr_a_ok$next[0:0]$9830 - attribute \src "libresoc.v:172285.7-172285.21" + attribute \src "libresoc.v:172081.7-172081.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 4 $1\logical_op__data_len$18$next[3:0]$9870 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9871 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9872 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__imm_data__ok$5$next[0:0]$9873 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 2 $1\logical_op__input_carry$12$next[1:0]$9874 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 32 $1\logical_op__insn$19$next[31:0]$9875 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 7 $1\logical_op__insn_type$2$next[6:0]$9876 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__invert_in$10$next[0:0]$9877 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__invert_out$13$next[0:0]$9878 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__is_32bit$16$next[0:0]$9879 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__is_signed$17$next[0:0]$9880 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__oe__oe$8$next[0:0]$9881 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__oe__ok$9$next[0:0]$9882 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__output_carry$15$next[0:0]$9883 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__rc__ok$7$next[0:0]$9884 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__rc__rc$6$next[0:0]$9885 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__write_cr0$14$next[0:0]$9886 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__zero_a$11$next[0:0]$9887 - attribute \src "libresoc.v:173682.3-173694.6" + attribute \src "libresoc.v:173478.3-173490.6" wire width 2 $1\muxid$1$next[1:0]$9850 - attribute \src "libresoc.v:173588.3-173606.6" + attribute \src "libresoc.v:173384.3-173402.6" wire width 64 $1\o$next[63:0]$9823 - attribute \src "libresoc.v:172765.14-172765.38" + attribute \src "libresoc.v:172561.14-172561.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:173588.3-173606.6" + attribute \src "libresoc.v:173384.3-173402.6" wire $1\o_ok$next[0:0]$9824 - attribute \src "libresoc.v:172772.7-172772.18" + attribute \src "libresoc.v:172568.7-172568.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:173664.3-173681.6" + attribute \src "libresoc.v:173460.3-173477.6" wire $1\r_busy$next[0:0]$9846 - attribute \src "libresoc.v:173368.7-173368.20" + attribute \src "libresoc.v:173164.7-173164.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:173626.3-173644.6" + attribute \src "libresoc.v:173422.3-173440.6" wire width 2 $1\xer_ov$next[1:0]$9835 - attribute \src "libresoc.v:173383.13-173383.26" + attribute \src "libresoc.v:173179.13-173179.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:173626.3-173644.6" + attribute \src "libresoc.v:173422.3-173440.6" wire $1\xer_ov_ok$next[0:0]$9836 - attribute \src "libresoc.v:173390.7-173390.23" + attribute \src "libresoc.v:173186.7-173186.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:173645.3-173663.6" + attribute \src "libresoc.v:173441.3-173459.6" wire $1\xer_so$20$next[0:0]$9842 - attribute \src "libresoc.v:173645.3-173663.6" + attribute \src "libresoc.v:173441.3-173459.6" wire $1\xer_so_ok$next[0:0]$9841 - attribute \src "libresoc.v:173408.7-173408.23" + attribute \src "libresoc.v:173204.7-173204.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:173607.3-173625.6" + attribute \src "libresoc.v:173403.3-173421.6" wire $2\cr_a_ok$next[0:0]$9831 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9888 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $2\logical_op__imm_data__ok$5$next[0:0]$9889 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $2\logical_op__oe__oe$8$next[0:0]$9890 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $2\logical_op__oe__ok$9$next[0:0]$9891 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $2\logical_op__rc__ok$7$next[0:0]$9892 - attribute \src "libresoc.v:173695.3-173736.6" + attribute \src "libresoc.v:173491.3-173532.6" wire $2\logical_op__rc__rc$6$next[0:0]$9893 - attribute \src "libresoc.v:173588.3-173606.6" + attribute \src "libresoc.v:173384.3-173402.6" wire $2\o_ok$next[0:0]$9825 - attribute \src "libresoc.v:173664.3-173681.6" + attribute \src "libresoc.v:173460.3-173477.6" wire $2\r_busy$next[0:0]$9847 - attribute \src "libresoc.v:173626.3-173644.6" + attribute \src "libresoc.v:173422.3-173440.6" wire $2\xer_ov_ok$next[0:0]$9837 - attribute \src "libresoc.v:173645.3-173663.6" + attribute \src "libresoc.v:173441.3-173459.6" wire $2\xer_so_ok$next[0:0]$9843 - attribute \src "libresoc.v:173417.18-173417.118" - wire $and$libresoc.v:173417$9771_Y + attribute \src "libresoc.v:173213.18-173213.118" + wire $and$libresoc.v:173213$9771_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 62 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 56 \cr_a @@ -318876,7 +318710,7 @@ module \pipe_end wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 26 \divisor_neg - attribute \src "libresoc.v:172267.7-172267.15" + attribute \src "libresoc.v:172063.7-172063.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -319967,7 +319801,7 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:173417$9771 + cell $and $and$libresoc.v:173213$9771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319975,16 +319809,16 @@ module \pipe_end parameter \Y_WIDTH 1 connect \A \p_valid_i$73 connect \B \p_ready_o - connect \Y $and$libresoc.v:173417$9771_Y + connect \Y $and$libresoc.v:173213$9771_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:173474.10-173477.4" + attribute \src "libresoc.v:173270.10-173273.4" cell \n$82 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:173478.15-173530.4" + attribute \src "libresoc.v:173274.15-173326.4" cell \output$83 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$62 @@ -320039,7 +319873,7 @@ module \pipe_end connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:173531.16-173583.4" + attribute \src "libresoc.v:173327.16-173379.4" cell \output_stage \output_stage connect \div_by_zero \output_stage_div_by_zero connect \dive_abs_ov32 \output_stage_dive_abs_ov32 @@ -320094,441 +319928,441 @@ module \pipe_end connect \xer_so$20 \output_stage_xer_so$40 end attribute \module_not_derived 1 - attribute \src "libresoc.v:173584.10-173587.4" + attribute \src "libresoc.v:173380.10-173383.4" cell \p$81 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:172267.7-172267.20" - process $proc$libresoc.v:172267$9894 + attribute \src "libresoc.v:172063.7-172063.20" + process $proc$libresoc.v:172063$9894 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172276.13-172276.24" - process $proc$libresoc.v:172276$9895 + attribute \src "libresoc.v:172072.13-172072.24" + process $proc$libresoc.v:172072$9895 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:172285.7-172285.21" - process $proc$libresoc.v:172285$9896 + attribute \src "libresoc.v:172081.7-172081.21" + process $proc$libresoc.v:172081$9896 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:172308.13-172308.45" - process $proc$libresoc.v:172308$9897 + attribute \src "libresoc.v:172104.13-172104.45" + process $proc$libresoc.v:172104$9897 assign { } { } assign $0\logical_op__data_len$18[3:0]$9898 4'0000 sync always sync init update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9898 end - attribute \src "libresoc.v:172347.14-172347.48" - process $proc$libresoc.v:172347$9899 + attribute \src "libresoc.v:172143.14-172143.48" + process $proc$libresoc.v:172143$9899 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$9900 14'00000000000000 sync always sync init update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9900 end - attribute \src "libresoc.v:172371.14-172371.67" - process $proc$libresoc.v:172371$9901 + attribute \src "libresoc.v:172167.14-172167.67" + process $proc$libresoc.v:172167$9901 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$9902 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9902 end - attribute \src "libresoc.v:172380.7-172380.42" - process $proc$libresoc.v:172380$9903 + attribute \src "libresoc.v:172176.7-172176.42" + process $proc$libresoc.v:172176$9903 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$9904 1'0 sync always sync init update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9904 end - attribute \src "libresoc.v:172397.13-172397.48" - process $proc$libresoc.v:172397$9905 + attribute \src "libresoc.v:172193.13-172193.48" + process $proc$libresoc.v:172193$9905 assign { } { } assign $0\logical_op__input_carry$12[1:0]$9906 2'00 sync always sync init update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9906 end - attribute \src "libresoc.v:172410.14-172410.43" - process $proc$libresoc.v:172410$9907 + attribute \src "libresoc.v:172206.14-172206.43" + process $proc$libresoc.v:172206$9907 assign { } { } assign $0\logical_op__insn$19[31:0]$9908 0 sync always sync init update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9908 end - attribute \src "libresoc.v:172569.13-172569.46" - process $proc$libresoc.v:172569$9909 + attribute \src "libresoc.v:172365.13-172365.46" + process $proc$libresoc.v:172365$9909 assign { } { } assign $0\logical_op__insn_type$2[6:0]$9910 7'0000000 sync always sync init update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9910 end - attribute \src "libresoc.v:172653.7-172653.40" - process $proc$libresoc.v:172653$9911 + attribute \src "libresoc.v:172449.7-172449.40" + process $proc$libresoc.v:172449$9911 assign { } { } assign $0\logical_op__invert_in$10[0:0]$9912 1'0 sync always sync init update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9912 end - attribute \src "libresoc.v:172662.7-172662.41" - process $proc$libresoc.v:172662$9913 + attribute \src "libresoc.v:172458.7-172458.41" + process $proc$libresoc.v:172458$9913 assign { } { } assign $0\logical_op__invert_out$13[0:0]$9914 1'0 sync always sync init update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9914 end - attribute \src "libresoc.v:172671.7-172671.39" - process $proc$libresoc.v:172671$9915 + attribute \src "libresoc.v:172467.7-172467.39" + process $proc$libresoc.v:172467$9915 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$9916 1'0 sync always sync init update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9916 end - attribute \src "libresoc.v:172680.7-172680.40" - process $proc$libresoc.v:172680$9917 + attribute \src "libresoc.v:172476.7-172476.40" + process $proc$libresoc.v:172476$9917 assign { } { } assign $0\logical_op__is_signed$17[0:0]$9918 1'0 sync always sync init update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9918 end - attribute \src "libresoc.v:172689.7-172689.36" - process $proc$libresoc.v:172689$9919 + attribute \src "libresoc.v:172485.7-172485.36" + process $proc$libresoc.v:172485$9919 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$9920 1'0 sync always sync init update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9920 end - attribute \src "libresoc.v:172700.7-172700.36" - process $proc$libresoc.v:172700$9921 + attribute \src "libresoc.v:172496.7-172496.36" + process $proc$libresoc.v:172496$9921 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$9922 1'0 sync always sync init update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9922 end - attribute \src "libresoc.v:172707.7-172707.43" - process $proc$libresoc.v:172707$9923 + attribute \src "libresoc.v:172503.7-172503.43" + process $proc$libresoc.v:172503$9923 assign { } { } assign $0\logical_op__output_carry$15[0:0]$9924 1'0 sync always sync init update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9924 end - attribute \src "libresoc.v:172716.7-172716.36" - process $proc$libresoc.v:172716$9925 + attribute \src "libresoc.v:172512.7-172512.36" + process $proc$libresoc.v:172512$9925 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$9926 1'0 sync always sync init update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9926 end - attribute \src "libresoc.v:172725.7-172725.36" - process $proc$libresoc.v:172725$9927 + attribute \src "libresoc.v:172521.7-172521.36" + process $proc$libresoc.v:172521$9927 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$9928 1'0 sync always sync init update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9928 end - attribute \src "libresoc.v:172734.7-172734.40" - process $proc$libresoc.v:172734$9929 + attribute \src "libresoc.v:172530.7-172530.40" + process $proc$libresoc.v:172530$9929 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$9930 1'0 sync always sync init update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9930 end - attribute \src "libresoc.v:172743.7-172743.37" - process $proc$libresoc.v:172743$9931 + attribute \src "libresoc.v:172539.7-172539.37" + process $proc$libresoc.v:172539$9931 assign { } { } assign $0\logical_op__zero_a$11[0:0]$9932 1'0 sync always sync init update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9932 end - attribute \src "libresoc.v:172752.13-172752.29" - process $proc$libresoc.v:172752$9933 + attribute \src "libresoc.v:172548.13-172548.29" + process $proc$libresoc.v:172548$9933 assign { } { } assign $0\muxid$1[1:0]$9934 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$9934 end - attribute \src "libresoc.v:172765.14-172765.38" - process $proc$libresoc.v:172765$9935 + attribute \src "libresoc.v:172561.14-172561.38" + process $proc$libresoc.v:172561$9935 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:172772.7-172772.18" - process $proc$libresoc.v:172772$9936 + attribute \src "libresoc.v:172568.7-172568.18" + process $proc$libresoc.v:172568$9936 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:173368.7-173368.20" - process $proc$libresoc.v:173368$9937 + attribute \src "libresoc.v:173164.7-173164.20" + process $proc$libresoc.v:173164$9937 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:173383.13-173383.26" - process $proc$libresoc.v:173383$9938 + attribute \src "libresoc.v:173179.13-173179.26" + process $proc$libresoc.v:173179$9938 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:173390.7-173390.23" - process $proc$libresoc.v:173390$9939 + attribute \src "libresoc.v:173186.7-173186.23" + process $proc$libresoc.v:173186$9939 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:173403.7-173403.25" - process $proc$libresoc.v:173403$9940 + attribute \src "libresoc.v:173199.7-173199.25" + process $proc$libresoc.v:173199$9940 assign { } { } assign $0\xer_so$20[0:0]$9941 1'0 sync always sync init update \xer_so$20 $0\xer_so$20[0:0]$9941 end - attribute \src "libresoc.v:173408.7-173408.23" - process $proc$libresoc.v:173408$9942 + attribute \src "libresoc.v:173204.7-173204.23" + process $proc$libresoc.v:173204$9942 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:173418.3-173419.37" - process $proc$libresoc.v:173418$9772 + attribute \src "libresoc.v:173214.3-173215.37" + process $proc$libresoc.v:173214$9772 assign { } { } assign $0\xer_so$20[0:0]$9773 \xer_so$20$next sync posedge \coresync_clk update \xer_so$20 $0\xer_so$20[0:0]$9773 end - attribute \src "libresoc.v:173420.3-173421.35" - process $proc$libresoc.v:173420$9774 + attribute \src "libresoc.v:173216.3-173217.35" + process $proc$libresoc.v:173216$9774 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:173422.3-173423.29" - process $proc$libresoc.v:173422$9775 + attribute \src "libresoc.v:173218.3-173219.29" + process $proc$libresoc.v:173218$9775 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:173424.3-173425.35" - process $proc$libresoc.v:173424$9776 + attribute \src "libresoc.v:173220.3-173221.35" + process $proc$libresoc.v:173220$9776 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:173426.3-173427.25" - process $proc$libresoc.v:173426$9777 + attribute \src "libresoc.v:173222.3-173223.25" + process $proc$libresoc.v:173222$9777 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:173428.3-173429.31" - process $proc$libresoc.v:173428$9778 + attribute \src "libresoc.v:173224.3-173225.31" + process $proc$libresoc.v:173224$9778 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:173430.3-173431.19" - process $proc$libresoc.v:173430$9779 + attribute \src "libresoc.v:173226.3-173227.19" + process $proc$libresoc.v:173226$9779 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:173432.3-173433.25" - process $proc$libresoc.v:173432$9780 + attribute \src "libresoc.v:173228.3-173229.25" + process $proc$libresoc.v:173228$9780 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:173434.3-173435.65" - process $proc$libresoc.v:173434$9781 + attribute \src "libresoc.v:173230.3-173231.65" + process $proc$libresoc.v:173230$9781 assign { } { } assign $0\logical_op__insn_type$2[6:0]$9782 \logical_op__insn_type$2$next sync posedge \coresync_clk update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9782 end - attribute \src "libresoc.v:173436.3-173437.61" - process $proc$libresoc.v:173436$9783 + attribute \src "libresoc.v:173232.3-173233.61" + process $proc$libresoc.v:173232$9783 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$9784 \logical_op__fn_unit$3$next sync posedge \coresync_clk update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9784 end - attribute \src "libresoc.v:173438.3-173439.75" - process $proc$libresoc.v:173438$9785 + attribute \src "libresoc.v:173234.3-173235.75" + process $proc$libresoc.v:173234$9785 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$9786 \logical_op__imm_data__data$4$next sync posedge \coresync_clk update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9786 end - attribute \src "libresoc.v:173440.3-173441.71" - process $proc$libresoc.v:173440$9787 + attribute \src "libresoc.v:173236.3-173237.71" + process $proc$libresoc.v:173236$9787 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$9788 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9788 end - attribute \src "libresoc.v:173442.3-173443.59" - process $proc$libresoc.v:173442$9789 + attribute \src "libresoc.v:173238.3-173239.59" + process $proc$libresoc.v:173238$9789 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$9790 \logical_op__rc__rc$6$next sync posedge \coresync_clk update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9790 end - attribute \src "libresoc.v:173444.3-173445.59" - process $proc$libresoc.v:173444$9791 + attribute \src "libresoc.v:173240.3-173241.59" + process $proc$libresoc.v:173240$9791 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$9792 \logical_op__rc__ok$7$next sync posedge \coresync_clk update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9792 end - attribute \src "libresoc.v:173446.3-173447.59" - process $proc$libresoc.v:173446$9793 + attribute \src "libresoc.v:173242.3-173243.59" + process $proc$libresoc.v:173242$9793 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$9794 \logical_op__oe__oe$8$next sync posedge \coresync_clk update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9794 end - attribute \src "libresoc.v:173448.3-173449.59" - process $proc$libresoc.v:173448$9795 + attribute \src "libresoc.v:173244.3-173245.59" + process $proc$libresoc.v:173244$9795 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$9796 \logical_op__oe__ok$9$next sync posedge \coresync_clk update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9796 end - attribute \src "libresoc.v:173450.3-173451.67" - process $proc$libresoc.v:173450$9797 + attribute \src "libresoc.v:173246.3-173247.67" + process $proc$libresoc.v:173246$9797 assign { } { } assign $0\logical_op__invert_in$10[0:0]$9798 \logical_op__invert_in$10$next sync posedge \coresync_clk update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9798 end - attribute \src "libresoc.v:173452.3-173453.61" - process $proc$libresoc.v:173452$9799 + attribute \src "libresoc.v:173248.3-173249.61" + process $proc$libresoc.v:173248$9799 assign { } { } assign $0\logical_op__zero_a$11[0:0]$9800 \logical_op__zero_a$11$next sync posedge \coresync_clk update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9800 end - attribute \src "libresoc.v:173454.3-173455.71" - process $proc$libresoc.v:173454$9801 + attribute \src "libresoc.v:173250.3-173251.71" + process $proc$libresoc.v:173250$9801 assign { } { } assign $0\logical_op__input_carry$12[1:0]$9802 \logical_op__input_carry$12$next sync posedge \coresync_clk update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9802 end - attribute \src "libresoc.v:173456.3-173457.69" - process $proc$libresoc.v:173456$9803 + attribute \src "libresoc.v:173252.3-173253.69" + process $proc$libresoc.v:173252$9803 assign { } { } assign $0\logical_op__invert_out$13[0:0]$9804 \logical_op__invert_out$13$next sync posedge \coresync_clk update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9804 end - attribute \src "libresoc.v:173458.3-173459.67" - process $proc$libresoc.v:173458$9805 + attribute \src "libresoc.v:173254.3-173255.67" + process $proc$libresoc.v:173254$9805 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$9806 \logical_op__write_cr0$14$next sync posedge \coresync_clk update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9806 end - attribute \src "libresoc.v:173460.3-173461.73" - process $proc$libresoc.v:173460$9807 + attribute \src "libresoc.v:173256.3-173257.73" + process $proc$libresoc.v:173256$9807 assign { } { } assign $0\logical_op__output_carry$15[0:0]$9808 \logical_op__output_carry$15$next sync posedge \coresync_clk update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9808 end - attribute \src "libresoc.v:173462.3-173463.65" - process $proc$libresoc.v:173462$9809 + attribute \src "libresoc.v:173258.3-173259.65" + process $proc$libresoc.v:173258$9809 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$9810 \logical_op__is_32bit$16$next sync posedge \coresync_clk update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9810 end - attribute \src "libresoc.v:173464.3-173465.67" - process $proc$libresoc.v:173464$9811 + attribute \src "libresoc.v:173260.3-173261.67" + process $proc$libresoc.v:173260$9811 assign { } { } assign $0\logical_op__is_signed$17[0:0]$9812 \logical_op__is_signed$17$next sync posedge \coresync_clk update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9812 end - attribute \src "libresoc.v:173466.3-173467.65" - process $proc$libresoc.v:173466$9813 + attribute \src "libresoc.v:173262.3-173263.65" + process $proc$libresoc.v:173262$9813 assign { } { } assign $0\logical_op__data_len$18[3:0]$9814 \logical_op__data_len$18$next sync posedge \coresync_clk update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9814 end - attribute \src "libresoc.v:173468.3-173469.57" - process $proc$libresoc.v:173468$9815 + attribute \src "libresoc.v:173264.3-173265.57" + process $proc$libresoc.v:173264$9815 assign { } { } assign $0\logical_op__insn$19[31:0]$9816 \logical_op__insn$19$next sync posedge \coresync_clk update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9816 end - attribute \src "libresoc.v:173470.3-173471.33" - process $proc$libresoc.v:173470$9817 + attribute \src "libresoc.v:173266.3-173267.33" + process $proc$libresoc.v:173266$9817 assign { } { } assign $0\muxid$1[1:0]$9818 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9818 end - attribute \src "libresoc.v:173472.3-173473.29" - process $proc$libresoc.v:173472$9819 + attribute \src "libresoc.v:173268.3-173269.29" + process $proc$libresoc.v:173268$9819 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:173588.3-173606.6" - process $proc$libresoc.v:173588$9820 + attribute \src "libresoc.v:173384.3-173402.6" + process $proc$libresoc.v:173384$9820 assign { } { } assign { } { } assign { } { } @@ -320536,9 +320370,9 @@ module \pipe_end assign $0\o$next[63:0]$9821 $1\o$next[63:0]$9823 assign { } { } assign $0\o_ok$next[0:0]$9822 $2\o_ok$next[0:0]$9825 - attribute \src "libresoc.v:173589.5-173589.29" + attribute \src "libresoc.v:173385.5-173385.29" switch \initial - attribute \src "libresoc.v:173589.9-173589.17" + attribute \src "libresoc.v:173385.9-173385.17" case 1'1 case end @@ -320571,8 +320405,8 @@ module \pipe_end update \o$next $0\o$next[63:0]$9821 update \o_ok$next $0\o_ok$next[0:0]$9822 end - attribute \src "libresoc.v:173607.3-173625.6" - process $proc$libresoc.v:173607$9826 + attribute \src "libresoc.v:173403.3-173421.6" + process $proc$libresoc.v:173403$9826 assign { } { } assign { } { } assign { } { } @@ -320580,9 +320414,9 @@ module \pipe_end assign $0\cr_a$next[3:0]$9827 $1\cr_a$next[3:0]$9829 assign { } { } assign $0\cr_a_ok$next[0:0]$9828 $2\cr_a_ok$next[0:0]$9831 - attribute \src "libresoc.v:173608.5-173608.29" + attribute \src "libresoc.v:173404.5-173404.29" switch \initial - attribute \src "libresoc.v:173608.9-173608.17" + attribute \src "libresoc.v:173404.9-173404.17" case 1'1 case end @@ -320615,8 +320449,8 @@ module \pipe_end update \cr_a$next $0\cr_a$next[3:0]$9827 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9828 end - attribute \src "libresoc.v:173626.3-173644.6" - process $proc$libresoc.v:173626$9832 + attribute \src "libresoc.v:173422.3-173440.6" + process $proc$libresoc.v:173422$9832 assign { } { } assign { } { } assign { } { } @@ -320624,9 +320458,9 @@ module \pipe_end assign $0\xer_ov$next[1:0]$9833 $1\xer_ov$next[1:0]$9835 assign { } { } assign $0\xer_ov_ok$next[0:0]$9834 $2\xer_ov_ok$next[0:0]$9837 - attribute \src "libresoc.v:173627.5-173627.29" + attribute \src "libresoc.v:173423.5-173423.29" switch \initial - attribute \src "libresoc.v:173627.9-173627.17" + attribute \src "libresoc.v:173423.9-173423.17" case 1'1 case end @@ -320659,8 +320493,8 @@ module \pipe_end update \xer_ov$next $0\xer_ov$next[1:0]$9833 update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9834 end - attribute \src "libresoc.v:173645.3-173663.6" - process $proc$libresoc.v:173645$9838 + attribute \src "libresoc.v:173441.3-173459.6" + process $proc$libresoc.v:173441$9838 assign { } { } assign { } { } assign { } { } @@ -320668,9 +320502,9 @@ module \pipe_end assign { } { } assign $0\xer_so$20$next[0:0]$9840 $1\xer_so$20$next[0:0]$9842 assign $0\xer_so_ok$next[0:0]$9839 $2\xer_so_ok$next[0:0]$9843 - attribute \src "libresoc.v:173646.5-173646.29" + attribute \src "libresoc.v:173442.5-173442.29" switch \initial - attribute \src "libresoc.v:173646.9-173646.17" + attribute \src "libresoc.v:173442.9-173442.17" case 1'1 case end @@ -320703,15 +320537,15 @@ module \pipe_end update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9839 update \xer_so$20$next $0\xer_so$20$next[0:0]$9840 end - attribute \src "libresoc.v:173664.3-173681.6" - process $proc$libresoc.v:173664$9844 + attribute \src "libresoc.v:173460.3-173477.6" + process $proc$libresoc.v:173460$9844 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9845 $2\r_busy$next[0:0]$9847 - attribute \src "libresoc.v:173665.5-173665.29" + attribute \src "libresoc.v:173461.5-173461.29" switch \initial - attribute \src "libresoc.v:173665.9-173665.17" + attribute \src "libresoc.v:173461.9-173461.17" case 1'1 case end @@ -320740,14 +320574,14 @@ module \pipe_end sync always update \r_busy$next $0\r_busy$next[0:0]$9845 end - attribute \src "libresoc.v:173682.3-173694.6" - process $proc$libresoc.v:173682$9848 + attribute \src "libresoc.v:173478.3-173490.6" + process $proc$libresoc.v:173478$9848 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9849 $1\muxid$1$next[1:0]$9850 - attribute \src "libresoc.v:173683.5-173683.29" + attribute \src "libresoc.v:173479.5-173479.29" switch \initial - attribute \src "libresoc.v:173683.9-173683.17" + attribute \src "libresoc.v:173479.9-173479.17" case 1'1 case end @@ -320767,8 +320601,8 @@ module \pipe_end sync always update \muxid$1$next $0\muxid$1$next[1:0]$9849 end - attribute \src "libresoc.v:173695.3-173736.6" - process $proc$libresoc.v:173695$9851 + attribute \src "libresoc.v:173491.3-173532.6" + process $proc$libresoc.v:173491$9851 assign { } { } assign { } { } assign { } { } @@ -320829,9 +320663,9 @@ module \pipe_end assign $0\logical_op__oe__ok$9$next[0:0]$9864 $2\logical_op__oe__ok$9$next[0:0]$9891 assign $0\logical_op__rc__ok$7$next[0:0]$9866 $2\logical_op__rc__ok$7$next[0:0]$9892 assign $0\logical_op__rc__rc$6$next[0:0]$9867 $2\logical_op__rc__rc$6$next[0:0]$9893 - attribute \src "libresoc.v:173696.5-173696.29" + attribute \src "libresoc.v:173492.5-173492.29" switch \initial - attribute \src "libresoc.v:173696.9-173696.17" + attribute \src "libresoc.v:173492.9-173492.17" case 1'1 case end @@ -320943,7 +320777,7 @@ module \pipe_end update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9868 update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9869 end - connect \$74 $and$libresoc.v:173417$9771_Y + connect \$74 $and$libresoc.v:173213$9771_Y connect \cr_a$68 4'0000 connect \cr_a_ok$69 1'0 connect \xer_so_ok$72 1'0 @@ -320977,381 +320811,381 @@ module \pipe_end connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_stage_muxid \muxid end -attribute \src "libresoc.v:173773.1-174760.10" +attribute \src "libresoc.v:173569.1-174556.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" attribute \generator "nMigen" module \pipe_middle_0 - attribute \src "libresoc.v:174685.3-174699.6" + attribute \src "libresoc.v:174481.3-174495.6" wire $0\div_by_zero$54$next[0:0]$10122 - attribute \src "libresoc.v:173796.7-173796.30" + attribute \src "libresoc.v:173592.7-173592.30" wire $0\div_by_zero$54[0:0]$10139 - attribute \src "libresoc.v:174359.3-174360.47" + attribute \src "libresoc.v:174155.3-174156.47" wire $0\div_by_zero$54[0:0]$9957 - attribute \src "libresoc.v:174481.3-174492.6" + attribute \src "libresoc.v:174277.3-174288.6" wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "libresoc.v:174469.3-174480.6" + attribute \src "libresoc.v:174265.3-174276.6" wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:174457.3-174468.6" + attribute \src "libresoc.v:174253.3-174264.6" wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:174655.3-174669.6" + attribute \src "libresoc.v:174451.3-174465.6" wire $0\dive_abs_ov32$52$next[0:0]$10114 - attribute \src "libresoc.v:173820.7-173820.32" + attribute \src "libresoc.v:173616.7-173616.32" wire $0\dive_abs_ov32$52[0:0]$10141 - attribute \src "libresoc.v:174363.3-174364.51" + attribute \src "libresoc.v:174159.3-174160.51" wire $0\dive_abs_ov32$52[0:0]$9961 - attribute \src "libresoc.v:174670.3-174684.6" + attribute \src "libresoc.v:174466.3-174480.6" wire $0\dive_abs_ov64$53$next[0:0]$10118 - attribute \src "libresoc.v:173828.7-173828.32" + attribute \src "libresoc.v:173624.7-173624.32" wire $0\dive_abs_ov64$53[0:0]$10143 - attribute \src "libresoc.v:174361.3-174362.51" + attribute \src "libresoc.v:174157.3-174158.51" wire $0\dive_abs_ov64$53[0:0]$9959 - attribute \src "libresoc.v:174700.3-174714.6" + attribute \src "libresoc.v:174496.3-174510.6" wire width 128 $0\dividend$68$next[127:0]$10126 - attribute \src "libresoc.v:173834.15-173834.68" + attribute \src "libresoc.v:173630.15-173630.68" wire width 128 $0\dividend$68[127:0]$10145 - attribute \src "libresoc.v:174357.3-174358.41" + attribute \src "libresoc.v:174153.3-174154.41" wire width 128 $0\dividend$68[127:0]$9955 - attribute \src "libresoc.v:174640.3-174654.6" + attribute \src "libresoc.v:174436.3-174450.6" wire $0\dividend_neg$51$next[0:0]$10110 - attribute \src "libresoc.v:173842.7-173842.31" + attribute \src "libresoc.v:173638.7-173638.31" wire $0\dividend_neg$51[0:0]$10147 - attribute \src "libresoc.v:174365.3-174366.49" + attribute \src "libresoc.v:174161.3-174162.49" wire $0\dividend_neg$51[0:0]$9963 - attribute \src "libresoc.v:174625.3-174639.6" + attribute \src "libresoc.v:174421.3-174435.6" wire $0\divisor_neg$50$next[0:0]$10106 - attribute \src "libresoc.v:173850.7-173850.30" + attribute \src "libresoc.v:173646.7-173646.30" wire $0\divisor_neg$50[0:0]$10149 - attribute \src "libresoc.v:174367.3-174368.47" + attribute \src "libresoc.v:174163.3-174164.47" wire $0\divisor_neg$50[0:0]$9965 - attribute \src "libresoc.v:174715.3-174729.6" + attribute \src "libresoc.v:174511.3-174525.6" wire width 64 $0\divisor_radicand$65$next[63:0]$10130 - attribute \src "libresoc.v:173856.14-173856.58" + attribute \src "libresoc.v:173652.14-173652.58" wire width 64 $0\divisor_radicand$65[63:0]$10151 - attribute \src "libresoc.v:174355.3-174356.57" + attribute \src "libresoc.v:174151.3-174152.57" wire width 64 $0\divisor_radicand$65[63:0]$9953 - attribute \src "libresoc.v:174493.3-174520.6" + attribute \src "libresoc.v:174289.3-174316.6" wire $0\empty$next[0:0]$10023 - attribute \src "libresoc.v:174413.3-174414.27" + attribute \src "libresoc.v:174209.3-174210.27" wire $0\empty[0:0] - attribute \src "libresoc.v:173774.7-173774.20" + attribute \src "libresoc.v:173570.7-173570.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 4 $0\logical_op__data_len$45$next[3:0]$10033 - attribute \src "libresoc.v:174407.3-174408.65" + attribute \src "libresoc.v:174203.3-174204.65" wire width 4 $0\logical_op__data_len$45[3:0]$10005 - attribute \src "libresoc.v:173868.13-173868.45" + attribute \src "libresoc.v:173664.13-173664.45" wire width 4 $0\logical_op__data_len$45[3:0]$10154 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10034 - attribute \src "libresoc.v:173921.14-173921.49" + attribute \src "libresoc.v:173717.14-173717.49" wire width 14 $0\logical_op__fn_unit$30[13:0]$10156 - attribute \src "libresoc.v:174377.3-174378.63" + attribute \src "libresoc.v:174173.3-174174.63" wire width 14 $0\logical_op__fn_unit$30[13:0]$9975 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10035 - attribute \src "libresoc.v:173927.14-173927.68" + attribute \src "libresoc.v:173723.14-173723.68" wire width 64 $0\logical_op__imm_data__data$31[63:0]$10158 - attribute \src "libresoc.v:174379.3-174380.77" + attribute \src "libresoc.v:174175.3-174176.77" wire width 64 $0\logical_op__imm_data__data$31[63:0]$9977 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__imm_data__ok$32$next[0:0]$10036 - attribute \src "libresoc.v:173935.7-173935.43" + attribute \src "libresoc.v:173731.7-173731.43" wire $0\logical_op__imm_data__ok$32[0:0]$10160 - attribute \src "libresoc.v:174381.3-174382.73" + attribute \src "libresoc.v:174177.3-174178.73" wire $0\logical_op__imm_data__ok$32[0:0]$9979 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 2 $0\logical_op__input_carry$39$next[1:0]$10037 - attribute \src "libresoc.v:173957.13-173957.48" + attribute \src "libresoc.v:173753.13-173753.48" wire width 2 $0\logical_op__input_carry$39[1:0]$10162 - attribute \src "libresoc.v:174395.3-174396.71" + attribute \src "libresoc.v:174191.3-174192.71" wire width 2 $0\logical_op__input_carry$39[1:0]$9993 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 32 $0\logical_op__insn$46$next[31:0]$10038 - attribute \src "libresoc.v:174409.3-174410.57" + attribute \src "libresoc.v:174205.3-174206.57" wire width 32 $0\logical_op__insn$46[31:0]$10007 - attribute \src "libresoc.v:173965.14-173965.43" + attribute \src "libresoc.v:173761.14-173761.43" wire width 32 $0\logical_op__insn$46[31:0]$10164 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 7 $0\logical_op__insn_type$29$next[6:0]$10039 - attribute \src "libresoc.v:174198.13-174198.47" + attribute \src "libresoc.v:173994.13-173994.47" wire width 7 $0\logical_op__insn_type$29[6:0]$10166 - attribute \src "libresoc.v:174375.3-174376.67" + attribute \src "libresoc.v:174171.3-174172.67" wire width 7 $0\logical_op__insn_type$29[6:0]$9973 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__invert_in$37$next[0:0]$10040 - attribute \src "libresoc.v:174206.7-174206.40" + attribute \src "libresoc.v:174002.7-174002.40" wire $0\logical_op__invert_in$37[0:0]$10168 - attribute \src "libresoc.v:174391.3-174392.67" + attribute \src "libresoc.v:174187.3-174188.67" wire $0\logical_op__invert_in$37[0:0]$9989 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__invert_out$40$next[0:0]$10041 - attribute \src "libresoc.v:174214.7-174214.41" + attribute \src "libresoc.v:174010.7-174010.41" wire $0\logical_op__invert_out$40[0:0]$10170 - attribute \src "libresoc.v:174397.3-174398.69" + attribute \src "libresoc.v:174193.3-174194.69" wire $0\logical_op__invert_out$40[0:0]$9995 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__is_32bit$43$next[0:0]$10042 - attribute \src "libresoc.v:174403.3-174404.65" + attribute \src "libresoc.v:174199.3-174200.65" wire $0\logical_op__is_32bit$43[0:0]$10001 - attribute \src "libresoc.v:174222.7-174222.39" + attribute \src "libresoc.v:174018.7-174018.39" wire $0\logical_op__is_32bit$43[0:0]$10172 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__is_signed$44$next[0:0]$10043 - attribute \src "libresoc.v:174405.3-174406.67" + attribute \src "libresoc.v:174201.3-174202.67" wire $0\logical_op__is_signed$44[0:0]$10003 - attribute \src "libresoc.v:174230.7-174230.40" + attribute \src "libresoc.v:174026.7-174026.40" wire $0\logical_op__is_signed$44[0:0]$10174 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__oe__oe$35$next[0:0]$10044 - attribute \src "libresoc.v:174236.7-174236.37" + attribute \src "libresoc.v:174032.7-174032.37" wire $0\logical_op__oe__oe$35[0:0]$10176 - attribute \src "libresoc.v:174387.3-174388.61" + attribute \src "libresoc.v:174183.3-174184.61" wire $0\logical_op__oe__oe$35[0:0]$9985 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__oe__ok$36$next[0:0]$10045 - attribute \src "libresoc.v:174244.7-174244.37" + attribute \src "libresoc.v:174040.7-174040.37" wire $0\logical_op__oe__ok$36[0:0]$10178 - attribute \src "libresoc.v:174389.3-174390.61" + attribute \src "libresoc.v:174185.3-174186.61" wire $0\logical_op__oe__ok$36[0:0]$9987 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__output_carry$42$next[0:0]$10046 - attribute \src "libresoc.v:174254.7-174254.43" + attribute \src "libresoc.v:174050.7-174050.43" wire $0\logical_op__output_carry$42[0:0]$10180 - attribute \src "libresoc.v:174401.3-174402.73" + attribute \src "libresoc.v:174197.3-174198.73" wire $0\logical_op__output_carry$42[0:0]$9999 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__rc__ok$34$next[0:0]$10047 - attribute \src "libresoc.v:174260.7-174260.37" + attribute \src "libresoc.v:174056.7-174056.37" wire $0\logical_op__rc__ok$34[0:0]$10182 - attribute \src "libresoc.v:174385.3-174386.61" + attribute \src "libresoc.v:174181.3-174182.61" wire $0\logical_op__rc__ok$34[0:0]$9983 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__rc__rc$33$next[0:0]$10048 - attribute \src "libresoc.v:174268.7-174268.37" + attribute \src "libresoc.v:174064.7-174064.37" wire $0\logical_op__rc__rc$33[0:0]$10184 - attribute \src "libresoc.v:174383.3-174384.61" + attribute \src "libresoc.v:174179.3-174180.61" wire $0\logical_op__rc__rc$33[0:0]$9981 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__write_cr0$41$next[0:0]$10049 - attribute \src "libresoc.v:174278.7-174278.40" + attribute \src "libresoc.v:174074.7-174074.40" wire $0\logical_op__write_cr0$41[0:0]$10186 - attribute \src "libresoc.v:174399.3-174400.67" + attribute \src "libresoc.v:174195.3-174196.67" wire $0\logical_op__write_cr0$41[0:0]$9997 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__zero_a$38$next[0:0]$10050 - attribute \src "libresoc.v:174286.7-174286.37" + attribute \src "libresoc.v:174082.7-174082.37" wire $0\logical_op__zero_a$38[0:0]$10188 - attribute \src "libresoc.v:174393.3-174394.61" + attribute \src "libresoc.v:174189.3-174190.61" wire $0\logical_op__zero_a$38[0:0]$9991 - attribute \src "libresoc.v:174521.3-174535.6" + attribute \src "libresoc.v:174317.3-174331.6" wire width 2 $0\muxid$28$next[1:0]$10029 - attribute \src "libresoc.v:174411.3-174412.35" + attribute \src "libresoc.v:174207.3-174208.35" wire width 2 $0\muxid$28[1:0]$10009 - attribute \src "libresoc.v:174294.13-174294.30" + attribute \src "libresoc.v:174090.13-174090.30" wire width 2 $0\muxid$28[1:0]$10190 - attribute \src "libresoc.v:174730.3-174744.6" + attribute \src "libresoc.v:174526.3-174540.6" wire width 2 $0\operation$69$next[1:0]$10134 - attribute \src "libresoc.v:174304.13-174304.34" + attribute \src "libresoc.v:174100.13-174100.34" wire width 2 $0\operation$69[1:0]$10192 - attribute \src "libresoc.v:174353.3-174354.43" + attribute \src "libresoc.v:174149.3-174150.43" wire width 2 $0\operation$69[1:0]$9951 - attribute \src "libresoc.v:174580.3-174594.6" + attribute \src "libresoc.v:174376.3-174390.6" wire width 64 $0\ra$47$next[63:0]$10094 - attribute \src "libresoc.v:174318.14-174318.44" + attribute \src "libresoc.v:174114.14-174114.44" wire width 64 $0\ra$47[63:0]$10194 - attribute \src "libresoc.v:174373.3-174374.29" + attribute \src "libresoc.v:174169.3-174170.29" wire width 64 $0\ra$47[63:0]$9971 - attribute \src "libresoc.v:174595.3-174609.6" + attribute \src "libresoc.v:174391.3-174405.6" wire width 64 $0\rb$48$next[63:0]$10098 - attribute \src "libresoc.v:174326.14-174326.44" + attribute \src "libresoc.v:174122.14-174122.44" wire width 64 $0\rb$48[63:0]$10196 - attribute \src "libresoc.v:174371.3-174372.29" + attribute \src "libresoc.v:174167.3-174168.29" wire width 64 $0\rb$48[63:0]$9969 - attribute \src "libresoc.v:174448.3-174456.6" + attribute \src "libresoc.v:174244.3-174252.6" wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10017 - attribute \src "libresoc.v:174415.3-174416.75" + attribute \src "libresoc.v:174211.3-174212.75" wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:174439.3-174447.6" + attribute \src "libresoc.v:174235.3-174243.6" wire width 7 $0\saved_state_q_bits_known$next[6:0]$10014 - attribute \src "libresoc.v:174417.3-174418.65" + attribute \src "libresoc.v:174213.3-174214.65" wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:174610.3-174624.6" + attribute \src "libresoc.v:174406.3-174420.6" wire $0\xer_so$49$next[0:0]$10102 - attribute \src "libresoc.v:174344.7-174344.25" + attribute \src "libresoc.v:174140.7-174140.25" wire $0\xer_so$49[0:0]$10200 - attribute \src "libresoc.v:174369.3-174370.37" + attribute \src "libresoc.v:174165.3-174166.37" wire $0\xer_so$49[0:0]$9967 - attribute \src "libresoc.v:174685.3-174699.6" + attribute \src "libresoc.v:174481.3-174495.6" wire $1\div_by_zero$54$next[0:0]$10123 - attribute \src "libresoc.v:174481.3-174492.6" + attribute \src "libresoc.v:174277.3-174288.6" wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:174469.3-174480.6" + attribute \src "libresoc.v:174265.3-174276.6" wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:174457.3-174468.6" + attribute \src "libresoc.v:174253.3-174264.6" wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:174655.3-174669.6" + attribute \src "libresoc.v:174451.3-174465.6" wire $1\dive_abs_ov32$52$next[0:0]$10115 - attribute \src "libresoc.v:174670.3-174684.6" + attribute \src "libresoc.v:174466.3-174480.6" wire $1\dive_abs_ov64$53$next[0:0]$10119 - attribute \src "libresoc.v:174700.3-174714.6" + attribute \src "libresoc.v:174496.3-174510.6" wire width 128 $1\dividend$68$next[127:0]$10127 - attribute \src "libresoc.v:174640.3-174654.6" + attribute \src "libresoc.v:174436.3-174450.6" wire $1\dividend_neg$51$next[0:0]$10111 - attribute \src "libresoc.v:174625.3-174639.6" + attribute \src "libresoc.v:174421.3-174435.6" wire $1\divisor_neg$50$next[0:0]$10107 - attribute \src "libresoc.v:174715.3-174729.6" + attribute \src "libresoc.v:174511.3-174525.6" wire width 64 $1\divisor_radicand$65$next[63:0]$10131 - attribute \src "libresoc.v:174493.3-174520.6" + attribute \src "libresoc.v:174289.3-174316.6" wire $1\empty$next[0:0]$10024 - attribute \src "libresoc.v:173860.7-173860.19" + attribute \src "libresoc.v:173656.7-173656.19" wire $1\empty[0:0] - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 4 $1\logical_op__data_len$45$next[3:0]$10051 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10052 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10053 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__imm_data__ok$32$next[0:0]$10054 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 2 $1\logical_op__input_carry$39$next[1:0]$10055 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 32 $1\logical_op__insn$46$next[31:0]$10056 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 7 $1\logical_op__insn_type$29$next[6:0]$10057 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__invert_in$37$next[0:0]$10058 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__invert_out$40$next[0:0]$10059 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__is_32bit$43$next[0:0]$10060 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__is_signed$44$next[0:0]$10061 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__oe__oe$35$next[0:0]$10062 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__oe__ok$36$next[0:0]$10063 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__output_carry$42$next[0:0]$10064 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__rc__ok$34$next[0:0]$10065 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__rc__rc$33$next[0:0]$10066 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__write_cr0$41$next[0:0]$10067 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__zero_a$38$next[0:0]$10068 - attribute \src "libresoc.v:174521.3-174535.6" + attribute \src "libresoc.v:174317.3-174331.6" wire width 2 $1\muxid$28$next[1:0]$10030 - attribute \src "libresoc.v:174730.3-174744.6" + attribute \src "libresoc.v:174526.3-174540.6" wire width 2 $1\operation$69$next[1:0]$10135 - attribute \src "libresoc.v:174580.3-174594.6" + attribute \src "libresoc.v:174376.3-174390.6" wire width 64 $1\ra$47$next[63:0]$10095 - attribute \src "libresoc.v:174595.3-174609.6" + attribute \src "libresoc.v:174391.3-174405.6" wire width 64 $1\rb$48$next[63:0]$10099 - attribute \src "libresoc.v:174448.3-174456.6" + attribute \src "libresoc.v:174244.3-174252.6" wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10018 - attribute \src "libresoc.v:174332.15-174332.84" + attribute \src "libresoc.v:174128.15-174128.84" wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:174439.3-174447.6" + attribute \src "libresoc.v:174235.3-174243.6" wire width 7 $1\saved_state_q_bits_known$next[6:0]$10015 - attribute \src "libresoc.v:174336.13-174336.45" + attribute \src "libresoc.v:174132.13-174132.45" wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:174610.3-174624.6" + attribute \src "libresoc.v:174406.3-174420.6" wire $1\xer_so$49$next[0:0]$10103 - attribute \src "libresoc.v:174685.3-174699.6" + attribute \src "libresoc.v:174481.3-174495.6" wire $2\div_by_zero$54$next[0:0]$10124 - attribute \src "libresoc.v:174655.3-174669.6" + attribute \src "libresoc.v:174451.3-174465.6" wire $2\dive_abs_ov32$52$next[0:0]$10116 - attribute \src "libresoc.v:174670.3-174684.6" + attribute \src "libresoc.v:174466.3-174480.6" wire $2\dive_abs_ov64$53$next[0:0]$10120 - attribute \src "libresoc.v:174700.3-174714.6" + attribute \src "libresoc.v:174496.3-174510.6" wire width 128 $2\dividend$68$next[127:0]$10128 - attribute \src "libresoc.v:174640.3-174654.6" + attribute \src "libresoc.v:174436.3-174450.6" wire $2\dividend_neg$51$next[0:0]$10112 - attribute \src "libresoc.v:174625.3-174639.6" + attribute \src "libresoc.v:174421.3-174435.6" wire $2\divisor_neg$50$next[0:0]$10108 - attribute \src "libresoc.v:174715.3-174729.6" + attribute \src "libresoc.v:174511.3-174525.6" wire width 64 $2\divisor_radicand$65$next[63:0]$10132 - attribute \src "libresoc.v:174493.3-174520.6" + attribute \src "libresoc.v:174289.3-174316.6" wire $2\empty$next[0:0]$10025 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 4 $2\logical_op__data_len$45$next[3:0]$10069 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10070 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10071 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__imm_data__ok$32$next[0:0]$10072 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 2 $2\logical_op__input_carry$39$next[1:0]$10073 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 32 $2\logical_op__insn$46$next[31:0]$10074 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 7 $2\logical_op__insn_type$29$next[6:0]$10075 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__invert_in$37$next[0:0]$10076 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__invert_out$40$next[0:0]$10077 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__is_32bit$43$next[0:0]$10078 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__is_signed$44$next[0:0]$10079 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__oe__oe$35$next[0:0]$10080 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__oe__ok$36$next[0:0]$10081 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__output_carry$42$next[0:0]$10082 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__rc__ok$34$next[0:0]$10083 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__rc__rc$33$next[0:0]$10084 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__write_cr0$41$next[0:0]$10085 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__zero_a$38$next[0:0]$10086 - attribute \src "libresoc.v:174521.3-174535.6" + attribute \src "libresoc.v:174317.3-174331.6" wire width 2 $2\muxid$28$next[1:0]$10031 - attribute \src "libresoc.v:174730.3-174744.6" + attribute \src "libresoc.v:174526.3-174540.6" wire width 2 $2\operation$69$next[1:0]$10136 - attribute \src "libresoc.v:174580.3-174594.6" + attribute \src "libresoc.v:174376.3-174390.6" wire width 64 $2\ra$47$next[63:0]$10096 - attribute \src "libresoc.v:174595.3-174609.6" + attribute \src "libresoc.v:174391.3-174405.6" wire width 64 $2\rb$48$next[63:0]$10100 - attribute \src "libresoc.v:174610.3-174624.6" + attribute \src "libresoc.v:174406.3-174420.6" wire $2\xer_so$49$next[0:0]$10104 - attribute \src "libresoc.v:174493.3-174520.6" + attribute \src "libresoc.v:174289.3-174316.6" wire $3\empty$next[0:0]$10026 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10087 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $3\logical_op__imm_data__ok$32$next[0:0]$10088 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $3\logical_op__oe__oe$35$next[0:0]$10089 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $3\logical_op__oe__ok$36$next[0:0]$10090 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $3\logical_op__rc__ok$34$next[0:0]$10091 - attribute \src "libresoc.v:174536.3-174579.6" + attribute \src "libresoc.v:174332.3-174375.6" wire $3\logical_op__rc__rc$33$next[0:0]$10092 - attribute \src "libresoc.v:174493.3-174520.6" + attribute \src "libresoc.v:174289.3-174316.6" wire $4\empty$next[0:0]$10027 - attribute \src "libresoc.v:174351.18-174351.98" - wire $and$libresoc.v:174351$9948_Y - attribute \src "libresoc.v:174352.18-174352.107" - wire $and$libresoc.v:174352$9949_Y - attribute \src "libresoc.v:174348.18-174348.92" - wire width 192 $extend$libresoc.v:174348$9944_Y - attribute \src "libresoc.v:174350.18-174350.119" - wire $ge$libresoc.v:174350$9947_Y - attribute \src "libresoc.v:174349.18-174349.93" - wire $not$libresoc.v:174349$9946_Y - attribute \src "libresoc.v:174348.18-174348.92" - wire width 192 $pos$libresoc.v:174348$9945_Y - attribute \src "libresoc.v:174347.18-174347.138" - wire width 191 $sshl$libresoc.v:174347$9943_Y + attribute \src "libresoc.v:174147.18-174147.98" + wire $and$libresoc.v:174147$9948_Y + attribute \src "libresoc.v:174148.18-174148.107" + wire $and$libresoc.v:174148$9949_Y + attribute \src "libresoc.v:174144.18-174144.92" + wire width 192 $extend$libresoc.v:174144$9944_Y + attribute \src "libresoc.v:174146.18-174146.119" + wire $ge$libresoc.v:174146$9947_Y + attribute \src "libresoc.v:174145.18-174145.93" + wire $not$libresoc.v:174145$9946_Y + attribute \src "libresoc.v:174144.18-174144.92" + wire width 192 $pos$libresoc.v:174144$9945_Y + attribute \src "libresoc.v:174143.18-174143.138" + wire width 191 $sshl$libresoc.v:174143$9943_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" wire width 192 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" @@ -321364,9 +321198,9 @@ module \pipe_middle_0 wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 65 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 30 \div_by_zero @@ -321440,7 +321274,7 @@ module \pipe_middle_0 wire \empty attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" wire \empty$next - attribute \src "libresoc.v:173774.7-173774.15" + attribute \src "libresoc.v:173570.7-173570.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -321927,7 +321761,7 @@ module \pipe_middle_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$49$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $and $and$libresoc.v:174351$9948 + cell $and $and$libresoc.v:174147$9948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321935,10 +321769,10 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:174351$9948_Y + connect \Y $and$libresoc.v:174147$9948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - cell $and $and$libresoc.v:174352$9949 + cell $and $and$libresoc.v:174148$9949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321946,18 +321780,18 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:174352$9949_Y + connect \Y $and$libresoc.v:174148$9949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $extend$libresoc.v:174348$9944 + cell $pos $extend$libresoc.v:174144$9944 parameter \A_SIGNED 0 parameter \A_WIDTH 191 parameter \Y_WIDTH 192 connect \A \$56 - connect \Y $extend$libresoc.v:174348$9944_Y + connect \Y $extend$libresoc.v:174144$9944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:174350$9947 + cell $ge $ge$libresoc.v:174146$9947 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -321965,26 +321799,26 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \saved_state_q_bits_known connect \B 6'111111 - connect \Y $ge$libresoc.v:174350$9947_Y + connect \Y $ge$libresoc.v:174146$9947_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $not $not$libresoc.v:174349$9946 + cell $not $not$libresoc.v:174145$9946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \empty - connect \Y $not$libresoc.v:174349$9946_Y + connect \Y $not$libresoc.v:174145$9946_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $pos$libresoc.v:174348$9945 + cell $pos $pos$libresoc.v:174144$9945 parameter \A_SIGNED 0 parameter \A_WIDTH 192 parameter \Y_WIDTH 192 - connect \A $extend$libresoc.v:174348$9944_Y - connect \Y $pos$libresoc.v:174348$9945_Y + connect \A $extend$libresoc.v:174144$9944_Y + connect \Y $pos$libresoc.v:174144$9945_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $sshl $sshl$libresoc.v:174347$9943 + cell $sshl $sshl$libresoc.v:174143$9943 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -321992,17 +321826,17 @@ module \pipe_middle_0 parameter \Y_WIDTH 191 connect \A \div_state_next_o_dividend_quotient [127:64] connect \B 7'1000000 - connect \Y $sshl$libresoc.v:174347$9943_Y + connect \Y $sshl$libresoc.v:174143$9943_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:174419.18-174423.4" + attribute \src "libresoc.v:174215.18-174219.4" cell \div_state_init \div_state_init connect \dividend \div_state_init_dividend connect \o_dividend_quotient \div_state_init_o_dividend_quotient connect \o_q_bits_known \div_state_init_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:174424.18-174430.4" + attribute \src "libresoc.v:174220.18-174226.4" cell \div_state_next \div_state_next connect \divisor \div_state_next_divisor connect \i_dividend_quotient \div_state_next_i_dividend_quotient @@ -322011,528 +321845,528 @@ module \pipe_middle_0 connect \o_q_bits_known \div_state_next_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:174431.10-174434.4" + attribute \src "libresoc.v:174227.10-174230.4" cell \n$80 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:174435.10-174438.4" + attribute \src "libresoc.v:174231.10-174234.4" cell \p$79 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:173774.7-173774.20" - process $proc$libresoc.v:173774$10137 + attribute \src "libresoc.v:173570.7-173570.20" + process $proc$libresoc.v:173570$10137 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173796.7-173796.30" - process $proc$libresoc.v:173796$10138 + attribute \src "libresoc.v:173592.7-173592.30" + process $proc$libresoc.v:173592$10138 assign { } { } assign $0\div_by_zero$54[0:0]$10139 1'0 sync always sync init update \div_by_zero$54 $0\div_by_zero$54[0:0]$10139 end - attribute \src "libresoc.v:173820.7-173820.32" - process $proc$libresoc.v:173820$10140 + attribute \src "libresoc.v:173616.7-173616.32" + process $proc$libresoc.v:173616$10140 assign { } { } assign $0\dive_abs_ov32$52[0:0]$10141 1'0 sync always sync init update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10141 end - attribute \src "libresoc.v:173828.7-173828.32" - process $proc$libresoc.v:173828$10142 + attribute \src "libresoc.v:173624.7-173624.32" + process $proc$libresoc.v:173624$10142 assign { } { } assign $0\dive_abs_ov64$53[0:0]$10143 1'0 sync always sync init update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10143 end - attribute \src "libresoc.v:173834.15-173834.68" - process $proc$libresoc.v:173834$10144 + attribute \src "libresoc.v:173630.15-173630.68" + process $proc$libresoc.v:173630$10144 assign { } { } assign $0\dividend$68[127:0]$10145 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend$68 $0\dividend$68[127:0]$10145 end - attribute \src "libresoc.v:173842.7-173842.31" - process $proc$libresoc.v:173842$10146 + attribute \src "libresoc.v:173638.7-173638.31" + process $proc$libresoc.v:173638$10146 assign { } { } assign $0\dividend_neg$51[0:0]$10147 1'0 sync always sync init update \dividend_neg$51 $0\dividend_neg$51[0:0]$10147 end - attribute \src "libresoc.v:173850.7-173850.30" - process $proc$libresoc.v:173850$10148 + attribute \src "libresoc.v:173646.7-173646.30" + process $proc$libresoc.v:173646$10148 assign { } { } assign $0\divisor_neg$50[0:0]$10149 1'0 sync always sync init update \divisor_neg$50 $0\divisor_neg$50[0:0]$10149 end - attribute \src "libresoc.v:173856.14-173856.58" - process $proc$libresoc.v:173856$10150 + attribute \src "libresoc.v:173652.14-173652.58" + process $proc$libresoc.v:173652$10150 assign { } { } assign $0\divisor_radicand$65[63:0]$10151 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10151 end - attribute \src "libresoc.v:173860.7-173860.19" - process $proc$libresoc.v:173860$10152 + attribute \src "libresoc.v:173656.7-173656.19" + process $proc$libresoc.v:173656$10152 assign { } { } assign $1\empty[0:0] 1'1 sync always sync init update \empty $1\empty[0:0] end - attribute \src "libresoc.v:173868.13-173868.45" - process $proc$libresoc.v:173868$10153 + attribute \src "libresoc.v:173664.13-173664.45" + process $proc$libresoc.v:173664$10153 assign { } { } assign $0\logical_op__data_len$45[3:0]$10154 4'0000 sync always sync init update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10154 end - attribute \src "libresoc.v:173921.14-173921.49" - process $proc$libresoc.v:173921$10155 + attribute \src "libresoc.v:173717.14-173717.49" + process $proc$libresoc.v:173717$10155 assign { } { } assign $0\logical_op__fn_unit$30[13:0]$10156 14'00000000000000 sync always sync init update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10156 end - attribute \src "libresoc.v:173927.14-173927.68" - process $proc$libresoc.v:173927$10157 + attribute \src "libresoc.v:173723.14-173723.68" + process $proc$libresoc.v:173723$10157 assign { } { } assign $0\logical_op__imm_data__data$31[63:0]$10158 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10158 end - attribute \src "libresoc.v:173935.7-173935.43" - process $proc$libresoc.v:173935$10159 + attribute \src "libresoc.v:173731.7-173731.43" + process $proc$libresoc.v:173731$10159 assign { } { } assign $0\logical_op__imm_data__ok$32[0:0]$10160 1'0 sync always sync init update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10160 end - attribute \src "libresoc.v:173957.13-173957.48" - process $proc$libresoc.v:173957$10161 + attribute \src "libresoc.v:173753.13-173753.48" + process $proc$libresoc.v:173753$10161 assign { } { } assign $0\logical_op__input_carry$39[1:0]$10162 2'00 sync always sync init update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10162 end - attribute \src "libresoc.v:173965.14-173965.43" - process $proc$libresoc.v:173965$10163 + attribute \src "libresoc.v:173761.14-173761.43" + process $proc$libresoc.v:173761$10163 assign { } { } assign $0\logical_op__insn$46[31:0]$10164 0 sync always sync init update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10164 end - attribute \src "libresoc.v:174198.13-174198.47" - process $proc$libresoc.v:174198$10165 + attribute \src "libresoc.v:173994.13-173994.47" + process $proc$libresoc.v:173994$10165 assign { } { } assign $0\logical_op__insn_type$29[6:0]$10166 7'0000000 sync always sync init update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10166 end - attribute \src "libresoc.v:174206.7-174206.40" - process $proc$libresoc.v:174206$10167 + attribute \src "libresoc.v:174002.7-174002.40" + process $proc$libresoc.v:174002$10167 assign { } { } assign $0\logical_op__invert_in$37[0:0]$10168 1'0 sync always sync init update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10168 end - attribute \src "libresoc.v:174214.7-174214.41" - process $proc$libresoc.v:174214$10169 + attribute \src "libresoc.v:174010.7-174010.41" + process $proc$libresoc.v:174010$10169 assign { } { } assign $0\logical_op__invert_out$40[0:0]$10170 1'0 sync always sync init update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10170 end - attribute \src "libresoc.v:174222.7-174222.39" - process $proc$libresoc.v:174222$10171 + attribute \src "libresoc.v:174018.7-174018.39" + process $proc$libresoc.v:174018$10171 assign { } { } assign $0\logical_op__is_32bit$43[0:0]$10172 1'0 sync always sync init update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10172 end - attribute \src "libresoc.v:174230.7-174230.40" - process $proc$libresoc.v:174230$10173 + attribute \src "libresoc.v:174026.7-174026.40" + process $proc$libresoc.v:174026$10173 assign { } { } assign $0\logical_op__is_signed$44[0:0]$10174 1'0 sync always sync init update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10174 end - attribute \src "libresoc.v:174236.7-174236.37" - process $proc$libresoc.v:174236$10175 + attribute \src "libresoc.v:174032.7-174032.37" + process $proc$libresoc.v:174032$10175 assign { } { } assign $0\logical_op__oe__oe$35[0:0]$10176 1'0 sync always sync init update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10176 end - attribute \src "libresoc.v:174244.7-174244.37" - process $proc$libresoc.v:174244$10177 + attribute \src "libresoc.v:174040.7-174040.37" + process $proc$libresoc.v:174040$10177 assign { } { } assign $0\logical_op__oe__ok$36[0:0]$10178 1'0 sync always sync init update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10178 end - attribute \src "libresoc.v:174254.7-174254.43" - process $proc$libresoc.v:174254$10179 + attribute \src "libresoc.v:174050.7-174050.43" + process $proc$libresoc.v:174050$10179 assign { } { } assign $0\logical_op__output_carry$42[0:0]$10180 1'0 sync always sync init update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10180 end - attribute \src "libresoc.v:174260.7-174260.37" - process $proc$libresoc.v:174260$10181 + attribute \src "libresoc.v:174056.7-174056.37" + process $proc$libresoc.v:174056$10181 assign { } { } assign $0\logical_op__rc__ok$34[0:0]$10182 1'0 sync always sync init update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10182 end - attribute \src "libresoc.v:174268.7-174268.37" - process $proc$libresoc.v:174268$10183 + attribute \src "libresoc.v:174064.7-174064.37" + process $proc$libresoc.v:174064$10183 assign { } { } assign $0\logical_op__rc__rc$33[0:0]$10184 1'0 sync always sync init update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10184 end - attribute \src "libresoc.v:174278.7-174278.40" - process $proc$libresoc.v:174278$10185 + attribute \src "libresoc.v:174074.7-174074.40" + process $proc$libresoc.v:174074$10185 assign { } { } assign $0\logical_op__write_cr0$41[0:0]$10186 1'0 sync always sync init update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10186 end - attribute \src "libresoc.v:174286.7-174286.37" - process $proc$libresoc.v:174286$10187 + attribute \src "libresoc.v:174082.7-174082.37" + process $proc$libresoc.v:174082$10187 assign { } { } assign $0\logical_op__zero_a$38[0:0]$10188 1'0 sync always sync init update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10188 end - attribute \src "libresoc.v:174294.13-174294.30" - process $proc$libresoc.v:174294$10189 + attribute \src "libresoc.v:174090.13-174090.30" + process $proc$libresoc.v:174090$10189 assign { } { } assign $0\muxid$28[1:0]$10190 2'00 sync always sync init update \muxid$28 $0\muxid$28[1:0]$10190 end - attribute \src "libresoc.v:174304.13-174304.34" - process $proc$libresoc.v:174304$10191 + attribute \src "libresoc.v:174100.13-174100.34" + process $proc$libresoc.v:174100$10191 assign { } { } assign $0\operation$69[1:0]$10192 2'00 sync always sync init update \operation$69 $0\operation$69[1:0]$10192 end - attribute \src "libresoc.v:174318.14-174318.44" - process $proc$libresoc.v:174318$10193 + attribute \src "libresoc.v:174114.14-174114.44" + process $proc$libresoc.v:174114$10193 assign { } { } assign $0\ra$47[63:0]$10194 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra$47 $0\ra$47[63:0]$10194 end - attribute \src "libresoc.v:174326.14-174326.44" - process $proc$libresoc.v:174326$10195 + attribute \src "libresoc.v:174122.14-174122.44" + process $proc$libresoc.v:174122$10195 assign { } { } assign $0\rb$48[63:0]$10196 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb$48 $0\rb$48[63:0]$10196 end - attribute \src "libresoc.v:174332.15-174332.84" - process $proc$libresoc.v:174332$10197 + attribute \src "libresoc.v:174128.15-174128.84" + process $proc$libresoc.v:174128$10197 assign { } { } assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:174336.13-174336.45" - process $proc$libresoc.v:174336$10198 + attribute \src "libresoc.v:174132.13-174132.45" + process $proc$libresoc.v:174132$10198 assign { } { } assign $1\saved_state_q_bits_known[6:0] 7'0000000 sync always sync init update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:174344.7-174344.25" - process $proc$libresoc.v:174344$10199 + attribute \src "libresoc.v:174140.7-174140.25" + process $proc$libresoc.v:174140$10199 assign { } { } assign $0\xer_so$49[0:0]$10200 1'0 sync always sync init update \xer_so$49 $0\xer_so$49[0:0]$10200 end - attribute \src "libresoc.v:174353.3-174354.43" - process $proc$libresoc.v:174353$9950 + attribute \src "libresoc.v:174149.3-174150.43" + process $proc$libresoc.v:174149$9950 assign { } { } assign $0\operation$69[1:0]$9951 \operation$69$next sync posedge \coresync_clk update \operation$69 $0\operation$69[1:0]$9951 end - attribute \src "libresoc.v:174355.3-174356.57" - process $proc$libresoc.v:174355$9952 + attribute \src "libresoc.v:174151.3-174152.57" + process $proc$libresoc.v:174151$9952 assign { } { } assign $0\divisor_radicand$65[63:0]$9953 \divisor_radicand$65$next sync posedge \coresync_clk update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9953 end - attribute \src "libresoc.v:174357.3-174358.41" - process $proc$libresoc.v:174357$9954 + attribute \src "libresoc.v:174153.3-174154.41" + process $proc$libresoc.v:174153$9954 assign { } { } assign $0\dividend$68[127:0]$9955 \dividend$68$next sync posedge \coresync_clk update \dividend$68 $0\dividend$68[127:0]$9955 end - attribute \src "libresoc.v:174359.3-174360.47" - process $proc$libresoc.v:174359$9956 + attribute \src "libresoc.v:174155.3-174156.47" + process $proc$libresoc.v:174155$9956 assign { } { } assign $0\div_by_zero$54[0:0]$9957 \div_by_zero$54$next sync posedge \coresync_clk update \div_by_zero$54 $0\div_by_zero$54[0:0]$9957 end - attribute \src "libresoc.v:174361.3-174362.51" - process $proc$libresoc.v:174361$9958 + attribute \src "libresoc.v:174157.3-174158.51" + process $proc$libresoc.v:174157$9958 assign { } { } assign $0\dive_abs_ov64$53[0:0]$9959 \dive_abs_ov64$53$next sync posedge \coresync_clk update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9959 end - attribute \src "libresoc.v:174363.3-174364.51" - process $proc$libresoc.v:174363$9960 + attribute \src "libresoc.v:174159.3-174160.51" + process $proc$libresoc.v:174159$9960 assign { } { } assign $0\dive_abs_ov32$52[0:0]$9961 \dive_abs_ov32$52$next sync posedge \coresync_clk update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9961 end - attribute \src "libresoc.v:174365.3-174366.49" - process $proc$libresoc.v:174365$9962 + attribute \src "libresoc.v:174161.3-174162.49" + process $proc$libresoc.v:174161$9962 assign { } { } assign $0\dividend_neg$51[0:0]$9963 \dividend_neg$51$next sync posedge \coresync_clk update \dividend_neg$51 $0\dividend_neg$51[0:0]$9963 end - attribute \src "libresoc.v:174367.3-174368.47" - process $proc$libresoc.v:174367$9964 + attribute \src "libresoc.v:174163.3-174164.47" + process $proc$libresoc.v:174163$9964 assign { } { } assign $0\divisor_neg$50[0:0]$9965 \divisor_neg$50$next sync posedge \coresync_clk update \divisor_neg$50 $0\divisor_neg$50[0:0]$9965 end - attribute \src "libresoc.v:174369.3-174370.37" - process $proc$libresoc.v:174369$9966 + attribute \src "libresoc.v:174165.3-174166.37" + process $proc$libresoc.v:174165$9966 assign { } { } assign $0\xer_so$49[0:0]$9967 \xer_so$49$next sync posedge \coresync_clk update \xer_so$49 $0\xer_so$49[0:0]$9967 end - attribute \src "libresoc.v:174371.3-174372.29" - process $proc$libresoc.v:174371$9968 + attribute \src "libresoc.v:174167.3-174168.29" + process $proc$libresoc.v:174167$9968 assign { } { } assign $0\rb$48[63:0]$9969 \rb$48$next sync posedge \coresync_clk update \rb$48 $0\rb$48[63:0]$9969 end - attribute \src "libresoc.v:174373.3-174374.29" - process $proc$libresoc.v:174373$9970 + attribute \src "libresoc.v:174169.3-174170.29" + process $proc$libresoc.v:174169$9970 assign { } { } assign $0\ra$47[63:0]$9971 \ra$47$next sync posedge \coresync_clk update \ra$47 $0\ra$47[63:0]$9971 end - attribute \src "libresoc.v:174375.3-174376.67" - process $proc$libresoc.v:174375$9972 + attribute \src "libresoc.v:174171.3-174172.67" + process $proc$libresoc.v:174171$9972 assign { } { } assign $0\logical_op__insn_type$29[6:0]$9973 \logical_op__insn_type$29$next sync posedge \coresync_clk update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9973 end - attribute \src "libresoc.v:174377.3-174378.63" - process $proc$libresoc.v:174377$9974 + attribute \src "libresoc.v:174173.3-174174.63" + process $proc$libresoc.v:174173$9974 assign { } { } assign $0\logical_op__fn_unit$30[13:0]$9975 \logical_op__fn_unit$30$next sync posedge \coresync_clk update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$9975 end - attribute \src "libresoc.v:174379.3-174380.77" - process $proc$libresoc.v:174379$9976 + attribute \src "libresoc.v:174175.3-174176.77" + process $proc$libresoc.v:174175$9976 assign { } { } assign $0\logical_op__imm_data__data$31[63:0]$9977 \logical_op__imm_data__data$31$next sync posedge \coresync_clk update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9977 end - attribute \src "libresoc.v:174381.3-174382.73" - process $proc$libresoc.v:174381$9978 + attribute \src "libresoc.v:174177.3-174178.73" + process $proc$libresoc.v:174177$9978 assign { } { } assign $0\logical_op__imm_data__ok$32[0:0]$9979 \logical_op__imm_data__ok$32$next sync posedge \coresync_clk update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9979 end - attribute \src "libresoc.v:174383.3-174384.61" - process $proc$libresoc.v:174383$9980 + attribute \src "libresoc.v:174179.3-174180.61" + process $proc$libresoc.v:174179$9980 assign { } { } assign $0\logical_op__rc__rc$33[0:0]$9981 \logical_op__rc__rc$33$next sync posedge \coresync_clk update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9981 end - attribute \src "libresoc.v:174385.3-174386.61" - process $proc$libresoc.v:174385$9982 + attribute \src "libresoc.v:174181.3-174182.61" + process $proc$libresoc.v:174181$9982 assign { } { } assign $0\logical_op__rc__ok$34[0:0]$9983 \logical_op__rc__ok$34$next sync posedge \coresync_clk update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9983 end - attribute \src "libresoc.v:174387.3-174388.61" - process $proc$libresoc.v:174387$9984 + attribute \src "libresoc.v:174183.3-174184.61" + process $proc$libresoc.v:174183$9984 assign { } { } assign $0\logical_op__oe__oe$35[0:0]$9985 \logical_op__oe__oe$35$next sync posedge \coresync_clk update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9985 end - attribute \src "libresoc.v:174389.3-174390.61" - process $proc$libresoc.v:174389$9986 + attribute \src "libresoc.v:174185.3-174186.61" + process $proc$libresoc.v:174185$9986 assign { } { } assign $0\logical_op__oe__ok$36[0:0]$9987 \logical_op__oe__ok$36$next sync posedge \coresync_clk update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9987 end - attribute \src "libresoc.v:174391.3-174392.67" - process $proc$libresoc.v:174391$9988 + attribute \src "libresoc.v:174187.3-174188.67" + process $proc$libresoc.v:174187$9988 assign { } { } assign $0\logical_op__invert_in$37[0:0]$9989 \logical_op__invert_in$37$next sync posedge \coresync_clk update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9989 end - attribute \src "libresoc.v:174393.3-174394.61" - process $proc$libresoc.v:174393$9990 + attribute \src "libresoc.v:174189.3-174190.61" + process $proc$libresoc.v:174189$9990 assign { } { } assign $0\logical_op__zero_a$38[0:0]$9991 \logical_op__zero_a$38$next sync posedge \coresync_clk update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9991 end - attribute \src "libresoc.v:174395.3-174396.71" - process $proc$libresoc.v:174395$9992 + attribute \src "libresoc.v:174191.3-174192.71" + process $proc$libresoc.v:174191$9992 assign { } { } assign $0\logical_op__input_carry$39[1:0]$9993 \logical_op__input_carry$39$next sync posedge \coresync_clk update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9993 end - attribute \src "libresoc.v:174397.3-174398.69" - process $proc$libresoc.v:174397$9994 + attribute \src "libresoc.v:174193.3-174194.69" + process $proc$libresoc.v:174193$9994 assign { } { } assign $0\logical_op__invert_out$40[0:0]$9995 \logical_op__invert_out$40$next sync posedge \coresync_clk update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9995 end - attribute \src "libresoc.v:174399.3-174400.67" - process $proc$libresoc.v:174399$9996 + attribute \src "libresoc.v:174195.3-174196.67" + process $proc$libresoc.v:174195$9996 assign { } { } assign $0\logical_op__write_cr0$41[0:0]$9997 \logical_op__write_cr0$41$next sync posedge \coresync_clk update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9997 end - attribute \src "libresoc.v:174401.3-174402.73" - process $proc$libresoc.v:174401$9998 + attribute \src "libresoc.v:174197.3-174198.73" + process $proc$libresoc.v:174197$9998 assign { } { } assign $0\logical_op__output_carry$42[0:0]$9999 \logical_op__output_carry$42$next sync posedge \coresync_clk update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9999 end - attribute \src "libresoc.v:174403.3-174404.65" - process $proc$libresoc.v:174403$10000 + attribute \src "libresoc.v:174199.3-174200.65" + process $proc$libresoc.v:174199$10000 assign { } { } assign $0\logical_op__is_32bit$43[0:0]$10001 \logical_op__is_32bit$43$next sync posedge \coresync_clk update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10001 end - attribute \src "libresoc.v:174405.3-174406.67" - process $proc$libresoc.v:174405$10002 + attribute \src "libresoc.v:174201.3-174202.67" + process $proc$libresoc.v:174201$10002 assign { } { } assign $0\logical_op__is_signed$44[0:0]$10003 \logical_op__is_signed$44$next sync posedge \coresync_clk update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10003 end - attribute \src "libresoc.v:174407.3-174408.65" - process $proc$libresoc.v:174407$10004 + attribute \src "libresoc.v:174203.3-174204.65" + process $proc$libresoc.v:174203$10004 assign { } { } assign $0\logical_op__data_len$45[3:0]$10005 \logical_op__data_len$45$next sync posedge \coresync_clk update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10005 end - attribute \src "libresoc.v:174409.3-174410.57" - process $proc$libresoc.v:174409$10006 + attribute \src "libresoc.v:174205.3-174206.57" + process $proc$libresoc.v:174205$10006 assign { } { } assign $0\logical_op__insn$46[31:0]$10007 \logical_op__insn$46$next sync posedge \coresync_clk update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10007 end - attribute \src "libresoc.v:174411.3-174412.35" - process $proc$libresoc.v:174411$10008 + attribute \src "libresoc.v:174207.3-174208.35" + process $proc$libresoc.v:174207$10008 assign { } { } assign $0\muxid$28[1:0]$10009 \muxid$28$next sync posedge \coresync_clk update \muxid$28 $0\muxid$28[1:0]$10009 end - attribute \src "libresoc.v:174413.3-174414.27" - process $proc$libresoc.v:174413$10010 + attribute \src "libresoc.v:174209.3-174210.27" + process $proc$libresoc.v:174209$10010 assign { } { } assign $0\empty[0:0] \empty$next sync posedge \coresync_clk update \empty $0\empty[0:0] end - attribute \src "libresoc.v:174415.3-174416.75" - process $proc$libresoc.v:174415$10011 + attribute \src "libresoc.v:174211.3-174212.75" + process $proc$libresoc.v:174211$10011 assign { } { } assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next sync posedge \coresync_clk update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:174417.3-174418.65" - process $proc$libresoc.v:174417$10012 + attribute \src "libresoc.v:174213.3-174214.65" + process $proc$libresoc.v:174213$10012 assign { } { } assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next sync posedge \coresync_clk update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:174439.3-174447.6" - process $proc$libresoc.v:174439$10013 + attribute \src "libresoc.v:174235.3-174243.6" + process $proc$libresoc.v:174235$10013 assign { } { } assign { } { } assign $0\saved_state_q_bits_known$next[6:0]$10014 $1\saved_state_q_bits_known$next[6:0]$10015 - attribute \src "libresoc.v:174440.5-174440.29" + attribute \src "libresoc.v:174236.5-174236.29" switch \initial - attribute \src "libresoc.v:174440.9-174440.17" + attribute \src "libresoc.v:174236.9-174236.17" case 1'1 case end @@ -322548,14 +322382,14 @@ module \pipe_middle_0 sync always update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10014 end - attribute \src "libresoc.v:174448.3-174456.6" - process $proc$libresoc.v:174448$10016 + attribute \src "libresoc.v:174244.3-174252.6" + process $proc$libresoc.v:174244$10016 assign { } { } assign { } { } assign $0\saved_state_dividend_quotient$next[127:0]$10017 $1\saved_state_dividend_quotient$next[127:0]$10018 - attribute \src "libresoc.v:174449.5-174449.29" + attribute \src "libresoc.v:174245.5-174245.29" switch \initial - attribute \src "libresoc.v:174449.9-174449.17" + attribute \src "libresoc.v:174245.9-174245.17" case 1'1 case end @@ -322571,13 +322405,13 @@ module \pipe_middle_0 sync always update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10017 end - attribute \src "libresoc.v:174457.3-174468.6" - process $proc$libresoc.v:174457$10019 + attribute \src "libresoc.v:174253.3-174264.6" + process $proc$libresoc.v:174253$10019 assign { } { } assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:174458.5-174458.29" + attribute \src "libresoc.v:174254.5-174254.29" switch \initial - attribute \src "libresoc.v:174458.9-174458.17" + attribute \src "libresoc.v:174254.9-174254.17" case 1'1 case end @@ -322595,13 +322429,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] end - attribute \src "libresoc.v:174469.3-174480.6" - process $proc$libresoc.v:174469$10020 + attribute \src "libresoc.v:174265.3-174276.6" + process $proc$libresoc.v:174265$10020 assign { } { } assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:174470.5-174470.29" + attribute \src "libresoc.v:174266.5-174266.29" switch \initial - attribute \src "libresoc.v:174470.9-174470.17" + attribute \src "libresoc.v:174266.9-174266.17" case 1'1 case end @@ -322619,13 +322453,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] end - attribute \src "libresoc.v:174481.3-174492.6" - process $proc$libresoc.v:174481$10021 + attribute \src "libresoc.v:174277.3-174288.6" + process $proc$libresoc.v:174277$10021 assign { } { } assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:174482.5-174482.29" + attribute \src "libresoc.v:174278.5-174278.29" switch \initial - attribute \src "libresoc.v:174482.9-174482.17" + attribute \src "libresoc.v:174278.9-174278.17" case 1'1 case end @@ -322643,15 +322477,15 @@ module \pipe_middle_0 sync always update \div_state_next_divisor $0\div_state_next_divisor[63:0] end - attribute \src "libresoc.v:174493.3-174520.6" - process $proc$libresoc.v:174493$10022 + attribute \src "libresoc.v:174289.3-174316.6" + process $proc$libresoc.v:174289$10022 assign { } { } assign { } { } assign { } { } assign $0\empty$next[0:0]$10023 $4\empty$next[0:0]$10027 - attribute \src "libresoc.v:174494.5-174494.29" + attribute \src "libresoc.v:174290.5-174290.29" switch \initial - attribute \src "libresoc.v:174494.9-174494.17" + attribute \src "libresoc.v:174290.9-174290.17" case 1'1 case end @@ -322696,14 +322530,14 @@ module \pipe_middle_0 sync always update \empty$next $0\empty$next[0:0]$10023 end - attribute \src "libresoc.v:174521.3-174535.6" - process $proc$libresoc.v:174521$10028 + attribute \src "libresoc.v:174317.3-174331.6" + process $proc$libresoc.v:174317$10028 assign { } { } assign { } { } assign $0\muxid$28$next[1:0]$10029 $1\muxid$28$next[1:0]$10030 - attribute \src "libresoc.v:174522.5-174522.29" + attribute \src "libresoc.v:174318.5-174318.29" switch \initial - attribute \src "libresoc.v:174522.9-174522.17" + attribute \src "libresoc.v:174318.9-174318.17" case 1'1 case end @@ -322728,8 +322562,8 @@ module \pipe_middle_0 sync always update \muxid$28$next $0\muxid$28$next[1:0]$10029 end - attribute \src "libresoc.v:174536.3-174579.6" - process $proc$libresoc.v:174536$10032 + attribute \src "libresoc.v:174332.3-174375.6" + process $proc$libresoc.v:174332$10032 assign { } { } assign { } { } assign { } { } @@ -322790,9 +322624,9 @@ module \pipe_middle_0 assign $0\logical_op__oe__ok$36$next[0:0]$10045 $3\logical_op__oe__ok$36$next[0:0]$10090 assign $0\logical_op__rc__ok$34$next[0:0]$10047 $3\logical_op__rc__ok$34$next[0:0]$10091 assign $0\logical_op__rc__rc$33$next[0:0]$10048 $3\logical_op__rc__rc$33$next[0:0]$10092 - attribute \src "libresoc.v:174537.5-174537.29" + attribute \src "libresoc.v:174333.5-174333.29" switch \initial - attribute \src "libresoc.v:174537.9-174537.17" + attribute \src "libresoc.v:174333.9-174333.17" case 1'1 case end @@ -322943,14 +322777,14 @@ module \pipe_middle_0 update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10049 update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10050 end - attribute \src "libresoc.v:174580.3-174594.6" - process $proc$libresoc.v:174580$10093 + attribute \src "libresoc.v:174376.3-174390.6" + process $proc$libresoc.v:174376$10093 assign { } { } assign { } { } assign $0\ra$47$next[63:0]$10094 $1\ra$47$next[63:0]$10095 - attribute \src "libresoc.v:174581.5-174581.29" + attribute \src "libresoc.v:174377.5-174377.29" switch \initial - attribute \src "libresoc.v:174581.9-174581.17" + attribute \src "libresoc.v:174377.9-174377.17" case 1'1 case end @@ -322975,14 +322809,14 @@ module \pipe_middle_0 sync always update \ra$47$next $0\ra$47$next[63:0]$10094 end - attribute \src "libresoc.v:174595.3-174609.6" - process $proc$libresoc.v:174595$10097 + attribute \src "libresoc.v:174391.3-174405.6" + process $proc$libresoc.v:174391$10097 assign { } { } assign { } { } assign $0\rb$48$next[63:0]$10098 $1\rb$48$next[63:0]$10099 - attribute \src "libresoc.v:174596.5-174596.29" + attribute \src "libresoc.v:174392.5-174392.29" switch \initial - attribute \src "libresoc.v:174596.9-174596.17" + attribute \src "libresoc.v:174392.9-174392.17" case 1'1 case end @@ -323007,14 +322841,14 @@ module \pipe_middle_0 sync always update \rb$48$next $0\rb$48$next[63:0]$10098 end - attribute \src "libresoc.v:174610.3-174624.6" - process $proc$libresoc.v:174610$10101 + attribute \src "libresoc.v:174406.3-174420.6" + process $proc$libresoc.v:174406$10101 assign { } { } assign { } { } assign $0\xer_so$49$next[0:0]$10102 $1\xer_so$49$next[0:0]$10103 - attribute \src "libresoc.v:174611.5-174611.29" + attribute \src "libresoc.v:174407.5-174407.29" switch \initial - attribute \src "libresoc.v:174611.9-174611.17" + attribute \src "libresoc.v:174407.9-174407.17" case 1'1 case end @@ -323039,14 +322873,14 @@ module \pipe_middle_0 sync always update \xer_so$49$next $0\xer_so$49$next[0:0]$10102 end - attribute \src "libresoc.v:174625.3-174639.6" - process $proc$libresoc.v:174625$10105 + attribute \src "libresoc.v:174421.3-174435.6" + process $proc$libresoc.v:174421$10105 assign { } { } assign { } { } assign $0\divisor_neg$50$next[0:0]$10106 $1\divisor_neg$50$next[0:0]$10107 - attribute \src "libresoc.v:174626.5-174626.29" + attribute \src "libresoc.v:174422.5-174422.29" switch \initial - attribute \src "libresoc.v:174626.9-174626.17" + attribute \src "libresoc.v:174422.9-174422.17" case 1'1 case end @@ -323071,14 +322905,14 @@ module \pipe_middle_0 sync always update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10106 end - attribute \src "libresoc.v:174640.3-174654.6" - process $proc$libresoc.v:174640$10109 + attribute \src "libresoc.v:174436.3-174450.6" + process $proc$libresoc.v:174436$10109 assign { } { } assign { } { } assign $0\dividend_neg$51$next[0:0]$10110 $1\dividend_neg$51$next[0:0]$10111 - attribute \src "libresoc.v:174641.5-174641.29" + attribute \src "libresoc.v:174437.5-174437.29" switch \initial - attribute \src "libresoc.v:174641.9-174641.17" + attribute \src "libresoc.v:174437.9-174437.17" case 1'1 case end @@ -323103,14 +322937,14 @@ module \pipe_middle_0 sync always update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10110 end - attribute \src "libresoc.v:174655.3-174669.6" - process $proc$libresoc.v:174655$10113 + attribute \src "libresoc.v:174451.3-174465.6" + process $proc$libresoc.v:174451$10113 assign { } { } assign { } { } assign $0\dive_abs_ov32$52$next[0:0]$10114 $1\dive_abs_ov32$52$next[0:0]$10115 - attribute \src "libresoc.v:174656.5-174656.29" + attribute \src "libresoc.v:174452.5-174452.29" switch \initial - attribute \src "libresoc.v:174656.9-174656.17" + attribute \src "libresoc.v:174452.9-174452.17" case 1'1 case end @@ -323135,14 +322969,14 @@ module \pipe_middle_0 sync always update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10114 end - attribute \src "libresoc.v:174670.3-174684.6" - process $proc$libresoc.v:174670$10117 + attribute \src "libresoc.v:174466.3-174480.6" + process $proc$libresoc.v:174466$10117 assign { } { } assign { } { } assign $0\dive_abs_ov64$53$next[0:0]$10118 $1\dive_abs_ov64$53$next[0:0]$10119 - attribute \src "libresoc.v:174671.5-174671.29" + attribute \src "libresoc.v:174467.5-174467.29" switch \initial - attribute \src "libresoc.v:174671.9-174671.17" + attribute \src "libresoc.v:174467.9-174467.17" case 1'1 case end @@ -323167,14 +323001,14 @@ module \pipe_middle_0 sync always update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10118 end - attribute \src "libresoc.v:174685.3-174699.6" - process $proc$libresoc.v:174685$10121 + attribute \src "libresoc.v:174481.3-174495.6" + process $proc$libresoc.v:174481$10121 assign { } { } assign { } { } assign $0\div_by_zero$54$next[0:0]$10122 $1\div_by_zero$54$next[0:0]$10123 - attribute \src "libresoc.v:174686.5-174686.29" + attribute \src "libresoc.v:174482.5-174482.29" switch \initial - attribute \src "libresoc.v:174686.9-174686.17" + attribute \src "libresoc.v:174482.9-174482.17" case 1'1 case end @@ -323199,14 +323033,14 @@ module \pipe_middle_0 sync always update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10122 end - attribute \src "libresoc.v:174700.3-174714.6" - process $proc$libresoc.v:174700$10125 + attribute \src "libresoc.v:174496.3-174510.6" + process $proc$libresoc.v:174496$10125 assign { } { } assign { } { } assign $0\dividend$68$next[127:0]$10126 $1\dividend$68$next[127:0]$10127 - attribute \src "libresoc.v:174701.5-174701.29" + attribute \src "libresoc.v:174497.5-174497.29" switch \initial - attribute \src "libresoc.v:174701.9-174701.17" + attribute \src "libresoc.v:174497.9-174497.17" case 1'1 case end @@ -323231,14 +323065,14 @@ module \pipe_middle_0 sync always update \dividend$68$next $0\dividend$68$next[127:0]$10126 end - attribute \src "libresoc.v:174715.3-174729.6" - process $proc$libresoc.v:174715$10129 + attribute \src "libresoc.v:174511.3-174525.6" + process $proc$libresoc.v:174511$10129 assign { } { } assign { } { } assign $0\divisor_radicand$65$next[63:0]$10130 $1\divisor_radicand$65$next[63:0]$10131 - attribute \src "libresoc.v:174716.5-174716.29" + attribute \src "libresoc.v:174512.5-174512.29" switch \initial - attribute \src "libresoc.v:174716.9-174716.17" + attribute \src "libresoc.v:174512.9-174512.17" case 1'1 case end @@ -323263,14 +323097,14 @@ module \pipe_middle_0 sync always update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10130 end - attribute \src "libresoc.v:174730.3-174744.6" - process $proc$libresoc.v:174730$10133 + attribute \src "libresoc.v:174526.3-174540.6" + process $proc$libresoc.v:174526$10133 assign { } { } assign { } { } assign $0\operation$69$next[1:0]$10134 $1\operation$69$next[1:0]$10135 - attribute \src "libresoc.v:174731.5-174731.29" + attribute \src "libresoc.v:174527.5-174527.29" switch \initial - attribute \src "libresoc.v:174731.9-174731.17" + attribute \src "libresoc.v:174527.9-174527.17" case 1'1 case end @@ -323295,12 +323129,12 @@ module \pipe_middle_0 sync always update \operation$69$next $0\operation$69$next[1:0]$10134 end - connect \$56 $sshl$libresoc.v:174347$9943_Y - connect \$55 $pos$libresoc.v:174348$9945_Y - connect \$59 $not$libresoc.v:174349$9946_Y - connect \$61 $ge$libresoc.v:174350$9947_Y - connect \$63 $and$libresoc.v:174351$9948_Y - connect \$66 $and$libresoc.v:174352$9949_Y + connect \$56 $sshl$libresoc.v:174143$9943_Y + connect \$55 $pos$libresoc.v:174144$9945_Y + connect \$59 $not$libresoc.v:174145$9946_Y + connect \$61 $ge$libresoc.v:174146$9947_Y + connect \$63 $and$libresoc.v:174147$9948_Y + connect \$66 $and$libresoc.v:174148$9949_Y connect \p_ready_o \empty connect \n_valid_o \$63 connect \remainder \$55 @@ -323317,282 +323151,282 @@ module \pipe_middle_0 connect \muxid$1 \muxid$28 connect \div_state_init_dividend \dividend end -attribute \src "libresoc.v:174764.1-176309.10" +attribute \src "libresoc.v:174560.1-176105.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" attribute \generator "nMigen" module \pipe_start - attribute \src "libresoc.v:176115.3-176127.6" + attribute \src "libresoc.v:175911.3-175923.6" wire $0\div_by_zero$next[0:0]$10246 - attribute \src "libresoc.v:175901.3-175902.39" + attribute \src "libresoc.v:175697.3-175698.39" wire $0\div_by_zero[0:0] - attribute \src "libresoc.v:176089.3-176101.6" + attribute \src "libresoc.v:175885.3-175897.6" wire $0\dive_abs_ov32$next[0:0]$10240 - attribute \src "libresoc.v:175905.3-175906.43" + attribute \src "libresoc.v:175701.3-175702.43" wire $0\dive_abs_ov32[0:0] - attribute \src "libresoc.v:176102.3-176114.6" + attribute \src "libresoc.v:175898.3-175910.6" wire $0\dive_abs_ov64$next[0:0]$10243 - attribute \src "libresoc.v:175903.3-175904.43" + attribute \src "libresoc.v:175699.3-175700.43" wire $0\dive_abs_ov64[0:0] - attribute \src "libresoc.v:176128.3-176140.6" + attribute \src "libresoc.v:175924.3-175936.6" wire width 128 $0\dividend$next[127:0]$10249 - attribute \src "libresoc.v:175899.3-175900.33" + attribute \src "libresoc.v:175695.3-175696.33" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:176076.3-176088.6" + attribute \src "libresoc.v:175872.3-175884.6" wire $0\dividend_neg$next[0:0]$10237 - attribute \src "libresoc.v:175907.3-175908.41" + attribute \src "libresoc.v:175703.3-175704.41" wire $0\dividend_neg[0:0] - attribute \src "libresoc.v:176063.3-176075.6" + attribute \src "libresoc.v:175859.3-175871.6" wire $0\divisor_neg$next[0:0]$10234 - attribute \src "libresoc.v:175909.3-175910.39" + attribute \src "libresoc.v:175705.3-175706.39" wire $0\divisor_neg[0:0] - attribute \src "libresoc.v:176141.3-176153.6" + attribute \src "libresoc.v:175937.3-175949.6" wire width 64 $0\divisor_radicand$next[63:0]$10252 - attribute \src "libresoc.v:175897.3-175898.49" + attribute \src "libresoc.v:175693.3-175694.49" wire width 64 $0\divisor_radicand[63:0] - attribute \src "libresoc.v:174765.7-174765.20" + attribute \src "libresoc.v:174561.7-174561.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 4 $0\logical_op__data_len$next[3:0]$10265 - attribute \src "libresoc.v:175949.3-175950.57" + attribute \src "libresoc.v:175745.3-175746.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 14 $0\logical_op__fn_unit$next[13:0]$10266 - attribute \src "libresoc.v:175919.3-175920.55" + attribute \src "libresoc.v:175715.3-175716.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 64 $0\logical_op__imm_data__data$next[63:0]$10267 - attribute \src "libresoc.v:175921.3-175922.69" + attribute \src "libresoc.v:175717.3-175718.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__imm_data__ok$next[0:0]$10268 - attribute \src "libresoc.v:175923.3-175924.65" + attribute \src "libresoc.v:175719.3-175720.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 2 $0\logical_op__input_carry$next[1:0]$10269 - attribute \src "libresoc.v:175937.3-175938.63" + attribute \src "libresoc.v:175733.3-175734.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 32 $0\logical_op__insn$next[31:0]$10270 - attribute \src "libresoc.v:175951.3-175952.49" + attribute \src "libresoc.v:175747.3-175748.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 7 $0\logical_op__insn_type$next[6:0]$10271 - attribute \src "libresoc.v:175917.3-175918.59" + attribute \src "libresoc.v:175713.3-175714.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__invert_in$next[0:0]$10272 - attribute \src "libresoc.v:175933.3-175934.59" + attribute \src "libresoc.v:175729.3-175730.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__invert_out$next[0:0]$10273 - attribute \src "libresoc.v:175939.3-175940.61" + attribute \src "libresoc.v:175735.3-175736.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__is_32bit$next[0:0]$10274 - attribute \src "libresoc.v:175945.3-175946.57" + attribute \src "libresoc.v:175741.3-175742.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__is_signed$next[0:0]$10275 - attribute \src "libresoc.v:175947.3-175948.59" + attribute \src "libresoc.v:175743.3-175744.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__oe__oe$next[0:0]$10276 - attribute \src "libresoc.v:175929.3-175930.53" + attribute \src "libresoc.v:175725.3-175726.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__oe__ok$next[0:0]$10277 - attribute \src "libresoc.v:175931.3-175932.53" + attribute \src "libresoc.v:175727.3-175728.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__output_carry$next[0:0]$10278 - attribute \src "libresoc.v:175943.3-175944.65" + attribute \src "libresoc.v:175739.3-175740.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__rc__ok$next[0:0]$10279 - attribute \src "libresoc.v:175927.3-175928.53" + attribute \src "libresoc.v:175723.3-175724.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__rc__rc$next[0:0]$10280 - attribute \src "libresoc.v:175925.3-175926.53" + attribute \src "libresoc.v:175721.3-175722.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__write_cr0$next[0:0]$10281 - attribute \src "libresoc.v:175941.3-175942.59" + attribute \src "libresoc.v:175737.3-175738.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__zero_a$next[0:0]$10282 - attribute \src "libresoc.v:175935.3-175936.53" + attribute \src "libresoc.v:175731.3-175732.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:176185.3-176197.6" + attribute \src "libresoc.v:175981.3-175993.6" wire width 2 $0\muxid$next[1:0]$10262 - attribute \src "libresoc.v:175953.3-175954.27" + attribute \src "libresoc.v:175749.3-175750.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:176154.3-176166.6" + attribute \src "libresoc.v:175950.3-175962.6" wire width 2 $0\operation$next[1:0]$10255 - attribute \src "libresoc.v:175895.3-175896.35" + attribute \src "libresoc.v:175691.3-175692.35" wire width 2 $0\operation[1:0] - attribute \src "libresoc.v:176167.3-176184.6" + attribute \src "libresoc.v:175963.3-175980.6" wire $0\r_busy$next[0:0]$10258 - attribute \src "libresoc.v:175955.3-175956.29" + attribute \src "libresoc.v:175751.3-175752.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:176240.3-176252.6" + attribute \src "libresoc.v:176036.3-176048.6" wire width 64 $0\ra$next[63:0]$10308 - attribute \src "libresoc.v:175915.3-175916.21" + attribute \src "libresoc.v:175711.3-175712.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:176253.3-176265.6" + attribute \src "libresoc.v:176049.3-176061.6" wire width 64 $0\rb$next[63:0]$10311 - attribute \src "libresoc.v:175913.3-175914.21" + attribute \src "libresoc.v:175709.3-175710.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:176266.3-176278.6" + attribute \src "libresoc.v:176062.3-176074.6" wire $0\xer_so$next[0:0]$10314 - attribute \src "libresoc.v:175911.3-175912.29" + attribute \src "libresoc.v:175707.3-175708.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:176115.3-176127.6" + attribute \src "libresoc.v:175911.3-175923.6" wire $1\div_by_zero$next[0:0]$10247 - attribute \src "libresoc.v:174774.7-174774.25" + attribute \src "libresoc.v:174570.7-174570.25" wire $1\div_by_zero[0:0] - attribute \src "libresoc.v:176089.3-176101.6" + attribute \src "libresoc.v:175885.3-175897.6" wire $1\dive_abs_ov32$next[0:0]$10241 - attribute \src "libresoc.v:174781.7-174781.27" + attribute \src "libresoc.v:174577.7-174577.27" wire $1\dive_abs_ov32[0:0] - attribute \src "libresoc.v:176102.3-176114.6" + attribute \src "libresoc.v:175898.3-175910.6" wire $1\dive_abs_ov64$next[0:0]$10244 - attribute \src "libresoc.v:174788.7-174788.27" + attribute \src "libresoc.v:174584.7-174584.27" wire $1\dive_abs_ov64[0:0] - attribute \src "libresoc.v:176128.3-176140.6" + attribute \src "libresoc.v:175924.3-175936.6" wire width 128 $1\dividend$next[127:0]$10250 - attribute \src "libresoc.v:174795.15-174795.63" + attribute \src "libresoc.v:174591.15-174591.63" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:176076.3-176088.6" + attribute \src "libresoc.v:175872.3-175884.6" wire $1\dividend_neg$next[0:0]$10238 - attribute \src "libresoc.v:174802.7-174802.26" + attribute \src "libresoc.v:174598.7-174598.26" wire $1\dividend_neg[0:0] - attribute \src "libresoc.v:176063.3-176075.6" + attribute \src "libresoc.v:175859.3-175871.6" wire $1\divisor_neg$next[0:0]$10235 - attribute \src "libresoc.v:174809.7-174809.25" + attribute \src "libresoc.v:174605.7-174605.25" wire $1\divisor_neg[0:0] - attribute \src "libresoc.v:176141.3-176153.6" + attribute \src "libresoc.v:175937.3-175949.6" wire width 64 $1\divisor_radicand$next[63:0]$10253 - attribute \src "libresoc.v:174816.14-174816.53" + attribute \src "libresoc.v:174612.14-174612.53" wire width 64 $1\divisor_radicand[63:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 4 $1\logical_op__data_len$next[3:0]$10283 - attribute \src "libresoc.v:175099.13-175099.40" + attribute \src "libresoc.v:174895.13-174895.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 14 $1\logical_op__fn_unit$next[13:0]$10284 - attribute \src "libresoc.v:175123.14-175123.44" + attribute \src "libresoc.v:174919.14-174919.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 64 $1\logical_op__imm_data__data$next[63:0]$10285 - attribute \src "libresoc.v:175162.14-175162.63" + attribute \src "libresoc.v:174958.14-174958.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__imm_data__ok$next[0:0]$10286 - attribute \src "libresoc.v:175171.7-175171.38" + attribute \src "libresoc.v:174967.7-174967.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 2 $1\logical_op__input_carry$next[1:0]$10287 - attribute \src "libresoc.v:175184.13-175184.43" + attribute \src "libresoc.v:174980.13-174980.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 32 $1\logical_op__insn$next[31:0]$10288 - attribute \src "libresoc.v:175201.14-175201.38" + attribute \src "libresoc.v:174997.14-174997.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 7 $1\logical_op__insn_type$next[6:0]$10289 - attribute \src "libresoc.v:175285.13-175285.42" + attribute \src "libresoc.v:175081.13-175081.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__invert_in$next[0:0]$10290 - attribute \src "libresoc.v:175444.7-175444.35" + attribute \src "libresoc.v:175240.7-175240.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__invert_out$next[0:0]$10291 - attribute \src "libresoc.v:175453.7-175453.36" + attribute \src "libresoc.v:175249.7-175249.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__is_32bit$next[0:0]$10292 - attribute \src "libresoc.v:175462.7-175462.34" + attribute \src "libresoc.v:175258.7-175258.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__is_signed$next[0:0]$10293 - attribute \src "libresoc.v:175471.7-175471.35" + attribute \src "libresoc.v:175267.7-175267.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__oe__oe$next[0:0]$10294 - attribute \src "libresoc.v:175480.7-175480.32" + attribute \src "libresoc.v:175276.7-175276.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__oe__ok$next[0:0]$10295 - attribute \src "libresoc.v:175489.7-175489.32" + attribute \src "libresoc.v:175285.7-175285.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__output_carry$next[0:0]$10296 - attribute \src "libresoc.v:175498.7-175498.38" + attribute \src "libresoc.v:175294.7-175294.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__rc__ok$next[0:0]$10297 - attribute \src "libresoc.v:175507.7-175507.32" + attribute \src "libresoc.v:175303.7-175303.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__rc__rc$next[0:0]$10298 - attribute \src "libresoc.v:175516.7-175516.32" + attribute \src "libresoc.v:175312.7-175312.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__write_cr0$next[0:0]$10299 - attribute \src "libresoc.v:175525.7-175525.35" + attribute \src "libresoc.v:175321.7-175321.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__zero_a$next[0:0]$10300 - attribute \src "libresoc.v:175534.7-175534.32" + attribute \src "libresoc.v:175330.7-175330.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:176185.3-176197.6" + attribute \src "libresoc.v:175981.3-175993.6" wire width 2 $1\muxid$next[1:0]$10263 - attribute \src "libresoc.v:175543.13-175543.25" + attribute \src "libresoc.v:175339.13-175339.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:176154.3-176166.6" + attribute \src "libresoc.v:175950.3-175962.6" wire width 2 $1\operation$next[1:0]$10256 - attribute \src "libresoc.v:175558.13-175558.29" + attribute \src "libresoc.v:175354.13-175354.29" wire width 2 $1\operation[1:0] - attribute \src "libresoc.v:176167.3-176184.6" + attribute \src "libresoc.v:175963.3-175980.6" wire $1\r_busy$next[0:0]$10259 - attribute \src "libresoc.v:175572.7-175572.20" + attribute \src "libresoc.v:175368.7-175368.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:176240.3-176252.6" + attribute \src "libresoc.v:176036.3-176048.6" wire width 64 $1\ra$next[63:0]$10309 - attribute \src "libresoc.v:175577.14-175577.39" + attribute \src "libresoc.v:175373.14-175373.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:176253.3-176265.6" + attribute \src "libresoc.v:176049.3-176061.6" wire width 64 $1\rb$next[63:0]$10312 - attribute \src "libresoc.v:175588.14-175588.39" + attribute \src "libresoc.v:175384.14-175384.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:176266.3-176278.6" + attribute \src "libresoc.v:176062.3-176074.6" wire $1\xer_so$next[0:0]$10315 - attribute \src "libresoc.v:175887.7-175887.20" + attribute \src "libresoc.v:175683.7-175683.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire width 64 $2\logical_op__imm_data__data$next[63:0]$10301 - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $2\logical_op__imm_data__ok$next[0:0]$10302 - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $2\logical_op__oe__oe$next[0:0]$10303 - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $2\logical_op__oe__ok$next[0:0]$10304 - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $2\logical_op__rc__ok$next[0:0]$10305 - attribute \src "libresoc.v:176198.3-176239.6" + attribute \src "libresoc.v:175994.3-176035.6" wire $2\logical_op__rc__rc$next[0:0]$10306 - attribute \src "libresoc.v:176167.3-176184.6" + attribute \src "libresoc.v:175963.3-175980.6" wire $2\r_busy$next[0:0]$10260 - attribute \src "libresoc.v:175894.18-175894.118" - wire $and$libresoc.v:175894$10201_Y + attribute \src "libresoc.v:175690.18-175690.118" + wire $and$libresoc.v:175690$10201_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire output 30 \div_by_zero @@ -323636,7 +323470,7 @@ module \pipe_start wire width 64 \divisor_radicand$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$next - attribute \src "libresoc.v:174765.7-174765.15" + attribute \src "libresoc.v:174561.7-174561.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -324689,7 +324523,7 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:175894$10201 + cell $and $and$libresoc.v:175690$10201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324697,10 +324531,10 @@ module \pipe_start parameter \Y_WIDTH 1 connect \A \p_valid_i$65 connect \B \p_ready_o - connect \Y $and$libresoc.v:175894$10201_Y + connect \Y $and$libresoc.v:175690$10201_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:175957.14-176002.4" + attribute \src "libresoc.v:175753.14-175798.4" cell \input$78 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$40 @@ -324748,19 +324582,19 @@ module \pipe_start connect \xer_so$22 \input_xer_so$44 end attribute \module_not_derived 1 - attribute \src "libresoc.v:176003.10-176006.4" + attribute \src "libresoc.v:175799.10-175802.4" cell \n$77 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:176007.10-176010.4" + attribute \src "libresoc.v:175803.10-175806.4" cell \p$76 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:176011.15-176062.4" + attribute \src "libresoc.v:175807.15-175858.4" cell \setup_stage \setup_stage connect \div_by_zero \setup_stage_div_by_zero connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 @@ -324813,487 +324647,487 @@ module \pipe_start connect \xer_so \setup_stage_xer_so connect \xer_so$20 \setup_stage_xer_so$64 end - attribute \src "libresoc.v:174765.7-174765.20" - process $proc$libresoc.v:174765$10316 + attribute \src "libresoc.v:174561.7-174561.20" + process $proc$libresoc.v:174561$10316 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174774.7-174774.25" - process $proc$libresoc.v:174774$10317 + attribute \src "libresoc.v:174570.7-174570.25" + process $proc$libresoc.v:174570$10317 assign { } { } assign $1\div_by_zero[0:0] 1'0 sync always sync init update \div_by_zero $1\div_by_zero[0:0] end - attribute \src "libresoc.v:174781.7-174781.27" - process $proc$libresoc.v:174781$10318 + attribute \src "libresoc.v:174577.7-174577.27" + process $proc$libresoc.v:174577$10318 assign { } { } assign $1\dive_abs_ov32[0:0] 1'0 sync always sync init update \dive_abs_ov32 $1\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:174788.7-174788.27" - process $proc$libresoc.v:174788$10319 + attribute \src "libresoc.v:174584.7-174584.27" + process $proc$libresoc.v:174584$10319 assign { } { } assign $1\dive_abs_ov64[0:0] 1'0 sync always sync init update \dive_abs_ov64 $1\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:174795.15-174795.63" - process $proc$libresoc.v:174795$10320 + attribute \src "libresoc.v:174591.15-174591.63" + process $proc$libresoc.v:174591$10320 assign { } { } assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend $1\dividend[127:0] end - attribute \src "libresoc.v:174802.7-174802.26" - process $proc$libresoc.v:174802$10321 + attribute \src "libresoc.v:174598.7-174598.26" + process $proc$libresoc.v:174598$10321 assign { } { } assign $1\dividend_neg[0:0] 1'0 sync always sync init update \dividend_neg $1\dividend_neg[0:0] end - attribute \src "libresoc.v:174809.7-174809.25" - process $proc$libresoc.v:174809$10322 + attribute \src "libresoc.v:174605.7-174605.25" + process $proc$libresoc.v:174605$10322 assign { } { } assign $1\divisor_neg[0:0] 1'0 sync always sync init update \divisor_neg $1\divisor_neg[0:0] end - attribute \src "libresoc.v:174816.14-174816.53" - process $proc$libresoc.v:174816$10323 + attribute \src "libresoc.v:174612.14-174612.53" + process $proc$libresoc.v:174612$10323 assign { } { } assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand $1\divisor_radicand[63:0] end - attribute \src "libresoc.v:175099.13-175099.40" - process $proc$libresoc.v:175099$10324 + attribute \src "libresoc.v:174895.13-174895.40" + process $proc$libresoc.v:174895$10324 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:175123.14-175123.44" - process $proc$libresoc.v:175123$10325 + attribute \src "libresoc.v:174919.14-174919.44" + process $proc$libresoc.v:174919$10325 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:175162.14-175162.63" - process $proc$libresoc.v:175162$10326 + attribute \src "libresoc.v:174958.14-174958.63" + process $proc$libresoc.v:174958$10326 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:175171.7-175171.38" - process $proc$libresoc.v:175171$10327 + attribute \src "libresoc.v:174967.7-174967.38" + process $proc$libresoc.v:174967$10327 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:175184.13-175184.43" - process $proc$libresoc.v:175184$10328 + attribute \src "libresoc.v:174980.13-174980.43" + process $proc$libresoc.v:174980$10328 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:175201.14-175201.38" - process $proc$libresoc.v:175201$10329 + attribute \src "libresoc.v:174997.14-174997.38" + process $proc$libresoc.v:174997$10329 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:175285.13-175285.42" - process $proc$libresoc.v:175285$10330 + attribute \src "libresoc.v:175081.13-175081.42" + process $proc$libresoc.v:175081$10330 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:175444.7-175444.35" - process $proc$libresoc.v:175444$10331 + attribute \src "libresoc.v:175240.7-175240.35" + process $proc$libresoc.v:175240$10331 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:175453.7-175453.36" - process $proc$libresoc.v:175453$10332 + attribute \src "libresoc.v:175249.7-175249.36" + process $proc$libresoc.v:175249$10332 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:175462.7-175462.34" - process $proc$libresoc.v:175462$10333 + attribute \src "libresoc.v:175258.7-175258.34" + process $proc$libresoc.v:175258$10333 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:175471.7-175471.35" - process $proc$libresoc.v:175471$10334 + attribute \src "libresoc.v:175267.7-175267.35" + process $proc$libresoc.v:175267$10334 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:175480.7-175480.32" - process $proc$libresoc.v:175480$10335 + attribute \src "libresoc.v:175276.7-175276.32" + process $proc$libresoc.v:175276$10335 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:175489.7-175489.32" - process $proc$libresoc.v:175489$10336 + attribute \src "libresoc.v:175285.7-175285.32" + process $proc$libresoc.v:175285$10336 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:175498.7-175498.38" - process $proc$libresoc.v:175498$10337 + attribute \src "libresoc.v:175294.7-175294.38" + process $proc$libresoc.v:175294$10337 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:175507.7-175507.32" - process $proc$libresoc.v:175507$10338 + attribute \src "libresoc.v:175303.7-175303.32" + process $proc$libresoc.v:175303$10338 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:175516.7-175516.32" - process $proc$libresoc.v:175516$10339 + attribute \src "libresoc.v:175312.7-175312.32" + process $proc$libresoc.v:175312$10339 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:175525.7-175525.35" - process $proc$libresoc.v:175525$10340 + attribute \src "libresoc.v:175321.7-175321.35" + process $proc$libresoc.v:175321$10340 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:175534.7-175534.32" - process $proc$libresoc.v:175534$10341 + attribute \src "libresoc.v:175330.7-175330.32" + process $proc$libresoc.v:175330$10341 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:175543.13-175543.25" - process $proc$libresoc.v:175543$10342 + attribute \src "libresoc.v:175339.13-175339.25" + process $proc$libresoc.v:175339$10342 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:175558.13-175558.29" - process $proc$libresoc.v:175558$10343 + attribute \src "libresoc.v:175354.13-175354.29" + process $proc$libresoc.v:175354$10343 assign { } { } assign $1\operation[1:0] 2'00 sync always sync init update \operation $1\operation[1:0] end - attribute \src "libresoc.v:175572.7-175572.20" - process $proc$libresoc.v:175572$10344 + attribute \src "libresoc.v:175368.7-175368.20" + process $proc$libresoc.v:175368$10344 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:175577.14-175577.39" - process $proc$libresoc.v:175577$10345 + attribute \src "libresoc.v:175373.14-175373.39" + process $proc$libresoc.v:175373$10345 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:175588.14-175588.39" - process $proc$libresoc.v:175588$10346 + attribute \src "libresoc.v:175384.14-175384.39" + process $proc$libresoc.v:175384$10346 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:175887.7-175887.20" - process $proc$libresoc.v:175887$10347 + attribute \src "libresoc.v:175683.7-175683.20" + process $proc$libresoc.v:175683$10347 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:175895.3-175896.35" - process $proc$libresoc.v:175895$10202 + attribute \src "libresoc.v:175691.3-175692.35" + process $proc$libresoc.v:175691$10202 assign { } { } assign $0\operation[1:0] \operation$next sync posedge \coresync_clk update \operation $0\operation[1:0] end - attribute \src "libresoc.v:175897.3-175898.49" - process $proc$libresoc.v:175897$10203 + attribute \src "libresoc.v:175693.3-175694.49" + process $proc$libresoc.v:175693$10203 assign { } { } assign $0\divisor_radicand[63:0] \divisor_radicand$next sync posedge \coresync_clk update \divisor_radicand $0\divisor_radicand[63:0] end - attribute \src "libresoc.v:175899.3-175900.33" - process $proc$libresoc.v:175899$10204 + attribute \src "libresoc.v:175695.3-175696.33" + process $proc$libresoc.v:175695$10204 assign { } { } assign $0\dividend[127:0] \dividend$next sync posedge \coresync_clk update \dividend $0\dividend[127:0] end - attribute \src "libresoc.v:175901.3-175902.39" - process $proc$libresoc.v:175901$10205 + attribute \src "libresoc.v:175697.3-175698.39" + process $proc$libresoc.v:175697$10205 assign { } { } assign $0\div_by_zero[0:0] \div_by_zero$next sync posedge \coresync_clk update \div_by_zero $0\div_by_zero[0:0] end - attribute \src "libresoc.v:175903.3-175904.43" - process $proc$libresoc.v:175903$10206 + attribute \src "libresoc.v:175699.3-175700.43" + process $proc$libresoc.v:175699$10206 assign { } { } assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next sync posedge \coresync_clk update \dive_abs_ov64 $0\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:175905.3-175906.43" - process $proc$libresoc.v:175905$10207 + attribute \src "libresoc.v:175701.3-175702.43" + process $proc$libresoc.v:175701$10207 assign { } { } assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next sync posedge \coresync_clk update \dive_abs_ov32 $0\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:175907.3-175908.41" - process $proc$libresoc.v:175907$10208 + attribute \src "libresoc.v:175703.3-175704.41" + process $proc$libresoc.v:175703$10208 assign { } { } assign $0\dividend_neg[0:0] \dividend_neg$next sync posedge \coresync_clk update \dividend_neg $0\dividend_neg[0:0] end - attribute \src "libresoc.v:175909.3-175910.39" - process $proc$libresoc.v:175909$10209 + attribute \src "libresoc.v:175705.3-175706.39" + process $proc$libresoc.v:175705$10209 assign { } { } assign $0\divisor_neg[0:0] \divisor_neg$next sync posedge \coresync_clk update \divisor_neg $0\divisor_neg[0:0] end - attribute \src "libresoc.v:175911.3-175912.29" - process $proc$libresoc.v:175911$10210 + attribute \src "libresoc.v:175707.3-175708.29" + process $proc$libresoc.v:175707$10210 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:175913.3-175914.21" - process $proc$libresoc.v:175913$10211 + attribute \src "libresoc.v:175709.3-175710.21" + process $proc$libresoc.v:175709$10211 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:175915.3-175916.21" - process $proc$libresoc.v:175915$10212 + attribute \src "libresoc.v:175711.3-175712.21" + process $proc$libresoc.v:175711$10212 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:175917.3-175918.59" - process $proc$libresoc.v:175917$10213 + attribute \src "libresoc.v:175713.3-175714.59" + process $proc$libresoc.v:175713$10213 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:175919.3-175920.55" - process $proc$libresoc.v:175919$10214 + attribute \src "libresoc.v:175715.3-175716.55" + process $proc$libresoc.v:175715$10214 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:175921.3-175922.69" - process $proc$libresoc.v:175921$10215 + attribute \src "libresoc.v:175717.3-175718.69" + process $proc$libresoc.v:175717$10215 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:175923.3-175924.65" - process $proc$libresoc.v:175923$10216 + attribute \src "libresoc.v:175719.3-175720.65" + process $proc$libresoc.v:175719$10216 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:175925.3-175926.53" - process $proc$libresoc.v:175925$10217 + attribute \src "libresoc.v:175721.3-175722.53" + process $proc$libresoc.v:175721$10217 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:175927.3-175928.53" - process $proc$libresoc.v:175927$10218 + attribute \src "libresoc.v:175723.3-175724.53" + process $proc$libresoc.v:175723$10218 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:175929.3-175930.53" - process $proc$libresoc.v:175929$10219 + attribute \src "libresoc.v:175725.3-175726.53" + process $proc$libresoc.v:175725$10219 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:175931.3-175932.53" - process $proc$libresoc.v:175931$10220 + attribute \src "libresoc.v:175727.3-175728.53" + process $proc$libresoc.v:175727$10220 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:175933.3-175934.59" - process $proc$libresoc.v:175933$10221 + attribute \src "libresoc.v:175729.3-175730.59" + process $proc$libresoc.v:175729$10221 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:175935.3-175936.53" - process $proc$libresoc.v:175935$10222 + attribute \src "libresoc.v:175731.3-175732.53" + process $proc$libresoc.v:175731$10222 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:175937.3-175938.63" - process $proc$libresoc.v:175937$10223 + attribute \src "libresoc.v:175733.3-175734.63" + process $proc$libresoc.v:175733$10223 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:175939.3-175940.61" - process $proc$libresoc.v:175939$10224 + attribute \src "libresoc.v:175735.3-175736.61" + process $proc$libresoc.v:175735$10224 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:175941.3-175942.59" - process $proc$libresoc.v:175941$10225 + attribute \src "libresoc.v:175737.3-175738.59" + process $proc$libresoc.v:175737$10225 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:175943.3-175944.65" - process $proc$libresoc.v:175943$10226 + attribute \src "libresoc.v:175739.3-175740.65" + process $proc$libresoc.v:175739$10226 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:175945.3-175946.57" - process $proc$libresoc.v:175945$10227 + attribute \src "libresoc.v:175741.3-175742.57" + process $proc$libresoc.v:175741$10227 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:175947.3-175948.59" - process $proc$libresoc.v:175947$10228 + attribute \src "libresoc.v:175743.3-175744.59" + process $proc$libresoc.v:175743$10228 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:175949.3-175950.57" - process $proc$libresoc.v:175949$10229 + attribute \src "libresoc.v:175745.3-175746.57" + process $proc$libresoc.v:175745$10229 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:175951.3-175952.49" - process $proc$libresoc.v:175951$10230 + attribute \src "libresoc.v:175747.3-175748.49" + process $proc$libresoc.v:175747$10230 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:175953.3-175954.27" - process $proc$libresoc.v:175953$10231 + attribute \src "libresoc.v:175749.3-175750.27" + process $proc$libresoc.v:175749$10231 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:175955.3-175956.29" - process $proc$libresoc.v:175955$10232 + attribute \src "libresoc.v:175751.3-175752.29" + process $proc$libresoc.v:175751$10232 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:176063.3-176075.6" - process $proc$libresoc.v:176063$10233 + attribute \src "libresoc.v:175859.3-175871.6" + process $proc$libresoc.v:175859$10233 assign { } { } assign { } { } assign $0\divisor_neg$next[0:0]$10234 $1\divisor_neg$next[0:0]$10235 - attribute \src "libresoc.v:176064.5-176064.29" + attribute \src "libresoc.v:175860.5-175860.29" switch \initial - attribute \src "libresoc.v:176064.9-176064.17" + attribute \src "libresoc.v:175860.9-175860.17" case 1'1 case end @@ -325313,14 +325147,14 @@ module \pipe_start sync always update \divisor_neg$next $0\divisor_neg$next[0:0]$10234 end - attribute \src "libresoc.v:176076.3-176088.6" - process $proc$libresoc.v:176076$10236 + attribute \src "libresoc.v:175872.3-175884.6" + process $proc$libresoc.v:175872$10236 assign { } { } assign { } { } assign $0\dividend_neg$next[0:0]$10237 $1\dividend_neg$next[0:0]$10238 - attribute \src "libresoc.v:176077.5-176077.29" + attribute \src "libresoc.v:175873.5-175873.29" switch \initial - attribute \src "libresoc.v:176077.9-176077.17" + attribute \src "libresoc.v:175873.9-175873.17" case 1'1 case end @@ -325340,14 +325174,14 @@ module \pipe_start sync always update \dividend_neg$next $0\dividend_neg$next[0:0]$10237 end - attribute \src "libresoc.v:176089.3-176101.6" - process $proc$libresoc.v:176089$10239 + attribute \src "libresoc.v:175885.3-175897.6" + process $proc$libresoc.v:175885$10239 assign { } { } assign { } { } assign $0\dive_abs_ov32$next[0:0]$10240 $1\dive_abs_ov32$next[0:0]$10241 - attribute \src "libresoc.v:176090.5-176090.29" + attribute \src "libresoc.v:175886.5-175886.29" switch \initial - attribute \src "libresoc.v:176090.9-176090.17" + attribute \src "libresoc.v:175886.9-175886.17" case 1'1 case end @@ -325367,14 +325201,14 @@ module \pipe_start sync always update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10240 end - attribute \src "libresoc.v:176102.3-176114.6" - process $proc$libresoc.v:176102$10242 + attribute \src "libresoc.v:175898.3-175910.6" + process $proc$libresoc.v:175898$10242 assign { } { } assign { } { } assign $0\dive_abs_ov64$next[0:0]$10243 $1\dive_abs_ov64$next[0:0]$10244 - attribute \src "libresoc.v:176103.5-176103.29" + attribute \src "libresoc.v:175899.5-175899.29" switch \initial - attribute \src "libresoc.v:176103.9-176103.17" + attribute \src "libresoc.v:175899.9-175899.17" case 1'1 case end @@ -325394,14 +325228,14 @@ module \pipe_start sync always update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10243 end - attribute \src "libresoc.v:176115.3-176127.6" - process $proc$libresoc.v:176115$10245 + attribute \src "libresoc.v:175911.3-175923.6" + process $proc$libresoc.v:175911$10245 assign { } { } assign { } { } assign $0\div_by_zero$next[0:0]$10246 $1\div_by_zero$next[0:0]$10247 - attribute \src "libresoc.v:176116.5-176116.29" + attribute \src "libresoc.v:175912.5-175912.29" switch \initial - attribute \src "libresoc.v:176116.9-176116.17" + attribute \src "libresoc.v:175912.9-175912.17" case 1'1 case end @@ -325421,14 +325255,14 @@ module \pipe_start sync always update \div_by_zero$next $0\div_by_zero$next[0:0]$10246 end - attribute \src "libresoc.v:176128.3-176140.6" - process $proc$libresoc.v:176128$10248 + attribute \src "libresoc.v:175924.3-175936.6" + process $proc$libresoc.v:175924$10248 assign { } { } assign { } { } assign $0\dividend$next[127:0]$10249 $1\dividend$next[127:0]$10250 - attribute \src "libresoc.v:176129.5-176129.29" + attribute \src "libresoc.v:175925.5-175925.29" switch \initial - attribute \src "libresoc.v:176129.9-176129.17" + attribute \src "libresoc.v:175925.9-175925.17" case 1'1 case end @@ -325448,14 +325282,14 @@ module \pipe_start sync always update \dividend$next $0\dividend$next[127:0]$10249 end - attribute \src "libresoc.v:176141.3-176153.6" - process $proc$libresoc.v:176141$10251 + attribute \src "libresoc.v:175937.3-175949.6" + process $proc$libresoc.v:175937$10251 assign { } { } assign { } { } assign $0\divisor_radicand$next[63:0]$10252 $1\divisor_radicand$next[63:0]$10253 - attribute \src "libresoc.v:176142.5-176142.29" + attribute \src "libresoc.v:175938.5-175938.29" switch \initial - attribute \src "libresoc.v:176142.9-176142.17" + attribute \src "libresoc.v:175938.9-175938.17" case 1'1 case end @@ -325475,14 +325309,14 @@ module \pipe_start sync always update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10252 end - attribute \src "libresoc.v:176154.3-176166.6" - process $proc$libresoc.v:176154$10254 + attribute \src "libresoc.v:175950.3-175962.6" + process $proc$libresoc.v:175950$10254 assign { } { } assign { } { } assign $0\operation$next[1:0]$10255 $1\operation$next[1:0]$10256 - attribute \src "libresoc.v:176155.5-176155.29" + attribute \src "libresoc.v:175951.5-175951.29" switch \initial - attribute \src "libresoc.v:176155.9-176155.17" + attribute \src "libresoc.v:175951.9-175951.17" case 1'1 case end @@ -325502,15 +325336,15 @@ module \pipe_start sync always update \operation$next $0\operation$next[1:0]$10255 end - attribute \src "libresoc.v:176167.3-176184.6" - process $proc$libresoc.v:176167$10257 + attribute \src "libresoc.v:175963.3-175980.6" + process $proc$libresoc.v:175963$10257 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$10258 $2\r_busy$next[0:0]$10260 - attribute \src "libresoc.v:176168.5-176168.29" + attribute \src "libresoc.v:175964.5-175964.29" switch \initial - attribute \src "libresoc.v:176168.9-176168.17" + attribute \src "libresoc.v:175964.9-175964.17" case 1'1 case end @@ -325539,14 +325373,14 @@ module \pipe_start sync always update \r_busy$next $0\r_busy$next[0:0]$10258 end - attribute \src "libresoc.v:176185.3-176197.6" - process $proc$libresoc.v:176185$10261 + attribute \src "libresoc.v:175981.3-175993.6" + process $proc$libresoc.v:175981$10261 assign { } { } assign { } { } assign $0\muxid$next[1:0]$10262 $1\muxid$next[1:0]$10263 - attribute \src "libresoc.v:176186.5-176186.29" + attribute \src "libresoc.v:175982.5-175982.29" switch \initial - attribute \src "libresoc.v:176186.9-176186.17" + attribute \src "libresoc.v:175982.9-175982.17" case 1'1 case end @@ -325566,8 +325400,8 @@ module \pipe_start sync always update \muxid$next $0\muxid$next[1:0]$10262 end - attribute \src "libresoc.v:176198.3-176239.6" - process $proc$libresoc.v:176198$10264 + attribute \src "libresoc.v:175994.3-176035.6" + process $proc$libresoc.v:175994$10264 assign { } { } assign { } { } assign { } { } @@ -325628,9 +325462,9 @@ module \pipe_start assign $0\logical_op__oe__ok$next[0:0]$10277 $2\logical_op__oe__ok$next[0:0]$10304 assign $0\logical_op__rc__ok$next[0:0]$10279 $2\logical_op__rc__ok$next[0:0]$10305 assign $0\logical_op__rc__rc$next[0:0]$10280 $2\logical_op__rc__rc$next[0:0]$10306 - attribute \src "libresoc.v:176199.5-176199.29" + attribute \src "libresoc.v:175995.5-175995.29" switch \initial - attribute \src "libresoc.v:176199.9-176199.17" + attribute \src "libresoc.v:175995.9-175995.17" case 1'1 case end @@ -325742,14 +325576,14 @@ module \pipe_start update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10281 update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10282 end - attribute \src "libresoc.v:176240.3-176252.6" - process $proc$libresoc.v:176240$10307 + attribute \src "libresoc.v:176036.3-176048.6" + process $proc$libresoc.v:176036$10307 assign { } { } assign { } { } assign $0\ra$next[63:0]$10308 $1\ra$next[63:0]$10309 - attribute \src "libresoc.v:176241.5-176241.29" + attribute \src "libresoc.v:176037.5-176037.29" switch \initial - attribute \src "libresoc.v:176241.9-176241.17" + attribute \src "libresoc.v:176037.9-176037.17" case 1'1 case end @@ -325769,14 +325603,14 @@ module \pipe_start sync always update \ra$next $0\ra$next[63:0]$10308 end - attribute \src "libresoc.v:176253.3-176265.6" - process $proc$libresoc.v:176253$10310 + attribute \src "libresoc.v:176049.3-176061.6" + process $proc$libresoc.v:176049$10310 assign { } { } assign { } { } assign $0\rb$next[63:0]$10311 $1\rb$next[63:0]$10312 - attribute \src "libresoc.v:176254.5-176254.29" + attribute \src "libresoc.v:176050.5-176050.29" switch \initial - attribute \src "libresoc.v:176254.9-176254.17" + attribute \src "libresoc.v:176050.9-176050.17" case 1'1 case end @@ -325796,14 +325630,14 @@ module \pipe_start sync always update \rb$next $0\rb$next[63:0]$10311 end - attribute \src "libresoc.v:176266.3-176278.6" - process $proc$libresoc.v:176266$10313 + attribute \src "libresoc.v:176062.3-176074.6" + process $proc$libresoc.v:176062$10313 assign { } { } assign { } { } assign $0\xer_so$next[0:0]$10314 $1\xer_so$next[0:0]$10315 - attribute \src "libresoc.v:176267.5-176267.29" + attribute \src "libresoc.v:176063.5-176063.29" switch \initial - attribute \src "libresoc.v:176267.9-176267.17" + attribute \src "libresoc.v:176063.9-176063.17" case 1'1 case end @@ -325823,7 +325657,7 @@ module \pipe_start sync always update \xer_so$next $0\xer_so$next[0:0]$10314 end - connect \$66 $and$libresoc.v:175894$10201_Y + connect \$66 $and$libresoc.v:175690$10201_Y connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 connect \p_ready_o \n_i_rdy_data @@ -325855,319 +325689,191 @@ module \pipe_start connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:176313.1-176357.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.pll" -attribute \generator "nMigen" -module \pll - attribute \src "libresoc.v:176314.7-176314.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:176346.3-176355.6" - wire $0\pll_18_o[0:0] - attribute \src "libresoc.v:176336.3-176345.6" - wire $0\pll_lck_o[0:0] - attribute \src "libresoc.v:176346.3-176355.6" - wire $1\pll_18_o[0:0] - attribute \src "libresoc.v:176336.3-176345.6" - wire $1\pll_lck_o[0:0] - attribute \src "libresoc.v:176333.17-176333.105" - wire $eq$libresoc.v:176333$10348_Y - attribute \src "libresoc.v:176334.17-176334.105" - wire $eq$libresoc.v:176334$10349_Y - attribute \src "libresoc.v:176335.17-176335.98" - wire $not$libresoc.v:176335$10350_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" - wire input 1 \clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" - wire output 5 \clk_pll_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 3 \clk_sel_i - attribute \src "libresoc.v:176314.7-176314.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" - wire output 2 \pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 4 \pll_lck_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:176333$10348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \clk_sel_i - connect \B 2'00 - connect \Y $eq$libresoc.v:176333$10348_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:176334$10349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \clk_sel_i - connect \B 2'00 - connect \Y $eq$libresoc.v:176334$10349_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - cell $not $not$libresoc.v:176335$10350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clk_24_i - connect \Y $not$libresoc.v:176335$10350_Y - end - attribute \src "libresoc.v:176314.7-176314.20" - process $proc$libresoc.v:176314$10353 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:176336.3-176345.6" - process $proc$libresoc.v:176336$10351 - assign { } { } - assign { } { } - assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] - attribute \src "libresoc.v:176337.5-176337.29" - switch \initial - attribute \src "libresoc.v:176337.9-176337.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pll_lck_o[0:0] \clk_24_i - case - assign $1\pll_lck_o[0:0] 1'0 - end - sync always - update \pll_lck_o $0\pll_lck_o[0:0] - end - attribute \src "libresoc.v:176346.3-176355.6" - process $proc$libresoc.v:176346$10352 - assign { } { } - assign { } { } - assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] - attribute \src "libresoc.v:176347.5-176347.29" - switch \initial - attribute \src "libresoc.v:176347.9-176347.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pll_18_o[0:0] \$5 - case - assign $1\pll_18_o[0:0] 1'0 - end - sync always - update \pll_18_o $0\pll_18_o[0:0] - end - connect \$1 $eq$libresoc.v:176333$10348_Y - connect \$3 $eq$libresoc.v:176334$10349_Y - connect \$5 $not$libresoc.v:176335$10350_Y - connect \clk_pll_o \clk_24_i -end -attribute \src "libresoc.v:176361.1-177003.10" +attribute \src "libresoc.v:176109.1-176751.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" attribute \generator "nMigen" module \popcount - attribute \src "libresoc.v:176362.7-176362.20" + attribute \src "libresoc.v:176110.7-176110.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176850.3-176876.6" + attribute \src "libresoc.v:176598.3-176624.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:176850.3-176876.6" + attribute \src "libresoc.v:176598.3-176624.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:176774.19-176774.132" - wire width 4 $add$libresoc.v:176774$10354_Y - attribute \src "libresoc.v:176775.19-176775.132" - wire width 4 $add$libresoc.v:176775$10355_Y - attribute \src "libresoc.v:176776.19-176776.132" - wire width 4 $add$libresoc.v:176776$10356_Y - attribute \src "libresoc.v:176777.19-176777.132" - wire width 4 $add$libresoc.v:176777$10357_Y - attribute \src "libresoc.v:176778.19-176778.134" - wire width 4 $add$libresoc.v:176778$10358_Y - attribute \src "libresoc.v:176779.19-176779.134" - wire width 4 $add$libresoc.v:176779$10359_Y - attribute \src "libresoc.v:176780.18-176780.125" - wire width 3 $add$libresoc.v:176780$10360_Y - attribute \src "libresoc.v:176781.19-176781.134" - wire width 4 $add$libresoc.v:176781$10361_Y - attribute \src "libresoc.v:176782.19-176782.134" - wire width 4 $add$libresoc.v:176782$10362_Y - attribute \src "libresoc.v:176783.19-176783.134" - wire width 4 $add$libresoc.v:176783$10363_Y - attribute \src "libresoc.v:176784.19-176784.134" - wire width 4 $add$libresoc.v:176784$10364_Y - attribute \src "libresoc.v:176785.19-176785.134" - wire width 4 $add$libresoc.v:176785$10365_Y - attribute \src "libresoc.v:176786.19-176786.134" - wire width 4 $add$libresoc.v:176786$10366_Y - attribute \src "libresoc.v:176787.19-176787.134" - wire width 4 $add$libresoc.v:176787$10367_Y - attribute \src "libresoc.v:176788.19-176788.134" - wire width 4 $add$libresoc.v:176788$10368_Y - attribute \src "libresoc.v:176789.19-176789.134" - wire width 4 $add$libresoc.v:176789$10369_Y - attribute \src "libresoc.v:176790.19-176790.132" - wire width 5 $add$libresoc.v:176790$10370_Y - attribute \src "libresoc.v:176791.18-176791.125" - wire width 3 $add$libresoc.v:176791$10371_Y - attribute \src "libresoc.v:176792.19-176792.132" - wire width 5 $add$libresoc.v:176792$10372_Y - attribute \src "libresoc.v:176793.19-176793.132" - wire width 5 $add$libresoc.v:176793$10373_Y - attribute \src "libresoc.v:176794.19-176794.132" - wire width 5 $add$libresoc.v:176794$10374_Y - attribute \src "libresoc.v:176795.19-176795.132" - wire width 5 $add$libresoc.v:176795$10375_Y - attribute \src "libresoc.v:176796.19-176796.134" - wire width 5 $add$libresoc.v:176796$10376_Y - attribute \src "libresoc.v:176797.19-176797.134" - wire width 5 $add$libresoc.v:176797$10377_Y - attribute \src "libresoc.v:176798.19-176798.134" - wire width 5 $add$libresoc.v:176798$10378_Y - attribute \src "libresoc.v:176799.19-176799.132" - wire width 6 $add$libresoc.v:176799$10379_Y - attribute \src "libresoc.v:176800.19-176800.132" - wire width 6 $add$libresoc.v:176800$10380_Y - attribute \src "libresoc.v:176801.19-176801.132" - wire width 6 $add$libresoc.v:176801$10381_Y - attribute \src "libresoc.v:176802.18-176802.127" - wire width 3 $add$libresoc.v:176802$10382_Y - attribute \src "libresoc.v:176803.19-176803.132" - wire width 6 $add$libresoc.v:176803$10383_Y - attribute \src "libresoc.v:176804.19-176804.132" - wire width 7 $add$libresoc.v:176804$10384_Y - attribute \src "libresoc.v:176805.19-176805.132" - wire width 7 $add$libresoc.v:176805$10385_Y - attribute \src "libresoc.v:176806.19-176806.132" - wire width 8 $add$libresoc.v:176806$10386_Y - attribute \src "libresoc.v:176817.18-176817.127" - wire width 3 $add$libresoc.v:176817$10405_Y - attribute \src "libresoc.v:176821.18-176821.127" - wire width 3 $add$libresoc.v:176821$10412_Y - attribute \src "libresoc.v:176822.18-176822.127" - wire width 3 $add$libresoc.v:176822$10413_Y - attribute \src "libresoc.v:176823.17-176823.124" - wire width 3 $add$libresoc.v:176823$10414_Y - attribute \src "libresoc.v:176824.18-176824.127" - wire width 3 $add$libresoc.v:176824$10415_Y - attribute \src "libresoc.v:176825.18-176825.127" - wire width 3 $add$libresoc.v:176825$10416_Y - attribute \src "libresoc.v:176826.18-176826.127" - wire width 3 $add$libresoc.v:176826$10417_Y - attribute \src "libresoc.v:176827.18-176827.127" - wire width 3 $add$libresoc.v:176827$10418_Y - attribute \src "libresoc.v:176828.18-176828.127" - wire width 3 $add$libresoc.v:176828$10419_Y - attribute \src "libresoc.v:176829.18-176829.127" - wire width 3 $add$libresoc.v:176829$10420_Y - attribute \src "libresoc.v:176830.18-176830.127" - wire width 3 $add$libresoc.v:176830$10421_Y - attribute \src "libresoc.v:176831.18-176831.127" - wire width 3 $add$libresoc.v:176831$10422_Y - attribute \src "libresoc.v:176832.18-176832.127" - wire width 3 $add$libresoc.v:176832$10423_Y - attribute \src "libresoc.v:176833.18-176833.127" - wire width 3 $add$libresoc.v:176833$10424_Y - attribute \src "libresoc.v:176834.17-176834.124" - wire width 3 $add$libresoc.v:176834$10425_Y - attribute \src "libresoc.v:176835.18-176835.127" - wire width 3 $add$libresoc.v:176835$10426_Y - attribute \src "libresoc.v:176836.18-176836.127" - wire width 3 $add$libresoc.v:176836$10427_Y - attribute \src "libresoc.v:176837.18-176837.127" - wire width 3 $add$libresoc.v:176837$10428_Y - attribute \src "libresoc.v:176838.18-176838.127" - wire width 3 $add$libresoc.v:176838$10429_Y - attribute \src "libresoc.v:176839.18-176839.127" - wire width 3 $add$libresoc.v:176839$10430_Y - attribute \src "libresoc.v:176840.18-176840.127" - wire width 3 $add$libresoc.v:176840$10431_Y - attribute \src "libresoc.v:176841.18-176841.127" - wire width 3 $add$libresoc.v:176841$10432_Y - attribute \src "libresoc.v:176842.18-176842.127" - wire width 3 $add$libresoc.v:176842$10433_Y - attribute \src "libresoc.v:176843.18-176843.127" - wire width 3 $add$libresoc.v:176843$10434_Y - attribute \src "libresoc.v:176844.18-176844.127" - wire width 3 $add$libresoc.v:176844$10435_Y - attribute \src "libresoc.v:176845.17-176845.124" - wire width 3 $add$libresoc.v:176845$10436_Y - attribute \src "libresoc.v:176846.18-176846.127" - wire width 3 $add$libresoc.v:176846$10437_Y - attribute \src "libresoc.v:176847.18-176847.127" - wire width 3 $add$libresoc.v:176847$10438_Y - attribute \src "libresoc.v:176848.18-176848.127" - wire width 3 $add$libresoc.v:176848$10439_Y - attribute \src "libresoc.v:176849.18-176849.131" - wire width 4 $add$libresoc.v:176849$10440_Y - attribute \src "libresoc.v:176807.19-176807.111" - wire $eq$libresoc.v:176807$10387_Y - attribute \src "libresoc.v:176808.19-176808.111" - wire $eq$libresoc.v:176808$10388_Y - attribute \src "libresoc.v:176809.19-176809.104" - wire width 8 $extend$libresoc.v:176809$10389_Y - attribute \src "libresoc.v:176810.19-176810.104" - wire width 8 $extend$libresoc.v:176810$10391_Y - attribute \src "libresoc.v:176811.19-176811.104" - wire width 8 $extend$libresoc.v:176811$10393_Y - attribute \src "libresoc.v:176812.19-176812.104" - wire width 8 $extend$libresoc.v:176812$10395_Y - attribute \src "libresoc.v:176813.19-176813.104" - wire width 8 $extend$libresoc.v:176813$10397_Y - attribute \src "libresoc.v:176814.19-176814.104" - wire width 8 $extend$libresoc.v:176814$10399_Y - attribute \src "libresoc.v:176815.19-176815.104" - wire width 8 $extend$libresoc.v:176815$10401_Y - attribute \src "libresoc.v:176816.19-176816.104" - wire width 8 $extend$libresoc.v:176816$10403_Y - attribute \src "libresoc.v:176818.19-176818.104" - wire width 32 $extend$libresoc.v:176818$10406_Y - attribute \src "libresoc.v:176819.19-176819.104" - wire width 32 $extend$libresoc.v:176819$10408_Y - attribute \src "libresoc.v:176820.19-176820.104" - wire width 64 $extend$libresoc.v:176820$10410_Y - attribute \src "libresoc.v:176809.19-176809.104" - wire width 8 $pos$libresoc.v:176809$10390_Y - attribute \src "libresoc.v:176810.19-176810.104" - wire width 8 $pos$libresoc.v:176810$10392_Y - attribute \src "libresoc.v:176811.19-176811.104" - wire width 8 $pos$libresoc.v:176811$10394_Y - attribute \src "libresoc.v:176812.19-176812.104" - wire width 8 $pos$libresoc.v:176812$10396_Y - attribute \src "libresoc.v:176813.19-176813.104" - wire width 8 $pos$libresoc.v:176813$10398_Y - attribute \src "libresoc.v:176814.19-176814.104" - wire width 8 $pos$libresoc.v:176814$10400_Y - attribute \src "libresoc.v:176815.19-176815.104" - wire width 8 $pos$libresoc.v:176815$10402_Y - attribute \src "libresoc.v:176816.19-176816.104" - wire width 8 $pos$libresoc.v:176816$10404_Y - attribute \src "libresoc.v:176818.19-176818.104" - wire width 32 $pos$libresoc.v:176818$10407_Y - attribute \src "libresoc.v:176819.19-176819.104" - wire width 32 $pos$libresoc.v:176819$10409_Y - attribute \src "libresoc.v:176820.19-176820.104" - wire width 64 $pos$libresoc.v:176820$10411_Y + attribute \src "libresoc.v:176522.19-176522.132" + wire width 4 $add$libresoc.v:176522$10348_Y + attribute \src "libresoc.v:176523.19-176523.132" + wire width 4 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"libresoc.v:176597.18-176597.131" + wire width 4 $add$libresoc.v:176597$10434_Y + attribute \src "libresoc.v:176555.19-176555.111" + wire $eq$libresoc.v:176555$10381_Y + attribute \src "libresoc.v:176556.19-176556.111" + wire $eq$libresoc.v:176556$10382_Y + attribute \src "libresoc.v:176557.19-176557.104" + wire width 8 $extend$libresoc.v:176557$10383_Y + attribute \src "libresoc.v:176558.19-176558.104" + wire width 8 $extend$libresoc.v:176558$10385_Y + attribute \src "libresoc.v:176559.19-176559.104" + wire width 8 $extend$libresoc.v:176559$10387_Y + attribute \src "libresoc.v:176560.19-176560.104" + wire width 8 $extend$libresoc.v:176560$10389_Y + attribute \src "libresoc.v:176561.19-176561.104" + wire width 8 $extend$libresoc.v:176561$10391_Y + attribute \src "libresoc.v:176562.19-176562.104" + wire width 8 $extend$libresoc.v:176562$10393_Y + attribute \src "libresoc.v:176563.19-176563.104" + wire width 8 $extend$libresoc.v:176563$10395_Y + attribute \src "libresoc.v:176564.19-176564.104" + wire width 8 $extend$libresoc.v:176564$10397_Y + attribute \src "libresoc.v:176566.19-176566.104" + wire width 32 $extend$libresoc.v:176566$10400_Y + attribute \src "libresoc.v:176567.19-176567.104" + wire width 32 $extend$libresoc.v:176567$10402_Y + attribute \src "libresoc.v:176568.19-176568.104" + wire width 64 $extend$libresoc.v:176568$10404_Y + attribute \src "libresoc.v:176557.19-176557.104" + wire width 8 $pos$libresoc.v:176557$10384_Y + attribute \src "libresoc.v:176558.19-176558.104" + wire width 8 $pos$libresoc.v:176558$10386_Y + attribute \src "libresoc.v:176559.19-176559.104" + wire width 8 $pos$libresoc.v:176559$10388_Y + attribute \src "libresoc.v:176560.19-176560.104" + wire width 8 $pos$libresoc.v:176560$10390_Y + attribute \src "libresoc.v:176561.19-176561.104" + wire width 8 $pos$libresoc.v:176561$10392_Y + attribute \src "libresoc.v:176562.19-176562.104" + wire width 8 $pos$libresoc.v:176562$10394_Y + attribute \src "libresoc.v:176563.19-176563.104" + wire width 8 $pos$libresoc.v:176563$10396_Y + attribute \src "libresoc.v:176564.19-176564.104" + wire width 8 $pos$libresoc.v:176564$10398_Y + attribute \src "libresoc.v:176566.19-176566.104" + wire width 32 $pos$libresoc.v:176566$10401_Y + attribute \src "libresoc.v:176567.19-176567.104" + wire width 32 $pos$libresoc.v:176567$10403_Y + attribute \src "libresoc.v:176568.19-176568.104" + wire width 64 $pos$libresoc.v:176568$10405_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" @@ -326450,7 +326156,7 @@ module \popcount wire width 64 input 3 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" wire width 64 input 1 \data_len - attribute \src "libresoc.v:176362.7-176362.15" + attribute \src "libresoc.v:176110.7-176110.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" wire width 64 output 2 \o @@ -326581,7 +326287,7 @@ module \popcount attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 7 \pop_7_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176774$10354 + cell $add $add$libresoc.v:176522$10348 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326589,10 +326295,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_2 } connect \B { 2'00 \pop_2_3 } - connect \Y $add$libresoc.v:176774$10354_Y + connect \Y $add$libresoc.v:176522$10348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176775$10355 + cell $add $add$libresoc.v:176523$10349 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326600,10 +326306,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_4 } connect \B { 2'00 \pop_2_5 } - connect \Y $add$libresoc.v:176775$10355_Y + connect \Y $add$libresoc.v:176523$10349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176776$10356 + cell $add $add$libresoc.v:176524$10350 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326611,10 +326317,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_6 } connect \B { 2'00 \pop_2_7 } - connect \Y $add$libresoc.v:176776$10356_Y + connect \Y $add$libresoc.v:176524$10350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176777$10357 + cell $add $add$libresoc.v:176525$10351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326622,10 +326328,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_8 } connect \B { 2'00 \pop_2_9 } - connect \Y $add$libresoc.v:176777$10357_Y + connect \Y $add$libresoc.v:176525$10351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176778$10358 + cell $add $add$libresoc.v:176526$10352 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326633,10 +326339,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_10 } connect \B { 2'00 \pop_2_11 } - connect \Y $add$libresoc.v:176778$10358_Y + connect \Y $add$libresoc.v:176526$10352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176779$10359 + cell $add $add$libresoc.v:176527$10353 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326644,10 +326350,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_12 } connect \B { 2'00 \pop_2_13 } - connect \Y $add$libresoc.v:176779$10359_Y + connect \Y $add$libresoc.v:176527$10353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176780$10360 + cell $add $add$libresoc.v:176528$10354 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -326655,10 +326361,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [6] } connect \B { 2'00 \a [7] } - connect \Y $add$libresoc.v:176780$10360_Y + connect \Y $add$libresoc.v:176528$10354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176781$10361 + cell $add $add$libresoc.v:176529$10355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326666,10 +326372,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_14 } connect \B { 2'00 \pop_2_15 } - connect \Y $add$libresoc.v:176781$10361_Y + connect \Y $add$libresoc.v:176529$10355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176782$10362 + cell $add $add$libresoc.v:176530$10356 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326677,10 +326383,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_16 } connect \B { 2'00 \pop_2_17 } - connect \Y $add$libresoc.v:176782$10362_Y + connect \Y $add$libresoc.v:176530$10356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176783$10363 + cell $add $add$libresoc.v:176531$10357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326688,10 +326394,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_18 } connect \B { 2'00 \pop_2_19 } - connect \Y $add$libresoc.v:176783$10363_Y + connect \Y $add$libresoc.v:176531$10357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176784$10364 + cell $add $add$libresoc.v:176532$10358 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326699,10 +326405,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_20 } connect \B { 2'00 \pop_2_21 } - connect \Y $add$libresoc.v:176784$10364_Y + connect \Y $add$libresoc.v:176532$10358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176785$10365 + cell $add $add$libresoc.v:176533$10359 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326710,10 +326416,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_22 } connect \B { 2'00 \pop_2_23 } - connect \Y $add$libresoc.v:176785$10365_Y + connect \Y $add$libresoc.v:176533$10359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176786$10366 + cell $add $add$libresoc.v:176534$10360 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326721,10 +326427,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_24 } connect \B { 2'00 \pop_2_25 } - connect \Y $add$libresoc.v:176786$10366_Y + connect \Y $add$libresoc.v:176534$10360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176787$10367 + cell $add $add$libresoc.v:176535$10361 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326732,10 +326438,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_26 } connect \B { 2'00 \pop_2_27 } - connect \Y $add$libresoc.v:176787$10367_Y + connect \Y $add$libresoc.v:176535$10361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176788$10368 + cell $add $add$libresoc.v:176536$10362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326743,10 +326449,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_28 } connect \B { 2'00 \pop_2_29 } - connect \Y $add$libresoc.v:176788$10368_Y + connect \Y $add$libresoc.v:176536$10362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176789$10369 + cell $add $add$libresoc.v:176537$10363 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -326754,10 +326460,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_30 } connect \B { 2'00 \pop_2_31 } - connect \Y $add$libresoc.v:176789$10369_Y + connect \Y $add$libresoc.v:176537$10363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176790$10370 + cell $add $add$libresoc.v:176538$10364 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -326765,10 +326471,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_0 } connect \B { 2'00 \pop_3_1 } - connect \Y $add$libresoc.v:176790$10370_Y + connect \Y $add$libresoc.v:176538$10364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176791$10371 + cell $add $add$libresoc.v:176539$10365 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -326776,10 +326482,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [8] } connect \B { 2'00 \a [9] } - connect \Y $add$libresoc.v:176791$10371_Y + connect \Y $add$libresoc.v:176539$10365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176792$10372 + cell $add $add$libresoc.v:176540$10366 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -326787,10 +326493,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_2 } connect \B { 2'00 \pop_3_3 } - connect \Y $add$libresoc.v:176792$10372_Y + connect \Y $add$libresoc.v:176540$10366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176793$10373 + cell $add $add$libresoc.v:176541$10367 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -326798,10 +326504,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_4 } connect \B { 2'00 \pop_3_5 } - connect \Y $add$libresoc.v:176793$10373_Y + connect \Y $add$libresoc.v:176541$10367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176794$10374 + cell $add $add$libresoc.v:176542$10368 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -326809,10 +326515,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_6 } connect \B { 2'00 \pop_3_7 } - connect \Y $add$libresoc.v:176794$10374_Y + connect \Y $add$libresoc.v:176542$10368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176795$10375 + cell $add $add$libresoc.v:176543$10369 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -326820,10 +326526,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_8 } connect \B { 2'00 \pop_3_9 } - connect \Y $add$libresoc.v:176795$10375_Y + connect \Y $add$libresoc.v:176543$10369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176796$10376 + cell $add $add$libresoc.v:176544$10370 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -326831,10 +326537,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_10 } connect \B { 2'00 \pop_3_11 } - connect \Y $add$libresoc.v:176796$10376_Y + connect \Y $add$libresoc.v:176544$10370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176797$10377 + cell $add $add$libresoc.v:176545$10371 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -326842,10 +326548,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_12 } connect \B { 2'00 \pop_3_13 } - connect \Y $add$libresoc.v:176797$10377_Y + connect \Y $add$libresoc.v:176545$10371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176798$10378 + cell $add $add$libresoc.v:176546$10372 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -326853,10 +326559,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_14 } connect \B { 2'00 \pop_3_15 } - connect \Y $add$libresoc.v:176798$10378_Y + connect \Y $add$libresoc.v:176546$10372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176799$10379 + cell $add $add$libresoc.v:176547$10373 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -326864,10 +326570,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_0 } connect \B { 2'00 \pop_4_1 } - connect \Y $add$libresoc.v:176799$10379_Y + connect \Y $add$libresoc.v:176547$10373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176800$10380 + cell $add $add$libresoc.v:176548$10374 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -326875,10 +326581,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_2 } connect \B { 2'00 \pop_4_3 } - connect \Y $add$libresoc.v:176800$10380_Y + connect \Y $add$libresoc.v:176548$10374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176801$10381 + cell $add $add$libresoc.v:176549$10375 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -326886,10 +326592,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_4 } connect \B { 2'00 \pop_4_5 } - connect \Y $add$libresoc.v:176801$10381_Y + connect \Y $add$libresoc.v:176549$10375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176802$10382 + cell $add $add$libresoc.v:176550$10376 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -326897,10 +326603,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [10] } connect \B { 2'00 \a [11] } - connect \Y $add$libresoc.v:176802$10382_Y + connect \Y $add$libresoc.v:176550$10376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176803$10383 + cell $add $add$libresoc.v:176551$10377 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -326908,10 +326614,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_6 } connect \B { 2'00 \pop_4_7 } - connect \Y $add$libresoc.v:176803$10383_Y + connect \Y $add$libresoc.v:176551$10377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176804$10384 + cell $add $add$libresoc.v:176552$10378 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326919,10 +326625,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_0 } connect \B { 2'00 \pop_5_1 } - connect \Y $add$libresoc.v:176804$10384_Y + connect \Y $add$libresoc.v:176552$10378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176805$10385 + cell $add $add$libresoc.v:176553$10379 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326930,10 +326636,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_2 } connect \B { 2'00 \pop_5_3 } - connect \Y $add$libresoc.v:176805$10385_Y + connect \Y $add$libresoc.v:176553$10379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176806$10386 + cell $add $add$libresoc.v:176554$10380 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -326941,10 +326647,10 @@ module \popcount parameter \Y_WIDTH 8 connect \A { 2'00 \pop_6_0 } connect \B { 2'00 \pop_6_1 } - connect \Y $add$libresoc.v:176806$10386_Y + connect \Y $add$libresoc.v:176554$10380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176817$10405 + cell $add $add$libresoc.v:176565$10399 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -326952,10 +326658,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [12] } connect \B { 2'00 \a [13] } - connect \Y $add$libresoc.v:176817$10405_Y + connect \Y $add$libresoc.v:176565$10399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176821$10412 + cell $add $add$libresoc.v:176569$10406 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -326963,10 +326669,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [14] } connect \B { 2'00 \a [15] } - connect \Y $add$libresoc.v:176821$10412_Y + connect \Y $add$libresoc.v:176569$10406_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176822$10413 + cell $add $add$libresoc.v:176570$10407 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -326974,10 +326680,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [16] } connect \B { 2'00 \a [17] } - connect \Y $add$libresoc.v:176822$10413_Y + connect \Y $add$libresoc.v:176570$10407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176823$10414 + cell $add $add$libresoc.v:176571$10408 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -326985,10 +326691,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [0] } connect \B { 2'00 \a [1] } - connect \Y $add$libresoc.v:176823$10414_Y + connect \Y $add$libresoc.v:176571$10408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176824$10415 + cell $add $add$libresoc.v:176572$10409 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -326996,10 +326702,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [18] } connect \B { 2'00 \a [19] } - connect \Y $add$libresoc.v:176824$10415_Y + connect \Y $add$libresoc.v:176572$10409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176825$10416 + cell $add $add$libresoc.v:176573$10410 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327007,10 +326713,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [20] } connect \B { 2'00 \a [21] } - connect \Y $add$libresoc.v:176825$10416_Y + connect \Y $add$libresoc.v:176573$10410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176826$10417 + cell $add $add$libresoc.v:176574$10411 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327018,10 +326724,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [22] } connect \B { 2'00 \a [23] } - connect \Y $add$libresoc.v:176826$10417_Y + connect \Y $add$libresoc.v:176574$10411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176827$10418 + cell $add $add$libresoc.v:176575$10412 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327029,10 +326735,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [24] } connect \B { 2'00 \a [25] } - connect \Y $add$libresoc.v:176827$10418_Y + connect \Y $add$libresoc.v:176575$10412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176828$10419 + cell $add $add$libresoc.v:176576$10413 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327040,10 +326746,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [26] } connect \B { 2'00 \a [27] } - connect \Y $add$libresoc.v:176828$10419_Y + connect \Y $add$libresoc.v:176576$10413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176829$10420 + cell $add $add$libresoc.v:176577$10414 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327051,10 +326757,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [28] } connect \B { 2'00 \a [29] } - connect \Y $add$libresoc.v:176829$10420_Y + connect \Y $add$libresoc.v:176577$10414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176830$10421 + cell $add $add$libresoc.v:176578$10415 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327062,10 +326768,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [30] } connect \B { 2'00 \a [31] } - connect \Y $add$libresoc.v:176830$10421_Y + connect \Y $add$libresoc.v:176578$10415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176831$10422 + cell $add $add$libresoc.v:176579$10416 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327073,10 +326779,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [32] } connect \B { 2'00 \a [33] } - connect \Y $add$libresoc.v:176831$10422_Y + connect \Y $add$libresoc.v:176579$10416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176832$10423 + cell $add $add$libresoc.v:176580$10417 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327084,10 +326790,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [34] } connect \B { 2'00 \a [35] } - connect \Y $add$libresoc.v:176832$10423_Y + connect \Y $add$libresoc.v:176580$10417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176833$10424 + cell $add $add$libresoc.v:176581$10418 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327095,10 +326801,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [36] } connect \B { 2'00 \a [37] } - connect \Y $add$libresoc.v:176833$10424_Y + connect \Y $add$libresoc.v:176581$10418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176834$10425 + cell $add $add$libresoc.v:176582$10419 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327106,10 +326812,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [2] } connect \B { 2'00 \a [3] } - connect \Y $add$libresoc.v:176834$10425_Y + connect \Y $add$libresoc.v:176582$10419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176835$10426 + cell $add $add$libresoc.v:176583$10420 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327117,10 +326823,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [38] } connect \B { 2'00 \a [39] } - connect \Y $add$libresoc.v:176835$10426_Y + connect \Y $add$libresoc.v:176583$10420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176836$10427 + cell $add $add$libresoc.v:176584$10421 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327128,10 +326834,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [40] } connect \B { 2'00 \a [41] } - connect \Y $add$libresoc.v:176836$10427_Y + connect \Y $add$libresoc.v:176584$10421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176837$10428 + cell $add $add$libresoc.v:176585$10422 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327139,10 +326845,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [42] } connect \B { 2'00 \a [43] } - connect \Y $add$libresoc.v:176837$10428_Y + connect \Y $add$libresoc.v:176585$10422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176838$10429 + cell $add $add$libresoc.v:176586$10423 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327150,10 +326856,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [44] } connect \B { 2'00 \a [45] } - connect \Y $add$libresoc.v:176838$10429_Y + connect \Y $add$libresoc.v:176586$10423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176839$10430 + cell $add $add$libresoc.v:176587$10424 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327161,10 +326867,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [46] } connect \B { 2'00 \a [47] } - connect \Y $add$libresoc.v:176839$10430_Y + connect \Y $add$libresoc.v:176587$10424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176840$10431 + cell $add $add$libresoc.v:176588$10425 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327172,10 +326878,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [48] } connect \B { 2'00 \a [49] } - connect \Y $add$libresoc.v:176840$10431_Y + connect \Y $add$libresoc.v:176588$10425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176841$10432 + cell $add $add$libresoc.v:176589$10426 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327183,10 +326889,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [50] } connect \B { 2'00 \a [51] } - connect \Y $add$libresoc.v:176841$10432_Y + connect \Y $add$libresoc.v:176589$10426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176842$10433 + cell $add $add$libresoc.v:176590$10427 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327194,10 +326900,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [52] } connect \B { 2'00 \a [53] } - connect \Y $add$libresoc.v:176842$10433_Y + connect \Y $add$libresoc.v:176590$10427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176843$10434 + cell $add $add$libresoc.v:176591$10428 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327205,10 +326911,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [54] } connect \B { 2'00 \a [55] } - connect \Y $add$libresoc.v:176843$10434_Y + connect \Y $add$libresoc.v:176591$10428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176844$10435 + cell $add $add$libresoc.v:176592$10429 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327216,10 +326922,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [56] } connect \B { 2'00 \a [57] } - connect \Y $add$libresoc.v:176844$10435_Y + connect \Y $add$libresoc.v:176592$10429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176845$10436 + cell $add $add$libresoc.v:176593$10430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327227,10 +326933,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [4] } connect \B { 2'00 \a [5] } - connect \Y $add$libresoc.v:176845$10436_Y + connect \Y $add$libresoc.v:176593$10430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176846$10437 + cell $add $add$libresoc.v:176594$10431 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327238,10 +326944,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [58] } connect \B { 2'00 \a [59] } - connect \Y $add$libresoc.v:176846$10437_Y + connect \Y $add$libresoc.v:176594$10431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176847$10438 + cell $add $add$libresoc.v:176595$10432 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327249,10 +326955,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [60] } connect \B { 2'00 \a [61] } - connect \Y $add$libresoc.v:176847$10438_Y + connect \Y $add$libresoc.v:176595$10432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176848$10439 + cell $add $add$libresoc.v:176596$10433 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -327260,10 +326966,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [62] } connect \B { 2'00 \a [63] } - connect \Y $add$libresoc.v:176848$10439_Y + connect \Y $add$libresoc.v:176596$10433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:176849$10440 + cell $add $add$libresoc.v:176597$10434 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -327271,10 +326977,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_0 } connect \B { 2'00 \pop_2_1 } - connect \Y $add$libresoc.v:176849$10440_Y + connect \Y $add$libresoc.v:176597$10434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $eq$libresoc.v:176807$10387 + cell $eq $eq$libresoc.v:176555$10381 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -327282,10 +326988,10 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 1'1 - connect \Y $eq$libresoc.v:176807$10387_Y + connect \Y $eq$libresoc.v:176555$10381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $eq$libresoc.v:176808$10388 + cell $eq $eq$libresoc.v:176556$10382 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -327293,199 +326999,199 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 3'100 - connect \Y $eq$libresoc.v:176808$10388_Y + connect \Y $eq$libresoc.v:176556$10382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:176809$10389 + cell $pos $extend$libresoc.v:176557$10383 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_0 - connect \Y $extend$libresoc.v:176809$10389_Y + connect \Y $extend$libresoc.v:176557$10383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:176810$10391 + cell $pos $extend$libresoc.v:176558$10385 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_1 - connect \Y $extend$libresoc.v:176810$10391_Y + connect \Y $extend$libresoc.v:176558$10385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:176811$10393 + cell $pos $extend$libresoc.v:176559$10387 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_2 - connect \Y $extend$libresoc.v:176811$10393_Y + connect \Y $extend$libresoc.v:176559$10387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:176812$10395 + cell $pos $extend$libresoc.v:176560$10389 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_3 - connect \Y $extend$libresoc.v:176812$10395_Y + connect \Y $extend$libresoc.v:176560$10389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:176813$10397 + cell $pos $extend$libresoc.v:176561$10391 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_4 - connect \Y $extend$libresoc.v:176813$10397_Y + connect \Y $extend$libresoc.v:176561$10391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:176814$10399 + cell $pos $extend$libresoc.v:176562$10393 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_5 - connect \Y $extend$libresoc.v:176814$10399_Y + connect \Y $extend$libresoc.v:176562$10393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:176815$10401 + cell $pos $extend$libresoc.v:176563$10395 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_6 - connect \Y $extend$libresoc.v:176815$10401_Y + connect \Y $extend$libresoc.v:176563$10395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:176816$10403 + cell $pos $extend$libresoc.v:176564$10397 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_7 - connect \Y $extend$libresoc.v:176816$10403_Y + connect \Y $extend$libresoc.v:176564$10397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:176818$10406 + cell $pos $extend$libresoc.v:176566$10400 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_0 - connect \Y $extend$libresoc.v:176818$10406_Y + connect \Y $extend$libresoc.v:176566$10400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:176819$10408 + cell $pos $extend$libresoc.v:176567$10402 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_1 - connect \Y $extend$libresoc.v:176819$10408_Y + connect \Y $extend$libresoc.v:176567$10402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:176820$10410 + cell $pos $extend$libresoc.v:176568$10404 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 64 connect \A \pop_7_0 - connect \Y $extend$libresoc.v:176820$10410_Y + connect \Y $extend$libresoc.v:176568$10404_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:176809$10390 + cell $pos $pos$libresoc.v:176557$10384 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:176809$10389_Y - connect \Y $pos$libresoc.v:176809$10390_Y + connect \A $extend$libresoc.v:176557$10383_Y + connect \Y $pos$libresoc.v:176557$10384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:176810$10392 + cell $pos $pos$libresoc.v:176558$10386 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:176810$10391_Y - connect \Y $pos$libresoc.v:176810$10392_Y + connect \A $extend$libresoc.v:176558$10385_Y + connect \Y $pos$libresoc.v:176558$10386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:176811$10394 + cell $pos $pos$libresoc.v:176559$10388 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:176811$10393_Y - connect \Y $pos$libresoc.v:176811$10394_Y + connect \A $extend$libresoc.v:176559$10387_Y + connect \Y $pos$libresoc.v:176559$10388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:176812$10396 + cell $pos $pos$libresoc.v:176560$10390 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:176812$10395_Y - connect \Y $pos$libresoc.v:176812$10396_Y + connect \A $extend$libresoc.v:176560$10389_Y + connect \Y $pos$libresoc.v:176560$10390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:176813$10398 + cell $pos $pos$libresoc.v:176561$10392 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:176813$10397_Y - connect \Y $pos$libresoc.v:176813$10398_Y + connect \A $extend$libresoc.v:176561$10391_Y + connect \Y $pos$libresoc.v:176561$10392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:176814$10400 + cell $pos $pos$libresoc.v:176562$10394 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:176814$10399_Y - connect \Y $pos$libresoc.v:176814$10400_Y + connect \A $extend$libresoc.v:176562$10393_Y + connect \Y $pos$libresoc.v:176562$10394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:176815$10402 + cell $pos $pos$libresoc.v:176563$10396 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:176815$10401_Y - connect \Y $pos$libresoc.v:176815$10402_Y + connect \A $extend$libresoc.v:176563$10395_Y + connect \Y $pos$libresoc.v:176563$10396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:176816$10404 + cell $pos $pos$libresoc.v:176564$10398 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:176816$10403_Y - connect \Y $pos$libresoc.v:176816$10404_Y + connect \A $extend$libresoc.v:176564$10397_Y + connect \Y $pos$libresoc.v:176564$10398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:176818$10407 + cell $pos $pos$libresoc.v:176566$10401 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:176818$10406_Y - connect \Y $pos$libresoc.v:176818$10407_Y + connect \A $extend$libresoc.v:176566$10400_Y + connect \Y $pos$libresoc.v:176566$10401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:176819$10409 + cell $pos $pos$libresoc.v:176567$10403 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:176819$10408_Y - connect \Y $pos$libresoc.v:176819$10409_Y + connect \A $extend$libresoc.v:176567$10402_Y + connect \Y $pos$libresoc.v:176567$10403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:176820$10411 + cell $pos $pos$libresoc.v:176568$10405 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:176820$10410_Y - connect \Y $pos$libresoc.v:176820$10411_Y + connect \A $extend$libresoc.v:176568$10404_Y + connect \Y $pos$libresoc.v:176568$10405_Y end - attribute \src "libresoc.v:176362.7-176362.20" - process $proc$libresoc.v:176362$10442 + attribute \src "libresoc.v:176110.7-176110.20" + process $proc$libresoc.v:176110$10436 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176850.3-176876.6" - process $proc$libresoc.v:176850$10441 + attribute \src "libresoc.v:176598.3-176624.6" + process $proc$libresoc.v:176598$10435 assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:176851.5-176851.29" + attribute \src "libresoc.v:176599.5-176599.29" switch \initial - attribute \src "libresoc.v:176851.9-176851.17" + attribute \src "libresoc.v:176599.9-176599.17" case 1'1 case end @@ -327515,82 +327221,82 @@ module \popcount sync always update \o $0\o[63:0] end - connect \$101 $add$libresoc.v:176774$10354_Y - connect \$104 $add$libresoc.v:176775$10355_Y - connect \$107 $add$libresoc.v:176776$10356_Y - connect \$110 $add$libresoc.v:176777$10357_Y - connect \$113 $add$libresoc.v:176778$10358_Y - connect \$116 $add$libresoc.v:176779$10359_Y - connect \$11 $add$libresoc.v:176780$10360_Y - connect \$119 $add$libresoc.v:176781$10361_Y - connect \$122 $add$libresoc.v:176782$10362_Y - connect \$125 $add$libresoc.v:176783$10363_Y - connect \$128 $add$libresoc.v:176784$10364_Y - connect \$131 $add$libresoc.v:176785$10365_Y - connect \$134 $add$libresoc.v:176786$10366_Y - connect \$137 $add$libresoc.v:176787$10367_Y - connect \$140 $add$libresoc.v:176788$10368_Y - connect \$143 $add$libresoc.v:176789$10369_Y - connect \$146 $add$libresoc.v:176790$10370_Y - connect \$14 $add$libresoc.v:176791$10371_Y - connect \$149 $add$libresoc.v:176792$10372_Y - connect \$152 $add$libresoc.v:176793$10373_Y - connect \$155 $add$libresoc.v:176794$10374_Y - connect \$158 $add$libresoc.v:176795$10375_Y - connect \$161 $add$libresoc.v:176796$10376_Y - connect \$164 $add$libresoc.v:176797$10377_Y - connect \$167 $add$libresoc.v:176798$10378_Y - connect \$170 $add$libresoc.v:176799$10379_Y - connect \$173 $add$libresoc.v:176800$10380_Y - connect \$176 $add$libresoc.v:176801$10381_Y - connect \$17 $add$libresoc.v:176802$10382_Y - connect \$179 $add$libresoc.v:176803$10383_Y - connect \$182 $add$libresoc.v:176804$10384_Y - connect \$185 $add$libresoc.v:176805$10385_Y - connect \$188 $add$libresoc.v:176806$10386_Y - connect \$190 $eq$libresoc.v:176807$10387_Y - connect \$192 $eq$libresoc.v:176808$10388_Y - connect \$194 $pos$libresoc.v:176809$10390_Y - connect \$196 $pos$libresoc.v:176810$10392_Y - connect \$198 $pos$libresoc.v:176811$10394_Y - connect \$200 $pos$libresoc.v:176812$10396_Y - connect \$202 $pos$libresoc.v:176813$10398_Y - connect \$204 $pos$libresoc.v:176814$10400_Y - connect \$206 $pos$libresoc.v:176815$10402_Y - connect \$208 $pos$libresoc.v:176816$10404_Y - connect \$20 $add$libresoc.v:176817$10405_Y - connect \$210 $pos$libresoc.v:176818$10407_Y - connect \$212 $pos$libresoc.v:176819$10409_Y - connect \$214 $pos$libresoc.v:176820$10411_Y - connect \$23 $add$libresoc.v:176821$10412_Y - connect \$26 $add$libresoc.v:176822$10413_Y - connect \$2 $add$libresoc.v:176823$10414_Y - connect \$29 $add$libresoc.v:176824$10415_Y - connect \$32 $add$libresoc.v:176825$10416_Y - connect \$35 $add$libresoc.v:176826$10417_Y - connect \$38 $add$libresoc.v:176827$10418_Y - connect \$41 $add$libresoc.v:176828$10419_Y - connect \$44 $add$libresoc.v:176829$10420_Y - connect \$47 $add$libresoc.v:176830$10421_Y - connect \$50 $add$libresoc.v:176831$10422_Y - connect \$53 $add$libresoc.v:176832$10423_Y - connect \$56 $add$libresoc.v:176833$10424_Y - connect \$5 $add$libresoc.v:176834$10425_Y - connect \$59 $add$libresoc.v:176835$10426_Y - connect \$62 $add$libresoc.v:176836$10427_Y - connect \$65 $add$libresoc.v:176837$10428_Y - connect \$68 $add$libresoc.v:176838$10429_Y - connect \$71 $add$libresoc.v:176839$10430_Y - connect \$74 $add$libresoc.v:176840$10431_Y - connect \$77 $add$libresoc.v:176841$10432_Y - connect \$80 $add$libresoc.v:176842$10433_Y - connect \$83 $add$libresoc.v:176843$10434_Y - connect \$86 $add$libresoc.v:176844$10435_Y - connect \$8 $add$libresoc.v:176845$10436_Y - connect \$89 $add$libresoc.v:176846$10437_Y - connect \$92 $add$libresoc.v:176847$10438_Y - connect \$95 $add$libresoc.v:176848$10439_Y - connect \$98 $add$libresoc.v:176849$10440_Y + connect \$101 $add$libresoc.v:176522$10348_Y + connect \$104 $add$libresoc.v:176523$10349_Y + connect \$107 $add$libresoc.v:176524$10350_Y + connect \$110 $add$libresoc.v:176525$10351_Y + connect \$113 $add$libresoc.v:176526$10352_Y + connect \$116 $add$libresoc.v:176527$10353_Y + connect \$11 $add$libresoc.v:176528$10354_Y + connect \$119 $add$libresoc.v:176529$10355_Y + connect \$122 $add$libresoc.v:176530$10356_Y + connect \$125 $add$libresoc.v:176531$10357_Y + connect \$128 $add$libresoc.v:176532$10358_Y + connect \$131 $add$libresoc.v:176533$10359_Y + connect \$134 $add$libresoc.v:176534$10360_Y + connect \$137 $add$libresoc.v:176535$10361_Y + connect \$140 $add$libresoc.v:176536$10362_Y + connect \$143 $add$libresoc.v:176537$10363_Y + connect \$146 $add$libresoc.v:176538$10364_Y + connect \$14 $add$libresoc.v:176539$10365_Y + connect \$149 $add$libresoc.v:176540$10366_Y + connect \$152 $add$libresoc.v:176541$10367_Y + connect \$155 $add$libresoc.v:176542$10368_Y + connect \$158 $add$libresoc.v:176543$10369_Y + connect \$161 $add$libresoc.v:176544$10370_Y + connect \$164 $add$libresoc.v:176545$10371_Y + connect \$167 $add$libresoc.v:176546$10372_Y + connect \$170 $add$libresoc.v:176547$10373_Y + connect \$173 $add$libresoc.v:176548$10374_Y + connect \$176 $add$libresoc.v:176549$10375_Y + connect \$17 $add$libresoc.v:176550$10376_Y + connect \$179 $add$libresoc.v:176551$10377_Y + connect \$182 $add$libresoc.v:176552$10378_Y + connect \$185 $add$libresoc.v:176553$10379_Y + connect \$188 $add$libresoc.v:176554$10380_Y + connect \$190 $eq$libresoc.v:176555$10381_Y + connect \$192 $eq$libresoc.v:176556$10382_Y + connect \$194 $pos$libresoc.v:176557$10384_Y + connect \$196 $pos$libresoc.v:176558$10386_Y + connect \$198 $pos$libresoc.v:176559$10388_Y + connect \$200 $pos$libresoc.v:176560$10390_Y + connect \$202 $pos$libresoc.v:176561$10392_Y + connect \$204 $pos$libresoc.v:176562$10394_Y + connect \$206 $pos$libresoc.v:176563$10396_Y + connect \$208 $pos$libresoc.v:176564$10398_Y + connect \$20 $add$libresoc.v:176565$10399_Y + connect \$210 $pos$libresoc.v:176566$10401_Y + connect \$212 $pos$libresoc.v:176567$10403_Y + connect \$214 $pos$libresoc.v:176568$10405_Y + connect \$23 $add$libresoc.v:176569$10406_Y + connect \$26 $add$libresoc.v:176570$10407_Y + connect \$2 $add$libresoc.v:176571$10408_Y + connect \$29 $add$libresoc.v:176572$10409_Y + connect \$32 $add$libresoc.v:176573$10410_Y + connect \$35 $add$libresoc.v:176574$10411_Y + connect \$38 $add$libresoc.v:176575$10412_Y + connect \$41 $add$libresoc.v:176576$10413_Y + connect \$44 $add$libresoc.v:176577$10414_Y + connect \$47 $add$libresoc.v:176578$10415_Y + connect \$50 $add$libresoc.v:176579$10416_Y + connect \$53 $add$libresoc.v:176580$10417_Y + connect \$56 $add$libresoc.v:176581$10418_Y + connect \$5 $add$libresoc.v:176582$10419_Y + connect \$59 $add$libresoc.v:176583$10420_Y + connect \$62 $add$libresoc.v:176584$10421_Y + connect \$65 $add$libresoc.v:176585$10422_Y + connect \$68 $add$libresoc.v:176586$10423_Y + connect \$71 $add$libresoc.v:176587$10424_Y + connect \$74 $add$libresoc.v:176588$10425_Y + connect \$77 $add$libresoc.v:176589$10426_Y + connect \$80 $add$libresoc.v:176590$10427_Y + connect \$83 $add$libresoc.v:176591$10428_Y + connect \$86 $add$libresoc.v:176592$10429_Y + connect \$8 $add$libresoc.v:176593$10430_Y + connect \$89 $add$libresoc.v:176594$10431_Y + connect \$92 $add$libresoc.v:176595$10432_Y + connect \$95 $add$libresoc.v:176596$10433_Y + connect \$98 $add$libresoc.v:176597$10434_Y connect \$1 \$2 connect \$4 \$5 connect \$7 \$8 @@ -327718,43 +327424,43 @@ module \popcount connect \pop_2_1 \$5 [1:0] connect \pop_2_0 \$2 [1:0] end -attribute \src "libresoc.v:177007.1-177091.10" +attribute \src "libresoc.v:176755.1-176839.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" attribute \generator "nMigen" module \ppick - attribute \src "libresoc.v:177064.17-177064.91" - wire $not$libresoc.v:177064$10443_Y - attribute \src "libresoc.v:177066.18-177066.93" - wire $not$libresoc.v:177066$10445_Y - attribute \src "libresoc.v:177068.18-177068.93" - wire $not$libresoc.v:177068$10447_Y - attribute \src "libresoc.v:177069.17-177069.138" - wire width 8 $not$libresoc.v:177069$10448_Y - attribute \src "libresoc.v:177071.18-177071.93" - wire $not$libresoc.v:177071$10450_Y - attribute \src "libresoc.v:177073.18-177073.93" - wire $not$libresoc.v:177073$10452_Y - attribute \src "libresoc.v:177075.18-177075.93" - wire $not$libresoc.v:177075$10454_Y - attribute \src "libresoc.v:177078.17-177078.91" - wire $not$libresoc.v:177078$10457_Y - attribute \src "libresoc.v:177065.18-177065.116" - wire $reduce_or$libresoc.v:177065$10444_Y - attribute \src "libresoc.v:177067.18-177067.122" - wire $reduce_or$libresoc.v:177067$10446_Y - attribute \src "libresoc.v:177070.18-177070.128" - wire $reduce_or$libresoc.v:177070$10449_Y - attribute \src "libresoc.v:177072.18-177072.134" - wire $reduce_or$libresoc.v:177072$10451_Y - attribute \src "libresoc.v:177074.18-177074.140" - wire $reduce_or$libresoc.v:177074$10453_Y - attribute \src "libresoc.v:177076.18-177076.90" - wire $reduce_or$libresoc.v:177076$10455_Y - attribute \src "libresoc.v:177077.17-177077.103" - wire $reduce_or$libresoc.v:177077$10456_Y - attribute \src "libresoc.v:177079.17-177079.109" - wire $reduce_or$libresoc.v:177079$10458_Y + attribute \src "libresoc.v:176812.17-176812.91" + wire $not$libresoc.v:176812$10437_Y + attribute \src "libresoc.v:176814.18-176814.93" + wire $not$libresoc.v:176814$10439_Y + attribute \src "libresoc.v:176816.18-176816.93" + wire $not$libresoc.v:176816$10441_Y + attribute \src "libresoc.v:176817.17-176817.138" + wire width 8 $not$libresoc.v:176817$10442_Y + attribute \src "libresoc.v:176819.18-176819.93" + wire $not$libresoc.v:176819$10444_Y + attribute \src "libresoc.v:176821.18-176821.93" + wire $not$libresoc.v:176821$10446_Y + attribute \src "libresoc.v:176823.18-176823.93" + wire $not$libresoc.v:176823$10448_Y + attribute \src "libresoc.v:176826.17-176826.91" + wire $not$libresoc.v:176826$10451_Y + attribute \src "libresoc.v:176813.18-176813.116" + wire $reduce_or$libresoc.v:176813$10438_Y + attribute \src "libresoc.v:176815.18-176815.122" + wire $reduce_or$libresoc.v:176815$10440_Y + attribute \src "libresoc.v:176818.18-176818.128" + wire $reduce_or$libresoc.v:176818$10443_Y + attribute \src "libresoc.v:176820.18-176820.134" + wire $reduce_or$libresoc.v:176820$10445_Y + attribute \src "libresoc.v:176822.18-176822.140" + wire $reduce_or$libresoc.v:176822$10447_Y + attribute \src "libresoc.v:176824.18-176824.90" + wire $reduce_or$libresoc.v:176824$10449_Y + attribute \src "libresoc.v:176825.17-176825.103" + wire $reduce_or$libresoc.v:176825$10450_Y + attribute \src "libresoc.v:176827.17-176827.109" + wire $reduce_or$libresoc.v:176827$10452_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -327812,149 +327518,149 @@ module \ppick attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177064$10443 + cell $not $not$libresoc.v:176812$10437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:177064$10443_Y + connect \Y $not$libresoc.v:176812$10437_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177066$10445 + cell $not $not$libresoc.v:176814$10439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:177066$10445_Y + connect \Y $not$libresoc.v:176814$10439_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177068$10447 + cell $not $not$libresoc.v:176816$10441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:177068$10447_Y + connect \Y $not$libresoc.v:176816$10441_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177069$10448 + cell $not $not$libresoc.v:176817$10442 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:177069$10448_Y + connect \Y $not$libresoc.v:176817$10442_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177071$10450 + cell $not $not$libresoc.v:176819$10444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:177071$10450_Y + connect \Y $not$libresoc.v:176819$10444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177073$10452 + cell $not $not$libresoc.v:176821$10446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:177073$10452_Y + connect \Y $not$libresoc.v:176821$10446_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177075$10454 + cell $not $not$libresoc.v:176823$10448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:177075$10454_Y + connect \Y $not$libresoc.v:176823$10448_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177078$10457 + cell $not $not$libresoc.v:176826$10451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:177078$10457_Y + connect \Y $not$libresoc.v:176826$10451_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177065$10444 + cell $reduce_or $reduce_or$libresoc.v:176813$10438 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:177065$10444_Y + connect \Y $reduce_or$libresoc.v:176813$10438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177067$10446 + cell $reduce_or $reduce_or$libresoc.v:176815$10440 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:177067$10446_Y + connect \Y $reduce_or$libresoc.v:176815$10440_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177070$10449 + cell $reduce_or $reduce_or$libresoc.v:176818$10443 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:177070$10449_Y + connect \Y $reduce_or$libresoc.v:176818$10443_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177072$10451 + cell $reduce_or $reduce_or$libresoc.v:176820$10445 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:177072$10451_Y + connect \Y $reduce_or$libresoc.v:176820$10445_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177074$10453 + cell $reduce_or $reduce_or$libresoc.v:176822$10447 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:177074$10453_Y + connect \Y $reduce_or$libresoc.v:176822$10447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177076$10455 + cell $reduce_or $reduce_or$libresoc.v:176824$10449 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177076$10455_Y + connect \Y $reduce_or$libresoc.v:176824$10449_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177077$10456 + cell $reduce_or $reduce_or$libresoc.v:176825$10450 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:177077$10456_Y + connect \Y $reduce_or$libresoc.v:176825$10450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177079$10458 + cell $reduce_or $reduce_or$libresoc.v:176827$10452 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:177079$10458_Y - end - connect \$7 $not$libresoc.v:177064$10443_Y - connect \$12 $reduce_or$libresoc.v:177065$10444_Y - connect \$11 $not$libresoc.v:177066$10445_Y - connect \$16 $reduce_or$libresoc.v:177067$10446_Y - connect \$15 $not$libresoc.v:177068$10447_Y - connect \$1 $not$libresoc.v:177069$10448_Y - connect \$20 $reduce_or$libresoc.v:177070$10449_Y - connect \$19 $not$libresoc.v:177071$10450_Y - connect \$24 $reduce_or$libresoc.v:177072$10451_Y - connect \$23 $not$libresoc.v:177073$10452_Y - connect \$28 $reduce_or$libresoc.v:177074$10453_Y - connect \$27 $not$libresoc.v:177075$10454_Y - connect \$31 $reduce_or$libresoc.v:177076$10455_Y - connect \$4 $reduce_or$libresoc.v:177077$10456_Y - connect \$3 $not$libresoc.v:177078$10457_Y - connect \$8 $reduce_or$libresoc.v:177079$10458_Y + connect \Y $reduce_or$libresoc.v:176827$10452_Y + end + connect \$7 $not$libresoc.v:176812$10437_Y + connect \$12 $reduce_or$libresoc.v:176813$10438_Y + connect \$11 $not$libresoc.v:176814$10439_Y + connect \$16 $reduce_or$libresoc.v:176815$10440_Y + connect \$15 $not$libresoc.v:176816$10441_Y + connect \$1 $not$libresoc.v:176817$10442_Y + connect \$20 $reduce_or$libresoc.v:176818$10443_Y + connect \$19 $not$libresoc.v:176819$10444_Y + connect \$24 $reduce_or$libresoc.v:176820$10445_Y + connect \$23 $not$libresoc.v:176821$10446_Y + connect \$28 $reduce_or$libresoc.v:176822$10447_Y + connect \$27 $not$libresoc.v:176823$10448_Y + connect \$31 $reduce_or$libresoc.v:176824$10449_Y + connect \$4 $reduce_or$libresoc.v:176825$10450_Y + connect \$3 $not$libresoc.v:176826$10451_Y + connect \$8 $reduce_or$libresoc.v:176827$10452_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -327967,43 +327673,43 @@ module \ppick connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:177095.1-177179.10" +attribute \src "libresoc.v:176843.1-176927.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" attribute \generator "nMigen" module \ppick$175 - attribute \src "libresoc.v:177152.17-177152.91" - wire $not$libresoc.v:177152$10459_Y - attribute \src "libresoc.v:177154.18-177154.93" - wire $not$libresoc.v:177154$10461_Y - attribute \src "libresoc.v:177156.18-177156.93" - wire $not$libresoc.v:177156$10463_Y - attribute \src "libresoc.v:177157.17-177157.138" - wire width 8 $not$libresoc.v:177157$10464_Y - attribute \src "libresoc.v:177159.18-177159.93" - wire $not$libresoc.v:177159$10466_Y - attribute \src "libresoc.v:177161.18-177161.93" - wire $not$libresoc.v:177161$10468_Y - attribute \src "libresoc.v:177163.18-177163.93" - wire $not$libresoc.v:177163$10470_Y - attribute \src "libresoc.v:177166.17-177166.91" - wire $not$libresoc.v:177166$10473_Y - attribute \src "libresoc.v:177153.18-177153.116" - wire $reduce_or$libresoc.v:177153$10460_Y - attribute \src "libresoc.v:177155.18-177155.122" - wire $reduce_or$libresoc.v:177155$10462_Y - attribute \src "libresoc.v:177158.18-177158.128" - wire $reduce_or$libresoc.v:177158$10465_Y - attribute \src "libresoc.v:177160.18-177160.134" - wire $reduce_or$libresoc.v:177160$10467_Y - attribute \src "libresoc.v:177162.18-177162.140" - wire $reduce_or$libresoc.v:177162$10469_Y - attribute \src "libresoc.v:177164.18-177164.90" - wire $reduce_or$libresoc.v:177164$10471_Y - attribute \src "libresoc.v:177165.17-177165.103" - wire $reduce_or$libresoc.v:177165$10472_Y - attribute \src "libresoc.v:177167.17-177167.109" - wire $reduce_or$libresoc.v:177167$10474_Y + attribute \src "libresoc.v:176900.17-176900.91" + wire $not$libresoc.v:176900$10453_Y + attribute \src "libresoc.v:176902.18-176902.93" + wire $not$libresoc.v:176902$10455_Y + attribute \src "libresoc.v:176904.18-176904.93" + wire $not$libresoc.v:176904$10457_Y + attribute \src "libresoc.v:176905.17-176905.138" + wire width 8 $not$libresoc.v:176905$10458_Y + attribute \src "libresoc.v:176907.18-176907.93" + wire $not$libresoc.v:176907$10460_Y + attribute \src "libresoc.v:176909.18-176909.93" + wire $not$libresoc.v:176909$10462_Y + attribute \src "libresoc.v:176911.18-176911.93" + wire $not$libresoc.v:176911$10464_Y + attribute \src "libresoc.v:176914.17-176914.91" + wire $not$libresoc.v:176914$10467_Y + attribute \src "libresoc.v:176901.18-176901.116" + wire $reduce_or$libresoc.v:176901$10454_Y + attribute \src "libresoc.v:176903.18-176903.122" + wire $reduce_or$libresoc.v:176903$10456_Y + attribute \src "libresoc.v:176906.18-176906.128" + wire $reduce_or$libresoc.v:176906$10459_Y + attribute \src "libresoc.v:176908.18-176908.134" + wire $reduce_or$libresoc.v:176908$10461_Y + attribute \src "libresoc.v:176910.18-176910.140" + wire $reduce_or$libresoc.v:176910$10463_Y + attribute \src "libresoc.v:176912.18-176912.90" + wire $reduce_or$libresoc.v:176912$10465_Y + attribute \src "libresoc.v:176913.17-176913.103" + wire $reduce_or$libresoc.v:176913$10466_Y + attribute \src "libresoc.v:176915.17-176915.109" + wire $reduce_or$libresoc.v:176915$10468_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -328061,149 +327767,149 @@ module \ppick$175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177152$10459 + cell $not $not$libresoc.v:176900$10453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:177152$10459_Y + connect \Y $not$libresoc.v:176900$10453_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177154$10461 + cell $not $not$libresoc.v:176902$10455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:177154$10461_Y + connect \Y $not$libresoc.v:176902$10455_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177156$10463 + cell $not $not$libresoc.v:176904$10457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:177156$10463_Y + connect \Y $not$libresoc.v:176904$10457_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177157$10464 + cell $not $not$libresoc.v:176905$10458 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:177157$10464_Y + connect \Y $not$libresoc.v:176905$10458_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177159$10466 + cell $not $not$libresoc.v:176907$10460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:177159$10466_Y + connect \Y $not$libresoc.v:176907$10460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177161$10468 + cell $not $not$libresoc.v:176909$10462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:177161$10468_Y + connect \Y $not$libresoc.v:176909$10462_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177163$10470 + cell $not $not$libresoc.v:176911$10464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:177163$10470_Y + connect \Y $not$libresoc.v:176911$10464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177166$10473 + cell $not $not$libresoc.v:176914$10467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:177166$10473_Y + connect \Y $not$libresoc.v:176914$10467_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177153$10460 + cell $reduce_or $reduce_or$libresoc.v:176901$10454 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:177153$10460_Y + connect \Y $reduce_or$libresoc.v:176901$10454_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177155$10462 + cell $reduce_or $reduce_or$libresoc.v:176903$10456 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:177155$10462_Y + connect \Y $reduce_or$libresoc.v:176903$10456_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177158$10465 + cell $reduce_or $reduce_or$libresoc.v:176906$10459 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:177158$10465_Y + connect \Y $reduce_or$libresoc.v:176906$10459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177160$10467 + cell $reduce_or $reduce_or$libresoc.v:176908$10461 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:177160$10467_Y + connect \Y $reduce_or$libresoc.v:176908$10461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177162$10469 + cell $reduce_or $reduce_or$libresoc.v:176910$10463 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:177162$10469_Y + connect \Y $reduce_or$libresoc.v:176910$10463_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177164$10471 + cell $reduce_or $reduce_or$libresoc.v:176912$10465 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177164$10471_Y + connect \Y $reduce_or$libresoc.v:176912$10465_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177165$10472 + cell $reduce_or $reduce_or$libresoc.v:176913$10466 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:177165$10472_Y + connect \Y $reduce_or$libresoc.v:176913$10466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177167$10474 + cell $reduce_or $reduce_or$libresoc.v:176915$10468 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:177167$10474_Y - end - connect \$7 $not$libresoc.v:177152$10459_Y - connect \$12 $reduce_or$libresoc.v:177153$10460_Y - connect \$11 $not$libresoc.v:177154$10461_Y - connect \$16 $reduce_or$libresoc.v:177155$10462_Y - connect \$15 $not$libresoc.v:177156$10463_Y - connect \$1 $not$libresoc.v:177157$10464_Y - connect \$20 $reduce_or$libresoc.v:177158$10465_Y - connect \$19 $not$libresoc.v:177159$10466_Y - connect \$24 $reduce_or$libresoc.v:177160$10467_Y - connect \$23 $not$libresoc.v:177161$10468_Y - connect \$28 $reduce_or$libresoc.v:177162$10469_Y - connect \$27 $not$libresoc.v:177163$10470_Y - connect \$31 $reduce_or$libresoc.v:177164$10471_Y - connect \$4 $reduce_or$libresoc.v:177165$10472_Y - connect \$3 $not$libresoc.v:177166$10473_Y - connect \$8 $reduce_or$libresoc.v:177167$10474_Y + connect \Y $reduce_or$libresoc.v:176915$10468_Y + end + connect \$7 $not$libresoc.v:176900$10453_Y + connect \$12 $reduce_or$libresoc.v:176901$10454_Y + connect \$11 $not$libresoc.v:176902$10455_Y + connect \$16 $reduce_or$libresoc.v:176903$10456_Y + connect \$15 $not$libresoc.v:176904$10457_Y + connect \$1 $not$libresoc.v:176905$10458_Y + connect \$20 $reduce_or$libresoc.v:176906$10459_Y + connect \$19 $not$libresoc.v:176907$10460_Y + connect \$24 $reduce_or$libresoc.v:176908$10461_Y + connect \$23 $not$libresoc.v:176909$10462_Y + connect \$28 $reduce_or$libresoc.v:176910$10463_Y + connect \$27 $not$libresoc.v:176911$10464_Y + connect \$31 $reduce_or$libresoc.v:176912$10465_Y + connect \$4 $reduce_or$libresoc.v:176913$10466_Y + connect \$3 $not$libresoc.v:176914$10467_Y + connect \$8 $reduce_or$libresoc.v:176915$10468_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -328216,19 +327922,19 @@ module \ppick$175 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:177183.1-177213.10" +attribute \src "libresoc.v:176931.1-176961.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" attribute \generator "nMigen" module \rdpick_CR_cr_a - attribute \src "libresoc.v:177204.17-177204.89" - wire width 2 $not$libresoc.v:177204$10475_Y - attribute \src "libresoc.v:177206.17-177206.91" - wire $not$libresoc.v:177206$10477_Y - attribute \src "libresoc.v:177205.17-177205.103" - wire $reduce_or$libresoc.v:177205$10476_Y - attribute \src "libresoc.v:177207.17-177207.89" - wire $reduce_or$libresoc.v:177207$10478_Y + attribute \src "libresoc.v:176952.17-176952.89" + wire width 2 $not$libresoc.v:176952$10469_Y + attribute \src "libresoc.v:176954.17-176954.91" + wire $not$libresoc.v:176954$10471_Y + attribute \src "libresoc.v:176953.17-176953.103" + wire $reduce_or$libresoc.v:176953$10470_Y + attribute \src "libresoc.v:176955.17-176955.89" + wire $reduce_or$libresoc.v:176955$10472_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -328250,56 +327956,56 @@ module \rdpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177204$10475 + cell $not $not$libresoc.v:176952$10469 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:177204$10475_Y + connect \Y $not$libresoc.v:176952$10469_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177206$10477 + cell $not $not$libresoc.v:176954$10471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:177206$10477_Y + connect \Y $not$libresoc.v:176954$10471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177205$10476 + cell $reduce_or $reduce_or$libresoc.v:176953$10470 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:177205$10476_Y + connect \Y $reduce_or$libresoc.v:176953$10470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177207$10478 + cell $reduce_or $reduce_or$libresoc.v:176955$10472 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177207$10478_Y + connect \Y $reduce_or$libresoc.v:176955$10472_Y end - connect \$1 $not$libresoc.v:177204$10475_Y - connect \$4 $reduce_or$libresoc.v:177205$10476_Y - connect \$3 $not$libresoc.v:177206$10477_Y - connect \$7 $reduce_or$libresoc.v:177207$10478_Y + connect \$1 $not$libresoc.v:176952$10469_Y + connect \$4 $reduce_or$libresoc.v:176953$10470_Y + connect \$3 $not$libresoc.v:176954$10471_Y + connect \$7 $reduce_or$libresoc.v:176955$10472_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:177217.1-177238.10" +attribute \src "libresoc.v:176965.1-176986.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" attribute \generator "nMigen" module \rdpick_CR_cr_b - attribute \src "libresoc.v:177232.17-177232.89" - wire $not$libresoc.v:177232$10479_Y - attribute \src "libresoc.v:177233.17-177233.89" - wire $reduce_or$libresoc.v:177233$10480_Y + attribute \src "libresoc.v:176980.17-176980.89" + wire $not$libresoc.v:176980$10473_Y + attribute \src "libresoc.v:176981.17-176981.89" + wire $reduce_or$libresoc.v:176981$10474_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -328315,37 +328021,37 @@ module \rdpick_CR_cr_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177232$10479 + cell $not $not$libresoc.v:176980$10473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:177232$10479_Y + connect \Y $not$libresoc.v:176980$10473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177233$10480 + cell $reduce_or $reduce_or$libresoc.v:176981$10474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177233$10480_Y + connect \Y $reduce_or$libresoc.v:176981$10474_Y end - connect \$1 $not$libresoc.v:177232$10479_Y - connect \$3 $reduce_or$libresoc.v:177233$10480_Y + connect \$1 $not$libresoc.v:176980$10473_Y + connect \$3 $reduce_or$libresoc.v:176981$10474_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:177242.1-177263.10" +attribute \src "libresoc.v:176990.1-177011.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" attribute \generator "nMigen" module \rdpick_CR_cr_c - attribute \src "libresoc.v:177257.17-177257.89" - wire $not$libresoc.v:177257$10481_Y - attribute \src "libresoc.v:177258.17-177258.89" - wire $reduce_or$libresoc.v:177258$10482_Y + attribute \src "libresoc.v:177005.17-177005.89" + wire $not$libresoc.v:177005$10475_Y + attribute \src "libresoc.v:177006.17-177006.89" + wire $reduce_or$libresoc.v:177006$10476_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -328361,37 +328067,37 @@ module \rdpick_CR_cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177257$10481 + cell $not $not$libresoc.v:177005$10475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:177257$10481_Y + connect \Y $not$libresoc.v:177005$10475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177258$10482 + cell $reduce_or $reduce_or$libresoc.v:177006$10476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177258$10482_Y + connect \Y $reduce_or$libresoc.v:177006$10476_Y end - connect \$1 $not$libresoc.v:177257$10481_Y - connect \$3 $reduce_or$libresoc.v:177258$10482_Y + connect \$1 $not$libresoc.v:177005$10475_Y + connect \$3 $reduce_or$libresoc.v:177006$10476_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:177267.1-177288.10" +attribute \src "libresoc.v:177015.1-177036.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" attribute \generator "nMigen" module \rdpick_CR_full_cr - attribute \src "libresoc.v:177282.17-177282.89" - wire $not$libresoc.v:177282$10483_Y - attribute \src "libresoc.v:177283.17-177283.89" - wire $reduce_or$libresoc.v:177283$10484_Y + attribute \src "libresoc.v:177030.17-177030.89" + wire $not$libresoc.v:177030$10477_Y + attribute \src "libresoc.v:177031.17-177031.89" + wire $reduce_or$libresoc.v:177031$10478_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -328407,53 +328113,53 @@ module \rdpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177282$10483 + cell $not $not$libresoc.v:177030$10477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:177282$10483_Y + connect \Y $not$libresoc.v:177030$10477_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177283$10484 + cell $reduce_or $reduce_or$libresoc.v:177031$10478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177283$10484_Y + connect \Y $reduce_or$libresoc.v:177031$10478_Y end - connect \$1 $not$libresoc.v:177282$10483_Y - connect \$3 $reduce_or$libresoc.v:177283$10484_Y + connect \$1 $not$libresoc.v:177030$10477_Y + connect \$3 $reduce_or$libresoc.v:177031$10478_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:177292.1-177349.10" +attribute \src "libresoc.v:177040.1-177097.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" attribute \generator "nMigen" module \rdpick_FAST_fast1 - attribute \src "libresoc.v:177331.17-177331.91" - wire $not$libresoc.v:177331$10485_Y - attribute \src "libresoc.v:177333.18-177333.93" - wire $not$libresoc.v:177333$10487_Y - attribute \src "libresoc.v:177335.18-177335.93" - wire $not$libresoc.v:177335$10489_Y - attribute \src "libresoc.v:177336.17-177336.89" - wire width 5 $not$libresoc.v:177336$10490_Y - attribute \src "libresoc.v:177339.17-177339.91" - wire $not$libresoc.v:177339$10493_Y - attribute \src "libresoc.v:177332.18-177332.106" - wire $reduce_or$libresoc.v:177332$10486_Y - attribute \src "libresoc.v:177334.18-177334.106" - wire $reduce_or$libresoc.v:177334$10488_Y - attribute \src "libresoc.v:177337.18-177337.90" - wire $reduce_or$libresoc.v:177337$10491_Y - attribute \src "libresoc.v:177338.17-177338.103" - wire $reduce_or$libresoc.v:177338$10492_Y - attribute \src "libresoc.v:177340.17-177340.105" - wire $reduce_or$libresoc.v:177340$10494_Y + attribute \src "libresoc.v:177079.17-177079.91" + wire $not$libresoc.v:177079$10479_Y + attribute \src "libresoc.v:177081.18-177081.93" + wire $not$libresoc.v:177081$10481_Y + attribute \src "libresoc.v:177083.18-177083.93" + wire $not$libresoc.v:177083$10483_Y + attribute \src "libresoc.v:177084.17-177084.89" + wire width 5 $not$libresoc.v:177084$10484_Y + attribute \src "libresoc.v:177087.17-177087.91" + wire $not$libresoc.v:177087$10487_Y + attribute \src "libresoc.v:177080.18-177080.106" + wire $reduce_or$libresoc.v:177080$10480_Y + attribute \src "libresoc.v:177082.18-177082.106" + wire $reduce_or$libresoc.v:177082$10482_Y + attribute \src "libresoc.v:177085.18-177085.90" + wire $reduce_or$libresoc.v:177085$10485_Y + attribute \src "libresoc.v:177086.17-177086.103" + wire $reduce_or$libresoc.v:177086$10486_Y + attribute \src "libresoc.v:177088.17-177088.105" + wire $reduce_or$libresoc.v:177088$10488_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -328493,95 +328199,95 @@ module \rdpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177331$10485 + cell $not $not$libresoc.v:177079$10479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:177331$10485_Y + connect \Y $not$libresoc.v:177079$10479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177333$10487 + cell $not $not$libresoc.v:177081$10481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:177333$10487_Y + connect \Y $not$libresoc.v:177081$10481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177335$10489 + cell $not $not$libresoc.v:177083$10483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:177335$10489_Y + connect \Y $not$libresoc.v:177083$10483_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177336$10490 + cell $not $not$libresoc.v:177084$10484 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i - connect \Y $not$libresoc.v:177336$10490_Y + connect \Y $not$libresoc.v:177084$10484_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177339$10493 + cell $not $not$libresoc.v:177087$10487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:177339$10493_Y + connect \Y $not$libresoc.v:177087$10487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177332$10486 + cell $reduce_or $reduce_or$libresoc.v:177080$10480 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:177332$10486_Y + connect \Y $reduce_or$libresoc.v:177080$10480_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177334$10488 + cell $reduce_or $reduce_or$libresoc.v:177082$10482 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:177334$10488_Y + connect \Y $reduce_or$libresoc.v:177082$10482_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177337$10491 + cell $reduce_or $reduce_or$libresoc.v:177085$10485 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177337$10491_Y + connect \Y $reduce_or$libresoc.v:177085$10485_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177338$10492 + cell $reduce_or $reduce_or$libresoc.v:177086$10486 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:177338$10492_Y + connect \Y $reduce_or$libresoc.v:177086$10486_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177340$10494 + cell $reduce_or $reduce_or$libresoc.v:177088$10488 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:177340$10494_Y - end - connect \$7 $not$libresoc.v:177331$10485_Y - connect \$12 $reduce_or$libresoc.v:177332$10486_Y - connect \$11 $not$libresoc.v:177333$10487_Y - connect \$16 $reduce_or$libresoc.v:177334$10488_Y - connect \$15 $not$libresoc.v:177335$10489_Y - connect \$1 $not$libresoc.v:177336$10490_Y - connect \$19 $reduce_or$libresoc.v:177337$10491_Y - connect \$4 $reduce_or$libresoc.v:177338$10492_Y - connect \$3 $not$libresoc.v:177339$10493_Y - connect \$8 $reduce_or$libresoc.v:177340$10494_Y + connect \Y $reduce_or$libresoc.v:177088$10488_Y + end + connect \$7 $not$libresoc.v:177079$10479_Y + connect \$12 $reduce_or$libresoc.v:177080$10480_Y + connect \$11 $not$libresoc.v:177081$10481_Y + connect \$16 $reduce_or$libresoc.v:177082$10482_Y + connect \$15 $not$libresoc.v:177083$10483_Y + connect \$1 $not$libresoc.v:177084$10484_Y + connect \$19 $reduce_or$libresoc.v:177085$10485_Y + connect \$4 $reduce_or$libresoc.v:177086$10486_Y + connect \$3 $not$libresoc.v:177087$10487_Y + connect \$8 $reduce_or$libresoc.v:177088$10488_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 @@ -328591,87 +328297,87 @@ module \rdpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:177353.1-177536.10" +attribute \src "libresoc.v:177101.1-177284.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rabc" attribute \generator "nMigen" module \rdpick_INT_rabc - attribute \src "libresoc.v:177476.17-177476.91" - wire $not$libresoc.v:177476$10495_Y - attribute \src "libresoc.v:177478.18-177478.93" - wire $not$libresoc.v:177478$10497_Y - attribute \src "libresoc.v:177480.18-177480.93" - wire $not$libresoc.v:177480$10499_Y - attribute \src "libresoc.v:177481.17-177481.89" - wire width 19 $not$libresoc.v:177481$10500_Y - attribute \src "libresoc.v:177483.18-177483.93" - wire $not$libresoc.v:177483$10502_Y - attribute \src "libresoc.v:177485.18-177485.93" - wire $not$libresoc.v:177485$10504_Y - attribute \src "libresoc.v:177487.18-177487.93" - wire $not$libresoc.v:177487$10506_Y - attribute \src "libresoc.v:177489.18-177489.93" - wire $not$libresoc.v:177489$10508_Y - attribute \src "libresoc.v:177491.18-177491.93" - wire $not$libresoc.v:177491$10510_Y - attribute \src "libresoc.v:177493.18-177493.93" - wire $not$libresoc.v:177493$10512_Y - attribute \src "libresoc.v:177495.18-177495.93" - wire $not$libresoc.v:177495$10514_Y - attribute \src "libresoc.v:177498.18-177498.93" - wire $not$libresoc.v:177498$10517_Y - attribute \src "libresoc.v:177500.18-177500.93" - wire $not$libresoc.v:177500$10519_Y - attribute \src "libresoc.v:177502.18-177502.93" - wire $not$libresoc.v:177502$10521_Y - attribute \src "libresoc.v:177503.17-177503.91" - wire $not$libresoc.v:177503$10522_Y - attribute \src "libresoc.v:177505.18-177505.93" - wire $not$libresoc.v:177505$10524_Y - attribute \src "libresoc.v:177507.18-177507.93" - wire $not$libresoc.v:177507$10526_Y - attribute \src "libresoc.v:177509.18-177509.93" - wire $not$libresoc.v:177509$10528_Y - attribute \src "libresoc.v:177511.18-177511.93" - wire $not$libresoc.v:177511$10530_Y - attribute \src "libresoc.v:177477.18-177477.106" - wire $reduce_or$libresoc.v:177477$10496_Y - attribute \src "libresoc.v:177479.18-177479.106" - wire $reduce_or$libresoc.v:177479$10498_Y - attribute \src "libresoc.v:177482.18-177482.106" - wire $reduce_or$libresoc.v:177482$10501_Y - attribute \src "libresoc.v:177484.18-177484.106" - wire $reduce_or$libresoc.v:177484$10503_Y - attribute \src "libresoc.v:177486.18-177486.106" - wire $reduce_or$libresoc.v:177486$10505_Y - attribute \src "libresoc.v:177488.18-177488.106" - wire $reduce_or$libresoc.v:177488$10507_Y - attribute \src "libresoc.v:177490.18-177490.106" - wire $reduce_or$libresoc.v:177490$10509_Y - attribute \src "libresoc.v:177492.18-177492.107" - wire $reduce_or$libresoc.v:177492$10511_Y - attribute \src "libresoc.v:177494.18-177494.108" - wire $reduce_or$libresoc.v:177494$10513_Y - attribute \src "libresoc.v:177496.18-177496.108" - wire $reduce_or$libresoc.v:177496$10515_Y - attribute \src "libresoc.v:177497.17-177497.103" - wire $reduce_or$libresoc.v:177497$10516_Y - attribute \src "libresoc.v:177499.18-177499.108" - wire $reduce_or$libresoc.v:177499$10518_Y - attribute \src "libresoc.v:177501.18-177501.108" - wire $reduce_or$libresoc.v:177501$10520_Y - attribute \src "libresoc.v:177504.18-177504.108" - wire $reduce_or$libresoc.v:177504$10523_Y - attribute \src "libresoc.v:177506.18-177506.108" - wire $reduce_or$libresoc.v:177506$10525_Y - attribute \src "libresoc.v:177508.18-177508.108" - wire $reduce_or$libresoc.v:177508$10527_Y - attribute \src "libresoc.v:177510.18-177510.108" - wire $reduce_or$libresoc.v:177510$10529_Y - attribute \src "libresoc.v:177512.18-177512.90" - wire $reduce_or$libresoc.v:177512$10531_Y - attribute \src "libresoc.v:177513.17-177513.105" - wire $reduce_or$libresoc.v:177513$10532_Y + attribute \src "libresoc.v:177224.17-177224.91" + wire $not$libresoc.v:177224$10489_Y + attribute \src "libresoc.v:177226.18-177226.93" + wire $not$libresoc.v:177226$10491_Y + attribute \src "libresoc.v:177228.18-177228.93" + wire $not$libresoc.v:177228$10493_Y + attribute \src "libresoc.v:177229.17-177229.89" + wire width 19 $not$libresoc.v:177229$10494_Y + attribute \src "libresoc.v:177231.18-177231.93" + wire $not$libresoc.v:177231$10496_Y + attribute \src "libresoc.v:177233.18-177233.93" + wire $not$libresoc.v:177233$10498_Y + attribute \src "libresoc.v:177235.18-177235.93" + wire $not$libresoc.v:177235$10500_Y + attribute \src "libresoc.v:177237.18-177237.93" + wire $not$libresoc.v:177237$10502_Y + attribute \src "libresoc.v:177239.18-177239.93" + wire $not$libresoc.v:177239$10504_Y + attribute \src "libresoc.v:177241.18-177241.93" + wire $not$libresoc.v:177241$10506_Y + attribute \src "libresoc.v:177243.18-177243.93" + wire $not$libresoc.v:177243$10508_Y + attribute \src "libresoc.v:177246.18-177246.93" + wire $not$libresoc.v:177246$10511_Y + attribute \src "libresoc.v:177248.18-177248.93" + wire $not$libresoc.v:177248$10513_Y + attribute \src "libresoc.v:177250.18-177250.93" + wire $not$libresoc.v:177250$10515_Y + attribute \src "libresoc.v:177251.17-177251.91" + wire $not$libresoc.v:177251$10516_Y + attribute \src "libresoc.v:177253.18-177253.93" + wire $not$libresoc.v:177253$10518_Y + attribute \src "libresoc.v:177255.18-177255.93" + wire $not$libresoc.v:177255$10520_Y + attribute \src "libresoc.v:177257.18-177257.93" + wire $not$libresoc.v:177257$10522_Y + attribute \src "libresoc.v:177259.18-177259.93" + wire $not$libresoc.v:177259$10524_Y + attribute \src "libresoc.v:177225.18-177225.106" + wire $reduce_or$libresoc.v:177225$10490_Y + attribute \src "libresoc.v:177227.18-177227.106" + wire $reduce_or$libresoc.v:177227$10492_Y + attribute \src "libresoc.v:177230.18-177230.106" + wire $reduce_or$libresoc.v:177230$10495_Y + attribute \src "libresoc.v:177232.18-177232.106" + wire $reduce_or$libresoc.v:177232$10497_Y + attribute \src "libresoc.v:177234.18-177234.106" + wire $reduce_or$libresoc.v:177234$10499_Y + attribute \src "libresoc.v:177236.18-177236.106" + wire $reduce_or$libresoc.v:177236$10501_Y + attribute \src "libresoc.v:177238.18-177238.106" + wire $reduce_or$libresoc.v:177238$10503_Y + attribute \src "libresoc.v:177240.18-177240.107" + wire $reduce_or$libresoc.v:177240$10505_Y + attribute \src "libresoc.v:177242.18-177242.108" + wire $reduce_or$libresoc.v:177242$10507_Y + attribute \src "libresoc.v:177244.18-177244.108" + wire $reduce_or$libresoc.v:177244$10509_Y + attribute \src "libresoc.v:177245.17-177245.103" + wire $reduce_or$libresoc.v:177245$10510_Y + attribute \src "libresoc.v:177247.18-177247.108" + wire $reduce_or$libresoc.v:177247$10512_Y + attribute \src "libresoc.v:177249.18-177249.108" + wire $reduce_or$libresoc.v:177249$10514_Y + attribute \src "libresoc.v:177252.18-177252.108" + wire $reduce_or$libresoc.v:177252$10517_Y + attribute \src "libresoc.v:177254.18-177254.108" + wire $reduce_or$libresoc.v:177254$10519_Y + attribute \src "libresoc.v:177256.18-177256.108" + wire $reduce_or$libresoc.v:177256$10521_Y + attribute \src "libresoc.v:177258.18-177258.108" + wire $reduce_or$libresoc.v:177258$10523_Y + attribute \src "libresoc.v:177260.18-177260.90" + wire $reduce_or$libresoc.v:177260$10525_Y + attribute \src "libresoc.v:177261.17-177261.105" + wire $reduce_or$libresoc.v:177261$10526_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 19 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -328795,347 +328501,347 @@ module \rdpick_INT_rabc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177476$10495 + cell $not $not$libresoc.v:177224$10489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:177476$10495_Y + connect \Y $not$libresoc.v:177224$10489_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177478$10497 + cell $not $not$libresoc.v:177226$10491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:177478$10497_Y + connect \Y $not$libresoc.v:177226$10491_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177480$10499 + cell $not $not$libresoc.v:177228$10493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:177480$10499_Y + connect \Y $not$libresoc.v:177228$10493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177481$10500 + cell $not $not$libresoc.v:177229$10494 parameter \A_SIGNED 0 parameter \A_WIDTH 19 parameter \Y_WIDTH 19 connect \A \i - connect \Y $not$libresoc.v:177481$10500_Y + connect \Y $not$libresoc.v:177229$10494_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177483$10502 + cell $not $not$libresoc.v:177231$10496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:177483$10502_Y + connect \Y $not$libresoc.v:177231$10496_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177485$10504 + cell $not $not$libresoc.v:177233$10498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:177485$10504_Y + connect \Y $not$libresoc.v:177233$10498_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177487$10506 + cell $not $not$libresoc.v:177235$10500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:177487$10506_Y + connect \Y $not$libresoc.v:177235$10500_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177489$10508 + cell $not $not$libresoc.v:177237$10502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:177489$10508_Y + connect \Y $not$libresoc.v:177237$10502_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177491$10510 + cell $not $not$libresoc.v:177239$10504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 - connect \Y $not$libresoc.v:177491$10510_Y + connect \Y $not$libresoc.v:177239$10504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177493$10512 + cell $not $not$libresoc.v:177241$10506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$40 - connect \Y $not$libresoc.v:177493$10512_Y + connect \Y $not$libresoc.v:177241$10506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177495$10514 + cell $not $not$libresoc.v:177243$10508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 - connect \Y $not$libresoc.v:177495$10514_Y + connect \Y $not$libresoc.v:177243$10508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177498$10517 + cell $not $not$libresoc.v:177246$10511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$48 - connect \Y $not$libresoc.v:177498$10517_Y + connect \Y $not$libresoc.v:177246$10511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177500$10519 + cell $not $not$libresoc.v:177248$10513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$52 - connect \Y $not$libresoc.v:177500$10519_Y + connect \Y $not$libresoc.v:177248$10513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177502$10521 + cell $not $not$libresoc.v:177250$10515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$56 - connect \Y $not$libresoc.v:177502$10521_Y + connect \Y $not$libresoc.v:177250$10515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177503$10522 + cell $not $not$libresoc.v:177251$10516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:177503$10522_Y + connect \Y $not$libresoc.v:177251$10516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177505$10524 + cell $not $not$libresoc.v:177253$10518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$60 - connect \Y $not$libresoc.v:177505$10524_Y + connect \Y $not$libresoc.v:177253$10518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177507$10526 + cell $not $not$libresoc.v:177255$10520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $not$libresoc.v:177507$10526_Y + connect \Y $not$libresoc.v:177255$10520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177509$10528 + cell $not $not$libresoc.v:177257$10522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$68 - connect \Y $not$libresoc.v:177509$10528_Y + connect \Y $not$libresoc.v:177257$10522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177511$10530 + cell $not $not$libresoc.v:177259$10524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$72 - connect \Y $not$libresoc.v:177511$10530_Y + connect \Y $not$libresoc.v:177259$10524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177477$10496 + cell $reduce_or $reduce_or$libresoc.v:177225$10490 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:177477$10496_Y + connect \Y $reduce_or$libresoc.v:177225$10490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177479$10498 + cell $reduce_or $reduce_or$libresoc.v:177227$10492 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:177479$10498_Y + connect \Y $reduce_or$libresoc.v:177227$10492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177482$10501 + cell $reduce_or $reduce_or$libresoc.v:177230$10495 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:177482$10501_Y + connect \Y $reduce_or$libresoc.v:177230$10495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177484$10503 + cell $reduce_or $reduce_or$libresoc.v:177232$10497 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:177484$10503_Y + connect \Y $reduce_or$libresoc.v:177232$10497_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177486$10505 + cell $reduce_or $reduce_or$libresoc.v:177234$10499 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:177486$10505_Y + connect \Y $reduce_or$libresoc.v:177234$10499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177488$10507 + cell $reduce_or $reduce_or$libresoc.v:177236$10501 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:177488$10507_Y + connect \Y $reduce_or$libresoc.v:177236$10501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177490$10509 + cell $reduce_or $reduce_or$libresoc.v:177238$10503 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:177490$10509_Y + connect \Y $reduce_or$libresoc.v:177238$10503_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177492$10511 + cell $reduce_or $reduce_or$libresoc.v:177240$10505 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 connect \A { \i [9:0] \ni [10] } - connect \Y $reduce_or$libresoc.v:177492$10511_Y + connect \Y $reduce_or$libresoc.v:177240$10505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177494$10513 + cell $reduce_or $reduce_or$libresoc.v:177242$10507 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 connect \A { \i [10:0] \ni [11] } - connect \Y $reduce_or$libresoc.v:177494$10513_Y + connect \Y $reduce_or$libresoc.v:177242$10507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177496$10515 + cell $reduce_or $reduce_or$libresoc.v:177244$10509 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A { \i [11:0] \ni [12] } - connect \Y $reduce_or$libresoc.v:177496$10515_Y + connect \Y $reduce_or$libresoc.v:177244$10509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177497$10516 + cell $reduce_or $reduce_or$libresoc.v:177245$10510 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:177497$10516_Y + connect \Y $reduce_or$libresoc.v:177245$10510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177499$10518 + cell $reduce_or $reduce_or$libresoc.v:177247$10512 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A { \i [12:0] \ni [13] } - connect \Y $reduce_or$libresoc.v:177499$10518_Y + connect \Y $reduce_or$libresoc.v:177247$10512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177501$10520 + cell $reduce_or $reduce_or$libresoc.v:177249$10514 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \Y_WIDTH 1 connect \A { \i [13:0] \ni [14] } - connect \Y $reduce_or$libresoc.v:177501$10520_Y + connect \Y $reduce_or$libresoc.v:177249$10514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177504$10523 + cell $reduce_or $reduce_or$libresoc.v:177252$10517 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 1 connect \A { \i [14:0] \ni [15] } - connect \Y $reduce_or$libresoc.v:177504$10523_Y + connect \Y $reduce_or$libresoc.v:177252$10517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177506$10525 + cell $reduce_or $reduce_or$libresoc.v:177254$10519 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \Y_WIDTH 1 connect \A { \i [15:0] \ni [16] } - connect \Y $reduce_or$libresoc.v:177506$10525_Y + connect \Y $reduce_or$libresoc.v:177254$10519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177508$10527 + cell $reduce_or $reduce_or$libresoc.v:177256$10521 parameter \A_SIGNED 0 parameter \A_WIDTH 18 parameter \Y_WIDTH 1 connect \A { \i [16:0] \ni [17] } - connect \Y $reduce_or$libresoc.v:177508$10527_Y + connect \Y $reduce_or$libresoc.v:177256$10521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177510$10529 + cell $reduce_or $reduce_or$libresoc.v:177258$10523 parameter \A_SIGNED 0 parameter \A_WIDTH 19 parameter \Y_WIDTH 1 connect \A { \i [17:0] \ni [18] } - connect \Y $reduce_or$libresoc.v:177510$10529_Y + connect \Y $reduce_or$libresoc.v:177258$10523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177512$10531 + cell $reduce_or $reduce_or$libresoc.v:177260$10525 parameter \A_SIGNED 0 parameter \A_WIDTH 19 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177512$10531_Y + connect \Y $reduce_or$libresoc.v:177260$10525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177513$10532 + cell $reduce_or $reduce_or$libresoc.v:177261$10526 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:177513$10532_Y - end - connect \$7 $not$libresoc.v:177476$10495_Y - connect \$12 $reduce_or$libresoc.v:177477$10496_Y - connect \$11 $not$libresoc.v:177478$10497_Y - connect \$16 $reduce_or$libresoc.v:177479$10498_Y - connect \$15 $not$libresoc.v:177480$10499_Y - connect \$1 $not$libresoc.v:177481$10500_Y - connect \$20 $reduce_or$libresoc.v:177482$10501_Y - connect \$19 $not$libresoc.v:177483$10502_Y - connect \$24 $reduce_or$libresoc.v:177484$10503_Y - connect \$23 $not$libresoc.v:177485$10504_Y - connect \$28 $reduce_or$libresoc.v:177486$10505_Y - connect \$27 $not$libresoc.v:177487$10506_Y - connect \$32 $reduce_or$libresoc.v:177488$10507_Y - connect \$31 $not$libresoc.v:177489$10508_Y - connect \$36 $reduce_or$libresoc.v:177490$10509_Y - connect \$35 $not$libresoc.v:177491$10510_Y - connect \$40 $reduce_or$libresoc.v:177492$10511_Y - connect \$39 $not$libresoc.v:177493$10512_Y - connect \$44 $reduce_or$libresoc.v:177494$10513_Y - connect \$43 $not$libresoc.v:177495$10514_Y - connect \$48 $reduce_or$libresoc.v:177496$10515_Y - connect \$4 $reduce_or$libresoc.v:177497$10516_Y - connect \$47 $not$libresoc.v:177498$10517_Y - connect \$52 $reduce_or$libresoc.v:177499$10518_Y - connect \$51 $not$libresoc.v:177500$10519_Y - connect \$56 $reduce_or$libresoc.v:177501$10520_Y - connect \$55 $not$libresoc.v:177502$10521_Y - connect \$3 $not$libresoc.v:177503$10522_Y - connect \$60 $reduce_or$libresoc.v:177504$10523_Y - connect \$59 $not$libresoc.v:177505$10524_Y - connect \$64 $reduce_or$libresoc.v:177506$10525_Y - connect \$63 $not$libresoc.v:177507$10526_Y - connect \$68 $reduce_or$libresoc.v:177508$10527_Y - connect \$67 $not$libresoc.v:177509$10528_Y - connect \$72 $reduce_or$libresoc.v:177510$10529_Y - connect \$71 $not$libresoc.v:177511$10530_Y - connect \$75 $reduce_or$libresoc.v:177512$10531_Y - connect \$8 $reduce_or$libresoc.v:177513$10532_Y + connect \Y $reduce_or$libresoc.v:177261$10526_Y + end + connect \$7 $not$libresoc.v:177224$10489_Y + connect \$12 $reduce_or$libresoc.v:177225$10490_Y + connect \$11 $not$libresoc.v:177226$10491_Y + connect \$16 $reduce_or$libresoc.v:177227$10492_Y + connect \$15 $not$libresoc.v:177228$10493_Y + connect \$1 $not$libresoc.v:177229$10494_Y + connect \$20 $reduce_or$libresoc.v:177230$10495_Y + connect \$19 $not$libresoc.v:177231$10496_Y + connect \$24 $reduce_or$libresoc.v:177232$10497_Y + connect \$23 $not$libresoc.v:177233$10498_Y + connect \$28 $reduce_or$libresoc.v:177234$10499_Y + connect \$27 $not$libresoc.v:177235$10500_Y + connect \$32 $reduce_or$libresoc.v:177236$10501_Y + connect \$31 $not$libresoc.v:177237$10502_Y + connect \$36 $reduce_or$libresoc.v:177238$10503_Y + connect \$35 $not$libresoc.v:177239$10504_Y + connect \$40 $reduce_or$libresoc.v:177240$10505_Y + connect \$39 $not$libresoc.v:177241$10506_Y + connect \$44 $reduce_or$libresoc.v:177242$10507_Y + connect \$43 $not$libresoc.v:177243$10508_Y + connect \$48 $reduce_or$libresoc.v:177244$10509_Y + connect \$4 $reduce_or$libresoc.v:177245$10510_Y + connect \$47 $not$libresoc.v:177246$10511_Y + connect \$52 $reduce_or$libresoc.v:177247$10512_Y + connect \$51 $not$libresoc.v:177248$10513_Y + connect \$56 $reduce_or$libresoc.v:177249$10514_Y + connect \$55 $not$libresoc.v:177250$10515_Y + connect \$3 $not$libresoc.v:177251$10516_Y + connect \$60 $reduce_or$libresoc.v:177252$10517_Y + connect \$59 $not$libresoc.v:177253$10518_Y + connect \$64 $reduce_or$libresoc.v:177254$10519_Y + connect \$63 $not$libresoc.v:177255$10520_Y + connect \$68 $reduce_or$libresoc.v:177256$10521_Y + connect \$67 $not$libresoc.v:177257$10522_Y + connect \$72 $reduce_or$libresoc.v:177258$10523_Y + connect \$71 $not$libresoc.v:177259$10524_Y + connect \$75 $reduce_or$libresoc.v:177260$10525_Y + connect \$8 $reduce_or$libresoc.v:177261$10526_Y connect \en_o \$75 connect \o { \t18 \t17 \t16 \t15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t18 \$71 @@ -329159,15 +328865,15 @@ module \rdpick_INT_rabc connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:177540.1-177561.10" +attribute \src "libresoc.v:177288.1-177309.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" attribute \generator "nMigen" module \rdpick_SPR_spr1 - attribute \src "libresoc.v:177555.17-177555.89" - wire $not$libresoc.v:177555$10533_Y - attribute \src "libresoc.v:177556.17-177556.89" - wire $reduce_or$libresoc.v:177556$10534_Y + attribute \src "libresoc.v:177303.17-177303.89" + wire $not$libresoc.v:177303$10527_Y + attribute \src "libresoc.v:177304.17-177304.89" + wire $reduce_or$libresoc.v:177304$10528_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -329183,45 +328889,45 @@ module \rdpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177555$10533 + cell $not $not$libresoc.v:177303$10527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:177555$10533_Y + connect \Y $not$libresoc.v:177303$10527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177556$10534 + cell $reduce_or $reduce_or$libresoc.v:177304$10528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177556$10534_Y + connect \Y $reduce_or$libresoc.v:177304$10528_Y end - connect \$1 $not$libresoc.v:177555$10533_Y - connect \$3 $reduce_or$libresoc.v:177556$10534_Y + connect \$1 $not$libresoc.v:177303$10527_Y + connect \$3 $reduce_or$libresoc.v:177304$10528_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:177565.1-177604.10" +attribute \src "libresoc.v:177313.1-177352.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" attribute \generator "nMigen" module \rdpick_XER_xer_ca - attribute \src "libresoc.v:177592.17-177592.91" - wire $not$libresoc.v:177592$10535_Y - attribute \src "libresoc.v:177594.17-177594.89" - wire width 3 $not$libresoc.v:177594$10537_Y - attribute \src "libresoc.v:177596.17-177596.91" - wire $not$libresoc.v:177596$10539_Y - attribute \src "libresoc.v:177593.18-177593.90" - wire $reduce_or$libresoc.v:177593$10536_Y - attribute \src "libresoc.v:177595.17-177595.103" - wire $reduce_or$libresoc.v:177595$10538_Y - attribute \src "libresoc.v:177597.17-177597.105" - wire $reduce_or$libresoc.v:177597$10540_Y + attribute \src "libresoc.v:177340.17-177340.91" + wire $not$libresoc.v:177340$10529_Y + attribute \src "libresoc.v:177342.17-177342.89" + wire width 3 $not$libresoc.v:177342$10531_Y + attribute \src "libresoc.v:177344.17-177344.91" + wire $not$libresoc.v:177344$10533_Y + attribute \src "libresoc.v:177341.18-177341.90" + wire $reduce_or$libresoc.v:177341$10530_Y + attribute \src "libresoc.v:177343.17-177343.103" + wire $reduce_or$libresoc.v:177343$10532_Y + attribute \src "libresoc.v:177345.17-177345.105" + wire $reduce_or$libresoc.v:177345$10534_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -329249,59 +328955,59 @@ module \rdpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177592$10535 + cell $not $not$libresoc.v:177340$10529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:177592$10535_Y + connect \Y $not$libresoc.v:177340$10529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177594$10537 + cell $not $not$libresoc.v:177342$10531 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:177594$10537_Y + connect \Y $not$libresoc.v:177342$10531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177596$10539 + cell $not $not$libresoc.v:177344$10533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:177596$10539_Y + connect \Y $not$libresoc.v:177344$10533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177593$10536 + cell $reduce_or $reduce_or$libresoc.v:177341$10530 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177593$10536_Y + connect \Y $reduce_or$libresoc.v:177341$10530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177595$10538 + cell $reduce_or $reduce_or$libresoc.v:177343$10532 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:177595$10538_Y + connect \Y $reduce_or$libresoc.v:177343$10532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177597$10540 + cell $reduce_or $reduce_or$libresoc.v:177345$10534 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:177597$10540_Y - end - connect \$7 $not$libresoc.v:177592$10535_Y - connect \$11 $reduce_or$libresoc.v:177593$10536_Y - connect \$1 $not$libresoc.v:177594$10537_Y - connect \$4 $reduce_or$libresoc.v:177595$10538_Y - connect \$3 $not$libresoc.v:177596$10539_Y - connect \$8 $reduce_or$libresoc.v:177597$10540_Y + connect \Y $reduce_or$libresoc.v:177345$10534_Y + end + connect \$7 $not$libresoc.v:177340$10529_Y + connect \$11 $reduce_or$libresoc.v:177341$10530_Y + connect \$1 $not$libresoc.v:177342$10531_Y + connect \$4 $reduce_or$libresoc.v:177343$10532_Y + connect \$3 $not$libresoc.v:177344$10533_Y + connect \$8 $reduce_or$libresoc.v:177345$10534_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -329309,15 +329015,15 @@ module \rdpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:177608.1-177629.10" +attribute \src "libresoc.v:177356.1-177377.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" attribute \generator "nMigen" module \rdpick_XER_xer_ov - attribute \src "libresoc.v:177623.17-177623.89" - wire $not$libresoc.v:177623$10541_Y - attribute \src "libresoc.v:177624.17-177624.89" - wire $reduce_or$libresoc.v:177624$10542_Y + attribute \src "libresoc.v:177371.17-177371.89" + wire $not$libresoc.v:177371$10535_Y + attribute \src "libresoc.v:177372.17-177372.89" + wire $reduce_or$libresoc.v:177372$10536_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -329333,57 +329039,57 @@ module \rdpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177623$10541 + cell $not $not$libresoc.v:177371$10535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:177623$10541_Y + connect \Y $not$libresoc.v:177371$10535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177624$10542 + cell $reduce_or $reduce_or$libresoc.v:177372$10536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177624$10542_Y + connect \Y $reduce_or$libresoc.v:177372$10536_Y end - connect \$1 $not$libresoc.v:177623$10541_Y - connect \$3 $reduce_or$libresoc.v:177624$10542_Y + connect \$1 $not$libresoc.v:177371$10535_Y + connect \$3 $reduce_or$libresoc.v:177372$10536_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:177633.1-177699.10" +attribute \src "libresoc.v:177381.1-177447.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" attribute \generator "nMigen" module \rdpick_XER_xer_so - attribute \src "libresoc.v:177678.17-177678.91" - wire $not$libresoc.v:177678$10543_Y - attribute \src "libresoc.v:177680.18-177680.93" - wire $not$libresoc.v:177680$10545_Y - attribute \src "libresoc.v:177682.18-177682.93" - wire $not$libresoc.v:177682$10547_Y - attribute \src "libresoc.v:177683.17-177683.89" - wire width 6 $not$libresoc.v:177683$10548_Y - attribute \src "libresoc.v:177685.18-177685.93" - wire $not$libresoc.v:177685$10550_Y - attribute \src "libresoc.v:177688.17-177688.91" - wire $not$libresoc.v:177688$10553_Y - attribute \src "libresoc.v:177679.18-177679.106" - wire $reduce_or$libresoc.v:177679$10544_Y - attribute \src "libresoc.v:177681.18-177681.106" - wire $reduce_or$libresoc.v:177681$10546_Y - attribute \src "libresoc.v:177684.18-177684.106" - wire $reduce_or$libresoc.v:177684$10549_Y - attribute \src "libresoc.v:177686.18-177686.90" - wire $reduce_or$libresoc.v:177686$10551_Y - attribute \src "libresoc.v:177687.17-177687.103" - wire $reduce_or$libresoc.v:177687$10552_Y - attribute \src "libresoc.v:177689.17-177689.105" - wire $reduce_or$libresoc.v:177689$10554_Y + attribute \src "libresoc.v:177426.17-177426.91" + wire $not$libresoc.v:177426$10537_Y + attribute \src "libresoc.v:177428.18-177428.93" + wire $not$libresoc.v:177428$10539_Y + attribute \src "libresoc.v:177430.18-177430.93" + wire $not$libresoc.v:177430$10541_Y + attribute \src "libresoc.v:177431.17-177431.89" + wire width 6 $not$libresoc.v:177431$10542_Y + attribute \src "libresoc.v:177433.18-177433.93" + wire $not$libresoc.v:177433$10544_Y + attribute \src "libresoc.v:177436.17-177436.91" + wire $not$libresoc.v:177436$10547_Y + attribute \src "libresoc.v:177427.18-177427.106" + wire $reduce_or$libresoc.v:177427$10538_Y + attribute \src "libresoc.v:177429.18-177429.106" + wire $reduce_or$libresoc.v:177429$10540_Y + attribute \src "libresoc.v:177432.18-177432.106" + wire $reduce_or$libresoc.v:177432$10543_Y + attribute \src "libresoc.v:177434.18-177434.90" + wire $reduce_or$libresoc.v:177434$10545_Y + attribute \src "libresoc.v:177435.17-177435.103" + wire $reduce_or$libresoc.v:177435$10546_Y + attribute \src "libresoc.v:177437.17-177437.105" + wire $reduce_or$libresoc.v:177437$10548_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -329429,113 +329135,113 @@ module \rdpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177678$10543 + cell $not $not$libresoc.v:177426$10537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:177678$10543_Y + connect \Y $not$libresoc.v:177426$10537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177680$10545 + cell $not $not$libresoc.v:177428$10539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:177680$10545_Y + connect \Y $not$libresoc.v:177428$10539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177682$10547 + cell $not $not$libresoc.v:177430$10541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:177682$10547_Y + connect \Y $not$libresoc.v:177430$10541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:177683$10548 + cell $not $not$libresoc.v:177431$10542 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:177683$10548_Y + connect \Y $not$libresoc.v:177431$10542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177685$10550 + cell $not $not$libresoc.v:177433$10544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:177685$10550_Y + connect \Y $not$libresoc.v:177433$10544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:177688$10553 + cell $not $not$libresoc.v:177436$10547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:177688$10553_Y + connect \Y $not$libresoc.v:177436$10547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177679$10544 + cell $reduce_or $reduce_or$libresoc.v:177427$10538 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:177679$10544_Y + connect \Y $reduce_or$libresoc.v:177427$10538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177681$10546 + cell $reduce_or $reduce_or$libresoc.v:177429$10540 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:177681$10546_Y + connect \Y $reduce_or$libresoc.v:177429$10540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177684$10549 + cell $reduce_or $reduce_or$libresoc.v:177432$10543 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:177684$10549_Y + connect \Y $reduce_or$libresoc.v:177432$10543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:177686$10551 + cell $reduce_or $reduce_or$libresoc.v:177434$10545 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:177686$10551_Y + connect \Y $reduce_or$libresoc.v:177434$10545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177687$10552 + cell $reduce_or $reduce_or$libresoc.v:177435$10546 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:177687$10552_Y + connect \Y $reduce_or$libresoc.v:177435$10546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:177689$10554 + cell $reduce_or $reduce_or$libresoc.v:177437$10548 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:177689$10554_Y - end - connect \$7 $not$libresoc.v:177678$10543_Y - connect \$12 $reduce_or$libresoc.v:177679$10544_Y - connect \$11 $not$libresoc.v:177680$10545_Y - connect \$16 $reduce_or$libresoc.v:177681$10546_Y - connect \$15 $not$libresoc.v:177682$10547_Y - connect \$1 $not$libresoc.v:177683$10548_Y - connect \$20 $reduce_or$libresoc.v:177684$10549_Y - connect \$19 $not$libresoc.v:177685$10550_Y - connect \$23 $reduce_or$libresoc.v:177686$10551_Y - connect \$4 $reduce_or$libresoc.v:177687$10552_Y - connect \$3 $not$libresoc.v:177688$10553_Y - connect \$8 $reduce_or$libresoc.v:177689$10554_Y + connect \Y $reduce_or$libresoc.v:177437$10548_Y + end + connect \$7 $not$libresoc.v:177426$10537_Y + connect \$12 $reduce_or$libresoc.v:177427$10538_Y + connect \$11 $not$libresoc.v:177428$10539_Y + connect \$16 $reduce_or$libresoc.v:177429$10540_Y + connect \$15 $not$libresoc.v:177430$10541_Y + connect \$1 $not$libresoc.v:177431$10542_Y + connect \$20 $reduce_or$libresoc.v:177432$10543_Y + connect \$19 $not$libresoc.v:177433$10544_Y + connect \$23 $reduce_or$libresoc.v:177434$10545_Y + connect \$4 $reduce_or$libresoc.v:177435$10546_Y + connect \$3 $not$libresoc.v:177436$10547_Y + connect \$8 $reduce_or$libresoc.v:177437$10548_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -329546,177 +329252,177 @@ module \rdpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:177703.1-178174.10" +attribute \src "libresoc.v:177451.1-177922.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" attribute \generator "nMigen" module \reg_0 - attribute \src "libresoc.v:177704.7-177704.20" + attribute \src "libresoc.v:177452.7-177452.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178034.3-178073.6" - wire width 4 $0\r0__data_o$next[3:0]$10610 - attribute \src "libresoc.v:177789.3-177790.37" + attribute \src "libresoc.v:177782.3-177821.6" + wire width 4 $0\r0__data_o$next[3:0]$10604 + attribute \src "libresoc.v:177537.3-177538.37" wire width 4 $0\r0__data_o[3:0] - attribute \src "libresoc.v:178104.3-178143.6" - wire width 4 $0\r20__data_o$next[3:0]$10624 - attribute \src "libresoc.v:177787.3-177788.39" + attribute \src "libresoc.v:177852.3-177891.6" + wire width 4 $0\r20__data_o$next[3:0]$10618 + attribute \src "libresoc.v:177535.3-177536.39" wire width 4 $0\r20__data_o[3:0] - attribute \src "libresoc.v:177867.3-177893.6" - wire width 4 $0\reg$next[3:0]$10576 - attribute \src "libresoc.v:177785.3-177786.25" + attribute \src "libresoc.v:177615.3-177641.6" + wire width 4 $0\reg$next[3:0]$10570 + attribute \src "libresoc.v:177533.3-177534.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:177797.3-177836.6" - wire width 4 $0\src10__data_o$next[3:0]$10567 - attribute \src "libresoc.v:177795.3-177796.43" + attribute \src "libresoc.v:177545.3-177584.6" + wire width 4 $0\src10__data_o$next[3:0]$10561 + attribute \src "libresoc.v:177543.3-177544.43" wire width 4 $0\src10__data_o[3:0] - attribute \src "libresoc.v:177894.3-177933.6" - wire width 4 $0\src20__data_o$next[3:0]$10582 - attribute \src "libresoc.v:177793.3-177794.43" + attribute \src "libresoc.v:177642.3-177681.6" + wire width 4 $0\src20__data_o$next[3:0]$10576 + attribute \src "libresoc.v:177541.3-177542.43" wire width 4 $0\src20__data_o[3:0] - attribute \src "libresoc.v:177964.3-178003.6" - wire width 4 $0\src30__data_o$next[3:0]$10596 - attribute \src "libresoc.v:177791.3-177792.43" + attribute \src "libresoc.v:177712.3-177751.6" + wire width 4 $0\src30__data_o$next[3:0]$10590 + attribute \src "libresoc.v:177539.3-177540.43" wire width 4 $0\src30__data_o[3:0] - attribute \src "libresoc.v:178074.3-178103.6" - wire $0\wr_detect$10[0:0]$10618 - attribute \src "libresoc.v:178144.3-178173.6" - wire $0\wr_detect$13[0:0]$10632 - attribute \src "libresoc.v:177934.3-177963.6" - wire $0\wr_detect$4[0:0]$10590 - attribute \src "libresoc.v:178004.3-178033.6" - wire $0\wr_detect$7[0:0]$10604 - attribute \src "libresoc.v:177837.3-177866.6" + attribute \src "libresoc.v:177822.3-177851.6" + wire $0\wr_detect$10[0:0]$10612 + attribute \src "libresoc.v:177892.3-177921.6" + wire $0\wr_detect$13[0:0]$10626 + attribute \src "libresoc.v:177682.3-177711.6" + wire $0\wr_detect$4[0:0]$10584 + attribute \src "libresoc.v:177752.3-177781.6" + wire $0\wr_detect$7[0:0]$10598 + attribute \src "libresoc.v:177585.3-177614.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178034.3-178073.6" - wire width 4 $1\r0__data_o$next[3:0]$10611 - attribute \src "libresoc.v:177729.13-177729.30" + attribute \src "libresoc.v:177782.3-177821.6" + wire width 4 $1\r0__data_o$next[3:0]$10605 + attribute \src "libresoc.v:177477.13-177477.30" wire width 4 $1\r0__data_o[3:0] - attribute \src "libresoc.v:178104.3-178143.6" - wire width 4 $1\r20__data_o$next[3:0]$10625 - attribute \src "libresoc.v:177736.13-177736.31" + attribute \src "libresoc.v:177852.3-177891.6" + wire width 4 $1\r20__data_o$next[3:0]$10619 + attribute \src "libresoc.v:177484.13-177484.31" wire width 4 $1\r20__data_o[3:0] - attribute \src "libresoc.v:177867.3-177893.6" - wire width 4 $1\reg$next[3:0]$10577 - attribute \src "libresoc.v:177742.13-177742.25" + attribute \src "libresoc.v:177615.3-177641.6" + wire width 4 $1\reg$next[3:0]$10571 + attribute \src "libresoc.v:177490.13-177490.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:177797.3-177836.6" - wire width 4 $1\src10__data_o$next[3:0]$10568 - attribute \src "libresoc.v:177747.13-177747.33" + attribute \src "libresoc.v:177545.3-177584.6" + wire width 4 $1\src10__data_o$next[3:0]$10562 + attribute \src "libresoc.v:177495.13-177495.33" wire width 4 $1\src10__data_o[3:0] - attribute \src "libresoc.v:177894.3-177933.6" - wire width 4 $1\src20__data_o$next[3:0]$10583 - attribute \src "libresoc.v:177754.13-177754.33" + attribute \src "libresoc.v:177642.3-177681.6" + wire width 4 $1\src20__data_o$next[3:0]$10577 + attribute \src "libresoc.v:177502.13-177502.33" wire width 4 $1\src20__data_o[3:0] - attribute \src "libresoc.v:177964.3-178003.6" - wire width 4 $1\src30__data_o$next[3:0]$10597 - attribute \src "libresoc.v:177761.13-177761.33" + attribute \src "libresoc.v:177712.3-177751.6" + wire width 4 $1\src30__data_o$next[3:0]$10591 + attribute \src "libresoc.v:177509.13-177509.33" wire width 4 $1\src30__data_o[3:0] - attribute \src "libresoc.v:178074.3-178103.6" - wire $1\wr_detect$10[0:0]$10619 - attribute \src "libresoc.v:178144.3-178173.6" - wire $1\wr_detect$13[0:0]$10633 - attribute \src "libresoc.v:177934.3-177963.6" - wire $1\wr_detect$4[0:0]$10591 - attribute \src "libresoc.v:178004.3-178033.6" - wire $1\wr_detect$7[0:0]$10605 - attribute \src "libresoc.v:177837.3-177866.6" + attribute \src "libresoc.v:177822.3-177851.6" + wire $1\wr_detect$10[0:0]$10613 + attribute \src "libresoc.v:177892.3-177921.6" + wire $1\wr_detect$13[0:0]$10627 + attribute \src "libresoc.v:177682.3-177711.6" + wire $1\wr_detect$4[0:0]$10585 + attribute \src "libresoc.v:177752.3-177781.6" + wire $1\wr_detect$7[0:0]$10599 + attribute \src "libresoc.v:177585.3-177614.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178034.3-178073.6" - wire width 4 $2\r0__data_o$next[3:0]$10612 - attribute \src "libresoc.v:178104.3-178143.6" - wire width 4 $2\r20__data_o$next[3:0]$10626 - attribute \src "libresoc.v:177867.3-177893.6" - wire width 4 $2\reg$next[3:0]$10578 - attribute \src "libresoc.v:177797.3-177836.6" - wire width 4 $2\src10__data_o$next[3:0]$10569 - attribute \src "libresoc.v:177894.3-177933.6" - wire width 4 $2\src20__data_o$next[3:0]$10584 - attribute \src "libresoc.v:177964.3-178003.6" - wire width 4 $2\src30__data_o$next[3:0]$10598 - attribute \src "libresoc.v:178074.3-178103.6" - wire $2\wr_detect$10[0:0]$10620 - attribute \src "libresoc.v:178144.3-178173.6" - wire $2\wr_detect$13[0:0]$10634 - attribute \src "libresoc.v:177934.3-177963.6" - wire $2\wr_detect$4[0:0]$10592 - attribute \src "libresoc.v:178004.3-178033.6" - wire $2\wr_detect$7[0:0]$10606 - attribute \src "libresoc.v:177837.3-177866.6" + attribute \src "libresoc.v:177782.3-177821.6" + wire width 4 $2\r0__data_o$next[3:0]$10606 + attribute \src "libresoc.v:177852.3-177891.6" + wire width 4 $2\r20__data_o$next[3:0]$10620 + attribute \src "libresoc.v:177615.3-177641.6" + wire width 4 $2\reg$next[3:0]$10572 + attribute \src "libresoc.v:177545.3-177584.6" + wire width 4 $2\src10__data_o$next[3:0]$10563 + attribute \src "libresoc.v:177642.3-177681.6" + wire width 4 $2\src20__data_o$next[3:0]$10578 + attribute \src "libresoc.v:177712.3-177751.6" + wire width 4 $2\src30__data_o$next[3:0]$10592 + attribute \src "libresoc.v:177822.3-177851.6" + wire $2\wr_detect$10[0:0]$10614 + attribute \src "libresoc.v:177892.3-177921.6" + wire $2\wr_detect$13[0:0]$10628 + attribute \src "libresoc.v:177682.3-177711.6" + wire $2\wr_detect$4[0:0]$10586 + attribute \src "libresoc.v:177752.3-177781.6" + wire $2\wr_detect$7[0:0]$10600 + attribute \src "libresoc.v:177585.3-177614.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178034.3-178073.6" - wire width 4 $3\r0__data_o$next[3:0]$10613 - attribute \src "libresoc.v:178104.3-178143.6" - wire width 4 $3\r20__data_o$next[3:0]$10627 - attribute \src "libresoc.v:177867.3-177893.6" - wire width 4 $3\reg$next[3:0]$10579 - attribute \src "libresoc.v:177797.3-177836.6" - wire width 4 $3\src10__data_o$next[3:0]$10570 - attribute \src "libresoc.v:177894.3-177933.6" - wire width 4 $3\src20__data_o$next[3:0]$10585 - attribute \src "libresoc.v:177964.3-178003.6" - wire width 4 $3\src30__data_o$next[3:0]$10599 - attribute \src "libresoc.v:178074.3-178103.6" - wire $3\wr_detect$10[0:0]$10621 - attribute \src "libresoc.v:178144.3-178173.6" - wire $3\wr_detect$13[0:0]$10635 - attribute \src "libresoc.v:177934.3-177963.6" - wire $3\wr_detect$4[0:0]$10593 - attribute \src "libresoc.v:178004.3-178033.6" - wire $3\wr_detect$7[0:0]$10607 - attribute \src "libresoc.v:177837.3-177866.6" + attribute \src "libresoc.v:177782.3-177821.6" + wire width 4 $3\r0__data_o$next[3:0]$10607 + attribute \src "libresoc.v:177852.3-177891.6" + wire width 4 $3\r20__data_o$next[3:0]$10621 + attribute \src "libresoc.v:177615.3-177641.6" + wire width 4 $3\reg$next[3:0]$10573 + attribute \src "libresoc.v:177545.3-177584.6" + wire width 4 $3\src10__data_o$next[3:0]$10564 + attribute \src "libresoc.v:177642.3-177681.6" + wire width 4 $3\src20__data_o$next[3:0]$10579 + attribute \src "libresoc.v:177712.3-177751.6" + wire width 4 $3\src30__data_o$next[3:0]$10593 + attribute \src "libresoc.v:177822.3-177851.6" + wire $3\wr_detect$10[0:0]$10615 + attribute \src "libresoc.v:177892.3-177921.6" + wire $3\wr_detect$13[0:0]$10629 + attribute \src "libresoc.v:177682.3-177711.6" + wire $3\wr_detect$4[0:0]$10587 + attribute \src "libresoc.v:177752.3-177781.6" + wire $3\wr_detect$7[0:0]$10601 + attribute \src "libresoc.v:177585.3-177614.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178034.3-178073.6" - wire width 4 $4\r0__data_o$next[3:0]$10614 - attribute \src "libresoc.v:178104.3-178143.6" - wire width 4 $4\r20__data_o$next[3:0]$10628 - attribute \src "libresoc.v:177867.3-177893.6" - wire width 4 $4\reg$next[3:0]$10580 - attribute \src "libresoc.v:177797.3-177836.6" - wire width 4 $4\src10__data_o$next[3:0]$10571 - attribute \src "libresoc.v:177894.3-177933.6" - wire width 4 $4\src20__data_o$next[3:0]$10586 - attribute \src "libresoc.v:177964.3-178003.6" - wire width 4 $4\src30__data_o$next[3:0]$10600 - attribute \src "libresoc.v:178074.3-178103.6" - wire $4\wr_detect$10[0:0]$10622 - attribute \src "libresoc.v:178144.3-178173.6" - wire $4\wr_detect$13[0:0]$10636 - attribute \src "libresoc.v:177934.3-177963.6" - wire $4\wr_detect$4[0:0]$10594 - attribute \src "libresoc.v:178004.3-178033.6" - wire $4\wr_detect$7[0:0]$10608 - attribute \src "libresoc.v:177837.3-177866.6" + attribute \src "libresoc.v:177782.3-177821.6" + wire width 4 $4\r0__data_o$next[3:0]$10608 + attribute \src "libresoc.v:177852.3-177891.6" + wire width 4 $4\r20__data_o$next[3:0]$10622 + attribute \src "libresoc.v:177615.3-177641.6" + wire width 4 $4\reg$next[3:0]$10574 + attribute \src "libresoc.v:177545.3-177584.6" + wire width 4 $4\src10__data_o$next[3:0]$10565 + attribute \src "libresoc.v:177642.3-177681.6" + wire width 4 $4\src20__data_o$next[3:0]$10580 + attribute \src "libresoc.v:177712.3-177751.6" + wire width 4 $4\src30__data_o$next[3:0]$10594 + attribute \src "libresoc.v:177822.3-177851.6" + wire $4\wr_detect$10[0:0]$10616 + attribute \src "libresoc.v:177892.3-177921.6" + wire $4\wr_detect$13[0:0]$10630 + attribute \src "libresoc.v:177682.3-177711.6" + wire $4\wr_detect$4[0:0]$10588 + attribute \src "libresoc.v:177752.3-177781.6" + wire $4\wr_detect$7[0:0]$10602 + attribute \src "libresoc.v:177585.3-177614.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178034.3-178073.6" - wire width 4 $5\r0__data_o$next[3:0]$10615 - attribute \src "libresoc.v:178104.3-178143.6" - wire width 4 $5\r20__data_o$next[3:0]$10629 - attribute \src "libresoc.v:177797.3-177836.6" - wire width 4 $5\src10__data_o$next[3:0]$10572 - attribute \src "libresoc.v:177894.3-177933.6" - wire width 4 $5\src20__data_o$next[3:0]$10587 - attribute \src "libresoc.v:177964.3-178003.6" - wire width 4 $5\src30__data_o$next[3:0]$10601 - attribute \src "libresoc.v:178034.3-178073.6" - wire width 4 $6\r0__data_o$next[3:0]$10616 - attribute \src "libresoc.v:178104.3-178143.6" - wire width 4 $6\r20__data_o$next[3:0]$10630 - attribute \src "libresoc.v:177797.3-177836.6" - wire width 4 $6\src10__data_o$next[3:0]$10573 - attribute \src "libresoc.v:177894.3-177933.6" - wire width 4 $6\src20__data_o$next[3:0]$10588 - attribute \src "libresoc.v:177964.3-178003.6" - wire width 4 $6\src30__data_o$next[3:0]$10602 - attribute \src "libresoc.v:177780.17-177780.104" - wire $not$libresoc.v:177780$10555_Y - attribute \src "libresoc.v:177781.18-177781.105" - wire $not$libresoc.v:177781$10556_Y - attribute \src "libresoc.v:177782.17-177782.100" - wire $not$libresoc.v:177782$10557_Y - attribute \src "libresoc.v:177783.17-177783.103" - wire $not$libresoc.v:177783$10558_Y - attribute \src "libresoc.v:177784.17-177784.103" - wire $not$libresoc.v:177784$10559_Y + attribute \src "libresoc.v:177782.3-177821.6" + wire width 4 $5\r0__data_o$next[3:0]$10609 + attribute \src "libresoc.v:177852.3-177891.6" + wire width 4 $5\r20__data_o$next[3:0]$10623 + attribute \src "libresoc.v:177545.3-177584.6" + wire width 4 $5\src10__data_o$next[3:0]$10566 + attribute \src "libresoc.v:177642.3-177681.6" + wire width 4 $5\src20__data_o$next[3:0]$10581 + attribute \src "libresoc.v:177712.3-177751.6" + wire width 4 $5\src30__data_o$next[3:0]$10595 + attribute \src "libresoc.v:177782.3-177821.6" + wire width 4 $6\r0__data_o$next[3:0]$10610 + attribute \src "libresoc.v:177852.3-177891.6" + wire width 4 $6\r20__data_o$next[3:0]$10624 + attribute \src "libresoc.v:177545.3-177584.6" + wire width 4 $6\src10__data_o$next[3:0]$10567 + attribute \src "libresoc.v:177642.3-177681.6" + wire width 4 $6\src20__data_o$next[3:0]$10582 + attribute \src "libresoc.v:177712.3-177751.6" + wire width 4 $6\src30__data_o$next[3:0]$10596 + attribute \src "libresoc.v:177528.17-177528.104" + wire $not$libresoc.v:177528$10549_Y + attribute \src "libresoc.v:177529.18-177529.105" + wire $not$libresoc.v:177529$10550_Y + attribute \src "libresoc.v:177530.17-177530.100" + wire $not$libresoc.v:177530$10551_Y + attribute \src "libresoc.v:177531.17-177531.103" + wire $not$libresoc.v:177531$10552_Y + attribute \src "libresoc.v:177532.17-177532.103" + wire $not$libresoc.v:177532$10553_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -329727,9 +329433,9 @@ module \reg_0 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest10__data_i @@ -329739,7 +329445,7 @@ module \reg_0 wire width 4 input 11 \dest20__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest20__wen - attribute \src "libresoc.v:177704.7-177704.15" + attribute \src "libresoc.v:177452.7-177452.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r0__data_o @@ -329790,152 +329496,152 @@ module \reg_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177780$10555 + cell $not $not$libresoc.v:177528$10549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:177780$10555_Y + connect \Y $not$libresoc.v:177528$10549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177781$10556 + cell $not $not$libresoc.v:177529$10550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:177781$10556_Y + connect \Y $not$libresoc.v:177529$10550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177782$10557 + cell $not $not$libresoc.v:177530$10551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177782$10557_Y + connect \Y $not$libresoc.v:177530$10551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177783$10558 + cell $not $not$libresoc.v:177531$10552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177783$10558_Y + connect \Y $not$libresoc.v:177531$10552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177784$10559 + cell $not $not$libresoc.v:177532$10553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177784$10559_Y + connect \Y $not$libresoc.v:177532$10553_Y end - attribute \src "libresoc.v:177704.7-177704.20" - process $proc$libresoc.v:177704$10637 + attribute \src "libresoc.v:177452.7-177452.20" + process $proc$libresoc.v:177452$10631 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177729.13-177729.30" - process $proc$libresoc.v:177729$10638 + attribute \src "libresoc.v:177477.13-177477.30" + process $proc$libresoc.v:177477$10632 assign { } { } assign $1\r0__data_o[3:0] 4'0000 sync always sync init update \r0__data_o $1\r0__data_o[3:0] end - attribute \src "libresoc.v:177736.13-177736.31" - process $proc$libresoc.v:177736$10639 + attribute \src "libresoc.v:177484.13-177484.31" + process $proc$libresoc.v:177484$10633 assign { } { } assign $1\r20__data_o[3:0] 4'0000 sync always sync init update \r20__data_o $1\r20__data_o[3:0] end - attribute \src "libresoc.v:177742.13-177742.25" - process $proc$libresoc.v:177742$10640 + attribute \src "libresoc.v:177490.13-177490.25" + process $proc$libresoc.v:177490$10634 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:177747.13-177747.33" - process $proc$libresoc.v:177747$10641 + attribute \src "libresoc.v:177495.13-177495.33" + process $proc$libresoc.v:177495$10635 assign { } { } assign $1\src10__data_o[3:0] 4'0000 sync always sync init update \src10__data_o $1\src10__data_o[3:0] end - attribute \src "libresoc.v:177754.13-177754.33" - process $proc$libresoc.v:177754$10642 + attribute \src "libresoc.v:177502.13-177502.33" + process $proc$libresoc.v:177502$10636 assign { } { } assign $1\src20__data_o[3:0] 4'0000 sync always sync init update \src20__data_o $1\src20__data_o[3:0] end - attribute \src "libresoc.v:177761.13-177761.33" - process $proc$libresoc.v:177761$10643 + attribute \src "libresoc.v:177509.13-177509.33" + process $proc$libresoc.v:177509$10637 assign { } { } assign $1\src30__data_o[3:0] 4'0000 sync always sync init update \src30__data_o $1\src30__data_o[3:0] end - attribute \src "libresoc.v:177785.3-177786.25" - process $proc$libresoc.v:177785$10560 + attribute \src "libresoc.v:177533.3-177534.25" + process $proc$libresoc.v:177533$10554 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:177787.3-177788.39" - process $proc$libresoc.v:177787$10561 + attribute \src "libresoc.v:177535.3-177536.39" + process $proc$libresoc.v:177535$10555 assign { } { } assign $0\r20__data_o[3:0] \r20__data_o$next sync posedge \coresync_clk update \r20__data_o $0\r20__data_o[3:0] end - attribute \src "libresoc.v:177789.3-177790.37" - process $proc$libresoc.v:177789$10562 + attribute \src "libresoc.v:177537.3-177538.37" + process $proc$libresoc.v:177537$10556 assign { } { } assign $0\r0__data_o[3:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[3:0] end - attribute \src "libresoc.v:177791.3-177792.43" - process $proc$libresoc.v:177791$10563 + attribute \src "libresoc.v:177539.3-177540.43" + process $proc$libresoc.v:177539$10557 assign { } { } assign $0\src30__data_o[3:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[3:0] end - attribute \src "libresoc.v:177793.3-177794.43" - process $proc$libresoc.v:177793$10564 + attribute \src "libresoc.v:177541.3-177542.43" + process $proc$libresoc.v:177541$10558 assign { } { } assign $0\src20__data_o[3:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[3:0] end - attribute \src "libresoc.v:177795.3-177796.43" - process $proc$libresoc.v:177795$10565 + attribute \src "libresoc.v:177543.3-177544.43" + process $proc$libresoc.v:177543$10559 assign { } { } assign $0\src10__data_o[3:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[3:0] end - attribute \src "libresoc.v:177797.3-177836.6" - process $proc$libresoc.v:177797$10566 + attribute \src "libresoc.v:177545.3-177584.6" + process $proc$libresoc.v:177545$10560 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[3:0]$10567 $6\src10__data_o$next[3:0]$10573 - attribute \src "libresoc.v:177798.5-177798.29" + assign $0\src10__data_o$next[3:0]$10561 $6\src10__data_o$next[3:0]$10567 + attribute \src "libresoc.v:177546.5-177546.29" switch \initial - attribute \src "libresoc.v:177798.9-177798.17" + attribute \src "libresoc.v:177546.9-177546.17" case 1'1 case end @@ -329947,66 +329653,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[3:0]$10568 $5\src10__data_o$next[3:0]$10572 + assign $1\src10__data_o$next[3:0]$10562 $5\src10__data_o$next[3:0]$10566 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[3:0]$10569 \dest10__data_i + assign $2\src10__data_o$next[3:0]$10563 \dest10__data_i case - assign $2\src10__data_o$next[3:0]$10569 4'0000 + assign $2\src10__data_o$next[3:0]$10563 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[3:0]$10570 \dest20__data_i + assign $3\src10__data_o$next[3:0]$10564 \dest20__data_i case - assign $3\src10__data_o$next[3:0]$10570 $2\src10__data_o$next[3:0]$10569 + assign $3\src10__data_o$next[3:0]$10564 $2\src10__data_o$next[3:0]$10563 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[3:0]$10571 \w0__data_i + assign $4\src10__data_o$next[3:0]$10565 \w0__data_i case - assign $4\src10__data_o$next[3:0]$10571 $3\src10__data_o$next[3:0]$10570 + assign $4\src10__data_o$next[3:0]$10565 $3\src10__data_o$next[3:0]$10564 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[3:0]$10572 \reg + assign $5\src10__data_o$next[3:0]$10566 \reg case - assign $5\src10__data_o$next[3:0]$10572 $4\src10__data_o$next[3:0]$10571 + assign $5\src10__data_o$next[3:0]$10566 $4\src10__data_o$next[3:0]$10565 end case - assign $1\src10__data_o$next[3:0]$10568 4'0000 + assign $1\src10__data_o$next[3:0]$10562 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[3:0]$10573 4'0000 + assign $6\src10__data_o$next[3:0]$10567 4'0000 case - assign $6\src10__data_o$next[3:0]$10573 $1\src10__data_o$next[3:0]$10568 + assign $6\src10__data_o$next[3:0]$10567 $1\src10__data_o$next[3:0]$10562 end sync always - update \src10__data_o$next $0\src10__data_o$next[3:0]$10567 + update \src10__data_o$next $0\src10__data_o$next[3:0]$10561 end - attribute \src "libresoc.v:177837.3-177866.6" - process $proc$libresoc.v:177837$10574 + attribute \src "libresoc.v:177585.3-177614.6" + process $proc$libresoc.v:177585$10568 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177838.5-177838.29" + attribute \src "libresoc.v:177586.5-177586.29" switch \initial - attribute \src "libresoc.v:177838.9-177838.17" + attribute \src "libresoc.v:177586.9-177586.17" case 1'1 case end @@ -330052,17 +329758,17 @@ module \reg_0 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177867.3-177893.6" - process $proc$libresoc.v:177867$10575 + attribute \src "libresoc.v:177615.3-177641.6" + process $proc$libresoc.v:177615$10569 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10576 $4\reg$next[3:0]$10580 - attribute \src "libresoc.v:177868.5-177868.29" + assign $0\reg$next[3:0]$10570 $4\reg$next[3:0]$10574 + attribute \src "libresoc.v:177616.5-177616.29" switch \initial - attribute \src "libresoc.v:177868.9-177868.17" + attribute \src "libresoc.v:177616.9-177616.17" case 1'1 case end @@ -330071,49 +329777,49 @@ module \reg_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10577 \dest10__data_i + assign $1\reg$next[3:0]$10571 \dest10__data_i case - assign $1\reg$next[3:0]$10577 \reg + assign $1\reg$next[3:0]$10571 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10578 \dest20__data_i + assign $2\reg$next[3:0]$10572 \dest20__data_i case - assign $2\reg$next[3:0]$10578 $1\reg$next[3:0]$10577 + assign $2\reg$next[3:0]$10572 $1\reg$next[3:0]$10571 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10579 \w0__data_i + assign $3\reg$next[3:0]$10573 \w0__data_i case - assign $3\reg$next[3:0]$10579 $2\reg$next[3:0]$10578 + assign $3\reg$next[3:0]$10573 $2\reg$next[3:0]$10572 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10580 4'0000 + assign $4\reg$next[3:0]$10574 4'0000 case - assign $4\reg$next[3:0]$10580 $3\reg$next[3:0]$10579 + assign $4\reg$next[3:0]$10574 $3\reg$next[3:0]$10573 end sync always - update \reg$next $0\reg$next[3:0]$10576 + update \reg$next $0\reg$next[3:0]$10570 end - attribute \src "libresoc.v:177894.3-177933.6" - process $proc$libresoc.v:177894$10581 + attribute \src "libresoc.v:177642.3-177681.6" + process $proc$libresoc.v:177642$10575 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[3:0]$10582 $6\src20__data_o$next[3:0]$10588 - attribute \src "libresoc.v:177895.5-177895.29" + assign $0\src20__data_o$next[3:0]$10576 $6\src20__data_o$next[3:0]$10582 + attribute \src "libresoc.v:177643.5-177643.29" switch \initial - attribute \src "libresoc.v:177895.9-177895.17" + attribute \src "libresoc.v:177643.9-177643.17" case 1'1 case end @@ -330125,66 +329831,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[3:0]$10583 $5\src20__data_o$next[3:0]$10587 + assign $1\src20__data_o$next[3:0]$10577 $5\src20__data_o$next[3:0]$10581 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[3:0]$10584 \dest10__data_i + assign $2\src20__data_o$next[3:0]$10578 \dest10__data_i case - assign $2\src20__data_o$next[3:0]$10584 4'0000 + assign $2\src20__data_o$next[3:0]$10578 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[3:0]$10585 \dest20__data_i + assign $3\src20__data_o$next[3:0]$10579 \dest20__data_i case - assign $3\src20__data_o$next[3:0]$10585 $2\src20__data_o$next[3:0]$10584 + assign $3\src20__data_o$next[3:0]$10579 $2\src20__data_o$next[3:0]$10578 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[3:0]$10586 \w0__data_i + assign $4\src20__data_o$next[3:0]$10580 \w0__data_i case - assign $4\src20__data_o$next[3:0]$10586 $3\src20__data_o$next[3:0]$10585 + assign $4\src20__data_o$next[3:0]$10580 $3\src20__data_o$next[3:0]$10579 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[3:0]$10587 \reg + assign $5\src20__data_o$next[3:0]$10581 \reg case - assign $5\src20__data_o$next[3:0]$10587 $4\src20__data_o$next[3:0]$10586 + assign $5\src20__data_o$next[3:0]$10581 $4\src20__data_o$next[3:0]$10580 end case - assign $1\src20__data_o$next[3:0]$10583 4'0000 + assign $1\src20__data_o$next[3:0]$10577 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[3:0]$10588 4'0000 + assign $6\src20__data_o$next[3:0]$10582 4'0000 case - assign $6\src20__data_o$next[3:0]$10588 $1\src20__data_o$next[3:0]$10583 + assign $6\src20__data_o$next[3:0]$10582 $1\src20__data_o$next[3:0]$10577 end sync always - update \src20__data_o$next $0\src20__data_o$next[3:0]$10582 + update \src20__data_o$next $0\src20__data_o$next[3:0]$10576 end - attribute \src "libresoc.v:177934.3-177963.6" - process $proc$libresoc.v:177934$10589 + attribute \src "libresoc.v:177682.3-177711.6" + process $proc$libresoc.v:177682$10583 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10590 $1\wr_detect$4[0:0]$10591 - attribute \src "libresoc.v:177935.5-177935.29" + assign $0\wr_detect$4[0:0]$10584 $1\wr_detect$4[0:0]$10585 + attribute \src "libresoc.v:177683.5-177683.29" switch \initial - attribute \src "libresoc.v:177935.9-177935.17" + attribute \src "libresoc.v:177683.9-177683.17" case 1'1 case end @@ -330196,49 +329902,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10591 $4\wr_detect$4[0:0]$10594 + assign $1\wr_detect$4[0:0]$10585 $4\wr_detect$4[0:0]$10588 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10592 1'1 + assign $2\wr_detect$4[0:0]$10586 1'1 case - assign $2\wr_detect$4[0:0]$10592 1'0 + assign $2\wr_detect$4[0:0]$10586 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10593 1'1 + assign $3\wr_detect$4[0:0]$10587 1'1 case - assign $3\wr_detect$4[0:0]$10593 $2\wr_detect$4[0:0]$10592 + assign $3\wr_detect$4[0:0]$10587 $2\wr_detect$4[0:0]$10586 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10594 1'1 + assign $4\wr_detect$4[0:0]$10588 1'1 case - assign $4\wr_detect$4[0:0]$10594 $3\wr_detect$4[0:0]$10593 + assign $4\wr_detect$4[0:0]$10588 $3\wr_detect$4[0:0]$10587 end case - assign $1\wr_detect$4[0:0]$10591 1'0 + assign $1\wr_detect$4[0:0]$10585 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10590 + update \wr_detect$4 $0\wr_detect$4[0:0]$10584 end - attribute \src "libresoc.v:177964.3-178003.6" - process $proc$libresoc.v:177964$10595 + attribute \src "libresoc.v:177712.3-177751.6" + process $proc$libresoc.v:177712$10589 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[3:0]$10596 $6\src30__data_o$next[3:0]$10602 - attribute \src "libresoc.v:177965.5-177965.29" + assign $0\src30__data_o$next[3:0]$10590 $6\src30__data_o$next[3:0]$10596 + attribute \src "libresoc.v:177713.5-177713.29" switch \initial - attribute \src "libresoc.v:177965.9-177965.17" + attribute \src "libresoc.v:177713.9-177713.17" case 1'1 case end @@ -330250,66 +329956,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[3:0]$10597 $5\src30__data_o$next[3:0]$10601 + assign $1\src30__data_o$next[3:0]$10591 $5\src30__data_o$next[3:0]$10595 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[3:0]$10598 \dest10__data_i + assign $2\src30__data_o$next[3:0]$10592 \dest10__data_i case - assign $2\src30__data_o$next[3:0]$10598 4'0000 + assign $2\src30__data_o$next[3:0]$10592 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[3:0]$10599 \dest20__data_i + assign $3\src30__data_o$next[3:0]$10593 \dest20__data_i case - assign $3\src30__data_o$next[3:0]$10599 $2\src30__data_o$next[3:0]$10598 + assign $3\src30__data_o$next[3:0]$10593 $2\src30__data_o$next[3:0]$10592 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[3:0]$10600 \w0__data_i + assign $4\src30__data_o$next[3:0]$10594 \w0__data_i case - assign $4\src30__data_o$next[3:0]$10600 $3\src30__data_o$next[3:0]$10599 + assign $4\src30__data_o$next[3:0]$10594 $3\src30__data_o$next[3:0]$10593 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[3:0]$10601 \reg + assign $5\src30__data_o$next[3:0]$10595 \reg case - assign $5\src30__data_o$next[3:0]$10601 $4\src30__data_o$next[3:0]$10600 + assign $5\src30__data_o$next[3:0]$10595 $4\src30__data_o$next[3:0]$10594 end case - assign $1\src30__data_o$next[3:0]$10597 4'0000 + assign $1\src30__data_o$next[3:0]$10591 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[3:0]$10602 4'0000 + assign $6\src30__data_o$next[3:0]$10596 4'0000 case - assign $6\src30__data_o$next[3:0]$10602 $1\src30__data_o$next[3:0]$10597 + assign $6\src30__data_o$next[3:0]$10596 $1\src30__data_o$next[3:0]$10591 end sync always - update \src30__data_o$next $0\src30__data_o$next[3:0]$10596 + update \src30__data_o$next $0\src30__data_o$next[3:0]$10590 end - attribute \src "libresoc.v:178004.3-178033.6" - process $proc$libresoc.v:178004$10603 + attribute \src "libresoc.v:177752.3-177781.6" + process $proc$libresoc.v:177752$10597 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10604 $1\wr_detect$7[0:0]$10605 - attribute \src "libresoc.v:178005.5-178005.29" + assign $0\wr_detect$7[0:0]$10598 $1\wr_detect$7[0:0]$10599 + attribute \src "libresoc.v:177753.5-177753.29" switch \initial - attribute \src "libresoc.v:178005.9-178005.17" + attribute \src "libresoc.v:177753.9-177753.17" case 1'1 case end @@ -330321,49 +330027,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10605 $4\wr_detect$7[0:0]$10608 + assign $1\wr_detect$7[0:0]$10599 $4\wr_detect$7[0:0]$10602 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10606 1'1 + assign $2\wr_detect$7[0:0]$10600 1'1 case - assign $2\wr_detect$7[0:0]$10606 1'0 + assign $2\wr_detect$7[0:0]$10600 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10607 1'1 + assign $3\wr_detect$7[0:0]$10601 1'1 case - assign $3\wr_detect$7[0:0]$10607 $2\wr_detect$7[0:0]$10606 + assign $3\wr_detect$7[0:0]$10601 $2\wr_detect$7[0:0]$10600 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10608 1'1 + assign $4\wr_detect$7[0:0]$10602 1'1 case - assign $4\wr_detect$7[0:0]$10608 $3\wr_detect$7[0:0]$10607 + assign $4\wr_detect$7[0:0]$10602 $3\wr_detect$7[0:0]$10601 end case - assign $1\wr_detect$7[0:0]$10605 1'0 + assign $1\wr_detect$7[0:0]$10599 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10604 + update \wr_detect$7 $0\wr_detect$7[0:0]$10598 end - attribute \src "libresoc.v:178034.3-178073.6" - process $proc$libresoc.v:178034$10609 + attribute \src "libresoc.v:177782.3-177821.6" + process $proc$libresoc.v:177782$10603 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[3:0]$10610 $6\r0__data_o$next[3:0]$10616 - attribute \src "libresoc.v:178035.5-178035.29" + assign $0\r0__data_o$next[3:0]$10604 $6\r0__data_o$next[3:0]$10610 + attribute \src "libresoc.v:177783.5-177783.29" switch \initial - attribute \src "libresoc.v:178035.9-178035.17" + attribute \src "libresoc.v:177783.9-177783.17" case 1'1 case end @@ -330375,66 +330081,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[3:0]$10611 $5\r0__data_o$next[3:0]$10615 + assign $1\r0__data_o$next[3:0]$10605 $5\r0__data_o$next[3:0]$10609 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[3:0]$10612 \dest10__data_i + assign $2\r0__data_o$next[3:0]$10606 \dest10__data_i case - assign $2\r0__data_o$next[3:0]$10612 4'0000 + assign $2\r0__data_o$next[3:0]$10606 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[3:0]$10613 \dest20__data_i + assign $3\r0__data_o$next[3:0]$10607 \dest20__data_i case - assign $3\r0__data_o$next[3:0]$10613 $2\r0__data_o$next[3:0]$10612 + assign $3\r0__data_o$next[3:0]$10607 $2\r0__data_o$next[3:0]$10606 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[3:0]$10614 \w0__data_i + assign $4\r0__data_o$next[3:0]$10608 \w0__data_i case - assign $4\r0__data_o$next[3:0]$10614 $3\r0__data_o$next[3:0]$10613 + assign $4\r0__data_o$next[3:0]$10608 $3\r0__data_o$next[3:0]$10607 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[3:0]$10615 \reg + assign $5\r0__data_o$next[3:0]$10609 \reg case - assign $5\r0__data_o$next[3:0]$10615 $4\r0__data_o$next[3:0]$10614 + assign $5\r0__data_o$next[3:0]$10609 $4\r0__data_o$next[3:0]$10608 end case - assign $1\r0__data_o$next[3:0]$10611 4'0000 + assign $1\r0__data_o$next[3:0]$10605 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[3:0]$10616 4'0000 + assign $6\r0__data_o$next[3:0]$10610 4'0000 case - assign $6\r0__data_o$next[3:0]$10616 $1\r0__data_o$next[3:0]$10611 + assign $6\r0__data_o$next[3:0]$10610 $1\r0__data_o$next[3:0]$10605 end sync always - update \r0__data_o$next $0\r0__data_o$next[3:0]$10610 + update \r0__data_o$next $0\r0__data_o$next[3:0]$10604 end - attribute \src "libresoc.v:178074.3-178103.6" - process $proc$libresoc.v:178074$10617 + attribute \src "libresoc.v:177822.3-177851.6" + process $proc$libresoc.v:177822$10611 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10618 $1\wr_detect$10[0:0]$10619 - attribute \src "libresoc.v:178075.5-178075.29" + assign $0\wr_detect$10[0:0]$10612 $1\wr_detect$10[0:0]$10613 + attribute \src "libresoc.v:177823.5-177823.29" switch \initial - attribute \src "libresoc.v:178075.9-178075.17" + attribute \src "libresoc.v:177823.9-177823.17" case 1'1 case end @@ -330446,49 +330152,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10619 $4\wr_detect$10[0:0]$10622 + assign $1\wr_detect$10[0:0]$10613 $4\wr_detect$10[0:0]$10616 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10620 1'1 + assign $2\wr_detect$10[0:0]$10614 1'1 case - assign $2\wr_detect$10[0:0]$10620 1'0 + assign $2\wr_detect$10[0:0]$10614 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10621 1'1 + assign $3\wr_detect$10[0:0]$10615 1'1 case - assign $3\wr_detect$10[0:0]$10621 $2\wr_detect$10[0:0]$10620 + assign $3\wr_detect$10[0:0]$10615 $2\wr_detect$10[0:0]$10614 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10622 1'1 + assign $4\wr_detect$10[0:0]$10616 1'1 case - assign $4\wr_detect$10[0:0]$10622 $3\wr_detect$10[0:0]$10621 + assign $4\wr_detect$10[0:0]$10616 $3\wr_detect$10[0:0]$10615 end case - assign $1\wr_detect$10[0:0]$10619 1'0 + assign $1\wr_detect$10[0:0]$10613 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10618 + update \wr_detect$10 $0\wr_detect$10[0:0]$10612 end - attribute \src "libresoc.v:178104.3-178143.6" - process $proc$libresoc.v:178104$10623 + attribute \src "libresoc.v:177852.3-177891.6" + process $proc$libresoc.v:177852$10617 assign { } { } assign { } { } assign { } { } - assign $0\r20__data_o$next[3:0]$10624 $6\r20__data_o$next[3:0]$10630 - attribute \src "libresoc.v:178105.5-178105.29" + assign $0\r20__data_o$next[3:0]$10618 $6\r20__data_o$next[3:0]$10624 + attribute \src "libresoc.v:177853.5-177853.29" switch \initial - attribute \src "libresoc.v:178105.9-178105.17" + attribute \src "libresoc.v:177853.9-177853.17" case 1'1 case end @@ -330500,66 +330206,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r20__data_o$next[3:0]$10625 $5\r20__data_o$next[3:0]$10629 + assign $1\r20__data_o$next[3:0]$10619 $5\r20__data_o$next[3:0]$10623 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r20__data_o$next[3:0]$10626 \dest10__data_i + assign $2\r20__data_o$next[3:0]$10620 \dest10__data_i case - assign $2\r20__data_o$next[3:0]$10626 4'0000 + assign $2\r20__data_o$next[3:0]$10620 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r20__data_o$next[3:0]$10627 \dest20__data_i + assign $3\r20__data_o$next[3:0]$10621 \dest20__data_i case - assign $3\r20__data_o$next[3:0]$10627 $2\r20__data_o$next[3:0]$10626 + assign $3\r20__data_o$next[3:0]$10621 $2\r20__data_o$next[3:0]$10620 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r20__data_o$next[3:0]$10628 \w0__data_i + assign $4\r20__data_o$next[3:0]$10622 \w0__data_i case - assign $4\r20__data_o$next[3:0]$10628 $3\r20__data_o$next[3:0]$10627 + assign $4\r20__data_o$next[3:0]$10622 $3\r20__data_o$next[3:0]$10621 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r20__data_o$next[3:0]$10629 \reg + assign $5\r20__data_o$next[3:0]$10623 \reg case - assign $5\r20__data_o$next[3:0]$10629 $4\r20__data_o$next[3:0]$10628 + assign $5\r20__data_o$next[3:0]$10623 $4\r20__data_o$next[3:0]$10622 end case - assign $1\r20__data_o$next[3:0]$10625 4'0000 + assign $1\r20__data_o$next[3:0]$10619 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r20__data_o$next[3:0]$10630 4'0000 + assign $6\r20__data_o$next[3:0]$10624 4'0000 case - assign $6\r20__data_o$next[3:0]$10630 $1\r20__data_o$next[3:0]$10625 + assign $6\r20__data_o$next[3:0]$10624 $1\r20__data_o$next[3:0]$10619 end sync always - update \r20__data_o$next $0\r20__data_o$next[3:0]$10624 + update \r20__data_o$next $0\r20__data_o$next[3:0]$10618 end - attribute \src "libresoc.v:178144.3-178173.6" - process $proc$libresoc.v:178144$10631 + attribute \src "libresoc.v:177892.3-177921.6" + process $proc$libresoc.v:177892$10625 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10632 $1\wr_detect$13[0:0]$10633 - attribute \src "libresoc.v:178145.5-178145.29" + assign $0\wr_detect$13[0:0]$10626 $1\wr_detect$13[0:0]$10627 + attribute \src "libresoc.v:177893.5-177893.29" switch \initial - attribute \src "libresoc.v:178145.9-178145.17" + attribute \src "libresoc.v:177893.9-177893.17" case 1'1 case end @@ -330571,205 +330277,205 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10633 $4\wr_detect$13[0:0]$10636 + assign $1\wr_detect$13[0:0]$10627 $4\wr_detect$13[0:0]$10630 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10634 1'1 + assign $2\wr_detect$13[0:0]$10628 1'1 case - assign $2\wr_detect$13[0:0]$10634 1'0 + assign $2\wr_detect$13[0:0]$10628 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10635 1'1 + assign $3\wr_detect$13[0:0]$10629 1'1 case - assign $3\wr_detect$13[0:0]$10635 $2\wr_detect$13[0:0]$10634 + assign $3\wr_detect$13[0:0]$10629 $2\wr_detect$13[0:0]$10628 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10636 1'1 + assign $4\wr_detect$13[0:0]$10630 1'1 case - assign $4\wr_detect$13[0:0]$10636 $3\wr_detect$13[0:0]$10635 + assign $4\wr_detect$13[0:0]$10630 $3\wr_detect$13[0:0]$10629 end case - assign $1\wr_detect$13[0:0]$10633 1'0 + assign $1\wr_detect$13[0:0]$10627 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10632 + update \wr_detect$13 $0\wr_detect$13[0:0]$10626 end - connect \$9 $not$libresoc.v:177780$10555_Y - connect \$12 $not$libresoc.v:177781$10556_Y - connect \$1 $not$libresoc.v:177782$10557_Y - connect \$3 $not$libresoc.v:177783$10558_Y - connect \$6 $not$libresoc.v:177784$10559_Y + connect \$9 $not$libresoc.v:177528$10549_Y + connect \$12 $not$libresoc.v:177529$10550_Y + connect \$1 $not$libresoc.v:177530$10551_Y + connect \$3 $not$libresoc.v:177531$10552_Y + connect \$6 $not$libresoc.v:177532$10553_Y end -attribute \src "libresoc.v:178178.1-178623.10" +attribute \src "libresoc.v:177926.1-178371.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" attribute \generator "nMigen" module \reg_0$132 - attribute \src "libresoc.v:178179.7-178179.20" + attribute \src "libresoc.v:177927.7-177927.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178508.3-178553.6" - wire width 2 $0\r0__data_o$next[1:0]$10696 - attribute \src "libresoc.v:178254.3-178255.37" + attribute \src "libresoc.v:178256.3-178301.6" + wire width 2 $0\r0__data_o$next[1:0]$10690 + attribute \src "libresoc.v:178002.3-178003.37" wire width 2 $0\r0__data_o[1:0] - attribute \src "libresoc.v:178590.3-178622.6" - wire width 2 $0\reg$next[1:0]$10712 - attribute \src "libresoc.v:178252.3-178253.25" + attribute \src "libresoc.v:178338.3-178370.6" + wire width 2 $0\reg$next[1:0]$10706 + attribute \src "libresoc.v:178000.3-178001.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:178262.3-178307.6" - wire width 2 $0\src10__data_o$next[1:0]$10654 - attribute \src "libresoc.v:178260.3-178261.43" + attribute \src "libresoc.v:178010.3-178055.6" + wire width 2 $0\src10__data_o$next[1:0]$10648 + attribute \src "libresoc.v:178008.3-178009.43" wire width 2 $0\src10__data_o[1:0] - attribute \src "libresoc.v:178344.3-178389.6" - wire width 2 $0\src20__data_o$next[1:0]$10664 - attribute \src "libresoc.v:178258.3-178259.43" + attribute \src "libresoc.v:178092.3-178137.6" + wire width 2 $0\src20__data_o$next[1:0]$10658 + attribute \src "libresoc.v:178006.3-178007.43" wire width 2 $0\src20__data_o[1:0] - attribute \src "libresoc.v:178426.3-178471.6" - wire width 2 $0\src30__data_o$next[1:0]$10680 - attribute \src "libresoc.v:178256.3-178257.43" + attribute \src "libresoc.v:178174.3-178219.6" + wire width 2 $0\src30__data_o$next[1:0]$10674 + attribute \src "libresoc.v:178004.3-178005.43" wire width 2 $0\src30__data_o[1:0] - attribute \src "libresoc.v:178554.3-178589.6" - wire $0\wr_detect$10[0:0]$10705 - attribute \src "libresoc.v:178390.3-178425.6" - wire $0\wr_detect$4[0:0]$10673 - attribute \src "libresoc.v:178472.3-178507.6" - wire $0\wr_detect$7[0:0]$10689 - attribute \src "libresoc.v:178308.3-178343.6" + attribute \src "libresoc.v:178302.3-178337.6" + wire $0\wr_detect$10[0:0]$10699 + attribute \src "libresoc.v:178138.3-178173.6" + wire $0\wr_detect$4[0:0]$10667 + attribute \src "libresoc.v:178220.3-178255.6" + wire $0\wr_detect$7[0:0]$10683 + attribute \src "libresoc.v:178056.3-178091.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178508.3-178553.6" - wire width 2 $1\r0__data_o$next[1:0]$10697 - attribute \src "libresoc.v:178206.13-178206.30" + attribute \src "libresoc.v:178256.3-178301.6" + wire width 2 $1\r0__data_o$next[1:0]$10691 + attribute \src "libresoc.v:177954.13-177954.30" wire width 2 $1\r0__data_o[1:0] - attribute \src "libresoc.v:178590.3-178622.6" - wire width 2 $1\reg$next[1:0]$10713 - attribute \src "libresoc.v:178212.13-178212.25" + attribute \src "libresoc.v:178338.3-178370.6" + wire width 2 $1\reg$next[1:0]$10707 + attribute \src "libresoc.v:177960.13-177960.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:178262.3-178307.6" - wire width 2 $1\src10__data_o$next[1:0]$10655 - attribute \src "libresoc.v:178217.13-178217.33" + attribute \src "libresoc.v:178010.3-178055.6" + wire width 2 $1\src10__data_o$next[1:0]$10649 + attribute \src "libresoc.v:177965.13-177965.33" wire width 2 $1\src10__data_o[1:0] - attribute \src "libresoc.v:178344.3-178389.6" - wire width 2 $1\src20__data_o$next[1:0]$10665 - attribute \src "libresoc.v:178224.13-178224.33" + attribute \src "libresoc.v:178092.3-178137.6" + wire width 2 $1\src20__data_o$next[1:0]$10659 + attribute \src "libresoc.v:177972.13-177972.33" wire width 2 $1\src20__data_o[1:0] - attribute \src "libresoc.v:178426.3-178471.6" - wire width 2 $1\src30__data_o$next[1:0]$10681 - attribute \src "libresoc.v:178231.13-178231.33" + attribute \src "libresoc.v:178174.3-178219.6" + wire width 2 $1\src30__data_o$next[1:0]$10675 + attribute \src "libresoc.v:177979.13-177979.33" wire width 2 $1\src30__data_o[1:0] - attribute \src "libresoc.v:178554.3-178589.6" - wire $1\wr_detect$10[0:0]$10706 - attribute \src "libresoc.v:178390.3-178425.6" - wire $1\wr_detect$4[0:0]$10674 - attribute \src "libresoc.v:178472.3-178507.6" - wire $1\wr_detect$7[0:0]$10690 - attribute \src "libresoc.v:178308.3-178343.6" + attribute \src "libresoc.v:178302.3-178337.6" + wire $1\wr_detect$10[0:0]$10700 + attribute \src "libresoc.v:178138.3-178173.6" + wire $1\wr_detect$4[0:0]$10668 + attribute \src "libresoc.v:178220.3-178255.6" + wire $1\wr_detect$7[0:0]$10684 + attribute \src "libresoc.v:178056.3-178091.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178508.3-178553.6" - wire width 2 $2\r0__data_o$next[1:0]$10698 - attribute \src "libresoc.v:178590.3-178622.6" - wire width 2 $2\reg$next[1:0]$10714 - attribute \src "libresoc.v:178262.3-178307.6" - wire width 2 $2\src10__data_o$next[1:0]$10656 - attribute \src "libresoc.v:178344.3-178389.6" - wire width 2 $2\src20__data_o$next[1:0]$10666 - attribute \src "libresoc.v:178426.3-178471.6" - wire width 2 $2\src30__data_o$next[1:0]$10682 - attribute \src "libresoc.v:178554.3-178589.6" - wire $2\wr_detect$10[0:0]$10707 - attribute \src "libresoc.v:178390.3-178425.6" - wire $2\wr_detect$4[0:0]$10675 - attribute \src "libresoc.v:178472.3-178507.6" - wire $2\wr_detect$7[0:0]$10691 - attribute \src "libresoc.v:178308.3-178343.6" + attribute \src "libresoc.v:178256.3-178301.6" + wire width 2 $2\r0__data_o$next[1:0]$10692 + attribute \src "libresoc.v:178338.3-178370.6" + wire width 2 $2\reg$next[1:0]$10708 + attribute \src "libresoc.v:178010.3-178055.6" + wire width 2 $2\src10__data_o$next[1:0]$10650 + attribute \src "libresoc.v:178092.3-178137.6" + wire width 2 $2\src20__data_o$next[1:0]$10660 + attribute \src "libresoc.v:178174.3-178219.6" + wire width 2 $2\src30__data_o$next[1:0]$10676 + attribute \src "libresoc.v:178302.3-178337.6" + wire $2\wr_detect$10[0:0]$10701 + attribute \src "libresoc.v:178138.3-178173.6" + wire $2\wr_detect$4[0:0]$10669 + attribute \src "libresoc.v:178220.3-178255.6" + wire $2\wr_detect$7[0:0]$10685 + attribute \src "libresoc.v:178056.3-178091.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178508.3-178553.6" - wire width 2 $3\r0__data_o$next[1:0]$10699 - attribute \src "libresoc.v:178590.3-178622.6" - wire width 2 $3\reg$next[1:0]$10715 - attribute \src "libresoc.v:178262.3-178307.6" - wire width 2 $3\src10__data_o$next[1:0]$10657 - attribute \src "libresoc.v:178344.3-178389.6" - wire width 2 $3\src20__data_o$next[1:0]$10667 - attribute \src "libresoc.v:178426.3-178471.6" - wire width 2 $3\src30__data_o$next[1:0]$10683 - attribute \src "libresoc.v:178554.3-178589.6" - wire $3\wr_detect$10[0:0]$10708 - attribute \src "libresoc.v:178390.3-178425.6" - wire $3\wr_detect$4[0:0]$10676 - attribute \src "libresoc.v:178472.3-178507.6" - wire $3\wr_detect$7[0:0]$10692 - attribute \src "libresoc.v:178308.3-178343.6" + attribute \src "libresoc.v:178256.3-178301.6" + wire width 2 $3\r0__data_o$next[1:0]$10693 + attribute \src "libresoc.v:178338.3-178370.6" + wire width 2 $3\reg$next[1:0]$10709 + attribute \src "libresoc.v:178010.3-178055.6" + wire width 2 $3\src10__data_o$next[1:0]$10651 + attribute \src "libresoc.v:178092.3-178137.6" + wire width 2 $3\src20__data_o$next[1:0]$10661 + attribute \src "libresoc.v:178174.3-178219.6" + wire width 2 $3\src30__data_o$next[1:0]$10677 + attribute \src "libresoc.v:178302.3-178337.6" + wire $3\wr_detect$10[0:0]$10702 + attribute \src "libresoc.v:178138.3-178173.6" + wire $3\wr_detect$4[0:0]$10670 + attribute \src "libresoc.v:178220.3-178255.6" + wire $3\wr_detect$7[0:0]$10686 + attribute \src "libresoc.v:178056.3-178091.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178508.3-178553.6" - wire width 2 $4\r0__data_o$next[1:0]$10700 - attribute \src "libresoc.v:178590.3-178622.6" - wire width 2 $4\reg$next[1:0]$10716 - attribute \src "libresoc.v:178262.3-178307.6" - wire width 2 $4\src10__data_o$next[1:0]$10658 - attribute \src "libresoc.v:178344.3-178389.6" - wire width 2 $4\src20__data_o$next[1:0]$10668 - attribute \src "libresoc.v:178426.3-178471.6" - wire width 2 $4\src30__data_o$next[1:0]$10684 - attribute \src "libresoc.v:178554.3-178589.6" - wire $4\wr_detect$10[0:0]$10709 - attribute \src "libresoc.v:178390.3-178425.6" - wire $4\wr_detect$4[0:0]$10677 - attribute \src "libresoc.v:178472.3-178507.6" - wire $4\wr_detect$7[0:0]$10693 - attribute \src "libresoc.v:178308.3-178343.6" + attribute \src "libresoc.v:178256.3-178301.6" + wire width 2 $4\r0__data_o$next[1:0]$10694 + attribute \src "libresoc.v:178338.3-178370.6" + wire width 2 $4\reg$next[1:0]$10710 + attribute \src "libresoc.v:178010.3-178055.6" + wire width 2 $4\src10__data_o$next[1:0]$10652 + attribute \src "libresoc.v:178092.3-178137.6" + wire width 2 $4\src20__data_o$next[1:0]$10662 + attribute \src "libresoc.v:178174.3-178219.6" + wire width 2 $4\src30__data_o$next[1:0]$10678 + attribute \src "libresoc.v:178302.3-178337.6" + wire $4\wr_detect$10[0:0]$10703 + attribute \src "libresoc.v:178138.3-178173.6" + wire $4\wr_detect$4[0:0]$10671 + attribute \src "libresoc.v:178220.3-178255.6" + wire $4\wr_detect$7[0:0]$10687 + attribute \src "libresoc.v:178056.3-178091.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178508.3-178553.6" - wire width 2 $5\r0__data_o$next[1:0]$10701 - attribute \src "libresoc.v:178590.3-178622.6" - wire width 2 $5\reg$next[1:0]$10717 - attribute \src "libresoc.v:178262.3-178307.6" - wire width 2 $5\src10__data_o$next[1:0]$10659 - attribute \src "libresoc.v:178344.3-178389.6" - wire width 2 $5\src20__data_o$next[1:0]$10669 - attribute \src "libresoc.v:178426.3-178471.6" - wire width 2 $5\src30__data_o$next[1:0]$10685 - attribute \src "libresoc.v:178554.3-178589.6" - wire $5\wr_detect$10[0:0]$10710 - attribute \src "libresoc.v:178390.3-178425.6" - wire $5\wr_detect$4[0:0]$10678 - attribute \src "libresoc.v:178472.3-178507.6" - wire $5\wr_detect$7[0:0]$10694 - attribute \src "libresoc.v:178308.3-178343.6" + attribute \src "libresoc.v:178256.3-178301.6" + wire width 2 $5\r0__data_o$next[1:0]$10695 + attribute \src "libresoc.v:178338.3-178370.6" + wire width 2 $5\reg$next[1:0]$10711 + attribute \src "libresoc.v:178010.3-178055.6" + wire width 2 $5\src10__data_o$next[1:0]$10653 + attribute \src "libresoc.v:178092.3-178137.6" + wire width 2 $5\src20__data_o$next[1:0]$10663 + attribute \src "libresoc.v:178174.3-178219.6" + wire width 2 $5\src30__data_o$next[1:0]$10679 + attribute \src "libresoc.v:178302.3-178337.6" + wire $5\wr_detect$10[0:0]$10704 + attribute \src "libresoc.v:178138.3-178173.6" + wire $5\wr_detect$4[0:0]$10672 + attribute \src "libresoc.v:178220.3-178255.6" + wire $5\wr_detect$7[0:0]$10688 + attribute \src "libresoc.v:178056.3-178091.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:178508.3-178553.6" - wire width 2 $6\r0__data_o$next[1:0]$10702 - attribute \src "libresoc.v:178262.3-178307.6" - wire width 2 $6\src10__data_o$next[1:0]$10660 - attribute \src "libresoc.v:178344.3-178389.6" - wire width 2 $6\src20__data_o$next[1:0]$10670 - attribute \src "libresoc.v:178426.3-178471.6" - wire width 2 $6\src30__data_o$next[1:0]$10686 - attribute \src "libresoc.v:178508.3-178553.6" - wire width 2 $7\r0__data_o$next[1:0]$10703 - attribute \src "libresoc.v:178262.3-178307.6" - wire width 2 $7\src10__data_o$next[1:0]$10661 - attribute \src "libresoc.v:178344.3-178389.6" - wire width 2 $7\src20__data_o$next[1:0]$10671 - attribute \src "libresoc.v:178426.3-178471.6" - wire width 2 $7\src30__data_o$next[1:0]$10687 - attribute \src "libresoc.v:178248.17-178248.104" - wire $not$libresoc.v:178248$10644_Y - attribute \src "libresoc.v:178249.17-178249.100" - wire $not$libresoc.v:178249$10645_Y - attribute \src "libresoc.v:178250.17-178250.103" - wire $not$libresoc.v:178250$10646_Y - attribute \src "libresoc.v:178251.17-178251.103" - wire $not$libresoc.v:178251$10647_Y + attribute \src "libresoc.v:178256.3-178301.6" + wire width 2 $6\r0__data_o$next[1:0]$10696 + attribute \src "libresoc.v:178010.3-178055.6" + wire width 2 $6\src10__data_o$next[1:0]$10654 + attribute \src "libresoc.v:178092.3-178137.6" + wire width 2 $6\src20__data_o$next[1:0]$10664 + attribute \src "libresoc.v:178174.3-178219.6" + wire width 2 $6\src30__data_o$next[1:0]$10680 + attribute \src "libresoc.v:178256.3-178301.6" + wire width 2 $7\r0__data_o$next[1:0]$10697 + attribute \src "libresoc.v:178010.3-178055.6" + wire width 2 $7\src10__data_o$next[1:0]$10655 + attribute \src "libresoc.v:178092.3-178137.6" + wire width 2 $7\src20__data_o$next[1:0]$10665 + attribute \src "libresoc.v:178174.3-178219.6" + wire width 2 $7\src30__data_o$next[1:0]$10681 + attribute \src "libresoc.v:177996.17-177996.104" + wire $not$libresoc.v:177996$10638_Y + attribute \src "libresoc.v:177997.17-177997.100" + wire $not$libresoc.v:177997$10639_Y + attribute \src "libresoc.v:177998.17-177998.103" + wire $not$libresoc.v:177998$10640_Y + attribute \src "libresoc.v:177999.17-177999.103" + wire $not$libresoc.v:177999$10641_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -330778,9 +330484,9 @@ module \reg_0$132 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest10__data_i @@ -330794,7 +330500,7 @@ module \reg_0$132 wire width 2 input 13 \dest30__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest30__wen - attribute \src "libresoc.v:178179.7-178179.15" + attribute \src "libresoc.v:177927.7-177927.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r0__data_o @@ -330837,129 +330543,129 @@ module \reg_0$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178248$10644 + cell $not $not$libresoc.v:177996$10638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:178248$10644_Y + connect \Y $not$libresoc.v:177996$10638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178249$10645 + cell $not $not$libresoc.v:177997$10639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178249$10645_Y + connect \Y $not$libresoc.v:177997$10639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178250$10646 + cell $not $not$libresoc.v:177998$10640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178250$10646_Y + connect \Y $not$libresoc.v:177998$10640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178251$10647 + cell $not $not$libresoc.v:177999$10641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178251$10647_Y + connect \Y $not$libresoc.v:177999$10641_Y end - attribute \src "libresoc.v:178179.7-178179.20" - process $proc$libresoc.v:178179$10718 + attribute \src "libresoc.v:177927.7-177927.20" + process $proc$libresoc.v:177927$10712 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178206.13-178206.30" - process $proc$libresoc.v:178206$10719 + attribute \src "libresoc.v:177954.13-177954.30" + process $proc$libresoc.v:177954$10713 assign { } { } assign $1\r0__data_o[1:0] 2'00 sync always sync init update \r0__data_o $1\r0__data_o[1:0] end - attribute \src "libresoc.v:178212.13-178212.25" - process $proc$libresoc.v:178212$10720 + attribute \src "libresoc.v:177960.13-177960.25" + process $proc$libresoc.v:177960$10714 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:178217.13-178217.33" - process $proc$libresoc.v:178217$10721 + attribute \src "libresoc.v:177965.13-177965.33" + process $proc$libresoc.v:177965$10715 assign { } { } assign $1\src10__data_o[1:0] 2'00 sync always sync init update \src10__data_o $1\src10__data_o[1:0] end - attribute \src "libresoc.v:178224.13-178224.33" - process $proc$libresoc.v:178224$10722 + attribute \src "libresoc.v:177972.13-177972.33" + process $proc$libresoc.v:177972$10716 assign { } { } assign $1\src20__data_o[1:0] 2'00 sync always sync init update \src20__data_o $1\src20__data_o[1:0] end - attribute \src "libresoc.v:178231.13-178231.33" - process $proc$libresoc.v:178231$10723 + attribute \src "libresoc.v:177979.13-177979.33" + process $proc$libresoc.v:177979$10717 assign { } { } assign $1\src30__data_o[1:0] 2'00 sync always sync init update \src30__data_o $1\src30__data_o[1:0] end - attribute \src "libresoc.v:178252.3-178253.25" - process $proc$libresoc.v:178252$10648 + attribute \src "libresoc.v:178000.3-178001.25" + process $proc$libresoc.v:178000$10642 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:178254.3-178255.37" - process $proc$libresoc.v:178254$10649 + attribute \src "libresoc.v:178002.3-178003.37" + process $proc$libresoc.v:178002$10643 assign { } { } assign $0\r0__data_o[1:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[1:0] end - attribute \src "libresoc.v:178256.3-178257.43" - process $proc$libresoc.v:178256$10650 + attribute \src "libresoc.v:178004.3-178005.43" + process $proc$libresoc.v:178004$10644 assign { } { } assign $0\src30__data_o[1:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[1:0] end - attribute \src "libresoc.v:178258.3-178259.43" - process $proc$libresoc.v:178258$10651 + attribute \src "libresoc.v:178006.3-178007.43" + process $proc$libresoc.v:178006$10645 assign { } { } assign $0\src20__data_o[1:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[1:0] end - attribute \src "libresoc.v:178260.3-178261.43" - process $proc$libresoc.v:178260$10652 + attribute \src "libresoc.v:178008.3-178009.43" + process $proc$libresoc.v:178008$10646 assign { } { } assign $0\src10__data_o[1:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[1:0] end - attribute \src "libresoc.v:178262.3-178307.6" - process $proc$libresoc.v:178262$10653 + attribute \src "libresoc.v:178010.3-178055.6" + process $proc$libresoc.v:178010$10647 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[1:0]$10654 $7\src10__data_o$next[1:0]$10661 - attribute \src "libresoc.v:178263.5-178263.29" + assign $0\src10__data_o$next[1:0]$10648 $7\src10__data_o$next[1:0]$10655 + attribute \src "libresoc.v:178011.5-178011.29" switch \initial - attribute \src "libresoc.v:178263.9-178263.17" + attribute \src "libresoc.v:178011.9-178011.17" case 1'1 case end @@ -330972,75 +330678,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[1:0]$10655 $6\src10__data_o$next[1:0]$10660 + assign $1\src10__data_o$next[1:0]$10649 $6\src10__data_o$next[1:0]$10654 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[1:0]$10656 \dest10__data_i + assign $2\src10__data_o$next[1:0]$10650 \dest10__data_i case - assign $2\src10__data_o$next[1:0]$10656 2'00 + assign $2\src10__data_o$next[1:0]$10650 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[1:0]$10657 \dest20__data_i + assign $3\src10__data_o$next[1:0]$10651 \dest20__data_i case - assign $3\src10__data_o$next[1:0]$10657 $2\src10__data_o$next[1:0]$10656 + assign $3\src10__data_o$next[1:0]$10651 $2\src10__data_o$next[1:0]$10650 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[1:0]$10658 \dest30__data_i + assign $4\src10__data_o$next[1:0]$10652 \dest30__data_i case - assign $4\src10__data_o$next[1:0]$10658 $3\src10__data_o$next[1:0]$10657 + assign $4\src10__data_o$next[1:0]$10652 $3\src10__data_o$next[1:0]$10651 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[1:0]$10659 \w0__data_i + assign $5\src10__data_o$next[1:0]$10653 \w0__data_i case - assign $5\src10__data_o$next[1:0]$10659 $4\src10__data_o$next[1:0]$10658 + assign $5\src10__data_o$next[1:0]$10653 $4\src10__data_o$next[1:0]$10652 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[1:0]$10660 \reg + assign $6\src10__data_o$next[1:0]$10654 \reg case - assign $6\src10__data_o$next[1:0]$10660 $5\src10__data_o$next[1:0]$10659 + assign $6\src10__data_o$next[1:0]$10654 $5\src10__data_o$next[1:0]$10653 end case - assign $1\src10__data_o$next[1:0]$10655 2'00 + assign $1\src10__data_o$next[1:0]$10649 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src10__data_o$next[1:0]$10661 2'00 + assign $7\src10__data_o$next[1:0]$10655 2'00 case - assign $7\src10__data_o$next[1:0]$10661 $1\src10__data_o$next[1:0]$10655 + assign $7\src10__data_o$next[1:0]$10655 $1\src10__data_o$next[1:0]$10649 end sync always - update \src10__data_o$next $0\src10__data_o$next[1:0]$10654 + update \src10__data_o$next $0\src10__data_o$next[1:0]$10648 end - attribute \src "libresoc.v:178308.3-178343.6" - process $proc$libresoc.v:178308$10662 + attribute \src "libresoc.v:178056.3-178091.6" + process $proc$libresoc.v:178056$10656 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178309.5-178309.29" + attribute \src "libresoc.v:178057.5-178057.29" switch \initial - attribute \src "libresoc.v:178309.9-178309.17" + attribute \src "libresoc.v:178057.9-178057.17" case 1'1 case end @@ -331096,15 +330802,15 @@ module \reg_0$132 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178344.3-178389.6" - process $proc$libresoc.v:178344$10663 + attribute \src "libresoc.v:178092.3-178137.6" + process $proc$libresoc.v:178092$10657 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[1:0]$10664 $7\src20__data_o$next[1:0]$10671 - attribute \src "libresoc.v:178345.5-178345.29" + assign $0\src20__data_o$next[1:0]$10658 $7\src20__data_o$next[1:0]$10665 + attribute \src "libresoc.v:178093.5-178093.29" switch \initial - attribute \src "libresoc.v:178345.9-178345.17" + attribute \src "libresoc.v:178093.9-178093.17" case 1'1 case end @@ -331117,75 +330823,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[1:0]$10665 $6\src20__data_o$next[1:0]$10670 + assign $1\src20__data_o$next[1:0]$10659 $6\src20__data_o$next[1:0]$10664 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[1:0]$10666 \dest10__data_i + assign $2\src20__data_o$next[1:0]$10660 \dest10__data_i case - assign $2\src20__data_o$next[1:0]$10666 2'00 + assign $2\src20__data_o$next[1:0]$10660 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[1:0]$10667 \dest20__data_i + assign $3\src20__data_o$next[1:0]$10661 \dest20__data_i case - assign $3\src20__data_o$next[1:0]$10667 $2\src20__data_o$next[1:0]$10666 + assign $3\src20__data_o$next[1:0]$10661 $2\src20__data_o$next[1:0]$10660 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[1:0]$10668 \dest30__data_i + assign $4\src20__data_o$next[1:0]$10662 \dest30__data_i case - assign $4\src20__data_o$next[1:0]$10668 $3\src20__data_o$next[1:0]$10667 + assign $4\src20__data_o$next[1:0]$10662 $3\src20__data_o$next[1:0]$10661 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[1:0]$10669 \w0__data_i + assign $5\src20__data_o$next[1:0]$10663 \w0__data_i case - assign $5\src20__data_o$next[1:0]$10669 $4\src20__data_o$next[1:0]$10668 + assign $5\src20__data_o$next[1:0]$10663 $4\src20__data_o$next[1:0]$10662 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[1:0]$10670 \reg + assign $6\src20__data_o$next[1:0]$10664 \reg case - assign $6\src20__data_o$next[1:0]$10670 $5\src20__data_o$next[1:0]$10669 + assign $6\src20__data_o$next[1:0]$10664 $5\src20__data_o$next[1:0]$10663 end case - assign $1\src20__data_o$next[1:0]$10665 2'00 + assign $1\src20__data_o$next[1:0]$10659 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src20__data_o$next[1:0]$10671 2'00 + assign $7\src20__data_o$next[1:0]$10665 2'00 case - assign $7\src20__data_o$next[1:0]$10671 $1\src20__data_o$next[1:0]$10665 + assign $7\src20__data_o$next[1:0]$10665 $1\src20__data_o$next[1:0]$10659 end sync always - update \src20__data_o$next $0\src20__data_o$next[1:0]$10664 + update \src20__data_o$next $0\src20__data_o$next[1:0]$10658 end - attribute \src "libresoc.v:178390.3-178425.6" - process $proc$libresoc.v:178390$10672 + attribute \src "libresoc.v:178138.3-178173.6" + process $proc$libresoc.v:178138$10666 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10673 $1\wr_detect$4[0:0]$10674 - attribute \src "libresoc.v:178391.5-178391.29" + assign $0\wr_detect$4[0:0]$10667 $1\wr_detect$4[0:0]$10668 + attribute \src "libresoc.v:178139.5-178139.29" switch \initial - attribute \src "libresoc.v:178391.9-178391.17" + attribute \src "libresoc.v:178139.9-178139.17" case 1'1 case end @@ -331198,58 +330904,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10674 $5\wr_detect$4[0:0]$10678 + assign $1\wr_detect$4[0:0]$10668 $5\wr_detect$4[0:0]$10672 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10675 1'1 + assign $2\wr_detect$4[0:0]$10669 1'1 case - assign $2\wr_detect$4[0:0]$10675 1'0 + assign $2\wr_detect$4[0:0]$10669 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10676 1'1 + assign $3\wr_detect$4[0:0]$10670 1'1 case - assign $3\wr_detect$4[0:0]$10676 $2\wr_detect$4[0:0]$10675 + assign $3\wr_detect$4[0:0]$10670 $2\wr_detect$4[0:0]$10669 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10677 1'1 + assign $4\wr_detect$4[0:0]$10671 1'1 case - assign $4\wr_detect$4[0:0]$10677 $3\wr_detect$4[0:0]$10676 + assign $4\wr_detect$4[0:0]$10671 $3\wr_detect$4[0:0]$10670 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10678 1'1 + assign $5\wr_detect$4[0:0]$10672 1'1 case - assign $5\wr_detect$4[0:0]$10678 $4\wr_detect$4[0:0]$10677 + assign $5\wr_detect$4[0:0]$10672 $4\wr_detect$4[0:0]$10671 end case - assign $1\wr_detect$4[0:0]$10674 1'0 + assign $1\wr_detect$4[0:0]$10668 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10673 + update \wr_detect$4 $0\wr_detect$4[0:0]$10667 end - attribute \src "libresoc.v:178426.3-178471.6" - process $proc$libresoc.v:178426$10679 + attribute \src "libresoc.v:178174.3-178219.6" + process $proc$libresoc.v:178174$10673 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[1:0]$10680 $7\src30__data_o$next[1:0]$10687 - attribute \src "libresoc.v:178427.5-178427.29" + assign $0\src30__data_o$next[1:0]$10674 $7\src30__data_o$next[1:0]$10681 + attribute \src "libresoc.v:178175.5-178175.29" switch \initial - attribute \src "libresoc.v:178427.9-178427.17" + attribute \src "libresoc.v:178175.9-178175.17" case 1'1 case end @@ -331262,75 +330968,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[1:0]$10681 $6\src30__data_o$next[1:0]$10686 + assign $1\src30__data_o$next[1:0]$10675 $6\src30__data_o$next[1:0]$10680 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[1:0]$10682 \dest10__data_i + assign $2\src30__data_o$next[1:0]$10676 \dest10__data_i case - assign $2\src30__data_o$next[1:0]$10682 2'00 + assign $2\src30__data_o$next[1:0]$10676 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[1:0]$10683 \dest20__data_i + assign $3\src30__data_o$next[1:0]$10677 \dest20__data_i case - assign $3\src30__data_o$next[1:0]$10683 $2\src30__data_o$next[1:0]$10682 + assign $3\src30__data_o$next[1:0]$10677 $2\src30__data_o$next[1:0]$10676 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[1:0]$10684 \dest30__data_i + assign $4\src30__data_o$next[1:0]$10678 \dest30__data_i case - assign $4\src30__data_o$next[1:0]$10684 $3\src30__data_o$next[1:0]$10683 + assign $4\src30__data_o$next[1:0]$10678 $3\src30__data_o$next[1:0]$10677 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[1:0]$10685 \w0__data_i + assign $5\src30__data_o$next[1:0]$10679 \w0__data_i case - assign $5\src30__data_o$next[1:0]$10685 $4\src30__data_o$next[1:0]$10684 + assign $5\src30__data_o$next[1:0]$10679 $4\src30__data_o$next[1:0]$10678 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[1:0]$10686 \reg + assign $6\src30__data_o$next[1:0]$10680 \reg case - assign $6\src30__data_o$next[1:0]$10686 $5\src30__data_o$next[1:0]$10685 + assign $6\src30__data_o$next[1:0]$10680 $5\src30__data_o$next[1:0]$10679 end case - assign $1\src30__data_o$next[1:0]$10681 2'00 + assign $1\src30__data_o$next[1:0]$10675 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src30__data_o$next[1:0]$10687 2'00 + assign $7\src30__data_o$next[1:0]$10681 2'00 case - assign $7\src30__data_o$next[1:0]$10687 $1\src30__data_o$next[1:0]$10681 + assign $7\src30__data_o$next[1:0]$10681 $1\src30__data_o$next[1:0]$10675 end sync always - update \src30__data_o$next $0\src30__data_o$next[1:0]$10680 + update \src30__data_o$next $0\src30__data_o$next[1:0]$10674 end - attribute \src "libresoc.v:178472.3-178507.6" - process $proc$libresoc.v:178472$10688 + attribute \src "libresoc.v:178220.3-178255.6" + process $proc$libresoc.v:178220$10682 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10689 $1\wr_detect$7[0:0]$10690 - attribute \src "libresoc.v:178473.5-178473.29" + assign $0\wr_detect$7[0:0]$10683 $1\wr_detect$7[0:0]$10684 + attribute \src "libresoc.v:178221.5-178221.29" switch \initial - attribute \src "libresoc.v:178473.9-178473.17" + attribute \src "libresoc.v:178221.9-178221.17" case 1'1 case end @@ -331343,58 +331049,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10690 $5\wr_detect$7[0:0]$10694 + assign $1\wr_detect$7[0:0]$10684 $5\wr_detect$7[0:0]$10688 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10691 1'1 + assign $2\wr_detect$7[0:0]$10685 1'1 case - assign $2\wr_detect$7[0:0]$10691 1'0 + assign $2\wr_detect$7[0:0]$10685 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10692 1'1 + assign $3\wr_detect$7[0:0]$10686 1'1 case - assign $3\wr_detect$7[0:0]$10692 $2\wr_detect$7[0:0]$10691 + assign $3\wr_detect$7[0:0]$10686 $2\wr_detect$7[0:0]$10685 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10693 1'1 + assign $4\wr_detect$7[0:0]$10687 1'1 case - assign $4\wr_detect$7[0:0]$10693 $3\wr_detect$7[0:0]$10692 + assign $4\wr_detect$7[0:0]$10687 $3\wr_detect$7[0:0]$10686 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10694 1'1 + assign $5\wr_detect$7[0:0]$10688 1'1 case - assign $5\wr_detect$7[0:0]$10694 $4\wr_detect$7[0:0]$10693 + assign $5\wr_detect$7[0:0]$10688 $4\wr_detect$7[0:0]$10687 end case - assign $1\wr_detect$7[0:0]$10690 1'0 + assign $1\wr_detect$7[0:0]$10684 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10689 + update \wr_detect$7 $0\wr_detect$7[0:0]$10683 end - attribute \src "libresoc.v:178508.3-178553.6" - process $proc$libresoc.v:178508$10695 + attribute \src "libresoc.v:178256.3-178301.6" + process $proc$libresoc.v:178256$10689 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[1:0]$10696 $7\r0__data_o$next[1:0]$10703 - attribute \src "libresoc.v:178509.5-178509.29" + assign $0\r0__data_o$next[1:0]$10690 $7\r0__data_o$next[1:0]$10697 + attribute \src "libresoc.v:178257.5-178257.29" switch \initial - attribute \src "libresoc.v:178509.9-178509.17" + attribute \src "libresoc.v:178257.9-178257.17" case 1'1 case end @@ -331407,75 +331113,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[1:0]$10697 $6\r0__data_o$next[1:0]$10702 + assign $1\r0__data_o$next[1:0]$10691 $6\r0__data_o$next[1:0]$10696 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[1:0]$10698 \dest10__data_i + assign $2\r0__data_o$next[1:0]$10692 \dest10__data_i case - assign $2\r0__data_o$next[1:0]$10698 2'00 + assign $2\r0__data_o$next[1:0]$10692 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[1:0]$10699 \dest20__data_i + assign $3\r0__data_o$next[1:0]$10693 \dest20__data_i case - assign $3\r0__data_o$next[1:0]$10699 $2\r0__data_o$next[1:0]$10698 + assign $3\r0__data_o$next[1:0]$10693 $2\r0__data_o$next[1:0]$10692 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[1:0]$10700 \dest30__data_i + assign $4\r0__data_o$next[1:0]$10694 \dest30__data_i case - assign $4\r0__data_o$next[1:0]$10700 $3\r0__data_o$next[1:0]$10699 + assign $4\r0__data_o$next[1:0]$10694 $3\r0__data_o$next[1:0]$10693 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[1:0]$10701 \w0__data_i + assign $5\r0__data_o$next[1:0]$10695 \w0__data_i case - assign $5\r0__data_o$next[1:0]$10701 $4\r0__data_o$next[1:0]$10700 + assign $5\r0__data_o$next[1:0]$10695 $4\r0__data_o$next[1:0]$10694 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[1:0]$10702 \reg + assign $6\r0__data_o$next[1:0]$10696 \reg case - assign $6\r0__data_o$next[1:0]$10702 $5\r0__data_o$next[1:0]$10701 + assign $6\r0__data_o$next[1:0]$10696 $5\r0__data_o$next[1:0]$10695 end case - assign $1\r0__data_o$next[1:0]$10697 2'00 + assign $1\r0__data_o$next[1:0]$10691 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r0__data_o$next[1:0]$10703 2'00 + assign $7\r0__data_o$next[1:0]$10697 2'00 case - assign $7\r0__data_o$next[1:0]$10703 $1\r0__data_o$next[1:0]$10697 + assign $7\r0__data_o$next[1:0]$10697 $1\r0__data_o$next[1:0]$10691 end sync always - update \r0__data_o$next $0\r0__data_o$next[1:0]$10696 + update \r0__data_o$next $0\r0__data_o$next[1:0]$10690 end - attribute \src "libresoc.v:178554.3-178589.6" - process $proc$libresoc.v:178554$10704 + attribute \src "libresoc.v:178302.3-178337.6" + process $proc$libresoc.v:178302$10698 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10705 $1\wr_detect$10[0:0]$10706 - attribute \src "libresoc.v:178555.5-178555.29" + assign $0\wr_detect$10[0:0]$10699 $1\wr_detect$10[0:0]$10700 + attribute \src "libresoc.v:178303.5-178303.29" switch \initial - attribute \src "libresoc.v:178555.9-178555.17" + attribute \src "libresoc.v:178303.9-178303.17" case 1'1 case end @@ -331488,61 +331194,61 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10706 $5\wr_detect$10[0:0]$10710 + assign $1\wr_detect$10[0:0]$10700 $5\wr_detect$10[0:0]$10704 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10707 1'1 + assign $2\wr_detect$10[0:0]$10701 1'1 case - assign $2\wr_detect$10[0:0]$10707 1'0 + assign $2\wr_detect$10[0:0]$10701 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10708 1'1 + assign $3\wr_detect$10[0:0]$10702 1'1 case - assign $3\wr_detect$10[0:0]$10708 $2\wr_detect$10[0:0]$10707 + assign $3\wr_detect$10[0:0]$10702 $2\wr_detect$10[0:0]$10701 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10709 1'1 + assign $4\wr_detect$10[0:0]$10703 1'1 case - assign $4\wr_detect$10[0:0]$10709 $3\wr_detect$10[0:0]$10708 + assign $4\wr_detect$10[0:0]$10703 $3\wr_detect$10[0:0]$10702 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10710 1'1 + assign $5\wr_detect$10[0:0]$10704 1'1 case - assign $5\wr_detect$10[0:0]$10710 $4\wr_detect$10[0:0]$10709 + assign $5\wr_detect$10[0:0]$10704 $4\wr_detect$10[0:0]$10703 end case - assign $1\wr_detect$10[0:0]$10706 1'0 + assign $1\wr_detect$10[0:0]$10700 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10705 + update \wr_detect$10 $0\wr_detect$10[0:0]$10699 end - attribute \src "libresoc.v:178590.3-178622.6" - process $proc$libresoc.v:178590$10711 + attribute \src "libresoc.v:178338.3-178370.6" + process $proc$libresoc.v:178338$10705 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10712 $5\reg$next[1:0]$10717 - attribute \src "libresoc.v:178591.5-178591.29" + assign $0\reg$next[1:0]$10706 $5\reg$next[1:0]$10711 + attribute \src "libresoc.v:178339.5-178339.29" switch \initial - attribute \src "libresoc.v:178591.9-178591.17" + attribute \src "libresoc.v:178339.9-178339.17" case 1'1 case end @@ -331551,179 +331257,179 @@ module \reg_0$132 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10713 \dest10__data_i + assign $1\reg$next[1:0]$10707 \dest10__data_i case - assign $1\reg$next[1:0]$10713 \reg + assign $1\reg$next[1:0]$10707 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10714 \dest20__data_i + assign $2\reg$next[1:0]$10708 \dest20__data_i case - assign $2\reg$next[1:0]$10714 $1\reg$next[1:0]$10713 + assign $2\reg$next[1:0]$10708 $1\reg$next[1:0]$10707 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10715 \dest30__data_i + assign $3\reg$next[1:0]$10709 \dest30__data_i case - assign $3\reg$next[1:0]$10715 $2\reg$next[1:0]$10714 + assign $3\reg$next[1:0]$10709 $2\reg$next[1:0]$10708 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10716 \w0__data_i + assign $4\reg$next[1:0]$10710 \w0__data_i case - assign $4\reg$next[1:0]$10716 $3\reg$next[1:0]$10715 + assign $4\reg$next[1:0]$10710 $3\reg$next[1:0]$10709 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10717 2'00 + assign $5\reg$next[1:0]$10711 2'00 case - assign $5\reg$next[1:0]$10717 $4\reg$next[1:0]$10716 + assign $5\reg$next[1:0]$10711 $4\reg$next[1:0]$10710 end sync always - update \reg$next $0\reg$next[1:0]$10712 + update \reg$next $0\reg$next[1:0]$10706 end - connect \$9 $not$libresoc.v:178248$10644_Y - connect \$1 $not$libresoc.v:178249$10645_Y - connect \$3 $not$libresoc.v:178250$10646_Y - connect \$6 $not$libresoc.v:178251$10647_Y + connect \$9 $not$libresoc.v:177996$10638_Y + connect \$1 $not$libresoc.v:177997$10639_Y + connect \$3 $not$libresoc.v:177998$10640_Y + connect \$6 $not$libresoc.v:177999$10641_Y end -attribute \src "libresoc.v:178627.1-178976.10" +attribute \src "libresoc.v:178375.1-178724.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" attribute \generator "nMigen" module \reg_0$135 - attribute \src "libresoc.v:178697.3-178742.6" - wire width 64 $0\cia0__data_o$next[63:0]$10732 - attribute \src "libresoc.v:178695.3-178696.41" + attribute \src "libresoc.v:178445.3-178490.6" + wire width 64 $0\cia0__data_o$next[63:0]$10726 + attribute \src "libresoc.v:178443.3-178444.41" wire width 64 $0\cia0__data_o[63:0] - attribute \src "libresoc.v:178628.7-178628.20" + attribute \src "libresoc.v:178376.7-178376.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178779.3-178824.6" - wire width 64 $0\msr0__data_o$next[63:0]$10742 - attribute \src "libresoc.v:178693.3-178694.41" + attribute \src "libresoc.v:178527.3-178572.6" + wire width 64 $0\msr0__data_o$next[63:0]$10736 + attribute \src "libresoc.v:178441.3-178442.41" wire width 64 $0\msr0__data_o[63:0] - attribute \src "libresoc.v:178943.3-178975.6" - wire width 64 $0\reg$next[63:0]$10774 - attribute \src "libresoc.v:178689.3-178690.25" + attribute \src "libresoc.v:178691.3-178723.6" + wire width 64 $0\reg$next[63:0]$10768 + attribute \src "libresoc.v:178437.3-178438.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:178861.3-178906.6" - wire width 64 $0\sv0__data_o$next[63:0]$10758 - attribute \src "libresoc.v:178691.3-178692.39" + attribute \src "libresoc.v:178609.3-178654.6" + wire width 64 $0\sv0__data_o$next[63:0]$10752 + attribute \src "libresoc.v:178439.3-178440.39" wire width 64 $0\sv0__data_o[63:0] - attribute \src "libresoc.v:178825.3-178860.6" - wire $0\wr_detect$4[0:0]$10751 - attribute \src "libresoc.v:178907.3-178942.6" - wire $0\wr_detect$7[0:0]$10767 - attribute \src "libresoc.v:178743.3-178778.6" + attribute \src "libresoc.v:178573.3-178608.6" + wire $0\wr_detect$4[0:0]$10745 + attribute \src "libresoc.v:178655.3-178690.6" + wire $0\wr_detect$7[0:0]$10761 + attribute \src "libresoc.v:178491.3-178526.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178697.3-178742.6" - wire width 64 $1\cia0__data_o$next[63:0]$10733 - attribute \src "libresoc.v:178637.14-178637.49" + attribute \src "libresoc.v:178445.3-178490.6" + wire width 64 $1\cia0__data_o$next[63:0]$10727 + attribute \src "libresoc.v:178385.14-178385.49" wire width 64 $1\cia0__data_o[63:0] - attribute \src "libresoc.v:178779.3-178824.6" - wire width 64 $1\msr0__data_o$next[63:0]$10743 - attribute \src "libresoc.v:178654.14-178654.49" + attribute \src "libresoc.v:178527.3-178572.6" + wire width 64 $1\msr0__data_o$next[63:0]$10737 + attribute \src "libresoc.v:178402.14-178402.49" wire width 64 $1\msr0__data_o[63:0] - attribute \src "libresoc.v:178943.3-178975.6" - wire width 64 $1\reg$next[63:0]$10775 - attribute \src "libresoc.v:178666.14-178666.42" + attribute \src "libresoc.v:178691.3-178723.6" + wire width 64 $1\reg$next[63:0]$10769 + attribute \src "libresoc.v:178414.14-178414.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:178861.3-178906.6" - wire width 64 $1\sv0__data_o$next[63:0]$10759 - attribute \src "libresoc.v:178673.14-178673.48" + attribute \src "libresoc.v:178609.3-178654.6" + wire width 64 $1\sv0__data_o$next[63:0]$10753 + attribute \src "libresoc.v:178421.14-178421.48" wire width 64 $1\sv0__data_o[63:0] - attribute \src "libresoc.v:178825.3-178860.6" - wire $1\wr_detect$4[0:0]$10752 - attribute \src "libresoc.v:178907.3-178942.6" - wire $1\wr_detect$7[0:0]$10768 - attribute \src "libresoc.v:178743.3-178778.6" + attribute \src "libresoc.v:178573.3-178608.6" + wire $1\wr_detect$4[0:0]$10746 + attribute \src "libresoc.v:178655.3-178690.6" + wire $1\wr_detect$7[0:0]$10762 + attribute \src "libresoc.v:178491.3-178526.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178697.3-178742.6" - wire width 64 $2\cia0__data_o$next[63:0]$10734 - attribute \src "libresoc.v:178779.3-178824.6" - wire width 64 $2\msr0__data_o$next[63:0]$10744 - attribute \src "libresoc.v:178943.3-178975.6" - wire width 64 $2\reg$next[63:0]$10776 - attribute \src "libresoc.v:178861.3-178906.6" - wire width 64 $2\sv0__data_o$next[63:0]$10760 - attribute \src "libresoc.v:178825.3-178860.6" - wire $2\wr_detect$4[0:0]$10753 - attribute \src "libresoc.v:178907.3-178942.6" - wire $2\wr_detect$7[0:0]$10769 - attribute \src "libresoc.v:178743.3-178778.6" + attribute \src "libresoc.v:178445.3-178490.6" + wire width 64 $2\cia0__data_o$next[63:0]$10728 + attribute \src "libresoc.v:178527.3-178572.6" + wire width 64 $2\msr0__data_o$next[63:0]$10738 + attribute \src "libresoc.v:178691.3-178723.6" + wire width 64 $2\reg$next[63:0]$10770 + attribute \src "libresoc.v:178609.3-178654.6" + wire width 64 $2\sv0__data_o$next[63:0]$10754 + attribute \src "libresoc.v:178573.3-178608.6" + wire $2\wr_detect$4[0:0]$10747 + attribute \src "libresoc.v:178655.3-178690.6" + wire $2\wr_detect$7[0:0]$10763 + attribute \src "libresoc.v:178491.3-178526.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178697.3-178742.6" - wire width 64 $3\cia0__data_o$next[63:0]$10735 - attribute \src "libresoc.v:178779.3-178824.6" - wire width 64 $3\msr0__data_o$next[63:0]$10745 - attribute \src "libresoc.v:178943.3-178975.6" - wire width 64 $3\reg$next[63:0]$10777 - attribute \src "libresoc.v:178861.3-178906.6" - wire width 64 $3\sv0__data_o$next[63:0]$10761 - attribute \src "libresoc.v:178825.3-178860.6" - wire $3\wr_detect$4[0:0]$10754 - attribute \src "libresoc.v:178907.3-178942.6" - wire $3\wr_detect$7[0:0]$10770 - attribute \src "libresoc.v:178743.3-178778.6" + attribute \src "libresoc.v:178445.3-178490.6" + wire width 64 $3\cia0__data_o$next[63:0]$10729 + attribute \src "libresoc.v:178527.3-178572.6" + wire width 64 $3\msr0__data_o$next[63:0]$10739 + attribute \src "libresoc.v:178691.3-178723.6" + wire width 64 $3\reg$next[63:0]$10771 + attribute \src "libresoc.v:178609.3-178654.6" + wire width 64 $3\sv0__data_o$next[63:0]$10755 + attribute \src "libresoc.v:178573.3-178608.6" + wire $3\wr_detect$4[0:0]$10748 + attribute \src "libresoc.v:178655.3-178690.6" + wire $3\wr_detect$7[0:0]$10764 + attribute \src "libresoc.v:178491.3-178526.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178697.3-178742.6" - wire width 64 $4\cia0__data_o$next[63:0]$10736 - attribute \src "libresoc.v:178779.3-178824.6" - wire width 64 $4\msr0__data_o$next[63:0]$10746 - attribute \src "libresoc.v:178943.3-178975.6" - wire width 64 $4\reg$next[63:0]$10778 - attribute \src "libresoc.v:178861.3-178906.6" - wire width 64 $4\sv0__data_o$next[63:0]$10762 - attribute \src "libresoc.v:178825.3-178860.6" - wire $4\wr_detect$4[0:0]$10755 - attribute \src "libresoc.v:178907.3-178942.6" - wire $4\wr_detect$7[0:0]$10771 - attribute \src "libresoc.v:178743.3-178778.6" + attribute \src "libresoc.v:178445.3-178490.6" + wire width 64 $4\cia0__data_o$next[63:0]$10730 + attribute \src "libresoc.v:178527.3-178572.6" + wire width 64 $4\msr0__data_o$next[63:0]$10740 + attribute \src "libresoc.v:178691.3-178723.6" + wire width 64 $4\reg$next[63:0]$10772 + attribute \src "libresoc.v:178609.3-178654.6" + wire width 64 $4\sv0__data_o$next[63:0]$10756 + attribute \src "libresoc.v:178573.3-178608.6" + wire $4\wr_detect$4[0:0]$10749 + attribute \src "libresoc.v:178655.3-178690.6" + wire $4\wr_detect$7[0:0]$10765 + attribute \src "libresoc.v:178491.3-178526.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178697.3-178742.6" - wire width 64 $5\cia0__data_o$next[63:0]$10737 - attribute \src "libresoc.v:178779.3-178824.6" - wire width 64 $5\msr0__data_o$next[63:0]$10747 - attribute \src "libresoc.v:178943.3-178975.6" - wire width 64 $5\reg$next[63:0]$10779 - attribute \src "libresoc.v:178861.3-178906.6" - wire width 64 $5\sv0__data_o$next[63:0]$10763 - attribute \src "libresoc.v:178825.3-178860.6" - wire $5\wr_detect$4[0:0]$10756 - attribute \src "libresoc.v:178907.3-178942.6" - wire $5\wr_detect$7[0:0]$10772 - attribute \src "libresoc.v:178743.3-178778.6" + attribute \src "libresoc.v:178445.3-178490.6" + wire width 64 $5\cia0__data_o$next[63:0]$10731 + attribute \src "libresoc.v:178527.3-178572.6" + wire width 64 $5\msr0__data_o$next[63:0]$10741 + attribute \src "libresoc.v:178691.3-178723.6" + wire width 64 $5\reg$next[63:0]$10773 + attribute \src "libresoc.v:178609.3-178654.6" + wire width 64 $5\sv0__data_o$next[63:0]$10757 + attribute \src "libresoc.v:178573.3-178608.6" + wire $5\wr_detect$4[0:0]$10750 + attribute \src "libresoc.v:178655.3-178690.6" + wire $5\wr_detect$7[0:0]$10766 + attribute \src "libresoc.v:178491.3-178526.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:178697.3-178742.6" - wire width 64 $6\cia0__data_o$next[63:0]$10738 - attribute \src "libresoc.v:178779.3-178824.6" - wire width 64 $6\msr0__data_o$next[63:0]$10748 - attribute \src "libresoc.v:178861.3-178906.6" - wire width 64 $6\sv0__data_o$next[63:0]$10764 - attribute \src "libresoc.v:178697.3-178742.6" - wire width 64 $7\cia0__data_o$next[63:0]$10739 - attribute \src "libresoc.v:178779.3-178824.6" - wire width 64 $7\msr0__data_o$next[63:0]$10749 - attribute \src "libresoc.v:178861.3-178906.6" - wire width 64 $7\sv0__data_o$next[63:0]$10765 - attribute \src "libresoc.v:178686.17-178686.100" - wire $not$libresoc.v:178686$10724_Y - attribute \src "libresoc.v:178687.17-178687.103" - wire $not$libresoc.v:178687$10725_Y - attribute \src "libresoc.v:178688.17-178688.103" - wire $not$libresoc.v:178688$10726_Y + attribute \src "libresoc.v:178445.3-178490.6" + wire width 64 $6\cia0__data_o$next[63:0]$10732 + attribute \src "libresoc.v:178527.3-178572.6" + wire width 64 $6\msr0__data_o$next[63:0]$10742 + attribute \src "libresoc.v:178609.3-178654.6" + wire width 64 $6\sv0__data_o$next[63:0]$10758 + attribute \src "libresoc.v:178445.3-178490.6" + wire width 64 $7\cia0__data_o$next[63:0]$10733 + attribute \src "libresoc.v:178527.3-178572.6" + wire width 64 $7\msr0__data_o$next[63:0]$10743 + attribute \src "libresoc.v:178609.3-178654.6" + wire width 64 $7\sv0__data_o$next[63:0]$10759 + attribute \src "libresoc.v:178434.17-178434.100" + wire $not$libresoc.v:178434$10718_Y + attribute \src "libresoc.v:178435.17-178435.103" + wire $not$libresoc.v:178435$10719_Y + attribute \src "libresoc.v:178436.17-178436.103" + wire $not$libresoc.v:178436$10720_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -331736,15 +331442,15 @@ module \reg_0$135 wire width 64 \cia0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr10__wen - attribute \src "libresoc.v:178628.7-178628.15" + attribute \src "libresoc.v:178376.7-178376.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr0__data_i @@ -331781,106 +331487,106 @@ module \reg_0$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178686$10724 + cell $not $not$libresoc.v:178434$10718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178686$10724_Y + connect \Y $not$libresoc.v:178434$10718_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178687$10725 + cell $not $not$libresoc.v:178435$10719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178687$10725_Y + connect \Y $not$libresoc.v:178435$10719_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178688$10726 + cell $not $not$libresoc.v:178436$10720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178688$10726_Y + connect \Y $not$libresoc.v:178436$10720_Y end - attribute \src "libresoc.v:178628.7-178628.20" - process $proc$libresoc.v:178628$10780 + attribute \src "libresoc.v:178376.7-178376.20" + process $proc$libresoc.v:178376$10774 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178637.14-178637.49" - process $proc$libresoc.v:178637$10781 + attribute \src "libresoc.v:178385.14-178385.49" + process $proc$libresoc.v:178385$10775 assign { } { } assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia0__data_o $1\cia0__data_o[63:0] end - attribute \src "libresoc.v:178654.14-178654.49" - process $proc$libresoc.v:178654$10782 + attribute \src "libresoc.v:178402.14-178402.49" + process $proc$libresoc.v:178402$10776 assign { } { } assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr0__data_o $1\msr0__data_o[63:0] end - attribute \src "libresoc.v:178666.14-178666.42" - process $proc$libresoc.v:178666$10783 + attribute \src "libresoc.v:178414.14-178414.42" + process $proc$libresoc.v:178414$10777 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:178673.14-178673.48" - process $proc$libresoc.v:178673$10784 + attribute \src "libresoc.v:178421.14-178421.48" + process $proc$libresoc.v:178421$10778 assign { } { } assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv0__data_o $1\sv0__data_o[63:0] end - attribute \src "libresoc.v:178689.3-178690.25" - process $proc$libresoc.v:178689$10727 + attribute \src "libresoc.v:178437.3-178438.25" + process $proc$libresoc.v:178437$10721 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:178691.3-178692.39" - process $proc$libresoc.v:178691$10728 + attribute \src "libresoc.v:178439.3-178440.39" + process $proc$libresoc.v:178439$10722 assign { } { } assign $0\sv0__data_o[63:0] \sv0__data_o$next sync posedge \coresync_clk update \sv0__data_o $0\sv0__data_o[63:0] end - attribute \src "libresoc.v:178693.3-178694.41" - process $proc$libresoc.v:178693$10729 + attribute \src "libresoc.v:178441.3-178442.41" + process $proc$libresoc.v:178441$10723 assign { } { } assign $0\msr0__data_o[63:0] \msr0__data_o$next sync posedge \coresync_clk update \msr0__data_o $0\msr0__data_o[63:0] end - attribute \src "libresoc.v:178695.3-178696.41" - process $proc$libresoc.v:178695$10730 + attribute \src "libresoc.v:178443.3-178444.41" + process $proc$libresoc.v:178443$10724 assign { } { } assign $0\cia0__data_o[63:0] \cia0__data_o$next sync posedge \coresync_clk update \cia0__data_o $0\cia0__data_o[63:0] end - attribute \src "libresoc.v:178697.3-178742.6" - process $proc$libresoc.v:178697$10731 + attribute \src "libresoc.v:178445.3-178490.6" + process $proc$libresoc.v:178445$10725 assign { } { } assign { } { } assign { } { } - assign $0\cia0__data_o$next[63:0]$10732 $7\cia0__data_o$next[63:0]$10739 - attribute \src "libresoc.v:178698.5-178698.29" + assign $0\cia0__data_o$next[63:0]$10726 $7\cia0__data_o$next[63:0]$10733 + attribute \src "libresoc.v:178446.5-178446.29" switch \initial - attribute \src "libresoc.v:178698.9-178698.17" + attribute \src "libresoc.v:178446.9-178446.17" case 1'1 case end @@ -331893,75 +331599,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\cia0__data_o$next[63:0]$10733 $6\cia0__data_o$next[63:0]$10738 + assign $1\cia0__data_o$next[63:0]$10727 $6\cia0__data_o$next[63:0]$10732 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia0__data_o$next[63:0]$10734 \nia0__data_i + assign $2\cia0__data_o$next[63:0]$10728 \nia0__data_i case - assign $2\cia0__data_o$next[63:0]$10734 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia0__data_o$next[63:0]$10728 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia0__data_o$next[63:0]$10735 \msr0__data_i + assign $3\cia0__data_o$next[63:0]$10729 \msr0__data_i case - assign $3\cia0__data_o$next[63:0]$10735 $2\cia0__data_o$next[63:0]$10734 + assign $3\cia0__data_o$next[63:0]$10729 $2\cia0__data_o$next[63:0]$10728 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia0__data_o$next[63:0]$10736 \sv0__data_i + assign $4\cia0__data_o$next[63:0]$10730 \sv0__data_i case - assign $4\cia0__data_o$next[63:0]$10736 $3\cia0__data_o$next[63:0]$10735 + assign $4\cia0__data_o$next[63:0]$10730 $3\cia0__data_o$next[63:0]$10729 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia0__data_o$next[63:0]$10737 \d_wr10__data_i + assign $5\cia0__data_o$next[63:0]$10731 \d_wr10__data_i case - assign $5\cia0__data_o$next[63:0]$10737 $4\cia0__data_o$next[63:0]$10736 + assign $5\cia0__data_o$next[63:0]$10731 $4\cia0__data_o$next[63:0]$10730 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia0__data_o$next[63:0]$10738 \reg + assign $6\cia0__data_o$next[63:0]$10732 \reg case - assign $6\cia0__data_o$next[63:0]$10738 $5\cia0__data_o$next[63:0]$10737 + assign $6\cia0__data_o$next[63:0]$10732 $5\cia0__data_o$next[63:0]$10731 end case - assign $1\cia0__data_o$next[63:0]$10733 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia0__data_o$next[63:0]$10727 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia0__data_o$next[63:0]$10739 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia0__data_o$next[63:0]$10733 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia0__data_o$next[63:0]$10739 $1\cia0__data_o$next[63:0]$10733 + assign $7\cia0__data_o$next[63:0]$10733 $1\cia0__data_o$next[63:0]$10727 end sync always - update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10732 + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10726 end - attribute \src "libresoc.v:178743.3-178778.6" - process $proc$libresoc.v:178743$10740 + attribute \src "libresoc.v:178491.3-178526.6" + process $proc$libresoc.v:178491$10734 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178744.5-178744.29" + attribute \src "libresoc.v:178492.5-178492.29" switch \initial - attribute \src "libresoc.v:178744.9-178744.17" + attribute \src "libresoc.v:178492.9-178492.17" case 1'1 case end @@ -332017,15 +331723,15 @@ module \reg_0$135 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178779.3-178824.6" - process $proc$libresoc.v:178779$10741 + attribute \src "libresoc.v:178527.3-178572.6" + process $proc$libresoc.v:178527$10735 assign { } { } assign { } { } assign { } { } - assign $0\msr0__data_o$next[63:0]$10742 $7\msr0__data_o$next[63:0]$10749 - attribute \src "libresoc.v:178780.5-178780.29" + assign $0\msr0__data_o$next[63:0]$10736 $7\msr0__data_o$next[63:0]$10743 + attribute \src "libresoc.v:178528.5-178528.29" switch \initial - attribute \src "libresoc.v:178780.9-178780.17" + attribute \src "libresoc.v:178528.9-178528.17" case 1'1 case end @@ -332038,75 +331744,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\msr0__data_o$next[63:0]$10743 $6\msr0__data_o$next[63:0]$10748 + assign $1\msr0__data_o$next[63:0]$10737 $6\msr0__data_o$next[63:0]$10742 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr0__data_o$next[63:0]$10744 \nia0__data_i + assign $2\msr0__data_o$next[63:0]$10738 \nia0__data_i case - assign $2\msr0__data_o$next[63:0]$10744 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr0__data_o$next[63:0]$10738 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr0__data_o$next[63:0]$10745 \msr0__data_i + assign $3\msr0__data_o$next[63:0]$10739 \msr0__data_i case - assign $3\msr0__data_o$next[63:0]$10745 $2\msr0__data_o$next[63:0]$10744 + assign $3\msr0__data_o$next[63:0]$10739 $2\msr0__data_o$next[63:0]$10738 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr0__data_o$next[63:0]$10746 \sv0__data_i + assign $4\msr0__data_o$next[63:0]$10740 \sv0__data_i case - assign $4\msr0__data_o$next[63:0]$10746 $3\msr0__data_o$next[63:0]$10745 + assign $4\msr0__data_o$next[63:0]$10740 $3\msr0__data_o$next[63:0]$10739 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr0__data_o$next[63:0]$10747 \d_wr10__data_i + assign $5\msr0__data_o$next[63:0]$10741 \d_wr10__data_i case - assign $5\msr0__data_o$next[63:0]$10747 $4\msr0__data_o$next[63:0]$10746 + assign $5\msr0__data_o$next[63:0]$10741 $4\msr0__data_o$next[63:0]$10740 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr0__data_o$next[63:0]$10748 \reg + assign $6\msr0__data_o$next[63:0]$10742 \reg case - assign $6\msr0__data_o$next[63:0]$10748 $5\msr0__data_o$next[63:0]$10747 + assign $6\msr0__data_o$next[63:0]$10742 $5\msr0__data_o$next[63:0]$10741 end case - assign $1\msr0__data_o$next[63:0]$10743 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr0__data_o$next[63:0]$10737 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr0__data_o$next[63:0]$10749 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr0__data_o$next[63:0]$10743 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr0__data_o$next[63:0]$10749 $1\msr0__data_o$next[63:0]$10743 + assign $7\msr0__data_o$next[63:0]$10743 $1\msr0__data_o$next[63:0]$10737 end sync always - update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10742 + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10736 end - attribute \src "libresoc.v:178825.3-178860.6" - process $proc$libresoc.v:178825$10750 + attribute \src "libresoc.v:178573.3-178608.6" + process $proc$libresoc.v:178573$10744 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10751 $1\wr_detect$4[0:0]$10752 - attribute \src "libresoc.v:178826.5-178826.29" + assign $0\wr_detect$4[0:0]$10745 $1\wr_detect$4[0:0]$10746 + attribute \src "libresoc.v:178574.5-178574.29" switch \initial - attribute \src "libresoc.v:178826.9-178826.17" + attribute \src "libresoc.v:178574.9-178574.17" case 1'1 case end @@ -332119,58 +331825,58 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10752 $5\wr_detect$4[0:0]$10756 + assign $1\wr_detect$4[0:0]$10746 $5\wr_detect$4[0:0]$10750 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10753 1'1 + assign $2\wr_detect$4[0:0]$10747 1'1 case - assign $2\wr_detect$4[0:0]$10753 1'0 + assign $2\wr_detect$4[0:0]$10747 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10754 1'1 + assign $3\wr_detect$4[0:0]$10748 1'1 case - assign $3\wr_detect$4[0:0]$10754 $2\wr_detect$4[0:0]$10753 + assign $3\wr_detect$4[0:0]$10748 $2\wr_detect$4[0:0]$10747 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10755 1'1 + assign $4\wr_detect$4[0:0]$10749 1'1 case - assign $4\wr_detect$4[0:0]$10755 $3\wr_detect$4[0:0]$10754 + assign $4\wr_detect$4[0:0]$10749 $3\wr_detect$4[0:0]$10748 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10756 1'1 + assign $5\wr_detect$4[0:0]$10750 1'1 case - assign $5\wr_detect$4[0:0]$10756 $4\wr_detect$4[0:0]$10755 + assign $5\wr_detect$4[0:0]$10750 $4\wr_detect$4[0:0]$10749 end case - assign $1\wr_detect$4[0:0]$10752 1'0 + assign $1\wr_detect$4[0:0]$10746 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10751 + update \wr_detect$4 $0\wr_detect$4[0:0]$10745 end - attribute \src "libresoc.v:178861.3-178906.6" - process $proc$libresoc.v:178861$10757 + attribute \src "libresoc.v:178609.3-178654.6" + process $proc$libresoc.v:178609$10751 assign { } { } assign { } { } assign { } { } - assign $0\sv0__data_o$next[63:0]$10758 $7\sv0__data_o$next[63:0]$10765 - attribute \src "libresoc.v:178862.5-178862.29" + assign $0\sv0__data_o$next[63:0]$10752 $7\sv0__data_o$next[63:0]$10759 + attribute \src "libresoc.v:178610.5-178610.29" switch \initial - attribute \src "libresoc.v:178862.9-178862.17" + attribute \src "libresoc.v:178610.9-178610.17" case 1'1 case end @@ -332183,75 +331889,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\sv0__data_o$next[63:0]$10759 $6\sv0__data_o$next[63:0]$10764 + assign $1\sv0__data_o$next[63:0]$10753 $6\sv0__data_o$next[63:0]$10758 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv0__data_o$next[63:0]$10760 \nia0__data_i + assign $2\sv0__data_o$next[63:0]$10754 \nia0__data_i case - assign $2\sv0__data_o$next[63:0]$10760 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv0__data_o$next[63:0]$10754 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv0__data_o$next[63:0]$10761 \msr0__data_i + assign $3\sv0__data_o$next[63:0]$10755 \msr0__data_i case - assign $3\sv0__data_o$next[63:0]$10761 $2\sv0__data_o$next[63:0]$10760 + assign $3\sv0__data_o$next[63:0]$10755 $2\sv0__data_o$next[63:0]$10754 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv0__data_o$next[63:0]$10762 \sv0__data_i + assign $4\sv0__data_o$next[63:0]$10756 \sv0__data_i case - assign $4\sv0__data_o$next[63:0]$10762 $3\sv0__data_o$next[63:0]$10761 + assign $4\sv0__data_o$next[63:0]$10756 $3\sv0__data_o$next[63:0]$10755 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv0__data_o$next[63:0]$10763 \d_wr10__data_i + assign $5\sv0__data_o$next[63:0]$10757 \d_wr10__data_i case - assign $5\sv0__data_o$next[63:0]$10763 $4\sv0__data_o$next[63:0]$10762 + assign $5\sv0__data_o$next[63:0]$10757 $4\sv0__data_o$next[63:0]$10756 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv0__data_o$next[63:0]$10764 \reg + assign $6\sv0__data_o$next[63:0]$10758 \reg case - assign $6\sv0__data_o$next[63:0]$10764 $5\sv0__data_o$next[63:0]$10763 + assign $6\sv0__data_o$next[63:0]$10758 $5\sv0__data_o$next[63:0]$10757 end case - assign $1\sv0__data_o$next[63:0]$10759 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv0__data_o$next[63:0]$10753 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv0__data_o$next[63:0]$10765 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv0__data_o$next[63:0]$10759 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv0__data_o$next[63:0]$10765 $1\sv0__data_o$next[63:0]$10759 + assign $7\sv0__data_o$next[63:0]$10759 $1\sv0__data_o$next[63:0]$10753 end sync always - update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10758 + update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10752 end - attribute \src "libresoc.v:178907.3-178942.6" - process $proc$libresoc.v:178907$10766 + attribute \src "libresoc.v:178655.3-178690.6" + process $proc$libresoc.v:178655$10760 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10767 $1\wr_detect$7[0:0]$10768 - attribute \src "libresoc.v:178908.5-178908.29" + assign $0\wr_detect$7[0:0]$10761 $1\wr_detect$7[0:0]$10762 + attribute \src "libresoc.v:178656.5-178656.29" switch \initial - attribute \src "libresoc.v:178908.9-178908.17" + attribute \src "libresoc.v:178656.9-178656.17" case 1'1 case end @@ -332264,61 +331970,61 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10768 $5\wr_detect$7[0:0]$10772 + assign $1\wr_detect$7[0:0]$10762 $5\wr_detect$7[0:0]$10766 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10769 1'1 + assign $2\wr_detect$7[0:0]$10763 1'1 case - assign $2\wr_detect$7[0:0]$10769 1'0 + assign $2\wr_detect$7[0:0]$10763 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10770 1'1 + assign $3\wr_detect$7[0:0]$10764 1'1 case - assign $3\wr_detect$7[0:0]$10770 $2\wr_detect$7[0:0]$10769 + assign $3\wr_detect$7[0:0]$10764 $2\wr_detect$7[0:0]$10763 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10771 1'1 + assign $4\wr_detect$7[0:0]$10765 1'1 case - assign $4\wr_detect$7[0:0]$10771 $3\wr_detect$7[0:0]$10770 + assign $4\wr_detect$7[0:0]$10765 $3\wr_detect$7[0:0]$10764 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10772 1'1 + assign $5\wr_detect$7[0:0]$10766 1'1 case - assign $5\wr_detect$7[0:0]$10772 $4\wr_detect$7[0:0]$10771 + assign $5\wr_detect$7[0:0]$10766 $4\wr_detect$7[0:0]$10765 end case - assign $1\wr_detect$7[0:0]$10768 1'0 + assign $1\wr_detect$7[0:0]$10762 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10767 + update \wr_detect$7 $0\wr_detect$7[0:0]$10761 end - attribute \src "libresoc.v:178943.3-178975.6" - process $proc$libresoc.v:178943$10773 + attribute \src "libresoc.v:178691.3-178723.6" + process $proc$libresoc.v:178691$10767 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$10774 $5\reg$next[63:0]$10779 - attribute \src "libresoc.v:178944.5-178944.29" + assign $0\reg$next[63:0]$10768 $5\reg$next[63:0]$10773 + attribute \src "libresoc.v:178692.5-178692.29" switch \initial - attribute \src "libresoc.v:178944.9-178944.17" + attribute \src "libresoc.v:178692.9-178692.17" case 1'1 case end @@ -332327,224 +332033,224 @@ module \reg_0$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10775 \nia0__data_i + assign $1\reg$next[63:0]$10769 \nia0__data_i case - assign $1\reg$next[63:0]$10775 \reg + assign $1\reg$next[63:0]$10769 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10776 \msr0__data_i + assign $2\reg$next[63:0]$10770 \msr0__data_i case - assign $2\reg$next[63:0]$10776 $1\reg$next[63:0]$10775 + assign $2\reg$next[63:0]$10770 $1\reg$next[63:0]$10769 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10777 \sv0__data_i + assign $3\reg$next[63:0]$10771 \sv0__data_i case - assign $3\reg$next[63:0]$10777 $2\reg$next[63:0]$10776 + assign $3\reg$next[63:0]$10771 $2\reg$next[63:0]$10770 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10778 \d_wr10__data_i + assign $4\reg$next[63:0]$10772 \d_wr10__data_i case - assign $4\reg$next[63:0]$10778 $3\reg$next[63:0]$10777 + assign $4\reg$next[63:0]$10772 $3\reg$next[63:0]$10771 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$10779 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$10773 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$10779 $4\reg$next[63:0]$10778 + assign $5\reg$next[63:0]$10773 $4\reg$next[63:0]$10772 end sync always - update \reg$next $0\reg$next[63:0]$10774 + update \reg$next $0\reg$next[63:0]$10768 end - connect \$1 $not$libresoc.v:178686$10724_Y - connect \$3 $not$libresoc.v:178687$10725_Y - connect \$6 $not$libresoc.v:178688$10726_Y + connect \$1 $not$libresoc.v:178434$10718_Y + connect \$3 $not$libresoc.v:178435$10719_Y + connect \$6 $not$libresoc.v:178436$10720_Y end -attribute \src "libresoc.v:178980.1-179451.10" +attribute \src "libresoc.v:178728.1-179199.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" attribute \generator "nMigen" module \reg_1 - attribute \src "libresoc.v:178981.7-178981.20" + attribute \src "libresoc.v:178729.7-178729.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179311.3-179350.6" - wire width 4 $0\r1__data_o$next[3:0]$10840 - attribute \src "libresoc.v:179066.3-179067.37" + attribute \src "libresoc.v:179059.3-179098.6" + wire width 4 $0\r1__data_o$next[3:0]$10834 + attribute \src "libresoc.v:178814.3-178815.37" wire width 4 $0\r1__data_o[3:0] - attribute \src "libresoc.v:179381.3-179420.6" - wire width 4 $0\r21__data_o$next[3:0]$10854 - attribute \src "libresoc.v:179064.3-179065.39" + attribute \src "libresoc.v:179129.3-179168.6" + wire width 4 $0\r21__data_o$next[3:0]$10848 + attribute \src "libresoc.v:178812.3-178813.39" wire width 4 $0\r21__data_o[3:0] - attribute \src "libresoc.v:179144.3-179170.6" - wire width 4 $0\reg$next[3:0]$10806 - attribute \src "libresoc.v:179062.3-179063.25" + attribute \src "libresoc.v:178892.3-178918.6" + wire width 4 $0\reg$next[3:0]$10800 + attribute \src "libresoc.v:178810.3-178811.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:179074.3-179113.6" - wire width 4 $0\src11__data_o$next[3:0]$10797 - attribute \src "libresoc.v:179072.3-179073.43" + attribute \src "libresoc.v:178822.3-178861.6" + wire width 4 $0\src11__data_o$next[3:0]$10791 + attribute \src "libresoc.v:178820.3-178821.43" wire width 4 $0\src11__data_o[3:0] - attribute \src "libresoc.v:179171.3-179210.6" - wire width 4 $0\src21__data_o$next[3:0]$10812 - attribute \src "libresoc.v:179070.3-179071.43" + attribute \src "libresoc.v:178919.3-178958.6" + wire width 4 $0\src21__data_o$next[3:0]$10806 + attribute \src "libresoc.v:178818.3-178819.43" wire width 4 $0\src21__data_o[3:0] - attribute \src "libresoc.v:179241.3-179280.6" - wire width 4 $0\src31__data_o$next[3:0]$10826 - attribute \src "libresoc.v:179068.3-179069.43" + attribute \src "libresoc.v:178989.3-179028.6" + wire width 4 $0\src31__data_o$next[3:0]$10820 + attribute \src "libresoc.v:178816.3-178817.43" wire width 4 $0\src31__data_o[3:0] - attribute \src "libresoc.v:179351.3-179380.6" - wire $0\wr_detect$10[0:0]$10848 - attribute \src "libresoc.v:179421.3-179450.6" - wire $0\wr_detect$13[0:0]$10862 - attribute \src "libresoc.v:179211.3-179240.6" - wire $0\wr_detect$4[0:0]$10820 - attribute \src "libresoc.v:179281.3-179310.6" - wire $0\wr_detect$7[0:0]$10834 - attribute \src "libresoc.v:179114.3-179143.6" + attribute \src "libresoc.v:179099.3-179128.6" + wire $0\wr_detect$10[0:0]$10842 + attribute \src "libresoc.v:179169.3-179198.6" + wire $0\wr_detect$13[0:0]$10856 + attribute \src "libresoc.v:178959.3-178988.6" + wire $0\wr_detect$4[0:0]$10814 + attribute \src "libresoc.v:179029.3-179058.6" + wire $0\wr_detect$7[0:0]$10828 + attribute \src "libresoc.v:178862.3-178891.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179311.3-179350.6" - wire width 4 $1\r1__data_o$next[3:0]$10841 - attribute \src "libresoc.v:179006.13-179006.30" + attribute \src "libresoc.v:179059.3-179098.6" + wire width 4 $1\r1__data_o$next[3:0]$10835 + attribute \src "libresoc.v:178754.13-178754.30" wire width 4 $1\r1__data_o[3:0] - attribute \src "libresoc.v:179381.3-179420.6" - wire width 4 $1\r21__data_o$next[3:0]$10855 - attribute \src "libresoc.v:179013.13-179013.31" + attribute \src "libresoc.v:179129.3-179168.6" + wire width 4 $1\r21__data_o$next[3:0]$10849 + attribute \src "libresoc.v:178761.13-178761.31" wire width 4 $1\r21__data_o[3:0] - attribute \src "libresoc.v:179144.3-179170.6" - wire width 4 $1\reg$next[3:0]$10807 - attribute \src "libresoc.v:179019.13-179019.25" + attribute \src "libresoc.v:178892.3-178918.6" + wire width 4 $1\reg$next[3:0]$10801 + attribute \src "libresoc.v:178767.13-178767.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:179074.3-179113.6" - wire width 4 $1\src11__data_o$next[3:0]$10798 - attribute \src "libresoc.v:179024.13-179024.33" + attribute \src "libresoc.v:178822.3-178861.6" + wire width 4 $1\src11__data_o$next[3:0]$10792 + attribute \src "libresoc.v:178772.13-178772.33" wire width 4 $1\src11__data_o[3:0] - attribute \src "libresoc.v:179171.3-179210.6" - wire width 4 $1\src21__data_o$next[3:0]$10813 - attribute \src "libresoc.v:179031.13-179031.33" + attribute \src "libresoc.v:178919.3-178958.6" + wire width 4 $1\src21__data_o$next[3:0]$10807 + attribute \src "libresoc.v:178779.13-178779.33" wire width 4 $1\src21__data_o[3:0] - attribute \src "libresoc.v:179241.3-179280.6" - wire width 4 $1\src31__data_o$next[3:0]$10827 - attribute \src "libresoc.v:179038.13-179038.33" + attribute \src "libresoc.v:178989.3-179028.6" + wire width 4 $1\src31__data_o$next[3:0]$10821 + attribute \src "libresoc.v:178786.13-178786.33" wire width 4 $1\src31__data_o[3:0] - attribute \src "libresoc.v:179351.3-179380.6" - wire $1\wr_detect$10[0:0]$10849 - attribute \src "libresoc.v:179421.3-179450.6" - wire $1\wr_detect$13[0:0]$10863 - attribute \src "libresoc.v:179211.3-179240.6" - wire $1\wr_detect$4[0:0]$10821 - attribute \src "libresoc.v:179281.3-179310.6" - wire $1\wr_detect$7[0:0]$10835 - attribute \src "libresoc.v:179114.3-179143.6" + attribute \src "libresoc.v:179099.3-179128.6" + wire $1\wr_detect$10[0:0]$10843 + attribute \src "libresoc.v:179169.3-179198.6" + wire $1\wr_detect$13[0:0]$10857 + attribute \src "libresoc.v:178959.3-178988.6" + wire $1\wr_detect$4[0:0]$10815 + attribute \src "libresoc.v:179029.3-179058.6" + wire $1\wr_detect$7[0:0]$10829 + attribute \src "libresoc.v:178862.3-178891.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179311.3-179350.6" - wire width 4 $2\r1__data_o$next[3:0]$10842 - attribute \src "libresoc.v:179381.3-179420.6" - wire width 4 $2\r21__data_o$next[3:0]$10856 - attribute \src "libresoc.v:179144.3-179170.6" - wire width 4 $2\reg$next[3:0]$10808 - attribute \src "libresoc.v:179074.3-179113.6" - wire width 4 $2\src11__data_o$next[3:0]$10799 - attribute \src "libresoc.v:179171.3-179210.6" - wire width 4 $2\src21__data_o$next[3:0]$10814 - attribute \src "libresoc.v:179241.3-179280.6" - wire width 4 $2\src31__data_o$next[3:0]$10828 - attribute \src "libresoc.v:179351.3-179380.6" - wire $2\wr_detect$10[0:0]$10850 - attribute \src "libresoc.v:179421.3-179450.6" - wire $2\wr_detect$13[0:0]$10864 - attribute \src "libresoc.v:179211.3-179240.6" - wire $2\wr_detect$4[0:0]$10822 - attribute \src "libresoc.v:179281.3-179310.6" - wire $2\wr_detect$7[0:0]$10836 - attribute \src "libresoc.v:179114.3-179143.6" + attribute \src "libresoc.v:179059.3-179098.6" + wire width 4 $2\r1__data_o$next[3:0]$10836 + attribute \src "libresoc.v:179129.3-179168.6" + wire width 4 $2\r21__data_o$next[3:0]$10850 + attribute \src "libresoc.v:178892.3-178918.6" + wire width 4 $2\reg$next[3:0]$10802 + attribute \src "libresoc.v:178822.3-178861.6" + wire width 4 $2\src11__data_o$next[3:0]$10793 + attribute \src "libresoc.v:178919.3-178958.6" + wire width 4 $2\src21__data_o$next[3:0]$10808 + attribute \src "libresoc.v:178989.3-179028.6" + wire width 4 $2\src31__data_o$next[3:0]$10822 + attribute \src "libresoc.v:179099.3-179128.6" + wire $2\wr_detect$10[0:0]$10844 + attribute \src "libresoc.v:179169.3-179198.6" + wire $2\wr_detect$13[0:0]$10858 + attribute \src "libresoc.v:178959.3-178988.6" + wire $2\wr_detect$4[0:0]$10816 + attribute \src "libresoc.v:179029.3-179058.6" + wire $2\wr_detect$7[0:0]$10830 + attribute \src "libresoc.v:178862.3-178891.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179311.3-179350.6" - wire width 4 $3\r1__data_o$next[3:0]$10843 - attribute \src "libresoc.v:179381.3-179420.6" - wire width 4 $3\r21__data_o$next[3:0]$10857 - attribute \src "libresoc.v:179144.3-179170.6" - wire width 4 $3\reg$next[3:0]$10809 - attribute \src "libresoc.v:179074.3-179113.6" - wire width 4 $3\src11__data_o$next[3:0]$10800 - attribute \src "libresoc.v:179171.3-179210.6" - wire width 4 $3\src21__data_o$next[3:0]$10815 - attribute \src "libresoc.v:179241.3-179280.6" - wire width 4 $3\src31__data_o$next[3:0]$10829 - attribute \src "libresoc.v:179351.3-179380.6" - wire $3\wr_detect$10[0:0]$10851 - attribute \src "libresoc.v:179421.3-179450.6" - wire $3\wr_detect$13[0:0]$10865 - attribute \src "libresoc.v:179211.3-179240.6" - wire $3\wr_detect$4[0:0]$10823 - attribute \src "libresoc.v:179281.3-179310.6" - wire $3\wr_detect$7[0:0]$10837 - attribute \src "libresoc.v:179114.3-179143.6" + attribute \src "libresoc.v:179059.3-179098.6" + wire width 4 $3\r1__data_o$next[3:0]$10837 + attribute \src "libresoc.v:179129.3-179168.6" + wire width 4 $3\r21__data_o$next[3:0]$10851 + attribute \src "libresoc.v:178892.3-178918.6" + wire width 4 $3\reg$next[3:0]$10803 + attribute \src "libresoc.v:178822.3-178861.6" + wire width 4 $3\src11__data_o$next[3:0]$10794 + attribute \src "libresoc.v:178919.3-178958.6" + wire width 4 $3\src21__data_o$next[3:0]$10809 + attribute \src "libresoc.v:178989.3-179028.6" + wire width 4 $3\src31__data_o$next[3:0]$10823 + attribute \src "libresoc.v:179099.3-179128.6" + wire $3\wr_detect$10[0:0]$10845 + attribute \src "libresoc.v:179169.3-179198.6" + wire $3\wr_detect$13[0:0]$10859 + attribute \src "libresoc.v:178959.3-178988.6" + wire $3\wr_detect$4[0:0]$10817 + attribute \src "libresoc.v:179029.3-179058.6" + wire $3\wr_detect$7[0:0]$10831 + attribute \src "libresoc.v:178862.3-178891.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179311.3-179350.6" - wire width 4 $4\r1__data_o$next[3:0]$10844 - attribute \src "libresoc.v:179381.3-179420.6" - wire width 4 $4\r21__data_o$next[3:0]$10858 - attribute \src "libresoc.v:179144.3-179170.6" - wire width 4 $4\reg$next[3:0]$10810 - attribute \src "libresoc.v:179074.3-179113.6" - wire width 4 $4\src11__data_o$next[3:0]$10801 - attribute \src "libresoc.v:179171.3-179210.6" - wire width 4 $4\src21__data_o$next[3:0]$10816 - attribute \src "libresoc.v:179241.3-179280.6" - wire width 4 $4\src31__data_o$next[3:0]$10830 - attribute \src "libresoc.v:179351.3-179380.6" - wire $4\wr_detect$10[0:0]$10852 - attribute \src "libresoc.v:179421.3-179450.6" - wire $4\wr_detect$13[0:0]$10866 - attribute \src "libresoc.v:179211.3-179240.6" - wire $4\wr_detect$4[0:0]$10824 - attribute \src "libresoc.v:179281.3-179310.6" - wire $4\wr_detect$7[0:0]$10838 - attribute \src "libresoc.v:179114.3-179143.6" + attribute \src "libresoc.v:179059.3-179098.6" + wire width 4 $4\r1__data_o$next[3:0]$10838 + attribute \src "libresoc.v:179129.3-179168.6" + wire width 4 $4\r21__data_o$next[3:0]$10852 + attribute \src "libresoc.v:178892.3-178918.6" + wire width 4 $4\reg$next[3:0]$10804 + attribute \src "libresoc.v:178822.3-178861.6" + wire width 4 $4\src11__data_o$next[3:0]$10795 + attribute \src "libresoc.v:178919.3-178958.6" + wire width 4 $4\src21__data_o$next[3:0]$10810 + attribute \src "libresoc.v:178989.3-179028.6" + wire width 4 $4\src31__data_o$next[3:0]$10824 + attribute \src "libresoc.v:179099.3-179128.6" + wire $4\wr_detect$10[0:0]$10846 + attribute \src "libresoc.v:179169.3-179198.6" + wire $4\wr_detect$13[0:0]$10860 + attribute \src "libresoc.v:178959.3-178988.6" + wire $4\wr_detect$4[0:0]$10818 + attribute \src "libresoc.v:179029.3-179058.6" + wire $4\wr_detect$7[0:0]$10832 + attribute \src "libresoc.v:178862.3-178891.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179311.3-179350.6" - wire width 4 $5\r1__data_o$next[3:0]$10845 - attribute \src "libresoc.v:179381.3-179420.6" - wire width 4 $5\r21__data_o$next[3:0]$10859 - attribute \src "libresoc.v:179074.3-179113.6" - wire width 4 $5\src11__data_o$next[3:0]$10802 - attribute \src "libresoc.v:179171.3-179210.6" - wire width 4 $5\src21__data_o$next[3:0]$10817 - attribute \src "libresoc.v:179241.3-179280.6" - wire width 4 $5\src31__data_o$next[3:0]$10831 - attribute \src "libresoc.v:179311.3-179350.6" - wire width 4 $6\r1__data_o$next[3:0]$10846 - attribute \src "libresoc.v:179381.3-179420.6" - wire width 4 $6\r21__data_o$next[3:0]$10860 - attribute \src "libresoc.v:179074.3-179113.6" - wire width 4 $6\src11__data_o$next[3:0]$10803 - attribute \src "libresoc.v:179171.3-179210.6" - wire width 4 $6\src21__data_o$next[3:0]$10818 - attribute \src "libresoc.v:179241.3-179280.6" - wire width 4 $6\src31__data_o$next[3:0]$10832 - attribute \src "libresoc.v:179057.17-179057.104" - wire $not$libresoc.v:179057$10785_Y - attribute \src "libresoc.v:179058.18-179058.105" - wire $not$libresoc.v:179058$10786_Y - attribute \src "libresoc.v:179059.17-179059.100" - wire $not$libresoc.v:179059$10787_Y - attribute \src "libresoc.v:179060.17-179060.103" - wire $not$libresoc.v:179060$10788_Y - attribute \src "libresoc.v:179061.17-179061.103" - wire $not$libresoc.v:179061$10789_Y + attribute \src "libresoc.v:179059.3-179098.6" + wire width 4 $5\r1__data_o$next[3:0]$10839 + attribute \src "libresoc.v:179129.3-179168.6" + wire width 4 $5\r21__data_o$next[3:0]$10853 + attribute \src "libresoc.v:178822.3-178861.6" + wire width 4 $5\src11__data_o$next[3:0]$10796 + attribute \src "libresoc.v:178919.3-178958.6" + wire width 4 $5\src21__data_o$next[3:0]$10811 + attribute \src "libresoc.v:178989.3-179028.6" + wire width 4 $5\src31__data_o$next[3:0]$10825 + attribute \src "libresoc.v:179059.3-179098.6" + wire width 4 $6\r1__data_o$next[3:0]$10840 + attribute \src "libresoc.v:179129.3-179168.6" + wire width 4 $6\r21__data_o$next[3:0]$10854 + attribute \src "libresoc.v:178822.3-178861.6" + wire width 4 $6\src11__data_o$next[3:0]$10797 + attribute \src "libresoc.v:178919.3-178958.6" + wire width 4 $6\src21__data_o$next[3:0]$10812 + attribute \src "libresoc.v:178989.3-179028.6" + wire width 4 $6\src31__data_o$next[3:0]$10826 + attribute \src "libresoc.v:178805.17-178805.104" + wire $not$libresoc.v:178805$10779_Y + attribute \src "libresoc.v:178806.18-178806.105" + wire $not$libresoc.v:178806$10780_Y + attribute \src "libresoc.v:178807.17-178807.100" + wire $not$libresoc.v:178807$10781_Y + attribute \src "libresoc.v:178808.17-178808.103" + wire $not$libresoc.v:178808$10782_Y + attribute \src "libresoc.v:178809.17-178809.103" + wire $not$libresoc.v:178809$10783_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -332555,9 +332261,9 @@ module \reg_1 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest11__data_i @@ -332567,7 +332273,7 @@ module \reg_1 wire width 4 input 11 \dest21__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest21__wen - attribute \src "libresoc.v:178981.7-178981.15" + attribute \src "libresoc.v:178729.7-178729.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r1__data_o @@ -332618,152 +332324,152 @@ module \reg_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179057$10785 + cell $not $not$libresoc.v:178805$10779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:179057$10785_Y + connect \Y $not$libresoc.v:178805$10779_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179058$10786 + cell $not $not$libresoc.v:178806$10780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:179058$10786_Y + connect \Y $not$libresoc.v:178806$10780_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179059$10787 + cell $not $not$libresoc.v:178807$10781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179059$10787_Y + connect \Y $not$libresoc.v:178807$10781_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179060$10788 + cell $not $not$libresoc.v:178808$10782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179060$10788_Y + connect \Y $not$libresoc.v:178808$10782_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179061$10789 + cell $not $not$libresoc.v:178809$10783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179061$10789_Y + connect \Y $not$libresoc.v:178809$10783_Y end - attribute \src "libresoc.v:178981.7-178981.20" - process $proc$libresoc.v:178981$10867 + attribute \src "libresoc.v:178729.7-178729.20" + process $proc$libresoc.v:178729$10861 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179006.13-179006.30" - process $proc$libresoc.v:179006$10868 + attribute \src "libresoc.v:178754.13-178754.30" + process $proc$libresoc.v:178754$10862 assign { } { } assign $1\r1__data_o[3:0] 4'0000 sync always sync init update \r1__data_o $1\r1__data_o[3:0] end - attribute \src "libresoc.v:179013.13-179013.31" - process $proc$libresoc.v:179013$10869 + attribute \src "libresoc.v:178761.13-178761.31" + process $proc$libresoc.v:178761$10863 assign { } { } assign $1\r21__data_o[3:0] 4'0000 sync always sync init update \r21__data_o $1\r21__data_o[3:0] end - attribute \src "libresoc.v:179019.13-179019.25" - process $proc$libresoc.v:179019$10870 + attribute \src "libresoc.v:178767.13-178767.25" + process $proc$libresoc.v:178767$10864 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:179024.13-179024.33" - process $proc$libresoc.v:179024$10871 + attribute \src "libresoc.v:178772.13-178772.33" + process $proc$libresoc.v:178772$10865 assign { } { } assign $1\src11__data_o[3:0] 4'0000 sync always sync init update \src11__data_o $1\src11__data_o[3:0] end - attribute \src "libresoc.v:179031.13-179031.33" - process $proc$libresoc.v:179031$10872 + attribute \src "libresoc.v:178779.13-178779.33" + process $proc$libresoc.v:178779$10866 assign { } { } assign $1\src21__data_o[3:0] 4'0000 sync always sync init update \src21__data_o $1\src21__data_o[3:0] end - attribute \src "libresoc.v:179038.13-179038.33" - process $proc$libresoc.v:179038$10873 + attribute \src "libresoc.v:178786.13-178786.33" + process $proc$libresoc.v:178786$10867 assign { } { } assign $1\src31__data_o[3:0] 4'0000 sync always sync init update \src31__data_o $1\src31__data_o[3:0] end - attribute \src "libresoc.v:179062.3-179063.25" - process $proc$libresoc.v:179062$10790 + attribute \src "libresoc.v:178810.3-178811.25" + process $proc$libresoc.v:178810$10784 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:179064.3-179065.39" - process $proc$libresoc.v:179064$10791 + attribute \src "libresoc.v:178812.3-178813.39" + process $proc$libresoc.v:178812$10785 assign { } { } assign $0\r21__data_o[3:0] \r21__data_o$next sync posedge \coresync_clk update \r21__data_o $0\r21__data_o[3:0] end - attribute \src "libresoc.v:179066.3-179067.37" - process $proc$libresoc.v:179066$10792 + attribute \src "libresoc.v:178814.3-178815.37" + process $proc$libresoc.v:178814$10786 assign { } { } assign $0\r1__data_o[3:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[3:0] end - attribute \src "libresoc.v:179068.3-179069.43" - process $proc$libresoc.v:179068$10793 + attribute \src "libresoc.v:178816.3-178817.43" + process $proc$libresoc.v:178816$10787 assign { } { } assign $0\src31__data_o[3:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[3:0] end - attribute \src "libresoc.v:179070.3-179071.43" - process $proc$libresoc.v:179070$10794 + attribute \src "libresoc.v:178818.3-178819.43" + process $proc$libresoc.v:178818$10788 assign { } { } assign $0\src21__data_o[3:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[3:0] end - attribute \src "libresoc.v:179072.3-179073.43" - process $proc$libresoc.v:179072$10795 + attribute \src "libresoc.v:178820.3-178821.43" + process $proc$libresoc.v:178820$10789 assign { } { } assign $0\src11__data_o[3:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[3:0] end - attribute \src "libresoc.v:179074.3-179113.6" - process $proc$libresoc.v:179074$10796 + attribute \src "libresoc.v:178822.3-178861.6" + process $proc$libresoc.v:178822$10790 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[3:0]$10797 $6\src11__data_o$next[3:0]$10803 - attribute \src "libresoc.v:179075.5-179075.29" + assign $0\src11__data_o$next[3:0]$10791 $6\src11__data_o$next[3:0]$10797 + attribute \src "libresoc.v:178823.5-178823.29" switch \initial - attribute \src "libresoc.v:179075.9-179075.17" + attribute \src "libresoc.v:178823.9-178823.17" case 1'1 case end @@ -332775,66 +332481,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[3:0]$10798 $5\src11__data_o$next[3:0]$10802 + assign $1\src11__data_o$next[3:0]$10792 $5\src11__data_o$next[3:0]$10796 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[3:0]$10799 \dest11__data_i + assign $2\src11__data_o$next[3:0]$10793 \dest11__data_i case - assign $2\src11__data_o$next[3:0]$10799 4'0000 + assign $2\src11__data_o$next[3:0]$10793 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[3:0]$10800 \dest21__data_i + assign $3\src11__data_o$next[3:0]$10794 \dest21__data_i case - assign $3\src11__data_o$next[3:0]$10800 $2\src11__data_o$next[3:0]$10799 + assign $3\src11__data_o$next[3:0]$10794 $2\src11__data_o$next[3:0]$10793 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[3:0]$10801 \w1__data_i + assign $4\src11__data_o$next[3:0]$10795 \w1__data_i case - assign $4\src11__data_o$next[3:0]$10801 $3\src11__data_o$next[3:0]$10800 + assign $4\src11__data_o$next[3:0]$10795 $3\src11__data_o$next[3:0]$10794 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[3:0]$10802 \reg + assign $5\src11__data_o$next[3:0]$10796 \reg case - assign $5\src11__data_o$next[3:0]$10802 $4\src11__data_o$next[3:0]$10801 + assign $5\src11__data_o$next[3:0]$10796 $4\src11__data_o$next[3:0]$10795 end case - assign $1\src11__data_o$next[3:0]$10798 4'0000 + assign $1\src11__data_o$next[3:0]$10792 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[3:0]$10803 4'0000 + assign $6\src11__data_o$next[3:0]$10797 4'0000 case - assign $6\src11__data_o$next[3:0]$10803 $1\src11__data_o$next[3:0]$10798 + assign $6\src11__data_o$next[3:0]$10797 $1\src11__data_o$next[3:0]$10792 end sync always - update \src11__data_o$next $0\src11__data_o$next[3:0]$10797 + update \src11__data_o$next $0\src11__data_o$next[3:0]$10791 end - attribute \src "libresoc.v:179114.3-179143.6" - process $proc$libresoc.v:179114$10804 + attribute \src "libresoc.v:178862.3-178891.6" + process $proc$libresoc.v:178862$10798 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179115.5-179115.29" + attribute \src "libresoc.v:178863.5-178863.29" switch \initial - attribute \src "libresoc.v:179115.9-179115.17" + attribute \src "libresoc.v:178863.9-178863.17" case 1'1 case end @@ -332880,17 +332586,17 @@ module \reg_1 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179144.3-179170.6" - process $proc$libresoc.v:179144$10805 + attribute \src "libresoc.v:178892.3-178918.6" + process $proc$libresoc.v:178892$10799 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10806 $4\reg$next[3:0]$10810 - attribute \src "libresoc.v:179145.5-179145.29" + assign $0\reg$next[3:0]$10800 $4\reg$next[3:0]$10804 + attribute \src "libresoc.v:178893.5-178893.29" switch \initial - attribute \src "libresoc.v:179145.9-179145.17" + attribute \src "libresoc.v:178893.9-178893.17" case 1'1 case end @@ -332899,49 +332605,49 @@ module \reg_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10807 \dest11__data_i + assign $1\reg$next[3:0]$10801 \dest11__data_i case - assign $1\reg$next[3:0]$10807 \reg + assign $1\reg$next[3:0]$10801 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10808 \dest21__data_i + assign $2\reg$next[3:0]$10802 \dest21__data_i case - assign $2\reg$next[3:0]$10808 $1\reg$next[3:0]$10807 + assign $2\reg$next[3:0]$10802 $1\reg$next[3:0]$10801 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10809 \w1__data_i + assign $3\reg$next[3:0]$10803 \w1__data_i case - assign $3\reg$next[3:0]$10809 $2\reg$next[3:0]$10808 + assign $3\reg$next[3:0]$10803 $2\reg$next[3:0]$10802 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10810 4'0000 + assign $4\reg$next[3:0]$10804 4'0000 case - assign $4\reg$next[3:0]$10810 $3\reg$next[3:0]$10809 + assign $4\reg$next[3:0]$10804 $3\reg$next[3:0]$10803 end sync always - update \reg$next $0\reg$next[3:0]$10806 + update \reg$next $0\reg$next[3:0]$10800 end - attribute \src "libresoc.v:179171.3-179210.6" - process $proc$libresoc.v:179171$10811 + attribute \src "libresoc.v:178919.3-178958.6" + process $proc$libresoc.v:178919$10805 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[3:0]$10812 $6\src21__data_o$next[3:0]$10818 - attribute \src "libresoc.v:179172.5-179172.29" + assign $0\src21__data_o$next[3:0]$10806 $6\src21__data_o$next[3:0]$10812 + attribute \src "libresoc.v:178920.5-178920.29" switch \initial - attribute \src "libresoc.v:179172.9-179172.17" + attribute \src "libresoc.v:178920.9-178920.17" case 1'1 case end @@ -332953,66 +332659,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[3:0]$10813 $5\src21__data_o$next[3:0]$10817 + assign $1\src21__data_o$next[3:0]$10807 $5\src21__data_o$next[3:0]$10811 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[3:0]$10814 \dest11__data_i + assign $2\src21__data_o$next[3:0]$10808 \dest11__data_i case - assign $2\src21__data_o$next[3:0]$10814 4'0000 + assign $2\src21__data_o$next[3:0]$10808 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[3:0]$10815 \dest21__data_i + assign $3\src21__data_o$next[3:0]$10809 \dest21__data_i case - assign $3\src21__data_o$next[3:0]$10815 $2\src21__data_o$next[3:0]$10814 + assign $3\src21__data_o$next[3:0]$10809 $2\src21__data_o$next[3:0]$10808 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[3:0]$10816 \w1__data_i + assign $4\src21__data_o$next[3:0]$10810 \w1__data_i case - assign $4\src21__data_o$next[3:0]$10816 $3\src21__data_o$next[3:0]$10815 + assign $4\src21__data_o$next[3:0]$10810 $3\src21__data_o$next[3:0]$10809 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[3:0]$10817 \reg + assign $5\src21__data_o$next[3:0]$10811 \reg case - assign $5\src21__data_o$next[3:0]$10817 $4\src21__data_o$next[3:0]$10816 + assign $5\src21__data_o$next[3:0]$10811 $4\src21__data_o$next[3:0]$10810 end case - assign $1\src21__data_o$next[3:0]$10813 4'0000 + assign $1\src21__data_o$next[3:0]$10807 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[3:0]$10818 4'0000 + assign $6\src21__data_o$next[3:0]$10812 4'0000 case - assign $6\src21__data_o$next[3:0]$10818 $1\src21__data_o$next[3:0]$10813 + assign $6\src21__data_o$next[3:0]$10812 $1\src21__data_o$next[3:0]$10807 end sync always - update \src21__data_o$next $0\src21__data_o$next[3:0]$10812 + update \src21__data_o$next $0\src21__data_o$next[3:0]$10806 end - attribute \src "libresoc.v:179211.3-179240.6" - process $proc$libresoc.v:179211$10819 + attribute \src "libresoc.v:178959.3-178988.6" + process $proc$libresoc.v:178959$10813 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10820 $1\wr_detect$4[0:0]$10821 - attribute \src "libresoc.v:179212.5-179212.29" + assign $0\wr_detect$4[0:0]$10814 $1\wr_detect$4[0:0]$10815 + attribute \src "libresoc.v:178960.5-178960.29" switch \initial - attribute \src "libresoc.v:179212.9-179212.17" + attribute \src "libresoc.v:178960.9-178960.17" case 1'1 case end @@ -333024,49 +332730,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10821 $4\wr_detect$4[0:0]$10824 + assign $1\wr_detect$4[0:0]$10815 $4\wr_detect$4[0:0]$10818 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10822 1'1 + assign $2\wr_detect$4[0:0]$10816 1'1 case - assign $2\wr_detect$4[0:0]$10822 1'0 + assign $2\wr_detect$4[0:0]$10816 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10823 1'1 + assign $3\wr_detect$4[0:0]$10817 1'1 case - assign $3\wr_detect$4[0:0]$10823 $2\wr_detect$4[0:0]$10822 + assign $3\wr_detect$4[0:0]$10817 $2\wr_detect$4[0:0]$10816 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10824 1'1 + assign $4\wr_detect$4[0:0]$10818 1'1 case - assign $4\wr_detect$4[0:0]$10824 $3\wr_detect$4[0:0]$10823 + assign $4\wr_detect$4[0:0]$10818 $3\wr_detect$4[0:0]$10817 end case - assign $1\wr_detect$4[0:0]$10821 1'0 + assign $1\wr_detect$4[0:0]$10815 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10820 + update \wr_detect$4 $0\wr_detect$4[0:0]$10814 end - attribute \src "libresoc.v:179241.3-179280.6" - process $proc$libresoc.v:179241$10825 + attribute \src "libresoc.v:178989.3-179028.6" + process $proc$libresoc.v:178989$10819 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[3:0]$10826 $6\src31__data_o$next[3:0]$10832 - attribute \src "libresoc.v:179242.5-179242.29" + assign $0\src31__data_o$next[3:0]$10820 $6\src31__data_o$next[3:0]$10826 + attribute \src "libresoc.v:178990.5-178990.29" switch \initial - attribute \src "libresoc.v:179242.9-179242.17" + attribute \src "libresoc.v:178990.9-178990.17" case 1'1 case end @@ -333078,66 +332784,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[3:0]$10827 $5\src31__data_o$next[3:0]$10831 + assign $1\src31__data_o$next[3:0]$10821 $5\src31__data_o$next[3:0]$10825 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[3:0]$10828 \dest11__data_i + assign $2\src31__data_o$next[3:0]$10822 \dest11__data_i case - assign $2\src31__data_o$next[3:0]$10828 4'0000 + assign $2\src31__data_o$next[3:0]$10822 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[3:0]$10829 \dest21__data_i + assign $3\src31__data_o$next[3:0]$10823 \dest21__data_i case - assign $3\src31__data_o$next[3:0]$10829 $2\src31__data_o$next[3:0]$10828 + assign $3\src31__data_o$next[3:0]$10823 $2\src31__data_o$next[3:0]$10822 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[3:0]$10830 \w1__data_i + assign $4\src31__data_o$next[3:0]$10824 \w1__data_i case - assign $4\src31__data_o$next[3:0]$10830 $3\src31__data_o$next[3:0]$10829 + assign $4\src31__data_o$next[3:0]$10824 $3\src31__data_o$next[3:0]$10823 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[3:0]$10831 \reg + assign $5\src31__data_o$next[3:0]$10825 \reg case - assign $5\src31__data_o$next[3:0]$10831 $4\src31__data_o$next[3:0]$10830 + assign $5\src31__data_o$next[3:0]$10825 $4\src31__data_o$next[3:0]$10824 end case - assign $1\src31__data_o$next[3:0]$10827 4'0000 + assign $1\src31__data_o$next[3:0]$10821 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[3:0]$10832 4'0000 + assign $6\src31__data_o$next[3:0]$10826 4'0000 case - assign $6\src31__data_o$next[3:0]$10832 $1\src31__data_o$next[3:0]$10827 + assign $6\src31__data_o$next[3:0]$10826 $1\src31__data_o$next[3:0]$10821 end sync always - update \src31__data_o$next $0\src31__data_o$next[3:0]$10826 + update \src31__data_o$next $0\src31__data_o$next[3:0]$10820 end - attribute \src "libresoc.v:179281.3-179310.6" - process $proc$libresoc.v:179281$10833 + attribute \src "libresoc.v:179029.3-179058.6" + process $proc$libresoc.v:179029$10827 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10834 $1\wr_detect$7[0:0]$10835 - attribute \src "libresoc.v:179282.5-179282.29" + assign $0\wr_detect$7[0:0]$10828 $1\wr_detect$7[0:0]$10829 + attribute \src "libresoc.v:179030.5-179030.29" switch \initial - attribute \src "libresoc.v:179282.9-179282.17" + attribute \src "libresoc.v:179030.9-179030.17" case 1'1 case end @@ -333149,49 +332855,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10835 $4\wr_detect$7[0:0]$10838 + assign $1\wr_detect$7[0:0]$10829 $4\wr_detect$7[0:0]$10832 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10836 1'1 + assign $2\wr_detect$7[0:0]$10830 1'1 case - assign $2\wr_detect$7[0:0]$10836 1'0 + assign $2\wr_detect$7[0:0]$10830 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10837 1'1 + assign $3\wr_detect$7[0:0]$10831 1'1 case - assign $3\wr_detect$7[0:0]$10837 $2\wr_detect$7[0:0]$10836 + assign $3\wr_detect$7[0:0]$10831 $2\wr_detect$7[0:0]$10830 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10838 1'1 + assign $4\wr_detect$7[0:0]$10832 1'1 case - assign $4\wr_detect$7[0:0]$10838 $3\wr_detect$7[0:0]$10837 + assign $4\wr_detect$7[0:0]$10832 $3\wr_detect$7[0:0]$10831 end case - assign $1\wr_detect$7[0:0]$10835 1'0 + assign $1\wr_detect$7[0:0]$10829 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10834 + update \wr_detect$7 $0\wr_detect$7[0:0]$10828 end - attribute \src "libresoc.v:179311.3-179350.6" - process $proc$libresoc.v:179311$10839 + attribute \src "libresoc.v:179059.3-179098.6" + process $proc$libresoc.v:179059$10833 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[3:0]$10840 $6\r1__data_o$next[3:0]$10846 - attribute \src "libresoc.v:179312.5-179312.29" + assign $0\r1__data_o$next[3:0]$10834 $6\r1__data_o$next[3:0]$10840 + attribute \src "libresoc.v:179060.5-179060.29" switch \initial - attribute \src "libresoc.v:179312.9-179312.17" + attribute \src "libresoc.v:179060.9-179060.17" case 1'1 case end @@ -333203,66 +332909,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[3:0]$10841 $5\r1__data_o$next[3:0]$10845 + assign $1\r1__data_o$next[3:0]$10835 $5\r1__data_o$next[3:0]$10839 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[3:0]$10842 \dest11__data_i + assign $2\r1__data_o$next[3:0]$10836 \dest11__data_i case - assign $2\r1__data_o$next[3:0]$10842 4'0000 + assign $2\r1__data_o$next[3:0]$10836 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[3:0]$10843 \dest21__data_i + assign $3\r1__data_o$next[3:0]$10837 \dest21__data_i case - assign $3\r1__data_o$next[3:0]$10843 $2\r1__data_o$next[3:0]$10842 + assign $3\r1__data_o$next[3:0]$10837 $2\r1__data_o$next[3:0]$10836 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[3:0]$10844 \w1__data_i + assign $4\r1__data_o$next[3:0]$10838 \w1__data_i case - assign $4\r1__data_o$next[3:0]$10844 $3\r1__data_o$next[3:0]$10843 + assign $4\r1__data_o$next[3:0]$10838 $3\r1__data_o$next[3:0]$10837 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[3:0]$10845 \reg + assign $5\r1__data_o$next[3:0]$10839 \reg case - assign $5\r1__data_o$next[3:0]$10845 $4\r1__data_o$next[3:0]$10844 + assign $5\r1__data_o$next[3:0]$10839 $4\r1__data_o$next[3:0]$10838 end case - assign $1\r1__data_o$next[3:0]$10841 4'0000 + assign $1\r1__data_o$next[3:0]$10835 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[3:0]$10846 4'0000 + assign $6\r1__data_o$next[3:0]$10840 4'0000 case - assign $6\r1__data_o$next[3:0]$10846 $1\r1__data_o$next[3:0]$10841 + assign $6\r1__data_o$next[3:0]$10840 $1\r1__data_o$next[3:0]$10835 end sync always - update \r1__data_o$next $0\r1__data_o$next[3:0]$10840 + update \r1__data_o$next $0\r1__data_o$next[3:0]$10834 end - attribute \src "libresoc.v:179351.3-179380.6" - process $proc$libresoc.v:179351$10847 + attribute \src "libresoc.v:179099.3-179128.6" + process $proc$libresoc.v:179099$10841 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10848 $1\wr_detect$10[0:0]$10849 - attribute \src "libresoc.v:179352.5-179352.29" + assign $0\wr_detect$10[0:0]$10842 $1\wr_detect$10[0:0]$10843 + attribute \src "libresoc.v:179100.5-179100.29" switch \initial - attribute \src "libresoc.v:179352.9-179352.17" + attribute \src "libresoc.v:179100.9-179100.17" case 1'1 case end @@ -333274,49 +332980,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10849 $4\wr_detect$10[0:0]$10852 + assign $1\wr_detect$10[0:0]$10843 $4\wr_detect$10[0:0]$10846 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10850 1'1 + assign $2\wr_detect$10[0:0]$10844 1'1 case - assign $2\wr_detect$10[0:0]$10850 1'0 + assign $2\wr_detect$10[0:0]$10844 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10851 1'1 + assign $3\wr_detect$10[0:0]$10845 1'1 case - assign $3\wr_detect$10[0:0]$10851 $2\wr_detect$10[0:0]$10850 + assign $3\wr_detect$10[0:0]$10845 $2\wr_detect$10[0:0]$10844 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10852 1'1 + assign $4\wr_detect$10[0:0]$10846 1'1 case - assign $4\wr_detect$10[0:0]$10852 $3\wr_detect$10[0:0]$10851 + assign $4\wr_detect$10[0:0]$10846 $3\wr_detect$10[0:0]$10845 end case - assign $1\wr_detect$10[0:0]$10849 1'0 + assign $1\wr_detect$10[0:0]$10843 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10848 + update \wr_detect$10 $0\wr_detect$10[0:0]$10842 end - attribute \src "libresoc.v:179381.3-179420.6" - process $proc$libresoc.v:179381$10853 + attribute \src "libresoc.v:179129.3-179168.6" + process $proc$libresoc.v:179129$10847 assign { } { } assign { } { } assign { } { } - assign $0\r21__data_o$next[3:0]$10854 $6\r21__data_o$next[3:0]$10860 - attribute \src "libresoc.v:179382.5-179382.29" + assign $0\r21__data_o$next[3:0]$10848 $6\r21__data_o$next[3:0]$10854 + attribute \src "libresoc.v:179130.5-179130.29" switch \initial - attribute \src "libresoc.v:179382.9-179382.17" + attribute \src "libresoc.v:179130.9-179130.17" case 1'1 case end @@ -333328,66 +333034,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r21__data_o$next[3:0]$10855 $5\r21__data_o$next[3:0]$10859 + assign $1\r21__data_o$next[3:0]$10849 $5\r21__data_o$next[3:0]$10853 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r21__data_o$next[3:0]$10856 \dest11__data_i + assign $2\r21__data_o$next[3:0]$10850 \dest11__data_i case - assign $2\r21__data_o$next[3:0]$10856 4'0000 + assign $2\r21__data_o$next[3:0]$10850 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r21__data_o$next[3:0]$10857 \dest21__data_i + assign $3\r21__data_o$next[3:0]$10851 \dest21__data_i case - assign $3\r21__data_o$next[3:0]$10857 $2\r21__data_o$next[3:0]$10856 + assign $3\r21__data_o$next[3:0]$10851 $2\r21__data_o$next[3:0]$10850 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r21__data_o$next[3:0]$10858 \w1__data_i + assign $4\r21__data_o$next[3:0]$10852 \w1__data_i case - assign $4\r21__data_o$next[3:0]$10858 $3\r21__data_o$next[3:0]$10857 + assign $4\r21__data_o$next[3:0]$10852 $3\r21__data_o$next[3:0]$10851 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r21__data_o$next[3:0]$10859 \reg + assign $5\r21__data_o$next[3:0]$10853 \reg case - assign $5\r21__data_o$next[3:0]$10859 $4\r21__data_o$next[3:0]$10858 + assign $5\r21__data_o$next[3:0]$10853 $4\r21__data_o$next[3:0]$10852 end case - assign $1\r21__data_o$next[3:0]$10855 4'0000 + assign $1\r21__data_o$next[3:0]$10849 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r21__data_o$next[3:0]$10860 4'0000 + assign $6\r21__data_o$next[3:0]$10854 4'0000 case - assign $6\r21__data_o$next[3:0]$10860 $1\r21__data_o$next[3:0]$10855 + assign $6\r21__data_o$next[3:0]$10854 $1\r21__data_o$next[3:0]$10849 end sync always - update \r21__data_o$next $0\r21__data_o$next[3:0]$10854 + update \r21__data_o$next $0\r21__data_o$next[3:0]$10848 end - attribute \src "libresoc.v:179421.3-179450.6" - process $proc$libresoc.v:179421$10861 + attribute \src "libresoc.v:179169.3-179198.6" + process $proc$libresoc.v:179169$10855 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10862 $1\wr_detect$13[0:0]$10863 - attribute \src "libresoc.v:179422.5-179422.29" + assign $0\wr_detect$13[0:0]$10856 $1\wr_detect$13[0:0]$10857 + attribute \src "libresoc.v:179170.5-179170.29" switch \initial - attribute \src "libresoc.v:179422.9-179422.17" + attribute \src "libresoc.v:179170.9-179170.17" case 1'1 case end @@ -333399,205 +333105,205 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10863 $4\wr_detect$13[0:0]$10866 + assign $1\wr_detect$13[0:0]$10857 $4\wr_detect$13[0:0]$10860 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10864 1'1 + assign $2\wr_detect$13[0:0]$10858 1'1 case - assign $2\wr_detect$13[0:0]$10864 1'0 + assign $2\wr_detect$13[0:0]$10858 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10865 1'1 + assign $3\wr_detect$13[0:0]$10859 1'1 case - assign $3\wr_detect$13[0:0]$10865 $2\wr_detect$13[0:0]$10864 + assign $3\wr_detect$13[0:0]$10859 $2\wr_detect$13[0:0]$10858 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10866 1'1 + assign $4\wr_detect$13[0:0]$10860 1'1 case - assign $4\wr_detect$13[0:0]$10866 $3\wr_detect$13[0:0]$10865 + assign $4\wr_detect$13[0:0]$10860 $3\wr_detect$13[0:0]$10859 end case - assign $1\wr_detect$13[0:0]$10863 1'0 + assign $1\wr_detect$13[0:0]$10857 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10862 + update \wr_detect$13 $0\wr_detect$13[0:0]$10856 end - connect \$9 $not$libresoc.v:179057$10785_Y - connect \$12 $not$libresoc.v:179058$10786_Y - connect \$1 $not$libresoc.v:179059$10787_Y - connect \$3 $not$libresoc.v:179060$10788_Y - connect \$6 $not$libresoc.v:179061$10789_Y + connect \$9 $not$libresoc.v:178805$10779_Y + connect \$12 $not$libresoc.v:178806$10780_Y + connect \$1 $not$libresoc.v:178807$10781_Y + connect \$3 $not$libresoc.v:178808$10782_Y + connect \$6 $not$libresoc.v:178809$10783_Y end -attribute \src "libresoc.v:179455.1-179900.10" +attribute \src "libresoc.v:179203.1-179648.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" attribute \generator "nMigen" module \reg_1$133 - attribute \src "libresoc.v:179456.7-179456.20" + attribute \src "libresoc.v:179204.7-179204.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179785.3-179830.6" - wire width 2 $0\r1__data_o$next[1:0]$10926 - attribute \src "libresoc.v:179531.3-179532.37" + attribute \src "libresoc.v:179533.3-179578.6" + wire width 2 $0\r1__data_o$next[1:0]$10920 + attribute \src "libresoc.v:179279.3-179280.37" wire width 2 $0\r1__data_o[1:0] - attribute \src "libresoc.v:179867.3-179899.6" - wire width 2 $0\reg$next[1:0]$10942 - attribute \src "libresoc.v:179529.3-179530.25" + attribute \src "libresoc.v:179615.3-179647.6" + wire width 2 $0\reg$next[1:0]$10936 + attribute \src "libresoc.v:179277.3-179278.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:179539.3-179584.6" - wire width 2 $0\src11__data_o$next[1:0]$10884 - attribute \src "libresoc.v:179537.3-179538.43" + attribute \src "libresoc.v:179287.3-179332.6" + wire width 2 $0\src11__data_o$next[1:0]$10878 + attribute \src "libresoc.v:179285.3-179286.43" wire width 2 $0\src11__data_o[1:0] - attribute \src "libresoc.v:179621.3-179666.6" - wire width 2 $0\src21__data_o$next[1:0]$10894 - attribute \src "libresoc.v:179535.3-179536.43" + attribute \src "libresoc.v:179369.3-179414.6" + wire width 2 $0\src21__data_o$next[1:0]$10888 + attribute \src "libresoc.v:179283.3-179284.43" wire width 2 $0\src21__data_o[1:0] - attribute \src "libresoc.v:179703.3-179748.6" - wire width 2 $0\src31__data_o$next[1:0]$10910 - attribute \src "libresoc.v:179533.3-179534.43" + attribute \src "libresoc.v:179451.3-179496.6" + wire width 2 $0\src31__data_o$next[1:0]$10904 + attribute \src "libresoc.v:179281.3-179282.43" wire width 2 $0\src31__data_o[1:0] - attribute \src "libresoc.v:179831.3-179866.6" - wire $0\wr_detect$10[0:0]$10935 - attribute \src "libresoc.v:179667.3-179702.6" - wire $0\wr_detect$4[0:0]$10903 - attribute \src "libresoc.v:179749.3-179784.6" - wire $0\wr_detect$7[0:0]$10919 - attribute \src "libresoc.v:179585.3-179620.6" + attribute \src "libresoc.v:179579.3-179614.6" + wire $0\wr_detect$10[0:0]$10929 + attribute \src "libresoc.v:179415.3-179450.6" + wire $0\wr_detect$4[0:0]$10897 + attribute \src "libresoc.v:179497.3-179532.6" + wire $0\wr_detect$7[0:0]$10913 + attribute \src "libresoc.v:179333.3-179368.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179785.3-179830.6" - wire width 2 $1\r1__data_o$next[1:0]$10927 - attribute \src "libresoc.v:179483.13-179483.30" + attribute \src "libresoc.v:179533.3-179578.6" + wire width 2 $1\r1__data_o$next[1:0]$10921 + attribute \src "libresoc.v:179231.13-179231.30" wire width 2 $1\r1__data_o[1:0] - attribute \src "libresoc.v:179867.3-179899.6" - wire width 2 $1\reg$next[1:0]$10943 - attribute \src "libresoc.v:179489.13-179489.25" + attribute \src "libresoc.v:179615.3-179647.6" + wire width 2 $1\reg$next[1:0]$10937 + attribute \src "libresoc.v:179237.13-179237.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:179539.3-179584.6" - wire width 2 $1\src11__data_o$next[1:0]$10885 - attribute \src "libresoc.v:179494.13-179494.33" + attribute \src "libresoc.v:179287.3-179332.6" + wire width 2 $1\src11__data_o$next[1:0]$10879 + attribute \src "libresoc.v:179242.13-179242.33" wire width 2 $1\src11__data_o[1:0] - attribute \src "libresoc.v:179621.3-179666.6" - wire width 2 $1\src21__data_o$next[1:0]$10895 - attribute \src "libresoc.v:179501.13-179501.33" + attribute \src "libresoc.v:179369.3-179414.6" + wire width 2 $1\src21__data_o$next[1:0]$10889 + attribute \src "libresoc.v:179249.13-179249.33" wire width 2 $1\src21__data_o[1:0] - attribute \src "libresoc.v:179703.3-179748.6" - wire width 2 $1\src31__data_o$next[1:0]$10911 - attribute \src "libresoc.v:179508.13-179508.33" + attribute \src "libresoc.v:179451.3-179496.6" + wire width 2 $1\src31__data_o$next[1:0]$10905 + attribute \src "libresoc.v:179256.13-179256.33" wire width 2 $1\src31__data_o[1:0] - attribute \src "libresoc.v:179831.3-179866.6" - wire $1\wr_detect$10[0:0]$10936 - attribute \src "libresoc.v:179667.3-179702.6" - wire $1\wr_detect$4[0:0]$10904 - attribute \src "libresoc.v:179749.3-179784.6" - wire $1\wr_detect$7[0:0]$10920 - attribute \src "libresoc.v:179585.3-179620.6" + attribute \src "libresoc.v:179579.3-179614.6" + wire $1\wr_detect$10[0:0]$10930 + attribute \src "libresoc.v:179415.3-179450.6" + wire $1\wr_detect$4[0:0]$10898 + attribute \src "libresoc.v:179497.3-179532.6" + wire $1\wr_detect$7[0:0]$10914 + attribute \src "libresoc.v:179333.3-179368.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179785.3-179830.6" - wire width 2 $2\r1__data_o$next[1:0]$10928 - attribute \src "libresoc.v:179867.3-179899.6" - wire width 2 $2\reg$next[1:0]$10944 - attribute \src "libresoc.v:179539.3-179584.6" - wire width 2 $2\src11__data_o$next[1:0]$10886 - attribute \src "libresoc.v:179621.3-179666.6" - wire width 2 $2\src21__data_o$next[1:0]$10896 - attribute \src "libresoc.v:179703.3-179748.6" - wire width 2 $2\src31__data_o$next[1:0]$10912 - attribute \src "libresoc.v:179831.3-179866.6" - wire $2\wr_detect$10[0:0]$10937 - attribute \src "libresoc.v:179667.3-179702.6" - wire $2\wr_detect$4[0:0]$10905 - attribute \src "libresoc.v:179749.3-179784.6" - wire $2\wr_detect$7[0:0]$10921 - attribute \src "libresoc.v:179585.3-179620.6" + attribute \src "libresoc.v:179533.3-179578.6" + wire width 2 $2\r1__data_o$next[1:0]$10922 + attribute \src "libresoc.v:179615.3-179647.6" + wire width 2 $2\reg$next[1:0]$10938 + attribute \src "libresoc.v:179287.3-179332.6" + wire width 2 $2\src11__data_o$next[1:0]$10880 + attribute \src "libresoc.v:179369.3-179414.6" + wire width 2 $2\src21__data_o$next[1:0]$10890 + attribute \src "libresoc.v:179451.3-179496.6" + wire width 2 $2\src31__data_o$next[1:0]$10906 + attribute \src "libresoc.v:179579.3-179614.6" + wire $2\wr_detect$10[0:0]$10931 + attribute \src "libresoc.v:179415.3-179450.6" + wire $2\wr_detect$4[0:0]$10899 + attribute \src "libresoc.v:179497.3-179532.6" + wire $2\wr_detect$7[0:0]$10915 + attribute \src "libresoc.v:179333.3-179368.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179785.3-179830.6" - wire width 2 $3\r1__data_o$next[1:0]$10929 - attribute \src "libresoc.v:179867.3-179899.6" - wire width 2 $3\reg$next[1:0]$10945 - attribute \src "libresoc.v:179539.3-179584.6" - wire width 2 $3\src11__data_o$next[1:0]$10887 - attribute \src "libresoc.v:179621.3-179666.6" - wire width 2 $3\src21__data_o$next[1:0]$10897 - attribute \src "libresoc.v:179703.3-179748.6" - wire width 2 $3\src31__data_o$next[1:0]$10913 - attribute \src "libresoc.v:179831.3-179866.6" - wire $3\wr_detect$10[0:0]$10938 - attribute \src "libresoc.v:179667.3-179702.6" - wire $3\wr_detect$4[0:0]$10906 - attribute \src "libresoc.v:179749.3-179784.6" - wire $3\wr_detect$7[0:0]$10922 - attribute \src "libresoc.v:179585.3-179620.6" + attribute \src "libresoc.v:179533.3-179578.6" + wire width 2 $3\r1__data_o$next[1:0]$10923 + attribute \src "libresoc.v:179615.3-179647.6" + wire width 2 $3\reg$next[1:0]$10939 + attribute \src "libresoc.v:179287.3-179332.6" + wire width 2 $3\src11__data_o$next[1:0]$10881 + attribute \src "libresoc.v:179369.3-179414.6" + wire width 2 $3\src21__data_o$next[1:0]$10891 + attribute \src "libresoc.v:179451.3-179496.6" + wire width 2 $3\src31__data_o$next[1:0]$10907 + attribute \src "libresoc.v:179579.3-179614.6" + wire $3\wr_detect$10[0:0]$10932 + attribute \src "libresoc.v:179415.3-179450.6" + wire $3\wr_detect$4[0:0]$10900 + attribute \src "libresoc.v:179497.3-179532.6" + wire $3\wr_detect$7[0:0]$10916 + attribute \src "libresoc.v:179333.3-179368.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179785.3-179830.6" - wire width 2 $4\r1__data_o$next[1:0]$10930 - attribute \src "libresoc.v:179867.3-179899.6" - wire width 2 $4\reg$next[1:0]$10946 - attribute \src "libresoc.v:179539.3-179584.6" - wire width 2 $4\src11__data_o$next[1:0]$10888 - attribute \src "libresoc.v:179621.3-179666.6" - wire width 2 $4\src21__data_o$next[1:0]$10898 - attribute \src "libresoc.v:179703.3-179748.6" - wire width 2 $4\src31__data_o$next[1:0]$10914 - attribute \src "libresoc.v:179831.3-179866.6" - wire $4\wr_detect$10[0:0]$10939 - attribute \src "libresoc.v:179667.3-179702.6" - wire $4\wr_detect$4[0:0]$10907 - attribute \src "libresoc.v:179749.3-179784.6" - wire $4\wr_detect$7[0:0]$10923 - attribute \src "libresoc.v:179585.3-179620.6" + attribute \src "libresoc.v:179533.3-179578.6" + wire width 2 $4\r1__data_o$next[1:0]$10924 + attribute \src "libresoc.v:179615.3-179647.6" + wire width 2 $4\reg$next[1:0]$10940 + attribute \src "libresoc.v:179287.3-179332.6" + wire width 2 $4\src11__data_o$next[1:0]$10882 + attribute \src "libresoc.v:179369.3-179414.6" + wire width 2 $4\src21__data_o$next[1:0]$10892 + attribute \src "libresoc.v:179451.3-179496.6" + wire width 2 $4\src31__data_o$next[1:0]$10908 + attribute \src "libresoc.v:179579.3-179614.6" + wire $4\wr_detect$10[0:0]$10933 + attribute \src "libresoc.v:179415.3-179450.6" + wire $4\wr_detect$4[0:0]$10901 + attribute \src "libresoc.v:179497.3-179532.6" + wire $4\wr_detect$7[0:0]$10917 + attribute \src "libresoc.v:179333.3-179368.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179785.3-179830.6" - wire width 2 $5\r1__data_o$next[1:0]$10931 - attribute \src "libresoc.v:179867.3-179899.6" - wire width 2 $5\reg$next[1:0]$10947 - attribute \src "libresoc.v:179539.3-179584.6" - wire width 2 $5\src11__data_o$next[1:0]$10889 - attribute \src "libresoc.v:179621.3-179666.6" - wire width 2 $5\src21__data_o$next[1:0]$10899 - attribute \src "libresoc.v:179703.3-179748.6" - wire width 2 $5\src31__data_o$next[1:0]$10915 - attribute \src "libresoc.v:179831.3-179866.6" - wire $5\wr_detect$10[0:0]$10940 - attribute \src "libresoc.v:179667.3-179702.6" - wire $5\wr_detect$4[0:0]$10908 - attribute \src "libresoc.v:179749.3-179784.6" - wire $5\wr_detect$7[0:0]$10924 - attribute \src "libresoc.v:179585.3-179620.6" + attribute \src "libresoc.v:179533.3-179578.6" + wire width 2 $5\r1__data_o$next[1:0]$10925 + attribute \src "libresoc.v:179615.3-179647.6" + wire width 2 $5\reg$next[1:0]$10941 + attribute \src "libresoc.v:179287.3-179332.6" + wire width 2 $5\src11__data_o$next[1:0]$10883 + attribute \src "libresoc.v:179369.3-179414.6" + wire width 2 $5\src21__data_o$next[1:0]$10893 + attribute \src "libresoc.v:179451.3-179496.6" + wire width 2 $5\src31__data_o$next[1:0]$10909 + attribute \src "libresoc.v:179579.3-179614.6" + wire $5\wr_detect$10[0:0]$10934 + attribute \src "libresoc.v:179415.3-179450.6" + wire $5\wr_detect$4[0:0]$10902 + attribute \src "libresoc.v:179497.3-179532.6" + wire $5\wr_detect$7[0:0]$10918 + attribute \src "libresoc.v:179333.3-179368.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:179785.3-179830.6" - wire width 2 $6\r1__data_o$next[1:0]$10932 - attribute \src "libresoc.v:179539.3-179584.6" - wire width 2 $6\src11__data_o$next[1:0]$10890 - attribute \src "libresoc.v:179621.3-179666.6" - wire width 2 $6\src21__data_o$next[1:0]$10900 - attribute \src "libresoc.v:179703.3-179748.6" - wire width 2 $6\src31__data_o$next[1:0]$10916 - attribute \src "libresoc.v:179785.3-179830.6" - wire width 2 $7\r1__data_o$next[1:0]$10933 - attribute \src "libresoc.v:179539.3-179584.6" - wire width 2 $7\src11__data_o$next[1:0]$10891 - attribute \src "libresoc.v:179621.3-179666.6" - wire width 2 $7\src21__data_o$next[1:0]$10901 - attribute \src "libresoc.v:179703.3-179748.6" - wire width 2 $7\src31__data_o$next[1:0]$10917 - attribute \src "libresoc.v:179525.17-179525.104" - wire $not$libresoc.v:179525$10874_Y - attribute \src "libresoc.v:179526.17-179526.100" - wire $not$libresoc.v:179526$10875_Y - attribute \src "libresoc.v:179527.17-179527.103" - wire $not$libresoc.v:179527$10876_Y - attribute \src "libresoc.v:179528.17-179528.103" - wire $not$libresoc.v:179528$10877_Y + attribute \src "libresoc.v:179533.3-179578.6" + wire width 2 $6\r1__data_o$next[1:0]$10926 + attribute \src "libresoc.v:179287.3-179332.6" + wire width 2 $6\src11__data_o$next[1:0]$10884 + attribute \src "libresoc.v:179369.3-179414.6" + wire width 2 $6\src21__data_o$next[1:0]$10894 + attribute \src "libresoc.v:179451.3-179496.6" + wire width 2 $6\src31__data_o$next[1:0]$10910 + attribute \src "libresoc.v:179533.3-179578.6" + wire width 2 $7\r1__data_o$next[1:0]$10927 + attribute \src "libresoc.v:179287.3-179332.6" + wire width 2 $7\src11__data_o$next[1:0]$10885 + attribute \src "libresoc.v:179369.3-179414.6" + wire width 2 $7\src21__data_o$next[1:0]$10895 + attribute \src "libresoc.v:179451.3-179496.6" + wire width 2 $7\src31__data_o$next[1:0]$10911 + attribute \src "libresoc.v:179273.17-179273.104" + wire $not$libresoc.v:179273$10868_Y + attribute \src "libresoc.v:179274.17-179274.100" + wire $not$libresoc.v:179274$10869_Y + attribute \src "libresoc.v:179275.17-179275.103" + wire $not$libresoc.v:179275$10870_Y + attribute \src "libresoc.v:179276.17-179276.103" + wire $not$libresoc.v:179276$10871_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -333606,9 +333312,9 @@ module \reg_1$133 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest11__data_i @@ -333622,7 +333328,7 @@ module \reg_1$133 wire width 2 input 13 \dest31__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest31__wen - attribute \src "libresoc.v:179456.7-179456.15" + attribute \src "libresoc.v:179204.7-179204.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r1__data_o @@ -333665,129 +333371,129 @@ module \reg_1$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179525$10874 + cell $not $not$libresoc.v:179273$10868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:179525$10874_Y + connect \Y $not$libresoc.v:179273$10868_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179526$10875 + cell $not $not$libresoc.v:179274$10869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179526$10875_Y + connect \Y $not$libresoc.v:179274$10869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179527$10876 + cell $not $not$libresoc.v:179275$10870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179527$10876_Y + connect \Y $not$libresoc.v:179275$10870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179528$10877 + cell $not $not$libresoc.v:179276$10871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179528$10877_Y + connect \Y $not$libresoc.v:179276$10871_Y end - attribute \src "libresoc.v:179456.7-179456.20" - process $proc$libresoc.v:179456$10948 + attribute \src "libresoc.v:179204.7-179204.20" + process $proc$libresoc.v:179204$10942 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179483.13-179483.30" - process $proc$libresoc.v:179483$10949 + attribute \src "libresoc.v:179231.13-179231.30" + process $proc$libresoc.v:179231$10943 assign { } { } assign $1\r1__data_o[1:0] 2'00 sync always sync init update \r1__data_o $1\r1__data_o[1:0] end - attribute \src "libresoc.v:179489.13-179489.25" - process $proc$libresoc.v:179489$10950 + attribute \src "libresoc.v:179237.13-179237.25" + process $proc$libresoc.v:179237$10944 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:179494.13-179494.33" - process $proc$libresoc.v:179494$10951 + attribute \src "libresoc.v:179242.13-179242.33" + process $proc$libresoc.v:179242$10945 assign { } { } assign $1\src11__data_o[1:0] 2'00 sync always sync init update \src11__data_o $1\src11__data_o[1:0] end - attribute \src "libresoc.v:179501.13-179501.33" - process $proc$libresoc.v:179501$10952 + attribute \src "libresoc.v:179249.13-179249.33" + process $proc$libresoc.v:179249$10946 assign { } { } assign $1\src21__data_o[1:0] 2'00 sync always sync init update \src21__data_o $1\src21__data_o[1:0] end - attribute \src "libresoc.v:179508.13-179508.33" - process $proc$libresoc.v:179508$10953 + attribute \src "libresoc.v:179256.13-179256.33" + process $proc$libresoc.v:179256$10947 assign { } { } assign $1\src31__data_o[1:0] 2'00 sync always sync init update \src31__data_o $1\src31__data_o[1:0] end - attribute \src "libresoc.v:179529.3-179530.25" - process $proc$libresoc.v:179529$10878 + attribute \src "libresoc.v:179277.3-179278.25" + process $proc$libresoc.v:179277$10872 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:179531.3-179532.37" - process $proc$libresoc.v:179531$10879 + attribute \src "libresoc.v:179279.3-179280.37" + process $proc$libresoc.v:179279$10873 assign { } { } assign $0\r1__data_o[1:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[1:0] end - attribute \src "libresoc.v:179533.3-179534.43" - process $proc$libresoc.v:179533$10880 + attribute \src "libresoc.v:179281.3-179282.43" + process $proc$libresoc.v:179281$10874 assign { } { } assign $0\src31__data_o[1:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[1:0] end - attribute \src "libresoc.v:179535.3-179536.43" - process $proc$libresoc.v:179535$10881 + attribute \src "libresoc.v:179283.3-179284.43" + process $proc$libresoc.v:179283$10875 assign { } { } assign $0\src21__data_o[1:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[1:0] end - attribute \src "libresoc.v:179537.3-179538.43" - process $proc$libresoc.v:179537$10882 + attribute \src "libresoc.v:179285.3-179286.43" + process $proc$libresoc.v:179285$10876 assign { } { } assign $0\src11__data_o[1:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[1:0] end - attribute \src "libresoc.v:179539.3-179584.6" - process $proc$libresoc.v:179539$10883 + attribute \src "libresoc.v:179287.3-179332.6" + process $proc$libresoc.v:179287$10877 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[1:0]$10884 $7\src11__data_o$next[1:0]$10891 - attribute \src "libresoc.v:179540.5-179540.29" + assign $0\src11__data_o$next[1:0]$10878 $7\src11__data_o$next[1:0]$10885 + attribute \src "libresoc.v:179288.5-179288.29" switch \initial - attribute \src "libresoc.v:179540.9-179540.17" + attribute \src "libresoc.v:179288.9-179288.17" case 1'1 case end @@ -333800,75 +333506,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[1:0]$10885 $6\src11__data_o$next[1:0]$10890 + assign $1\src11__data_o$next[1:0]$10879 $6\src11__data_o$next[1:0]$10884 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[1:0]$10886 \dest11__data_i + assign $2\src11__data_o$next[1:0]$10880 \dest11__data_i case - assign $2\src11__data_o$next[1:0]$10886 2'00 + assign $2\src11__data_o$next[1:0]$10880 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[1:0]$10887 \dest21__data_i + assign $3\src11__data_o$next[1:0]$10881 \dest21__data_i case - assign $3\src11__data_o$next[1:0]$10887 $2\src11__data_o$next[1:0]$10886 + assign $3\src11__data_o$next[1:0]$10881 $2\src11__data_o$next[1:0]$10880 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[1:0]$10888 \dest31__data_i + assign $4\src11__data_o$next[1:0]$10882 \dest31__data_i case - assign $4\src11__data_o$next[1:0]$10888 $3\src11__data_o$next[1:0]$10887 + assign $4\src11__data_o$next[1:0]$10882 $3\src11__data_o$next[1:0]$10881 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[1:0]$10889 \w1__data_i + assign $5\src11__data_o$next[1:0]$10883 \w1__data_i case - assign $5\src11__data_o$next[1:0]$10889 $4\src11__data_o$next[1:0]$10888 + assign $5\src11__data_o$next[1:0]$10883 $4\src11__data_o$next[1:0]$10882 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[1:0]$10890 \reg + assign $6\src11__data_o$next[1:0]$10884 \reg case - assign $6\src11__data_o$next[1:0]$10890 $5\src11__data_o$next[1:0]$10889 + assign $6\src11__data_o$next[1:0]$10884 $5\src11__data_o$next[1:0]$10883 end case - assign $1\src11__data_o$next[1:0]$10885 2'00 + assign $1\src11__data_o$next[1:0]$10879 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src11__data_o$next[1:0]$10891 2'00 + assign $7\src11__data_o$next[1:0]$10885 2'00 case - assign $7\src11__data_o$next[1:0]$10891 $1\src11__data_o$next[1:0]$10885 + assign $7\src11__data_o$next[1:0]$10885 $1\src11__data_o$next[1:0]$10879 end sync always - update \src11__data_o$next $0\src11__data_o$next[1:0]$10884 + update \src11__data_o$next $0\src11__data_o$next[1:0]$10878 end - attribute \src "libresoc.v:179585.3-179620.6" - process $proc$libresoc.v:179585$10892 + attribute \src "libresoc.v:179333.3-179368.6" + process $proc$libresoc.v:179333$10886 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179586.5-179586.29" + attribute \src "libresoc.v:179334.5-179334.29" switch \initial - attribute \src "libresoc.v:179586.9-179586.17" + attribute \src "libresoc.v:179334.9-179334.17" case 1'1 case end @@ -333924,15 +333630,15 @@ module \reg_1$133 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179621.3-179666.6" - process $proc$libresoc.v:179621$10893 + attribute \src "libresoc.v:179369.3-179414.6" + process $proc$libresoc.v:179369$10887 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[1:0]$10894 $7\src21__data_o$next[1:0]$10901 - attribute \src "libresoc.v:179622.5-179622.29" + assign $0\src21__data_o$next[1:0]$10888 $7\src21__data_o$next[1:0]$10895 + attribute \src "libresoc.v:179370.5-179370.29" switch \initial - attribute \src "libresoc.v:179622.9-179622.17" + attribute \src "libresoc.v:179370.9-179370.17" case 1'1 case end @@ -333945,75 +333651,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[1:0]$10895 $6\src21__data_o$next[1:0]$10900 + assign $1\src21__data_o$next[1:0]$10889 $6\src21__data_o$next[1:0]$10894 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[1:0]$10896 \dest11__data_i + assign $2\src21__data_o$next[1:0]$10890 \dest11__data_i case - assign $2\src21__data_o$next[1:0]$10896 2'00 + assign $2\src21__data_o$next[1:0]$10890 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[1:0]$10897 \dest21__data_i + assign $3\src21__data_o$next[1:0]$10891 \dest21__data_i case - assign $3\src21__data_o$next[1:0]$10897 $2\src21__data_o$next[1:0]$10896 + assign $3\src21__data_o$next[1:0]$10891 $2\src21__data_o$next[1:0]$10890 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[1:0]$10898 \dest31__data_i + assign $4\src21__data_o$next[1:0]$10892 \dest31__data_i case - assign $4\src21__data_o$next[1:0]$10898 $3\src21__data_o$next[1:0]$10897 + assign $4\src21__data_o$next[1:0]$10892 $3\src21__data_o$next[1:0]$10891 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[1:0]$10899 \w1__data_i + assign $5\src21__data_o$next[1:0]$10893 \w1__data_i case - assign $5\src21__data_o$next[1:0]$10899 $4\src21__data_o$next[1:0]$10898 + assign $5\src21__data_o$next[1:0]$10893 $4\src21__data_o$next[1:0]$10892 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[1:0]$10900 \reg + assign $6\src21__data_o$next[1:0]$10894 \reg case - assign $6\src21__data_o$next[1:0]$10900 $5\src21__data_o$next[1:0]$10899 + assign $6\src21__data_o$next[1:0]$10894 $5\src21__data_o$next[1:0]$10893 end case - assign $1\src21__data_o$next[1:0]$10895 2'00 + assign $1\src21__data_o$next[1:0]$10889 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src21__data_o$next[1:0]$10901 2'00 + assign $7\src21__data_o$next[1:0]$10895 2'00 case - assign $7\src21__data_o$next[1:0]$10901 $1\src21__data_o$next[1:0]$10895 + assign $7\src21__data_o$next[1:0]$10895 $1\src21__data_o$next[1:0]$10889 end sync always - update \src21__data_o$next $0\src21__data_o$next[1:0]$10894 + update \src21__data_o$next $0\src21__data_o$next[1:0]$10888 end - attribute \src "libresoc.v:179667.3-179702.6" - process $proc$libresoc.v:179667$10902 + attribute \src "libresoc.v:179415.3-179450.6" + process $proc$libresoc.v:179415$10896 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10903 $1\wr_detect$4[0:0]$10904 - attribute \src "libresoc.v:179668.5-179668.29" + assign $0\wr_detect$4[0:0]$10897 $1\wr_detect$4[0:0]$10898 + attribute \src "libresoc.v:179416.5-179416.29" switch \initial - attribute \src "libresoc.v:179668.9-179668.17" + attribute \src "libresoc.v:179416.9-179416.17" case 1'1 case end @@ -334026,58 +333732,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10904 $5\wr_detect$4[0:0]$10908 + assign $1\wr_detect$4[0:0]$10898 $5\wr_detect$4[0:0]$10902 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10905 1'1 + assign $2\wr_detect$4[0:0]$10899 1'1 case - assign $2\wr_detect$4[0:0]$10905 1'0 + assign $2\wr_detect$4[0:0]$10899 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10906 1'1 + assign $3\wr_detect$4[0:0]$10900 1'1 case - assign $3\wr_detect$4[0:0]$10906 $2\wr_detect$4[0:0]$10905 + assign $3\wr_detect$4[0:0]$10900 $2\wr_detect$4[0:0]$10899 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10907 1'1 + assign $4\wr_detect$4[0:0]$10901 1'1 case - assign $4\wr_detect$4[0:0]$10907 $3\wr_detect$4[0:0]$10906 + assign $4\wr_detect$4[0:0]$10901 $3\wr_detect$4[0:0]$10900 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10908 1'1 + assign $5\wr_detect$4[0:0]$10902 1'1 case - assign $5\wr_detect$4[0:0]$10908 $4\wr_detect$4[0:0]$10907 + assign $5\wr_detect$4[0:0]$10902 $4\wr_detect$4[0:0]$10901 end case - assign $1\wr_detect$4[0:0]$10904 1'0 + assign $1\wr_detect$4[0:0]$10898 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10903 + update \wr_detect$4 $0\wr_detect$4[0:0]$10897 end - attribute \src "libresoc.v:179703.3-179748.6" - process $proc$libresoc.v:179703$10909 + attribute \src "libresoc.v:179451.3-179496.6" + process $proc$libresoc.v:179451$10903 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[1:0]$10910 $7\src31__data_o$next[1:0]$10917 - attribute \src "libresoc.v:179704.5-179704.29" + assign $0\src31__data_o$next[1:0]$10904 $7\src31__data_o$next[1:0]$10911 + attribute \src "libresoc.v:179452.5-179452.29" switch \initial - attribute \src "libresoc.v:179704.9-179704.17" + attribute \src "libresoc.v:179452.9-179452.17" case 1'1 case end @@ -334090,75 +333796,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[1:0]$10911 $6\src31__data_o$next[1:0]$10916 + assign $1\src31__data_o$next[1:0]$10905 $6\src31__data_o$next[1:0]$10910 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[1:0]$10912 \dest11__data_i + assign $2\src31__data_o$next[1:0]$10906 \dest11__data_i case - assign $2\src31__data_o$next[1:0]$10912 2'00 + assign $2\src31__data_o$next[1:0]$10906 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[1:0]$10913 \dest21__data_i + assign $3\src31__data_o$next[1:0]$10907 \dest21__data_i case - assign $3\src31__data_o$next[1:0]$10913 $2\src31__data_o$next[1:0]$10912 + assign $3\src31__data_o$next[1:0]$10907 $2\src31__data_o$next[1:0]$10906 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[1:0]$10914 \dest31__data_i + assign $4\src31__data_o$next[1:0]$10908 \dest31__data_i case - assign $4\src31__data_o$next[1:0]$10914 $3\src31__data_o$next[1:0]$10913 + assign $4\src31__data_o$next[1:0]$10908 $3\src31__data_o$next[1:0]$10907 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[1:0]$10915 \w1__data_i + assign $5\src31__data_o$next[1:0]$10909 \w1__data_i case - assign $5\src31__data_o$next[1:0]$10915 $4\src31__data_o$next[1:0]$10914 + assign $5\src31__data_o$next[1:0]$10909 $4\src31__data_o$next[1:0]$10908 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[1:0]$10916 \reg + assign $6\src31__data_o$next[1:0]$10910 \reg case - assign $6\src31__data_o$next[1:0]$10916 $5\src31__data_o$next[1:0]$10915 + assign $6\src31__data_o$next[1:0]$10910 $5\src31__data_o$next[1:0]$10909 end case - assign $1\src31__data_o$next[1:0]$10911 2'00 + assign $1\src31__data_o$next[1:0]$10905 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src31__data_o$next[1:0]$10917 2'00 + assign $7\src31__data_o$next[1:0]$10911 2'00 case - assign $7\src31__data_o$next[1:0]$10917 $1\src31__data_o$next[1:0]$10911 + assign $7\src31__data_o$next[1:0]$10911 $1\src31__data_o$next[1:0]$10905 end sync always - update \src31__data_o$next $0\src31__data_o$next[1:0]$10910 + update \src31__data_o$next $0\src31__data_o$next[1:0]$10904 end - attribute \src "libresoc.v:179749.3-179784.6" - process $proc$libresoc.v:179749$10918 + attribute \src "libresoc.v:179497.3-179532.6" + process $proc$libresoc.v:179497$10912 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10919 $1\wr_detect$7[0:0]$10920 - attribute \src "libresoc.v:179750.5-179750.29" + assign $0\wr_detect$7[0:0]$10913 $1\wr_detect$7[0:0]$10914 + attribute \src "libresoc.v:179498.5-179498.29" switch \initial - attribute \src "libresoc.v:179750.9-179750.17" + attribute \src "libresoc.v:179498.9-179498.17" case 1'1 case end @@ -334171,58 +333877,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10920 $5\wr_detect$7[0:0]$10924 + assign $1\wr_detect$7[0:0]$10914 $5\wr_detect$7[0:0]$10918 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10921 1'1 + assign $2\wr_detect$7[0:0]$10915 1'1 case - assign $2\wr_detect$7[0:0]$10921 1'0 + assign $2\wr_detect$7[0:0]$10915 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10922 1'1 + assign $3\wr_detect$7[0:0]$10916 1'1 case - assign $3\wr_detect$7[0:0]$10922 $2\wr_detect$7[0:0]$10921 + assign $3\wr_detect$7[0:0]$10916 $2\wr_detect$7[0:0]$10915 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10923 1'1 + assign $4\wr_detect$7[0:0]$10917 1'1 case - assign $4\wr_detect$7[0:0]$10923 $3\wr_detect$7[0:0]$10922 + assign $4\wr_detect$7[0:0]$10917 $3\wr_detect$7[0:0]$10916 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10924 1'1 + assign $5\wr_detect$7[0:0]$10918 1'1 case - assign $5\wr_detect$7[0:0]$10924 $4\wr_detect$7[0:0]$10923 + assign $5\wr_detect$7[0:0]$10918 $4\wr_detect$7[0:0]$10917 end case - assign $1\wr_detect$7[0:0]$10920 1'0 + assign $1\wr_detect$7[0:0]$10914 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10919 + update \wr_detect$7 $0\wr_detect$7[0:0]$10913 end - attribute \src "libresoc.v:179785.3-179830.6" - process $proc$libresoc.v:179785$10925 + attribute \src "libresoc.v:179533.3-179578.6" + process $proc$libresoc.v:179533$10919 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[1:0]$10926 $7\r1__data_o$next[1:0]$10933 - attribute \src "libresoc.v:179786.5-179786.29" + assign $0\r1__data_o$next[1:0]$10920 $7\r1__data_o$next[1:0]$10927 + attribute \src "libresoc.v:179534.5-179534.29" switch \initial - attribute \src "libresoc.v:179786.9-179786.17" + attribute \src "libresoc.v:179534.9-179534.17" case 1'1 case end @@ -334235,75 +333941,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[1:0]$10927 $6\r1__data_o$next[1:0]$10932 + assign $1\r1__data_o$next[1:0]$10921 $6\r1__data_o$next[1:0]$10926 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[1:0]$10928 \dest11__data_i + assign $2\r1__data_o$next[1:0]$10922 \dest11__data_i case - assign $2\r1__data_o$next[1:0]$10928 2'00 + assign $2\r1__data_o$next[1:0]$10922 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[1:0]$10929 \dest21__data_i + assign $3\r1__data_o$next[1:0]$10923 \dest21__data_i case - assign $3\r1__data_o$next[1:0]$10929 $2\r1__data_o$next[1:0]$10928 + assign $3\r1__data_o$next[1:0]$10923 $2\r1__data_o$next[1:0]$10922 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[1:0]$10930 \dest31__data_i + assign $4\r1__data_o$next[1:0]$10924 \dest31__data_i case - assign $4\r1__data_o$next[1:0]$10930 $3\r1__data_o$next[1:0]$10929 + assign $4\r1__data_o$next[1:0]$10924 $3\r1__data_o$next[1:0]$10923 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[1:0]$10931 \w1__data_i + assign $5\r1__data_o$next[1:0]$10925 \w1__data_i case - assign $5\r1__data_o$next[1:0]$10931 $4\r1__data_o$next[1:0]$10930 + assign $5\r1__data_o$next[1:0]$10925 $4\r1__data_o$next[1:0]$10924 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[1:0]$10932 \reg + assign $6\r1__data_o$next[1:0]$10926 \reg case - assign $6\r1__data_o$next[1:0]$10932 $5\r1__data_o$next[1:0]$10931 + assign $6\r1__data_o$next[1:0]$10926 $5\r1__data_o$next[1:0]$10925 end case - assign $1\r1__data_o$next[1:0]$10927 2'00 + assign $1\r1__data_o$next[1:0]$10921 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r1__data_o$next[1:0]$10933 2'00 + assign $7\r1__data_o$next[1:0]$10927 2'00 case - assign $7\r1__data_o$next[1:0]$10933 $1\r1__data_o$next[1:0]$10927 + assign $7\r1__data_o$next[1:0]$10927 $1\r1__data_o$next[1:0]$10921 end sync always - update \r1__data_o$next $0\r1__data_o$next[1:0]$10926 + update \r1__data_o$next $0\r1__data_o$next[1:0]$10920 end - attribute \src "libresoc.v:179831.3-179866.6" - process $proc$libresoc.v:179831$10934 + attribute \src "libresoc.v:179579.3-179614.6" + process $proc$libresoc.v:179579$10928 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10935 $1\wr_detect$10[0:0]$10936 - attribute \src "libresoc.v:179832.5-179832.29" + assign $0\wr_detect$10[0:0]$10929 $1\wr_detect$10[0:0]$10930 + attribute \src "libresoc.v:179580.5-179580.29" switch \initial - attribute \src "libresoc.v:179832.9-179832.17" + attribute \src "libresoc.v:179580.9-179580.17" case 1'1 case end @@ -334316,61 +334022,61 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10936 $5\wr_detect$10[0:0]$10940 + assign $1\wr_detect$10[0:0]$10930 $5\wr_detect$10[0:0]$10934 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10937 1'1 + assign $2\wr_detect$10[0:0]$10931 1'1 case - assign $2\wr_detect$10[0:0]$10937 1'0 + assign $2\wr_detect$10[0:0]$10931 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10938 1'1 + assign $3\wr_detect$10[0:0]$10932 1'1 case - assign $3\wr_detect$10[0:0]$10938 $2\wr_detect$10[0:0]$10937 + assign $3\wr_detect$10[0:0]$10932 $2\wr_detect$10[0:0]$10931 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10939 1'1 + assign $4\wr_detect$10[0:0]$10933 1'1 case - assign $4\wr_detect$10[0:0]$10939 $3\wr_detect$10[0:0]$10938 + assign $4\wr_detect$10[0:0]$10933 $3\wr_detect$10[0:0]$10932 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10940 1'1 + assign $5\wr_detect$10[0:0]$10934 1'1 case - assign $5\wr_detect$10[0:0]$10940 $4\wr_detect$10[0:0]$10939 + assign $5\wr_detect$10[0:0]$10934 $4\wr_detect$10[0:0]$10933 end case - assign $1\wr_detect$10[0:0]$10936 1'0 + assign $1\wr_detect$10[0:0]$10930 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10935 + update \wr_detect$10 $0\wr_detect$10[0:0]$10929 end - attribute \src "libresoc.v:179867.3-179899.6" - process $proc$libresoc.v:179867$10941 + attribute \src "libresoc.v:179615.3-179647.6" + process $proc$libresoc.v:179615$10935 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10942 $5\reg$next[1:0]$10947 - attribute \src "libresoc.v:179868.5-179868.29" + assign $0\reg$next[1:0]$10936 $5\reg$next[1:0]$10941 + attribute \src "libresoc.v:179616.5-179616.29" switch \initial - attribute \src "libresoc.v:179868.9-179868.17" + attribute \src "libresoc.v:179616.9-179616.17" case 1'1 case end @@ -334379,179 +334085,179 @@ module \reg_1$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10943 \dest11__data_i + assign $1\reg$next[1:0]$10937 \dest11__data_i case - assign $1\reg$next[1:0]$10943 \reg + assign $1\reg$next[1:0]$10937 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10944 \dest21__data_i + assign $2\reg$next[1:0]$10938 \dest21__data_i case - assign $2\reg$next[1:0]$10944 $1\reg$next[1:0]$10943 + assign $2\reg$next[1:0]$10938 $1\reg$next[1:0]$10937 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10945 \dest31__data_i + assign $3\reg$next[1:0]$10939 \dest31__data_i case - assign $3\reg$next[1:0]$10945 $2\reg$next[1:0]$10944 + assign $3\reg$next[1:0]$10939 $2\reg$next[1:0]$10938 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10946 \w1__data_i + assign $4\reg$next[1:0]$10940 \w1__data_i case - assign $4\reg$next[1:0]$10946 $3\reg$next[1:0]$10945 + assign $4\reg$next[1:0]$10940 $3\reg$next[1:0]$10939 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10947 2'00 + assign $5\reg$next[1:0]$10941 2'00 case - assign $5\reg$next[1:0]$10947 $4\reg$next[1:0]$10946 + assign $5\reg$next[1:0]$10941 $4\reg$next[1:0]$10940 end sync always - update \reg$next $0\reg$next[1:0]$10942 + update \reg$next $0\reg$next[1:0]$10936 end - connect \$9 $not$libresoc.v:179525$10874_Y - connect \$1 $not$libresoc.v:179526$10875_Y - connect \$3 $not$libresoc.v:179527$10876_Y - connect \$6 $not$libresoc.v:179528$10877_Y + connect \$9 $not$libresoc.v:179273$10868_Y + connect \$1 $not$libresoc.v:179274$10869_Y + connect \$3 $not$libresoc.v:179275$10870_Y + connect \$6 $not$libresoc.v:179276$10871_Y end -attribute \src "libresoc.v:179904.1-180253.10" +attribute \src "libresoc.v:179652.1-180001.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" attribute \generator "nMigen" module \reg_1$136 - attribute \src "libresoc.v:179974.3-180019.6" - wire width 64 $0\cia1__data_o$next[63:0]$10962 - attribute \src "libresoc.v:179972.3-179973.41" + attribute \src "libresoc.v:179722.3-179767.6" + wire width 64 $0\cia1__data_o$next[63:0]$10956 + attribute \src "libresoc.v:179720.3-179721.41" wire width 64 $0\cia1__data_o[63:0] - attribute \src "libresoc.v:179905.7-179905.20" + attribute \src "libresoc.v:179653.7-179653.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180056.3-180101.6" - wire width 64 $0\msr1__data_o$next[63:0]$10972 - attribute \src "libresoc.v:179970.3-179971.41" + attribute \src "libresoc.v:179804.3-179849.6" + wire width 64 $0\msr1__data_o$next[63:0]$10966 + attribute \src "libresoc.v:179718.3-179719.41" wire width 64 $0\msr1__data_o[63:0] - attribute \src "libresoc.v:180220.3-180252.6" - wire width 64 $0\reg$next[63:0]$11004 - attribute \src "libresoc.v:179966.3-179967.25" + attribute \src "libresoc.v:179968.3-180000.6" + wire width 64 $0\reg$next[63:0]$10998 + attribute \src "libresoc.v:179714.3-179715.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:180138.3-180183.6" - wire width 64 $0\sv1__data_o$next[63:0]$10988 - attribute \src "libresoc.v:179968.3-179969.39" + attribute \src "libresoc.v:179886.3-179931.6" + wire width 64 $0\sv1__data_o$next[63:0]$10982 + attribute \src "libresoc.v:179716.3-179717.39" wire width 64 $0\sv1__data_o[63:0] - attribute \src "libresoc.v:180102.3-180137.6" - wire $0\wr_detect$4[0:0]$10981 - attribute \src "libresoc.v:180184.3-180219.6" - wire $0\wr_detect$7[0:0]$10997 - attribute \src "libresoc.v:180020.3-180055.6" + attribute \src "libresoc.v:179850.3-179885.6" + wire $0\wr_detect$4[0:0]$10975 + attribute \src "libresoc.v:179932.3-179967.6" + wire $0\wr_detect$7[0:0]$10991 + attribute \src "libresoc.v:179768.3-179803.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179974.3-180019.6" - wire width 64 $1\cia1__data_o$next[63:0]$10963 - attribute \src "libresoc.v:179914.14-179914.49" + attribute \src "libresoc.v:179722.3-179767.6" + wire width 64 $1\cia1__data_o$next[63:0]$10957 + attribute \src "libresoc.v:179662.14-179662.49" wire width 64 $1\cia1__data_o[63:0] - attribute \src "libresoc.v:180056.3-180101.6" - wire width 64 $1\msr1__data_o$next[63:0]$10973 - attribute \src "libresoc.v:179931.14-179931.49" + attribute \src "libresoc.v:179804.3-179849.6" + wire width 64 $1\msr1__data_o$next[63:0]$10967 + attribute \src "libresoc.v:179679.14-179679.49" wire width 64 $1\msr1__data_o[63:0] - attribute \src "libresoc.v:180220.3-180252.6" - wire width 64 $1\reg$next[63:0]$11005 - attribute \src "libresoc.v:179943.14-179943.42" + attribute \src "libresoc.v:179968.3-180000.6" + wire width 64 $1\reg$next[63:0]$10999 + attribute \src "libresoc.v:179691.14-179691.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:180138.3-180183.6" - wire width 64 $1\sv1__data_o$next[63:0]$10989 - attribute \src "libresoc.v:179950.14-179950.48" + attribute \src "libresoc.v:179886.3-179931.6" + wire width 64 $1\sv1__data_o$next[63:0]$10983 + attribute \src "libresoc.v:179698.14-179698.48" wire width 64 $1\sv1__data_o[63:0] - attribute \src "libresoc.v:180102.3-180137.6" - wire $1\wr_detect$4[0:0]$10982 - attribute \src "libresoc.v:180184.3-180219.6" - wire $1\wr_detect$7[0:0]$10998 - attribute \src "libresoc.v:180020.3-180055.6" + attribute \src "libresoc.v:179850.3-179885.6" + wire $1\wr_detect$4[0:0]$10976 + attribute \src "libresoc.v:179932.3-179967.6" + wire $1\wr_detect$7[0:0]$10992 + attribute \src "libresoc.v:179768.3-179803.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179974.3-180019.6" - wire width 64 $2\cia1__data_o$next[63:0]$10964 - attribute \src "libresoc.v:180056.3-180101.6" - wire width 64 $2\msr1__data_o$next[63:0]$10974 - attribute \src "libresoc.v:180220.3-180252.6" - wire width 64 $2\reg$next[63:0]$11006 - attribute \src "libresoc.v:180138.3-180183.6" - wire width 64 $2\sv1__data_o$next[63:0]$10990 - attribute \src "libresoc.v:180102.3-180137.6" - wire $2\wr_detect$4[0:0]$10983 - attribute \src "libresoc.v:180184.3-180219.6" - wire $2\wr_detect$7[0:0]$10999 - attribute \src "libresoc.v:180020.3-180055.6" + attribute \src "libresoc.v:179722.3-179767.6" + wire width 64 $2\cia1__data_o$next[63:0]$10958 + attribute \src "libresoc.v:179804.3-179849.6" + wire width 64 $2\msr1__data_o$next[63:0]$10968 + attribute \src "libresoc.v:179968.3-180000.6" + wire width 64 $2\reg$next[63:0]$11000 + attribute \src "libresoc.v:179886.3-179931.6" + wire width 64 $2\sv1__data_o$next[63:0]$10984 + attribute \src "libresoc.v:179850.3-179885.6" + wire $2\wr_detect$4[0:0]$10977 + attribute \src "libresoc.v:179932.3-179967.6" + wire $2\wr_detect$7[0:0]$10993 + attribute \src "libresoc.v:179768.3-179803.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179974.3-180019.6" - wire width 64 $3\cia1__data_o$next[63:0]$10965 - attribute \src "libresoc.v:180056.3-180101.6" - wire width 64 $3\msr1__data_o$next[63:0]$10975 - attribute \src "libresoc.v:180220.3-180252.6" - wire width 64 $3\reg$next[63:0]$11007 - attribute \src "libresoc.v:180138.3-180183.6" - wire width 64 $3\sv1__data_o$next[63:0]$10991 - attribute \src "libresoc.v:180102.3-180137.6" - wire $3\wr_detect$4[0:0]$10984 - attribute \src "libresoc.v:180184.3-180219.6" - wire $3\wr_detect$7[0:0]$11000 - attribute \src "libresoc.v:180020.3-180055.6" + attribute \src "libresoc.v:179722.3-179767.6" + wire width 64 $3\cia1__data_o$next[63:0]$10959 + attribute \src "libresoc.v:179804.3-179849.6" + wire width 64 $3\msr1__data_o$next[63:0]$10969 + attribute \src "libresoc.v:179968.3-180000.6" + wire width 64 $3\reg$next[63:0]$11001 + attribute \src "libresoc.v:179886.3-179931.6" + wire width 64 $3\sv1__data_o$next[63:0]$10985 + attribute \src "libresoc.v:179850.3-179885.6" + wire $3\wr_detect$4[0:0]$10978 + attribute \src "libresoc.v:179932.3-179967.6" + wire $3\wr_detect$7[0:0]$10994 + attribute \src "libresoc.v:179768.3-179803.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179974.3-180019.6" - wire width 64 $4\cia1__data_o$next[63:0]$10966 - attribute \src "libresoc.v:180056.3-180101.6" - wire width 64 $4\msr1__data_o$next[63:0]$10976 - attribute \src "libresoc.v:180220.3-180252.6" - wire width 64 $4\reg$next[63:0]$11008 - attribute \src "libresoc.v:180138.3-180183.6" - wire width 64 $4\sv1__data_o$next[63:0]$10992 - attribute \src "libresoc.v:180102.3-180137.6" - wire $4\wr_detect$4[0:0]$10985 - attribute \src "libresoc.v:180184.3-180219.6" - wire $4\wr_detect$7[0:0]$11001 - attribute \src "libresoc.v:180020.3-180055.6" + attribute \src "libresoc.v:179722.3-179767.6" + wire width 64 $4\cia1__data_o$next[63:0]$10960 + attribute \src "libresoc.v:179804.3-179849.6" + wire width 64 $4\msr1__data_o$next[63:0]$10970 + attribute \src "libresoc.v:179968.3-180000.6" + wire width 64 $4\reg$next[63:0]$11002 + attribute \src "libresoc.v:179886.3-179931.6" + wire width 64 $4\sv1__data_o$next[63:0]$10986 + attribute \src "libresoc.v:179850.3-179885.6" + wire $4\wr_detect$4[0:0]$10979 + attribute \src "libresoc.v:179932.3-179967.6" + wire $4\wr_detect$7[0:0]$10995 + attribute \src "libresoc.v:179768.3-179803.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179974.3-180019.6" - wire width 64 $5\cia1__data_o$next[63:0]$10967 - attribute \src "libresoc.v:180056.3-180101.6" - wire width 64 $5\msr1__data_o$next[63:0]$10977 - attribute \src "libresoc.v:180220.3-180252.6" - wire width 64 $5\reg$next[63:0]$11009 - attribute \src "libresoc.v:180138.3-180183.6" - wire width 64 $5\sv1__data_o$next[63:0]$10993 - attribute \src "libresoc.v:180102.3-180137.6" - wire $5\wr_detect$4[0:0]$10986 - attribute \src "libresoc.v:180184.3-180219.6" - wire $5\wr_detect$7[0:0]$11002 - attribute \src "libresoc.v:180020.3-180055.6" + attribute \src "libresoc.v:179722.3-179767.6" + wire width 64 $5\cia1__data_o$next[63:0]$10961 + attribute \src "libresoc.v:179804.3-179849.6" + wire width 64 $5\msr1__data_o$next[63:0]$10971 + attribute \src "libresoc.v:179968.3-180000.6" + wire width 64 $5\reg$next[63:0]$11003 + attribute \src "libresoc.v:179886.3-179931.6" + wire width 64 $5\sv1__data_o$next[63:0]$10987 + attribute \src "libresoc.v:179850.3-179885.6" + wire $5\wr_detect$4[0:0]$10980 + attribute \src "libresoc.v:179932.3-179967.6" + wire $5\wr_detect$7[0:0]$10996 + attribute \src "libresoc.v:179768.3-179803.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:179974.3-180019.6" - wire width 64 $6\cia1__data_o$next[63:0]$10968 - attribute \src "libresoc.v:180056.3-180101.6" - wire width 64 $6\msr1__data_o$next[63:0]$10978 - attribute \src "libresoc.v:180138.3-180183.6" - wire width 64 $6\sv1__data_o$next[63:0]$10994 - attribute \src "libresoc.v:179974.3-180019.6" - wire width 64 $7\cia1__data_o$next[63:0]$10969 - attribute \src "libresoc.v:180056.3-180101.6" - wire width 64 $7\msr1__data_o$next[63:0]$10979 - attribute \src "libresoc.v:180138.3-180183.6" - wire width 64 $7\sv1__data_o$next[63:0]$10995 - attribute \src "libresoc.v:179963.17-179963.100" - wire $not$libresoc.v:179963$10954_Y - attribute \src "libresoc.v:179964.17-179964.103" - wire $not$libresoc.v:179964$10955_Y - attribute \src "libresoc.v:179965.17-179965.103" - wire $not$libresoc.v:179965$10956_Y + attribute \src "libresoc.v:179722.3-179767.6" + wire width 64 $6\cia1__data_o$next[63:0]$10962 + attribute \src "libresoc.v:179804.3-179849.6" + wire width 64 $6\msr1__data_o$next[63:0]$10972 + attribute \src "libresoc.v:179886.3-179931.6" + wire width 64 $6\sv1__data_o$next[63:0]$10988 + attribute \src "libresoc.v:179722.3-179767.6" + wire width 64 $7\cia1__data_o$next[63:0]$10963 + attribute \src "libresoc.v:179804.3-179849.6" + wire width 64 $7\msr1__data_o$next[63:0]$10973 + attribute \src "libresoc.v:179886.3-179931.6" + wire width 64 $7\sv1__data_o$next[63:0]$10989 + attribute \src "libresoc.v:179711.17-179711.100" + wire $not$libresoc.v:179711$10948_Y + attribute \src "libresoc.v:179712.17-179712.103" + wire $not$libresoc.v:179712$10949_Y + attribute \src "libresoc.v:179713.17-179713.103" + wire $not$libresoc.v:179713$10950_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -334564,15 +334270,15 @@ module \reg_1$136 wire width 64 \cia1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr11__wen - attribute \src "libresoc.v:179905.7-179905.15" + attribute \src "libresoc.v:179653.7-179653.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr1__data_i @@ -334609,106 +334315,106 @@ module \reg_1$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179963$10954 + cell $not $not$libresoc.v:179711$10948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179963$10954_Y + connect \Y $not$libresoc.v:179711$10948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179964$10955 + cell $not $not$libresoc.v:179712$10949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179964$10955_Y + connect \Y $not$libresoc.v:179712$10949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179965$10956 + cell $not $not$libresoc.v:179713$10950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179965$10956_Y + connect \Y $not$libresoc.v:179713$10950_Y end - attribute \src "libresoc.v:179905.7-179905.20" - process $proc$libresoc.v:179905$11010 + attribute \src "libresoc.v:179653.7-179653.20" + process $proc$libresoc.v:179653$11004 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179914.14-179914.49" - process $proc$libresoc.v:179914$11011 + attribute \src "libresoc.v:179662.14-179662.49" + process $proc$libresoc.v:179662$11005 assign { } { } assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia1__data_o $1\cia1__data_o[63:0] end - attribute \src "libresoc.v:179931.14-179931.49" - process $proc$libresoc.v:179931$11012 + attribute \src "libresoc.v:179679.14-179679.49" + process $proc$libresoc.v:179679$11006 assign { } { } assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr1__data_o $1\msr1__data_o[63:0] end - attribute \src "libresoc.v:179943.14-179943.42" - process $proc$libresoc.v:179943$11013 + attribute \src "libresoc.v:179691.14-179691.42" + process $proc$libresoc.v:179691$11007 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:179950.14-179950.48" - process $proc$libresoc.v:179950$11014 + attribute \src "libresoc.v:179698.14-179698.48" + process $proc$libresoc.v:179698$11008 assign { } { } assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv1__data_o $1\sv1__data_o[63:0] end - attribute \src "libresoc.v:179966.3-179967.25" - process $proc$libresoc.v:179966$10957 + attribute \src "libresoc.v:179714.3-179715.25" + process $proc$libresoc.v:179714$10951 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:179968.3-179969.39" - process $proc$libresoc.v:179968$10958 + attribute \src "libresoc.v:179716.3-179717.39" + process $proc$libresoc.v:179716$10952 assign { } { } assign $0\sv1__data_o[63:0] \sv1__data_o$next sync posedge \coresync_clk update \sv1__data_o $0\sv1__data_o[63:0] end - attribute \src "libresoc.v:179970.3-179971.41" - process $proc$libresoc.v:179970$10959 + attribute \src "libresoc.v:179718.3-179719.41" + process $proc$libresoc.v:179718$10953 assign { } { } assign $0\msr1__data_o[63:0] \msr1__data_o$next sync posedge \coresync_clk update \msr1__data_o $0\msr1__data_o[63:0] end - attribute \src "libresoc.v:179972.3-179973.41" - process $proc$libresoc.v:179972$10960 + attribute \src "libresoc.v:179720.3-179721.41" + process $proc$libresoc.v:179720$10954 assign { } { } assign $0\cia1__data_o[63:0] \cia1__data_o$next sync posedge \coresync_clk update \cia1__data_o $0\cia1__data_o[63:0] end - attribute \src "libresoc.v:179974.3-180019.6" - process $proc$libresoc.v:179974$10961 + attribute \src "libresoc.v:179722.3-179767.6" + process $proc$libresoc.v:179722$10955 assign { } { } assign { } { } assign { } { } - assign $0\cia1__data_o$next[63:0]$10962 $7\cia1__data_o$next[63:0]$10969 - attribute \src "libresoc.v:179975.5-179975.29" + assign $0\cia1__data_o$next[63:0]$10956 $7\cia1__data_o$next[63:0]$10963 + attribute \src "libresoc.v:179723.5-179723.29" switch \initial - attribute \src "libresoc.v:179975.9-179975.17" + attribute \src "libresoc.v:179723.9-179723.17" case 1'1 case end @@ -334721,75 +334427,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\cia1__data_o$next[63:0]$10963 $6\cia1__data_o$next[63:0]$10968 + assign $1\cia1__data_o$next[63:0]$10957 $6\cia1__data_o$next[63:0]$10962 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia1__data_o$next[63:0]$10964 \nia1__data_i + assign $2\cia1__data_o$next[63:0]$10958 \nia1__data_i case - assign $2\cia1__data_o$next[63:0]$10964 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia1__data_o$next[63:0]$10958 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia1__data_o$next[63:0]$10965 \msr1__data_i + assign $3\cia1__data_o$next[63:0]$10959 \msr1__data_i case - assign $3\cia1__data_o$next[63:0]$10965 $2\cia1__data_o$next[63:0]$10964 + assign $3\cia1__data_o$next[63:0]$10959 $2\cia1__data_o$next[63:0]$10958 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia1__data_o$next[63:0]$10966 \sv1__data_i + assign $4\cia1__data_o$next[63:0]$10960 \sv1__data_i case - assign $4\cia1__data_o$next[63:0]$10966 $3\cia1__data_o$next[63:0]$10965 + assign $4\cia1__data_o$next[63:0]$10960 $3\cia1__data_o$next[63:0]$10959 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia1__data_o$next[63:0]$10967 \d_wr11__data_i + assign $5\cia1__data_o$next[63:0]$10961 \d_wr11__data_i case - assign $5\cia1__data_o$next[63:0]$10967 $4\cia1__data_o$next[63:0]$10966 + assign $5\cia1__data_o$next[63:0]$10961 $4\cia1__data_o$next[63:0]$10960 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia1__data_o$next[63:0]$10968 \reg + assign $6\cia1__data_o$next[63:0]$10962 \reg case - assign $6\cia1__data_o$next[63:0]$10968 $5\cia1__data_o$next[63:0]$10967 + assign $6\cia1__data_o$next[63:0]$10962 $5\cia1__data_o$next[63:0]$10961 end case - assign $1\cia1__data_o$next[63:0]$10963 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia1__data_o$next[63:0]$10957 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia1__data_o$next[63:0]$10969 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia1__data_o$next[63:0]$10963 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia1__data_o$next[63:0]$10969 $1\cia1__data_o$next[63:0]$10963 + assign $7\cia1__data_o$next[63:0]$10963 $1\cia1__data_o$next[63:0]$10957 end sync always - update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10962 + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10956 end - attribute \src "libresoc.v:180020.3-180055.6" - process $proc$libresoc.v:180020$10970 + attribute \src "libresoc.v:179768.3-179803.6" + process $proc$libresoc.v:179768$10964 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180021.5-180021.29" + attribute \src "libresoc.v:179769.5-179769.29" switch \initial - attribute \src "libresoc.v:180021.9-180021.17" + attribute \src "libresoc.v:179769.9-179769.17" case 1'1 case end @@ -334845,15 +334551,15 @@ module \reg_1$136 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180056.3-180101.6" - process $proc$libresoc.v:180056$10971 + attribute \src "libresoc.v:179804.3-179849.6" + process $proc$libresoc.v:179804$10965 assign { } { } assign { } { } assign { } { } - assign $0\msr1__data_o$next[63:0]$10972 $7\msr1__data_o$next[63:0]$10979 - attribute \src "libresoc.v:180057.5-180057.29" + assign $0\msr1__data_o$next[63:0]$10966 $7\msr1__data_o$next[63:0]$10973 + attribute \src "libresoc.v:179805.5-179805.29" switch \initial - attribute \src "libresoc.v:180057.9-180057.17" + attribute \src "libresoc.v:179805.9-179805.17" case 1'1 case end @@ -334866,75 +334572,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\msr1__data_o$next[63:0]$10973 $6\msr1__data_o$next[63:0]$10978 + assign $1\msr1__data_o$next[63:0]$10967 $6\msr1__data_o$next[63:0]$10972 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr1__data_o$next[63:0]$10974 \nia1__data_i + assign $2\msr1__data_o$next[63:0]$10968 \nia1__data_i case - assign $2\msr1__data_o$next[63:0]$10974 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr1__data_o$next[63:0]$10968 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr1__data_o$next[63:0]$10975 \msr1__data_i + assign $3\msr1__data_o$next[63:0]$10969 \msr1__data_i case - assign $3\msr1__data_o$next[63:0]$10975 $2\msr1__data_o$next[63:0]$10974 + assign $3\msr1__data_o$next[63:0]$10969 $2\msr1__data_o$next[63:0]$10968 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr1__data_o$next[63:0]$10976 \sv1__data_i + assign $4\msr1__data_o$next[63:0]$10970 \sv1__data_i case - assign $4\msr1__data_o$next[63:0]$10976 $3\msr1__data_o$next[63:0]$10975 + assign $4\msr1__data_o$next[63:0]$10970 $3\msr1__data_o$next[63:0]$10969 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr1__data_o$next[63:0]$10977 \d_wr11__data_i + assign $5\msr1__data_o$next[63:0]$10971 \d_wr11__data_i case - assign $5\msr1__data_o$next[63:0]$10977 $4\msr1__data_o$next[63:0]$10976 + assign $5\msr1__data_o$next[63:0]$10971 $4\msr1__data_o$next[63:0]$10970 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr1__data_o$next[63:0]$10978 \reg + assign $6\msr1__data_o$next[63:0]$10972 \reg case - assign $6\msr1__data_o$next[63:0]$10978 $5\msr1__data_o$next[63:0]$10977 + assign $6\msr1__data_o$next[63:0]$10972 $5\msr1__data_o$next[63:0]$10971 end case - assign $1\msr1__data_o$next[63:0]$10973 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr1__data_o$next[63:0]$10967 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr1__data_o$next[63:0]$10979 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr1__data_o$next[63:0]$10973 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr1__data_o$next[63:0]$10979 $1\msr1__data_o$next[63:0]$10973 + assign $7\msr1__data_o$next[63:0]$10973 $1\msr1__data_o$next[63:0]$10967 end sync always - update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10972 + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10966 end - attribute \src "libresoc.v:180102.3-180137.6" - process $proc$libresoc.v:180102$10980 + attribute \src "libresoc.v:179850.3-179885.6" + process $proc$libresoc.v:179850$10974 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10981 $1\wr_detect$4[0:0]$10982 - attribute \src "libresoc.v:180103.5-180103.29" + assign $0\wr_detect$4[0:0]$10975 $1\wr_detect$4[0:0]$10976 + attribute \src "libresoc.v:179851.5-179851.29" switch \initial - attribute \src "libresoc.v:180103.9-180103.17" + attribute \src "libresoc.v:179851.9-179851.17" case 1'1 case end @@ -334947,58 +334653,58 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10982 $5\wr_detect$4[0:0]$10986 + assign $1\wr_detect$4[0:0]$10976 $5\wr_detect$4[0:0]$10980 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10983 1'1 + assign $2\wr_detect$4[0:0]$10977 1'1 case - assign $2\wr_detect$4[0:0]$10983 1'0 + assign $2\wr_detect$4[0:0]$10977 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10984 1'1 + assign $3\wr_detect$4[0:0]$10978 1'1 case - assign $3\wr_detect$4[0:0]$10984 $2\wr_detect$4[0:0]$10983 + assign $3\wr_detect$4[0:0]$10978 $2\wr_detect$4[0:0]$10977 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10985 1'1 + assign $4\wr_detect$4[0:0]$10979 1'1 case - assign $4\wr_detect$4[0:0]$10985 $3\wr_detect$4[0:0]$10984 + assign $4\wr_detect$4[0:0]$10979 $3\wr_detect$4[0:0]$10978 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10986 1'1 + assign $5\wr_detect$4[0:0]$10980 1'1 case - assign $5\wr_detect$4[0:0]$10986 $4\wr_detect$4[0:0]$10985 + assign $5\wr_detect$4[0:0]$10980 $4\wr_detect$4[0:0]$10979 end case - assign $1\wr_detect$4[0:0]$10982 1'0 + assign $1\wr_detect$4[0:0]$10976 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10981 + update \wr_detect$4 $0\wr_detect$4[0:0]$10975 end - attribute \src "libresoc.v:180138.3-180183.6" - process $proc$libresoc.v:180138$10987 + attribute \src "libresoc.v:179886.3-179931.6" + process $proc$libresoc.v:179886$10981 assign { } { } assign { } { } assign { } { } - assign $0\sv1__data_o$next[63:0]$10988 $7\sv1__data_o$next[63:0]$10995 - attribute \src "libresoc.v:180139.5-180139.29" + assign $0\sv1__data_o$next[63:0]$10982 $7\sv1__data_o$next[63:0]$10989 + attribute \src "libresoc.v:179887.5-179887.29" switch \initial - attribute \src "libresoc.v:180139.9-180139.17" + attribute \src "libresoc.v:179887.9-179887.17" case 1'1 case end @@ -335011,75 +334717,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\sv1__data_o$next[63:0]$10989 $6\sv1__data_o$next[63:0]$10994 + assign $1\sv1__data_o$next[63:0]$10983 $6\sv1__data_o$next[63:0]$10988 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv1__data_o$next[63:0]$10990 \nia1__data_i + assign $2\sv1__data_o$next[63:0]$10984 \nia1__data_i case - assign $2\sv1__data_o$next[63:0]$10990 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv1__data_o$next[63:0]$10984 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv1__data_o$next[63:0]$10991 \msr1__data_i + assign $3\sv1__data_o$next[63:0]$10985 \msr1__data_i case - assign $3\sv1__data_o$next[63:0]$10991 $2\sv1__data_o$next[63:0]$10990 + assign $3\sv1__data_o$next[63:0]$10985 $2\sv1__data_o$next[63:0]$10984 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv1__data_o$next[63:0]$10992 \sv1__data_i + assign $4\sv1__data_o$next[63:0]$10986 \sv1__data_i case - assign $4\sv1__data_o$next[63:0]$10992 $3\sv1__data_o$next[63:0]$10991 + assign $4\sv1__data_o$next[63:0]$10986 $3\sv1__data_o$next[63:0]$10985 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv1__data_o$next[63:0]$10993 \d_wr11__data_i + assign $5\sv1__data_o$next[63:0]$10987 \d_wr11__data_i case - assign $5\sv1__data_o$next[63:0]$10993 $4\sv1__data_o$next[63:0]$10992 + assign $5\sv1__data_o$next[63:0]$10987 $4\sv1__data_o$next[63:0]$10986 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv1__data_o$next[63:0]$10994 \reg + assign $6\sv1__data_o$next[63:0]$10988 \reg case - assign $6\sv1__data_o$next[63:0]$10994 $5\sv1__data_o$next[63:0]$10993 + assign $6\sv1__data_o$next[63:0]$10988 $5\sv1__data_o$next[63:0]$10987 end case - assign $1\sv1__data_o$next[63:0]$10989 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv1__data_o$next[63:0]$10983 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv1__data_o$next[63:0]$10995 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv1__data_o$next[63:0]$10989 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv1__data_o$next[63:0]$10995 $1\sv1__data_o$next[63:0]$10989 + assign $7\sv1__data_o$next[63:0]$10989 $1\sv1__data_o$next[63:0]$10983 end sync always - update \sv1__data_o$next $0\sv1__data_o$next[63:0]$10988 + update \sv1__data_o$next $0\sv1__data_o$next[63:0]$10982 end - attribute \src "libresoc.v:180184.3-180219.6" - process $proc$libresoc.v:180184$10996 + attribute \src "libresoc.v:179932.3-179967.6" + process $proc$libresoc.v:179932$10990 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10997 $1\wr_detect$7[0:0]$10998 - attribute \src "libresoc.v:180185.5-180185.29" + assign $0\wr_detect$7[0:0]$10991 $1\wr_detect$7[0:0]$10992 + attribute \src "libresoc.v:179933.5-179933.29" switch \initial - attribute \src "libresoc.v:180185.9-180185.17" + attribute \src "libresoc.v:179933.9-179933.17" case 1'1 case end @@ -335092,61 +334798,61 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10998 $5\wr_detect$7[0:0]$11002 + assign $1\wr_detect$7[0:0]$10992 $5\wr_detect$7[0:0]$10996 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10999 1'1 + assign $2\wr_detect$7[0:0]$10993 1'1 case - assign $2\wr_detect$7[0:0]$10999 1'0 + assign $2\wr_detect$7[0:0]$10993 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11000 1'1 + assign $3\wr_detect$7[0:0]$10994 1'1 case - assign $3\wr_detect$7[0:0]$11000 $2\wr_detect$7[0:0]$10999 + assign $3\wr_detect$7[0:0]$10994 $2\wr_detect$7[0:0]$10993 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11001 1'1 + assign $4\wr_detect$7[0:0]$10995 1'1 case - assign $4\wr_detect$7[0:0]$11001 $3\wr_detect$7[0:0]$11000 + assign $4\wr_detect$7[0:0]$10995 $3\wr_detect$7[0:0]$10994 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11002 1'1 + assign $5\wr_detect$7[0:0]$10996 1'1 case - assign $5\wr_detect$7[0:0]$11002 $4\wr_detect$7[0:0]$11001 + assign $5\wr_detect$7[0:0]$10996 $4\wr_detect$7[0:0]$10995 end case - assign $1\wr_detect$7[0:0]$10998 1'0 + assign $1\wr_detect$7[0:0]$10992 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10997 + update \wr_detect$7 $0\wr_detect$7[0:0]$10991 end - attribute \src "libresoc.v:180220.3-180252.6" - process $proc$libresoc.v:180220$11003 + attribute \src "libresoc.v:179968.3-180000.6" + process $proc$libresoc.v:179968$10997 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11004 $5\reg$next[63:0]$11009 - attribute \src "libresoc.v:180221.5-180221.29" + assign $0\reg$next[63:0]$10998 $5\reg$next[63:0]$11003 + attribute \src "libresoc.v:179969.5-179969.29" switch \initial - attribute \src "libresoc.v:180221.9-180221.17" + attribute \src "libresoc.v:179969.9-179969.17" case 1'1 case end @@ -335155,224 +334861,224 @@ module \reg_1$136 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11005 \nia1__data_i + assign $1\reg$next[63:0]$10999 \nia1__data_i case - assign $1\reg$next[63:0]$11005 \reg + assign $1\reg$next[63:0]$10999 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11006 \msr1__data_i + assign $2\reg$next[63:0]$11000 \msr1__data_i case - assign $2\reg$next[63:0]$11006 $1\reg$next[63:0]$11005 + assign $2\reg$next[63:0]$11000 $1\reg$next[63:0]$10999 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11007 \sv1__data_i + assign $3\reg$next[63:0]$11001 \sv1__data_i case - assign $3\reg$next[63:0]$11007 $2\reg$next[63:0]$11006 + assign $3\reg$next[63:0]$11001 $2\reg$next[63:0]$11000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11008 \d_wr11__data_i + assign $4\reg$next[63:0]$11002 \d_wr11__data_i case - assign $4\reg$next[63:0]$11008 $3\reg$next[63:0]$11007 + assign $4\reg$next[63:0]$11002 $3\reg$next[63:0]$11001 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11009 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11003 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11009 $4\reg$next[63:0]$11008 + assign $5\reg$next[63:0]$11003 $4\reg$next[63:0]$11002 end sync always - update \reg$next $0\reg$next[63:0]$11004 + update \reg$next $0\reg$next[63:0]$10998 end - connect \$1 $not$libresoc.v:179963$10954_Y - connect \$3 $not$libresoc.v:179964$10955_Y - connect \$6 $not$libresoc.v:179965$10956_Y + connect \$1 $not$libresoc.v:179711$10948_Y + connect \$3 $not$libresoc.v:179712$10949_Y + connect \$6 $not$libresoc.v:179713$10950_Y end -attribute \src "libresoc.v:180257.1-180728.10" +attribute \src "libresoc.v:180005.1-180476.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" attribute \generator "nMigen" module \reg_2 - attribute \src "libresoc.v:180258.7-180258.20" + attribute \src "libresoc.v:180006.7-180006.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180658.3-180697.6" - wire width 4 $0\r22__data_o$next[3:0]$11084 - attribute \src "libresoc.v:180341.3-180342.39" + attribute \src "libresoc.v:180406.3-180445.6" + wire width 4 $0\r22__data_o$next[3:0]$11078 + attribute \src "libresoc.v:180089.3-180090.39" wire width 4 $0\r22__data_o[3:0] - attribute \src "libresoc.v:180588.3-180627.6" - wire width 4 $0\r2__data_o$next[3:0]$11070 - attribute \src "libresoc.v:180343.3-180344.37" + attribute \src "libresoc.v:180336.3-180375.6" + wire width 4 $0\r2__data_o$next[3:0]$11064 + attribute \src "libresoc.v:180091.3-180092.37" wire width 4 $0\r2__data_o[3:0] - attribute \src "libresoc.v:180421.3-180447.6" - wire width 4 $0\reg$next[3:0]$11036 - attribute \src "libresoc.v:180339.3-180340.25" + attribute \src "libresoc.v:180169.3-180195.6" + wire width 4 $0\reg$next[3:0]$11030 + attribute \src "libresoc.v:180087.3-180088.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:180351.3-180390.6" - wire width 4 $0\src12__data_o$next[3:0]$11027 - attribute \src "libresoc.v:180349.3-180350.43" + attribute \src "libresoc.v:180099.3-180138.6" + wire width 4 $0\src12__data_o$next[3:0]$11021 + attribute \src "libresoc.v:180097.3-180098.43" wire width 4 $0\src12__data_o[3:0] - attribute \src "libresoc.v:180448.3-180487.6" - wire width 4 $0\src22__data_o$next[3:0]$11042 - attribute \src "libresoc.v:180347.3-180348.43" + attribute \src "libresoc.v:180196.3-180235.6" + wire width 4 $0\src22__data_o$next[3:0]$11036 + attribute \src "libresoc.v:180095.3-180096.43" wire width 4 $0\src22__data_o[3:0] - attribute \src "libresoc.v:180518.3-180557.6" - wire width 4 $0\src32__data_o$next[3:0]$11056 - attribute \src "libresoc.v:180345.3-180346.43" + attribute \src "libresoc.v:180266.3-180305.6" + wire width 4 $0\src32__data_o$next[3:0]$11050 + attribute \src "libresoc.v:180093.3-180094.43" wire width 4 $0\src32__data_o[3:0] - attribute \src "libresoc.v:180628.3-180657.6" - wire $0\wr_detect$10[0:0]$11078 - attribute \src "libresoc.v:180698.3-180727.6" - wire $0\wr_detect$13[0:0]$11092 - attribute \src "libresoc.v:180488.3-180517.6" - wire $0\wr_detect$4[0:0]$11050 - attribute \src "libresoc.v:180558.3-180587.6" - wire $0\wr_detect$7[0:0]$11064 - attribute \src "libresoc.v:180391.3-180420.6" + attribute \src "libresoc.v:180376.3-180405.6" + wire $0\wr_detect$10[0:0]$11072 + attribute \src "libresoc.v:180446.3-180475.6" + wire $0\wr_detect$13[0:0]$11086 + attribute \src "libresoc.v:180236.3-180265.6" + wire $0\wr_detect$4[0:0]$11044 + attribute \src "libresoc.v:180306.3-180335.6" + wire $0\wr_detect$7[0:0]$11058 + attribute \src "libresoc.v:180139.3-180168.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180658.3-180697.6" - wire width 4 $1\r22__data_o$next[3:0]$11085 - attribute \src "libresoc.v:180283.13-180283.31" + attribute \src "libresoc.v:180406.3-180445.6" + wire width 4 $1\r22__data_o$next[3:0]$11079 + attribute \src "libresoc.v:180031.13-180031.31" wire width 4 $1\r22__data_o[3:0] - attribute \src "libresoc.v:180588.3-180627.6" - wire width 4 $1\r2__data_o$next[3:0]$11071 - attribute \src "libresoc.v:180290.13-180290.30" + attribute \src "libresoc.v:180336.3-180375.6" + wire width 4 $1\r2__data_o$next[3:0]$11065 + attribute \src "libresoc.v:180038.13-180038.30" wire width 4 $1\r2__data_o[3:0] - attribute \src "libresoc.v:180421.3-180447.6" - wire width 4 $1\reg$next[3:0]$11037 - attribute \src "libresoc.v:180296.13-180296.25" + attribute \src "libresoc.v:180169.3-180195.6" + wire width 4 $1\reg$next[3:0]$11031 + attribute \src "libresoc.v:180044.13-180044.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:180351.3-180390.6" - wire width 4 $1\src12__data_o$next[3:0]$11028 - attribute \src "libresoc.v:180301.13-180301.33" + attribute \src "libresoc.v:180099.3-180138.6" + wire width 4 $1\src12__data_o$next[3:0]$11022 + attribute \src "libresoc.v:180049.13-180049.33" wire width 4 $1\src12__data_o[3:0] - attribute \src "libresoc.v:180448.3-180487.6" - wire width 4 $1\src22__data_o$next[3:0]$11043 - attribute \src "libresoc.v:180308.13-180308.33" + attribute \src "libresoc.v:180196.3-180235.6" + wire width 4 $1\src22__data_o$next[3:0]$11037 + attribute \src "libresoc.v:180056.13-180056.33" wire width 4 $1\src22__data_o[3:0] - attribute \src "libresoc.v:180518.3-180557.6" - wire width 4 $1\src32__data_o$next[3:0]$11057 - attribute \src "libresoc.v:180315.13-180315.33" + attribute \src "libresoc.v:180266.3-180305.6" + wire width 4 $1\src32__data_o$next[3:0]$11051 + attribute \src "libresoc.v:180063.13-180063.33" wire width 4 $1\src32__data_o[3:0] - attribute \src "libresoc.v:180628.3-180657.6" - wire $1\wr_detect$10[0:0]$11079 - attribute \src "libresoc.v:180698.3-180727.6" - wire $1\wr_detect$13[0:0]$11093 - attribute \src "libresoc.v:180488.3-180517.6" - wire $1\wr_detect$4[0:0]$11051 - attribute \src "libresoc.v:180558.3-180587.6" - wire $1\wr_detect$7[0:0]$11065 - attribute \src "libresoc.v:180391.3-180420.6" + attribute \src "libresoc.v:180376.3-180405.6" + wire $1\wr_detect$10[0:0]$11073 + attribute \src "libresoc.v:180446.3-180475.6" + wire $1\wr_detect$13[0:0]$11087 + attribute \src "libresoc.v:180236.3-180265.6" + wire $1\wr_detect$4[0:0]$11045 + attribute \src "libresoc.v:180306.3-180335.6" + wire $1\wr_detect$7[0:0]$11059 + attribute \src "libresoc.v:180139.3-180168.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180658.3-180697.6" - wire width 4 $2\r22__data_o$next[3:0]$11086 - attribute \src "libresoc.v:180588.3-180627.6" - wire width 4 $2\r2__data_o$next[3:0]$11072 - attribute \src "libresoc.v:180421.3-180447.6" - wire width 4 $2\reg$next[3:0]$11038 - attribute \src "libresoc.v:180351.3-180390.6" - wire width 4 $2\src12__data_o$next[3:0]$11029 - attribute \src "libresoc.v:180448.3-180487.6" - wire width 4 $2\src22__data_o$next[3:0]$11044 - attribute \src "libresoc.v:180518.3-180557.6" - wire width 4 $2\src32__data_o$next[3:0]$11058 - attribute \src "libresoc.v:180628.3-180657.6" - wire $2\wr_detect$10[0:0]$11080 - attribute \src "libresoc.v:180698.3-180727.6" - wire $2\wr_detect$13[0:0]$11094 - attribute \src "libresoc.v:180488.3-180517.6" - wire $2\wr_detect$4[0:0]$11052 - attribute \src "libresoc.v:180558.3-180587.6" - wire $2\wr_detect$7[0:0]$11066 - attribute \src "libresoc.v:180391.3-180420.6" + attribute \src "libresoc.v:180406.3-180445.6" + wire width 4 $2\r22__data_o$next[3:0]$11080 + attribute \src "libresoc.v:180336.3-180375.6" + wire width 4 $2\r2__data_o$next[3:0]$11066 + attribute \src "libresoc.v:180169.3-180195.6" + wire width 4 $2\reg$next[3:0]$11032 + attribute \src "libresoc.v:180099.3-180138.6" + wire width 4 $2\src12__data_o$next[3:0]$11023 + attribute \src "libresoc.v:180196.3-180235.6" + wire width 4 $2\src22__data_o$next[3:0]$11038 + attribute \src "libresoc.v:180266.3-180305.6" + wire width 4 $2\src32__data_o$next[3:0]$11052 + attribute \src "libresoc.v:180376.3-180405.6" + wire $2\wr_detect$10[0:0]$11074 + attribute \src "libresoc.v:180446.3-180475.6" + wire $2\wr_detect$13[0:0]$11088 + attribute \src "libresoc.v:180236.3-180265.6" + wire $2\wr_detect$4[0:0]$11046 + attribute \src "libresoc.v:180306.3-180335.6" + wire $2\wr_detect$7[0:0]$11060 + attribute \src "libresoc.v:180139.3-180168.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180658.3-180697.6" - wire width 4 $3\r22__data_o$next[3:0]$11087 - attribute \src "libresoc.v:180588.3-180627.6" - wire width 4 $3\r2__data_o$next[3:0]$11073 - attribute \src "libresoc.v:180421.3-180447.6" - wire width 4 $3\reg$next[3:0]$11039 - attribute \src "libresoc.v:180351.3-180390.6" - wire width 4 $3\src12__data_o$next[3:0]$11030 - attribute \src "libresoc.v:180448.3-180487.6" - wire width 4 $3\src22__data_o$next[3:0]$11045 - attribute \src "libresoc.v:180518.3-180557.6" - wire width 4 $3\src32__data_o$next[3:0]$11059 - attribute \src "libresoc.v:180628.3-180657.6" - wire $3\wr_detect$10[0:0]$11081 - attribute \src "libresoc.v:180698.3-180727.6" - wire $3\wr_detect$13[0:0]$11095 - attribute \src "libresoc.v:180488.3-180517.6" - wire $3\wr_detect$4[0:0]$11053 - attribute \src "libresoc.v:180558.3-180587.6" - wire $3\wr_detect$7[0:0]$11067 - attribute \src "libresoc.v:180391.3-180420.6" + attribute \src "libresoc.v:180406.3-180445.6" + wire width 4 $3\r22__data_o$next[3:0]$11081 + attribute \src "libresoc.v:180336.3-180375.6" + wire width 4 $3\r2__data_o$next[3:0]$11067 + attribute \src "libresoc.v:180169.3-180195.6" + wire width 4 $3\reg$next[3:0]$11033 + attribute \src "libresoc.v:180099.3-180138.6" + wire width 4 $3\src12__data_o$next[3:0]$11024 + attribute \src "libresoc.v:180196.3-180235.6" + wire width 4 $3\src22__data_o$next[3:0]$11039 + attribute \src "libresoc.v:180266.3-180305.6" + wire width 4 $3\src32__data_o$next[3:0]$11053 + attribute \src "libresoc.v:180376.3-180405.6" + wire $3\wr_detect$10[0:0]$11075 + attribute \src "libresoc.v:180446.3-180475.6" + wire $3\wr_detect$13[0:0]$11089 + attribute \src "libresoc.v:180236.3-180265.6" + wire $3\wr_detect$4[0:0]$11047 + attribute \src "libresoc.v:180306.3-180335.6" + wire $3\wr_detect$7[0:0]$11061 + attribute \src "libresoc.v:180139.3-180168.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180658.3-180697.6" - wire width 4 $4\r22__data_o$next[3:0]$11088 - attribute \src "libresoc.v:180588.3-180627.6" - wire width 4 $4\r2__data_o$next[3:0]$11074 - attribute \src "libresoc.v:180421.3-180447.6" - wire width 4 $4\reg$next[3:0]$11040 - attribute \src "libresoc.v:180351.3-180390.6" - wire width 4 $4\src12__data_o$next[3:0]$11031 - attribute \src "libresoc.v:180448.3-180487.6" - wire width 4 $4\src22__data_o$next[3:0]$11046 - attribute \src "libresoc.v:180518.3-180557.6" - wire width 4 $4\src32__data_o$next[3:0]$11060 - attribute \src "libresoc.v:180628.3-180657.6" - wire $4\wr_detect$10[0:0]$11082 - attribute \src "libresoc.v:180698.3-180727.6" - wire $4\wr_detect$13[0:0]$11096 - attribute \src "libresoc.v:180488.3-180517.6" - wire $4\wr_detect$4[0:0]$11054 - attribute \src "libresoc.v:180558.3-180587.6" - wire $4\wr_detect$7[0:0]$11068 - attribute \src "libresoc.v:180391.3-180420.6" + attribute \src "libresoc.v:180406.3-180445.6" + wire width 4 $4\r22__data_o$next[3:0]$11082 + attribute \src "libresoc.v:180336.3-180375.6" + wire width 4 $4\r2__data_o$next[3:0]$11068 + attribute \src "libresoc.v:180169.3-180195.6" + wire width 4 $4\reg$next[3:0]$11034 + attribute \src "libresoc.v:180099.3-180138.6" + wire width 4 $4\src12__data_o$next[3:0]$11025 + attribute \src "libresoc.v:180196.3-180235.6" + wire width 4 $4\src22__data_o$next[3:0]$11040 + attribute \src "libresoc.v:180266.3-180305.6" + wire width 4 $4\src32__data_o$next[3:0]$11054 + attribute \src "libresoc.v:180376.3-180405.6" + wire $4\wr_detect$10[0:0]$11076 + attribute \src "libresoc.v:180446.3-180475.6" + wire $4\wr_detect$13[0:0]$11090 + attribute \src "libresoc.v:180236.3-180265.6" + wire $4\wr_detect$4[0:0]$11048 + attribute \src "libresoc.v:180306.3-180335.6" + wire $4\wr_detect$7[0:0]$11062 + attribute \src "libresoc.v:180139.3-180168.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180658.3-180697.6" - wire width 4 $5\r22__data_o$next[3:0]$11089 - attribute \src "libresoc.v:180588.3-180627.6" - wire width 4 $5\r2__data_o$next[3:0]$11075 - attribute \src "libresoc.v:180351.3-180390.6" - wire width 4 $5\src12__data_o$next[3:0]$11032 - attribute \src "libresoc.v:180448.3-180487.6" - wire width 4 $5\src22__data_o$next[3:0]$11047 - attribute \src "libresoc.v:180518.3-180557.6" - wire width 4 $5\src32__data_o$next[3:0]$11061 - attribute \src "libresoc.v:180658.3-180697.6" - wire width 4 $6\r22__data_o$next[3:0]$11090 - attribute \src "libresoc.v:180588.3-180627.6" - wire width 4 $6\r2__data_o$next[3:0]$11076 - attribute \src "libresoc.v:180351.3-180390.6" - wire width 4 $6\src12__data_o$next[3:0]$11033 - attribute \src "libresoc.v:180448.3-180487.6" - wire width 4 $6\src22__data_o$next[3:0]$11048 - attribute \src "libresoc.v:180518.3-180557.6" - wire width 4 $6\src32__data_o$next[3:0]$11062 - attribute \src "libresoc.v:180334.17-180334.104" - wire $not$libresoc.v:180334$11015_Y - attribute \src "libresoc.v:180335.18-180335.105" - wire $not$libresoc.v:180335$11016_Y - attribute \src "libresoc.v:180336.17-180336.100" - wire $not$libresoc.v:180336$11017_Y - attribute \src "libresoc.v:180337.17-180337.103" - wire $not$libresoc.v:180337$11018_Y - attribute \src "libresoc.v:180338.17-180338.103" - wire $not$libresoc.v:180338$11019_Y + attribute \src "libresoc.v:180406.3-180445.6" + wire width 4 $5\r22__data_o$next[3:0]$11083 + attribute \src "libresoc.v:180336.3-180375.6" + wire width 4 $5\r2__data_o$next[3:0]$11069 + attribute \src "libresoc.v:180099.3-180138.6" + wire width 4 $5\src12__data_o$next[3:0]$11026 + attribute \src "libresoc.v:180196.3-180235.6" + wire width 4 $5\src22__data_o$next[3:0]$11041 + attribute \src "libresoc.v:180266.3-180305.6" + wire width 4 $5\src32__data_o$next[3:0]$11055 + attribute \src "libresoc.v:180406.3-180445.6" + wire width 4 $6\r22__data_o$next[3:0]$11084 + attribute \src "libresoc.v:180336.3-180375.6" + wire width 4 $6\r2__data_o$next[3:0]$11070 + attribute \src "libresoc.v:180099.3-180138.6" + wire width 4 $6\src12__data_o$next[3:0]$11027 + attribute \src "libresoc.v:180196.3-180235.6" + wire width 4 $6\src22__data_o$next[3:0]$11042 + attribute \src "libresoc.v:180266.3-180305.6" + wire width 4 $6\src32__data_o$next[3:0]$11056 + attribute \src "libresoc.v:180082.17-180082.104" + wire $not$libresoc.v:180082$11009_Y + attribute \src "libresoc.v:180083.18-180083.105" + wire $not$libresoc.v:180083$11010_Y + attribute \src "libresoc.v:180084.17-180084.100" + wire $not$libresoc.v:180084$11011_Y + attribute \src "libresoc.v:180085.17-180085.103" + wire $not$libresoc.v:180085$11012_Y + attribute \src "libresoc.v:180086.17-180086.103" + wire $not$libresoc.v:180086$11013_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -335383,9 +335089,9 @@ module \reg_2 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest12__data_i @@ -335395,7 +335101,7 @@ module \reg_2 wire width 4 input 11 \dest22__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest22__wen - attribute \src "libresoc.v:180258.7-180258.15" + attribute \src "libresoc.v:180006.7-180006.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r22__data_o @@ -335446,152 +335152,152 @@ module \reg_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180334$11015 + cell $not $not$libresoc.v:180082$11009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180334$11015_Y + connect \Y $not$libresoc.v:180082$11009_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180335$11016 + cell $not $not$libresoc.v:180083$11010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:180335$11016_Y + connect \Y $not$libresoc.v:180083$11010_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180336$11017 + cell $not $not$libresoc.v:180084$11011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180336$11017_Y + connect \Y $not$libresoc.v:180084$11011_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180337$11018 + cell $not $not$libresoc.v:180085$11012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180337$11018_Y + connect \Y $not$libresoc.v:180085$11012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180338$11019 + cell $not $not$libresoc.v:180086$11013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180338$11019_Y + connect \Y $not$libresoc.v:180086$11013_Y end - attribute \src "libresoc.v:180258.7-180258.20" - process $proc$libresoc.v:180258$11097 + attribute \src "libresoc.v:180006.7-180006.20" + process $proc$libresoc.v:180006$11091 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180283.13-180283.31" - process $proc$libresoc.v:180283$11098 + attribute \src "libresoc.v:180031.13-180031.31" + process $proc$libresoc.v:180031$11092 assign { } { } assign $1\r22__data_o[3:0] 4'0000 sync always sync init update \r22__data_o $1\r22__data_o[3:0] end - attribute \src "libresoc.v:180290.13-180290.30" - process $proc$libresoc.v:180290$11099 + attribute \src "libresoc.v:180038.13-180038.30" + process $proc$libresoc.v:180038$11093 assign { } { } assign $1\r2__data_o[3:0] 4'0000 sync always sync init update \r2__data_o $1\r2__data_o[3:0] end - attribute \src "libresoc.v:180296.13-180296.25" - process $proc$libresoc.v:180296$11100 + attribute \src "libresoc.v:180044.13-180044.25" + process $proc$libresoc.v:180044$11094 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:180301.13-180301.33" - process $proc$libresoc.v:180301$11101 + attribute \src "libresoc.v:180049.13-180049.33" + process $proc$libresoc.v:180049$11095 assign { } { } assign $1\src12__data_o[3:0] 4'0000 sync always sync init update \src12__data_o $1\src12__data_o[3:0] end - attribute \src "libresoc.v:180308.13-180308.33" - process $proc$libresoc.v:180308$11102 + attribute \src "libresoc.v:180056.13-180056.33" + process $proc$libresoc.v:180056$11096 assign { } { } assign $1\src22__data_o[3:0] 4'0000 sync always sync init update \src22__data_o $1\src22__data_o[3:0] end - attribute \src "libresoc.v:180315.13-180315.33" - process $proc$libresoc.v:180315$11103 + attribute \src "libresoc.v:180063.13-180063.33" + process $proc$libresoc.v:180063$11097 assign { } { } assign $1\src32__data_o[3:0] 4'0000 sync always sync init update \src32__data_o $1\src32__data_o[3:0] end - attribute \src "libresoc.v:180339.3-180340.25" - process $proc$libresoc.v:180339$11020 + attribute \src "libresoc.v:180087.3-180088.25" + process $proc$libresoc.v:180087$11014 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:180341.3-180342.39" - process $proc$libresoc.v:180341$11021 + attribute \src "libresoc.v:180089.3-180090.39" + process $proc$libresoc.v:180089$11015 assign { } { } assign $0\r22__data_o[3:0] \r22__data_o$next sync posedge \coresync_clk update \r22__data_o $0\r22__data_o[3:0] end - attribute \src "libresoc.v:180343.3-180344.37" - process $proc$libresoc.v:180343$11022 + attribute \src "libresoc.v:180091.3-180092.37" + process $proc$libresoc.v:180091$11016 assign { } { } assign $0\r2__data_o[3:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[3:0] end - attribute \src "libresoc.v:180345.3-180346.43" - process $proc$libresoc.v:180345$11023 + attribute \src "libresoc.v:180093.3-180094.43" + process $proc$libresoc.v:180093$11017 assign { } { } assign $0\src32__data_o[3:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[3:0] end - attribute \src "libresoc.v:180347.3-180348.43" - process $proc$libresoc.v:180347$11024 + attribute \src "libresoc.v:180095.3-180096.43" + process $proc$libresoc.v:180095$11018 assign { } { } assign $0\src22__data_o[3:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[3:0] end - attribute \src "libresoc.v:180349.3-180350.43" - process $proc$libresoc.v:180349$11025 + attribute \src "libresoc.v:180097.3-180098.43" + process $proc$libresoc.v:180097$11019 assign { } { } assign $0\src12__data_o[3:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[3:0] end - attribute \src "libresoc.v:180351.3-180390.6" - process $proc$libresoc.v:180351$11026 + attribute \src "libresoc.v:180099.3-180138.6" + process $proc$libresoc.v:180099$11020 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[3:0]$11027 $6\src12__data_o$next[3:0]$11033 - attribute \src "libresoc.v:180352.5-180352.29" + assign $0\src12__data_o$next[3:0]$11021 $6\src12__data_o$next[3:0]$11027 + attribute \src "libresoc.v:180100.5-180100.29" switch \initial - attribute \src "libresoc.v:180352.9-180352.17" + attribute \src "libresoc.v:180100.9-180100.17" case 1'1 case end @@ -335603,66 +335309,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[3:0]$11028 $5\src12__data_o$next[3:0]$11032 + assign $1\src12__data_o$next[3:0]$11022 $5\src12__data_o$next[3:0]$11026 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[3:0]$11029 \dest12__data_i + assign $2\src12__data_o$next[3:0]$11023 \dest12__data_i case - assign $2\src12__data_o$next[3:0]$11029 4'0000 + assign $2\src12__data_o$next[3:0]$11023 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[3:0]$11030 \dest22__data_i + assign $3\src12__data_o$next[3:0]$11024 \dest22__data_i case - assign $3\src12__data_o$next[3:0]$11030 $2\src12__data_o$next[3:0]$11029 + assign $3\src12__data_o$next[3:0]$11024 $2\src12__data_o$next[3:0]$11023 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[3:0]$11031 \w2__data_i + assign $4\src12__data_o$next[3:0]$11025 \w2__data_i case - assign $4\src12__data_o$next[3:0]$11031 $3\src12__data_o$next[3:0]$11030 + assign $4\src12__data_o$next[3:0]$11025 $3\src12__data_o$next[3:0]$11024 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[3:0]$11032 \reg + assign $5\src12__data_o$next[3:0]$11026 \reg case - assign $5\src12__data_o$next[3:0]$11032 $4\src12__data_o$next[3:0]$11031 + assign $5\src12__data_o$next[3:0]$11026 $4\src12__data_o$next[3:0]$11025 end case - assign $1\src12__data_o$next[3:0]$11028 4'0000 + assign $1\src12__data_o$next[3:0]$11022 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[3:0]$11033 4'0000 + assign $6\src12__data_o$next[3:0]$11027 4'0000 case - assign $6\src12__data_o$next[3:0]$11033 $1\src12__data_o$next[3:0]$11028 + assign $6\src12__data_o$next[3:0]$11027 $1\src12__data_o$next[3:0]$11022 end sync always - update \src12__data_o$next $0\src12__data_o$next[3:0]$11027 + update \src12__data_o$next $0\src12__data_o$next[3:0]$11021 end - attribute \src "libresoc.v:180391.3-180420.6" - process $proc$libresoc.v:180391$11034 + attribute \src "libresoc.v:180139.3-180168.6" + process $proc$libresoc.v:180139$11028 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180392.5-180392.29" + attribute \src "libresoc.v:180140.5-180140.29" switch \initial - attribute \src "libresoc.v:180392.9-180392.17" + attribute \src "libresoc.v:180140.9-180140.17" case 1'1 case end @@ -335708,17 +335414,17 @@ module \reg_2 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180421.3-180447.6" - process $proc$libresoc.v:180421$11035 + attribute \src "libresoc.v:180169.3-180195.6" + process $proc$libresoc.v:180169$11029 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11036 $4\reg$next[3:0]$11040 - attribute \src "libresoc.v:180422.5-180422.29" + assign $0\reg$next[3:0]$11030 $4\reg$next[3:0]$11034 + attribute \src "libresoc.v:180170.5-180170.29" switch \initial - attribute \src "libresoc.v:180422.9-180422.17" + attribute \src "libresoc.v:180170.9-180170.17" case 1'1 case end @@ -335727,49 +335433,49 @@ module \reg_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11037 \dest12__data_i + assign $1\reg$next[3:0]$11031 \dest12__data_i case - assign $1\reg$next[3:0]$11037 \reg + assign $1\reg$next[3:0]$11031 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11038 \dest22__data_i + assign $2\reg$next[3:0]$11032 \dest22__data_i case - assign $2\reg$next[3:0]$11038 $1\reg$next[3:0]$11037 + assign $2\reg$next[3:0]$11032 $1\reg$next[3:0]$11031 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11039 \w2__data_i + assign $3\reg$next[3:0]$11033 \w2__data_i case - assign $3\reg$next[3:0]$11039 $2\reg$next[3:0]$11038 + assign $3\reg$next[3:0]$11033 $2\reg$next[3:0]$11032 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11040 4'0000 + assign $4\reg$next[3:0]$11034 4'0000 case - assign $4\reg$next[3:0]$11040 $3\reg$next[3:0]$11039 + assign $4\reg$next[3:0]$11034 $3\reg$next[3:0]$11033 end sync always - update \reg$next $0\reg$next[3:0]$11036 + update \reg$next $0\reg$next[3:0]$11030 end - attribute \src "libresoc.v:180448.3-180487.6" - process $proc$libresoc.v:180448$11041 + attribute \src "libresoc.v:180196.3-180235.6" + process $proc$libresoc.v:180196$11035 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[3:0]$11042 $6\src22__data_o$next[3:0]$11048 - attribute \src "libresoc.v:180449.5-180449.29" + assign $0\src22__data_o$next[3:0]$11036 $6\src22__data_o$next[3:0]$11042 + attribute \src "libresoc.v:180197.5-180197.29" switch \initial - attribute \src "libresoc.v:180449.9-180449.17" + attribute \src "libresoc.v:180197.9-180197.17" case 1'1 case end @@ -335781,66 +335487,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[3:0]$11043 $5\src22__data_o$next[3:0]$11047 + assign $1\src22__data_o$next[3:0]$11037 $5\src22__data_o$next[3:0]$11041 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[3:0]$11044 \dest12__data_i + assign $2\src22__data_o$next[3:0]$11038 \dest12__data_i case - assign $2\src22__data_o$next[3:0]$11044 4'0000 + assign $2\src22__data_o$next[3:0]$11038 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[3:0]$11045 \dest22__data_i + assign $3\src22__data_o$next[3:0]$11039 \dest22__data_i case - assign $3\src22__data_o$next[3:0]$11045 $2\src22__data_o$next[3:0]$11044 + assign $3\src22__data_o$next[3:0]$11039 $2\src22__data_o$next[3:0]$11038 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[3:0]$11046 \w2__data_i + assign $4\src22__data_o$next[3:0]$11040 \w2__data_i case - assign $4\src22__data_o$next[3:0]$11046 $3\src22__data_o$next[3:0]$11045 + assign $4\src22__data_o$next[3:0]$11040 $3\src22__data_o$next[3:0]$11039 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[3:0]$11047 \reg + assign $5\src22__data_o$next[3:0]$11041 \reg case - assign $5\src22__data_o$next[3:0]$11047 $4\src22__data_o$next[3:0]$11046 + assign $5\src22__data_o$next[3:0]$11041 $4\src22__data_o$next[3:0]$11040 end case - assign $1\src22__data_o$next[3:0]$11043 4'0000 + assign $1\src22__data_o$next[3:0]$11037 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[3:0]$11048 4'0000 + assign $6\src22__data_o$next[3:0]$11042 4'0000 case - assign $6\src22__data_o$next[3:0]$11048 $1\src22__data_o$next[3:0]$11043 + assign $6\src22__data_o$next[3:0]$11042 $1\src22__data_o$next[3:0]$11037 end sync always - update \src22__data_o$next $0\src22__data_o$next[3:0]$11042 + update \src22__data_o$next $0\src22__data_o$next[3:0]$11036 end - attribute \src "libresoc.v:180488.3-180517.6" - process $proc$libresoc.v:180488$11049 + attribute \src "libresoc.v:180236.3-180265.6" + process $proc$libresoc.v:180236$11043 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11050 $1\wr_detect$4[0:0]$11051 - attribute \src "libresoc.v:180489.5-180489.29" + assign $0\wr_detect$4[0:0]$11044 $1\wr_detect$4[0:0]$11045 + attribute \src "libresoc.v:180237.5-180237.29" switch \initial - attribute \src "libresoc.v:180489.9-180489.17" + attribute \src "libresoc.v:180237.9-180237.17" case 1'1 case end @@ -335852,49 +335558,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11051 $4\wr_detect$4[0:0]$11054 + assign $1\wr_detect$4[0:0]$11045 $4\wr_detect$4[0:0]$11048 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11052 1'1 + assign $2\wr_detect$4[0:0]$11046 1'1 case - assign $2\wr_detect$4[0:0]$11052 1'0 + assign $2\wr_detect$4[0:0]$11046 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11053 1'1 + assign $3\wr_detect$4[0:0]$11047 1'1 case - assign $3\wr_detect$4[0:0]$11053 $2\wr_detect$4[0:0]$11052 + assign $3\wr_detect$4[0:0]$11047 $2\wr_detect$4[0:0]$11046 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11054 1'1 + assign $4\wr_detect$4[0:0]$11048 1'1 case - assign $4\wr_detect$4[0:0]$11054 $3\wr_detect$4[0:0]$11053 + assign $4\wr_detect$4[0:0]$11048 $3\wr_detect$4[0:0]$11047 end case - assign $1\wr_detect$4[0:0]$11051 1'0 + assign $1\wr_detect$4[0:0]$11045 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11050 + update \wr_detect$4 $0\wr_detect$4[0:0]$11044 end - attribute \src "libresoc.v:180518.3-180557.6" - process $proc$libresoc.v:180518$11055 + attribute \src "libresoc.v:180266.3-180305.6" + process $proc$libresoc.v:180266$11049 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[3:0]$11056 $6\src32__data_o$next[3:0]$11062 - attribute \src "libresoc.v:180519.5-180519.29" + assign $0\src32__data_o$next[3:0]$11050 $6\src32__data_o$next[3:0]$11056 + attribute \src "libresoc.v:180267.5-180267.29" switch \initial - attribute \src "libresoc.v:180519.9-180519.17" + attribute \src "libresoc.v:180267.9-180267.17" case 1'1 case end @@ -335906,66 +335612,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[3:0]$11057 $5\src32__data_o$next[3:0]$11061 + assign $1\src32__data_o$next[3:0]$11051 $5\src32__data_o$next[3:0]$11055 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[3:0]$11058 \dest12__data_i + assign $2\src32__data_o$next[3:0]$11052 \dest12__data_i case - assign $2\src32__data_o$next[3:0]$11058 4'0000 + assign $2\src32__data_o$next[3:0]$11052 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[3:0]$11059 \dest22__data_i + assign $3\src32__data_o$next[3:0]$11053 \dest22__data_i case - assign $3\src32__data_o$next[3:0]$11059 $2\src32__data_o$next[3:0]$11058 + assign $3\src32__data_o$next[3:0]$11053 $2\src32__data_o$next[3:0]$11052 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[3:0]$11060 \w2__data_i + assign $4\src32__data_o$next[3:0]$11054 \w2__data_i case - assign $4\src32__data_o$next[3:0]$11060 $3\src32__data_o$next[3:0]$11059 + assign $4\src32__data_o$next[3:0]$11054 $3\src32__data_o$next[3:0]$11053 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[3:0]$11061 \reg + assign $5\src32__data_o$next[3:0]$11055 \reg case - assign $5\src32__data_o$next[3:0]$11061 $4\src32__data_o$next[3:0]$11060 + assign $5\src32__data_o$next[3:0]$11055 $4\src32__data_o$next[3:0]$11054 end case - assign $1\src32__data_o$next[3:0]$11057 4'0000 + assign $1\src32__data_o$next[3:0]$11051 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[3:0]$11062 4'0000 + assign $6\src32__data_o$next[3:0]$11056 4'0000 case - assign $6\src32__data_o$next[3:0]$11062 $1\src32__data_o$next[3:0]$11057 + assign $6\src32__data_o$next[3:0]$11056 $1\src32__data_o$next[3:0]$11051 end sync always - update \src32__data_o$next $0\src32__data_o$next[3:0]$11056 + update \src32__data_o$next $0\src32__data_o$next[3:0]$11050 end - attribute \src "libresoc.v:180558.3-180587.6" - process $proc$libresoc.v:180558$11063 + attribute \src "libresoc.v:180306.3-180335.6" + process $proc$libresoc.v:180306$11057 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11064 $1\wr_detect$7[0:0]$11065 - attribute \src "libresoc.v:180559.5-180559.29" + assign $0\wr_detect$7[0:0]$11058 $1\wr_detect$7[0:0]$11059 + attribute \src "libresoc.v:180307.5-180307.29" switch \initial - attribute \src "libresoc.v:180559.9-180559.17" + attribute \src "libresoc.v:180307.9-180307.17" case 1'1 case end @@ -335977,49 +335683,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11065 $4\wr_detect$7[0:0]$11068 + assign $1\wr_detect$7[0:0]$11059 $4\wr_detect$7[0:0]$11062 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11066 1'1 + assign $2\wr_detect$7[0:0]$11060 1'1 case - assign $2\wr_detect$7[0:0]$11066 1'0 + assign $2\wr_detect$7[0:0]$11060 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11067 1'1 + assign $3\wr_detect$7[0:0]$11061 1'1 case - assign $3\wr_detect$7[0:0]$11067 $2\wr_detect$7[0:0]$11066 + assign $3\wr_detect$7[0:0]$11061 $2\wr_detect$7[0:0]$11060 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11068 1'1 + assign $4\wr_detect$7[0:0]$11062 1'1 case - assign $4\wr_detect$7[0:0]$11068 $3\wr_detect$7[0:0]$11067 + assign $4\wr_detect$7[0:0]$11062 $3\wr_detect$7[0:0]$11061 end case - assign $1\wr_detect$7[0:0]$11065 1'0 + assign $1\wr_detect$7[0:0]$11059 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11064 + update \wr_detect$7 $0\wr_detect$7[0:0]$11058 end - attribute \src "libresoc.v:180588.3-180627.6" - process $proc$libresoc.v:180588$11069 + attribute \src "libresoc.v:180336.3-180375.6" + process $proc$libresoc.v:180336$11063 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[3:0]$11070 $6\r2__data_o$next[3:0]$11076 - attribute \src "libresoc.v:180589.5-180589.29" + assign $0\r2__data_o$next[3:0]$11064 $6\r2__data_o$next[3:0]$11070 + attribute \src "libresoc.v:180337.5-180337.29" switch \initial - attribute \src "libresoc.v:180589.9-180589.17" + attribute \src "libresoc.v:180337.9-180337.17" case 1'1 case end @@ -336031,66 +335737,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[3:0]$11071 $5\r2__data_o$next[3:0]$11075 + assign $1\r2__data_o$next[3:0]$11065 $5\r2__data_o$next[3:0]$11069 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[3:0]$11072 \dest12__data_i + assign $2\r2__data_o$next[3:0]$11066 \dest12__data_i case - assign $2\r2__data_o$next[3:0]$11072 4'0000 + assign $2\r2__data_o$next[3:0]$11066 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[3:0]$11073 \dest22__data_i + assign $3\r2__data_o$next[3:0]$11067 \dest22__data_i case - assign $3\r2__data_o$next[3:0]$11073 $2\r2__data_o$next[3:0]$11072 + assign $3\r2__data_o$next[3:0]$11067 $2\r2__data_o$next[3:0]$11066 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[3:0]$11074 \w2__data_i + assign $4\r2__data_o$next[3:0]$11068 \w2__data_i case - assign $4\r2__data_o$next[3:0]$11074 $3\r2__data_o$next[3:0]$11073 + assign $4\r2__data_o$next[3:0]$11068 $3\r2__data_o$next[3:0]$11067 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[3:0]$11075 \reg + assign $5\r2__data_o$next[3:0]$11069 \reg case - assign $5\r2__data_o$next[3:0]$11075 $4\r2__data_o$next[3:0]$11074 + assign $5\r2__data_o$next[3:0]$11069 $4\r2__data_o$next[3:0]$11068 end case - assign $1\r2__data_o$next[3:0]$11071 4'0000 + assign $1\r2__data_o$next[3:0]$11065 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[3:0]$11076 4'0000 + assign $6\r2__data_o$next[3:0]$11070 4'0000 case - assign $6\r2__data_o$next[3:0]$11076 $1\r2__data_o$next[3:0]$11071 + assign $6\r2__data_o$next[3:0]$11070 $1\r2__data_o$next[3:0]$11065 end sync always - update \r2__data_o$next $0\r2__data_o$next[3:0]$11070 + update \r2__data_o$next $0\r2__data_o$next[3:0]$11064 end - attribute \src "libresoc.v:180628.3-180657.6" - process $proc$libresoc.v:180628$11077 + attribute \src "libresoc.v:180376.3-180405.6" + process $proc$libresoc.v:180376$11071 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11078 $1\wr_detect$10[0:0]$11079 - attribute \src "libresoc.v:180629.5-180629.29" + assign $0\wr_detect$10[0:0]$11072 $1\wr_detect$10[0:0]$11073 + attribute \src "libresoc.v:180377.5-180377.29" switch \initial - attribute \src "libresoc.v:180629.9-180629.17" + attribute \src "libresoc.v:180377.9-180377.17" case 1'1 case end @@ -336102,49 +335808,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11079 $4\wr_detect$10[0:0]$11082 + assign $1\wr_detect$10[0:0]$11073 $4\wr_detect$10[0:0]$11076 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11080 1'1 + assign $2\wr_detect$10[0:0]$11074 1'1 case - assign $2\wr_detect$10[0:0]$11080 1'0 + assign $2\wr_detect$10[0:0]$11074 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11081 1'1 + assign $3\wr_detect$10[0:0]$11075 1'1 case - assign $3\wr_detect$10[0:0]$11081 $2\wr_detect$10[0:0]$11080 + assign $3\wr_detect$10[0:0]$11075 $2\wr_detect$10[0:0]$11074 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11082 1'1 + assign $4\wr_detect$10[0:0]$11076 1'1 case - assign $4\wr_detect$10[0:0]$11082 $3\wr_detect$10[0:0]$11081 + assign $4\wr_detect$10[0:0]$11076 $3\wr_detect$10[0:0]$11075 end case - assign $1\wr_detect$10[0:0]$11079 1'0 + assign $1\wr_detect$10[0:0]$11073 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11078 + update \wr_detect$10 $0\wr_detect$10[0:0]$11072 end - attribute \src "libresoc.v:180658.3-180697.6" - process $proc$libresoc.v:180658$11083 + attribute \src "libresoc.v:180406.3-180445.6" + process $proc$libresoc.v:180406$11077 assign { } { } assign { } { } assign { } { } - assign $0\r22__data_o$next[3:0]$11084 $6\r22__data_o$next[3:0]$11090 - attribute \src "libresoc.v:180659.5-180659.29" + assign $0\r22__data_o$next[3:0]$11078 $6\r22__data_o$next[3:0]$11084 + attribute \src "libresoc.v:180407.5-180407.29" switch \initial - attribute \src "libresoc.v:180659.9-180659.17" + attribute \src "libresoc.v:180407.9-180407.17" case 1'1 case end @@ -336156,66 +335862,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r22__data_o$next[3:0]$11085 $5\r22__data_o$next[3:0]$11089 + assign $1\r22__data_o$next[3:0]$11079 $5\r22__data_o$next[3:0]$11083 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r22__data_o$next[3:0]$11086 \dest12__data_i + assign $2\r22__data_o$next[3:0]$11080 \dest12__data_i case - assign $2\r22__data_o$next[3:0]$11086 4'0000 + assign $2\r22__data_o$next[3:0]$11080 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r22__data_o$next[3:0]$11087 \dest22__data_i + assign $3\r22__data_o$next[3:0]$11081 \dest22__data_i case - assign $3\r22__data_o$next[3:0]$11087 $2\r22__data_o$next[3:0]$11086 + assign $3\r22__data_o$next[3:0]$11081 $2\r22__data_o$next[3:0]$11080 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r22__data_o$next[3:0]$11088 \w2__data_i + assign $4\r22__data_o$next[3:0]$11082 \w2__data_i case - assign $4\r22__data_o$next[3:0]$11088 $3\r22__data_o$next[3:0]$11087 + assign $4\r22__data_o$next[3:0]$11082 $3\r22__data_o$next[3:0]$11081 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r22__data_o$next[3:0]$11089 \reg + assign $5\r22__data_o$next[3:0]$11083 \reg case - assign $5\r22__data_o$next[3:0]$11089 $4\r22__data_o$next[3:0]$11088 + assign $5\r22__data_o$next[3:0]$11083 $4\r22__data_o$next[3:0]$11082 end case - assign $1\r22__data_o$next[3:0]$11085 4'0000 + assign $1\r22__data_o$next[3:0]$11079 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r22__data_o$next[3:0]$11090 4'0000 + assign $6\r22__data_o$next[3:0]$11084 4'0000 case - assign $6\r22__data_o$next[3:0]$11090 $1\r22__data_o$next[3:0]$11085 + assign $6\r22__data_o$next[3:0]$11084 $1\r22__data_o$next[3:0]$11079 end sync always - update \r22__data_o$next $0\r22__data_o$next[3:0]$11084 + update \r22__data_o$next $0\r22__data_o$next[3:0]$11078 end - attribute \src "libresoc.v:180698.3-180727.6" - process $proc$libresoc.v:180698$11091 + attribute \src "libresoc.v:180446.3-180475.6" + process $proc$libresoc.v:180446$11085 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11092 $1\wr_detect$13[0:0]$11093 - attribute \src "libresoc.v:180699.5-180699.29" + assign $0\wr_detect$13[0:0]$11086 $1\wr_detect$13[0:0]$11087 + attribute \src "libresoc.v:180447.5-180447.29" switch \initial - attribute \src "libresoc.v:180699.9-180699.17" + attribute \src "libresoc.v:180447.9-180447.17" case 1'1 case end @@ -336227,205 +335933,205 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11093 $4\wr_detect$13[0:0]$11096 + assign $1\wr_detect$13[0:0]$11087 $4\wr_detect$13[0:0]$11090 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11094 1'1 + assign $2\wr_detect$13[0:0]$11088 1'1 case - assign $2\wr_detect$13[0:0]$11094 1'0 + assign $2\wr_detect$13[0:0]$11088 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11095 1'1 + assign $3\wr_detect$13[0:0]$11089 1'1 case - assign $3\wr_detect$13[0:0]$11095 $2\wr_detect$13[0:0]$11094 + assign $3\wr_detect$13[0:0]$11089 $2\wr_detect$13[0:0]$11088 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11096 1'1 + assign $4\wr_detect$13[0:0]$11090 1'1 case - assign $4\wr_detect$13[0:0]$11096 $3\wr_detect$13[0:0]$11095 + assign $4\wr_detect$13[0:0]$11090 $3\wr_detect$13[0:0]$11089 end case - assign $1\wr_detect$13[0:0]$11093 1'0 + assign $1\wr_detect$13[0:0]$11087 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11092 + update \wr_detect$13 $0\wr_detect$13[0:0]$11086 end - connect \$9 $not$libresoc.v:180334$11015_Y - connect \$12 $not$libresoc.v:180335$11016_Y - connect \$1 $not$libresoc.v:180336$11017_Y - connect \$3 $not$libresoc.v:180337$11018_Y - connect \$6 $not$libresoc.v:180338$11019_Y + connect \$9 $not$libresoc.v:180082$11009_Y + connect \$12 $not$libresoc.v:180083$11010_Y + connect \$1 $not$libresoc.v:180084$11011_Y + connect \$3 $not$libresoc.v:180085$11012_Y + connect \$6 $not$libresoc.v:180086$11013_Y end -attribute \src "libresoc.v:180732.1-181177.10" +attribute \src "libresoc.v:180480.1-180925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" attribute \generator "nMigen" module \reg_2$134 - attribute \src "libresoc.v:180733.7-180733.20" + attribute \src "libresoc.v:180481.7-180481.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181062.3-181107.6" - wire width 2 $0\r2__data_o$next[1:0]$11156 - attribute \src "libresoc.v:180808.3-180809.37" + attribute \src "libresoc.v:180810.3-180855.6" + wire width 2 $0\r2__data_o$next[1:0]$11150 + attribute \src "libresoc.v:180556.3-180557.37" wire width 2 $0\r2__data_o[1:0] - attribute \src "libresoc.v:181144.3-181176.6" - wire width 2 $0\reg$next[1:0]$11172 - attribute \src "libresoc.v:180806.3-180807.25" + attribute \src "libresoc.v:180892.3-180924.6" + wire width 2 $0\reg$next[1:0]$11166 + attribute \src "libresoc.v:180554.3-180555.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:180816.3-180861.6" - wire width 2 $0\src12__data_o$next[1:0]$11114 - attribute \src "libresoc.v:180814.3-180815.43" + attribute \src "libresoc.v:180564.3-180609.6" + wire width 2 $0\src12__data_o$next[1:0]$11108 + attribute \src "libresoc.v:180562.3-180563.43" wire width 2 $0\src12__data_o[1:0] - attribute \src "libresoc.v:180898.3-180943.6" - wire width 2 $0\src22__data_o$next[1:0]$11124 - attribute \src "libresoc.v:180812.3-180813.43" + attribute \src "libresoc.v:180646.3-180691.6" + wire width 2 $0\src22__data_o$next[1:0]$11118 + attribute \src "libresoc.v:180560.3-180561.43" wire width 2 $0\src22__data_o[1:0] - attribute \src "libresoc.v:180980.3-181025.6" - wire width 2 $0\src32__data_o$next[1:0]$11140 - attribute \src "libresoc.v:180810.3-180811.43" + attribute \src "libresoc.v:180728.3-180773.6" + wire width 2 $0\src32__data_o$next[1:0]$11134 + attribute \src "libresoc.v:180558.3-180559.43" wire width 2 $0\src32__data_o[1:0] - attribute \src "libresoc.v:181108.3-181143.6" - wire $0\wr_detect$10[0:0]$11165 - attribute \src "libresoc.v:180944.3-180979.6" - wire $0\wr_detect$4[0:0]$11133 - attribute \src "libresoc.v:181026.3-181061.6" - wire $0\wr_detect$7[0:0]$11149 - attribute \src "libresoc.v:180862.3-180897.6" + attribute \src "libresoc.v:180856.3-180891.6" + wire $0\wr_detect$10[0:0]$11159 + attribute \src "libresoc.v:180692.3-180727.6" + wire $0\wr_detect$4[0:0]$11127 + attribute \src "libresoc.v:180774.3-180809.6" + wire $0\wr_detect$7[0:0]$11143 + attribute \src "libresoc.v:180610.3-180645.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:181062.3-181107.6" - wire width 2 $1\r2__data_o$next[1:0]$11157 - attribute \src "libresoc.v:180760.13-180760.30" + attribute \src "libresoc.v:180810.3-180855.6" + wire width 2 $1\r2__data_o$next[1:0]$11151 + attribute \src "libresoc.v:180508.13-180508.30" wire width 2 $1\r2__data_o[1:0] - attribute \src "libresoc.v:181144.3-181176.6" - wire width 2 $1\reg$next[1:0]$11173 - attribute \src "libresoc.v:180766.13-180766.25" + attribute \src "libresoc.v:180892.3-180924.6" + wire width 2 $1\reg$next[1:0]$11167 + attribute \src "libresoc.v:180514.13-180514.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:180816.3-180861.6" - wire width 2 $1\src12__data_o$next[1:0]$11115 - attribute \src "libresoc.v:180771.13-180771.33" + attribute \src "libresoc.v:180564.3-180609.6" + wire width 2 $1\src12__data_o$next[1:0]$11109 + attribute \src "libresoc.v:180519.13-180519.33" wire width 2 $1\src12__data_o[1:0] - attribute \src "libresoc.v:180898.3-180943.6" - wire width 2 $1\src22__data_o$next[1:0]$11125 - attribute \src "libresoc.v:180778.13-180778.33" + attribute \src "libresoc.v:180646.3-180691.6" + wire width 2 $1\src22__data_o$next[1:0]$11119 + attribute \src "libresoc.v:180526.13-180526.33" wire width 2 $1\src22__data_o[1:0] - attribute \src "libresoc.v:180980.3-181025.6" - wire width 2 $1\src32__data_o$next[1:0]$11141 - attribute \src "libresoc.v:180785.13-180785.33" + attribute \src "libresoc.v:180728.3-180773.6" + wire width 2 $1\src32__data_o$next[1:0]$11135 + attribute \src "libresoc.v:180533.13-180533.33" wire width 2 $1\src32__data_o[1:0] - attribute \src "libresoc.v:181108.3-181143.6" - wire $1\wr_detect$10[0:0]$11166 - attribute \src "libresoc.v:180944.3-180979.6" - wire $1\wr_detect$4[0:0]$11134 - attribute \src "libresoc.v:181026.3-181061.6" - wire $1\wr_detect$7[0:0]$11150 - attribute \src "libresoc.v:180862.3-180897.6" + attribute \src "libresoc.v:180856.3-180891.6" + wire $1\wr_detect$10[0:0]$11160 + attribute \src "libresoc.v:180692.3-180727.6" + wire $1\wr_detect$4[0:0]$11128 + attribute \src "libresoc.v:180774.3-180809.6" + wire $1\wr_detect$7[0:0]$11144 + attribute \src "libresoc.v:180610.3-180645.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:181062.3-181107.6" - wire width 2 $2\r2__data_o$next[1:0]$11158 - attribute \src "libresoc.v:181144.3-181176.6" - wire width 2 $2\reg$next[1:0]$11174 - attribute \src "libresoc.v:180816.3-180861.6" - wire width 2 $2\src12__data_o$next[1:0]$11116 - attribute \src "libresoc.v:180898.3-180943.6" - wire width 2 $2\src22__data_o$next[1:0]$11126 - attribute \src "libresoc.v:180980.3-181025.6" - wire width 2 $2\src32__data_o$next[1:0]$11142 - attribute \src "libresoc.v:181108.3-181143.6" - wire $2\wr_detect$10[0:0]$11167 - attribute \src "libresoc.v:180944.3-180979.6" - wire $2\wr_detect$4[0:0]$11135 - attribute \src "libresoc.v:181026.3-181061.6" - wire $2\wr_detect$7[0:0]$11151 - attribute \src "libresoc.v:180862.3-180897.6" + attribute \src "libresoc.v:180810.3-180855.6" + wire width 2 $2\r2__data_o$next[1:0]$11152 + attribute \src "libresoc.v:180892.3-180924.6" + wire width 2 $2\reg$next[1:0]$11168 + attribute \src "libresoc.v:180564.3-180609.6" + wire width 2 $2\src12__data_o$next[1:0]$11110 + attribute \src "libresoc.v:180646.3-180691.6" + wire width 2 $2\src22__data_o$next[1:0]$11120 + attribute \src "libresoc.v:180728.3-180773.6" + wire width 2 $2\src32__data_o$next[1:0]$11136 + attribute \src "libresoc.v:180856.3-180891.6" + wire $2\wr_detect$10[0:0]$11161 + attribute \src "libresoc.v:180692.3-180727.6" + wire $2\wr_detect$4[0:0]$11129 + attribute \src "libresoc.v:180774.3-180809.6" + wire $2\wr_detect$7[0:0]$11145 + attribute \src "libresoc.v:180610.3-180645.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:181062.3-181107.6" - wire width 2 $3\r2__data_o$next[1:0]$11159 - attribute \src "libresoc.v:181144.3-181176.6" - wire width 2 $3\reg$next[1:0]$11175 - attribute \src "libresoc.v:180816.3-180861.6" - wire width 2 $3\src12__data_o$next[1:0]$11117 - attribute \src "libresoc.v:180898.3-180943.6" - wire width 2 $3\src22__data_o$next[1:0]$11127 - attribute \src "libresoc.v:180980.3-181025.6" - wire width 2 $3\src32__data_o$next[1:0]$11143 - attribute \src "libresoc.v:181108.3-181143.6" - wire $3\wr_detect$10[0:0]$11168 - attribute \src "libresoc.v:180944.3-180979.6" - wire $3\wr_detect$4[0:0]$11136 - attribute \src "libresoc.v:181026.3-181061.6" - wire $3\wr_detect$7[0:0]$11152 - attribute \src "libresoc.v:180862.3-180897.6" + attribute \src "libresoc.v:180810.3-180855.6" + wire width 2 $3\r2__data_o$next[1:0]$11153 + attribute \src "libresoc.v:180892.3-180924.6" + wire width 2 $3\reg$next[1:0]$11169 + attribute \src "libresoc.v:180564.3-180609.6" + wire width 2 $3\src12__data_o$next[1:0]$11111 + attribute \src "libresoc.v:180646.3-180691.6" + wire width 2 $3\src22__data_o$next[1:0]$11121 + attribute \src "libresoc.v:180728.3-180773.6" + wire width 2 $3\src32__data_o$next[1:0]$11137 + attribute \src "libresoc.v:180856.3-180891.6" + wire $3\wr_detect$10[0:0]$11162 + attribute \src "libresoc.v:180692.3-180727.6" + wire $3\wr_detect$4[0:0]$11130 + attribute \src "libresoc.v:180774.3-180809.6" + wire $3\wr_detect$7[0:0]$11146 + attribute \src "libresoc.v:180610.3-180645.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:181062.3-181107.6" - wire width 2 $4\r2__data_o$next[1:0]$11160 - attribute \src "libresoc.v:181144.3-181176.6" - wire width 2 $4\reg$next[1:0]$11176 - attribute \src "libresoc.v:180816.3-180861.6" - wire width 2 $4\src12__data_o$next[1:0]$11118 - attribute \src "libresoc.v:180898.3-180943.6" - wire width 2 $4\src22__data_o$next[1:0]$11128 - attribute \src "libresoc.v:180980.3-181025.6" - wire width 2 $4\src32__data_o$next[1:0]$11144 - attribute \src "libresoc.v:181108.3-181143.6" - wire $4\wr_detect$10[0:0]$11169 - attribute \src "libresoc.v:180944.3-180979.6" - wire $4\wr_detect$4[0:0]$11137 - attribute \src "libresoc.v:181026.3-181061.6" - wire $4\wr_detect$7[0:0]$11153 - attribute \src "libresoc.v:180862.3-180897.6" + attribute \src "libresoc.v:180810.3-180855.6" + wire width 2 $4\r2__data_o$next[1:0]$11154 + attribute \src "libresoc.v:180892.3-180924.6" + wire width 2 $4\reg$next[1:0]$11170 + attribute \src "libresoc.v:180564.3-180609.6" + wire width 2 $4\src12__data_o$next[1:0]$11112 + attribute \src "libresoc.v:180646.3-180691.6" + wire width 2 $4\src22__data_o$next[1:0]$11122 + attribute \src "libresoc.v:180728.3-180773.6" + wire width 2 $4\src32__data_o$next[1:0]$11138 + attribute \src "libresoc.v:180856.3-180891.6" + wire $4\wr_detect$10[0:0]$11163 + attribute \src "libresoc.v:180692.3-180727.6" + wire $4\wr_detect$4[0:0]$11131 + attribute \src "libresoc.v:180774.3-180809.6" + wire $4\wr_detect$7[0:0]$11147 + attribute \src "libresoc.v:180610.3-180645.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:181062.3-181107.6" - wire width 2 $5\r2__data_o$next[1:0]$11161 - attribute \src "libresoc.v:181144.3-181176.6" - wire width 2 $5\reg$next[1:0]$11177 - attribute \src "libresoc.v:180816.3-180861.6" - wire width 2 $5\src12__data_o$next[1:0]$11119 - attribute \src "libresoc.v:180898.3-180943.6" - wire width 2 $5\src22__data_o$next[1:0]$11129 - attribute \src "libresoc.v:180980.3-181025.6" - wire width 2 $5\src32__data_o$next[1:0]$11145 - attribute \src "libresoc.v:181108.3-181143.6" - wire $5\wr_detect$10[0:0]$11170 - attribute \src "libresoc.v:180944.3-180979.6" - wire $5\wr_detect$4[0:0]$11138 - attribute \src "libresoc.v:181026.3-181061.6" - wire $5\wr_detect$7[0:0]$11154 - attribute \src "libresoc.v:180862.3-180897.6" + attribute \src "libresoc.v:180810.3-180855.6" + wire width 2 $5\r2__data_o$next[1:0]$11155 + attribute \src "libresoc.v:180892.3-180924.6" + wire width 2 $5\reg$next[1:0]$11171 + attribute \src "libresoc.v:180564.3-180609.6" + wire width 2 $5\src12__data_o$next[1:0]$11113 + attribute \src "libresoc.v:180646.3-180691.6" + wire width 2 $5\src22__data_o$next[1:0]$11123 + attribute \src "libresoc.v:180728.3-180773.6" + wire width 2 $5\src32__data_o$next[1:0]$11139 + attribute \src "libresoc.v:180856.3-180891.6" + wire $5\wr_detect$10[0:0]$11164 + attribute \src "libresoc.v:180692.3-180727.6" + wire $5\wr_detect$4[0:0]$11132 + attribute \src "libresoc.v:180774.3-180809.6" + wire $5\wr_detect$7[0:0]$11148 + attribute \src "libresoc.v:180610.3-180645.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:181062.3-181107.6" - wire width 2 $6\r2__data_o$next[1:0]$11162 - attribute \src "libresoc.v:180816.3-180861.6" - wire width 2 $6\src12__data_o$next[1:0]$11120 - attribute \src "libresoc.v:180898.3-180943.6" - wire width 2 $6\src22__data_o$next[1:0]$11130 - attribute \src "libresoc.v:180980.3-181025.6" - wire width 2 $6\src32__data_o$next[1:0]$11146 - attribute \src "libresoc.v:181062.3-181107.6" - wire width 2 $7\r2__data_o$next[1:0]$11163 - attribute \src "libresoc.v:180816.3-180861.6" - wire width 2 $7\src12__data_o$next[1:0]$11121 - attribute \src "libresoc.v:180898.3-180943.6" - wire width 2 $7\src22__data_o$next[1:0]$11131 - attribute \src "libresoc.v:180980.3-181025.6" - wire width 2 $7\src32__data_o$next[1:0]$11147 - attribute \src "libresoc.v:180802.17-180802.104" - wire $not$libresoc.v:180802$11104_Y - attribute \src "libresoc.v:180803.17-180803.100" - wire $not$libresoc.v:180803$11105_Y - attribute \src "libresoc.v:180804.17-180804.103" - wire $not$libresoc.v:180804$11106_Y - attribute \src "libresoc.v:180805.17-180805.103" - wire $not$libresoc.v:180805$11107_Y + attribute \src "libresoc.v:180810.3-180855.6" + wire width 2 $6\r2__data_o$next[1:0]$11156 + attribute \src "libresoc.v:180564.3-180609.6" + wire width 2 $6\src12__data_o$next[1:0]$11114 + attribute \src "libresoc.v:180646.3-180691.6" + wire width 2 $6\src22__data_o$next[1:0]$11124 + attribute \src "libresoc.v:180728.3-180773.6" + wire width 2 $6\src32__data_o$next[1:0]$11140 + attribute \src "libresoc.v:180810.3-180855.6" + wire width 2 $7\r2__data_o$next[1:0]$11157 + attribute \src "libresoc.v:180564.3-180609.6" + wire width 2 $7\src12__data_o$next[1:0]$11115 + attribute \src "libresoc.v:180646.3-180691.6" + wire width 2 $7\src22__data_o$next[1:0]$11125 + attribute \src "libresoc.v:180728.3-180773.6" + wire width 2 $7\src32__data_o$next[1:0]$11141 + attribute \src "libresoc.v:180550.17-180550.104" + wire $not$libresoc.v:180550$11098_Y + attribute \src "libresoc.v:180551.17-180551.100" + wire $not$libresoc.v:180551$11099_Y + attribute \src "libresoc.v:180552.17-180552.103" + wire $not$libresoc.v:180552$11100_Y + attribute \src "libresoc.v:180553.17-180553.103" + wire $not$libresoc.v:180553$11101_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -336434,9 +336140,9 @@ module \reg_2$134 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest12__data_i @@ -336450,7 +336156,7 @@ module \reg_2$134 wire width 2 input 13 \dest32__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest32__wen - attribute \src "libresoc.v:180733.7-180733.15" + attribute \src "libresoc.v:180481.7-180481.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r2__data_o @@ -336493,129 +336199,129 @@ module \reg_2$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180802$11104 + cell $not $not$libresoc.v:180550$11098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180802$11104_Y + connect \Y $not$libresoc.v:180550$11098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180803$11105 + cell $not $not$libresoc.v:180551$11099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180803$11105_Y + connect \Y $not$libresoc.v:180551$11099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180804$11106 + cell $not $not$libresoc.v:180552$11100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180804$11106_Y + connect \Y $not$libresoc.v:180552$11100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180805$11107 + cell $not $not$libresoc.v:180553$11101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180805$11107_Y + connect \Y $not$libresoc.v:180553$11101_Y end - attribute \src "libresoc.v:180733.7-180733.20" - process $proc$libresoc.v:180733$11178 + attribute \src "libresoc.v:180481.7-180481.20" + process $proc$libresoc.v:180481$11172 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180760.13-180760.30" - process $proc$libresoc.v:180760$11179 + attribute \src "libresoc.v:180508.13-180508.30" + process $proc$libresoc.v:180508$11173 assign { } { } assign $1\r2__data_o[1:0] 2'00 sync always sync init update \r2__data_o $1\r2__data_o[1:0] end - attribute \src "libresoc.v:180766.13-180766.25" - process $proc$libresoc.v:180766$11180 + attribute \src "libresoc.v:180514.13-180514.25" + process $proc$libresoc.v:180514$11174 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:180771.13-180771.33" - process $proc$libresoc.v:180771$11181 + attribute \src "libresoc.v:180519.13-180519.33" + process $proc$libresoc.v:180519$11175 assign { } { } assign $1\src12__data_o[1:0] 2'00 sync always sync init update \src12__data_o $1\src12__data_o[1:0] end - attribute \src "libresoc.v:180778.13-180778.33" - process $proc$libresoc.v:180778$11182 + attribute \src "libresoc.v:180526.13-180526.33" + process $proc$libresoc.v:180526$11176 assign { } { } assign $1\src22__data_o[1:0] 2'00 sync always sync init update \src22__data_o $1\src22__data_o[1:0] end - attribute \src "libresoc.v:180785.13-180785.33" - process $proc$libresoc.v:180785$11183 + attribute \src "libresoc.v:180533.13-180533.33" + process $proc$libresoc.v:180533$11177 assign { } { } assign $1\src32__data_o[1:0] 2'00 sync always sync init update \src32__data_o $1\src32__data_o[1:0] end - attribute \src "libresoc.v:180806.3-180807.25" - process $proc$libresoc.v:180806$11108 + attribute \src "libresoc.v:180554.3-180555.25" + process $proc$libresoc.v:180554$11102 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:180808.3-180809.37" - process $proc$libresoc.v:180808$11109 + attribute \src "libresoc.v:180556.3-180557.37" + process $proc$libresoc.v:180556$11103 assign { } { } assign $0\r2__data_o[1:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[1:0] end - attribute \src "libresoc.v:180810.3-180811.43" - process $proc$libresoc.v:180810$11110 + attribute \src "libresoc.v:180558.3-180559.43" + process $proc$libresoc.v:180558$11104 assign { } { } assign $0\src32__data_o[1:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[1:0] end - attribute \src "libresoc.v:180812.3-180813.43" - process $proc$libresoc.v:180812$11111 + attribute \src "libresoc.v:180560.3-180561.43" + process $proc$libresoc.v:180560$11105 assign { } { } assign $0\src22__data_o[1:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[1:0] end - attribute \src "libresoc.v:180814.3-180815.43" - process $proc$libresoc.v:180814$11112 + attribute \src "libresoc.v:180562.3-180563.43" + process $proc$libresoc.v:180562$11106 assign { } { } assign $0\src12__data_o[1:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[1:0] end - attribute \src "libresoc.v:180816.3-180861.6" - process $proc$libresoc.v:180816$11113 + attribute \src "libresoc.v:180564.3-180609.6" + process $proc$libresoc.v:180564$11107 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[1:0]$11114 $7\src12__data_o$next[1:0]$11121 - attribute \src "libresoc.v:180817.5-180817.29" + assign $0\src12__data_o$next[1:0]$11108 $7\src12__data_o$next[1:0]$11115 + attribute \src "libresoc.v:180565.5-180565.29" switch \initial - attribute \src "libresoc.v:180817.9-180817.17" + attribute \src "libresoc.v:180565.9-180565.17" case 1'1 case end @@ -336628,75 +336334,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[1:0]$11115 $6\src12__data_o$next[1:0]$11120 + assign $1\src12__data_o$next[1:0]$11109 $6\src12__data_o$next[1:0]$11114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[1:0]$11116 \dest12__data_i + assign $2\src12__data_o$next[1:0]$11110 \dest12__data_i case - assign $2\src12__data_o$next[1:0]$11116 2'00 + assign $2\src12__data_o$next[1:0]$11110 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[1:0]$11117 \dest22__data_i + assign $3\src12__data_o$next[1:0]$11111 \dest22__data_i case - assign $3\src12__data_o$next[1:0]$11117 $2\src12__data_o$next[1:0]$11116 + assign $3\src12__data_o$next[1:0]$11111 $2\src12__data_o$next[1:0]$11110 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[1:0]$11118 \dest32__data_i + assign $4\src12__data_o$next[1:0]$11112 \dest32__data_i case - assign $4\src12__data_o$next[1:0]$11118 $3\src12__data_o$next[1:0]$11117 + assign $4\src12__data_o$next[1:0]$11112 $3\src12__data_o$next[1:0]$11111 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[1:0]$11119 \w2__data_i + assign $5\src12__data_o$next[1:0]$11113 \w2__data_i case - assign $5\src12__data_o$next[1:0]$11119 $4\src12__data_o$next[1:0]$11118 + assign $5\src12__data_o$next[1:0]$11113 $4\src12__data_o$next[1:0]$11112 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[1:0]$11120 \reg + assign $6\src12__data_o$next[1:0]$11114 \reg case - assign $6\src12__data_o$next[1:0]$11120 $5\src12__data_o$next[1:0]$11119 + assign $6\src12__data_o$next[1:0]$11114 $5\src12__data_o$next[1:0]$11113 end case - assign $1\src12__data_o$next[1:0]$11115 2'00 + assign $1\src12__data_o$next[1:0]$11109 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src12__data_o$next[1:0]$11121 2'00 + assign $7\src12__data_o$next[1:0]$11115 2'00 case - assign $7\src12__data_o$next[1:0]$11121 $1\src12__data_o$next[1:0]$11115 + assign $7\src12__data_o$next[1:0]$11115 $1\src12__data_o$next[1:0]$11109 end sync always - update \src12__data_o$next $0\src12__data_o$next[1:0]$11114 + update \src12__data_o$next $0\src12__data_o$next[1:0]$11108 end - attribute \src "libresoc.v:180862.3-180897.6" - process $proc$libresoc.v:180862$11122 + attribute \src "libresoc.v:180610.3-180645.6" + process $proc$libresoc.v:180610$11116 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180863.5-180863.29" + attribute \src "libresoc.v:180611.5-180611.29" switch \initial - attribute \src "libresoc.v:180863.9-180863.17" + attribute \src "libresoc.v:180611.9-180611.17" case 1'1 case end @@ -336752,15 +336458,15 @@ module \reg_2$134 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180898.3-180943.6" - process $proc$libresoc.v:180898$11123 + attribute \src "libresoc.v:180646.3-180691.6" + process $proc$libresoc.v:180646$11117 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[1:0]$11124 $7\src22__data_o$next[1:0]$11131 - attribute \src "libresoc.v:180899.5-180899.29" + assign $0\src22__data_o$next[1:0]$11118 $7\src22__data_o$next[1:0]$11125 + attribute \src "libresoc.v:180647.5-180647.29" switch \initial - attribute \src "libresoc.v:180899.9-180899.17" + attribute \src "libresoc.v:180647.9-180647.17" case 1'1 case end @@ -336773,75 +336479,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[1:0]$11125 $6\src22__data_o$next[1:0]$11130 + assign $1\src22__data_o$next[1:0]$11119 $6\src22__data_o$next[1:0]$11124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[1:0]$11126 \dest12__data_i + assign $2\src22__data_o$next[1:0]$11120 \dest12__data_i case - assign $2\src22__data_o$next[1:0]$11126 2'00 + assign $2\src22__data_o$next[1:0]$11120 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[1:0]$11127 \dest22__data_i + assign $3\src22__data_o$next[1:0]$11121 \dest22__data_i case - assign $3\src22__data_o$next[1:0]$11127 $2\src22__data_o$next[1:0]$11126 + assign $3\src22__data_o$next[1:0]$11121 $2\src22__data_o$next[1:0]$11120 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[1:0]$11128 \dest32__data_i + assign $4\src22__data_o$next[1:0]$11122 \dest32__data_i case - assign $4\src22__data_o$next[1:0]$11128 $3\src22__data_o$next[1:0]$11127 + assign $4\src22__data_o$next[1:0]$11122 $3\src22__data_o$next[1:0]$11121 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[1:0]$11129 \w2__data_i + assign $5\src22__data_o$next[1:0]$11123 \w2__data_i case - assign $5\src22__data_o$next[1:0]$11129 $4\src22__data_o$next[1:0]$11128 + assign $5\src22__data_o$next[1:0]$11123 $4\src22__data_o$next[1:0]$11122 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[1:0]$11130 \reg + assign $6\src22__data_o$next[1:0]$11124 \reg case - assign $6\src22__data_o$next[1:0]$11130 $5\src22__data_o$next[1:0]$11129 + assign $6\src22__data_o$next[1:0]$11124 $5\src22__data_o$next[1:0]$11123 end case - assign $1\src22__data_o$next[1:0]$11125 2'00 + assign $1\src22__data_o$next[1:0]$11119 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src22__data_o$next[1:0]$11131 2'00 + assign $7\src22__data_o$next[1:0]$11125 2'00 case - assign $7\src22__data_o$next[1:0]$11131 $1\src22__data_o$next[1:0]$11125 + assign $7\src22__data_o$next[1:0]$11125 $1\src22__data_o$next[1:0]$11119 end sync always - update \src22__data_o$next $0\src22__data_o$next[1:0]$11124 + update \src22__data_o$next $0\src22__data_o$next[1:0]$11118 end - attribute \src "libresoc.v:180944.3-180979.6" - process $proc$libresoc.v:180944$11132 + attribute \src "libresoc.v:180692.3-180727.6" + process $proc$libresoc.v:180692$11126 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11133 $1\wr_detect$4[0:0]$11134 - attribute \src "libresoc.v:180945.5-180945.29" + assign $0\wr_detect$4[0:0]$11127 $1\wr_detect$4[0:0]$11128 + attribute \src "libresoc.v:180693.5-180693.29" switch \initial - attribute \src "libresoc.v:180945.9-180945.17" + attribute \src "libresoc.v:180693.9-180693.17" case 1'1 case end @@ -336854,58 +336560,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11134 $5\wr_detect$4[0:0]$11138 + assign $1\wr_detect$4[0:0]$11128 $5\wr_detect$4[0:0]$11132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11135 1'1 + assign $2\wr_detect$4[0:0]$11129 1'1 case - assign $2\wr_detect$4[0:0]$11135 1'0 + assign $2\wr_detect$4[0:0]$11129 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11136 1'1 + assign $3\wr_detect$4[0:0]$11130 1'1 case - assign $3\wr_detect$4[0:0]$11136 $2\wr_detect$4[0:0]$11135 + assign $3\wr_detect$4[0:0]$11130 $2\wr_detect$4[0:0]$11129 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11137 1'1 + assign $4\wr_detect$4[0:0]$11131 1'1 case - assign $4\wr_detect$4[0:0]$11137 $3\wr_detect$4[0:0]$11136 + assign $4\wr_detect$4[0:0]$11131 $3\wr_detect$4[0:0]$11130 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11138 1'1 + assign $5\wr_detect$4[0:0]$11132 1'1 case - assign $5\wr_detect$4[0:0]$11138 $4\wr_detect$4[0:0]$11137 + assign $5\wr_detect$4[0:0]$11132 $4\wr_detect$4[0:0]$11131 end case - assign $1\wr_detect$4[0:0]$11134 1'0 + assign $1\wr_detect$4[0:0]$11128 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11133 + update \wr_detect$4 $0\wr_detect$4[0:0]$11127 end - attribute \src "libresoc.v:180980.3-181025.6" - process $proc$libresoc.v:180980$11139 + attribute \src "libresoc.v:180728.3-180773.6" + process $proc$libresoc.v:180728$11133 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[1:0]$11140 $7\src32__data_o$next[1:0]$11147 - attribute \src "libresoc.v:180981.5-180981.29" + assign $0\src32__data_o$next[1:0]$11134 $7\src32__data_o$next[1:0]$11141 + attribute \src "libresoc.v:180729.5-180729.29" switch \initial - attribute \src "libresoc.v:180981.9-180981.17" + attribute \src "libresoc.v:180729.9-180729.17" case 1'1 case end @@ -336918,75 +336624,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[1:0]$11141 $6\src32__data_o$next[1:0]$11146 + assign $1\src32__data_o$next[1:0]$11135 $6\src32__data_o$next[1:0]$11140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[1:0]$11142 \dest12__data_i + assign $2\src32__data_o$next[1:0]$11136 \dest12__data_i case - assign $2\src32__data_o$next[1:0]$11142 2'00 + assign $2\src32__data_o$next[1:0]$11136 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[1:0]$11143 \dest22__data_i + assign $3\src32__data_o$next[1:0]$11137 \dest22__data_i case - assign $3\src32__data_o$next[1:0]$11143 $2\src32__data_o$next[1:0]$11142 + assign $3\src32__data_o$next[1:0]$11137 $2\src32__data_o$next[1:0]$11136 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[1:0]$11144 \dest32__data_i + assign $4\src32__data_o$next[1:0]$11138 \dest32__data_i case - assign $4\src32__data_o$next[1:0]$11144 $3\src32__data_o$next[1:0]$11143 + assign $4\src32__data_o$next[1:0]$11138 $3\src32__data_o$next[1:0]$11137 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[1:0]$11145 \w2__data_i + assign $5\src32__data_o$next[1:0]$11139 \w2__data_i case - assign $5\src32__data_o$next[1:0]$11145 $4\src32__data_o$next[1:0]$11144 + assign $5\src32__data_o$next[1:0]$11139 $4\src32__data_o$next[1:0]$11138 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[1:0]$11146 \reg + assign $6\src32__data_o$next[1:0]$11140 \reg case - assign $6\src32__data_o$next[1:0]$11146 $5\src32__data_o$next[1:0]$11145 + assign $6\src32__data_o$next[1:0]$11140 $5\src32__data_o$next[1:0]$11139 end case - assign $1\src32__data_o$next[1:0]$11141 2'00 + assign $1\src32__data_o$next[1:0]$11135 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src32__data_o$next[1:0]$11147 2'00 + assign $7\src32__data_o$next[1:0]$11141 2'00 case - assign $7\src32__data_o$next[1:0]$11147 $1\src32__data_o$next[1:0]$11141 + assign $7\src32__data_o$next[1:0]$11141 $1\src32__data_o$next[1:0]$11135 end sync always - update \src32__data_o$next $0\src32__data_o$next[1:0]$11140 + update \src32__data_o$next $0\src32__data_o$next[1:0]$11134 end - attribute \src "libresoc.v:181026.3-181061.6" - process $proc$libresoc.v:181026$11148 + attribute \src "libresoc.v:180774.3-180809.6" + process $proc$libresoc.v:180774$11142 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11149 $1\wr_detect$7[0:0]$11150 - attribute \src "libresoc.v:181027.5-181027.29" + assign $0\wr_detect$7[0:0]$11143 $1\wr_detect$7[0:0]$11144 + attribute \src "libresoc.v:180775.5-180775.29" switch \initial - attribute \src "libresoc.v:181027.9-181027.17" + attribute \src "libresoc.v:180775.9-180775.17" case 1'1 case end @@ -336999,58 +336705,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11150 $5\wr_detect$7[0:0]$11154 + assign $1\wr_detect$7[0:0]$11144 $5\wr_detect$7[0:0]$11148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11151 1'1 + assign $2\wr_detect$7[0:0]$11145 1'1 case - assign $2\wr_detect$7[0:0]$11151 1'0 + assign $2\wr_detect$7[0:0]$11145 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11152 1'1 + assign $3\wr_detect$7[0:0]$11146 1'1 case - assign $3\wr_detect$7[0:0]$11152 $2\wr_detect$7[0:0]$11151 + assign $3\wr_detect$7[0:0]$11146 $2\wr_detect$7[0:0]$11145 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11153 1'1 + assign $4\wr_detect$7[0:0]$11147 1'1 case - assign $4\wr_detect$7[0:0]$11153 $3\wr_detect$7[0:0]$11152 + assign $4\wr_detect$7[0:0]$11147 $3\wr_detect$7[0:0]$11146 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11154 1'1 + assign $5\wr_detect$7[0:0]$11148 1'1 case - assign $5\wr_detect$7[0:0]$11154 $4\wr_detect$7[0:0]$11153 + assign $5\wr_detect$7[0:0]$11148 $4\wr_detect$7[0:0]$11147 end case - assign $1\wr_detect$7[0:0]$11150 1'0 + assign $1\wr_detect$7[0:0]$11144 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11149 + update \wr_detect$7 $0\wr_detect$7[0:0]$11143 end - attribute \src "libresoc.v:181062.3-181107.6" - process $proc$libresoc.v:181062$11155 + attribute \src "libresoc.v:180810.3-180855.6" + process $proc$libresoc.v:180810$11149 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[1:0]$11156 $7\r2__data_o$next[1:0]$11163 - attribute \src "libresoc.v:181063.5-181063.29" + assign $0\r2__data_o$next[1:0]$11150 $7\r2__data_o$next[1:0]$11157 + attribute \src "libresoc.v:180811.5-180811.29" switch \initial - attribute \src "libresoc.v:181063.9-181063.17" + attribute \src "libresoc.v:180811.9-180811.17" case 1'1 case end @@ -337063,75 +336769,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[1:0]$11157 $6\r2__data_o$next[1:0]$11162 + assign $1\r2__data_o$next[1:0]$11151 $6\r2__data_o$next[1:0]$11156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[1:0]$11158 \dest12__data_i + assign $2\r2__data_o$next[1:0]$11152 \dest12__data_i case - assign $2\r2__data_o$next[1:0]$11158 2'00 + assign $2\r2__data_o$next[1:0]$11152 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[1:0]$11159 \dest22__data_i + assign $3\r2__data_o$next[1:0]$11153 \dest22__data_i case - assign $3\r2__data_o$next[1:0]$11159 $2\r2__data_o$next[1:0]$11158 + assign $3\r2__data_o$next[1:0]$11153 $2\r2__data_o$next[1:0]$11152 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[1:0]$11160 \dest32__data_i + assign $4\r2__data_o$next[1:0]$11154 \dest32__data_i case - assign $4\r2__data_o$next[1:0]$11160 $3\r2__data_o$next[1:0]$11159 + assign $4\r2__data_o$next[1:0]$11154 $3\r2__data_o$next[1:0]$11153 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[1:0]$11161 \w2__data_i + assign $5\r2__data_o$next[1:0]$11155 \w2__data_i case - assign $5\r2__data_o$next[1:0]$11161 $4\r2__data_o$next[1:0]$11160 + assign $5\r2__data_o$next[1:0]$11155 $4\r2__data_o$next[1:0]$11154 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[1:0]$11162 \reg + assign $6\r2__data_o$next[1:0]$11156 \reg case - assign $6\r2__data_o$next[1:0]$11162 $5\r2__data_o$next[1:0]$11161 + assign $6\r2__data_o$next[1:0]$11156 $5\r2__data_o$next[1:0]$11155 end case - assign $1\r2__data_o$next[1:0]$11157 2'00 + assign $1\r2__data_o$next[1:0]$11151 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r2__data_o$next[1:0]$11163 2'00 + assign $7\r2__data_o$next[1:0]$11157 2'00 case - assign $7\r2__data_o$next[1:0]$11163 $1\r2__data_o$next[1:0]$11157 + assign $7\r2__data_o$next[1:0]$11157 $1\r2__data_o$next[1:0]$11151 end sync always - update \r2__data_o$next $0\r2__data_o$next[1:0]$11156 + update \r2__data_o$next $0\r2__data_o$next[1:0]$11150 end - attribute \src "libresoc.v:181108.3-181143.6" - process $proc$libresoc.v:181108$11164 + attribute \src "libresoc.v:180856.3-180891.6" + process $proc$libresoc.v:180856$11158 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11165 $1\wr_detect$10[0:0]$11166 - attribute \src "libresoc.v:181109.5-181109.29" + assign $0\wr_detect$10[0:0]$11159 $1\wr_detect$10[0:0]$11160 + attribute \src "libresoc.v:180857.5-180857.29" switch \initial - attribute \src "libresoc.v:181109.9-181109.17" + attribute \src "libresoc.v:180857.9-180857.17" case 1'1 case end @@ -337144,61 +336850,61 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11166 $5\wr_detect$10[0:0]$11170 + assign $1\wr_detect$10[0:0]$11160 $5\wr_detect$10[0:0]$11164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11167 1'1 + assign $2\wr_detect$10[0:0]$11161 1'1 case - assign $2\wr_detect$10[0:0]$11167 1'0 + assign $2\wr_detect$10[0:0]$11161 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11168 1'1 + assign $3\wr_detect$10[0:0]$11162 1'1 case - assign $3\wr_detect$10[0:0]$11168 $2\wr_detect$10[0:0]$11167 + assign $3\wr_detect$10[0:0]$11162 $2\wr_detect$10[0:0]$11161 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11169 1'1 + assign $4\wr_detect$10[0:0]$11163 1'1 case - assign $4\wr_detect$10[0:0]$11169 $3\wr_detect$10[0:0]$11168 + assign $4\wr_detect$10[0:0]$11163 $3\wr_detect$10[0:0]$11162 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11170 1'1 + assign $5\wr_detect$10[0:0]$11164 1'1 case - assign $5\wr_detect$10[0:0]$11170 $4\wr_detect$10[0:0]$11169 + assign $5\wr_detect$10[0:0]$11164 $4\wr_detect$10[0:0]$11163 end case - assign $1\wr_detect$10[0:0]$11166 1'0 + assign $1\wr_detect$10[0:0]$11160 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11165 + update \wr_detect$10 $0\wr_detect$10[0:0]$11159 end - attribute \src "libresoc.v:181144.3-181176.6" - process $proc$libresoc.v:181144$11171 + attribute \src "libresoc.v:180892.3-180924.6" + process $proc$libresoc.v:180892$11165 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$11172 $5\reg$next[1:0]$11177 - attribute \src "libresoc.v:181145.5-181145.29" + assign $0\reg$next[1:0]$11166 $5\reg$next[1:0]$11171 + attribute \src "libresoc.v:180893.5-180893.29" switch \initial - attribute \src "libresoc.v:181145.9-181145.17" + attribute \src "libresoc.v:180893.9-180893.17" case 1'1 case end @@ -337207,179 +336913,179 @@ module \reg_2$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$11173 \dest12__data_i + assign $1\reg$next[1:0]$11167 \dest12__data_i case - assign $1\reg$next[1:0]$11173 \reg + assign $1\reg$next[1:0]$11167 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$11174 \dest22__data_i + assign $2\reg$next[1:0]$11168 \dest22__data_i case - assign $2\reg$next[1:0]$11174 $1\reg$next[1:0]$11173 + assign $2\reg$next[1:0]$11168 $1\reg$next[1:0]$11167 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$11175 \dest32__data_i + assign $3\reg$next[1:0]$11169 \dest32__data_i case - assign $3\reg$next[1:0]$11175 $2\reg$next[1:0]$11174 + assign $3\reg$next[1:0]$11169 $2\reg$next[1:0]$11168 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$11176 \w2__data_i + assign $4\reg$next[1:0]$11170 \w2__data_i case - assign $4\reg$next[1:0]$11176 $3\reg$next[1:0]$11175 + assign $4\reg$next[1:0]$11170 $3\reg$next[1:0]$11169 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$11177 2'00 + assign $5\reg$next[1:0]$11171 2'00 case - assign $5\reg$next[1:0]$11177 $4\reg$next[1:0]$11176 + assign $5\reg$next[1:0]$11171 $4\reg$next[1:0]$11170 end sync always - update \reg$next $0\reg$next[1:0]$11172 + update \reg$next $0\reg$next[1:0]$11166 end - connect \$9 $not$libresoc.v:180802$11104_Y - connect \$1 $not$libresoc.v:180803$11105_Y - connect \$3 $not$libresoc.v:180804$11106_Y - connect \$6 $not$libresoc.v:180805$11107_Y + connect \$9 $not$libresoc.v:180550$11098_Y + connect \$1 $not$libresoc.v:180551$11099_Y + connect \$3 $not$libresoc.v:180552$11100_Y + connect \$6 $not$libresoc.v:180553$11101_Y end -attribute \src "libresoc.v:181181.1-181530.10" +attribute \src "libresoc.v:180929.1-181278.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" attribute \generator "nMigen" module \reg_2$137 - attribute \src "libresoc.v:181251.3-181296.6" - wire width 64 $0\cia2__data_o$next[63:0]$11192 - attribute \src "libresoc.v:181249.3-181250.41" + attribute \src "libresoc.v:180999.3-181044.6" + wire width 64 $0\cia2__data_o$next[63:0]$11186 + attribute \src "libresoc.v:180997.3-180998.41" wire width 64 $0\cia2__data_o[63:0] - attribute \src "libresoc.v:181182.7-181182.20" + attribute \src "libresoc.v:180930.7-180930.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181333.3-181378.6" - wire width 64 $0\msr2__data_o$next[63:0]$11202 - attribute \src "libresoc.v:181247.3-181248.41" + attribute \src "libresoc.v:181081.3-181126.6" + wire width 64 $0\msr2__data_o$next[63:0]$11196 + attribute \src "libresoc.v:180995.3-180996.41" wire width 64 $0\msr2__data_o[63:0] - attribute \src "libresoc.v:181497.3-181529.6" - wire width 64 $0\reg$next[63:0]$11234 - attribute \src "libresoc.v:181243.3-181244.25" + attribute \src "libresoc.v:181245.3-181277.6" + wire width 64 $0\reg$next[63:0]$11228 + attribute \src "libresoc.v:180991.3-180992.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:181415.3-181460.6" - wire width 64 $0\sv2__data_o$next[63:0]$11218 - attribute \src "libresoc.v:181245.3-181246.39" + attribute \src "libresoc.v:181163.3-181208.6" + wire width 64 $0\sv2__data_o$next[63:0]$11212 + attribute \src "libresoc.v:180993.3-180994.39" wire width 64 $0\sv2__data_o[63:0] - attribute \src "libresoc.v:181379.3-181414.6" - wire $0\wr_detect$4[0:0]$11211 - attribute \src "libresoc.v:181461.3-181496.6" - wire $0\wr_detect$7[0:0]$11227 - attribute \src "libresoc.v:181297.3-181332.6" + attribute \src "libresoc.v:181127.3-181162.6" + wire $0\wr_detect$4[0:0]$11205 + attribute \src "libresoc.v:181209.3-181244.6" + wire $0\wr_detect$7[0:0]$11221 + attribute \src "libresoc.v:181045.3-181080.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:181251.3-181296.6" - wire width 64 $1\cia2__data_o$next[63:0]$11193 - attribute \src "libresoc.v:181191.14-181191.49" + attribute \src "libresoc.v:180999.3-181044.6" + wire width 64 $1\cia2__data_o$next[63:0]$11187 + attribute \src "libresoc.v:180939.14-180939.49" wire width 64 $1\cia2__data_o[63:0] - attribute \src "libresoc.v:181333.3-181378.6" - wire width 64 $1\msr2__data_o$next[63:0]$11203 - attribute \src "libresoc.v:181208.14-181208.49" + attribute \src "libresoc.v:181081.3-181126.6" + wire width 64 $1\msr2__data_o$next[63:0]$11197 + attribute \src "libresoc.v:180956.14-180956.49" wire width 64 $1\msr2__data_o[63:0] - attribute \src "libresoc.v:181497.3-181529.6" - wire width 64 $1\reg$next[63:0]$11235 - attribute \src "libresoc.v:181220.14-181220.42" + attribute \src "libresoc.v:181245.3-181277.6" + wire width 64 $1\reg$next[63:0]$11229 + attribute \src "libresoc.v:180968.14-180968.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:181415.3-181460.6" - wire width 64 $1\sv2__data_o$next[63:0]$11219 - attribute \src "libresoc.v:181227.14-181227.48" + attribute \src "libresoc.v:181163.3-181208.6" + wire width 64 $1\sv2__data_o$next[63:0]$11213 + attribute \src "libresoc.v:180975.14-180975.48" wire width 64 $1\sv2__data_o[63:0] - attribute \src "libresoc.v:181379.3-181414.6" - wire $1\wr_detect$4[0:0]$11212 - attribute \src "libresoc.v:181461.3-181496.6" - wire $1\wr_detect$7[0:0]$11228 - attribute \src "libresoc.v:181297.3-181332.6" + attribute \src "libresoc.v:181127.3-181162.6" + wire $1\wr_detect$4[0:0]$11206 + attribute \src "libresoc.v:181209.3-181244.6" + wire $1\wr_detect$7[0:0]$11222 + attribute \src "libresoc.v:181045.3-181080.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:181251.3-181296.6" - wire width 64 $2\cia2__data_o$next[63:0]$11194 - attribute \src "libresoc.v:181333.3-181378.6" - wire width 64 $2\msr2__data_o$next[63:0]$11204 - attribute \src "libresoc.v:181497.3-181529.6" - wire width 64 $2\reg$next[63:0]$11236 - attribute \src "libresoc.v:181415.3-181460.6" - wire width 64 $2\sv2__data_o$next[63:0]$11220 - attribute \src "libresoc.v:181379.3-181414.6" - wire $2\wr_detect$4[0:0]$11213 - attribute \src "libresoc.v:181461.3-181496.6" - wire $2\wr_detect$7[0:0]$11229 - attribute \src "libresoc.v:181297.3-181332.6" + attribute \src "libresoc.v:180999.3-181044.6" + wire width 64 $2\cia2__data_o$next[63:0]$11188 + attribute \src "libresoc.v:181081.3-181126.6" + wire width 64 $2\msr2__data_o$next[63:0]$11198 + attribute \src "libresoc.v:181245.3-181277.6" + wire width 64 $2\reg$next[63:0]$11230 + attribute \src "libresoc.v:181163.3-181208.6" + wire width 64 $2\sv2__data_o$next[63:0]$11214 + attribute \src "libresoc.v:181127.3-181162.6" + wire $2\wr_detect$4[0:0]$11207 + attribute \src "libresoc.v:181209.3-181244.6" + wire $2\wr_detect$7[0:0]$11223 + attribute \src "libresoc.v:181045.3-181080.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:181251.3-181296.6" - wire width 64 $3\cia2__data_o$next[63:0]$11195 - attribute \src "libresoc.v:181333.3-181378.6" - wire width 64 $3\msr2__data_o$next[63:0]$11205 - attribute \src "libresoc.v:181497.3-181529.6" - wire width 64 $3\reg$next[63:0]$11237 - attribute \src "libresoc.v:181415.3-181460.6" - wire width 64 $3\sv2__data_o$next[63:0]$11221 - attribute \src "libresoc.v:181379.3-181414.6" - wire $3\wr_detect$4[0:0]$11214 - attribute \src "libresoc.v:181461.3-181496.6" - wire $3\wr_detect$7[0:0]$11230 - attribute \src "libresoc.v:181297.3-181332.6" + attribute \src "libresoc.v:180999.3-181044.6" + wire width 64 $3\cia2__data_o$next[63:0]$11189 + attribute \src "libresoc.v:181081.3-181126.6" + wire width 64 $3\msr2__data_o$next[63:0]$11199 + attribute \src "libresoc.v:181245.3-181277.6" + wire width 64 $3\reg$next[63:0]$11231 + attribute \src "libresoc.v:181163.3-181208.6" + wire width 64 $3\sv2__data_o$next[63:0]$11215 + attribute \src "libresoc.v:181127.3-181162.6" + wire $3\wr_detect$4[0:0]$11208 + attribute \src "libresoc.v:181209.3-181244.6" + wire $3\wr_detect$7[0:0]$11224 + attribute \src "libresoc.v:181045.3-181080.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:181251.3-181296.6" - wire width 64 $4\cia2__data_o$next[63:0]$11196 - attribute \src "libresoc.v:181333.3-181378.6" - wire width 64 $4\msr2__data_o$next[63:0]$11206 - attribute \src "libresoc.v:181497.3-181529.6" - wire width 64 $4\reg$next[63:0]$11238 - attribute \src "libresoc.v:181415.3-181460.6" - wire width 64 $4\sv2__data_o$next[63:0]$11222 - attribute \src "libresoc.v:181379.3-181414.6" - wire $4\wr_detect$4[0:0]$11215 - attribute \src "libresoc.v:181461.3-181496.6" - wire $4\wr_detect$7[0:0]$11231 - attribute \src "libresoc.v:181297.3-181332.6" + attribute \src "libresoc.v:180999.3-181044.6" + wire width 64 $4\cia2__data_o$next[63:0]$11190 + attribute \src "libresoc.v:181081.3-181126.6" + wire width 64 $4\msr2__data_o$next[63:0]$11200 + attribute \src "libresoc.v:181245.3-181277.6" + wire width 64 $4\reg$next[63:0]$11232 + attribute \src "libresoc.v:181163.3-181208.6" + wire width 64 $4\sv2__data_o$next[63:0]$11216 + attribute \src "libresoc.v:181127.3-181162.6" + wire $4\wr_detect$4[0:0]$11209 + attribute \src "libresoc.v:181209.3-181244.6" + wire $4\wr_detect$7[0:0]$11225 + attribute \src "libresoc.v:181045.3-181080.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:181251.3-181296.6" - wire width 64 $5\cia2__data_o$next[63:0]$11197 - attribute \src "libresoc.v:181333.3-181378.6" - wire width 64 $5\msr2__data_o$next[63:0]$11207 - attribute \src "libresoc.v:181497.3-181529.6" - wire width 64 $5\reg$next[63:0]$11239 - attribute \src "libresoc.v:181415.3-181460.6" - wire width 64 $5\sv2__data_o$next[63:0]$11223 - attribute \src "libresoc.v:181379.3-181414.6" - wire $5\wr_detect$4[0:0]$11216 - attribute \src "libresoc.v:181461.3-181496.6" - wire $5\wr_detect$7[0:0]$11232 - attribute \src "libresoc.v:181297.3-181332.6" + attribute \src "libresoc.v:180999.3-181044.6" + wire width 64 $5\cia2__data_o$next[63:0]$11191 + attribute \src "libresoc.v:181081.3-181126.6" + wire width 64 $5\msr2__data_o$next[63:0]$11201 + attribute \src "libresoc.v:181245.3-181277.6" + wire width 64 $5\reg$next[63:0]$11233 + attribute \src "libresoc.v:181163.3-181208.6" + wire width 64 $5\sv2__data_o$next[63:0]$11217 + attribute \src "libresoc.v:181127.3-181162.6" + wire $5\wr_detect$4[0:0]$11210 + attribute \src "libresoc.v:181209.3-181244.6" + wire $5\wr_detect$7[0:0]$11226 + attribute \src "libresoc.v:181045.3-181080.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:181251.3-181296.6" - wire width 64 $6\cia2__data_o$next[63:0]$11198 - attribute \src "libresoc.v:181333.3-181378.6" - wire width 64 $6\msr2__data_o$next[63:0]$11208 - attribute \src "libresoc.v:181415.3-181460.6" - wire width 64 $6\sv2__data_o$next[63:0]$11224 - attribute \src "libresoc.v:181251.3-181296.6" - wire width 64 $7\cia2__data_o$next[63:0]$11199 - attribute \src "libresoc.v:181333.3-181378.6" - wire width 64 $7\msr2__data_o$next[63:0]$11209 - attribute \src "libresoc.v:181415.3-181460.6" - wire width 64 $7\sv2__data_o$next[63:0]$11225 - attribute \src "libresoc.v:181240.17-181240.100" - wire $not$libresoc.v:181240$11184_Y - attribute \src "libresoc.v:181241.17-181241.103" - wire $not$libresoc.v:181241$11185_Y - attribute \src "libresoc.v:181242.17-181242.103" - wire $not$libresoc.v:181242$11186_Y + attribute \src "libresoc.v:180999.3-181044.6" + wire width 64 $6\cia2__data_o$next[63:0]$11192 + attribute \src "libresoc.v:181081.3-181126.6" + wire width 64 $6\msr2__data_o$next[63:0]$11202 + attribute \src "libresoc.v:181163.3-181208.6" + wire width 64 $6\sv2__data_o$next[63:0]$11218 + attribute \src "libresoc.v:180999.3-181044.6" + wire width 64 $7\cia2__data_o$next[63:0]$11193 + attribute \src "libresoc.v:181081.3-181126.6" + wire width 64 $7\msr2__data_o$next[63:0]$11203 + attribute \src "libresoc.v:181163.3-181208.6" + wire width 64 $7\sv2__data_o$next[63:0]$11219 + attribute \src "libresoc.v:180988.17-180988.100" + wire $not$libresoc.v:180988$11178_Y + attribute \src "libresoc.v:180989.17-180989.103" + wire $not$libresoc.v:180989$11179_Y + attribute \src "libresoc.v:180990.17-180990.103" + wire $not$libresoc.v:180990$11180_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -337392,15 +337098,15 @@ module \reg_2$137 wire width 64 \cia2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr12__wen - attribute \src "libresoc.v:181182.7-181182.15" + attribute \src "libresoc.v:180930.7-180930.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr2__data_i @@ -337437,106 +337143,106 @@ module \reg_2$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181240$11184 + cell $not $not$libresoc.v:180988$11178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:181240$11184_Y + connect \Y $not$libresoc.v:180988$11178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181241$11185 + cell $not $not$libresoc.v:180989$11179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:181241$11185_Y + connect \Y $not$libresoc.v:180989$11179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181242$11186 + cell $not $not$libresoc.v:180990$11180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:181242$11186_Y + connect \Y $not$libresoc.v:180990$11180_Y end - attribute \src "libresoc.v:181182.7-181182.20" - process $proc$libresoc.v:181182$11240 + attribute \src "libresoc.v:180930.7-180930.20" + process $proc$libresoc.v:180930$11234 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181191.14-181191.49" - process $proc$libresoc.v:181191$11241 + attribute \src "libresoc.v:180939.14-180939.49" + process $proc$libresoc.v:180939$11235 assign { } { } assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia2__data_o $1\cia2__data_o[63:0] end - attribute \src "libresoc.v:181208.14-181208.49" - process $proc$libresoc.v:181208$11242 + attribute \src "libresoc.v:180956.14-180956.49" + process $proc$libresoc.v:180956$11236 assign { } { } assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr2__data_o $1\msr2__data_o[63:0] end - attribute \src "libresoc.v:181220.14-181220.42" - process $proc$libresoc.v:181220$11243 + attribute \src "libresoc.v:180968.14-180968.42" + process $proc$libresoc.v:180968$11237 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:181227.14-181227.48" - process $proc$libresoc.v:181227$11244 + attribute \src "libresoc.v:180975.14-180975.48" + process $proc$libresoc.v:180975$11238 assign { } { } assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv2__data_o $1\sv2__data_o[63:0] end - attribute \src "libresoc.v:181243.3-181244.25" - process $proc$libresoc.v:181243$11187 + attribute \src "libresoc.v:180991.3-180992.25" + process $proc$libresoc.v:180991$11181 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:181245.3-181246.39" - process $proc$libresoc.v:181245$11188 + attribute \src "libresoc.v:180993.3-180994.39" + process $proc$libresoc.v:180993$11182 assign { } { } assign $0\sv2__data_o[63:0] \sv2__data_o$next sync posedge \coresync_clk update \sv2__data_o $0\sv2__data_o[63:0] end - attribute \src "libresoc.v:181247.3-181248.41" - process $proc$libresoc.v:181247$11189 + attribute \src "libresoc.v:180995.3-180996.41" + process $proc$libresoc.v:180995$11183 assign { } { } assign $0\msr2__data_o[63:0] \msr2__data_o$next sync posedge \coresync_clk update \msr2__data_o $0\msr2__data_o[63:0] end - attribute \src "libresoc.v:181249.3-181250.41" - process $proc$libresoc.v:181249$11190 + attribute \src "libresoc.v:180997.3-180998.41" + process $proc$libresoc.v:180997$11184 assign { } { } assign $0\cia2__data_o[63:0] \cia2__data_o$next sync posedge \coresync_clk update \cia2__data_o $0\cia2__data_o[63:0] end - attribute \src "libresoc.v:181251.3-181296.6" - process $proc$libresoc.v:181251$11191 + attribute \src "libresoc.v:180999.3-181044.6" + process $proc$libresoc.v:180999$11185 assign { } { } assign { } { } assign { } { } - assign $0\cia2__data_o$next[63:0]$11192 $7\cia2__data_o$next[63:0]$11199 - attribute \src "libresoc.v:181252.5-181252.29" + assign $0\cia2__data_o$next[63:0]$11186 $7\cia2__data_o$next[63:0]$11193 + attribute \src "libresoc.v:181000.5-181000.29" switch \initial - attribute \src "libresoc.v:181252.9-181252.17" + attribute \src "libresoc.v:181000.9-181000.17" case 1'1 case end @@ -337549,75 +337255,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\cia2__data_o$next[63:0]$11193 $6\cia2__data_o$next[63:0]$11198 + assign $1\cia2__data_o$next[63:0]$11187 $6\cia2__data_o$next[63:0]$11192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia2__data_o$next[63:0]$11194 \nia2__data_i + assign $2\cia2__data_o$next[63:0]$11188 \nia2__data_i case - assign $2\cia2__data_o$next[63:0]$11194 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia2__data_o$next[63:0]$11188 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia2__data_o$next[63:0]$11195 \msr2__data_i + assign $3\cia2__data_o$next[63:0]$11189 \msr2__data_i case - assign $3\cia2__data_o$next[63:0]$11195 $2\cia2__data_o$next[63:0]$11194 + assign $3\cia2__data_o$next[63:0]$11189 $2\cia2__data_o$next[63:0]$11188 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia2__data_o$next[63:0]$11196 \sv2__data_i + assign $4\cia2__data_o$next[63:0]$11190 \sv2__data_i case - assign $4\cia2__data_o$next[63:0]$11196 $3\cia2__data_o$next[63:0]$11195 + assign $4\cia2__data_o$next[63:0]$11190 $3\cia2__data_o$next[63:0]$11189 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia2__data_o$next[63:0]$11197 \d_wr12__data_i + assign $5\cia2__data_o$next[63:0]$11191 \d_wr12__data_i case - assign $5\cia2__data_o$next[63:0]$11197 $4\cia2__data_o$next[63:0]$11196 + assign $5\cia2__data_o$next[63:0]$11191 $4\cia2__data_o$next[63:0]$11190 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia2__data_o$next[63:0]$11198 \reg + assign $6\cia2__data_o$next[63:0]$11192 \reg case - assign $6\cia2__data_o$next[63:0]$11198 $5\cia2__data_o$next[63:0]$11197 + assign $6\cia2__data_o$next[63:0]$11192 $5\cia2__data_o$next[63:0]$11191 end case - assign $1\cia2__data_o$next[63:0]$11193 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia2__data_o$next[63:0]$11187 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia2__data_o$next[63:0]$11199 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia2__data_o$next[63:0]$11193 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia2__data_o$next[63:0]$11199 $1\cia2__data_o$next[63:0]$11193 + assign $7\cia2__data_o$next[63:0]$11193 $1\cia2__data_o$next[63:0]$11187 end sync always - update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11192 + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11186 end - attribute \src "libresoc.v:181297.3-181332.6" - process $proc$libresoc.v:181297$11200 + attribute \src "libresoc.v:181045.3-181080.6" + process $proc$libresoc.v:181045$11194 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181298.5-181298.29" + attribute \src "libresoc.v:181046.5-181046.29" switch \initial - attribute \src "libresoc.v:181298.9-181298.17" + attribute \src "libresoc.v:181046.9-181046.17" case 1'1 case end @@ -337673,15 +337379,15 @@ module \reg_2$137 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181333.3-181378.6" - process $proc$libresoc.v:181333$11201 + attribute \src "libresoc.v:181081.3-181126.6" + process $proc$libresoc.v:181081$11195 assign { } { } assign { } { } assign { } { } - assign $0\msr2__data_o$next[63:0]$11202 $7\msr2__data_o$next[63:0]$11209 - attribute \src "libresoc.v:181334.5-181334.29" + assign $0\msr2__data_o$next[63:0]$11196 $7\msr2__data_o$next[63:0]$11203 + attribute \src "libresoc.v:181082.5-181082.29" switch \initial - attribute \src "libresoc.v:181334.9-181334.17" + attribute \src "libresoc.v:181082.9-181082.17" case 1'1 case end @@ -337694,75 +337400,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\msr2__data_o$next[63:0]$11203 $6\msr2__data_o$next[63:0]$11208 + assign $1\msr2__data_o$next[63:0]$11197 $6\msr2__data_o$next[63:0]$11202 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr2__data_o$next[63:0]$11204 \nia2__data_i + assign $2\msr2__data_o$next[63:0]$11198 \nia2__data_i case - assign $2\msr2__data_o$next[63:0]$11204 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr2__data_o$next[63:0]$11198 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr2__data_o$next[63:0]$11205 \msr2__data_i + assign $3\msr2__data_o$next[63:0]$11199 \msr2__data_i case - assign $3\msr2__data_o$next[63:0]$11205 $2\msr2__data_o$next[63:0]$11204 + assign $3\msr2__data_o$next[63:0]$11199 $2\msr2__data_o$next[63:0]$11198 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr2__data_o$next[63:0]$11206 \sv2__data_i + assign $4\msr2__data_o$next[63:0]$11200 \sv2__data_i case - assign $4\msr2__data_o$next[63:0]$11206 $3\msr2__data_o$next[63:0]$11205 + assign $4\msr2__data_o$next[63:0]$11200 $3\msr2__data_o$next[63:0]$11199 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr2__data_o$next[63:0]$11207 \d_wr12__data_i + assign $5\msr2__data_o$next[63:0]$11201 \d_wr12__data_i case - assign $5\msr2__data_o$next[63:0]$11207 $4\msr2__data_o$next[63:0]$11206 + assign $5\msr2__data_o$next[63:0]$11201 $4\msr2__data_o$next[63:0]$11200 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr2__data_o$next[63:0]$11208 \reg + assign $6\msr2__data_o$next[63:0]$11202 \reg case - assign $6\msr2__data_o$next[63:0]$11208 $5\msr2__data_o$next[63:0]$11207 + assign $6\msr2__data_o$next[63:0]$11202 $5\msr2__data_o$next[63:0]$11201 end case - assign $1\msr2__data_o$next[63:0]$11203 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr2__data_o$next[63:0]$11197 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr2__data_o$next[63:0]$11209 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr2__data_o$next[63:0]$11203 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr2__data_o$next[63:0]$11209 $1\msr2__data_o$next[63:0]$11203 + assign $7\msr2__data_o$next[63:0]$11203 $1\msr2__data_o$next[63:0]$11197 end sync always - update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11202 + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11196 end - attribute \src "libresoc.v:181379.3-181414.6" - process $proc$libresoc.v:181379$11210 + attribute \src "libresoc.v:181127.3-181162.6" + process $proc$libresoc.v:181127$11204 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11211 $1\wr_detect$4[0:0]$11212 - attribute \src "libresoc.v:181380.5-181380.29" + assign $0\wr_detect$4[0:0]$11205 $1\wr_detect$4[0:0]$11206 + attribute \src "libresoc.v:181128.5-181128.29" switch \initial - attribute \src "libresoc.v:181380.9-181380.17" + attribute \src "libresoc.v:181128.9-181128.17" case 1'1 case end @@ -337775,58 +337481,58 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11212 $5\wr_detect$4[0:0]$11216 + assign $1\wr_detect$4[0:0]$11206 $5\wr_detect$4[0:0]$11210 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11213 1'1 + assign $2\wr_detect$4[0:0]$11207 1'1 case - assign $2\wr_detect$4[0:0]$11213 1'0 + assign $2\wr_detect$4[0:0]$11207 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11214 1'1 + assign $3\wr_detect$4[0:0]$11208 1'1 case - assign $3\wr_detect$4[0:0]$11214 $2\wr_detect$4[0:0]$11213 + assign $3\wr_detect$4[0:0]$11208 $2\wr_detect$4[0:0]$11207 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11215 1'1 + assign $4\wr_detect$4[0:0]$11209 1'1 case - assign $4\wr_detect$4[0:0]$11215 $3\wr_detect$4[0:0]$11214 + assign $4\wr_detect$4[0:0]$11209 $3\wr_detect$4[0:0]$11208 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11216 1'1 + assign $5\wr_detect$4[0:0]$11210 1'1 case - assign $5\wr_detect$4[0:0]$11216 $4\wr_detect$4[0:0]$11215 + assign $5\wr_detect$4[0:0]$11210 $4\wr_detect$4[0:0]$11209 end case - assign $1\wr_detect$4[0:0]$11212 1'0 + assign $1\wr_detect$4[0:0]$11206 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11211 + update \wr_detect$4 $0\wr_detect$4[0:0]$11205 end - attribute \src "libresoc.v:181415.3-181460.6" - process $proc$libresoc.v:181415$11217 + attribute \src "libresoc.v:181163.3-181208.6" + process $proc$libresoc.v:181163$11211 assign { } { } assign { } { } assign { } { } - assign $0\sv2__data_o$next[63:0]$11218 $7\sv2__data_o$next[63:0]$11225 - attribute \src "libresoc.v:181416.5-181416.29" + assign $0\sv2__data_o$next[63:0]$11212 $7\sv2__data_o$next[63:0]$11219 + attribute \src "libresoc.v:181164.5-181164.29" switch \initial - attribute \src "libresoc.v:181416.9-181416.17" + attribute \src "libresoc.v:181164.9-181164.17" case 1'1 case end @@ -337839,75 +337545,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\sv2__data_o$next[63:0]$11219 $6\sv2__data_o$next[63:0]$11224 + assign $1\sv2__data_o$next[63:0]$11213 $6\sv2__data_o$next[63:0]$11218 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv2__data_o$next[63:0]$11220 \nia2__data_i + assign $2\sv2__data_o$next[63:0]$11214 \nia2__data_i case - assign $2\sv2__data_o$next[63:0]$11220 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv2__data_o$next[63:0]$11214 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv2__data_o$next[63:0]$11221 \msr2__data_i + assign $3\sv2__data_o$next[63:0]$11215 \msr2__data_i case - assign $3\sv2__data_o$next[63:0]$11221 $2\sv2__data_o$next[63:0]$11220 + assign $3\sv2__data_o$next[63:0]$11215 $2\sv2__data_o$next[63:0]$11214 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv2__data_o$next[63:0]$11222 \sv2__data_i + assign $4\sv2__data_o$next[63:0]$11216 \sv2__data_i case - assign $4\sv2__data_o$next[63:0]$11222 $3\sv2__data_o$next[63:0]$11221 + assign $4\sv2__data_o$next[63:0]$11216 $3\sv2__data_o$next[63:0]$11215 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv2__data_o$next[63:0]$11223 \d_wr12__data_i + assign $5\sv2__data_o$next[63:0]$11217 \d_wr12__data_i case - assign $5\sv2__data_o$next[63:0]$11223 $4\sv2__data_o$next[63:0]$11222 + assign $5\sv2__data_o$next[63:0]$11217 $4\sv2__data_o$next[63:0]$11216 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv2__data_o$next[63:0]$11224 \reg + assign $6\sv2__data_o$next[63:0]$11218 \reg case - assign $6\sv2__data_o$next[63:0]$11224 $5\sv2__data_o$next[63:0]$11223 + assign $6\sv2__data_o$next[63:0]$11218 $5\sv2__data_o$next[63:0]$11217 end case - assign $1\sv2__data_o$next[63:0]$11219 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv2__data_o$next[63:0]$11213 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv2__data_o$next[63:0]$11225 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv2__data_o$next[63:0]$11219 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv2__data_o$next[63:0]$11225 $1\sv2__data_o$next[63:0]$11219 + assign $7\sv2__data_o$next[63:0]$11219 $1\sv2__data_o$next[63:0]$11213 end sync always - update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11218 + update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11212 end - attribute \src "libresoc.v:181461.3-181496.6" - process $proc$libresoc.v:181461$11226 + attribute \src "libresoc.v:181209.3-181244.6" + process $proc$libresoc.v:181209$11220 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11227 $1\wr_detect$7[0:0]$11228 - attribute \src "libresoc.v:181462.5-181462.29" + assign $0\wr_detect$7[0:0]$11221 $1\wr_detect$7[0:0]$11222 + attribute \src "libresoc.v:181210.5-181210.29" switch \initial - attribute \src "libresoc.v:181462.9-181462.17" + attribute \src "libresoc.v:181210.9-181210.17" case 1'1 case end @@ -337920,61 +337626,61 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11228 $5\wr_detect$7[0:0]$11232 + assign $1\wr_detect$7[0:0]$11222 $5\wr_detect$7[0:0]$11226 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11229 1'1 + assign $2\wr_detect$7[0:0]$11223 1'1 case - assign $2\wr_detect$7[0:0]$11229 1'0 + assign $2\wr_detect$7[0:0]$11223 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11230 1'1 + assign $3\wr_detect$7[0:0]$11224 1'1 case - assign $3\wr_detect$7[0:0]$11230 $2\wr_detect$7[0:0]$11229 + assign $3\wr_detect$7[0:0]$11224 $2\wr_detect$7[0:0]$11223 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11231 1'1 + assign $4\wr_detect$7[0:0]$11225 1'1 case - assign $4\wr_detect$7[0:0]$11231 $3\wr_detect$7[0:0]$11230 + assign $4\wr_detect$7[0:0]$11225 $3\wr_detect$7[0:0]$11224 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11232 1'1 + assign $5\wr_detect$7[0:0]$11226 1'1 case - assign $5\wr_detect$7[0:0]$11232 $4\wr_detect$7[0:0]$11231 + assign $5\wr_detect$7[0:0]$11226 $4\wr_detect$7[0:0]$11225 end case - assign $1\wr_detect$7[0:0]$11228 1'0 + assign $1\wr_detect$7[0:0]$11222 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11227 + update \wr_detect$7 $0\wr_detect$7[0:0]$11221 end - attribute \src "libresoc.v:181497.3-181529.6" - process $proc$libresoc.v:181497$11233 + attribute \src "libresoc.v:181245.3-181277.6" + process $proc$libresoc.v:181245$11227 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11234 $5\reg$next[63:0]$11239 - attribute \src "libresoc.v:181498.5-181498.29" + assign $0\reg$next[63:0]$11228 $5\reg$next[63:0]$11233 + attribute \src "libresoc.v:181246.5-181246.29" switch \initial - attribute \src "libresoc.v:181498.9-181498.17" + attribute \src "libresoc.v:181246.9-181246.17" case 1'1 case end @@ -337983,224 +337689,224 @@ module \reg_2$137 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11235 \nia2__data_i + assign $1\reg$next[63:0]$11229 \nia2__data_i case - assign $1\reg$next[63:0]$11235 \reg + assign $1\reg$next[63:0]$11229 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11236 \msr2__data_i + assign $2\reg$next[63:0]$11230 \msr2__data_i case - assign $2\reg$next[63:0]$11236 $1\reg$next[63:0]$11235 + assign $2\reg$next[63:0]$11230 $1\reg$next[63:0]$11229 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11237 \sv2__data_i + assign $3\reg$next[63:0]$11231 \sv2__data_i case - assign $3\reg$next[63:0]$11237 $2\reg$next[63:0]$11236 + assign $3\reg$next[63:0]$11231 $2\reg$next[63:0]$11230 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11238 \d_wr12__data_i + assign $4\reg$next[63:0]$11232 \d_wr12__data_i case - assign $4\reg$next[63:0]$11238 $3\reg$next[63:0]$11237 + assign $4\reg$next[63:0]$11232 $3\reg$next[63:0]$11231 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11239 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11233 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11239 $4\reg$next[63:0]$11238 + assign $5\reg$next[63:0]$11233 $4\reg$next[63:0]$11232 end sync always - update \reg$next $0\reg$next[63:0]$11234 + update \reg$next $0\reg$next[63:0]$11228 end - connect \$1 $not$libresoc.v:181240$11184_Y - connect \$3 $not$libresoc.v:181241$11185_Y - connect \$6 $not$libresoc.v:181242$11186_Y + connect \$1 $not$libresoc.v:180988$11178_Y + connect \$3 $not$libresoc.v:180989$11179_Y + connect \$6 $not$libresoc.v:180990$11180_Y end -attribute \src "libresoc.v:181534.1-182005.10" +attribute \src "libresoc.v:181282.1-181753.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" attribute \generator "nMigen" module \reg_3 - attribute \src "libresoc.v:181535.7-181535.20" + attribute \src "libresoc.v:181283.7-181283.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181935.3-181974.6" - wire width 4 $0\r23__data_o$next[3:0]$11314 - attribute \src "libresoc.v:181618.3-181619.39" + attribute \src "libresoc.v:181683.3-181722.6" + wire width 4 $0\r23__data_o$next[3:0]$11308 + attribute \src "libresoc.v:181366.3-181367.39" wire width 4 $0\r23__data_o[3:0] - attribute \src "libresoc.v:181865.3-181904.6" - wire width 4 $0\r3__data_o$next[3:0]$11300 - attribute \src "libresoc.v:181620.3-181621.37" + attribute \src "libresoc.v:181613.3-181652.6" + wire width 4 $0\r3__data_o$next[3:0]$11294 + attribute \src "libresoc.v:181368.3-181369.37" wire width 4 $0\r3__data_o[3:0] - attribute \src "libresoc.v:181698.3-181724.6" - wire width 4 $0\reg$next[3:0]$11266 - attribute \src "libresoc.v:181616.3-181617.25" + attribute \src "libresoc.v:181446.3-181472.6" + wire width 4 $0\reg$next[3:0]$11260 + attribute \src "libresoc.v:181364.3-181365.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:181628.3-181667.6" - wire width 4 $0\src13__data_o$next[3:0]$11257 - attribute \src "libresoc.v:181626.3-181627.43" + attribute \src "libresoc.v:181376.3-181415.6" + wire width 4 $0\src13__data_o$next[3:0]$11251 + attribute \src "libresoc.v:181374.3-181375.43" wire width 4 $0\src13__data_o[3:0] - attribute \src "libresoc.v:181725.3-181764.6" - wire width 4 $0\src23__data_o$next[3:0]$11272 - attribute \src "libresoc.v:181624.3-181625.43" + attribute \src "libresoc.v:181473.3-181512.6" + wire width 4 $0\src23__data_o$next[3:0]$11266 + attribute \src "libresoc.v:181372.3-181373.43" wire width 4 $0\src23__data_o[3:0] - attribute \src "libresoc.v:181795.3-181834.6" - wire width 4 $0\src33__data_o$next[3:0]$11286 - attribute \src "libresoc.v:181622.3-181623.43" + attribute \src "libresoc.v:181543.3-181582.6" + wire width 4 $0\src33__data_o$next[3:0]$11280 + attribute \src "libresoc.v:181370.3-181371.43" wire width 4 $0\src33__data_o[3:0] - attribute \src "libresoc.v:181905.3-181934.6" - wire $0\wr_detect$10[0:0]$11308 - attribute \src "libresoc.v:181975.3-182004.6" - wire $0\wr_detect$13[0:0]$11322 - attribute \src "libresoc.v:181765.3-181794.6" - wire $0\wr_detect$4[0:0]$11280 - attribute \src "libresoc.v:181835.3-181864.6" - wire $0\wr_detect$7[0:0]$11294 - attribute \src "libresoc.v:181668.3-181697.6" + attribute \src "libresoc.v:181653.3-181682.6" + wire $0\wr_detect$10[0:0]$11302 + attribute \src "libresoc.v:181723.3-181752.6" + wire $0\wr_detect$13[0:0]$11316 + attribute \src "libresoc.v:181513.3-181542.6" + wire $0\wr_detect$4[0:0]$11274 + attribute \src "libresoc.v:181583.3-181612.6" + wire $0\wr_detect$7[0:0]$11288 + attribute \src "libresoc.v:181416.3-181445.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:181935.3-181974.6" - wire width 4 $1\r23__data_o$next[3:0]$11315 - attribute \src "libresoc.v:181560.13-181560.31" + attribute \src "libresoc.v:181683.3-181722.6" + wire width 4 $1\r23__data_o$next[3:0]$11309 + attribute \src "libresoc.v:181308.13-181308.31" wire width 4 $1\r23__data_o[3:0] - attribute \src "libresoc.v:181865.3-181904.6" - wire width 4 $1\r3__data_o$next[3:0]$11301 - attribute \src "libresoc.v:181567.13-181567.30" + attribute \src "libresoc.v:181613.3-181652.6" + wire width 4 $1\r3__data_o$next[3:0]$11295 + attribute \src "libresoc.v:181315.13-181315.30" wire width 4 $1\r3__data_o[3:0] - attribute \src "libresoc.v:181698.3-181724.6" - wire width 4 $1\reg$next[3:0]$11267 - attribute \src "libresoc.v:181573.13-181573.25" + attribute \src "libresoc.v:181446.3-181472.6" + wire width 4 $1\reg$next[3:0]$11261 + attribute \src "libresoc.v:181321.13-181321.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:181628.3-181667.6" - wire width 4 $1\src13__data_o$next[3:0]$11258 - attribute \src "libresoc.v:181578.13-181578.33" + attribute \src "libresoc.v:181376.3-181415.6" + wire width 4 $1\src13__data_o$next[3:0]$11252 + attribute \src "libresoc.v:181326.13-181326.33" wire width 4 $1\src13__data_o[3:0] - attribute \src "libresoc.v:181725.3-181764.6" - wire width 4 $1\src23__data_o$next[3:0]$11273 - attribute \src "libresoc.v:181585.13-181585.33" + attribute \src "libresoc.v:181473.3-181512.6" + wire width 4 $1\src23__data_o$next[3:0]$11267 + attribute \src "libresoc.v:181333.13-181333.33" wire width 4 $1\src23__data_o[3:0] - attribute \src "libresoc.v:181795.3-181834.6" - wire width 4 $1\src33__data_o$next[3:0]$11287 - attribute \src "libresoc.v:181592.13-181592.33" + attribute \src "libresoc.v:181543.3-181582.6" + wire width 4 $1\src33__data_o$next[3:0]$11281 + attribute \src "libresoc.v:181340.13-181340.33" wire width 4 $1\src33__data_o[3:0] - attribute \src "libresoc.v:181905.3-181934.6" - wire $1\wr_detect$10[0:0]$11309 - attribute \src "libresoc.v:181975.3-182004.6" - wire $1\wr_detect$13[0:0]$11323 - attribute \src "libresoc.v:181765.3-181794.6" - wire $1\wr_detect$4[0:0]$11281 - attribute \src "libresoc.v:181835.3-181864.6" - wire $1\wr_detect$7[0:0]$11295 - attribute \src "libresoc.v:181668.3-181697.6" + attribute \src "libresoc.v:181653.3-181682.6" + wire $1\wr_detect$10[0:0]$11303 + attribute \src "libresoc.v:181723.3-181752.6" + wire $1\wr_detect$13[0:0]$11317 + attribute \src "libresoc.v:181513.3-181542.6" + wire $1\wr_detect$4[0:0]$11275 + attribute \src "libresoc.v:181583.3-181612.6" + wire $1\wr_detect$7[0:0]$11289 + attribute \src "libresoc.v:181416.3-181445.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:181935.3-181974.6" - wire width 4 $2\r23__data_o$next[3:0]$11316 - attribute \src "libresoc.v:181865.3-181904.6" - wire width 4 $2\r3__data_o$next[3:0]$11302 - attribute \src "libresoc.v:181698.3-181724.6" - wire width 4 $2\reg$next[3:0]$11268 - attribute \src "libresoc.v:181628.3-181667.6" - wire width 4 $2\src13__data_o$next[3:0]$11259 - attribute \src "libresoc.v:181725.3-181764.6" - wire width 4 $2\src23__data_o$next[3:0]$11274 - attribute \src "libresoc.v:181795.3-181834.6" - wire width 4 $2\src33__data_o$next[3:0]$11288 - attribute \src "libresoc.v:181905.3-181934.6" - wire $2\wr_detect$10[0:0]$11310 - attribute \src "libresoc.v:181975.3-182004.6" - wire $2\wr_detect$13[0:0]$11324 - attribute \src "libresoc.v:181765.3-181794.6" - wire $2\wr_detect$4[0:0]$11282 - attribute \src "libresoc.v:181835.3-181864.6" - wire $2\wr_detect$7[0:0]$11296 - attribute \src "libresoc.v:181668.3-181697.6" + attribute \src "libresoc.v:181683.3-181722.6" + wire width 4 $2\r23__data_o$next[3:0]$11310 + attribute \src "libresoc.v:181613.3-181652.6" + wire width 4 $2\r3__data_o$next[3:0]$11296 + attribute \src "libresoc.v:181446.3-181472.6" + wire width 4 $2\reg$next[3:0]$11262 + attribute \src "libresoc.v:181376.3-181415.6" + wire width 4 $2\src13__data_o$next[3:0]$11253 + attribute \src "libresoc.v:181473.3-181512.6" + wire width 4 $2\src23__data_o$next[3:0]$11268 + attribute \src "libresoc.v:181543.3-181582.6" + wire width 4 $2\src33__data_o$next[3:0]$11282 + attribute \src "libresoc.v:181653.3-181682.6" + wire $2\wr_detect$10[0:0]$11304 + attribute \src "libresoc.v:181723.3-181752.6" + wire $2\wr_detect$13[0:0]$11318 + attribute \src "libresoc.v:181513.3-181542.6" + wire $2\wr_detect$4[0:0]$11276 + attribute \src "libresoc.v:181583.3-181612.6" + wire $2\wr_detect$7[0:0]$11290 + attribute \src "libresoc.v:181416.3-181445.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:181935.3-181974.6" - wire width 4 $3\r23__data_o$next[3:0]$11317 - attribute \src "libresoc.v:181865.3-181904.6" - wire width 4 $3\r3__data_o$next[3:0]$11303 - attribute \src "libresoc.v:181698.3-181724.6" - wire width 4 $3\reg$next[3:0]$11269 - attribute \src "libresoc.v:181628.3-181667.6" - wire width 4 $3\src13__data_o$next[3:0]$11260 - attribute \src "libresoc.v:181725.3-181764.6" - wire width 4 $3\src23__data_o$next[3:0]$11275 - attribute \src "libresoc.v:181795.3-181834.6" - wire width 4 $3\src33__data_o$next[3:0]$11289 - attribute \src "libresoc.v:181905.3-181934.6" - wire $3\wr_detect$10[0:0]$11311 - attribute \src "libresoc.v:181975.3-182004.6" - wire $3\wr_detect$13[0:0]$11325 - attribute \src "libresoc.v:181765.3-181794.6" - wire $3\wr_detect$4[0:0]$11283 - attribute \src "libresoc.v:181835.3-181864.6" - wire $3\wr_detect$7[0:0]$11297 - attribute \src "libresoc.v:181668.3-181697.6" + attribute \src "libresoc.v:181683.3-181722.6" + wire width 4 $3\r23__data_o$next[3:0]$11311 + attribute \src "libresoc.v:181613.3-181652.6" + wire width 4 $3\r3__data_o$next[3:0]$11297 + attribute \src "libresoc.v:181446.3-181472.6" + wire width 4 $3\reg$next[3:0]$11263 + attribute \src "libresoc.v:181376.3-181415.6" + wire width 4 $3\src13__data_o$next[3:0]$11254 + attribute \src "libresoc.v:181473.3-181512.6" + wire width 4 $3\src23__data_o$next[3:0]$11269 + attribute \src "libresoc.v:181543.3-181582.6" + wire width 4 $3\src33__data_o$next[3:0]$11283 + attribute \src "libresoc.v:181653.3-181682.6" + wire $3\wr_detect$10[0:0]$11305 + attribute \src "libresoc.v:181723.3-181752.6" + wire $3\wr_detect$13[0:0]$11319 + attribute \src "libresoc.v:181513.3-181542.6" + wire $3\wr_detect$4[0:0]$11277 + attribute \src "libresoc.v:181583.3-181612.6" + wire $3\wr_detect$7[0:0]$11291 + attribute \src "libresoc.v:181416.3-181445.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:181935.3-181974.6" - wire width 4 $4\r23__data_o$next[3:0]$11318 - attribute \src "libresoc.v:181865.3-181904.6" - wire width 4 $4\r3__data_o$next[3:0]$11304 - attribute \src "libresoc.v:181698.3-181724.6" - wire width 4 $4\reg$next[3:0]$11270 - attribute \src "libresoc.v:181628.3-181667.6" - wire width 4 $4\src13__data_o$next[3:0]$11261 - attribute \src "libresoc.v:181725.3-181764.6" - wire width 4 $4\src23__data_o$next[3:0]$11276 - attribute \src "libresoc.v:181795.3-181834.6" - wire width 4 $4\src33__data_o$next[3:0]$11290 - attribute \src "libresoc.v:181905.3-181934.6" - wire $4\wr_detect$10[0:0]$11312 - attribute \src "libresoc.v:181975.3-182004.6" - wire $4\wr_detect$13[0:0]$11326 - attribute \src "libresoc.v:181765.3-181794.6" - wire $4\wr_detect$4[0:0]$11284 - attribute \src "libresoc.v:181835.3-181864.6" - wire $4\wr_detect$7[0:0]$11298 - attribute \src "libresoc.v:181668.3-181697.6" + attribute \src "libresoc.v:181683.3-181722.6" + wire width 4 $4\r23__data_o$next[3:0]$11312 + attribute \src "libresoc.v:181613.3-181652.6" + wire width 4 $4\r3__data_o$next[3:0]$11298 + attribute \src "libresoc.v:181446.3-181472.6" + wire width 4 $4\reg$next[3:0]$11264 + attribute \src "libresoc.v:181376.3-181415.6" + wire width 4 $4\src13__data_o$next[3:0]$11255 + attribute \src "libresoc.v:181473.3-181512.6" + wire width 4 $4\src23__data_o$next[3:0]$11270 + attribute \src "libresoc.v:181543.3-181582.6" + wire width 4 $4\src33__data_o$next[3:0]$11284 + attribute \src "libresoc.v:181653.3-181682.6" + wire $4\wr_detect$10[0:0]$11306 + attribute \src "libresoc.v:181723.3-181752.6" + wire $4\wr_detect$13[0:0]$11320 + attribute \src "libresoc.v:181513.3-181542.6" + wire $4\wr_detect$4[0:0]$11278 + attribute \src "libresoc.v:181583.3-181612.6" + wire $4\wr_detect$7[0:0]$11292 + attribute \src "libresoc.v:181416.3-181445.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:181935.3-181974.6" - wire width 4 $5\r23__data_o$next[3:0]$11319 - attribute \src "libresoc.v:181865.3-181904.6" - wire width 4 $5\r3__data_o$next[3:0]$11305 - attribute \src "libresoc.v:181628.3-181667.6" - wire width 4 $5\src13__data_o$next[3:0]$11262 - attribute \src "libresoc.v:181725.3-181764.6" - wire width 4 $5\src23__data_o$next[3:0]$11277 - attribute \src "libresoc.v:181795.3-181834.6" - wire width 4 $5\src33__data_o$next[3:0]$11291 - attribute \src "libresoc.v:181935.3-181974.6" - wire width 4 $6\r23__data_o$next[3:0]$11320 - attribute \src "libresoc.v:181865.3-181904.6" - wire width 4 $6\r3__data_o$next[3:0]$11306 - attribute \src "libresoc.v:181628.3-181667.6" - wire width 4 $6\src13__data_o$next[3:0]$11263 - attribute \src "libresoc.v:181725.3-181764.6" - wire width 4 $6\src23__data_o$next[3:0]$11278 - attribute \src "libresoc.v:181795.3-181834.6" - wire width 4 $6\src33__data_o$next[3:0]$11292 - attribute \src "libresoc.v:181611.17-181611.104" - wire $not$libresoc.v:181611$11245_Y - attribute \src "libresoc.v:181612.18-181612.105" - wire $not$libresoc.v:181612$11246_Y - attribute \src "libresoc.v:181613.17-181613.100" - wire $not$libresoc.v:181613$11247_Y - attribute \src "libresoc.v:181614.17-181614.103" - wire $not$libresoc.v:181614$11248_Y - attribute \src "libresoc.v:181615.17-181615.103" - wire $not$libresoc.v:181615$11249_Y + attribute \src "libresoc.v:181683.3-181722.6" + wire width 4 $5\r23__data_o$next[3:0]$11313 + attribute \src "libresoc.v:181613.3-181652.6" + wire width 4 $5\r3__data_o$next[3:0]$11299 + attribute \src "libresoc.v:181376.3-181415.6" + wire width 4 $5\src13__data_o$next[3:0]$11256 + attribute \src "libresoc.v:181473.3-181512.6" + wire width 4 $5\src23__data_o$next[3:0]$11271 + attribute \src "libresoc.v:181543.3-181582.6" + wire width 4 $5\src33__data_o$next[3:0]$11285 + attribute \src "libresoc.v:181683.3-181722.6" + wire width 4 $6\r23__data_o$next[3:0]$11314 + attribute \src "libresoc.v:181613.3-181652.6" + wire width 4 $6\r3__data_o$next[3:0]$11300 + attribute \src "libresoc.v:181376.3-181415.6" + wire width 4 $6\src13__data_o$next[3:0]$11257 + attribute \src "libresoc.v:181473.3-181512.6" + wire width 4 $6\src23__data_o$next[3:0]$11272 + attribute \src "libresoc.v:181543.3-181582.6" + wire width 4 $6\src33__data_o$next[3:0]$11286 + attribute \src "libresoc.v:181359.17-181359.104" + wire $not$libresoc.v:181359$11239_Y + attribute \src "libresoc.v:181360.18-181360.105" + wire $not$libresoc.v:181360$11240_Y + attribute \src "libresoc.v:181361.17-181361.100" + wire $not$libresoc.v:181361$11241_Y + attribute \src "libresoc.v:181362.17-181362.103" + wire $not$libresoc.v:181362$11242_Y + attribute \src "libresoc.v:181363.17-181363.103" + wire $not$libresoc.v:181363$11243_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -338211,9 +337917,9 @@ module \reg_3 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest13__data_i @@ -338223,7 +337929,7 @@ module \reg_3 wire width 4 input 11 \dest23__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest23__wen - attribute \src "libresoc.v:181535.7-181535.15" + attribute \src "libresoc.v:181283.7-181283.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r23__data_o @@ -338274,152 +337980,152 @@ module \reg_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181611$11245 + cell $not $not$libresoc.v:181359$11239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:181611$11245_Y + connect \Y $not$libresoc.v:181359$11239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181612$11246 + cell $not $not$libresoc.v:181360$11240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:181612$11246_Y + connect \Y $not$libresoc.v:181360$11240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181613$11247 + cell $not $not$libresoc.v:181361$11241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:181613$11247_Y + connect \Y $not$libresoc.v:181361$11241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181614$11248 + cell $not $not$libresoc.v:181362$11242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:181614$11248_Y + connect \Y $not$libresoc.v:181362$11242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181615$11249 + cell $not $not$libresoc.v:181363$11243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:181615$11249_Y + connect \Y $not$libresoc.v:181363$11243_Y end - attribute \src "libresoc.v:181535.7-181535.20" - process $proc$libresoc.v:181535$11327 + attribute \src "libresoc.v:181283.7-181283.20" + process $proc$libresoc.v:181283$11321 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181560.13-181560.31" - process $proc$libresoc.v:181560$11328 + attribute \src "libresoc.v:181308.13-181308.31" + process $proc$libresoc.v:181308$11322 assign { } { } assign $1\r23__data_o[3:0] 4'0000 sync always sync init update \r23__data_o $1\r23__data_o[3:0] end - attribute \src "libresoc.v:181567.13-181567.30" - process $proc$libresoc.v:181567$11329 + attribute \src "libresoc.v:181315.13-181315.30" + process $proc$libresoc.v:181315$11323 assign { } { } assign $1\r3__data_o[3:0] 4'0000 sync always sync init update \r3__data_o $1\r3__data_o[3:0] end - attribute \src "libresoc.v:181573.13-181573.25" - process $proc$libresoc.v:181573$11330 + attribute \src "libresoc.v:181321.13-181321.25" + process $proc$libresoc.v:181321$11324 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:181578.13-181578.33" - process $proc$libresoc.v:181578$11331 + attribute \src "libresoc.v:181326.13-181326.33" + process $proc$libresoc.v:181326$11325 assign { } { } assign $1\src13__data_o[3:0] 4'0000 sync always sync init update \src13__data_o $1\src13__data_o[3:0] end - attribute \src "libresoc.v:181585.13-181585.33" - process $proc$libresoc.v:181585$11332 + attribute \src "libresoc.v:181333.13-181333.33" + process $proc$libresoc.v:181333$11326 assign { } { } assign $1\src23__data_o[3:0] 4'0000 sync always sync init update \src23__data_o $1\src23__data_o[3:0] end - attribute \src "libresoc.v:181592.13-181592.33" - process $proc$libresoc.v:181592$11333 + attribute \src "libresoc.v:181340.13-181340.33" + process $proc$libresoc.v:181340$11327 assign { } { } assign $1\src33__data_o[3:0] 4'0000 sync always sync init update \src33__data_o $1\src33__data_o[3:0] end - attribute \src "libresoc.v:181616.3-181617.25" - process $proc$libresoc.v:181616$11250 + attribute \src "libresoc.v:181364.3-181365.25" + process $proc$libresoc.v:181364$11244 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:181618.3-181619.39" - process $proc$libresoc.v:181618$11251 + attribute \src "libresoc.v:181366.3-181367.39" + process $proc$libresoc.v:181366$11245 assign { } { } assign $0\r23__data_o[3:0] \r23__data_o$next sync posedge \coresync_clk update \r23__data_o $0\r23__data_o[3:0] end - attribute \src "libresoc.v:181620.3-181621.37" - process $proc$libresoc.v:181620$11252 + attribute \src "libresoc.v:181368.3-181369.37" + process $proc$libresoc.v:181368$11246 assign { } { } assign $0\r3__data_o[3:0] \r3__data_o$next sync posedge \coresync_clk update \r3__data_o $0\r3__data_o[3:0] end - attribute \src "libresoc.v:181622.3-181623.43" - process $proc$libresoc.v:181622$11253 + attribute \src "libresoc.v:181370.3-181371.43" + process $proc$libresoc.v:181370$11247 assign { } { } assign $0\src33__data_o[3:0] \src33__data_o$next sync posedge \coresync_clk update \src33__data_o $0\src33__data_o[3:0] end - attribute \src "libresoc.v:181624.3-181625.43" - process $proc$libresoc.v:181624$11254 + attribute \src "libresoc.v:181372.3-181373.43" + process $proc$libresoc.v:181372$11248 assign { } { } assign $0\src23__data_o[3:0] \src23__data_o$next sync posedge \coresync_clk update \src23__data_o $0\src23__data_o[3:0] end - attribute \src "libresoc.v:181626.3-181627.43" - process $proc$libresoc.v:181626$11255 + attribute \src "libresoc.v:181374.3-181375.43" + process $proc$libresoc.v:181374$11249 assign { } { } assign $0\src13__data_o[3:0] \src13__data_o$next sync posedge \coresync_clk update \src13__data_o $0\src13__data_o[3:0] end - attribute \src "libresoc.v:181628.3-181667.6" - process $proc$libresoc.v:181628$11256 + attribute \src "libresoc.v:181376.3-181415.6" + process $proc$libresoc.v:181376$11250 assign { } { } assign { } { } assign { } { } - assign $0\src13__data_o$next[3:0]$11257 $6\src13__data_o$next[3:0]$11263 - attribute \src "libresoc.v:181629.5-181629.29" + assign $0\src13__data_o$next[3:0]$11251 $6\src13__data_o$next[3:0]$11257 + attribute \src "libresoc.v:181377.5-181377.29" switch \initial - attribute \src "libresoc.v:181629.9-181629.17" + attribute \src "libresoc.v:181377.9-181377.17" case 1'1 case end @@ -338431,66 +338137,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src13__data_o$next[3:0]$11258 $5\src13__data_o$next[3:0]$11262 + assign $1\src13__data_o$next[3:0]$11252 $5\src13__data_o$next[3:0]$11256 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src13__data_o$next[3:0]$11259 \dest13__data_i + assign $2\src13__data_o$next[3:0]$11253 \dest13__data_i case - assign $2\src13__data_o$next[3:0]$11259 4'0000 + assign $2\src13__data_o$next[3:0]$11253 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src13__data_o$next[3:0]$11260 \dest23__data_i + assign $3\src13__data_o$next[3:0]$11254 \dest23__data_i case - assign $3\src13__data_o$next[3:0]$11260 $2\src13__data_o$next[3:0]$11259 + assign $3\src13__data_o$next[3:0]$11254 $2\src13__data_o$next[3:0]$11253 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src13__data_o$next[3:0]$11261 \w3__data_i + assign $4\src13__data_o$next[3:0]$11255 \w3__data_i case - assign $4\src13__data_o$next[3:0]$11261 $3\src13__data_o$next[3:0]$11260 + assign $4\src13__data_o$next[3:0]$11255 $3\src13__data_o$next[3:0]$11254 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src13__data_o$next[3:0]$11262 \reg + assign $5\src13__data_o$next[3:0]$11256 \reg case - assign $5\src13__data_o$next[3:0]$11262 $4\src13__data_o$next[3:0]$11261 + assign $5\src13__data_o$next[3:0]$11256 $4\src13__data_o$next[3:0]$11255 end case - assign $1\src13__data_o$next[3:0]$11258 4'0000 + assign $1\src13__data_o$next[3:0]$11252 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src13__data_o$next[3:0]$11263 4'0000 + assign $6\src13__data_o$next[3:0]$11257 4'0000 case - assign $6\src13__data_o$next[3:0]$11263 $1\src13__data_o$next[3:0]$11258 + assign $6\src13__data_o$next[3:0]$11257 $1\src13__data_o$next[3:0]$11252 end sync always - update \src13__data_o$next $0\src13__data_o$next[3:0]$11257 + update \src13__data_o$next $0\src13__data_o$next[3:0]$11251 end - attribute \src "libresoc.v:181668.3-181697.6" - process $proc$libresoc.v:181668$11264 + attribute \src "libresoc.v:181416.3-181445.6" + process $proc$libresoc.v:181416$11258 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181669.5-181669.29" + attribute \src "libresoc.v:181417.5-181417.29" switch \initial - attribute \src "libresoc.v:181669.9-181669.17" + attribute \src "libresoc.v:181417.9-181417.17" case 1'1 case end @@ -338536,17 +338242,17 @@ module \reg_3 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181698.3-181724.6" - process $proc$libresoc.v:181698$11265 + attribute \src "libresoc.v:181446.3-181472.6" + process $proc$libresoc.v:181446$11259 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11266 $4\reg$next[3:0]$11270 - attribute \src "libresoc.v:181699.5-181699.29" + assign $0\reg$next[3:0]$11260 $4\reg$next[3:0]$11264 + attribute \src "libresoc.v:181447.5-181447.29" switch \initial - attribute \src "libresoc.v:181699.9-181699.17" + attribute \src "libresoc.v:181447.9-181447.17" case 1'1 case end @@ -338555,49 +338261,49 @@ module \reg_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11267 \dest13__data_i + assign $1\reg$next[3:0]$11261 \dest13__data_i case - assign $1\reg$next[3:0]$11267 \reg + assign $1\reg$next[3:0]$11261 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11268 \dest23__data_i + assign $2\reg$next[3:0]$11262 \dest23__data_i case - assign $2\reg$next[3:0]$11268 $1\reg$next[3:0]$11267 + assign $2\reg$next[3:0]$11262 $1\reg$next[3:0]$11261 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11269 \w3__data_i + assign $3\reg$next[3:0]$11263 \w3__data_i case - assign $3\reg$next[3:0]$11269 $2\reg$next[3:0]$11268 + assign $3\reg$next[3:0]$11263 $2\reg$next[3:0]$11262 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11270 4'0000 + assign $4\reg$next[3:0]$11264 4'0000 case - assign $4\reg$next[3:0]$11270 $3\reg$next[3:0]$11269 + assign $4\reg$next[3:0]$11264 $3\reg$next[3:0]$11263 end sync always - update \reg$next $0\reg$next[3:0]$11266 + update \reg$next $0\reg$next[3:0]$11260 end - attribute \src "libresoc.v:181725.3-181764.6" - process $proc$libresoc.v:181725$11271 + attribute \src "libresoc.v:181473.3-181512.6" + process $proc$libresoc.v:181473$11265 assign { } { } assign { } { } assign { } { } - assign $0\src23__data_o$next[3:0]$11272 $6\src23__data_o$next[3:0]$11278 - attribute \src "libresoc.v:181726.5-181726.29" + assign $0\src23__data_o$next[3:0]$11266 $6\src23__data_o$next[3:0]$11272 + attribute \src "libresoc.v:181474.5-181474.29" switch \initial - attribute \src "libresoc.v:181726.9-181726.17" + attribute \src "libresoc.v:181474.9-181474.17" case 1'1 case end @@ -338609,66 +338315,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src23__data_o$next[3:0]$11273 $5\src23__data_o$next[3:0]$11277 + assign $1\src23__data_o$next[3:0]$11267 $5\src23__data_o$next[3:0]$11271 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src23__data_o$next[3:0]$11274 \dest13__data_i + assign $2\src23__data_o$next[3:0]$11268 \dest13__data_i case - assign $2\src23__data_o$next[3:0]$11274 4'0000 + assign $2\src23__data_o$next[3:0]$11268 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src23__data_o$next[3:0]$11275 \dest23__data_i + assign $3\src23__data_o$next[3:0]$11269 \dest23__data_i case - assign $3\src23__data_o$next[3:0]$11275 $2\src23__data_o$next[3:0]$11274 + assign $3\src23__data_o$next[3:0]$11269 $2\src23__data_o$next[3:0]$11268 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src23__data_o$next[3:0]$11276 \w3__data_i + assign $4\src23__data_o$next[3:0]$11270 \w3__data_i case - assign $4\src23__data_o$next[3:0]$11276 $3\src23__data_o$next[3:0]$11275 + assign $4\src23__data_o$next[3:0]$11270 $3\src23__data_o$next[3:0]$11269 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src23__data_o$next[3:0]$11277 \reg + assign $5\src23__data_o$next[3:0]$11271 \reg case - assign $5\src23__data_o$next[3:0]$11277 $4\src23__data_o$next[3:0]$11276 + assign $5\src23__data_o$next[3:0]$11271 $4\src23__data_o$next[3:0]$11270 end case - assign $1\src23__data_o$next[3:0]$11273 4'0000 + assign $1\src23__data_o$next[3:0]$11267 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src23__data_o$next[3:0]$11278 4'0000 + assign $6\src23__data_o$next[3:0]$11272 4'0000 case - assign $6\src23__data_o$next[3:0]$11278 $1\src23__data_o$next[3:0]$11273 + assign $6\src23__data_o$next[3:0]$11272 $1\src23__data_o$next[3:0]$11267 end sync always - update \src23__data_o$next $0\src23__data_o$next[3:0]$11272 + update \src23__data_o$next $0\src23__data_o$next[3:0]$11266 end - attribute \src "libresoc.v:181765.3-181794.6" - process $proc$libresoc.v:181765$11279 + attribute \src "libresoc.v:181513.3-181542.6" + process $proc$libresoc.v:181513$11273 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11280 $1\wr_detect$4[0:0]$11281 - attribute \src "libresoc.v:181766.5-181766.29" + assign $0\wr_detect$4[0:0]$11274 $1\wr_detect$4[0:0]$11275 + attribute \src "libresoc.v:181514.5-181514.29" switch \initial - attribute \src "libresoc.v:181766.9-181766.17" + attribute \src "libresoc.v:181514.9-181514.17" case 1'1 case end @@ -338680,49 +338386,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11281 $4\wr_detect$4[0:0]$11284 + assign $1\wr_detect$4[0:0]$11275 $4\wr_detect$4[0:0]$11278 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11282 1'1 + assign $2\wr_detect$4[0:0]$11276 1'1 case - assign $2\wr_detect$4[0:0]$11282 1'0 + assign $2\wr_detect$4[0:0]$11276 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11283 1'1 + assign $3\wr_detect$4[0:0]$11277 1'1 case - assign $3\wr_detect$4[0:0]$11283 $2\wr_detect$4[0:0]$11282 + assign $3\wr_detect$4[0:0]$11277 $2\wr_detect$4[0:0]$11276 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11284 1'1 + assign $4\wr_detect$4[0:0]$11278 1'1 case - assign $4\wr_detect$4[0:0]$11284 $3\wr_detect$4[0:0]$11283 + assign $4\wr_detect$4[0:0]$11278 $3\wr_detect$4[0:0]$11277 end case - assign $1\wr_detect$4[0:0]$11281 1'0 + assign $1\wr_detect$4[0:0]$11275 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11280 + update \wr_detect$4 $0\wr_detect$4[0:0]$11274 end - attribute \src "libresoc.v:181795.3-181834.6" - process $proc$libresoc.v:181795$11285 + attribute \src "libresoc.v:181543.3-181582.6" + process $proc$libresoc.v:181543$11279 assign { } { } assign { } { } assign { } { } - assign $0\src33__data_o$next[3:0]$11286 $6\src33__data_o$next[3:0]$11292 - attribute \src "libresoc.v:181796.5-181796.29" + assign $0\src33__data_o$next[3:0]$11280 $6\src33__data_o$next[3:0]$11286 + attribute \src "libresoc.v:181544.5-181544.29" switch \initial - attribute \src "libresoc.v:181796.9-181796.17" + attribute \src "libresoc.v:181544.9-181544.17" case 1'1 case end @@ -338734,66 +338440,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src33__data_o$next[3:0]$11287 $5\src33__data_o$next[3:0]$11291 + assign $1\src33__data_o$next[3:0]$11281 $5\src33__data_o$next[3:0]$11285 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src33__data_o$next[3:0]$11288 \dest13__data_i + assign $2\src33__data_o$next[3:0]$11282 \dest13__data_i case - assign $2\src33__data_o$next[3:0]$11288 4'0000 + assign $2\src33__data_o$next[3:0]$11282 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src33__data_o$next[3:0]$11289 \dest23__data_i + assign $3\src33__data_o$next[3:0]$11283 \dest23__data_i case - assign $3\src33__data_o$next[3:0]$11289 $2\src33__data_o$next[3:0]$11288 + assign $3\src33__data_o$next[3:0]$11283 $2\src33__data_o$next[3:0]$11282 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src33__data_o$next[3:0]$11290 \w3__data_i + assign $4\src33__data_o$next[3:0]$11284 \w3__data_i case - assign $4\src33__data_o$next[3:0]$11290 $3\src33__data_o$next[3:0]$11289 + assign $4\src33__data_o$next[3:0]$11284 $3\src33__data_o$next[3:0]$11283 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src33__data_o$next[3:0]$11291 \reg + assign $5\src33__data_o$next[3:0]$11285 \reg case - assign $5\src33__data_o$next[3:0]$11291 $4\src33__data_o$next[3:0]$11290 + assign $5\src33__data_o$next[3:0]$11285 $4\src33__data_o$next[3:0]$11284 end case - assign $1\src33__data_o$next[3:0]$11287 4'0000 + assign $1\src33__data_o$next[3:0]$11281 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src33__data_o$next[3:0]$11292 4'0000 + assign $6\src33__data_o$next[3:0]$11286 4'0000 case - assign $6\src33__data_o$next[3:0]$11292 $1\src33__data_o$next[3:0]$11287 + assign $6\src33__data_o$next[3:0]$11286 $1\src33__data_o$next[3:0]$11281 end sync always - update \src33__data_o$next $0\src33__data_o$next[3:0]$11286 + update \src33__data_o$next $0\src33__data_o$next[3:0]$11280 end - attribute \src "libresoc.v:181835.3-181864.6" - process $proc$libresoc.v:181835$11293 + attribute \src "libresoc.v:181583.3-181612.6" + process $proc$libresoc.v:181583$11287 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11294 $1\wr_detect$7[0:0]$11295 - attribute \src "libresoc.v:181836.5-181836.29" + assign $0\wr_detect$7[0:0]$11288 $1\wr_detect$7[0:0]$11289 + attribute \src "libresoc.v:181584.5-181584.29" switch \initial - attribute \src "libresoc.v:181836.9-181836.17" + attribute \src "libresoc.v:181584.9-181584.17" case 1'1 case end @@ -338805,49 +338511,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11295 $4\wr_detect$7[0:0]$11298 + assign $1\wr_detect$7[0:0]$11289 $4\wr_detect$7[0:0]$11292 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11296 1'1 + assign $2\wr_detect$7[0:0]$11290 1'1 case - assign $2\wr_detect$7[0:0]$11296 1'0 + assign $2\wr_detect$7[0:0]$11290 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11297 1'1 + assign $3\wr_detect$7[0:0]$11291 1'1 case - assign $3\wr_detect$7[0:0]$11297 $2\wr_detect$7[0:0]$11296 + assign $3\wr_detect$7[0:0]$11291 $2\wr_detect$7[0:0]$11290 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11298 1'1 + assign $4\wr_detect$7[0:0]$11292 1'1 case - assign $4\wr_detect$7[0:0]$11298 $3\wr_detect$7[0:0]$11297 + assign $4\wr_detect$7[0:0]$11292 $3\wr_detect$7[0:0]$11291 end case - assign $1\wr_detect$7[0:0]$11295 1'0 + assign $1\wr_detect$7[0:0]$11289 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11294 + update \wr_detect$7 $0\wr_detect$7[0:0]$11288 end - attribute \src "libresoc.v:181865.3-181904.6" - process $proc$libresoc.v:181865$11299 + attribute \src "libresoc.v:181613.3-181652.6" + process $proc$libresoc.v:181613$11293 assign { } { } assign { } { } assign { } { } - assign $0\r3__data_o$next[3:0]$11300 $6\r3__data_o$next[3:0]$11306 - attribute \src "libresoc.v:181866.5-181866.29" + assign $0\r3__data_o$next[3:0]$11294 $6\r3__data_o$next[3:0]$11300 + attribute \src "libresoc.v:181614.5-181614.29" switch \initial - attribute \src "libresoc.v:181866.9-181866.17" + attribute \src "libresoc.v:181614.9-181614.17" case 1'1 case end @@ -338859,66 +338565,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\r3__data_o$next[3:0]$11301 $5\r3__data_o$next[3:0]$11305 + assign $1\r3__data_o$next[3:0]$11295 $5\r3__data_o$next[3:0]$11299 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r3__data_o$next[3:0]$11302 \dest13__data_i + assign $2\r3__data_o$next[3:0]$11296 \dest13__data_i case - assign $2\r3__data_o$next[3:0]$11302 4'0000 + assign $2\r3__data_o$next[3:0]$11296 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r3__data_o$next[3:0]$11303 \dest23__data_i + assign $3\r3__data_o$next[3:0]$11297 \dest23__data_i case - assign $3\r3__data_o$next[3:0]$11303 $2\r3__data_o$next[3:0]$11302 + assign $3\r3__data_o$next[3:0]$11297 $2\r3__data_o$next[3:0]$11296 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r3__data_o$next[3:0]$11304 \w3__data_i + assign $4\r3__data_o$next[3:0]$11298 \w3__data_i case - assign $4\r3__data_o$next[3:0]$11304 $3\r3__data_o$next[3:0]$11303 + assign $4\r3__data_o$next[3:0]$11298 $3\r3__data_o$next[3:0]$11297 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r3__data_o$next[3:0]$11305 \reg + assign $5\r3__data_o$next[3:0]$11299 \reg case - assign $5\r3__data_o$next[3:0]$11305 $4\r3__data_o$next[3:0]$11304 + assign $5\r3__data_o$next[3:0]$11299 $4\r3__data_o$next[3:0]$11298 end case - assign $1\r3__data_o$next[3:0]$11301 4'0000 + assign $1\r3__data_o$next[3:0]$11295 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r3__data_o$next[3:0]$11306 4'0000 + assign $6\r3__data_o$next[3:0]$11300 4'0000 case - assign $6\r3__data_o$next[3:0]$11306 $1\r3__data_o$next[3:0]$11301 + assign $6\r3__data_o$next[3:0]$11300 $1\r3__data_o$next[3:0]$11295 end sync always - update \r3__data_o$next $0\r3__data_o$next[3:0]$11300 + update \r3__data_o$next $0\r3__data_o$next[3:0]$11294 end - attribute \src "libresoc.v:181905.3-181934.6" - process $proc$libresoc.v:181905$11307 + attribute \src "libresoc.v:181653.3-181682.6" + process $proc$libresoc.v:181653$11301 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11308 $1\wr_detect$10[0:0]$11309 - attribute \src "libresoc.v:181906.5-181906.29" + assign $0\wr_detect$10[0:0]$11302 $1\wr_detect$10[0:0]$11303 + attribute \src "libresoc.v:181654.5-181654.29" switch \initial - attribute \src "libresoc.v:181906.9-181906.17" + attribute \src "libresoc.v:181654.9-181654.17" case 1'1 case end @@ -338930,49 +338636,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11309 $4\wr_detect$10[0:0]$11312 + assign $1\wr_detect$10[0:0]$11303 $4\wr_detect$10[0:0]$11306 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11310 1'1 + assign $2\wr_detect$10[0:0]$11304 1'1 case - assign $2\wr_detect$10[0:0]$11310 1'0 + assign $2\wr_detect$10[0:0]$11304 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11311 1'1 + assign $3\wr_detect$10[0:0]$11305 1'1 case - assign $3\wr_detect$10[0:0]$11311 $2\wr_detect$10[0:0]$11310 + assign $3\wr_detect$10[0:0]$11305 $2\wr_detect$10[0:0]$11304 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11312 1'1 + assign $4\wr_detect$10[0:0]$11306 1'1 case - assign $4\wr_detect$10[0:0]$11312 $3\wr_detect$10[0:0]$11311 + assign $4\wr_detect$10[0:0]$11306 $3\wr_detect$10[0:0]$11305 end case - assign $1\wr_detect$10[0:0]$11309 1'0 + assign $1\wr_detect$10[0:0]$11303 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11308 + update \wr_detect$10 $0\wr_detect$10[0:0]$11302 end - attribute \src "libresoc.v:181935.3-181974.6" - process $proc$libresoc.v:181935$11313 + attribute \src "libresoc.v:181683.3-181722.6" + process $proc$libresoc.v:181683$11307 assign { } { } assign { } { } assign { } { } - assign $0\r23__data_o$next[3:0]$11314 $6\r23__data_o$next[3:0]$11320 - attribute \src "libresoc.v:181936.5-181936.29" + assign $0\r23__data_o$next[3:0]$11308 $6\r23__data_o$next[3:0]$11314 + attribute \src "libresoc.v:181684.5-181684.29" switch \initial - attribute \src "libresoc.v:181936.9-181936.17" + attribute \src "libresoc.v:181684.9-181684.17" case 1'1 case end @@ -338984,66 +338690,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\r23__data_o$next[3:0]$11315 $5\r23__data_o$next[3:0]$11319 + assign $1\r23__data_o$next[3:0]$11309 $5\r23__data_o$next[3:0]$11313 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r23__data_o$next[3:0]$11316 \dest13__data_i + assign $2\r23__data_o$next[3:0]$11310 \dest13__data_i case - assign $2\r23__data_o$next[3:0]$11316 4'0000 + assign $2\r23__data_o$next[3:0]$11310 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r23__data_o$next[3:0]$11317 \dest23__data_i + assign $3\r23__data_o$next[3:0]$11311 \dest23__data_i case - assign $3\r23__data_o$next[3:0]$11317 $2\r23__data_o$next[3:0]$11316 + assign $3\r23__data_o$next[3:0]$11311 $2\r23__data_o$next[3:0]$11310 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r23__data_o$next[3:0]$11318 \w3__data_i + assign $4\r23__data_o$next[3:0]$11312 \w3__data_i case - assign $4\r23__data_o$next[3:0]$11318 $3\r23__data_o$next[3:0]$11317 + assign $4\r23__data_o$next[3:0]$11312 $3\r23__data_o$next[3:0]$11311 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r23__data_o$next[3:0]$11319 \reg + assign $5\r23__data_o$next[3:0]$11313 \reg case - assign $5\r23__data_o$next[3:0]$11319 $4\r23__data_o$next[3:0]$11318 + assign $5\r23__data_o$next[3:0]$11313 $4\r23__data_o$next[3:0]$11312 end case - assign $1\r23__data_o$next[3:0]$11315 4'0000 + assign $1\r23__data_o$next[3:0]$11309 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r23__data_o$next[3:0]$11320 4'0000 + assign $6\r23__data_o$next[3:0]$11314 4'0000 case - assign $6\r23__data_o$next[3:0]$11320 $1\r23__data_o$next[3:0]$11315 + assign $6\r23__data_o$next[3:0]$11314 $1\r23__data_o$next[3:0]$11309 end sync always - update \r23__data_o$next $0\r23__data_o$next[3:0]$11314 + update \r23__data_o$next $0\r23__data_o$next[3:0]$11308 end - attribute \src "libresoc.v:181975.3-182004.6" - process $proc$libresoc.v:181975$11321 + attribute \src "libresoc.v:181723.3-181752.6" + process $proc$libresoc.v:181723$11315 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11322 $1\wr_detect$13[0:0]$11323 - attribute \src "libresoc.v:181976.5-181976.29" + assign $0\wr_detect$13[0:0]$11316 $1\wr_detect$13[0:0]$11317 + attribute \src "libresoc.v:181724.5-181724.29" switch \initial - attribute \src "libresoc.v:181976.9-181976.17" + attribute \src "libresoc.v:181724.9-181724.17" case 1'1 case end @@ -339055,217 +338761,217 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11323 $4\wr_detect$13[0:0]$11326 + assign $1\wr_detect$13[0:0]$11317 $4\wr_detect$13[0:0]$11320 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11324 1'1 + assign $2\wr_detect$13[0:0]$11318 1'1 case - assign $2\wr_detect$13[0:0]$11324 1'0 + assign $2\wr_detect$13[0:0]$11318 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11325 1'1 + assign $3\wr_detect$13[0:0]$11319 1'1 case - assign $3\wr_detect$13[0:0]$11325 $2\wr_detect$13[0:0]$11324 + assign $3\wr_detect$13[0:0]$11319 $2\wr_detect$13[0:0]$11318 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11326 1'1 + assign $4\wr_detect$13[0:0]$11320 1'1 case - assign $4\wr_detect$13[0:0]$11326 $3\wr_detect$13[0:0]$11325 + assign $4\wr_detect$13[0:0]$11320 $3\wr_detect$13[0:0]$11319 end case - assign $1\wr_detect$13[0:0]$11323 1'0 + assign $1\wr_detect$13[0:0]$11317 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11322 + update \wr_detect$13 $0\wr_detect$13[0:0]$11316 end - connect \$9 $not$libresoc.v:181611$11245_Y - connect \$12 $not$libresoc.v:181612$11246_Y - connect \$1 $not$libresoc.v:181613$11247_Y - connect \$3 $not$libresoc.v:181614$11248_Y - connect \$6 $not$libresoc.v:181615$11249_Y + connect \$9 $not$libresoc.v:181359$11239_Y + connect \$12 $not$libresoc.v:181360$11240_Y + connect \$1 $not$libresoc.v:181361$11241_Y + connect \$3 $not$libresoc.v:181362$11242_Y + connect \$6 $not$libresoc.v:181363$11243_Y end -attribute \src "libresoc.v:182009.1-182480.10" +attribute \src "libresoc.v:181757.1-182228.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" attribute \generator "nMigen" module \reg_4 - attribute \src "libresoc.v:182010.7-182010.20" + attribute \src "libresoc.v:181758.7-181758.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182410.3-182449.6" - wire width 4 $0\r24__data_o$next[3:0]$11403 - attribute \src "libresoc.v:182093.3-182094.39" + attribute \src "libresoc.v:182158.3-182197.6" + wire width 4 $0\r24__data_o$next[3:0]$11397 + attribute \src "libresoc.v:181841.3-181842.39" wire width 4 $0\r24__data_o[3:0] - attribute \src "libresoc.v:182340.3-182379.6" - wire width 4 $0\r4__data_o$next[3:0]$11389 - attribute \src "libresoc.v:182095.3-182096.37" + attribute \src "libresoc.v:182088.3-182127.6" + wire width 4 $0\r4__data_o$next[3:0]$11383 + attribute \src "libresoc.v:181843.3-181844.37" wire width 4 $0\r4__data_o[3:0] - attribute \src "libresoc.v:182173.3-182199.6" - wire width 4 $0\reg$next[3:0]$11355 - attribute \src "libresoc.v:182091.3-182092.25" + attribute \src "libresoc.v:181921.3-181947.6" + wire width 4 $0\reg$next[3:0]$11349 + attribute \src "libresoc.v:181839.3-181840.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:182103.3-182142.6" - wire width 4 $0\src14__data_o$next[3:0]$11346 - attribute \src "libresoc.v:182101.3-182102.43" + attribute \src "libresoc.v:181851.3-181890.6" + wire width 4 $0\src14__data_o$next[3:0]$11340 + attribute \src "libresoc.v:181849.3-181850.43" wire width 4 $0\src14__data_o[3:0] - attribute \src "libresoc.v:182200.3-182239.6" - wire width 4 $0\src24__data_o$next[3:0]$11361 - attribute \src "libresoc.v:182099.3-182100.43" + attribute \src "libresoc.v:181948.3-181987.6" + wire width 4 $0\src24__data_o$next[3:0]$11355 + attribute \src "libresoc.v:181847.3-181848.43" wire width 4 $0\src24__data_o[3:0] - attribute \src "libresoc.v:182270.3-182309.6" - wire width 4 $0\src34__data_o$next[3:0]$11375 - attribute \src "libresoc.v:182097.3-182098.43" + attribute \src "libresoc.v:182018.3-182057.6" + wire width 4 $0\src34__data_o$next[3:0]$11369 + attribute \src "libresoc.v:181845.3-181846.43" wire width 4 $0\src34__data_o[3:0] - attribute \src "libresoc.v:182380.3-182409.6" - wire $0\wr_detect$10[0:0]$11397 - attribute \src "libresoc.v:182450.3-182479.6" - wire $0\wr_detect$13[0:0]$11411 - attribute \src "libresoc.v:182240.3-182269.6" - wire $0\wr_detect$4[0:0]$11369 - attribute \src "libresoc.v:182310.3-182339.6" - wire $0\wr_detect$7[0:0]$11383 - attribute \src "libresoc.v:182143.3-182172.6" + attribute \src "libresoc.v:182128.3-182157.6" + wire $0\wr_detect$10[0:0]$11391 + attribute \src "libresoc.v:182198.3-182227.6" + wire $0\wr_detect$13[0:0]$11405 + attribute \src "libresoc.v:181988.3-182017.6" + wire $0\wr_detect$4[0:0]$11363 + attribute \src "libresoc.v:182058.3-182087.6" + wire $0\wr_detect$7[0:0]$11377 + attribute \src "libresoc.v:181891.3-181920.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:182410.3-182449.6" - wire width 4 $1\r24__data_o$next[3:0]$11404 - attribute \src "libresoc.v:182035.13-182035.31" + attribute \src "libresoc.v:182158.3-182197.6" + wire width 4 $1\r24__data_o$next[3:0]$11398 + attribute \src "libresoc.v:181783.13-181783.31" wire width 4 $1\r24__data_o[3:0] - attribute \src "libresoc.v:182340.3-182379.6" - wire width 4 $1\r4__data_o$next[3:0]$11390 - attribute \src "libresoc.v:182042.13-182042.30" + attribute \src "libresoc.v:182088.3-182127.6" + wire width 4 $1\r4__data_o$next[3:0]$11384 + attribute \src "libresoc.v:181790.13-181790.30" wire width 4 $1\r4__data_o[3:0] - attribute \src "libresoc.v:182173.3-182199.6" - wire width 4 $1\reg$next[3:0]$11356 - attribute \src "libresoc.v:182048.13-182048.25" + attribute \src "libresoc.v:181921.3-181947.6" + wire width 4 $1\reg$next[3:0]$11350 + attribute \src "libresoc.v:181796.13-181796.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:182103.3-182142.6" - wire width 4 $1\src14__data_o$next[3:0]$11347 - attribute \src "libresoc.v:182053.13-182053.33" + attribute \src "libresoc.v:181851.3-181890.6" + wire width 4 $1\src14__data_o$next[3:0]$11341 + attribute \src "libresoc.v:181801.13-181801.33" wire width 4 $1\src14__data_o[3:0] - attribute \src "libresoc.v:182200.3-182239.6" - wire width 4 $1\src24__data_o$next[3:0]$11362 - attribute \src "libresoc.v:182060.13-182060.33" + attribute \src "libresoc.v:181948.3-181987.6" + wire width 4 $1\src24__data_o$next[3:0]$11356 + attribute \src "libresoc.v:181808.13-181808.33" wire width 4 $1\src24__data_o[3:0] - attribute \src "libresoc.v:182270.3-182309.6" - wire width 4 $1\src34__data_o$next[3:0]$11376 - attribute \src "libresoc.v:182067.13-182067.33" + attribute \src "libresoc.v:182018.3-182057.6" + wire width 4 $1\src34__data_o$next[3:0]$11370 + attribute \src "libresoc.v:181815.13-181815.33" wire width 4 $1\src34__data_o[3:0] - attribute \src "libresoc.v:182380.3-182409.6" - wire $1\wr_detect$10[0:0]$11398 - attribute \src "libresoc.v:182450.3-182479.6" - wire $1\wr_detect$13[0:0]$11412 - attribute \src "libresoc.v:182240.3-182269.6" - wire $1\wr_detect$4[0:0]$11370 - attribute \src "libresoc.v:182310.3-182339.6" - wire $1\wr_detect$7[0:0]$11384 - attribute \src "libresoc.v:182143.3-182172.6" + attribute \src "libresoc.v:182128.3-182157.6" + wire $1\wr_detect$10[0:0]$11392 + attribute \src "libresoc.v:182198.3-182227.6" + wire $1\wr_detect$13[0:0]$11406 + attribute \src "libresoc.v:181988.3-182017.6" + wire $1\wr_detect$4[0:0]$11364 + attribute \src "libresoc.v:182058.3-182087.6" + wire $1\wr_detect$7[0:0]$11378 + attribute \src "libresoc.v:181891.3-181920.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:182410.3-182449.6" - wire width 4 $2\r24__data_o$next[3:0]$11405 - attribute \src "libresoc.v:182340.3-182379.6" - wire width 4 $2\r4__data_o$next[3:0]$11391 - attribute \src "libresoc.v:182173.3-182199.6" - wire width 4 $2\reg$next[3:0]$11357 - attribute \src "libresoc.v:182103.3-182142.6" - wire width 4 $2\src14__data_o$next[3:0]$11348 - attribute \src "libresoc.v:182200.3-182239.6" - wire width 4 $2\src24__data_o$next[3:0]$11363 - attribute \src "libresoc.v:182270.3-182309.6" - wire width 4 $2\src34__data_o$next[3:0]$11377 - attribute \src "libresoc.v:182380.3-182409.6" - wire $2\wr_detect$10[0:0]$11399 - attribute \src "libresoc.v:182450.3-182479.6" - wire $2\wr_detect$13[0:0]$11413 - attribute \src "libresoc.v:182240.3-182269.6" - wire $2\wr_detect$4[0:0]$11371 - attribute \src "libresoc.v:182310.3-182339.6" - wire $2\wr_detect$7[0:0]$11385 - attribute \src "libresoc.v:182143.3-182172.6" + attribute \src "libresoc.v:182158.3-182197.6" + wire width 4 $2\r24__data_o$next[3:0]$11399 + attribute \src "libresoc.v:182088.3-182127.6" + wire width 4 $2\r4__data_o$next[3:0]$11385 + attribute \src "libresoc.v:181921.3-181947.6" + wire width 4 $2\reg$next[3:0]$11351 + attribute \src "libresoc.v:181851.3-181890.6" + wire width 4 $2\src14__data_o$next[3:0]$11342 + attribute \src "libresoc.v:181948.3-181987.6" + wire width 4 $2\src24__data_o$next[3:0]$11357 + attribute \src "libresoc.v:182018.3-182057.6" + wire width 4 $2\src34__data_o$next[3:0]$11371 + attribute \src "libresoc.v:182128.3-182157.6" + wire $2\wr_detect$10[0:0]$11393 + attribute \src "libresoc.v:182198.3-182227.6" + wire $2\wr_detect$13[0:0]$11407 + attribute \src "libresoc.v:181988.3-182017.6" + wire $2\wr_detect$4[0:0]$11365 + attribute \src "libresoc.v:182058.3-182087.6" + wire $2\wr_detect$7[0:0]$11379 + attribute \src "libresoc.v:181891.3-181920.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:182410.3-182449.6" - wire width 4 $3\r24__data_o$next[3:0]$11406 - attribute \src "libresoc.v:182340.3-182379.6" - wire width 4 $3\r4__data_o$next[3:0]$11392 - attribute \src "libresoc.v:182173.3-182199.6" - wire width 4 $3\reg$next[3:0]$11358 - attribute \src "libresoc.v:182103.3-182142.6" - wire width 4 $3\src14__data_o$next[3:0]$11349 - attribute \src "libresoc.v:182200.3-182239.6" - wire width 4 $3\src24__data_o$next[3:0]$11364 - attribute \src "libresoc.v:182270.3-182309.6" - wire width 4 $3\src34__data_o$next[3:0]$11378 - attribute \src "libresoc.v:182380.3-182409.6" - wire $3\wr_detect$10[0:0]$11400 - attribute \src "libresoc.v:182450.3-182479.6" - wire $3\wr_detect$13[0:0]$11414 - attribute \src "libresoc.v:182240.3-182269.6" - wire $3\wr_detect$4[0:0]$11372 - attribute \src "libresoc.v:182310.3-182339.6" - wire $3\wr_detect$7[0:0]$11386 - attribute \src "libresoc.v:182143.3-182172.6" + attribute \src "libresoc.v:182158.3-182197.6" + wire width 4 $3\r24__data_o$next[3:0]$11400 + attribute \src "libresoc.v:182088.3-182127.6" + wire width 4 $3\r4__data_o$next[3:0]$11386 + attribute \src "libresoc.v:181921.3-181947.6" + wire width 4 $3\reg$next[3:0]$11352 + attribute \src "libresoc.v:181851.3-181890.6" + wire width 4 $3\src14__data_o$next[3:0]$11343 + attribute \src "libresoc.v:181948.3-181987.6" + wire width 4 $3\src24__data_o$next[3:0]$11358 + attribute \src "libresoc.v:182018.3-182057.6" + wire width 4 $3\src34__data_o$next[3:0]$11372 + attribute \src "libresoc.v:182128.3-182157.6" + wire $3\wr_detect$10[0:0]$11394 + attribute \src "libresoc.v:182198.3-182227.6" + wire $3\wr_detect$13[0:0]$11408 + attribute \src "libresoc.v:181988.3-182017.6" + wire $3\wr_detect$4[0:0]$11366 + attribute \src "libresoc.v:182058.3-182087.6" + wire $3\wr_detect$7[0:0]$11380 + attribute \src "libresoc.v:181891.3-181920.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:182410.3-182449.6" - wire width 4 $4\r24__data_o$next[3:0]$11407 - attribute \src "libresoc.v:182340.3-182379.6" - wire width 4 $4\r4__data_o$next[3:0]$11393 - attribute \src "libresoc.v:182173.3-182199.6" - wire width 4 $4\reg$next[3:0]$11359 - attribute \src "libresoc.v:182103.3-182142.6" - wire width 4 $4\src14__data_o$next[3:0]$11350 - attribute \src "libresoc.v:182200.3-182239.6" - wire width 4 $4\src24__data_o$next[3:0]$11365 - attribute \src "libresoc.v:182270.3-182309.6" - wire width 4 $4\src34__data_o$next[3:0]$11379 - attribute \src "libresoc.v:182380.3-182409.6" - wire $4\wr_detect$10[0:0]$11401 - attribute \src "libresoc.v:182450.3-182479.6" - wire $4\wr_detect$13[0:0]$11415 - attribute \src "libresoc.v:182240.3-182269.6" - wire $4\wr_detect$4[0:0]$11373 - attribute \src "libresoc.v:182310.3-182339.6" - wire $4\wr_detect$7[0:0]$11387 - attribute \src "libresoc.v:182143.3-182172.6" + attribute \src "libresoc.v:182158.3-182197.6" + wire width 4 $4\r24__data_o$next[3:0]$11401 + attribute \src "libresoc.v:182088.3-182127.6" + wire width 4 $4\r4__data_o$next[3:0]$11387 + attribute \src "libresoc.v:181921.3-181947.6" + wire width 4 $4\reg$next[3:0]$11353 + attribute \src "libresoc.v:181851.3-181890.6" + wire width 4 $4\src14__data_o$next[3:0]$11344 + attribute \src "libresoc.v:181948.3-181987.6" + wire width 4 $4\src24__data_o$next[3:0]$11359 + attribute \src "libresoc.v:182018.3-182057.6" + wire width 4 $4\src34__data_o$next[3:0]$11373 + attribute \src "libresoc.v:182128.3-182157.6" + wire $4\wr_detect$10[0:0]$11395 + attribute \src "libresoc.v:182198.3-182227.6" + wire $4\wr_detect$13[0:0]$11409 + attribute \src "libresoc.v:181988.3-182017.6" + wire $4\wr_detect$4[0:0]$11367 + attribute \src "libresoc.v:182058.3-182087.6" + wire $4\wr_detect$7[0:0]$11381 + attribute \src "libresoc.v:181891.3-181920.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:182410.3-182449.6" - wire width 4 $5\r24__data_o$next[3:0]$11408 - attribute \src "libresoc.v:182340.3-182379.6" - wire width 4 $5\r4__data_o$next[3:0]$11394 - attribute \src "libresoc.v:182103.3-182142.6" - wire width 4 $5\src14__data_o$next[3:0]$11351 - attribute \src "libresoc.v:182200.3-182239.6" - wire width 4 $5\src24__data_o$next[3:0]$11366 - attribute \src "libresoc.v:182270.3-182309.6" - wire width 4 $5\src34__data_o$next[3:0]$11380 - attribute \src "libresoc.v:182410.3-182449.6" - wire width 4 $6\r24__data_o$next[3:0]$11409 - attribute \src "libresoc.v:182340.3-182379.6" - wire width 4 $6\r4__data_o$next[3:0]$11395 - attribute \src "libresoc.v:182103.3-182142.6" - wire width 4 $6\src14__data_o$next[3:0]$11352 - attribute \src "libresoc.v:182200.3-182239.6" - wire width 4 $6\src24__data_o$next[3:0]$11367 - attribute \src "libresoc.v:182270.3-182309.6" - wire width 4 $6\src34__data_o$next[3:0]$11381 - attribute \src "libresoc.v:182086.17-182086.104" - wire $not$libresoc.v:182086$11334_Y - attribute \src "libresoc.v:182087.18-182087.105" - wire $not$libresoc.v:182087$11335_Y - attribute \src "libresoc.v:182088.17-182088.100" - wire $not$libresoc.v:182088$11336_Y - attribute \src "libresoc.v:182089.17-182089.103" - wire $not$libresoc.v:182089$11337_Y - attribute \src "libresoc.v:182090.17-182090.103" - wire $not$libresoc.v:182090$11338_Y + attribute \src "libresoc.v:182158.3-182197.6" + wire width 4 $5\r24__data_o$next[3:0]$11402 + attribute \src "libresoc.v:182088.3-182127.6" + wire width 4 $5\r4__data_o$next[3:0]$11388 + attribute \src "libresoc.v:181851.3-181890.6" + wire width 4 $5\src14__data_o$next[3:0]$11345 + attribute \src "libresoc.v:181948.3-181987.6" + wire width 4 $5\src24__data_o$next[3:0]$11360 + attribute \src "libresoc.v:182018.3-182057.6" + wire width 4 $5\src34__data_o$next[3:0]$11374 + attribute \src "libresoc.v:182158.3-182197.6" + wire width 4 $6\r24__data_o$next[3:0]$11403 + attribute \src "libresoc.v:182088.3-182127.6" + wire width 4 $6\r4__data_o$next[3:0]$11389 + attribute \src "libresoc.v:181851.3-181890.6" + wire width 4 $6\src14__data_o$next[3:0]$11346 + attribute \src "libresoc.v:181948.3-181987.6" + wire width 4 $6\src24__data_o$next[3:0]$11361 + attribute \src "libresoc.v:182018.3-182057.6" + wire width 4 $6\src34__data_o$next[3:0]$11375 + attribute \src "libresoc.v:181834.17-181834.104" + wire $not$libresoc.v:181834$11328_Y + attribute \src "libresoc.v:181835.18-181835.105" + wire $not$libresoc.v:181835$11329_Y + attribute \src "libresoc.v:181836.17-181836.100" + wire $not$libresoc.v:181836$11330_Y + attribute \src "libresoc.v:181837.17-181837.103" + wire $not$libresoc.v:181837$11331_Y + attribute \src "libresoc.v:181838.17-181838.103" + wire $not$libresoc.v:181838$11332_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -339276,9 +338982,9 @@ module \reg_4 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest14__data_i @@ -339288,7 +338994,7 @@ module \reg_4 wire width 4 input 11 \dest24__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest24__wen - attribute \src "libresoc.v:182010.7-182010.15" + attribute \src "libresoc.v:181758.7-181758.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r24__data_o @@ -339339,152 +339045,152 @@ module \reg_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182086$11334 + cell $not $not$libresoc.v:181834$11328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:182086$11334_Y + connect \Y $not$libresoc.v:181834$11328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182087$11335 + cell $not $not$libresoc.v:181835$11329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:182087$11335_Y + connect \Y $not$libresoc.v:181835$11329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182088$11336 + cell $not $not$libresoc.v:181836$11330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:182088$11336_Y + connect \Y $not$libresoc.v:181836$11330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182089$11337 + cell $not $not$libresoc.v:181837$11331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:182089$11337_Y + connect \Y $not$libresoc.v:181837$11331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182090$11338 + cell $not $not$libresoc.v:181838$11332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:182090$11338_Y + connect \Y $not$libresoc.v:181838$11332_Y end - attribute \src "libresoc.v:182010.7-182010.20" - process $proc$libresoc.v:182010$11416 + attribute \src "libresoc.v:181758.7-181758.20" + process $proc$libresoc.v:181758$11410 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182035.13-182035.31" - process $proc$libresoc.v:182035$11417 + attribute \src "libresoc.v:181783.13-181783.31" + process $proc$libresoc.v:181783$11411 assign { } { } assign $1\r24__data_o[3:0] 4'0000 sync always sync init update \r24__data_o $1\r24__data_o[3:0] end - attribute \src "libresoc.v:182042.13-182042.30" - process $proc$libresoc.v:182042$11418 + attribute \src "libresoc.v:181790.13-181790.30" + process $proc$libresoc.v:181790$11412 assign { } { } assign $1\r4__data_o[3:0] 4'0000 sync always sync init update \r4__data_o $1\r4__data_o[3:0] end - attribute \src "libresoc.v:182048.13-182048.25" - process $proc$libresoc.v:182048$11419 + attribute \src "libresoc.v:181796.13-181796.25" + process $proc$libresoc.v:181796$11413 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:182053.13-182053.33" - process $proc$libresoc.v:182053$11420 + attribute \src "libresoc.v:181801.13-181801.33" + process $proc$libresoc.v:181801$11414 assign { } { } assign $1\src14__data_o[3:0] 4'0000 sync always sync init update \src14__data_o $1\src14__data_o[3:0] end - attribute \src "libresoc.v:182060.13-182060.33" - process $proc$libresoc.v:182060$11421 + attribute \src "libresoc.v:181808.13-181808.33" + process $proc$libresoc.v:181808$11415 assign { } { } assign $1\src24__data_o[3:0] 4'0000 sync always sync init update \src24__data_o $1\src24__data_o[3:0] end - attribute \src "libresoc.v:182067.13-182067.33" - process $proc$libresoc.v:182067$11422 + attribute \src "libresoc.v:181815.13-181815.33" + process $proc$libresoc.v:181815$11416 assign { } { } assign $1\src34__data_o[3:0] 4'0000 sync always sync init update \src34__data_o $1\src34__data_o[3:0] end - attribute \src "libresoc.v:182091.3-182092.25" - process $proc$libresoc.v:182091$11339 + attribute \src "libresoc.v:181839.3-181840.25" + process $proc$libresoc.v:181839$11333 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:182093.3-182094.39" - process $proc$libresoc.v:182093$11340 + attribute \src "libresoc.v:181841.3-181842.39" + process $proc$libresoc.v:181841$11334 assign { } { } assign $0\r24__data_o[3:0] \r24__data_o$next sync posedge \coresync_clk update \r24__data_o $0\r24__data_o[3:0] end - attribute \src "libresoc.v:182095.3-182096.37" - process $proc$libresoc.v:182095$11341 + attribute \src "libresoc.v:181843.3-181844.37" + process $proc$libresoc.v:181843$11335 assign { } { } assign $0\r4__data_o[3:0] \r4__data_o$next sync posedge \coresync_clk update \r4__data_o $0\r4__data_o[3:0] end - attribute \src "libresoc.v:182097.3-182098.43" - process $proc$libresoc.v:182097$11342 + attribute \src "libresoc.v:181845.3-181846.43" + process $proc$libresoc.v:181845$11336 assign { } { } assign $0\src34__data_o[3:0] \src34__data_o$next sync posedge \coresync_clk update \src34__data_o $0\src34__data_o[3:0] end - attribute \src "libresoc.v:182099.3-182100.43" - process $proc$libresoc.v:182099$11343 + attribute \src "libresoc.v:181847.3-181848.43" + process $proc$libresoc.v:181847$11337 assign { } { } assign $0\src24__data_o[3:0] \src24__data_o$next sync posedge \coresync_clk update \src24__data_o $0\src24__data_o[3:0] end - attribute \src "libresoc.v:182101.3-182102.43" - process $proc$libresoc.v:182101$11344 + attribute \src "libresoc.v:181849.3-181850.43" + process $proc$libresoc.v:181849$11338 assign { } { } assign $0\src14__data_o[3:0] \src14__data_o$next sync posedge \coresync_clk update \src14__data_o $0\src14__data_o[3:0] end - attribute \src "libresoc.v:182103.3-182142.6" - process $proc$libresoc.v:182103$11345 + attribute \src "libresoc.v:181851.3-181890.6" + process $proc$libresoc.v:181851$11339 assign { } { } assign { } { } assign { } { } - assign $0\src14__data_o$next[3:0]$11346 $6\src14__data_o$next[3:0]$11352 - attribute \src "libresoc.v:182104.5-182104.29" + assign $0\src14__data_o$next[3:0]$11340 $6\src14__data_o$next[3:0]$11346 + attribute \src "libresoc.v:181852.5-181852.29" switch \initial - attribute \src "libresoc.v:182104.9-182104.17" + attribute \src "libresoc.v:181852.9-181852.17" case 1'1 case end @@ -339496,66 +339202,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src14__data_o$next[3:0]$11347 $5\src14__data_o$next[3:0]$11351 + assign $1\src14__data_o$next[3:0]$11341 $5\src14__data_o$next[3:0]$11345 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src14__data_o$next[3:0]$11348 \dest14__data_i + assign $2\src14__data_o$next[3:0]$11342 \dest14__data_i case - assign $2\src14__data_o$next[3:0]$11348 4'0000 + assign $2\src14__data_o$next[3:0]$11342 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src14__data_o$next[3:0]$11349 \dest24__data_i + assign $3\src14__data_o$next[3:0]$11343 \dest24__data_i case - assign $3\src14__data_o$next[3:0]$11349 $2\src14__data_o$next[3:0]$11348 + assign $3\src14__data_o$next[3:0]$11343 $2\src14__data_o$next[3:0]$11342 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src14__data_o$next[3:0]$11350 \w4__data_i + assign $4\src14__data_o$next[3:0]$11344 \w4__data_i case - assign $4\src14__data_o$next[3:0]$11350 $3\src14__data_o$next[3:0]$11349 + assign $4\src14__data_o$next[3:0]$11344 $3\src14__data_o$next[3:0]$11343 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src14__data_o$next[3:0]$11351 \reg + assign $5\src14__data_o$next[3:0]$11345 \reg case - assign $5\src14__data_o$next[3:0]$11351 $4\src14__data_o$next[3:0]$11350 + assign $5\src14__data_o$next[3:0]$11345 $4\src14__data_o$next[3:0]$11344 end case - assign $1\src14__data_o$next[3:0]$11347 4'0000 + assign $1\src14__data_o$next[3:0]$11341 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src14__data_o$next[3:0]$11352 4'0000 + assign $6\src14__data_o$next[3:0]$11346 4'0000 case - assign $6\src14__data_o$next[3:0]$11352 $1\src14__data_o$next[3:0]$11347 + assign $6\src14__data_o$next[3:0]$11346 $1\src14__data_o$next[3:0]$11341 end sync always - update \src14__data_o$next $0\src14__data_o$next[3:0]$11346 + update \src14__data_o$next $0\src14__data_o$next[3:0]$11340 end - attribute \src "libresoc.v:182143.3-182172.6" - process $proc$libresoc.v:182143$11353 + attribute \src "libresoc.v:181891.3-181920.6" + process $proc$libresoc.v:181891$11347 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:182144.5-182144.29" + attribute \src "libresoc.v:181892.5-181892.29" switch \initial - attribute \src "libresoc.v:182144.9-182144.17" + attribute \src "libresoc.v:181892.9-181892.17" case 1'1 case end @@ -339601,17 +339307,17 @@ module \reg_4 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:182173.3-182199.6" - process $proc$libresoc.v:182173$11354 + attribute \src "libresoc.v:181921.3-181947.6" + process $proc$libresoc.v:181921$11348 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11355 $4\reg$next[3:0]$11359 - attribute \src "libresoc.v:182174.5-182174.29" + assign $0\reg$next[3:0]$11349 $4\reg$next[3:0]$11353 + attribute \src "libresoc.v:181922.5-181922.29" switch \initial - attribute \src "libresoc.v:182174.9-182174.17" + attribute \src "libresoc.v:181922.9-181922.17" case 1'1 case end @@ -339620,49 +339326,49 @@ module \reg_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11356 \dest14__data_i + assign $1\reg$next[3:0]$11350 \dest14__data_i case - assign $1\reg$next[3:0]$11356 \reg + assign $1\reg$next[3:0]$11350 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11357 \dest24__data_i + assign $2\reg$next[3:0]$11351 \dest24__data_i case - assign $2\reg$next[3:0]$11357 $1\reg$next[3:0]$11356 + assign $2\reg$next[3:0]$11351 $1\reg$next[3:0]$11350 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11358 \w4__data_i + assign $3\reg$next[3:0]$11352 \w4__data_i case - assign $3\reg$next[3:0]$11358 $2\reg$next[3:0]$11357 + assign $3\reg$next[3:0]$11352 $2\reg$next[3:0]$11351 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11359 4'0000 + assign $4\reg$next[3:0]$11353 4'0000 case - assign $4\reg$next[3:0]$11359 $3\reg$next[3:0]$11358 + assign $4\reg$next[3:0]$11353 $3\reg$next[3:0]$11352 end sync always - update \reg$next $0\reg$next[3:0]$11355 + update \reg$next $0\reg$next[3:0]$11349 end - attribute \src "libresoc.v:182200.3-182239.6" - process $proc$libresoc.v:182200$11360 + attribute \src "libresoc.v:181948.3-181987.6" + process $proc$libresoc.v:181948$11354 assign { } { } assign { } { } assign { } { } - assign $0\src24__data_o$next[3:0]$11361 $6\src24__data_o$next[3:0]$11367 - attribute \src "libresoc.v:182201.5-182201.29" + assign $0\src24__data_o$next[3:0]$11355 $6\src24__data_o$next[3:0]$11361 + attribute \src "libresoc.v:181949.5-181949.29" switch \initial - attribute \src "libresoc.v:182201.9-182201.17" + attribute \src "libresoc.v:181949.9-181949.17" case 1'1 case end @@ -339674,66 +339380,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src24__data_o$next[3:0]$11362 $5\src24__data_o$next[3:0]$11366 + assign $1\src24__data_o$next[3:0]$11356 $5\src24__data_o$next[3:0]$11360 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src24__data_o$next[3:0]$11363 \dest14__data_i + assign $2\src24__data_o$next[3:0]$11357 \dest14__data_i case - assign $2\src24__data_o$next[3:0]$11363 4'0000 + assign $2\src24__data_o$next[3:0]$11357 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src24__data_o$next[3:0]$11364 \dest24__data_i + assign $3\src24__data_o$next[3:0]$11358 \dest24__data_i case - assign $3\src24__data_o$next[3:0]$11364 $2\src24__data_o$next[3:0]$11363 + assign $3\src24__data_o$next[3:0]$11358 $2\src24__data_o$next[3:0]$11357 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src24__data_o$next[3:0]$11365 \w4__data_i + assign $4\src24__data_o$next[3:0]$11359 \w4__data_i case - assign $4\src24__data_o$next[3:0]$11365 $3\src24__data_o$next[3:0]$11364 + assign $4\src24__data_o$next[3:0]$11359 $3\src24__data_o$next[3:0]$11358 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src24__data_o$next[3:0]$11366 \reg + assign $5\src24__data_o$next[3:0]$11360 \reg case - assign $5\src24__data_o$next[3:0]$11366 $4\src24__data_o$next[3:0]$11365 + assign $5\src24__data_o$next[3:0]$11360 $4\src24__data_o$next[3:0]$11359 end case - assign $1\src24__data_o$next[3:0]$11362 4'0000 + assign $1\src24__data_o$next[3:0]$11356 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src24__data_o$next[3:0]$11367 4'0000 + assign $6\src24__data_o$next[3:0]$11361 4'0000 case - assign $6\src24__data_o$next[3:0]$11367 $1\src24__data_o$next[3:0]$11362 + assign $6\src24__data_o$next[3:0]$11361 $1\src24__data_o$next[3:0]$11356 end sync always - update \src24__data_o$next $0\src24__data_o$next[3:0]$11361 + update \src24__data_o$next $0\src24__data_o$next[3:0]$11355 end - attribute \src "libresoc.v:182240.3-182269.6" - process $proc$libresoc.v:182240$11368 + attribute \src "libresoc.v:181988.3-182017.6" + process $proc$libresoc.v:181988$11362 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11369 $1\wr_detect$4[0:0]$11370 - attribute \src "libresoc.v:182241.5-182241.29" + assign $0\wr_detect$4[0:0]$11363 $1\wr_detect$4[0:0]$11364 + attribute \src "libresoc.v:181989.5-181989.29" switch \initial - attribute \src "libresoc.v:182241.9-182241.17" + attribute \src "libresoc.v:181989.9-181989.17" case 1'1 case end @@ -339745,49 +339451,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11370 $4\wr_detect$4[0:0]$11373 + assign $1\wr_detect$4[0:0]$11364 $4\wr_detect$4[0:0]$11367 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11371 1'1 + assign $2\wr_detect$4[0:0]$11365 1'1 case - assign $2\wr_detect$4[0:0]$11371 1'0 + assign $2\wr_detect$4[0:0]$11365 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11372 1'1 + assign $3\wr_detect$4[0:0]$11366 1'1 case - assign $3\wr_detect$4[0:0]$11372 $2\wr_detect$4[0:0]$11371 + assign $3\wr_detect$4[0:0]$11366 $2\wr_detect$4[0:0]$11365 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11373 1'1 + assign $4\wr_detect$4[0:0]$11367 1'1 case - assign $4\wr_detect$4[0:0]$11373 $3\wr_detect$4[0:0]$11372 + assign $4\wr_detect$4[0:0]$11367 $3\wr_detect$4[0:0]$11366 end case - assign $1\wr_detect$4[0:0]$11370 1'0 + assign $1\wr_detect$4[0:0]$11364 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11369 + update \wr_detect$4 $0\wr_detect$4[0:0]$11363 end - attribute \src "libresoc.v:182270.3-182309.6" - process $proc$libresoc.v:182270$11374 + attribute \src "libresoc.v:182018.3-182057.6" + process $proc$libresoc.v:182018$11368 assign { } { } assign { } { } assign { } { } - assign $0\src34__data_o$next[3:0]$11375 $6\src34__data_o$next[3:0]$11381 - attribute \src "libresoc.v:182271.5-182271.29" + assign $0\src34__data_o$next[3:0]$11369 $6\src34__data_o$next[3:0]$11375 + attribute \src "libresoc.v:182019.5-182019.29" switch \initial - attribute \src "libresoc.v:182271.9-182271.17" + attribute \src "libresoc.v:182019.9-182019.17" case 1'1 case end @@ -339799,66 +339505,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src34__data_o$next[3:0]$11376 $5\src34__data_o$next[3:0]$11380 + assign $1\src34__data_o$next[3:0]$11370 $5\src34__data_o$next[3:0]$11374 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src34__data_o$next[3:0]$11377 \dest14__data_i + assign $2\src34__data_o$next[3:0]$11371 \dest14__data_i case - assign $2\src34__data_o$next[3:0]$11377 4'0000 + assign $2\src34__data_o$next[3:0]$11371 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src34__data_o$next[3:0]$11378 \dest24__data_i + assign $3\src34__data_o$next[3:0]$11372 \dest24__data_i case - assign $3\src34__data_o$next[3:0]$11378 $2\src34__data_o$next[3:0]$11377 + assign $3\src34__data_o$next[3:0]$11372 $2\src34__data_o$next[3:0]$11371 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src34__data_o$next[3:0]$11379 \w4__data_i + assign $4\src34__data_o$next[3:0]$11373 \w4__data_i case - assign $4\src34__data_o$next[3:0]$11379 $3\src34__data_o$next[3:0]$11378 + assign $4\src34__data_o$next[3:0]$11373 $3\src34__data_o$next[3:0]$11372 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src34__data_o$next[3:0]$11380 \reg + assign $5\src34__data_o$next[3:0]$11374 \reg case - assign $5\src34__data_o$next[3:0]$11380 $4\src34__data_o$next[3:0]$11379 + assign $5\src34__data_o$next[3:0]$11374 $4\src34__data_o$next[3:0]$11373 end case - assign $1\src34__data_o$next[3:0]$11376 4'0000 + assign $1\src34__data_o$next[3:0]$11370 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src34__data_o$next[3:0]$11381 4'0000 + assign $6\src34__data_o$next[3:0]$11375 4'0000 case - assign $6\src34__data_o$next[3:0]$11381 $1\src34__data_o$next[3:0]$11376 + assign $6\src34__data_o$next[3:0]$11375 $1\src34__data_o$next[3:0]$11370 end sync always - update \src34__data_o$next $0\src34__data_o$next[3:0]$11375 + update \src34__data_o$next $0\src34__data_o$next[3:0]$11369 end - attribute \src "libresoc.v:182310.3-182339.6" - process $proc$libresoc.v:182310$11382 + attribute \src "libresoc.v:182058.3-182087.6" + process $proc$libresoc.v:182058$11376 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11383 $1\wr_detect$7[0:0]$11384 - attribute \src "libresoc.v:182311.5-182311.29" + assign $0\wr_detect$7[0:0]$11377 $1\wr_detect$7[0:0]$11378 + attribute \src "libresoc.v:182059.5-182059.29" switch \initial - attribute \src "libresoc.v:182311.9-182311.17" + attribute \src "libresoc.v:182059.9-182059.17" case 1'1 case end @@ -339870,49 +339576,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11384 $4\wr_detect$7[0:0]$11387 + assign $1\wr_detect$7[0:0]$11378 $4\wr_detect$7[0:0]$11381 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11385 1'1 + assign $2\wr_detect$7[0:0]$11379 1'1 case - assign $2\wr_detect$7[0:0]$11385 1'0 + assign $2\wr_detect$7[0:0]$11379 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11386 1'1 + assign $3\wr_detect$7[0:0]$11380 1'1 case - assign $3\wr_detect$7[0:0]$11386 $2\wr_detect$7[0:0]$11385 + assign $3\wr_detect$7[0:0]$11380 $2\wr_detect$7[0:0]$11379 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11387 1'1 + assign $4\wr_detect$7[0:0]$11381 1'1 case - assign $4\wr_detect$7[0:0]$11387 $3\wr_detect$7[0:0]$11386 + assign $4\wr_detect$7[0:0]$11381 $3\wr_detect$7[0:0]$11380 end case - assign $1\wr_detect$7[0:0]$11384 1'0 + assign $1\wr_detect$7[0:0]$11378 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11383 + update \wr_detect$7 $0\wr_detect$7[0:0]$11377 end - attribute \src "libresoc.v:182340.3-182379.6" - process $proc$libresoc.v:182340$11388 + attribute \src "libresoc.v:182088.3-182127.6" + process $proc$libresoc.v:182088$11382 assign { } { } assign { } { } assign { } { } - assign $0\r4__data_o$next[3:0]$11389 $6\r4__data_o$next[3:0]$11395 - attribute \src "libresoc.v:182341.5-182341.29" + assign $0\r4__data_o$next[3:0]$11383 $6\r4__data_o$next[3:0]$11389 + attribute \src "libresoc.v:182089.5-182089.29" switch \initial - attribute \src "libresoc.v:182341.9-182341.17" + attribute \src "libresoc.v:182089.9-182089.17" case 1'1 case end @@ -339924,66 +339630,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r4__data_o$next[3:0]$11390 $5\r4__data_o$next[3:0]$11394 + assign $1\r4__data_o$next[3:0]$11384 $5\r4__data_o$next[3:0]$11388 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r4__data_o$next[3:0]$11391 \dest14__data_i + assign $2\r4__data_o$next[3:0]$11385 \dest14__data_i case - assign $2\r4__data_o$next[3:0]$11391 4'0000 + assign $2\r4__data_o$next[3:0]$11385 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r4__data_o$next[3:0]$11392 \dest24__data_i + assign $3\r4__data_o$next[3:0]$11386 \dest24__data_i case - assign $3\r4__data_o$next[3:0]$11392 $2\r4__data_o$next[3:0]$11391 + assign $3\r4__data_o$next[3:0]$11386 $2\r4__data_o$next[3:0]$11385 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r4__data_o$next[3:0]$11393 \w4__data_i + assign $4\r4__data_o$next[3:0]$11387 \w4__data_i case - assign $4\r4__data_o$next[3:0]$11393 $3\r4__data_o$next[3:0]$11392 + assign $4\r4__data_o$next[3:0]$11387 $3\r4__data_o$next[3:0]$11386 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r4__data_o$next[3:0]$11394 \reg + assign $5\r4__data_o$next[3:0]$11388 \reg case - assign $5\r4__data_o$next[3:0]$11394 $4\r4__data_o$next[3:0]$11393 + assign $5\r4__data_o$next[3:0]$11388 $4\r4__data_o$next[3:0]$11387 end case - assign $1\r4__data_o$next[3:0]$11390 4'0000 + assign $1\r4__data_o$next[3:0]$11384 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r4__data_o$next[3:0]$11395 4'0000 + assign $6\r4__data_o$next[3:0]$11389 4'0000 case - assign $6\r4__data_o$next[3:0]$11395 $1\r4__data_o$next[3:0]$11390 + assign $6\r4__data_o$next[3:0]$11389 $1\r4__data_o$next[3:0]$11384 end sync always - update \r4__data_o$next $0\r4__data_o$next[3:0]$11389 + update \r4__data_o$next $0\r4__data_o$next[3:0]$11383 end - attribute \src "libresoc.v:182380.3-182409.6" - process $proc$libresoc.v:182380$11396 + attribute \src "libresoc.v:182128.3-182157.6" + process $proc$libresoc.v:182128$11390 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11397 $1\wr_detect$10[0:0]$11398 - attribute \src "libresoc.v:182381.5-182381.29" + assign $0\wr_detect$10[0:0]$11391 $1\wr_detect$10[0:0]$11392 + attribute \src "libresoc.v:182129.5-182129.29" switch \initial - attribute \src "libresoc.v:182381.9-182381.17" + attribute \src "libresoc.v:182129.9-182129.17" case 1'1 case end @@ -339995,49 +339701,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11398 $4\wr_detect$10[0:0]$11401 + assign $1\wr_detect$10[0:0]$11392 $4\wr_detect$10[0:0]$11395 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11399 1'1 + assign $2\wr_detect$10[0:0]$11393 1'1 case - assign $2\wr_detect$10[0:0]$11399 1'0 + assign $2\wr_detect$10[0:0]$11393 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11400 1'1 + assign $3\wr_detect$10[0:0]$11394 1'1 case - assign $3\wr_detect$10[0:0]$11400 $2\wr_detect$10[0:0]$11399 + assign $3\wr_detect$10[0:0]$11394 $2\wr_detect$10[0:0]$11393 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11401 1'1 + assign $4\wr_detect$10[0:0]$11395 1'1 case - assign $4\wr_detect$10[0:0]$11401 $3\wr_detect$10[0:0]$11400 + assign $4\wr_detect$10[0:0]$11395 $3\wr_detect$10[0:0]$11394 end case - assign $1\wr_detect$10[0:0]$11398 1'0 + assign $1\wr_detect$10[0:0]$11392 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11397 + update \wr_detect$10 $0\wr_detect$10[0:0]$11391 end - attribute \src "libresoc.v:182410.3-182449.6" - process $proc$libresoc.v:182410$11402 + attribute \src "libresoc.v:182158.3-182197.6" + process $proc$libresoc.v:182158$11396 assign { } { } assign { } { } assign { } { } - assign $0\r24__data_o$next[3:0]$11403 $6\r24__data_o$next[3:0]$11409 - attribute \src "libresoc.v:182411.5-182411.29" + assign $0\r24__data_o$next[3:0]$11397 $6\r24__data_o$next[3:0]$11403 + attribute \src "libresoc.v:182159.5-182159.29" switch \initial - attribute \src "libresoc.v:182411.9-182411.17" + attribute \src "libresoc.v:182159.9-182159.17" case 1'1 case end @@ -340049,66 +339755,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r24__data_o$next[3:0]$11404 $5\r24__data_o$next[3:0]$11408 + assign $1\r24__data_o$next[3:0]$11398 $5\r24__data_o$next[3:0]$11402 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r24__data_o$next[3:0]$11405 \dest14__data_i + assign $2\r24__data_o$next[3:0]$11399 \dest14__data_i case - assign $2\r24__data_o$next[3:0]$11405 4'0000 + assign $2\r24__data_o$next[3:0]$11399 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r24__data_o$next[3:0]$11406 \dest24__data_i + assign $3\r24__data_o$next[3:0]$11400 \dest24__data_i case - assign $3\r24__data_o$next[3:0]$11406 $2\r24__data_o$next[3:0]$11405 + assign $3\r24__data_o$next[3:0]$11400 $2\r24__data_o$next[3:0]$11399 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r24__data_o$next[3:0]$11407 \w4__data_i + assign $4\r24__data_o$next[3:0]$11401 \w4__data_i case - assign $4\r24__data_o$next[3:0]$11407 $3\r24__data_o$next[3:0]$11406 + assign $4\r24__data_o$next[3:0]$11401 $3\r24__data_o$next[3:0]$11400 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r24__data_o$next[3:0]$11408 \reg + assign $5\r24__data_o$next[3:0]$11402 \reg case - assign $5\r24__data_o$next[3:0]$11408 $4\r24__data_o$next[3:0]$11407 + assign $5\r24__data_o$next[3:0]$11402 $4\r24__data_o$next[3:0]$11401 end case - assign $1\r24__data_o$next[3:0]$11404 4'0000 + assign $1\r24__data_o$next[3:0]$11398 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r24__data_o$next[3:0]$11409 4'0000 + assign $6\r24__data_o$next[3:0]$11403 4'0000 case - assign $6\r24__data_o$next[3:0]$11409 $1\r24__data_o$next[3:0]$11404 + assign $6\r24__data_o$next[3:0]$11403 $1\r24__data_o$next[3:0]$11398 end sync always - update \r24__data_o$next $0\r24__data_o$next[3:0]$11403 + update \r24__data_o$next $0\r24__data_o$next[3:0]$11397 end - attribute \src "libresoc.v:182450.3-182479.6" - process $proc$libresoc.v:182450$11410 + attribute \src "libresoc.v:182198.3-182227.6" + process $proc$libresoc.v:182198$11404 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11411 $1\wr_detect$13[0:0]$11412 - attribute \src "libresoc.v:182451.5-182451.29" + assign $0\wr_detect$13[0:0]$11405 $1\wr_detect$13[0:0]$11406 + attribute \src "libresoc.v:182199.5-182199.29" switch \initial - attribute \src "libresoc.v:182451.9-182451.17" + attribute \src "libresoc.v:182199.9-182199.17" case 1'1 case end @@ -340120,217 +339826,217 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11412 $4\wr_detect$13[0:0]$11415 + assign $1\wr_detect$13[0:0]$11406 $4\wr_detect$13[0:0]$11409 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11413 1'1 + assign $2\wr_detect$13[0:0]$11407 1'1 case - assign $2\wr_detect$13[0:0]$11413 1'0 + assign $2\wr_detect$13[0:0]$11407 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11414 1'1 + assign $3\wr_detect$13[0:0]$11408 1'1 case - assign $3\wr_detect$13[0:0]$11414 $2\wr_detect$13[0:0]$11413 + assign $3\wr_detect$13[0:0]$11408 $2\wr_detect$13[0:0]$11407 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11415 1'1 + assign $4\wr_detect$13[0:0]$11409 1'1 case - assign $4\wr_detect$13[0:0]$11415 $3\wr_detect$13[0:0]$11414 + assign $4\wr_detect$13[0:0]$11409 $3\wr_detect$13[0:0]$11408 end case - assign $1\wr_detect$13[0:0]$11412 1'0 + assign $1\wr_detect$13[0:0]$11406 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11411 + update \wr_detect$13 $0\wr_detect$13[0:0]$11405 end - connect \$9 $not$libresoc.v:182086$11334_Y - connect \$12 $not$libresoc.v:182087$11335_Y - connect \$1 $not$libresoc.v:182088$11336_Y - connect \$3 $not$libresoc.v:182089$11337_Y - connect \$6 $not$libresoc.v:182090$11338_Y + connect \$9 $not$libresoc.v:181834$11328_Y + connect \$12 $not$libresoc.v:181835$11329_Y + connect \$1 $not$libresoc.v:181836$11330_Y + connect \$3 $not$libresoc.v:181837$11331_Y + connect \$6 $not$libresoc.v:181838$11332_Y end -attribute \src "libresoc.v:182484.1-182955.10" +attribute \src "libresoc.v:182232.1-182703.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" attribute \generator "nMigen" module \reg_5 - attribute \src "libresoc.v:182485.7-182485.20" + attribute \src "libresoc.v:182233.7-182233.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $0\r25__data_o$next[3:0]$11492 - attribute \src "libresoc.v:182568.3-182569.39" + attribute \src "libresoc.v:182633.3-182672.6" + wire width 4 $0\r25__data_o$next[3:0]$11486 + attribute \src "libresoc.v:182316.3-182317.39" wire width 4 $0\r25__data_o[3:0] - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $0\r5__data_o$next[3:0]$11478 - attribute \src "libresoc.v:182570.3-182571.37" + attribute \src "libresoc.v:182563.3-182602.6" + wire width 4 $0\r5__data_o$next[3:0]$11472 + attribute \src "libresoc.v:182318.3-182319.37" wire width 4 $0\r5__data_o[3:0] - attribute \src "libresoc.v:182648.3-182674.6" - wire width 4 $0\reg$next[3:0]$11444 - attribute \src "libresoc.v:182566.3-182567.25" + attribute \src "libresoc.v:182396.3-182422.6" + wire width 4 $0\reg$next[3:0]$11438 + attribute \src "libresoc.v:182314.3-182315.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:182578.3-182617.6" - wire width 4 $0\src15__data_o$next[3:0]$11435 - attribute \src "libresoc.v:182576.3-182577.43" + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $0\src15__data_o$next[3:0]$11429 + attribute \src "libresoc.v:182324.3-182325.43" wire width 4 $0\src15__data_o[3:0] - attribute \src "libresoc.v:182675.3-182714.6" - wire width 4 $0\src25__data_o$next[3:0]$11450 - attribute \src "libresoc.v:182574.3-182575.43" + attribute \src "libresoc.v:182423.3-182462.6" + wire width 4 $0\src25__data_o$next[3:0]$11444 + attribute \src "libresoc.v:182322.3-182323.43" wire width 4 $0\src25__data_o[3:0] - attribute \src "libresoc.v:182745.3-182784.6" - wire width 4 $0\src35__data_o$next[3:0]$11464 - attribute \src "libresoc.v:182572.3-182573.43" + attribute \src "libresoc.v:182493.3-182532.6" + wire width 4 $0\src35__data_o$next[3:0]$11458 + attribute \src "libresoc.v:182320.3-182321.43" wire width 4 $0\src35__data_o[3:0] - attribute \src "libresoc.v:182855.3-182884.6" - wire $0\wr_detect$10[0:0]$11486 - attribute \src "libresoc.v:182925.3-182954.6" - wire $0\wr_detect$13[0:0]$11500 - attribute \src "libresoc.v:182715.3-182744.6" - wire $0\wr_detect$4[0:0]$11458 - attribute \src "libresoc.v:182785.3-182814.6" - wire $0\wr_detect$7[0:0]$11472 - attribute \src "libresoc.v:182618.3-182647.6" + attribute \src "libresoc.v:182603.3-182632.6" + wire $0\wr_detect$10[0:0]$11480 + attribute \src "libresoc.v:182673.3-182702.6" + wire $0\wr_detect$13[0:0]$11494 + attribute \src "libresoc.v:182463.3-182492.6" + wire $0\wr_detect$4[0:0]$11452 + attribute \src "libresoc.v:182533.3-182562.6" + wire $0\wr_detect$7[0:0]$11466 + attribute \src "libresoc.v:182366.3-182395.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $1\r25__data_o$next[3:0]$11493 - attribute \src "libresoc.v:182510.13-182510.31" + attribute \src "libresoc.v:182633.3-182672.6" + wire width 4 $1\r25__data_o$next[3:0]$11487 + attribute \src "libresoc.v:182258.13-182258.31" wire width 4 $1\r25__data_o[3:0] - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $1\r5__data_o$next[3:0]$11479 - attribute \src "libresoc.v:182517.13-182517.30" + attribute \src "libresoc.v:182563.3-182602.6" + wire width 4 $1\r5__data_o$next[3:0]$11473 + attribute \src "libresoc.v:182265.13-182265.30" wire width 4 $1\r5__data_o[3:0] - attribute \src "libresoc.v:182648.3-182674.6" - wire width 4 $1\reg$next[3:0]$11445 - attribute \src "libresoc.v:182523.13-182523.25" + attribute \src "libresoc.v:182396.3-182422.6" + wire width 4 $1\reg$next[3:0]$11439 + attribute \src "libresoc.v:182271.13-182271.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:182578.3-182617.6" - wire width 4 $1\src15__data_o$next[3:0]$11436 - attribute \src "libresoc.v:182528.13-182528.33" + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $1\src15__data_o$next[3:0]$11430 + attribute \src "libresoc.v:182276.13-182276.33" wire width 4 $1\src15__data_o[3:0] - attribute \src "libresoc.v:182675.3-182714.6" - wire width 4 $1\src25__data_o$next[3:0]$11451 - attribute \src "libresoc.v:182535.13-182535.33" + attribute \src "libresoc.v:182423.3-182462.6" + wire width 4 $1\src25__data_o$next[3:0]$11445 + attribute \src "libresoc.v:182283.13-182283.33" wire width 4 $1\src25__data_o[3:0] - attribute \src "libresoc.v:182745.3-182784.6" - wire width 4 $1\src35__data_o$next[3:0]$11465 - attribute \src "libresoc.v:182542.13-182542.33" + attribute \src "libresoc.v:182493.3-182532.6" + wire width 4 $1\src35__data_o$next[3:0]$11459 + attribute \src "libresoc.v:182290.13-182290.33" wire width 4 $1\src35__data_o[3:0] - attribute \src "libresoc.v:182855.3-182884.6" - wire $1\wr_detect$10[0:0]$11487 - attribute \src "libresoc.v:182925.3-182954.6" - wire $1\wr_detect$13[0:0]$11501 - attribute \src "libresoc.v:182715.3-182744.6" - wire $1\wr_detect$4[0:0]$11459 - attribute \src "libresoc.v:182785.3-182814.6" - wire $1\wr_detect$7[0:0]$11473 - attribute \src "libresoc.v:182618.3-182647.6" + attribute \src "libresoc.v:182603.3-182632.6" + wire $1\wr_detect$10[0:0]$11481 + attribute \src "libresoc.v:182673.3-182702.6" + wire $1\wr_detect$13[0:0]$11495 + attribute \src "libresoc.v:182463.3-182492.6" + wire $1\wr_detect$4[0:0]$11453 + attribute \src "libresoc.v:182533.3-182562.6" + wire $1\wr_detect$7[0:0]$11467 + attribute \src "libresoc.v:182366.3-182395.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $2\r25__data_o$next[3:0]$11494 - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $2\r5__data_o$next[3:0]$11480 - attribute \src "libresoc.v:182648.3-182674.6" - wire width 4 $2\reg$next[3:0]$11446 - attribute \src "libresoc.v:182578.3-182617.6" - wire width 4 $2\src15__data_o$next[3:0]$11437 - attribute \src "libresoc.v:182675.3-182714.6" - wire width 4 $2\src25__data_o$next[3:0]$11452 - attribute \src "libresoc.v:182745.3-182784.6" - wire width 4 $2\src35__data_o$next[3:0]$11466 - attribute \src "libresoc.v:182855.3-182884.6" - wire $2\wr_detect$10[0:0]$11488 - attribute \src "libresoc.v:182925.3-182954.6" - wire $2\wr_detect$13[0:0]$11502 - attribute \src "libresoc.v:182715.3-182744.6" - wire $2\wr_detect$4[0:0]$11460 - attribute \src "libresoc.v:182785.3-182814.6" - wire $2\wr_detect$7[0:0]$11474 - attribute \src "libresoc.v:182618.3-182647.6" + attribute \src "libresoc.v:182633.3-182672.6" + wire width 4 $2\r25__data_o$next[3:0]$11488 + attribute \src "libresoc.v:182563.3-182602.6" + wire width 4 $2\r5__data_o$next[3:0]$11474 + attribute \src "libresoc.v:182396.3-182422.6" + wire width 4 $2\reg$next[3:0]$11440 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $2\src15__data_o$next[3:0]$11431 + attribute \src "libresoc.v:182423.3-182462.6" + wire width 4 $2\src25__data_o$next[3:0]$11446 + attribute \src "libresoc.v:182493.3-182532.6" + wire width 4 $2\src35__data_o$next[3:0]$11460 + attribute \src "libresoc.v:182603.3-182632.6" + wire $2\wr_detect$10[0:0]$11482 + attribute \src "libresoc.v:182673.3-182702.6" + wire $2\wr_detect$13[0:0]$11496 + attribute \src "libresoc.v:182463.3-182492.6" + wire $2\wr_detect$4[0:0]$11454 + attribute \src "libresoc.v:182533.3-182562.6" + wire $2\wr_detect$7[0:0]$11468 + attribute \src "libresoc.v:182366.3-182395.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $3\r25__data_o$next[3:0]$11495 - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $3\r5__data_o$next[3:0]$11481 - attribute \src "libresoc.v:182648.3-182674.6" - wire width 4 $3\reg$next[3:0]$11447 - attribute \src "libresoc.v:182578.3-182617.6" - wire width 4 $3\src15__data_o$next[3:0]$11438 - attribute \src "libresoc.v:182675.3-182714.6" - wire width 4 $3\src25__data_o$next[3:0]$11453 - attribute \src "libresoc.v:182745.3-182784.6" - wire width 4 $3\src35__data_o$next[3:0]$11467 - attribute \src "libresoc.v:182855.3-182884.6" - wire $3\wr_detect$10[0:0]$11489 - attribute \src "libresoc.v:182925.3-182954.6" - wire $3\wr_detect$13[0:0]$11503 - attribute \src "libresoc.v:182715.3-182744.6" - wire $3\wr_detect$4[0:0]$11461 - attribute \src "libresoc.v:182785.3-182814.6" - wire $3\wr_detect$7[0:0]$11475 - attribute \src "libresoc.v:182618.3-182647.6" + attribute \src "libresoc.v:182633.3-182672.6" + wire width 4 $3\r25__data_o$next[3:0]$11489 + attribute \src "libresoc.v:182563.3-182602.6" + wire width 4 $3\r5__data_o$next[3:0]$11475 + attribute \src "libresoc.v:182396.3-182422.6" + wire width 4 $3\reg$next[3:0]$11441 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $3\src15__data_o$next[3:0]$11432 + attribute \src "libresoc.v:182423.3-182462.6" + wire width 4 $3\src25__data_o$next[3:0]$11447 + attribute \src "libresoc.v:182493.3-182532.6" + wire width 4 $3\src35__data_o$next[3:0]$11461 + attribute \src "libresoc.v:182603.3-182632.6" + wire $3\wr_detect$10[0:0]$11483 + attribute \src "libresoc.v:182673.3-182702.6" + wire $3\wr_detect$13[0:0]$11497 + attribute \src "libresoc.v:182463.3-182492.6" + wire $3\wr_detect$4[0:0]$11455 + attribute \src "libresoc.v:182533.3-182562.6" + wire $3\wr_detect$7[0:0]$11469 + attribute \src "libresoc.v:182366.3-182395.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $4\r25__data_o$next[3:0]$11496 - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $4\r5__data_o$next[3:0]$11482 - attribute \src "libresoc.v:182648.3-182674.6" - wire width 4 $4\reg$next[3:0]$11448 - attribute \src "libresoc.v:182578.3-182617.6" - wire width 4 $4\src15__data_o$next[3:0]$11439 - attribute \src "libresoc.v:182675.3-182714.6" - wire width 4 $4\src25__data_o$next[3:0]$11454 - attribute \src "libresoc.v:182745.3-182784.6" - wire width 4 $4\src35__data_o$next[3:0]$11468 - attribute \src "libresoc.v:182855.3-182884.6" - wire $4\wr_detect$10[0:0]$11490 - attribute \src "libresoc.v:182925.3-182954.6" - wire $4\wr_detect$13[0:0]$11504 - attribute \src "libresoc.v:182715.3-182744.6" - wire $4\wr_detect$4[0:0]$11462 - attribute \src "libresoc.v:182785.3-182814.6" - wire $4\wr_detect$7[0:0]$11476 - attribute \src "libresoc.v:182618.3-182647.6" + attribute \src "libresoc.v:182633.3-182672.6" + wire width 4 $4\r25__data_o$next[3:0]$11490 + attribute \src "libresoc.v:182563.3-182602.6" + wire width 4 $4\r5__data_o$next[3:0]$11476 + attribute \src "libresoc.v:182396.3-182422.6" + wire width 4 $4\reg$next[3:0]$11442 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $4\src15__data_o$next[3:0]$11433 + attribute \src "libresoc.v:182423.3-182462.6" + wire width 4 $4\src25__data_o$next[3:0]$11448 + attribute \src "libresoc.v:182493.3-182532.6" + wire width 4 $4\src35__data_o$next[3:0]$11462 + attribute \src "libresoc.v:182603.3-182632.6" + wire $4\wr_detect$10[0:0]$11484 + attribute \src "libresoc.v:182673.3-182702.6" + wire $4\wr_detect$13[0:0]$11498 + attribute \src "libresoc.v:182463.3-182492.6" + wire $4\wr_detect$4[0:0]$11456 + attribute \src "libresoc.v:182533.3-182562.6" + wire $4\wr_detect$7[0:0]$11470 + attribute \src "libresoc.v:182366.3-182395.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $5\r25__data_o$next[3:0]$11497 - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $5\r5__data_o$next[3:0]$11483 - attribute \src "libresoc.v:182578.3-182617.6" - wire width 4 $5\src15__data_o$next[3:0]$11440 - attribute \src "libresoc.v:182675.3-182714.6" - wire width 4 $5\src25__data_o$next[3:0]$11455 - attribute \src "libresoc.v:182745.3-182784.6" - wire width 4 $5\src35__data_o$next[3:0]$11469 - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $6\r25__data_o$next[3:0]$11498 - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $6\r5__data_o$next[3:0]$11484 - attribute \src "libresoc.v:182578.3-182617.6" - wire width 4 $6\src15__data_o$next[3:0]$11441 - attribute \src "libresoc.v:182675.3-182714.6" - wire width 4 $6\src25__data_o$next[3:0]$11456 - attribute \src "libresoc.v:182745.3-182784.6" - wire width 4 $6\src35__data_o$next[3:0]$11470 - attribute \src "libresoc.v:182561.17-182561.104" - wire $not$libresoc.v:182561$11423_Y - attribute \src "libresoc.v:182562.18-182562.105" - wire $not$libresoc.v:182562$11424_Y - attribute \src "libresoc.v:182563.17-182563.100" - wire $not$libresoc.v:182563$11425_Y - attribute \src "libresoc.v:182564.17-182564.103" - wire $not$libresoc.v:182564$11426_Y - attribute \src "libresoc.v:182565.17-182565.103" - wire $not$libresoc.v:182565$11427_Y + attribute \src "libresoc.v:182633.3-182672.6" + wire width 4 $5\r25__data_o$next[3:0]$11491 + attribute \src "libresoc.v:182563.3-182602.6" + wire width 4 $5\r5__data_o$next[3:0]$11477 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $5\src15__data_o$next[3:0]$11434 + attribute \src "libresoc.v:182423.3-182462.6" + wire width 4 $5\src25__data_o$next[3:0]$11449 + attribute \src "libresoc.v:182493.3-182532.6" + wire width 4 $5\src35__data_o$next[3:0]$11463 + attribute \src "libresoc.v:182633.3-182672.6" + wire width 4 $6\r25__data_o$next[3:0]$11492 + attribute \src "libresoc.v:182563.3-182602.6" + wire width 4 $6\r5__data_o$next[3:0]$11478 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $6\src15__data_o$next[3:0]$11435 + attribute \src "libresoc.v:182423.3-182462.6" + wire width 4 $6\src25__data_o$next[3:0]$11450 + attribute \src "libresoc.v:182493.3-182532.6" + wire width 4 $6\src35__data_o$next[3:0]$11464 + attribute \src "libresoc.v:182309.17-182309.104" + wire $not$libresoc.v:182309$11417_Y + attribute \src "libresoc.v:182310.18-182310.105" + wire $not$libresoc.v:182310$11418_Y + attribute \src "libresoc.v:182311.17-182311.100" + wire $not$libresoc.v:182311$11419_Y + attribute \src "libresoc.v:182312.17-182312.103" + wire $not$libresoc.v:182312$11420_Y + attribute \src "libresoc.v:182313.17-182313.103" + wire $not$libresoc.v:182313$11421_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -340341,9 +340047,9 @@ module \reg_5 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest15__data_i @@ -340353,7 +340059,7 @@ module \reg_5 wire width 4 input 11 \dest25__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest25__wen - attribute \src "libresoc.v:182485.7-182485.15" + attribute \src "libresoc.v:182233.7-182233.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r25__data_o @@ -340404,152 +340110,152 @@ module \reg_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182561$11423 + cell $not $not$libresoc.v:182309$11417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:182561$11423_Y + connect \Y $not$libresoc.v:182309$11417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182562$11424 + cell $not $not$libresoc.v:182310$11418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:182562$11424_Y + connect \Y $not$libresoc.v:182310$11418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182563$11425 + cell $not $not$libresoc.v:182311$11419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:182563$11425_Y + connect \Y $not$libresoc.v:182311$11419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182564$11426 + cell $not $not$libresoc.v:182312$11420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:182564$11426_Y + connect \Y $not$libresoc.v:182312$11420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182565$11427 + cell $not $not$libresoc.v:182313$11421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:182565$11427_Y + connect \Y $not$libresoc.v:182313$11421_Y end - attribute \src "libresoc.v:182485.7-182485.20" - process $proc$libresoc.v:182485$11505 + attribute \src "libresoc.v:182233.7-182233.20" + process $proc$libresoc.v:182233$11499 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182510.13-182510.31" - process $proc$libresoc.v:182510$11506 + attribute \src "libresoc.v:182258.13-182258.31" + process $proc$libresoc.v:182258$11500 assign { } { } assign $1\r25__data_o[3:0] 4'0000 sync always sync init update \r25__data_o $1\r25__data_o[3:0] end - attribute \src "libresoc.v:182517.13-182517.30" - process $proc$libresoc.v:182517$11507 + attribute \src "libresoc.v:182265.13-182265.30" + process $proc$libresoc.v:182265$11501 assign { } { } assign $1\r5__data_o[3:0] 4'0000 sync always sync init update \r5__data_o $1\r5__data_o[3:0] end - attribute \src "libresoc.v:182523.13-182523.25" - process $proc$libresoc.v:182523$11508 + attribute \src "libresoc.v:182271.13-182271.25" + process $proc$libresoc.v:182271$11502 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:182528.13-182528.33" - process $proc$libresoc.v:182528$11509 + attribute \src "libresoc.v:182276.13-182276.33" + process $proc$libresoc.v:182276$11503 assign { } { } assign $1\src15__data_o[3:0] 4'0000 sync always sync init update \src15__data_o $1\src15__data_o[3:0] end - attribute \src "libresoc.v:182535.13-182535.33" - process $proc$libresoc.v:182535$11510 + attribute \src "libresoc.v:182283.13-182283.33" + process $proc$libresoc.v:182283$11504 assign { } { } assign $1\src25__data_o[3:0] 4'0000 sync always sync init update \src25__data_o $1\src25__data_o[3:0] end - attribute \src "libresoc.v:182542.13-182542.33" - process $proc$libresoc.v:182542$11511 + attribute \src "libresoc.v:182290.13-182290.33" + process $proc$libresoc.v:182290$11505 assign { } { } assign $1\src35__data_o[3:0] 4'0000 sync always sync init update \src35__data_o $1\src35__data_o[3:0] end - attribute \src "libresoc.v:182566.3-182567.25" - process $proc$libresoc.v:182566$11428 + attribute \src "libresoc.v:182314.3-182315.25" + process $proc$libresoc.v:182314$11422 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:182568.3-182569.39" - process $proc$libresoc.v:182568$11429 + attribute \src "libresoc.v:182316.3-182317.39" + process $proc$libresoc.v:182316$11423 assign { } { } assign $0\r25__data_o[3:0] \r25__data_o$next sync posedge \coresync_clk update \r25__data_o $0\r25__data_o[3:0] end - attribute \src "libresoc.v:182570.3-182571.37" - process $proc$libresoc.v:182570$11430 + attribute \src "libresoc.v:182318.3-182319.37" + process $proc$libresoc.v:182318$11424 assign { } { } assign $0\r5__data_o[3:0] \r5__data_o$next sync posedge \coresync_clk update \r5__data_o $0\r5__data_o[3:0] end - attribute \src "libresoc.v:182572.3-182573.43" - process $proc$libresoc.v:182572$11431 + attribute \src "libresoc.v:182320.3-182321.43" + process $proc$libresoc.v:182320$11425 assign { } { } assign $0\src35__data_o[3:0] \src35__data_o$next sync posedge \coresync_clk update \src35__data_o $0\src35__data_o[3:0] end - attribute \src "libresoc.v:182574.3-182575.43" - process $proc$libresoc.v:182574$11432 + attribute \src "libresoc.v:182322.3-182323.43" + process $proc$libresoc.v:182322$11426 assign { } { } assign $0\src25__data_o[3:0] \src25__data_o$next sync posedge \coresync_clk update \src25__data_o $0\src25__data_o[3:0] end - attribute \src "libresoc.v:182576.3-182577.43" - process $proc$libresoc.v:182576$11433 + attribute \src "libresoc.v:182324.3-182325.43" + process $proc$libresoc.v:182324$11427 assign { } { } assign $0\src15__data_o[3:0] \src15__data_o$next sync posedge \coresync_clk update \src15__data_o $0\src15__data_o[3:0] end - attribute \src "libresoc.v:182578.3-182617.6" - process $proc$libresoc.v:182578$11434 + attribute \src "libresoc.v:182326.3-182365.6" + process $proc$libresoc.v:182326$11428 assign { } { } assign { } { } assign { } { } - assign $0\src15__data_o$next[3:0]$11435 $6\src15__data_o$next[3:0]$11441 - attribute \src "libresoc.v:182579.5-182579.29" + assign $0\src15__data_o$next[3:0]$11429 $6\src15__data_o$next[3:0]$11435 + attribute \src "libresoc.v:182327.5-182327.29" switch \initial - attribute \src "libresoc.v:182579.9-182579.17" + attribute \src "libresoc.v:182327.9-182327.17" case 1'1 case end @@ -340561,66 +340267,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src15__data_o$next[3:0]$11436 $5\src15__data_o$next[3:0]$11440 + assign $1\src15__data_o$next[3:0]$11430 $5\src15__data_o$next[3:0]$11434 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src15__data_o$next[3:0]$11437 \dest15__data_i + assign $2\src15__data_o$next[3:0]$11431 \dest15__data_i case - assign $2\src15__data_o$next[3:0]$11437 4'0000 + assign $2\src15__data_o$next[3:0]$11431 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src15__data_o$next[3:0]$11438 \dest25__data_i + assign $3\src15__data_o$next[3:0]$11432 \dest25__data_i case - assign $3\src15__data_o$next[3:0]$11438 $2\src15__data_o$next[3:0]$11437 + assign $3\src15__data_o$next[3:0]$11432 $2\src15__data_o$next[3:0]$11431 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src15__data_o$next[3:0]$11439 \w5__data_i + assign $4\src15__data_o$next[3:0]$11433 \w5__data_i case - assign $4\src15__data_o$next[3:0]$11439 $3\src15__data_o$next[3:0]$11438 + assign $4\src15__data_o$next[3:0]$11433 $3\src15__data_o$next[3:0]$11432 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src15__data_o$next[3:0]$11440 \reg + assign $5\src15__data_o$next[3:0]$11434 \reg case - assign $5\src15__data_o$next[3:0]$11440 $4\src15__data_o$next[3:0]$11439 + assign $5\src15__data_o$next[3:0]$11434 $4\src15__data_o$next[3:0]$11433 end case - assign $1\src15__data_o$next[3:0]$11436 4'0000 + assign $1\src15__data_o$next[3:0]$11430 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src15__data_o$next[3:0]$11441 4'0000 + assign $6\src15__data_o$next[3:0]$11435 4'0000 case - assign $6\src15__data_o$next[3:0]$11441 $1\src15__data_o$next[3:0]$11436 + assign $6\src15__data_o$next[3:0]$11435 $1\src15__data_o$next[3:0]$11430 end sync always - update \src15__data_o$next $0\src15__data_o$next[3:0]$11435 + update \src15__data_o$next $0\src15__data_o$next[3:0]$11429 end - attribute \src "libresoc.v:182618.3-182647.6" - process $proc$libresoc.v:182618$11442 + attribute \src "libresoc.v:182366.3-182395.6" + process $proc$libresoc.v:182366$11436 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:182619.5-182619.29" + attribute \src "libresoc.v:182367.5-182367.29" switch \initial - attribute \src "libresoc.v:182619.9-182619.17" + attribute \src "libresoc.v:182367.9-182367.17" case 1'1 case end @@ -340666,17 +340372,17 @@ module \reg_5 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:182648.3-182674.6" - process $proc$libresoc.v:182648$11443 + attribute \src "libresoc.v:182396.3-182422.6" + process $proc$libresoc.v:182396$11437 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11444 $4\reg$next[3:0]$11448 - attribute \src "libresoc.v:182649.5-182649.29" + assign $0\reg$next[3:0]$11438 $4\reg$next[3:0]$11442 + attribute \src "libresoc.v:182397.5-182397.29" switch \initial - attribute \src "libresoc.v:182649.9-182649.17" + attribute \src "libresoc.v:182397.9-182397.17" case 1'1 case end @@ -340685,49 +340391,49 @@ module \reg_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11445 \dest15__data_i + assign $1\reg$next[3:0]$11439 \dest15__data_i case - assign $1\reg$next[3:0]$11445 \reg + assign $1\reg$next[3:0]$11439 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11446 \dest25__data_i + assign $2\reg$next[3:0]$11440 \dest25__data_i case - assign $2\reg$next[3:0]$11446 $1\reg$next[3:0]$11445 + assign $2\reg$next[3:0]$11440 $1\reg$next[3:0]$11439 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11447 \w5__data_i + assign $3\reg$next[3:0]$11441 \w5__data_i case - assign $3\reg$next[3:0]$11447 $2\reg$next[3:0]$11446 + assign $3\reg$next[3:0]$11441 $2\reg$next[3:0]$11440 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11448 4'0000 + assign $4\reg$next[3:0]$11442 4'0000 case - assign $4\reg$next[3:0]$11448 $3\reg$next[3:0]$11447 + assign $4\reg$next[3:0]$11442 $3\reg$next[3:0]$11441 end sync always - update \reg$next $0\reg$next[3:0]$11444 + update \reg$next $0\reg$next[3:0]$11438 end - attribute \src "libresoc.v:182675.3-182714.6" - process $proc$libresoc.v:182675$11449 + attribute \src "libresoc.v:182423.3-182462.6" + process $proc$libresoc.v:182423$11443 assign { } { } assign { } { } assign { } { } - assign $0\src25__data_o$next[3:0]$11450 $6\src25__data_o$next[3:0]$11456 - attribute \src "libresoc.v:182676.5-182676.29" + assign $0\src25__data_o$next[3:0]$11444 $6\src25__data_o$next[3:0]$11450 + attribute \src "libresoc.v:182424.5-182424.29" switch \initial - attribute \src "libresoc.v:182676.9-182676.17" + attribute \src "libresoc.v:182424.9-182424.17" case 1'1 case end @@ -340739,66 +340445,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src25__data_o$next[3:0]$11451 $5\src25__data_o$next[3:0]$11455 + assign $1\src25__data_o$next[3:0]$11445 $5\src25__data_o$next[3:0]$11449 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src25__data_o$next[3:0]$11452 \dest15__data_i + assign $2\src25__data_o$next[3:0]$11446 \dest15__data_i case - assign $2\src25__data_o$next[3:0]$11452 4'0000 + assign $2\src25__data_o$next[3:0]$11446 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src25__data_o$next[3:0]$11453 \dest25__data_i + assign $3\src25__data_o$next[3:0]$11447 \dest25__data_i case - assign $3\src25__data_o$next[3:0]$11453 $2\src25__data_o$next[3:0]$11452 + assign $3\src25__data_o$next[3:0]$11447 $2\src25__data_o$next[3:0]$11446 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src25__data_o$next[3:0]$11454 \w5__data_i + assign $4\src25__data_o$next[3:0]$11448 \w5__data_i case - assign $4\src25__data_o$next[3:0]$11454 $3\src25__data_o$next[3:0]$11453 + assign $4\src25__data_o$next[3:0]$11448 $3\src25__data_o$next[3:0]$11447 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src25__data_o$next[3:0]$11455 \reg + assign $5\src25__data_o$next[3:0]$11449 \reg case - assign $5\src25__data_o$next[3:0]$11455 $4\src25__data_o$next[3:0]$11454 + assign $5\src25__data_o$next[3:0]$11449 $4\src25__data_o$next[3:0]$11448 end case - assign $1\src25__data_o$next[3:0]$11451 4'0000 + assign $1\src25__data_o$next[3:0]$11445 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src25__data_o$next[3:0]$11456 4'0000 + assign $6\src25__data_o$next[3:0]$11450 4'0000 case - assign $6\src25__data_o$next[3:0]$11456 $1\src25__data_o$next[3:0]$11451 + assign $6\src25__data_o$next[3:0]$11450 $1\src25__data_o$next[3:0]$11445 end sync always - update \src25__data_o$next $0\src25__data_o$next[3:0]$11450 + update \src25__data_o$next $0\src25__data_o$next[3:0]$11444 end - attribute \src "libresoc.v:182715.3-182744.6" - process $proc$libresoc.v:182715$11457 + attribute \src "libresoc.v:182463.3-182492.6" + process $proc$libresoc.v:182463$11451 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11458 $1\wr_detect$4[0:0]$11459 - attribute \src "libresoc.v:182716.5-182716.29" + assign $0\wr_detect$4[0:0]$11452 $1\wr_detect$4[0:0]$11453 + attribute \src "libresoc.v:182464.5-182464.29" switch \initial - attribute \src "libresoc.v:182716.9-182716.17" + attribute \src "libresoc.v:182464.9-182464.17" case 1'1 case end @@ -340810,49 +340516,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11459 $4\wr_detect$4[0:0]$11462 + assign $1\wr_detect$4[0:0]$11453 $4\wr_detect$4[0:0]$11456 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11460 1'1 + assign $2\wr_detect$4[0:0]$11454 1'1 case - assign $2\wr_detect$4[0:0]$11460 1'0 + assign $2\wr_detect$4[0:0]$11454 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11461 1'1 + assign $3\wr_detect$4[0:0]$11455 1'1 case - assign $3\wr_detect$4[0:0]$11461 $2\wr_detect$4[0:0]$11460 + assign $3\wr_detect$4[0:0]$11455 $2\wr_detect$4[0:0]$11454 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11462 1'1 + assign $4\wr_detect$4[0:0]$11456 1'1 case - assign $4\wr_detect$4[0:0]$11462 $3\wr_detect$4[0:0]$11461 + assign $4\wr_detect$4[0:0]$11456 $3\wr_detect$4[0:0]$11455 end case - assign $1\wr_detect$4[0:0]$11459 1'0 + assign $1\wr_detect$4[0:0]$11453 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11458 + update \wr_detect$4 $0\wr_detect$4[0:0]$11452 end - attribute \src "libresoc.v:182745.3-182784.6" - process $proc$libresoc.v:182745$11463 + attribute \src "libresoc.v:182493.3-182532.6" + process $proc$libresoc.v:182493$11457 assign { } { } assign { } { } assign { } { } - assign $0\src35__data_o$next[3:0]$11464 $6\src35__data_o$next[3:0]$11470 - attribute \src "libresoc.v:182746.5-182746.29" + assign $0\src35__data_o$next[3:0]$11458 $6\src35__data_o$next[3:0]$11464 + attribute \src "libresoc.v:182494.5-182494.29" switch \initial - attribute \src "libresoc.v:182746.9-182746.17" + attribute \src "libresoc.v:182494.9-182494.17" case 1'1 case end @@ -340864,66 +340570,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src35__data_o$next[3:0]$11465 $5\src35__data_o$next[3:0]$11469 + assign $1\src35__data_o$next[3:0]$11459 $5\src35__data_o$next[3:0]$11463 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src35__data_o$next[3:0]$11466 \dest15__data_i + assign $2\src35__data_o$next[3:0]$11460 \dest15__data_i case - assign $2\src35__data_o$next[3:0]$11466 4'0000 + assign $2\src35__data_o$next[3:0]$11460 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src35__data_o$next[3:0]$11467 \dest25__data_i + assign $3\src35__data_o$next[3:0]$11461 \dest25__data_i case - assign $3\src35__data_o$next[3:0]$11467 $2\src35__data_o$next[3:0]$11466 + assign $3\src35__data_o$next[3:0]$11461 $2\src35__data_o$next[3:0]$11460 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src35__data_o$next[3:0]$11468 \w5__data_i + assign $4\src35__data_o$next[3:0]$11462 \w5__data_i case - assign $4\src35__data_o$next[3:0]$11468 $3\src35__data_o$next[3:0]$11467 + assign $4\src35__data_o$next[3:0]$11462 $3\src35__data_o$next[3:0]$11461 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src35__data_o$next[3:0]$11469 \reg + assign $5\src35__data_o$next[3:0]$11463 \reg case - assign $5\src35__data_o$next[3:0]$11469 $4\src35__data_o$next[3:0]$11468 + assign $5\src35__data_o$next[3:0]$11463 $4\src35__data_o$next[3:0]$11462 end case - assign $1\src35__data_o$next[3:0]$11465 4'0000 + assign $1\src35__data_o$next[3:0]$11459 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src35__data_o$next[3:0]$11470 4'0000 + assign $6\src35__data_o$next[3:0]$11464 4'0000 case - assign $6\src35__data_o$next[3:0]$11470 $1\src35__data_o$next[3:0]$11465 + assign $6\src35__data_o$next[3:0]$11464 $1\src35__data_o$next[3:0]$11459 end sync always - update \src35__data_o$next $0\src35__data_o$next[3:0]$11464 + update \src35__data_o$next $0\src35__data_o$next[3:0]$11458 end - attribute \src "libresoc.v:182785.3-182814.6" - process $proc$libresoc.v:182785$11471 + attribute \src "libresoc.v:182533.3-182562.6" + process $proc$libresoc.v:182533$11465 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11472 $1\wr_detect$7[0:0]$11473 - attribute \src "libresoc.v:182786.5-182786.29" + assign $0\wr_detect$7[0:0]$11466 $1\wr_detect$7[0:0]$11467 + attribute \src "libresoc.v:182534.5-182534.29" switch \initial - attribute \src "libresoc.v:182786.9-182786.17" + attribute \src "libresoc.v:182534.9-182534.17" case 1'1 case end @@ -340935,49 +340641,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11473 $4\wr_detect$7[0:0]$11476 + assign $1\wr_detect$7[0:0]$11467 $4\wr_detect$7[0:0]$11470 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11474 1'1 + assign $2\wr_detect$7[0:0]$11468 1'1 case - assign $2\wr_detect$7[0:0]$11474 1'0 + assign $2\wr_detect$7[0:0]$11468 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11475 1'1 + assign $3\wr_detect$7[0:0]$11469 1'1 case - assign $3\wr_detect$7[0:0]$11475 $2\wr_detect$7[0:0]$11474 + assign $3\wr_detect$7[0:0]$11469 $2\wr_detect$7[0:0]$11468 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11476 1'1 + assign $4\wr_detect$7[0:0]$11470 1'1 case - assign $4\wr_detect$7[0:0]$11476 $3\wr_detect$7[0:0]$11475 + assign $4\wr_detect$7[0:0]$11470 $3\wr_detect$7[0:0]$11469 end case - assign $1\wr_detect$7[0:0]$11473 1'0 + assign $1\wr_detect$7[0:0]$11467 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11472 + update \wr_detect$7 $0\wr_detect$7[0:0]$11466 end - attribute \src "libresoc.v:182815.3-182854.6" - process $proc$libresoc.v:182815$11477 + attribute \src "libresoc.v:182563.3-182602.6" + process $proc$libresoc.v:182563$11471 assign { } { } assign { } { } assign { } { } - assign $0\r5__data_o$next[3:0]$11478 $6\r5__data_o$next[3:0]$11484 - attribute \src "libresoc.v:182816.5-182816.29" + assign $0\r5__data_o$next[3:0]$11472 $6\r5__data_o$next[3:0]$11478 + attribute \src "libresoc.v:182564.5-182564.29" switch \initial - attribute \src "libresoc.v:182816.9-182816.17" + attribute \src "libresoc.v:182564.9-182564.17" case 1'1 case end @@ -340989,66 +340695,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r5__data_o$next[3:0]$11479 $5\r5__data_o$next[3:0]$11483 + assign $1\r5__data_o$next[3:0]$11473 $5\r5__data_o$next[3:0]$11477 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r5__data_o$next[3:0]$11480 \dest15__data_i + assign $2\r5__data_o$next[3:0]$11474 \dest15__data_i case - assign $2\r5__data_o$next[3:0]$11480 4'0000 + assign $2\r5__data_o$next[3:0]$11474 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r5__data_o$next[3:0]$11481 \dest25__data_i + assign $3\r5__data_o$next[3:0]$11475 \dest25__data_i case - assign $3\r5__data_o$next[3:0]$11481 $2\r5__data_o$next[3:0]$11480 + assign $3\r5__data_o$next[3:0]$11475 $2\r5__data_o$next[3:0]$11474 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r5__data_o$next[3:0]$11482 \w5__data_i + assign $4\r5__data_o$next[3:0]$11476 \w5__data_i case - assign $4\r5__data_o$next[3:0]$11482 $3\r5__data_o$next[3:0]$11481 + assign $4\r5__data_o$next[3:0]$11476 $3\r5__data_o$next[3:0]$11475 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r5__data_o$next[3:0]$11483 \reg + assign $5\r5__data_o$next[3:0]$11477 \reg case - assign $5\r5__data_o$next[3:0]$11483 $4\r5__data_o$next[3:0]$11482 + assign $5\r5__data_o$next[3:0]$11477 $4\r5__data_o$next[3:0]$11476 end case - assign $1\r5__data_o$next[3:0]$11479 4'0000 + assign $1\r5__data_o$next[3:0]$11473 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r5__data_o$next[3:0]$11484 4'0000 + assign $6\r5__data_o$next[3:0]$11478 4'0000 case - assign $6\r5__data_o$next[3:0]$11484 $1\r5__data_o$next[3:0]$11479 + assign $6\r5__data_o$next[3:0]$11478 $1\r5__data_o$next[3:0]$11473 end sync always - update \r5__data_o$next $0\r5__data_o$next[3:0]$11478 + update \r5__data_o$next $0\r5__data_o$next[3:0]$11472 end - attribute \src "libresoc.v:182855.3-182884.6" - process $proc$libresoc.v:182855$11485 + attribute \src "libresoc.v:182603.3-182632.6" + process $proc$libresoc.v:182603$11479 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11486 $1\wr_detect$10[0:0]$11487 - attribute \src "libresoc.v:182856.5-182856.29" + assign $0\wr_detect$10[0:0]$11480 $1\wr_detect$10[0:0]$11481 + attribute \src "libresoc.v:182604.5-182604.29" switch \initial - attribute \src "libresoc.v:182856.9-182856.17" + attribute \src "libresoc.v:182604.9-182604.17" case 1'1 case end @@ -341060,49 +340766,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11487 $4\wr_detect$10[0:0]$11490 + assign $1\wr_detect$10[0:0]$11481 $4\wr_detect$10[0:0]$11484 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11488 1'1 + assign $2\wr_detect$10[0:0]$11482 1'1 case - assign $2\wr_detect$10[0:0]$11488 1'0 + assign $2\wr_detect$10[0:0]$11482 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11489 1'1 + assign $3\wr_detect$10[0:0]$11483 1'1 case - assign $3\wr_detect$10[0:0]$11489 $2\wr_detect$10[0:0]$11488 + assign $3\wr_detect$10[0:0]$11483 $2\wr_detect$10[0:0]$11482 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11490 1'1 + assign $4\wr_detect$10[0:0]$11484 1'1 case - assign $4\wr_detect$10[0:0]$11490 $3\wr_detect$10[0:0]$11489 + assign $4\wr_detect$10[0:0]$11484 $3\wr_detect$10[0:0]$11483 end case - assign $1\wr_detect$10[0:0]$11487 1'0 + assign $1\wr_detect$10[0:0]$11481 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11486 + update \wr_detect$10 $0\wr_detect$10[0:0]$11480 end - attribute \src "libresoc.v:182885.3-182924.6" - process $proc$libresoc.v:182885$11491 + attribute \src "libresoc.v:182633.3-182672.6" + process $proc$libresoc.v:182633$11485 assign { } { } assign { } { } assign { } { } - assign $0\r25__data_o$next[3:0]$11492 $6\r25__data_o$next[3:0]$11498 - attribute \src "libresoc.v:182886.5-182886.29" + assign $0\r25__data_o$next[3:0]$11486 $6\r25__data_o$next[3:0]$11492 + attribute \src "libresoc.v:182634.5-182634.29" switch \initial - attribute \src "libresoc.v:182886.9-182886.17" + attribute \src "libresoc.v:182634.9-182634.17" case 1'1 case end @@ -341114,66 +340820,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r25__data_o$next[3:0]$11493 $5\r25__data_o$next[3:0]$11497 + assign $1\r25__data_o$next[3:0]$11487 $5\r25__data_o$next[3:0]$11491 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r25__data_o$next[3:0]$11494 \dest15__data_i + assign $2\r25__data_o$next[3:0]$11488 \dest15__data_i case - assign $2\r25__data_o$next[3:0]$11494 4'0000 + assign $2\r25__data_o$next[3:0]$11488 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r25__data_o$next[3:0]$11495 \dest25__data_i + assign $3\r25__data_o$next[3:0]$11489 \dest25__data_i case - assign $3\r25__data_o$next[3:0]$11495 $2\r25__data_o$next[3:0]$11494 + assign $3\r25__data_o$next[3:0]$11489 $2\r25__data_o$next[3:0]$11488 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r25__data_o$next[3:0]$11496 \w5__data_i + assign $4\r25__data_o$next[3:0]$11490 \w5__data_i case - assign $4\r25__data_o$next[3:0]$11496 $3\r25__data_o$next[3:0]$11495 + assign $4\r25__data_o$next[3:0]$11490 $3\r25__data_o$next[3:0]$11489 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r25__data_o$next[3:0]$11497 \reg + assign $5\r25__data_o$next[3:0]$11491 \reg case - assign $5\r25__data_o$next[3:0]$11497 $4\r25__data_o$next[3:0]$11496 + assign $5\r25__data_o$next[3:0]$11491 $4\r25__data_o$next[3:0]$11490 end case - assign $1\r25__data_o$next[3:0]$11493 4'0000 + assign $1\r25__data_o$next[3:0]$11487 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r25__data_o$next[3:0]$11498 4'0000 + assign $6\r25__data_o$next[3:0]$11492 4'0000 case - assign $6\r25__data_o$next[3:0]$11498 $1\r25__data_o$next[3:0]$11493 + assign $6\r25__data_o$next[3:0]$11492 $1\r25__data_o$next[3:0]$11487 end sync always - update \r25__data_o$next $0\r25__data_o$next[3:0]$11492 + update \r25__data_o$next $0\r25__data_o$next[3:0]$11486 end - attribute \src "libresoc.v:182925.3-182954.6" - process $proc$libresoc.v:182925$11499 + attribute \src "libresoc.v:182673.3-182702.6" + process $proc$libresoc.v:182673$11493 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11500 $1\wr_detect$13[0:0]$11501 - attribute \src "libresoc.v:182926.5-182926.29" + assign $0\wr_detect$13[0:0]$11494 $1\wr_detect$13[0:0]$11495 + attribute \src "libresoc.v:182674.5-182674.29" switch \initial - attribute \src "libresoc.v:182926.9-182926.17" + attribute \src "libresoc.v:182674.9-182674.17" case 1'1 case end @@ -341185,217 +340891,217 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11501 $4\wr_detect$13[0:0]$11504 + assign $1\wr_detect$13[0:0]$11495 $4\wr_detect$13[0:0]$11498 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11502 1'1 + assign $2\wr_detect$13[0:0]$11496 1'1 case - assign $2\wr_detect$13[0:0]$11502 1'0 + assign $2\wr_detect$13[0:0]$11496 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11503 1'1 + assign $3\wr_detect$13[0:0]$11497 1'1 case - assign $3\wr_detect$13[0:0]$11503 $2\wr_detect$13[0:0]$11502 + assign $3\wr_detect$13[0:0]$11497 $2\wr_detect$13[0:0]$11496 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11504 1'1 + assign $4\wr_detect$13[0:0]$11498 1'1 case - assign $4\wr_detect$13[0:0]$11504 $3\wr_detect$13[0:0]$11503 + assign $4\wr_detect$13[0:0]$11498 $3\wr_detect$13[0:0]$11497 end case - assign $1\wr_detect$13[0:0]$11501 1'0 + assign $1\wr_detect$13[0:0]$11495 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11500 + update \wr_detect$13 $0\wr_detect$13[0:0]$11494 end - connect \$9 $not$libresoc.v:182561$11423_Y - connect \$12 $not$libresoc.v:182562$11424_Y - connect \$1 $not$libresoc.v:182563$11425_Y - connect \$3 $not$libresoc.v:182564$11426_Y - connect \$6 $not$libresoc.v:182565$11427_Y + connect \$9 $not$libresoc.v:182309$11417_Y + connect \$12 $not$libresoc.v:182310$11418_Y + connect \$1 $not$libresoc.v:182311$11419_Y + connect \$3 $not$libresoc.v:182312$11420_Y + connect \$6 $not$libresoc.v:182313$11421_Y end -attribute \src "libresoc.v:182959.1-183430.10" +attribute \src "libresoc.v:182707.1-183178.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" attribute \generator "nMigen" module \reg_6 - attribute \src "libresoc.v:182960.7-182960.20" + attribute \src "libresoc.v:182708.7-182708.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183360.3-183399.6" - wire width 4 $0\r26__data_o$next[3:0]$11581 - attribute \src "libresoc.v:183043.3-183044.39" + attribute \src "libresoc.v:183108.3-183147.6" + wire width 4 $0\r26__data_o$next[3:0]$11575 + attribute \src "libresoc.v:182791.3-182792.39" wire width 4 $0\r26__data_o[3:0] - attribute \src "libresoc.v:183290.3-183329.6" - wire width 4 $0\r6__data_o$next[3:0]$11567 - attribute \src "libresoc.v:183045.3-183046.37" + attribute \src "libresoc.v:183038.3-183077.6" + wire width 4 $0\r6__data_o$next[3:0]$11561 + attribute \src "libresoc.v:182793.3-182794.37" wire width 4 $0\r6__data_o[3:0] - attribute \src "libresoc.v:183123.3-183149.6" - wire width 4 $0\reg$next[3:0]$11533 - attribute \src "libresoc.v:183041.3-183042.25" + attribute \src "libresoc.v:182871.3-182897.6" + wire width 4 $0\reg$next[3:0]$11527 + attribute \src "libresoc.v:182789.3-182790.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:183053.3-183092.6" - wire width 4 $0\src16__data_o$next[3:0]$11524 - attribute \src "libresoc.v:183051.3-183052.43" + attribute \src "libresoc.v:182801.3-182840.6" + wire width 4 $0\src16__data_o$next[3:0]$11518 + attribute \src "libresoc.v:182799.3-182800.43" wire width 4 $0\src16__data_o[3:0] - attribute \src "libresoc.v:183150.3-183189.6" - wire width 4 $0\src26__data_o$next[3:0]$11539 - attribute \src "libresoc.v:183049.3-183050.43" + attribute \src "libresoc.v:182898.3-182937.6" + wire width 4 $0\src26__data_o$next[3:0]$11533 + attribute \src "libresoc.v:182797.3-182798.43" wire width 4 $0\src26__data_o[3:0] - attribute \src "libresoc.v:183220.3-183259.6" - wire width 4 $0\src36__data_o$next[3:0]$11553 - attribute \src "libresoc.v:183047.3-183048.43" + attribute \src "libresoc.v:182968.3-183007.6" + wire width 4 $0\src36__data_o$next[3:0]$11547 + attribute \src "libresoc.v:182795.3-182796.43" wire width 4 $0\src36__data_o[3:0] - attribute \src "libresoc.v:183330.3-183359.6" - wire $0\wr_detect$10[0:0]$11575 - attribute \src "libresoc.v:183400.3-183429.6" - wire $0\wr_detect$13[0:0]$11589 - attribute \src "libresoc.v:183190.3-183219.6" - wire $0\wr_detect$4[0:0]$11547 - attribute \src "libresoc.v:183260.3-183289.6" - wire $0\wr_detect$7[0:0]$11561 - attribute \src "libresoc.v:183093.3-183122.6" + attribute \src "libresoc.v:183078.3-183107.6" + wire $0\wr_detect$10[0:0]$11569 + attribute \src "libresoc.v:183148.3-183177.6" + wire $0\wr_detect$13[0:0]$11583 + attribute \src "libresoc.v:182938.3-182967.6" + wire $0\wr_detect$4[0:0]$11541 + attribute \src "libresoc.v:183008.3-183037.6" + wire $0\wr_detect$7[0:0]$11555 + attribute \src "libresoc.v:182841.3-182870.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:183360.3-183399.6" - wire width 4 $1\r26__data_o$next[3:0]$11582 - attribute \src "libresoc.v:182985.13-182985.31" + attribute \src "libresoc.v:183108.3-183147.6" + wire width 4 $1\r26__data_o$next[3:0]$11576 + attribute \src "libresoc.v:182733.13-182733.31" wire width 4 $1\r26__data_o[3:0] - attribute \src "libresoc.v:183290.3-183329.6" - wire width 4 $1\r6__data_o$next[3:0]$11568 - attribute \src "libresoc.v:182992.13-182992.30" + attribute \src "libresoc.v:183038.3-183077.6" + wire width 4 $1\r6__data_o$next[3:0]$11562 + attribute \src "libresoc.v:182740.13-182740.30" wire width 4 $1\r6__data_o[3:0] - attribute \src "libresoc.v:183123.3-183149.6" - wire width 4 $1\reg$next[3:0]$11534 - attribute \src "libresoc.v:182998.13-182998.25" + attribute \src "libresoc.v:182871.3-182897.6" + wire width 4 $1\reg$next[3:0]$11528 + attribute \src "libresoc.v:182746.13-182746.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:183053.3-183092.6" - wire width 4 $1\src16__data_o$next[3:0]$11525 - attribute \src "libresoc.v:183003.13-183003.33" + attribute \src "libresoc.v:182801.3-182840.6" + wire width 4 $1\src16__data_o$next[3:0]$11519 + attribute \src "libresoc.v:182751.13-182751.33" wire width 4 $1\src16__data_o[3:0] - attribute \src "libresoc.v:183150.3-183189.6" - wire width 4 $1\src26__data_o$next[3:0]$11540 - attribute \src "libresoc.v:183010.13-183010.33" + attribute \src "libresoc.v:182898.3-182937.6" + wire width 4 $1\src26__data_o$next[3:0]$11534 + attribute \src "libresoc.v:182758.13-182758.33" wire width 4 $1\src26__data_o[3:0] - attribute \src "libresoc.v:183220.3-183259.6" - wire width 4 $1\src36__data_o$next[3:0]$11554 - attribute \src "libresoc.v:183017.13-183017.33" + attribute \src "libresoc.v:182968.3-183007.6" + wire width 4 $1\src36__data_o$next[3:0]$11548 + attribute \src "libresoc.v:182765.13-182765.33" wire width 4 $1\src36__data_o[3:0] - attribute \src "libresoc.v:183330.3-183359.6" - wire $1\wr_detect$10[0:0]$11576 - attribute \src "libresoc.v:183400.3-183429.6" - wire $1\wr_detect$13[0:0]$11590 - attribute \src "libresoc.v:183190.3-183219.6" - wire $1\wr_detect$4[0:0]$11548 - attribute \src "libresoc.v:183260.3-183289.6" - wire $1\wr_detect$7[0:0]$11562 - attribute \src "libresoc.v:183093.3-183122.6" + attribute \src "libresoc.v:183078.3-183107.6" + wire $1\wr_detect$10[0:0]$11570 + attribute \src "libresoc.v:183148.3-183177.6" + wire $1\wr_detect$13[0:0]$11584 + attribute \src "libresoc.v:182938.3-182967.6" + wire $1\wr_detect$4[0:0]$11542 + attribute \src "libresoc.v:183008.3-183037.6" + wire $1\wr_detect$7[0:0]$11556 + attribute \src "libresoc.v:182841.3-182870.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:183360.3-183399.6" - wire width 4 $2\r26__data_o$next[3:0]$11583 - attribute \src "libresoc.v:183290.3-183329.6" - wire width 4 $2\r6__data_o$next[3:0]$11569 - attribute \src "libresoc.v:183123.3-183149.6" - wire width 4 $2\reg$next[3:0]$11535 - attribute \src "libresoc.v:183053.3-183092.6" - wire width 4 $2\src16__data_o$next[3:0]$11526 - attribute \src "libresoc.v:183150.3-183189.6" - wire width 4 $2\src26__data_o$next[3:0]$11541 - attribute \src "libresoc.v:183220.3-183259.6" - wire width 4 $2\src36__data_o$next[3:0]$11555 - attribute \src "libresoc.v:183330.3-183359.6" - wire $2\wr_detect$10[0:0]$11577 - attribute \src "libresoc.v:183400.3-183429.6" - wire $2\wr_detect$13[0:0]$11591 - attribute \src "libresoc.v:183190.3-183219.6" - wire $2\wr_detect$4[0:0]$11549 - attribute \src "libresoc.v:183260.3-183289.6" - wire $2\wr_detect$7[0:0]$11563 - attribute \src "libresoc.v:183093.3-183122.6" + attribute \src "libresoc.v:183108.3-183147.6" + wire width 4 $2\r26__data_o$next[3:0]$11577 + attribute \src "libresoc.v:183038.3-183077.6" + wire width 4 $2\r6__data_o$next[3:0]$11563 + attribute \src "libresoc.v:182871.3-182897.6" + wire width 4 $2\reg$next[3:0]$11529 + attribute \src "libresoc.v:182801.3-182840.6" + wire width 4 $2\src16__data_o$next[3:0]$11520 + attribute \src "libresoc.v:182898.3-182937.6" + wire width 4 $2\src26__data_o$next[3:0]$11535 + attribute \src "libresoc.v:182968.3-183007.6" + wire width 4 $2\src36__data_o$next[3:0]$11549 + attribute \src "libresoc.v:183078.3-183107.6" + wire $2\wr_detect$10[0:0]$11571 + attribute \src "libresoc.v:183148.3-183177.6" + wire $2\wr_detect$13[0:0]$11585 + attribute \src "libresoc.v:182938.3-182967.6" + wire $2\wr_detect$4[0:0]$11543 + attribute \src "libresoc.v:183008.3-183037.6" + wire $2\wr_detect$7[0:0]$11557 + attribute \src "libresoc.v:182841.3-182870.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:183360.3-183399.6" - wire width 4 $3\r26__data_o$next[3:0]$11584 - attribute \src "libresoc.v:183290.3-183329.6" - wire width 4 $3\r6__data_o$next[3:0]$11570 - attribute \src "libresoc.v:183123.3-183149.6" - wire width 4 $3\reg$next[3:0]$11536 - attribute \src "libresoc.v:183053.3-183092.6" - wire width 4 $3\src16__data_o$next[3:0]$11527 - attribute \src "libresoc.v:183150.3-183189.6" - wire width 4 $3\src26__data_o$next[3:0]$11542 - attribute \src "libresoc.v:183220.3-183259.6" - wire width 4 $3\src36__data_o$next[3:0]$11556 - attribute \src "libresoc.v:183330.3-183359.6" - wire $3\wr_detect$10[0:0]$11578 - attribute \src "libresoc.v:183400.3-183429.6" - wire $3\wr_detect$13[0:0]$11592 - attribute \src "libresoc.v:183190.3-183219.6" - wire $3\wr_detect$4[0:0]$11550 - attribute \src "libresoc.v:183260.3-183289.6" - wire $3\wr_detect$7[0:0]$11564 - attribute \src "libresoc.v:183093.3-183122.6" + attribute \src "libresoc.v:183108.3-183147.6" + wire width 4 $3\r26__data_o$next[3:0]$11578 + attribute \src "libresoc.v:183038.3-183077.6" + wire width 4 $3\r6__data_o$next[3:0]$11564 + attribute \src "libresoc.v:182871.3-182897.6" + wire width 4 $3\reg$next[3:0]$11530 + attribute \src "libresoc.v:182801.3-182840.6" + wire width 4 $3\src16__data_o$next[3:0]$11521 + attribute \src "libresoc.v:182898.3-182937.6" + wire width 4 $3\src26__data_o$next[3:0]$11536 + attribute \src "libresoc.v:182968.3-183007.6" + wire width 4 $3\src36__data_o$next[3:0]$11550 + attribute \src "libresoc.v:183078.3-183107.6" + wire $3\wr_detect$10[0:0]$11572 + attribute \src "libresoc.v:183148.3-183177.6" + wire $3\wr_detect$13[0:0]$11586 + attribute \src "libresoc.v:182938.3-182967.6" + wire $3\wr_detect$4[0:0]$11544 + attribute \src "libresoc.v:183008.3-183037.6" + wire $3\wr_detect$7[0:0]$11558 + attribute \src "libresoc.v:182841.3-182870.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:183360.3-183399.6" - wire width 4 $4\r26__data_o$next[3:0]$11585 - attribute \src "libresoc.v:183290.3-183329.6" - wire width 4 $4\r6__data_o$next[3:0]$11571 - attribute \src "libresoc.v:183123.3-183149.6" - wire width 4 $4\reg$next[3:0]$11537 - attribute \src "libresoc.v:183053.3-183092.6" - wire width 4 $4\src16__data_o$next[3:0]$11528 - attribute \src "libresoc.v:183150.3-183189.6" - wire width 4 $4\src26__data_o$next[3:0]$11543 - attribute \src "libresoc.v:183220.3-183259.6" - wire width 4 $4\src36__data_o$next[3:0]$11557 - attribute \src "libresoc.v:183330.3-183359.6" - wire $4\wr_detect$10[0:0]$11579 - attribute \src "libresoc.v:183400.3-183429.6" - wire $4\wr_detect$13[0:0]$11593 - attribute \src "libresoc.v:183190.3-183219.6" - wire $4\wr_detect$4[0:0]$11551 - attribute \src "libresoc.v:183260.3-183289.6" - wire $4\wr_detect$7[0:0]$11565 - attribute \src "libresoc.v:183093.3-183122.6" + attribute \src "libresoc.v:183108.3-183147.6" + wire width 4 $4\r26__data_o$next[3:0]$11579 + attribute \src "libresoc.v:183038.3-183077.6" + wire width 4 $4\r6__data_o$next[3:0]$11565 + attribute \src "libresoc.v:182871.3-182897.6" + wire width 4 $4\reg$next[3:0]$11531 + attribute \src "libresoc.v:182801.3-182840.6" + wire width 4 $4\src16__data_o$next[3:0]$11522 + attribute \src "libresoc.v:182898.3-182937.6" + wire width 4 $4\src26__data_o$next[3:0]$11537 + attribute \src "libresoc.v:182968.3-183007.6" + wire width 4 $4\src36__data_o$next[3:0]$11551 + attribute \src "libresoc.v:183078.3-183107.6" + wire $4\wr_detect$10[0:0]$11573 + attribute \src "libresoc.v:183148.3-183177.6" + wire $4\wr_detect$13[0:0]$11587 + attribute \src "libresoc.v:182938.3-182967.6" + wire $4\wr_detect$4[0:0]$11545 + attribute \src "libresoc.v:183008.3-183037.6" + wire $4\wr_detect$7[0:0]$11559 + attribute \src "libresoc.v:182841.3-182870.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:183360.3-183399.6" - wire width 4 $5\r26__data_o$next[3:0]$11586 - attribute \src "libresoc.v:183290.3-183329.6" - wire width 4 $5\r6__data_o$next[3:0]$11572 - attribute \src "libresoc.v:183053.3-183092.6" - wire width 4 $5\src16__data_o$next[3:0]$11529 - attribute \src "libresoc.v:183150.3-183189.6" - wire width 4 $5\src26__data_o$next[3:0]$11544 - attribute \src "libresoc.v:183220.3-183259.6" - wire width 4 $5\src36__data_o$next[3:0]$11558 - attribute \src "libresoc.v:183360.3-183399.6" - wire width 4 $6\r26__data_o$next[3:0]$11587 - attribute \src "libresoc.v:183290.3-183329.6" - wire width 4 $6\r6__data_o$next[3:0]$11573 - attribute \src "libresoc.v:183053.3-183092.6" - wire width 4 $6\src16__data_o$next[3:0]$11530 - attribute \src "libresoc.v:183150.3-183189.6" - wire width 4 $6\src26__data_o$next[3:0]$11545 - attribute \src "libresoc.v:183220.3-183259.6" - wire width 4 $6\src36__data_o$next[3:0]$11559 - attribute \src "libresoc.v:183036.17-183036.104" - wire $not$libresoc.v:183036$11512_Y - attribute \src "libresoc.v:183037.18-183037.105" - wire $not$libresoc.v:183037$11513_Y - attribute \src "libresoc.v:183038.17-183038.100" - wire $not$libresoc.v:183038$11514_Y - attribute \src "libresoc.v:183039.17-183039.103" - wire $not$libresoc.v:183039$11515_Y - attribute \src "libresoc.v:183040.17-183040.103" - wire $not$libresoc.v:183040$11516_Y + attribute \src "libresoc.v:183108.3-183147.6" + wire width 4 $5\r26__data_o$next[3:0]$11580 + attribute \src "libresoc.v:183038.3-183077.6" + wire width 4 $5\r6__data_o$next[3:0]$11566 + attribute \src "libresoc.v:182801.3-182840.6" + wire width 4 $5\src16__data_o$next[3:0]$11523 + attribute \src "libresoc.v:182898.3-182937.6" + wire width 4 $5\src26__data_o$next[3:0]$11538 + attribute \src "libresoc.v:182968.3-183007.6" + wire width 4 $5\src36__data_o$next[3:0]$11552 + attribute \src "libresoc.v:183108.3-183147.6" + wire width 4 $6\r26__data_o$next[3:0]$11581 + attribute \src "libresoc.v:183038.3-183077.6" + wire width 4 $6\r6__data_o$next[3:0]$11567 + attribute \src "libresoc.v:182801.3-182840.6" + wire width 4 $6\src16__data_o$next[3:0]$11524 + attribute \src "libresoc.v:182898.3-182937.6" + wire width 4 $6\src26__data_o$next[3:0]$11539 + attribute \src "libresoc.v:182968.3-183007.6" + wire width 4 $6\src36__data_o$next[3:0]$11553 + attribute \src "libresoc.v:182784.17-182784.104" + wire $not$libresoc.v:182784$11506_Y + attribute \src "libresoc.v:182785.18-182785.105" + wire $not$libresoc.v:182785$11507_Y + attribute \src "libresoc.v:182786.17-182786.100" + wire $not$libresoc.v:182786$11508_Y + attribute \src "libresoc.v:182787.17-182787.103" + wire $not$libresoc.v:182787$11509_Y + attribute \src "libresoc.v:182788.17-182788.103" + wire $not$libresoc.v:182788$11510_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -341406,9 +341112,9 @@ module \reg_6 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest16__data_i @@ -341418,7 +341124,7 @@ module \reg_6 wire width 4 input 11 \dest26__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest26__wen - attribute \src "libresoc.v:182960.7-182960.15" + attribute \src "libresoc.v:182708.7-182708.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r26__data_o @@ -341469,152 +341175,152 @@ module \reg_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183036$11512 + cell $not $not$libresoc.v:182784$11506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:183036$11512_Y + connect \Y $not$libresoc.v:182784$11506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183037$11513 + cell $not $not$libresoc.v:182785$11507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:183037$11513_Y + connect \Y $not$libresoc.v:182785$11507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183038$11514 + cell $not $not$libresoc.v:182786$11508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:183038$11514_Y + connect \Y $not$libresoc.v:182786$11508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183039$11515 + cell $not $not$libresoc.v:182787$11509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:183039$11515_Y + connect \Y $not$libresoc.v:182787$11509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183040$11516 + cell $not $not$libresoc.v:182788$11510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:183040$11516_Y + connect \Y $not$libresoc.v:182788$11510_Y end - attribute \src "libresoc.v:182960.7-182960.20" - process $proc$libresoc.v:182960$11594 + attribute \src "libresoc.v:182708.7-182708.20" + process $proc$libresoc.v:182708$11588 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182985.13-182985.31" - process $proc$libresoc.v:182985$11595 + attribute \src "libresoc.v:182733.13-182733.31" + process $proc$libresoc.v:182733$11589 assign { } { } assign $1\r26__data_o[3:0] 4'0000 sync always sync init update \r26__data_o $1\r26__data_o[3:0] end - attribute \src "libresoc.v:182992.13-182992.30" - process $proc$libresoc.v:182992$11596 + attribute \src "libresoc.v:182740.13-182740.30" + process $proc$libresoc.v:182740$11590 assign { } { } assign $1\r6__data_o[3:0] 4'0000 sync always sync init update \r6__data_o $1\r6__data_o[3:0] end - attribute \src "libresoc.v:182998.13-182998.25" - process $proc$libresoc.v:182998$11597 + attribute \src "libresoc.v:182746.13-182746.25" + process $proc$libresoc.v:182746$11591 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:183003.13-183003.33" - process $proc$libresoc.v:183003$11598 + attribute \src "libresoc.v:182751.13-182751.33" + process $proc$libresoc.v:182751$11592 assign { } { } assign $1\src16__data_o[3:0] 4'0000 sync always sync init update \src16__data_o $1\src16__data_o[3:0] end - attribute \src "libresoc.v:183010.13-183010.33" - process $proc$libresoc.v:183010$11599 + attribute \src "libresoc.v:182758.13-182758.33" + process $proc$libresoc.v:182758$11593 assign { } { } assign $1\src26__data_o[3:0] 4'0000 sync always sync init update \src26__data_o $1\src26__data_o[3:0] end - attribute \src "libresoc.v:183017.13-183017.33" - process $proc$libresoc.v:183017$11600 + attribute \src "libresoc.v:182765.13-182765.33" + process $proc$libresoc.v:182765$11594 assign { } { } assign $1\src36__data_o[3:0] 4'0000 sync always sync init update \src36__data_o $1\src36__data_o[3:0] end - attribute \src "libresoc.v:183041.3-183042.25" - process $proc$libresoc.v:183041$11517 + attribute \src "libresoc.v:182789.3-182790.25" + process $proc$libresoc.v:182789$11511 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:183043.3-183044.39" - process $proc$libresoc.v:183043$11518 + attribute \src "libresoc.v:182791.3-182792.39" + process $proc$libresoc.v:182791$11512 assign { } { } assign $0\r26__data_o[3:0] \r26__data_o$next sync posedge \coresync_clk update \r26__data_o $0\r26__data_o[3:0] end - attribute \src "libresoc.v:183045.3-183046.37" - process $proc$libresoc.v:183045$11519 + attribute \src "libresoc.v:182793.3-182794.37" + process $proc$libresoc.v:182793$11513 assign { } { } assign $0\r6__data_o[3:0] \r6__data_o$next sync posedge \coresync_clk update \r6__data_o $0\r6__data_o[3:0] end - attribute \src "libresoc.v:183047.3-183048.43" - process $proc$libresoc.v:183047$11520 + attribute \src "libresoc.v:182795.3-182796.43" + process $proc$libresoc.v:182795$11514 assign { } { } assign $0\src36__data_o[3:0] \src36__data_o$next sync posedge \coresync_clk update \src36__data_o $0\src36__data_o[3:0] end - attribute \src "libresoc.v:183049.3-183050.43" - process $proc$libresoc.v:183049$11521 + attribute \src "libresoc.v:182797.3-182798.43" + process $proc$libresoc.v:182797$11515 assign { } { } assign $0\src26__data_o[3:0] \src26__data_o$next sync posedge \coresync_clk update \src26__data_o $0\src26__data_o[3:0] end - attribute \src "libresoc.v:183051.3-183052.43" - process $proc$libresoc.v:183051$11522 + attribute \src "libresoc.v:182799.3-182800.43" + process $proc$libresoc.v:182799$11516 assign { } { } assign $0\src16__data_o[3:0] \src16__data_o$next sync posedge \coresync_clk update \src16__data_o $0\src16__data_o[3:0] end - attribute \src "libresoc.v:183053.3-183092.6" - process $proc$libresoc.v:183053$11523 + attribute \src "libresoc.v:182801.3-182840.6" + process $proc$libresoc.v:182801$11517 assign { } { } assign { } { } assign { } { } - assign $0\src16__data_o$next[3:0]$11524 $6\src16__data_o$next[3:0]$11530 - attribute \src "libresoc.v:183054.5-183054.29" + assign $0\src16__data_o$next[3:0]$11518 $6\src16__data_o$next[3:0]$11524 + attribute \src "libresoc.v:182802.5-182802.29" switch \initial - attribute \src "libresoc.v:183054.9-183054.17" + attribute \src "libresoc.v:182802.9-182802.17" case 1'1 case end @@ -341626,66 +341332,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src16__data_o$next[3:0]$11525 $5\src16__data_o$next[3:0]$11529 + assign $1\src16__data_o$next[3:0]$11519 $5\src16__data_o$next[3:0]$11523 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src16__data_o$next[3:0]$11526 \dest16__data_i + assign $2\src16__data_o$next[3:0]$11520 \dest16__data_i case - assign $2\src16__data_o$next[3:0]$11526 4'0000 + assign $2\src16__data_o$next[3:0]$11520 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src16__data_o$next[3:0]$11527 \dest26__data_i + assign $3\src16__data_o$next[3:0]$11521 \dest26__data_i case - assign $3\src16__data_o$next[3:0]$11527 $2\src16__data_o$next[3:0]$11526 + assign $3\src16__data_o$next[3:0]$11521 $2\src16__data_o$next[3:0]$11520 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src16__data_o$next[3:0]$11528 \w6__data_i + assign $4\src16__data_o$next[3:0]$11522 \w6__data_i case - assign $4\src16__data_o$next[3:0]$11528 $3\src16__data_o$next[3:0]$11527 + assign $4\src16__data_o$next[3:0]$11522 $3\src16__data_o$next[3:0]$11521 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src16__data_o$next[3:0]$11529 \reg + assign $5\src16__data_o$next[3:0]$11523 \reg case - assign $5\src16__data_o$next[3:0]$11529 $4\src16__data_o$next[3:0]$11528 + assign $5\src16__data_o$next[3:0]$11523 $4\src16__data_o$next[3:0]$11522 end case - assign $1\src16__data_o$next[3:0]$11525 4'0000 + assign $1\src16__data_o$next[3:0]$11519 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src16__data_o$next[3:0]$11530 4'0000 + assign $6\src16__data_o$next[3:0]$11524 4'0000 case - assign $6\src16__data_o$next[3:0]$11530 $1\src16__data_o$next[3:0]$11525 + assign $6\src16__data_o$next[3:0]$11524 $1\src16__data_o$next[3:0]$11519 end sync always - update \src16__data_o$next $0\src16__data_o$next[3:0]$11524 + update \src16__data_o$next $0\src16__data_o$next[3:0]$11518 end - attribute \src "libresoc.v:183093.3-183122.6" - process $proc$libresoc.v:183093$11531 + attribute \src "libresoc.v:182841.3-182870.6" + process $proc$libresoc.v:182841$11525 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:183094.5-183094.29" + attribute \src "libresoc.v:182842.5-182842.29" switch \initial - attribute \src "libresoc.v:183094.9-183094.17" + attribute \src "libresoc.v:182842.9-182842.17" case 1'1 case end @@ -341731,17 +341437,17 @@ module \reg_6 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:183123.3-183149.6" - process $proc$libresoc.v:183123$11532 + attribute \src "libresoc.v:182871.3-182897.6" + process $proc$libresoc.v:182871$11526 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11533 $4\reg$next[3:0]$11537 - attribute \src "libresoc.v:183124.5-183124.29" + assign $0\reg$next[3:0]$11527 $4\reg$next[3:0]$11531 + attribute \src "libresoc.v:182872.5-182872.29" switch \initial - attribute \src "libresoc.v:183124.9-183124.17" + attribute \src "libresoc.v:182872.9-182872.17" case 1'1 case end @@ -341750,49 +341456,49 @@ module \reg_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11534 \dest16__data_i + assign $1\reg$next[3:0]$11528 \dest16__data_i case - assign $1\reg$next[3:0]$11534 \reg + assign $1\reg$next[3:0]$11528 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11535 \dest26__data_i + assign $2\reg$next[3:0]$11529 \dest26__data_i case - assign $2\reg$next[3:0]$11535 $1\reg$next[3:0]$11534 + assign $2\reg$next[3:0]$11529 $1\reg$next[3:0]$11528 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11536 \w6__data_i + assign $3\reg$next[3:0]$11530 \w6__data_i case - assign $3\reg$next[3:0]$11536 $2\reg$next[3:0]$11535 + assign $3\reg$next[3:0]$11530 $2\reg$next[3:0]$11529 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11537 4'0000 + assign $4\reg$next[3:0]$11531 4'0000 case - assign $4\reg$next[3:0]$11537 $3\reg$next[3:0]$11536 + assign $4\reg$next[3:0]$11531 $3\reg$next[3:0]$11530 end sync always - update \reg$next $0\reg$next[3:0]$11533 + update \reg$next $0\reg$next[3:0]$11527 end - attribute \src "libresoc.v:183150.3-183189.6" - process $proc$libresoc.v:183150$11538 + attribute \src "libresoc.v:182898.3-182937.6" + process $proc$libresoc.v:182898$11532 assign { } { } assign { } { } assign { } { } - assign $0\src26__data_o$next[3:0]$11539 $6\src26__data_o$next[3:0]$11545 - attribute \src "libresoc.v:183151.5-183151.29" + assign $0\src26__data_o$next[3:0]$11533 $6\src26__data_o$next[3:0]$11539 + attribute \src "libresoc.v:182899.5-182899.29" switch \initial - attribute \src "libresoc.v:183151.9-183151.17" + attribute \src "libresoc.v:182899.9-182899.17" case 1'1 case end @@ -341804,66 +341510,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src26__data_o$next[3:0]$11540 $5\src26__data_o$next[3:0]$11544 + assign $1\src26__data_o$next[3:0]$11534 $5\src26__data_o$next[3:0]$11538 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src26__data_o$next[3:0]$11541 \dest16__data_i + assign $2\src26__data_o$next[3:0]$11535 \dest16__data_i case - assign $2\src26__data_o$next[3:0]$11541 4'0000 + assign $2\src26__data_o$next[3:0]$11535 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src26__data_o$next[3:0]$11542 \dest26__data_i + assign $3\src26__data_o$next[3:0]$11536 \dest26__data_i case - assign $3\src26__data_o$next[3:0]$11542 $2\src26__data_o$next[3:0]$11541 + assign $3\src26__data_o$next[3:0]$11536 $2\src26__data_o$next[3:0]$11535 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src26__data_o$next[3:0]$11543 \w6__data_i + assign $4\src26__data_o$next[3:0]$11537 \w6__data_i case - assign $4\src26__data_o$next[3:0]$11543 $3\src26__data_o$next[3:0]$11542 + assign $4\src26__data_o$next[3:0]$11537 $3\src26__data_o$next[3:0]$11536 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src26__data_o$next[3:0]$11544 \reg + assign $5\src26__data_o$next[3:0]$11538 \reg case - assign $5\src26__data_o$next[3:0]$11544 $4\src26__data_o$next[3:0]$11543 + assign $5\src26__data_o$next[3:0]$11538 $4\src26__data_o$next[3:0]$11537 end case - assign $1\src26__data_o$next[3:0]$11540 4'0000 + assign $1\src26__data_o$next[3:0]$11534 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src26__data_o$next[3:0]$11545 4'0000 + assign $6\src26__data_o$next[3:0]$11539 4'0000 case - assign $6\src26__data_o$next[3:0]$11545 $1\src26__data_o$next[3:0]$11540 + assign $6\src26__data_o$next[3:0]$11539 $1\src26__data_o$next[3:0]$11534 end sync always - update \src26__data_o$next $0\src26__data_o$next[3:0]$11539 + update \src26__data_o$next $0\src26__data_o$next[3:0]$11533 end - attribute \src "libresoc.v:183190.3-183219.6" - process $proc$libresoc.v:183190$11546 + attribute \src "libresoc.v:182938.3-182967.6" + process $proc$libresoc.v:182938$11540 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11547 $1\wr_detect$4[0:0]$11548 - attribute \src "libresoc.v:183191.5-183191.29" + assign $0\wr_detect$4[0:0]$11541 $1\wr_detect$4[0:0]$11542 + attribute \src "libresoc.v:182939.5-182939.29" switch \initial - attribute \src "libresoc.v:183191.9-183191.17" + attribute \src "libresoc.v:182939.9-182939.17" case 1'1 case end @@ -341875,49 +341581,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11548 $4\wr_detect$4[0:0]$11551 + assign $1\wr_detect$4[0:0]$11542 $4\wr_detect$4[0:0]$11545 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11549 1'1 + assign $2\wr_detect$4[0:0]$11543 1'1 case - assign $2\wr_detect$4[0:0]$11549 1'0 + assign $2\wr_detect$4[0:0]$11543 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11550 1'1 + assign $3\wr_detect$4[0:0]$11544 1'1 case - assign $3\wr_detect$4[0:0]$11550 $2\wr_detect$4[0:0]$11549 + assign $3\wr_detect$4[0:0]$11544 $2\wr_detect$4[0:0]$11543 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11551 1'1 + assign $4\wr_detect$4[0:0]$11545 1'1 case - assign $4\wr_detect$4[0:0]$11551 $3\wr_detect$4[0:0]$11550 + assign $4\wr_detect$4[0:0]$11545 $3\wr_detect$4[0:0]$11544 end case - assign $1\wr_detect$4[0:0]$11548 1'0 + assign $1\wr_detect$4[0:0]$11542 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11547 + update \wr_detect$4 $0\wr_detect$4[0:0]$11541 end - attribute \src "libresoc.v:183220.3-183259.6" - process $proc$libresoc.v:183220$11552 + attribute \src "libresoc.v:182968.3-183007.6" + process $proc$libresoc.v:182968$11546 assign { } { } assign { } { } assign { } { } - assign $0\src36__data_o$next[3:0]$11553 $6\src36__data_o$next[3:0]$11559 - attribute \src "libresoc.v:183221.5-183221.29" + assign $0\src36__data_o$next[3:0]$11547 $6\src36__data_o$next[3:0]$11553 + attribute \src "libresoc.v:182969.5-182969.29" switch \initial - attribute \src "libresoc.v:183221.9-183221.17" + attribute \src "libresoc.v:182969.9-182969.17" case 1'1 case end @@ -341929,66 +341635,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src36__data_o$next[3:0]$11554 $5\src36__data_o$next[3:0]$11558 + assign $1\src36__data_o$next[3:0]$11548 $5\src36__data_o$next[3:0]$11552 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src36__data_o$next[3:0]$11555 \dest16__data_i + assign $2\src36__data_o$next[3:0]$11549 \dest16__data_i case - assign $2\src36__data_o$next[3:0]$11555 4'0000 + assign $2\src36__data_o$next[3:0]$11549 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src36__data_o$next[3:0]$11556 \dest26__data_i + assign $3\src36__data_o$next[3:0]$11550 \dest26__data_i case - assign $3\src36__data_o$next[3:0]$11556 $2\src36__data_o$next[3:0]$11555 + assign $3\src36__data_o$next[3:0]$11550 $2\src36__data_o$next[3:0]$11549 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src36__data_o$next[3:0]$11557 \w6__data_i + assign $4\src36__data_o$next[3:0]$11551 \w6__data_i case - assign $4\src36__data_o$next[3:0]$11557 $3\src36__data_o$next[3:0]$11556 + assign $4\src36__data_o$next[3:0]$11551 $3\src36__data_o$next[3:0]$11550 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src36__data_o$next[3:0]$11558 \reg + assign $5\src36__data_o$next[3:0]$11552 \reg case - assign $5\src36__data_o$next[3:0]$11558 $4\src36__data_o$next[3:0]$11557 + assign $5\src36__data_o$next[3:0]$11552 $4\src36__data_o$next[3:0]$11551 end case - assign $1\src36__data_o$next[3:0]$11554 4'0000 + assign $1\src36__data_o$next[3:0]$11548 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src36__data_o$next[3:0]$11559 4'0000 + assign $6\src36__data_o$next[3:0]$11553 4'0000 case - assign $6\src36__data_o$next[3:0]$11559 $1\src36__data_o$next[3:0]$11554 + assign $6\src36__data_o$next[3:0]$11553 $1\src36__data_o$next[3:0]$11548 end sync always - update \src36__data_o$next $0\src36__data_o$next[3:0]$11553 + update \src36__data_o$next $0\src36__data_o$next[3:0]$11547 end - attribute \src "libresoc.v:183260.3-183289.6" - process $proc$libresoc.v:183260$11560 + attribute \src "libresoc.v:183008.3-183037.6" + process $proc$libresoc.v:183008$11554 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11561 $1\wr_detect$7[0:0]$11562 - attribute \src "libresoc.v:183261.5-183261.29" + assign $0\wr_detect$7[0:0]$11555 $1\wr_detect$7[0:0]$11556 + attribute \src "libresoc.v:183009.5-183009.29" switch \initial - attribute \src "libresoc.v:183261.9-183261.17" + attribute \src "libresoc.v:183009.9-183009.17" case 1'1 case end @@ -342000,49 +341706,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11562 $4\wr_detect$7[0:0]$11565 + assign $1\wr_detect$7[0:0]$11556 $4\wr_detect$7[0:0]$11559 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11563 1'1 + assign $2\wr_detect$7[0:0]$11557 1'1 case - assign $2\wr_detect$7[0:0]$11563 1'0 + assign $2\wr_detect$7[0:0]$11557 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11564 1'1 + assign $3\wr_detect$7[0:0]$11558 1'1 case - assign $3\wr_detect$7[0:0]$11564 $2\wr_detect$7[0:0]$11563 + assign $3\wr_detect$7[0:0]$11558 $2\wr_detect$7[0:0]$11557 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11565 1'1 + assign $4\wr_detect$7[0:0]$11559 1'1 case - assign $4\wr_detect$7[0:0]$11565 $3\wr_detect$7[0:0]$11564 + assign $4\wr_detect$7[0:0]$11559 $3\wr_detect$7[0:0]$11558 end case - assign $1\wr_detect$7[0:0]$11562 1'0 + assign $1\wr_detect$7[0:0]$11556 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11561 + update \wr_detect$7 $0\wr_detect$7[0:0]$11555 end - attribute \src "libresoc.v:183290.3-183329.6" - process $proc$libresoc.v:183290$11566 + attribute \src "libresoc.v:183038.3-183077.6" + process $proc$libresoc.v:183038$11560 assign { } { } assign { } { } assign { } { } - assign $0\r6__data_o$next[3:0]$11567 $6\r6__data_o$next[3:0]$11573 - attribute \src "libresoc.v:183291.5-183291.29" + assign $0\r6__data_o$next[3:0]$11561 $6\r6__data_o$next[3:0]$11567 + attribute \src "libresoc.v:183039.5-183039.29" switch \initial - attribute \src "libresoc.v:183291.9-183291.17" + attribute \src "libresoc.v:183039.9-183039.17" case 1'1 case end @@ -342054,66 +341760,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r6__data_o$next[3:0]$11568 $5\r6__data_o$next[3:0]$11572 + assign $1\r6__data_o$next[3:0]$11562 $5\r6__data_o$next[3:0]$11566 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r6__data_o$next[3:0]$11569 \dest16__data_i + assign $2\r6__data_o$next[3:0]$11563 \dest16__data_i case - assign $2\r6__data_o$next[3:0]$11569 4'0000 + assign $2\r6__data_o$next[3:0]$11563 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r6__data_o$next[3:0]$11570 \dest26__data_i + assign $3\r6__data_o$next[3:0]$11564 \dest26__data_i case - assign $3\r6__data_o$next[3:0]$11570 $2\r6__data_o$next[3:0]$11569 + assign $3\r6__data_o$next[3:0]$11564 $2\r6__data_o$next[3:0]$11563 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r6__data_o$next[3:0]$11571 \w6__data_i + assign $4\r6__data_o$next[3:0]$11565 \w6__data_i case - assign $4\r6__data_o$next[3:0]$11571 $3\r6__data_o$next[3:0]$11570 + assign $4\r6__data_o$next[3:0]$11565 $3\r6__data_o$next[3:0]$11564 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r6__data_o$next[3:0]$11572 \reg + assign $5\r6__data_o$next[3:0]$11566 \reg case - assign $5\r6__data_o$next[3:0]$11572 $4\r6__data_o$next[3:0]$11571 + assign $5\r6__data_o$next[3:0]$11566 $4\r6__data_o$next[3:0]$11565 end case - assign $1\r6__data_o$next[3:0]$11568 4'0000 + assign $1\r6__data_o$next[3:0]$11562 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r6__data_o$next[3:0]$11573 4'0000 + assign $6\r6__data_o$next[3:0]$11567 4'0000 case - assign $6\r6__data_o$next[3:0]$11573 $1\r6__data_o$next[3:0]$11568 + assign $6\r6__data_o$next[3:0]$11567 $1\r6__data_o$next[3:0]$11562 end sync always - update \r6__data_o$next $0\r6__data_o$next[3:0]$11567 + update \r6__data_o$next $0\r6__data_o$next[3:0]$11561 end - attribute \src "libresoc.v:183330.3-183359.6" - process $proc$libresoc.v:183330$11574 + attribute \src "libresoc.v:183078.3-183107.6" + process $proc$libresoc.v:183078$11568 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11575 $1\wr_detect$10[0:0]$11576 - attribute \src "libresoc.v:183331.5-183331.29" + assign $0\wr_detect$10[0:0]$11569 $1\wr_detect$10[0:0]$11570 + attribute \src "libresoc.v:183079.5-183079.29" switch \initial - attribute \src "libresoc.v:183331.9-183331.17" + attribute \src "libresoc.v:183079.9-183079.17" case 1'1 case end @@ -342125,49 +341831,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11576 $4\wr_detect$10[0:0]$11579 + assign $1\wr_detect$10[0:0]$11570 $4\wr_detect$10[0:0]$11573 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11577 1'1 + assign $2\wr_detect$10[0:0]$11571 1'1 case - assign $2\wr_detect$10[0:0]$11577 1'0 + assign $2\wr_detect$10[0:0]$11571 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11578 1'1 + assign $3\wr_detect$10[0:0]$11572 1'1 case - assign $3\wr_detect$10[0:0]$11578 $2\wr_detect$10[0:0]$11577 + assign $3\wr_detect$10[0:0]$11572 $2\wr_detect$10[0:0]$11571 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11579 1'1 + assign $4\wr_detect$10[0:0]$11573 1'1 case - assign $4\wr_detect$10[0:0]$11579 $3\wr_detect$10[0:0]$11578 + assign $4\wr_detect$10[0:0]$11573 $3\wr_detect$10[0:0]$11572 end case - assign $1\wr_detect$10[0:0]$11576 1'0 + assign $1\wr_detect$10[0:0]$11570 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11575 + update \wr_detect$10 $0\wr_detect$10[0:0]$11569 end - attribute \src "libresoc.v:183360.3-183399.6" - process $proc$libresoc.v:183360$11580 + attribute \src "libresoc.v:183108.3-183147.6" + process $proc$libresoc.v:183108$11574 assign { } { } assign { } { } assign { } { } - assign $0\r26__data_o$next[3:0]$11581 $6\r26__data_o$next[3:0]$11587 - attribute \src "libresoc.v:183361.5-183361.29" + assign $0\r26__data_o$next[3:0]$11575 $6\r26__data_o$next[3:0]$11581 + attribute \src "libresoc.v:183109.5-183109.29" switch \initial - attribute \src "libresoc.v:183361.9-183361.17" + attribute \src "libresoc.v:183109.9-183109.17" case 1'1 case end @@ -342179,66 +341885,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r26__data_o$next[3:0]$11582 $5\r26__data_o$next[3:0]$11586 + assign $1\r26__data_o$next[3:0]$11576 $5\r26__data_o$next[3:0]$11580 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r26__data_o$next[3:0]$11583 \dest16__data_i + assign $2\r26__data_o$next[3:0]$11577 \dest16__data_i case - assign $2\r26__data_o$next[3:0]$11583 4'0000 + assign $2\r26__data_o$next[3:0]$11577 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r26__data_o$next[3:0]$11584 \dest26__data_i + assign $3\r26__data_o$next[3:0]$11578 \dest26__data_i case - assign $3\r26__data_o$next[3:0]$11584 $2\r26__data_o$next[3:0]$11583 + assign $3\r26__data_o$next[3:0]$11578 $2\r26__data_o$next[3:0]$11577 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r26__data_o$next[3:0]$11585 \w6__data_i + assign $4\r26__data_o$next[3:0]$11579 \w6__data_i case - assign $4\r26__data_o$next[3:0]$11585 $3\r26__data_o$next[3:0]$11584 + assign $4\r26__data_o$next[3:0]$11579 $3\r26__data_o$next[3:0]$11578 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r26__data_o$next[3:0]$11586 \reg + assign $5\r26__data_o$next[3:0]$11580 \reg case - assign $5\r26__data_o$next[3:0]$11586 $4\r26__data_o$next[3:0]$11585 + assign $5\r26__data_o$next[3:0]$11580 $4\r26__data_o$next[3:0]$11579 end case - assign $1\r26__data_o$next[3:0]$11582 4'0000 + assign $1\r26__data_o$next[3:0]$11576 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r26__data_o$next[3:0]$11587 4'0000 + assign $6\r26__data_o$next[3:0]$11581 4'0000 case - assign $6\r26__data_o$next[3:0]$11587 $1\r26__data_o$next[3:0]$11582 + assign $6\r26__data_o$next[3:0]$11581 $1\r26__data_o$next[3:0]$11576 end sync always - update \r26__data_o$next $0\r26__data_o$next[3:0]$11581 + update \r26__data_o$next $0\r26__data_o$next[3:0]$11575 end - attribute \src "libresoc.v:183400.3-183429.6" - process $proc$libresoc.v:183400$11588 + attribute \src "libresoc.v:183148.3-183177.6" + process $proc$libresoc.v:183148$11582 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11589 $1\wr_detect$13[0:0]$11590 - attribute \src "libresoc.v:183401.5-183401.29" + assign $0\wr_detect$13[0:0]$11583 $1\wr_detect$13[0:0]$11584 + attribute \src "libresoc.v:183149.5-183149.29" switch \initial - attribute \src "libresoc.v:183401.9-183401.17" + attribute \src "libresoc.v:183149.9-183149.17" case 1'1 case end @@ -342250,217 +341956,217 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11590 $4\wr_detect$13[0:0]$11593 + assign $1\wr_detect$13[0:0]$11584 $4\wr_detect$13[0:0]$11587 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11591 1'1 + assign $2\wr_detect$13[0:0]$11585 1'1 case - assign $2\wr_detect$13[0:0]$11591 1'0 + assign $2\wr_detect$13[0:0]$11585 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11592 1'1 + assign $3\wr_detect$13[0:0]$11586 1'1 case - assign $3\wr_detect$13[0:0]$11592 $2\wr_detect$13[0:0]$11591 + assign $3\wr_detect$13[0:0]$11586 $2\wr_detect$13[0:0]$11585 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11593 1'1 + assign $4\wr_detect$13[0:0]$11587 1'1 case - assign $4\wr_detect$13[0:0]$11593 $3\wr_detect$13[0:0]$11592 + assign $4\wr_detect$13[0:0]$11587 $3\wr_detect$13[0:0]$11586 end case - assign $1\wr_detect$13[0:0]$11590 1'0 + assign $1\wr_detect$13[0:0]$11584 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11589 + update \wr_detect$13 $0\wr_detect$13[0:0]$11583 end - connect \$9 $not$libresoc.v:183036$11512_Y - connect \$12 $not$libresoc.v:183037$11513_Y - connect \$1 $not$libresoc.v:183038$11514_Y - connect \$3 $not$libresoc.v:183039$11515_Y - connect \$6 $not$libresoc.v:183040$11516_Y + connect \$9 $not$libresoc.v:182784$11506_Y + connect \$12 $not$libresoc.v:182785$11507_Y + connect \$1 $not$libresoc.v:182786$11508_Y + connect \$3 $not$libresoc.v:182787$11509_Y + connect \$6 $not$libresoc.v:182788$11510_Y end -attribute \src "libresoc.v:183434.1-183905.10" +attribute \src "libresoc.v:183182.1-183653.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" attribute \generator "nMigen" module \reg_7 - attribute \src "libresoc.v:183435.7-183435.20" + attribute \src "libresoc.v:183183.7-183183.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183835.3-183874.6" - wire width 4 $0\r27__data_o$next[3:0]$11670 - attribute \src "libresoc.v:183518.3-183519.39" + attribute \src "libresoc.v:183583.3-183622.6" + wire width 4 $0\r27__data_o$next[3:0]$11664 + attribute \src "libresoc.v:183266.3-183267.39" wire width 4 $0\r27__data_o[3:0] - attribute \src "libresoc.v:183765.3-183804.6" - wire width 4 $0\r7__data_o$next[3:0]$11656 - attribute \src "libresoc.v:183520.3-183521.37" + attribute \src "libresoc.v:183513.3-183552.6" + wire width 4 $0\r7__data_o$next[3:0]$11650 + attribute \src "libresoc.v:183268.3-183269.37" wire width 4 $0\r7__data_o[3:0] - attribute \src "libresoc.v:183598.3-183624.6" - wire width 4 $0\reg$next[3:0]$11622 - attribute \src "libresoc.v:183516.3-183517.25" + attribute \src "libresoc.v:183346.3-183372.6" + wire width 4 $0\reg$next[3:0]$11616 + attribute \src "libresoc.v:183264.3-183265.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:183528.3-183567.6" - wire width 4 $0\src17__data_o$next[3:0]$11613 - attribute \src "libresoc.v:183526.3-183527.43" + attribute \src "libresoc.v:183276.3-183315.6" + wire width 4 $0\src17__data_o$next[3:0]$11607 + attribute \src "libresoc.v:183274.3-183275.43" wire width 4 $0\src17__data_o[3:0] - attribute \src "libresoc.v:183625.3-183664.6" - wire width 4 $0\src27__data_o$next[3:0]$11628 - attribute \src "libresoc.v:183524.3-183525.43" + attribute \src "libresoc.v:183373.3-183412.6" + wire width 4 $0\src27__data_o$next[3:0]$11622 + attribute \src "libresoc.v:183272.3-183273.43" wire width 4 $0\src27__data_o[3:0] - attribute \src "libresoc.v:183695.3-183734.6" - wire width 4 $0\src37__data_o$next[3:0]$11642 - attribute \src "libresoc.v:183522.3-183523.43" + attribute \src "libresoc.v:183443.3-183482.6" + wire width 4 $0\src37__data_o$next[3:0]$11636 + attribute \src "libresoc.v:183270.3-183271.43" wire width 4 $0\src37__data_o[3:0] - attribute \src "libresoc.v:183805.3-183834.6" - wire $0\wr_detect$10[0:0]$11664 - attribute \src "libresoc.v:183875.3-183904.6" - wire $0\wr_detect$13[0:0]$11678 - attribute \src "libresoc.v:183665.3-183694.6" - wire $0\wr_detect$4[0:0]$11636 - attribute \src "libresoc.v:183735.3-183764.6" - wire $0\wr_detect$7[0:0]$11650 - attribute \src "libresoc.v:183568.3-183597.6" + attribute \src "libresoc.v:183553.3-183582.6" + wire $0\wr_detect$10[0:0]$11658 + attribute \src "libresoc.v:183623.3-183652.6" + wire $0\wr_detect$13[0:0]$11672 + attribute \src "libresoc.v:183413.3-183442.6" + wire $0\wr_detect$4[0:0]$11630 + attribute \src "libresoc.v:183483.3-183512.6" + wire $0\wr_detect$7[0:0]$11644 + attribute \src "libresoc.v:183316.3-183345.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:183835.3-183874.6" - wire width 4 $1\r27__data_o$next[3:0]$11671 - attribute \src "libresoc.v:183460.13-183460.31" + attribute \src "libresoc.v:183583.3-183622.6" + wire width 4 $1\r27__data_o$next[3:0]$11665 + attribute \src "libresoc.v:183208.13-183208.31" wire width 4 $1\r27__data_o[3:0] - attribute \src "libresoc.v:183765.3-183804.6" - wire width 4 $1\r7__data_o$next[3:0]$11657 - attribute \src "libresoc.v:183467.13-183467.30" + attribute \src "libresoc.v:183513.3-183552.6" + wire width 4 $1\r7__data_o$next[3:0]$11651 + attribute \src "libresoc.v:183215.13-183215.30" wire width 4 $1\r7__data_o[3:0] - attribute \src "libresoc.v:183598.3-183624.6" - wire width 4 $1\reg$next[3:0]$11623 - attribute \src "libresoc.v:183473.13-183473.25" + attribute \src "libresoc.v:183346.3-183372.6" + wire width 4 $1\reg$next[3:0]$11617 + attribute \src "libresoc.v:183221.13-183221.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:183528.3-183567.6" - wire width 4 $1\src17__data_o$next[3:0]$11614 - attribute \src "libresoc.v:183478.13-183478.33" + attribute \src "libresoc.v:183276.3-183315.6" + wire width 4 $1\src17__data_o$next[3:0]$11608 + attribute \src "libresoc.v:183226.13-183226.33" wire width 4 $1\src17__data_o[3:0] - attribute \src "libresoc.v:183625.3-183664.6" - wire width 4 $1\src27__data_o$next[3:0]$11629 - attribute \src "libresoc.v:183485.13-183485.33" + attribute \src "libresoc.v:183373.3-183412.6" + wire width 4 $1\src27__data_o$next[3:0]$11623 + attribute \src "libresoc.v:183233.13-183233.33" wire width 4 $1\src27__data_o[3:0] - attribute \src "libresoc.v:183695.3-183734.6" - wire width 4 $1\src37__data_o$next[3:0]$11643 - attribute \src "libresoc.v:183492.13-183492.33" + attribute \src "libresoc.v:183443.3-183482.6" + wire width 4 $1\src37__data_o$next[3:0]$11637 + attribute \src "libresoc.v:183240.13-183240.33" wire width 4 $1\src37__data_o[3:0] - attribute \src "libresoc.v:183805.3-183834.6" - wire $1\wr_detect$10[0:0]$11665 - attribute \src "libresoc.v:183875.3-183904.6" - wire $1\wr_detect$13[0:0]$11679 - attribute \src "libresoc.v:183665.3-183694.6" - wire $1\wr_detect$4[0:0]$11637 - attribute \src "libresoc.v:183735.3-183764.6" - wire $1\wr_detect$7[0:0]$11651 - attribute \src "libresoc.v:183568.3-183597.6" + attribute \src "libresoc.v:183553.3-183582.6" + wire $1\wr_detect$10[0:0]$11659 + attribute \src "libresoc.v:183623.3-183652.6" + wire $1\wr_detect$13[0:0]$11673 + attribute \src "libresoc.v:183413.3-183442.6" + wire $1\wr_detect$4[0:0]$11631 + attribute \src "libresoc.v:183483.3-183512.6" + wire $1\wr_detect$7[0:0]$11645 + attribute \src "libresoc.v:183316.3-183345.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:183835.3-183874.6" - wire width 4 $2\r27__data_o$next[3:0]$11672 - attribute \src "libresoc.v:183765.3-183804.6" - wire width 4 $2\r7__data_o$next[3:0]$11658 - attribute \src "libresoc.v:183598.3-183624.6" - wire width 4 $2\reg$next[3:0]$11624 - attribute \src "libresoc.v:183528.3-183567.6" - wire width 4 $2\src17__data_o$next[3:0]$11615 - attribute \src "libresoc.v:183625.3-183664.6" - wire width 4 $2\src27__data_o$next[3:0]$11630 - attribute \src "libresoc.v:183695.3-183734.6" - wire width 4 $2\src37__data_o$next[3:0]$11644 - attribute \src "libresoc.v:183805.3-183834.6" - wire $2\wr_detect$10[0:0]$11666 - attribute \src "libresoc.v:183875.3-183904.6" - wire $2\wr_detect$13[0:0]$11680 - attribute \src "libresoc.v:183665.3-183694.6" - wire $2\wr_detect$4[0:0]$11638 - attribute \src "libresoc.v:183735.3-183764.6" - wire $2\wr_detect$7[0:0]$11652 - attribute \src "libresoc.v:183568.3-183597.6" + attribute \src "libresoc.v:183583.3-183622.6" + wire width 4 $2\r27__data_o$next[3:0]$11666 + attribute \src "libresoc.v:183513.3-183552.6" + wire width 4 $2\r7__data_o$next[3:0]$11652 + attribute \src "libresoc.v:183346.3-183372.6" + wire width 4 $2\reg$next[3:0]$11618 + attribute \src "libresoc.v:183276.3-183315.6" + wire width 4 $2\src17__data_o$next[3:0]$11609 + attribute \src "libresoc.v:183373.3-183412.6" + wire width 4 $2\src27__data_o$next[3:0]$11624 + attribute \src "libresoc.v:183443.3-183482.6" + wire width 4 $2\src37__data_o$next[3:0]$11638 + attribute \src "libresoc.v:183553.3-183582.6" + wire $2\wr_detect$10[0:0]$11660 + attribute \src "libresoc.v:183623.3-183652.6" + wire $2\wr_detect$13[0:0]$11674 + attribute \src "libresoc.v:183413.3-183442.6" + wire $2\wr_detect$4[0:0]$11632 + attribute \src "libresoc.v:183483.3-183512.6" + wire $2\wr_detect$7[0:0]$11646 + attribute \src "libresoc.v:183316.3-183345.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:183835.3-183874.6" - wire width 4 $3\r27__data_o$next[3:0]$11673 - attribute \src "libresoc.v:183765.3-183804.6" - wire width 4 $3\r7__data_o$next[3:0]$11659 - attribute \src "libresoc.v:183598.3-183624.6" - wire width 4 $3\reg$next[3:0]$11625 - attribute \src "libresoc.v:183528.3-183567.6" - wire width 4 $3\src17__data_o$next[3:0]$11616 - attribute \src "libresoc.v:183625.3-183664.6" - wire width 4 $3\src27__data_o$next[3:0]$11631 - attribute \src "libresoc.v:183695.3-183734.6" - wire width 4 $3\src37__data_o$next[3:0]$11645 - attribute \src "libresoc.v:183805.3-183834.6" - wire $3\wr_detect$10[0:0]$11667 - attribute \src "libresoc.v:183875.3-183904.6" - wire $3\wr_detect$13[0:0]$11681 - attribute \src "libresoc.v:183665.3-183694.6" - wire $3\wr_detect$4[0:0]$11639 - attribute \src "libresoc.v:183735.3-183764.6" - wire $3\wr_detect$7[0:0]$11653 - attribute \src "libresoc.v:183568.3-183597.6" + attribute \src "libresoc.v:183583.3-183622.6" + wire width 4 $3\r27__data_o$next[3:0]$11667 + attribute \src "libresoc.v:183513.3-183552.6" + wire width 4 $3\r7__data_o$next[3:0]$11653 + attribute \src "libresoc.v:183346.3-183372.6" + wire width 4 $3\reg$next[3:0]$11619 + attribute \src "libresoc.v:183276.3-183315.6" + wire width 4 $3\src17__data_o$next[3:0]$11610 + attribute \src "libresoc.v:183373.3-183412.6" + wire width 4 $3\src27__data_o$next[3:0]$11625 + attribute \src "libresoc.v:183443.3-183482.6" + wire width 4 $3\src37__data_o$next[3:0]$11639 + attribute \src "libresoc.v:183553.3-183582.6" + wire $3\wr_detect$10[0:0]$11661 + attribute \src "libresoc.v:183623.3-183652.6" + wire $3\wr_detect$13[0:0]$11675 + attribute \src "libresoc.v:183413.3-183442.6" + wire $3\wr_detect$4[0:0]$11633 + attribute \src "libresoc.v:183483.3-183512.6" + wire $3\wr_detect$7[0:0]$11647 + attribute \src "libresoc.v:183316.3-183345.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:183835.3-183874.6" - wire width 4 $4\r27__data_o$next[3:0]$11674 - attribute \src "libresoc.v:183765.3-183804.6" - wire width 4 $4\r7__data_o$next[3:0]$11660 - attribute \src "libresoc.v:183598.3-183624.6" - wire width 4 $4\reg$next[3:0]$11626 - attribute \src "libresoc.v:183528.3-183567.6" - wire width 4 $4\src17__data_o$next[3:0]$11617 - attribute \src "libresoc.v:183625.3-183664.6" - wire width 4 $4\src27__data_o$next[3:0]$11632 - attribute \src "libresoc.v:183695.3-183734.6" - wire width 4 $4\src37__data_o$next[3:0]$11646 - attribute \src "libresoc.v:183805.3-183834.6" - wire $4\wr_detect$10[0:0]$11668 - attribute \src "libresoc.v:183875.3-183904.6" - wire $4\wr_detect$13[0:0]$11682 - attribute \src "libresoc.v:183665.3-183694.6" - wire $4\wr_detect$4[0:0]$11640 - attribute \src "libresoc.v:183735.3-183764.6" - wire $4\wr_detect$7[0:0]$11654 - attribute \src "libresoc.v:183568.3-183597.6" + attribute \src "libresoc.v:183583.3-183622.6" + wire width 4 $4\r27__data_o$next[3:0]$11668 + attribute \src "libresoc.v:183513.3-183552.6" + wire width 4 $4\r7__data_o$next[3:0]$11654 + attribute \src "libresoc.v:183346.3-183372.6" + wire width 4 $4\reg$next[3:0]$11620 + attribute \src "libresoc.v:183276.3-183315.6" + wire width 4 $4\src17__data_o$next[3:0]$11611 + attribute \src "libresoc.v:183373.3-183412.6" + wire width 4 $4\src27__data_o$next[3:0]$11626 + attribute \src "libresoc.v:183443.3-183482.6" + wire width 4 $4\src37__data_o$next[3:0]$11640 + attribute \src "libresoc.v:183553.3-183582.6" + wire $4\wr_detect$10[0:0]$11662 + attribute \src "libresoc.v:183623.3-183652.6" + wire $4\wr_detect$13[0:0]$11676 + attribute \src "libresoc.v:183413.3-183442.6" + wire $4\wr_detect$4[0:0]$11634 + attribute \src "libresoc.v:183483.3-183512.6" + wire $4\wr_detect$7[0:0]$11648 + attribute \src "libresoc.v:183316.3-183345.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:183835.3-183874.6" - wire width 4 $5\r27__data_o$next[3:0]$11675 - attribute \src "libresoc.v:183765.3-183804.6" - wire width 4 $5\r7__data_o$next[3:0]$11661 - attribute \src "libresoc.v:183528.3-183567.6" - wire width 4 $5\src17__data_o$next[3:0]$11618 - attribute \src "libresoc.v:183625.3-183664.6" - wire width 4 $5\src27__data_o$next[3:0]$11633 - attribute \src "libresoc.v:183695.3-183734.6" - wire width 4 $5\src37__data_o$next[3:0]$11647 - attribute \src "libresoc.v:183835.3-183874.6" - wire width 4 $6\r27__data_o$next[3:0]$11676 - attribute \src "libresoc.v:183765.3-183804.6" - wire width 4 $6\r7__data_o$next[3:0]$11662 - attribute \src "libresoc.v:183528.3-183567.6" - wire width 4 $6\src17__data_o$next[3:0]$11619 - attribute \src "libresoc.v:183625.3-183664.6" - wire width 4 $6\src27__data_o$next[3:0]$11634 - attribute \src "libresoc.v:183695.3-183734.6" - wire width 4 $6\src37__data_o$next[3:0]$11648 - attribute \src "libresoc.v:183511.17-183511.104" - wire $not$libresoc.v:183511$11601_Y - attribute \src "libresoc.v:183512.18-183512.105" - wire $not$libresoc.v:183512$11602_Y - attribute \src "libresoc.v:183513.17-183513.100" - wire $not$libresoc.v:183513$11603_Y - attribute \src "libresoc.v:183514.17-183514.103" - wire $not$libresoc.v:183514$11604_Y - attribute \src "libresoc.v:183515.17-183515.103" - wire $not$libresoc.v:183515$11605_Y + attribute \src "libresoc.v:183583.3-183622.6" + wire width 4 $5\r27__data_o$next[3:0]$11669 + attribute \src "libresoc.v:183513.3-183552.6" + wire width 4 $5\r7__data_o$next[3:0]$11655 + attribute \src "libresoc.v:183276.3-183315.6" + wire width 4 $5\src17__data_o$next[3:0]$11612 + attribute \src "libresoc.v:183373.3-183412.6" + wire width 4 $5\src27__data_o$next[3:0]$11627 + attribute \src "libresoc.v:183443.3-183482.6" + wire width 4 $5\src37__data_o$next[3:0]$11641 + attribute \src "libresoc.v:183583.3-183622.6" + wire width 4 $6\r27__data_o$next[3:0]$11670 + attribute \src "libresoc.v:183513.3-183552.6" + wire width 4 $6\r7__data_o$next[3:0]$11656 + attribute \src "libresoc.v:183276.3-183315.6" + wire width 4 $6\src17__data_o$next[3:0]$11613 + attribute \src "libresoc.v:183373.3-183412.6" + wire width 4 $6\src27__data_o$next[3:0]$11628 + attribute \src "libresoc.v:183443.3-183482.6" + wire width 4 $6\src37__data_o$next[3:0]$11642 + attribute \src "libresoc.v:183259.17-183259.104" + wire $not$libresoc.v:183259$11595_Y + attribute \src "libresoc.v:183260.18-183260.105" + wire $not$libresoc.v:183260$11596_Y + attribute \src "libresoc.v:183261.17-183261.100" + wire $not$libresoc.v:183261$11597_Y + attribute \src "libresoc.v:183262.17-183262.103" + wire $not$libresoc.v:183262$11598_Y + attribute \src "libresoc.v:183263.17-183263.103" + wire $not$libresoc.v:183263$11599_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -342471,9 +342177,9 @@ module \reg_7 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest17__data_i @@ -342483,7 +342189,7 @@ module \reg_7 wire width 4 input 11 \dest27__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest27__wen - attribute \src "libresoc.v:183435.7-183435.15" + attribute \src "libresoc.v:183183.7-183183.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r27__data_o @@ -342534,152 +342240,152 @@ module \reg_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183511$11601 + cell $not $not$libresoc.v:183259$11595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:183511$11601_Y + connect \Y $not$libresoc.v:183259$11595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183512$11602 + cell $not $not$libresoc.v:183260$11596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:183512$11602_Y + connect \Y $not$libresoc.v:183260$11596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183513$11603 + cell $not $not$libresoc.v:183261$11597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:183513$11603_Y + connect \Y $not$libresoc.v:183261$11597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183514$11604 + cell $not $not$libresoc.v:183262$11598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:183514$11604_Y + connect \Y $not$libresoc.v:183262$11598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183515$11605 + cell $not $not$libresoc.v:183263$11599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:183515$11605_Y + connect \Y $not$libresoc.v:183263$11599_Y end - attribute \src "libresoc.v:183435.7-183435.20" - process $proc$libresoc.v:183435$11683 + attribute \src "libresoc.v:183183.7-183183.20" + process $proc$libresoc.v:183183$11677 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183460.13-183460.31" - process $proc$libresoc.v:183460$11684 + attribute \src "libresoc.v:183208.13-183208.31" + process $proc$libresoc.v:183208$11678 assign { } { } assign $1\r27__data_o[3:0] 4'0000 sync always sync init update \r27__data_o $1\r27__data_o[3:0] end - attribute \src "libresoc.v:183467.13-183467.30" - process $proc$libresoc.v:183467$11685 + attribute \src "libresoc.v:183215.13-183215.30" + process $proc$libresoc.v:183215$11679 assign { } { } assign $1\r7__data_o[3:0] 4'0000 sync always sync init update \r7__data_o $1\r7__data_o[3:0] end - attribute \src "libresoc.v:183473.13-183473.25" - process $proc$libresoc.v:183473$11686 + attribute \src "libresoc.v:183221.13-183221.25" + process $proc$libresoc.v:183221$11680 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:183478.13-183478.33" - process $proc$libresoc.v:183478$11687 + attribute \src "libresoc.v:183226.13-183226.33" + process $proc$libresoc.v:183226$11681 assign { } { } assign $1\src17__data_o[3:0] 4'0000 sync always sync init update \src17__data_o $1\src17__data_o[3:0] end - attribute \src "libresoc.v:183485.13-183485.33" - process $proc$libresoc.v:183485$11688 + attribute \src "libresoc.v:183233.13-183233.33" + process $proc$libresoc.v:183233$11682 assign { } { } assign $1\src27__data_o[3:0] 4'0000 sync always sync init update \src27__data_o $1\src27__data_o[3:0] end - attribute \src "libresoc.v:183492.13-183492.33" - process $proc$libresoc.v:183492$11689 + attribute \src "libresoc.v:183240.13-183240.33" + process $proc$libresoc.v:183240$11683 assign { } { } assign $1\src37__data_o[3:0] 4'0000 sync always sync init update \src37__data_o $1\src37__data_o[3:0] end - attribute \src "libresoc.v:183516.3-183517.25" - process $proc$libresoc.v:183516$11606 + attribute \src "libresoc.v:183264.3-183265.25" + process $proc$libresoc.v:183264$11600 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:183518.3-183519.39" - process $proc$libresoc.v:183518$11607 + attribute \src "libresoc.v:183266.3-183267.39" + process $proc$libresoc.v:183266$11601 assign { } { } assign $0\r27__data_o[3:0] \r27__data_o$next sync posedge \coresync_clk update \r27__data_o $0\r27__data_o[3:0] end - attribute \src "libresoc.v:183520.3-183521.37" - process $proc$libresoc.v:183520$11608 + attribute \src "libresoc.v:183268.3-183269.37" + process $proc$libresoc.v:183268$11602 assign { } { } assign $0\r7__data_o[3:0] \r7__data_o$next sync posedge \coresync_clk update \r7__data_o $0\r7__data_o[3:0] end - attribute \src "libresoc.v:183522.3-183523.43" - process $proc$libresoc.v:183522$11609 + attribute \src "libresoc.v:183270.3-183271.43" + process $proc$libresoc.v:183270$11603 assign { } { } assign $0\src37__data_o[3:0] \src37__data_o$next sync posedge \coresync_clk update \src37__data_o $0\src37__data_o[3:0] end - attribute \src "libresoc.v:183524.3-183525.43" - process $proc$libresoc.v:183524$11610 + attribute \src "libresoc.v:183272.3-183273.43" + process $proc$libresoc.v:183272$11604 assign { } { } assign $0\src27__data_o[3:0] \src27__data_o$next sync posedge \coresync_clk update \src27__data_o $0\src27__data_o[3:0] end - attribute \src "libresoc.v:183526.3-183527.43" - process $proc$libresoc.v:183526$11611 + attribute \src "libresoc.v:183274.3-183275.43" + process $proc$libresoc.v:183274$11605 assign { } { } assign $0\src17__data_o[3:0] \src17__data_o$next sync posedge \coresync_clk update \src17__data_o $0\src17__data_o[3:0] end - attribute \src "libresoc.v:183528.3-183567.6" - process $proc$libresoc.v:183528$11612 + attribute \src "libresoc.v:183276.3-183315.6" + process $proc$libresoc.v:183276$11606 assign { } { } assign { } { } assign { } { } - assign $0\src17__data_o$next[3:0]$11613 $6\src17__data_o$next[3:0]$11619 - attribute \src "libresoc.v:183529.5-183529.29" + assign $0\src17__data_o$next[3:0]$11607 $6\src17__data_o$next[3:0]$11613 + attribute \src "libresoc.v:183277.5-183277.29" switch \initial - attribute \src "libresoc.v:183529.9-183529.17" + attribute \src "libresoc.v:183277.9-183277.17" case 1'1 case end @@ -342691,66 +342397,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src17__data_o$next[3:0]$11614 $5\src17__data_o$next[3:0]$11618 + assign $1\src17__data_o$next[3:0]$11608 $5\src17__data_o$next[3:0]$11612 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src17__data_o$next[3:0]$11615 \dest17__data_i + assign $2\src17__data_o$next[3:0]$11609 \dest17__data_i case - assign $2\src17__data_o$next[3:0]$11615 4'0000 + assign $2\src17__data_o$next[3:0]$11609 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src17__data_o$next[3:0]$11616 \dest27__data_i + assign $3\src17__data_o$next[3:0]$11610 \dest27__data_i case - assign $3\src17__data_o$next[3:0]$11616 $2\src17__data_o$next[3:0]$11615 + assign $3\src17__data_o$next[3:0]$11610 $2\src17__data_o$next[3:0]$11609 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src17__data_o$next[3:0]$11617 \w7__data_i + assign $4\src17__data_o$next[3:0]$11611 \w7__data_i case - assign $4\src17__data_o$next[3:0]$11617 $3\src17__data_o$next[3:0]$11616 + assign $4\src17__data_o$next[3:0]$11611 $3\src17__data_o$next[3:0]$11610 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src17__data_o$next[3:0]$11618 \reg + assign $5\src17__data_o$next[3:0]$11612 \reg case - assign $5\src17__data_o$next[3:0]$11618 $4\src17__data_o$next[3:0]$11617 + assign $5\src17__data_o$next[3:0]$11612 $4\src17__data_o$next[3:0]$11611 end case - assign $1\src17__data_o$next[3:0]$11614 4'0000 + assign $1\src17__data_o$next[3:0]$11608 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src17__data_o$next[3:0]$11619 4'0000 + assign $6\src17__data_o$next[3:0]$11613 4'0000 case - assign $6\src17__data_o$next[3:0]$11619 $1\src17__data_o$next[3:0]$11614 + assign $6\src17__data_o$next[3:0]$11613 $1\src17__data_o$next[3:0]$11608 end sync always - update \src17__data_o$next $0\src17__data_o$next[3:0]$11613 + update \src17__data_o$next $0\src17__data_o$next[3:0]$11607 end - attribute \src "libresoc.v:183568.3-183597.6" - process $proc$libresoc.v:183568$11620 + attribute \src "libresoc.v:183316.3-183345.6" + process $proc$libresoc.v:183316$11614 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:183569.5-183569.29" + attribute \src "libresoc.v:183317.5-183317.29" switch \initial - attribute \src "libresoc.v:183569.9-183569.17" + attribute \src "libresoc.v:183317.9-183317.17" case 1'1 case end @@ -342796,17 +342502,17 @@ module \reg_7 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:183598.3-183624.6" - process $proc$libresoc.v:183598$11621 + attribute \src "libresoc.v:183346.3-183372.6" + process $proc$libresoc.v:183346$11615 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11622 $4\reg$next[3:0]$11626 - attribute \src "libresoc.v:183599.5-183599.29" + assign $0\reg$next[3:0]$11616 $4\reg$next[3:0]$11620 + attribute \src "libresoc.v:183347.5-183347.29" switch \initial - attribute \src "libresoc.v:183599.9-183599.17" + attribute \src "libresoc.v:183347.9-183347.17" case 1'1 case end @@ -342815,49 +342521,49 @@ module \reg_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11623 \dest17__data_i + assign $1\reg$next[3:0]$11617 \dest17__data_i case - assign $1\reg$next[3:0]$11623 \reg + assign $1\reg$next[3:0]$11617 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11624 \dest27__data_i + assign $2\reg$next[3:0]$11618 \dest27__data_i case - assign $2\reg$next[3:0]$11624 $1\reg$next[3:0]$11623 + assign $2\reg$next[3:0]$11618 $1\reg$next[3:0]$11617 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11625 \w7__data_i + assign $3\reg$next[3:0]$11619 \w7__data_i case - assign $3\reg$next[3:0]$11625 $2\reg$next[3:0]$11624 + assign $3\reg$next[3:0]$11619 $2\reg$next[3:0]$11618 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11626 4'0000 + assign $4\reg$next[3:0]$11620 4'0000 case - assign $4\reg$next[3:0]$11626 $3\reg$next[3:0]$11625 + assign $4\reg$next[3:0]$11620 $3\reg$next[3:0]$11619 end sync always - update \reg$next $0\reg$next[3:0]$11622 + update \reg$next $0\reg$next[3:0]$11616 end - attribute \src "libresoc.v:183625.3-183664.6" - process $proc$libresoc.v:183625$11627 + attribute \src "libresoc.v:183373.3-183412.6" + process $proc$libresoc.v:183373$11621 assign { } { } assign { } { } assign { } { } - assign $0\src27__data_o$next[3:0]$11628 $6\src27__data_o$next[3:0]$11634 - attribute \src "libresoc.v:183626.5-183626.29" + assign $0\src27__data_o$next[3:0]$11622 $6\src27__data_o$next[3:0]$11628 + attribute \src "libresoc.v:183374.5-183374.29" switch \initial - attribute \src "libresoc.v:183626.9-183626.17" + attribute \src "libresoc.v:183374.9-183374.17" case 1'1 case end @@ -342869,66 +342575,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src27__data_o$next[3:0]$11629 $5\src27__data_o$next[3:0]$11633 + assign $1\src27__data_o$next[3:0]$11623 $5\src27__data_o$next[3:0]$11627 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src27__data_o$next[3:0]$11630 \dest17__data_i + assign $2\src27__data_o$next[3:0]$11624 \dest17__data_i case - assign $2\src27__data_o$next[3:0]$11630 4'0000 + assign $2\src27__data_o$next[3:0]$11624 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src27__data_o$next[3:0]$11631 \dest27__data_i + assign $3\src27__data_o$next[3:0]$11625 \dest27__data_i case - assign $3\src27__data_o$next[3:0]$11631 $2\src27__data_o$next[3:0]$11630 + assign $3\src27__data_o$next[3:0]$11625 $2\src27__data_o$next[3:0]$11624 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src27__data_o$next[3:0]$11632 \w7__data_i + assign $4\src27__data_o$next[3:0]$11626 \w7__data_i case - assign $4\src27__data_o$next[3:0]$11632 $3\src27__data_o$next[3:0]$11631 + assign $4\src27__data_o$next[3:0]$11626 $3\src27__data_o$next[3:0]$11625 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src27__data_o$next[3:0]$11633 \reg + assign $5\src27__data_o$next[3:0]$11627 \reg case - assign $5\src27__data_o$next[3:0]$11633 $4\src27__data_o$next[3:0]$11632 + assign $5\src27__data_o$next[3:0]$11627 $4\src27__data_o$next[3:0]$11626 end case - assign $1\src27__data_o$next[3:0]$11629 4'0000 + assign $1\src27__data_o$next[3:0]$11623 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src27__data_o$next[3:0]$11634 4'0000 + assign $6\src27__data_o$next[3:0]$11628 4'0000 case - assign $6\src27__data_o$next[3:0]$11634 $1\src27__data_o$next[3:0]$11629 + assign $6\src27__data_o$next[3:0]$11628 $1\src27__data_o$next[3:0]$11623 end sync always - update \src27__data_o$next $0\src27__data_o$next[3:0]$11628 + update \src27__data_o$next $0\src27__data_o$next[3:0]$11622 end - attribute \src "libresoc.v:183665.3-183694.6" - process $proc$libresoc.v:183665$11635 + attribute \src "libresoc.v:183413.3-183442.6" + process $proc$libresoc.v:183413$11629 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11636 $1\wr_detect$4[0:0]$11637 - attribute \src "libresoc.v:183666.5-183666.29" + assign $0\wr_detect$4[0:0]$11630 $1\wr_detect$4[0:0]$11631 + attribute \src "libresoc.v:183414.5-183414.29" switch \initial - attribute \src "libresoc.v:183666.9-183666.17" + attribute \src "libresoc.v:183414.9-183414.17" case 1'1 case end @@ -342940,49 +342646,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11637 $4\wr_detect$4[0:0]$11640 + assign $1\wr_detect$4[0:0]$11631 $4\wr_detect$4[0:0]$11634 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11638 1'1 + assign $2\wr_detect$4[0:0]$11632 1'1 case - assign $2\wr_detect$4[0:0]$11638 1'0 + assign $2\wr_detect$4[0:0]$11632 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11639 1'1 + assign $3\wr_detect$4[0:0]$11633 1'1 case - assign $3\wr_detect$4[0:0]$11639 $2\wr_detect$4[0:0]$11638 + assign $3\wr_detect$4[0:0]$11633 $2\wr_detect$4[0:0]$11632 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11640 1'1 + assign $4\wr_detect$4[0:0]$11634 1'1 case - assign $4\wr_detect$4[0:0]$11640 $3\wr_detect$4[0:0]$11639 + assign $4\wr_detect$4[0:0]$11634 $3\wr_detect$4[0:0]$11633 end case - assign $1\wr_detect$4[0:0]$11637 1'0 + assign $1\wr_detect$4[0:0]$11631 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11636 + update \wr_detect$4 $0\wr_detect$4[0:0]$11630 end - attribute \src "libresoc.v:183695.3-183734.6" - process $proc$libresoc.v:183695$11641 + attribute \src "libresoc.v:183443.3-183482.6" + process $proc$libresoc.v:183443$11635 assign { } { } assign { } { } assign { } { } - assign $0\src37__data_o$next[3:0]$11642 $6\src37__data_o$next[3:0]$11648 - attribute \src "libresoc.v:183696.5-183696.29" + assign $0\src37__data_o$next[3:0]$11636 $6\src37__data_o$next[3:0]$11642 + attribute \src "libresoc.v:183444.5-183444.29" switch \initial - attribute \src "libresoc.v:183696.9-183696.17" + attribute \src "libresoc.v:183444.9-183444.17" case 1'1 case end @@ -342994,66 +342700,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src37__data_o$next[3:0]$11643 $5\src37__data_o$next[3:0]$11647 + assign $1\src37__data_o$next[3:0]$11637 $5\src37__data_o$next[3:0]$11641 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src37__data_o$next[3:0]$11644 \dest17__data_i + assign $2\src37__data_o$next[3:0]$11638 \dest17__data_i case - assign $2\src37__data_o$next[3:0]$11644 4'0000 + assign $2\src37__data_o$next[3:0]$11638 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src37__data_o$next[3:0]$11645 \dest27__data_i + assign $3\src37__data_o$next[3:0]$11639 \dest27__data_i case - assign $3\src37__data_o$next[3:0]$11645 $2\src37__data_o$next[3:0]$11644 + assign $3\src37__data_o$next[3:0]$11639 $2\src37__data_o$next[3:0]$11638 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src37__data_o$next[3:0]$11646 \w7__data_i + assign $4\src37__data_o$next[3:0]$11640 \w7__data_i case - assign $4\src37__data_o$next[3:0]$11646 $3\src37__data_o$next[3:0]$11645 + assign $4\src37__data_o$next[3:0]$11640 $3\src37__data_o$next[3:0]$11639 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src37__data_o$next[3:0]$11647 \reg + assign $5\src37__data_o$next[3:0]$11641 \reg case - assign $5\src37__data_o$next[3:0]$11647 $4\src37__data_o$next[3:0]$11646 + assign $5\src37__data_o$next[3:0]$11641 $4\src37__data_o$next[3:0]$11640 end case - assign $1\src37__data_o$next[3:0]$11643 4'0000 + assign $1\src37__data_o$next[3:0]$11637 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src37__data_o$next[3:0]$11648 4'0000 + assign $6\src37__data_o$next[3:0]$11642 4'0000 case - assign $6\src37__data_o$next[3:0]$11648 $1\src37__data_o$next[3:0]$11643 + assign $6\src37__data_o$next[3:0]$11642 $1\src37__data_o$next[3:0]$11637 end sync always - update \src37__data_o$next $0\src37__data_o$next[3:0]$11642 + update \src37__data_o$next $0\src37__data_o$next[3:0]$11636 end - attribute \src "libresoc.v:183735.3-183764.6" - process $proc$libresoc.v:183735$11649 + attribute \src "libresoc.v:183483.3-183512.6" + process $proc$libresoc.v:183483$11643 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11650 $1\wr_detect$7[0:0]$11651 - attribute \src "libresoc.v:183736.5-183736.29" + assign $0\wr_detect$7[0:0]$11644 $1\wr_detect$7[0:0]$11645 + attribute \src "libresoc.v:183484.5-183484.29" switch \initial - attribute \src "libresoc.v:183736.9-183736.17" + attribute \src "libresoc.v:183484.9-183484.17" case 1'1 case end @@ -343065,49 +342771,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11651 $4\wr_detect$7[0:0]$11654 + assign $1\wr_detect$7[0:0]$11645 $4\wr_detect$7[0:0]$11648 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11652 1'1 + assign $2\wr_detect$7[0:0]$11646 1'1 case - assign $2\wr_detect$7[0:0]$11652 1'0 + assign $2\wr_detect$7[0:0]$11646 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11653 1'1 + assign $3\wr_detect$7[0:0]$11647 1'1 case - assign $3\wr_detect$7[0:0]$11653 $2\wr_detect$7[0:0]$11652 + assign $3\wr_detect$7[0:0]$11647 $2\wr_detect$7[0:0]$11646 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11654 1'1 + assign $4\wr_detect$7[0:0]$11648 1'1 case - assign $4\wr_detect$7[0:0]$11654 $3\wr_detect$7[0:0]$11653 + assign $4\wr_detect$7[0:0]$11648 $3\wr_detect$7[0:0]$11647 end case - assign $1\wr_detect$7[0:0]$11651 1'0 + assign $1\wr_detect$7[0:0]$11645 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11650 + update \wr_detect$7 $0\wr_detect$7[0:0]$11644 end - attribute \src "libresoc.v:183765.3-183804.6" - process $proc$libresoc.v:183765$11655 + attribute \src "libresoc.v:183513.3-183552.6" + process $proc$libresoc.v:183513$11649 assign { } { } assign { } { } assign { } { } - assign $0\r7__data_o$next[3:0]$11656 $6\r7__data_o$next[3:0]$11662 - attribute \src "libresoc.v:183766.5-183766.29" + assign $0\r7__data_o$next[3:0]$11650 $6\r7__data_o$next[3:0]$11656 + attribute \src "libresoc.v:183514.5-183514.29" switch \initial - attribute \src "libresoc.v:183766.9-183766.17" + attribute \src "libresoc.v:183514.9-183514.17" case 1'1 case end @@ -343119,66 +342825,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r7__data_o$next[3:0]$11657 $5\r7__data_o$next[3:0]$11661 + assign $1\r7__data_o$next[3:0]$11651 $5\r7__data_o$next[3:0]$11655 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r7__data_o$next[3:0]$11658 \dest17__data_i + assign $2\r7__data_o$next[3:0]$11652 \dest17__data_i case - assign $2\r7__data_o$next[3:0]$11658 4'0000 + assign $2\r7__data_o$next[3:0]$11652 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r7__data_o$next[3:0]$11659 \dest27__data_i + assign $3\r7__data_o$next[3:0]$11653 \dest27__data_i case - assign $3\r7__data_o$next[3:0]$11659 $2\r7__data_o$next[3:0]$11658 + assign $3\r7__data_o$next[3:0]$11653 $2\r7__data_o$next[3:0]$11652 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r7__data_o$next[3:0]$11660 \w7__data_i + assign $4\r7__data_o$next[3:0]$11654 \w7__data_i case - assign $4\r7__data_o$next[3:0]$11660 $3\r7__data_o$next[3:0]$11659 + assign $4\r7__data_o$next[3:0]$11654 $3\r7__data_o$next[3:0]$11653 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r7__data_o$next[3:0]$11661 \reg + assign $5\r7__data_o$next[3:0]$11655 \reg case - assign $5\r7__data_o$next[3:0]$11661 $4\r7__data_o$next[3:0]$11660 + assign $5\r7__data_o$next[3:0]$11655 $4\r7__data_o$next[3:0]$11654 end case - assign $1\r7__data_o$next[3:0]$11657 4'0000 + assign $1\r7__data_o$next[3:0]$11651 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r7__data_o$next[3:0]$11662 4'0000 + assign $6\r7__data_o$next[3:0]$11656 4'0000 case - assign $6\r7__data_o$next[3:0]$11662 $1\r7__data_o$next[3:0]$11657 + assign $6\r7__data_o$next[3:0]$11656 $1\r7__data_o$next[3:0]$11651 end sync always - update \r7__data_o$next $0\r7__data_o$next[3:0]$11656 + update \r7__data_o$next $0\r7__data_o$next[3:0]$11650 end - attribute \src "libresoc.v:183805.3-183834.6" - process $proc$libresoc.v:183805$11663 + attribute \src "libresoc.v:183553.3-183582.6" + process $proc$libresoc.v:183553$11657 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11664 $1\wr_detect$10[0:0]$11665 - attribute \src "libresoc.v:183806.5-183806.29" + assign $0\wr_detect$10[0:0]$11658 $1\wr_detect$10[0:0]$11659 + attribute \src "libresoc.v:183554.5-183554.29" switch \initial - attribute \src "libresoc.v:183806.9-183806.17" + attribute \src "libresoc.v:183554.9-183554.17" case 1'1 case end @@ -343190,49 +342896,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11665 $4\wr_detect$10[0:0]$11668 + assign $1\wr_detect$10[0:0]$11659 $4\wr_detect$10[0:0]$11662 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11666 1'1 + assign $2\wr_detect$10[0:0]$11660 1'1 case - assign $2\wr_detect$10[0:0]$11666 1'0 + assign $2\wr_detect$10[0:0]$11660 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11667 1'1 + assign $3\wr_detect$10[0:0]$11661 1'1 case - assign $3\wr_detect$10[0:0]$11667 $2\wr_detect$10[0:0]$11666 + assign $3\wr_detect$10[0:0]$11661 $2\wr_detect$10[0:0]$11660 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11668 1'1 + assign $4\wr_detect$10[0:0]$11662 1'1 case - assign $4\wr_detect$10[0:0]$11668 $3\wr_detect$10[0:0]$11667 + assign $4\wr_detect$10[0:0]$11662 $3\wr_detect$10[0:0]$11661 end case - assign $1\wr_detect$10[0:0]$11665 1'0 + assign $1\wr_detect$10[0:0]$11659 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11664 + update \wr_detect$10 $0\wr_detect$10[0:0]$11658 end - attribute \src "libresoc.v:183835.3-183874.6" - process $proc$libresoc.v:183835$11669 + attribute \src "libresoc.v:183583.3-183622.6" + process $proc$libresoc.v:183583$11663 assign { } { } assign { } { } assign { } { } - assign $0\r27__data_o$next[3:0]$11670 $6\r27__data_o$next[3:0]$11676 - attribute \src "libresoc.v:183836.5-183836.29" + assign $0\r27__data_o$next[3:0]$11664 $6\r27__data_o$next[3:0]$11670 + attribute \src "libresoc.v:183584.5-183584.29" switch \initial - attribute \src "libresoc.v:183836.9-183836.17" + attribute \src "libresoc.v:183584.9-183584.17" case 1'1 case end @@ -343244,66 +342950,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r27__data_o$next[3:0]$11671 $5\r27__data_o$next[3:0]$11675 + assign $1\r27__data_o$next[3:0]$11665 $5\r27__data_o$next[3:0]$11669 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r27__data_o$next[3:0]$11672 \dest17__data_i + assign $2\r27__data_o$next[3:0]$11666 \dest17__data_i case - assign $2\r27__data_o$next[3:0]$11672 4'0000 + assign $2\r27__data_o$next[3:0]$11666 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r27__data_o$next[3:0]$11673 \dest27__data_i + assign $3\r27__data_o$next[3:0]$11667 \dest27__data_i case - assign $3\r27__data_o$next[3:0]$11673 $2\r27__data_o$next[3:0]$11672 + assign $3\r27__data_o$next[3:0]$11667 $2\r27__data_o$next[3:0]$11666 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r27__data_o$next[3:0]$11674 \w7__data_i + assign $4\r27__data_o$next[3:0]$11668 \w7__data_i case - assign $4\r27__data_o$next[3:0]$11674 $3\r27__data_o$next[3:0]$11673 + assign $4\r27__data_o$next[3:0]$11668 $3\r27__data_o$next[3:0]$11667 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r27__data_o$next[3:0]$11675 \reg + assign $5\r27__data_o$next[3:0]$11669 \reg case - assign $5\r27__data_o$next[3:0]$11675 $4\r27__data_o$next[3:0]$11674 + assign $5\r27__data_o$next[3:0]$11669 $4\r27__data_o$next[3:0]$11668 end case - assign $1\r27__data_o$next[3:0]$11671 4'0000 + assign $1\r27__data_o$next[3:0]$11665 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r27__data_o$next[3:0]$11676 4'0000 + assign $6\r27__data_o$next[3:0]$11670 4'0000 case - assign $6\r27__data_o$next[3:0]$11676 $1\r27__data_o$next[3:0]$11671 + assign $6\r27__data_o$next[3:0]$11670 $1\r27__data_o$next[3:0]$11665 end sync always - update \r27__data_o$next $0\r27__data_o$next[3:0]$11670 + update \r27__data_o$next $0\r27__data_o$next[3:0]$11664 end - attribute \src "libresoc.v:183875.3-183904.6" - process $proc$libresoc.v:183875$11677 + attribute \src "libresoc.v:183623.3-183652.6" + process $proc$libresoc.v:183623$11671 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11678 $1\wr_detect$13[0:0]$11679 - attribute \src "libresoc.v:183876.5-183876.29" + assign $0\wr_detect$13[0:0]$11672 $1\wr_detect$13[0:0]$11673 + attribute \src "libresoc.v:183624.5-183624.29" switch \initial - attribute \src "libresoc.v:183876.9-183876.17" + attribute \src "libresoc.v:183624.9-183624.17" case 1'1 case end @@ -343315,77 +343021,77 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11679 $4\wr_detect$13[0:0]$11682 + assign $1\wr_detect$13[0:0]$11673 $4\wr_detect$13[0:0]$11676 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11680 1'1 + assign $2\wr_detect$13[0:0]$11674 1'1 case - assign $2\wr_detect$13[0:0]$11680 1'0 + assign $2\wr_detect$13[0:0]$11674 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11681 1'1 + assign $3\wr_detect$13[0:0]$11675 1'1 case - assign $3\wr_detect$13[0:0]$11681 $2\wr_detect$13[0:0]$11680 + assign $3\wr_detect$13[0:0]$11675 $2\wr_detect$13[0:0]$11674 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11682 1'1 + assign $4\wr_detect$13[0:0]$11676 1'1 case - assign $4\wr_detect$13[0:0]$11682 $3\wr_detect$13[0:0]$11681 + assign $4\wr_detect$13[0:0]$11676 $3\wr_detect$13[0:0]$11675 end case - assign $1\wr_detect$13[0:0]$11679 1'0 + assign $1\wr_detect$13[0:0]$11673 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11678 + update \wr_detect$13 $0\wr_detect$13[0:0]$11672 end - connect \$9 $not$libresoc.v:183511$11601_Y - connect \$12 $not$libresoc.v:183512$11602_Y - connect \$1 $not$libresoc.v:183513$11603_Y - connect \$3 $not$libresoc.v:183514$11604_Y - connect \$6 $not$libresoc.v:183515$11605_Y + connect \$9 $not$libresoc.v:183259$11595_Y + connect \$12 $not$libresoc.v:183260$11596_Y + connect \$1 $not$libresoc.v:183261$11597_Y + connect \$3 $not$libresoc.v:183262$11598_Y + connect \$6 $not$libresoc.v:183263$11599_Y end -attribute \src "libresoc.v:183909.1-183967.10" +attribute \src "libresoc.v:183657.1-183715.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" attribute \generator "nMigen" module \req_l - attribute \src "libresoc.v:183910.7-183910.20" + attribute \src "libresoc.v:183658.7-183658.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183955.3-183963.6" - wire width 5 $0\q_int$next[4:0]$11700 - attribute \src "libresoc.v:183953.3-183954.27" + attribute \src "libresoc.v:183703.3-183711.6" + wire width 5 $0\q_int$next[4:0]$11694 + attribute \src "libresoc.v:183701.3-183702.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:183955.3-183963.6" - wire width 5 $1\q_int$next[4:0]$11701 - attribute \src "libresoc.v:183932.13-183932.26" + attribute \src "libresoc.v:183703.3-183711.6" + wire width 5 $1\q_int$next[4:0]$11695 + attribute \src "libresoc.v:183680.13-183680.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:183945.17-183945.96" - wire width 5 $and$libresoc.v:183945$11690_Y - attribute \src "libresoc.v:183950.17-183950.96" - wire width 5 $and$libresoc.v:183950$11695_Y - attribute \src "libresoc.v:183947.18-183947.93" - wire width 5 $not$libresoc.v:183947$11692_Y - attribute \src "libresoc.v:183949.17-183949.92" - wire width 5 $not$libresoc.v:183949$11694_Y - attribute \src "libresoc.v:183952.17-183952.92" - wire width 5 $not$libresoc.v:183952$11697_Y - attribute \src "libresoc.v:183946.18-183946.98" - wire width 5 $or$libresoc.v:183946$11691_Y - attribute \src "libresoc.v:183948.18-183948.99" - wire width 5 $or$libresoc.v:183948$11693_Y - attribute \src "libresoc.v:183951.17-183951.97" - wire width 5 $or$libresoc.v:183951$11696_Y + attribute \src "libresoc.v:183693.17-183693.96" + wire width 5 $and$libresoc.v:183693$11684_Y + attribute \src "libresoc.v:183698.17-183698.96" + wire width 5 $and$libresoc.v:183698$11689_Y + attribute \src "libresoc.v:183695.18-183695.93" + wire width 5 $not$libresoc.v:183695$11686_Y + attribute \src "libresoc.v:183697.17-183697.92" + wire width 5 $not$libresoc.v:183697$11688_Y + attribute \src "libresoc.v:183700.17-183700.92" + wire width 5 $not$libresoc.v:183700$11691_Y + attribute \src "libresoc.v:183694.18-183694.98" + wire width 5 $or$libresoc.v:183694$11685_Y + attribute \src "libresoc.v:183696.18-183696.99" + wire width 5 $or$libresoc.v:183696$11687_Y + attribute \src "libresoc.v:183699.17-183699.97" + wire width 5 $or$libresoc.v:183699$11690_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -343402,11 +343108,11 @@ module \req_l wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:183910.7-183910.15" + attribute \src "libresoc.v:183658.7-183658.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -343423,7 +343129,7 @@ module \req_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183945$11690 + cell $and $and$libresoc.v:183693$11684 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -343431,10 +343137,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183945$11690_Y + connect \Y $and$libresoc.v:183693$11684_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183950$11695 + cell $and $and$libresoc.v:183698$11689 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -343442,34 +343148,34 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183950$11695_Y + connect \Y $and$libresoc.v:183698$11689_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183947$11692 + cell $not $not$libresoc.v:183695$11686 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:183947$11692_Y + connect \Y $not$libresoc.v:183695$11686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183949$11694 + cell $not $not$libresoc.v:183697$11688 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:183949$11694_Y + connect \Y $not$libresoc.v:183697$11688_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183952$11697 + cell $not $not$libresoc.v:183700$11691 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:183952$11697_Y + connect \Y $not$libresoc.v:183700$11691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183946$11691 + cell $or $or$libresoc.v:183694$11685 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -343477,10 +343183,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183946$11691_Y + connect \Y $or$libresoc.v:183694$11685_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183948$11693 + cell $or $or$libresoc.v:183696$11687 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -343488,10 +343194,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183948$11693_Y + connect \Y $or$libresoc.v:183696$11687_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183951$11696 + cell $or $or$libresoc.v:183699$11690 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -343499,39 +343205,39 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183951$11696_Y + connect \Y $or$libresoc.v:183699$11690_Y end - attribute \src "libresoc.v:183910.7-183910.20" - process $proc$libresoc.v:183910$11702 + attribute \src "libresoc.v:183658.7-183658.20" + process $proc$libresoc.v:183658$11696 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183932.13-183932.26" - process $proc$libresoc.v:183932$11703 + attribute \src "libresoc.v:183680.13-183680.26" + process $proc$libresoc.v:183680$11697 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:183953.3-183954.27" - process $proc$libresoc.v:183953$11698 + attribute \src "libresoc.v:183701.3-183702.27" + process $proc$libresoc.v:183701$11692 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:183955.3-183963.6" - process $proc$libresoc.v:183955$11699 + attribute \src "libresoc.v:183703.3-183711.6" + process $proc$libresoc.v:183703$11693 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11700 $1\q_int$next[4:0]$11701 - attribute \src "libresoc.v:183956.5-183956.29" + assign $0\q_int$next[4:0]$11694 $1\q_int$next[4:0]$11695 + attribute \src "libresoc.v:183704.5-183704.29" switch \initial - attribute \src "libresoc.v:183956.9-183956.17" + attribute \src "libresoc.v:183704.9-183704.17" case 1'1 case end @@ -343540,56 +343246,56 @@ module \req_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11701 5'00000 + assign $1\q_int$next[4:0]$11695 5'00000 case - assign $1\q_int$next[4:0]$11701 \$5 + assign $1\q_int$next[4:0]$11695 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11700 + update \q_int$next $0\q_int$next[4:0]$11694 end - connect \$9 $and$libresoc.v:183945$11690_Y - connect \$11 $or$libresoc.v:183946$11691_Y - connect \$13 $not$libresoc.v:183947$11692_Y - connect \$15 $or$libresoc.v:183948$11693_Y - connect \$1 $not$libresoc.v:183949$11694_Y - connect \$3 $and$libresoc.v:183950$11695_Y - connect \$5 $or$libresoc.v:183951$11696_Y - connect \$7 $not$libresoc.v:183952$11697_Y + connect \$9 $and$libresoc.v:183693$11684_Y + connect \$11 $or$libresoc.v:183694$11685_Y + connect \$13 $not$libresoc.v:183695$11686_Y + connect \$15 $or$libresoc.v:183696$11687_Y + connect \$1 $not$libresoc.v:183697$11688_Y + connect \$3 $and$libresoc.v:183698$11689_Y + connect \$5 $or$libresoc.v:183699$11690_Y + connect \$7 $not$libresoc.v:183700$11691_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183971.1-184029.10" +attribute \src "libresoc.v:183719.1-183777.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" attribute \generator "nMigen" module \req_l$103 - attribute \src "libresoc.v:183972.7-183972.20" + attribute \src "libresoc.v:183720.7-183720.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184017.3-184025.6" - wire width 4 $0\q_int$next[3:0]$11714 - attribute \src "libresoc.v:184015.3-184016.27" + attribute \src "libresoc.v:183765.3-183773.6" + wire width 4 $0\q_int$next[3:0]$11708 + attribute \src "libresoc.v:183763.3-183764.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:184017.3-184025.6" - wire width 4 $1\q_int$next[3:0]$11715 - attribute \src "libresoc.v:183994.13-183994.25" + attribute \src "libresoc.v:183765.3-183773.6" + wire width 4 $1\q_int$next[3:0]$11709 + attribute \src "libresoc.v:183742.13-183742.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:184007.17-184007.96" - wire width 4 $and$libresoc.v:184007$11704_Y - attribute \src "libresoc.v:184012.17-184012.96" - wire width 4 $and$libresoc.v:184012$11709_Y - attribute \src "libresoc.v:184009.18-184009.93" - wire width 4 $not$libresoc.v:184009$11706_Y - attribute \src "libresoc.v:184011.17-184011.92" - wire width 4 $not$libresoc.v:184011$11708_Y - attribute \src "libresoc.v:184014.17-184014.92" - wire width 4 $not$libresoc.v:184014$11711_Y - attribute \src "libresoc.v:184008.18-184008.98" - wire width 4 $or$libresoc.v:184008$11705_Y - attribute \src "libresoc.v:184010.18-184010.99" - wire width 4 $or$libresoc.v:184010$11707_Y - attribute \src "libresoc.v:184013.17-184013.97" - wire width 4 $or$libresoc.v:184013$11710_Y + attribute \src "libresoc.v:183755.17-183755.96" + wire width 4 $and$libresoc.v:183755$11698_Y + attribute \src "libresoc.v:183760.17-183760.96" + wire width 4 $and$libresoc.v:183760$11703_Y + attribute \src "libresoc.v:183757.18-183757.93" + wire width 4 $not$libresoc.v:183757$11700_Y + attribute \src "libresoc.v:183759.17-183759.92" + wire width 4 $not$libresoc.v:183759$11702_Y + attribute \src "libresoc.v:183762.17-183762.92" + wire width 4 $not$libresoc.v:183762$11705_Y + attribute \src "libresoc.v:183756.18-183756.98" + wire width 4 $or$libresoc.v:183756$11699_Y + attribute \src "libresoc.v:183758.18-183758.99" + wire width 4 $or$libresoc.v:183758$11701_Y + attribute \src "libresoc.v:183761.17-183761.97" + wire width 4 $or$libresoc.v:183761$11704_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -343606,11 +343312,11 @@ module \req_l$103 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:183972.7-183972.15" + attribute \src "libresoc.v:183720.7-183720.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -343627,7 +343333,7 @@ module \req_l$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184007$11704 + cell $and $and$libresoc.v:183755$11698 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -343635,10 +343341,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184007$11704_Y + connect \Y $and$libresoc.v:183755$11698_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184012$11709 + cell $and $and$libresoc.v:183760$11703 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -343646,34 +343352,34 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184012$11709_Y + connect \Y $and$libresoc.v:183760$11703_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184009$11706 + cell $not $not$libresoc.v:183757$11700 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:184009$11706_Y + connect \Y $not$libresoc.v:183757$11700_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184011$11708 + cell $not $not$libresoc.v:183759$11702 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:184011$11708_Y + connect \Y $not$libresoc.v:183759$11702_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184014$11711 + cell $not $not$libresoc.v:183762$11705 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:184014$11711_Y + connect \Y $not$libresoc.v:183762$11705_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184008$11705 + cell $or $or$libresoc.v:183756$11699 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -343681,10 +343387,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184008$11705_Y + connect \Y $or$libresoc.v:183756$11699_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184010$11707 + cell $or $or$libresoc.v:183758$11701 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -343692,10 +343398,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184010$11707_Y + connect \Y $or$libresoc.v:183758$11701_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184013$11710 + cell $or $or$libresoc.v:183761$11704 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -343703,39 +343409,39 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184013$11710_Y + connect \Y $or$libresoc.v:183761$11704_Y end - attribute \src "libresoc.v:183972.7-183972.20" - process $proc$libresoc.v:183972$11716 + attribute \src "libresoc.v:183720.7-183720.20" + process $proc$libresoc.v:183720$11710 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183994.13-183994.25" - process $proc$libresoc.v:183994$11717 + attribute \src "libresoc.v:183742.13-183742.25" + process $proc$libresoc.v:183742$11711 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:184015.3-184016.27" - process $proc$libresoc.v:184015$11712 + attribute \src "libresoc.v:183763.3-183764.27" + process $proc$libresoc.v:183763$11706 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:184017.3-184025.6" - process $proc$libresoc.v:184017$11713 + attribute \src "libresoc.v:183765.3-183773.6" + process $proc$libresoc.v:183765$11707 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11714 $1\q_int$next[3:0]$11715 - attribute \src "libresoc.v:184018.5-184018.29" + assign $0\q_int$next[3:0]$11708 $1\q_int$next[3:0]$11709 + attribute \src "libresoc.v:183766.5-183766.29" switch \initial - attribute \src "libresoc.v:184018.9-184018.17" + attribute \src "libresoc.v:183766.9-183766.17" case 1'1 case end @@ -343744,56 +343450,56 @@ module \req_l$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11715 4'0000 + assign $1\q_int$next[3:0]$11709 4'0000 case - assign $1\q_int$next[3:0]$11715 \$5 + assign $1\q_int$next[3:0]$11709 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11714 + update \q_int$next $0\q_int$next[3:0]$11708 end - connect \$9 $and$libresoc.v:184007$11704_Y - connect \$11 $or$libresoc.v:184008$11705_Y - connect \$13 $not$libresoc.v:184009$11706_Y - connect \$15 $or$libresoc.v:184010$11707_Y - connect \$1 $not$libresoc.v:184011$11708_Y - connect \$3 $and$libresoc.v:184012$11709_Y - connect \$5 $or$libresoc.v:184013$11710_Y - connect \$7 $not$libresoc.v:184014$11711_Y + connect \$9 $and$libresoc.v:183755$11698_Y + connect \$11 $or$libresoc.v:183756$11699_Y + connect \$13 $not$libresoc.v:183757$11700_Y + connect \$15 $or$libresoc.v:183758$11701_Y + connect \$1 $not$libresoc.v:183759$11702_Y + connect \$3 $and$libresoc.v:183760$11703_Y + connect \$5 $or$libresoc.v:183761$11704_Y + connect \$7 $not$libresoc.v:183762$11705_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184033.1-184091.10" +attribute \src "libresoc.v:183781.1-183839.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" attribute \generator "nMigen" module \req_l$12 - attribute \src "libresoc.v:184034.7-184034.20" + attribute \src "libresoc.v:183782.7-183782.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184079.3-184087.6" - wire width 3 $0\q_int$next[2:0]$11728 - attribute \src "libresoc.v:184077.3-184078.27" + attribute \src "libresoc.v:183827.3-183835.6" + wire width 3 $0\q_int$next[2:0]$11722 + attribute \src "libresoc.v:183825.3-183826.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:184079.3-184087.6" - wire width 3 $1\q_int$next[2:0]$11729 - attribute \src "libresoc.v:184056.13-184056.25" + attribute \src "libresoc.v:183827.3-183835.6" + wire width 3 $1\q_int$next[2:0]$11723 + attribute \src "libresoc.v:183804.13-183804.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:184069.17-184069.96" - wire width 3 $and$libresoc.v:184069$11718_Y - attribute \src "libresoc.v:184074.17-184074.96" - wire width 3 $and$libresoc.v:184074$11723_Y - attribute \src "libresoc.v:184071.18-184071.93" - wire width 3 $not$libresoc.v:184071$11720_Y - attribute \src "libresoc.v:184073.17-184073.92" - wire width 3 $not$libresoc.v:184073$11722_Y - attribute \src "libresoc.v:184076.17-184076.92" - wire width 3 $not$libresoc.v:184076$11725_Y - attribute \src "libresoc.v:184070.18-184070.98" - wire width 3 $or$libresoc.v:184070$11719_Y - attribute \src "libresoc.v:184072.18-184072.99" - wire width 3 $or$libresoc.v:184072$11721_Y - attribute \src "libresoc.v:184075.17-184075.97" - wire width 3 $or$libresoc.v:184075$11724_Y + attribute \src "libresoc.v:183817.17-183817.96" + wire width 3 $and$libresoc.v:183817$11712_Y + attribute \src "libresoc.v:183822.17-183822.96" + wire width 3 $and$libresoc.v:183822$11717_Y + attribute \src "libresoc.v:183819.18-183819.93" + wire width 3 $not$libresoc.v:183819$11714_Y + attribute \src "libresoc.v:183821.17-183821.92" + wire width 3 $not$libresoc.v:183821$11716_Y + attribute \src "libresoc.v:183824.17-183824.92" + wire width 3 $not$libresoc.v:183824$11719_Y + attribute \src "libresoc.v:183818.18-183818.98" + wire width 3 $or$libresoc.v:183818$11713_Y + attribute \src "libresoc.v:183820.18-183820.99" + wire width 3 $or$libresoc.v:183820$11715_Y + attribute \src "libresoc.v:183823.17-183823.97" + wire width 3 $or$libresoc.v:183823$11718_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -343810,11 +343516,11 @@ module \req_l$12 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:184034.7-184034.15" + attribute \src "libresoc.v:183782.7-183782.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -343831,7 +343537,7 @@ module \req_l$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184069$11718 + cell $and $and$libresoc.v:183817$11712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -343839,10 +343545,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184069$11718_Y + connect \Y $and$libresoc.v:183817$11712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184074$11723 + cell $and $and$libresoc.v:183822$11717 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -343850,34 +343556,34 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184074$11723_Y + connect \Y $and$libresoc.v:183822$11717_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184071$11720 + cell $not $not$libresoc.v:183819$11714 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:184071$11720_Y + connect \Y $not$libresoc.v:183819$11714_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184073$11722 + cell $not $not$libresoc.v:183821$11716 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:184073$11722_Y + connect \Y $not$libresoc.v:183821$11716_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184076$11725 + cell $not $not$libresoc.v:183824$11719 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:184076$11725_Y + connect \Y $not$libresoc.v:183824$11719_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184070$11719 + cell $or $or$libresoc.v:183818$11713 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -343885,10 +343591,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184070$11719_Y + connect \Y $or$libresoc.v:183818$11713_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184072$11721 + cell $or $or$libresoc.v:183820$11715 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -343896,10 +343602,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184072$11721_Y + connect \Y $or$libresoc.v:183820$11715_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184075$11724 + cell $or $or$libresoc.v:183823$11718 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -343907,39 +343613,39 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184075$11724_Y + connect \Y $or$libresoc.v:183823$11718_Y end - attribute \src "libresoc.v:184034.7-184034.20" - process $proc$libresoc.v:184034$11730 + attribute \src "libresoc.v:183782.7-183782.20" + process $proc$libresoc.v:183782$11724 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184056.13-184056.25" - process $proc$libresoc.v:184056$11731 + attribute \src "libresoc.v:183804.13-183804.25" + process $proc$libresoc.v:183804$11725 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:184077.3-184078.27" - process $proc$libresoc.v:184077$11726 + attribute \src "libresoc.v:183825.3-183826.27" + process $proc$libresoc.v:183825$11720 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:184079.3-184087.6" - process $proc$libresoc.v:184079$11727 + attribute \src "libresoc.v:183827.3-183835.6" + process $proc$libresoc.v:183827$11721 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11728 $1\q_int$next[2:0]$11729 - attribute \src "libresoc.v:184080.5-184080.29" + assign $0\q_int$next[2:0]$11722 $1\q_int$next[2:0]$11723 + attribute \src "libresoc.v:183828.5-183828.29" switch \initial - attribute \src "libresoc.v:184080.9-184080.17" + attribute \src "libresoc.v:183828.9-183828.17" case 1'1 case end @@ -343948,56 +343654,56 @@ module \req_l$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11729 3'000 + assign $1\q_int$next[2:0]$11723 3'000 case - assign $1\q_int$next[2:0]$11729 \$5 + assign $1\q_int$next[2:0]$11723 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11728 + update \q_int$next $0\q_int$next[2:0]$11722 end - connect \$9 $and$libresoc.v:184069$11718_Y - connect \$11 $or$libresoc.v:184070$11719_Y - connect \$13 $not$libresoc.v:184071$11720_Y - connect \$15 $or$libresoc.v:184072$11721_Y - connect \$1 $not$libresoc.v:184073$11722_Y - connect \$3 $and$libresoc.v:184074$11723_Y - connect \$5 $or$libresoc.v:184075$11724_Y - connect \$7 $not$libresoc.v:184076$11725_Y + connect \$9 $and$libresoc.v:183817$11712_Y + connect \$11 $or$libresoc.v:183818$11713_Y + connect \$13 $not$libresoc.v:183819$11714_Y + connect \$15 $or$libresoc.v:183820$11715_Y + connect \$1 $not$libresoc.v:183821$11716_Y + connect \$3 $and$libresoc.v:183822$11717_Y + connect \$5 $or$libresoc.v:183823$11718_Y + connect \$7 $not$libresoc.v:183824$11719_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184095.1-184153.10" +attribute \src "libresoc.v:183843.1-183901.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" attribute \generator "nMigen" module \req_l$121 - attribute \src "libresoc.v:184096.7-184096.20" + attribute \src "libresoc.v:183844.7-183844.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184141.3-184149.6" - wire width 3 $0\q_int$next[2:0]$11742 - attribute \src "libresoc.v:184139.3-184140.27" + attribute \src "libresoc.v:183889.3-183897.6" + wire width 3 $0\q_int$next[2:0]$11736 + attribute \src "libresoc.v:183887.3-183888.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:184141.3-184149.6" - wire width 3 $1\q_int$next[2:0]$11743 - attribute \src "libresoc.v:184118.13-184118.25" + attribute \src "libresoc.v:183889.3-183897.6" + wire width 3 $1\q_int$next[2:0]$11737 + attribute \src "libresoc.v:183866.13-183866.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:184131.17-184131.96" - wire width 3 $and$libresoc.v:184131$11732_Y - attribute \src "libresoc.v:184136.17-184136.96" - wire width 3 $and$libresoc.v:184136$11737_Y - attribute \src "libresoc.v:184133.18-184133.93" - wire width 3 $not$libresoc.v:184133$11734_Y - attribute \src "libresoc.v:184135.17-184135.92" - wire width 3 $not$libresoc.v:184135$11736_Y - attribute \src "libresoc.v:184138.17-184138.92" - wire width 3 $not$libresoc.v:184138$11739_Y - attribute \src "libresoc.v:184132.18-184132.98" - wire width 3 $or$libresoc.v:184132$11733_Y - attribute \src "libresoc.v:184134.18-184134.99" - wire width 3 $or$libresoc.v:184134$11735_Y - attribute \src "libresoc.v:184137.17-184137.97" - wire width 3 $or$libresoc.v:184137$11738_Y + attribute \src "libresoc.v:183879.17-183879.96" + wire width 3 $and$libresoc.v:183879$11726_Y + attribute \src "libresoc.v:183884.17-183884.96" + wire width 3 $and$libresoc.v:183884$11731_Y + attribute \src "libresoc.v:183881.18-183881.93" + wire width 3 $not$libresoc.v:183881$11728_Y + attribute \src "libresoc.v:183883.17-183883.92" + wire width 3 $not$libresoc.v:183883$11730_Y + attribute \src "libresoc.v:183886.17-183886.92" + wire width 3 $not$libresoc.v:183886$11733_Y + attribute \src "libresoc.v:183880.18-183880.98" + wire width 3 $or$libresoc.v:183880$11727_Y + attribute \src "libresoc.v:183882.18-183882.99" + wire width 3 $or$libresoc.v:183882$11729_Y + attribute \src "libresoc.v:183885.17-183885.97" + wire width 3 $or$libresoc.v:183885$11732_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -344014,11 +343720,11 @@ module \req_l$121 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:184096.7-184096.15" + attribute \src "libresoc.v:183844.7-183844.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -344035,7 +343741,7 @@ module \req_l$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184131$11732 + cell $and $and$libresoc.v:183879$11726 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -344043,10 +343749,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184131$11732_Y + connect \Y $and$libresoc.v:183879$11726_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184136$11737 + cell $and $and$libresoc.v:183884$11731 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -344054,34 +343760,34 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184136$11737_Y + connect \Y $and$libresoc.v:183884$11731_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184133$11734 + cell $not $not$libresoc.v:183881$11728 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:184133$11734_Y + connect \Y $not$libresoc.v:183881$11728_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184135$11736 + cell $not $not$libresoc.v:183883$11730 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:184135$11736_Y + connect \Y $not$libresoc.v:183883$11730_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184138$11739 + cell $not $not$libresoc.v:183886$11733 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:184138$11739_Y + connect \Y $not$libresoc.v:183886$11733_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184132$11733 + cell $or $or$libresoc.v:183880$11727 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -344089,10 +343795,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184132$11733_Y + connect \Y $or$libresoc.v:183880$11727_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184134$11735 + cell $or $or$libresoc.v:183882$11729 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -344100,10 +343806,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184134$11735_Y + connect \Y $or$libresoc.v:183882$11729_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184137$11738 + cell $or $or$libresoc.v:183885$11732 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -344111,39 +343817,39 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184137$11738_Y + connect \Y $or$libresoc.v:183885$11732_Y end - attribute \src "libresoc.v:184096.7-184096.20" - process $proc$libresoc.v:184096$11744 + attribute \src "libresoc.v:183844.7-183844.20" + process $proc$libresoc.v:183844$11738 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184118.13-184118.25" - process $proc$libresoc.v:184118$11745 + attribute \src "libresoc.v:183866.13-183866.25" + process $proc$libresoc.v:183866$11739 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:184139.3-184140.27" - process $proc$libresoc.v:184139$11740 + attribute \src "libresoc.v:183887.3-183888.27" + process $proc$libresoc.v:183887$11734 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:184141.3-184149.6" - process $proc$libresoc.v:184141$11741 + attribute \src "libresoc.v:183889.3-183897.6" + process $proc$libresoc.v:183889$11735 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11742 $1\q_int$next[2:0]$11743 - attribute \src "libresoc.v:184142.5-184142.29" + assign $0\q_int$next[2:0]$11736 $1\q_int$next[2:0]$11737 + attribute \src "libresoc.v:183890.5-183890.29" switch \initial - attribute \src "libresoc.v:184142.9-184142.17" + attribute \src "libresoc.v:183890.9-183890.17" case 1'1 case end @@ -344152,56 +343858,56 @@ module \req_l$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11743 3'000 + assign $1\q_int$next[2:0]$11737 3'000 case - assign $1\q_int$next[2:0]$11743 \$5 + assign $1\q_int$next[2:0]$11737 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11742 + update \q_int$next $0\q_int$next[2:0]$11736 end - connect \$9 $and$libresoc.v:184131$11732_Y - connect \$11 $or$libresoc.v:184132$11733_Y - connect \$13 $not$libresoc.v:184133$11734_Y - connect \$15 $or$libresoc.v:184134$11735_Y - connect \$1 $not$libresoc.v:184135$11736_Y - connect \$3 $and$libresoc.v:184136$11737_Y - connect \$5 $or$libresoc.v:184137$11738_Y - connect \$7 $not$libresoc.v:184138$11739_Y + connect \$9 $and$libresoc.v:183879$11726_Y + connect \$11 $or$libresoc.v:183880$11727_Y + connect \$13 $not$libresoc.v:183881$11728_Y + connect \$15 $or$libresoc.v:183882$11729_Y + connect \$1 $not$libresoc.v:183883$11730_Y + connect \$3 $and$libresoc.v:183884$11731_Y + connect \$5 $or$libresoc.v:183885$11732_Y + connect \$7 $not$libresoc.v:183886$11733_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184157.1-184215.10" +attribute \src "libresoc.v:183905.1-183963.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" attribute \generator "nMigen" module \req_l$25 - attribute \src "libresoc.v:184158.7-184158.20" + attribute \src "libresoc.v:183906.7-183906.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184203.3-184211.6" - wire width 3 $0\q_int$next[2:0]$11756 - attribute \src "libresoc.v:184201.3-184202.27" + attribute \src "libresoc.v:183951.3-183959.6" + wire width 3 $0\q_int$next[2:0]$11750 + attribute \src "libresoc.v:183949.3-183950.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:184203.3-184211.6" - wire width 3 $1\q_int$next[2:0]$11757 - attribute \src "libresoc.v:184180.13-184180.25" + attribute \src "libresoc.v:183951.3-183959.6" + wire width 3 $1\q_int$next[2:0]$11751 + attribute \src "libresoc.v:183928.13-183928.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:184193.17-184193.96" - wire width 3 $and$libresoc.v:184193$11746_Y - attribute \src "libresoc.v:184198.17-184198.96" - wire width 3 $and$libresoc.v:184198$11751_Y - attribute \src "libresoc.v:184195.18-184195.93" - wire width 3 $not$libresoc.v:184195$11748_Y - attribute \src "libresoc.v:184197.17-184197.92" - wire width 3 $not$libresoc.v:184197$11750_Y - attribute \src "libresoc.v:184200.17-184200.92" - wire width 3 $not$libresoc.v:184200$11753_Y - attribute \src "libresoc.v:184194.18-184194.98" - wire width 3 $or$libresoc.v:184194$11747_Y - attribute \src "libresoc.v:184196.18-184196.99" - wire width 3 $or$libresoc.v:184196$11749_Y - attribute \src "libresoc.v:184199.17-184199.97" - wire width 3 $or$libresoc.v:184199$11752_Y + attribute \src "libresoc.v:183941.17-183941.96" + wire width 3 $and$libresoc.v:183941$11740_Y + attribute \src "libresoc.v:183946.17-183946.96" + wire width 3 $and$libresoc.v:183946$11745_Y + attribute \src "libresoc.v:183943.18-183943.93" + wire width 3 $not$libresoc.v:183943$11742_Y + attribute \src "libresoc.v:183945.17-183945.92" + wire width 3 $not$libresoc.v:183945$11744_Y + attribute \src "libresoc.v:183948.17-183948.92" + wire width 3 $not$libresoc.v:183948$11747_Y + attribute \src "libresoc.v:183942.18-183942.98" + wire width 3 $or$libresoc.v:183942$11741_Y + attribute \src "libresoc.v:183944.18-183944.99" + wire width 3 $or$libresoc.v:183944$11743_Y + attribute \src "libresoc.v:183947.17-183947.97" + wire width 3 $or$libresoc.v:183947$11746_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -344218,11 +343924,11 @@ module \req_l$25 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:184158.7-184158.15" + attribute \src "libresoc.v:183906.7-183906.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -344239,7 +343945,7 @@ module \req_l$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184193$11746 + cell $and $and$libresoc.v:183941$11740 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -344247,10 +343953,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184193$11746_Y + connect \Y $and$libresoc.v:183941$11740_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184198$11751 + cell $and $and$libresoc.v:183946$11745 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -344258,34 +343964,34 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184198$11751_Y + connect \Y $and$libresoc.v:183946$11745_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184195$11748 + cell $not $not$libresoc.v:183943$11742 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:184195$11748_Y + connect \Y $not$libresoc.v:183943$11742_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184197$11750 + cell $not $not$libresoc.v:183945$11744 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:184197$11750_Y + connect \Y $not$libresoc.v:183945$11744_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184200$11753 + cell $not $not$libresoc.v:183948$11747 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:184200$11753_Y + connect \Y $not$libresoc.v:183948$11747_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184194$11747 + cell $or $or$libresoc.v:183942$11741 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -344293,10 +343999,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184194$11747_Y + connect \Y $or$libresoc.v:183942$11741_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184196$11749 + cell $or $or$libresoc.v:183944$11743 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -344304,10 +344010,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184196$11749_Y + connect \Y $or$libresoc.v:183944$11743_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184199$11752 + cell $or $or$libresoc.v:183947$11746 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -344315,39 +344021,39 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184199$11752_Y + connect \Y $or$libresoc.v:183947$11746_Y end - attribute \src "libresoc.v:184158.7-184158.20" - process $proc$libresoc.v:184158$11758 + attribute \src "libresoc.v:183906.7-183906.20" + process $proc$libresoc.v:183906$11752 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184180.13-184180.25" - process $proc$libresoc.v:184180$11759 + attribute \src "libresoc.v:183928.13-183928.25" + process $proc$libresoc.v:183928$11753 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:184201.3-184202.27" - process $proc$libresoc.v:184201$11754 + attribute \src "libresoc.v:183949.3-183950.27" + process $proc$libresoc.v:183949$11748 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:184203.3-184211.6" - process $proc$libresoc.v:184203$11755 + attribute \src "libresoc.v:183951.3-183959.6" + process $proc$libresoc.v:183951$11749 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11756 $1\q_int$next[2:0]$11757 - attribute \src "libresoc.v:184204.5-184204.29" + assign $0\q_int$next[2:0]$11750 $1\q_int$next[2:0]$11751 + attribute \src "libresoc.v:183952.5-183952.29" switch \initial - attribute \src "libresoc.v:184204.9-184204.17" + attribute \src "libresoc.v:183952.9-183952.17" case 1'1 case end @@ -344356,56 +344062,56 @@ module \req_l$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11757 3'000 + assign $1\q_int$next[2:0]$11751 3'000 case - assign $1\q_int$next[2:0]$11757 \$5 + assign $1\q_int$next[2:0]$11751 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11756 + update \q_int$next $0\q_int$next[2:0]$11750 end - connect \$9 $and$libresoc.v:184193$11746_Y - connect \$11 $or$libresoc.v:184194$11747_Y - connect \$13 $not$libresoc.v:184195$11748_Y - connect \$15 $or$libresoc.v:184196$11749_Y - connect \$1 $not$libresoc.v:184197$11750_Y - connect \$3 $and$libresoc.v:184198$11751_Y - connect \$5 $or$libresoc.v:184199$11752_Y - connect \$7 $not$libresoc.v:184200$11753_Y + connect \$9 $and$libresoc.v:183941$11740_Y + connect \$11 $or$libresoc.v:183942$11741_Y + connect \$13 $not$libresoc.v:183943$11742_Y + connect \$15 $or$libresoc.v:183944$11743_Y + connect \$1 $not$libresoc.v:183945$11744_Y + connect \$3 $and$libresoc.v:183946$11745_Y + connect \$5 $or$libresoc.v:183947$11746_Y + connect \$7 $not$libresoc.v:183948$11747_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184219.1-184277.10" +attribute \src "libresoc.v:183967.1-184025.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" attribute \generator "nMigen" module \req_l$41 - attribute \src "libresoc.v:184220.7-184220.20" + attribute \src "libresoc.v:183968.7-183968.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184265.3-184273.6" - wire width 5 $0\q_int$next[4:0]$11770 - attribute \src "libresoc.v:184263.3-184264.27" + attribute \src "libresoc.v:184013.3-184021.6" + wire width 5 $0\q_int$next[4:0]$11764 + attribute \src "libresoc.v:184011.3-184012.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:184265.3-184273.6" - wire width 5 $1\q_int$next[4:0]$11771 - attribute \src "libresoc.v:184242.13-184242.26" + attribute \src "libresoc.v:184013.3-184021.6" + wire width 5 $1\q_int$next[4:0]$11765 + attribute \src "libresoc.v:183990.13-183990.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:184255.17-184255.96" - wire width 5 $and$libresoc.v:184255$11760_Y - attribute \src "libresoc.v:184260.17-184260.96" - wire width 5 $and$libresoc.v:184260$11765_Y - attribute \src "libresoc.v:184257.18-184257.93" - wire width 5 $not$libresoc.v:184257$11762_Y - attribute \src "libresoc.v:184259.17-184259.92" - wire width 5 $not$libresoc.v:184259$11764_Y - attribute \src "libresoc.v:184262.17-184262.92" - wire width 5 $not$libresoc.v:184262$11767_Y - attribute \src "libresoc.v:184256.18-184256.98" - wire width 5 $or$libresoc.v:184256$11761_Y - attribute \src "libresoc.v:184258.18-184258.99" - wire width 5 $or$libresoc.v:184258$11763_Y - attribute \src "libresoc.v:184261.17-184261.97" - wire width 5 $or$libresoc.v:184261$11766_Y + attribute \src "libresoc.v:184003.17-184003.96" + wire width 5 $and$libresoc.v:184003$11754_Y + attribute \src "libresoc.v:184008.17-184008.96" + wire width 5 $and$libresoc.v:184008$11759_Y + attribute \src "libresoc.v:184005.18-184005.93" + wire width 5 $not$libresoc.v:184005$11756_Y + attribute \src "libresoc.v:184007.17-184007.92" + wire width 5 $not$libresoc.v:184007$11758_Y + attribute \src "libresoc.v:184010.17-184010.92" + wire width 5 $not$libresoc.v:184010$11761_Y + attribute \src "libresoc.v:184004.18-184004.98" + wire width 5 $or$libresoc.v:184004$11755_Y + attribute \src "libresoc.v:184006.18-184006.99" + wire width 5 $or$libresoc.v:184006$11757_Y + attribute \src "libresoc.v:184009.17-184009.97" + wire width 5 $or$libresoc.v:184009$11760_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -344422,11 +344128,11 @@ module \req_l$41 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:184220.7-184220.15" + attribute \src "libresoc.v:183968.7-183968.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -344443,7 +344149,7 @@ module \req_l$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184255$11760 + cell $and $and$libresoc.v:184003$11754 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -344451,10 +344157,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184255$11760_Y + connect \Y $and$libresoc.v:184003$11754_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184260$11765 + cell $and $and$libresoc.v:184008$11759 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -344462,34 +344168,34 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184260$11765_Y + connect \Y $and$libresoc.v:184008$11759_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184257$11762 + cell $not $not$libresoc.v:184005$11756 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:184257$11762_Y + connect \Y $not$libresoc.v:184005$11756_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184259$11764 + cell $not $not$libresoc.v:184007$11758 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:184259$11764_Y + connect \Y $not$libresoc.v:184007$11758_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184262$11767 + cell $not $not$libresoc.v:184010$11761 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:184262$11767_Y + connect \Y $not$libresoc.v:184010$11761_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184256$11761 + cell $or $or$libresoc.v:184004$11755 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -344497,10 +344203,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184256$11761_Y + connect \Y $or$libresoc.v:184004$11755_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184258$11763 + cell $or $or$libresoc.v:184006$11757 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -344508,10 +344214,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184258$11763_Y + connect \Y $or$libresoc.v:184006$11757_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184261$11766 + cell $or $or$libresoc.v:184009$11760 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -344519,39 +344225,39 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184261$11766_Y + connect \Y $or$libresoc.v:184009$11760_Y end - attribute \src "libresoc.v:184220.7-184220.20" - process $proc$libresoc.v:184220$11772 + attribute \src "libresoc.v:183968.7-183968.20" + process $proc$libresoc.v:183968$11766 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184242.13-184242.26" - process $proc$libresoc.v:184242$11773 + attribute \src "libresoc.v:183990.13-183990.26" + process $proc$libresoc.v:183990$11767 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:184263.3-184264.27" - process $proc$libresoc.v:184263$11768 + attribute \src "libresoc.v:184011.3-184012.27" + process $proc$libresoc.v:184011$11762 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:184265.3-184273.6" - process $proc$libresoc.v:184265$11769 + attribute \src "libresoc.v:184013.3-184021.6" + process $proc$libresoc.v:184013$11763 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11770 $1\q_int$next[4:0]$11771 - attribute \src "libresoc.v:184266.5-184266.29" + assign $0\q_int$next[4:0]$11764 $1\q_int$next[4:0]$11765 + attribute \src "libresoc.v:184014.5-184014.29" switch \initial - attribute \src "libresoc.v:184266.9-184266.17" + attribute \src "libresoc.v:184014.9-184014.17" case 1'1 case end @@ -344560,56 +344266,56 @@ module \req_l$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11771 5'00000 + assign $1\q_int$next[4:0]$11765 5'00000 case - assign $1\q_int$next[4:0]$11771 \$5 + assign $1\q_int$next[4:0]$11765 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11770 + update \q_int$next $0\q_int$next[4:0]$11764 end - connect \$9 $and$libresoc.v:184255$11760_Y - connect \$11 $or$libresoc.v:184256$11761_Y - connect \$13 $not$libresoc.v:184257$11762_Y - connect \$15 $or$libresoc.v:184258$11763_Y - connect \$1 $not$libresoc.v:184259$11764_Y - connect \$3 $and$libresoc.v:184260$11765_Y - connect \$5 $or$libresoc.v:184261$11766_Y - connect \$7 $not$libresoc.v:184262$11767_Y + connect \$9 $and$libresoc.v:184003$11754_Y + connect \$11 $or$libresoc.v:184004$11755_Y + connect \$13 $not$libresoc.v:184005$11756_Y + connect \$15 $or$libresoc.v:184006$11757_Y + connect \$1 $not$libresoc.v:184007$11758_Y + connect \$3 $and$libresoc.v:184008$11759_Y + connect \$5 $or$libresoc.v:184009$11760_Y + connect \$7 $not$libresoc.v:184010$11761_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184281.1-184339.10" +attribute \src "libresoc.v:184029.1-184087.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" attribute \generator "nMigen" module \req_l$57 - attribute \src "libresoc.v:184282.7-184282.20" + attribute \src "libresoc.v:184030.7-184030.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184327.3-184335.6" - wire width 2 $0\q_int$next[1:0]$11784 - attribute \src "libresoc.v:184325.3-184326.27" + attribute \src "libresoc.v:184075.3-184083.6" + wire width 2 $0\q_int$next[1:0]$11778 + attribute \src "libresoc.v:184073.3-184074.27" wire width 2 $0\q_int[1:0] - attribute \src "libresoc.v:184327.3-184335.6" - wire width 2 $1\q_int$next[1:0]$11785 - attribute \src "libresoc.v:184304.13-184304.25" + attribute \src "libresoc.v:184075.3-184083.6" + wire width 2 $1\q_int$next[1:0]$11779 + attribute \src "libresoc.v:184052.13-184052.25" wire width 2 $1\q_int[1:0] - attribute \src "libresoc.v:184317.17-184317.96" - wire width 2 $and$libresoc.v:184317$11774_Y - attribute \src "libresoc.v:184322.17-184322.96" - wire width 2 $and$libresoc.v:184322$11779_Y - attribute \src "libresoc.v:184319.18-184319.93" - wire width 2 $not$libresoc.v:184319$11776_Y - attribute \src "libresoc.v:184321.17-184321.92" - wire width 2 $not$libresoc.v:184321$11778_Y - attribute \src "libresoc.v:184324.17-184324.92" - wire width 2 $not$libresoc.v:184324$11781_Y - attribute \src "libresoc.v:184318.18-184318.98" - wire width 2 $or$libresoc.v:184318$11775_Y - attribute \src "libresoc.v:184320.18-184320.99" - wire width 2 $or$libresoc.v:184320$11777_Y - attribute \src "libresoc.v:184323.17-184323.97" - wire width 2 $or$libresoc.v:184323$11780_Y + attribute \src "libresoc.v:184065.17-184065.96" + wire width 2 $and$libresoc.v:184065$11768_Y + attribute \src "libresoc.v:184070.17-184070.96" + wire width 2 $and$libresoc.v:184070$11773_Y + attribute \src "libresoc.v:184067.18-184067.93" + wire width 2 $not$libresoc.v:184067$11770_Y + attribute \src "libresoc.v:184069.17-184069.92" + wire width 2 $not$libresoc.v:184069$11772_Y + attribute \src "libresoc.v:184072.17-184072.92" + wire width 2 $not$libresoc.v:184072$11775_Y + attribute \src "libresoc.v:184066.18-184066.98" + wire width 2 $or$libresoc.v:184066$11769_Y + attribute \src "libresoc.v:184068.18-184068.99" + wire width 2 $or$libresoc.v:184068$11771_Y + attribute \src "libresoc.v:184071.17-184071.97" + wire width 2 $or$libresoc.v:184071$11774_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -344626,11 +344332,11 @@ module \req_l$57 wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:184282.7-184282.15" + attribute \src "libresoc.v:184030.7-184030.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int @@ -344647,7 +344353,7 @@ module \req_l$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184317$11774 + cell $and $and$libresoc.v:184065$11768 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -344655,10 +344361,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184317$11774_Y + connect \Y $and$libresoc.v:184065$11768_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184322$11779 + cell $and $and$libresoc.v:184070$11773 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -344666,34 +344372,34 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184322$11779_Y + connect \Y $and$libresoc.v:184070$11773_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184319$11776 + cell $not $not$libresoc.v:184067$11770 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req - connect \Y $not$libresoc.v:184319$11776_Y + connect \Y $not$libresoc.v:184067$11770_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184321$11778 + cell $not $not$libresoc.v:184069$11772 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:184321$11778_Y + connect \Y $not$libresoc.v:184069$11772_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184324$11781 + cell $not $not$libresoc.v:184072$11775 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:184324$11781_Y + connect \Y $not$libresoc.v:184072$11775_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184318$11775 + cell $or $or$libresoc.v:184066$11769 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -344701,10 +344407,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184318$11775_Y + connect \Y $or$libresoc.v:184066$11769_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184320$11777 + cell $or $or$libresoc.v:184068$11771 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -344712,10 +344418,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184320$11777_Y + connect \Y $or$libresoc.v:184068$11771_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184323$11780 + cell $or $or$libresoc.v:184071$11774 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -344723,39 +344429,39 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184323$11780_Y + connect \Y $or$libresoc.v:184071$11774_Y end - attribute \src "libresoc.v:184282.7-184282.20" - process $proc$libresoc.v:184282$11786 + attribute \src "libresoc.v:184030.7-184030.20" + process $proc$libresoc.v:184030$11780 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184304.13-184304.25" - process $proc$libresoc.v:184304$11787 + attribute \src "libresoc.v:184052.13-184052.25" + process $proc$libresoc.v:184052$11781 assign { } { } assign $1\q_int[1:0] 2'00 sync always sync init update \q_int $1\q_int[1:0] end - attribute \src "libresoc.v:184325.3-184326.27" - process $proc$libresoc.v:184325$11782 + attribute \src "libresoc.v:184073.3-184074.27" + process $proc$libresoc.v:184073$11776 assign { } { } assign $0\q_int[1:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[1:0] end - attribute \src "libresoc.v:184327.3-184335.6" - process $proc$libresoc.v:184327$11783 + attribute \src "libresoc.v:184075.3-184083.6" + process $proc$libresoc.v:184075$11777 assign { } { } assign { } { } - assign $0\q_int$next[1:0]$11784 $1\q_int$next[1:0]$11785 - attribute \src "libresoc.v:184328.5-184328.29" + assign $0\q_int$next[1:0]$11778 $1\q_int$next[1:0]$11779 + attribute \src "libresoc.v:184076.5-184076.29" switch \initial - attribute \src "libresoc.v:184328.9-184328.17" + attribute \src "libresoc.v:184076.9-184076.17" case 1'1 case end @@ -344764,56 +344470,56 @@ module \req_l$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[1:0]$11785 2'00 + assign $1\q_int$next[1:0]$11779 2'00 case - assign $1\q_int$next[1:0]$11785 \$5 + assign $1\q_int$next[1:0]$11779 \$5 end sync always - update \q_int$next $0\q_int$next[1:0]$11784 + update \q_int$next $0\q_int$next[1:0]$11778 end - connect \$9 $and$libresoc.v:184317$11774_Y - connect \$11 $or$libresoc.v:184318$11775_Y - connect \$13 $not$libresoc.v:184319$11776_Y - connect \$15 $or$libresoc.v:184320$11777_Y - connect \$1 $not$libresoc.v:184321$11778_Y - connect \$3 $and$libresoc.v:184322$11779_Y - connect \$5 $or$libresoc.v:184323$11780_Y - connect \$7 $not$libresoc.v:184324$11781_Y + connect \$9 $and$libresoc.v:184065$11768_Y + connect \$11 $or$libresoc.v:184066$11769_Y + connect \$13 $not$libresoc.v:184067$11770_Y + connect \$15 $or$libresoc.v:184068$11771_Y + connect \$1 $not$libresoc.v:184069$11772_Y + connect \$3 $and$libresoc.v:184070$11773_Y + connect \$5 $or$libresoc.v:184071$11774_Y + connect \$7 $not$libresoc.v:184072$11775_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184343.1-184401.10" +attribute \src "libresoc.v:184091.1-184149.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" attribute \generator "nMigen" module \req_l$69 - attribute \src "libresoc.v:184344.7-184344.20" + attribute \src "libresoc.v:184092.7-184092.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184389.3-184397.6" - wire width 6 $0\q_int$next[5:0]$11798 - attribute \src "libresoc.v:184387.3-184388.27" + attribute \src "libresoc.v:184137.3-184145.6" + wire width 6 $0\q_int$next[5:0]$11792 + attribute \src "libresoc.v:184135.3-184136.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:184389.3-184397.6" - wire width 6 $1\q_int$next[5:0]$11799 - attribute \src "libresoc.v:184366.13-184366.26" + attribute \src "libresoc.v:184137.3-184145.6" + wire width 6 $1\q_int$next[5:0]$11793 + attribute \src "libresoc.v:184114.13-184114.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:184379.17-184379.96" - wire width 6 $and$libresoc.v:184379$11788_Y - attribute \src "libresoc.v:184384.17-184384.96" - wire width 6 $and$libresoc.v:184384$11793_Y - attribute \src "libresoc.v:184381.18-184381.93" - wire width 6 $not$libresoc.v:184381$11790_Y - attribute \src "libresoc.v:184383.17-184383.92" - wire width 6 $not$libresoc.v:184383$11792_Y - attribute \src "libresoc.v:184386.17-184386.92" - wire width 6 $not$libresoc.v:184386$11795_Y - attribute \src "libresoc.v:184380.18-184380.98" - wire width 6 $or$libresoc.v:184380$11789_Y - attribute \src "libresoc.v:184382.18-184382.99" - wire width 6 $or$libresoc.v:184382$11791_Y - attribute \src "libresoc.v:184385.17-184385.97" - wire width 6 $or$libresoc.v:184385$11794_Y + attribute \src "libresoc.v:184127.17-184127.96" + wire width 6 $and$libresoc.v:184127$11782_Y + attribute \src "libresoc.v:184132.17-184132.96" + wire width 6 $and$libresoc.v:184132$11787_Y + attribute \src "libresoc.v:184129.18-184129.93" + wire width 6 $not$libresoc.v:184129$11784_Y + attribute \src "libresoc.v:184131.17-184131.92" + wire width 6 $not$libresoc.v:184131$11786_Y + attribute \src "libresoc.v:184134.17-184134.92" + wire width 6 $not$libresoc.v:184134$11789_Y + attribute \src "libresoc.v:184128.18-184128.98" + wire width 6 $or$libresoc.v:184128$11783_Y + attribute \src "libresoc.v:184130.18-184130.99" + wire width 6 $or$libresoc.v:184130$11785_Y + attribute \src "libresoc.v:184133.17-184133.97" + wire width 6 $or$libresoc.v:184133$11788_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -344830,11 +344536,11 @@ module \req_l$69 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:184344.7-184344.15" + attribute \src "libresoc.v:184092.7-184092.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -344851,7 +344557,7 @@ module \req_l$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184379$11788 + cell $and $and$libresoc.v:184127$11782 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -344859,10 +344565,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184379$11788_Y + connect \Y $and$libresoc.v:184127$11782_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184384$11793 + cell $and $and$libresoc.v:184132$11787 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -344870,34 +344576,34 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184384$11793_Y + connect \Y $and$libresoc.v:184132$11787_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184381$11790 + cell $not $not$libresoc.v:184129$11784 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req - connect \Y $not$libresoc.v:184381$11790_Y + connect \Y $not$libresoc.v:184129$11784_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184383$11792 + cell $not $not$libresoc.v:184131$11786 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:184383$11792_Y + connect \Y $not$libresoc.v:184131$11786_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184386$11795 + cell $not $not$libresoc.v:184134$11789 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:184386$11795_Y + connect \Y $not$libresoc.v:184134$11789_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184380$11789 + cell $or $or$libresoc.v:184128$11783 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -344905,10 +344611,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184380$11789_Y + connect \Y $or$libresoc.v:184128$11783_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184382$11791 + cell $or $or$libresoc.v:184130$11785 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -344916,10 +344622,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184382$11791_Y + connect \Y $or$libresoc.v:184130$11785_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184385$11794 + cell $or $or$libresoc.v:184133$11788 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -344927,39 +344633,39 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184385$11794_Y + connect \Y $or$libresoc.v:184133$11788_Y end - attribute \src "libresoc.v:184344.7-184344.20" - process $proc$libresoc.v:184344$11800 + attribute \src "libresoc.v:184092.7-184092.20" + process $proc$libresoc.v:184092$11794 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184366.13-184366.26" - process $proc$libresoc.v:184366$11801 + attribute \src "libresoc.v:184114.13-184114.26" + process $proc$libresoc.v:184114$11795 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:184387.3-184388.27" - process $proc$libresoc.v:184387$11796 + attribute \src "libresoc.v:184135.3-184136.27" + process $proc$libresoc.v:184135$11790 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:184389.3-184397.6" - process $proc$libresoc.v:184389$11797 + attribute \src "libresoc.v:184137.3-184145.6" + process $proc$libresoc.v:184137$11791 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$11798 $1\q_int$next[5:0]$11799 - attribute \src "libresoc.v:184390.5-184390.29" + assign $0\q_int$next[5:0]$11792 $1\q_int$next[5:0]$11793 + attribute \src "libresoc.v:184138.5-184138.29" switch \initial - attribute \src "libresoc.v:184390.9-184390.17" + attribute \src "libresoc.v:184138.9-184138.17" case 1'1 case end @@ -344968,56 +344674,56 @@ module \req_l$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$11799 6'000000 + assign $1\q_int$next[5:0]$11793 6'000000 case - assign $1\q_int$next[5:0]$11799 \$5 + assign $1\q_int$next[5:0]$11793 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$11798 + update \q_int$next $0\q_int$next[5:0]$11792 end - connect \$9 $and$libresoc.v:184379$11788_Y - connect \$11 $or$libresoc.v:184380$11789_Y - connect \$13 $not$libresoc.v:184381$11790_Y - connect \$15 $or$libresoc.v:184382$11791_Y - connect \$1 $not$libresoc.v:184383$11792_Y - connect \$3 $and$libresoc.v:184384$11793_Y - connect \$5 $or$libresoc.v:184385$11794_Y - connect \$7 $not$libresoc.v:184386$11795_Y + connect \$9 $and$libresoc.v:184127$11782_Y + connect \$11 $or$libresoc.v:184128$11783_Y + connect \$13 $not$libresoc.v:184129$11784_Y + connect \$15 $or$libresoc.v:184130$11785_Y + connect \$1 $not$libresoc.v:184131$11786_Y + connect \$3 $and$libresoc.v:184132$11787_Y + connect \$5 $or$libresoc.v:184133$11788_Y + connect \$7 $not$libresoc.v:184134$11789_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184405.1-184463.10" +attribute \src "libresoc.v:184153.1-184211.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" attribute \generator "nMigen" module \req_l$86 - attribute \src "libresoc.v:184406.7-184406.20" + attribute \src "libresoc.v:184154.7-184154.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184451.3-184459.6" - wire width 4 $0\q_int$next[3:0]$11812 - attribute \src "libresoc.v:184449.3-184450.27" + attribute \src "libresoc.v:184199.3-184207.6" + wire width 4 $0\q_int$next[3:0]$11806 + attribute \src "libresoc.v:184197.3-184198.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:184451.3-184459.6" - wire width 4 $1\q_int$next[3:0]$11813 - attribute \src "libresoc.v:184428.13-184428.25" + attribute \src "libresoc.v:184199.3-184207.6" + wire width 4 $1\q_int$next[3:0]$11807 + attribute \src "libresoc.v:184176.13-184176.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:184441.17-184441.96" - wire width 4 $and$libresoc.v:184441$11802_Y - attribute \src "libresoc.v:184446.17-184446.96" - wire width 4 $and$libresoc.v:184446$11807_Y - attribute \src "libresoc.v:184443.18-184443.93" - wire width 4 $not$libresoc.v:184443$11804_Y - attribute \src "libresoc.v:184445.17-184445.92" - wire width 4 $not$libresoc.v:184445$11806_Y - attribute \src "libresoc.v:184448.17-184448.92" - wire width 4 $not$libresoc.v:184448$11809_Y - attribute \src "libresoc.v:184442.18-184442.98" - wire width 4 $or$libresoc.v:184442$11803_Y - attribute \src "libresoc.v:184444.18-184444.99" - wire width 4 $or$libresoc.v:184444$11805_Y - attribute \src "libresoc.v:184447.17-184447.97" - wire width 4 $or$libresoc.v:184447$11808_Y + attribute \src "libresoc.v:184189.17-184189.96" + wire width 4 $and$libresoc.v:184189$11796_Y + attribute \src "libresoc.v:184194.17-184194.96" + wire width 4 $and$libresoc.v:184194$11801_Y + attribute \src "libresoc.v:184191.18-184191.93" + wire width 4 $not$libresoc.v:184191$11798_Y + attribute \src "libresoc.v:184193.17-184193.92" + wire width 4 $not$libresoc.v:184193$11800_Y + attribute \src "libresoc.v:184196.17-184196.92" + wire width 4 $not$libresoc.v:184196$11803_Y + attribute \src "libresoc.v:184190.18-184190.98" + wire width 4 $or$libresoc.v:184190$11797_Y + attribute \src "libresoc.v:184192.18-184192.99" + wire width 4 $or$libresoc.v:184192$11799_Y + attribute \src "libresoc.v:184195.17-184195.97" + wire width 4 $or$libresoc.v:184195$11802_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -345034,11 +344740,11 @@ module \req_l$86 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:184406.7-184406.15" + attribute \src "libresoc.v:184154.7-184154.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -345055,7 +344761,7 @@ module \req_l$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184441$11802 + cell $and $and$libresoc.v:184189$11796 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -345063,10 +344769,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184441$11802_Y + connect \Y $and$libresoc.v:184189$11796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184446$11807 + cell $and $and$libresoc.v:184194$11801 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -345074,34 +344780,34 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184446$11807_Y + connect \Y $and$libresoc.v:184194$11801_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184443$11804 + cell $not $not$libresoc.v:184191$11798 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:184443$11804_Y + connect \Y $not$libresoc.v:184191$11798_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184445$11806 + cell $not $not$libresoc.v:184193$11800 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:184445$11806_Y + connect \Y $not$libresoc.v:184193$11800_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184448$11809 + cell $not $not$libresoc.v:184196$11803 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:184448$11809_Y + connect \Y $not$libresoc.v:184196$11803_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184442$11803 + cell $or $or$libresoc.v:184190$11797 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -345109,10 +344815,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184442$11803_Y + connect \Y $or$libresoc.v:184190$11797_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184444$11805 + cell $or $or$libresoc.v:184192$11799 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -345120,10 +344826,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184444$11805_Y + connect \Y $or$libresoc.v:184192$11799_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184447$11808 + cell $or $or$libresoc.v:184195$11802 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -345131,39 +344837,39 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184447$11808_Y + connect \Y $or$libresoc.v:184195$11802_Y end - attribute \src "libresoc.v:184406.7-184406.20" - process $proc$libresoc.v:184406$11814 + attribute \src "libresoc.v:184154.7-184154.20" + process $proc$libresoc.v:184154$11808 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184428.13-184428.25" - process $proc$libresoc.v:184428$11815 + attribute \src "libresoc.v:184176.13-184176.25" + process $proc$libresoc.v:184176$11809 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:184449.3-184450.27" - process $proc$libresoc.v:184449$11810 + attribute \src "libresoc.v:184197.3-184198.27" + process $proc$libresoc.v:184197$11804 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:184451.3-184459.6" - process $proc$libresoc.v:184451$11811 + attribute \src "libresoc.v:184199.3-184207.6" + process $proc$libresoc.v:184199$11805 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11812 $1\q_int$next[3:0]$11813 - attribute \src "libresoc.v:184452.5-184452.29" + assign $0\q_int$next[3:0]$11806 $1\q_int$next[3:0]$11807 + attribute \src "libresoc.v:184200.5-184200.29" switch \initial - attribute \src "libresoc.v:184452.9-184452.17" + attribute \src "libresoc.v:184200.9-184200.17" case 1'1 case end @@ -345172,50 +344878,50 @@ module \req_l$86 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11813 4'0000 + assign $1\q_int$next[3:0]$11807 4'0000 case - assign $1\q_int$next[3:0]$11813 \$5 + assign $1\q_int$next[3:0]$11807 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11812 + update \q_int$next $0\q_int$next[3:0]$11806 end - connect \$9 $and$libresoc.v:184441$11802_Y - connect \$11 $or$libresoc.v:184442$11803_Y - connect \$13 $not$libresoc.v:184443$11804_Y - connect \$15 $or$libresoc.v:184444$11805_Y - connect \$1 $not$libresoc.v:184445$11806_Y - connect \$3 $and$libresoc.v:184446$11807_Y - connect \$5 $or$libresoc.v:184447$11808_Y - connect \$7 $not$libresoc.v:184448$11809_Y + connect \$9 $and$libresoc.v:184189$11796_Y + connect \$11 $or$libresoc.v:184190$11797_Y + connect \$13 $not$libresoc.v:184191$11798_Y + connect \$15 $or$libresoc.v:184192$11799_Y + connect \$1 $not$libresoc.v:184193$11800_Y + connect \$3 $and$libresoc.v:184194$11801_Y + connect \$5 $or$libresoc.v:184195$11802_Y + connect \$7 $not$libresoc.v:184196$11803_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184467.1-184516.10" +attribute \src "libresoc.v:184215.1-184264.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" attribute \generator "nMigen" module \reset_l - attribute \src "libresoc.v:184468.7-184468.20" + attribute \src "libresoc.v:184216.7-184216.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184504.3-184512.6" - wire $0\q_int$next[0:0]$11823 - attribute \src "libresoc.v:184502.3-184503.27" + attribute \src "libresoc.v:184252.3-184260.6" + wire $0\q_int$next[0:0]$11817 + attribute \src "libresoc.v:184250.3-184251.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184504.3-184512.6" - wire $1\q_int$next[0:0]$11824 - attribute \src "libresoc.v:184484.7-184484.19" + attribute \src "libresoc.v:184252.3-184260.6" + wire $1\q_int$next[0:0]$11818 + attribute \src "libresoc.v:184232.7-184232.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184499.17-184499.96" - wire $and$libresoc.v:184499$11818_Y - attribute \src "libresoc.v:184498.17-184498.94" - wire $not$libresoc.v:184498$11817_Y - attribute \src "libresoc.v:184501.17-184501.94" - wire $not$libresoc.v:184501$11820_Y - attribute \src "libresoc.v:184497.17-184497.100" - wire $or$libresoc.v:184497$11816_Y - attribute \src "libresoc.v:184500.17-184500.99" - wire $or$libresoc.v:184500$11819_Y + attribute \src "libresoc.v:184247.17-184247.96" + wire $and$libresoc.v:184247$11812_Y + attribute \src "libresoc.v:184246.17-184246.94" + wire $not$libresoc.v:184246$11811_Y + attribute \src "libresoc.v:184249.17-184249.94" + wire $not$libresoc.v:184249$11814_Y + attribute \src "libresoc.v:184245.17-184245.100" + wire $or$libresoc.v:184245$11810_Y + attribute \src "libresoc.v:184248.17-184248.99" + wire $or$libresoc.v:184248$11813_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -345226,11 +344932,11 @@ module \reset_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:184468.7-184468.15" + attribute \src "libresoc.v:184216.7-184216.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -345247,7 +344953,7 @@ module \reset_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184499$11818 + cell $and $and$libresoc.v:184247$11812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -345255,26 +344961,26 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184499$11818_Y + connect \Y $and$libresoc.v:184247$11812_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184498$11817 + cell $not $not$libresoc.v:184246$11811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:184498$11817_Y + connect \Y $not$libresoc.v:184246$11811_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184501$11820 + cell $not $not$libresoc.v:184249$11814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:184501$11820_Y + connect \Y $not$libresoc.v:184249$11814_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184497$11816 + cell $or $or$libresoc.v:184245$11810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -345282,10 +344988,10 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:184497$11816_Y + connect \Y $or$libresoc.v:184245$11810_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184500$11819 + cell $or $or$libresoc.v:184248$11813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -345293,39 +344999,39 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:184500$11819_Y + connect \Y $or$libresoc.v:184248$11813_Y end - attribute \src "libresoc.v:184468.7-184468.20" - process $proc$libresoc.v:184468$11825 + attribute \src "libresoc.v:184216.7-184216.20" + process $proc$libresoc.v:184216$11819 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184484.7-184484.19" - process $proc$libresoc.v:184484$11826 + attribute \src "libresoc.v:184232.7-184232.19" + process $proc$libresoc.v:184232$11820 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184502.3-184503.27" - process $proc$libresoc.v:184502$11821 + attribute \src "libresoc.v:184250.3-184251.27" + process $proc$libresoc.v:184250$11815 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184504.3-184512.6" - process $proc$libresoc.v:184504$11822 + attribute \src "libresoc.v:184252.3-184260.6" + process $proc$libresoc.v:184252$11816 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11823 $1\q_int$next[0:0]$11824 - attribute \src "libresoc.v:184505.5-184505.29" + assign $0\q_int$next[0:0]$11817 $1\q_int$next[0:0]$11818 + attribute \src "libresoc.v:184253.5-184253.29" switch \initial - attribute \src "libresoc.v:184505.9-184505.17" + attribute \src "libresoc.v:184253.9-184253.17" case 1'1 case end @@ -345334,47 +345040,47 @@ module \reset_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11824 1'0 + assign $1\q_int$next[0:0]$11818 1'0 case - assign $1\q_int$next[0:0]$11824 \$5 + assign $1\q_int$next[0:0]$11818 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11823 + update \q_int$next $0\q_int$next[0:0]$11817 end - connect \$9 $or$libresoc.v:184497$11816_Y - connect \$1 $not$libresoc.v:184498$11817_Y - connect \$3 $and$libresoc.v:184499$11818_Y - connect \$5 $or$libresoc.v:184500$11819_Y - connect \$7 $not$libresoc.v:184501$11820_Y + connect \$9 $or$libresoc.v:184245$11810_Y + connect \$1 $not$libresoc.v:184246$11811_Y + connect \$3 $and$libresoc.v:184247$11812_Y + connect \$5 $or$libresoc.v:184248$11813_Y + connect \$7 $not$libresoc.v:184249$11814_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:184520.1-184569.10" +attribute \src "libresoc.v:184268.1-184317.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" attribute \generator "nMigen" module \reset_l$131 - attribute \src "libresoc.v:184521.7-184521.20" + attribute \src "libresoc.v:184269.7-184269.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184557.3-184565.6" - wire $0\q_int$next[0:0]$11834 - attribute \src "libresoc.v:184555.3-184556.27" + attribute \src "libresoc.v:184305.3-184313.6" + wire $0\q_int$next[0:0]$11828 + attribute \src "libresoc.v:184303.3-184304.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184557.3-184565.6" - wire $1\q_int$next[0:0]$11835 - attribute \src "libresoc.v:184537.7-184537.19" + attribute \src "libresoc.v:184305.3-184313.6" + wire $1\q_int$next[0:0]$11829 + attribute \src "libresoc.v:184285.7-184285.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184552.17-184552.96" - wire $and$libresoc.v:184552$11829_Y - attribute \src "libresoc.v:184551.17-184551.94" - wire $not$libresoc.v:184551$11828_Y - attribute \src "libresoc.v:184554.17-184554.94" - wire $not$libresoc.v:184554$11831_Y - attribute \src "libresoc.v:184550.17-184550.100" - wire $or$libresoc.v:184550$11827_Y - attribute \src "libresoc.v:184553.17-184553.99" - wire $or$libresoc.v:184553$11830_Y + attribute \src "libresoc.v:184300.17-184300.96" + wire $and$libresoc.v:184300$11823_Y + attribute \src "libresoc.v:184299.17-184299.94" + wire $not$libresoc.v:184299$11822_Y + attribute \src "libresoc.v:184302.17-184302.94" + wire $not$libresoc.v:184302$11825_Y + attribute \src "libresoc.v:184298.17-184298.100" + wire $or$libresoc.v:184298$11821_Y + attribute \src "libresoc.v:184301.17-184301.99" + wire $or$libresoc.v:184301$11824_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -345385,11 +345091,11 @@ module \reset_l$131 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:184521.7-184521.15" + attribute \src "libresoc.v:184269.7-184269.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -345406,7 +345112,7 @@ module \reset_l$131 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184552$11829 + cell $and $and$libresoc.v:184300$11823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -345414,26 +345120,26 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184552$11829_Y + connect \Y $and$libresoc.v:184300$11823_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184551$11828 + cell $not $not$libresoc.v:184299$11822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:184551$11828_Y + connect \Y $not$libresoc.v:184299$11822_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184554$11831 + cell $not $not$libresoc.v:184302$11825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:184554$11831_Y + connect \Y $not$libresoc.v:184302$11825_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184550$11827 + cell $or $or$libresoc.v:184298$11821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -345441,10 +345147,10 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:184550$11827_Y + connect \Y $or$libresoc.v:184298$11821_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184553$11830 + cell $or $or$libresoc.v:184301$11824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -345452,39 +345158,39 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:184553$11830_Y + connect \Y $or$libresoc.v:184301$11824_Y end - attribute \src "libresoc.v:184521.7-184521.20" - process $proc$libresoc.v:184521$11836 + attribute \src "libresoc.v:184269.7-184269.20" + process $proc$libresoc.v:184269$11830 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184537.7-184537.19" - process $proc$libresoc.v:184537$11837 + attribute \src "libresoc.v:184285.7-184285.19" + process $proc$libresoc.v:184285$11831 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184555.3-184556.27" - process $proc$libresoc.v:184555$11832 + attribute \src "libresoc.v:184303.3-184304.27" + process $proc$libresoc.v:184303$11826 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184557.3-184565.6" - process $proc$libresoc.v:184557$11833 + attribute \src "libresoc.v:184305.3-184313.6" + process $proc$libresoc.v:184305$11827 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11834 $1\q_int$next[0:0]$11835 - attribute \src "libresoc.v:184558.5-184558.29" + assign $0\q_int$next[0:0]$11828 $1\q_int$next[0:0]$11829 + attribute \src "libresoc.v:184306.5-184306.29" switch \initial - attribute \src "libresoc.v:184558.9-184558.17" + attribute \src "libresoc.v:184306.9-184306.17" case 1'1 case end @@ -345493,287 +345199,287 @@ module \reset_l$131 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11835 1'0 + assign $1\q_int$next[0:0]$11829 1'0 case - assign $1\q_int$next[0:0]$11835 \$5 + assign $1\q_int$next[0:0]$11829 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11834 + update \q_int$next $0\q_int$next[0:0]$11828 end - connect \$9 $or$libresoc.v:184550$11827_Y - connect \$1 $not$libresoc.v:184551$11828_Y - connect \$3 $and$libresoc.v:184552$11829_Y - connect \$5 $or$libresoc.v:184553$11830_Y - connect \$7 $not$libresoc.v:184554$11831_Y + connect \$9 $or$libresoc.v:184298$11821_Y + connect \$1 $not$libresoc.v:184299$11822_Y + connect \$3 $and$libresoc.v:184300$11823_Y + connect \$5 $or$libresoc.v:184301$11824_Y + connect \$7 $not$libresoc.v:184302$11825_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:184573.1-185160.10" +attribute \src "libresoc.v:184321.1-184908.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" attribute \generator "nMigen" module \right_mask - attribute \src "libresoc.v:184574.7-184574.20" + attribute \src "libresoc.v:184322.7-184322.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $10\mask[9:9] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $11\mask[10:10] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $12\mask[11:11] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $13\mask[12:12] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $14\mask[13:13] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $15\mask[14:14] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $16\mask[15:15] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $17\mask[16:16] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $18\mask[17:17] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $19\mask[18:18] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $1\mask[0:0] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $20\mask[19:19] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $21\mask[20:20] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $22\mask[21:21] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $23\mask[22:22] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $24\mask[23:23] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $25\mask[24:24] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $26\mask[25:25] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $27\mask[26:26] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $28\mask[27:27] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $29\mask[28:28] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $2\mask[1:1] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $30\mask[29:29] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $31\mask[30:30] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $32\mask[31:31] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $33\mask[32:32] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $34\mask[33:33] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $35\mask[34:34] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $36\mask[35:35] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $37\mask[36:36] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $38\mask[37:37] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $39\mask[38:38] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $3\mask[2:2] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $40\mask[39:39] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $41\mask[40:40] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $42\mask[41:41] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $43\mask[42:42] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $44\mask[43:43] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $45\mask[44:44] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $46\mask[45:45] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $47\mask[46:46] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $48\mask[47:47] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $49\mask[48:48] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $4\mask[3:3] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $50\mask[49:49] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $51\mask[50:50] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $52\mask[51:51] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $53\mask[52:52] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $54\mask[53:53] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $55\mask[54:54] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $56\mask[55:55] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $57\mask[56:56] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $58\mask[57:57] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $59\mask[58:58] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $5\mask[4:4] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $60\mask[59:59] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $61\mask[60:60] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $62\mask[61:61] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $63\mask[62:62] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $64\mask[63:63] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $6\mask[5:5] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $7\mask[6:6] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $8\mask[7:7] - attribute \src "libresoc.v:184772.3-185159.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $9\mask[8:8] - attribute \src "libresoc.v:184708.17-184708.96" - wire $gt$libresoc.v:184708$11838_Y - attribute \src "libresoc.v:184709.18-184709.98" - wire $gt$libresoc.v:184709$11839_Y - attribute \src "libresoc.v:184710.19-184710.99" - wire $gt$libresoc.v:184710$11840_Y - attribute \src "libresoc.v:184711.19-184711.99" - wire $gt$libresoc.v:184711$11841_Y - attribute \src "libresoc.v:184712.19-184712.99" - wire $gt$libresoc.v:184712$11842_Y - attribute \src "libresoc.v:184713.19-184713.99" - wire $gt$libresoc.v:184713$11843_Y - attribute \src "libresoc.v:184714.19-184714.99" - wire $gt$libresoc.v:184714$11844_Y - attribute \src "libresoc.v:184715.19-184715.99" - wire $gt$libresoc.v:184715$11845_Y - attribute \src "libresoc.v:184716.19-184716.99" - wire $gt$libresoc.v:184716$11846_Y - attribute \src "libresoc.v:184717.19-184717.99" - wire $gt$libresoc.v:184717$11847_Y - attribute \src "libresoc.v:184718.19-184718.99" - wire $gt$libresoc.v:184718$11848_Y - attribute \src "libresoc.v:184719.18-184719.97" - wire $gt$libresoc.v:184719$11849_Y - attribute \src "libresoc.v:184720.19-184720.99" - wire $gt$libresoc.v:184720$11850_Y - attribute \src "libresoc.v:184721.19-184721.99" - wire $gt$libresoc.v:184721$11851_Y - attribute \src "libresoc.v:184722.19-184722.99" - wire $gt$libresoc.v:184722$11852_Y - attribute \src "libresoc.v:184723.19-184723.99" - wire $gt$libresoc.v:184723$11853_Y - attribute \src "libresoc.v:184724.19-184724.99" - wire $gt$libresoc.v:184724$11854_Y - attribute \src "libresoc.v:184725.18-184725.97" - wire $gt$libresoc.v:184725$11855_Y - attribute \src "libresoc.v:184726.18-184726.97" - wire $gt$libresoc.v:184726$11856_Y - attribute \src "libresoc.v:184727.18-184727.97" - wire $gt$libresoc.v:184727$11857_Y - attribute \src "libresoc.v:184728.17-184728.96" - wire $gt$libresoc.v:184728$11858_Y - attribute \src "libresoc.v:184729.18-184729.97" - wire $gt$libresoc.v:184729$11859_Y - attribute \src "libresoc.v:184730.18-184730.97" - wire $gt$libresoc.v:184730$11860_Y - attribute \src "libresoc.v:184731.18-184731.97" - wire $gt$libresoc.v:184731$11861_Y - attribute \src "libresoc.v:184732.18-184732.97" - wire $gt$libresoc.v:184732$11862_Y - attribute \src "libresoc.v:184733.18-184733.97" - wire $gt$libresoc.v:184733$11863_Y - attribute \src "libresoc.v:184734.18-184734.97" - wire $gt$libresoc.v:184734$11864_Y - attribute \src "libresoc.v:184735.18-184735.97" - wire $gt$libresoc.v:184735$11865_Y - attribute \src "libresoc.v:184736.18-184736.98" - wire $gt$libresoc.v:184736$11866_Y - attribute \src "libresoc.v:184737.18-184737.98" - wire $gt$libresoc.v:184737$11867_Y - attribute \src "libresoc.v:184738.18-184738.98" - wire $gt$libresoc.v:184738$11868_Y - attribute \src "libresoc.v:184739.17-184739.96" - wire $gt$libresoc.v:184739$11869_Y - attribute \src "libresoc.v:184740.18-184740.98" - wire $gt$libresoc.v:184740$11870_Y - attribute \src "libresoc.v:184741.18-184741.98" - wire $gt$libresoc.v:184741$11871_Y - attribute \src "libresoc.v:184742.18-184742.98" - wire $gt$libresoc.v:184742$11872_Y - attribute \src "libresoc.v:184743.18-184743.98" - wire $gt$libresoc.v:184743$11873_Y - attribute \src "libresoc.v:184744.18-184744.98" - wire $gt$libresoc.v:184744$11874_Y - attribute \src "libresoc.v:184745.18-184745.98" - wire $gt$libresoc.v:184745$11875_Y - attribute \src "libresoc.v:184746.18-184746.98" - wire $gt$libresoc.v:184746$11876_Y - attribute \src "libresoc.v:184747.18-184747.98" - wire $gt$libresoc.v:184747$11877_Y - attribute \src "libresoc.v:184748.18-184748.98" - wire $gt$libresoc.v:184748$11878_Y - attribute \src "libresoc.v:184749.18-184749.98" - wire $gt$libresoc.v:184749$11879_Y - attribute \src "libresoc.v:184750.17-184750.96" - wire $gt$libresoc.v:184750$11880_Y - attribute \src "libresoc.v:184751.18-184751.98" - wire $gt$libresoc.v:184751$11881_Y - attribute \src "libresoc.v:184752.18-184752.98" - wire $gt$libresoc.v:184752$11882_Y - attribute \src "libresoc.v:184753.18-184753.98" - wire $gt$libresoc.v:184753$11883_Y - attribute \src "libresoc.v:184754.18-184754.98" - wire $gt$libresoc.v:184754$11884_Y - attribute \src "libresoc.v:184755.18-184755.98" - wire $gt$libresoc.v:184755$11885_Y - attribute \src "libresoc.v:184756.18-184756.98" - wire $gt$libresoc.v:184756$11886_Y - attribute \src "libresoc.v:184757.18-184757.98" - wire $gt$libresoc.v:184757$11887_Y - attribute \src "libresoc.v:184758.18-184758.98" - wire $gt$libresoc.v:184758$11888_Y - attribute \src "libresoc.v:184759.18-184759.98" - wire $gt$libresoc.v:184759$11889_Y - attribute \src "libresoc.v:184760.18-184760.98" - wire $gt$libresoc.v:184760$11890_Y - attribute \src "libresoc.v:184761.17-184761.96" - wire $gt$libresoc.v:184761$11891_Y - attribute \src "libresoc.v:184762.18-184762.98" - wire $gt$libresoc.v:184762$11892_Y - attribute \src "libresoc.v:184763.18-184763.98" - wire $gt$libresoc.v:184763$11893_Y - attribute \src "libresoc.v:184764.18-184764.98" - wire $gt$libresoc.v:184764$11894_Y - attribute \src "libresoc.v:184765.18-184765.98" - wire $gt$libresoc.v:184765$11895_Y - attribute \src "libresoc.v:184766.18-184766.98" - wire $gt$libresoc.v:184766$11896_Y - attribute \src "libresoc.v:184767.18-184767.98" - wire $gt$libresoc.v:184767$11897_Y - attribute \src "libresoc.v:184768.18-184768.98" - wire $gt$libresoc.v:184768$11898_Y - attribute \src "libresoc.v:184769.18-184769.98" - wire $gt$libresoc.v:184769$11899_Y - attribute \src "libresoc.v:184770.18-184770.98" - wire $gt$libresoc.v:184770$11900_Y - attribute \src "libresoc.v:184771.18-184771.98" - wire $gt$libresoc.v:184771$11901_Y + attribute \src "libresoc.v:184456.17-184456.96" + wire $gt$libresoc.v:184456$11832_Y + attribute \src "libresoc.v:184457.18-184457.98" + wire $gt$libresoc.v:184457$11833_Y + attribute \src "libresoc.v:184458.19-184458.99" + wire $gt$libresoc.v:184458$11834_Y + attribute \src "libresoc.v:184459.19-184459.99" + wire $gt$libresoc.v:184459$11835_Y + attribute \src "libresoc.v:184460.19-184460.99" + wire $gt$libresoc.v:184460$11836_Y + attribute \src "libresoc.v:184461.19-184461.99" + wire $gt$libresoc.v:184461$11837_Y + attribute \src "libresoc.v:184462.19-184462.99" + wire $gt$libresoc.v:184462$11838_Y + attribute \src "libresoc.v:184463.19-184463.99" + wire $gt$libresoc.v:184463$11839_Y + attribute \src "libresoc.v:184464.19-184464.99" + wire $gt$libresoc.v:184464$11840_Y + attribute \src "libresoc.v:184465.19-184465.99" + wire $gt$libresoc.v:184465$11841_Y + attribute \src "libresoc.v:184466.19-184466.99" + wire $gt$libresoc.v:184466$11842_Y + attribute \src "libresoc.v:184467.18-184467.97" + wire $gt$libresoc.v:184467$11843_Y + attribute \src "libresoc.v:184468.19-184468.99" + wire $gt$libresoc.v:184468$11844_Y + attribute \src "libresoc.v:184469.19-184469.99" + wire $gt$libresoc.v:184469$11845_Y + attribute \src "libresoc.v:184470.19-184470.99" + wire $gt$libresoc.v:184470$11846_Y + attribute \src "libresoc.v:184471.19-184471.99" + wire $gt$libresoc.v:184471$11847_Y + attribute \src "libresoc.v:184472.19-184472.99" + wire $gt$libresoc.v:184472$11848_Y + attribute \src "libresoc.v:184473.18-184473.97" + wire $gt$libresoc.v:184473$11849_Y + attribute \src "libresoc.v:184474.18-184474.97" + wire $gt$libresoc.v:184474$11850_Y + attribute \src "libresoc.v:184475.18-184475.97" + wire $gt$libresoc.v:184475$11851_Y + attribute \src "libresoc.v:184476.17-184476.96" + wire $gt$libresoc.v:184476$11852_Y + attribute \src "libresoc.v:184477.18-184477.97" + wire $gt$libresoc.v:184477$11853_Y + attribute \src "libresoc.v:184478.18-184478.97" + wire $gt$libresoc.v:184478$11854_Y + attribute \src "libresoc.v:184479.18-184479.97" + wire $gt$libresoc.v:184479$11855_Y + attribute \src "libresoc.v:184480.18-184480.97" + wire $gt$libresoc.v:184480$11856_Y + attribute \src "libresoc.v:184481.18-184481.97" + wire $gt$libresoc.v:184481$11857_Y + attribute \src "libresoc.v:184482.18-184482.97" + wire $gt$libresoc.v:184482$11858_Y + attribute \src "libresoc.v:184483.18-184483.97" + wire $gt$libresoc.v:184483$11859_Y + attribute \src "libresoc.v:184484.18-184484.98" + wire $gt$libresoc.v:184484$11860_Y + attribute \src "libresoc.v:184485.18-184485.98" + wire $gt$libresoc.v:184485$11861_Y + attribute \src "libresoc.v:184486.18-184486.98" + wire $gt$libresoc.v:184486$11862_Y + attribute \src "libresoc.v:184487.17-184487.96" + wire $gt$libresoc.v:184487$11863_Y + attribute \src "libresoc.v:184488.18-184488.98" + wire $gt$libresoc.v:184488$11864_Y + attribute \src "libresoc.v:184489.18-184489.98" + wire $gt$libresoc.v:184489$11865_Y + attribute \src "libresoc.v:184490.18-184490.98" + wire $gt$libresoc.v:184490$11866_Y + attribute \src "libresoc.v:184491.18-184491.98" + wire $gt$libresoc.v:184491$11867_Y + attribute \src "libresoc.v:184492.18-184492.98" + wire $gt$libresoc.v:184492$11868_Y + attribute \src "libresoc.v:184493.18-184493.98" + wire $gt$libresoc.v:184493$11869_Y + attribute \src "libresoc.v:184494.18-184494.98" + wire $gt$libresoc.v:184494$11870_Y + attribute \src "libresoc.v:184495.18-184495.98" + wire $gt$libresoc.v:184495$11871_Y + attribute \src "libresoc.v:184496.18-184496.98" + wire $gt$libresoc.v:184496$11872_Y + attribute \src "libresoc.v:184497.18-184497.98" + wire $gt$libresoc.v:184497$11873_Y + attribute \src "libresoc.v:184498.17-184498.96" + wire $gt$libresoc.v:184498$11874_Y + attribute \src "libresoc.v:184499.18-184499.98" + wire $gt$libresoc.v:184499$11875_Y + attribute \src "libresoc.v:184500.18-184500.98" + wire $gt$libresoc.v:184500$11876_Y + attribute \src "libresoc.v:184501.18-184501.98" + wire $gt$libresoc.v:184501$11877_Y + attribute \src "libresoc.v:184502.18-184502.98" + wire $gt$libresoc.v:184502$11878_Y + attribute \src "libresoc.v:184503.18-184503.98" + wire $gt$libresoc.v:184503$11879_Y + attribute \src "libresoc.v:184504.18-184504.98" + wire $gt$libresoc.v:184504$11880_Y + attribute \src "libresoc.v:184505.18-184505.98" + wire $gt$libresoc.v:184505$11881_Y + attribute \src "libresoc.v:184506.18-184506.98" + wire $gt$libresoc.v:184506$11882_Y + attribute \src "libresoc.v:184507.18-184507.98" + wire $gt$libresoc.v:184507$11883_Y + attribute \src "libresoc.v:184508.18-184508.98" + wire $gt$libresoc.v:184508$11884_Y + attribute \src "libresoc.v:184509.17-184509.96" + wire $gt$libresoc.v:184509$11885_Y + attribute \src "libresoc.v:184510.18-184510.98" + wire $gt$libresoc.v:184510$11886_Y + attribute \src "libresoc.v:184511.18-184511.98" + wire $gt$libresoc.v:184511$11887_Y + attribute \src "libresoc.v:184512.18-184512.98" + wire $gt$libresoc.v:184512$11888_Y + attribute \src "libresoc.v:184513.18-184513.98" + wire $gt$libresoc.v:184513$11889_Y + attribute \src "libresoc.v:184514.18-184514.98" + wire $gt$libresoc.v:184514$11890_Y + attribute \src "libresoc.v:184515.18-184515.98" + wire $gt$libresoc.v:184515$11891_Y + attribute \src "libresoc.v:184516.18-184516.98" + wire $gt$libresoc.v:184516$11892_Y + attribute \src "libresoc.v:184517.18-184517.98" + wire $gt$libresoc.v:184517$11893_Y + attribute \src "libresoc.v:184518.18-184518.98" + wire $gt$libresoc.v:184518$11894_Y + attribute \src "libresoc.v:184519.18-184519.98" + wire $gt$libresoc.v:184519$11895_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -345902,14 +345608,14 @@ module \right_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:184574.7-184574.15" + attribute \src "libresoc.v:184322.7-184322.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184708$11838 + cell $gt $gt$libresoc.v:184456$11832 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -345917,10 +345623,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:184708$11838_Y + connect \Y $gt$libresoc.v:184456$11832_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184709$11839 + cell $gt $gt$libresoc.v:184457$11833 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -345928,10 +345634,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:184709$11839_Y + connect \Y $gt$libresoc.v:184457$11833_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184710$11840 + cell $gt $gt$libresoc.v:184458$11834 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -345939,10 +345645,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:184710$11840_Y + connect \Y $gt$libresoc.v:184458$11834_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184711$11841 + cell $gt $gt$libresoc.v:184459$11835 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -345950,10 +345656,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:184711$11841_Y + connect \Y $gt$libresoc.v:184459$11835_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184712$11842 + cell $gt $gt$libresoc.v:184460$11836 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -345961,10 +345667,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:184712$11842_Y + connect \Y $gt$libresoc.v:184460$11836_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184713$11843 + cell $gt $gt$libresoc.v:184461$11837 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -345972,10 +345678,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:184713$11843_Y + connect \Y $gt$libresoc.v:184461$11837_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184714$11844 + cell $gt $gt$libresoc.v:184462$11838 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -345983,10 +345689,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:184714$11844_Y + connect \Y $gt$libresoc.v:184462$11838_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184715$11845 + cell $gt $gt$libresoc.v:184463$11839 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -345994,10 +345700,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:184715$11845_Y + connect \Y $gt$libresoc.v:184463$11839_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184716$11846 + cell $gt $gt$libresoc.v:184464$11840 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346005,10 +345711,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:184716$11846_Y + connect \Y $gt$libresoc.v:184464$11840_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184717$11847 + cell $gt $gt$libresoc.v:184465$11841 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346016,10 +345722,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:184717$11847_Y + connect \Y $gt$libresoc.v:184465$11841_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184718$11848 + cell $gt $gt$libresoc.v:184466$11842 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346027,10 +345733,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:184718$11848_Y + connect \Y $gt$libresoc.v:184466$11842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184719$11849 + cell $gt $gt$libresoc.v:184467$11843 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346038,10 +345744,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:184719$11849_Y + connect \Y $gt$libresoc.v:184467$11843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184720$11850 + cell $gt $gt$libresoc.v:184468$11844 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346049,10 +345755,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:184720$11850_Y + connect \Y $gt$libresoc.v:184468$11844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184721$11851 + cell $gt $gt$libresoc.v:184469$11845 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346060,10 +345766,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:184721$11851_Y + connect \Y $gt$libresoc.v:184469$11845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184722$11852 + cell $gt $gt$libresoc.v:184470$11846 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346071,10 +345777,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:184722$11852_Y + connect \Y $gt$libresoc.v:184470$11846_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184723$11853 + cell $gt $gt$libresoc.v:184471$11847 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346082,10 +345788,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:184723$11853_Y + connect \Y $gt$libresoc.v:184471$11847_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184724$11854 + cell $gt $gt$libresoc.v:184472$11848 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346093,10 +345799,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:184724$11854_Y + connect \Y $gt$libresoc.v:184472$11848_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184725$11855 + cell $gt $gt$libresoc.v:184473$11849 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346104,10 +345810,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:184725$11855_Y + connect \Y $gt$libresoc.v:184473$11849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184726$11856 + cell $gt $gt$libresoc.v:184474$11850 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346115,10 +345821,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:184726$11856_Y + connect \Y $gt$libresoc.v:184474$11850_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184727$11857 + cell $gt $gt$libresoc.v:184475$11851 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346126,10 +345832,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:184727$11857_Y + connect \Y $gt$libresoc.v:184475$11851_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184728$11858 + cell $gt $gt$libresoc.v:184476$11852 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346137,10 +345843,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:184728$11858_Y + connect \Y $gt$libresoc.v:184476$11852_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184729$11859 + cell $gt $gt$libresoc.v:184477$11853 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346148,10 +345854,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:184729$11859_Y + connect \Y $gt$libresoc.v:184477$11853_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184730$11860 + cell $gt $gt$libresoc.v:184478$11854 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346159,10 +345865,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:184730$11860_Y + connect \Y $gt$libresoc.v:184478$11854_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184731$11861 + cell $gt $gt$libresoc.v:184479$11855 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346170,10 +345876,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:184731$11861_Y + connect \Y $gt$libresoc.v:184479$11855_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184732$11862 + cell $gt $gt$libresoc.v:184480$11856 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346181,10 +345887,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:184732$11862_Y + connect \Y $gt$libresoc.v:184480$11856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184733$11863 + cell $gt $gt$libresoc.v:184481$11857 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346192,10 +345898,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:184733$11863_Y + connect \Y $gt$libresoc.v:184481$11857_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184734$11864 + cell $gt $gt$libresoc.v:184482$11858 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346203,10 +345909,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:184734$11864_Y + connect \Y $gt$libresoc.v:184482$11858_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184735$11865 + cell $gt $gt$libresoc.v:184483$11859 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346214,10 +345920,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:184735$11865_Y + connect \Y $gt$libresoc.v:184483$11859_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184736$11866 + cell $gt $gt$libresoc.v:184484$11860 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346225,10 +345931,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:184736$11866_Y + connect \Y $gt$libresoc.v:184484$11860_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184737$11867 + cell $gt $gt$libresoc.v:184485$11861 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346236,10 +345942,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:184737$11867_Y + connect \Y $gt$libresoc.v:184485$11861_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184738$11868 + cell $gt $gt$libresoc.v:184486$11862 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346247,10 +345953,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:184738$11868_Y + connect \Y $gt$libresoc.v:184486$11862_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184739$11869 + cell $gt $gt$libresoc.v:184487$11863 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346258,10 +345964,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:184739$11869_Y + connect \Y $gt$libresoc.v:184487$11863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184740$11870 + cell $gt $gt$libresoc.v:184488$11864 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346269,10 +345975,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:184740$11870_Y + connect \Y $gt$libresoc.v:184488$11864_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184741$11871 + cell $gt $gt$libresoc.v:184489$11865 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346280,10 +345986,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:184741$11871_Y + connect \Y $gt$libresoc.v:184489$11865_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184742$11872 + cell $gt $gt$libresoc.v:184490$11866 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346291,10 +345997,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:184742$11872_Y + connect \Y $gt$libresoc.v:184490$11866_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184743$11873 + cell $gt $gt$libresoc.v:184491$11867 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346302,10 +346008,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:184743$11873_Y + connect \Y $gt$libresoc.v:184491$11867_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184744$11874 + cell $gt $gt$libresoc.v:184492$11868 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346313,10 +346019,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:184744$11874_Y + connect \Y $gt$libresoc.v:184492$11868_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184745$11875 + cell $gt $gt$libresoc.v:184493$11869 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346324,10 +346030,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:184745$11875_Y + connect \Y $gt$libresoc.v:184493$11869_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184746$11876 + cell $gt $gt$libresoc.v:184494$11870 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346335,10 +346041,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:184746$11876_Y + connect \Y $gt$libresoc.v:184494$11870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184747$11877 + cell $gt $gt$libresoc.v:184495$11871 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346346,10 +346052,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:184747$11877_Y + connect \Y $gt$libresoc.v:184495$11871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184748$11878 + cell $gt $gt$libresoc.v:184496$11872 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346357,10 +346063,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:184748$11878_Y + connect \Y $gt$libresoc.v:184496$11872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184749$11879 + cell $gt $gt$libresoc.v:184497$11873 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346368,10 +346074,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:184749$11879_Y + connect \Y $gt$libresoc.v:184497$11873_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184750$11880 + cell $gt $gt$libresoc.v:184498$11874 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346379,10 +346085,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:184750$11880_Y + connect \Y $gt$libresoc.v:184498$11874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184751$11881 + cell $gt $gt$libresoc.v:184499$11875 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346390,10 +346096,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:184751$11881_Y + connect \Y $gt$libresoc.v:184499$11875_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184752$11882 + cell $gt $gt$libresoc.v:184500$11876 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346401,10 +346107,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:184752$11882_Y + connect \Y $gt$libresoc.v:184500$11876_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184753$11883 + cell $gt $gt$libresoc.v:184501$11877 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346412,10 +346118,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:184753$11883_Y + connect \Y $gt$libresoc.v:184501$11877_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184754$11884 + cell $gt $gt$libresoc.v:184502$11878 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346423,10 +346129,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:184754$11884_Y + connect \Y $gt$libresoc.v:184502$11878_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184755$11885 + cell $gt $gt$libresoc.v:184503$11879 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346434,10 +346140,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:184755$11885_Y + connect \Y $gt$libresoc.v:184503$11879_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184756$11886 + cell $gt $gt$libresoc.v:184504$11880 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346445,10 +346151,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:184756$11886_Y + connect \Y $gt$libresoc.v:184504$11880_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184757$11887 + cell $gt $gt$libresoc.v:184505$11881 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346456,10 +346162,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:184757$11887_Y + connect \Y $gt$libresoc.v:184505$11881_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184758$11888 + cell $gt $gt$libresoc.v:184506$11882 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346467,10 +346173,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:184758$11888_Y + connect \Y $gt$libresoc.v:184506$11882_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184759$11889 + cell $gt $gt$libresoc.v:184507$11883 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346478,10 +346184,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:184759$11889_Y + connect \Y $gt$libresoc.v:184507$11883_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184760$11890 + cell $gt $gt$libresoc.v:184508$11884 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346489,10 +346195,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:184760$11890_Y + connect \Y $gt$libresoc.v:184508$11884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184761$11891 + cell $gt $gt$libresoc.v:184509$11885 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346500,10 +346206,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:184761$11891_Y + connect \Y $gt$libresoc.v:184509$11885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184762$11892 + cell $gt $gt$libresoc.v:184510$11886 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346511,10 +346217,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:184762$11892_Y + connect \Y $gt$libresoc.v:184510$11886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184763$11893 + cell $gt $gt$libresoc.v:184511$11887 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346522,10 +346228,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:184763$11893_Y + connect \Y $gt$libresoc.v:184511$11887_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184764$11894 + cell $gt $gt$libresoc.v:184512$11888 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346533,10 +346239,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:184764$11894_Y + connect \Y $gt$libresoc.v:184512$11888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184765$11895 + cell $gt $gt$libresoc.v:184513$11889 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346544,10 +346250,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:184765$11895_Y + connect \Y $gt$libresoc.v:184513$11889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184766$11896 + cell $gt $gt$libresoc.v:184514$11890 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346555,10 +346261,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:184766$11896_Y + connect \Y $gt$libresoc.v:184514$11890_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184767$11897 + cell $gt $gt$libresoc.v:184515$11891 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346566,10 +346272,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:184767$11897_Y + connect \Y $gt$libresoc.v:184515$11891_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184768$11898 + cell $gt $gt$libresoc.v:184516$11892 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346577,10 +346283,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:184768$11898_Y + connect \Y $gt$libresoc.v:184516$11892_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184769$11899 + cell $gt $gt$libresoc.v:184517$11893 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346588,10 +346294,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:184769$11899_Y + connect \Y $gt$libresoc.v:184517$11893_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184770$11900 + cell $gt $gt$libresoc.v:184518$11894 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346599,10 +346305,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:184770$11900_Y + connect \Y $gt$libresoc.v:184518$11894_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184771$11901 + cell $gt $gt$libresoc.v:184519$11895 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -346610,18 +346316,18 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:184771$11901_Y + connect \Y $gt$libresoc.v:184519$11895_Y end - attribute \src "libresoc.v:184574.7-184574.20" - process $proc$libresoc.v:184574$11903 + attribute \src "libresoc.v:184322.7-184322.20" + process $proc$libresoc.v:184322$11897 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184772.3-185159.6" - process $proc$libresoc.v:184772$11902 + attribute \src "libresoc.v:184520.3-184907.6" + process $proc$libresoc.v:184520$11896 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -346688,9 +346394,9 @@ module \right_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:184773.5-184773.29" + attribute \src "libresoc.v:184521.5-184521.29" switch \initial - attribute \src "libresoc.v:184773.9-184773.17" + attribute \src "libresoc.v:184521.9-184521.17" case 1'1 case end @@ -347273,102 +346979,102 @@ module \right_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:184708$11838_Y - connect \$99 $gt$libresoc.v:184709$11839_Y - connect \$101 $gt$libresoc.v:184710$11840_Y - connect \$103 $gt$libresoc.v:184711$11841_Y - connect \$105 $gt$libresoc.v:184712$11842_Y - connect \$107 $gt$libresoc.v:184713$11843_Y - connect \$109 $gt$libresoc.v:184714$11844_Y - connect \$111 $gt$libresoc.v:184715$11845_Y - connect \$113 $gt$libresoc.v:184716$11846_Y - connect \$115 $gt$libresoc.v:184717$11847_Y - connect \$117 $gt$libresoc.v:184718$11848_Y - connect \$11 $gt$libresoc.v:184719$11849_Y - connect \$119 $gt$libresoc.v:184720$11850_Y - connect \$121 $gt$libresoc.v:184721$11851_Y - connect \$123 $gt$libresoc.v:184722$11852_Y - connect \$125 $gt$libresoc.v:184723$11853_Y - connect \$127 $gt$libresoc.v:184724$11854_Y - connect \$13 $gt$libresoc.v:184725$11855_Y - connect \$15 $gt$libresoc.v:184726$11856_Y - connect \$17 $gt$libresoc.v:184727$11857_Y - connect \$1 $gt$libresoc.v:184728$11858_Y - connect \$19 $gt$libresoc.v:184729$11859_Y - connect \$21 $gt$libresoc.v:184730$11860_Y - connect \$23 $gt$libresoc.v:184731$11861_Y - connect \$25 $gt$libresoc.v:184732$11862_Y - connect \$27 $gt$libresoc.v:184733$11863_Y - connect \$29 $gt$libresoc.v:184734$11864_Y - connect \$31 $gt$libresoc.v:184735$11865_Y - connect \$33 $gt$libresoc.v:184736$11866_Y - connect \$35 $gt$libresoc.v:184737$11867_Y - connect \$37 $gt$libresoc.v:184738$11868_Y - connect \$3 $gt$libresoc.v:184739$11869_Y - connect \$39 $gt$libresoc.v:184740$11870_Y - connect \$41 $gt$libresoc.v:184741$11871_Y - connect \$43 $gt$libresoc.v:184742$11872_Y - connect \$45 $gt$libresoc.v:184743$11873_Y - connect \$47 $gt$libresoc.v:184744$11874_Y - connect \$49 $gt$libresoc.v:184745$11875_Y - connect \$51 $gt$libresoc.v:184746$11876_Y - connect \$53 $gt$libresoc.v:184747$11877_Y - connect \$55 $gt$libresoc.v:184748$11878_Y - connect \$57 $gt$libresoc.v:184749$11879_Y - connect \$5 $gt$libresoc.v:184750$11880_Y - connect \$59 $gt$libresoc.v:184751$11881_Y - connect \$61 $gt$libresoc.v:184752$11882_Y - connect \$63 $gt$libresoc.v:184753$11883_Y - connect \$65 $gt$libresoc.v:184754$11884_Y - connect \$67 $gt$libresoc.v:184755$11885_Y - connect \$69 $gt$libresoc.v:184756$11886_Y - connect \$71 $gt$libresoc.v:184757$11887_Y - connect \$73 $gt$libresoc.v:184758$11888_Y - connect \$75 $gt$libresoc.v:184759$11889_Y - connect \$77 $gt$libresoc.v:184760$11890_Y - connect \$7 $gt$libresoc.v:184761$11891_Y - connect \$79 $gt$libresoc.v:184762$11892_Y - connect \$81 $gt$libresoc.v:184763$11893_Y - connect \$83 $gt$libresoc.v:184764$11894_Y - connect \$85 $gt$libresoc.v:184765$11895_Y - connect \$87 $gt$libresoc.v:184766$11896_Y - connect \$89 $gt$libresoc.v:184767$11897_Y - connect \$91 $gt$libresoc.v:184768$11898_Y - connect \$93 $gt$libresoc.v:184769$11899_Y - connect \$95 $gt$libresoc.v:184770$11900_Y - connect \$97 $gt$libresoc.v:184771$11901_Y + connect \$9 $gt$libresoc.v:184456$11832_Y + connect \$99 $gt$libresoc.v:184457$11833_Y + connect \$101 $gt$libresoc.v:184458$11834_Y + connect \$103 $gt$libresoc.v:184459$11835_Y + connect \$105 $gt$libresoc.v:184460$11836_Y + connect \$107 $gt$libresoc.v:184461$11837_Y + connect \$109 $gt$libresoc.v:184462$11838_Y + connect \$111 $gt$libresoc.v:184463$11839_Y + connect \$113 $gt$libresoc.v:184464$11840_Y + connect \$115 $gt$libresoc.v:184465$11841_Y + connect \$117 $gt$libresoc.v:184466$11842_Y + connect \$11 $gt$libresoc.v:184467$11843_Y + connect \$119 $gt$libresoc.v:184468$11844_Y + connect \$121 $gt$libresoc.v:184469$11845_Y + connect \$123 $gt$libresoc.v:184470$11846_Y + connect \$125 $gt$libresoc.v:184471$11847_Y + connect \$127 $gt$libresoc.v:184472$11848_Y + connect \$13 $gt$libresoc.v:184473$11849_Y + connect \$15 $gt$libresoc.v:184474$11850_Y + connect \$17 $gt$libresoc.v:184475$11851_Y + connect \$1 $gt$libresoc.v:184476$11852_Y + connect \$19 $gt$libresoc.v:184477$11853_Y + connect \$21 $gt$libresoc.v:184478$11854_Y + connect \$23 $gt$libresoc.v:184479$11855_Y + connect \$25 $gt$libresoc.v:184480$11856_Y + connect \$27 $gt$libresoc.v:184481$11857_Y + connect \$29 $gt$libresoc.v:184482$11858_Y + connect \$31 $gt$libresoc.v:184483$11859_Y + connect \$33 $gt$libresoc.v:184484$11860_Y + connect \$35 $gt$libresoc.v:184485$11861_Y + connect \$37 $gt$libresoc.v:184486$11862_Y + connect \$3 $gt$libresoc.v:184487$11863_Y + connect \$39 $gt$libresoc.v:184488$11864_Y + connect \$41 $gt$libresoc.v:184489$11865_Y + connect \$43 $gt$libresoc.v:184490$11866_Y + connect \$45 $gt$libresoc.v:184491$11867_Y + connect \$47 $gt$libresoc.v:184492$11868_Y + connect \$49 $gt$libresoc.v:184493$11869_Y + connect \$51 $gt$libresoc.v:184494$11870_Y + connect \$53 $gt$libresoc.v:184495$11871_Y + connect \$55 $gt$libresoc.v:184496$11872_Y + connect \$57 $gt$libresoc.v:184497$11873_Y + connect \$5 $gt$libresoc.v:184498$11874_Y + connect \$59 $gt$libresoc.v:184499$11875_Y + connect \$61 $gt$libresoc.v:184500$11876_Y + connect \$63 $gt$libresoc.v:184501$11877_Y + connect \$65 $gt$libresoc.v:184502$11878_Y + connect \$67 $gt$libresoc.v:184503$11879_Y + connect \$69 $gt$libresoc.v:184504$11880_Y + connect \$71 $gt$libresoc.v:184505$11881_Y + connect \$73 $gt$libresoc.v:184506$11882_Y + connect \$75 $gt$libresoc.v:184507$11883_Y + connect \$77 $gt$libresoc.v:184508$11884_Y + connect \$7 $gt$libresoc.v:184509$11885_Y + connect \$79 $gt$libresoc.v:184510$11886_Y + connect \$81 $gt$libresoc.v:184511$11887_Y + connect \$83 $gt$libresoc.v:184512$11888_Y + connect \$85 $gt$libresoc.v:184513$11889_Y + connect \$87 $gt$libresoc.v:184514$11890_Y + connect \$89 $gt$libresoc.v:184515$11891_Y + connect \$91 $gt$libresoc.v:184516$11892_Y + connect \$93 $gt$libresoc.v:184517$11893_Y + connect \$95 $gt$libresoc.v:184518$11894_Y + connect \$97 $gt$libresoc.v:184519$11895_Y end -attribute \src "libresoc.v:185164.1-185222.10" +attribute \src "libresoc.v:184912.1-184970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" attribute \generator "nMigen" module \rok_l - attribute \src "libresoc.v:185165.7-185165.20" + attribute \src "libresoc.v:184913.7-184913.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185210.3-185218.6" - wire $0\q_int$next[0:0]$11914 - attribute \src "libresoc.v:185208.3-185209.27" + attribute \src "libresoc.v:184958.3-184966.6" + wire $0\q_int$next[0:0]$11908 + attribute \src "libresoc.v:184956.3-184957.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185210.3-185218.6" - wire $1\q_int$next[0:0]$11915 - attribute \src "libresoc.v:185187.7-185187.19" + attribute \src "libresoc.v:184958.3-184966.6" + wire $1\q_int$next[0:0]$11909 + attribute \src "libresoc.v:184935.7-184935.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185200.17-185200.96" - wire $and$libresoc.v:185200$11904_Y - attribute \src "libresoc.v:185205.17-185205.96" - wire $and$libresoc.v:185205$11909_Y - attribute \src "libresoc.v:185202.18-185202.94" - wire $not$libresoc.v:185202$11906_Y - attribute \src "libresoc.v:185204.17-185204.93" - wire $not$libresoc.v:185204$11908_Y - attribute \src "libresoc.v:185207.17-185207.93" - wire $not$libresoc.v:185207$11911_Y - attribute \src "libresoc.v:185201.18-185201.99" - wire $or$libresoc.v:185201$11905_Y - attribute \src "libresoc.v:185203.18-185203.100" - wire $or$libresoc.v:185203$11907_Y - attribute \src "libresoc.v:185206.17-185206.98" - wire $or$libresoc.v:185206$11910_Y + attribute \src "libresoc.v:184948.17-184948.96" + wire $and$libresoc.v:184948$11898_Y + attribute \src "libresoc.v:184953.17-184953.96" + wire $and$libresoc.v:184953$11903_Y + attribute \src "libresoc.v:184950.18-184950.94" + wire $not$libresoc.v:184950$11900_Y + attribute \src "libresoc.v:184952.17-184952.93" + wire $not$libresoc.v:184952$11902_Y + attribute \src "libresoc.v:184955.17-184955.93" + wire $not$libresoc.v:184955$11905_Y + attribute \src "libresoc.v:184949.18-184949.99" + wire $or$libresoc.v:184949$11899_Y + attribute \src "libresoc.v:184951.18-184951.100" + wire $or$libresoc.v:184951$11901_Y + attribute \src "libresoc.v:184954.17-184954.98" + wire $or$libresoc.v:184954$11904_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -347385,11 +347091,11 @@ module \rok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:185165.7-185165.15" + attribute \src "libresoc.v:184913.7-184913.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -347406,7 +347112,7 @@ module \rok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185200$11904 + cell $and $and$libresoc.v:184948$11898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347414,10 +347120,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185200$11904_Y + connect \Y $and$libresoc.v:184948$11898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185205$11909 + cell $and $and$libresoc.v:184953$11903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347425,34 +347131,34 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185205$11909_Y + connect \Y $and$libresoc.v:184953$11903_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185202$11906 + cell $not $not$libresoc.v:184950$11900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185202$11906_Y + connect \Y $not$libresoc.v:184950$11900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185204$11908 + cell $not $not$libresoc.v:184952$11902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185204$11908_Y + connect \Y $not$libresoc.v:184952$11902_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185207$11911 + cell $not $not$libresoc.v:184955$11905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185207$11911_Y + connect \Y $not$libresoc.v:184955$11905_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185201$11905 + cell $or $or$libresoc.v:184949$11899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347460,10 +347166,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185201$11905_Y + connect \Y $or$libresoc.v:184949$11899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185203$11907 + cell $or $or$libresoc.v:184951$11901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347471,10 +347177,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185203$11907_Y + connect \Y $or$libresoc.v:184951$11901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185206$11910 + cell $or $or$libresoc.v:184954$11904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347482,39 +347188,39 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185206$11910_Y + connect \Y $or$libresoc.v:184954$11904_Y end - attribute \src "libresoc.v:185165.7-185165.20" - process $proc$libresoc.v:185165$11916 + attribute \src "libresoc.v:184913.7-184913.20" + process $proc$libresoc.v:184913$11910 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185187.7-185187.19" - process $proc$libresoc.v:185187$11917 + attribute \src "libresoc.v:184935.7-184935.19" + process $proc$libresoc.v:184935$11911 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185208.3-185209.27" - process $proc$libresoc.v:185208$11912 + attribute \src "libresoc.v:184956.3-184957.27" + process $proc$libresoc.v:184956$11906 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185210.3-185218.6" - process $proc$libresoc.v:185210$11913 + attribute \src "libresoc.v:184958.3-184966.6" + process $proc$libresoc.v:184958$11907 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11914 $1\q_int$next[0:0]$11915 - attribute \src "libresoc.v:185211.5-185211.29" + assign $0\q_int$next[0:0]$11908 $1\q_int$next[0:0]$11909 + attribute \src "libresoc.v:184959.5-184959.29" switch \initial - attribute \src "libresoc.v:185211.9-185211.17" + attribute \src "libresoc.v:184959.9-184959.17" case 1'1 case end @@ -347523,56 +347229,56 @@ module \rok_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11915 1'0 + assign $1\q_int$next[0:0]$11909 1'0 case - assign $1\q_int$next[0:0]$11915 \$5 + assign $1\q_int$next[0:0]$11909 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11914 + update \q_int$next $0\q_int$next[0:0]$11908 end - connect \$9 $and$libresoc.v:185200$11904_Y - connect \$11 $or$libresoc.v:185201$11905_Y - connect \$13 $not$libresoc.v:185202$11906_Y - connect \$15 $or$libresoc.v:185203$11907_Y - connect \$1 $not$libresoc.v:185204$11908_Y - connect \$3 $and$libresoc.v:185205$11909_Y - connect \$5 $or$libresoc.v:185206$11910_Y - connect \$7 $not$libresoc.v:185207$11911_Y + connect \$9 $and$libresoc.v:184948$11898_Y + connect \$11 $or$libresoc.v:184949$11899_Y + connect \$13 $not$libresoc.v:184950$11900_Y + connect \$15 $or$libresoc.v:184951$11901_Y + connect \$1 $not$libresoc.v:184952$11902_Y + connect \$3 $and$libresoc.v:184953$11903_Y + connect \$5 $or$libresoc.v:184954$11904_Y + connect \$7 $not$libresoc.v:184955$11905_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185226.1-185284.10" +attribute \src "libresoc.v:184974.1-185032.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" attribute \generator "nMigen" module \rok_l$105 - attribute \src "libresoc.v:185227.7-185227.20" + attribute \src "libresoc.v:184975.7-184975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185272.3-185280.6" - wire $0\q_int$next[0:0]$11928 - attribute \src "libresoc.v:185270.3-185271.27" + attribute \src "libresoc.v:185020.3-185028.6" + wire $0\q_int$next[0:0]$11922 + attribute \src "libresoc.v:185018.3-185019.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185272.3-185280.6" - wire $1\q_int$next[0:0]$11929 - attribute \src "libresoc.v:185249.7-185249.19" + attribute \src "libresoc.v:185020.3-185028.6" + wire $1\q_int$next[0:0]$11923 + attribute \src "libresoc.v:184997.7-184997.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185262.17-185262.96" - wire $and$libresoc.v:185262$11918_Y - attribute \src "libresoc.v:185267.17-185267.96" - wire $and$libresoc.v:185267$11923_Y - attribute \src "libresoc.v:185264.18-185264.94" - wire $not$libresoc.v:185264$11920_Y - attribute \src "libresoc.v:185266.17-185266.93" - wire $not$libresoc.v:185266$11922_Y - attribute \src "libresoc.v:185269.17-185269.93" - wire $not$libresoc.v:185269$11925_Y - attribute \src "libresoc.v:185263.18-185263.99" - wire $or$libresoc.v:185263$11919_Y - attribute \src "libresoc.v:185265.18-185265.100" - wire $or$libresoc.v:185265$11921_Y - attribute \src "libresoc.v:185268.17-185268.98" - wire $or$libresoc.v:185268$11924_Y + attribute \src "libresoc.v:185010.17-185010.96" + wire $and$libresoc.v:185010$11912_Y + attribute \src "libresoc.v:185015.17-185015.96" + wire $and$libresoc.v:185015$11917_Y + attribute \src "libresoc.v:185012.18-185012.94" + wire $not$libresoc.v:185012$11914_Y + attribute \src "libresoc.v:185014.17-185014.93" + wire $not$libresoc.v:185014$11916_Y + attribute \src "libresoc.v:185017.17-185017.93" + wire $not$libresoc.v:185017$11919_Y + attribute \src "libresoc.v:185011.18-185011.99" + wire $or$libresoc.v:185011$11913_Y + attribute \src "libresoc.v:185013.18-185013.100" + wire $or$libresoc.v:185013$11915_Y + attribute \src "libresoc.v:185016.17-185016.98" + wire $or$libresoc.v:185016$11918_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -347589,11 +347295,11 @@ module \rok_l$105 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:185227.7-185227.15" + attribute \src "libresoc.v:184975.7-184975.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -347610,7 +347316,7 @@ module \rok_l$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185262$11918 + cell $and $and$libresoc.v:185010$11912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347618,10 +347324,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185262$11918_Y + connect \Y $and$libresoc.v:185010$11912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185267$11923 + cell $and $and$libresoc.v:185015$11917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347629,34 +347335,34 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185267$11923_Y + connect \Y $and$libresoc.v:185015$11917_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185264$11920 + cell $not $not$libresoc.v:185012$11914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185264$11920_Y + connect \Y $not$libresoc.v:185012$11914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185266$11922 + cell $not $not$libresoc.v:185014$11916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185266$11922_Y + connect \Y $not$libresoc.v:185014$11916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185269$11925 + cell $not $not$libresoc.v:185017$11919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185269$11925_Y + connect \Y $not$libresoc.v:185017$11919_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185263$11919 + cell $or $or$libresoc.v:185011$11913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347664,10 +347370,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185263$11919_Y + connect \Y $or$libresoc.v:185011$11913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185265$11921 + cell $or $or$libresoc.v:185013$11915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347675,10 +347381,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185265$11921_Y + connect \Y $or$libresoc.v:185013$11915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185268$11924 + cell $or $or$libresoc.v:185016$11918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347686,39 +347392,39 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185268$11924_Y + connect \Y $or$libresoc.v:185016$11918_Y end - attribute \src "libresoc.v:185227.7-185227.20" - process $proc$libresoc.v:185227$11930 + attribute \src "libresoc.v:184975.7-184975.20" + process $proc$libresoc.v:184975$11924 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185249.7-185249.19" - process $proc$libresoc.v:185249$11931 + attribute \src "libresoc.v:184997.7-184997.19" + process $proc$libresoc.v:184997$11925 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185270.3-185271.27" - process $proc$libresoc.v:185270$11926 + attribute \src "libresoc.v:185018.3-185019.27" + process $proc$libresoc.v:185018$11920 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185272.3-185280.6" - process $proc$libresoc.v:185272$11927 + attribute \src "libresoc.v:185020.3-185028.6" + process $proc$libresoc.v:185020$11921 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11928 $1\q_int$next[0:0]$11929 - attribute \src "libresoc.v:185273.5-185273.29" + assign $0\q_int$next[0:0]$11922 $1\q_int$next[0:0]$11923 + attribute \src "libresoc.v:185021.5-185021.29" switch \initial - attribute \src "libresoc.v:185273.9-185273.17" + attribute \src "libresoc.v:185021.9-185021.17" case 1'1 case end @@ -347727,56 +347433,56 @@ module \rok_l$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11929 1'0 + assign $1\q_int$next[0:0]$11923 1'0 case - assign $1\q_int$next[0:0]$11929 \$5 + assign $1\q_int$next[0:0]$11923 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11928 + update \q_int$next $0\q_int$next[0:0]$11922 end - connect \$9 $and$libresoc.v:185262$11918_Y - connect \$11 $or$libresoc.v:185263$11919_Y - connect \$13 $not$libresoc.v:185264$11920_Y - connect \$15 $or$libresoc.v:185265$11921_Y - connect \$1 $not$libresoc.v:185266$11922_Y - connect \$3 $and$libresoc.v:185267$11923_Y - connect \$5 $or$libresoc.v:185268$11924_Y - connect \$7 $not$libresoc.v:185269$11925_Y + connect \$9 $and$libresoc.v:185010$11912_Y + connect \$11 $or$libresoc.v:185011$11913_Y + connect \$13 $not$libresoc.v:185012$11914_Y + connect \$15 $or$libresoc.v:185013$11915_Y + connect \$1 $not$libresoc.v:185014$11916_Y + connect \$3 $and$libresoc.v:185015$11917_Y + connect \$5 $or$libresoc.v:185016$11918_Y + connect \$7 $not$libresoc.v:185017$11919_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185288.1-185346.10" +attribute \src "libresoc.v:185036.1-185094.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" attribute \generator "nMigen" module \rok_l$123 - attribute \src "libresoc.v:185289.7-185289.20" + attribute \src "libresoc.v:185037.7-185037.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185334.3-185342.6" - wire $0\q_int$next[0:0]$11942 - attribute \src "libresoc.v:185332.3-185333.27" + attribute \src "libresoc.v:185082.3-185090.6" + wire $0\q_int$next[0:0]$11936 + attribute \src "libresoc.v:185080.3-185081.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185334.3-185342.6" - wire $1\q_int$next[0:0]$11943 - attribute \src "libresoc.v:185311.7-185311.19" + attribute \src "libresoc.v:185082.3-185090.6" + wire $1\q_int$next[0:0]$11937 + attribute \src "libresoc.v:185059.7-185059.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185324.17-185324.96" - wire $and$libresoc.v:185324$11932_Y - attribute \src "libresoc.v:185329.17-185329.96" - wire $and$libresoc.v:185329$11937_Y - attribute \src "libresoc.v:185326.18-185326.94" - wire $not$libresoc.v:185326$11934_Y - attribute \src "libresoc.v:185328.17-185328.93" - wire $not$libresoc.v:185328$11936_Y - attribute \src "libresoc.v:185331.17-185331.93" - wire $not$libresoc.v:185331$11939_Y - attribute \src "libresoc.v:185325.18-185325.99" - wire $or$libresoc.v:185325$11933_Y - attribute \src "libresoc.v:185327.18-185327.100" - wire $or$libresoc.v:185327$11935_Y - attribute \src "libresoc.v:185330.17-185330.98" - wire $or$libresoc.v:185330$11938_Y + attribute \src "libresoc.v:185072.17-185072.96" + wire $and$libresoc.v:185072$11926_Y + attribute \src "libresoc.v:185077.17-185077.96" + wire $and$libresoc.v:185077$11931_Y + attribute \src "libresoc.v:185074.18-185074.94" + wire $not$libresoc.v:185074$11928_Y + attribute \src "libresoc.v:185076.17-185076.93" + wire $not$libresoc.v:185076$11930_Y + attribute \src "libresoc.v:185079.17-185079.93" + wire $not$libresoc.v:185079$11933_Y + attribute \src "libresoc.v:185073.18-185073.99" + wire $or$libresoc.v:185073$11927_Y + attribute \src "libresoc.v:185075.18-185075.100" + wire $or$libresoc.v:185075$11929_Y + attribute \src "libresoc.v:185078.17-185078.98" + wire $or$libresoc.v:185078$11932_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -347793,11 +347499,11 @@ module \rok_l$123 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:185289.7-185289.15" + attribute \src "libresoc.v:185037.7-185037.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -347814,7 +347520,7 @@ module \rok_l$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185324$11932 + cell $and $and$libresoc.v:185072$11926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347822,10 +347528,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185324$11932_Y + connect \Y $and$libresoc.v:185072$11926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185329$11937 + cell $and $and$libresoc.v:185077$11931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347833,34 +347539,34 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185329$11937_Y + connect \Y $and$libresoc.v:185077$11931_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185326$11934 + cell $not $not$libresoc.v:185074$11928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185326$11934_Y + connect \Y $not$libresoc.v:185074$11928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185328$11936 + cell $not $not$libresoc.v:185076$11930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185328$11936_Y + connect \Y $not$libresoc.v:185076$11930_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185331$11939 + cell $not $not$libresoc.v:185079$11933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185331$11939_Y + connect \Y $not$libresoc.v:185079$11933_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185325$11933 + cell $or $or$libresoc.v:185073$11927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347868,10 +347574,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185325$11933_Y + connect \Y $or$libresoc.v:185073$11927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185327$11935 + cell $or $or$libresoc.v:185075$11929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347879,10 +347585,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185327$11935_Y + connect \Y $or$libresoc.v:185075$11929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185330$11938 + cell $or $or$libresoc.v:185078$11932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347890,39 +347596,39 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185330$11938_Y + connect \Y $or$libresoc.v:185078$11932_Y end - attribute \src "libresoc.v:185289.7-185289.20" - process $proc$libresoc.v:185289$11944 + attribute \src "libresoc.v:185037.7-185037.20" + process $proc$libresoc.v:185037$11938 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185311.7-185311.19" - process $proc$libresoc.v:185311$11945 + attribute \src "libresoc.v:185059.7-185059.19" + process $proc$libresoc.v:185059$11939 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185332.3-185333.27" - process $proc$libresoc.v:185332$11940 + attribute \src "libresoc.v:185080.3-185081.27" + process $proc$libresoc.v:185080$11934 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185334.3-185342.6" - process $proc$libresoc.v:185334$11941 + attribute \src "libresoc.v:185082.3-185090.6" + process $proc$libresoc.v:185082$11935 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11942 $1\q_int$next[0:0]$11943 - attribute \src "libresoc.v:185335.5-185335.29" + assign $0\q_int$next[0:0]$11936 $1\q_int$next[0:0]$11937 + attribute \src "libresoc.v:185083.5-185083.29" switch \initial - attribute \src "libresoc.v:185335.9-185335.17" + attribute \src "libresoc.v:185083.9-185083.17" case 1'1 case end @@ -347931,56 +347637,56 @@ module \rok_l$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11943 1'0 + assign $1\q_int$next[0:0]$11937 1'0 case - assign $1\q_int$next[0:0]$11943 \$5 + assign $1\q_int$next[0:0]$11937 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11942 + update \q_int$next $0\q_int$next[0:0]$11936 end - connect \$9 $and$libresoc.v:185324$11932_Y - connect \$11 $or$libresoc.v:185325$11933_Y - connect \$13 $not$libresoc.v:185326$11934_Y - connect \$15 $or$libresoc.v:185327$11935_Y - connect \$1 $not$libresoc.v:185328$11936_Y - connect \$3 $and$libresoc.v:185329$11937_Y - connect \$5 $or$libresoc.v:185330$11938_Y - connect \$7 $not$libresoc.v:185331$11939_Y + connect \$9 $and$libresoc.v:185072$11926_Y + connect \$11 $or$libresoc.v:185073$11927_Y + connect \$13 $not$libresoc.v:185074$11928_Y + connect \$15 $or$libresoc.v:185075$11929_Y + connect \$1 $not$libresoc.v:185076$11930_Y + connect \$3 $and$libresoc.v:185077$11931_Y + connect \$5 $or$libresoc.v:185078$11932_Y + connect \$7 $not$libresoc.v:185079$11933_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185350.1-185408.10" +attribute \src "libresoc.v:185098.1-185156.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" attribute \generator "nMigen" module \rok_l$14 - attribute \src "libresoc.v:185351.7-185351.20" + attribute \src "libresoc.v:185099.7-185099.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185396.3-185404.6" - wire $0\q_int$next[0:0]$11956 - attribute \src "libresoc.v:185394.3-185395.27" + attribute \src "libresoc.v:185144.3-185152.6" + wire $0\q_int$next[0:0]$11950 + attribute \src "libresoc.v:185142.3-185143.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185396.3-185404.6" - wire $1\q_int$next[0:0]$11957 - attribute \src "libresoc.v:185373.7-185373.19" + attribute \src "libresoc.v:185144.3-185152.6" + wire $1\q_int$next[0:0]$11951 + attribute \src "libresoc.v:185121.7-185121.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185386.17-185386.96" - wire $and$libresoc.v:185386$11946_Y - attribute \src "libresoc.v:185391.17-185391.96" - wire $and$libresoc.v:185391$11951_Y - attribute \src "libresoc.v:185388.18-185388.94" - wire $not$libresoc.v:185388$11948_Y - attribute \src "libresoc.v:185390.17-185390.93" - wire $not$libresoc.v:185390$11950_Y - attribute \src "libresoc.v:185393.17-185393.93" - wire $not$libresoc.v:185393$11953_Y - attribute \src "libresoc.v:185387.18-185387.99" - wire $or$libresoc.v:185387$11947_Y - attribute \src "libresoc.v:185389.18-185389.100" - wire $or$libresoc.v:185389$11949_Y - attribute \src "libresoc.v:185392.17-185392.98" - wire $or$libresoc.v:185392$11952_Y + attribute \src "libresoc.v:185134.17-185134.96" + wire $and$libresoc.v:185134$11940_Y + attribute \src "libresoc.v:185139.17-185139.96" + wire $and$libresoc.v:185139$11945_Y + attribute \src "libresoc.v:185136.18-185136.94" + wire $not$libresoc.v:185136$11942_Y + attribute \src "libresoc.v:185138.17-185138.93" + wire $not$libresoc.v:185138$11944_Y + attribute \src "libresoc.v:185141.17-185141.93" + wire $not$libresoc.v:185141$11947_Y + attribute \src "libresoc.v:185135.18-185135.99" + wire $or$libresoc.v:185135$11941_Y + attribute \src "libresoc.v:185137.18-185137.100" + wire $or$libresoc.v:185137$11943_Y + attribute \src "libresoc.v:185140.17-185140.98" + wire $or$libresoc.v:185140$11946_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -347997,11 +347703,11 @@ module \rok_l$14 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:185351.7-185351.15" + attribute \src "libresoc.v:185099.7-185099.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -348018,7 +347724,7 @@ module \rok_l$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185386$11946 + cell $and $and$libresoc.v:185134$11940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348026,10 +347732,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185386$11946_Y + connect \Y $and$libresoc.v:185134$11940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185391$11951 + cell $and $and$libresoc.v:185139$11945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348037,34 +347743,34 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185391$11951_Y + connect \Y $and$libresoc.v:185139$11945_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185388$11948 + cell $not $not$libresoc.v:185136$11942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185388$11948_Y + connect \Y $not$libresoc.v:185136$11942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185390$11950 + cell $not $not$libresoc.v:185138$11944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185390$11950_Y + connect \Y $not$libresoc.v:185138$11944_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185393$11953 + cell $not $not$libresoc.v:185141$11947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185393$11953_Y + connect \Y $not$libresoc.v:185141$11947_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185387$11947 + cell $or $or$libresoc.v:185135$11941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348072,10 +347778,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185387$11947_Y + connect \Y $or$libresoc.v:185135$11941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185389$11949 + cell $or $or$libresoc.v:185137$11943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348083,10 +347789,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185389$11949_Y + connect \Y $or$libresoc.v:185137$11943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185392$11952 + cell $or $or$libresoc.v:185140$11946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348094,39 +347800,39 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185392$11952_Y + connect \Y $or$libresoc.v:185140$11946_Y end - attribute \src "libresoc.v:185351.7-185351.20" - process $proc$libresoc.v:185351$11958 + attribute \src "libresoc.v:185099.7-185099.20" + process $proc$libresoc.v:185099$11952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185373.7-185373.19" - process $proc$libresoc.v:185373$11959 + attribute \src "libresoc.v:185121.7-185121.19" + process $proc$libresoc.v:185121$11953 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185394.3-185395.27" - process $proc$libresoc.v:185394$11954 + attribute \src "libresoc.v:185142.3-185143.27" + process $proc$libresoc.v:185142$11948 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185396.3-185404.6" - process $proc$libresoc.v:185396$11955 + attribute \src "libresoc.v:185144.3-185152.6" + process $proc$libresoc.v:185144$11949 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11956 $1\q_int$next[0:0]$11957 - attribute \src "libresoc.v:185397.5-185397.29" + assign $0\q_int$next[0:0]$11950 $1\q_int$next[0:0]$11951 + attribute \src "libresoc.v:185145.5-185145.29" switch \initial - attribute \src "libresoc.v:185397.9-185397.17" + attribute \src "libresoc.v:185145.9-185145.17" case 1'1 case end @@ -348135,56 +347841,56 @@ module \rok_l$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11957 1'0 + assign $1\q_int$next[0:0]$11951 1'0 case - assign $1\q_int$next[0:0]$11957 \$5 + assign $1\q_int$next[0:0]$11951 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11956 + update \q_int$next $0\q_int$next[0:0]$11950 end - connect \$9 $and$libresoc.v:185386$11946_Y - connect \$11 $or$libresoc.v:185387$11947_Y - connect \$13 $not$libresoc.v:185388$11948_Y - connect \$15 $or$libresoc.v:185389$11949_Y - connect \$1 $not$libresoc.v:185390$11950_Y - connect \$3 $and$libresoc.v:185391$11951_Y - connect \$5 $or$libresoc.v:185392$11952_Y - connect \$7 $not$libresoc.v:185393$11953_Y + connect \$9 $and$libresoc.v:185134$11940_Y + connect \$11 $or$libresoc.v:185135$11941_Y + connect \$13 $not$libresoc.v:185136$11942_Y + connect \$15 $or$libresoc.v:185137$11943_Y + connect \$1 $not$libresoc.v:185138$11944_Y + connect \$3 $and$libresoc.v:185139$11945_Y + connect \$5 $or$libresoc.v:185140$11946_Y + connect \$7 $not$libresoc.v:185141$11947_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185412.1-185470.10" +attribute \src "libresoc.v:185160.1-185218.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" attribute \generator "nMigen" module \rok_l$27 - attribute \src "libresoc.v:185413.7-185413.20" + attribute \src "libresoc.v:185161.7-185161.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185458.3-185466.6" - wire $0\q_int$next[0:0]$11970 - attribute \src "libresoc.v:185456.3-185457.27" + attribute \src "libresoc.v:185206.3-185214.6" + wire $0\q_int$next[0:0]$11964 + attribute \src "libresoc.v:185204.3-185205.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185458.3-185466.6" - wire $1\q_int$next[0:0]$11971 - attribute \src "libresoc.v:185435.7-185435.19" + attribute \src "libresoc.v:185206.3-185214.6" + wire $1\q_int$next[0:0]$11965 + attribute \src "libresoc.v:185183.7-185183.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185448.17-185448.96" - wire $and$libresoc.v:185448$11960_Y - attribute \src "libresoc.v:185453.17-185453.96" - wire $and$libresoc.v:185453$11965_Y - attribute \src "libresoc.v:185450.18-185450.94" - wire $not$libresoc.v:185450$11962_Y - attribute \src "libresoc.v:185452.17-185452.93" - wire $not$libresoc.v:185452$11964_Y - attribute \src "libresoc.v:185455.17-185455.93" - wire $not$libresoc.v:185455$11967_Y - attribute \src "libresoc.v:185449.18-185449.99" - wire $or$libresoc.v:185449$11961_Y - attribute \src "libresoc.v:185451.18-185451.100" - wire $or$libresoc.v:185451$11963_Y - attribute \src "libresoc.v:185454.17-185454.98" - wire $or$libresoc.v:185454$11966_Y + attribute \src "libresoc.v:185196.17-185196.96" + wire $and$libresoc.v:185196$11954_Y + attribute \src "libresoc.v:185201.17-185201.96" + wire $and$libresoc.v:185201$11959_Y + attribute \src "libresoc.v:185198.18-185198.94" + wire $not$libresoc.v:185198$11956_Y + attribute \src "libresoc.v:185200.17-185200.93" + wire $not$libresoc.v:185200$11958_Y + attribute \src "libresoc.v:185203.17-185203.93" + wire $not$libresoc.v:185203$11961_Y + attribute \src "libresoc.v:185197.18-185197.99" + wire $or$libresoc.v:185197$11955_Y + attribute \src "libresoc.v:185199.18-185199.100" + wire $or$libresoc.v:185199$11957_Y + attribute \src "libresoc.v:185202.17-185202.98" + wire $or$libresoc.v:185202$11960_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -348201,11 +347907,11 @@ module \rok_l$27 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:185413.7-185413.15" + attribute \src "libresoc.v:185161.7-185161.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -348222,7 +347928,7 @@ module \rok_l$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185448$11960 + cell $and $and$libresoc.v:185196$11954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348230,10 +347936,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185448$11960_Y + connect \Y $and$libresoc.v:185196$11954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185453$11965 + cell $and $and$libresoc.v:185201$11959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348241,34 +347947,34 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185453$11965_Y + connect \Y $and$libresoc.v:185201$11959_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185450$11962 + cell $not $not$libresoc.v:185198$11956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185450$11962_Y + connect \Y $not$libresoc.v:185198$11956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185452$11964 + cell $not $not$libresoc.v:185200$11958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185452$11964_Y + connect \Y $not$libresoc.v:185200$11958_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185455$11967 + cell $not $not$libresoc.v:185203$11961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185455$11967_Y + connect \Y $not$libresoc.v:185203$11961_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185449$11961 + cell $or $or$libresoc.v:185197$11955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348276,10 +347982,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185449$11961_Y + connect \Y $or$libresoc.v:185197$11955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185451$11963 + cell $or $or$libresoc.v:185199$11957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348287,10 +347993,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185451$11963_Y + connect \Y $or$libresoc.v:185199$11957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185454$11966 + cell $or $or$libresoc.v:185202$11960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348298,39 +348004,39 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185454$11966_Y + connect \Y $or$libresoc.v:185202$11960_Y end - attribute \src "libresoc.v:185413.7-185413.20" - process $proc$libresoc.v:185413$11972 + attribute \src "libresoc.v:185161.7-185161.20" + process $proc$libresoc.v:185161$11966 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185435.7-185435.19" - process $proc$libresoc.v:185435$11973 + attribute \src "libresoc.v:185183.7-185183.19" + process $proc$libresoc.v:185183$11967 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185456.3-185457.27" - process $proc$libresoc.v:185456$11968 + attribute \src "libresoc.v:185204.3-185205.27" + process $proc$libresoc.v:185204$11962 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185458.3-185466.6" - process $proc$libresoc.v:185458$11969 + attribute \src "libresoc.v:185206.3-185214.6" + process $proc$libresoc.v:185206$11963 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11970 $1\q_int$next[0:0]$11971 - attribute \src "libresoc.v:185459.5-185459.29" + assign $0\q_int$next[0:0]$11964 $1\q_int$next[0:0]$11965 + attribute \src "libresoc.v:185207.5-185207.29" switch \initial - attribute \src "libresoc.v:185459.9-185459.17" + attribute \src "libresoc.v:185207.9-185207.17" case 1'1 case end @@ -348339,56 +348045,56 @@ module \rok_l$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11971 1'0 + assign $1\q_int$next[0:0]$11965 1'0 case - assign $1\q_int$next[0:0]$11971 \$5 + assign $1\q_int$next[0:0]$11965 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11970 + update \q_int$next $0\q_int$next[0:0]$11964 end - connect \$9 $and$libresoc.v:185448$11960_Y - connect \$11 $or$libresoc.v:185449$11961_Y - connect \$13 $not$libresoc.v:185450$11962_Y - connect \$15 $or$libresoc.v:185451$11963_Y - connect \$1 $not$libresoc.v:185452$11964_Y - connect \$3 $and$libresoc.v:185453$11965_Y - connect \$5 $or$libresoc.v:185454$11966_Y - connect \$7 $not$libresoc.v:185455$11967_Y + connect \$9 $and$libresoc.v:185196$11954_Y + connect \$11 $or$libresoc.v:185197$11955_Y + connect \$13 $not$libresoc.v:185198$11956_Y + connect \$15 $or$libresoc.v:185199$11957_Y + connect \$1 $not$libresoc.v:185200$11958_Y + connect \$3 $and$libresoc.v:185201$11959_Y + connect \$5 $or$libresoc.v:185202$11960_Y + connect \$7 $not$libresoc.v:185203$11961_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185474.1-185532.10" +attribute \src "libresoc.v:185222.1-185280.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" attribute \generator "nMigen" module \rok_l$43 - attribute \src "libresoc.v:185475.7-185475.20" + attribute \src "libresoc.v:185223.7-185223.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185520.3-185528.6" - wire $0\q_int$next[0:0]$11984 - attribute \src "libresoc.v:185518.3-185519.27" + attribute \src "libresoc.v:185268.3-185276.6" + wire $0\q_int$next[0:0]$11978 + attribute \src "libresoc.v:185266.3-185267.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185520.3-185528.6" - wire $1\q_int$next[0:0]$11985 - attribute \src "libresoc.v:185497.7-185497.19" + attribute \src "libresoc.v:185268.3-185276.6" + wire $1\q_int$next[0:0]$11979 + attribute \src "libresoc.v:185245.7-185245.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185510.17-185510.96" - wire $and$libresoc.v:185510$11974_Y - attribute \src "libresoc.v:185515.17-185515.96" - wire $and$libresoc.v:185515$11979_Y - attribute \src "libresoc.v:185512.18-185512.94" - wire $not$libresoc.v:185512$11976_Y - attribute \src "libresoc.v:185514.17-185514.93" - wire $not$libresoc.v:185514$11978_Y - attribute \src "libresoc.v:185517.17-185517.93" - wire $not$libresoc.v:185517$11981_Y - attribute \src "libresoc.v:185511.18-185511.99" - wire $or$libresoc.v:185511$11975_Y - attribute \src "libresoc.v:185513.18-185513.100" - wire $or$libresoc.v:185513$11977_Y - attribute \src "libresoc.v:185516.17-185516.98" - wire $or$libresoc.v:185516$11980_Y + attribute \src "libresoc.v:185258.17-185258.96" + wire $and$libresoc.v:185258$11968_Y + attribute \src "libresoc.v:185263.17-185263.96" + wire $and$libresoc.v:185263$11973_Y + attribute \src "libresoc.v:185260.18-185260.94" + wire $not$libresoc.v:185260$11970_Y + attribute \src "libresoc.v:185262.17-185262.93" + wire $not$libresoc.v:185262$11972_Y + attribute \src "libresoc.v:185265.17-185265.93" + wire $not$libresoc.v:185265$11975_Y + attribute \src "libresoc.v:185259.18-185259.99" + wire $or$libresoc.v:185259$11969_Y + attribute \src "libresoc.v:185261.18-185261.100" + wire $or$libresoc.v:185261$11971_Y + attribute \src "libresoc.v:185264.17-185264.98" + wire $or$libresoc.v:185264$11974_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -348405,11 +348111,11 @@ module \rok_l$43 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:185475.7-185475.15" + attribute \src "libresoc.v:185223.7-185223.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -348426,7 +348132,7 @@ module \rok_l$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185510$11974 + cell $and $and$libresoc.v:185258$11968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348434,10 +348140,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185510$11974_Y + connect \Y $and$libresoc.v:185258$11968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185515$11979 + cell $and $and$libresoc.v:185263$11973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348445,34 +348151,34 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185515$11979_Y + connect \Y $and$libresoc.v:185263$11973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185512$11976 + cell $not $not$libresoc.v:185260$11970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185512$11976_Y + connect \Y $not$libresoc.v:185260$11970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185514$11978 + cell $not $not$libresoc.v:185262$11972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185514$11978_Y + connect \Y $not$libresoc.v:185262$11972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185517$11981 + cell $not $not$libresoc.v:185265$11975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185517$11981_Y + connect \Y $not$libresoc.v:185265$11975_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185511$11975 + cell $or $or$libresoc.v:185259$11969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348480,10 +348186,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185511$11975_Y + connect \Y $or$libresoc.v:185259$11969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185513$11977 + cell $or $or$libresoc.v:185261$11971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348491,10 +348197,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185513$11977_Y + connect \Y $or$libresoc.v:185261$11971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185516$11980 + cell $or $or$libresoc.v:185264$11974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348502,39 +348208,39 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185516$11980_Y + connect \Y $or$libresoc.v:185264$11974_Y end - attribute \src "libresoc.v:185475.7-185475.20" - process $proc$libresoc.v:185475$11986 + attribute \src "libresoc.v:185223.7-185223.20" + process $proc$libresoc.v:185223$11980 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185497.7-185497.19" - process $proc$libresoc.v:185497$11987 + attribute \src "libresoc.v:185245.7-185245.19" + process $proc$libresoc.v:185245$11981 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185518.3-185519.27" - process $proc$libresoc.v:185518$11982 + attribute \src "libresoc.v:185266.3-185267.27" + process $proc$libresoc.v:185266$11976 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185520.3-185528.6" - process $proc$libresoc.v:185520$11983 + attribute \src "libresoc.v:185268.3-185276.6" + process $proc$libresoc.v:185268$11977 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11984 $1\q_int$next[0:0]$11985 - attribute \src "libresoc.v:185521.5-185521.29" + assign $0\q_int$next[0:0]$11978 $1\q_int$next[0:0]$11979 + attribute \src "libresoc.v:185269.5-185269.29" switch \initial - attribute \src "libresoc.v:185521.9-185521.17" + attribute \src "libresoc.v:185269.9-185269.17" case 1'1 case end @@ -348543,56 +348249,56 @@ module \rok_l$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11985 1'0 + assign $1\q_int$next[0:0]$11979 1'0 case - assign $1\q_int$next[0:0]$11985 \$5 + assign $1\q_int$next[0:0]$11979 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11984 + update \q_int$next $0\q_int$next[0:0]$11978 end - connect \$9 $and$libresoc.v:185510$11974_Y - connect \$11 $or$libresoc.v:185511$11975_Y - connect \$13 $not$libresoc.v:185512$11976_Y - connect \$15 $or$libresoc.v:185513$11977_Y - connect \$1 $not$libresoc.v:185514$11978_Y - connect \$3 $and$libresoc.v:185515$11979_Y - connect \$5 $or$libresoc.v:185516$11980_Y - connect \$7 $not$libresoc.v:185517$11981_Y + connect \$9 $and$libresoc.v:185258$11968_Y + connect \$11 $or$libresoc.v:185259$11969_Y + connect \$13 $not$libresoc.v:185260$11970_Y + connect \$15 $or$libresoc.v:185261$11971_Y + connect \$1 $not$libresoc.v:185262$11972_Y + connect \$3 $and$libresoc.v:185263$11973_Y + connect \$5 $or$libresoc.v:185264$11974_Y + connect \$7 $not$libresoc.v:185265$11975_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185536.1-185594.10" +attribute \src "libresoc.v:185284.1-185342.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" attribute \generator "nMigen" module \rok_l$59 - attribute \src "libresoc.v:185537.7-185537.20" + attribute \src "libresoc.v:185285.7-185285.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185582.3-185590.6" - wire $0\q_int$next[0:0]$11998 - attribute \src "libresoc.v:185580.3-185581.27" + attribute \src "libresoc.v:185330.3-185338.6" + wire $0\q_int$next[0:0]$11992 + attribute \src "libresoc.v:185328.3-185329.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185582.3-185590.6" - wire $1\q_int$next[0:0]$11999 - attribute \src "libresoc.v:185559.7-185559.19" + attribute \src "libresoc.v:185330.3-185338.6" + wire $1\q_int$next[0:0]$11993 + attribute \src "libresoc.v:185307.7-185307.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185572.17-185572.96" - wire $and$libresoc.v:185572$11988_Y - attribute \src "libresoc.v:185577.17-185577.96" - wire $and$libresoc.v:185577$11993_Y - attribute \src "libresoc.v:185574.18-185574.94" - wire $not$libresoc.v:185574$11990_Y - attribute \src "libresoc.v:185576.17-185576.93" - wire $not$libresoc.v:185576$11992_Y - attribute \src "libresoc.v:185579.17-185579.93" - wire $not$libresoc.v:185579$11995_Y - attribute \src "libresoc.v:185573.18-185573.99" - wire $or$libresoc.v:185573$11989_Y - attribute \src "libresoc.v:185575.18-185575.100" - wire $or$libresoc.v:185575$11991_Y - attribute \src "libresoc.v:185578.17-185578.98" - wire $or$libresoc.v:185578$11994_Y + attribute \src "libresoc.v:185320.17-185320.96" + wire $and$libresoc.v:185320$11982_Y + attribute \src "libresoc.v:185325.17-185325.96" + wire $and$libresoc.v:185325$11987_Y + attribute \src "libresoc.v:185322.18-185322.94" + wire $not$libresoc.v:185322$11984_Y + attribute \src "libresoc.v:185324.17-185324.93" + wire $not$libresoc.v:185324$11986_Y + attribute \src "libresoc.v:185327.17-185327.93" + wire $not$libresoc.v:185327$11989_Y + attribute \src "libresoc.v:185321.18-185321.99" + wire $or$libresoc.v:185321$11983_Y + attribute \src "libresoc.v:185323.18-185323.100" + wire $or$libresoc.v:185323$11985_Y + attribute \src "libresoc.v:185326.17-185326.98" + wire $or$libresoc.v:185326$11988_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -348609,11 +348315,11 @@ module \rok_l$59 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:185537.7-185537.15" + attribute \src "libresoc.v:185285.7-185285.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -348630,7 +348336,7 @@ module \rok_l$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185572$11988 + cell $and $and$libresoc.v:185320$11982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348638,10 +348344,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185572$11988_Y + connect \Y $and$libresoc.v:185320$11982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185577$11993 + cell $and $and$libresoc.v:185325$11987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348649,34 +348355,34 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185577$11993_Y + connect \Y $and$libresoc.v:185325$11987_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185574$11990 + cell $not $not$libresoc.v:185322$11984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185574$11990_Y + connect \Y $not$libresoc.v:185322$11984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185576$11992 + cell $not $not$libresoc.v:185324$11986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185576$11992_Y + connect \Y $not$libresoc.v:185324$11986_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185579$11995 + cell $not $not$libresoc.v:185327$11989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185579$11995_Y + connect \Y $not$libresoc.v:185327$11989_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185573$11989 + cell $or $or$libresoc.v:185321$11983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348684,10 +348390,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185573$11989_Y + connect \Y $or$libresoc.v:185321$11983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185575$11991 + cell $or $or$libresoc.v:185323$11985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348695,10 +348401,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185575$11991_Y + connect \Y $or$libresoc.v:185323$11985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185578$11994 + cell $or $or$libresoc.v:185326$11988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348706,39 +348412,39 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185578$11994_Y + connect \Y $or$libresoc.v:185326$11988_Y end - attribute \src "libresoc.v:185537.7-185537.20" - process $proc$libresoc.v:185537$12000 + attribute \src "libresoc.v:185285.7-185285.20" + process $proc$libresoc.v:185285$11994 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185559.7-185559.19" - process $proc$libresoc.v:185559$12001 + attribute \src "libresoc.v:185307.7-185307.19" + process $proc$libresoc.v:185307$11995 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185580.3-185581.27" - process $proc$libresoc.v:185580$11996 + attribute \src "libresoc.v:185328.3-185329.27" + process $proc$libresoc.v:185328$11990 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185582.3-185590.6" - process $proc$libresoc.v:185582$11997 + attribute \src "libresoc.v:185330.3-185338.6" + process $proc$libresoc.v:185330$11991 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11998 $1\q_int$next[0:0]$11999 - attribute \src "libresoc.v:185583.5-185583.29" + assign $0\q_int$next[0:0]$11992 $1\q_int$next[0:0]$11993 + attribute \src "libresoc.v:185331.5-185331.29" switch \initial - attribute \src "libresoc.v:185583.9-185583.17" + attribute \src "libresoc.v:185331.9-185331.17" case 1'1 case end @@ -348747,56 +348453,56 @@ module \rok_l$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11999 1'0 + assign $1\q_int$next[0:0]$11993 1'0 case - assign $1\q_int$next[0:0]$11999 \$5 + assign $1\q_int$next[0:0]$11993 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11998 + update \q_int$next $0\q_int$next[0:0]$11992 end - connect \$9 $and$libresoc.v:185572$11988_Y - connect \$11 $or$libresoc.v:185573$11989_Y - connect \$13 $not$libresoc.v:185574$11990_Y - connect \$15 $or$libresoc.v:185575$11991_Y - connect \$1 $not$libresoc.v:185576$11992_Y - connect \$3 $and$libresoc.v:185577$11993_Y - connect \$5 $or$libresoc.v:185578$11994_Y - connect \$7 $not$libresoc.v:185579$11995_Y + connect \$9 $and$libresoc.v:185320$11982_Y + connect \$11 $or$libresoc.v:185321$11983_Y + connect \$13 $not$libresoc.v:185322$11984_Y + connect \$15 $or$libresoc.v:185323$11985_Y + connect \$1 $not$libresoc.v:185324$11986_Y + connect \$3 $and$libresoc.v:185325$11987_Y + connect \$5 $or$libresoc.v:185326$11988_Y + connect \$7 $not$libresoc.v:185327$11989_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185598.1-185656.10" +attribute \src "libresoc.v:185346.1-185404.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" attribute \generator "nMigen" module \rok_l$71 - attribute \src "libresoc.v:185599.7-185599.20" + attribute \src "libresoc.v:185347.7-185347.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185644.3-185652.6" - wire $0\q_int$next[0:0]$12012 - attribute \src "libresoc.v:185642.3-185643.27" + attribute \src "libresoc.v:185392.3-185400.6" + wire $0\q_int$next[0:0]$12006 + attribute \src "libresoc.v:185390.3-185391.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185644.3-185652.6" - wire $1\q_int$next[0:0]$12013 - attribute \src "libresoc.v:185621.7-185621.19" + attribute \src "libresoc.v:185392.3-185400.6" + wire $1\q_int$next[0:0]$12007 + attribute \src "libresoc.v:185369.7-185369.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185634.17-185634.96" - wire $and$libresoc.v:185634$12002_Y - attribute \src "libresoc.v:185639.17-185639.96" - wire $and$libresoc.v:185639$12007_Y - attribute \src "libresoc.v:185636.18-185636.94" - wire $not$libresoc.v:185636$12004_Y - attribute \src "libresoc.v:185638.17-185638.93" - wire $not$libresoc.v:185638$12006_Y - attribute \src "libresoc.v:185641.17-185641.93" - wire $not$libresoc.v:185641$12009_Y - attribute \src "libresoc.v:185635.18-185635.99" - wire $or$libresoc.v:185635$12003_Y - attribute \src "libresoc.v:185637.18-185637.100" - wire $or$libresoc.v:185637$12005_Y - attribute \src "libresoc.v:185640.17-185640.98" - wire $or$libresoc.v:185640$12008_Y + attribute \src "libresoc.v:185382.17-185382.96" + wire $and$libresoc.v:185382$11996_Y + attribute \src "libresoc.v:185387.17-185387.96" + wire $and$libresoc.v:185387$12001_Y + attribute \src "libresoc.v:185384.18-185384.94" + wire $not$libresoc.v:185384$11998_Y + attribute \src "libresoc.v:185386.17-185386.93" + wire $not$libresoc.v:185386$12000_Y + attribute \src "libresoc.v:185389.17-185389.93" + wire $not$libresoc.v:185389$12003_Y + attribute \src "libresoc.v:185383.18-185383.99" + wire $or$libresoc.v:185383$11997_Y + attribute \src "libresoc.v:185385.18-185385.100" + wire $or$libresoc.v:185385$11999_Y + attribute \src "libresoc.v:185388.17-185388.98" + wire $or$libresoc.v:185388$12002_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -348813,11 +348519,11 @@ module \rok_l$71 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:185599.7-185599.15" + attribute \src "libresoc.v:185347.7-185347.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -348834,7 +348540,7 @@ module \rok_l$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185634$12002 + cell $and $and$libresoc.v:185382$11996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348842,10 +348548,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185634$12002_Y + connect \Y $and$libresoc.v:185382$11996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185639$12007 + cell $and $and$libresoc.v:185387$12001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348853,34 +348559,34 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185639$12007_Y + connect \Y $and$libresoc.v:185387$12001_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185636$12004 + cell $not $not$libresoc.v:185384$11998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185636$12004_Y + connect \Y $not$libresoc.v:185384$11998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185638$12006 + cell $not $not$libresoc.v:185386$12000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185638$12006_Y + connect \Y $not$libresoc.v:185386$12000_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185641$12009 + cell $not $not$libresoc.v:185389$12003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185641$12009_Y + connect \Y $not$libresoc.v:185389$12003_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185635$12003 + cell $or $or$libresoc.v:185383$11997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348888,10 +348594,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185635$12003_Y + connect \Y $or$libresoc.v:185383$11997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185637$12005 + cell $or $or$libresoc.v:185385$11999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348899,10 +348605,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185637$12005_Y + connect \Y $or$libresoc.v:185385$11999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185640$12008 + cell $or $or$libresoc.v:185388$12002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348910,39 +348616,39 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185640$12008_Y + connect \Y $or$libresoc.v:185388$12002_Y end - attribute \src "libresoc.v:185599.7-185599.20" - process $proc$libresoc.v:185599$12014 + attribute \src "libresoc.v:185347.7-185347.20" + process $proc$libresoc.v:185347$12008 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185621.7-185621.19" - process $proc$libresoc.v:185621$12015 + attribute \src "libresoc.v:185369.7-185369.19" + process $proc$libresoc.v:185369$12009 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185642.3-185643.27" - process $proc$libresoc.v:185642$12010 + attribute \src "libresoc.v:185390.3-185391.27" + process $proc$libresoc.v:185390$12004 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185644.3-185652.6" - process $proc$libresoc.v:185644$12011 + attribute \src "libresoc.v:185392.3-185400.6" + process $proc$libresoc.v:185392$12005 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12012 $1\q_int$next[0:0]$12013 - attribute \src "libresoc.v:185645.5-185645.29" + assign $0\q_int$next[0:0]$12006 $1\q_int$next[0:0]$12007 + attribute \src "libresoc.v:185393.5-185393.29" switch \initial - attribute \src "libresoc.v:185645.9-185645.17" + attribute \src "libresoc.v:185393.9-185393.17" case 1'1 case end @@ -348951,56 +348657,56 @@ module \rok_l$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12013 1'0 + assign $1\q_int$next[0:0]$12007 1'0 case - assign $1\q_int$next[0:0]$12013 \$5 + assign $1\q_int$next[0:0]$12007 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12012 + update \q_int$next $0\q_int$next[0:0]$12006 end - connect \$9 $and$libresoc.v:185634$12002_Y - connect \$11 $or$libresoc.v:185635$12003_Y - connect \$13 $not$libresoc.v:185636$12004_Y - connect \$15 $or$libresoc.v:185637$12005_Y - connect \$1 $not$libresoc.v:185638$12006_Y - connect \$3 $and$libresoc.v:185639$12007_Y - connect \$5 $or$libresoc.v:185640$12008_Y - connect \$7 $not$libresoc.v:185641$12009_Y + connect \$9 $and$libresoc.v:185382$11996_Y + connect \$11 $or$libresoc.v:185383$11997_Y + connect \$13 $not$libresoc.v:185384$11998_Y + connect \$15 $or$libresoc.v:185385$11999_Y + connect \$1 $not$libresoc.v:185386$12000_Y + connect \$3 $and$libresoc.v:185387$12001_Y + connect \$5 $or$libresoc.v:185388$12002_Y + connect \$7 $not$libresoc.v:185389$12003_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185660.1-185718.10" +attribute \src "libresoc.v:185408.1-185466.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" attribute \generator "nMigen" module \rok_l$88 - attribute \src "libresoc.v:185661.7-185661.20" + attribute \src "libresoc.v:185409.7-185409.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185706.3-185714.6" - wire $0\q_int$next[0:0]$12026 - attribute \src "libresoc.v:185704.3-185705.27" + attribute \src "libresoc.v:185454.3-185462.6" + wire $0\q_int$next[0:0]$12020 + attribute \src "libresoc.v:185452.3-185453.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185706.3-185714.6" - wire $1\q_int$next[0:0]$12027 - attribute \src "libresoc.v:185683.7-185683.19" + attribute \src "libresoc.v:185454.3-185462.6" + wire $1\q_int$next[0:0]$12021 + attribute \src "libresoc.v:185431.7-185431.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185696.17-185696.96" - wire $and$libresoc.v:185696$12016_Y - attribute \src "libresoc.v:185701.17-185701.96" - wire $and$libresoc.v:185701$12021_Y - attribute \src "libresoc.v:185698.18-185698.94" - wire $not$libresoc.v:185698$12018_Y - attribute \src "libresoc.v:185700.17-185700.93" - wire $not$libresoc.v:185700$12020_Y - attribute \src "libresoc.v:185703.17-185703.93" - wire $not$libresoc.v:185703$12023_Y - attribute \src "libresoc.v:185697.18-185697.99" - wire $or$libresoc.v:185697$12017_Y - attribute \src "libresoc.v:185699.18-185699.100" - wire $or$libresoc.v:185699$12019_Y - attribute \src "libresoc.v:185702.17-185702.98" - wire $or$libresoc.v:185702$12022_Y + attribute \src "libresoc.v:185444.17-185444.96" + wire $and$libresoc.v:185444$12010_Y + attribute \src "libresoc.v:185449.17-185449.96" + wire $and$libresoc.v:185449$12015_Y + attribute \src "libresoc.v:185446.18-185446.94" + wire $not$libresoc.v:185446$12012_Y + attribute \src "libresoc.v:185448.17-185448.93" + wire $not$libresoc.v:185448$12014_Y + attribute \src "libresoc.v:185451.17-185451.93" + wire $not$libresoc.v:185451$12017_Y + attribute \src "libresoc.v:185445.18-185445.99" + wire $or$libresoc.v:185445$12011_Y + attribute \src "libresoc.v:185447.18-185447.100" + wire $or$libresoc.v:185447$12013_Y + attribute \src "libresoc.v:185450.17-185450.98" + wire $or$libresoc.v:185450$12016_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -349017,11 +348723,11 @@ module \rok_l$88 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:185661.7-185661.15" + attribute \src "libresoc.v:185409.7-185409.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -349038,7 +348744,7 @@ module \rok_l$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185696$12016 + cell $and $and$libresoc.v:185444$12010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349046,10 +348752,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185696$12016_Y + connect \Y $and$libresoc.v:185444$12010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185701$12021 + cell $and $and$libresoc.v:185449$12015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349057,34 +348763,34 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185701$12021_Y + connect \Y $and$libresoc.v:185449$12015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185698$12018 + cell $not $not$libresoc.v:185446$12012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185698$12018_Y + connect \Y $not$libresoc.v:185446$12012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185700$12020 + cell $not $not$libresoc.v:185448$12014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185700$12020_Y + connect \Y $not$libresoc.v:185448$12014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185703$12023 + cell $not $not$libresoc.v:185451$12017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185703$12023_Y + connect \Y $not$libresoc.v:185451$12017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185697$12017 + cell $or $or$libresoc.v:185445$12011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349092,10 +348798,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185697$12017_Y + connect \Y $or$libresoc.v:185445$12011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185699$12019 + cell $or $or$libresoc.v:185447$12013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349103,10 +348809,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185699$12019_Y + connect \Y $or$libresoc.v:185447$12013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185702$12022 + cell $or $or$libresoc.v:185450$12016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349114,39 +348820,39 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185702$12022_Y + connect \Y $or$libresoc.v:185450$12016_Y end - attribute \src "libresoc.v:185661.7-185661.20" - process $proc$libresoc.v:185661$12028 + attribute \src "libresoc.v:185409.7-185409.20" + process $proc$libresoc.v:185409$12022 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185683.7-185683.19" - process $proc$libresoc.v:185683$12029 + attribute \src "libresoc.v:185431.7-185431.19" + process $proc$libresoc.v:185431$12023 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185704.3-185705.27" - process $proc$libresoc.v:185704$12024 + attribute \src "libresoc.v:185452.3-185453.27" + process $proc$libresoc.v:185452$12018 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185706.3-185714.6" - process $proc$libresoc.v:185706$12025 + attribute \src "libresoc.v:185454.3-185462.6" + process $proc$libresoc.v:185454$12019 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12026 $1\q_int$next[0:0]$12027 - attribute \src "libresoc.v:185707.5-185707.29" + assign $0\q_int$next[0:0]$12020 $1\q_int$next[0:0]$12021 + attribute \src "libresoc.v:185455.5-185455.29" switch \initial - attribute \src "libresoc.v:185707.9-185707.17" + attribute \src "libresoc.v:185455.9-185455.17" case 1'1 case end @@ -349155,150 +348861,150 @@ module \rok_l$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12027 1'0 + assign $1\q_int$next[0:0]$12021 1'0 case - assign $1\q_int$next[0:0]$12027 \$5 + assign $1\q_int$next[0:0]$12021 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12026 + update \q_int$next $0\q_int$next[0:0]$12020 end - connect \$9 $and$libresoc.v:185696$12016_Y - connect \$11 $or$libresoc.v:185697$12017_Y - connect \$13 $not$libresoc.v:185698$12018_Y - connect \$15 $or$libresoc.v:185699$12019_Y - connect \$1 $not$libresoc.v:185700$12020_Y - connect \$3 $and$libresoc.v:185701$12021_Y - connect \$5 $or$libresoc.v:185702$12022_Y - connect \$7 $not$libresoc.v:185703$12023_Y + connect \$9 $and$libresoc.v:185444$12010_Y + connect \$11 $or$libresoc.v:185445$12011_Y + connect \$13 $not$libresoc.v:185446$12012_Y + connect \$15 $or$libresoc.v:185447$12013_Y + connect \$1 $not$libresoc.v:185448$12014_Y + connect \$3 $and$libresoc.v:185449$12015_Y + connect \$5 $or$libresoc.v:185450$12016_Y + connect \$7 $not$libresoc.v:185451$12017_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185722.1-186082.10" +attribute \src "libresoc.v:185470.1-185830.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" attribute \generator "nMigen" module \rotator - attribute \src "libresoc.v:185991.3-186009.6" + attribute \src "libresoc.v:185739.3-185757.6" wire $0\carry_out_o[0:0] - attribute \src "libresoc.v:185923.3-185937.6" + attribute \src "libresoc.v:185671.3-185685.6" wire width 32 $0\hi32[31:0] - attribute \src "libresoc.v:185723.7-185723.20" + attribute \src "libresoc.v:185471.7-185471.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186022.3-186055.6" - wire width 7 $0\mb$8[6:0]$12077 - attribute \src "libresoc.v:186056.3-186070.6" - wire width 7 $0\me$13[6:0]$12082 - attribute \src "libresoc.v:185948.3-185959.6" + attribute \src "libresoc.v:185770.3-185803.6" + wire width 7 $0\mb$8[6:0]$12071 + attribute \src "libresoc.v:185804.3-185818.6" + wire width 7 $0\me$13[6:0]$12076 + attribute \src "libresoc.v:185696.3-185707.6" wire width 64 $0\mr[63:0] - attribute \src "libresoc.v:185960.3-185971.6" + attribute \src "libresoc.v:185708.3-185719.6" wire width 2 $0\output_mode[1:0] - attribute \src "libresoc.v:185972.3-185990.6" + attribute \src "libresoc.v:185720.3-185738.6" wire width 64 $0\result_o[63:0] - attribute \src "libresoc.v:185938.3-185947.6" + attribute \src "libresoc.v:185686.3-185695.6" wire width 7 $0\right_mask_shift[6:0] - attribute \src "libresoc.v:186010.3-186021.6" + attribute \src "libresoc.v:185758.3-185769.6" wire width 6 $0\rot_count[5:0] - attribute \src "libresoc.v:185991.3-186009.6" + attribute \src "libresoc.v:185739.3-185757.6" wire $1\carry_out_o[0:0] - attribute \src "libresoc.v:185923.3-185937.6" + attribute \src "libresoc.v:185671.3-185685.6" wire width 32 $1\hi32[31:0] - attribute \src "libresoc.v:186022.3-186055.6" - wire width 7 $1\mb$8[6:0]$12078 - attribute \src "libresoc.v:186056.3-186070.6" - wire width 7 $1\me$13[6:0]$12083 - attribute \src "libresoc.v:185948.3-185959.6" + attribute \src "libresoc.v:185770.3-185803.6" + wire width 7 $1\mb$8[6:0]$12072 + attribute \src "libresoc.v:185804.3-185818.6" + wire width 7 $1\me$13[6:0]$12077 + attribute \src "libresoc.v:185696.3-185707.6" wire width 64 $1\mr[63:0] - attribute \src "libresoc.v:185960.3-185971.6" + attribute \src "libresoc.v:185708.3-185719.6" wire width 2 $1\output_mode[1:0] - attribute \src "libresoc.v:185972.3-185990.6" + attribute \src "libresoc.v:185720.3-185738.6" wire width 64 $1\result_o[63:0] - attribute \src "libresoc.v:185938.3-185947.6" + attribute \src "libresoc.v:185686.3-185695.6" wire width 7 $1\right_mask_shift[6:0] - attribute \src "libresoc.v:186010.3-186021.6" + attribute \src "libresoc.v:185758.3-185769.6" wire width 6 $1\rot_count[5:0] - attribute \src "libresoc.v:186022.3-186055.6" - wire width 2 $2\mb$8[6:5]$12079 - attribute \src "libresoc.v:186022.3-186055.6" - wire width 2 $3\mb$8[6:5]$12080 - attribute \src "libresoc.v:185874.18-185874.118" - wire $and$libresoc.v:185874$12033_Y - attribute \src "libresoc.v:185876.18-185876.114" - wire $and$libresoc.v:185876$12035_Y - attribute \src "libresoc.v:185885.18-185885.113" - wire $and$libresoc.v:185885$12044_Y - attribute \src "libresoc.v:185887.18-185887.114" - wire $and$libresoc.v:185887$12046_Y - attribute \src "libresoc.v:185889.18-185889.114" - wire $and$libresoc.v:185889$12048_Y - attribute \src "libresoc.v:185890.18-185890.103" - wire width 64 $and$libresoc.v:185890$12049_Y - attribute \src "libresoc.v:185891.18-185891.106" - wire width 64 $and$libresoc.v:185891$12050_Y - attribute \src "libresoc.v:185893.18-185893.103" - wire width 64 $and$libresoc.v:185893$12052_Y - attribute \src "libresoc.v:185895.18-185895.105" - wire width 64 $and$libresoc.v:185895$12054_Y - attribute \src "libresoc.v:185898.18-185898.106" - wire width 64 $and$libresoc.v:185898$12057_Y - attribute \src "libresoc.v:185901.18-185901.105" - wire width 64 $and$libresoc.v:185901$12060_Y - attribute \src "libresoc.v:185903.17-185903.109" - wire $and$libresoc.v:185903$12062_Y - attribute \src "libresoc.v:185904.18-185904.104" - wire width 64 $and$libresoc.v:185904$12063_Y - attribute \src "libresoc.v:185908.18-185908.105" - wire width 64 $and$libresoc.v:185908$12067_Y - attribute \src "libresoc.v:185872.17-185872.98" - wire width 7 $extend$libresoc.v:185872$12030_Y - attribute \src "libresoc.v:185888.18-185888.122" - wire $gt$libresoc.v:185888$12047_Y - attribute \src "libresoc.v:185878.18-185878.111" - wire $le$libresoc.v:185878$12037_Y - attribute \src "libresoc.v:185880.18-185880.111" - wire $le$libresoc.v:185880$12039_Y - attribute \src "libresoc.v:185881.17-185881.117" - wire width 7 signed $neg$libresoc.v:185881$12040_Y - attribute \src "libresoc.v:185873.18-185873.103" - wire $not$libresoc.v:185873$12032_Y - attribute \src "libresoc.v:185875.18-185875.108" - wire $not$libresoc.v:185875$12034_Y - attribute \src "libresoc.v:185877.18-185877.105" - wire width 6 $not$libresoc.v:185877$12036_Y - attribute \src "libresoc.v:185883.18-185883.112" - wire width 64 $not$libresoc.v:185883$12042_Y - attribute \src "libresoc.v:185884.18-185884.109" - wire $not$libresoc.v:185884$12043_Y - attribute \src "libresoc.v:185892.17-185892.105" - wire $not$libresoc.v:185892$12051_Y - attribute \src "libresoc.v:185894.18-185894.102" - wire width 64 $not$libresoc.v:185894$12053_Y - attribute \src "libresoc.v:185900.18-185900.102" - wire width 64 $not$libresoc.v:185900$12059_Y - attribute \src "libresoc.v:185905.18-185905.100" - wire width 64 $not$libresoc.v:185905$12064_Y - attribute \src "libresoc.v:185907.18-185907.100" - wire width 64 $not$libresoc.v:185907$12066_Y - attribute \src "libresoc.v:185886.18-185886.115" - wire $or$libresoc.v:185886$12045_Y - attribute \src "libresoc.v:185896.18-185896.108" - wire width 64 $or$libresoc.v:185896$12055_Y - attribute \src "libresoc.v:185897.18-185897.103" - wire width 64 $or$libresoc.v:185897$12056_Y - attribute \src "libresoc.v:185899.18-185899.103" - wire width 64 $or$libresoc.v:185899$12058_Y - attribute \src "libresoc.v:185902.18-185902.108" - wire width 64 $or$libresoc.v:185902$12061_Y - attribute \src "libresoc.v:185906.18-185906.106" - wire width 64 $or$libresoc.v:185906$12065_Y - attribute \src "libresoc.v:185872.17-185872.98" - wire width 7 $pos$libresoc.v:185872$12031_Y - attribute \src "libresoc.v:185909.18-185909.102" - wire $reduce_or$libresoc.v:185909$12068_Y - attribute \src "libresoc.v:185879.18-185879.109" - wire width 8 $sub$libresoc.v:185879$12038_Y - attribute \src "libresoc.v:185882.18-185882.110" - wire width 8 $sub$libresoc.v:185882$12041_Y + attribute \src "libresoc.v:185770.3-185803.6" + wire width 2 $2\mb$8[6:5]$12073 + attribute \src "libresoc.v:185770.3-185803.6" + wire width 2 $3\mb$8[6:5]$12074 + attribute \src "libresoc.v:185622.18-185622.118" + wire $and$libresoc.v:185622$12027_Y + attribute \src "libresoc.v:185624.18-185624.114" + wire $and$libresoc.v:185624$12029_Y + attribute \src "libresoc.v:185633.18-185633.113" + wire $and$libresoc.v:185633$12038_Y + attribute \src "libresoc.v:185635.18-185635.114" + wire $and$libresoc.v:185635$12040_Y + attribute \src "libresoc.v:185637.18-185637.114" + wire $and$libresoc.v:185637$12042_Y + attribute \src "libresoc.v:185638.18-185638.103" + wire width 64 $and$libresoc.v:185638$12043_Y + attribute \src "libresoc.v:185639.18-185639.106" + wire width 64 $and$libresoc.v:185639$12044_Y + attribute \src "libresoc.v:185641.18-185641.103" + wire width 64 $and$libresoc.v:185641$12046_Y + attribute \src "libresoc.v:185643.18-185643.105" + wire width 64 $and$libresoc.v:185643$12048_Y + attribute \src "libresoc.v:185646.18-185646.106" + wire width 64 $and$libresoc.v:185646$12051_Y + attribute \src "libresoc.v:185649.18-185649.105" + wire width 64 $and$libresoc.v:185649$12054_Y + attribute \src "libresoc.v:185651.17-185651.109" + wire $and$libresoc.v:185651$12056_Y + attribute \src "libresoc.v:185652.18-185652.104" + wire width 64 $and$libresoc.v:185652$12057_Y + attribute \src "libresoc.v:185656.18-185656.105" + wire width 64 $and$libresoc.v:185656$12061_Y + attribute \src "libresoc.v:185620.17-185620.98" + wire width 7 $extend$libresoc.v:185620$12024_Y + attribute \src "libresoc.v:185636.18-185636.122" + wire $gt$libresoc.v:185636$12041_Y + attribute \src "libresoc.v:185626.18-185626.111" + wire $le$libresoc.v:185626$12031_Y + attribute \src "libresoc.v:185628.18-185628.111" + wire $le$libresoc.v:185628$12033_Y + attribute \src "libresoc.v:185629.17-185629.117" + wire width 7 signed $neg$libresoc.v:185629$12034_Y + attribute \src "libresoc.v:185621.18-185621.103" + wire $not$libresoc.v:185621$12026_Y + attribute \src "libresoc.v:185623.18-185623.108" + wire $not$libresoc.v:185623$12028_Y + attribute \src "libresoc.v:185625.18-185625.105" + wire width 6 $not$libresoc.v:185625$12030_Y + attribute \src "libresoc.v:185631.18-185631.112" + wire width 64 $not$libresoc.v:185631$12036_Y + attribute \src "libresoc.v:185632.18-185632.109" + wire $not$libresoc.v:185632$12037_Y + attribute \src "libresoc.v:185640.17-185640.105" + wire $not$libresoc.v:185640$12045_Y + attribute \src "libresoc.v:185642.18-185642.102" + wire width 64 $not$libresoc.v:185642$12047_Y + attribute \src "libresoc.v:185648.18-185648.102" + wire width 64 $not$libresoc.v:185648$12053_Y + attribute \src "libresoc.v:185653.18-185653.100" + wire width 64 $not$libresoc.v:185653$12058_Y + attribute \src "libresoc.v:185655.18-185655.100" + wire width 64 $not$libresoc.v:185655$12060_Y + attribute \src "libresoc.v:185634.18-185634.115" + wire $or$libresoc.v:185634$12039_Y + attribute \src "libresoc.v:185644.18-185644.108" + wire width 64 $or$libresoc.v:185644$12049_Y + attribute \src "libresoc.v:185645.18-185645.103" + wire width 64 $or$libresoc.v:185645$12050_Y + attribute \src "libresoc.v:185647.18-185647.103" + wire width 64 $or$libresoc.v:185647$12052_Y + attribute \src "libresoc.v:185650.18-185650.108" + wire width 64 $or$libresoc.v:185650$12055_Y + attribute \src "libresoc.v:185654.18-185654.106" + wire width 64 $or$libresoc.v:185654$12059_Y + attribute \src "libresoc.v:185620.17-185620.98" + wire width 7 $pos$libresoc.v:185620$12025_Y + attribute \src "libresoc.v:185657.18-185657.102" + wire $reduce_or$libresoc.v:185657$12062_Y + attribute \src "libresoc.v:185627.18-185627.109" + wire width 8 $sub$libresoc.v:185627$12032_Y + attribute \src "libresoc.v:185630.18-185630.110" + wire width 8 $sub$libresoc.v:185630$12035_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" @@ -349391,7 +349097,7 @@ module \rotator wire input 10 \clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" wire width 32 \hi32 - attribute \src "libresoc.v:185723.7-185723.15" + attribute \src "libresoc.v:185471.7-185471.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire input 6 \is_32bit @@ -349448,7 +349154,7 @@ module \rotator attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire input 11 \sign_ext_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $and$libresoc.v:185874$12033 + cell $and $and$libresoc.v:185622$12027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349456,10 +349162,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \is_32bit - connect \Y $and$libresoc.v:185874$12033_Y + connect \Y $and$libresoc.v:185622$12027_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $and $and$libresoc.v:185876$12035 + cell $and $and$libresoc.v:185624$12029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349467,10 +349173,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$16 - connect \Y $and$libresoc.v:185876$12035_Y + connect \Y $and$libresoc.v:185624$12029_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $and $and$libresoc.v:185885$12044 + cell $and $and$libresoc.v:185633$12038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349478,10 +349184,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_left connect \B \$34 - connect \Y $and$libresoc.v:185885$12044_Y + connect \Y $and$libresoc.v:185633$12038_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $and$libresoc.v:185887$12046 + cell $and $and$libresoc.v:185635$12040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349489,10 +349195,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \arith connect \B \repl32 [63] - connect \Y $and$libresoc.v:185887$12046_Y + connect \Y $and$libresoc.v:185635$12040_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $and$libresoc.v:185889$12048 + cell $and $and$libresoc.v:185637$12042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349500,10 +349206,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$42 - connect \Y $and$libresoc.v:185889$12048_Y + connect \Y $and$libresoc.v:185637$12042_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185890$12049 + cell $and $and$libresoc.v:185638$12043 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349511,10 +349217,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:185890$12049_Y + connect \Y $and$libresoc.v:185638$12043_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185891$12050 + cell $and $and$libresoc.v:185639$12044 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349522,10 +349228,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$46 - connect \Y $and$libresoc.v:185891$12050_Y + connect \Y $and$libresoc.v:185639$12044_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185893$12052 + cell $and $and$libresoc.v:185641$12046 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349533,10 +349239,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:185893$12052_Y + connect \Y $and$libresoc.v:185641$12046_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185895$12054 + cell $and $and$libresoc.v:185643$12048 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349544,10 +349250,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$50 - connect \Y $and$libresoc.v:185895$12054_Y + connect \Y $and$libresoc.v:185643$12048_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:185898$12057 + cell $and $and$libresoc.v:185646$12051 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349555,10 +349261,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$58 - connect \Y $and$libresoc.v:185898$12057_Y + connect \Y $and$libresoc.v:185646$12051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:185901$12060 + cell $and $and$libresoc.v:185649$12054 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349566,10 +349272,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$62 - connect \Y $and$libresoc.v:185901$12060_Y + connect \Y $and$libresoc.v:185649$12054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $and$libresoc.v:185903$12062 + cell $and $and$libresoc.v:185651$12056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349577,10 +349283,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \shift [6] connect \B \$4 - connect \Y $and$libresoc.v:185903$12062_Y + connect \Y $and$libresoc.v:185651$12056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" - cell $and $and$libresoc.v:185904$12063 + cell $and $and$libresoc.v:185652$12057 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349588,10 +349294,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \mr - connect \Y $and$libresoc.v:185904$12063_Y + connect \Y $and$libresoc.v:185652$12057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$libresoc.v:185908$12067 + cell $and $and$libresoc.v:185656$12061 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349599,18 +349305,18 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rs connect \B \$77 - connect \Y $and$libresoc.v:185908$12067_Y + connect \Y $and$libresoc.v:185656$12061_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$libresoc.v:185872$12030 + cell $pos $extend$libresoc.v:185620$12024 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \mb - connect \Y $extend$libresoc.v:185872$12030_Y + connect \Y $extend$libresoc.v:185620$12024_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $gt$libresoc.v:185888$12047 + cell $gt $gt$libresoc.v:185636$12041 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -349618,10 +349324,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 [5:0] connect \B \me$13 [5:0] - connect \Y $gt$libresoc.v:185888$12047_Y + connect \Y $gt$libresoc.v:185636$12041_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:185878$12037 + cell $le $le$libresoc.v:185626$12031 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -349629,10 +349335,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:185878$12037_Y + connect \Y $le$libresoc.v:185626$12031_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:185880$12039 + cell $le $le$libresoc.v:185628$12033 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -349640,98 +349346,98 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:185880$12039_Y + connect \Y $le$libresoc.v:185628$12033_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $neg$libresoc.v:185881$12040 + cell $neg $neg$libresoc.v:185629$12034 parameter \A_SIGNED 1 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { \shift_signed [5] \shift_signed } - connect \Y $neg$libresoc.v:185881$12040_Y + connect \Y $neg$libresoc.v:185629$12034_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $not$libresoc.v:185873$12032 + cell $not $not$libresoc.v:185621$12026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sh [5] - connect \Y $not$libresoc.v:185873$12032_Y + connect \Y $not$libresoc.v:185621$12026_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$libresoc.v:185875$12034 + cell $not $not$libresoc.v:185623$12028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left - connect \Y $not$libresoc.v:185875$12034_Y + connect \Y $not$libresoc.v:185623$12028_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$libresoc.v:185877$12036 + cell $not $not$libresoc.v:185625$12030 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \sh [5:0] - connect \Y $not$libresoc.v:185877$12036_Y + connect \Y $not$libresoc.v:185625$12030_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$libresoc.v:185883$12042 + cell $not $not$libresoc.v:185631$12036 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \left_mask_mask - connect \Y $not$libresoc.v:185883$12042_Y + connect \Y $not$libresoc.v:185631$12036_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $not$libresoc.v:185884$12043 + cell $not $not$libresoc.v:185632$12037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right - connect \Y $not$libresoc.v:185884$12043_Y + connect \Y $not$libresoc.v:185632$12037_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $not$libresoc.v:185892$12051 + cell $not $not$libresoc.v:185640$12045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit - connect \Y $not$libresoc.v:185892$12051_Y + connect \Y $not$libresoc.v:185640$12045_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $not $not$libresoc.v:185894$12053 + cell $not $not$libresoc.v:185642$12047 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$51 - connect \Y $not$libresoc.v:185894$12053_Y + connect \Y $not$libresoc.v:185642$12047_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $not $not$libresoc.v:185900$12059 + cell $not $not$libresoc.v:185648$12053 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$63 - connect \Y $not$libresoc.v:185900$12059_Y + connect \Y $not$libresoc.v:185648$12053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$libresoc.v:185905$12064 + cell $not $not$libresoc.v:185653$12058 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr - connect \Y $not$libresoc.v:185905$12064_Y + connect \Y $not$libresoc.v:185653$12058_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$libresoc.v:185907$12066 + cell $not $not$libresoc.v:185655$12060 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ml - connect \Y $not$libresoc.v:185907$12066_Y + connect \Y $not$libresoc.v:185655$12060_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$libresoc.v:185886$12045 + cell $or $or$libresoc.v:185634$12039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349739,10 +349445,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \$36 connect \B \right_shift - connect \Y $or$libresoc.v:185886$12045_Y + connect \Y $or$libresoc.v:185634$12039_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$libresoc.v:185896$12055 + cell $or $or$libresoc.v:185644$12049 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349750,10 +349456,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$48 connect \B \$54 - connect \Y $or$libresoc.v:185896$12055_Y + connect \Y $or$libresoc.v:185644$12049_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185897$12056 + cell $or $or$libresoc.v:185645$12050 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349761,10 +349467,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:185897$12056_Y + connect \Y $or$libresoc.v:185645$12050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185899$12058 + cell $or $or$libresoc.v:185647$12052 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349772,10 +349478,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:185899$12058_Y + connect \Y $or$libresoc.v:185647$12052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185902$12061 + cell $or $or$libresoc.v:185650$12055 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349783,10 +349489,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$60 connect \B \$66 - connect \Y $or$libresoc.v:185902$12061_Y + connect \Y $or$libresoc.v:185650$12055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$libresoc.v:185906$12065 + cell $or $or$libresoc.v:185654$12059 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349794,26 +349500,26 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$72 - connect \Y $or$libresoc.v:185906$12065_Y + connect \Y $or$libresoc.v:185654$12059_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$libresoc.v:185872$12031 + cell $pos $pos$libresoc.v:185620$12025 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:185872$12030_Y - connect \Y $pos$libresoc.v:185872$12031_Y + connect \A $extend$libresoc.v:185620$12024_Y + connect \Y $pos$libresoc.v:185620$12025_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$libresoc.v:185909$12068 + cell $reduce_or $reduce_or$libresoc.v:185657$12062 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \$79 - connect \Y $reduce_or$libresoc.v:185909$12068_Y + connect \Y $reduce_or$libresoc.v:185657$12062_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$libresoc.v:185879$12038 + cell $sub $sub$libresoc.v:185627$12032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -349821,10 +349527,10 @@ module \rotator parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \mb$8 - connect \Y $sub$libresoc.v:185879$12038_Y + connect \Y $sub$libresoc.v:185627$12032_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$libresoc.v:185882$12041 + cell $sub $sub$libresoc.v:185630$12035 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -349832,42 +349538,42 @@ module \rotator parameter \Y_WIDTH 8 connect \A 6'111111 connect \B \me$13 - connect \Y $sub$libresoc.v:185882$12041_Y + connect \Y $sub$libresoc.v:185630$12035_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:185910.13-185913.4" + attribute \src "libresoc.v:185658.13-185661.4" cell \left_mask \left_mask connect \mask \left_mask_mask connect \shift \left_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:185914.14-185917.4" + attribute \src "libresoc.v:185662.14-185665.4" cell \right_mask \right_mask connect \mask \right_mask_mask connect \shift \right_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:185918.8-185922.4" + attribute \src "libresoc.v:185666.8-185670.4" cell \rotl \rotl connect \a \rotl_a connect \b \rotl_b connect \o \rotl_o end - attribute \src "libresoc.v:185723.7-185723.20" - process $proc$libresoc.v:185723$12084 + attribute \src "libresoc.v:185471.7-185471.20" + process $proc$libresoc.v:185471$12078 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185923.3-185937.6" - process $proc$libresoc.v:185923$12069 + attribute \src "libresoc.v:185671.3-185685.6" + process $proc$libresoc.v:185671$12063 assign { } { } assign $0\hi32[31:0] $1\hi32[31:0] - attribute \src "libresoc.v:185924.5-185924.29" + attribute \src "libresoc.v:185672.5-185672.29" switch \initial - attribute \src "libresoc.v:185924.9-185924.17" + attribute \src "libresoc.v:185672.9-185672.17" case 1'1 case end @@ -349889,14 +349595,14 @@ module \rotator sync always update \hi32 $0\hi32[31:0] end - attribute \src "libresoc.v:185938.3-185947.6" - process $proc$libresoc.v:185938$12070 + attribute \src "libresoc.v:185686.3-185695.6" + process $proc$libresoc.v:185686$12064 assign { } { } assign { } { } assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "libresoc.v:185939.5-185939.29" + attribute \src "libresoc.v:185687.5-185687.29" switch \initial - attribute \src "libresoc.v:185939.9-185939.17" + attribute \src "libresoc.v:185687.9-185687.17" case 1'1 case end @@ -349912,13 +349618,13 @@ module \rotator sync always update \right_mask_shift $0\right_mask_shift[6:0] end - attribute \src "libresoc.v:185948.3-185959.6" - process $proc$libresoc.v:185948$12071 + attribute \src "libresoc.v:185696.3-185707.6" + process $proc$libresoc.v:185696$12065 assign { } { } assign $0\mr[63:0] $1\mr[63:0] - attribute \src "libresoc.v:185949.5-185949.29" + attribute \src "libresoc.v:185697.5-185697.29" switch \initial - attribute \src "libresoc.v:185949.9-185949.17" + attribute \src "libresoc.v:185697.9-185697.17" case 1'1 case end @@ -349936,13 +349642,13 @@ module \rotator sync always update \mr $0\mr[63:0] end - attribute \src "libresoc.v:185960.3-185971.6" - process $proc$libresoc.v:185960$12072 + attribute \src "libresoc.v:185708.3-185719.6" + process $proc$libresoc.v:185708$12066 assign { } { } assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "libresoc.v:185961.5-185961.29" + attribute \src "libresoc.v:185709.5-185709.29" switch \initial - attribute \src "libresoc.v:185961.9-185961.17" + attribute \src "libresoc.v:185709.9-185709.17" case 1'1 case end @@ -349960,14 +349666,14 @@ module \rotator sync always update \output_mode $0\output_mode[1:0] end - attribute \src "libresoc.v:185972.3-185990.6" - process $proc$libresoc.v:185972$12073 + attribute \src "libresoc.v:185720.3-185738.6" + process $proc$libresoc.v:185720$12067 assign { } { } assign { } { } assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "libresoc.v:185973.5-185973.29" + attribute \src "libresoc.v:185721.5-185721.29" switch \initial - attribute \src "libresoc.v:185973.9-185973.17" + attribute \src "libresoc.v:185721.9-185721.17" case 1'1 case end @@ -349995,14 +349701,14 @@ module \rotator sync always update \result_o $0\result_o[63:0] end - attribute \src "libresoc.v:185991.3-186009.6" - process $proc$libresoc.v:185991$12074 + attribute \src "libresoc.v:185739.3-185757.6" + process $proc$libresoc.v:185739$12068 assign { } { } assign { } { } assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "libresoc.v:185992.5-185992.29" + attribute \src "libresoc.v:185740.5-185740.29" switch \initial - attribute \src "libresoc.v:185992.9-185992.17" + attribute \src "libresoc.v:185740.9-185740.17" case 1'1 case end @@ -350027,13 +349733,13 @@ module \rotator sync always update \carry_out_o $0\carry_out_o[0:0] end - attribute \src "libresoc.v:186010.3-186021.6" - process $proc$libresoc.v:186010$12075 + attribute \src "libresoc.v:185758.3-185769.6" + process $proc$libresoc.v:185758$12069 assign { } { } assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "libresoc.v:186011.5-186011.29" + attribute \src "libresoc.v:185759.5-185759.29" switch \initial - attribute \src "libresoc.v:186011.9-186011.17" + attribute \src "libresoc.v:185759.9-185759.17" case 1'1 case end @@ -350051,13 +349757,13 @@ module \rotator sync always update \rot_count $0\rot_count[5:0] end - attribute \src "libresoc.v:186022.3-186055.6" - process $proc$libresoc.v:186022$12076 + attribute \src "libresoc.v:185770.3-185803.6" + process $proc$libresoc.v:185770$12070 assign { } { } - assign $0\mb$8[6:0]$12077 $1\mb$8[6:0]$12078 - attribute \src "libresoc.v:186023.5-186023.29" + assign $0\mb$8[6:0]$12071 $1\mb$8[6:0]$12072 + attribute \src "libresoc.v:185771.5-185771.29" switch \initial - attribute \src "libresoc.v:186023.9-186023.17" + attribute \src "libresoc.v:185771.9-185771.17" case 1'1 case end @@ -350066,48 +349772,48 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\mb$8[6:0]$12078 [4:0] \$9 [4:0] - assign $1\mb$8[6:0]$12078 [6:5] $2\mb$8[6:5]$12079 + assign $1\mb$8[6:0]$12072 [4:0] \$9 [4:0] + assign $1\mb$8[6:0]$12072 [6:5] $2\mb$8[6:5]$12073 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\mb$8[6:5]$12079 2'01 + assign $2\mb$8[6:5]$12073 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\mb$8[6:5]$12079 { 1'0 \mb_extra } + assign $2\mb$8[6:5]$12073 { 1'0 \mb_extra } end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\mb$8[6:0]$12078 [4:0] \sh [4:0] - assign $1\mb$8[6:0]$12078 [6:5] $3\mb$8[6:5]$12080 + assign $1\mb$8[6:0]$12072 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$12072 [6:5] $3\mb$8[6:5]$12074 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\mb$8[6:5]$12080 { \sh [5] \$11 } + assign $3\mb$8[6:5]$12074 { \sh [5] \$11 } case - assign $3\mb$8[6:5]$12080 \sh [6:5] + assign $3\mb$8[6:5]$12074 \sh [6:5] end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\mb$8[6:0]$12078 { 1'0 \is_32bit 5'00000 } + assign $1\mb$8[6:0]$12072 { 1'0 \is_32bit 5'00000 } end sync always - update \mb$8 $0\mb$8[6:0]$12077 + update \mb$8 $0\mb$8[6:0]$12071 end - attribute \src "libresoc.v:186056.3-186070.6" - process $proc$libresoc.v:186056$12081 + attribute \src "libresoc.v:185804.3-185818.6" + process $proc$libresoc.v:185804$12075 assign { } { } - assign $0\me$13[6:0]$12082 $1\me$13[6:0]$12083 - attribute \src "libresoc.v:186057.5-186057.29" + assign $0\me$13[6:0]$12076 $1\me$13[6:0]$12077 + attribute \src "libresoc.v:185805.5-185805.29" switch \initial - attribute \src "libresoc.v:186057.9-186057.17" + attribute \src "libresoc.v:185805.9-185805.17" case 1'1 case end @@ -350116,57 +349822,57 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\me$13[6:0]$12083 { 2'01 \me } + assign $1\me$13[6:0]$12077 { 2'01 \me } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\me$13[6:0]$12083 { 1'0 \mb_extra \mb } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\me$13[6:0]$12083 { \sh [6] \$20 } - end - sync always - update \me$13 $0\me$13[6:0]$12082 - end - connect \$9 $pos$libresoc.v:185872$12031_Y - connect \$11 $not$libresoc.v:185873$12032_Y - connect \$14 $and$libresoc.v:185874$12033_Y - connect \$16 $not$libresoc.v:185875$12034_Y - connect \$18 $and$libresoc.v:185876$12035_Y - connect \$20 $not$libresoc.v:185877$12036_Y - connect \$22 $le$libresoc.v:185878$12037_Y - connect \$25 $sub$libresoc.v:185879$12038_Y - connect \$27 $le$libresoc.v:185880$12039_Y - connect \$2 $neg$libresoc.v:185881$12040_Y - connect \$30 $sub$libresoc.v:185882$12041_Y - connect \$32 $not$libresoc.v:185883$12042_Y - connect \$34 $not$libresoc.v:185884$12043_Y - connect \$36 $and$libresoc.v:185885$12044_Y - connect \$38 $or$libresoc.v:185886$12045_Y - connect \$40 $and$libresoc.v:185887$12046_Y - connect \$42 $gt$libresoc.v:185888$12047_Y - connect \$44 $and$libresoc.v:185889$12048_Y - connect \$46 $and$libresoc.v:185890$12049_Y - connect \$48 $and$libresoc.v:185891$12050_Y - connect \$4 $not$libresoc.v:185892$12051_Y - connect \$51 $and$libresoc.v:185893$12052_Y - connect \$50 $not$libresoc.v:185894$12053_Y - connect \$54 $and$libresoc.v:185895$12054_Y - connect \$56 $or$libresoc.v:185896$12055_Y - connect \$58 $or$libresoc.v:185897$12056_Y - connect \$60 $and$libresoc.v:185898$12057_Y - connect \$63 $or$libresoc.v:185899$12058_Y - connect \$62 $not$libresoc.v:185900$12059_Y - connect \$66 $and$libresoc.v:185901$12060_Y - connect \$68 $or$libresoc.v:185902$12061_Y - connect \$6 $and$libresoc.v:185903$12062_Y - connect \$70 $and$libresoc.v:185904$12063_Y - connect \$72 $not$libresoc.v:185905$12064_Y - connect \$74 $or$libresoc.v:185906$12065_Y - connect \$77 $not$libresoc.v:185907$12066_Y - connect \$79 $and$libresoc.v:185908$12067_Y - connect \$76 $reduce_or$libresoc.v:185909$12068_Y + assign $1\me$13[6:0]$12077 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$12077 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$12076 + end + connect \$9 $pos$libresoc.v:185620$12025_Y + connect \$11 $not$libresoc.v:185621$12026_Y + connect \$14 $and$libresoc.v:185622$12027_Y + connect \$16 $not$libresoc.v:185623$12028_Y + connect \$18 $and$libresoc.v:185624$12029_Y + connect \$20 $not$libresoc.v:185625$12030_Y + connect \$22 $le$libresoc.v:185626$12031_Y + connect \$25 $sub$libresoc.v:185627$12032_Y + connect \$27 $le$libresoc.v:185628$12033_Y + connect \$2 $neg$libresoc.v:185629$12034_Y + connect \$30 $sub$libresoc.v:185630$12035_Y + connect \$32 $not$libresoc.v:185631$12036_Y + connect \$34 $not$libresoc.v:185632$12037_Y + connect \$36 $and$libresoc.v:185633$12038_Y + connect \$38 $or$libresoc.v:185634$12039_Y + connect \$40 $and$libresoc.v:185635$12040_Y + connect \$42 $gt$libresoc.v:185636$12041_Y + connect \$44 $and$libresoc.v:185637$12042_Y + connect \$46 $and$libresoc.v:185638$12043_Y + connect \$48 $and$libresoc.v:185639$12044_Y + connect \$4 $not$libresoc.v:185640$12045_Y + connect \$51 $and$libresoc.v:185641$12046_Y + connect \$50 $not$libresoc.v:185642$12047_Y + connect \$54 $and$libresoc.v:185643$12048_Y + connect \$56 $or$libresoc.v:185644$12049_Y + connect \$58 $or$libresoc.v:185645$12050_Y + connect \$60 $and$libresoc.v:185646$12051_Y + connect \$63 $or$libresoc.v:185647$12052_Y + connect \$62 $not$libresoc.v:185648$12053_Y + connect \$66 $and$libresoc.v:185649$12054_Y + connect \$68 $or$libresoc.v:185650$12055_Y + connect \$6 $and$libresoc.v:185651$12056_Y + connect \$70 $and$libresoc.v:185652$12057_Y + connect \$72 $not$libresoc.v:185653$12058_Y + connect \$74 $or$libresoc.v:185654$12059_Y + connect \$77 $not$libresoc.v:185655$12060_Y + connect \$79 $and$libresoc.v:185656$12061_Y + connect \$76 $reduce_or$libresoc.v:185657$12062_Y connect \$1 \$2 connect \$24 \$25 connect \$29 \$30 @@ -350179,15 +349885,15 @@ module \rotator connect \shift_signed \shift [5:0] connect \repl32 { \hi32 \rs [31:0] } end -attribute \src "libresoc.v:186086.1-186100.10" +attribute \src "libresoc.v:185834.1-185848.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" attribute \generator "nMigen" module \rotl - attribute \src "libresoc.v:186098.17-186098.32" - wire width 128 $shr$libresoc.v:186098$12086_Y - attribute \src "libresoc.v:186097.17-186097.100" - wire width 8 $sub$libresoc.v:186097$12085_Y + attribute \src "libresoc.v:185846.17-185846.32" + wire width 128 $shr$libresoc.v:185846$12080_Y + attribute \src "libresoc.v:185845.17-185845.100" + wire width 8 $sub$libresoc.v:185845$12079_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" @@ -350198,8 +349904,8 @@ module \rotl wire width 6 input 1 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 output 2 \o - attribute \src "libresoc.v:186098.17-186098.32" - cell $shr $shr$libresoc.v:186098$12086 + attribute \src "libresoc.v:185846.17-185846.32" + cell $shr $shr$libresoc.v:185846$12080 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -350207,10 +349913,10 @@ module \rotl parameter \Y_WIDTH 128 connect \A { \a \a } connect \B \$2 - connect \Y $shr$libresoc.v:186098$12086_Y + connect \Y $shr$libresoc.v:185846$12080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$libresoc.v:186097$12085 + cell $sub $sub$libresoc.v:185845$12079 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -350218,43 +349924,43 @@ module \rotl parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \b - connect \Y $sub$libresoc.v:186097$12085_Y + connect \Y $sub$libresoc.v:185845$12079_Y end - connect \$2 $sub$libresoc.v:186097$12085_Y - connect \$1 $shr$libresoc.v:186098$12086_Y [63:0] + connect \$2 $sub$libresoc.v:185845$12079_Y + connect \$1 $shr$libresoc.v:185846$12080_Y [63:0] connect \o \$1 end -attribute \src "libresoc.v:186104.1-186162.10" +attribute \src "libresoc.v:185852.1-185910.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" attribute \generator "nMigen" module \rst_l - attribute \src "libresoc.v:186105.7-186105.20" + attribute \src "libresoc.v:185853.7-185853.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186150.3-186158.6" - wire $0\q_int$next[0:0]$12097 - attribute \src "libresoc.v:186148.3-186149.27" + attribute \src "libresoc.v:185898.3-185906.6" + wire $0\q_int$next[0:0]$12091 + attribute \src "libresoc.v:185896.3-185897.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186150.3-186158.6" - wire $1\q_int$next[0:0]$12098 - attribute \src "libresoc.v:186127.7-186127.19" + attribute \src "libresoc.v:185898.3-185906.6" + wire $1\q_int$next[0:0]$12092 + attribute \src "libresoc.v:185875.7-185875.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186140.17-186140.96" - wire $and$libresoc.v:186140$12087_Y - attribute \src "libresoc.v:186145.17-186145.96" - wire $and$libresoc.v:186145$12092_Y - attribute \src "libresoc.v:186142.18-186142.93" - wire $not$libresoc.v:186142$12089_Y - attribute \src "libresoc.v:186144.17-186144.92" - wire $not$libresoc.v:186144$12091_Y - attribute \src "libresoc.v:186147.17-186147.92" - wire $not$libresoc.v:186147$12094_Y - attribute \src "libresoc.v:186141.18-186141.98" - wire $or$libresoc.v:186141$12088_Y - attribute \src "libresoc.v:186143.18-186143.99" - wire $or$libresoc.v:186143$12090_Y - attribute \src "libresoc.v:186146.17-186146.97" - wire $or$libresoc.v:186146$12093_Y + attribute \src "libresoc.v:185888.17-185888.96" + wire $and$libresoc.v:185888$12081_Y + attribute \src "libresoc.v:185893.17-185893.96" + wire $and$libresoc.v:185893$12086_Y + attribute \src "libresoc.v:185890.18-185890.93" + wire $not$libresoc.v:185890$12083_Y + attribute \src "libresoc.v:185892.17-185892.92" + wire $not$libresoc.v:185892$12085_Y + attribute \src "libresoc.v:185895.17-185895.92" + wire $not$libresoc.v:185895$12088_Y + attribute \src "libresoc.v:185889.18-185889.98" + wire $or$libresoc.v:185889$12082_Y + attribute \src "libresoc.v:185891.18-185891.99" + wire $or$libresoc.v:185891$12084_Y + attribute \src "libresoc.v:185894.17-185894.97" + wire $or$libresoc.v:185894$12087_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -350271,11 +349977,11 @@ module \rst_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:186105.7-186105.15" + attribute \src "libresoc.v:185853.7-185853.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -350292,7 +349998,7 @@ module \rst_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186140$12087 + cell $and $and$libresoc.v:185888$12081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350300,10 +350006,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186140$12087_Y + connect \Y $and$libresoc.v:185888$12081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186145$12092 + cell $and $and$libresoc.v:185893$12086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350311,34 +350017,34 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186145$12092_Y + connect \Y $and$libresoc.v:185893$12086_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186142$12089 + cell $not $not$libresoc.v:185890$12083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186142$12089_Y + connect \Y $not$libresoc.v:185890$12083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186144$12091 + cell $not $not$libresoc.v:185892$12085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186144$12091_Y + connect \Y $not$libresoc.v:185892$12085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186147$12094 + cell $not $not$libresoc.v:185895$12088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186147$12094_Y + connect \Y $not$libresoc.v:185895$12088_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186141$12088 + cell $or $or$libresoc.v:185889$12082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350346,10 +350052,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186141$12088_Y + connect \Y $or$libresoc.v:185889$12082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186143$12090 + cell $or $or$libresoc.v:185891$12084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350357,10 +350063,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186143$12090_Y + connect \Y $or$libresoc.v:185891$12084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186146$12093 + cell $or $or$libresoc.v:185894$12087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350368,39 +350074,39 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186146$12093_Y + connect \Y $or$libresoc.v:185894$12087_Y end - attribute \src "libresoc.v:186105.7-186105.20" - process $proc$libresoc.v:186105$12099 + attribute \src "libresoc.v:185853.7-185853.20" + process $proc$libresoc.v:185853$12093 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186127.7-186127.19" - process $proc$libresoc.v:186127$12100 + attribute \src "libresoc.v:185875.7-185875.19" + process $proc$libresoc.v:185875$12094 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186148.3-186149.27" - process $proc$libresoc.v:186148$12095 + attribute \src "libresoc.v:185896.3-185897.27" + process $proc$libresoc.v:185896$12089 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186150.3-186158.6" - process $proc$libresoc.v:186150$12096 + attribute \src "libresoc.v:185898.3-185906.6" + process $proc$libresoc.v:185898$12090 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12097 $1\q_int$next[0:0]$12098 - attribute \src "libresoc.v:186151.5-186151.29" + assign $0\q_int$next[0:0]$12091 $1\q_int$next[0:0]$12092 + attribute \src "libresoc.v:185899.5-185899.29" switch \initial - attribute \src "libresoc.v:186151.9-186151.17" + attribute \src "libresoc.v:185899.9-185899.17" case 1'1 case end @@ -350409,56 +350115,56 @@ module \rst_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12098 1'0 + assign $1\q_int$next[0:0]$12092 1'0 case - assign $1\q_int$next[0:0]$12098 \$5 + assign $1\q_int$next[0:0]$12092 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12097 + update \q_int$next $0\q_int$next[0:0]$12091 end - connect \$9 $and$libresoc.v:186140$12087_Y - connect \$11 $or$libresoc.v:186141$12088_Y - connect \$13 $not$libresoc.v:186142$12089_Y - connect \$15 $or$libresoc.v:186143$12090_Y - connect \$1 $not$libresoc.v:186144$12091_Y - connect \$3 $and$libresoc.v:186145$12092_Y - connect \$5 $or$libresoc.v:186146$12093_Y - connect \$7 $not$libresoc.v:186147$12094_Y + connect \$9 $and$libresoc.v:185888$12081_Y + connect \$11 $or$libresoc.v:185889$12082_Y + connect \$13 $not$libresoc.v:185890$12083_Y + connect \$15 $or$libresoc.v:185891$12084_Y + connect \$1 $not$libresoc.v:185892$12085_Y + connect \$3 $and$libresoc.v:185893$12086_Y + connect \$5 $or$libresoc.v:185894$12087_Y + connect \$7 $not$libresoc.v:185895$12088_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186166.1-186224.10" +attribute \src "libresoc.v:185914.1-185972.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" attribute \generator "nMigen" module \rst_l$104 - attribute \src "libresoc.v:186167.7-186167.20" + attribute \src "libresoc.v:185915.7-185915.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186212.3-186220.6" - wire $0\q_int$next[0:0]$12111 - attribute \src "libresoc.v:186210.3-186211.27" + attribute \src "libresoc.v:185960.3-185968.6" + wire $0\q_int$next[0:0]$12105 + attribute \src "libresoc.v:185958.3-185959.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186212.3-186220.6" - wire $1\q_int$next[0:0]$12112 - attribute \src "libresoc.v:186189.7-186189.19" + attribute \src "libresoc.v:185960.3-185968.6" + wire $1\q_int$next[0:0]$12106 + attribute \src "libresoc.v:185937.7-185937.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186202.17-186202.96" - wire $and$libresoc.v:186202$12101_Y - attribute \src "libresoc.v:186207.17-186207.96" - wire $and$libresoc.v:186207$12106_Y - attribute \src "libresoc.v:186204.18-186204.93" - wire $not$libresoc.v:186204$12103_Y - attribute \src "libresoc.v:186206.17-186206.92" - wire $not$libresoc.v:186206$12105_Y - attribute \src "libresoc.v:186209.17-186209.92" - wire $not$libresoc.v:186209$12108_Y - attribute \src "libresoc.v:186203.18-186203.98" - wire $or$libresoc.v:186203$12102_Y - attribute \src "libresoc.v:186205.18-186205.99" - wire $or$libresoc.v:186205$12104_Y - attribute \src "libresoc.v:186208.17-186208.97" - wire $or$libresoc.v:186208$12107_Y + attribute \src "libresoc.v:185950.17-185950.96" + wire $and$libresoc.v:185950$12095_Y + attribute \src "libresoc.v:185955.17-185955.96" + wire $and$libresoc.v:185955$12100_Y + attribute \src "libresoc.v:185952.18-185952.93" + wire $not$libresoc.v:185952$12097_Y + attribute \src "libresoc.v:185954.17-185954.92" + wire $not$libresoc.v:185954$12099_Y + attribute \src "libresoc.v:185957.17-185957.92" + wire $not$libresoc.v:185957$12102_Y + attribute \src "libresoc.v:185951.18-185951.98" + wire $or$libresoc.v:185951$12096_Y + attribute \src "libresoc.v:185953.18-185953.99" + wire $or$libresoc.v:185953$12098_Y + attribute \src "libresoc.v:185956.17-185956.97" + wire $or$libresoc.v:185956$12101_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -350475,11 +350181,11 @@ module \rst_l$104 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:186167.7-186167.15" + attribute \src "libresoc.v:185915.7-185915.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -350496,7 +350202,7 @@ module \rst_l$104 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186202$12101 + cell $and $and$libresoc.v:185950$12095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350504,10 +350210,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186202$12101_Y + connect \Y $and$libresoc.v:185950$12095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186207$12106 + cell $and $and$libresoc.v:185955$12100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350515,34 +350221,34 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186207$12106_Y + connect \Y $and$libresoc.v:185955$12100_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186204$12103 + cell $not $not$libresoc.v:185952$12097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186204$12103_Y + connect \Y $not$libresoc.v:185952$12097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186206$12105 + cell $not $not$libresoc.v:185954$12099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186206$12105_Y + connect \Y $not$libresoc.v:185954$12099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186209$12108 + cell $not $not$libresoc.v:185957$12102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186209$12108_Y + connect \Y $not$libresoc.v:185957$12102_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186203$12102 + cell $or $or$libresoc.v:185951$12096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350550,10 +350256,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186203$12102_Y + connect \Y $or$libresoc.v:185951$12096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186205$12104 + cell $or $or$libresoc.v:185953$12098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350561,10 +350267,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186205$12104_Y + connect \Y $or$libresoc.v:185953$12098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186208$12107 + cell $or $or$libresoc.v:185956$12101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350572,39 +350278,39 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186208$12107_Y + connect \Y $or$libresoc.v:185956$12101_Y end - attribute \src "libresoc.v:186167.7-186167.20" - process $proc$libresoc.v:186167$12113 + attribute \src "libresoc.v:185915.7-185915.20" + process $proc$libresoc.v:185915$12107 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186189.7-186189.19" - process $proc$libresoc.v:186189$12114 + attribute \src "libresoc.v:185937.7-185937.19" + process $proc$libresoc.v:185937$12108 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186210.3-186211.27" - process $proc$libresoc.v:186210$12109 + attribute \src "libresoc.v:185958.3-185959.27" + process $proc$libresoc.v:185958$12103 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186212.3-186220.6" - process $proc$libresoc.v:186212$12110 + attribute \src "libresoc.v:185960.3-185968.6" + process $proc$libresoc.v:185960$12104 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12111 $1\q_int$next[0:0]$12112 - attribute \src "libresoc.v:186213.5-186213.29" + assign $0\q_int$next[0:0]$12105 $1\q_int$next[0:0]$12106 + attribute \src "libresoc.v:185961.5-185961.29" switch \initial - attribute \src "libresoc.v:186213.9-186213.17" + attribute \src "libresoc.v:185961.9-185961.17" case 1'1 case end @@ -350613,56 +350319,56 @@ module \rst_l$104 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12112 1'0 + assign $1\q_int$next[0:0]$12106 1'0 case - assign $1\q_int$next[0:0]$12112 \$5 + assign $1\q_int$next[0:0]$12106 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12111 + update \q_int$next $0\q_int$next[0:0]$12105 end - connect \$9 $and$libresoc.v:186202$12101_Y - connect \$11 $or$libresoc.v:186203$12102_Y - connect \$13 $not$libresoc.v:186204$12103_Y - connect \$15 $or$libresoc.v:186205$12104_Y - connect \$1 $not$libresoc.v:186206$12105_Y - connect \$3 $and$libresoc.v:186207$12106_Y - connect \$5 $or$libresoc.v:186208$12107_Y - connect \$7 $not$libresoc.v:186209$12108_Y + connect \$9 $and$libresoc.v:185950$12095_Y + connect \$11 $or$libresoc.v:185951$12096_Y + connect \$13 $not$libresoc.v:185952$12097_Y + connect \$15 $or$libresoc.v:185953$12098_Y + connect \$1 $not$libresoc.v:185954$12099_Y + connect \$3 $and$libresoc.v:185955$12100_Y + connect \$5 $or$libresoc.v:185956$12101_Y + connect \$7 $not$libresoc.v:185957$12102_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186228.1-186286.10" +attribute \src "libresoc.v:185976.1-186034.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" attribute \generator "nMigen" module \rst_l$122 - attribute \src "libresoc.v:186229.7-186229.20" + attribute \src "libresoc.v:185977.7-185977.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186274.3-186282.6" - wire $0\q_int$next[0:0]$12125 - attribute \src "libresoc.v:186272.3-186273.27" + attribute \src "libresoc.v:186022.3-186030.6" + wire $0\q_int$next[0:0]$12119 + attribute \src "libresoc.v:186020.3-186021.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186274.3-186282.6" - wire $1\q_int$next[0:0]$12126 - attribute \src "libresoc.v:186251.7-186251.19" + attribute \src "libresoc.v:186022.3-186030.6" + wire $1\q_int$next[0:0]$12120 + attribute \src "libresoc.v:185999.7-185999.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186264.17-186264.96" - wire $and$libresoc.v:186264$12115_Y - attribute \src "libresoc.v:186269.17-186269.96" - wire $and$libresoc.v:186269$12120_Y - attribute \src "libresoc.v:186266.18-186266.93" - wire $not$libresoc.v:186266$12117_Y - attribute \src "libresoc.v:186268.17-186268.92" - wire $not$libresoc.v:186268$12119_Y - attribute \src "libresoc.v:186271.17-186271.92" - wire $not$libresoc.v:186271$12122_Y - attribute \src "libresoc.v:186265.18-186265.98" - wire $or$libresoc.v:186265$12116_Y - attribute \src "libresoc.v:186267.18-186267.99" - wire $or$libresoc.v:186267$12118_Y - attribute \src "libresoc.v:186270.17-186270.97" - wire $or$libresoc.v:186270$12121_Y + attribute \src "libresoc.v:186012.17-186012.96" + wire $and$libresoc.v:186012$12109_Y + attribute \src "libresoc.v:186017.17-186017.96" + wire $and$libresoc.v:186017$12114_Y + attribute \src "libresoc.v:186014.18-186014.93" + wire $not$libresoc.v:186014$12111_Y + attribute \src "libresoc.v:186016.17-186016.92" + wire $not$libresoc.v:186016$12113_Y + attribute \src "libresoc.v:186019.17-186019.92" + wire $not$libresoc.v:186019$12116_Y + attribute \src "libresoc.v:186013.18-186013.98" + wire $or$libresoc.v:186013$12110_Y + attribute \src "libresoc.v:186015.18-186015.99" + wire $or$libresoc.v:186015$12112_Y + attribute \src "libresoc.v:186018.17-186018.97" + wire $or$libresoc.v:186018$12115_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -350679,11 +350385,11 @@ module \rst_l$122 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:186229.7-186229.15" + attribute \src "libresoc.v:185977.7-185977.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -350700,7 +350406,7 @@ module \rst_l$122 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186264$12115 + cell $and $and$libresoc.v:186012$12109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350708,10 +350414,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186264$12115_Y + connect \Y $and$libresoc.v:186012$12109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186269$12120 + cell $and $and$libresoc.v:186017$12114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350719,34 +350425,34 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186269$12120_Y + connect \Y $and$libresoc.v:186017$12114_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186266$12117 + cell $not $not$libresoc.v:186014$12111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186266$12117_Y + connect \Y $not$libresoc.v:186014$12111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186268$12119 + cell $not $not$libresoc.v:186016$12113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186268$12119_Y + connect \Y $not$libresoc.v:186016$12113_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186271$12122 + cell $not $not$libresoc.v:186019$12116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186271$12122_Y + connect \Y $not$libresoc.v:186019$12116_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186265$12116 + cell $or $or$libresoc.v:186013$12110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350754,10 +350460,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186265$12116_Y + connect \Y $or$libresoc.v:186013$12110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186267$12118 + cell $or $or$libresoc.v:186015$12112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350765,10 +350471,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186267$12118_Y + connect \Y $or$libresoc.v:186015$12112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186270$12121 + cell $or $or$libresoc.v:186018$12115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350776,39 +350482,39 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186270$12121_Y + connect \Y $or$libresoc.v:186018$12115_Y end - attribute \src "libresoc.v:186229.7-186229.20" - process $proc$libresoc.v:186229$12127 + attribute \src "libresoc.v:185977.7-185977.20" + process $proc$libresoc.v:185977$12121 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186251.7-186251.19" - process $proc$libresoc.v:186251$12128 + attribute \src "libresoc.v:185999.7-185999.19" + process $proc$libresoc.v:185999$12122 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186272.3-186273.27" - process $proc$libresoc.v:186272$12123 + attribute \src "libresoc.v:186020.3-186021.27" + process $proc$libresoc.v:186020$12117 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186274.3-186282.6" - process $proc$libresoc.v:186274$12124 + attribute \src "libresoc.v:186022.3-186030.6" + process $proc$libresoc.v:186022$12118 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12125 $1\q_int$next[0:0]$12126 - attribute \src "libresoc.v:186275.5-186275.29" + assign $0\q_int$next[0:0]$12119 $1\q_int$next[0:0]$12120 + attribute \src "libresoc.v:186023.5-186023.29" switch \initial - attribute \src "libresoc.v:186275.9-186275.17" + attribute \src "libresoc.v:186023.9-186023.17" case 1'1 case end @@ -350817,56 +350523,56 @@ module \rst_l$122 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12126 1'0 + assign $1\q_int$next[0:0]$12120 1'0 case - assign $1\q_int$next[0:0]$12126 \$5 + assign $1\q_int$next[0:0]$12120 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12125 + update \q_int$next $0\q_int$next[0:0]$12119 end - connect \$9 $and$libresoc.v:186264$12115_Y - connect \$11 $or$libresoc.v:186265$12116_Y - connect \$13 $not$libresoc.v:186266$12117_Y - connect \$15 $or$libresoc.v:186267$12118_Y - connect \$1 $not$libresoc.v:186268$12119_Y - connect \$3 $and$libresoc.v:186269$12120_Y - connect \$5 $or$libresoc.v:186270$12121_Y - connect \$7 $not$libresoc.v:186271$12122_Y + connect \$9 $and$libresoc.v:186012$12109_Y + connect \$11 $or$libresoc.v:186013$12110_Y + connect \$13 $not$libresoc.v:186014$12111_Y + connect \$15 $or$libresoc.v:186015$12112_Y + connect \$1 $not$libresoc.v:186016$12113_Y + connect \$3 $and$libresoc.v:186017$12114_Y + connect \$5 $or$libresoc.v:186018$12115_Y + connect \$7 $not$libresoc.v:186019$12116_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186290.1-186348.10" +attribute \src "libresoc.v:186038.1-186096.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" attribute \generator "nMigen" module \rst_l$129 - attribute \src "libresoc.v:186291.7-186291.20" + attribute \src "libresoc.v:186039.7-186039.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186336.3-186344.6" - wire $0\q_int$next[0:0]$12139 - attribute \src "libresoc.v:186334.3-186335.27" + attribute \src "libresoc.v:186084.3-186092.6" + wire $0\q_int$next[0:0]$12133 + attribute \src "libresoc.v:186082.3-186083.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186336.3-186344.6" - wire $1\q_int$next[0:0]$12140 - attribute \src "libresoc.v:186313.7-186313.19" + attribute \src "libresoc.v:186084.3-186092.6" + wire $1\q_int$next[0:0]$12134 + attribute \src "libresoc.v:186061.7-186061.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186326.17-186326.96" - wire $and$libresoc.v:186326$12129_Y - attribute \src "libresoc.v:186331.17-186331.96" - wire $and$libresoc.v:186331$12134_Y - attribute \src "libresoc.v:186328.18-186328.93" - wire $not$libresoc.v:186328$12131_Y - attribute \src "libresoc.v:186330.17-186330.92" - wire $not$libresoc.v:186330$12133_Y - attribute \src "libresoc.v:186333.17-186333.92" - wire $not$libresoc.v:186333$12136_Y - attribute \src "libresoc.v:186327.18-186327.98" - wire $or$libresoc.v:186327$12130_Y - attribute \src "libresoc.v:186329.18-186329.99" - wire $or$libresoc.v:186329$12132_Y - attribute \src "libresoc.v:186332.17-186332.97" - wire $or$libresoc.v:186332$12135_Y + attribute \src "libresoc.v:186074.17-186074.96" + wire $and$libresoc.v:186074$12123_Y + attribute \src "libresoc.v:186079.17-186079.96" + wire $and$libresoc.v:186079$12128_Y + attribute \src "libresoc.v:186076.18-186076.93" + wire $not$libresoc.v:186076$12125_Y + attribute \src "libresoc.v:186078.17-186078.92" + wire $not$libresoc.v:186078$12127_Y + attribute \src "libresoc.v:186081.17-186081.92" + wire $not$libresoc.v:186081$12130_Y + attribute \src "libresoc.v:186075.18-186075.98" + wire $or$libresoc.v:186075$12124_Y + attribute \src "libresoc.v:186077.18-186077.99" + wire $or$libresoc.v:186077$12126_Y + attribute \src "libresoc.v:186080.17-186080.97" + wire $or$libresoc.v:186080$12129_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -350883,11 +350589,11 @@ module \rst_l$129 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:186291.7-186291.15" + attribute \src "libresoc.v:186039.7-186039.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -350904,7 +350610,7 @@ module \rst_l$129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186326$12129 + cell $and $and$libresoc.v:186074$12123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350912,10 +350618,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186326$12129_Y + connect \Y $and$libresoc.v:186074$12123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186331$12134 + cell $and $and$libresoc.v:186079$12128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350923,34 +350629,34 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186331$12134_Y + connect \Y $and$libresoc.v:186079$12128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186328$12131 + cell $not $not$libresoc.v:186076$12125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186328$12131_Y + connect \Y $not$libresoc.v:186076$12125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186330$12133 + cell $not $not$libresoc.v:186078$12127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186330$12133_Y + connect \Y $not$libresoc.v:186078$12127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186333$12136 + cell $not $not$libresoc.v:186081$12130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186333$12136_Y + connect \Y $not$libresoc.v:186081$12130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186327$12130 + cell $or $or$libresoc.v:186075$12124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350958,10 +350664,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186327$12130_Y + connect \Y $or$libresoc.v:186075$12124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186329$12132 + cell $or $or$libresoc.v:186077$12126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350969,10 +350675,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186329$12132_Y + connect \Y $or$libresoc.v:186077$12126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186332$12135 + cell $or $or$libresoc.v:186080$12129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350980,39 +350686,39 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186332$12135_Y + connect \Y $or$libresoc.v:186080$12129_Y end - attribute \src "libresoc.v:186291.7-186291.20" - process $proc$libresoc.v:186291$12141 + attribute \src "libresoc.v:186039.7-186039.20" + process $proc$libresoc.v:186039$12135 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186313.7-186313.19" - process $proc$libresoc.v:186313$12142 + attribute \src "libresoc.v:186061.7-186061.19" + process $proc$libresoc.v:186061$12136 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186334.3-186335.27" - process $proc$libresoc.v:186334$12137 + attribute \src "libresoc.v:186082.3-186083.27" + process $proc$libresoc.v:186082$12131 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186336.3-186344.6" - process $proc$libresoc.v:186336$12138 + attribute \src "libresoc.v:186084.3-186092.6" + process $proc$libresoc.v:186084$12132 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12139 $1\q_int$next[0:0]$12140 - attribute \src "libresoc.v:186337.5-186337.29" + assign $0\q_int$next[0:0]$12133 $1\q_int$next[0:0]$12134 + attribute \src "libresoc.v:186085.5-186085.29" switch \initial - attribute \src "libresoc.v:186337.9-186337.17" + attribute \src "libresoc.v:186085.9-186085.17" case 1'1 case end @@ -351021,56 +350727,56 @@ module \rst_l$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12140 1'0 + assign $1\q_int$next[0:0]$12134 1'0 case - assign $1\q_int$next[0:0]$12140 \$5 + assign $1\q_int$next[0:0]$12134 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12139 + update \q_int$next $0\q_int$next[0:0]$12133 end - connect \$9 $and$libresoc.v:186326$12129_Y - connect \$11 $or$libresoc.v:186327$12130_Y - connect \$13 $not$libresoc.v:186328$12131_Y - connect \$15 $or$libresoc.v:186329$12132_Y - connect \$1 $not$libresoc.v:186330$12133_Y - connect \$3 $and$libresoc.v:186331$12134_Y - connect \$5 $or$libresoc.v:186332$12135_Y - connect \$7 $not$libresoc.v:186333$12136_Y + connect \$9 $and$libresoc.v:186074$12123_Y + connect \$11 $or$libresoc.v:186075$12124_Y + connect \$13 $not$libresoc.v:186076$12125_Y + connect \$15 $or$libresoc.v:186077$12126_Y + connect \$1 $not$libresoc.v:186078$12127_Y + connect \$3 $and$libresoc.v:186079$12128_Y + connect \$5 $or$libresoc.v:186080$12129_Y + connect \$7 $not$libresoc.v:186081$12130_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186352.1-186410.10" +attribute \src "libresoc.v:186100.1-186158.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" attribute \generator "nMigen" module \rst_l$13 - attribute \src "libresoc.v:186353.7-186353.20" + attribute \src "libresoc.v:186101.7-186101.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186398.3-186406.6" - wire $0\q_int$next[0:0]$12153 - attribute \src "libresoc.v:186396.3-186397.27" + attribute \src "libresoc.v:186146.3-186154.6" + wire $0\q_int$next[0:0]$12147 + attribute \src "libresoc.v:186144.3-186145.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186398.3-186406.6" - wire $1\q_int$next[0:0]$12154 - attribute \src "libresoc.v:186375.7-186375.19" + attribute \src "libresoc.v:186146.3-186154.6" + wire $1\q_int$next[0:0]$12148 + attribute \src "libresoc.v:186123.7-186123.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186388.17-186388.96" - wire $and$libresoc.v:186388$12143_Y - attribute \src "libresoc.v:186393.17-186393.96" - wire $and$libresoc.v:186393$12148_Y - attribute \src "libresoc.v:186390.18-186390.93" - wire $not$libresoc.v:186390$12145_Y - attribute \src "libresoc.v:186392.17-186392.92" - wire $not$libresoc.v:186392$12147_Y - attribute \src "libresoc.v:186395.17-186395.92" - wire $not$libresoc.v:186395$12150_Y - attribute \src "libresoc.v:186389.18-186389.98" - wire $or$libresoc.v:186389$12144_Y - attribute \src "libresoc.v:186391.18-186391.99" - wire $or$libresoc.v:186391$12146_Y - attribute \src "libresoc.v:186394.17-186394.97" - wire $or$libresoc.v:186394$12149_Y + attribute \src "libresoc.v:186136.17-186136.96" + wire $and$libresoc.v:186136$12137_Y + attribute \src "libresoc.v:186141.17-186141.96" + wire $and$libresoc.v:186141$12142_Y + attribute \src "libresoc.v:186138.18-186138.93" + wire $not$libresoc.v:186138$12139_Y + attribute \src "libresoc.v:186140.17-186140.92" + wire $not$libresoc.v:186140$12141_Y + attribute \src "libresoc.v:186143.17-186143.92" + wire $not$libresoc.v:186143$12144_Y + attribute \src "libresoc.v:186137.18-186137.98" + wire $or$libresoc.v:186137$12138_Y + attribute \src "libresoc.v:186139.18-186139.99" + wire $or$libresoc.v:186139$12140_Y + attribute \src "libresoc.v:186142.17-186142.97" + wire $or$libresoc.v:186142$12143_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -351087,11 +350793,11 @@ module \rst_l$13 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:186353.7-186353.15" + attribute \src "libresoc.v:186101.7-186101.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -351108,7 +350814,7 @@ module \rst_l$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186388$12143 + cell $and $and$libresoc.v:186136$12137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351116,10 +350822,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186388$12143_Y + connect \Y $and$libresoc.v:186136$12137_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186393$12148 + cell $and $and$libresoc.v:186141$12142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351127,34 +350833,34 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186393$12148_Y + connect \Y $and$libresoc.v:186141$12142_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186390$12145 + cell $not $not$libresoc.v:186138$12139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186390$12145_Y + connect \Y $not$libresoc.v:186138$12139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186392$12147 + cell $not $not$libresoc.v:186140$12141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186392$12147_Y + connect \Y $not$libresoc.v:186140$12141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186395$12150 + cell $not $not$libresoc.v:186143$12144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186395$12150_Y + connect \Y $not$libresoc.v:186143$12144_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186389$12144 + cell $or $or$libresoc.v:186137$12138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351162,10 +350868,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186389$12144_Y + connect \Y $or$libresoc.v:186137$12138_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186391$12146 + cell $or $or$libresoc.v:186139$12140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351173,10 +350879,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186391$12146_Y + connect \Y $or$libresoc.v:186139$12140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186394$12149 + cell $or $or$libresoc.v:186142$12143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351184,39 +350890,39 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186394$12149_Y + connect \Y $or$libresoc.v:186142$12143_Y end - attribute \src "libresoc.v:186353.7-186353.20" - process $proc$libresoc.v:186353$12155 + attribute \src "libresoc.v:186101.7-186101.20" + process $proc$libresoc.v:186101$12149 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186375.7-186375.19" - process $proc$libresoc.v:186375$12156 + attribute \src "libresoc.v:186123.7-186123.19" + process $proc$libresoc.v:186123$12150 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186396.3-186397.27" - process $proc$libresoc.v:186396$12151 + attribute \src "libresoc.v:186144.3-186145.27" + process $proc$libresoc.v:186144$12145 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186398.3-186406.6" - process $proc$libresoc.v:186398$12152 + attribute \src "libresoc.v:186146.3-186154.6" + process $proc$libresoc.v:186146$12146 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12153 $1\q_int$next[0:0]$12154 - attribute \src "libresoc.v:186399.5-186399.29" + assign $0\q_int$next[0:0]$12147 $1\q_int$next[0:0]$12148 + attribute \src "libresoc.v:186147.5-186147.29" switch \initial - attribute \src "libresoc.v:186399.9-186399.17" + attribute \src "libresoc.v:186147.9-186147.17" case 1'1 case end @@ -351225,56 +350931,56 @@ module \rst_l$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12154 1'0 + assign $1\q_int$next[0:0]$12148 1'0 case - assign $1\q_int$next[0:0]$12154 \$5 + assign $1\q_int$next[0:0]$12148 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12153 + update \q_int$next $0\q_int$next[0:0]$12147 end - connect \$9 $and$libresoc.v:186388$12143_Y - connect \$11 $or$libresoc.v:186389$12144_Y - connect \$13 $not$libresoc.v:186390$12145_Y - connect \$15 $or$libresoc.v:186391$12146_Y - connect \$1 $not$libresoc.v:186392$12147_Y - connect \$3 $and$libresoc.v:186393$12148_Y - connect \$5 $or$libresoc.v:186394$12149_Y - connect \$7 $not$libresoc.v:186395$12150_Y + connect \$9 $and$libresoc.v:186136$12137_Y + connect \$11 $or$libresoc.v:186137$12138_Y + connect \$13 $not$libresoc.v:186138$12139_Y + connect \$15 $or$libresoc.v:186139$12140_Y + connect \$1 $not$libresoc.v:186140$12141_Y + connect \$3 $and$libresoc.v:186141$12142_Y + connect \$5 $or$libresoc.v:186142$12143_Y + connect \$7 $not$libresoc.v:186143$12144_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186414.1-186472.10" +attribute \src "libresoc.v:186162.1-186220.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" attribute \generator "nMigen" module \rst_l$26 - attribute \src "libresoc.v:186415.7-186415.20" + attribute \src "libresoc.v:186163.7-186163.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186460.3-186468.6" - wire $0\q_int$next[0:0]$12167 - attribute \src "libresoc.v:186458.3-186459.27" + attribute \src "libresoc.v:186208.3-186216.6" + wire $0\q_int$next[0:0]$12161 + attribute \src "libresoc.v:186206.3-186207.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186460.3-186468.6" - wire $1\q_int$next[0:0]$12168 - attribute \src "libresoc.v:186437.7-186437.19" + attribute \src "libresoc.v:186208.3-186216.6" + wire $1\q_int$next[0:0]$12162 + attribute \src "libresoc.v:186185.7-186185.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186450.17-186450.96" - wire $and$libresoc.v:186450$12157_Y - attribute \src "libresoc.v:186455.17-186455.96" - wire $and$libresoc.v:186455$12162_Y - attribute \src "libresoc.v:186452.18-186452.93" - wire $not$libresoc.v:186452$12159_Y - attribute \src "libresoc.v:186454.17-186454.92" - wire $not$libresoc.v:186454$12161_Y - attribute \src "libresoc.v:186457.17-186457.92" - wire $not$libresoc.v:186457$12164_Y - attribute \src "libresoc.v:186451.18-186451.98" - wire $or$libresoc.v:186451$12158_Y - attribute \src "libresoc.v:186453.18-186453.99" - wire $or$libresoc.v:186453$12160_Y - attribute \src "libresoc.v:186456.17-186456.97" - wire $or$libresoc.v:186456$12163_Y + attribute \src "libresoc.v:186198.17-186198.96" + wire $and$libresoc.v:186198$12151_Y + attribute \src "libresoc.v:186203.17-186203.96" + wire $and$libresoc.v:186203$12156_Y + attribute \src "libresoc.v:186200.18-186200.93" + wire $not$libresoc.v:186200$12153_Y + attribute \src "libresoc.v:186202.17-186202.92" + wire $not$libresoc.v:186202$12155_Y + attribute \src "libresoc.v:186205.17-186205.92" + wire $not$libresoc.v:186205$12158_Y + attribute \src "libresoc.v:186199.18-186199.98" + wire $or$libresoc.v:186199$12152_Y + attribute \src "libresoc.v:186201.18-186201.99" + wire $or$libresoc.v:186201$12154_Y + attribute \src "libresoc.v:186204.17-186204.97" + wire $or$libresoc.v:186204$12157_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -351291,11 +350997,11 @@ module \rst_l$26 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:186415.7-186415.15" + attribute \src "libresoc.v:186163.7-186163.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -351312,7 +351018,7 @@ module \rst_l$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186450$12157 + cell $and $and$libresoc.v:186198$12151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351320,10 +351026,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186450$12157_Y + connect \Y $and$libresoc.v:186198$12151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186455$12162 + cell $and $and$libresoc.v:186203$12156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351331,34 +351037,34 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186455$12162_Y + connect \Y $and$libresoc.v:186203$12156_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186452$12159 + cell $not $not$libresoc.v:186200$12153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186452$12159_Y + connect \Y $not$libresoc.v:186200$12153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186454$12161 + cell $not $not$libresoc.v:186202$12155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186454$12161_Y + connect \Y $not$libresoc.v:186202$12155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186457$12164 + cell $not $not$libresoc.v:186205$12158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186457$12164_Y + connect \Y $not$libresoc.v:186205$12158_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186451$12158 + cell $or $or$libresoc.v:186199$12152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351366,10 +351072,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186451$12158_Y + connect \Y $or$libresoc.v:186199$12152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186453$12160 + cell $or $or$libresoc.v:186201$12154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351377,10 +351083,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186453$12160_Y + connect \Y $or$libresoc.v:186201$12154_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186456$12163 + cell $or $or$libresoc.v:186204$12157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351388,39 +351094,39 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186456$12163_Y + connect \Y $or$libresoc.v:186204$12157_Y end - attribute \src "libresoc.v:186415.7-186415.20" - process $proc$libresoc.v:186415$12169 + attribute \src "libresoc.v:186163.7-186163.20" + process $proc$libresoc.v:186163$12163 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186437.7-186437.19" - process $proc$libresoc.v:186437$12170 + attribute \src "libresoc.v:186185.7-186185.19" + process $proc$libresoc.v:186185$12164 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186458.3-186459.27" - process $proc$libresoc.v:186458$12165 + attribute \src "libresoc.v:186206.3-186207.27" + process $proc$libresoc.v:186206$12159 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186460.3-186468.6" - process $proc$libresoc.v:186460$12166 + attribute \src "libresoc.v:186208.3-186216.6" + process $proc$libresoc.v:186208$12160 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12167 $1\q_int$next[0:0]$12168 - attribute \src "libresoc.v:186461.5-186461.29" + assign $0\q_int$next[0:0]$12161 $1\q_int$next[0:0]$12162 + attribute \src "libresoc.v:186209.5-186209.29" switch \initial - attribute \src "libresoc.v:186461.9-186461.17" + attribute \src "libresoc.v:186209.9-186209.17" case 1'1 case end @@ -351429,56 +351135,56 @@ module \rst_l$26 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12168 1'0 + assign $1\q_int$next[0:0]$12162 1'0 case - assign $1\q_int$next[0:0]$12168 \$5 + assign $1\q_int$next[0:0]$12162 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12167 + update \q_int$next $0\q_int$next[0:0]$12161 end - connect \$9 $and$libresoc.v:186450$12157_Y - connect \$11 $or$libresoc.v:186451$12158_Y - connect \$13 $not$libresoc.v:186452$12159_Y - connect \$15 $or$libresoc.v:186453$12160_Y - connect \$1 $not$libresoc.v:186454$12161_Y - connect \$3 $and$libresoc.v:186455$12162_Y - connect \$5 $or$libresoc.v:186456$12163_Y - connect \$7 $not$libresoc.v:186457$12164_Y + connect \$9 $and$libresoc.v:186198$12151_Y + connect \$11 $or$libresoc.v:186199$12152_Y + connect \$13 $not$libresoc.v:186200$12153_Y + connect \$15 $or$libresoc.v:186201$12154_Y + connect \$1 $not$libresoc.v:186202$12155_Y + connect \$3 $and$libresoc.v:186203$12156_Y + connect \$5 $or$libresoc.v:186204$12157_Y + connect \$7 $not$libresoc.v:186205$12158_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186476.1-186534.10" +attribute \src "libresoc.v:186224.1-186282.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" attribute \generator "nMigen" module \rst_l$42 - attribute \src "libresoc.v:186477.7-186477.20" + attribute \src "libresoc.v:186225.7-186225.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186522.3-186530.6" - wire $0\q_int$next[0:0]$12181 - attribute \src "libresoc.v:186520.3-186521.27" + attribute \src "libresoc.v:186270.3-186278.6" + wire $0\q_int$next[0:0]$12175 + attribute \src "libresoc.v:186268.3-186269.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186522.3-186530.6" - wire $1\q_int$next[0:0]$12182 - attribute \src "libresoc.v:186499.7-186499.19" + attribute \src "libresoc.v:186270.3-186278.6" + wire $1\q_int$next[0:0]$12176 + attribute \src "libresoc.v:186247.7-186247.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186512.17-186512.96" - wire $and$libresoc.v:186512$12171_Y - attribute \src "libresoc.v:186517.17-186517.96" - wire $and$libresoc.v:186517$12176_Y - attribute \src "libresoc.v:186514.18-186514.93" - wire $not$libresoc.v:186514$12173_Y - attribute \src "libresoc.v:186516.17-186516.92" - wire $not$libresoc.v:186516$12175_Y - attribute \src "libresoc.v:186519.17-186519.92" - wire $not$libresoc.v:186519$12178_Y - attribute \src "libresoc.v:186513.18-186513.98" - wire $or$libresoc.v:186513$12172_Y - attribute \src "libresoc.v:186515.18-186515.99" - wire $or$libresoc.v:186515$12174_Y - attribute \src "libresoc.v:186518.17-186518.97" - wire $or$libresoc.v:186518$12177_Y + attribute \src "libresoc.v:186260.17-186260.96" + wire $and$libresoc.v:186260$12165_Y + attribute \src "libresoc.v:186265.17-186265.96" + wire $and$libresoc.v:186265$12170_Y + attribute \src "libresoc.v:186262.18-186262.93" + wire $not$libresoc.v:186262$12167_Y + attribute \src "libresoc.v:186264.17-186264.92" + wire $not$libresoc.v:186264$12169_Y + attribute \src "libresoc.v:186267.17-186267.92" + wire $not$libresoc.v:186267$12172_Y + attribute \src "libresoc.v:186261.18-186261.98" + wire $or$libresoc.v:186261$12166_Y + attribute \src "libresoc.v:186263.18-186263.99" + wire $or$libresoc.v:186263$12168_Y + attribute \src "libresoc.v:186266.17-186266.97" + wire $or$libresoc.v:186266$12171_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -351495,11 +351201,11 @@ module \rst_l$42 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:186477.7-186477.15" + attribute \src "libresoc.v:186225.7-186225.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -351516,7 +351222,7 @@ module \rst_l$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186512$12171 + cell $and $and$libresoc.v:186260$12165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351524,10 +351230,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186512$12171_Y + connect \Y $and$libresoc.v:186260$12165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186517$12176 + cell $and $and$libresoc.v:186265$12170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351535,34 +351241,34 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186517$12176_Y + connect \Y $and$libresoc.v:186265$12170_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186514$12173 + cell $not $not$libresoc.v:186262$12167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186514$12173_Y + connect \Y $not$libresoc.v:186262$12167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186516$12175 + cell $not $not$libresoc.v:186264$12169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186516$12175_Y + connect \Y $not$libresoc.v:186264$12169_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186519$12178 + cell $not $not$libresoc.v:186267$12172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186519$12178_Y + connect \Y $not$libresoc.v:186267$12172_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186513$12172 + cell $or $or$libresoc.v:186261$12166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351570,10 +351276,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186513$12172_Y + connect \Y $or$libresoc.v:186261$12166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186515$12174 + cell $or $or$libresoc.v:186263$12168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351581,10 +351287,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186515$12174_Y + connect \Y $or$libresoc.v:186263$12168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186518$12177 + cell $or $or$libresoc.v:186266$12171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351592,39 +351298,39 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186518$12177_Y + connect \Y $or$libresoc.v:186266$12171_Y end - attribute \src "libresoc.v:186477.7-186477.20" - process $proc$libresoc.v:186477$12183 + attribute \src "libresoc.v:186225.7-186225.20" + process $proc$libresoc.v:186225$12177 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186499.7-186499.19" - process $proc$libresoc.v:186499$12184 + attribute \src "libresoc.v:186247.7-186247.19" + process $proc$libresoc.v:186247$12178 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186520.3-186521.27" - process $proc$libresoc.v:186520$12179 + attribute \src "libresoc.v:186268.3-186269.27" + process $proc$libresoc.v:186268$12173 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186522.3-186530.6" - process $proc$libresoc.v:186522$12180 + attribute \src "libresoc.v:186270.3-186278.6" + process $proc$libresoc.v:186270$12174 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12181 $1\q_int$next[0:0]$12182 - attribute \src "libresoc.v:186523.5-186523.29" + assign $0\q_int$next[0:0]$12175 $1\q_int$next[0:0]$12176 + attribute \src "libresoc.v:186271.5-186271.29" switch \initial - attribute \src "libresoc.v:186523.9-186523.17" + attribute \src "libresoc.v:186271.9-186271.17" case 1'1 case end @@ -351633,56 +351339,56 @@ module \rst_l$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12182 1'0 + assign $1\q_int$next[0:0]$12176 1'0 case - assign $1\q_int$next[0:0]$12182 \$5 + assign $1\q_int$next[0:0]$12176 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12181 + update \q_int$next $0\q_int$next[0:0]$12175 end - connect \$9 $and$libresoc.v:186512$12171_Y - connect \$11 $or$libresoc.v:186513$12172_Y - connect \$13 $not$libresoc.v:186514$12173_Y - connect \$15 $or$libresoc.v:186515$12174_Y - connect \$1 $not$libresoc.v:186516$12175_Y - connect \$3 $and$libresoc.v:186517$12176_Y - connect \$5 $or$libresoc.v:186518$12177_Y - connect \$7 $not$libresoc.v:186519$12178_Y + connect \$9 $and$libresoc.v:186260$12165_Y + connect \$11 $or$libresoc.v:186261$12166_Y + connect \$13 $not$libresoc.v:186262$12167_Y + connect \$15 $or$libresoc.v:186263$12168_Y + connect \$1 $not$libresoc.v:186264$12169_Y + connect \$3 $and$libresoc.v:186265$12170_Y + connect \$5 $or$libresoc.v:186266$12171_Y + connect \$7 $not$libresoc.v:186267$12172_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186538.1-186596.10" +attribute \src "libresoc.v:186286.1-186344.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" attribute \generator "nMigen" module \rst_l$58 - attribute \src "libresoc.v:186539.7-186539.20" + attribute \src "libresoc.v:186287.7-186287.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186584.3-186592.6" - wire $0\q_int$next[0:0]$12195 - attribute \src "libresoc.v:186582.3-186583.27" + attribute \src "libresoc.v:186332.3-186340.6" + wire $0\q_int$next[0:0]$12189 + attribute \src "libresoc.v:186330.3-186331.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186584.3-186592.6" - wire $1\q_int$next[0:0]$12196 - attribute \src "libresoc.v:186561.7-186561.19" + attribute \src "libresoc.v:186332.3-186340.6" + wire $1\q_int$next[0:0]$12190 + attribute \src "libresoc.v:186309.7-186309.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186574.17-186574.96" - wire $and$libresoc.v:186574$12185_Y - attribute \src "libresoc.v:186579.17-186579.96" - wire $and$libresoc.v:186579$12190_Y - attribute \src "libresoc.v:186576.18-186576.93" - wire $not$libresoc.v:186576$12187_Y - attribute \src "libresoc.v:186578.17-186578.92" - wire $not$libresoc.v:186578$12189_Y - attribute \src "libresoc.v:186581.17-186581.92" - wire $not$libresoc.v:186581$12192_Y - attribute \src "libresoc.v:186575.18-186575.98" - wire $or$libresoc.v:186575$12186_Y - attribute \src "libresoc.v:186577.18-186577.99" - wire $or$libresoc.v:186577$12188_Y - attribute \src "libresoc.v:186580.17-186580.97" - wire $or$libresoc.v:186580$12191_Y + attribute \src "libresoc.v:186322.17-186322.96" + wire $and$libresoc.v:186322$12179_Y + attribute \src "libresoc.v:186327.17-186327.96" + wire $and$libresoc.v:186327$12184_Y + attribute \src "libresoc.v:186324.18-186324.93" + wire $not$libresoc.v:186324$12181_Y + attribute \src "libresoc.v:186326.17-186326.92" + wire $not$libresoc.v:186326$12183_Y + attribute \src "libresoc.v:186329.17-186329.92" + wire $not$libresoc.v:186329$12186_Y + attribute \src "libresoc.v:186323.18-186323.98" + wire $or$libresoc.v:186323$12180_Y + attribute \src "libresoc.v:186325.18-186325.99" + wire $or$libresoc.v:186325$12182_Y + attribute \src "libresoc.v:186328.17-186328.97" + wire $or$libresoc.v:186328$12185_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -351699,11 +351405,11 @@ module \rst_l$58 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:186539.7-186539.15" + attribute \src "libresoc.v:186287.7-186287.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -351720,7 +351426,7 @@ module \rst_l$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186574$12185 + cell $and $and$libresoc.v:186322$12179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351728,10 +351434,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186574$12185_Y + connect \Y $and$libresoc.v:186322$12179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186579$12190 + cell $and $and$libresoc.v:186327$12184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351739,34 +351445,34 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186579$12190_Y + connect \Y $and$libresoc.v:186327$12184_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186576$12187 + cell $not $not$libresoc.v:186324$12181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186576$12187_Y + connect \Y $not$libresoc.v:186324$12181_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186578$12189 + cell $not $not$libresoc.v:186326$12183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186578$12189_Y + connect \Y $not$libresoc.v:186326$12183_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186581$12192 + cell $not $not$libresoc.v:186329$12186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186581$12192_Y + connect \Y $not$libresoc.v:186329$12186_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186575$12186 + cell $or $or$libresoc.v:186323$12180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351774,10 +351480,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186575$12186_Y + connect \Y $or$libresoc.v:186323$12180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186577$12188 + cell $or $or$libresoc.v:186325$12182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351785,10 +351491,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186577$12188_Y + connect \Y $or$libresoc.v:186325$12182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186580$12191 + cell $or $or$libresoc.v:186328$12185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351796,39 +351502,39 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186580$12191_Y + connect \Y $or$libresoc.v:186328$12185_Y end - attribute \src "libresoc.v:186539.7-186539.20" - process $proc$libresoc.v:186539$12197 + attribute \src "libresoc.v:186287.7-186287.20" + process $proc$libresoc.v:186287$12191 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186561.7-186561.19" - process $proc$libresoc.v:186561$12198 + attribute \src "libresoc.v:186309.7-186309.19" + process $proc$libresoc.v:186309$12192 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186582.3-186583.27" - process $proc$libresoc.v:186582$12193 + attribute \src "libresoc.v:186330.3-186331.27" + process $proc$libresoc.v:186330$12187 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186584.3-186592.6" - process $proc$libresoc.v:186584$12194 + attribute \src "libresoc.v:186332.3-186340.6" + process $proc$libresoc.v:186332$12188 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12195 $1\q_int$next[0:0]$12196 - attribute \src "libresoc.v:186585.5-186585.29" + assign $0\q_int$next[0:0]$12189 $1\q_int$next[0:0]$12190 + attribute \src "libresoc.v:186333.5-186333.29" switch \initial - attribute \src "libresoc.v:186585.9-186585.17" + attribute \src "libresoc.v:186333.9-186333.17" case 1'1 case end @@ -351837,56 +351543,56 @@ module \rst_l$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12196 1'0 + assign $1\q_int$next[0:0]$12190 1'0 case - assign $1\q_int$next[0:0]$12196 \$5 + assign $1\q_int$next[0:0]$12190 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12195 + update \q_int$next $0\q_int$next[0:0]$12189 end - connect \$9 $and$libresoc.v:186574$12185_Y - connect \$11 $or$libresoc.v:186575$12186_Y - connect \$13 $not$libresoc.v:186576$12187_Y - connect \$15 $or$libresoc.v:186577$12188_Y - connect \$1 $not$libresoc.v:186578$12189_Y - connect \$3 $and$libresoc.v:186579$12190_Y - connect \$5 $or$libresoc.v:186580$12191_Y - connect \$7 $not$libresoc.v:186581$12192_Y + connect \$9 $and$libresoc.v:186322$12179_Y + connect \$11 $or$libresoc.v:186323$12180_Y + connect \$13 $not$libresoc.v:186324$12181_Y + connect \$15 $or$libresoc.v:186325$12182_Y + connect \$1 $not$libresoc.v:186326$12183_Y + connect \$3 $and$libresoc.v:186327$12184_Y + connect \$5 $or$libresoc.v:186328$12185_Y + connect \$7 $not$libresoc.v:186329$12186_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186600.1-186658.10" +attribute \src "libresoc.v:186348.1-186406.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" attribute \generator "nMigen" module \rst_l$70 - attribute \src "libresoc.v:186601.7-186601.20" + attribute \src "libresoc.v:186349.7-186349.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186646.3-186654.6" - wire $0\q_int$next[0:0]$12209 - attribute \src "libresoc.v:186644.3-186645.27" + attribute \src "libresoc.v:186394.3-186402.6" + wire $0\q_int$next[0:0]$12203 + attribute \src "libresoc.v:186392.3-186393.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186646.3-186654.6" - wire $1\q_int$next[0:0]$12210 - attribute \src "libresoc.v:186623.7-186623.19" + attribute \src "libresoc.v:186394.3-186402.6" + wire $1\q_int$next[0:0]$12204 + attribute \src "libresoc.v:186371.7-186371.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186636.17-186636.96" - wire $and$libresoc.v:186636$12199_Y - attribute \src "libresoc.v:186641.17-186641.96" - wire $and$libresoc.v:186641$12204_Y - attribute \src "libresoc.v:186638.18-186638.93" - wire $not$libresoc.v:186638$12201_Y - attribute \src "libresoc.v:186640.17-186640.92" - wire $not$libresoc.v:186640$12203_Y - attribute \src "libresoc.v:186643.17-186643.92" - wire $not$libresoc.v:186643$12206_Y - attribute \src "libresoc.v:186637.18-186637.98" - wire $or$libresoc.v:186637$12200_Y - attribute \src "libresoc.v:186639.18-186639.99" - wire $or$libresoc.v:186639$12202_Y - attribute \src "libresoc.v:186642.17-186642.97" - wire $or$libresoc.v:186642$12205_Y + attribute \src "libresoc.v:186384.17-186384.96" + wire $and$libresoc.v:186384$12193_Y + attribute \src "libresoc.v:186389.17-186389.96" + wire $and$libresoc.v:186389$12198_Y + attribute \src "libresoc.v:186386.18-186386.93" + wire $not$libresoc.v:186386$12195_Y + attribute \src "libresoc.v:186388.17-186388.92" + wire $not$libresoc.v:186388$12197_Y + attribute \src "libresoc.v:186391.17-186391.92" + wire $not$libresoc.v:186391$12200_Y + attribute \src "libresoc.v:186385.18-186385.98" + wire $or$libresoc.v:186385$12194_Y + attribute \src "libresoc.v:186387.18-186387.99" + wire $or$libresoc.v:186387$12196_Y + attribute \src "libresoc.v:186390.17-186390.97" + wire $or$libresoc.v:186390$12199_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -351903,11 +351609,11 @@ module \rst_l$70 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:186601.7-186601.15" + attribute \src "libresoc.v:186349.7-186349.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -351924,7 +351630,7 @@ module \rst_l$70 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186636$12199 + cell $and $and$libresoc.v:186384$12193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351932,10 +351638,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186636$12199_Y + connect \Y $and$libresoc.v:186384$12193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186641$12204 + cell $and $and$libresoc.v:186389$12198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351943,34 +351649,34 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186641$12204_Y + connect \Y $and$libresoc.v:186389$12198_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186638$12201 + cell $not $not$libresoc.v:186386$12195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186638$12201_Y + connect \Y $not$libresoc.v:186386$12195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186640$12203 + cell $not $not$libresoc.v:186388$12197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186640$12203_Y + connect \Y $not$libresoc.v:186388$12197_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186643$12206 + cell $not $not$libresoc.v:186391$12200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186643$12206_Y + connect \Y $not$libresoc.v:186391$12200_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186637$12200 + cell $or $or$libresoc.v:186385$12194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351978,10 +351684,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186637$12200_Y + connect \Y $or$libresoc.v:186385$12194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186639$12202 + cell $or $or$libresoc.v:186387$12196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351989,10 +351695,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186639$12202_Y + connect \Y $or$libresoc.v:186387$12196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186642$12205 + cell $or $or$libresoc.v:186390$12199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352000,39 +351706,39 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186642$12205_Y + connect \Y $or$libresoc.v:186390$12199_Y end - attribute \src "libresoc.v:186601.7-186601.20" - process $proc$libresoc.v:186601$12211 + attribute \src "libresoc.v:186349.7-186349.20" + process $proc$libresoc.v:186349$12205 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186623.7-186623.19" - process $proc$libresoc.v:186623$12212 + attribute \src "libresoc.v:186371.7-186371.19" + process $proc$libresoc.v:186371$12206 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186644.3-186645.27" - process $proc$libresoc.v:186644$12207 + attribute \src "libresoc.v:186392.3-186393.27" + process $proc$libresoc.v:186392$12201 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186646.3-186654.6" - process $proc$libresoc.v:186646$12208 + attribute \src "libresoc.v:186394.3-186402.6" + process $proc$libresoc.v:186394$12202 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12209 $1\q_int$next[0:0]$12210 - attribute \src "libresoc.v:186647.5-186647.29" + assign $0\q_int$next[0:0]$12203 $1\q_int$next[0:0]$12204 + attribute \src "libresoc.v:186395.5-186395.29" switch \initial - attribute \src "libresoc.v:186647.9-186647.17" + attribute \src "libresoc.v:186395.9-186395.17" case 1'1 case end @@ -352041,56 +351747,56 @@ module \rst_l$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12210 1'0 + assign $1\q_int$next[0:0]$12204 1'0 case - assign $1\q_int$next[0:0]$12210 \$5 + assign $1\q_int$next[0:0]$12204 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12209 + update \q_int$next $0\q_int$next[0:0]$12203 end - connect \$9 $and$libresoc.v:186636$12199_Y - connect \$11 $or$libresoc.v:186637$12200_Y - connect \$13 $not$libresoc.v:186638$12201_Y - connect \$15 $or$libresoc.v:186639$12202_Y - connect \$1 $not$libresoc.v:186640$12203_Y - connect \$3 $and$libresoc.v:186641$12204_Y - connect \$5 $or$libresoc.v:186642$12205_Y - connect \$7 $not$libresoc.v:186643$12206_Y + connect \$9 $and$libresoc.v:186384$12193_Y + connect \$11 $or$libresoc.v:186385$12194_Y + connect \$13 $not$libresoc.v:186386$12195_Y + connect \$15 $or$libresoc.v:186387$12196_Y + connect \$1 $not$libresoc.v:186388$12197_Y + connect \$3 $and$libresoc.v:186389$12198_Y + connect \$5 $or$libresoc.v:186390$12199_Y + connect \$7 $not$libresoc.v:186391$12200_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186662.1-186720.10" +attribute \src "libresoc.v:186410.1-186468.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" attribute \generator "nMigen" module \rst_l$87 - attribute \src "libresoc.v:186663.7-186663.20" + attribute \src "libresoc.v:186411.7-186411.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186708.3-186716.6" - wire $0\q_int$next[0:0]$12223 - attribute \src "libresoc.v:186706.3-186707.27" + attribute \src "libresoc.v:186456.3-186464.6" + wire $0\q_int$next[0:0]$12217 + attribute \src "libresoc.v:186454.3-186455.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186708.3-186716.6" - wire $1\q_int$next[0:0]$12224 - attribute \src "libresoc.v:186685.7-186685.19" + attribute \src "libresoc.v:186456.3-186464.6" + wire $1\q_int$next[0:0]$12218 + attribute \src "libresoc.v:186433.7-186433.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186698.17-186698.96" - wire $and$libresoc.v:186698$12213_Y - attribute \src "libresoc.v:186703.17-186703.96" - wire $and$libresoc.v:186703$12218_Y - attribute \src "libresoc.v:186700.18-186700.93" - wire $not$libresoc.v:186700$12215_Y - attribute \src "libresoc.v:186702.17-186702.92" - wire $not$libresoc.v:186702$12217_Y - attribute \src "libresoc.v:186705.17-186705.92" - wire $not$libresoc.v:186705$12220_Y - attribute \src "libresoc.v:186699.18-186699.98" - wire $or$libresoc.v:186699$12214_Y - attribute \src "libresoc.v:186701.18-186701.99" - wire $or$libresoc.v:186701$12216_Y - attribute \src "libresoc.v:186704.17-186704.97" - wire $or$libresoc.v:186704$12219_Y + attribute \src "libresoc.v:186446.17-186446.96" + wire $and$libresoc.v:186446$12207_Y + attribute \src "libresoc.v:186451.17-186451.96" + wire $and$libresoc.v:186451$12212_Y + attribute \src "libresoc.v:186448.18-186448.93" + wire $not$libresoc.v:186448$12209_Y + attribute \src "libresoc.v:186450.17-186450.92" + wire $not$libresoc.v:186450$12211_Y + attribute \src "libresoc.v:186453.17-186453.92" + wire $not$libresoc.v:186453$12214_Y + attribute \src "libresoc.v:186447.18-186447.98" + wire $or$libresoc.v:186447$12208_Y + attribute \src "libresoc.v:186449.18-186449.99" + wire $or$libresoc.v:186449$12210_Y + attribute \src "libresoc.v:186452.17-186452.97" + wire $or$libresoc.v:186452$12213_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -352107,11 +351813,11 @@ module \rst_l$87 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:186663.7-186663.15" + attribute \src "libresoc.v:186411.7-186411.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -352128,7 +351834,7 @@ module \rst_l$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186698$12213 + cell $and $and$libresoc.v:186446$12207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352136,10 +351842,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186698$12213_Y + connect \Y $and$libresoc.v:186446$12207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186703$12218 + cell $and $and$libresoc.v:186451$12212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352147,34 +351853,34 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186703$12218_Y + connect \Y $and$libresoc.v:186451$12212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186700$12215 + cell $not $not$libresoc.v:186448$12209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186700$12215_Y + connect \Y $not$libresoc.v:186448$12209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186702$12217 + cell $not $not$libresoc.v:186450$12211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186702$12217_Y + connect \Y $not$libresoc.v:186450$12211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186705$12220 + cell $not $not$libresoc.v:186453$12214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186705$12220_Y + connect \Y $not$libresoc.v:186453$12214_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186699$12214 + cell $or $or$libresoc.v:186447$12208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352182,10 +351888,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186699$12214_Y + connect \Y $or$libresoc.v:186447$12208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186701$12216 + cell $or $or$libresoc.v:186449$12210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352193,10 +351899,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186701$12216_Y + connect \Y $or$libresoc.v:186449$12210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186704$12219 + cell $or $or$libresoc.v:186452$12213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352204,39 +351910,39 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186704$12219_Y + connect \Y $or$libresoc.v:186452$12213_Y end - attribute \src "libresoc.v:186663.7-186663.20" - process $proc$libresoc.v:186663$12225 + attribute \src "libresoc.v:186411.7-186411.20" + process $proc$libresoc.v:186411$12219 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186685.7-186685.19" - process $proc$libresoc.v:186685$12226 + attribute \src "libresoc.v:186433.7-186433.19" + process $proc$libresoc.v:186433$12220 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186706.3-186707.27" - process $proc$libresoc.v:186706$12221 + attribute \src "libresoc.v:186454.3-186455.27" + process $proc$libresoc.v:186454$12215 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186708.3-186716.6" - process $proc$libresoc.v:186708$12222 + attribute \src "libresoc.v:186456.3-186464.6" + process $proc$libresoc.v:186456$12216 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12223 $1\q_int$next[0:0]$12224 - attribute \src "libresoc.v:186709.5-186709.29" + assign $0\q_int$next[0:0]$12217 $1\q_int$next[0:0]$12218 + attribute \src "libresoc.v:186457.5-186457.29" switch \initial - attribute \src "libresoc.v:186709.9-186709.17" + attribute \src "libresoc.v:186457.9-186457.17" case 1'1 case end @@ -352245,92 +351951,92 @@ module \rst_l$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12224 1'0 + assign $1\q_int$next[0:0]$12218 1'0 case - assign $1\q_int$next[0:0]$12224 \$5 + assign $1\q_int$next[0:0]$12218 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12223 + update \q_int$next $0\q_int$next[0:0]$12217 end - connect \$9 $and$libresoc.v:186698$12213_Y - connect \$11 $or$libresoc.v:186699$12214_Y - connect \$13 $not$libresoc.v:186700$12215_Y - connect \$15 $or$libresoc.v:186701$12216_Y - connect \$1 $not$libresoc.v:186702$12217_Y - connect \$3 $and$libresoc.v:186703$12218_Y - connect \$5 $or$libresoc.v:186704$12219_Y - connect \$7 $not$libresoc.v:186705$12220_Y + connect \$9 $and$libresoc.v:186446$12207_Y + connect \$11 $or$libresoc.v:186447$12208_Y + connect \$13 $not$libresoc.v:186448$12209_Y + connect \$15 $or$libresoc.v:186449$12210_Y + connect \$1 $not$libresoc.v:186450$12211_Y + connect \$3 $and$libresoc.v:186451$12212_Y + connect \$5 $or$libresoc.v:186452$12213_Y + connect \$7 $not$libresoc.v:186453$12214_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186724.1-187133.10" +attribute \src "libresoc.v:186472.1-186881.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" attribute \generator "nMigen" module \setup_stage - attribute \src "libresoc.v:187091.3-187116.6" + attribute \src "libresoc.v:186839.3-186864.6" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:186725.7-186725.20" + attribute \src "libresoc.v:186473.7-186473.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187091.3-187116.6" + attribute \src "libresoc.v:186839.3-186864.6" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:187091.3-187116.6" + attribute \src "libresoc.v:186839.3-186864.6" wire width 128 $2\dividend[127:0] - attribute \src "libresoc.v:187070.18-187070.122" - wire $and$libresoc.v:187070$12228_Y - attribute \src "libresoc.v:187072.18-187072.122" - wire $and$libresoc.v:187072$12230_Y - attribute \src "libresoc.v:187081.18-187081.105" - wire $and$libresoc.v:187081$12243_Y - attribute \src "libresoc.v:187084.18-187084.105" - wire $and$libresoc.v:187084$12246_Y - attribute \src "libresoc.v:187080.18-187080.123" - wire $eq$libresoc.v:187080$12242_Y - attribute \src "libresoc.v:187083.18-187083.123" - wire $eq$libresoc.v:187083$12245_Y - attribute \src "libresoc.v:187086.18-187086.117" - wire $eq$libresoc.v:187086$12248_Y - attribute \src "libresoc.v:187073.18-187073.97" - wire width 65 $extend$libresoc.v:187073$12231_Y - attribute \src "libresoc.v:187074.18-187074.91" - wire width 65 $extend$libresoc.v:187074$12233_Y - attribute \src "libresoc.v:187076.18-187076.97" - wire width 65 $extend$libresoc.v:187076$12236_Y - attribute \src "libresoc.v:187077.18-187077.91" - wire width 65 $extend$libresoc.v:187077$12238_Y - attribute \src "libresoc.v:187089.18-187089.99" - wire width 128 $extend$libresoc.v:187089$12251_Y - attribute \src "libresoc.v:187079.18-187079.112" - wire $ge$libresoc.v:187079$12241_Y - attribute \src "libresoc.v:187082.18-187082.124" - wire $ge$libresoc.v:187082$12244_Y - attribute \src "libresoc.v:187073.18-187073.97" - wire width 65 $neg$libresoc.v:187073$12232_Y - attribute \src "libresoc.v:187076.18-187076.97" - wire width 65 $neg$libresoc.v:187076$12237_Y - attribute \src "libresoc.v:187074.18-187074.91" - wire width 65 $pos$libresoc.v:187074$12234_Y - attribute \src "libresoc.v:187077.18-187077.91" - wire width 65 $pos$libresoc.v:187077$12239_Y - attribute \src "libresoc.v:187089.18-187089.99" - wire width 128 $pos$libresoc.v:187089$12252_Y - attribute \src "libresoc.v:187088.18-187088.117" - wire width 95 $sshl$libresoc.v:187088$12250_Y - attribute \src "libresoc.v:187090.18-187090.111" - wire width 191 $sshl$libresoc.v:187090$12253_Y - attribute \src "libresoc.v:187069.18-187069.131" - wire $ternary$libresoc.v:187069$12227_Y - attribute \src "libresoc.v:187071.18-187071.131" - wire $ternary$libresoc.v:187071$12229_Y - attribute \src "libresoc.v:187075.18-187075.119" - wire width 65 $ternary$libresoc.v:187075$12235_Y - attribute \src "libresoc.v:187078.18-187078.120" - wire width 65 $ternary$libresoc.v:187078$12240_Y - attribute \src "libresoc.v:187085.18-187085.130" - wire width 32 $ternary$libresoc.v:187085$12247_Y - attribute \src "libresoc.v:187087.18-187087.131" - wire width 32 $ternary$libresoc.v:187087$12249_Y + attribute \src "libresoc.v:186818.18-186818.122" + wire $and$libresoc.v:186818$12222_Y + attribute \src "libresoc.v:186820.18-186820.122" + wire $and$libresoc.v:186820$12224_Y + attribute \src "libresoc.v:186829.18-186829.105" + wire $and$libresoc.v:186829$12237_Y + attribute \src "libresoc.v:186832.18-186832.105" + wire $and$libresoc.v:186832$12240_Y + attribute \src "libresoc.v:186828.18-186828.123" + wire $eq$libresoc.v:186828$12236_Y + attribute \src "libresoc.v:186831.18-186831.123" + wire $eq$libresoc.v:186831$12239_Y + attribute \src "libresoc.v:186834.18-186834.117" + wire $eq$libresoc.v:186834$12242_Y + attribute \src "libresoc.v:186821.18-186821.97" + wire width 65 $extend$libresoc.v:186821$12225_Y + attribute \src "libresoc.v:186822.18-186822.91" + wire width 65 $extend$libresoc.v:186822$12227_Y + attribute \src "libresoc.v:186824.18-186824.97" + wire width 65 $extend$libresoc.v:186824$12230_Y + attribute \src "libresoc.v:186825.18-186825.91" + wire width 65 $extend$libresoc.v:186825$12232_Y + attribute \src "libresoc.v:186837.18-186837.99" + wire width 128 $extend$libresoc.v:186837$12245_Y + attribute \src "libresoc.v:186827.18-186827.112" + wire $ge$libresoc.v:186827$12235_Y + attribute \src "libresoc.v:186830.18-186830.124" + wire $ge$libresoc.v:186830$12238_Y + attribute \src "libresoc.v:186821.18-186821.97" + wire width 65 $neg$libresoc.v:186821$12226_Y + attribute \src "libresoc.v:186824.18-186824.97" + wire width 65 $neg$libresoc.v:186824$12231_Y + attribute \src "libresoc.v:186822.18-186822.91" + wire width 65 $pos$libresoc.v:186822$12228_Y + attribute \src "libresoc.v:186825.18-186825.91" + wire width 65 $pos$libresoc.v:186825$12233_Y + attribute \src "libresoc.v:186837.18-186837.99" + wire width 128 $pos$libresoc.v:186837$12246_Y + attribute \src "libresoc.v:186836.18-186836.117" + wire width 95 $sshl$libresoc.v:186836$12244_Y + attribute \src "libresoc.v:186838.18-186838.111" + wire width 191 $sshl$libresoc.v:186838$12247_Y + attribute \src "libresoc.v:186817.18-186817.131" + wire $ternary$libresoc.v:186817$12221_Y + attribute \src "libresoc.v:186819.18-186819.131" + wire $ternary$libresoc.v:186819$12223_Y + attribute \src "libresoc.v:186823.18-186823.119" + wire width 65 $ternary$libresoc.v:186823$12229_Y + attribute \src "libresoc.v:186826.18-186826.120" + wire width 65 $ternary$libresoc.v:186826$12234_Y + attribute \src "libresoc.v:186833.18-186833.130" + wire width 32 $ternary$libresoc.v:186833$12241_Y + attribute \src "libresoc.v:186835.18-186835.131" + wire width 32 $ternary$libresoc.v:186835$12243_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" @@ -352399,7 +352105,7 @@ module \setup_stage wire output 42 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand - attribute \src "libresoc.v:186725.7-186725.15" + attribute \src "libresoc.v:186473.7-186473.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -352676,7 +352382,7 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 41 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$libresoc.v:187070$12228 + cell $and $and$libresoc.v:186818$12222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352684,10 +352390,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$21 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:187070$12228_Y + connect \Y $and$libresoc.v:186818$12222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$libresoc.v:187072$12230 + cell $and $and$libresoc.v:186820$12224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352695,10 +352401,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$25 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:187072$12230_Y + connect \Y $and$libresoc.v:186820$12224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$libresoc.v:187081$12243 + cell $and $and$libresoc.v:186829$12237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352706,10 +352412,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$43 connect \B \$45 - connect \Y $and$libresoc.v:187081$12243_Y + connect \Y $and$libresoc.v:186829$12237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$libresoc.v:187084$12246 + cell $and $and$libresoc.v:186832$12240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352717,10 +352423,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 - connect \Y $and$libresoc.v:187084$12246_Y + connect \Y $and$libresoc.v:186832$12240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$libresoc.v:187080$12242 + cell $eq $eq$libresoc.v:186828$12236 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352728,10 +352434,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:187080$12242_Y + connect \Y $eq$libresoc.v:186828$12236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$libresoc.v:187083$12245 + cell $eq $eq$libresoc.v:186831$12239 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352739,10 +352445,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:187083$12245_Y + connect \Y $eq$libresoc.v:186831$12239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$libresoc.v:187086$12248 + cell $eq $eq$libresoc.v:186834$12242 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -352750,50 +352456,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \divisor_radicand connect \B 1'0 - connect \Y $eq$libresoc.v:187086$12248_Y + connect \Y $eq$libresoc.v:186834$12242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$libresoc.v:187073$12231 + cell $pos $extend$libresoc.v:186821$12225 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:187073$12231_Y + connect \Y $extend$libresoc.v:186821$12225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:187074$12233 + cell $pos $extend$libresoc.v:186822$12227 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:187074$12233_Y + connect \Y $extend$libresoc.v:186822$12227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$libresoc.v:187076$12236 + cell $pos $extend$libresoc.v:186824$12230 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:187076$12236_Y + connect \Y $extend$libresoc.v:186824$12230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:187077$12238 + cell $pos $extend$libresoc.v:186825$12232 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:187077$12238_Y + connect \Y $extend$libresoc.v:186825$12232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$libresoc.v:187089$12251 + cell $pos $extend$libresoc.v:186837$12245 parameter \A_SIGNED 0 parameter \A_WIDTH 95 parameter \Y_WIDTH 128 connect \A \$62 - connect \Y $extend$libresoc.v:187089$12251_Y + connect \Y $extend$libresoc.v:186837$12245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$libresoc.v:187079$12241 + cell $ge $ge$libresoc.v:186827$12235 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -352801,10 +352507,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend connect \B \abs_dor - connect \Y $ge$libresoc.v:187079$12241_Y + connect \Y $ge$libresoc.v:186827$12235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$libresoc.v:187082$12244 + cell $ge $ge$libresoc.v:186830$12238 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -352812,50 +352518,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend [31:0] connect \B \abs_dor [31:0] - connect \Y $ge$libresoc.v:187082$12244_Y + connect \Y $ge$libresoc.v:186830$12238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$libresoc.v:187073$12232 + cell $neg $neg$libresoc.v:186821$12226 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:187073$12231_Y - connect \Y $neg$libresoc.v:187073$12232_Y + connect \A $extend$libresoc.v:186821$12225_Y + connect \Y $neg$libresoc.v:186821$12226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$libresoc.v:187076$12237 + cell $neg $neg$libresoc.v:186824$12231 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:187076$12236_Y - connect \Y $neg$libresoc.v:187076$12237_Y + connect \A $extend$libresoc.v:186824$12230_Y + connect \Y $neg$libresoc.v:186824$12231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:187074$12234 + cell $pos $pos$libresoc.v:186822$12228 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:187074$12233_Y - connect \Y $pos$libresoc.v:187074$12234_Y + connect \A $extend$libresoc.v:186822$12227_Y + connect \Y $pos$libresoc.v:186822$12228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:187077$12239 + cell $pos $pos$libresoc.v:186825$12233 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:187077$12238_Y - connect \Y $pos$libresoc.v:187077$12239_Y + connect \A $extend$libresoc.v:186825$12232_Y + connect \Y $pos$libresoc.v:186825$12233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$libresoc.v:187089$12252 + cell $pos $pos$libresoc.v:186837$12246 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 128 - connect \A $extend$libresoc.v:187089$12251_Y - connect \Y $pos$libresoc.v:187089$12252_Y + connect \A $extend$libresoc.v:186837$12245_Y + connect \Y $pos$libresoc.v:186837$12246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$libresoc.v:187088$12250 + cell $sshl $sshl$libresoc.v:186836$12244 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -352863,10 +352569,10 @@ module \setup_stage parameter \Y_WIDTH 95 connect \A \abs_dend [31:0] connect \B 6'100000 - connect \Y $sshl$libresoc.v:187088$12250_Y + connect \Y $sshl$libresoc.v:186836$12244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$libresoc.v:187090$12253 + cell $sshl $sshl$libresoc.v:186838$12247 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -352874,72 +352580,72 @@ module \setup_stage parameter \Y_WIDTH 191 connect \A \abs_dend connect \B 7'1000000 - connect \Y $sshl$libresoc.v:187090$12253_Y + connect \Y $sshl$libresoc.v:186838$12247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$libresoc.v:187069$12227 + cell $mux $ternary$libresoc.v:186817$12221 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:187069$12227_Y + connect \Y $ternary$libresoc.v:186817$12221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$libresoc.v:187071$12229 + cell $mux $ternary$libresoc.v:186819$12223 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:187071$12229_Y + connect \Y $ternary$libresoc.v:186819$12223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$libresoc.v:187075$12235 + cell $mux $ternary$libresoc.v:186823$12229 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \divisor_neg - connect \Y $ternary$libresoc.v:187075$12235_Y + connect \Y $ternary$libresoc.v:186823$12229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$libresoc.v:187078$12240 + cell $mux $ternary$libresoc.v:186826$12234 parameter \WIDTH 65 connect \A \$39 connect \B \$37 connect \S \dividend_neg - connect \Y $ternary$libresoc.v:187078$12240_Y + connect \Y $ternary$libresoc.v:186826$12234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:187085$12247 + cell $mux $ternary$libresoc.v:186833$12241 parameter \WIDTH 32 connect \A \abs_dor [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:187085$12247_Y + connect \Y $ternary$libresoc.v:186833$12241_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:187087$12249 + cell $mux $ternary$libresoc.v:186835$12243 parameter \WIDTH 32 connect \A \abs_dend [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:187087$12249_Y + connect \Y $ternary$libresoc.v:186835$12243_Y end - attribute \src "libresoc.v:186725.7-186725.20" - process $proc$libresoc.v:186725$12255 + attribute \src "libresoc.v:186473.7-186473.20" + process $proc$libresoc.v:186473$12249 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187091.3-187116.6" - process $proc$libresoc.v:187091$12254 + attribute \src "libresoc.v:186839.3-186864.6" + process $proc$libresoc.v:186839$12248 assign { } { } assign { } { } assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "libresoc.v:187092.5-187092.29" + attribute \src "libresoc.v:186840.5-186840.29" switch \initial - attribute \src "libresoc.v:187092.9-187092.17" + attribute \src "libresoc.v:186840.9-186840.17" case 1'1 case end @@ -352971,28 +352677,28 @@ module \setup_stage sync always update \dividend $0\dividend[127:0] end - connect \$21 $ternary$libresoc.v:187069$12227_Y - connect \$23 $and$libresoc.v:187070$12228_Y - connect \$25 $ternary$libresoc.v:187071$12229_Y - connect \$27 $and$libresoc.v:187072$12230_Y - connect \$30 $neg$libresoc.v:187073$12232_Y - connect \$32 $pos$libresoc.v:187074$12234_Y - connect \$34 $ternary$libresoc.v:187075$12235_Y - connect \$37 $neg$libresoc.v:187076$12237_Y - connect \$39 $pos$libresoc.v:187077$12239_Y - connect \$41 $ternary$libresoc.v:187078$12240_Y - connect \$43 $ge$libresoc.v:187079$12241_Y - connect \$45 $eq$libresoc.v:187080$12242_Y - connect \$47 $and$libresoc.v:187081$12243_Y - connect \$49 $ge$libresoc.v:187082$12244_Y - connect \$51 $eq$libresoc.v:187083$12245_Y - connect \$53 $and$libresoc.v:187084$12246_Y - connect \$55 $ternary$libresoc.v:187085$12247_Y - connect \$57 $eq$libresoc.v:187086$12248_Y - connect \$59 $ternary$libresoc.v:187087$12249_Y - connect \$62 $sshl$libresoc.v:187088$12250_Y - connect \$61 $pos$libresoc.v:187089$12252_Y - connect \$66 $sshl$libresoc.v:187090$12253_Y + connect \$21 $ternary$libresoc.v:186817$12221_Y + connect \$23 $and$libresoc.v:186818$12222_Y + connect \$25 $ternary$libresoc.v:186819$12223_Y + connect \$27 $and$libresoc.v:186820$12224_Y + connect \$30 $neg$libresoc.v:186821$12226_Y + connect \$32 $pos$libresoc.v:186822$12228_Y + connect \$34 $ternary$libresoc.v:186823$12229_Y + connect \$37 $neg$libresoc.v:186824$12231_Y + connect \$39 $pos$libresoc.v:186825$12233_Y + connect \$41 $ternary$libresoc.v:186826$12234_Y + connect \$43 $ge$libresoc.v:186827$12235_Y + connect \$45 $eq$libresoc.v:186828$12236_Y + connect \$47 $and$libresoc.v:186829$12237_Y + connect \$49 $ge$libresoc.v:186830$12238_Y + connect \$51 $eq$libresoc.v:186831$12239_Y + connect \$53 $and$libresoc.v:186832$12240_Y + connect \$55 $ternary$libresoc.v:186833$12241_Y + connect \$57 $eq$libresoc.v:186834$12242_Y + connect \$59 $ternary$libresoc.v:186835$12243_Y + connect \$62 $sshl$libresoc.v:186836$12244_Y + connect \$61 $pos$libresoc.v:186837$12246_Y + connect \$66 $sshl$libresoc.v:186838$12247_Y connect \$29 \$34 connect \$36 \$41 connect \$65 \$66 @@ -353010,513 +352716,513 @@ module \setup_stage connect \dividend_neg \$23 connect \operation 2'01 end -attribute \src "libresoc.v:187137.1-188344.10" +attribute \src "libresoc.v:186885.1-188092.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" attribute \generator "nMigen" module \shiftrot0 - attribute \src "libresoc.v:187915.3-187916.25" + attribute \src "libresoc.v:187663.3-187664.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:187913.3-187914.46" + attribute \src "libresoc.v:187661.3-187662.46" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:188264.3-188272.6" - wire $0\alu_l_r_alu$next[0:0]$12473 - attribute \src "libresoc.v:187831.3-187832.39" + attribute \src "libresoc.v:188012.3-188020.6" + wire $0\alu_l_r_alu$next[0:0]$12467 + attribute \src "libresoc.v:187579.3-187580.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12390 - attribute \src "libresoc.v:187859.3-187860.75" + attribute \src "libresoc.v:187849.3-187886.6" + wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12384 + attribute \src "libresoc.v:187607.3-187608.75" wire width 14 $0\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12391 - attribute \src "libresoc.v:187861.3-187862.89" + attribute \src "libresoc.v:187849.3-187886.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12385 + attribute \src "libresoc.v:187609.3-187610.89" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12392 - attribute \src "libresoc.v:187863.3-187864.85" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12386 + attribute \src "libresoc.v:187611.3-187612.85" wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12393 - attribute \src "libresoc.v:187877.3-187878.83" + attribute \src "libresoc.v:187849.3-187886.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12387 + attribute \src "libresoc.v:187625.3-187626.83" wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12394 - attribute \src "libresoc.v:187881.3-187882.77" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12388 + attribute \src "libresoc.v:187629.3-187630.77" wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12395 - attribute \src "libresoc.v:187889.3-187890.69" + attribute \src "libresoc.v:187849.3-187886.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12389 + attribute \src "libresoc.v:187637.3-187638.69" wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12396 - attribute \src "libresoc.v:187857.3-187858.79" + attribute \src "libresoc.v:187849.3-187886.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12390 + attribute \src "libresoc.v:187605.3-187606.79" wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12397 - attribute \src "libresoc.v:187875.3-187876.79" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12391 + attribute \src "libresoc.v:187623.3-187624.79" wire $0\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12398 - attribute \src "libresoc.v:187885.3-187886.77" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12392 + attribute \src "libresoc.v:187633.3-187634.77" wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12399 - attribute \src "libresoc.v:187887.3-187888.79" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12393 + attribute \src "libresoc.v:187635.3-187636.79" wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12400 - attribute \src "libresoc.v:187869.3-187870.73" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12394 + attribute \src "libresoc.v:187617.3-187618.73" wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12401 - attribute \src "libresoc.v:187871.3-187872.73" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12395 + attribute \src "libresoc.v:187619.3-187620.73" wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12402 - attribute \src "libresoc.v:187879.3-187880.85" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12396 + attribute \src "libresoc.v:187627.3-187628.85" wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12403 - attribute \src "libresoc.v:187883.3-187884.79" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12397 + attribute \src "libresoc.v:187631.3-187632.79" wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12404 - attribute \src "libresoc.v:187867.3-187868.73" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12398 + attribute \src "libresoc.v:187615.3-187616.73" wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12405 - attribute \src "libresoc.v:187865.3-187866.73" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12399 + attribute \src "libresoc.v:187613.3-187614.73" wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12406 - attribute \src "libresoc.v:187873.3-187874.79" + attribute \src "libresoc.v:187849.3-187886.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12400 + attribute \src "libresoc.v:187621.3-187622.79" wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:188255.3-188263.6" - wire $0\alui_l_r_alui$next[0:0]$12470 - attribute \src "libresoc.v:187833.3-187834.43" + attribute \src "libresoc.v:188003.3-188011.6" + wire $0\alui_l_r_alui$next[0:0]$12464 + attribute \src "libresoc.v:187581.3-187582.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:188139.3-188160.6" - wire width 64 $0\data_r0__o$next[63:0]$12431 - attribute \src "libresoc.v:187853.3-187854.37" + attribute \src "libresoc.v:187887.3-187908.6" + wire width 64 $0\data_r0__o$next[63:0]$12425 + attribute \src "libresoc.v:187601.3-187602.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:188139.3-188160.6" - wire $0\data_r0__o_ok$next[0:0]$12432 - attribute \src "libresoc.v:187855.3-187856.43" + attribute \src "libresoc.v:187887.3-187908.6" + wire $0\data_r0__o_ok$next[0:0]$12426 + attribute \src "libresoc.v:187603.3-187604.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:188161.3-188182.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$12439 - attribute \src "libresoc.v:187849.3-187850.43" + attribute \src "libresoc.v:187909.3-187930.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12433 + attribute \src "libresoc.v:187597.3-187598.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:188161.3-188182.6" - wire $0\data_r1__cr_a_ok$next[0:0]$12440 - attribute \src "libresoc.v:187851.3-187852.49" + attribute \src "libresoc.v:187909.3-187930.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12434 + attribute \src "libresoc.v:187599.3-187600.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:188183.3-188204.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$12447 - attribute \src "libresoc.v:187845.3-187846.47" + attribute \src "libresoc.v:187931.3-187952.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12441 + attribute \src "libresoc.v:187593.3-187594.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:188183.3-188204.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$12448 - attribute \src "libresoc.v:187847.3-187848.53" + attribute \src "libresoc.v:187931.3-187952.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12442 + attribute \src "libresoc.v:187595.3-187596.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:188273.3-188282.6" + attribute \src "libresoc.v:188021.3-188030.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:188283.3-188292.6" + attribute \src "libresoc.v:188031.3-188040.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:188293.3-188302.6" + attribute \src "libresoc.v:188041.3-188050.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:187138.7-187138.20" + attribute \src "libresoc.v:186886.7-186886.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188056.3-188064.6" - wire $0\opc_l_r_opc$next[0:0]$12375 - attribute \src "libresoc.v:187899.3-187900.39" + attribute \src "libresoc.v:187804.3-187812.6" + wire $0\opc_l_r_opc$next[0:0]$12369 + attribute \src "libresoc.v:187647.3-187648.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:188047.3-188055.6" - wire $0\opc_l_s_opc$next[0:0]$12372 - attribute \src "libresoc.v:187901.3-187902.39" + attribute \src "libresoc.v:187795.3-187803.6" + wire $0\opc_l_s_opc$next[0:0]$12366 + attribute \src "libresoc.v:187649.3-187650.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:188303.3-188311.6" - wire width 3 $0\prev_wr_go$next[2:0]$12479 - attribute \src "libresoc.v:187911.3-187912.37" + attribute \src "libresoc.v:188051.3-188059.6" + wire width 3 $0\prev_wr_go$next[2:0]$12473 + attribute \src "libresoc.v:187659.3-187660.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:188001.3-188010.6" + attribute \src "libresoc.v:187749.3-187758.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:188092.3-188100.6" - wire width 3 $0\req_l_r_req$next[2:0]$12387 - attribute \src "libresoc.v:187891.3-187892.39" + attribute \src "libresoc.v:187840.3-187848.6" + wire width 3 $0\req_l_r_req$next[2:0]$12381 + attribute \src "libresoc.v:187639.3-187640.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:188083.3-188091.6" - wire width 3 $0\req_l_s_req$next[2:0]$12384 - attribute \src "libresoc.v:187893.3-187894.39" + attribute \src "libresoc.v:187831.3-187839.6" + wire width 3 $0\req_l_s_req$next[2:0]$12378 + attribute \src "libresoc.v:187641.3-187642.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:188020.3-188028.6" - wire $0\rok_l_r_rdok$next[0:0]$12363 - attribute \src "libresoc.v:187907.3-187908.41" + attribute \src "libresoc.v:187768.3-187776.6" + wire $0\rok_l_r_rdok$next[0:0]$12357 + attribute \src "libresoc.v:187655.3-187656.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:188011.3-188019.6" - wire $0\rok_l_s_rdok$next[0:0]$12360 - attribute \src "libresoc.v:187909.3-187910.41" + attribute \src "libresoc.v:187759.3-187767.6" + wire $0\rok_l_s_rdok$next[0:0]$12354 + attribute \src "libresoc.v:187657.3-187658.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:188038.3-188046.6" - wire $0\rst_l_r_rst$next[0:0]$12369 - attribute \src "libresoc.v:187903.3-187904.39" + attribute \src "libresoc.v:187786.3-187794.6" + wire $0\rst_l_r_rst$next[0:0]$12363 + attribute \src "libresoc.v:187651.3-187652.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:188029.3-188037.6" - wire $0\rst_l_s_rst$next[0:0]$12366 - attribute \src "libresoc.v:187905.3-187906.39" + attribute \src "libresoc.v:187777.3-187785.6" + wire $0\rst_l_s_rst$next[0:0]$12360 + attribute \src "libresoc.v:187653.3-187654.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:188074.3-188082.6" - wire width 5 $0\src_l_r_src$next[4:0]$12381 - attribute \src "libresoc.v:187895.3-187896.39" + attribute \src "libresoc.v:187822.3-187830.6" + wire width 5 $0\src_l_r_src$next[4:0]$12375 + attribute \src "libresoc.v:187643.3-187644.39" wire width 5 $0\src_l_r_src[4:0] - attribute \src "libresoc.v:188065.3-188073.6" - wire width 5 $0\src_l_s_src$next[4:0]$12378 - attribute \src "libresoc.v:187897.3-187898.39" + attribute \src "libresoc.v:187813.3-187821.6" + wire width 5 $0\src_l_s_src$next[4:0]$12372 + attribute \src "libresoc.v:187645.3-187646.39" wire width 5 $0\src_l_s_src[4:0] - attribute \src "libresoc.v:188205.3-188214.6" - wire width 64 $0\src_r0$next[63:0]$12455 - attribute \src "libresoc.v:187843.3-187844.29" + attribute \src "libresoc.v:187953.3-187962.6" + wire width 64 $0\src_r0$next[63:0]$12449 + attribute \src "libresoc.v:187591.3-187592.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:188215.3-188224.6" - wire width 64 $0\src_r1$next[63:0]$12458 - attribute \src "libresoc.v:187841.3-187842.29" + attribute \src "libresoc.v:187963.3-187972.6" + wire width 64 $0\src_r1$next[63:0]$12452 + attribute \src "libresoc.v:187589.3-187590.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:188225.3-188234.6" - wire width 64 $0\src_r2$next[63:0]$12461 - attribute \src "libresoc.v:187839.3-187840.29" + attribute \src "libresoc.v:187973.3-187982.6" + wire width 64 $0\src_r2$next[63:0]$12455 + attribute \src "libresoc.v:187587.3-187588.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:188235.3-188244.6" - wire $0\src_r3$next[0:0]$12464 - attribute \src "libresoc.v:187837.3-187838.29" + attribute \src "libresoc.v:187983.3-187992.6" + wire $0\src_r3$next[0:0]$12458 + attribute \src "libresoc.v:187585.3-187586.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:188245.3-188254.6" - wire width 2 $0\src_r4$next[1:0]$12467 - attribute \src "libresoc.v:187835.3-187836.29" + attribute \src "libresoc.v:187993.3-188002.6" + wire width 2 $0\src_r4$next[1:0]$12461 + attribute \src "libresoc.v:187583.3-187584.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:187260.7-187260.24" + attribute \src "libresoc.v:187008.7-187008.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:187270.7-187270.26" + attribute \src "libresoc.v:187018.7-187018.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:188264.3-188272.6" - wire $1\alu_l_r_alu$next[0:0]$12474 - attribute \src "libresoc.v:187278.7-187278.25" + attribute \src "libresoc.v:188012.3-188020.6" + wire $1\alu_l_r_alu$next[0:0]$12468 + attribute \src "libresoc.v:187026.7-187026.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407 - attribute \src "libresoc.v:187321.14-187321.54" + attribute \src "libresoc.v:187849.3-187886.6" + wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12401 + attribute \src "libresoc.v:187069.14-187069.54" wire width 14 $1\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408 - attribute \src "libresoc.v:187325.14-187325.73" + attribute \src "libresoc.v:187849.3-187886.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12402 + attribute \src "libresoc.v:187073.14-187073.73" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409 - attribute \src "libresoc.v:187329.7-187329.48" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12403 + attribute \src "libresoc.v:187077.7-187077.48" wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410 - attribute \src "libresoc.v:187337.13-187337.53" + attribute \src "libresoc.v:187849.3-187886.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12404 + attribute \src "libresoc.v:187085.13-187085.53" wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411 - attribute \src "libresoc.v:187341.7-187341.44" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12405 + attribute \src "libresoc.v:187089.7-187089.44" wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412 - attribute \src "libresoc.v:187345.14-187345.48" + attribute \src "libresoc.v:187849.3-187886.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12406 + attribute \src "libresoc.v:187093.14-187093.48" wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413 - attribute \src "libresoc.v:187424.13-187424.52" + attribute \src "libresoc.v:187849.3-187886.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12407 + attribute \src "libresoc.v:187172.13-187172.52" wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414 - attribute \src "libresoc.v:187428.7-187428.45" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12408 + attribute \src "libresoc.v:187176.7-187176.45" wire $1\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415 - attribute \src "libresoc.v:187432.7-187432.44" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12409 + attribute \src "libresoc.v:187180.7-187180.44" wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416 - attribute \src "libresoc.v:187436.7-187436.45" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12410 + attribute \src "libresoc.v:187184.7-187184.45" wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417 - attribute \src "libresoc.v:187440.7-187440.42" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12411 + attribute \src "libresoc.v:187188.7-187188.42" wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418 - attribute \src "libresoc.v:187444.7-187444.42" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12412 + attribute \src "libresoc.v:187192.7-187192.42" wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419 - attribute \src "libresoc.v:187448.7-187448.48" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12413 + attribute \src "libresoc.v:187196.7-187196.48" wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420 - attribute \src "libresoc.v:187452.7-187452.45" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12414 + attribute \src "libresoc.v:187200.7-187200.45" wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421 - attribute \src "libresoc.v:187456.7-187456.42" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12415 + attribute \src "libresoc.v:187204.7-187204.42" wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422 - attribute \src "libresoc.v:187460.7-187460.42" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12416 + attribute \src "libresoc.v:187208.7-187208.42" wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423 - attribute \src "libresoc.v:187464.7-187464.45" + attribute \src "libresoc.v:187849.3-187886.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12417 + attribute \src "libresoc.v:187212.7-187212.45" wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:188255.3-188263.6" - wire $1\alui_l_r_alui$next[0:0]$12471 - attribute \src "libresoc.v:187476.7-187476.27" + attribute \src "libresoc.v:188003.3-188011.6" + wire $1\alui_l_r_alui$next[0:0]$12465 + attribute \src "libresoc.v:187224.7-187224.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:188139.3-188160.6" - wire width 64 $1\data_r0__o$next[63:0]$12433 - attribute \src "libresoc.v:187510.14-187510.47" + attribute \src "libresoc.v:187887.3-187908.6" + wire width 64 $1\data_r0__o$next[63:0]$12427 + attribute \src "libresoc.v:187258.14-187258.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:188139.3-188160.6" - wire $1\data_r0__o_ok$next[0:0]$12434 - attribute \src "libresoc.v:187514.7-187514.27" + attribute \src "libresoc.v:187887.3-187908.6" + wire $1\data_r0__o_ok$next[0:0]$12428 + attribute \src "libresoc.v:187262.7-187262.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:188161.3-188182.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$12441 - attribute \src "libresoc.v:187518.13-187518.33" + attribute \src "libresoc.v:187909.3-187930.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12435 + attribute \src "libresoc.v:187266.13-187266.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:188161.3-188182.6" - wire $1\data_r1__cr_a_ok$next[0:0]$12442 - attribute \src "libresoc.v:187522.7-187522.30" + attribute \src "libresoc.v:187909.3-187930.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12436 + attribute \src "libresoc.v:187270.7-187270.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:188183.3-188204.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$12449 - attribute \src "libresoc.v:187526.13-187526.35" + attribute \src "libresoc.v:187931.3-187952.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12443 + attribute \src "libresoc.v:187274.13-187274.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:188183.3-188204.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$12450 - attribute \src "libresoc.v:187530.7-187530.32" + attribute \src "libresoc.v:187931.3-187952.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12444 + attribute \src "libresoc.v:187278.7-187278.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:188273.3-188282.6" + attribute \src "libresoc.v:188021.3-188030.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:188283.3-188292.6" + attribute \src "libresoc.v:188031.3-188040.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:188293.3-188302.6" + attribute \src "libresoc.v:188041.3-188050.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:188056.3-188064.6" - wire $1\opc_l_r_opc$next[0:0]$12376 - attribute \src "libresoc.v:187547.7-187547.25" + attribute \src "libresoc.v:187804.3-187812.6" + wire $1\opc_l_r_opc$next[0:0]$12370 + attribute \src "libresoc.v:187295.7-187295.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:188047.3-188055.6" - wire $1\opc_l_s_opc$next[0:0]$12373 - attribute \src "libresoc.v:187551.7-187551.25" + attribute \src "libresoc.v:187795.3-187803.6" + wire $1\opc_l_s_opc$next[0:0]$12367 + attribute \src "libresoc.v:187299.7-187299.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:188303.3-188311.6" - wire width 3 $1\prev_wr_go$next[2:0]$12480 - attribute \src "libresoc.v:187683.13-187683.30" + attribute \src "libresoc.v:188051.3-188059.6" + wire width 3 $1\prev_wr_go$next[2:0]$12474 + attribute \src "libresoc.v:187431.13-187431.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:188001.3-188010.6" + attribute \src "libresoc.v:187749.3-187758.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:188092.3-188100.6" - wire width 3 $1\req_l_r_req$next[2:0]$12388 - attribute \src "libresoc.v:187691.13-187691.31" + attribute \src "libresoc.v:187840.3-187848.6" + wire width 3 $1\req_l_r_req$next[2:0]$12382 + attribute \src "libresoc.v:187439.13-187439.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:188083.3-188091.6" - wire width 3 $1\req_l_s_req$next[2:0]$12385 - attribute \src "libresoc.v:187695.13-187695.31" + attribute \src "libresoc.v:187831.3-187839.6" + wire width 3 $1\req_l_s_req$next[2:0]$12379 + attribute \src "libresoc.v:187443.13-187443.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:188020.3-188028.6" - wire $1\rok_l_r_rdok$next[0:0]$12364 - attribute \src "libresoc.v:187707.7-187707.26" + attribute \src "libresoc.v:187768.3-187776.6" + wire $1\rok_l_r_rdok$next[0:0]$12358 + attribute \src "libresoc.v:187455.7-187455.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:188011.3-188019.6" - wire $1\rok_l_s_rdok$next[0:0]$12361 - attribute \src "libresoc.v:187711.7-187711.26" + attribute \src "libresoc.v:187759.3-187767.6" + wire $1\rok_l_s_rdok$next[0:0]$12355 + attribute \src "libresoc.v:187459.7-187459.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:188038.3-188046.6" - wire $1\rst_l_r_rst$next[0:0]$12370 - attribute \src "libresoc.v:187715.7-187715.25" + attribute \src "libresoc.v:187786.3-187794.6" + wire $1\rst_l_r_rst$next[0:0]$12364 + attribute \src "libresoc.v:187463.7-187463.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:188029.3-188037.6" - wire $1\rst_l_s_rst$next[0:0]$12367 - attribute \src "libresoc.v:187719.7-187719.25" + attribute \src "libresoc.v:187777.3-187785.6" + wire $1\rst_l_s_rst$next[0:0]$12361 + attribute \src "libresoc.v:187467.7-187467.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:188074.3-188082.6" - wire width 5 $1\src_l_r_src$next[4:0]$12382 - attribute \src "libresoc.v:187737.13-187737.32" + attribute \src "libresoc.v:187822.3-187830.6" + wire width 5 $1\src_l_r_src$next[4:0]$12376 + attribute \src "libresoc.v:187485.13-187485.32" wire width 5 $1\src_l_r_src[4:0] - attribute \src "libresoc.v:188065.3-188073.6" - wire width 5 $1\src_l_s_src$next[4:0]$12379 - attribute \src "libresoc.v:187741.13-187741.32" + attribute \src "libresoc.v:187813.3-187821.6" + wire width 5 $1\src_l_s_src$next[4:0]$12373 + attribute \src "libresoc.v:187489.13-187489.32" wire width 5 $1\src_l_s_src[4:0] - attribute \src "libresoc.v:188205.3-188214.6" - wire width 64 $1\src_r0$next[63:0]$12456 - attribute \src "libresoc.v:187747.14-187747.43" + attribute \src "libresoc.v:187953.3-187962.6" + wire width 64 $1\src_r0$next[63:0]$12450 + attribute \src "libresoc.v:187495.14-187495.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:188215.3-188224.6" - wire width 64 $1\src_r1$next[63:0]$12459 - attribute \src "libresoc.v:187751.14-187751.43" + attribute \src "libresoc.v:187963.3-187972.6" + wire width 64 $1\src_r1$next[63:0]$12453 + attribute \src "libresoc.v:187499.14-187499.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:188225.3-188234.6" - wire width 64 $1\src_r2$next[63:0]$12462 - attribute \src "libresoc.v:187755.14-187755.43" + attribute \src "libresoc.v:187973.3-187982.6" + wire width 64 $1\src_r2$next[63:0]$12456 + attribute \src "libresoc.v:187503.14-187503.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:188235.3-188244.6" - wire $1\src_r3$next[0:0]$12465 - attribute \src "libresoc.v:187759.7-187759.20" + attribute \src "libresoc.v:187983.3-187992.6" + wire $1\src_r3$next[0:0]$12459 + attribute \src "libresoc.v:187507.7-187507.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:188245.3-188254.6" - wire width 2 $1\src_r4$next[1:0]$12468 - attribute \src "libresoc.v:187763.13-187763.26" + attribute \src "libresoc.v:187993.3-188002.6" + wire width 2 $1\src_r4$next[1:0]$12462 + attribute \src "libresoc.v:187511.13-187511.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:188101.3-188138.6" - wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424 - attribute \src "libresoc.v:188101.3-188138.6" - wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425 - attribute \src "libresoc.v:188101.3-188138.6" - wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426 - attribute \src "libresoc.v:188101.3-188138.6" - wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427 - attribute \src "libresoc.v:188101.3-188138.6" - wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428 - attribute \src "libresoc.v:188101.3-188138.6" - wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429 - attribute \src "libresoc.v:188139.3-188160.6" - wire width 64 $2\data_r0__o$next[63:0]$12435 - attribute \src "libresoc.v:188139.3-188160.6" - wire $2\data_r0__o_ok$next[0:0]$12436 - attribute \src "libresoc.v:188161.3-188182.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$12443 - attribute \src "libresoc.v:188161.3-188182.6" - wire $2\data_r1__cr_a_ok$next[0:0]$12444 - attribute \src "libresoc.v:188183.3-188204.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$12451 - attribute \src "libresoc.v:188183.3-188204.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$12452 - attribute \src "libresoc.v:188139.3-188160.6" - wire $3\data_r0__o_ok$next[0:0]$12437 - attribute \src "libresoc.v:188161.3-188182.6" - wire $3\data_r1__cr_a_ok$next[0:0]$12445 - attribute \src "libresoc.v:188183.3-188204.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$12453 - attribute \src "libresoc.v:187773.19-187773.114" - wire width 5 $and$libresoc.v:187773$12257_Y - attribute \src "libresoc.v:187774.19-187774.125" - wire $and$libresoc.v:187774$12258_Y - attribute \src "libresoc.v:187775.19-187775.125" - wire $and$libresoc.v:187775$12259_Y - attribute \src "libresoc.v:187776.19-187776.125" - wire $and$libresoc.v:187776$12260_Y - attribute \src "libresoc.v:187777.18-187777.110" - wire $and$libresoc.v:187777$12261_Y - attribute \src "libresoc.v:187778.19-187778.141" - wire width 3 $and$libresoc.v:187778$12262_Y - attribute \src "libresoc.v:187779.19-187779.121" - wire width 3 $and$libresoc.v:187779$12263_Y - attribute \src "libresoc.v:187780.19-187780.127" - wire $and$libresoc.v:187780$12264_Y - attribute \src "libresoc.v:187781.19-187781.127" - wire $and$libresoc.v:187781$12265_Y - attribute \src "libresoc.v:187782.19-187782.127" - wire $and$libresoc.v:187782$12266_Y - attribute \src "libresoc.v:187784.18-187784.98" - wire $and$libresoc.v:187784$12268_Y - attribute \src "libresoc.v:187786.18-187786.100" - wire $and$libresoc.v:187786$12270_Y - attribute \src "libresoc.v:187787.18-187787.149" - wire width 3 $and$libresoc.v:187787$12271_Y - attribute \src "libresoc.v:187789.18-187789.119" - wire width 3 $and$libresoc.v:187789$12273_Y - attribute \src "libresoc.v:187792.17-187792.123" - wire $and$libresoc.v:187792$12276_Y - attribute \src "libresoc.v:187793.18-187793.116" - wire $and$libresoc.v:187793$12277_Y - attribute \src "libresoc.v:187798.18-187798.113" - wire $and$libresoc.v:187798$12282_Y - attribute \src "libresoc.v:187799.18-187799.125" - wire width 3 $and$libresoc.v:187799$12283_Y - attribute \src "libresoc.v:187801.18-187801.112" - wire $and$libresoc.v:187801$12285_Y - attribute \src "libresoc.v:187803.18-187803.132" - wire $and$libresoc.v:187803$12287_Y - attribute \src "libresoc.v:187804.18-187804.132" - wire $and$libresoc.v:187804$12288_Y - attribute \src "libresoc.v:187805.18-187805.117" - wire $and$libresoc.v:187805$12289_Y - attribute \src "libresoc.v:187811.18-187811.136" - wire $and$libresoc.v:187811$12295_Y - attribute \src "libresoc.v:187812.18-187812.124" - wire width 3 $and$libresoc.v:187812$12296_Y - attribute \src "libresoc.v:187814.18-187814.116" - wire $and$libresoc.v:187814$12298_Y - attribute \src "libresoc.v:187815.18-187815.119" - wire $and$libresoc.v:187815$12299_Y - attribute \src "libresoc.v:187816.18-187816.121" - wire $and$libresoc.v:187816$12300_Y - attribute \src "libresoc.v:187826.18-187826.140" - wire $and$libresoc.v:187826$12310_Y - attribute \src "libresoc.v:187827.18-187827.138" - wire $and$libresoc.v:187827$12311_Y - attribute \src "libresoc.v:187828.18-187828.171" - wire width 5 $and$libresoc.v:187828$12312_Y - attribute \src "libresoc.v:187830.18-187830.129" - wire width 5 $and$libresoc.v:187830$12314_Y - attribute \src "libresoc.v:187800.18-187800.113" - wire $eq$libresoc.v:187800$12284_Y - attribute \src "libresoc.v:187802.18-187802.119" - wire $eq$libresoc.v:187802$12286_Y - attribute \src "libresoc.v:187772.19-187772.115" - wire width 5 $not$libresoc.v:187772$12256_Y - attribute \src "libresoc.v:187783.18-187783.97" - wire $not$libresoc.v:187783$12267_Y - attribute \src "libresoc.v:187785.18-187785.99" - wire $not$libresoc.v:187785$12269_Y - attribute \src "libresoc.v:187788.18-187788.113" - wire width 3 $not$libresoc.v:187788$12272_Y - attribute \src "libresoc.v:187791.18-187791.106" - wire $not$libresoc.v:187791$12275_Y - attribute \src "libresoc.v:187797.18-187797.126" - wire $not$libresoc.v:187797$12281_Y - attribute \src "libresoc.v:187808.17-187808.113" - wire width 5 $not$libresoc.v:187808$12292_Y - attribute \src "libresoc.v:187829.18-187829.136" - wire $not$libresoc.v:187829$12313_Y - attribute \src "libresoc.v:187796.18-187796.112" - wire $or$libresoc.v:187796$12280_Y - attribute \src "libresoc.v:187806.18-187806.122" - wire $or$libresoc.v:187806$12290_Y - attribute \src "libresoc.v:187807.18-187807.124" - wire $or$libresoc.v:187807$12291_Y - attribute \src "libresoc.v:187809.18-187809.155" - wire width 3 $or$libresoc.v:187809$12293_Y - attribute \src "libresoc.v:187810.18-187810.181" - wire width 5 $or$libresoc.v:187810$12294_Y - attribute \src "libresoc.v:187813.18-187813.120" - wire width 3 $or$libresoc.v:187813$12297_Y - attribute \src "libresoc.v:187819.17-187819.117" - wire width 5 $or$libresoc.v:187819$12303_Y - attribute \src "libresoc.v:187825.17-187825.104" - wire $reduce_and$libresoc.v:187825$12309_Y - attribute \src "libresoc.v:187790.18-187790.106" - wire $reduce_or$libresoc.v:187790$12274_Y - attribute \src "libresoc.v:187794.18-187794.113" - wire $reduce_or$libresoc.v:187794$12278_Y - attribute \src "libresoc.v:187795.18-187795.112" - wire $reduce_or$libresoc.v:187795$12279_Y - attribute \src "libresoc.v:187817.18-187817.165" - wire $ternary$libresoc.v:187817$12301_Y - attribute \src "libresoc.v:187818.18-187818.182" - wire width 64 $ternary$libresoc.v:187818$12302_Y - attribute \src "libresoc.v:187820.18-187820.118" - wire width 64 $ternary$libresoc.v:187820$12304_Y - attribute \src "libresoc.v:187821.18-187821.115" - wire width 64 $ternary$libresoc.v:187821$12305_Y - attribute \src "libresoc.v:187822.18-187822.118" - wire width 64 $ternary$libresoc.v:187822$12306_Y - attribute \src "libresoc.v:187823.18-187823.118" - wire $ternary$libresoc.v:187823$12307_Y - attribute \src "libresoc.v:187824.18-187824.118" - wire width 2 $ternary$libresoc.v:187824$12308_Y + attribute \src "libresoc.v:187849.3-187886.6" + wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12418 + attribute \src "libresoc.v:187849.3-187886.6" + wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12419 + attribute \src "libresoc.v:187849.3-187886.6" + wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 + attribute \src "libresoc.v:187849.3-187886.6" + wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 + attribute \src "libresoc.v:187849.3-187886.6" + wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12422 + attribute \src "libresoc.v:187849.3-187886.6" + wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12423 + attribute \src "libresoc.v:187887.3-187908.6" + wire width 64 $2\data_r0__o$next[63:0]$12429 + attribute \src "libresoc.v:187887.3-187908.6" + wire $2\data_r0__o_ok$next[0:0]$12430 + attribute \src "libresoc.v:187909.3-187930.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$12437 + attribute \src "libresoc.v:187909.3-187930.6" + wire $2\data_r1__cr_a_ok$next[0:0]$12438 + attribute \src "libresoc.v:187931.3-187952.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$12445 + attribute \src "libresoc.v:187931.3-187952.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$12446 + attribute \src "libresoc.v:187887.3-187908.6" + wire $3\data_r0__o_ok$next[0:0]$12431 + attribute \src "libresoc.v:187909.3-187930.6" + wire $3\data_r1__cr_a_ok$next[0:0]$12439 + attribute \src "libresoc.v:187931.3-187952.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$12447 + attribute \src "libresoc.v:187521.19-187521.114" + wire width 5 $and$libresoc.v:187521$12251_Y + attribute \src "libresoc.v:187522.19-187522.125" + wire $and$libresoc.v:187522$12252_Y + attribute \src "libresoc.v:187523.19-187523.125" + wire $and$libresoc.v:187523$12253_Y + attribute \src "libresoc.v:187524.19-187524.125" + wire $and$libresoc.v:187524$12254_Y + attribute \src "libresoc.v:187525.18-187525.110" + wire $and$libresoc.v:187525$12255_Y + attribute \src "libresoc.v:187526.19-187526.141" + wire width 3 $and$libresoc.v:187526$12256_Y + attribute \src "libresoc.v:187527.19-187527.121" + wire width 3 $and$libresoc.v:187527$12257_Y + attribute \src "libresoc.v:187528.19-187528.127" + wire $and$libresoc.v:187528$12258_Y + attribute \src "libresoc.v:187529.19-187529.127" + wire $and$libresoc.v:187529$12259_Y + attribute \src "libresoc.v:187530.19-187530.127" + wire $and$libresoc.v:187530$12260_Y + attribute \src "libresoc.v:187532.18-187532.98" + wire $and$libresoc.v:187532$12262_Y + attribute \src "libresoc.v:187534.18-187534.100" + wire $and$libresoc.v:187534$12264_Y + attribute \src "libresoc.v:187535.18-187535.149" + wire width 3 $and$libresoc.v:187535$12265_Y + attribute \src "libresoc.v:187537.18-187537.119" + wire width 3 $and$libresoc.v:187537$12267_Y + attribute \src "libresoc.v:187540.17-187540.123" + wire $and$libresoc.v:187540$12270_Y + attribute \src "libresoc.v:187541.18-187541.116" + wire $and$libresoc.v:187541$12271_Y + attribute \src "libresoc.v:187546.18-187546.113" + wire $and$libresoc.v:187546$12276_Y + attribute \src "libresoc.v:187547.18-187547.125" + wire width 3 $and$libresoc.v:187547$12277_Y + attribute \src "libresoc.v:187549.18-187549.112" + wire $and$libresoc.v:187549$12279_Y + attribute \src "libresoc.v:187551.18-187551.132" + wire $and$libresoc.v:187551$12281_Y + attribute \src "libresoc.v:187552.18-187552.132" + wire $and$libresoc.v:187552$12282_Y + attribute \src "libresoc.v:187553.18-187553.117" + wire $and$libresoc.v:187553$12283_Y + attribute \src "libresoc.v:187559.18-187559.136" + wire $and$libresoc.v:187559$12289_Y + attribute \src "libresoc.v:187560.18-187560.124" + wire width 3 $and$libresoc.v:187560$12290_Y + attribute \src "libresoc.v:187562.18-187562.116" + wire $and$libresoc.v:187562$12292_Y + attribute \src "libresoc.v:187563.18-187563.119" + wire $and$libresoc.v:187563$12293_Y + attribute \src "libresoc.v:187564.18-187564.121" + wire $and$libresoc.v:187564$12294_Y + attribute \src "libresoc.v:187574.18-187574.140" + wire $and$libresoc.v:187574$12304_Y + attribute \src "libresoc.v:187575.18-187575.138" + wire $and$libresoc.v:187575$12305_Y + attribute \src "libresoc.v:187576.18-187576.171" + wire width 5 $and$libresoc.v:187576$12306_Y + attribute \src "libresoc.v:187578.18-187578.129" + wire width 5 $and$libresoc.v:187578$12308_Y + attribute \src "libresoc.v:187548.18-187548.113" + wire $eq$libresoc.v:187548$12278_Y + attribute \src "libresoc.v:187550.18-187550.119" + wire $eq$libresoc.v:187550$12280_Y + attribute \src "libresoc.v:187520.19-187520.115" + wire width 5 $not$libresoc.v:187520$12250_Y + attribute \src "libresoc.v:187531.18-187531.97" + wire $not$libresoc.v:187531$12261_Y + attribute \src "libresoc.v:187533.18-187533.99" + wire $not$libresoc.v:187533$12263_Y + attribute \src "libresoc.v:187536.18-187536.113" + wire width 3 $not$libresoc.v:187536$12266_Y + attribute \src "libresoc.v:187539.18-187539.106" + wire $not$libresoc.v:187539$12269_Y + attribute \src "libresoc.v:187545.18-187545.126" + wire $not$libresoc.v:187545$12275_Y + attribute \src "libresoc.v:187556.17-187556.113" + wire width 5 $not$libresoc.v:187556$12286_Y + attribute \src "libresoc.v:187577.18-187577.136" + wire $not$libresoc.v:187577$12307_Y + attribute \src "libresoc.v:187544.18-187544.112" + wire $or$libresoc.v:187544$12274_Y + attribute \src "libresoc.v:187554.18-187554.122" + wire $or$libresoc.v:187554$12284_Y + attribute \src "libresoc.v:187555.18-187555.124" + wire $or$libresoc.v:187555$12285_Y + attribute \src "libresoc.v:187557.18-187557.155" + wire width 3 $or$libresoc.v:187557$12287_Y + attribute \src "libresoc.v:187558.18-187558.181" + wire width 5 $or$libresoc.v:187558$12288_Y + attribute \src "libresoc.v:187561.18-187561.120" + wire width 3 $or$libresoc.v:187561$12291_Y + attribute \src "libresoc.v:187567.17-187567.117" + wire width 5 $or$libresoc.v:187567$12297_Y + attribute \src "libresoc.v:187573.17-187573.104" + wire $reduce_and$libresoc.v:187573$12303_Y + attribute \src "libresoc.v:187538.18-187538.106" + wire $reduce_or$libresoc.v:187538$12268_Y + attribute \src "libresoc.v:187542.18-187542.113" + wire $reduce_or$libresoc.v:187542$12272_Y + attribute \src "libresoc.v:187543.18-187543.112" + wire $reduce_or$libresoc.v:187543$12273_Y + attribute \src "libresoc.v:187565.18-187565.165" + wire $ternary$libresoc.v:187565$12295_Y + attribute \src "libresoc.v:187566.18-187566.182" + wire width 64 $ternary$libresoc.v:187566$12296_Y + attribute \src "libresoc.v:187568.18-187568.118" + wire width 64 $ternary$libresoc.v:187568$12298_Y + attribute \src "libresoc.v:187569.18-187569.115" + wire width 64 $ternary$libresoc.v:187569$12299_Y + attribute \src "libresoc.v:187570.18-187570.118" + wire width 64 $ternary$libresoc.v:187570$12300_Y + attribute \src "libresoc.v:187571.18-187571.118" + wire $ternary$libresoc.v:187571$12301_Y + attribute \src "libresoc.v:187572.18-187572.118" + wire width 2 $ternary$libresoc.v:187572$12302_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -353859,9 +353565,9 @@ module \shiftrot0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 37 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \cr_a_ok @@ -353917,7 +353623,7 @@ module \shiftrot0 wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 36 \dest3_o - attribute \src "libresoc.v:187138.7-187138.15" + attribute \src "libresoc.v:186886.7-186886.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \o_ok @@ -354150,7 +353856,7 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187773$12257 + cell $and $and$libresoc.v:187521$12251 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354158,10 +353864,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$98 connect \B \$100 - connect \Y $and$libresoc.v:187773$12257_Y + connect \Y $and$libresoc.v:187521$12251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187774$12258 + cell $and $and$libresoc.v:187522$12252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354169,10 +353875,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187774$12258_Y + connect \Y $and$libresoc.v:187522$12252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187775$12259 + cell $and $and$libresoc.v:187523$12253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354180,10 +353886,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187775$12259_Y + connect \Y $and$libresoc.v:187523$12253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187776$12260 + cell $and $and$libresoc.v:187524$12254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354191,10 +353897,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187776$12260_Y + connect \Y $and$libresoc.v:187524$12254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:187777$12261 + cell $and $and$libresoc.v:187525$12255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354202,10 +353908,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:187777$12261_Y + connect \Y $and$libresoc.v:187525$12255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187778$12262 + cell $and $and$libresoc.v:187526$12256 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354213,10 +353919,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$104 \$106 \$108 } - connect \Y $and$libresoc.v:187778$12262_Y + connect \Y $and$libresoc.v:187526$12256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187779$12263 + cell $and $and$libresoc.v:187527$12257 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354224,10 +353930,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187779$12263_Y + connect \Y $and$libresoc.v:187527$12257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187780$12264 + cell $and $and$libresoc.v:187528$12258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354235,10 +353941,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187780$12264_Y + connect \Y $and$libresoc.v:187528$12258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187781$12265 + cell $and $and$libresoc.v:187529$12259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354246,10 +353952,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187781$12265_Y + connect \Y $and$libresoc.v:187529$12259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187782$12266 + cell $and $and$libresoc.v:187530$12260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354257,10 +353963,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187782$12266_Y + connect \Y $and$libresoc.v:187530$12260_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:187784$12268 + cell $and $and$libresoc.v:187532$12262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354268,10 +353974,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:187784$12268_Y + connect \Y $and$libresoc.v:187532$12262_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:187786$12270 + cell $and $and$libresoc.v:187534$12264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354279,10 +353985,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:187786$12270_Y + connect \Y $and$libresoc.v:187534$12264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:187787$12271 + cell $and $and$libresoc.v:187535$12265 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354290,10 +353996,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187787$12271_Y + connect \Y $and$libresoc.v:187535$12265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187789$12273 + cell $and $and$libresoc.v:187537$12267 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354301,10 +354007,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:187789$12273_Y + connect \Y $and$libresoc.v:187537$12267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:187792$12276 + cell $and $and$libresoc.v:187540$12270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354312,10 +354018,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:187792$12276_Y + connect \Y $and$libresoc.v:187540$12270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187793$12277 + cell $and $and$libresoc.v:187541$12271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354323,10 +354029,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:187793$12277_Y + connect \Y $and$libresoc.v:187541$12271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:187798$12282 + cell $and $and$libresoc.v:187546$12276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354334,10 +354040,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:187798$12282_Y + connect \Y $and$libresoc.v:187546$12276_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187799$12283 + cell $and $and$libresoc.v:187547$12277 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354345,10 +354051,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187799$12283_Y + connect \Y $and$libresoc.v:187547$12277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187801$12285 + cell $and $and$libresoc.v:187549$12279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354356,10 +354062,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:187801$12285_Y + connect \Y $and$libresoc.v:187549$12279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187803$12287 + cell $and $and$libresoc.v:187551$12281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354367,10 +354073,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_shift_rot0_n_ready_i - connect \Y $and$libresoc.v:187803$12287_Y + connect \Y $and$libresoc.v:187551$12281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187804$12288 + cell $and $and$libresoc.v:187552$12282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354378,10 +354084,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_shift_rot0_n_valid_o - connect \Y $and$libresoc.v:187804$12288_Y + connect \Y $and$libresoc.v:187552$12282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187805$12289 + cell $and $and$libresoc.v:187553$12283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354389,10 +354095,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:187805$12289_Y + connect \Y $and$libresoc.v:187553$12283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:187811$12295 + cell $and $and$libresoc.v:187559$12289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354400,10 +354106,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:187811$12295_Y + connect \Y $and$libresoc.v:187559$12289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:187812$12296 + cell $and $and$libresoc.v:187560$12290 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354411,10 +354117,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187812$12296_Y + connect \Y $and$libresoc.v:187560$12290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187814$12298 + cell $and $and$libresoc.v:187562$12292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354422,10 +354128,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187814$12298_Y + connect \Y $and$libresoc.v:187562$12292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187815$12299 + cell $and $and$libresoc.v:187563$12293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354433,10 +354139,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187815$12299_Y + connect \Y $and$libresoc.v:187563$12293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187816$12300 + cell $and $and$libresoc.v:187564$12294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354444,10 +354150,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187816$12300_Y + connect \Y $and$libresoc.v:187564$12294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:187826$12310 + cell $and $and$libresoc.v:187574$12304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354455,10 +354161,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:187826$12310_Y + connect \Y $and$libresoc.v:187574$12304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:187827$12311 + cell $and $and$libresoc.v:187575$12305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354466,10 +354172,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:187827$12311_Y + connect \Y $and$libresoc.v:187575$12305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187828$12312 + cell $and $and$libresoc.v:187576$12306 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354477,10 +354183,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187828$12312_Y + connect \Y $and$libresoc.v:187576$12306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187830$12314 + cell $and $and$libresoc.v:187578$12308 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354488,10 +354194,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$94 connect \B { 3'111 \$96 1'1 } - connect \Y $and$libresoc.v:187830$12314_Y + connect \Y $and$libresoc.v:187578$12308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:187800$12284 + cell $eq $eq$libresoc.v:187548$12278 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354499,10 +354205,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:187800$12284_Y + connect \Y $eq$libresoc.v:187548$12278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:187802$12286 + cell $eq $eq$libresoc.v:187550$12280 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354510,74 +354216,74 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:187802$12286_Y + connect \Y $eq$libresoc.v:187550$12280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:187772$12256 + cell $not $not$libresoc.v:187520$12250 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:187772$12256_Y + connect \Y $not$libresoc.v:187520$12250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:187783$12267 + cell $not $not$libresoc.v:187531$12261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:187783$12267_Y + connect \Y $not$libresoc.v:187531$12261_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:187785$12269 + cell $not $not$libresoc.v:187533$12263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:187785$12269_Y + connect \Y $not$libresoc.v:187533$12263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187788$12272 + cell $not $not$libresoc.v:187536$12266 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:187788$12272_Y + connect \Y $not$libresoc.v:187536$12266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187791$12275 + cell $not $not$libresoc.v:187539$12269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:187791$12275_Y + connect \Y $not$libresoc.v:187539$12269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:187797$12281 + cell $not $not$libresoc.v:187545$12275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$libresoc.v:187797$12281_Y + connect \Y $not$libresoc.v:187545$12275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:187808$12292 + cell $not $not$libresoc.v:187556$12286 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:187808$12292_Y + connect \Y $not$libresoc.v:187556$12286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:187829$12313 + cell $not $not$libresoc.v:187577$12307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$libresoc.v:187829$12313_Y + connect \Y $not$libresoc.v:187577$12307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:187796$12280 + cell $or $or$libresoc.v:187544$12274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354585,10 +354291,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:187796$12280_Y + connect \Y $or$libresoc.v:187544$12274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:187806$12290 + cell $or $or$libresoc.v:187554$12284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354596,10 +354302,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187806$12290_Y + connect \Y $or$libresoc.v:187554$12284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:187807$12291 + cell $or $or$libresoc.v:187555$12285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354607,10 +354313,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187807$12291_Y + connect \Y $or$libresoc.v:187555$12285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:187809$12293 + cell $or $or$libresoc.v:187557$12287 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354618,10 +354324,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187809$12293_Y + connect \Y $or$libresoc.v:187557$12287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:187810$12294 + cell $or $or$libresoc.v:187558$12288 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354629,10 +354335,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187810$12294_Y + connect \Y $or$libresoc.v:187558$12288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:187813$12297 + cell $or $or$libresoc.v:187561$12291 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354640,10 +354346,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:187813$12297_Y + connect \Y $or$libresoc.v:187561$12291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:187819$12303 + cell $or $or$libresoc.v:187567$12297 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354651,98 +354357,98 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:187819$12303_Y + connect \Y $or$libresoc.v:187567$12297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:187825$12309 + cell $reduce_and $reduce_and$libresoc.v:187573$12303 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:187825$12309_Y + connect \Y $reduce_and$libresoc.v:187573$12303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:187790$12274 + cell $reduce_or $reduce_or$libresoc.v:187538$12268 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:187790$12274_Y + connect \Y $reduce_or$libresoc.v:187538$12268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187794$12278 + cell $reduce_or $reduce_or$libresoc.v:187542$12272 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:187794$12278_Y + connect \Y $reduce_or$libresoc.v:187542$12272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187795$12279 + cell $reduce_or $reduce_or$libresoc.v:187543$12273 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:187795$12279_Y + connect \Y $reduce_or$libresoc.v:187543$12273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:187817$12301 + cell $mux $ternary$libresoc.v:187565$12295 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:187817$12301_Y + connect \Y $ternary$libresoc.v:187565$12295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:187818$12302 + cell $mux $ternary$libresoc.v:187566$12296 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_shift_rot0_sr_op__imm_data__data connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:187818$12302_Y + connect \Y $ternary$libresoc.v:187566$12296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187820$12304 + cell $mux $ternary$libresoc.v:187568$12298 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:187820$12304_Y + connect \Y $ternary$libresoc.v:187568$12298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187821$12305 + cell $mux $ternary$libresoc.v:187569$12299 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:187821$12305_Y + connect \Y $ternary$libresoc.v:187569$12299_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187822$12306 + cell $mux $ternary$libresoc.v:187570$12300 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:187822$12306_Y + connect \Y $ternary$libresoc.v:187570$12300_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187823$12307 + cell $mux $ternary$libresoc.v:187571$12301 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:187823$12307_Y + connect \Y $ternary$libresoc.v:187571$12301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187824$12308 + cell $mux $ternary$libresoc.v:187572$12302 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:187824$12308_Y + connect \Y $ternary$libresoc.v:187572$12302_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:187917.15-187923.4" + attribute \src "libresoc.v:187665.15-187671.4" cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -354751,7 +354457,7 @@ module \shiftrot0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:187924.18-187959.4" + attribute \src "libresoc.v:187672.18-187707.4" cell \alu_shift_rot0 \alu_shift_rot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -354789,7 +354495,7 @@ module \shiftrot0 connect \xer_so \alu_shift_rot0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:187960.16-187966.4" + attribute \src "libresoc.v:187708.16-187714.4" cell \alui_l$124 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -354798,7 +354504,7 @@ module \shiftrot0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:187967.15-187973.4" + attribute \src "libresoc.v:187715.15-187721.4" cell \opc_l$120 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -354807,7 +354513,7 @@ module \shiftrot0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:187974.15-187980.4" + attribute \src "libresoc.v:187722.15-187728.4" cell \req_l$121 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -354816,7 +354522,7 @@ module \shiftrot0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:187981.15-187987.4" + attribute \src "libresoc.v:187729.15-187735.4" cell \rok_l$123 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -354825,7 +354531,7 @@ module \shiftrot0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:187988.15-187993.4" + attribute \src "libresoc.v:187736.15-187741.4" cell \rst_l$122 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -354833,7 +354539,7 @@ module \shiftrot0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:187994.15-188000.4" + attribute \src "libresoc.v:187742.15-187748.4" cell \src_l$119 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -354841,667 +354547,667 @@ module \shiftrot0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:187138.7-187138.20" - process $proc$libresoc.v:187138$12481 + attribute \src "libresoc.v:186886.7-186886.20" + process $proc$libresoc.v:186886$12475 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187260.7-187260.24" - process $proc$libresoc.v:187260$12482 + attribute \src "libresoc.v:187008.7-187008.24" + process $proc$libresoc.v:187008$12476 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:187270.7-187270.26" - process $proc$libresoc.v:187270$12483 + attribute \src "libresoc.v:187018.7-187018.26" + process $proc$libresoc.v:187018$12477 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:187278.7-187278.25" - process $proc$libresoc.v:187278$12484 + attribute \src "libresoc.v:187026.7-187026.25" + process $proc$libresoc.v:187026$12478 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:187321.14-187321.54" - process $proc$libresoc.v:187321$12485 + attribute \src "libresoc.v:187069.14-187069.54" + process $proc$libresoc.v:187069$12479 assign { } { } assign $1\alu_shift_rot0_sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:187325.14-187325.73" - process $proc$libresoc.v:187325$12486 + attribute \src "libresoc.v:187073.14-187073.73" + process $proc$libresoc.v:187073$12480 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:187329.7-187329.48" - process $proc$libresoc.v:187329$12487 + attribute \src "libresoc.v:187077.7-187077.48" + process $proc$libresoc.v:187077$12481 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:187337.13-187337.53" - process $proc$libresoc.v:187337$12488 + attribute \src "libresoc.v:187085.13-187085.53" + process $proc$libresoc.v:187085$12482 assign { } { } assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 sync always sync init update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:187341.7-187341.44" - process $proc$libresoc.v:187341$12489 + attribute \src "libresoc.v:187089.7-187089.44" + process $proc$libresoc.v:187089$12483 assign { } { } assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:187345.14-187345.48" - process $proc$libresoc.v:187345$12490 + attribute \src "libresoc.v:187093.14-187093.48" + process $proc$libresoc.v:187093$12484 assign { } { } assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 sync always sync init update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:187424.13-187424.52" - process $proc$libresoc.v:187424$12491 + attribute \src "libresoc.v:187172.13-187172.52" + process $proc$libresoc.v:187172$12485 assign { } { } assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:187428.7-187428.45" - process $proc$libresoc.v:187428$12492 + attribute \src "libresoc.v:187176.7-187176.45" + process $proc$libresoc.v:187176$12486 assign { } { } assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:187432.7-187432.44" - process $proc$libresoc.v:187432$12493 + attribute \src "libresoc.v:187180.7-187180.44" + process $proc$libresoc.v:187180$12487 assign { } { } assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:187436.7-187436.45" - process $proc$libresoc.v:187436$12494 + attribute \src "libresoc.v:187184.7-187184.45" + process $proc$libresoc.v:187184$12488 assign { } { } assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:187440.7-187440.42" - process $proc$libresoc.v:187440$12495 + attribute \src "libresoc.v:187188.7-187188.42" + process $proc$libresoc.v:187188$12489 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:187444.7-187444.42" - process $proc$libresoc.v:187444$12496 + attribute \src "libresoc.v:187192.7-187192.42" + process $proc$libresoc.v:187192$12490 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:187448.7-187448.48" - process $proc$libresoc.v:187448$12497 + attribute \src "libresoc.v:187196.7-187196.48" + process $proc$libresoc.v:187196$12491 assign { } { } assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:187452.7-187452.45" - process $proc$libresoc.v:187452$12498 + attribute \src "libresoc.v:187200.7-187200.45" + process $proc$libresoc.v:187200$12492 assign { } { } assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:187456.7-187456.42" - process $proc$libresoc.v:187456$12499 + attribute \src "libresoc.v:187204.7-187204.42" + process $proc$libresoc.v:187204$12493 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:187460.7-187460.42" - process $proc$libresoc.v:187460$12500 + attribute \src "libresoc.v:187208.7-187208.42" + process $proc$libresoc.v:187208$12494 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:187464.7-187464.45" - process $proc$libresoc.v:187464$12501 + attribute \src "libresoc.v:187212.7-187212.45" + process $proc$libresoc.v:187212$12495 assign { } { } assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:187476.7-187476.27" - process $proc$libresoc.v:187476$12502 + attribute \src "libresoc.v:187224.7-187224.27" + process $proc$libresoc.v:187224$12496 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:187510.14-187510.47" - process $proc$libresoc.v:187510$12503 + attribute \src "libresoc.v:187258.14-187258.47" + process $proc$libresoc.v:187258$12497 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:187514.7-187514.27" - process $proc$libresoc.v:187514$12504 + attribute \src "libresoc.v:187262.7-187262.27" + process $proc$libresoc.v:187262$12498 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:187518.13-187518.33" - process $proc$libresoc.v:187518$12505 + attribute \src "libresoc.v:187266.13-187266.33" + process $proc$libresoc.v:187266$12499 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:187522.7-187522.30" - process $proc$libresoc.v:187522$12506 + attribute \src "libresoc.v:187270.7-187270.30" + process $proc$libresoc.v:187270$12500 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:187526.13-187526.35" - process $proc$libresoc.v:187526$12507 + attribute \src "libresoc.v:187274.13-187274.35" + process $proc$libresoc.v:187274$12501 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:187530.7-187530.32" - process $proc$libresoc.v:187530$12508 + attribute \src "libresoc.v:187278.7-187278.32" + process $proc$libresoc.v:187278$12502 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:187547.7-187547.25" - process $proc$libresoc.v:187547$12509 + attribute \src "libresoc.v:187295.7-187295.25" + process $proc$libresoc.v:187295$12503 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:187551.7-187551.25" - process $proc$libresoc.v:187551$12510 + attribute \src "libresoc.v:187299.7-187299.25" + process $proc$libresoc.v:187299$12504 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:187683.13-187683.30" - process $proc$libresoc.v:187683$12511 + attribute \src "libresoc.v:187431.13-187431.30" + process $proc$libresoc.v:187431$12505 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:187691.13-187691.31" - process $proc$libresoc.v:187691$12512 + attribute \src "libresoc.v:187439.13-187439.31" + process $proc$libresoc.v:187439$12506 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:187695.13-187695.31" - process $proc$libresoc.v:187695$12513 + attribute \src "libresoc.v:187443.13-187443.31" + process $proc$libresoc.v:187443$12507 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:187707.7-187707.26" - process $proc$libresoc.v:187707$12514 + attribute \src "libresoc.v:187455.7-187455.26" + process $proc$libresoc.v:187455$12508 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:187711.7-187711.26" - process $proc$libresoc.v:187711$12515 + attribute \src "libresoc.v:187459.7-187459.26" + process $proc$libresoc.v:187459$12509 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:187715.7-187715.25" - process $proc$libresoc.v:187715$12516 + attribute \src "libresoc.v:187463.7-187463.25" + process $proc$libresoc.v:187463$12510 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:187719.7-187719.25" - process $proc$libresoc.v:187719$12517 + attribute \src "libresoc.v:187467.7-187467.25" + process $proc$libresoc.v:187467$12511 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:187737.13-187737.32" - process $proc$libresoc.v:187737$12518 + attribute \src "libresoc.v:187485.13-187485.32" + process $proc$libresoc.v:187485$12512 assign { } { } assign $1\src_l_r_src[4:0] 5'11111 sync always sync init update \src_l_r_src $1\src_l_r_src[4:0] end - attribute \src "libresoc.v:187741.13-187741.32" - process $proc$libresoc.v:187741$12519 + attribute \src "libresoc.v:187489.13-187489.32" + process $proc$libresoc.v:187489$12513 assign { } { } assign $1\src_l_s_src[4:0] 5'00000 sync always sync init update \src_l_s_src $1\src_l_s_src[4:0] end - attribute \src "libresoc.v:187747.14-187747.43" - process $proc$libresoc.v:187747$12520 + attribute \src "libresoc.v:187495.14-187495.43" + process $proc$libresoc.v:187495$12514 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:187751.14-187751.43" - process $proc$libresoc.v:187751$12521 + attribute \src "libresoc.v:187499.14-187499.43" + process $proc$libresoc.v:187499$12515 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:187755.14-187755.43" - process $proc$libresoc.v:187755$12522 + attribute \src "libresoc.v:187503.14-187503.43" + process $proc$libresoc.v:187503$12516 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:187759.7-187759.20" - process $proc$libresoc.v:187759$12523 + attribute \src "libresoc.v:187507.7-187507.20" + process $proc$libresoc.v:187507$12517 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:187763.13-187763.26" - process $proc$libresoc.v:187763$12524 + attribute \src "libresoc.v:187511.13-187511.26" + process $proc$libresoc.v:187511$12518 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:187831.3-187832.39" - process $proc$libresoc.v:187831$12315 + attribute \src "libresoc.v:187579.3-187580.39" + process $proc$libresoc.v:187579$12309 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:187833.3-187834.43" - process $proc$libresoc.v:187833$12316 + attribute \src "libresoc.v:187581.3-187582.43" + process $proc$libresoc.v:187581$12310 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:187835.3-187836.29" - process $proc$libresoc.v:187835$12317 + attribute \src "libresoc.v:187583.3-187584.29" + process $proc$libresoc.v:187583$12311 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:187837.3-187838.29" - process $proc$libresoc.v:187837$12318 + attribute \src "libresoc.v:187585.3-187586.29" + process $proc$libresoc.v:187585$12312 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:187839.3-187840.29" - process $proc$libresoc.v:187839$12319 + attribute \src "libresoc.v:187587.3-187588.29" + process $proc$libresoc.v:187587$12313 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:187841.3-187842.29" - process $proc$libresoc.v:187841$12320 + attribute \src "libresoc.v:187589.3-187590.29" + process $proc$libresoc.v:187589$12314 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:187843.3-187844.29" - process $proc$libresoc.v:187843$12321 + attribute \src "libresoc.v:187591.3-187592.29" + process $proc$libresoc.v:187591$12315 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:187845.3-187846.47" - process $proc$libresoc.v:187845$12322 + attribute \src "libresoc.v:187593.3-187594.47" + process $proc$libresoc.v:187593$12316 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:187847.3-187848.53" - process $proc$libresoc.v:187847$12323 + attribute \src "libresoc.v:187595.3-187596.53" + process $proc$libresoc.v:187595$12317 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:187849.3-187850.43" - process $proc$libresoc.v:187849$12324 + attribute \src "libresoc.v:187597.3-187598.43" + process $proc$libresoc.v:187597$12318 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:187851.3-187852.49" - process $proc$libresoc.v:187851$12325 + attribute \src "libresoc.v:187599.3-187600.49" + process $proc$libresoc.v:187599$12319 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:187853.3-187854.37" - process $proc$libresoc.v:187853$12326 + attribute \src "libresoc.v:187601.3-187602.37" + process $proc$libresoc.v:187601$12320 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:187855.3-187856.43" - process $proc$libresoc.v:187855$12327 + attribute \src "libresoc.v:187603.3-187604.43" + process $proc$libresoc.v:187603$12321 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:187857.3-187858.79" - process $proc$libresoc.v:187857$12328 + attribute \src "libresoc.v:187605.3-187606.79" + process $proc$libresoc.v:187605$12322 assign { } { } assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:187859.3-187860.75" - process $proc$libresoc.v:187859$12329 + attribute \src "libresoc.v:187607.3-187608.75" + process $proc$libresoc.v:187607$12323 assign { } { } assign $0\alu_shift_rot0_sr_op__fn_unit[13:0] \alu_shift_rot0_sr_op__fn_unit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:187861.3-187862.89" - process $proc$libresoc.v:187861$12330 + attribute \src "libresoc.v:187609.3-187610.89" + process $proc$libresoc.v:187609$12324 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:187863.3-187864.85" - process $proc$libresoc.v:187863$12331 + attribute \src "libresoc.v:187611.3-187612.85" + process $proc$libresoc.v:187611$12325 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:187865.3-187866.73" - process $proc$libresoc.v:187865$12332 + attribute \src "libresoc.v:187613.3-187614.73" + process $proc$libresoc.v:187613$12326 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:187867.3-187868.73" - process $proc$libresoc.v:187867$12333 + attribute \src "libresoc.v:187615.3-187616.73" + process $proc$libresoc.v:187615$12327 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:187869.3-187870.73" - process $proc$libresoc.v:187869$12334 + attribute \src "libresoc.v:187617.3-187618.73" + process $proc$libresoc.v:187617$12328 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:187871.3-187872.73" - process $proc$libresoc.v:187871$12335 + attribute \src "libresoc.v:187619.3-187620.73" + process $proc$libresoc.v:187619$12329 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:187873.3-187874.79" - process $proc$libresoc.v:187873$12336 + attribute \src "libresoc.v:187621.3-187622.79" + process $proc$libresoc.v:187621$12330 assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:187875.3-187876.79" - process $proc$libresoc.v:187875$12337 + attribute \src "libresoc.v:187623.3-187624.79" + process $proc$libresoc.v:187623$12331 assign { } { } assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:187877.3-187878.83" - process $proc$libresoc.v:187877$12338 + attribute \src "libresoc.v:187625.3-187626.83" + process $proc$libresoc.v:187625$12332 assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:187879.3-187880.85" - process $proc$libresoc.v:187879$12339 + attribute \src "libresoc.v:187627.3-187628.85" + process $proc$libresoc.v:187627$12333 assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:187881.3-187882.77" - process $proc$libresoc.v:187881$12340 + attribute \src "libresoc.v:187629.3-187630.77" + process $proc$libresoc.v:187629$12334 assign { } { } assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:187883.3-187884.79" - process $proc$libresoc.v:187883$12341 + attribute \src "libresoc.v:187631.3-187632.79" + process $proc$libresoc.v:187631$12335 assign { } { } assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:187885.3-187886.77" - process $proc$libresoc.v:187885$12342 + attribute \src "libresoc.v:187633.3-187634.77" + process $proc$libresoc.v:187633$12336 assign { } { } assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:187887.3-187888.79" - process $proc$libresoc.v:187887$12343 + attribute \src "libresoc.v:187635.3-187636.79" + process $proc$libresoc.v:187635$12337 assign { } { } assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:187889.3-187890.69" - process $proc$libresoc.v:187889$12344 + attribute \src "libresoc.v:187637.3-187638.69" + process $proc$libresoc.v:187637$12338 assign { } { } assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:187891.3-187892.39" - process $proc$libresoc.v:187891$12345 + attribute \src "libresoc.v:187639.3-187640.39" + process $proc$libresoc.v:187639$12339 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:187893.3-187894.39" - process $proc$libresoc.v:187893$12346 + attribute \src "libresoc.v:187641.3-187642.39" + process $proc$libresoc.v:187641$12340 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:187895.3-187896.39" - process $proc$libresoc.v:187895$12347 + attribute \src "libresoc.v:187643.3-187644.39" + process $proc$libresoc.v:187643$12341 assign { } { } assign $0\src_l_r_src[4:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[4:0] end - attribute \src "libresoc.v:187897.3-187898.39" - process $proc$libresoc.v:187897$12348 + attribute \src "libresoc.v:187645.3-187646.39" + process $proc$libresoc.v:187645$12342 assign { } { } assign $0\src_l_s_src[4:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[4:0] end - attribute \src "libresoc.v:187899.3-187900.39" - process $proc$libresoc.v:187899$12349 + attribute \src "libresoc.v:187647.3-187648.39" + process $proc$libresoc.v:187647$12343 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:187901.3-187902.39" - process $proc$libresoc.v:187901$12350 + attribute \src "libresoc.v:187649.3-187650.39" + process $proc$libresoc.v:187649$12344 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:187903.3-187904.39" - process $proc$libresoc.v:187903$12351 + attribute \src "libresoc.v:187651.3-187652.39" + process $proc$libresoc.v:187651$12345 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:187905.3-187906.39" - process $proc$libresoc.v:187905$12352 + attribute \src "libresoc.v:187653.3-187654.39" + process $proc$libresoc.v:187653$12346 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:187907.3-187908.41" - process $proc$libresoc.v:187907$12353 + attribute \src "libresoc.v:187655.3-187656.41" + process $proc$libresoc.v:187655$12347 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:187909.3-187910.41" - process $proc$libresoc.v:187909$12354 + attribute \src "libresoc.v:187657.3-187658.41" + process $proc$libresoc.v:187657$12348 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:187911.3-187912.37" - process $proc$libresoc.v:187911$12355 + attribute \src "libresoc.v:187659.3-187660.37" + process $proc$libresoc.v:187659$12349 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:187913.3-187914.46" - process $proc$libresoc.v:187913$12356 + attribute \src "libresoc.v:187661.3-187662.46" + process $proc$libresoc.v:187661$12350 assign { } { } assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:187915.3-187916.25" - process $proc$libresoc.v:187915$12357 + attribute \src "libresoc.v:187663.3-187664.25" + process $proc$libresoc.v:187663$12351 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:188001.3-188010.6" - process $proc$libresoc.v:188001$12358 + attribute \src "libresoc.v:187749.3-187758.6" + process $proc$libresoc.v:187749$12352 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:188002.5-188002.29" + attribute \src "libresoc.v:187750.5-187750.29" switch \initial - attribute \src "libresoc.v:188002.9-188002.17" + attribute \src "libresoc.v:187750.9-187750.17" case 1'1 case end @@ -355517,14 +355223,14 @@ module \shiftrot0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:188011.3-188019.6" - process $proc$libresoc.v:188011$12359 + attribute \src "libresoc.v:187759.3-187767.6" + process $proc$libresoc.v:187759$12353 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12360 $1\rok_l_s_rdok$next[0:0]$12361 - attribute \src "libresoc.v:188012.5-188012.29" + assign $0\rok_l_s_rdok$next[0:0]$12354 $1\rok_l_s_rdok$next[0:0]$12355 + attribute \src "libresoc.v:187760.5-187760.29" switch \initial - attribute \src "libresoc.v:188012.9-188012.17" + attribute \src "libresoc.v:187760.9-187760.17" case 1'1 case end @@ -355533,21 +355239,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12361 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12355 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12361 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12355 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12360 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12354 end - attribute \src "libresoc.v:188020.3-188028.6" - process $proc$libresoc.v:188020$12362 + attribute \src "libresoc.v:187768.3-187776.6" + process $proc$libresoc.v:187768$12356 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12363 $1\rok_l_r_rdok$next[0:0]$12364 - attribute \src "libresoc.v:188021.5-188021.29" + assign $0\rok_l_r_rdok$next[0:0]$12357 $1\rok_l_r_rdok$next[0:0]$12358 + attribute \src "libresoc.v:187769.5-187769.29" switch \initial - attribute \src "libresoc.v:188021.9-188021.17" + attribute \src "libresoc.v:187769.9-187769.17" case 1'1 case end @@ -355556,21 +355262,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12364 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12358 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12364 \$64 + assign $1\rok_l_r_rdok$next[0:0]$12358 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12363 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12357 end - attribute \src "libresoc.v:188029.3-188037.6" - process $proc$libresoc.v:188029$12365 + attribute \src "libresoc.v:187777.3-187785.6" + process $proc$libresoc.v:187777$12359 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12366 $1\rst_l_s_rst$next[0:0]$12367 - attribute \src "libresoc.v:188030.5-188030.29" + assign $0\rst_l_s_rst$next[0:0]$12360 $1\rst_l_s_rst$next[0:0]$12361 + attribute \src "libresoc.v:187778.5-187778.29" switch \initial - attribute \src "libresoc.v:188030.9-188030.17" + attribute \src "libresoc.v:187778.9-187778.17" case 1'1 case end @@ -355579,21 +355285,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12367 1'0 + assign $1\rst_l_s_rst$next[0:0]$12361 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12367 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12361 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12366 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12360 end - attribute \src "libresoc.v:188038.3-188046.6" - process $proc$libresoc.v:188038$12368 + attribute \src "libresoc.v:187786.3-187794.6" + process $proc$libresoc.v:187786$12362 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12369 $1\rst_l_r_rst$next[0:0]$12370 - attribute \src "libresoc.v:188039.5-188039.29" + assign $0\rst_l_r_rst$next[0:0]$12363 $1\rst_l_r_rst$next[0:0]$12364 + attribute \src "libresoc.v:187787.5-187787.29" switch \initial - attribute \src "libresoc.v:188039.9-188039.17" + attribute \src "libresoc.v:187787.9-187787.17" case 1'1 case end @@ -355602,21 +355308,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12370 1'1 + assign $1\rst_l_r_rst$next[0:0]$12364 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12370 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12364 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12369 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12363 end - attribute \src "libresoc.v:188047.3-188055.6" - process $proc$libresoc.v:188047$12371 + attribute \src "libresoc.v:187795.3-187803.6" + process $proc$libresoc.v:187795$12365 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12372 $1\opc_l_s_opc$next[0:0]$12373 - attribute \src "libresoc.v:188048.5-188048.29" + assign $0\opc_l_s_opc$next[0:0]$12366 $1\opc_l_s_opc$next[0:0]$12367 + attribute \src "libresoc.v:187796.5-187796.29" switch \initial - attribute \src "libresoc.v:188048.9-188048.17" + attribute \src "libresoc.v:187796.9-187796.17" case 1'1 case end @@ -355625,21 +355331,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12373 1'0 + assign $1\opc_l_s_opc$next[0:0]$12367 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12373 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12367 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12372 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12366 end - attribute \src "libresoc.v:188056.3-188064.6" - process $proc$libresoc.v:188056$12374 + attribute \src "libresoc.v:187804.3-187812.6" + process $proc$libresoc.v:187804$12368 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12375 $1\opc_l_r_opc$next[0:0]$12376 - attribute \src "libresoc.v:188057.5-188057.29" + assign $0\opc_l_r_opc$next[0:0]$12369 $1\opc_l_r_opc$next[0:0]$12370 + attribute \src "libresoc.v:187805.5-187805.29" switch \initial - attribute \src "libresoc.v:188057.9-188057.17" + attribute \src "libresoc.v:187805.9-187805.17" case 1'1 case end @@ -355648,21 +355354,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12376 1'1 + assign $1\opc_l_r_opc$next[0:0]$12370 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12376 \req_done + assign $1\opc_l_r_opc$next[0:0]$12370 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12375 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12369 end - attribute \src "libresoc.v:188065.3-188073.6" - process $proc$libresoc.v:188065$12377 + attribute \src "libresoc.v:187813.3-187821.6" + process $proc$libresoc.v:187813$12371 assign { } { } assign { } { } - assign $0\src_l_s_src$next[4:0]$12378 $1\src_l_s_src$next[4:0]$12379 - attribute \src "libresoc.v:188066.5-188066.29" + assign $0\src_l_s_src$next[4:0]$12372 $1\src_l_s_src$next[4:0]$12373 + attribute \src "libresoc.v:187814.5-187814.29" switch \initial - attribute \src "libresoc.v:188066.9-188066.17" + attribute \src "libresoc.v:187814.9-187814.17" case 1'1 case end @@ -355671,21 +355377,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[4:0]$12379 5'00000 + assign $1\src_l_s_src$next[4:0]$12373 5'00000 case - assign $1\src_l_s_src$next[4:0]$12379 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[4:0]$12373 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12378 + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12372 end - attribute \src "libresoc.v:188074.3-188082.6" - process $proc$libresoc.v:188074$12380 + attribute \src "libresoc.v:187822.3-187830.6" + process $proc$libresoc.v:187822$12374 assign { } { } assign { } { } - assign $0\src_l_r_src$next[4:0]$12381 $1\src_l_r_src$next[4:0]$12382 - attribute \src "libresoc.v:188075.5-188075.29" + assign $0\src_l_r_src$next[4:0]$12375 $1\src_l_r_src$next[4:0]$12376 + attribute \src "libresoc.v:187823.5-187823.29" switch \initial - attribute \src "libresoc.v:188075.9-188075.17" + attribute \src "libresoc.v:187823.9-187823.17" case 1'1 case end @@ -355694,21 +355400,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[4:0]$12382 5'11111 + assign $1\src_l_r_src$next[4:0]$12376 5'11111 case - assign $1\src_l_r_src$next[4:0]$12382 \reset_r + assign $1\src_l_r_src$next[4:0]$12376 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12381 + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12375 end - attribute \src "libresoc.v:188083.3-188091.6" - process $proc$libresoc.v:188083$12383 + attribute \src "libresoc.v:187831.3-187839.6" + process $proc$libresoc.v:187831$12377 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$12384 $1\req_l_s_req$next[2:0]$12385 - attribute \src "libresoc.v:188084.5-188084.29" + assign $0\req_l_s_req$next[2:0]$12378 $1\req_l_s_req$next[2:0]$12379 + attribute \src "libresoc.v:187832.5-187832.29" switch \initial - attribute \src "libresoc.v:188084.9-188084.17" + attribute \src "libresoc.v:187832.9-187832.17" case 1'1 case end @@ -355717,21 +355423,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$12385 3'000 + assign $1\req_l_s_req$next[2:0]$12379 3'000 case - assign $1\req_l_s_req$next[2:0]$12385 \$66 + assign $1\req_l_s_req$next[2:0]$12379 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12384 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12378 end - attribute \src "libresoc.v:188092.3-188100.6" - process $proc$libresoc.v:188092$12386 + attribute \src "libresoc.v:187840.3-187848.6" + process $proc$libresoc.v:187840$12380 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$12387 $1\req_l_r_req$next[2:0]$12388 - attribute \src "libresoc.v:188093.5-188093.29" + assign $0\req_l_r_req$next[2:0]$12381 $1\req_l_r_req$next[2:0]$12382 + attribute \src "libresoc.v:187841.5-187841.29" switch \initial - attribute \src "libresoc.v:188093.9-188093.17" + attribute \src "libresoc.v:187841.9-187841.17" case 1'1 case end @@ -355740,15 +355446,15 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$12388 3'111 + assign $1\req_l_r_req$next[2:0]$12382 3'111 case - assign $1\req_l_r_req$next[2:0]$12388 \$68 + assign $1\req_l_r_req$next[2:0]$12382 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12387 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12381 end - attribute \src "libresoc.v:188101.3-188138.6" - process $proc$libresoc.v:188101$12389 + attribute \src "libresoc.v:187849.3-187886.6" + process $proc$libresoc.v:187849$12383 assign { } { } assign { } { } assign { } { } @@ -355783,32 +355489,32 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12390 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407 + assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12384 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12401 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12393 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410 - assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12394 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411 - assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12395 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412 - assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12396 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413 - assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12397 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414 - assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12398 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415 - assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12399 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416 + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12387 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12404 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12388 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12405 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12389 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12406 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12390 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12407 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12391 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12408 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12392 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12409 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12393 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12410 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12402 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419 - assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12403 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420 + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12396 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12413 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12397 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12414 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12406 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423 - assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12391 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424 - assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12392 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425 - assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12400 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426 - assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12401 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427 - assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12404 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428 - assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12405 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429 - attribute \src "libresoc.v:188102.5-188102.29" + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12400 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12417 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12385 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12418 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12386 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12419 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12394 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12395 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12398 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12422 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12399 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12423 + attribute \src "libresoc.v:187850.5-187850.29" switch \initial - attribute \src "libresoc.v:188102.9-188102.17" + attribute \src "libresoc.v:187850.9-187850.17" case 1'1 case end @@ -355833,25 +355539,25 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12406 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12410 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12409 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12414 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12405 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12413 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12404 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12408 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12417 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12412 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12411 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12415 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12416 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12403 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12402 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12401 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12407 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } case - assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407 \alu_shift_rot0_sr_op__fn_unit - assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408 \alu_shift_rot0_sr_op__imm_data__data - assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409 \alu_shift_rot0_sr_op__imm_data__ok - assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410 \alu_shift_rot0_sr_op__input_carry - assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411 \alu_shift_rot0_sr_op__input_cr - assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412 \alu_shift_rot0_sr_op__insn - assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413 \alu_shift_rot0_sr_op__insn_type - assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414 \alu_shift_rot0_sr_op__invert_in - assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415 \alu_shift_rot0_sr_op__is_32bit - assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416 \alu_shift_rot0_sr_op__is_signed - assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417 \alu_shift_rot0_sr_op__oe__oe - assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418 \alu_shift_rot0_sr_op__oe__ok - assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419 \alu_shift_rot0_sr_op__output_carry - assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420 \alu_shift_rot0_sr_op__output_cr - assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421 \alu_shift_rot0_sr_op__rc__ok - assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422 \alu_shift_rot0_sr_op__rc__rc - assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423 \alu_shift_rot0_sr_op__write_cr0 + assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12401 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12402 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12403 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12404 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12405 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12406 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12407 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12408 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12409 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12410 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12411 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12412 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12413 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12414 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12415 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12416 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12417 \alu_shift_rot0_sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -355863,53 +355569,53 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425 1'0 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429 1'0 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428 1'0 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426 1'0 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427 1'0 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12418 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12419 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12423 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12422 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 1'0 case - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12418 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12402 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12419 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12403 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12411 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12412 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12422 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12415 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12423 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12416 end sync always - update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12390 - update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12391 - update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12392 - update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12393 - update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12394 - update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12395 - update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12396 - update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12397 - update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12398 - update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12399 - update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12400 - update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12401 - update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12402 - update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12403 - update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12404 - update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12405 - update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12406 + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12384 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12385 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12386 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12387 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12388 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12389 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12390 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12391 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12392 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12393 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12394 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12395 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12396 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12397 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12398 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12399 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12400 end - attribute \src "libresoc.v:188139.3-188160.6" - process $proc$libresoc.v:188139$12430 + attribute \src "libresoc.v:187887.3-187908.6" + process $proc$libresoc.v:187887$12424 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12431 $2\data_r0__o$next[63:0]$12435 + assign $0\data_r0__o$next[63:0]$12425 $2\data_r0__o$next[63:0]$12429 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12432 $3\data_r0__o_ok$next[0:0]$12437 - attribute \src "libresoc.v:188140.5-188140.29" + assign $0\data_r0__o_ok$next[0:0]$12426 $3\data_r0__o_ok$next[0:0]$12431 + attribute \src "libresoc.v:187888.5-187888.29" switch \initial - attribute \src "libresoc.v:188140.9-188140.17" + attribute \src "libresoc.v:187888.9-187888.17" case 1'1 case end @@ -355919,10 +355625,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12434 $1\data_r0__o$next[63:0]$12433 } { \o_ok \alu_shift_rot0_o } + assign { $1\data_r0__o_ok$next[0:0]$12428 $1\data_r0__o$next[63:0]$12427 } { \o_ok \alu_shift_rot0_o } case - assign $1\data_r0__o$next[63:0]$12433 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12434 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12427 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12428 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -355930,38 +355636,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12436 $2\data_r0__o$next[63:0]$12435 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12430 $2\data_r0__o$next[63:0]$12429 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12435 $1\data_r0__o$next[63:0]$12433 - assign $2\data_r0__o_ok$next[0:0]$12436 $1\data_r0__o_ok$next[0:0]$12434 + assign $2\data_r0__o$next[63:0]$12429 $1\data_r0__o$next[63:0]$12427 + assign $2\data_r0__o_ok$next[0:0]$12430 $1\data_r0__o_ok$next[0:0]$12428 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12437 1'0 + assign $3\data_r0__o_ok$next[0:0]$12431 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12437 $2\data_r0__o_ok$next[0:0]$12436 + assign $3\data_r0__o_ok$next[0:0]$12431 $2\data_r0__o_ok$next[0:0]$12430 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12431 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12432 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12425 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12426 end - attribute \src "libresoc.v:188161.3-188182.6" - process $proc$libresoc.v:188161$12438 + attribute \src "libresoc.v:187909.3-187930.6" + process $proc$libresoc.v:187909$12432 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$12439 $2\data_r1__cr_a$next[3:0]$12443 + assign $0\data_r1__cr_a$next[3:0]$12433 $2\data_r1__cr_a$next[3:0]$12437 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$12440 $3\data_r1__cr_a_ok$next[0:0]$12445 - attribute \src "libresoc.v:188162.5-188162.29" + assign $0\data_r1__cr_a_ok$next[0:0]$12434 $3\data_r1__cr_a_ok$next[0:0]$12439 + attribute \src "libresoc.v:187910.5-187910.29" switch \initial - attribute \src "libresoc.v:188162.9-188162.17" + attribute \src "libresoc.v:187910.9-187910.17" case 1'1 case end @@ -355971,10 +355677,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$12442 $1\data_r1__cr_a$next[3:0]$12441 } { \cr_a_ok \alu_shift_rot0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$12436 $1\data_r1__cr_a$next[3:0]$12435 } { \cr_a_ok \alu_shift_rot0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$12441 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$12442 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$12435 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12436 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -355982,38 +355688,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$12444 $2\data_r1__cr_a$next[3:0]$12443 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$12438 $2\data_r1__cr_a$next[3:0]$12437 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$12443 $1\data_r1__cr_a$next[3:0]$12441 - assign $2\data_r1__cr_a_ok$next[0:0]$12444 $1\data_r1__cr_a_ok$next[0:0]$12442 + assign $2\data_r1__cr_a$next[3:0]$12437 $1\data_r1__cr_a$next[3:0]$12435 + assign $2\data_r1__cr_a_ok$next[0:0]$12438 $1\data_r1__cr_a_ok$next[0:0]$12436 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$12445 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$12439 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$12445 $2\data_r1__cr_a_ok$next[0:0]$12444 + assign $3\data_r1__cr_a_ok$next[0:0]$12439 $2\data_r1__cr_a_ok$next[0:0]$12438 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12439 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12440 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12433 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12434 end - attribute \src "libresoc.v:188183.3-188204.6" - process $proc$libresoc.v:188183$12446 + attribute \src "libresoc.v:187931.3-187952.6" + process $proc$libresoc.v:187931$12440 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$12447 $2\data_r2__xer_ca$next[1:0]$12451 + assign $0\data_r2__xer_ca$next[1:0]$12441 $2\data_r2__xer_ca$next[1:0]$12445 assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$12448 $3\data_r2__xer_ca_ok$next[0:0]$12453 - attribute \src "libresoc.v:188184.5-188184.29" + assign $0\data_r2__xer_ca_ok$next[0:0]$12442 $3\data_r2__xer_ca_ok$next[0:0]$12447 + attribute \src "libresoc.v:187932.5-187932.29" switch \initial - attribute \src "libresoc.v:188184.9-188184.17" + attribute \src "libresoc.v:187932.9-187932.17" case 1'1 case end @@ -356023,10 +355729,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$12450 $1\data_r2__xer_ca$next[1:0]$12449 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12444 $1\data_r2__xer_ca$next[1:0]$12443 } { \xer_ca_ok \alu_shift_rot0_xer_ca } case - assign $1\data_r2__xer_ca$next[1:0]$12449 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$12450 \data_r2__xer_ca_ok + assign $1\data_r2__xer_ca$next[1:0]$12443 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12444 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -356034,32 +355740,32 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$12452 $2\data_r2__xer_ca$next[1:0]$12451 } 3'000 + assign { $2\data_r2__xer_ca_ok$next[0:0]$12446 $2\data_r2__xer_ca$next[1:0]$12445 } 3'000 case - assign $2\data_r2__xer_ca$next[1:0]$12451 $1\data_r2__xer_ca$next[1:0]$12449 - assign $2\data_r2__xer_ca_ok$next[0:0]$12452 $1\data_r2__xer_ca_ok$next[0:0]$12450 + assign $2\data_r2__xer_ca$next[1:0]$12445 $1\data_r2__xer_ca$next[1:0]$12443 + assign $2\data_r2__xer_ca_ok$next[0:0]$12446 $1\data_r2__xer_ca_ok$next[0:0]$12444 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$12453 1'0 + assign $3\data_r2__xer_ca_ok$next[0:0]$12447 1'0 case - assign $3\data_r2__xer_ca_ok$next[0:0]$12453 $2\data_r2__xer_ca_ok$next[0:0]$12452 + assign $3\data_r2__xer_ca_ok$next[0:0]$12447 $2\data_r2__xer_ca_ok$next[0:0]$12446 end sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12447 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12448 + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12441 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12442 end - attribute \src "libresoc.v:188205.3-188214.6" - process $proc$libresoc.v:188205$12454 + attribute \src "libresoc.v:187953.3-187962.6" + process $proc$libresoc.v:187953$12448 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12455 $1\src_r0$next[63:0]$12456 - attribute \src "libresoc.v:188206.5-188206.29" + assign $0\src_r0$next[63:0]$12449 $1\src_r0$next[63:0]$12450 + attribute \src "libresoc.v:187954.5-187954.29" switch \initial - attribute \src "libresoc.v:188206.9-188206.17" + attribute \src "libresoc.v:187954.9-187954.17" case 1'1 case end @@ -356068,21 +355774,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12456 \src1_i + assign $1\src_r0$next[63:0]$12450 \src1_i case - assign $1\src_r0$next[63:0]$12456 \src_r0 + assign $1\src_r0$next[63:0]$12450 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12455 + update \src_r0$next $0\src_r0$next[63:0]$12449 end - attribute \src "libresoc.v:188215.3-188224.6" - process $proc$libresoc.v:188215$12457 + attribute \src "libresoc.v:187963.3-187972.6" + process $proc$libresoc.v:187963$12451 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12458 $1\src_r1$next[63:0]$12459 - attribute \src "libresoc.v:188216.5-188216.29" + assign $0\src_r1$next[63:0]$12452 $1\src_r1$next[63:0]$12453 + attribute \src "libresoc.v:187964.5-187964.29" switch \initial - attribute \src "libresoc.v:188216.9-188216.17" + attribute \src "libresoc.v:187964.9-187964.17" case 1'1 case end @@ -356091,21 +355797,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12459 \src_or_imm + assign $1\src_r1$next[63:0]$12453 \src_or_imm case - assign $1\src_r1$next[63:0]$12459 \src_r1 + assign $1\src_r1$next[63:0]$12453 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12458 + update \src_r1$next $0\src_r1$next[63:0]$12452 end - attribute \src "libresoc.v:188225.3-188234.6" - process $proc$libresoc.v:188225$12460 + attribute \src "libresoc.v:187973.3-187982.6" + process $proc$libresoc.v:187973$12454 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12461 $1\src_r2$next[63:0]$12462 - attribute \src "libresoc.v:188226.5-188226.29" + assign $0\src_r2$next[63:0]$12455 $1\src_r2$next[63:0]$12456 + attribute \src "libresoc.v:187974.5-187974.29" switch \initial - attribute \src "libresoc.v:188226.9-188226.17" + attribute \src "libresoc.v:187974.9-187974.17" case 1'1 case end @@ -356114,21 +355820,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12462 \src3_i + assign $1\src_r2$next[63:0]$12456 \src3_i case - assign $1\src_r2$next[63:0]$12462 \src_r2 + assign $1\src_r2$next[63:0]$12456 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12461 + update \src_r2$next $0\src_r2$next[63:0]$12455 end - attribute \src "libresoc.v:188235.3-188244.6" - process $proc$libresoc.v:188235$12463 + attribute \src "libresoc.v:187983.3-187992.6" + process $proc$libresoc.v:187983$12457 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12464 $1\src_r3$next[0:0]$12465 - attribute \src "libresoc.v:188236.5-188236.29" + assign $0\src_r3$next[0:0]$12458 $1\src_r3$next[0:0]$12459 + attribute \src "libresoc.v:187984.5-187984.29" switch \initial - attribute \src "libresoc.v:188236.9-188236.17" + attribute \src "libresoc.v:187984.9-187984.17" case 1'1 case end @@ -356137,21 +355843,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12465 \src4_i + assign $1\src_r3$next[0:0]$12459 \src4_i case - assign $1\src_r3$next[0:0]$12465 \src_r3 + assign $1\src_r3$next[0:0]$12459 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12464 + update \src_r3$next $0\src_r3$next[0:0]$12458 end - attribute \src "libresoc.v:188245.3-188254.6" - process $proc$libresoc.v:188245$12466 + attribute \src "libresoc.v:187993.3-188002.6" + process $proc$libresoc.v:187993$12460 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12467 $1\src_r4$next[1:0]$12468 - attribute \src "libresoc.v:188246.5-188246.29" + assign $0\src_r4$next[1:0]$12461 $1\src_r4$next[1:0]$12462 + attribute \src "libresoc.v:187994.5-187994.29" switch \initial - attribute \src "libresoc.v:188246.9-188246.17" + attribute \src "libresoc.v:187994.9-187994.17" case 1'1 case end @@ -356160,21 +355866,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12468 \src5_i + assign $1\src_r4$next[1:0]$12462 \src5_i case - assign $1\src_r4$next[1:0]$12468 \src_r4 + assign $1\src_r4$next[1:0]$12462 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12467 + update \src_r4$next $0\src_r4$next[1:0]$12461 end - attribute \src "libresoc.v:188255.3-188263.6" - process $proc$libresoc.v:188255$12469 + attribute \src "libresoc.v:188003.3-188011.6" + process $proc$libresoc.v:188003$12463 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12470 $1\alui_l_r_alui$next[0:0]$12471 - attribute \src "libresoc.v:188256.5-188256.29" + assign $0\alui_l_r_alui$next[0:0]$12464 $1\alui_l_r_alui$next[0:0]$12465 + attribute \src "libresoc.v:188004.5-188004.29" switch \initial - attribute \src "libresoc.v:188256.9-188256.17" + attribute \src "libresoc.v:188004.9-188004.17" case 1'1 case end @@ -356183,21 +355889,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12471 1'1 + assign $1\alui_l_r_alui$next[0:0]$12465 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12471 \$90 + assign $1\alui_l_r_alui$next[0:0]$12465 \$90 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12470 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12464 end - attribute \src "libresoc.v:188264.3-188272.6" - process $proc$libresoc.v:188264$12472 + attribute \src "libresoc.v:188012.3-188020.6" + process $proc$libresoc.v:188012$12466 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12473 $1\alu_l_r_alu$next[0:0]$12474 - attribute \src "libresoc.v:188265.5-188265.29" + assign $0\alu_l_r_alu$next[0:0]$12467 $1\alu_l_r_alu$next[0:0]$12468 + attribute \src "libresoc.v:188013.5-188013.29" switch \initial - attribute \src "libresoc.v:188265.9-188265.17" + attribute \src "libresoc.v:188013.9-188013.17" case 1'1 case end @@ -356206,21 +355912,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12474 1'1 + assign $1\alu_l_r_alu$next[0:0]$12468 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12474 \$92 + assign $1\alu_l_r_alu$next[0:0]$12468 \$92 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12473 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12467 end - attribute \src "libresoc.v:188273.3-188282.6" - process $proc$libresoc.v:188273$12475 + attribute \src "libresoc.v:188021.3-188030.6" + process $proc$libresoc.v:188021$12469 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:188274.5-188274.29" + attribute \src "libresoc.v:188022.5-188022.29" switch \initial - attribute \src "libresoc.v:188274.9-188274.17" + attribute \src "libresoc.v:188022.9-188022.17" case 1'1 case end @@ -356236,14 +355942,14 @@ module \shiftrot0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:188283.3-188292.6" - process $proc$libresoc.v:188283$12476 + attribute \src "libresoc.v:188031.3-188040.6" + process $proc$libresoc.v:188031$12470 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:188284.5-188284.29" + attribute \src "libresoc.v:188032.5-188032.29" switch \initial - attribute \src "libresoc.v:188284.9-188284.17" + attribute \src "libresoc.v:188032.9-188032.17" case 1'1 case end @@ -356259,14 +355965,14 @@ module \shiftrot0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:188293.3-188302.6" - process $proc$libresoc.v:188293$12477 + attribute \src "libresoc.v:188041.3-188050.6" + process $proc$libresoc.v:188041$12471 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:188294.5-188294.29" + attribute \src "libresoc.v:188042.5-188042.29" switch \initial - attribute \src "libresoc.v:188294.9-188294.17" + attribute \src "libresoc.v:188042.9-188042.17" case 1'1 case end @@ -356282,14 +355988,14 @@ module \shiftrot0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:188303.3-188311.6" - process $proc$libresoc.v:188303$12478 + attribute \src "libresoc.v:188051.3-188059.6" + process $proc$libresoc.v:188051$12472 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$12479 $1\prev_wr_go$next[2:0]$12480 - attribute \src "libresoc.v:188304.5-188304.29" + assign $0\prev_wr_go$next[2:0]$12473 $1\prev_wr_go$next[2:0]$12474 + attribute \src "libresoc.v:188052.5-188052.29" switch \initial - attribute \src "libresoc.v:188304.9-188304.17" + attribute \src "libresoc.v:188052.9-188052.17" case 1'1 case end @@ -356298,72 +356004,72 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$12480 3'000 - case - assign $1\prev_wr_go$next[2:0]$12480 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12479 - end - connect \$100 $not$libresoc.v:187772$12256_Y - connect \$102 $and$libresoc.v:187773$12257_Y - connect \$104 $and$libresoc.v:187774$12258_Y - connect \$106 $and$libresoc.v:187775$12259_Y - connect \$108 $and$libresoc.v:187776$12260_Y - connect \$10 $and$libresoc.v:187777$12261_Y - connect \$110 $and$libresoc.v:187778$12262_Y - connect \$112 $and$libresoc.v:187779$12263_Y - connect \$114 $and$libresoc.v:187780$12264_Y - connect \$116 $and$libresoc.v:187781$12265_Y - connect \$118 $and$libresoc.v:187782$12266_Y - connect \$12 $not$libresoc.v:187783$12267_Y - connect \$14 $and$libresoc.v:187784$12268_Y - connect \$16 $not$libresoc.v:187785$12269_Y - connect \$18 $and$libresoc.v:187786$12270_Y - connect \$20 $and$libresoc.v:187787$12271_Y - connect \$24 $not$libresoc.v:187788$12272_Y - connect \$26 $and$libresoc.v:187789$12273_Y - connect \$23 $reduce_or$libresoc.v:187790$12274_Y - connect \$22 $not$libresoc.v:187791$12275_Y - connect \$2 $and$libresoc.v:187792$12276_Y - connect \$30 $and$libresoc.v:187793$12277_Y - connect \$32 $reduce_or$libresoc.v:187794$12278_Y - connect \$34 $reduce_or$libresoc.v:187795$12279_Y - connect \$36 $or$libresoc.v:187796$12280_Y - connect \$38 $not$libresoc.v:187797$12281_Y - connect \$40 $and$libresoc.v:187798$12282_Y - connect \$42 $and$libresoc.v:187799$12283_Y - connect \$44 $eq$libresoc.v:187800$12284_Y - connect \$46 $and$libresoc.v:187801$12285_Y - connect \$48 $eq$libresoc.v:187802$12286_Y - connect \$50 $and$libresoc.v:187803$12287_Y - connect \$52 $and$libresoc.v:187804$12288_Y - connect \$54 $and$libresoc.v:187805$12289_Y - connect \$56 $or$libresoc.v:187806$12290_Y - connect \$58 $or$libresoc.v:187807$12291_Y - connect \$5 $not$libresoc.v:187808$12292_Y - connect \$60 $or$libresoc.v:187809$12293_Y - connect \$62 $or$libresoc.v:187810$12294_Y - connect \$64 $and$libresoc.v:187811$12295_Y - connect \$66 $and$libresoc.v:187812$12296_Y - connect \$68 $or$libresoc.v:187813$12297_Y - connect \$70 $and$libresoc.v:187814$12298_Y - connect \$72 $and$libresoc.v:187815$12299_Y - connect \$74 $and$libresoc.v:187816$12300_Y - connect \$76 $ternary$libresoc.v:187817$12301_Y - connect \$78 $ternary$libresoc.v:187818$12302_Y - connect \$7 $or$libresoc.v:187819$12303_Y - connect \$80 $ternary$libresoc.v:187820$12304_Y - connect \$82 $ternary$libresoc.v:187821$12305_Y - connect \$84 $ternary$libresoc.v:187822$12306_Y - connect \$86 $ternary$libresoc.v:187823$12307_Y - connect \$88 $ternary$libresoc.v:187824$12308_Y - connect \$4 $reduce_and$libresoc.v:187825$12309_Y - connect \$90 $and$libresoc.v:187826$12310_Y - connect \$92 $and$libresoc.v:187827$12311_Y - connect \$94 $and$libresoc.v:187828$12312_Y - connect \$96 $not$libresoc.v:187829$12313_Y - connect \$98 $and$libresoc.v:187830$12314_Y + assign $1\prev_wr_go$next[2:0]$12474 3'000 + case + assign $1\prev_wr_go$next[2:0]$12474 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12473 + end + connect \$100 $not$libresoc.v:187520$12250_Y + connect \$102 $and$libresoc.v:187521$12251_Y + connect \$104 $and$libresoc.v:187522$12252_Y + connect \$106 $and$libresoc.v:187523$12253_Y + connect \$108 $and$libresoc.v:187524$12254_Y + connect \$10 $and$libresoc.v:187525$12255_Y + connect \$110 $and$libresoc.v:187526$12256_Y + connect \$112 $and$libresoc.v:187527$12257_Y + connect \$114 $and$libresoc.v:187528$12258_Y + connect \$116 $and$libresoc.v:187529$12259_Y + connect \$118 $and$libresoc.v:187530$12260_Y + connect \$12 $not$libresoc.v:187531$12261_Y + connect \$14 $and$libresoc.v:187532$12262_Y + connect \$16 $not$libresoc.v:187533$12263_Y + connect \$18 $and$libresoc.v:187534$12264_Y + connect \$20 $and$libresoc.v:187535$12265_Y + connect \$24 $not$libresoc.v:187536$12266_Y + connect \$26 $and$libresoc.v:187537$12267_Y + connect \$23 $reduce_or$libresoc.v:187538$12268_Y + connect \$22 $not$libresoc.v:187539$12269_Y + connect \$2 $and$libresoc.v:187540$12270_Y + connect \$30 $and$libresoc.v:187541$12271_Y + connect \$32 $reduce_or$libresoc.v:187542$12272_Y + connect \$34 $reduce_or$libresoc.v:187543$12273_Y + connect \$36 $or$libresoc.v:187544$12274_Y + connect \$38 $not$libresoc.v:187545$12275_Y + connect \$40 $and$libresoc.v:187546$12276_Y + connect \$42 $and$libresoc.v:187547$12277_Y + connect \$44 $eq$libresoc.v:187548$12278_Y + connect \$46 $and$libresoc.v:187549$12279_Y + connect \$48 $eq$libresoc.v:187550$12280_Y + connect \$50 $and$libresoc.v:187551$12281_Y + connect \$52 $and$libresoc.v:187552$12282_Y + connect \$54 $and$libresoc.v:187553$12283_Y + connect \$56 $or$libresoc.v:187554$12284_Y + connect \$58 $or$libresoc.v:187555$12285_Y + connect \$5 $not$libresoc.v:187556$12286_Y + connect \$60 $or$libresoc.v:187557$12287_Y + connect \$62 $or$libresoc.v:187558$12288_Y + connect \$64 $and$libresoc.v:187559$12289_Y + connect \$66 $and$libresoc.v:187560$12290_Y + connect \$68 $or$libresoc.v:187561$12291_Y + connect \$70 $and$libresoc.v:187562$12292_Y + connect \$72 $and$libresoc.v:187563$12293_Y + connect \$74 $and$libresoc.v:187564$12294_Y + connect \$76 $ternary$libresoc.v:187565$12295_Y + connect \$78 $ternary$libresoc.v:187566$12296_Y + connect \$7 $or$libresoc.v:187567$12297_Y + connect \$80 $ternary$libresoc.v:187568$12298_Y + connect \$82 $ternary$libresoc.v:187569$12299_Y + connect \$84 $ternary$libresoc.v:187570$12300_Y + connect \$86 $ternary$libresoc.v:187571$12301_Y + connect \$88 $ternary$libresoc.v:187572$12302_Y + connect \$4 $reduce_and$libresoc.v:187573$12303_Y + connect \$90 $and$libresoc.v:187574$12304_Y + connect \$92 $and$libresoc.v:187575$12305_Y + connect \$94 $and$libresoc.v:187576$12306_Y + connect \$96 $not$libresoc.v:187577$12307_Y + connect \$98 $and$libresoc.v:187578$12308_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -356397,54 +356103,54 @@ module \shiftrot0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:188348.1-188424.10" +attribute \src "libresoc.v:188096.1-188174.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.spr" attribute \generator "nMigen" module \spr - attribute \src "libresoc.v:188394.3-188397.6" - wire width 4 $0$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12536 - attribute \src "libresoc.v:188394.3-188397.6" - wire width 64 $0$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12537 - attribute \src "libresoc.v:188394.3-188397.6" - wire width 64 $0$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12538 - attribute \src "libresoc.v:188394.3-188397.6" + attribute \src "libresoc.v:188144.3-188147.6" + wire width 4 $0$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12532 + attribute \src "libresoc.v:188144.3-188147.6" + wire width 64 $0$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12533 + attribute \src "libresoc.v:188144.3-188147.6" + wire width 64 $0$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12534 + attribute \src "libresoc.v:188144.3-188147.6" wire width 4 $0\_0_[3:0] - attribute \src "libresoc.v:188349.7-188349.20" + attribute \src "libresoc.v:188097.7-188097.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188401.3-188409.6" - wire $0\ren_delay$next[0:0]$12545 - attribute \src "libresoc.v:188399.3-188400.35" + attribute \src "libresoc.v:188151.3-188159.6" + wire $0\ren_delay$next[0:0]$12541 + attribute \src "libresoc.v:188149.3-188150.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:188410.3-188419.6" + attribute \src "libresoc.v:188160.3-188169.6" wire width 64 $0\spr1__data_o[63:0] - attribute \src "libresoc.v:188394.3-188397.6" - wire width 4 $1$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12539 - attribute \src "libresoc.v:188394.3-188397.6" - wire width 64 $1$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12540 - attribute \src "libresoc.v:188394.3-188397.6" - wire width 64 $1$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12541 - attribute \src "libresoc.v:188401.3-188409.6" - wire $1\ren_delay$next[0:0]$12546 - attribute \src "libresoc.v:188365.7-188365.23" + attribute \src "libresoc.v:188144.3-188147.6" + wire width 4 $1$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12535 + attribute \src "libresoc.v:188144.3-188147.6" + wire width 64 $1$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12536 + attribute \src "libresoc.v:188144.3-188147.6" + wire width 64 $1$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12537 + attribute \src "libresoc.v:188151.3-188159.6" + wire $1\ren_delay$next[0:0]$12542 + attribute \src "libresoc.v:188113.7-188113.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:188410.3-188419.6" + attribute \src "libresoc.v:188160.3-188169.6" wire width 64 $1\spr1__data_o[63:0] - attribute \src "libresoc.v:188398.26-188398.32" - wire width 64 $memrd$\memory$libresoc.v:188398$12542_DATA + attribute \src "libresoc.v:188148.26-188148.32" + wire width 64 $memrd$\memory$libresoc.v:188148$12538_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 4 $memwr$\memory$libresoc.v:188396$12534_ADDR + wire width 4 $memwr$\memory$libresoc.v:188146$12530_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:188396$12534_DATA + wire width 64 $memwr$\memory$libresoc.v:188146$12530_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:188396$12534_EN - attribute \src "libresoc.v:188393.13-188393.16" + wire width 64 $memwr$\memory$libresoc.v:188146$12530_EN + attribute \src "libresoc.v:188143.13-188143.16" wire width 4 \_0_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 8 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:188349.7-188349.15" + attribute \src "libresoc.v:188097.7-188097.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 4 \memory_r_addr @@ -356472,100 +356178,120 @@ module \spr wire input 4 \spr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \spr1__wen - attribute \src "libresoc.v:188381.14-188381.20" - memory width 64 size 9 \memory - attribute \src "libresoc.v:188383.5-188383.37" - cell $meminit $meminit$\memory$libresoc.v:188383$12548 + attribute \src "libresoc.v:188129.14-188129.20" + memory width 64 size 11 \memory + attribute \src "libresoc.v:188131.5-188131.37" + cell $meminit $meminit$\memory$libresoc.v:188131$12544 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12548 + parameter \PRIORITY 12544 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:188384.5-188384.37" - cell $meminit $meminit$\memory$libresoc.v:188384$12549 + attribute \src "libresoc.v:188132.5-188132.37" + cell $meminit $meminit$\memory$libresoc.v:188132$12545 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12549 + parameter \PRIORITY 12545 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:188385.5-188385.37" - cell $meminit $meminit$\memory$libresoc.v:188385$12550 + attribute \src "libresoc.v:188133.5-188133.37" + cell $meminit $meminit$\memory$libresoc.v:188133$12546 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12550 + parameter \PRIORITY 12546 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:188386.5-188386.37" - cell $meminit $meminit$\memory$libresoc.v:188386$12551 + attribute \src "libresoc.v:188134.5-188134.37" + cell $meminit $meminit$\memory$libresoc.v:188134$12547 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12551 + parameter \PRIORITY 12547 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:188387.5-188387.37" - cell $meminit $meminit$\memory$libresoc.v:188387$12552 + attribute \src "libresoc.v:188135.5-188135.37" + cell $meminit $meminit$\memory$libresoc.v:188135$12548 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12552 + parameter \PRIORITY 12548 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:188388.5-188388.37" - cell $meminit $meminit$\memory$libresoc.v:188388$12553 + attribute \src "libresoc.v:188136.5-188136.37" + cell $meminit $meminit$\memory$libresoc.v:188136$12549 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12553 + parameter \PRIORITY 12549 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:188389.5-188389.37" - cell $meminit $meminit$\memory$libresoc.v:188389$12554 + attribute \src "libresoc.v:188137.5-188137.37" + cell $meminit $meminit$\memory$libresoc.v:188137$12550 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12554 + parameter \PRIORITY 12550 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:188390.5-188390.37" - cell $meminit $meminit$\memory$libresoc.v:188390$12555 + attribute \src "libresoc.v:188138.5-188138.37" + cell $meminit $meminit$\memory$libresoc.v:188138$12551 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12555 + parameter \PRIORITY 12551 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:188391.5-188391.37" - cell $meminit $meminit$\memory$libresoc.v:188391$12556 + attribute \src "libresoc.v:188139.5-188139.37" + cell $meminit $meminit$\memory$libresoc.v:188139$12552 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12556 + parameter \PRIORITY 12552 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:188398.26-188398.32" - cell $memrd $memrd$\memory$libresoc.v:188398$12542 + attribute \src "libresoc.v:188140.5-188140.37" + cell $meminit $meminit$\memory$libresoc.v:188140$12553 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12553 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 9 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:188141.5-188141.38" + cell $meminit $meminit$\memory$libresoc.v:188141$12554 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12554 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 10 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:188148.26-188148.32" + cell $memrd $memrd$\memory$libresoc.v:188148$12538 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -356574,32 +356300,32 @@ module \spr parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:188398$12542_DATA + connect \DATA $memrd$\memory$libresoc.v:188148$12538_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$12559 + process $proc$libresoc.v:0$12557 sync always sync init end - attribute \src "libresoc.v:188349.7-188349.20" - process $proc$libresoc.v:188349$12557 + attribute \src "libresoc.v:188097.7-188097.20" + process $proc$libresoc.v:188097$12555 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188365.7-188365.23" - process $proc$libresoc.v:188365$12558 + attribute \src "libresoc.v:188113.7-188113.23" + process $proc$libresoc.v:188113$12556 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:188394.3-188397.6" - process $proc$libresoc.v:188394$12535 + attribute \src "libresoc.v:188144.3-188147.6" + process $proc$libresoc.v:188144$12531 assign { } { } assign { } { } assign { } { } @@ -356608,47 +356334,47 @@ module \spr assign { } { } assign { } { } assign $0\_0_[3:0] \memory_r_addr - assign $0$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12536 $1$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12539 - assign $0$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12537 $1$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12540 - assign $0$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12538 $1$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12541 - attribute \src "libresoc.v:188396.5-188396.61" + assign $0$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12532 $1$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12535 + assign $0$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12533 $1$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12536 + assign $0$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12534 $1$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12537 + attribute \src "libresoc.v:188146.5-188146.61" switch \memory_w_en - attribute \src "libresoc.v:188396.9-188396.20" + attribute \src "libresoc.v:188146.9-188146.20" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12539 \memory_w_addr - assign $1$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12540 \memory_w_data - assign $1$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12541 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $1$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12535 \memory_w_addr + assign $1$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12536 \memory_w_data + assign $1$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12537 64'1111111111111111111111111111111111111111111111111111111111111111 case - assign $1$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12539 4'xxxx - assign $1$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12540 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $1$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12541 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12535 4'xxxx + assign $1$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12536 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12537 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \coresync_clk update \_0_ $0\_0_[3:0] - update $memwr$\memory$libresoc.v:188396$12534_ADDR $0$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12536 - update $memwr$\memory$libresoc.v:188396$12534_DATA $0$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12537 - update $memwr$\memory$libresoc.v:188396$12534_EN $0$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12538 - attribute \src "libresoc.v:188396.22-188396.60" - memwr \memory $1$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12539 $1$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12540 $1$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12541 0' + update $memwr$\memory$libresoc.v:188146$12530_ADDR $0$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12532 + update $memwr$\memory$libresoc.v:188146$12530_DATA $0$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12533 + update $memwr$\memory$libresoc.v:188146$12530_EN $0$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12534 + attribute \src "libresoc.v:188146.22-188146.60" + memwr \memory $1$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12535 $1$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12536 $1$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12537 0' end - attribute \src "libresoc.v:188399.3-188400.35" - process $proc$libresoc.v:188399$12543 + attribute \src "libresoc.v:188149.3-188150.35" + process $proc$libresoc.v:188149$12539 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:188401.3-188409.6" - process $proc$libresoc.v:188401$12544 + attribute \src "libresoc.v:188151.3-188159.6" + process $proc$libresoc.v:188151$12540 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$12545 $1\ren_delay$next[0:0]$12546 - attribute \src "libresoc.v:188402.5-188402.29" + assign $0\ren_delay$next[0:0]$12541 $1\ren_delay$next[0:0]$12542 + attribute \src "libresoc.v:188152.5-188152.29" switch \initial - attribute \src "libresoc.v:188402.9-188402.17" + attribute \src "libresoc.v:188152.9-188152.17" case 1'1 case end @@ -356657,21 +356383,21 @@ module \spr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$12546 1'0 + assign $1\ren_delay$next[0:0]$12542 1'0 case - assign $1\ren_delay$next[0:0]$12546 \spr1__ren + assign $1\ren_delay$next[0:0]$12542 \spr1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$12545 + update \ren_delay$next $0\ren_delay$next[0:0]$12541 end - attribute \src "libresoc.v:188410.3-188419.6" - process $proc$libresoc.v:188410$12547 + attribute \src "libresoc.v:188160.3-188169.6" + process $proc$libresoc.v:188160$12543 assign { } { } assign { } { } assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "libresoc.v:188411.5-188411.29" + attribute \src "libresoc.v:188161.5-188161.29" switch \initial - attribute \src "libresoc.v:188411.9-188411.17" + attribute \src "libresoc.v:188161.9-188161.17" case 1'1 case end @@ -356687,503 +356413,503 @@ module \spr sync always update \spr1__data_o $0\spr1__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:188398$12542_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:188148$12538_DATA connect \memory_w_data \spr1__data_i connect \memory_w_en \spr1__wen connect \memory_w_addr \spr1__addr$1 connect \memory_r_addr \spr1__addr end -attribute \src "libresoc.v:188428.1-189681.10" +attribute \src "libresoc.v:188178.1-189431.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" attribute \generator "nMigen" module \spr0 - attribute \src "libresoc.v:189178.3-189179.25" + attribute \src "libresoc.v:188928.3-188929.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:189176.3-189177.40" + attribute \src "libresoc.v:188926.3-188927.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:189572.3-189580.6" - wire $0\alu_l_r_alu$next[0:0]$12773 - attribute \src "libresoc.v:189106.3-189107.39" + attribute \src "libresoc.v:189322.3-189330.6" + wire $0\alu_l_r_alu$next[0:0]$12771 + attribute \src "libresoc.v:188856.3-188857.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:189358.3-189370.6" - wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$12695 - attribute \src "libresoc.v:189148.3-189149.65" + attribute \src "libresoc.v:189108.3-189120.6" + wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$12693 + attribute \src "libresoc.v:188898.3-188899.65" wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:189358.3-189370.6" - wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12696 - attribute \src "libresoc.v:189150.3-189151.59" + attribute \src "libresoc.v:189108.3-189120.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12694 + attribute \src "libresoc.v:188900.3-188901.59" wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:189358.3-189370.6" - wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12697 - attribute \src "libresoc.v:189146.3-189147.69" + attribute \src "libresoc.v:189108.3-189120.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12695 + attribute \src "libresoc.v:188896.3-188897.69" wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:189358.3-189370.6" - wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12698 - attribute \src "libresoc.v:189152.3-189153.67" + attribute \src "libresoc.v:189108.3-189120.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12696 + attribute \src "libresoc.v:188902.3-188903.67" wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:189563.3-189571.6" - wire $0\alui_l_r_alui$next[0:0]$12770 - attribute \src "libresoc.v:189108.3-189109.43" + attribute \src "libresoc.v:189313.3-189321.6" + wire $0\alui_l_r_alui$next[0:0]$12768 + attribute \src "libresoc.v:188858.3-188859.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:189371.3-189392.6" - wire width 64 $0\data_r0__o$next[63:0]$12704 - attribute \src "libresoc.v:189142.3-189143.37" + attribute \src "libresoc.v:189121.3-189142.6" + wire width 64 $0\data_r0__o$next[63:0]$12702 + attribute \src "libresoc.v:188892.3-188893.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:189371.3-189392.6" - wire $0\data_r0__o_ok$next[0:0]$12705 - attribute \src "libresoc.v:189144.3-189145.43" + attribute \src "libresoc.v:189121.3-189142.6" + wire $0\data_r0__o_ok$next[0:0]$12703 + attribute \src "libresoc.v:188894.3-188895.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:189393.3-189414.6" - wire width 64 $0\data_r1__spr1$next[63:0]$12712 - attribute \src "libresoc.v:189138.3-189139.43" + attribute \src "libresoc.v:189143.3-189164.6" + wire width 64 $0\data_r1__spr1$next[63:0]$12710 + attribute \src "libresoc.v:188888.3-188889.43" wire width 64 $0\data_r1__spr1[63:0] - attribute \src "libresoc.v:189393.3-189414.6" - wire $0\data_r1__spr1_ok$next[0:0]$12713 - attribute \src "libresoc.v:189140.3-189141.49" + attribute \src "libresoc.v:189143.3-189164.6" + wire $0\data_r1__spr1_ok$next[0:0]$12711 + attribute \src "libresoc.v:188890.3-188891.49" wire $0\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:189415.3-189436.6" - wire width 64 $0\data_r2__fast1$next[63:0]$12720 - attribute \src "libresoc.v:189134.3-189135.45" + attribute \src "libresoc.v:189165.3-189186.6" + wire width 64 $0\data_r2__fast1$next[63:0]$12718 + attribute \src "libresoc.v:188884.3-188885.45" wire width 64 $0\data_r2__fast1[63:0] - attribute \src "libresoc.v:189415.3-189436.6" - wire $0\data_r2__fast1_ok$next[0:0]$12721 - attribute \src "libresoc.v:189136.3-189137.51" + attribute \src "libresoc.v:189165.3-189186.6" + wire $0\data_r2__fast1_ok$next[0:0]$12719 + attribute \src "libresoc.v:188886.3-188887.51" wire $0\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:189437.3-189458.6" - wire $0\data_r3__xer_so$next[0:0]$12728 - attribute \src "libresoc.v:189130.3-189131.47" + attribute \src "libresoc.v:189187.3-189208.6" + wire $0\data_r3__xer_so$next[0:0]$12726 + attribute \src "libresoc.v:188880.3-188881.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:189437.3-189458.6" - wire $0\data_r3__xer_so_ok$next[0:0]$12729 - attribute \src "libresoc.v:189132.3-189133.53" + attribute \src "libresoc.v:189187.3-189208.6" + wire $0\data_r3__xer_so_ok$next[0:0]$12727 + attribute \src "libresoc.v:188882.3-188883.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:189459.3-189480.6" - wire width 2 $0\data_r4__xer_ov$next[1:0]$12736 - attribute \src "libresoc.v:189126.3-189127.47" + attribute \src "libresoc.v:189209.3-189230.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$12734 + attribute \src "libresoc.v:188876.3-188877.47" wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:189459.3-189480.6" - wire $0\data_r4__xer_ov_ok$next[0:0]$12737 - attribute \src "libresoc.v:189128.3-189129.53" + attribute \src "libresoc.v:189209.3-189230.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$12735 + attribute \src "libresoc.v:188878.3-188879.53" wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:189481.3-189502.6" - wire width 2 $0\data_r5__xer_ca$next[1:0]$12744 - attribute \src "libresoc.v:189122.3-189123.47" + attribute \src "libresoc.v:189231.3-189252.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$12742 + attribute \src "libresoc.v:188872.3-188873.47" wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:189481.3-189502.6" - wire $0\data_r5__xer_ca_ok$next[0:0]$12745 - attribute \src "libresoc.v:189124.3-189125.53" + attribute \src "libresoc.v:189231.3-189252.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$12743 + attribute \src "libresoc.v:188874.3-188875.53" wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:189581.3-189590.6" + attribute \src "libresoc.v:189331.3-189340.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:189591.3-189600.6" + attribute \src "libresoc.v:189341.3-189350.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:189601.3-189610.6" + attribute \src "libresoc.v:189351.3-189360.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:189611.3-189620.6" + attribute \src "libresoc.v:189361.3-189370.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:189621.3-189630.6" + attribute \src "libresoc.v:189371.3-189380.6" wire width 2 $0\dest5_o[1:0] - attribute \src "libresoc.v:189631.3-189640.6" + attribute \src "libresoc.v:189381.3-189390.6" wire width 2 $0\dest6_o[1:0] - attribute \src "libresoc.v:188429.7-188429.20" + attribute \src "libresoc.v:188179.7-188179.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189313.3-189321.6" - wire $0\opc_l_r_opc$next[0:0]$12680 - attribute \src "libresoc.v:189162.3-189163.39" + attribute \src "libresoc.v:189063.3-189071.6" + wire $0\opc_l_r_opc$next[0:0]$12678 + attribute \src "libresoc.v:188912.3-188913.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:189304.3-189312.6" - wire $0\opc_l_s_opc$next[0:0]$12677 - attribute \src "libresoc.v:189164.3-189165.39" + attribute \src "libresoc.v:189054.3-189062.6" + wire $0\opc_l_s_opc$next[0:0]$12675 + attribute \src "libresoc.v:188914.3-188915.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:189641.3-189649.6" - wire width 6 $0\prev_wr_go$next[5:0]$12782 - attribute \src "libresoc.v:189174.3-189175.37" + attribute \src "libresoc.v:189391.3-189399.6" + wire width 6 $0\prev_wr_go$next[5:0]$12780 + attribute \src "libresoc.v:188924.3-188925.37" wire width 6 $0\prev_wr_go[5:0] - attribute \src "libresoc.v:189258.3-189267.6" + attribute \src "libresoc.v:189008.3-189017.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:189349.3-189357.6" - wire width 6 $0\req_l_r_req$next[5:0]$12692 - attribute \src "libresoc.v:189154.3-189155.39" + attribute \src "libresoc.v:189099.3-189107.6" + wire width 6 $0\req_l_r_req$next[5:0]$12690 + attribute \src "libresoc.v:188904.3-188905.39" wire width 6 $0\req_l_r_req[5:0] - attribute \src "libresoc.v:189340.3-189348.6" - wire width 6 $0\req_l_s_req$next[5:0]$12689 - attribute \src "libresoc.v:189156.3-189157.39" + attribute \src "libresoc.v:189090.3-189098.6" + wire width 6 $0\req_l_s_req$next[5:0]$12687 + attribute \src "libresoc.v:188906.3-188907.39" wire width 6 $0\req_l_s_req[5:0] - attribute \src "libresoc.v:189277.3-189285.6" - wire $0\rok_l_r_rdok$next[0:0]$12668 - attribute \src "libresoc.v:189170.3-189171.41" + attribute \src "libresoc.v:189027.3-189035.6" + wire $0\rok_l_r_rdok$next[0:0]$12666 + attribute \src "libresoc.v:188920.3-188921.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:189268.3-189276.6" - wire $0\rok_l_s_rdok$next[0:0]$12665 - attribute \src "libresoc.v:189172.3-189173.41" + attribute \src "libresoc.v:189018.3-189026.6" + wire $0\rok_l_s_rdok$next[0:0]$12663 + attribute \src "libresoc.v:188922.3-188923.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:189295.3-189303.6" - wire $0\rst_l_r_rst$next[0:0]$12674 - attribute \src "libresoc.v:189166.3-189167.39" + attribute \src "libresoc.v:189045.3-189053.6" + wire $0\rst_l_r_rst$next[0:0]$12672 + attribute \src "libresoc.v:188916.3-188917.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:189286.3-189294.6" - wire $0\rst_l_s_rst$next[0:0]$12671 - attribute \src "libresoc.v:189168.3-189169.39" + attribute \src "libresoc.v:189036.3-189044.6" + wire $0\rst_l_s_rst$next[0:0]$12669 + attribute \src "libresoc.v:188918.3-188919.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:189331.3-189339.6" - wire width 6 $0\src_l_r_src$next[5:0]$12686 - attribute \src "libresoc.v:189158.3-189159.39" + attribute \src "libresoc.v:189081.3-189089.6" + wire width 6 $0\src_l_r_src$next[5:0]$12684 + attribute \src "libresoc.v:188908.3-188909.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:189322.3-189330.6" - wire width 6 $0\src_l_s_src$next[5:0]$12683 - attribute \src "libresoc.v:189160.3-189161.39" + attribute \src "libresoc.v:189072.3-189080.6" + wire width 6 $0\src_l_s_src$next[5:0]$12681 + attribute \src "libresoc.v:188910.3-188911.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:189503.3-189512.6" - wire width 64 $0\src_r0$next[63:0]$12752 - attribute \src "libresoc.v:189120.3-189121.29" + attribute \src "libresoc.v:189253.3-189262.6" + wire width 64 $0\src_r0$next[63:0]$12750 + attribute \src "libresoc.v:188870.3-188871.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:189513.3-189522.6" - wire width 64 $0\src_r1$next[63:0]$12755 - attribute \src "libresoc.v:189118.3-189119.29" + attribute \src "libresoc.v:189263.3-189272.6" + wire width 64 $0\src_r1$next[63:0]$12753 + attribute \src "libresoc.v:188868.3-188869.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:189523.3-189532.6" - wire width 64 $0\src_r2$next[63:0]$12758 - attribute \src "libresoc.v:189116.3-189117.29" + attribute \src "libresoc.v:189273.3-189282.6" + wire width 64 $0\src_r2$next[63:0]$12756 + attribute \src "libresoc.v:188866.3-188867.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:189533.3-189542.6" - wire $0\src_r3$next[0:0]$12761 - attribute \src "libresoc.v:189114.3-189115.29" + attribute \src "libresoc.v:189283.3-189292.6" + wire $0\src_r3$next[0:0]$12759 + attribute \src "libresoc.v:188864.3-188865.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:189543.3-189552.6" - wire width 2 $0\src_r4$next[1:0]$12764 - attribute \src "libresoc.v:189112.3-189113.29" + attribute \src "libresoc.v:189293.3-189302.6" + wire width 2 $0\src_r4$next[1:0]$12762 + attribute \src "libresoc.v:188862.3-188863.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:189553.3-189562.6" - wire width 2 $0\src_r5$next[1:0]$12767 - attribute \src "libresoc.v:189110.3-189111.29" + attribute \src "libresoc.v:189303.3-189312.6" + wire width 2 $0\src_r5$next[1:0]$12765 + attribute \src "libresoc.v:188860.3-188861.29" wire width 2 $0\src_r5[1:0] - attribute \src "libresoc.v:188565.7-188565.24" + attribute \src "libresoc.v:188315.7-188315.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:188575.7-188575.26" + attribute \src "libresoc.v:188325.7-188325.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:189572.3-189580.6" - wire $1\alu_l_r_alu$next[0:0]$12774 - attribute \src "libresoc.v:188583.7-188583.25" + attribute \src "libresoc.v:189322.3-189330.6" + wire $1\alu_l_r_alu$next[0:0]$12772 + attribute \src "libresoc.v:188333.7-188333.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:189358.3-189370.6" - wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12699 - attribute \src "libresoc.v:188628.14-188628.49" + attribute \src "libresoc.v:189108.3-189120.6" + wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12697 + attribute \src "libresoc.v:188378.14-188378.49" wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:189358.3-189370.6" - wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12700 - attribute \src "libresoc.v:188632.14-188632.43" + attribute \src "libresoc.v:189108.3-189120.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12698 + attribute \src "libresoc.v:188382.14-188382.43" wire width 32 $1\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:189358.3-189370.6" - wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12701 - attribute \src "libresoc.v:188711.13-188711.47" + attribute \src "libresoc.v:189108.3-189120.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12699 + attribute \src "libresoc.v:188461.13-188461.47" wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:189358.3-189370.6" - wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12702 - attribute \src "libresoc.v:188715.7-188715.39" + attribute \src "libresoc.v:189108.3-189120.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12700 + attribute \src "libresoc.v:188465.7-188465.39" wire $1\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:189563.3-189571.6" - wire $1\alui_l_r_alui$next[0:0]$12771 - attribute \src "libresoc.v:188733.7-188733.27" + attribute \src "libresoc.v:189313.3-189321.6" + wire $1\alui_l_r_alui$next[0:0]$12769 + attribute \src "libresoc.v:188483.7-188483.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:189371.3-189392.6" - wire width 64 $1\data_r0__o$next[63:0]$12706 - attribute \src "libresoc.v:188765.14-188765.47" + attribute \src "libresoc.v:189121.3-189142.6" + wire width 64 $1\data_r0__o$next[63:0]$12704 + attribute \src "libresoc.v:188515.14-188515.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:189371.3-189392.6" - wire $1\data_r0__o_ok$next[0:0]$12707 - attribute \src "libresoc.v:188769.7-188769.27" + attribute \src "libresoc.v:189121.3-189142.6" + wire $1\data_r0__o_ok$next[0:0]$12705 + attribute \src "libresoc.v:188519.7-188519.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:189393.3-189414.6" - wire width 64 $1\data_r1__spr1$next[63:0]$12714 - attribute \src "libresoc.v:188773.14-188773.50" + attribute \src "libresoc.v:189143.3-189164.6" + wire width 64 $1\data_r1__spr1$next[63:0]$12712 + attribute \src "libresoc.v:188523.14-188523.50" wire width 64 $1\data_r1__spr1[63:0] - attribute \src "libresoc.v:189393.3-189414.6" - wire $1\data_r1__spr1_ok$next[0:0]$12715 - attribute \src "libresoc.v:188777.7-188777.30" + attribute \src "libresoc.v:189143.3-189164.6" + wire $1\data_r1__spr1_ok$next[0:0]$12713 + attribute \src "libresoc.v:188527.7-188527.30" wire $1\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:189415.3-189436.6" - wire width 64 $1\data_r2__fast1$next[63:0]$12722 - attribute \src "libresoc.v:188781.14-188781.51" + attribute \src "libresoc.v:189165.3-189186.6" + wire width 64 $1\data_r2__fast1$next[63:0]$12720 + attribute \src "libresoc.v:188531.14-188531.51" wire width 64 $1\data_r2__fast1[63:0] - attribute \src "libresoc.v:189415.3-189436.6" - wire $1\data_r2__fast1_ok$next[0:0]$12723 - attribute \src "libresoc.v:188785.7-188785.31" + attribute \src "libresoc.v:189165.3-189186.6" + wire $1\data_r2__fast1_ok$next[0:0]$12721 + attribute \src "libresoc.v:188535.7-188535.31" wire $1\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:189437.3-189458.6" - wire $1\data_r3__xer_so$next[0:0]$12730 - attribute \src "libresoc.v:188789.7-188789.29" + attribute \src "libresoc.v:189187.3-189208.6" + wire $1\data_r3__xer_so$next[0:0]$12728 + attribute \src "libresoc.v:188539.7-188539.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:189437.3-189458.6" - wire $1\data_r3__xer_so_ok$next[0:0]$12731 - attribute \src "libresoc.v:188793.7-188793.32" + attribute \src "libresoc.v:189187.3-189208.6" + wire $1\data_r3__xer_so_ok$next[0:0]$12729 + attribute \src "libresoc.v:188543.7-188543.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:189459.3-189480.6" - wire width 2 $1\data_r4__xer_ov$next[1:0]$12738 - attribute \src "libresoc.v:188797.13-188797.35" + attribute \src "libresoc.v:189209.3-189230.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$12736 + attribute \src "libresoc.v:188547.13-188547.35" wire width 2 $1\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:189459.3-189480.6" - wire $1\data_r4__xer_ov_ok$next[0:0]$12739 - attribute \src "libresoc.v:188801.7-188801.32" + attribute \src "libresoc.v:189209.3-189230.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$12737 + attribute \src "libresoc.v:188551.7-188551.32" wire $1\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:189481.3-189502.6" - wire width 2 $1\data_r5__xer_ca$next[1:0]$12746 - attribute \src "libresoc.v:188805.13-188805.35" + attribute \src "libresoc.v:189231.3-189252.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$12744 + attribute \src "libresoc.v:188555.13-188555.35" wire width 2 $1\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:189481.3-189502.6" - wire $1\data_r5__xer_ca_ok$next[0:0]$12747 - attribute \src "libresoc.v:188809.7-188809.32" + attribute \src "libresoc.v:189231.3-189252.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$12745 + attribute \src "libresoc.v:188559.7-188559.32" wire $1\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:189581.3-189590.6" + attribute \src "libresoc.v:189331.3-189340.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:189591.3-189600.6" + attribute \src "libresoc.v:189341.3-189350.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:189601.3-189610.6" + attribute \src "libresoc.v:189351.3-189360.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:189611.3-189620.6" + attribute \src "libresoc.v:189361.3-189370.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:189621.3-189630.6" + attribute \src "libresoc.v:189371.3-189380.6" wire width 2 $1\dest5_o[1:0] - attribute \src "libresoc.v:189631.3-189640.6" + attribute \src "libresoc.v:189381.3-189390.6" wire width 2 $1\dest6_o[1:0] - attribute \src "libresoc.v:189313.3-189321.6" - wire $1\opc_l_r_opc$next[0:0]$12681 - attribute \src "libresoc.v:188837.7-188837.25" + attribute \src "libresoc.v:189063.3-189071.6" + wire $1\opc_l_r_opc$next[0:0]$12679 + attribute \src "libresoc.v:188587.7-188587.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:189304.3-189312.6" - wire $1\opc_l_s_opc$next[0:0]$12678 - attribute \src "libresoc.v:188841.7-188841.25" + attribute \src "libresoc.v:189054.3-189062.6" + wire $1\opc_l_s_opc$next[0:0]$12676 + attribute \src "libresoc.v:188591.7-188591.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:189641.3-189649.6" - wire width 6 $1\prev_wr_go$next[5:0]$12783 - attribute \src "libresoc.v:188943.13-188943.31" + attribute \src "libresoc.v:189391.3-189399.6" + wire width 6 $1\prev_wr_go$next[5:0]$12781 + attribute \src "libresoc.v:188693.13-188693.31" wire width 6 $1\prev_wr_go[5:0] - attribute \src "libresoc.v:189258.3-189267.6" + attribute \src "libresoc.v:189008.3-189017.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:189349.3-189357.6" - wire width 6 $1\req_l_r_req$next[5:0]$12693 - attribute \src "libresoc.v:188951.13-188951.32" + attribute \src "libresoc.v:189099.3-189107.6" + wire width 6 $1\req_l_r_req$next[5:0]$12691 + attribute \src "libresoc.v:188701.13-188701.32" wire width 6 $1\req_l_r_req[5:0] - attribute \src "libresoc.v:189340.3-189348.6" - wire width 6 $1\req_l_s_req$next[5:0]$12690 - attribute \src "libresoc.v:188955.13-188955.32" + attribute \src "libresoc.v:189090.3-189098.6" + wire width 6 $1\req_l_s_req$next[5:0]$12688 + attribute \src "libresoc.v:188705.13-188705.32" wire width 6 $1\req_l_s_req[5:0] - attribute \src "libresoc.v:189277.3-189285.6" - wire $1\rok_l_r_rdok$next[0:0]$12669 - attribute \src "libresoc.v:188967.7-188967.26" + attribute \src "libresoc.v:189027.3-189035.6" + wire $1\rok_l_r_rdok$next[0:0]$12667 + attribute \src "libresoc.v:188717.7-188717.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:189268.3-189276.6" - wire $1\rok_l_s_rdok$next[0:0]$12666 - attribute \src "libresoc.v:188971.7-188971.26" + attribute \src "libresoc.v:189018.3-189026.6" + wire $1\rok_l_s_rdok$next[0:0]$12664 + attribute \src "libresoc.v:188721.7-188721.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:189295.3-189303.6" - wire $1\rst_l_r_rst$next[0:0]$12675 - attribute \src "libresoc.v:188975.7-188975.25" + attribute \src "libresoc.v:189045.3-189053.6" + wire $1\rst_l_r_rst$next[0:0]$12673 + attribute \src "libresoc.v:188725.7-188725.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:189286.3-189294.6" - wire $1\rst_l_s_rst$next[0:0]$12672 - attribute \src "libresoc.v:188979.7-188979.25" + attribute \src "libresoc.v:189036.3-189044.6" + wire $1\rst_l_s_rst$next[0:0]$12670 + attribute \src "libresoc.v:188729.7-188729.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:189331.3-189339.6" - wire width 6 $1\src_l_r_src$next[5:0]$12687 - attribute \src "libresoc.v:189001.13-189001.32" + attribute \src "libresoc.v:189081.3-189089.6" + wire width 6 $1\src_l_r_src$next[5:0]$12685 + attribute \src "libresoc.v:188751.13-188751.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:189322.3-189330.6" - wire width 6 $1\src_l_s_src$next[5:0]$12684 - attribute \src "libresoc.v:189005.13-189005.32" + attribute \src "libresoc.v:189072.3-189080.6" + wire width 6 $1\src_l_s_src$next[5:0]$12682 + attribute \src "libresoc.v:188755.13-188755.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:189503.3-189512.6" - wire width 64 $1\src_r0$next[63:0]$12753 - attribute \src "libresoc.v:189009.14-189009.43" + attribute \src "libresoc.v:189253.3-189262.6" + wire width 64 $1\src_r0$next[63:0]$12751 + attribute \src "libresoc.v:188759.14-188759.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:189513.3-189522.6" - wire width 64 $1\src_r1$next[63:0]$12756 - attribute \src "libresoc.v:189013.14-189013.43" + attribute \src "libresoc.v:189263.3-189272.6" + wire width 64 $1\src_r1$next[63:0]$12754 + attribute \src "libresoc.v:188763.14-188763.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:189523.3-189532.6" - wire width 64 $1\src_r2$next[63:0]$12759 - attribute \src "libresoc.v:189017.14-189017.43" + attribute \src "libresoc.v:189273.3-189282.6" + wire width 64 $1\src_r2$next[63:0]$12757 + attribute \src "libresoc.v:188767.14-188767.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:189533.3-189542.6" - wire $1\src_r3$next[0:0]$12762 - attribute \src "libresoc.v:189021.7-189021.20" + attribute \src "libresoc.v:189283.3-189292.6" + wire $1\src_r3$next[0:0]$12760 + attribute \src "libresoc.v:188771.7-188771.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:189543.3-189552.6" - wire width 2 $1\src_r4$next[1:0]$12765 - attribute \src "libresoc.v:189025.13-189025.26" + attribute \src "libresoc.v:189293.3-189302.6" + wire width 2 $1\src_r4$next[1:0]$12763 + attribute \src "libresoc.v:188775.13-188775.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:189553.3-189562.6" - wire width 2 $1\src_r5$next[1:0]$12768 - attribute \src "libresoc.v:189029.13-189029.26" + attribute \src "libresoc.v:189303.3-189312.6" + wire width 2 $1\src_r5$next[1:0]$12766 + attribute \src "libresoc.v:188779.13-188779.26" wire width 2 $1\src_r5[1:0] - attribute \src "libresoc.v:189371.3-189392.6" - wire width 64 $2\data_r0__o$next[63:0]$12708 - attribute \src "libresoc.v:189371.3-189392.6" - wire $2\data_r0__o_ok$next[0:0]$12709 - attribute \src "libresoc.v:189393.3-189414.6" - wire width 64 $2\data_r1__spr1$next[63:0]$12716 - attribute \src "libresoc.v:189393.3-189414.6" - wire $2\data_r1__spr1_ok$next[0:0]$12717 - attribute \src "libresoc.v:189415.3-189436.6" - wire width 64 $2\data_r2__fast1$next[63:0]$12724 - attribute \src "libresoc.v:189415.3-189436.6" - wire $2\data_r2__fast1_ok$next[0:0]$12725 - attribute \src "libresoc.v:189437.3-189458.6" - wire $2\data_r3__xer_so$next[0:0]$12732 - attribute \src "libresoc.v:189437.3-189458.6" - wire $2\data_r3__xer_so_ok$next[0:0]$12733 - attribute \src "libresoc.v:189459.3-189480.6" - wire width 2 $2\data_r4__xer_ov$next[1:0]$12740 - attribute \src "libresoc.v:189459.3-189480.6" - wire $2\data_r4__xer_ov_ok$next[0:0]$12741 - attribute \src "libresoc.v:189481.3-189502.6" - wire width 2 $2\data_r5__xer_ca$next[1:0]$12748 - attribute \src "libresoc.v:189481.3-189502.6" - wire $2\data_r5__xer_ca_ok$next[0:0]$12749 - attribute \src "libresoc.v:189371.3-189392.6" - wire $3\data_r0__o_ok$next[0:0]$12710 - attribute \src "libresoc.v:189393.3-189414.6" - wire $3\data_r1__spr1_ok$next[0:0]$12718 - attribute \src "libresoc.v:189415.3-189436.6" - wire $3\data_r2__fast1_ok$next[0:0]$12726 - attribute \src "libresoc.v:189437.3-189458.6" - wire $3\data_r3__xer_so_ok$next[0:0]$12734 - attribute \src "libresoc.v:189459.3-189480.6" - wire $3\data_r4__xer_ov_ok$next[0:0]$12742 - attribute \src "libresoc.v:189481.3-189502.6" - wire $3\data_r5__xer_ca_ok$next[0:0]$12750 - attribute \src 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$reduce_and$libresoc.v:188807$12575_Y + attribute \src "libresoc.v:188820.18-188820.106" + wire $reduce_or$libresoc.v:188820$12588_Y + attribute \src "libresoc.v:188823.18-188823.113" + wire $reduce_or$libresoc.v:188823$12591_Y + attribute \src "libresoc.v:188824.18-188824.112" + wire $reduce_or$libresoc.v:188824$12592_Y + attribute \src "libresoc.v:188849.18-188849.118" + wire width 64 $ternary$libresoc.v:188849$12617_Y + attribute \src "libresoc.v:188850.18-188850.118" + wire width 64 $ternary$libresoc.v:188850$12618_Y + attribute \src "libresoc.v:188851.18-188851.118" + wire width 64 $ternary$libresoc.v:188851$12619_Y + attribute \src "libresoc.v:188852.18-188852.118" + wire $ternary$libresoc.v:188852$12620_Y + attribute \src "libresoc.v:188853.18-188853.118" + wire width 2 $ternary$libresoc.v:188853$12621_Y + attribute \src "libresoc.v:188854.18-188854.118" + wire width 2 $ternary$libresoc.v:188854$12622_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -357492,9 +357218,9 @@ module \spr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 7 \cu_busy_o @@ -357580,7 +357306,7 @@ module \spr0 wire width 2 output 22 \dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \fast1_ok - attribute \src "libresoc.v:188429.7-188429.15" + attribute \src "libresoc.v:188179.7-188179.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \o_ok @@ -357791,7 +357517,7 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:189041$12561 + cell $and $and$libresoc.v:188791$12559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357799,10 +357525,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:189041$12561_Y + connect \Y $and$libresoc.v:188791$12559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:189042$12562 + cell $and $and$libresoc.v:188792$12560 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357810,10 +357536,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:189042$12562_Y + connect \Y $and$libresoc.v:188792$12560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:189043$12563 + cell $and $and$libresoc.v:188793$12561 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357821,10 +357547,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$102 connect \B 6'111111 - connect \Y $and$libresoc.v:189043$12563_Y + connect \Y $and$libresoc.v:188793$12561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:189045$12565 + cell $and $and$libresoc.v:188795$12563 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357832,10 +357558,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:189045$12565_Y + connect \Y $and$libresoc.v:188795$12563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:189046$12566 + cell $and $and$libresoc.v:188796$12564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357843,10 +357569,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:189046$12566_Y + connect \Y $and$libresoc.v:188796$12564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:189047$12567 + cell $and $and$libresoc.v:188797$12565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357854,10 +357580,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:189047$12567_Y + connect \Y $and$libresoc.v:188797$12565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:189048$12568 + cell $and $and$libresoc.v:188798$12566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357865,10 +357591,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:189048$12568_Y + connect \Y $and$libresoc.v:188798$12566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:189049$12569 + cell $and $and$libresoc.v:188799$12567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357876,10 +357602,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:189049$12569_Y + connect \Y $and$libresoc.v:188799$12567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:189050$12570 + cell $and $and$libresoc.v:188800$12568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357887,10 +357613,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:189050$12570_Y + connect \Y $and$libresoc.v:188800$12568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:189052$12572 + cell $and $and$libresoc.v:188802$12570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357898,10 +357624,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:189052$12572_Y + connect \Y $and$libresoc.v:188802$12570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:189053$12573 + cell $and $and$libresoc.v:188803$12571 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357909,10 +357635,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } - connect \Y $and$libresoc.v:189053$12573_Y + connect \Y $and$libresoc.v:188803$12571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:189054$12574 + cell $and $and$libresoc.v:188804$12572 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357920,10 +357646,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$122 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:189054$12574_Y + connect \Y $and$libresoc.v:188804$12572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:189055$12575 + cell $and $and$libresoc.v:188805$12573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357931,10 +357657,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:189055$12575_Y + connect \Y $and$libresoc.v:188805$12573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:189056$12576 + cell $and $and$libresoc.v:188806$12574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357942,10 +357668,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:189056$12576_Y + connect \Y $and$libresoc.v:188806$12574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:189058$12578 + cell $and $and$libresoc.v:188808$12576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357953,10 +357679,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:189058$12578_Y + connect \Y $and$libresoc.v:188808$12576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:189059$12579 + cell $and $and$libresoc.v:188809$12577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357964,10 +357690,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:189059$12579_Y + connect \Y $and$libresoc.v:188809$12577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:189060$12580 + cell $and $and$libresoc.v:188810$12578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357975,10 +357701,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:189060$12580_Y + connect \Y $and$libresoc.v:188810$12578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:189061$12581 + cell $and $and$libresoc.v:188811$12579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357986,10 +357712,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [5] connect \B \cu_busy_o - connect \Y $and$libresoc.v:189061$12581_Y + connect \Y $and$libresoc.v:188811$12579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:189062$12582 + cell $and $and$libresoc.v:188812$12580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357997,10 +357723,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$6 connect \B \$8 - connect \Y $and$libresoc.v:189062$12582_Y + connect \Y $and$libresoc.v:188812$12580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:189064$12584 + cell $and $and$libresoc.v:188814$12582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358008,10 +357734,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$16 - connect \Y $and$libresoc.v:189064$12584_Y + connect \Y $and$libresoc.v:188814$12582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:189066$12586 + cell $and $and$libresoc.v:188816$12584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358019,10 +357745,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$20 - connect \Y $and$libresoc.v:189066$12586_Y + connect \Y $and$libresoc.v:188816$12584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:189067$12587 + cell $and $and$libresoc.v:188817$12585 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -358030,10 +357756,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:189067$12587_Y + connect \Y $and$libresoc.v:188817$12585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:189069$12589 + cell $and $and$libresoc.v:188819$12587 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -358041,10 +357767,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o connect \B \$28 - connect \Y $and$libresoc.v:189069$12589_Y + connect \Y $and$libresoc.v:188819$12587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:189072$12592 + cell $and $and$libresoc.v:188822$12590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358052,10 +357778,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$26 - connect \Y $and$libresoc.v:189072$12592_Y + connect \Y $and$libresoc.v:188822$12590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:189077$12597 + cell $and $and$libresoc.v:188827$12595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358063,10 +357789,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$42 - connect \Y $and$libresoc.v:189077$12597_Y + connect \Y $and$libresoc.v:188827$12595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:189078$12598 + cell $and $and$libresoc.v:188828$12596 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -358074,10 +357800,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:189078$12598_Y + connect \Y $and$libresoc.v:188828$12596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:189080$12600 + cell $and $and$libresoc.v:188830$12598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358085,10 +357811,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$48 - connect \Y $and$libresoc.v:189080$12600_Y + connect \Y $and$libresoc.v:188830$12598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:189082$12602 + cell $and $and$libresoc.v:188832$12600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358096,10 +357822,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \alu_spr0_n_ready_i - connect \Y $and$libresoc.v:189082$12602_Y + connect \Y $and$libresoc.v:188832$12600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:189083$12603 + cell $and $and$libresoc.v:188833$12601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358107,10 +357833,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$54 connect \B \alu_spr0_n_valid_o - connect \Y $and$libresoc.v:189083$12603_Y + connect \Y $and$libresoc.v:188833$12601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:189084$12604 + cell $and $and$libresoc.v:188834$12602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358118,10 +357844,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$56 connect \B \cu_busy_o - connect \Y $and$libresoc.v:189084$12604_Y + connect \Y $and$libresoc.v:188834$12602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:189089$12609 + cell $and $and$libresoc.v:188839$12607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358129,10 +357855,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:189089$12609_Y + connect \Y $and$libresoc.v:188839$12607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:189090$12610 + cell $and $and$libresoc.v:188840$12608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358140,10 +357866,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:189090$12610_Y + connect \Y $and$libresoc.v:188840$12608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:189091$12611 + cell $and $and$libresoc.v:188841$12609 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -358151,10 +357877,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:189091$12611_Y + connect \Y $and$libresoc.v:188841$12609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:189093$12613 + cell $and $and$libresoc.v:188843$12611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358162,10 +357888,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:189093$12613_Y + connect \Y $and$libresoc.v:188843$12611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:189094$12614 + cell $and $and$libresoc.v:188844$12612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358173,10 +357899,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \spr1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:189094$12614_Y + connect \Y $and$libresoc.v:188844$12612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:189095$12615 + cell $and $and$libresoc.v:188845$12613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358184,10 +357910,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:189095$12615_Y + connect \Y $and$libresoc.v:188845$12613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:189096$12616 + cell $and $and$libresoc.v:188846$12614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358195,10 +357921,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:189096$12616_Y + connect \Y $and$libresoc.v:188846$12614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:189097$12617 + cell $and $and$libresoc.v:188847$12615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358206,10 +357932,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:189097$12617_Y + connect \Y $and$libresoc.v:188847$12615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:189098$12618 + cell $and $and$libresoc.v:188848$12616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358217,10 +357943,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:189098$12618_Y + connect \Y $and$libresoc.v:188848$12616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:189105$12625 + cell $and $and$libresoc.v:188855$12623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358228,10 +357954,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:189105$12625_Y + connect \Y $and$libresoc.v:188855$12623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:189079$12599 + cell $eq $eq$libresoc.v:188829$12597 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -358239,10 +357965,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$46 connect \B 1'0 - connect \Y $eq$libresoc.v:189079$12599_Y + connect \Y $eq$libresoc.v:188829$12597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:189081$12601 + cell $eq $eq$libresoc.v:188831$12599 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -358250,66 +357976,66 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:189081$12601_Y + connect \Y $eq$libresoc.v:188831$12599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:189040$12560 + cell $not $not$libresoc.v:188790$12558 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:189040$12560_Y + connect \Y $not$libresoc.v:188790$12558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:189044$12564 + cell $not $not$libresoc.v:188794$12562 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:189044$12564_Y + connect \Y $not$libresoc.v:188794$12562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:189063$12583 + cell $not $not$libresoc.v:188813$12581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:189063$12583_Y + connect \Y $not$libresoc.v:188813$12581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:189065$12585 + cell $not $not$libresoc.v:188815$12583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:189065$12585_Y + connect \Y $not$libresoc.v:188815$12583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:189068$12588 + cell $not $not$libresoc.v:188818$12586 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:189068$12588_Y + connect \Y $not$libresoc.v:188818$12586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:189071$12591 + cell $not $not$libresoc.v:188821$12589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $not$libresoc.v:189071$12591_Y + connect \Y $not$libresoc.v:188821$12589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:189076$12596 + cell $not $not$libresoc.v:188826$12594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_ready_i - connect \Y $not$libresoc.v:189076$12596_Y + connect \Y $not$libresoc.v:188826$12594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:189051$12571 + cell $or $or$libresoc.v:188801$12569 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -358317,10 +358043,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$9 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:189051$12571_Y + connect \Y $or$libresoc.v:188801$12569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:189075$12595 + cell $or $or$libresoc.v:188825$12593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358328,10 +358054,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:189075$12595_Y + connect \Y $or$libresoc.v:188825$12593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:189085$12605 + cell $or $or$libresoc.v:188835$12603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358339,10 +358065,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:189085$12605_Y + connect \Y $or$libresoc.v:188835$12603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:189086$12606 + cell $or $or$libresoc.v:188836$12604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358350,10 +358076,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:189086$12606_Y + connect \Y $or$libresoc.v:188836$12604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:189087$12607 + cell $or $or$libresoc.v:188837$12605 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -358361,10 +358087,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:189087$12607_Y + connect \Y $or$libresoc.v:188837$12605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:189088$12608 + cell $or $or$libresoc.v:188838$12606 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -358372,10 +358098,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:189088$12608_Y + connect \Y $or$libresoc.v:188838$12606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:189092$12612 + cell $or $or$libresoc.v:188842$12610 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -358383,90 +358109,90 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:189092$12612_Y + connect \Y $or$libresoc.v:188842$12610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:189057$12577 + cell $reduce_and $reduce_and$libresoc.v:188807$12575 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$11 - connect \Y $reduce_and$libresoc.v:189057$12577_Y + connect \Y $reduce_and$libresoc.v:188807$12575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:189070$12590 + cell $reduce_or $reduce_or$libresoc.v:188820$12588 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$30 - connect \Y $reduce_or$libresoc.v:189070$12590_Y + connect \Y $reduce_or$libresoc.v:188820$12588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:189073$12593 + cell $reduce_or $reduce_or$libresoc.v:188823$12591 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:189073$12593_Y + connect \Y $reduce_or$libresoc.v:188823$12591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:189074$12594 + cell $reduce_or $reduce_or$libresoc.v:188824$12592 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:189074$12594_Y + connect \Y $reduce_or$libresoc.v:188824$12592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:189099$12619 + cell $mux $ternary$libresoc.v:188849$12617 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:189099$12619_Y + connect \Y $ternary$libresoc.v:188849$12617_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:189100$12620 + cell $mux $ternary$libresoc.v:188850$12618 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:189100$12620_Y + connect \Y $ternary$libresoc.v:188850$12618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:189101$12621 + cell $mux $ternary$libresoc.v:188851$12619 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:189101$12621_Y + connect \Y $ternary$libresoc.v:188851$12619_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:189102$12622 + cell $mux $ternary$libresoc.v:188852$12620 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:189102$12622_Y + connect \Y $ternary$libresoc.v:188852$12620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:189103$12623 + cell $mux $ternary$libresoc.v:188853$12621 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:189103$12623_Y + connect \Y $ternary$libresoc.v:188853$12621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:189104$12624 + cell $mux $ternary$libresoc.v:188854$12622 parameter \WIDTH 2 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:189104$12624_Y + connect \Y $ternary$libresoc.v:188854$12622_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189180.14-189186.4" + attribute \src "libresoc.v:188930.14-188936.4" cell \alu_l$73 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -358475,7 +358201,7 @@ module \spr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:189187.12-189216.4" + attribute \src "libresoc.v:188937.12-188966.4" cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -358507,7 +358233,7 @@ module \spr0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:189217.15-189223.4" + attribute \src "libresoc.v:188967.15-188973.4" cell \alui_l$72 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -358516,7 +358242,7 @@ module \spr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:189224.14-189230.4" + attribute \src "libresoc.v:188974.14-188980.4" cell \opc_l$68 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -358525,7 +358251,7 @@ module \spr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:189231.14-189237.4" + attribute \src "libresoc.v:188981.14-188987.4" cell \req_l$69 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -358534,7 +358260,7 @@ module \spr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:189238.14-189244.4" + attribute \src "libresoc.v:188988.14-188994.4" cell \rok_l$71 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -358543,7 +358269,7 @@ module \spr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:189245.14-189250.4" + attribute \src "libresoc.v:188995.14-189000.4" cell \rst_l$70 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -358551,7 +358277,7 @@ module \spr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:189251.14-189257.4" + attribute \src "libresoc.v:189001.14-189007.4" cell \src_l$67 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -358559,577 +358285,577 @@ module \spr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:188429.7-188429.20" - process $proc$libresoc.v:188429$12784 + attribute \src "libresoc.v:188179.7-188179.20" + process $proc$libresoc.v:188179$12782 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188565.7-188565.24" - process $proc$libresoc.v:188565$12785 + attribute \src "libresoc.v:188315.7-188315.24" + process $proc$libresoc.v:188315$12783 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:188575.7-188575.26" - process $proc$libresoc.v:188575$12786 + attribute \src "libresoc.v:188325.7-188325.26" + process $proc$libresoc.v:188325$12784 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:188583.7-188583.25" - process $proc$libresoc.v:188583$12787 + attribute \src "libresoc.v:188333.7-188333.25" + process $proc$libresoc.v:188333$12785 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:188628.14-188628.49" - process $proc$libresoc.v:188628$12788 + attribute \src "libresoc.v:188378.14-188378.49" + process $proc$libresoc.v:188378$12786 assign { } { } assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:188632.14-188632.43" - process $proc$libresoc.v:188632$12789 + attribute \src "libresoc.v:188382.14-188382.43" + process $proc$libresoc.v:188382$12787 assign { } { } assign $1\alu_spr0_spr_op__insn[31:0] 0 sync always sync init update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:188711.13-188711.47" - process $proc$libresoc.v:188711$12790 + attribute \src "libresoc.v:188461.13-188461.47" + process $proc$libresoc.v:188461$12788 assign { } { } assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:188715.7-188715.39" - process $proc$libresoc.v:188715$12791 + attribute \src "libresoc.v:188465.7-188465.39" + process $proc$libresoc.v:188465$12789 assign { } { } assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:188733.7-188733.27" - process $proc$libresoc.v:188733$12792 + attribute \src "libresoc.v:188483.7-188483.27" + process $proc$libresoc.v:188483$12790 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:188765.14-188765.47" - process $proc$libresoc.v:188765$12793 + attribute \src "libresoc.v:188515.14-188515.47" + process $proc$libresoc.v:188515$12791 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:188769.7-188769.27" - process $proc$libresoc.v:188769$12794 + attribute \src "libresoc.v:188519.7-188519.27" + process $proc$libresoc.v:188519$12792 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:188773.14-188773.50" - process $proc$libresoc.v:188773$12795 + attribute \src "libresoc.v:188523.14-188523.50" + process $proc$libresoc.v:188523$12793 assign { } { } assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__spr1 $1\data_r1__spr1[63:0] end - attribute \src "libresoc.v:188777.7-188777.30" - process $proc$libresoc.v:188777$12796 + attribute \src "libresoc.v:188527.7-188527.30" + process $proc$libresoc.v:188527$12794 assign { } { } assign $1\data_r1__spr1_ok[0:0] 1'0 sync always sync init update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:188781.14-188781.51" - process $proc$libresoc.v:188781$12797 + attribute \src "libresoc.v:188531.14-188531.51" + process $proc$libresoc.v:188531$12795 assign { } { } assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast1 $1\data_r2__fast1[63:0] end - attribute \src "libresoc.v:188785.7-188785.31" - process $proc$libresoc.v:188785$12798 + attribute \src "libresoc.v:188535.7-188535.31" + process $proc$libresoc.v:188535$12796 assign { } { } assign $1\data_r2__fast1_ok[0:0] 1'0 sync always sync init update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:188789.7-188789.29" - process $proc$libresoc.v:188789$12799 + attribute \src "libresoc.v:188539.7-188539.29" + process $proc$libresoc.v:188539$12797 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:188793.7-188793.32" - process $proc$libresoc.v:188793$12800 + attribute \src "libresoc.v:188543.7-188543.32" + process $proc$libresoc.v:188543$12798 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:188797.13-188797.35" - process $proc$libresoc.v:188797$12801 + attribute \src "libresoc.v:188547.13-188547.35" + process $proc$libresoc.v:188547$12799 assign { } { } assign $1\data_r4__xer_ov[1:0] 2'00 sync always sync init update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:188801.7-188801.32" - process $proc$libresoc.v:188801$12802 + attribute \src "libresoc.v:188551.7-188551.32" + process $proc$libresoc.v:188551$12800 assign { } { } assign $1\data_r4__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:188805.13-188805.35" - process $proc$libresoc.v:188805$12803 + attribute \src "libresoc.v:188555.13-188555.35" + process $proc$libresoc.v:188555$12801 assign { } { } assign $1\data_r5__xer_ca[1:0] 2'00 sync always sync init update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:188809.7-188809.32" - process $proc$libresoc.v:188809$12804 + attribute \src "libresoc.v:188559.7-188559.32" + process $proc$libresoc.v:188559$12802 assign { } { } assign $1\data_r5__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:188837.7-188837.25" - process $proc$libresoc.v:188837$12805 + attribute \src "libresoc.v:188587.7-188587.25" + process $proc$libresoc.v:188587$12803 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:188841.7-188841.25" - process $proc$libresoc.v:188841$12806 + attribute \src "libresoc.v:188591.7-188591.25" + process $proc$libresoc.v:188591$12804 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:188943.13-188943.31" - process $proc$libresoc.v:188943$12807 + attribute \src "libresoc.v:188693.13-188693.31" + process $proc$libresoc.v:188693$12805 assign { } { } assign $1\prev_wr_go[5:0] 6'000000 sync always sync init update \prev_wr_go $1\prev_wr_go[5:0] end - attribute \src "libresoc.v:188951.13-188951.32" - process $proc$libresoc.v:188951$12808 + attribute \src "libresoc.v:188701.13-188701.32" + process $proc$libresoc.v:188701$12806 assign { } { } assign $1\req_l_r_req[5:0] 6'111111 sync always sync init update \req_l_r_req $1\req_l_r_req[5:0] end - attribute \src "libresoc.v:188955.13-188955.32" - process $proc$libresoc.v:188955$12809 + attribute \src "libresoc.v:188705.13-188705.32" + process $proc$libresoc.v:188705$12807 assign { } { } assign $1\req_l_s_req[5:0] 6'000000 sync always sync init update \req_l_s_req $1\req_l_s_req[5:0] end - attribute \src "libresoc.v:188967.7-188967.26" - process $proc$libresoc.v:188967$12810 + attribute \src "libresoc.v:188717.7-188717.26" + process $proc$libresoc.v:188717$12808 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:188971.7-188971.26" - process $proc$libresoc.v:188971$12811 + attribute \src "libresoc.v:188721.7-188721.26" + process $proc$libresoc.v:188721$12809 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:188975.7-188975.25" - process $proc$libresoc.v:188975$12812 + attribute \src "libresoc.v:188725.7-188725.25" + process $proc$libresoc.v:188725$12810 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:188979.7-188979.25" - process $proc$libresoc.v:188979$12813 + attribute \src "libresoc.v:188729.7-188729.25" + process $proc$libresoc.v:188729$12811 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:189001.13-189001.32" - process $proc$libresoc.v:189001$12814 + attribute \src "libresoc.v:188751.13-188751.32" + process $proc$libresoc.v:188751$12812 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:189005.13-189005.32" - process $proc$libresoc.v:189005$12815 + attribute \src "libresoc.v:188755.13-188755.32" + process $proc$libresoc.v:188755$12813 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:189009.14-189009.43" - process $proc$libresoc.v:189009$12816 + attribute \src "libresoc.v:188759.14-188759.43" + process $proc$libresoc.v:188759$12814 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:189013.14-189013.43" - process $proc$libresoc.v:189013$12817 + attribute \src "libresoc.v:188763.14-188763.43" + process $proc$libresoc.v:188763$12815 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:189017.14-189017.43" - process $proc$libresoc.v:189017$12818 + attribute \src "libresoc.v:188767.14-188767.43" + process $proc$libresoc.v:188767$12816 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:189021.7-189021.20" - process $proc$libresoc.v:189021$12819 + attribute \src "libresoc.v:188771.7-188771.20" + process $proc$libresoc.v:188771$12817 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:189025.13-189025.26" - process $proc$libresoc.v:189025$12820 + attribute \src "libresoc.v:188775.13-188775.26" + process $proc$libresoc.v:188775$12818 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:189029.13-189029.26" - process $proc$libresoc.v:189029$12821 + attribute \src "libresoc.v:188779.13-188779.26" + process $proc$libresoc.v:188779$12819 assign { } { } assign $1\src_r5[1:0] 2'00 sync always sync init update \src_r5 $1\src_r5[1:0] end - attribute \src "libresoc.v:189106.3-189107.39" - process $proc$libresoc.v:189106$12626 + attribute \src "libresoc.v:188856.3-188857.39" + process $proc$libresoc.v:188856$12624 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:189108.3-189109.43" - process $proc$libresoc.v:189108$12627 + attribute \src "libresoc.v:188858.3-188859.43" + process $proc$libresoc.v:188858$12625 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:189110.3-189111.29" - process $proc$libresoc.v:189110$12628 + attribute \src "libresoc.v:188860.3-188861.29" + process $proc$libresoc.v:188860$12626 assign { } { } assign $0\src_r5[1:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[1:0] end - attribute \src "libresoc.v:189112.3-189113.29" - process $proc$libresoc.v:189112$12629 + attribute \src "libresoc.v:188862.3-188863.29" + process $proc$libresoc.v:188862$12627 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:189114.3-189115.29" - process $proc$libresoc.v:189114$12630 + attribute \src "libresoc.v:188864.3-188865.29" + process $proc$libresoc.v:188864$12628 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:189116.3-189117.29" - process $proc$libresoc.v:189116$12631 + attribute \src "libresoc.v:188866.3-188867.29" + process $proc$libresoc.v:188866$12629 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:189118.3-189119.29" - process $proc$libresoc.v:189118$12632 + attribute \src "libresoc.v:188868.3-188869.29" + process $proc$libresoc.v:188868$12630 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:189120.3-189121.29" - process $proc$libresoc.v:189120$12633 + attribute \src "libresoc.v:188870.3-188871.29" + process $proc$libresoc.v:188870$12631 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:189122.3-189123.47" - process $proc$libresoc.v:189122$12634 + attribute \src "libresoc.v:188872.3-188873.47" + process $proc$libresoc.v:188872$12632 assign { } { } assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next sync posedge \coresync_clk update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:189124.3-189125.53" - process $proc$libresoc.v:189124$12635 + attribute \src "libresoc.v:188874.3-188875.53" + process $proc$libresoc.v:188874$12633 assign { } { } assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next sync posedge \coresync_clk update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:189126.3-189127.47" - process $proc$libresoc.v:189126$12636 + attribute \src "libresoc.v:188876.3-188877.47" + process $proc$libresoc.v:188876$12634 assign { } { } assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next sync posedge \coresync_clk update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:189128.3-189129.53" - process $proc$libresoc.v:189128$12637 + attribute \src "libresoc.v:188878.3-188879.53" + process $proc$libresoc.v:188878$12635 assign { } { } assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next sync posedge \coresync_clk update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:189130.3-189131.47" - process $proc$libresoc.v:189130$12638 + attribute \src "libresoc.v:188880.3-188881.47" + process $proc$libresoc.v:188880$12636 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:189132.3-189133.53" - process $proc$libresoc.v:189132$12639 + attribute \src "libresoc.v:188882.3-188883.53" + process $proc$libresoc.v:188882$12637 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:189134.3-189135.45" - process $proc$libresoc.v:189134$12640 + attribute \src "libresoc.v:188884.3-188885.45" + process $proc$libresoc.v:188884$12638 assign { } { } assign $0\data_r2__fast1[63:0] \data_r2__fast1$next sync posedge \coresync_clk update \data_r2__fast1 $0\data_r2__fast1[63:0] end - attribute \src "libresoc.v:189136.3-189137.51" - process $proc$libresoc.v:189136$12641 + attribute \src "libresoc.v:188886.3-188887.51" + process $proc$libresoc.v:188886$12639 assign { } { } assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next sync posedge \coresync_clk update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:189138.3-189139.43" - process $proc$libresoc.v:189138$12642 + attribute \src "libresoc.v:188888.3-188889.43" + process $proc$libresoc.v:188888$12640 assign { } { } assign $0\data_r1__spr1[63:0] \data_r1__spr1$next sync posedge \coresync_clk update \data_r1__spr1 $0\data_r1__spr1[63:0] end - attribute \src "libresoc.v:189140.3-189141.49" - process $proc$libresoc.v:189140$12643 + attribute \src "libresoc.v:188890.3-188891.49" + process $proc$libresoc.v:188890$12641 assign { } { } assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next sync posedge \coresync_clk update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:189142.3-189143.37" - process $proc$libresoc.v:189142$12644 + attribute \src "libresoc.v:188892.3-188893.37" + process $proc$libresoc.v:188892$12642 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:189144.3-189145.43" - process $proc$libresoc.v:189144$12645 + attribute \src "libresoc.v:188894.3-188895.43" + process $proc$libresoc.v:188894$12643 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:189146.3-189147.69" - process $proc$libresoc.v:189146$12646 + attribute \src "libresoc.v:188896.3-188897.69" + process $proc$libresoc.v:188896$12644 assign { } { } assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:189148.3-189149.65" - process $proc$libresoc.v:189148$12647 + attribute \src "libresoc.v:188898.3-188899.65" + process $proc$libresoc.v:188898$12645 assign { } { } assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next sync posedge \coresync_clk update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:189150.3-189151.59" - process $proc$libresoc.v:189150$12648 + attribute \src "libresoc.v:188900.3-188901.59" + process $proc$libresoc.v:188900$12646 assign { } { } assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:189152.3-189153.67" - process $proc$libresoc.v:189152$12649 + attribute \src "libresoc.v:188902.3-188903.67" + process $proc$libresoc.v:188902$12647 assign { } { } assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next sync posedge \coresync_clk update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:189154.3-189155.39" - process $proc$libresoc.v:189154$12650 + attribute \src "libresoc.v:188904.3-188905.39" + process $proc$libresoc.v:188904$12648 assign { } { } assign $0\req_l_r_req[5:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[5:0] end - attribute \src "libresoc.v:189156.3-189157.39" - process $proc$libresoc.v:189156$12651 + attribute \src "libresoc.v:188906.3-188907.39" + process $proc$libresoc.v:188906$12649 assign { } { } assign $0\req_l_s_req[5:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[5:0] end - attribute \src "libresoc.v:189158.3-189159.39" - process $proc$libresoc.v:189158$12652 + attribute \src "libresoc.v:188908.3-188909.39" + process $proc$libresoc.v:188908$12650 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:189160.3-189161.39" - process $proc$libresoc.v:189160$12653 + attribute \src "libresoc.v:188910.3-188911.39" + process $proc$libresoc.v:188910$12651 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:189162.3-189163.39" - process $proc$libresoc.v:189162$12654 + attribute \src "libresoc.v:188912.3-188913.39" + process $proc$libresoc.v:188912$12652 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:189164.3-189165.39" - process $proc$libresoc.v:189164$12655 + attribute \src "libresoc.v:188914.3-188915.39" + process $proc$libresoc.v:188914$12653 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:189166.3-189167.39" - process $proc$libresoc.v:189166$12656 + attribute \src "libresoc.v:188916.3-188917.39" + process $proc$libresoc.v:188916$12654 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:189168.3-189169.39" - process $proc$libresoc.v:189168$12657 + attribute \src "libresoc.v:188918.3-188919.39" + process $proc$libresoc.v:188918$12655 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:189170.3-189171.41" - process $proc$libresoc.v:189170$12658 + attribute \src "libresoc.v:188920.3-188921.41" + process $proc$libresoc.v:188920$12656 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:189172.3-189173.41" - process $proc$libresoc.v:189172$12659 + attribute \src "libresoc.v:188922.3-188923.41" + process $proc$libresoc.v:188922$12657 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:189174.3-189175.37" - process $proc$libresoc.v:189174$12660 + attribute \src "libresoc.v:188924.3-188925.37" + process $proc$libresoc.v:188924$12658 assign { } { } assign $0\prev_wr_go[5:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[5:0] end - attribute \src "libresoc.v:189176.3-189177.40" - process $proc$libresoc.v:189176$12661 + attribute \src "libresoc.v:188926.3-188927.40" + process $proc$libresoc.v:188926$12659 assign { } { } assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:189178.3-189179.25" - process $proc$libresoc.v:189178$12662 + attribute \src "libresoc.v:188928.3-188929.25" + process $proc$libresoc.v:188928$12660 assign { } { } assign $0\all_rd_dly[0:0] \$14 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:189258.3-189267.6" - process $proc$libresoc.v:189258$12663 + attribute \src "libresoc.v:189008.3-189017.6" + process $proc$libresoc.v:189008$12661 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:189259.5-189259.29" + attribute \src "libresoc.v:189009.5-189009.29" switch \initial - attribute \src "libresoc.v:189259.9-189259.17" + attribute \src "libresoc.v:189009.9-189009.17" case 1'1 case end @@ -359145,14 +358871,14 @@ module \spr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:189268.3-189276.6" - process $proc$libresoc.v:189268$12664 + attribute \src "libresoc.v:189018.3-189026.6" + process $proc$libresoc.v:189018$12662 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12665 $1\rok_l_s_rdok$next[0:0]$12666 - attribute \src "libresoc.v:189269.5-189269.29" + assign $0\rok_l_s_rdok$next[0:0]$12663 $1\rok_l_s_rdok$next[0:0]$12664 + attribute \src "libresoc.v:189019.5-189019.29" switch \initial - attribute \src "libresoc.v:189269.9-189269.17" + attribute \src "libresoc.v:189019.9-189019.17" case 1'1 case end @@ -359161,21 +358887,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12666 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12664 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12666 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12664 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12665 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12663 end - attribute \src "libresoc.v:189277.3-189285.6" - process $proc$libresoc.v:189277$12667 + attribute \src "libresoc.v:189027.3-189035.6" + process $proc$libresoc.v:189027$12665 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12668 $1\rok_l_r_rdok$next[0:0]$12669 - attribute \src "libresoc.v:189278.5-189278.29" + assign $0\rok_l_r_rdok$next[0:0]$12666 $1\rok_l_r_rdok$next[0:0]$12667 + attribute \src "libresoc.v:189028.5-189028.29" switch \initial - attribute \src "libresoc.v:189278.9-189278.17" + attribute \src "libresoc.v:189028.9-189028.17" case 1'1 case end @@ -359184,21 +358910,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12669 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12667 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12669 \$68 + assign $1\rok_l_r_rdok$next[0:0]$12667 \$68 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12668 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12666 end - attribute \src "libresoc.v:189286.3-189294.6" - process $proc$libresoc.v:189286$12670 + attribute \src "libresoc.v:189036.3-189044.6" + process $proc$libresoc.v:189036$12668 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12671 $1\rst_l_s_rst$next[0:0]$12672 - attribute \src "libresoc.v:189287.5-189287.29" + assign $0\rst_l_s_rst$next[0:0]$12669 $1\rst_l_s_rst$next[0:0]$12670 + attribute \src "libresoc.v:189037.5-189037.29" switch \initial - attribute \src "libresoc.v:189287.9-189287.17" + attribute \src "libresoc.v:189037.9-189037.17" case 1'1 case end @@ -359207,21 +358933,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12672 1'0 + assign $1\rst_l_s_rst$next[0:0]$12670 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12672 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12670 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12671 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12669 end - attribute \src "libresoc.v:189295.3-189303.6" - process $proc$libresoc.v:189295$12673 + attribute \src "libresoc.v:189045.3-189053.6" + process $proc$libresoc.v:189045$12671 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12674 $1\rst_l_r_rst$next[0:0]$12675 - attribute \src "libresoc.v:189296.5-189296.29" + assign $0\rst_l_r_rst$next[0:0]$12672 $1\rst_l_r_rst$next[0:0]$12673 + attribute \src "libresoc.v:189046.5-189046.29" switch \initial - attribute \src "libresoc.v:189296.9-189296.17" + attribute \src "libresoc.v:189046.9-189046.17" case 1'1 case end @@ -359230,21 +358956,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12675 1'1 + assign $1\rst_l_r_rst$next[0:0]$12673 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12675 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12673 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12674 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12672 end - attribute \src "libresoc.v:189304.3-189312.6" - process $proc$libresoc.v:189304$12676 + attribute \src "libresoc.v:189054.3-189062.6" + process $proc$libresoc.v:189054$12674 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12677 $1\opc_l_s_opc$next[0:0]$12678 - attribute \src "libresoc.v:189305.5-189305.29" + assign $0\opc_l_s_opc$next[0:0]$12675 $1\opc_l_s_opc$next[0:0]$12676 + attribute \src "libresoc.v:189055.5-189055.29" switch \initial - attribute \src "libresoc.v:189305.9-189305.17" + attribute \src "libresoc.v:189055.9-189055.17" case 1'1 case end @@ -359253,21 +358979,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12678 1'0 + assign $1\opc_l_s_opc$next[0:0]$12676 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12678 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12676 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12677 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12675 end - attribute \src "libresoc.v:189313.3-189321.6" - process $proc$libresoc.v:189313$12679 + attribute \src "libresoc.v:189063.3-189071.6" + process $proc$libresoc.v:189063$12677 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12680 $1\opc_l_r_opc$next[0:0]$12681 - attribute \src "libresoc.v:189314.5-189314.29" + assign $0\opc_l_r_opc$next[0:0]$12678 $1\opc_l_r_opc$next[0:0]$12679 + attribute \src "libresoc.v:189064.5-189064.29" switch \initial - attribute \src "libresoc.v:189314.9-189314.17" + attribute \src "libresoc.v:189064.9-189064.17" case 1'1 case end @@ -359276,21 +359002,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12681 1'1 + assign $1\opc_l_r_opc$next[0:0]$12679 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12681 \req_done + assign $1\opc_l_r_opc$next[0:0]$12679 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12680 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12678 end - attribute \src "libresoc.v:189322.3-189330.6" - process $proc$libresoc.v:189322$12682 + attribute \src "libresoc.v:189072.3-189080.6" + process $proc$libresoc.v:189072$12680 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$12683 $1\src_l_s_src$next[5:0]$12684 - attribute \src "libresoc.v:189323.5-189323.29" + assign $0\src_l_s_src$next[5:0]$12681 $1\src_l_s_src$next[5:0]$12682 + attribute \src "libresoc.v:189073.5-189073.29" switch \initial - attribute \src "libresoc.v:189323.9-189323.17" + attribute \src "libresoc.v:189073.9-189073.17" case 1'1 case end @@ -359299,21 +359025,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$12684 6'000000 + assign $1\src_l_s_src$next[5:0]$12682 6'000000 case - assign $1\src_l_s_src$next[5:0]$12684 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$12682 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12683 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12681 end - attribute \src "libresoc.v:189331.3-189339.6" - process $proc$libresoc.v:189331$12685 + attribute \src "libresoc.v:189081.3-189089.6" + process $proc$libresoc.v:189081$12683 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$12686 $1\src_l_r_src$next[5:0]$12687 - attribute \src "libresoc.v:189332.5-189332.29" + assign $0\src_l_r_src$next[5:0]$12684 $1\src_l_r_src$next[5:0]$12685 + attribute \src "libresoc.v:189082.5-189082.29" switch \initial - attribute \src "libresoc.v:189332.9-189332.17" + attribute \src "libresoc.v:189082.9-189082.17" case 1'1 case end @@ -359322,21 +359048,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$12687 6'111111 + assign $1\src_l_r_src$next[5:0]$12685 6'111111 case - assign $1\src_l_r_src$next[5:0]$12687 \reset_r + assign $1\src_l_r_src$next[5:0]$12685 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12686 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12684 end - attribute \src "libresoc.v:189340.3-189348.6" - process $proc$libresoc.v:189340$12688 + attribute \src "libresoc.v:189090.3-189098.6" + process $proc$libresoc.v:189090$12686 assign { } { } assign { } { } - assign $0\req_l_s_req$next[5:0]$12689 $1\req_l_s_req$next[5:0]$12690 - attribute \src "libresoc.v:189341.5-189341.29" + assign $0\req_l_s_req$next[5:0]$12687 $1\req_l_s_req$next[5:0]$12688 + attribute \src "libresoc.v:189091.5-189091.29" switch \initial - attribute \src "libresoc.v:189341.9-189341.17" + attribute \src "libresoc.v:189091.9-189091.17" case 1'1 case end @@ -359345,21 +359071,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[5:0]$12690 6'000000 + assign $1\req_l_s_req$next[5:0]$12688 6'000000 case - assign $1\req_l_s_req$next[5:0]$12690 \$70 + assign $1\req_l_s_req$next[5:0]$12688 \$70 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12689 + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12687 end - attribute \src "libresoc.v:189349.3-189357.6" - process $proc$libresoc.v:189349$12691 + attribute \src "libresoc.v:189099.3-189107.6" + process $proc$libresoc.v:189099$12689 assign { } { } assign { } { } - assign $0\req_l_r_req$next[5:0]$12692 $1\req_l_r_req$next[5:0]$12693 - attribute \src "libresoc.v:189350.5-189350.29" + assign $0\req_l_r_req$next[5:0]$12690 $1\req_l_r_req$next[5:0]$12691 + attribute \src "libresoc.v:189100.5-189100.29" switch \initial - attribute \src "libresoc.v:189350.9-189350.17" + attribute \src "libresoc.v:189100.9-189100.17" case 1'1 case end @@ -359368,15 +359094,15 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[5:0]$12693 6'111111 + assign $1\req_l_r_req$next[5:0]$12691 6'111111 case - assign $1\req_l_r_req$next[5:0]$12693 \$72 + assign $1\req_l_r_req$next[5:0]$12691 \$72 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12692 + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12690 end - attribute \src "libresoc.v:189358.3-189370.6" - process $proc$libresoc.v:189358$12694 + attribute \src "libresoc.v:189108.3-189120.6" + process $proc$libresoc.v:189108$12692 assign { } { } assign { } { } assign { } { } @@ -359385,13 +359111,13 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$12695 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12699 - assign $0\alu_spr0_spr_op__insn$next[31:0]$12696 $1\alu_spr0_spr_op__insn$next[31:0]$12700 - assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12697 $1\alu_spr0_spr_op__insn_type$next[6:0]$12701 - assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12698 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12702 - attribute \src "libresoc.v:189359.5-189359.29" + assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$12693 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12697 + assign $0\alu_spr0_spr_op__insn$next[31:0]$12694 $1\alu_spr0_spr_op__insn$next[31:0]$12698 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12695 $1\alu_spr0_spr_op__insn_type$next[6:0]$12699 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12696 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12700 + attribute \src "libresoc.v:189109.5-189109.29" switch \initial - attribute \src "libresoc.v:189359.9-189359.17" + attribute \src "libresoc.v:189109.9-189109.17" case 1'1 case end @@ -359403,33 +359129,33 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12702 $1\alu_spr0_spr_op__insn$next[31:0]$12700 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12699 $1\alu_spr0_spr_op__insn_type$next[6:0]$12701 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12700 $1\alu_spr0_spr_op__insn$next[31:0]$12698 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12697 $1\alu_spr0_spr_op__insn_type$next[6:0]$12699 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } case - assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$12699 \alu_spr0_spr_op__fn_unit - assign $1\alu_spr0_spr_op__insn$next[31:0]$12700 \alu_spr0_spr_op__insn - assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12701 \alu_spr0_spr_op__insn_type - assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12702 \alu_spr0_spr_op__is_32bit + assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$12697 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$12698 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12699 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12700 \alu_spr0_spr_op__is_32bit end sync always - update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$12695 - update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12696 - update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12697 - update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12698 + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$12693 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12694 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12695 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12696 end - attribute \src "libresoc.v:189371.3-189392.6" - process $proc$libresoc.v:189371$12703 + attribute \src "libresoc.v:189121.3-189142.6" + process $proc$libresoc.v:189121$12701 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12704 $2\data_r0__o$next[63:0]$12708 + assign $0\data_r0__o$next[63:0]$12702 $2\data_r0__o$next[63:0]$12706 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12705 $3\data_r0__o_ok$next[0:0]$12710 - attribute \src "libresoc.v:189372.5-189372.29" + assign $0\data_r0__o_ok$next[0:0]$12703 $3\data_r0__o_ok$next[0:0]$12708 + attribute \src "libresoc.v:189122.5-189122.29" switch \initial - attribute \src "libresoc.v:189372.9-189372.17" + attribute \src "libresoc.v:189122.9-189122.17" case 1'1 case end @@ -359439,10 +359165,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12707 $1\data_r0__o$next[63:0]$12706 } { \o_ok \alu_spr0_o } + assign { $1\data_r0__o_ok$next[0:0]$12705 $1\data_r0__o$next[63:0]$12704 } { \o_ok \alu_spr0_o } case - assign $1\data_r0__o$next[63:0]$12706 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12707 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12704 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12705 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -359450,38 +359176,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12709 $2\data_r0__o$next[63:0]$12708 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12707 $2\data_r0__o$next[63:0]$12706 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12708 $1\data_r0__o$next[63:0]$12706 - assign $2\data_r0__o_ok$next[0:0]$12709 $1\data_r0__o_ok$next[0:0]$12707 + assign $2\data_r0__o$next[63:0]$12706 $1\data_r0__o$next[63:0]$12704 + assign $2\data_r0__o_ok$next[0:0]$12707 $1\data_r0__o_ok$next[0:0]$12705 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12710 1'0 + assign $3\data_r0__o_ok$next[0:0]$12708 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12710 $2\data_r0__o_ok$next[0:0]$12709 + assign $3\data_r0__o_ok$next[0:0]$12708 $2\data_r0__o_ok$next[0:0]$12707 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12704 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12705 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12702 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12703 end - attribute \src "libresoc.v:189393.3-189414.6" - process $proc$libresoc.v:189393$12711 + attribute \src "libresoc.v:189143.3-189164.6" + process $proc$libresoc.v:189143$12709 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__spr1$next[63:0]$12712 $2\data_r1__spr1$next[63:0]$12716 + assign $0\data_r1__spr1$next[63:0]$12710 $2\data_r1__spr1$next[63:0]$12714 assign { } { } - assign $0\data_r1__spr1_ok$next[0:0]$12713 $3\data_r1__spr1_ok$next[0:0]$12718 - attribute \src "libresoc.v:189394.5-189394.29" + assign $0\data_r1__spr1_ok$next[0:0]$12711 $3\data_r1__spr1_ok$next[0:0]$12716 + attribute \src "libresoc.v:189144.5-189144.29" switch \initial - attribute \src "libresoc.v:189394.9-189394.17" + attribute \src "libresoc.v:189144.9-189144.17" case 1'1 case end @@ -359491,10 +359217,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__spr1_ok$next[0:0]$12715 $1\data_r1__spr1$next[63:0]$12714 } { \spr1_ok \alu_spr0_spr1 } + assign { $1\data_r1__spr1_ok$next[0:0]$12713 $1\data_r1__spr1$next[63:0]$12712 } { \spr1_ok \alu_spr0_spr1 } case - assign $1\data_r1__spr1$next[63:0]$12714 \data_r1__spr1 - assign $1\data_r1__spr1_ok$next[0:0]$12715 \data_r1__spr1_ok + assign $1\data_r1__spr1$next[63:0]$12712 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$12713 \data_r1__spr1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -359502,38 +359228,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__spr1_ok$next[0:0]$12717 $2\data_r1__spr1$next[63:0]$12716 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__spr1_ok$next[0:0]$12715 $2\data_r1__spr1$next[63:0]$12714 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__spr1$next[63:0]$12716 $1\data_r1__spr1$next[63:0]$12714 - assign $2\data_r1__spr1_ok$next[0:0]$12717 $1\data_r1__spr1_ok$next[0:0]$12715 + assign $2\data_r1__spr1$next[63:0]$12714 $1\data_r1__spr1$next[63:0]$12712 + assign $2\data_r1__spr1_ok$next[0:0]$12715 $1\data_r1__spr1_ok$next[0:0]$12713 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__spr1_ok$next[0:0]$12718 1'0 + assign $3\data_r1__spr1_ok$next[0:0]$12716 1'0 case - assign $3\data_r1__spr1_ok$next[0:0]$12718 $2\data_r1__spr1_ok$next[0:0]$12717 + assign $3\data_r1__spr1_ok$next[0:0]$12716 $2\data_r1__spr1_ok$next[0:0]$12715 end sync always - update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12712 - update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12713 + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12710 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12711 end - attribute \src "libresoc.v:189415.3-189436.6" - process $proc$libresoc.v:189415$12719 + attribute \src "libresoc.v:189165.3-189186.6" + process $proc$libresoc.v:189165$12717 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast1$next[63:0]$12720 $2\data_r2__fast1$next[63:0]$12724 + assign $0\data_r2__fast1$next[63:0]$12718 $2\data_r2__fast1$next[63:0]$12722 assign { } { } - assign $0\data_r2__fast1_ok$next[0:0]$12721 $3\data_r2__fast1_ok$next[0:0]$12726 - attribute \src "libresoc.v:189416.5-189416.29" + assign $0\data_r2__fast1_ok$next[0:0]$12719 $3\data_r2__fast1_ok$next[0:0]$12724 + attribute \src "libresoc.v:189166.5-189166.29" switch \initial - attribute \src "libresoc.v:189416.9-189416.17" + attribute \src "libresoc.v:189166.9-189166.17" case 1'1 case end @@ -359543,10 +359269,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast1_ok$next[0:0]$12723 $1\data_r2__fast1$next[63:0]$12722 } { \fast1_ok \alu_spr0_fast1 } + assign { $1\data_r2__fast1_ok$next[0:0]$12721 $1\data_r2__fast1$next[63:0]$12720 } { \fast1_ok \alu_spr0_fast1 } case - assign $1\data_r2__fast1$next[63:0]$12722 \data_r2__fast1 - assign $1\data_r2__fast1_ok$next[0:0]$12723 \data_r2__fast1_ok + assign $1\data_r2__fast1$next[63:0]$12720 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$12721 \data_r2__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -359554,38 +359280,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast1_ok$next[0:0]$12725 $2\data_r2__fast1$next[63:0]$12724 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast1_ok$next[0:0]$12723 $2\data_r2__fast1$next[63:0]$12722 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast1$next[63:0]$12724 $1\data_r2__fast1$next[63:0]$12722 - assign $2\data_r2__fast1_ok$next[0:0]$12725 $1\data_r2__fast1_ok$next[0:0]$12723 + assign $2\data_r2__fast1$next[63:0]$12722 $1\data_r2__fast1$next[63:0]$12720 + assign $2\data_r2__fast1_ok$next[0:0]$12723 $1\data_r2__fast1_ok$next[0:0]$12721 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast1_ok$next[0:0]$12726 1'0 + assign $3\data_r2__fast1_ok$next[0:0]$12724 1'0 case - assign $3\data_r2__fast1_ok$next[0:0]$12726 $2\data_r2__fast1_ok$next[0:0]$12725 + assign $3\data_r2__fast1_ok$next[0:0]$12724 $2\data_r2__fast1_ok$next[0:0]$12723 end sync always - update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12720 - update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12721 + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12718 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12719 end - attribute \src "libresoc.v:189437.3-189458.6" - process $proc$libresoc.v:189437$12727 + attribute \src "libresoc.v:189187.3-189208.6" + process $proc$libresoc.v:189187$12725 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$12728 $2\data_r3__xer_so$next[0:0]$12732 + assign $0\data_r3__xer_so$next[0:0]$12726 $2\data_r3__xer_so$next[0:0]$12730 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$12729 $3\data_r3__xer_so_ok$next[0:0]$12734 - attribute \src "libresoc.v:189438.5-189438.29" + assign $0\data_r3__xer_so_ok$next[0:0]$12727 $3\data_r3__xer_so_ok$next[0:0]$12732 + attribute \src "libresoc.v:189188.5-189188.29" switch \initial - attribute \src "libresoc.v:189438.9-189438.17" + attribute \src "libresoc.v:189188.9-189188.17" case 1'1 case end @@ -359595,10 +359321,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$12731 $1\data_r3__xer_so$next[0:0]$12730 } { \xer_so_ok \alu_spr0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$12729 $1\data_r3__xer_so$next[0:0]$12728 } { \xer_so_ok \alu_spr0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$12730 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$12731 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$12728 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$12729 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -359606,38 +359332,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$12733 $2\data_r3__xer_so$next[0:0]$12732 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$12731 $2\data_r3__xer_so$next[0:0]$12730 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$12732 $1\data_r3__xer_so$next[0:0]$12730 - assign $2\data_r3__xer_so_ok$next[0:0]$12733 $1\data_r3__xer_so_ok$next[0:0]$12731 + assign $2\data_r3__xer_so$next[0:0]$12730 $1\data_r3__xer_so$next[0:0]$12728 + assign $2\data_r3__xer_so_ok$next[0:0]$12731 $1\data_r3__xer_so_ok$next[0:0]$12729 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$12734 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$12732 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$12734 $2\data_r3__xer_so_ok$next[0:0]$12733 + assign $3\data_r3__xer_so_ok$next[0:0]$12732 $2\data_r3__xer_so_ok$next[0:0]$12731 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12728 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12729 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12726 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12727 end - attribute \src "libresoc.v:189459.3-189480.6" - process $proc$libresoc.v:189459$12735 + attribute \src "libresoc.v:189209.3-189230.6" + process $proc$libresoc.v:189209$12733 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__xer_ov$next[1:0]$12736 $2\data_r4__xer_ov$next[1:0]$12740 + assign $0\data_r4__xer_ov$next[1:0]$12734 $2\data_r4__xer_ov$next[1:0]$12738 assign { } { } - assign $0\data_r4__xer_ov_ok$next[0:0]$12737 $3\data_r4__xer_ov_ok$next[0:0]$12742 - attribute \src "libresoc.v:189460.5-189460.29" + assign $0\data_r4__xer_ov_ok$next[0:0]$12735 $3\data_r4__xer_ov_ok$next[0:0]$12740 + attribute \src "libresoc.v:189210.5-189210.29" switch \initial - attribute \src "libresoc.v:189460.9-189460.17" + attribute \src "libresoc.v:189210.9-189210.17" case 1'1 case end @@ -359647,10 +359373,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__xer_ov_ok$next[0:0]$12739 $1\data_r4__xer_ov$next[1:0]$12738 } { \xer_ov_ok \alu_spr0_xer_ov } + assign { $1\data_r4__xer_ov_ok$next[0:0]$12737 $1\data_r4__xer_ov$next[1:0]$12736 } { \xer_ov_ok \alu_spr0_xer_ov } case - assign $1\data_r4__xer_ov$next[1:0]$12738 \data_r4__xer_ov - assign $1\data_r4__xer_ov_ok$next[0:0]$12739 \data_r4__xer_ov_ok + assign $1\data_r4__xer_ov$next[1:0]$12736 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$12737 \data_r4__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -359658,38 +359384,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__xer_ov_ok$next[0:0]$12741 $2\data_r4__xer_ov$next[1:0]$12740 } 3'000 + assign { $2\data_r4__xer_ov_ok$next[0:0]$12739 $2\data_r4__xer_ov$next[1:0]$12738 } 3'000 case - assign $2\data_r4__xer_ov$next[1:0]$12740 $1\data_r4__xer_ov$next[1:0]$12738 - assign $2\data_r4__xer_ov_ok$next[0:0]$12741 $1\data_r4__xer_ov_ok$next[0:0]$12739 + assign $2\data_r4__xer_ov$next[1:0]$12738 $1\data_r4__xer_ov$next[1:0]$12736 + assign $2\data_r4__xer_ov_ok$next[0:0]$12739 $1\data_r4__xer_ov_ok$next[0:0]$12737 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__xer_ov_ok$next[0:0]$12742 1'0 + assign $3\data_r4__xer_ov_ok$next[0:0]$12740 1'0 case - assign $3\data_r4__xer_ov_ok$next[0:0]$12742 $2\data_r4__xer_ov_ok$next[0:0]$12741 + assign $3\data_r4__xer_ov_ok$next[0:0]$12740 $2\data_r4__xer_ov_ok$next[0:0]$12739 end sync always - update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12736 - update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12737 + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12734 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12735 end - attribute \src "libresoc.v:189481.3-189502.6" - process $proc$libresoc.v:189481$12743 + attribute \src "libresoc.v:189231.3-189252.6" + process $proc$libresoc.v:189231$12741 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r5__xer_ca$next[1:0]$12744 $2\data_r5__xer_ca$next[1:0]$12748 + assign $0\data_r5__xer_ca$next[1:0]$12742 $2\data_r5__xer_ca$next[1:0]$12746 assign { } { } - assign $0\data_r5__xer_ca_ok$next[0:0]$12745 $3\data_r5__xer_ca_ok$next[0:0]$12750 - attribute \src "libresoc.v:189482.5-189482.29" + assign $0\data_r5__xer_ca_ok$next[0:0]$12743 $3\data_r5__xer_ca_ok$next[0:0]$12748 + attribute \src "libresoc.v:189232.5-189232.29" switch \initial - attribute \src "libresoc.v:189482.9-189482.17" + attribute \src "libresoc.v:189232.9-189232.17" case 1'1 case end @@ -359699,10 +359425,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r5__xer_ca_ok$next[0:0]$12747 $1\data_r5__xer_ca$next[1:0]$12746 } { \xer_ca_ok \alu_spr0_xer_ca } + assign { $1\data_r5__xer_ca_ok$next[0:0]$12745 $1\data_r5__xer_ca$next[1:0]$12744 } { \xer_ca_ok \alu_spr0_xer_ca } case - assign $1\data_r5__xer_ca$next[1:0]$12746 \data_r5__xer_ca - assign $1\data_r5__xer_ca_ok$next[0:0]$12747 \data_r5__xer_ca_ok + assign $1\data_r5__xer_ca$next[1:0]$12744 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$12745 \data_r5__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -359710,32 +359436,32 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r5__xer_ca_ok$next[0:0]$12749 $2\data_r5__xer_ca$next[1:0]$12748 } 3'000 + assign { $2\data_r5__xer_ca_ok$next[0:0]$12747 $2\data_r5__xer_ca$next[1:0]$12746 } 3'000 case - assign $2\data_r5__xer_ca$next[1:0]$12748 $1\data_r5__xer_ca$next[1:0]$12746 - assign $2\data_r5__xer_ca_ok$next[0:0]$12749 $1\data_r5__xer_ca_ok$next[0:0]$12747 + assign $2\data_r5__xer_ca$next[1:0]$12746 $1\data_r5__xer_ca$next[1:0]$12744 + assign $2\data_r5__xer_ca_ok$next[0:0]$12747 $1\data_r5__xer_ca_ok$next[0:0]$12745 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r5__xer_ca_ok$next[0:0]$12750 1'0 + assign $3\data_r5__xer_ca_ok$next[0:0]$12748 1'0 case - assign $3\data_r5__xer_ca_ok$next[0:0]$12750 $2\data_r5__xer_ca_ok$next[0:0]$12749 + assign $3\data_r5__xer_ca_ok$next[0:0]$12748 $2\data_r5__xer_ca_ok$next[0:0]$12747 end sync always - update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12744 - update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12745 + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12742 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12743 end - attribute \src "libresoc.v:189503.3-189512.6" - process $proc$libresoc.v:189503$12751 + attribute \src "libresoc.v:189253.3-189262.6" + process $proc$libresoc.v:189253$12749 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12752 $1\src_r0$next[63:0]$12753 - attribute \src "libresoc.v:189504.5-189504.29" + assign $0\src_r0$next[63:0]$12750 $1\src_r0$next[63:0]$12751 + attribute \src "libresoc.v:189254.5-189254.29" switch \initial - attribute \src "libresoc.v:189504.9-189504.17" + attribute \src "libresoc.v:189254.9-189254.17" case 1'1 case end @@ -359744,21 +359470,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12753 \src1_i + assign $1\src_r0$next[63:0]$12751 \src1_i case - assign $1\src_r0$next[63:0]$12753 \src_r0 + assign $1\src_r0$next[63:0]$12751 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12752 + update \src_r0$next $0\src_r0$next[63:0]$12750 end - attribute \src "libresoc.v:189513.3-189522.6" - process $proc$libresoc.v:189513$12754 + attribute \src "libresoc.v:189263.3-189272.6" + process $proc$libresoc.v:189263$12752 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12755 $1\src_r1$next[63:0]$12756 - attribute \src "libresoc.v:189514.5-189514.29" + assign $0\src_r1$next[63:0]$12753 $1\src_r1$next[63:0]$12754 + attribute \src "libresoc.v:189264.5-189264.29" switch \initial - attribute \src "libresoc.v:189514.9-189514.17" + attribute \src "libresoc.v:189264.9-189264.17" case 1'1 case end @@ -359767,21 +359493,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12756 \src2_i + assign $1\src_r1$next[63:0]$12754 \src2_i case - assign $1\src_r1$next[63:0]$12756 \src_r1 + assign $1\src_r1$next[63:0]$12754 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12755 + update \src_r1$next $0\src_r1$next[63:0]$12753 end - attribute \src "libresoc.v:189523.3-189532.6" - process $proc$libresoc.v:189523$12757 + attribute \src "libresoc.v:189273.3-189282.6" + process $proc$libresoc.v:189273$12755 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12758 $1\src_r2$next[63:0]$12759 - attribute \src "libresoc.v:189524.5-189524.29" + assign $0\src_r2$next[63:0]$12756 $1\src_r2$next[63:0]$12757 + attribute \src "libresoc.v:189274.5-189274.29" switch \initial - attribute \src "libresoc.v:189524.9-189524.17" + attribute \src "libresoc.v:189274.9-189274.17" case 1'1 case end @@ -359790,21 +359516,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12759 \src3_i + assign $1\src_r2$next[63:0]$12757 \src3_i case - assign $1\src_r2$next[63:0]$12759 \src_r2 + assign $1\src_r2$next[63:0]$12757 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12758 + update \src_r2$next $0\src_r2$next[63:0]$12756 end - attribute \src "libresoc.v:189533.3-189542.6" - process $proc$libresoc.v:189533$12760 + attribute \src "libresoc.v:189283.3-189292.6" + process $proc$libresoc.v:189283$12758 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12761 $1\src_r3$next[0:0]$12762 - attribute \src "libresoc.v:189534.5-189534.29" + assign $0\src_r3$next[0:0]$12759 $1\src_r3$next[0:0]$12760 + attribute \src "libresoc.v:189284.5-189284.29" switch \initial - attribute \src "libresoc.v:189534.9-189534.17" + attribute \src "libresoc.v:189284.9-189284.17" case 1'1 case end @@ -359813,21 +359539,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12762 \src4_i + assign $1\src_r3$next[0:0]$12760 \src4_i case - assign $1\src_r3$next[0:0]$12762 \src_r3 + assign $1\src_r3$next[0:0]$12760 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12761 + update \src_r3$next $0\src_r3$next[0:0]$12759 end - attribute \src "libresoc.v:189543.3-189552.6" - process $proc$libresoc.v:189543$12763 + attribute \src "libresoc.v:189293.3-189302.6" + process $proc$libresoc.v:189293$12761 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12764 $1\src_r4$next[1:0]$12765 - attribute \src "libresoc.v:189544.5-189544.29" + assign $0\src_r4$next[1:0]$12762 $1\src_r4$next[1:0]$12763 + attribute \src "libresoc.v:189294.5-189294.29" switch \initial - attribute \src "libresoc.v:189544.9-189544.17" + attribute \src "libresoc.v:189294.9-189294.17" case 1'1 case end @@ -359836,21 +359562,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12765 \src5_i + assign $1\src_r4$next[1:0]$12763 \src5_i case - assign $1\src_r4$next[1:0]$12765 \src_r4 + assign $1\src_r4$next[1:0]$12763 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12764 + update \src_r4$next $0\src_r4$next[1:0]$12762 end - attribute \src "libresoc.v:189553.3-189562.6" - process $proc$libresoc.v:189553$12766 + attribute \src "libresoc.v:189303.3-189312.6" + process $proc$libresoc.v:189303$12764 assign { } { } assign { } { } - assign $0\src_r5$next[1:0]$12767 $1\src_r5$next[1:0]$12768 - attribute \src "libresoc.v:189554.5-189554.29" + assign $0\src_r5$next[1:0]$12765 $1\src_r5$next[1:0]$12766 + attribute \src "libresoc.v:189304.5-189304.29" switch \initial - attribute \src "libresoc.v:189554.9-189554.17" + attribute \src "libresoc.v:189304.9-189304.17" case 1'1 case end @@ -359859,21 +359585,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[1:0]$12768 \src6_i + assign $1\src_r5$next[1:0]$12766 \src6_i case - assign $1\src_r5$next[1:0]$12768 \src_r5 + assign $1\src_r5$next[1:0]$12766 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[1:0]$12767 + update \src_r5$next $0\src_r5$next[1:0]$12765 end - attribute \src "libresoc.v:189563.3-189571.6" - process $proc$libresoc.v:189563$12769 + attribute \src "libresoc.v:189313.3-189321.6" + process $proc$libresoc.v:189313$12767 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12770 $1\alui_l_r_alui$next[0:0]$12771 - attribute \src "libresoc.v:189564.5-189564.29" + assign $0\alui_l_r_alui$next[0:0]$12768 $1\alui_l_r_alui$next[0:0]$12769 + attribute \src "libresoc.v:189314.5-189314.29" switch \initial - attribute \src "libresoc.v:189564.9-189564.17" + attribute \src "libresoc.v:189314.9-189314.17" case 1'1 case end @@ -359882,21 +359608,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12771 1'1 + assign $1\alui_l_r_alui$next[0:0]$12769 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12771 \$98 + assign $1\alui_l_r_alui$next[0:0]$12769 \$98 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12770 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12768 end - attribute \src "libresoc.v:189572.3-189580.6" - process $proc$libresoc.v:189572$12772 + attribute \src "libresoc.v:189322.3-189330.6" + process $proc$libresoc.v:189322$12770 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12773 $1\alu_l_r_alu$next[0:0]$12774 - attribute \src "libresoc.v:189573.5-189573.29" + assign $0\alu_l_r_alu$next[0:0]$12771 $1\alu_l_r_alu$next[0:0]$12772 + attribute \src "libresoc.v:189323.5-189323.29" switch \initial - attribute \src "libresoc.v:189573.9-189573.17" + attribute \src "libresoc.v:189323.9-189323.17" case 1'1 case end @@ -359905,21 +359631,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12774 1'1 + assign $1\alu_l_r_alu$next[0:0]$12772 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12774 \$100 + assign $1\alu_l_r_alu$next[0:0]$12772 \$100 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12773 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12771 end - attribute \src "libresoc.v:189581.3-189590.6" - process $proc$libresoc.v:189581$12775 + attribute \src "libresoc.v:189331.3-189340.6" + process $proc$libresoc.v:189331$12773 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:189582.5-189582.29" + attribute \src "libresoc.v:189332.5-189332.29" switch \initial - attribute \src "libresoc.v:189582.9-189582.17" + attribute \src "libresoc.v:189332.9-189332.17" case 1'1 case end @@ -359935,14 +359661,14 @@ module \spr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:189591.3-189600.6" - process $proc$libresoc.v:189591$12776 + attribute \src "libresoc.v:189341.3-189350.6" + process $proc$libresoc.v:189341$12774 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:189592.5-189592.29" + attribute \src "libresoc.v:189342.5-189342.29" switch \initial - attribute \src "libresoc.v:189592.9-189592.17" + attribute \src "libresoc.v:189342.9-189342.17" case 1'1 case end @@ -359958,14 +359684,14 @@ module \spr0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:189601.3-189610.6" - process $proc$libresoc.v:189601$12777 + attribute \src "libresoc.v:189351.3-189360.6" + process $proc$libresoc.v:189351$12775 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:189602.5-189602.29" + attribute \src "libresoc.v:189352.5-189352.29" switch \initial - attribute \src "libresoc.v:189602.9-189602.17" + attribute \src "libresoc.v:189352.9-189352.17" case 1'1 case end @@ -359981,14 +359707,14 @@ module \spr0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:189611.3-189620.6" - process $proc$libresoc.v:189611$12778 + attribute \src "libresoc.v:189361.3-189370.6" + process $proc$libresoc.v:189361$12776 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:189612.5-189612.29" + attribute \src "libresoc.v:189362.5-189362.29" switch \initial - attribute \src "libresoc.v:189612.9-189612.17" + attribute \src "libresoc.v:189362.9-189362.17" case 1'1 case end @@ -360004,14 +359730,14 @@ module \spr0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:189621.3-189630.6" - process $proc$libresoc.v:189621$12779 + attribute \src "libresoc.v:189371.3-189380.6" + process $proc$libresoc.v:189371$12777 assign { } { } assign { } { } assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "libresoc.v:189622.5-189622.29" + attribute \src "libresoc.v:189372.5-189372.29" switch \initial - attribute \src "libresoc.v:189622.9-189622.17" + attribute \src "libresoc.v:189372.9-189372.17" case 1'1 case end @@ -360027,14 +359753,14 @@ module \spr0 sync always update \dest5_o $0\dest5_o[1:0] end - attribute \src "libresoc.v:189631.3-189640.6" - process $proc$libresoc.v:189631$12780 + attribute \src "libresoc.v:189381.3-189390.6" + process $proc$libresoc.v:189381$12778 assign { } { } assign { } { } assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "libresoc.v:189632.5-189632.29" + attribute \src "libresoc.v:189382.5-189382.29" switch \initial - attribute \src "libresoc.v:189632.9-189632.17" + attribute \src "libresoc.v:189382.9-189382.17" case 1'1 case end @@ -360050,14 +359776,14 @@ module \spr0 sync always update \dest6_o $0\dest6_o[1:0] end - attribute \src "libresoc.v:189641.3-189649.6" - process $proc$libresoc.v:189641$12781 + attribute \src "libresoc.v:189391.3-189399.6" + process $proc$libresoc.v:189391$12779 assign { } { } assign { } { } - assign $0\prev_wr_go$next[5:0]$12782 $1\prev_wr_go$next[5:0]$12783 - attribute \src "libresoc.v:189642.5-189642.29" + assign $0\prev_wr_go$next[5:0]$12780 $1\prev_wr_go$next[5:0]$12781 + attribute \src "libresoc.v:189392.5-189392.29" switch \initial - attribute \src "libresoc.v:189642.9-189642.17" + attribute \src "libresoc.v:189392.9-189392.17" case 1'1 case end @@ -360066,79 +359792,79 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[5:0]$12783 6'000000 - case - assign $1\prev_wr_go$next[5:0]$12783 \$24 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12782 - end - connect \$9 $not$libresoc.v:189040$12560_Y - connect \$100 $and$libresoc.v:189041$12561_Y - connect \$102 $and$libresoc.v:189042$12562_Y - connect \$104 $and$libresoc.v:189043$12563_Y - connect \$106 $not$libresoc.v:189044$12564_Y - connect \$108 $and$libresoc.v:189045$12565_Y - connect \$110 $and$libresoc.v:189046$12566_Y - connect \$112 $and$libresoc.v:189047$12567_Y - connect \$114 $and$libresoc.v:189048$12568_Y - connect \$116 $and$libresoc.v:189049$12569_Y - connect \$118 $and$libresoc.v:189050$12570_Y - connect \$11 $or$libresoc.v:189051$12571_Y - connect \$120 $and$libresoc.v:189052$12572_Y - connect \$122 $and$libresoc.v:189053$12573_Y - connect \$124 $and$libresoc.v:189054$12574_Y - connect \$126 $and$libresoc.v:189055$12575_Y - connect \$128 $and$libresoc.v:189056$12576_Y - connect \$8 $reduce_and$libresoc.v:189057$12577_Y - connect \$130 $and$libresoc.v:189058$12578_Y - connect \$132 $and$libresoc.v:189059$12579_Y - connect \$134 $and$libresoc.v:189060$12580_Y - connect \$136 $and$libresoc.v:189061$12581_Y - connect \$14 $and$libresoc.v:189062$12582_Y - connect \$16 $not$libresoc.v:189063$12583_Y - connect \$18 $and$libresoc.v:189064$12584_Y - connect \$20 $not$libresoc.v:189065$12585_Y - connect \$22 $and$libresoc.v:189066$12586_Y - connect \$24 $and$libresoc.v:189067$12587_Y - connect \$28 $not$libresoc.v:189068$12588_Y - connect \$30 $and$libresoc.v:189069$12589_Y - connect \$27 $reduce_or$libresoc.v:189070$12590_Y - connect \$26 $not$libresoc.v:189071$12591_Y - connect \$34 $and$libresoc.v:189072$12592_Y - connect \$36 $reduce_or$libresoc.v:189073$12593_Y - connect \$38 $reduce_or$libresoc.v:189074$12594_Y - connect \$40 $or$libresoc.v:189075$12595_Y - connect \$42 $not$libresoc.v:189076$12596_Y - connect \$44 $and$libresoc.v:189077$12597_Y - connect \$46 $and$libresoc.v:189078$12598_Y - connect \$48 $eq$libresoc.v:189079$12599_Y - connect \$50 $and$libresoc.v:189080$12600_Y - connect \$52 $eq$libresoc.v:189081$12601_Y - connect \$54 $and$libresoc.v:189082$12602_Y - connect \$56 $and$libresoc.v:189083$12603_Y - connect \$58 $and$libresoc.v:189084$12604_Y - connect \$60 $or$libresoc.v:189085$12605_Y - connect \$62 $or$libresoc.v:189086$12606_Y - connect \$64 $or$libresoc.v:189087$12607_Y - connect \$66 $or$libresoc.v:189088$12608_Y - connect \$68 $and$libresoc.v:189089$12609_Y - connect \$6 $and$libresoc.v:189090$12610_Y - connect \$70 $and$libresoc.v:189091$12611_Y - connect \$72 $or$libresoc.v:189092$12612_Y - connect \$74 $and$libresoc.v:189093$12613_Y - connect \$76 $and$libresoc.v:189094$12614_Y - connect \$78 $and$libresoc.v:189095$12615_Y - connect \$80 $and$libresoc.v:189096$12616_Y - connect \$82 $and$libresoc.v:189097$12617_Y - connect \$84 $and$libresoc.v:189098$12618_Y - connect \$86 $ternary$libresoc.v:189099$12619_Y - connect \$88 $ternary$libresoc.v:189100$12620_Y - connect \$90 $ternary$libresoc.v:189101$12621_Y - connect \$92 $ternary$libresoc.v:189102$12622_Y - connect \$94 $ternary$libresoc.v:189103$12623_Y - connect \$96 $ternary$libresoc.v:189104$12624_Y - connect \$98 $and$libresoc.v:189105$12625_Y + assign $1\prev_wr_go$next[5:0]$12781 6'000000 + case + assign $1\prev_wr_go$next[5:0]$12781 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12780 + end + connect \$9 $not$libresoc.v:188790$12558_Y + connect \$100 $and$libresoc.v:188791$12559_Y + connect \$102 $and$libresoc.v:188792$12560_Y + connect \$104 $and$libresoc.v:188793$12561_Y + connect \$106 $not$libresoc.v:188794$12562_Y + connect \$108 $and$libresoc.v:188795$12563_Y + connect \$110 $and$libresoc.v:188796$12564_Y + connect \$112 $and$libresoc.v:188797$12565_Y + connect \$114 $and$libresoc.v:188798$12566_Y + connect \$116 $and$libresoc.v:188799$12567_Y + connect \$118 $and$libresoc.v:188800$12568_Y + connect \$11 $or$libresoc.v:188801$12569_Y + connect \$120 $and$libresoc.v:188802$12570_Y + connect \$122 $and$libresoc.v:188803$12571_Y + connect \$124 $and$libresoc.v:188804$12572_Y + connect \$126 $and$libresoc.v:188805$12573_Y + connect \$128 $and$libresoc.v:188806$12574_Y + connect \$8 $reduce_and$libresoc.v:188807$12575_Y + connect \$130 $and$libresoc.v:188808$12576_Y + connect \$132 $and$libresoc.v:188809$12577_Y + connect \$134 $and$libresoc.v:188810$12578_Y + connect \$136 $and$libresoc.v:188811$12579_Y + connect \$14 $and$libresoc.v:188812$12580_Y + connect \$16 $not$libresoc.v:188813$12581_Y + connect \$18 $and$libresoc.v:188814$12582_Y + connect \$20 $not$libresoc.v:188815$12583_Y + connect \$22 $and$libresoc.v:188816$12584_Y + connect \$24 $and$libresoc.v:188817$12585_Y + connect \$28 $not$libresoc.v:188818$12586_Y + connect \$30 $and$libresoc.v:188819$12587_Y + connect \$27 $reduce_or$libresoc.v:188820$12588_Y + connect \$26 $not$libresoc.v:188821$12589_Y + connect \$34 $and$libresoc.v:188822$12590_Y + connect \$36 $reduce_or$libresoc.v:188823$12591_Y + connect \$38 $reduce_or$libresoc.v:188824$12592_Y + connect \$40 $or$libresoc.v:188825$12593_Y + connect \$42 $not$libresoc.v:188826$12594_Y + connect \$44 $and$libresoc.v:188827$12595_Y + connect \$46 $and$libresoc.v:188828$12596_Y + connect \$48 $eq$libresoc.v:188829$12597_Y + connect \$50 $and$libresoc.v:188830$12598_Y + connect \$52 $eq$libresoc.v:188831$12599_Y + connect \$54 $and$libresoc.v:188832$12600_Y + connect \$56 $and$libresoc.v:188833$12601_Y + connect \$58 $and$libresoc.v:188834$12602_Y + connect \$60 $or$libresoc.v:188835$12603_Y + connect \$62 $or$libresoc.v:188836$12604_Y + connect \$64 $or$libresoc.v:188837$12605_Y + connect \$66 $or$libresoc.v:188838$12606_Y + connect \$68 $and$libresoc.v:188839$12607_Y + connect \$6 $and$libresoc.v:188840$12608_Y + connect \$70 $and$libresoc.v:188841$12609_Y + connect \$72 $or$libresoc.v:188842$12610_Y + connect \$74 $and$libresoc.v:188843$12611_Y + connect \$76 $and$libresoc.v:188844$12612_Y + connect \$78 $and$libresoc.v:188845$12613_Y + connect \$80 $and$libresoc.v:188846$12614_Y + connect \$82 $and$libresoc.v:188847$12615_Y + connect \$84 $and$libresoc.v:188848$12616_Y + connect \$86 $ternary$libresoc.v:188849$12617_Y + connect \$88 $ternary$libresoc.v:188850$12618_Y + connect \$90 $ternary$libresoc.v:188851$12619_Y + connect \$92 $ternary$libresoc.v:188852$12620_Y + connect \$94 $ternary$libresoc.v:188853$12621_Y + connect \$96 $ternary$libresoc.v:188854$12622_Y + connect \$98 $and$libresoc.v:188855$12623_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$124 @@ -360171,111 +359897,111 @@ module \spr0 connect \all_rd_dly$next \all_rd connect \all_rd \$14 end -attribute \src "libresoc.v:189685.1-190209.10" +attribute \src "libresoc.v:189435.1-189959.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" attribute \generator "nMigen" module \spr_main - attribute \src "libresoc.v:189958.3-189973.6" - wire width 64 $0\fast1$7[63:0]$12830 - attribute \src "libresoc.v:190039.3-190054.6" + attribute \src "libresoc.v:189708.3-189723.6" + wire width 64 $0\fast1$7[63:0]$12828 + attribute \src "libresoc.v:189789.3-189804.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:189686.7-189686.20" + attribute \src "libresoc.v:189436.7-189436.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189993.3-190038.6" + attribute \src "libresoc.v:189743.3-189788.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:189993.3-190038.6" + attribute \src "libresoc.v:189743.3-189788.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:190187.3-190205.6" - wire width 64 $0\spr1$6[63:0]$12855 - attribute \src "libresoc.v:189974.3-189992.6" + attribute \src "libresoc.v:189937.3-189955.6" + wire width 64 $0\spr1$6[63:0]$12853 + attribute \src "libresoc.v:189724.3-189742.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:190142.3-190165.6" - wire width 2 $0\xer_ca$10[1:0]$12849 - attribute \src "libresoc.v:190166.3-190186.6" + attribute \src "libresoc.v:189892.3-189915.6" + wire width 2 $0\xer_ca$10[1:0]$12847 + attribute \src "libresoc.v:189916.3-189936.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:190097.3-190120.6" - wire width 2 $0\xer_ov$9[1:0]$12843 - attribute \src "libresoc.v:190121.3-190141.6" + attribute \src "libresoc.v:189847.3-189870.6" + wire width 2 $0\xer_ov$9[1:0]$12841 + attribute \src "libresoc.v:189871.3-189891.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:190055.3-190075.6" - wire $0\xer_so$8[0:0]$12837 - attribute \src "libresoc.v:190076.3-190096.6" + attribute \src "libresoc.v:189805.3-189825.6" + wire $0\xer_so$8[0:0]$12835 + attribute \src "libresoc.v:189826.3-189846.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:189958.3-189973.6" - wire width 64 $1\fast1$7[63:0]$12831 - attribute \src "libresoc.v:190039.3-190054.6" + attribute \src "libresoc.v:189708.3-189723.6" + wire width 64 $1\fast1$7[63:0]$12829 + attribute \src "libresoc.v:189789.3-189804.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:189993.3-190038.6" + attribute \src "libresoc.v:189743.3-189788.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:189993.3-190038.6" + attribute \src "libresoc.v:189743.3-189788.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:190187.3-190205.6" - wire width 64 $1\spr1$6[63:0]$12856 - attribute \src "libresoc.v:189974.3-189992.6" + attribute \src "libresoc.v:189937.3-189955.6" + wire width 64 $1\spr1$6[63:0]$12854 + attribute \src "libresoc.v:189724.3-189742.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:190142.3-190165.6" - wire width 2 $1\xer_ca$10[1:0]$12850 - attribute \src "libresoc.v:190166.3-190186.6" + attribute \src "libresoc.v:189892.3-189915.6" + wire width 2 $1\xer_ca$10[1:0]$12848 + attribute \src "libresoc.v:189916.3-189936.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:190097.3-190120.6" - wire width 2 $1\xer_ov$9[1:0]$12844 - attribute \src "libresoc.v:190121.3-190141.6" + attribute \src "libresoc.v:189847.3-189870.6" + wire width 2 $1\xer_ov$9[1:0]$12842 + attribute \src "libresoc.v:189871.3-189891.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:190055.3-190075.6" - wire $1\xer_so$8[0:0]$12838 - attribute \src "libresoc.v:190076.3-190096.6" + attribute \src "libresoc.v:189805.3-189825.6" + wire $1\xer_so$8[0:0]$12836 + attribute \src "libresoc.v:189826.3-189846.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:189958.3-189973.6" - wire width 64 $2\fast1$7[63:0]$12832 - attribute \src "libresoc.v:190039.3-190054.6" + attribute \src "libresoc.v:189708.3-189723.6" + wire width 64 $2\fast1$7[63:0]$12830 + attribute \src "libresoc.v:189789.3-189804.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:189993.3-190038.6" + attribute \src "libresoc.v:189743.3-189788.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:190187.3-190205.6" - wire width 64 $2\spr1$6[63:0]$12857 - attribute \src "libresoc.v:189974.3-189992.6" + attribute \src "libresoc.v:189937.3-189955.6" + wire width 64 $2\spr1$6[63:0]$12855 + attribute \src "libresoc.v:189724.3-189742.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:190142.3-190165.6" - wire width 2 $2\xer_ca$10[1:0]$12851 - attribute \src "libresoc.v:190166.3-190186.6" + attribute \src "libresoc.v:189892.3-189915.6" + wire width 2 $2\xer_ca$10[1:0]$12849 + attribute \src "libresoc.v:189916.3-189936.6" wire $2\xer_ca_ok[0:0] - attribute \src "libresoc.v:190097.3-190120.6" - wire width 2 $2\xer_ov$9[1:0]$12845 - attribute \src "libresoc.v:190121.3-190141.6" + attribute \src "libresoc.v:189847.3-189870.6" + wire width 2 $2\xer_ov$9[1:0]$12843 + attribute \src "libresoc.v:189871.3-189891.6" wire $2\xer_ov_ok[0:0] - attribute \src "libresoc.v:190055.3-190075.6" - wire $2\xer_so$8[0:0]$12839 - attribute \src "libresoc.v:190076.3-190096.6" + attribute \src "libresoc.v:189805.3-189825.6" + wire $2\xer_so$8[0:0]$12837 + attribute \src "libresoc.v:189826.3-189846.6" wire $2\xer_so_ok[0:0] - attribute \src "libresoc.v:189993.3-190038.6" + attribute \src "libresoc.v:189743.3-189788.6" wire width 46 $3\o[63:18] - attribute \src "libresoc.v:190142.3-190165.6" - wire width 2 $3\xer_ca$10[1:0]$12852 - attribute \src "libresoc.v:190166.3-190186.6" + attribute \src "libresoc.v:189892.3-189915.6" + wire width 2 $3\xer_ca$10[1:0]$12850 + attribute \src "libresoc.v:189916.3-189936.6" wire $3\xer_ca_ok[0:0] - attribute \src "libresoc.v:190097.3-190120.6" - wire width 2 $3\xer_ov$9[1:0]$12846 - attribute \src "libresoc.v:190121.3-190141.6" + attribute \src "libresoc.v:189847.3-189870.6" + wire width 2 $3\xer_ov$9[1:0]$12844 + attribute \src "libresoc.v:189871.3-189891.6" wire $3\xer_ov_ok[0:0] - attribute \src "libresoc.v:190055.3-190075.6" - wire $3\xer_so$8[0:0]$12840 - attribute \src "libresoc.v:190076.3-190096.6" + attribute \src "libresoc.v:189805.3-189825.6" + wire $3\xer_so$8[0:0]$12838 + attribute \src "libresoc.v:189826.3-189846.6" wire $3\xer_so_ok[0:0] - attribute \src "libresoc.v:189951.18-189951.106" - wire $eq$libresoc.v:189951$12822_Y - attribute \src "libresoc.v:189952.18-189952.106" - wire $eq$libresoc.v:189952$12823_Y - attribute \src "libresoc.v:189953.18-189953.106" - wire $eq$libresoc.v:189953$12824_Y - attribute \src "libresoc.v:189954.18-189954.106" - wire $eq$libresoc.v:189954$12825_Y - attribute \src "libresoc.v:189955.18-189955.106" - wire $eq$libresoc.v:189955$12826_Y - attribute \src "libresoc.v:189956.18-189956.106" - wire $eq$libresoc.v:189956$12827_Y - attribute \src "libresoc.v:189957.18-189957.106" - wire $eq$libresoc.v:189957$12828_Y + attribute \src "libresoc.v:189701.18-189701.106" + wire $eq$libresoc.v:189701$12820_Y + attribute \src "libresoc.v:189702.18-189702.106" + wire $eq$libresoc.v:189702$12821_Y + attribute \src "libresoc.v:189703.18-189703.106" + wire $eq$libresoc.v:189703$12822_Y + attribute \src "libresoc.v:189704.18-189704.106" + wire $eq$libresoc.v:189704$12823_Y + attribute \src "libresoc.v:189705.18-189705.106" + wire $eq$libresoc.v:189705$12824_Y + attribute \src "libresoc.v:189706.18-189706.106" + wire $eq$libresoc.v:189706$12825_Y + attribute \src "libresoc.v:189707.18-189707.106" + wire $eq$libresoc.v:189707$12826_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" @@ -360296,7 +360022,7 @@ module \spr_main wire width 64 output 20 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 21 \fast1_ok - attribute \src "libresoc.v:189686.7-189686.15" + attribute \src "libresoc.v:189436.7-189436.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid @@ -360531,7 +360257,7 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" - cell $eq $eq$libresoc.v:189951$12822 + cell $eq $eq$libresoc.v:189701$12820 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -360539,10 +360265,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189951$12822_Y + connect \Y $eq$libresoc.v:189701$12820_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" - cell $eq $eq$libresoc.v:189952$12823 + cell $eq $eq$libresoc.v:189702$12821 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -360550,10 +360276,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189952$12823_Y + connect \Y $eq$libresoc.v:189702$12821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" - cell $eq $eq$libresoc.v:189953$12824 + cell $eq $eq$libresoc.v:189703$12822 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -360561,10 +360287,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189953$12824_Y + connect \Y $eq$libresoc.v:189703$12822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" - cell $eq $eq$libresoc.v:189954$12825 + cell $eq $eq$libresoc.v:189704$12823 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -360572,10 +360298,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189954$12825_Y + connect \Y $eq$libresoc.v:189704$12823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" - cell $eq $eq$libresoc.v:189955$12826 + cell $eq $eq$libresoc.v:189705$12824 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -360583,10 +360309,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189955$12826_Y + connect \Y $eq$libresoc.v:189705$12824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" - cell $eq $eq$libresoc.v:189956$12827 + cell $eq $eq$libresoc.v:189706$12825 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -360594,10 +360320,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189956$12827_Y + connect \Y $eq$libresoc.v:189706$12825_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" - cell $eq $eq$libresoc.v:189957$12828 + cell $eq $eq$libresoc.v:189707$12826 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -360605,24 +360331,24 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189957$12828_Y + connect \Y $eq$libresoc.v:189707$12826_Y end - attribute \src "libresoc.v:189686.7-189686.20" - process $proc$libresoc.v:189686$12858 + attribute \src "libresoc.v:189436.7-189436.20" + process $proc$libresoc.v:189436$12856 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189958.3-189973.6" - process $proc$libresoc.v:189958$12829 + attribute \src "libresoc.v:189708.3-189723.6" + process $proc$libresoc.v:189708$12827 assign { } { } assign { } { } - assign $0\fast1$7[63:0]$12830 $1\fast1$7[63:0]$12831 - attribute \src "libresoc.v:189959.5-189959.29" + assign $0\fast1$7[63:0]$12828 $1\fast1$7[63:0]$12829 + attribute \src "libresoc.v:189709.5-189709.29" switch \initial - attribute \src "libresoc.v:189959.9-189959.17" + attribute \src "libresoc.v:189709.9-189709.17" case 1'1 case end @@ -360631,30 +360357,30 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\fast1$7[63:0]$12831 $2\fast1$7[63:0]$12832 + assign $1\fast1$7[63:0]$12829 $2\fast1$7[63:0]$12830 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\fast1$7[63:0]$12832 \ra + assign $2\fast1$7[63:0]$12830 \ra case - assign $2\fast1$7[63:0]$12832 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$7[63:0]$12830 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\fast1$7[63:0]$12831 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$7[63:0]$12829 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$7 $0\fast1$7[63:0]$12830 + update \fast1$7 $0\fast1$7[63:0]$12828 end - attribute \src "libresoc.v:189974.3-189992.6" - process $proc$libresoc.v:189974$12833 + attribute \src "libresoc.v:189724.3-189742.6" + process $proc$libresoc.v:189724$12831 assign { } { } assign { } { } assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "libresoc.v:189975.5-189975.29" + attribute \src "libresoc.v:189725.5-189725.29" switch \initial - attribute \src "libresoc.v:189975.9-189975.17" + attribute \src "libresoc.v:189725.9-189725.17" case 1'1 case end @@ -360680,17 +360406,17 @@ module \spr_main sync always update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:189993.3-190038.6" - process $proc$libresoc.v:189993$12834 + attribute \src "libresoc.v:189743.3-189788.6" + process $proc$libresoc.v:189743$12832 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:189994.5-189994.29" + attribute \src "libresoc.v:189744.5-189744.29" switch \initial - attribute \src "libresoc.v:189994.9-189994.17" + attribute \src "libresoc.v:189744.9-189744.17" case 1'1 case end @@ -360745,14 +360471,14 @@ module \spr_main update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:190039.3-190054.6" - process $proc$libresoc.v:190039$12835 + attribute \src "libresoc.v:189789.3-189804.6" + process $proc$libresoc.v:189789$12833 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:190040.5-190040.29" + attribute \src "libresoc.v:189790.5-189790.29" switch \initial - attribute \src "libresoc.v:190040.9-190040.17" + attribute \src "libresoc.v:189790.9-189790.17" case 1'1 case end @@ -360777,14 +360503,14 @@ module \spr_main sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:190055.3-190075.6" - process $proc$libresoc.v:190055$12836 + attribute \src "libresoc.v:189805.3-189825.6" + process $proc$libresoc.v:189805$12834 assign { } { } assign { } { } - assign $0\xer_so$8[0:0]$12837 $1\xer_so$8[0:0]$12838 - attribute \src "libresoc.v:190056.5-190056.29" + assign $0\xer_so$8[0:0]$12835 $1\xer_so$8[0:0]$12836 + attribute \src "libresoc.v:189806.5-189806.29" switch \initial - attribute \src "libresoc.v:190056.9-190056.17" + attribute \src "libresoc.v:189806.9-189806.17" case 1'1 case end @@ -360793,39 +360519,39 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_so$8[0:0]$12838 $2\xer_so$8[0:0]$12839 + assign $1\xer_so$8[0:0]$12836 $2\xer_so$8[0:0]$12837 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_so$8[0:0]$12839 $3\xer_so$8[0:0]$12840 + assign $2\xer_so$8[0:0]$12837 $3\xer_so$8[0:0]$12838 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_so$8[0:0]$12840 \ra [31] + assign $3\xer_so$8[0:0]$12838 \ra [31] case - assign $3\xer_so$8[0:0]$12840 1'0 + assign $3\xer_so$8[0:0]$12838 1'0 end case - assign $2\xer_so$8[0:0]$12839 1'0 + assign $2\xer_so$8[0:0]$12837 1'0 end case - assign $1\xer_so$8[0:0]$12838 1'0 + assign $1\xer_so$8[0:0]$12836 1'0 end sync always - update \xer_so$8 $0\xer_so$8[0:0]$12837 + update \xer_so$8 $0\xer_so$8[0:0]$12835 end - attribute \src "libresoc.v:190076.3-190096.6" - process $proc$libresoc.v:190076$12841 + attribute \src "libresoc.v:189826.3-189846.6" + process $proc$libresoc.v:189826$12839 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:190077.5-190077.29" + attribute \src "libresoc.v:189827.5-189827.29" switch \initial - attribute \src "libresoc.v:190077.9-190077.17" + attribute \src "libresoc.v:189827.9-189827.17" case 1'1 case end @@ -360859,14 +360585,14 @@ module \spr_main sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:190097.3-190120.6" - process $proc$libresoc.v:190097$12842 + attribute \src "libresoc.v:189847.3-189870.6" + process $proc$libresoc.v:189847$12840 assign { } { } assign { } { } - assign $0\xer_ov$9[1:0]$12843 $1\xer_ov$9[1:0]$12844 - attribute \src "libresoc.v:190098.5-190098.29" + assign $0\xer_ov$9[1:0]$12841 $1\xer_ov$9[1:0]$12842 + attribute \src "libresoc.v:189848.5-189848.29" switch \initial - attribute \src "libresoc.v:190098.9-190098.17" + attribute \src "libresoc.v:189848.9-189848.17" case 1'1 case end @@ -360875,40 +360601,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ov$9[1:0]$12844 $2\xer_ov$9[1:0]$12845 + assign $1\xer_ov$9[1:0]$12842 $2\xer_ov$9[1:0]$12843 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ov$9[1:0]$12845 $3\xer_ov$9[1:0]$12846 + assign $2\xer_ov$9[1:0]$12843 $3\xer_ov$9[1:0]$12844 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ov$9[1:0]$12846 [0] \ra [30] - assign $3\xer_ov$9[1:0]$12846 [1] \ra [19] + assign $3\xer_ov$9[1:0]$12844 [0] \ra [30] + assign $3\xer_ov$9[1:0]$12844 [1] \ra [19] case - assign $3\xer_ov$9[1:0]$12846 2'00 + assign $3\xer_ov$9[1:0]$12844 2'00 end case - assign $2\xer_ov$9[1:0]$12845 2'00 + assign $2\xer_ov$9[1:0]$12843 2'00 end case - assign $1\xer_ov$9[1:0]$12844 2'00 + assign $1\xer_ov$9[1:0]$12842 2'00 end sync always - update \xer_ov$9 $0\xer_ov$9[1:0]$12843 + update \xer_ov$9 $0\xer_ov$9[1:0]$12841 end - attribute \src "libresoc.v:190121.3-190141.6" - process $proc$libresoc.v:190121$12847 + attribute \src "libresoc.v:189871.3-189891.6" + process $proc$libresoc.v:189871$12845 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:190122.5-190122.29" + attribute \src "libresoc.v:189872.5-189872.29" switch \initial - attribute \src "libresoc.v:190122.9-190122.17" + attribute \src "libresoc.v:189872.9-189872.17" case 1'1 case end @@ -360942,14 +360668,14 @@ module \spr_main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:190142.3-190165.6" - process $proc$libresoc.v:190142$12848 + attribute \src "libresoc.v:189892.3-189915.6" + process $proc$libresoc.v:189892$12846 assign { } { } assign { } { } - assign $0\xer_ca$10[1:0]$12849 $1\xer_ca$10[1:0]$12850 - attribute \src "libresoc.v:190143.5-190143.29" + assign $0\xer_ca$10[1:0]$12847 $1\xer_ca$10[1:0]$12848 + attribute \src "libresoc.v:189893.5-189893.29" switch \initial - attribute \src "libresoc.v:190143.9-190143.17" + attribute \src "libresoc.v:189893.9-189893.17" case 1'1 case end @@ -360958,40 +360684,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ca$10[1:0]$12850 $2\xer_ca$10[1:0]$12851 + assign $1\xer_ca$10[1:0]$12848 $2\xer_ca$10[1:0]$12849 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ca$10[1:0]$12851 $3\xer_ca$10[1:0]$12852 + assign $2\xer_ca$10[1:0]$12849 $3\xer_ca$10[1:0]$12850 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ca$10[1:0]$12852 [0] \ra [29] - assign $3\xer_ca$10[1:0]$12852 [1] \ra [18] + assign $3\xer_ca$10[1:0]$12850 [0] \ra [29] + assign $3\xer_ca$10[1:0]$12850 [1] \ra [18] case - assign $3\xer_ca$10[1:0]$12852 2'00 + assign $3\xer_ca$10[1:0]$12850 2'00 end case - assign $2\xer_ca$10[1:0]$12851 2'00 + assign $2\xer_ca$10[1:0]$12849 2'00 end case - assign $1\xer_ca$10[1:0]$12850 2'00 + assign $1\xer_ca$10[1:0]$12848 2'00 end sync always - update \xer_ca$10 $0\xer_ca$10[1:0]$12849 + update \xer_ca$10 $0\xer_ca$10[1:0]$12847 end - attribute \src "libresoc.v:190166.3-190186.6" - process $proc$libresoc.v:190166$12853 + attribute \src "libresoc.v:189916.3-189936.6" + process $proc$libresoc.v:189916$12851 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:190167.5-190167.29" + attribute \src "libresoc.v:189917.5-189917.29" switch \initial - attribute \src "libresoc.v:190167.9-190167.17" + attribute \src "libresoc.v:189917.9-189917.17" case 1'1 case end @@ -361025,14 +360751,14 @@ module \spr_main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:190187.3-190205.6" - process $proc$libresoc.v:190187$12854 + attribute \src "libresoc.v:189937.3-189955.6" + process $proc$libresoc.v:189937$12852 assign { } { } assign { } { } - assign $0\spr1$6[63:0]$12855 $1\spr1$6[63:0]$12856 - attribute \src "libresoc.v:190188.5-190188.29" + assign $0\spr1$6[63:0]$12853 $1\spr1$6[63:0]$12854 + attribute \src "libresoc.v:189938.5-189938.29" switch \initial - attribute \src "libresoc.v:190188.9-190188.17" + attribute \src "libresoc.v:189938.9-189938.17" case 1'1 case end @@ -361041,62 +360767,62 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\spr1$6[63:0]$12856 $2\spr1$6[63:0]$12857 + assign $1\spr1$6[63:0]$12854 $2\spr1$6[63:0]$12855 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1$6[63:0]$12857 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\spr1$6[63:0]$12855 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\spr1$6[63:0]$12857 \ra + assign $2\spr1$6[63:0]$12855 \ra end case - assign $1\spr1$6[63:0]$12856 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr1$6[63:0]$12854 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \spr1$6 $0\spr1$6[63:0]$12855 + update \spr1$6 $0\spr1$6[63:0]$12853 end - connect \$11 $eq$libresoc.v:189951$12822_Y - connect \$13 $eq$libresoc.v:189952$12823_Y - connect \$15 $eq$libresoc.v:189953$12824_Y - connect \$17 $eq$libresoc.v:189954$12825_Y - connect \$19 $eq$libresoc.v:189955$12826_Y - connect \$21 $eq$libresoc.v:189956$12827_Y - connect \$23 $eq$libresoc.v:189957$12828_Y + connect \$11 $eq$libresoc.v:189701$12820_Y + connect \$13 $eq$libresoc.v:189702$12821_Y + connect \$15 $eq$libresoc.v:189703$12822_Y + connect \$17 $eq$libresoc.v:189704$12823_Y + connect \$19 $eq$libresoc.v:189705$12824_Y + connect \$21 $eq$libresoc.v:189706$12825_Y + connect \$23 $eq$libresoc.v:189707$12826_Y connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \muxid$1 \muxid connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } end -attribute \src "libresoc.v:190213.1-191679.10" +attribute \src "libresoc.v:189963.1-191429.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" attribute \generator "nMigen" module \sprmap - attribute \src "libresoc.v:190343.3-190664.6" + attribute \src "libresoc.v:190093.3-190414.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:190665.3-190986.6" + attribute \src "libresoc.v:190415.3-190736.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:190214.7-190214.20" + attribute \src "libresoc.v:189964.7-189964.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190987.3-191332.6" + attribute \src "libresoc.v:190737.3-191082.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:191333.3-191678.6" + attribute \src "libresoc.v:191083.3-191428.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:190343.3-190664.6" + attribute \src "libresoc.v:190093.3-190414.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:190665.3-190986.6" + attribute \src "libresoc.v:190415.3-190736.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:190987.3-191332.6" + attribute \src "libresoc.v:190737.3-191082.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:191333.3-191678.6" + attribute \src "libresoc.v:191083.3-191428.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \fast_o_ok - attribute \src "libresoc.v:190214.7-190214.15" + attribute \src "libresoc.v:189964.7-189964.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" wire width 10 input 5 \spr_i @@ -361218,22 +360944,22 @@ module \sprmap wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \spr_o_ok - attribute \src "libresoc.v:190214.7-190214.20" - process $proc$libresoc.v:190214$12863 + attribute \src "libresoc.v:189964.7-189964.20" + process $proc$libresoc.v:189964$12861 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190343.3-190664.6" - process $proc$libresoc.v:190343$12859 + attribute \src "libresoc.v:190093.3-190414.6" + process $proc$libresoc.v:190093$12857 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:190344.5-190344.29" + attribute \src "libresoc.v:190094.5-190094.29" switch \initial - attribute \src "libresoc.v:190344.9-190344.17" + attribute \src "libresoc.v:190094.9-190094.17" case 1'1 case end @@ -361568,14 +361294,14 @@ module \sprmap sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:190665.3-190986.6" - process $proc$libresoc.v:190665$12860 + attribute \src "libresoc.v:190415.3-190736.6" + process $proc$libresoc.v:190415$12858 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:190666.5-190666.29" + attribute \src "libresoc.v:190416.5-190416.29" switch \initial - attribute \src "libresoc.v:190666.9-190666.17" + attribute \src "libresoc.v:190416.9-190416.17" case 1'1 case end @@ -361910,14 +361636,14 @@ module \sprmap sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:190987.3-191332.6" - process $proc$libresoc.v:190987$12861 + attribute \src "libresoc.v:190737.3-191082.6" + process $proc$libresoc.v:190737$12859 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:190988.5-190988.29" + attribute \src "libresoc.v:190738.5-190738.29" switch \initial - attribute \src "libresoc.v:190988.9-190988.17" + attribute \src "libresoc.v:190738.9-190738.17" case 1'1 case end @@ -362373,14 +362099,14 @@ module \sprmap sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:191333.3-191678.6" - process $proc$libresoc.v:191333$12862 + attribute \src "libresoc.v:191083.3-191428.6" + process $proc$libresoc.v:191083$12860 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:191334.5-191334.29" + attribute \src "libresoc.v:191084.5-191084.29" switch \initial - attribute \src "libresoc.v:191334.9-191334.17" + attribute \src "libresoc.v:191084.9-191084.17" case 1'1 case end @@ -362837,34 +362563,34 @@ module \sprmap update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:191683.1-193149.10" +attribute \src "libresoc.v:191433.1-192899.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" attribute \generator "nMigen" module \sprmap$174 - attribute \src "libresoc.v:191813.3-192134.6" + attribute \src "libresoc.v:191563.3-191884.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:192135.3-192456.6" + attribute \src "libresoc.v:191885.3-192206.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:191684.7-191684.20" + attribute \src "libresoc.v:191434.7-191434.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192457.3-192802.6" + attribute \src "libresoc.v:192207.3-192552.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:192803.3-193148.6" + attribute \src "libresoc.v:192553.3-192898.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:191813.3-192134.6" + attribute \src "libresoc.v:191563.3-191884.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:192135.3-192456.6" + attribute \src "libresoc.v:191885.3-192206.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:192457.3-192802.6" + attribute \src "libresoc.v:192207.3-192552.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:192803.3-193148.6" + attribute \src "libresoc.v:192553.3-192898.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \fast_o_ok - attribute \src "libresoc.v:191684.7-191684.15" + attribute \src "libresoc.v:191434.7-191434.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" wire width 10 input 5 \spr_i @@ -362986,22 +362712,22 @@ module \sprmap$174 wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \spr_o_ok - attribute \src "libresoc.v:191684.7-191684.20" - process $proc$libresoc.v:191684$12868 + attribute \src "libresoc.v:191434.7-191434.20" + process $proc$libresoc.v:191434$12866 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191813.3-192134.6" - process $proc$libresoc.v:191813$12864 + attribute \src "libresoc.v:191563.3-191884.6" + process $proc$libresoc.v:191563$12862 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:191814.5-191814.29" + attribute \src "libresoc.v:191564.5-191564.29" switch \initial - attribute \src "libresoc.v:191814.9-191814.17" + attribute \src "libresoc.v:191564.9-191564.17" case 1'1 case end @@ -363336,14 +363062,14 @@ module \sprmap$174 sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:192135.3-192456.6" - process $proc$libresoc.v:192135$12865 + attribute \src "libresoc.v:191885.3-192206.6" + process $proc$libresoc.v:191885$12863 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:192136.5-192136.29" + attribute \src "libresoc.v:191886.5-191886.29" switch \initial - attribute \src "libresoc.v:192136.9-192136.17" + attribute \src "libresoc.v:191886.9-191886.17" case 1'1 case end @@ -363678,14 +363404,14 @@ module \sprmap$174 sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:192457.3-192802.6" - process $proc$libresoc.v:192457$12866 + attribute \src "libresoc.v:192207.3-192552.6" + process $proc$libresoc.v:192207$12864 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:192458.5-192458.29" + attribute \src "libresoc.v:192208.5-192208.29" switch \initial - attribute \src "libresoc.v:192458.9-192458.17" + attribute \src "libresoc.v:192208.9-192208.17" case 1'1 case end @@ -364141,14 +363867,14 @@ module \sprmap$174 sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:192803.3-193148.6" - process $proc$libresoc.v:192803$12867 + attribute \src "libresoc.v:192553.3-192898.6" + process $proc$libresoc.v:192553$12865 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:192804.5-192804.29" + attribute \src "libresoc.v:192554.5-192554.29" switch \initial - attribute \src "libresoc.v:192804.9-192804.17" + attribute \src "libresoc.v:192554.9-192554.17" case 1'1 case end @@ -364605,37 +364331,37 @@ module \sprmap$174 update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:193153.1-193211.10" +attribute \src "libresoc.v:192903.1-192961.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" attribute \generator "nMigen" module \src_l - attribute \src "libresoc.v:193154.7-193154.20" + attribute \src "libresoc.v:192904.7-192904.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193199.3-193207.6" - wire width 4 $0\q_int$next[3:0]$12879 - attribute \src "libresoc.v:193197.3-193198.27" + attribute \src "libresoc.v:192949.3-192957.6" + wire width 4 $0\q_int$next[3:0]$12877 + attribute \src "libresoc.v:192947.3-192948.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:193199.3-193207.6" - wire width 4 $1\q_int$next[3:0]$12880 - attribute \src "libresoc.v:193176.13-193176.25" + attribute \src "libresoc.v:192949.3-192957.6" + wire width 4 $1\q_int$next[3:0]$12878 + attribute \src "libresoc.v:192926.13-192926.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:193189.17-193189.96" - wire width 4 $and$libresoc.v:193189$12869_Y - attribute \src "libresoc.v:193194.17-193194.96" - wire width 4 $and$libresoc.v:193194$12874_Y - attribute \src "libresoc.v:193191.18-193191.93" - wire width 4 $not$libresoc.v:193191$12871_Y - attribute \src "libresoc.v:193193.17-193193.92" - wire width 4 $not$libresoc.v:193193$12873_Y - attribute \src "libresoc.v:193196.17-193196.92" - wire width 4 $not$libresoc.v:193196$12876_Y - attribute \src "libresoc.v:193190.18-193190.98" - wire width 4 $or$libresoc.v:193190$12870_Y - attribute \src "libresoc.v:193192.18-193192.99" - wire width 4 $or$libresoc.v:193192$12872_Y - attribute \src "libresoc.v:193195.17-193195.97" - wire width 4 $or$libresoc.v:193195$12875_Y + attribute \src "libresoc.v:192939.17-192939.96" + wire width 4 $and$libresoc.v:192939$12867_Y + attribute \src "libresoc.v:192944.17-192944.96" + wire width 4 $and$libresoc.v:192944$12872_Y + attribute \src "libresoc.v:192941.18-192941.93" + wire width 4 $not$libresoc.v:192941$12869_Y + attribute \src "libresoc.v:192943.17-192943.92" + wire width 4 $not$libresoc.v:192943$12871_Y + attribute \src "libresoc.v:192946.17-192946.92" + wire width 4 $not$libresoc.v:192946$12874_Y + attribute \src "libresoc.v:192940.18-192940.98" + wire width 4 $or$libresoc.v:192940$12868_Y + attribute \src "libresoc.v:192942.18-192942.99" + wire width 4 $or$libresoc.v:192942$12870_Y + attribute \src "libresoc.v:192945.17-192945.97" + wire width 4 $or$libresoc.v:192945$12873_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -364652,11 +364378,11 @@ module \src_l wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193154.7-193154.15" + attribute \src "libresoc.v:192904.7-192904.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -364673,7 +364399,7 @@ module \src_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193189$12869 + cell $and $and$libresoc.v:192939$12867 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -364681,10 +364407,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193189$12869_Y + connect \Y $and$libresoc.v:192939$12867_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193194$12874 + cell $and $and$libresoc.v:192944$12872 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -364692,34 +364418,34 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193194$12874_Y + connect \Y $and$libresoc.v:192944$12872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193191$12871 + cell $not $not$libresoc.v:192941$12869 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:193191$12871_Y + connect \Y $not$libresoc.v:192941$12869_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193193$12873 + cell $not $not$libresoc.v:192943$12871 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:193193$12873_Y + connect \Y $not$libresoc.v:192943$12871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193196$12876 + cell $not $not$libresoc.v:192946$12874 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:193196$12876_Y + connect \Y $not$libresoc.v:192946$12874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193190$12870 + cell $or $or$libresoc.v:192940$12868 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -364727,10 +364453,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:193190$12870_Y + connect \Y $or$libresoc.v:192940$12868_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193192$12872 + cell $or $or$libresoc.v:192942$12870 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -364738,10 +364464,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:193192$12872_Y + connect \Y $or$libresoc.v:192942$12870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193195$12875 + cell $or $or$libresoc.v:192945$12873 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -364749,39 +364475,39 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:193195$12875_Y + connect \Y $or$libresoc.v:192945$12873_Y end - attribute \src "libresoc.v:193154.7-193154.20" - process $proc$libresoc.v:193154$12881 + attribute \src "libresoc.v:192904.7-192904.20" + process $proc$libresoc.v:192904$12879 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193176.13-193176.25" - process $proc$libresoc.v:193176$12882 + attribute \src "libresoc.v:192926.13-192926.25" + process $proc$libresoc.v:192926$12880 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:193197.3-193198.27" - process $proc$libresoc.v:193197$12877 + attribute \src "libresoc.v:192947.3-192948.27" + process $proc$libresoc.v:192947$12875 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:193199.3-193207.6" - process $proc$libresoc.v:193199$12878 + attribute \src "libresoc.v:192949.3-192957.6" + process $proc$libresoc.v:192949$12876 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$12879 $1\q_int$next[3:0]$12880 - attribute \src "libresoc.v:193200.5-193200.29" + assign $0\q_int$next[3:0]$12877 $1\q_int$next[3:0]$12878 + attribute \src "libresoc.v:192950.5-192950.29" switch \initial - attribute \src "libresoc.v:193200.9-193200.17" + attribute \src "libresoc.v:192950.9-192950.17" case 1'1 case end @@ -364790,56 +364516,56 @@ module \src_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$12880 4'0000 + assign $1\q_int$next[3:0]$12878 4'0000 case - assign $1\q_int$next[3:0]$12880 \$5 + assign $1\q_int$next[3:0]$12878 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$12879 + update \q_int$next $0\q_int$next[3:0]$12877 end - connect \$9 $and$libresoc.v:193189$12869_Y - connect \$11 $or$libresoc.v:193190$12870_Y - connect \$13 $not$libresoc.v:193191$12871_Y - connect \$15 $or$libresoc.v:193192$12872_Y - connect \$1 $not$libresoc.v:193193$12873_Y - connect \$3 $and$libresoc.v:193194$12874_Y - connect \$5 $or$libresoc.v:193195$12875_Y - connect \$7 $not$libresoc.v:193196$12876_Y + connect \$9 $and$libresoc.v:192939$12867_Y + connect \$11 $or$libresoc.v:192940$12868_Y + connect \$13 $not$libresoc.v:192941$12869_Y + connect \$15 $or$libresoc.v:192942$12870_Y + connect \$1 $not$libresoc.v:192943$12871_Y + connect \$3 $and$libresoc.v:192944$12872_Y + connect \$5 $or$libresoc.v:192945$12873_Y + connect \$7 $not$libresoc.v:192946$12874_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:193215.1-193273.10" +attribute \src "libresoc.v:192965.1-193023.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" attribute \generator "nMigen" module \src_l$10 - attribute \src "libresoc.v:193216.7-193216.20" + attribute \src "libresoc.v:192966.7-192966.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193261.3-193269.6" - wire width 6 $0\q_int$next[5:0]$12893 - attribute \src "libresoc.v:193259.3-193260.27" + attribute \src "libresoc.v:193011.3-193019.6" + wire width 6 $0\q_int$next[5:0]$12891 + attribute \src "libresoc.v:193009.3-193010.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:193261.3-193269.6" - wire width 6 $1\q_int$next[5:0]$12894 - attribute \src "libresoc.v:193238.13-193238.26" + attribute \src "libresoc.v:193011.3-193019.6" + wire width 6 $1\q_int$next[5:0]$12892 + attribute \src "libresoc.v:192988.13-192988.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:193251.17-193251.96" - wire width 6 $and$libresoc.v:193251$12883_Y - attribute \src "libresoc.v:193256.17-193256.96" - wire width 6 $and$libresoc.v:193256$12888_Y - attribute \src "libresoc.v:193253.18-193253.93" - wire width 6 $not$libresoc.v:193253$12885_Y - attribute \src "libresoc.v:193255.17-193255.92" - wire width 6 $not$libresoc.v:193255$12887_Y - attribute \src "libresoc.v:193258.17-193258.92" - wire width 6 $not$libresoc.v:193258$12890_Y - attribute \src "libresoc.v:193252.18-193252.98" - wire width 6 $or$libresoc.v:193252$12884_Y - attribute \src "libresoc.v:193254.18-193254.99" - wire width 6 $or$libresoc.v:193254$12886_Y - attribute \src "libresoc.v:193257.17-193257.97" - wire width 6 $or$libresoc.v:193257$12889_Y + attribute \src "libresoc.v:193001.17-193001.96" + wire width 6 $and$libresoc.v:193001$12881_Y + attribute \src "libresoc.v:193006.17-193006.96" + wire width 6 $and$libresoc.v:193006$12886_Y + attribute \src "libresoc.v:193003.18-193003.93" + wire width 6 $not$libresoc.v:193003$12883_Y + attribute \src "libresoc.v:193005.17-193005.92" + wire width 6 $not$libresoc.v:193005$12885_Y + attribute \src "libresoc.v:193008.17-193008.92" + wire width 6 $not$libresoc.v:193008$12888_Y + attribute \src "libresoc.v:193002.18-193002.98" + wire width 6 $or$libresoc.v:193002$12882_Y + attribute \src "libresoc.v:193004.18-193004.99" + wire width 6 $or$libresoc.v:193004$12884_Y + attribute \src "libresoc.v:193007.17-193007.97" + wire width 6 $or$libresoc.v:193007$12887_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -364856,11 +364582,11 @@ module \src_l$10 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193216.7-193216.15" + attribute \src "libresoc.v:192966.7-192966.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -364877,7 +364603,7 @@ module \src_l$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193251$12883 + cell $and $and$libresoc.v:193001$12881 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -364885,10 +364611,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193251$12883_Y + connect \Y $and$libresoc.v:193001$12881_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193256$12888 + cell $and $and$libresoc.v:193006$12886 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -364896,34 +364622,34 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193256$12888_Y + connect \Y $and$libresoc.v:193006$12886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193253$12885 + cell $not $not$libresoc.v:193003$12883 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:193253$12885_Y + connect \Y $not$libresoc.v:193003$12883_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193255$12887 + cell $not $not$libresoc.v:193005$12885 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:193255$12887_Y + connect \Y $not$libresoc.v:193005$12885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193258$12890 + cell $not $not$libresoc.v:193008$12888 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:193258$12890_Y + connect \Y $not$libresoc.v:193008$12888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193252$12884 + cell $or $or$libresoc.v:193002$12882 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -364931,10 +364657,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:193252$12884_Y + connect \Y $or$libresoc.v:193002$12882_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193254$12886 + cell $or $or$libresoc.v:193004$12884 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -364942,10 +364668,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:193254$12886_Y + connect \Y $or$libresoc.v:193004$12884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193257$12889 + cell $or $or$libresoc.v:193007$12887 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -364953,39 +364679,39 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:193257$12889_Y + connect \Y $or$libresoc.v:193007$12887_Y end - attribute \src "libresoc.v:193216.7-193216.20" - process $proc$libresoc.v:193216$12895 + attribute \src "libresoc.v:192966.7-192966.20" + process $proc$libresoc.v:192966$12893 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193238.13-193238.26" - process $proc$libresoc.v:193238$12896 + attribute \src "libresoc.v:192988.13-192988.26" + process $proc$libresoc.v:192988$12894 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:193259.3-193260.27" - process $proc$libresoc.v:193259$12891 + attribute \src "libresoc.v:193009.3-193010.27" + process $proc$libresoc.v:193009$12889 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:193261.3-193269.6" - process $proc$libresoc.v:193261$12892 + attribute \src "libresoc.v:193011.3-193019.6" + process $proc$libresoc.v:193011$12890 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$12893 $1\q_int$next[5:0]$12894 - attribute \src "libresoc.v:193262.5-193262.29" + assign $0\q_int$next[5:0]$12891 $1\q_int$next[5:0]$12892 + attribute \src "libresoc.v:193012.5-193012.29" switch \initial - attribute \src "libresoc.v:193262.9-193262.17" + attribute \src "libresoc.v:193012.9-193012.17" case 1'1 case end @@ -364994,56 +364720,56 @@ module \src_l$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$12894 6'000000 + assign $1\q_int$next[5:0]$12892 6'000000 case - assign $1\q_int$next[5:0]$12894 \$5 + assign $1\q_int$next[5:0]$12892 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$12893 + update \q_int$next $0\q_int$next[5:0]$12891 end - connect \$9 $and$libresoc.v:193251$12883_Y - connect \$11 $or$libresoc.v:193252$12884_Y - connect \$13 $not$libresoc.v:193253$12885_Y - connect \$15 $or$libresoc.v:193254$12886_Y - connect \$1 $not$libresoc.v:193255$12887_Y - connect \$3 $and$libresoc.v:193256$12888_Y - connect \$5 $or$libresoc.v:193257$12889_Y - connect \$7 $not$libresoc.v:193258$12890_Y + connect \$9 $and$libresoc.v:193001$12881_Y + connect \$11 $or$libresoc.v:193002$12882_Y + connect \$13 $not$libresoc.v:193003$12883_Y + connect \$15 $or$libresoc.v:193004$12884_Y + connect \$1 $not$libresoc.v:193005$12885_Y + connect \$3 $and$libresoc.v:193006$12886_Y + connect \$5 $or$libresoc.v:193007$12887_Y + connect \$7 $not$libresoc.v:193008$12888_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:193277.1-193335.10" +attribute \src "libresoc.v:193027.1-193085.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" attribute \generator "nMigen" module \src_l$101 - attribute \src "libresoc.v:193278.7-193278.20" + attribute \src "libresoc.v:193028.7-193028.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193323.3-193331.6" - wire width 3 $0\q_int$next[2:0]$12907 - attribute \src "libresoc.v:193321.3-193322.27" + attribute \src "libresoc.v:193073.3-193081.6" + wire width 3 $0\q_int$next[2:0]$12905 + attribute \src "libresoc.v:193071.3-193072.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:193323.3-193331.6" - wire width 3 $1\q_int$next[2:0]$12908 - attribute \src "libresoc.v:193300.13-193300.25" + attribute \src "libresoc.v:193073.3-193081.6" + wire width 3 $1\q_int$next[2:0]$12906 + attribute \src "libresoc.v:193050.13-193050.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:193313.17-193313.96" - wire width 3 $and$libresoc.v:193313$12897_Y - attribute \src "libresoc.v:193318.17-193318.96" - wire width 3 $and$libresoc.v:193318$12902_Y - attribute \src "libresoc.v:193315.18-193315.93" - wire width 3 $not$libresoc.v:193315$12899_Y - attribute \src "libresoc.v:193317.17-193317.92" - wire width 3 $not$libresoc.v:193317$12901_Y - attribute \src "libresoc.v:193320.17-193320.92" - wire width 3 $not$libresoc.v:193320$12904_Y - attribute \src "libresoc.v:193314.18-193314.98" - wire width 3 $or$libresoc.v:193314$12898_Y - attribute \src "libresoc.v:193316.18-193316.99" - wire width 3 $or$libresoc.v:193316$12900_Y - attribute \src "libresoc.v:193319.17-193319.97" - wire width 3 $or$libresoc.v:193319$12903_Y + attribute \src "libresoc.v:193063.17-193063.96" + wire width 3 $and$libresoc.v:193063$12895_Y + attribute \src "libresoc.v:193068.17-193068.96" + wire width 3 $and$libresoc.v:193068$12900_Y + attribute \src "libresoc.v:193065.18-193065.93" + wire width 3 $not$libresoc.v:193065$12897_Y + attribute \src "libresoc.v:193067.17-193067.92" + wire width 3 $not$libresoc.v:193067$12899_Y + attribute \src "libresoc.v:193070.17-193070.92" + wire width 3 $not$libresoc.v:193070$12902_Y + attribute \src "libresoc.v:193064.18-193064.98" + wire width 3 $or$libresoc.v:193064$12896_Y + attribute \src "libresoc.v:193066.18-193066.99" + wire width 3 $or$libresoc.v:193066$12898_Y + attribute \src "libresoc.v:193069.17-193069.97" + wire width 3 $or$libresoc.v:193069$12901_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -365060,11 +364786,11 @@ module \src_l$101 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193278.7-193278.15" + attribute \src "libresoc.v:193028.7-193028.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -365081,7 +364807,7 @@ module \src_l$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193313$12897 + cell $and $and$libresoc.v:193063$12895 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365089,10 +364815,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193313$12897_Y + connect \Y $and$libresoc.v:193063$12895_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193318$12902 + cell $and $and$libresoc.v:193068$12900 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365100,34 +364826,34 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193318$12902_Y + connect \Y $and$libresoc.v:193068$12900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193315$12899 + cell $not $not$libresoc.v:193065$12897 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:193315$12899_Y + connect \Y $not$libresoc.v:193065$12897_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193317$12901 + cell $not $not$libresoc.v:193067$12899 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:193317$12901_Y + connect \Y $not$libresoc.v:193067$12899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193320$12904 + cell $not $not$libresoc.v:193070$12902 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:193320$12904_Y + connect \Y $not$libresoc.v:193070$12902_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193314$12898 + cell $or $or$libresoc.v:193064$12896 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365135,10 +364861,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:193314$12898_Y + connect \Y $or$libresoc.v:193064$12896_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193316$12900 + cell $or $or$libresoc.v:193066$12898 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365146,10 +364872,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:193316$12900_Y + connect \Y $or$libresoc.v:193066$12898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193319$12903 + cell $or $or$libresoc.v:193069$12901 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365157,39 +364883,39 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:193319$12903_Y + connect \Y $or$libresoc.v:193069$12901_Y end - attribute \src "libresoc.v:193278.7-193278.20" - process $proc$libresoc.v:193278$12909 + attribute \src "libresoc.v:193028.7-193028.20" + process $proc$libresoc.v:193028$12907 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193300.13-193300.25" - process $proc$libresoc.v:193300$12910 + attribute \src "libresoc.v:193050.13-193050.25" + process $proc$libresoc.v:193050$12908 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:193321.3-193322.27" - process $proc$libresoc.v:193321$12905 + attribute \src "libresoc.v:193071.3-193072.27" + process $proc$libresoc.v:193071$12903 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:193323.3-193331.6" - process $proc$libresoc.v:193323$12906 + attribute \src "libresoc.v:193073.3-193081.6" + process $proc$libresoc.v:193073$12904 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$12907 $1\q_int$next[2:0]$12908 - attribute \src "libresoc.v:193324.5-193324.29" + assign $0\q_int$next[2:0]$12905 $1\q_int$next[2:0]$12906 + attribute \src "libresoc.v:193074.5-193074.29" switch \initial - attribute \src "libresoc.v:193324.9-193324.17" + attribute \src "libresoc.v:193074.9-193074.17" case 1'1 case end @@ -365198,56 +364924,56 @@ module \src_l$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$12908 3'000 + assign $1\q_int$next[2:0]$12906 3'000 case - assign $1\q_int$next[2:0]$12908 \$5 + assign $1\q_int$next[2:0]$12906 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$12907 + update \q_int$next $0\q_int$next[2:0]$12905 end - connect \$9 $and$libresoc.v:193313$12897_Y - connect \$11 $or$libresoc.v:193314$12898_Y - connect \$13 $not$libresoc.v:193315$12899_Y - connect \$15 $or$libresoc.v:193316$12900_Y - connect \$1 $not$libresoc.v:193317$12901_Y - connect \$3 $and$libresoc.v:193318$12902_Y - connect \$5 $or$libresoc.v:193319$12903_Y - connect \$7 $not$libresoc.v:193320$12904_Y + connect \$9 $and$libresoc.v:193063$12895_Y + connect \$11 $or$libresoc.v:193064$12896_Y + connect \$13 $not$libresoc.v:193065$12897_Y + connect \$15 $or$libresoc.v:193066$12898_Y + connect \$1 $not$libresoc.v:193067$12899_Y + connect \$3 $and$libresoc.v:193068$12900_Y + connect \$5 $or$libresoc.v:193069$12901_Y + connect \$7 $not$libresoc.v:193070$12902_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:193339.1-193397.10" +attribute \src "libresoc.v:193089.1-193147.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" attribute \generator "nMigen" module \src_l$119 - attribute \src "libresoc.v:193340.7-193340.20" + attribute \src "libresoc.v:193090.7-193090.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193385.3-193393.6" - wire width 5 $0\q_int$next[4:0]$12921 - attribute \src "libresoc.v:193383.3-193384.27" + attribute \src "libresoc.v:193135.3-193143.6" + wire width 5 $0\q_int$next[4:0]$12919 + attribute \src "libresoc.v:193133.3-193134.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:193385.3-193393.6" - wire width 5 $1\q_int$next[4:0]$12922 - attribute \src "libresoc.v:193362.13-193362.26" + attribute \src "libresoc.v:193135.3-193143.6" + wire width 5 $1\q_int$next[4:0]$12920 + attribute \src "libresoc.v:193112.13-193112.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:193375.17-193375.96" - wire width 5 $and$libresoc.v:193375$12911_Y - attribute \src "libresoc.v:193380.17-193380.96" - wire width 5 $and$libresoc.v:193380$12916_Y - attribute \src "libresoc.v:193377.18-193377.93" - wire width 5 $not$libresoc.v:193377$12913_Y - attribute \src "libresoc.v:193379.17-193379.92" - wire width 5 $not$libresoc.v:193379$12915_Y - attribute \src "libresoc.v:193382.17-193382.92" - wire width 5 $not$libresoc.v:193382$12918_Y - attribute \src "libresoc.v:193376.18-193376.98" - wire width 5 $or$libresoc.v:193376$12912_Y - attribute \src "libresoc.v:193378.18-193378.99" - wire width 5 $or$libresoc.v:193378$12914_Y - attribute \src "libresoc.v:193381.17-193381.97" - wire width 5 $or$libresoc.v:193381$12917_Y + attribute \src "libresoc.v:193125.17-193125.96" + wire width 5 $and$libresoc.v:193125$12909_Y + attribute \src "libresoc.v:193130.17-193130.96" + wire width 5 $and$libresoc.v:193130$12914_Y + attribute \src "libresoc.v:193127.18-193127.93" + wire width 5 $not$libresoc.v:193127$12911_Y + attribute \src "libresoc.v:193129.17-193129.92" + wire width 5 $not$libresoc.v:193129$12913_Y + attribute \src "libresoc.v:193132.17-193132.92" + wire width 5 $not$libresoc.v:193132$12916_Y + attribute \src "libresoc.v:193126.18-193126.98" + wire width 5 $or$libresoc.v:193126$12910_Y + attribute \src "libresoc.v:193128.18-193128.99" + wire width 5 $or$libresoc.v:193128$12912_Y + attribute \src "libresoc.v:193131.17-193131.97" + wire width 5 $or$libresoc.v:193131$12915_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -365264,11 +364990,11 @@ module \src_l$119 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193340.7-193340.15" + attribute \src "libresoc.v:193090.7-193090.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -365285,7 +365011,7 @@ module \src_l$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193375$12911 + cell $and $and$libresoc.v:193125$12909 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -365293,10 +365019,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193375$12911_Y + connect \Y $and$libresoc.v:193125$12909_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193380$12916 + cell $and $and$libresoc.v:193130$12914 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -365304,34 +365030,34 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193380$12916_Y + connect \Y $and$libresoc.v:193130$12914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193377$12913 + cell $not $not$libresoc.v:193127$12911 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src - connect \Y $not$libresoc.v:193377$12913_Y + connect \Y $not$libresoc.v:193127$12911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193379$12915 + cell $not $not$libresoc.v:193129$12913 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:193379$12915_Y + connect \Y $not$libresoc.v:193129$12913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193382$12918 + cell $not $not$libresoc.v:193132$12916 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:193382$12918_Y + connect \Y $not$libresoc.v:193132$12916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193376$12912 + cell $or $or$libresoc.v:193126$12910 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -365339,10 +365065,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:193376$12912_Y + connect \Y $or$libresoc.v:193126$12910_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193378$12914 + cell $or $or$libresoc.v:193128$12912 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -365350,10 +365076,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:193378$12914_Y + connect \Y $or$libresoc.v:193128$12912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193381$12917 + cell $or $or$libresoc.v:193131$12915 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -365361,39 +365087,39 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:193381$12917_Y + connect \Y $or$libresoc.v:193131$12915_Y end - attribute \src "libresoc.v:193340.7-193340.20" - process $proc$libresoc.v:193340$12923 + attribute \src "libresoc.v:193090.7-193090.20" + process $proc$libresoc.v:193090$12921 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193362.13-193362.26" - process $proc$libresoc.v:193362$12924 + attribute \src "libresoc.v:193112.13-193112.26" + process $proc$libresoc.v:193112$12922 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:193383.3-193384.27" - process $proc$libresoc.v:193383$12919 + attribute \src "libresoc.v:193133.3-193134.27" + process $proc$libresoc.v:193133$12917 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:193385.3-193393.6" - process $proc$libresoc.v:193385$12920 + attribute \src "libresoc.v:193135.3-193143.6" + process $proc$libresoc.v:193135$12918 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$12921 $1\q_int$next[4:0]$12922 - attribute \src "libresoc.v:193386.5-193386.29" + assign $0\q_int$next[4:0]$12919 $1\q_int$next[4:0]$12920 + attribute \src "libresoc.v:193136.5-193136.29" switch \initial - attribute \src "libresoc.v:193386.9-193386.17" + attribute \src "libresoc.v:193136.9-193136.17" case 1'1 case end @@ -365402,56 +365128,56 @@ module \src_l$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$12922 5'00000 + assign $1\q_int$next[4:0]$12920 5'00000 case - assign $1\q_int$next[4:0]$12922 \$5 + assign $1\q_int$next[4:0]$12920 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$12921 + update \q_int$next $0\q_int$next[4:0]$12919 end - connect \$9 $and$libresoc.v:193375$12911_Y - connect \$11 $or$libresoc.v:193376$12912_Y - connect \$13 $not$libresoc.v:193377$12913_Y - connect \$15 $or$libresoc.v:193378$12914_Y - connect \$1 $not$libresoc.v:193379$12915_Y - connect \$3 $and$libresoc.v:193380$12916_Y - connect \$5 $or$libresoc.v:193381$12917_Y - connect \$7 $not$libresoc.v:193382$12918_Y + connect \$9 $and$libresoc.v:193125$12909_Y + connect \$11 $or$libresoc.v:193126$12910_Y + connect \$13 $not$libresoc.v:193127$12911_Y + connect \$15 $or$libresoc.v:193128$12912_Y + connect \$1 $not$libresoc.v:193129$12913_Y + connect \$3 $and$libresoc.v:193130$12914_Y + connect \$5 $or$libresoc.v:193131$12915_Y + connect \$7 $not$libresoc.v:193132$12916_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:193401.1-193459.10" +attribute \src "libresoc.v:193151.1-193209.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" attribute \generator "nMigen" module \src_l$127 - attribute \src "libresoc.v:193402.7-193402.20" + attribute \src "libresoc.v:193152.7-193152.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193447.3-193455.6" - wire width 3 $0\q_int$next[2:0]$12935 - attribute \src "libresoc.v:193445.3-193446.27" + attribute \src "libresoc.v:193197.3-193205.6" + wire width 3 $0\q_int$next[2:0]$12933 + attribute \src "libresoc.v:193195.3-193196.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:193447.3-193455.6" - wire width 3 $1\q_int$next[2:0]$12936 - attribute \src "libresoc.v:193424.13-193424.25" + attribute \src "libresoc.v:193197.3-193205.6" + wire width 3 $1\q_int$next[2:0]$12934 + attribute \src "libresoc.v:193174.13-193174.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:193437.17-193437.96" - wire width 3 $and$libresoc.v:193437$12925_Y - attribute \src "libresoc.v:193442.17-193442.96" - wire width 3 $and$libresoc.v:193442$12930_Y - attribute \src "libresoc.v:193439.18-193439.93" - wire width 3 $not$libresoc.v:193439$12927_Y - attribute \src "libresoc.v:193441.17-193441.92" - wire width 3 $not$libresoc.v:193441$12929_Y - attribute \src "libresoc.v:193444.17-193444.92" - wire width 3 $not$libresoc.v:193444$12932_Y - attribute \src "libresoc.v:193438.18-193438.98" - wire width 3 $or$libresoc.v:193438$12926_Y - attribute \src "libresoc.v:193440.18-193440.99" - wire width 3 $or$libresoc.v:193440$12928_Y - attribute \src "libresoc.v:193443.17-193443.97" - wire width 3 $or$libresoc.v:193443$12931_Y + attribute \src "libresoc.v:193187.17-193187.96" + wire width 3 $and$libresoc.v:193187$12923_Y + attribute \src "libresoc.v:193192.17-193192.96" + wire width 3 $and$libresoc.v:193192$12928_Y + attribute \src "libresoc.v:193189.18-193189.93" + wire width 3 $not$libresoc.v:193189$12925_Y + attribute \src "libresoc.v:193191.17-193191.92" + wire width 3 $not$libresoc.v:193191$12927_Y + attribute \src "libresoc.v:193194.17-193194.92" + wire width 3 $not$libresoc.v:193194$12930_Y + attribute \src "libresoc.v:193188.18-193188.98" + wire width 3 $or$libresoc.v:193188$12924_Y + attribute \src "libresoc.v:193190.18-193190.99" + wire width 3 $or$libresoc.v:193190$12926_Y + attribute \src "libresoc.v:193193.17-193193.97" + wire width 3 $or$libresoc.v:193193$12929_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -365468,11 +365194,11 @@ module \src_l$127 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193402.7-193402.15" + attribute \src "libresoc.v:193152.7-193152.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -365489,7 +365215,7 @@ module \src_l$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193437$12925 + cell $and $and$libresoc.v:193187$12923 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365497,10 +365223,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193437$12925_Y + connect \Y $and$libresoc.v:193187$12923_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193442$12930 + cell $and $and$libresoc.v:193192$12928 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365508,34 +365234,34 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193442$12930_Y + connect \Y $and$libresoc.v:193192$12928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193439$12927 + cell $not $not$libresoc.v:193189$12925 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:193439$12927_Y + connect \Y $not$libresoc.v:193189$12925_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193441$12929 + cell $not $not$libresoc.v:193191$12927 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:193441$12929_Y + connect \Y $not$libresoc.v:193191$12927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193444$12932 + cell $not $not$libresoc.v:193194$12930 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:193444$12932_Y + connect \Y $not$libresoc.v:193194$12930_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193438$12926 + cell $or $or$libresoc.v:193188$12924 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365543,10 +365269,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:193438$12926_Y + connect \Y $or$libresoc.v:193188$12924_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193440$12928 + cell $or $or$libresoc.v:193190$12926 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365554,10 +365280,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:193440$12928_Y + connect \Y $or$libresoc.v:193190$12926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193443$12931 + cell $or $or$libresoc.v:193193$12929 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365565,39 +365291,39 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:193443$12931_Y + connect \Y $or$libresoc.v:193193$12929_Y end - attribute \src "libresoc.v:193402.7-193402.20" - process $proc$libresoc.v:193402$12937 + attribute \src "libresoc.v:193152.7-193152.20" + process $proc$libresoc.v:193152$12935 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193424.13-193424.25" - process $proc$libresoc.v:193424$12938 + attribute \src "libresoc.v:193174.13-193174.25" + process $proc$libresoc.v:193174$12936 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:193445.3-193446.27" - process $proc$libresoc.v:193445$12933 + attribute \src "libresoc.v:193195.3-193196.27" + process $proc$libresoc.v:193195$12931 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:193447.3-193455.6" - process $proc$libresoc.v:193447$12934 + attribute \src "libresoc.v:193197.3-193205.6" + process $proc$libresoc.v:193197$12932 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$12935 $1\q_int$next[2:0]$12936 - attribute \src "libresoc.v:193448.5-193448.29" + assign $0\q_int$next[2:0]$12933 $1\q_int$next[2:0]$12934 + attribute \src "libresoc.v:193198.5-193198.29" switch \initial - attribute \src "libresoc.v:193448.9-193448.17" + attribute \src "libresoc.v:193198.9-193198.17" case 1'1 case end @@ -365606,56 +365332,56 @@ module \src_l$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$12936 3'000 + assign $1\q_int$next[2:0]$12934 3'000 case - assign $1\q_int$next[2:0]$12936 \$5 + assign $1\q_int$next[2:0]$12934 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$12935 + update \q_int$next $0\q_int$next[2:0]$12933 end - connect \$9 $and$libresoc.v:193437$12925_Y - connect \$11 $or$libresoc.v:193438$12926_Y - connect \$13 $not$libresoc.v:193439$12927_Y - connect \$15 $or$libresoc.v:193440$12928_Y - connect \$1 $not$libresoc.v:193441$12929_Y - connect \$3 $and$libresoc.v:193442$12930_Y - connect \$5 $or$libresoc.v:193443$12931_Y - connect \$7 $not$libresoc.v:193444$12932_Y + connect \$9 $and$libresoc.v:193187$12923_Y + connect \$11 $or$libresoc.v:193188$12924_Y + connect \$13 $not$libresoc.v:193189$12925_Y + connect \$15 $or$libresoc.v:193190$12926_Y + connect \$1 $not$libresoc.v:193191$12927_Y + connect \$3 $and$libresoc.v:193192$12928_Y + connect \$5 $or$libresoc.v:193193$12929_Y + connect \$7 $not$libresoc.v:193194$12930_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:193463.1-193521.10" +attribute \src "libresoc.v:193213.1-193271.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" attribute \generator "nMigen" module \src_l$23 - attribute \src "libresoc.v:193464.7-193464.20" + attribute \src "libresoc.v:193214.7-193214.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193509.3-193517.6" - wire width 3 $0\q_int$next[2:0]$12949 - attribute \src "libresoc.v:193507.3-193508.27" + attribute \src "libresoc.v:193259.3-193267.6" + wire width 3 $0\q_int$next[2:0]$12947 + attribute \src "libresoc.v:193257.3-193258.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:193509.3-193517.6" - wire width 3 $1\q_int$next[2:0]$12950 - attribute \src "libresoc.v:193486.13-193486.25" + attribute \src "libresoc.v:193259.3-193267.6" + wire width 3 $1\q_int$next[2:0]$12948 + attribute \src "libresoc.v:193236.13-193236.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:193499.17-193499.96" - wire width 3 $and$libresoc.v:193499$12939_Y - attribute \src "libresoc.v:193504.17-193504.96" - wire width 3 $and$libresoc.v:193504$12944_Y - attribute \src "libresoc.v:193501.18-193501.93" - wire width 3 $not$libresoc.v:193501$12941_Y - attribute \src "libresoc.v:193503.17-193503.92" - wire width 3 $not$libresoc.v:193503$12943_Y - attribute \src "libresoc.v:193506.17-193506.92" - wire width 3 $not$libresoc.v:193506$12946_Y - attribute \src "libresoc.v:193500.18-193500.98" - wire width 3 $or$libresoc.v:193500$12940_Y - attribute \src "libresoc.v:193502.18-193502.99" - wire width 3 $or$libresoc.v:193502$12942_Y - attribute \src "libresoc.v:193505.17-193505.97" - wire width 3 $or$libresoc.v:193505$12945_Y + attribute \src "libresoc.v:193249.17-193249.96" + wire width 3 $and$libresoc.v:193249$12937_Y + attribute \src "libresoc.v:193254.17-193254.96" + wire width 3 $and$libresoc.v:193254$12942_Y + attribute \src "libresoc.v:193251.18-193251.93" + wire width 3 $not$libresoc.v:193251$12939_Y + attribute \src "libresoc.v:193253.17-193253.92" + wire width 3 $not$libresoc.v:193253$12941_Y + attribute \src "libresoc.v:193256.17-193256.92" + wire width 3 $not$libresoc.v:193256$12944_Y + attribute \src "libresoc.v:193250.18-193250.98" + wire width 3 $or$libresoc.v:193250$12938_Y + attribute \src "libresoc.v:193252.18-193252.99" + wire width 3 $or$libresoc.v:193252$12940_Y + attribute \src "libresoc.v:193255.17-193255.97" + wire width 3 $or$libresoc.v:193255$12943_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -365672,11 +365398,11 @@ module \src_l$23 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193464.7-193464.15" + attribute \src "libresoc.v:193214.7-193214.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -365693,7 +365419,7 @@ module \src_l$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193499$12939 + cell $and $and$libresoc.v:193249$12937 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365701,10 +365427,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193499$12939_Y + connect \Y $and$libresoc.v:193249$12937_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193504$12944 + cell $and $and$libresoc.v:193254$12942 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365712,34 +365438,34 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193504$12944_Y + connect \Y $and$libresoc.v:193254$12942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193501$12941 + cell $not $not$libresoc.v:193251$12939 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:193501$12941_Y + connect \Y $not$libresoc.v:193251$12939_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193503$12943 + cell $not $not$libresoc.v:193253$12941 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:193503$12943_Y + connect \Y $not$libresoc.v:193253$12941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193506$12946 + cell $not $not$libresoc.v:193256$12944 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:193506$12946_Y + connect \Y $not$libresoc.v:193256$12944_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193500$12940 + cell $or $or$libresoc.v:193250$12938 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365747,10 +365473,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:193500$12940_Y + connect \Y $or$libresoc.v:193250$12938_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193502$12942 + cell $or $or$libresoc.v:193252$12940 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365758,10 +365484,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:193502$12942_Y + connect \Y $or$libresoc.v:193252$12940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193505$12945 + cell $or $or$libresoc.v:193255$12943 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -365769,39 +365495,39 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:193505$12945_Y + connect \Y $or$libresoc.v:193255$12943_Y end - attribute \src "libresoc.v:193464.7-193464.20" - process $proc$libresoc.v:193464$12951 + attribute \src "libresoc.v:193214.7-193214.20" + process $proc$libresoc.v:193214$12949 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193486.13-193486.25" - process $proc$libresoc.v:193486$12952 + attribute \src "libresoc.v:193236.13-193236.25" + process $proc$libresoc.v:193236$12950 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:193507.3-193508.27" - process $proc$libresoc.v:193507$12947 + attribute \src "libresoc.v:193257.3-193258.27" + process $proc$libresoc.v:193257$12945 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:193509.3-193517.6" - process $proc$libresoc.v:193509$12948 + attribute \src "libresoc.v:193259.3-193267.6" + process $proc$libresoc.v:193259$12946 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$12949 $1\q_int$next[2:0]$12950 - attribute \src "libresoc.v:193510.5-193510.29" + assign $0\q_int$next[2:0]$12947 $1\q_int$next[2:0]$12948 + attribute \src "libresoc.v:193260.5-193260.29" switch \initial - attribute \src "libresoc.v:193510.9-193510.17" + attribute \src "libresoc.v:193260.9-193260.17" case 1'1 case end @@ -365810,56 +365536,56 @@ module \src_l$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$12950 3'000 + assign $1\q_int$next[2:0]$12948 3'000 case - assign $1\q_int$next[2:0]$12950 \$5 + assign $1\q_int$next[2:0]$12948 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$12949 + update \q_int$next $0\q_int$next[2:0]$12947 end - connect \$9 $and$libresoc.v:193499$12939_Y - connect \$11 $or$libresoc.v:193500$12940_Y - connect \$13 $not$libresoc.v:193501$12941_Y - connect \$15 $or$libresoc.v:193502$12942_Y - connect \$1 $not$libresoc.v:193503$12943_Y - connect \$3 $and$libresoc.v:193504$12944_Y - connect \$5 $or$libresoc.v:193505$12945_Y - connect \$7 $not$libresoc.v:193506$12946_Y + connect \$9 $and$libresoc.v:193249$12937_Y + connect \$11 $or$libresoc.v:193250$12938_Y + connect \$13 $not$libresoc.v:193251$12939_Y + connect \$15 $or$libresoc.v:193252$12940_Y + connect \$1 $not$libresoc.v:193253$12941_Y + connect \$3 $and$libresoc.v:193254$12942_Y + connect \$5 $or$libresoc.v:193255$12943_Y + connect \$7 $not$libresoc.v:193256$12944_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:193525.1-193583.10" +attribute \src "libresoc.v:193275.1-193333.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" attribute \generator "nMigen" module \src_l$39 - attribute \src "libresoc.v:193526.7-193526.20" + attribute \src "libresoc.v:193276.7-193276.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193571.3-193579.6" - wire width 4 $0\q_int$next[3:0]$12963 - attribute \src "libresoc.v:193569.3-193570.27" + attribute \src "libresoc.v:193321.3-193329.6" + wire width 4 $0\q_int$next[3:0]$12961 + attribute \src "libresoc.v:193319.3-193320.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:193571.3-193579.6" - wire width 4 $1\q_int$next[3:0]$12964 - attribute \src "libresoc.v:193548.13-193548.25" + attribute \src "libresoc.v:193321.3-193329.6" + wire width 4 $1\q_int$next[3:0]$12962 + attribute \src "libresoc.v:193298.13-193298.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:193561.17-193561.96" - wire width 4 $and$libresoc.v:193561$12953_Y - attribute \src "libresoc.v:193566.17-193566.96" - wire width 4 $and$libresoc.v:193566$12958_Y - attribute \src "libresoc.v:193563.18-193563.93" - wire width 4 $not$libresoc.v:193563$12955_Y - attribute \src "libresoc.v:193565.17-193565.92" - wire width 4 $not$libresoc.v:193565$12957_Y - attribute \src "libresoc.v:193568.17-193568.92" - wire width 4 $not$libresoc.v:193568$12960_Y - attribute \src "libresoc.v:193562.18-193562.98" - wire width 4 $or$libresoc.v:193562$12954_Y - attribute \src "libresoc.v:193564.18-193564.99" - wire width 4 $or$libresoc.v:193564$12956_Y - attribute \src "libresoc.v:193567.17-193567.97" - wire width 4 $or$libresoc.v:193567$12959_Y + attribute \src "libresoc.v:193311.17-193311.96" + wire width 4 $and$libresoc.v:193311$12951_Y + attribute \src "libresoc.v:193316.17-193316.96" + wire width 4 $and$libresoc.v:193316$12956_Y + attribute \src "libresoc.v:193313.18-193313.93" + wire width 4 $not$libresoc.v:193313$12953_Y + attribute \src "libresoc.v:193315.17-193315.92" + wire width 4 $not$libresoc.v:193315$12955_Y + attribute \src "libresoc.v:193318.17-193318.92" + wire width 4 $not$libresoc.v:193318$12958_Y + attribute \src "libresoc.v:193312.18-193312.98" + wire width 4 $or$libresoc.v:193312$12952_Y + attribute \src "libresoc.v:193314.18-193314.99" + wire width 4 $or$libresoc.v:193314$12954_Y + attribute \src "libresoc.v:193317.17-193317.97" + wire width 4 $or$libresoc.v:193317$12957_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -365876,11 +365602,11 @@ module \src_l$39 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193526.7-193526.15" + attribute \src "libresoc.v:193276.7-193276.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -365897,7 +365623,7 @@ module \src_l$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193561$12953 + cell $and $and$libresoc.v:193311$12951 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -365905,10 +365631,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193561$12953_Y + connect \Y $and$libresoc.v:193311$12951_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193566$12958 + cell $and $and$libresoc.v:193316$12956 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -365916,34 +365642,34 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193566$12958_Y + connect \Y $and$libresoc.v:193316$12956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193563$12955 + cell $not $not$libresoc.v:193313$12953 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:193563$12955_Y + connect \Y $not$libresoc.v:193313$12953_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193565$12957 + cell $not $not$libresoc.v:193315$12955 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:193565$12957_Y + connect \Y $not$libresoc.v:193315$12955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193568$12960 + cell $not $not$libresoc.v:193318$12958 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:193568$12960_Y + connect \Y $not$libresoc.v:193318$12958_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193562$12954 + cell $or $or$libresoc.v:193312$12952 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -365951,10 +365677,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:193562$12954_Y + connect \Y $or$libresoc.v:193312$12952_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193564$12956 + cell $or $or$libresoc.v:193314$12954 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -365962,10 +365688,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:193564$12956_Y + connect \Y $or$libresoc.v:193314$12954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193567$12959 + cell $or $or$libresoc.v:193317$12957 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -365973,39 +365699,39 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:193567$12959_Y + connect \Y $or$libresoc.v:193317$12957_Y end - attribute \src "libresoc.v:193526.7-193526.20" - process $proc$libresoc.v:193526$12965 + attribute \src "libresoc.v:193276.7-193276.20" + process $proc$libresoc.v:193276$12963 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193548.13-193548.25" - process $proc$libresoc.v:193548$12966 + attribute \src "libresoc.v:193298.13-193298.25" + process $proc$libresoc.v:193298$12964 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:193569.3-193570.27" - process $proc$libresoc.v:193569$12961 + attribute \src "libresoc.v:193319.3-193320.27" + process $proc$libresoc.v:193319$12959 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:193571.3-193579.6" - process $proc$libresoc.v:193571$12962 + attribute \src "libresoc.v:193321.3-193329.6" + process $proc$libresoc.v:193321$12960 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$12963 $1\q_int$next[3:0]$12964 - attribute \src "libresoc.v:193572.5-193572.29" + assign $0\q_int$next[3:0]$12961 $1\q_int$next[3:0]$12962 + attribute \src "libresoc.v:193322.5-193322.29" switch \initial - attribute \src "libresoc.v:193572.9-193572.17" + attribute \src "libresoc.v:193322.9-193322.17" case 1'1 case end @@ -366014,56 +365740,56 @@ module \src_l$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$12964 4'0000 + assign $1\q_int$next[3:0]$12962 4'0000 case - assign $1\q_int$next[3:0]$12964 \$5 + assign $1\q_int$next[3:0]$12962 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$12963 + update \q_int$next $0\q_int$next[3:0]$12961 end - connect \$9 $and$libresoc.v:193561$12953_Y - connect \$11 $or$libresoc.v:193562$12954_Y - connect \$13 $not$libresoc.v:193563$12955_Y - connect \$15 $or$libresoc.v:193564$12956_Y - connect \$1 $not$libresoc.v:193565$12957_Y - connect \$3 $and$libresoc.v:193566$12958_Y - connect \$5 $or$libresoc.v:193567$12959_Y - connect \$7 $not$libresoc.v:193568$12960_Y + connect \$9 $and$libresoc.v:193311$12951_Y + connect \$11 $or$libresoc.v:193312$12952_Y + connect \$13 $not$libresoc.v:193313$12953_Y + connect \$15 $or$libresoc.v:193314$12954_Y + connect \$1 $not$libresoc.v:193315$12955_Y + connect \$3 $and$libresoc.v:193316$12956_Y + connect \$5 $or$libresoc.v:193317$12957_Y + connect \$7 $not$libresoc.v:193318$12958_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:193587.1-193645.10" +attribute \src "libresoc.v:193337.1-193395.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" attribute \generator "nMigen" module \src_l$55 - attribute \src "libresoc.v:193588.7-193588.20" + attribute \src "libresoc.v:193338.7-193338.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193633.3-193641.6" - wire width 3 $0\q_int$next[2:0]$12977 - attribute \src "libresoc.v:193631.3-193632.27" + attribute \src "libresoc.v:193383.3-193391.6" + wire width 3 $0\q_int$next[2:0]$12975 + attribute \src "libresoc.v:193381.3-193382.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:193633.3-193641.6" - wire width 3 $1\q_int$next[2:0]$12978 - attribute \src "libresoc.v:193610.13-193610.25" + attribute \src "libresoc.v:193383.3-193391.6" + wire width 3 $1\q_int$next[2:0]$12976 + attribute \src "libresoc.v:193360.13-193360.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:193623.17-193623.96" - wire width 3 $and$libresoc.v:193623$12967_Y - attribute \src "libresoc.v:193628.17-193628.96" - wire width 3 $and$libresoc.v:193628$12972_Y - attribute \src "libresoc.v:193625.18-193625.93" - wire width 3 $not$libresoc.v:193625$12969_Y - attribute \src "libresoc.v:193627.17-193627.92" - wire width 3 $not$libresoc.v:193627$12971_Y - attribute \src "libresoc.v:193630.17-193630.92" - wire width 3 $not$libresoc.v:193630$12974_Y - attribute \src "libresoc.v:193624.18-193624.98" - wire width 3 $or$libresoc.v:193624$12968_Y - attribute \src "libresoc.v:193626.18-193626.99" - wire width 3 $or$libresoc.v:193626$12970_Y - attribute \src "libresoc.v:193629.17-193629.97" - wire width 3 $or$libresoc.v:193629$12973_Y + attribute \src "libresoc.v:193373.17-193373.96" + wire width 3 $and$libresoc.v:193373$12965_Y + attribute \src "libresoc.v:193378.17-193378.96" + wire width 3 $and$libresoc.v:193378$12970_Y + attribute \src "libresoc.v:193375.18-193375.93" + wire width 3 $not$libresoc.v:193375$12967_Y + attribute \src "libresoc.v:193377.17-193377.92" + wire width 3 $not$libresoc.v:193377$12969_Y + attribute \src "libresoc.v:193380.17-193380.92" + wire width 3 $not$libresoc.v:193380$12972_Y + attribute \src "libresoc.v:193374.18-193374.98" + wire width 3 $or$libresoc.v:193374$12966_Y + attribute \src "libresoc.v:193376.18-193376.99" + wire width 3 $or$libresoc.v:193376$12968_Y + attribute \src "libresoc.v:193379.17-193379.97" + wire width 3 $or$libresoc.v:193379$12971_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -366080,11 +365806,11 @@ module \src_l$55 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193588.7-193588.15" + attribute \src "libresoc.v:193338.7-193338.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -366101,7 +365827,7 @@ module \src_l$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193623$12967 + cell $and $and$libresoc.v:193373$12965 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -366109,10 +365835,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193623$12967_Y + connect \Y $and$libresoc.v:193373$12965_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193628$12972 + cell $and $and$libresoc.v:193378$12970 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -366120,34 +365846,34 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193628$12972_Y + connect \Y $and$libresoc.v:193378$12970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193625$12969 + cell $not $not$libresoc.v:193375$12967 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:193625$12969_Y + connect \Y $not$libresoc.v:193375$12967_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193627$12971 + cell $not $not$libresoc.v:193377$12969 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:193627$12971_Y + connect \Y $not$libresoc.v:193377$12969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193630$12974 + cell $not $not$libresoc.v:193380$12972 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:193630$12974_Y + connect \Y $not$libresoc.v:193380$12972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193624$12968 + cell $or $or$libresoc.v:193374$12966 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -366155,10 +365881,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:193624$12968_Y + connect \Y $or$libresoc.v:193374$12966_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193626$12970 + cell $or $or$libresoc.v:193376$12968 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -366166,10 +365892,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:193626$12970_Y + connect \Y $or$libresoc.v:193376$12968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193629$12973 + cell $or $or$libresoc.v:193379$12971 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -366177,39 +365903,39 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:193629$12973_Y + connect \Y $or$libresoc.v:193379$12971_Y end - attribute \src "libresoc.v:193588.7-193588.20" - process $proc$libresoc.v:193588$12979 + attribute \src "libresoc.v:193338.7-193338.20" + process $proc$libresoc.v:193338$12977 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193610.13-193610.25" - process $proc$libresoc.v:193610$12980 + attribute \src "libresoc.v:193360.13-193360.25" + process $proc$libresoc.v:193360$12978 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:193631.3-193632.27" - process $proc$libresoc.v:193631$12975 + attribute \src "libresoc.v:193381.3-193382.27" + process $proc$libresoc.v:193381$12973 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:193633.3-193641.6" - process $proc$libresoc.v:193633$12976 + attribute \src "libresoc.v:193383.3-193391.6" + process $proc$libresoc.v:193383$12974 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$12977 $1\q_int$next[2:0]$12978 - attribute \src "libresoc.v:193634.5-193634.29" + assign $0\q_int$next[2:0]$12975 $1\q_int$next[2:0]$12976 + attribute \src "libresoc.v:193384.5-193384.29" switch \initial - attribute \src "libresoc.v:193634.9-193634.17" + attribute \src "libresoc.v:193384.9-193384.17" case 1'1 case end @@ -366218,56 +365944,56 @@ module \src_l$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$12978 3'000 + assign $1\q_int$next[2:0]$12976 3'000 case - assign $1\q_int$next[2:0]$12978 \$5 + assign $1\q_int$next[2:0]$12976 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$12977 + update \q_int$next $0\q_int$next[2:0]$12975 end - connect \$9 $and$libresoc.v:193623$12967_Y - connect \$11 $or$libresoc.v:193624$12968_Y - connect \$13 $not$libresoc.v:193625$12969_Y - connect \$15 $or$libresoc.v:193626$12970_Y - connect \$1 $not$libresoc.v:193627$12971_Y - connect \$3 $and$libresoc.v:193628$12972_Y - connect \$5 $or$libresoc.v:193629$12973_Y - connect \$7 $not$libresoc.v:193630$12974_Y + connect \$9 $and$libresoc.v:193373$12965_Y + connect \$11 $or$libresoc.v:193374$12966_Y + connect \$13 $not$libresoc.v:193375$12967_Y + connect \$15 $or$libresoc.v:193376$12968_Y + connect \$1 $not$libresoc.v:193377$12969_Y + connect \$3 $and$libresoc.v:193378$12970_Y + connect \$5 $or$libresoc.v:193379$12971_Y + connect \$7 $not$libresoc.v:193380$12972_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:193649.1-193707.10" +attribute \src "libresoc.v:193399.1-193457.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" attribute \generator "nMigen" module \src_l$67 - attribute \src "libresoc.v:193650.7-193650.20" + attribute \src "libresoc.v:193400.7-193400.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193695.3-193703.6" - wire width 6 $0\q_int$next[5:0]$12991 - attribute \src "libresoc.v:193693.3-193694.27" + attribute \src "libresoc.v:193445.3-193453.6" + wire width 6 $0\q_int$next[5:0]$12989 + attribute \src "libresoc.v:193443.3-193444.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:193695.3-193703.6" - wire width 6 $1\q_int$next[5:0]$12992 - attribute \src "libresoc.v:193672.13-193672.26" + attribute \src "libresoc.v:193445.3-193453.6" + wire width 6 $1\q_int$next[5:0]$12990 + attribute \src "libresoc.v:193422.13-193422.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:193685.17-193685.96" - wire width 6 $and$libresoc.v:193685$12981_Y - attribute \src "libresoc.v:193690.17-193690.96" - wire width 6 $and$libresoc.v:193690$12986_Y - attribute \src "libresoc.v:193687.18-193687.93" - wire width 6 $not$libresoc.v:193687$12983_Y - attribute \src "libresoc.v:193689.17-193689.92" - wire width 6 $not$libresoc.v:193689$12985_Y - attribute \src "libresoc.v:193692.17-193692.92" - wire width 6 $not$libresoc.v:193692$12988_Y - attribute \src "libresoc.v:193686.18-193686.98" - wire width 6 $or$libresoc.v:193686$12982_Y - attribute \src "libresoc.v:193688.18-193688.99" - wire width 6 $or$libresoc.v:193688$12984_Y - attribute \src "libresoc.v:193691.17-193691.97" - wire width 6 $or$libresoc.v:193691$12987_Y + attribute \src "libresoc.v:193435.17-193435.96" + wire width 6 $and$libresoc.v:193435$12979_Y + attribute \src "libresoc.v:193440.17-193440.96" + wire width 6 $and$libresoc.v:193440$12984_Y + attribute \src "libresoc.v:193437.18-193437.93" + wire width 6 $not$libresoc.v:193437$12981_Y + attribute \src "libresoc.v:193439.17-193439.92" + wire width 6 $not$libresoc.v:193439$12983_Y + attribute \src "libresoc.v:193442.17-193442.92" + wire width 6 $not$libresoc.v:193442$12986_Y + attribute \src "libresoc.v:193436.18-193436.98" + wire width 6 $or$libresoc.v:193436$12980_Y + attribute \src "libresoc.v:193438.18-193438.99" + wire width 6 $or$libresoc.v:193438$12982_Y + attribute \src "libresoc.v:193441.17-193441.97" + wire width 6 $or$libresoc.v:193441$12985_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -366284,11 +366010,11 @@ module \src_l$67 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193650.7-193650.15" + attribute \src "libresoc.v:193400.7-193400.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -366305,7 +366031,7 @@ module \src_l$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193685$12981 + cell $and $and$libresoc.v:193435$12979 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -366313,10 +366039,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193685$12981_Y + connect \Y $and$libresoc.v:193435$12979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193690$12986 + cell $and $and$libresoc.v:193440$12984 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -366324,34 +366050,34 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193690$12986_Y + connect \Y $and$libresoc.v:193440$12984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193687$12983 + cell $not $not$libresoc.v:193437$12981 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:193687$12983_Y + connect \Y $not$libresoc.v:193437$12981_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193689$12985 + cell $not $not$libresoc.v:193439$12983 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:193689$12985_Y + connect \Y $not$libresoc.v:193439$12983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193692$12988 + cell $not $not$libresoc.v:193442$12986 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:193692$12988_Y + connect \Y $not$libresoc.v:193442$12986_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193686$12982 + cell $or $or$libresoc.v:193436$12980 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -366359,10 +366085,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:193686$12982_Y + connect \Y $or$libresoc.v:193436$12980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193688$12984 + cell $or $or$libresoc.v:193438$12982 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -366370,10 +366096,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:193688$12984_Y + connect \Y $or$libresoc.v:193438$12982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193691$12987 + cell $or $or$libresoc.v:193441$12985 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -366381,39 +366107,39 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:193691$12987_Y + connect \Y $or$libresoc.v:193441$12985_Y end - attribute \src "libresoc.v:193650.7-193650.20" - process $proc$libresoc.v:193650$12993 + attribute \src "libresoc.v:193400.7-193400.20" + process $proc$libresoc.v:193400$12991 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193672.13-193672.26" - process $proc$libresoc.v:193672$12994 + attribute \src "libresoc.v:193422.13-193422.26" + process $proc$libresoc.v:193422$12992 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:193693.3-193694.27" - process $proc$libresoc.v:193693$12989 + attribute \src "libresoc.v:193443.3-193444.27" + process $proc$libresoc.v:193443$12987 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:193695.3-193703.6" - process $proc$libresoc.v:193695$12990 + attribute \src "libresoc.v:193445.3-193453.6" + process $proc$libresoc.v:193445$12988 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$12991 $1\q_int$next[5:0]$12992 - attribute \src "libresoc.v:193696.5-193696.29" + assign $0\q_int$next[5:0]$12989 $1\q_int$next[5:0]$12990 + attribute \src "libresoc.v:193446.5-193446.29" switch \initial - attribute \src "libresoc.v:193696.9-193696.17" + attribute \src "libresoc.v:193446.9-193446.17" case 1'1 case end @@ -366422,56 +366148,56 @@ module \src_l$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$12992 6'000000 + assign $1\q_int$next[5:0]$12990 6'000000 case - assign $1\q_int$next[5:0]$12992 \$5 + assign $1\q_int$next[5:0]$12990 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$12991 + update \q_int$next $0\q_int$next[5:0]$12989 end - connect \$9 $and$libresoc.v:193685$12981_Y - connect \$11 $or$libresoc.v:193686$12982_Y - connect \$13 $not$libresoc.v:193687$12983_Y - connect \$15 $or$libresoc.v:193688$12984_Y - connect \$1 $not$libresoc.v:193689$12985_Y - connect \$3 $and$libresoc.v:193690$12986_Y - connect \$5 $or$libresoc.v:193691$12987_Y - connect \$7 $not$libresoc.v:193692$12988_Y + connect \$9 $and$libresoc.v:193435$12979_Y + connect \$11 $or$libresoc.v:193436$12980_Y + connect \$13 $not$libresoc.v:193437$12981_Y + connect \$15 $or$libresoc.v:193438$12982_Y + connect \$1 $not$libresoc.v:193439$12983_Y + connect \$3 $and$libresoc.v:193440$12984_Y + connect \$5 $or$libresoc.v:193441$12985_Y + connect \$7 $not$libresoc.v:193442$12986_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:193711.1-193769.10" +attribute \src "libresoc.v:193461.1-193519.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" attribute \generator "nMigen" module \src_l$84 - attribute \src "libresoc.v:193712.7-193712.20" + attribute \src "libresoc.v:193462.7-193462.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193757.3-193765.6" - wire width 3 $0\q_int$next[2:0]$13005 - attribute \src "libresoc.v:193755.3-193756.27" + attribute \src "libresoc.v:193507.3-193515.6" + wire width 3 $0\q_int$next[2:0]$13003 + attribute \src "libresoc.v:193505.3-193506.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:193757.3-193765.6" - wire width 3 $1\q_int$next[2:0]$13006 - attribute \src "libresoc.v:193734.13-193734.25" + attribute \src "libresoc.v:193507.3-193515.6" + wire width 3 $1\q_int$next[2:0]$13004 + attribute \src "libresoc.v:193484.13-193484.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:193747.17-193747.96" - wire width 3 $and$libresoc.v:193747$12995_Y - attribute \src "libresoc.v:193752.17-193752.96" - wire width 3 $and$libresoc.v:193752$13000_Y - attribute \src "libresoc.v:193749.18-193749.93" - wire width 3 $not$libresoc.v:193749$12997_Y - attribute \src "libresoc.v:193751.17-193751.92" - wire width 3 $not$libresoc.v:193751$12999_Y - attribute \src "libresoc.v:193754.17-193754.92" - wire width 3 $not$libresoc.v:193754$13002_Y - attribute \src "libresoc.v:193748.18-193748.98" - wire width 3 $or$libresoc.v:193748$12996_Y - attribute \src "libresoc.v:193750.18-193750.99" - wire width 3 $or$libresoc.v:193750$12998_Y - attribute \src "libresoc.v:193753.17-193753.97" - wire width 3 $or$libresoc.v:193753$13001_Y + attribute \src "libresoc.v:193497.17-193497.96" + wire width 3 $and$libresoc.v:193497$12993_Y + attribute \src "libresoc.v:193502.17-193502.96" + wire width 3 $and$libresoc.v:193502$12998_Y + attribute \src "libresoc.v:193499.18-193499.93" + wire width 3 $not$libresoc.v:193499$12995_Y + attribute \src "libresoc.v:193501.17-193501.92" + wire width 3 $not$libresoc.v:193501$12997_Y + attribute \src "libresoc.v:193504.17-193504.92" + wire width 3 $not$libresoc.v:193504$13000_Y + attribute \src "libresoc.v:193498.18-193498.98" + wire width 3 $or$libresoc.v:193498$12994_Y + attribute \src "libresoc.v:193500.18-193500.99" + wire width 3 $or$libresoc.v:193500$12996_Y + attribute \src "libresoc.v:193503.17-193503.97" + wire width 3 $or$libresoc.v:193503$12999_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -366488,11 +366214,11 @@ module \src_l$84 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193712.7-193712.15" + attribute \src "libresoc.v:193462.7-193462.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -366509,7 +366235,7 @@ module \src_l$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193747$12995 + cell $and $and$libresoc.v:193497$12993 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -366517,10 +366243,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193747$12995_Y + connect \Y $and$libresoc.v:193497$12993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193752$13000 + cell $and $and$libresoc.v:193502$12998 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -366528,34 +366254,34 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193752$13000_Y + connect \Y $and$libresoc.v:193502$12998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193749$12997 + cell $not $not$libresoc.v:193499$12995 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:193749$12997_Y + connect \Y $not$libresoc.v:193499$12995_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193751$12999 + cell $not $not$libresoc.v:193501$12997 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:193751$12999_Y + connect \Y $not$libresoc.v:193501$12997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193754$13002 + cell $not $not$libresoc.v:193504$13000 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:193754$13002_Y + connect \Y $not$libresoc.v:193504$13000_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193748$12996 + cell $or $or$libresoc.v:193498$12994 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -366563,10 +366289,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:193748$12996_Y + connect \Y $or$libresoc.v:193498$12994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193750$12998 + cell $or $or$libresoc.v:193500$12996 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -366574,10 +366300,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:193750$12998_Y + connect \Y $or$libresoc.v:193500$12996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193753$13001 + cell $or $or$libresoc.v:193503$12999 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -366585,39 +366311,39 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:193753$13001_Y + connect \Y $or$libresoc.v:193503$12999_Y end - attribute \src "libresoc.v:193712.7-193712.20" - process $proc$libresoc.v:193712$13007 + attribute \src "libresoc.v:193462.7-193462.20" + process $proc$libresoc.v:193462$13005 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193734.13-193734.25" - process $proc$libresoc.v:193734$13008 + attribute \src "libresoc.v:193484.13-193484.25" + process $proc$libresoc.v:193484$13006 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:193755.3-193756.27" - process $proc$libresoc.v:193755$13003 + attribute \src "libresoc.v:193505.3-193506.27" + process $proc$libresoc.v:193505$13001 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:193757.3-193765.6" - process $proc$libresoc.v:193757$13004 + attribute \src "libresoc.v:193507.3-193515.6" + process $proc$libresoc.v:193507$13002 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13005 $1\q_int$next[2:0]$13006 - attribute \src "libresoc.v:193758.5-193758.29" + assign $0\q_int$next[2:0]$13003 $1\q_int$next[2:0]$13004 + attribute \src "libresoc.v:193508.5-193508.29" switch \initial - attribute \src "libresoc.v:193758.9-193758.17" + attribute \src "libresoc.v:193508.9-193508.17" case 1'1 case end @@ -366626,56 +366352,56 @@ module \src_l$84 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13006 3'000 + assign $1\q_int$next[2:0]$13004 3'000 case - assign $1\q_int$next[2:0]$13006 \$5 + assign $1\q_int$next[2:0]$13004 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13005 + update \q_int$next $0\q_int$next[2:0]$13003 end - connect \$9 $and$libresoc.v:193747$12995_Y - connect \$11 $or$libresoc.v:193748$12996_Y - connect \$13 $not$libresoc.v:193749$12997_Y - connect \$15 $or$libresoc.v:193750$12998_Y - connect \$1 $not$libresoc.v:193751$12999_Y - connect \$3 $and$libresoc.v:193752$13000_Y - connect \$5 $or$libresoc.v:193753$13001_Y - connect \$7 $not$libresoc.v:193754$13002_Y + connect \$9 $and$libresoc.v:193497$12993_Y + connect \$11 $or$libresoc.v:193498$12994_Y + connect \$13 $not$libresoc.v:193499$12995_Y + connect \$15 $or$libresoc.v:193500$12996_Y + connect \$1 $not$libresoc.v:193501$12997_Y + connect \$3 $and$libresoc.v:193502$12998_Y + connect \$5 $or$libresoc.v:193503$12999_Y + connect \$7 $not$libresoc.v:193504$13000_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:193773.1-193831.10" +attribute \src "libresoc.v:193523.1-193581.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" attribute \generator "nMigen" module \st_active - attribute \src "libresoc.v:193774.7-193774.20" + attribute \src "libresoc.v:193524.7-193524.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193819.3-193827.6" - wire $0\q_int$next[0:0]$13019 - attribute \src "libresoc.v:193817.3-193818.27" + attribute \src "libresoc.v:193569.3-193577.6" + wire $0\q_int$next[0:0]$13017 + attribute \src "libresoc.v:193567.3-193568.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:193819.3-193827.6" - wire $1\q_int$next[0:0]$13020 - attribute \src "libresoc.v:193796.7-193796.19" + attribute \src "libresoc.v:193569.3-193577.6" + wire $1\q_int$next[0:0]$13018 + attribute \src "libresoc.v:193546.7-193546.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:193809.17-193809.96" - wire $and$libresoc.v:193809$13009_Y - attribute \src "libresoc.v:193814.17-193814.96" - wire $and$libresoc.v:193814$13014_Y - attribute \src "libresoc.v:193811.18-193811.99" - wire $not$libresoc.v:193811$13011_Y - attribute \src "libresoc.v:193813.17-193813.98" - wire $not$libresoc.v:193813$13013_Y - attribute \src "libresoc.v:193816.17-193816.98" - wire $not$libresoc.v:193816$13016_Y - attribute \src "libresoc.v:193810.18-193810.104" - wire $or$libresoc.v:193810$13010_Y - attribute \src "libresoc.v:193812.18-193812.105" - wire $or$libresoc.v:193812$13012_Y - attribute \src "libresoc.v:193815.17-193815.103" - wire $or$libresoc.v:193815$13015_Y + attribute \src "libresoc.v:193559.17-193559.96" + wire $and$libresoc.v:193559$13007_Y + attribute \src "libresoc.v:193564.17-193564.96" + wire $and$libresoc.v:193564$13012_Y + attribute \src "libresoc.v:193561.18-193561.99" + wire $not$libresoc.v:193561$13009_Y + attribute \src "libresoc.v:193563.17-193563.98" + wire $not$libresoc.v:193563$13011_Y + attribute \src "libresoc.v:193566.17-193566.98" + wire $not$libresoc.v:193566$13014_Y + attribute \src "libresoc.v:193560.18-193560.104" + wire $or$libresoc.v:193560$13008_Y + attribute \src "libresoc.v:193562.18-193562.105" + wire $or$libresoc.v:193562$13010_Y + attribute \src "libresoc.v:193565.17-193565.103" + wire $or$libresoc.v:193565$13013_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -366692,11 +366418,11 @@ module \st_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193774.7-193774.15" + attribute \src "libresoc.v:193524.7-193524.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -366713,7 +366439,7 @@ module \st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193809$13009 + cell $and $and$libresoc.v:193559$13007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366721,10 +366447,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193809$13009_Y + connect \Y $and$libresoc.v:193559$13007_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193814$13014 + cell $and $and$libresoc.v:193564$13012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366732,34 +366458,34 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193814$13014_Y + connect \Y $and$libresoc.v:193564$13012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193811$13011 + cell $not $not$libresoc.v:193561$13009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active - connect \Y $not$libresoc.v:193811$13011_Y + connect \Y $not$libresoc.v:193561$13009_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193813$13013 + cell $not $not$libresoc.v:193563$13011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:193813$13013_Y + connect \Y $not$libresoc.v:193563$13011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193816$13016 + cell $not $not$libresoc.v:193566$13014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:193816$13016_Y + connect \Y $not$libresoc.v:193566$13014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193810$13010 + cell $or $or$libresoc.v:193560$13008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366767,10 +366493,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_active - connect \Y $or$libresoc.v:193810$13010_Y + connect \Y $or$libresoc.v:193560$13008_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193812$13012 + cell $or $or$libresoc.v:193562$13010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366778,10 +366504,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_st_active connect \B \q_int - connect \Y $or$libresoc.v:193812$13012_Y + connect \Y $or$libresoc.v:193562$13010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193815$13015 + cell $or $or$libresoc.v:193565$13013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366789,39 +366515,39 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_active - connect \Y $or$libresoc.v:193815$13015_Y + connect \Y $or$libresoc.v:193565$13013_Y end - attribute \src "libresoc.v:193774.7-193774.20" - process $proc$libresoc.v:193774$13021 + attribute \src "libresoc.v:193524.7-193524.20" + process $proc$libresoc.v:193524$13019 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193796.7-193796.19" - process $proc$libresoc.v:193796$13022 + attribute \src "libresoc.v:193546.7-193546.19" + process $proc$libresoc.v:193546$13020 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:193817.3-193818.27" - process $proc$libresoc.v:193817$13017 + attribute \src "libresoc.v:193567.3-193568.27" + process $proc$libresoc.v:193567$13015 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:193819.3-193827.6" - process $proc$libresoc.v:193819$13018 + attribute \src "libresoc.v:193569.3-193577.6" + process $proc$libresoc.v:193569$13016 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13019 $1\q_int$next[0:0]$13020 - attribute \src "libresoc.v:193820.5-193820.29" + assign $0\q_int$next[0:0]$13017 $1\q_int$next[0:0]$13018 + attribute \src "libresoc.v:193570.5-193570.29" switch \initial - attribute \src "libresoc.v:193820.9-193820.17" + attribute \src "libresoc.v:193570.9-193570.17" case 1'1 case end @@ -366830,56 +366556,56 @@ module \st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13020 1'0 + assign $1\q_int$next[0:0]$13018 1'0 case - assign $1\q_int$next[0:0]$13020 \$5 + assign $1\q_int$next[0:0]$13018 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13019 + update \q_int$next $0\q_int$next[0:0]$13017 end - connect \$9 $and$libresoc.v:193809$13009_Y - connect \$11 $or$libresoc.v:193810$13010_Y - connect \$13 $not$libresoc.v:193811$13011_Y - connect \$15 $or$libresoc.v:193812$13012_Y - connect \$1 $not$libresoc.v:193813$13013_Y - connect \$3 $and$libresoc.v:193814$13014_Y - connect \$5 $or$libresoc.v:193815$13015_Y - connect \$7 $not$libresoc.v:193816$13016_Y + connect \$9 $and$libresoc.v:193559$13007_Y + connect \$11 $or$libresoc.v:193560$13008_Y + connect \$13 $not$libresoc.v:193561$13009_Y + connect \$15 $or$libresoc.v:193562$13010_Y + connect \$1 $not$libresoc.v:193563$13011_Y + connect \$3 $and$libresoc.v:193564$13012_Y + connect \$5 $or$libresoc.v:193565$13013_Y + connect \$7 $not$libresoc.v:193566$13014_Y connect \qlq_st_active \$15 connect \qn_st_active \$13 connect \q_st_active \$11 end -attribute \src "libresoc.v:193835.1-193893.10" +attribute \src "libresoc.v:193585.1-193643.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" attribute \generator "nMigen" module \st_done - attribute \src "libresoc.v:193836.7-193836.20" + attribute \src "libresoc.v:193586.7-193586.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193881.3-193889.6" - wire $0\q_int$next[0:0]$13033 - attribute \src "libresoc.v:193879.3-193880.27" + attribute \src "libresoc.v:193631.3-193639.6" + wire $0\q_int$next[0:0]$13031 + attribute \src "libresoc.v:193629.3-193630.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:193881.3-193889.6" - wire $1\q_int$next[0:0]$13034 - attribute \src "libresoc.v:193858.7-193858.19" + attribute \src "libresoc.v:193631.3-193639.6" + wire $1\q_int$next[0:0]$13032 + attribute \src "libresoc.v:193608.7-193608.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:193871.17-193871.96" - wire $and$libresoc.v:193871$13023_Y - attribute \src "libresoc.v:193876.17-193876.96" - wire $and$libresoc.v:193876$13028_Y - attribute \src "libresoc.v:193873.18-193873.97" - wire $not$libresoc.v:193873$13025_Y - attribute \src "libresoc.v:193875.17-193875.96" - wire $not$libresoc.v:193875$13027_Y - attribute \src "libresoc.v:193878.17-193878.96" - wire $not$libresoc.v:193878$13030_Y - attribute \src "libresoc.v:193872.18-193872.102" - wire $or$libresoc.v:193872$13024_Y - attribute \src "libresoc.v:193874.18-193874.103" - wire $or$libresoc.v:193874$13026_Y - attribute \src "libresoc.v:193877.17-193877.101" - wire $or$libresoc.v:193877$13029_Y + attribute \src "libresoc.v:193621.17-193621.96" + wire $and$libresoc.v:193621$13021_Y + attribute \src "libresoc.v:193626.17-193626.96" + wire $and$libresoc.v:193626$13026_Y + attribute \src "libresoc.v:193623.18-193623.97" + wire $not$libresoc.v:193623$13023_Y + attribute \src "libresoc.v:193625.17-193625.96" + wire $not$libresoc.v:193625$13025_Y + attribute \src "libresoc.v:193628.17-193628.96" + wire $not$libresoc.v:193628$13028_Y + attribute \src "libresoc.v:193622.18-193622.102" + wire $or$libresoc.v:193622$13022_Y + attribute \src "libresoc.v:193624.18-193624.103" + wire $or$libresoc.v:193624$13024_Y + attribute \src "libresoc.v:193627.17-193627.101" + wire $or$libresoc.v:193627$13027_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -366896,11 +366622,11 @@ module \st_done wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:193836.7-193836.15" + attribute \src "libresoc.v:193586.7-193586.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -366917,7 +366643,7 @@ module \st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193871$13023 + cell $and $and$libresoc.v:193621$13021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366925,10 +366651,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193871$13023_Y + connect \Y $and$libresoc.v:193621$13021_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193876$13028 + cell $and $and$libresoc.v:193626$13026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366936,34 +366662,34 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193876$13028_Y + connect \Y $and$libresoc.v:193626$13026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193873$13025 + cell $not $not$libresoc.v:193623$13023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done - connect \Y $not$libresoc.v:193873$13025_Y + connect \Y $not$libresoc.v:193623$13023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193875$13027 + cell $not $not$libresoc.v:193625$13025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:193875$13027_Y + connect \Y $not$libresoc.v:193625$13025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193878$13030 + cell $not $not$libresoc.v:193628$13028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:193878$13030_Y + connect \Y $not$libresoc.v:193628$13028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193872$13024 + cell $or $or$libresoc.v:193622$13022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366971,10 +366697,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_done - connect \Y $or$libresoc.v:193872$13024_Y + connect \Y $or$libresoc.v:193622$13022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193874$13026 + cell $or $or$libresoc.v:193624$13024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366982,10 +366708,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_st_done connect \B \q_int - connect \Y $or$libresoc.v:193874$13026_Y + connect \Y $or$libresoc.v:193624$13024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193877$13029 + cell $or $or$libresoc.v:193627$13027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366993,39 +366719,39 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_done - connect \Y $or$libresoc.v:193877$13029_Y + connect \Y $or$libresoc.v:193627$13027_Y end - attribute \src "libresoc.v:193836.7-193836.20" - process $proc$libresoc.v:193836$13035 + attribute \src "libresoc.v:193586.7-193586.20" + process $proc$libresoc.v:193586$13033 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193858.7-193858.19" - process $proc$libresoc.v:193858$13036 + attribute \src "libresoc.v:193608.7-193608.19" + process $proc$libresoc.v:193608$13034 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:193879.3-193880.27" - process $proc$libresoc.v:193879$13031 + attribute \src "libresoc.v:193629.3-193630.27" + process $proc$libresoc.v:193629$13029 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:193881.3-193889.6" - process $proc$libresoc.v:193881$13032 + attribute \src "libresoc.v:193631.3-193639.6" + process $proc$libresoc.v:193631$13030 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13033 $1\q_int$next[0:0]$13034 - attribute \src "libresoc.v:193882.5-193882.29" + assign $0\q_int$next[0:0]$13031 $1\q_int$next[0:0]$13032 + attribute \src "libresoc.v:193632.5-193632.29" switch \initial - attribute \src "libresoc.v:193882.9-193882.17" + attribute \src "libresoc.v:193632.9-193632.17" case 1'1 case end @@ -367034,86 +366760,86 @@ module \st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13034 1'0 + assign $1\q_int$next[0:0]$13032 1'0 case - assign $1\q_int$next[0:0]$13034 \$5 + assign $1\q_int$next[0:0]$13032 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13033 + update \q_int$next $0\q_int$next[0:0]$13031 end - connect \$9 $and$libresoc.v:193871$13023_Y - connect \$11 $or$libresoc.v:193872$13024_Y - connect \$13 $not$libresoc.v:193873$13025_Y - connect \$15 $or$libresoc.v:193874$13026_Y - connect \$1 $not$libresoc.v:193875$13027_Y - connect \$3 $and$libresoc.v:193876$13028_Y - connect \$5 $or$libresoc.v:193877$13029_Y - connect \$7 $not$libresoc.v:193878$13030_Y + connect \$9 $and$libresoc.v:193621$13021_Y + connect \$11 $or$libresoc.v:193622$13022_Y + connect \$13 $not$libresoc.v:193623$13023_Y + connect \$15 $or$libresoc.v:193624$13024_Y + connect \$1 $not$libresoc.v:193625$13025_Y + connect \$3 $and$libresoc.v:193626$13026_Y + connect \$5 $or$libresoc.v:193627$13027_Y + connect \$7 $not$libresoc.v:193628$13028_Y connect \qlq_st_done \$15 connect \qn_st_done \$13 connect \q_st_done \$11 end -attribute \src "libresoc.v:193897.1-194193.10" +attribute \src "libresoc.v:193647.1-193943.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state" attribute \generator "nMigen" module \state - attribute \src "libresoc.v:194145.3-194154.6" + attribute \src "libresoc.v:193895.3-193904.6" wire width 64 $0\cia__data_o[63:0] - attribute \src "libresoc.v:193898.7-193898.20" + attribute \src "libresoc.v:193648.7-193648.20" wire $0\initial[0:0] - attribute \src "libresoc.v:194164.3-194173.6" + attribute \src "libresoc.v:193914.3-193923.6" wire width 64 $0\msr__data_o[63:0] - attribute \src "libresoc.v:194155.3-194163.6" - wire width 3 $0\ren_delay$12$next[2:0]$13060 - attribute \src "libresoc.v:194059.3-194060.43" - wire width 3 $0\ren_delay$12[2:0]$13049 - attribute \src "libresoc.v:194026.13-194026.34" - wire width 3 $0\ren_delay$12[2:0]$13066 - attribute \src "libresoc.v:194117.3-194125.6" - wire width 3 $0\ren_delay$19$next[2:0]$13052 - attribute \src "libresoc.v:194057.3-194058.43" - wire width 3 $0\ren_delay$19[2:0]$13047 - attribute \src "libresoc.v:194030.13-194030.34" - wire width 3 $0\ren_delay$19[2:0]$13068 - attribute \src "libresoc.v:194136.3-194144.6" - wire width 3 $0\ren_delay$next[2:0]$13056 - attribute \src "libresoc.v:194061.3-194062.35" + attribute \src "libresoc.v:193905.3-193913.6" + wire width 3 $0\ren_delay$12$next[2:0]$13058 + attribute \src "libresoc.v:193809.3-193810.43" + wire width 3 $0\ren_delay$12[2:0]$13047 + attribute \src "libresoc.v:193776.13-193776.34" + wire width 3 $0\ren_delay$12[2:0]$13064 + attribute \src "libresoc.v:193867.3-193875.6" + wire width 3 $0\ren_delay$19$next[2:0]$13050 + attribute \src "libresoc.v:193807.3-193808.43" + wire width 3 $0\ren_delay$19[2:0]$13045 + attribute \src "libresoc.v:193780.13-193780.34" + wire width 3 $0\ren_delay$19[2:0]$13066 + attribute \src "libresoc.v:193886.3-193894.6" + wire width 3 $0\ren_delay$next[2:0]$13054 + attribute \src "libresoc.v:193811.3-193812.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:194126.3-194135.6" + attribute \src "libresoc.v:193876.3-193885.6" wire width 64 $0\sv__data_o[63:0] - attribute \src "libresoc.v:194145.3-194154.6" + attribute \src "libresoc.v:193895.3-193904.6" wire width 64 $1\cia__data_o[63:0] - attribute \src "libresoc.v:194164.3-194173.6" + attribute \src "libresoc.v:193914.3-193923.6" wire width 64 $1\msr__data_o[63:0] - attribute \src "libresoc.v:194155.3-194163.6" - wire width 3 $1\ren_delay$12$next[2:0]$13061 - attribute \src "libresoc.v:194117.3-194125.6" - wire width 3 $1\ren_delay$19$next[2:0]$13053 - attribute \src "libresoc.v:194136.3-194144.6" - wire width 3 $1\ren_delay$next[2:0]$13057 - attribute \src "libresoc.v:194024.13-194024.29" + attribute \src "libresoc.v:193905.3-193913.6" + wire width 3 $1\ren_delay$12$next[2:0]$13059 + attribute \src "libresoc.v:193867.3-193875.6" + wire width 3 $1\ren_delay$19$next[2:0]$13051 + attribute \src "libresoc.v:193886.3-193894.6" + wire width 3 $1\ren_delay$next[2:0]$13055 + attribute \src "libresoc.v:193774.13-193774.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:194126.3-194135.6" + attribute \src "libresoc.v:193876.3-193885.6" wire width 64 $1\sv__data_o[63:0] - attribute \src "libresoc.v:194048.18-194048.109" - wire width 64 $or$libresoc.v:194048$13037_Y - attribute \src "libresoc.v:194050.18-194050.124" - wire width 64 $or$libresoc.v:194050$13039_Y - attribute \src "libresoc.v:194051.18-194051.110" - wire width 64 $or$libresoc.v:194051$13040_Y - attribute \src "libresoc.v:194053.18-194053.122" - wire width 64 $or$libresoc.v:194053$13042_Y - attribute \src "libresoc.v:194054.18-194054.109" - wire width 64 $or$libresoc.v:194054$13043_Y - attribute \src "libresoc.v:194056.17-194056.123" - wire width 64 $or$libresoc.v:194056$13045_Y - attribute \src "libresoc.v:194049.18-194049.100" - wire $reduce_or$libresoc.v:194049$13038_Y - attribute \src "libresoc.v:194052.18-194052.100" - wire $reduce_or$libresoc.v:194052$13041_Y - attribute \src "libresoc.v:194055.17-194055.95" - wire $reduce_or$libresoc.v:194055$13044_Y + attribute \src "libresoc.v:193798.18-193798.109" + wire width 64 $or$libresoc.v:193798$13035_Y + attribute \src "libresoc.v:193800.18-193800.124" + wire width 64 $or$libresoc.v:193800$13037_Y + attribute \src "libresoc.v:193801.18-193801.110" + wire width 64 $or$libresoc.v:193801$13038_Y + attribute \src "libresoc.v:193803.18-193803.122" + wire width 64 $or$libresoc.v:193803$13040_Y + attribute \src "libresoc.v:193804.18-193804.109" + wire width 64 $or$libresoc.v:193804$13041_Y + attribute \src "libresoc.v:193806.17-193806.123" + wire width 64 $or$libresoc.v:193806$13043_Y + attribute \src "libresoc.v:193799.18-193799.100" + wire $reduce_or$libresoc.v:193799$13036_Y + attribute \src "libresoc.v:193802.18-193802.100" + wire $reduce_or$libresoc.v:193802$13039_Y + attribute \src "libresoc.v:193805.17-193805.95" + wire $reduce_or$libresoc.v:193805$13042_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" @@ -367136,9 +366862,9 @@ module \state wire width 64 output 3 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 7 \data_i @@ -367148,7 +366874,7 @@ module \state wire width 64 input 13 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 14 \data_i$4 - attribute \src "libresoc.v:193898.7-193898.15" + attribute \src "libresoc.v:193648.7-193648.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 9 \msr__data_o @@ -367263,7 +366989,7 @@ module \state attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:194048$13037 + cell $or $or$libresoc.v:193798$13035 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -367271,10 +366997,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_cia0__data_o connect \B \$8 - connect \Y $or$libresoc.v:194048$13037_Y + connect \Y $or$libresoc.v:193798$13035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:194050$13039 + cell $or $or$libresoc.v:193800$13037 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -367282,10 +367008,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_msr1__data_o connect \B \reg_2_msr2__data_o - connect \Y $or$libresoc.v:194050$13039_Y + connect \Y $or$libresoc.v:193800$13037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:194051$13040 + cell $or $or$libresoc.v:193801$13038 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -367293,10 +367019,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_msr0__data_o connect \B \$15 - connect \Y $or$libresoc.v:194051$13040_Y + connect \Y $or$libresoc.v:193801$13038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:194053$13042 + cell $or $or$libresoc.v:193803$13040 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -367304,10 +367030,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_sv1__data_o connect \B \reg_2_sv2__data_o - connect \Y $or$libresoc.v:194053$13042_Y + connect \Y $or$libresoc.v:193803$13040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:194054$13043 + cell $or $or$libresoc.v:193804$13041 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -367315,10 +367041,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_sv0__data_o connect \B \$22 - connect \Y $or$libresoc.v:194054$13043_Y + connect \Y $or$libresoc.v:193804$13041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:194056$13045 + cell $or $or$libresoc.v:193806$13043 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -367326,34 +367052,34 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_cia1__data_o connect \B \reg_2_cia2__data_o - connect \Y $or$libresoc.v:194056$13045_Y + connect \Y $or$libresoc.v:193806$13043_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:194049$13038 + cell $reduce_or $reduce_or$libresoc.v:193799$13036 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$12 - connect \Y $reduce_or$libresoc.v:194049$13038_Y + connect \Y $reduce_or$libresoc.v:193799$13036_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:194052$13041 + cell $reduce_or $reduce_or$libresoc.v:193802$13039 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$19 - connect \Y $reduce_or$libresoc.v:194052$13041_Y + connect \Y $reduce_or$libresoc.v:193802$13039_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:194055$13044 + cell $reduce_or $reduce_or$libresoc.v:193805$13042 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:194055$13044_Y + connect \Y $reduce_or$libresoc.v:193805$13042_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:194063.15-194080.4" + attribute \src "libresoc.v:193813.15-193830.4" cell \reg_0$135 \reg_0 connect \cia0__data_o \reg_0_cia0__data_o connect \cia0__ren \reg_0_cia0__ren @@ -367373,7 +367099,7 @@ module \state connect \sv0__wen \reg_0_sv0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:194081.15-194098.4" + attribute \src "libresoc.v:193831.15-193848.4" cell \reg_1$136 \reg_1 connect \cia1__data_o \reg_1_cia1__data_o connect \cia1__ren \reg_1_cia1__ren @@ -367393,7 +367119,7 @@ module \state connect \sv1__wen \reg_1_sv1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:194099.15-194116.4" + attribute \src "libresoc.v:193849.15-193866.4" cell \reg_2$137 \reg_2 connect \cia2__data_o \reg_2_cia2__data_o connect \cia2__ren \reg_2_cia2__ren @@ -367412,67 +367138,67 @@ module \state connect \sv2__ren \reg_2_sv2__ren connect \sv2__wen \reg_2_sv2__wen end - attribute \src "libresoc.v:193898.7-193898.20" - process $proc$libresoc.v:193898$13063 + attribute \src "libresoc.v:193648.7-193648.20" + process $proc$libresoc.v:193648$13061 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:194024.13-194024.29" - process $proc$libresoc.v:194024$13064 + attribute \src "libresoc.v:193774.13-193774.29" + process $proc$libresoc.v:193774$13062 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:194026.13-194026.34" - process $proc$libresoc.v:194026$13065 + attribute \src "libresoc.v:193776.13-193776.34" + process $proc$libresoc.v:193776$13063 assign { } { } - assign $0\ren_delay$12[2:0]$13066 3'000 + assign $0\ren_delay$12[2:0]$13064 3'000 sync always sync init - update \ren_delay$12 $0\ren_delay$12[2:0]$13066 + update \ren_delay$12 $0\ren_delay$12[2:0]$13064 end - attribute \src "libresoc.v:194030.13-194030.34" - process $proc$libresoc.v:194030$13067 + attribute \src "libresoc.v:193780.13-193780.34" + process $proc$libresoc.v:193780$13065 assign { } { } - assign $0\ren_delay$19[2:0]$13068 3'000 + assign $0\ren_delay$19[2:0]$13066 3'000 sync always sync init - update \ren_delay$19 $0\ren_delay$19[2:0]$13068 + update \ren_delay$19 $0\ren_delay$19[2:0]$13066 end - attribute \src "libresoc.v:194057.3-194058.43" - process $proc$libresoc.v:194057$13046 + attribute \src "libresoc.v:193807.3-193808.43" + process $proc$libresoc.v:193807$13044 assign { } { } - assign $0\ren_delay$19[2:0]$13047 \ren_delay$19$next + assign $0\ren_delay$19[2:0]$13045 \ren_delay$19$next sync posedge \coresync_clk - update \ren_delay$19 $0\ren_delay$19[2:0]$13047 + update \ren_delay$19 $0\ren_delay$19[2:0]$13045 end - attribute \src "libresoc.v:194059.3-194060.43" - process $proc$libresoc.v:194059$13048 + attribute \src "libresoc.v:193809.3-193810.43" + process $proc$libresoc.v:193809$13046 assign { } { } - assign $0\ren_delay$12[2:0]$13049 \ren_delay$12$next + assign $0\ren_delay$12[2:0]$13047 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[2:0]$13049 + update \ren_delay$12 $0\ren_delay$12[2:0]$13047 end - attribute \src "libresoc.v:194061.3-194062.35" - process $proc$libresoc.v:194061$13050 + attribute \src "libresoc.v:193811.3-193812.35" + process $proc$libresoc.v:193811$13048 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:194117.3-194125.6" - process $proc$libresoc.v:194117$13051 + attribute \src "libresoc.v:193867.3-193875.6" + process $proc$libresoc.v:193867$13049 assign { } { } assign { } { } - assign $0\ren_delay$19$next[2:0]$13052 $1\ren_delay$19$next[2:0]$13053 - attribute \src "libresoc.v:194118.5-194118.29" + assign $0\ren_delay$19$next[2:0]$13050 $1\ren_delay$19$next[2:0]$13051 + attribute \src "libresoc.v:193868.5-193868.29" switch \initial - attribute \src "libresoc.v:194118.9-194118.17" + attribute \src "libresoc.v:193868.9-193868.17" case 1'1 case end @@ -367481,21 +367207,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$19$next[2:0]$13053 3'000 + assign $1\ren_delay$19$next[2:0]$13051 3'000 case - assign $1\ren_delay$19$next[2:0]$13053 \sv__ren + assign $1\ren_delay$19$next[2:0]$13051 \sv__ren end sync always - update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13052 + update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13050 end - attribute \src "libresoc.v:194126.3-194135.6" - process $proc$libresoc.v:194126$13054 + attribute \src "libresoc.v:193876.3-193885.6" + process $proc$libresoc.v:193876$13052 assign { } { } assign { } { } assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] - attribute \src "libresoc.v:194127.5-194127.29" + attribute \src "libresoc.v:193877.5-193877.29" switch \initial - attribute \src "libresoc.v:194127.9-194127.17" + attribute \src "libresoc.v:193877.9-193877.17" case 1'1 case end @@ -367511,14 +367237,14 @@ module \state sync always update \sv__data_o $0\sv__data_o[63:0] end - attribute \src "libresoc.v:194136.3-194144.6" - process $proc$libresoc.v:194136$13055 + attribute \src "libresoc.v:193886.3-193894.6" + process $proc$libresoc.v:193886$13053 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$13056 $1\ren_delay$next[2:0]$13057 - attribute \src "libresoc.v:194137.5-194137.29" + assign $0\ren_delay$next[2:0]$13054 $1\ren_delay$next[2:0]$13055 + attribute \src "libresoc.v:193887.5-193887.29" switch \initial - attribute \src "libresoc.v:194137.9-194137.17" + attribute \src "libresoc.v:193887.9-193887.17" case 1'1 case end @@ -367527,21 +367253,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$13057 3'000 + assign $1\ren_delay$next[2:0]$13055 3'000 case - assign $1\ren_delay$next[2:0]$13057 \cia__ren + assign $1\ren_delay$next[2:0]$13055 \cia__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$13056 + update \ren_delay$next $0\ren_delay$next[2:0]$13054 end - attribute \src "libresoc.v:194145.3-194154.6" - process $proc$libresoc.v:194145$13058 + attribute \src "libresoc.v:193895.3-193904.6" + process $proc$libresoc.v:193895$13056 assign { } { } assign { } { } assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "libresoc.v:194146.5-194146.29" + attribute \src "libresoc.v:193896.5-193896.29" switch \initial - attribute \src "libresoc.v:194146.9-194146.17" + attribute \src "libresoc.v:193896.9-193896.17" case 1'1 case end @@ -367557,14 +367283,14 @@ module \state sync always update \cia__data_o $0\cia__data_o[63:0] end - attribute \src "libresoc.v:194155.3-194163.6" - process $proc$libresoc.v:194155$13059 + attribute \src "libresoc.v:193905.3-193913.6" + process $proc$libresoc.v:193905$13057 assign { } { } assign { } { } - assign $0\ren_delay$12$next[2:0]$13060 $1\ren_delay$12$next[2:0]$13061 - attribute \src "libresoc.v:194156.5-194156.29" + assign $0\ren_delay$12$next[2:0]$13058 $1\ren_delay$12$next[2:0]$13059 + attribute \src "libresoc.v:193906.5-193906.29" switch \initial - attribute \src "libresoc.v:194156.9-194156.17" + attribute \src "libresoc.v:193906.9-193906.17" case 1'1 case end @@ -367573,21 +367299,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[2:0]$13061 3'000 + assign $1\ren_delay$12$next[2:0]$13059 3'000 case - assign $1\ren_delay$12$next[2:0]$13061 \msr__ren + assign $1\ren_delay$12$next[2:0]$13059 \msr__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13060 + update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13058 end - attribute \src "libresoc.v:194164.3-194173.6" - process $proc$libresoc.v:194164$13062 + attribute \src "libresoc.v:193914.3-193923.6" + process $proc$libresoc.v:193914$13060 assign { } { } assign { } { } assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "libresoc.v:194165.5-194165.29" + attribute \src "libresoc.v:193915.5-193915.29" switch \initial - attribute \src "libresoc.v:194165.9-194165.17" + attribute \src "libresoc.v:193915.9-193915.17" case 1'1 case end @@ -367603,15 +367329,15 @@ module \state sync always update \msr__data_o $0\msr__data_o[63:0] end - connect \$10 $or$libresoc.v:194048$13037_Y - connect \$13 $reduce_or$libresoc.v:194049$13038_Y - connect \$15 $or$libresoc.v:194050$13039_Y - connect \$17 $or$libresoc.v:194051$13040_Y - connect \$20 $reduce_or$libresoc.v:194052$13041_Y - connect \$22 $or$libresoc.v:194053$13042_Y - connect \$24 $or$libresoc.v:194054$13043_Y - connect \$6 $reduce_or$libresoc.v:194055$13044_Y - connect \$8 $or$libresoc.v:194056$13045_Y + connect \$10 $or$libresoc.v:193798$13035_Y + connect \$13 $reduce_or$libresoc.v:193799$13036_Y + connect \$15 $or$libresoc.v:193800$13037_Y + connect \$17 $or$libresoc.v:193801$13038_Y + connect \$20 $reduce_or$libresoc.v:193802$13039_Y + connect \$22 $or$libresoc.v:193803$13040_Y + connect \$24 $or$libresoc.v:193804$13041_Y + connect \$6 $reduce_or$libresoc.v:193805$13042_Y + connect \$8 $or$libresoc.v:193806$13043_Y connect \reg_2_d_wr12__data_i \data_i connect \reg_1_d_wr11__data_i \data_i connect \reg_0_d_wr10__data_i \data_i @@ -367632,37 +367358,37 @@ module \state connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren end -attribute \src "libresoc.v:194197.1-194255.10" +attribute \src "libresoc.v:193947.1-194005.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" attribute \generator "nMigen" module \sto_l - attribute \src "libresoc.v:194198.7-194198.20" + attribute \src "libresoc.v:193948.7-193948.20" wire $0\initial[0:0] - attribute \src "libresoc.v:194243.3-194251.6" - wire $0\q_int$next[0:0]$13079 - attribute \src "libresoc.v:194241.3-194242.27" + attribute \src "libresoc.v:193993.3-194001.6" + wire $0\q_int$next[0:0]$13077 + attribute \src "libresoc.v:193991.3-193992.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:194243.3-194251.6" - wire $1\q_int$next[0:0]$13080 - attribute \src "libresoc.v:194220.7-194220.19" + attribute \src "libresoc.v:193993.3-194001.6" + wire $1\q_int$next[0:0]$13078 + attribute \src "libresoc.v:193970.7-193970.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:194233.17-194233.96" - wire $and$libresoc.v:194233$13069_Y - attribute \src "libresoc.v:194238.17-194238.96" - wire $and$libresoc.v:194238$13074_Y - attribute \src "libresoc.v:194235.18-194235.93" - wire $not$libresoc.v:194235$13071_Y - attribute \src "libresoc.v:194237.17-194237.92" - wire $not$libresoc.v:194237$13073_Y - attribute \src "libresoc.v:194240.17-194240.92" - wire $not$libresoc.v:194240$13076_Y - attribute \src "libresoc.v:194234.18-194234.98" - wire $or$libresoc.v:194234$13070_Y - attribute \src "libresoc.v:194236.18-194236.99" - wire $or$libresoc.v:194236$13072_Y - attribute \src "libresoc.v:194239.17-194239.97" - wire $or$libresoc.v:194239$13075_Y + attribute \src "libresoc.v:193983.17-193983.96" + wire $and$libresoc.v:193983$13067_Y + attribute \src "libresoc.v:193988.17-193988.96" + wire $and$libresoc.v:193988$13072_Y + attribute \src "libresoc.v:193985.18-193985.93" + wire $not$libresoc.v:193985$13069_Y + attribute \src "libresoc.v:193987.17-193987.92" + wire $not$libresoc.v:193987$13071_Y + attribute \src "libresoc.v:193990.17-193990.92" + wire $not$libresoc.v:193990$13074_Y + attribute \src "libresoc.v:193984.18-193984.98" + wire $or$libresoc.v:193984$13068_Y + attribute \src "libresoc.v:193986.18-193986.99" + wire $or$libresoc.v:193986$13070_Y + attribute \src "libresoc.v:193989.17-193989.97" + wire $or$libresoc.v:193989$13073_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -367679,11 +367405,11 @@ module \sto_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:194198.7-194198.15" + attribute \src "libresoc.v:193948.7-193948.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -367700,7 +367426,7 @@ module \sto_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:194233$13069 + cell $and $and$libresoc.v:193983$13067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367708,10 +367434,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:194233$13069_Y + connect \Y $and$libresoc.v:193983$13067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:194238$13074 + cell $and $and$libresoc.v:193988$13072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367719,34 +367445,34 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:194238$13074_Y + connect \Y $and$libresoc.v:193988$13072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:194235$13071 + cell $not $not$libresoc.v:193985$13069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto - connect \Y $not$libresoc.v:194235$13071_Y + connect \Y $not$libresoc.v:193985$13069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:194237$13073 + cell $not $not$libresoc.v:193987$13071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:194237$13073_Y + connect \Y $not$libresoc.v:193987$13071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:194240$13076 + cell $not $not$libresoc.v:193990$13074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:194240$13076_Y + connect \Y $not$libresoc.v:193990$13074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:194234$13070 + cell $or $or$libresoc.v:193984$13068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367754,10 +367480,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_sto - connect \Y $or$libresoc.v:194234$13070_Y + connect \Y $or$libresoc.v:193984$13068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:194236$13072 + cell $or $or$libresoc.v:193986$13070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367765,10 +367491,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_sto connect \B \q_int - connect \Y $or$libresoc.v:194236$13072_Y + connect \Y $or$libresoc.v:193986$13070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:194239$13075 + cell $or $or$libresoc.v:193989$13073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -367776,39 +367502,39 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_sto - connect \Y $or$libresoc.v:194239$13075_Y + connect \Y $or$libresoc.v:193989$13073_Y end - attribute \src "libresoc.v:194198.7-194198.20" - process $proc$libresoc.v:194198$13081 + attribute \src "libresoc.v:193948.7-193948.20" + process $proc$libresoc.v:193948$13079 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:194220.7-194220.19" - process $proc$libresoc.v:194220$13082 + attribute \src "libresoc.v:193970.7-193970.19" + process $proc$libresoc.v:193970$13080 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:194241.3-194242.27" - process $proc$libresoc.v:194241$13077 + attribute \src "libresoc.v:193991.3-193992.27" + process $proc$libresoc.v:193991$13075 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:194243.3-194251.6" - process $proc$libresoc.v:194243$13078 + attribute \src "libresoc.v:193993.3-194001.6" + process $proc$libresoc.v:193993$13076 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13079 $1\q_int$next[0:0]$13080 - attribute \src "libresoc.v:194244.5-194244.29" + assign $0\q_int$next[0:0]$13077 $1\q_int$next[0:0]$13078 + attribute \src "libresoc.v:193994.5-193994.29" switch \initial - attribute \src "libresoc.v:194244.9-194244.17" + attribute \src "libresoc.v:193994.9-193994.17" case 1'1 case end @@ -367817,26 +367543,26 @@ module \sto_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13080 1'0 + assign $1\q_int$next[0:0]$13078 1'0 case - assign $1\q_int$next[0:0]$13080 \$5 + assign $1\q_int$next[0:0]$13078 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13079 + update \q_int$next $0\q_int$next[0:0]$13077 end - connect \$9 $and$libresoc.v:194233$13069_Y - connect \$11 $or$libresoc.v:194234$13070_Y - connect \$13 $not$libresoc.v:194235$13071_Y - connect \$15 $or$libresoc.v:194236$13072_Y - connect \$1 $not$libresoc.v:194237$13073_Y - connect \$3 $and$libresoc.v:194238$13074_Y - connect \$5 $or$libresoc.v:194239$13075_Y - connect \$7 $not$libresoc.v:194240$13076_Y + connect \$9 $and$libresoc.v:193983$13067_Y + connect \$11 $or$libresoc.v:193984$13068_Y + connect \$13 $not$libresoc.v:193985$13069_Y + connect \$15 $or$libresoc.v:193986$13070_Y + connect \$1 $not$libresoc.v:193987$13071_Y + connect \$3 $and$libresoc.v:193988$13072_Y + connect \$5 $or$libresoc.v:193989$13073_Y + connect \$7 $not$libresoc.v:193990$13074_Y connect \qlq_sto \$15 connect \qn_sto \$13 connect \q_sto \$11 end -attribute \src "libresoc.v:194260.1-195249.10" +attribute \src "libresoc.v:194010.1-194972.10" attribute \cells_not_processed 1 attribute \top 1 attribute \nmigen.hierarchy "test_issuer" @@ -367850,13 +367576,11 @@ module \test_issuer wire output 6 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 8 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 320 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 322 \clk_sel_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:237" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 296 \dbus__ack @@ -367881,209 +367605,209 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 297 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 19 \eint_0__core__i + wire output 273 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 20 \eint_0__pad__i + wire input 274 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 21 \eint_1__core__i + wire output 275 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 22 \eint_1__pad__i + wire input 276 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 23 \eint_2__core__i + wire output 277 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \eint_2__pad__i + wire input 278 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 37 \gpio_e10__core__i + wire output 181 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_e10__core__o + wire input 182 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_e10__core__oe + wire input 183 \gpio_e10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_e10__pad__i + wire input 184 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 41 \gpio_e10__pad__o + wire output 185 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 42 \gpio_e10__pad__oe + wire output 186 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 43 \gpio_e11__core__i + wire output 187 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_e11__core__o + wire input 188 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_e11__core__oe + wire input 189 \gpio_e11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_e11__pad__i + wire input 190 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 47 \gpio_e11__pad__o + wire output 191 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 48 \gpio_e11__pad__oe + wire output 192 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 49 \gpio_e12__core__i + wire output 193 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_e12__core__o + wire input 194 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_e12__core__oe + wire input 195 \gpio_e12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_e12__pad__i + wire input 196 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 53 \gpio_e12__pad__o + wire output 197 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 54 \gpio_e12__pad__oe + wire output 198 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 55 \gpio_e13__core__i + wire output 199 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_e13__core__o + wire input 200 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_e13__core__oe + wire input 201 \gpio_e13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_e13__pad__i + wire input 202 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 59 \gpio_e13__pad__o + wire output 203 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 60 \gpio_e13__pad__oe + wire output 204 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 61 \gpio_e14__core__i + wire output 205 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \gpio_e14__core__o + wire input 206 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \gpio_e14__core__oe + wire input 207 \gpio_e14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \gpio_e14__pad__i + wire input 208 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 65 \gpio_e14__pad__o + wire output 209 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 66 \gpio_e14__pad__oe + wire output 210 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 67 \gpio_e15__core__i + wire output 211 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \gpio_e15__core__o + wire input 212 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \gpio_e15__core__oe + wire input 213 \gpio_e15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \gpio_e15__pad__i + wire input 214 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 71 \gpio_e15__pad__o + wire output 215 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 72 \gpio_e15__pad__oe + wire output 216 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 25 \gpio_e8__core__i + wire output 169 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \gpio_e8__core__o + wire input 170 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e8__core__oe + wire input 171 \gpio_e8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e8__pad__i + wire input 172 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 29 \gpio_e8__pad__o + wire output 173 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 30 \gpio_e8__pad__oe + wire output 174 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 31 \gpio_e9__core__i + wire output 175 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e9__core__o + wire input 176 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e9__core__oe + wire input 177 \gpio_e9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e9__pad__i + wire input 178 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 35 \gpio_e9__pad__o + wire output 179 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 36 \gpio_e9__pad__oe + wire output 180 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 73 \gpio_s0__core__i + wire output 217 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \gpio_s0__core__o + wire input 218 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \gpio_s0__core__oe + wire input 219 \gpio_s0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \gpio_s0__pad__i + wire input 220 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 77 \gpio_s0__pad__o + wire output 221 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 78 \gpio_s0__pad__oe + wire output 222 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 79 \gpio_s1__core__i + wire output 223 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \gpio_s1__core__o + wire input 224 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \gpio_s1__core__oe + wire input 225 \gpio_s1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \gpio_s1__pad__i + wire input 226 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 83 \gpio_s1__pad__o + wire output 227 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 84 \gpio_s1__pad__oe + wire output 228 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 85 \gpio_s2__core__i + wire output 229 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \gpio_s2__core__o + wire input 230 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \gpio_s2__core__oe + wire input 231 \gpio_s2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \gpio_s2__pad__i + wire input 232 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 89 \gpio_s2__pad__o + wire output 233 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 90 \gpio_s2__pad__oe + wire output 234 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 91 \gpio_s3__core__i + wire output 235 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \gpio_s3__core__o + wire input 236 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \gpio_s3__core__oe + wire input 237 \gpio_s3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \gpio_s3__pad__i + wire input 238 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 95 \gpio_s3__pad__o + wire output 239 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 96 \gpio_s3__pad__oe + wire output 240 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 97 \gpio_s4__core__i + wire output 241 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \gpio_s4__core__o + wire input 242 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \gpio_s4__core__oe + wire input 243 \gpio_s4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \gpio_s4__pad__i + wire input 244 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 101 \gpio_s4__pad__o + wire output 245 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 102 \gpio_s4__pad__oe + wire output 246 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 103 \gpio_s5__core__i + wire output 247 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \gpio_s5__core__o + wire input 248 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \gpio_s5__core__oe + wire input 249 \gpio_s5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \gpio_s5__pad__i + wire input 250 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 107 \gpio_s5__pad__o + wire output 251 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 108 \gpio_s5__pad__oe + wire output 252 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 109 \gpio_s6__core__i + wire output 253 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \gpio_s6__core__o + wire input 254 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \gpio_s6__core__oe + wire input 255 \gpio_s6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \gpio_s6__pad__i + wire input 256 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 113 \gpio_s6__pad__o + wire output 257 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 114 \gpio_s6__pad__oe + wire output 258 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 115 \gpio_s7__core__i + wire output 259 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \gpio_s7__core__o + wire input 260 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \gpio_s7__core__oe + wire input 261 \gpio_s7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \gpio_s7__pad__i + wire input 262 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 119 \gpio_s7__pad__o + wire output 263 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 120 \gpio_s7__pad__oe + wire output 264 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 285 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" @@ -368162,359 +367886,336 @@ module \test_issuer wire output 15 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 16 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" wire input 3 \memerr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \mspi0_clk__core__o + wire input 19 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 122 \mspi0_clk__pad__o + wire output 20 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \mspi0_cs_n__core__o + wire input 21 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 124 \mspi0_cs_n__pad__o + wire output 22 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 127 \mspi0_miso__core__i + wire output 25 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \mspi0_miso__pad__i + wire input 26 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \mspi0_mosi__core__o + wire input 23 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 126 \mspi0_mosi__pad__o + wire output 24 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \mtwi_scl__core__o + wire input 271 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 136 \mtwi_scl__pad__o + wire output 272 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 129 \mtwi_sda__core__i + wire output 265 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \mtwi_sda__core__o + wire input 266 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \mtwi_sda__core__oe + wire input 267 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \mtwi_sda__pad__i + wire input 268 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 133 \mtwi_sda__pad__o + wire output 269 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 134 \mtwi_sda__pad__oe + wire output 270 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - wire width 64 input 325 \pc_i + wire width 64 input 322 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 1 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:234" wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1088" - wire output 323 \pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" - wire \pll_clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" - wire \pll_clk_pll_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 324 \pll_lck_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" - wire \pll_pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1103" - wire \pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1103" - wire \pllclk_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 321 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 187 \sdr_a_0__core__o + wire input 77 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \sdr_a_0__pad__o + wire output 78 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 223 \sdr_a_10__core__o + wire input 113 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \sdr_a_10__pad__o + wire output 114 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 225 \sdr_a_11__core__o + wire input 115 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \sdr_a_11__pad__o + wire output 116 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 227 \sdr_a_12__core__o + wire input 117 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \sdr_a_12__pad__o + wire output 118 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 189 \sdr_a_1__core__o + wire input 79 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \sdr_a_1__pad__o + wire output 80 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 191 \sdr_a_2__core__o + wire input 81 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \sdr_a_2__pad__o + wire output 82 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 193 \sdr_a_3__core__o + wire input 83 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \sdr_a_3__pad__o + wire output 84 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 195 \sdr_a_4__core__o + wire input 85 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \sdr_a_4__pad__o + wire output 86 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 197 \sdr_a_5__core__o + wire input 87 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \sdr_a_5__pad__o + wire output 88 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 199 \sdr_a_6__core__o + wire input 89 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \sdr_a_6__pad__o + wire output 90 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 201 \sdr_a_7__core__o + wire input 91 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \sdr_a_7__pad__o + wire output 92 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 203 \sdr_a_8__core__o + wire input 93 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \sdr_a_8__pad__o + wire output 94 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 205 \sdr_a_9__core__o + wire input 95 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \sdr_a_9__pad__o + wire output 96 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 207 \sdr_ba_0__core__o + wire input 97 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \sdr_ba_0__pad__o + wire output 98 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 209 \sdr_ba_1__core__o + wire input 99 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \sdr_ba_1__pad__o + wire output 100 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 217 \sdr_cas_n__core__o + wire input 107 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \sdr_cas_n__pad__o + wire output 108 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 213 \sdr_cke__core__o + wire input 103 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \sdr_cke__pad__o + wire output 104 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 211 \sdr_clock__core__o + wire input 101 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \sdr_clock__pad__o + wire output 102 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 221 \sdr_cs_n__core__o + wire input 111 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \sdr_cs_n__pad__o + wire output 112 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_dm_0__core__o + wire input 27 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 138 \sdr_dm_0__pad__o + wire output 28 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 229 \sdr_dm_1__core__o + wire input 119 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sdr_dm_1__pad__o + wire output 120 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 139 \sdr_dq_0__core__i + wire output 29 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dq_0__core__o + wire input 30 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_0__core__oe + wire input 31 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_0__pad__i + wire input 32 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 143 \sdr_dq_0__pad__o + wire output 33 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 144 \sdr_dq_0__pad__oe + wire output 34 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sdr_dq_10__core__i + wire output 133 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 244 \sdr_dq_10__core__o + wire input 134 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 245 \sdr_dq_10__core__oe + wire input 135 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 246 \sdr_dq_10__pad__i + wire input 136 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dq_10__pad__o + wire output 137 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_10__pad__oe + wire output 138 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_11__core__i + wire output 139 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 250 \sdr_dq_11__core__o + wire input 140 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 251 \sdr_dq_11__core__oe + wire input 141 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 252 \sdr_dq_11__pad__i + wire input 142 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_11__pad__o + wire output 143 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_11__pad__oe + wire output 144 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_12__core__i + wire output 145 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 256 \sdr_dq_12__core__o + wire input 146 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 257 \sdr_dq_12__core__oe + wire input 147 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 258 \sdr_dq_12__pad__i + wire input 148 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_12__pad__o + wire output 149 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_12__pad__oe + wire output 150 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_13__core__i + wire output 151 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 262 \sdr_dq_13__core__o + wire input 152 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 263 \sdr_dq_13__core__oe + wire input 153 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 264 \sdr_dq_13__pad__i + wire input 154 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_13__pad__o + wire output 155 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_13__pad__oe + wire output 156 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_14__core__i + wire output 157 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 268 \sdr_dq_14__core__o + wire input 158 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 269 \sdr_dq_14__core__oe + wire input 159 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 270 \sdr_dq_14__pad__i + wire input 160 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_dq_14__pad__o + wire output 161 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_dq_14__pad__oe + wire output 162 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dq_15__core__i + wire output 163 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 274 \sdr_dq_15__core__o + wire input 164 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 275 \sdr_dq_15__core__oe + wire input 165 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 276 \sdr_dq_15__pad__i + wire input 166 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_dq_15__pad__o + wire output 167 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_dq_15__pad__oe + wire output 168 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 145 \sdr_dq_1__core__i + wire output 35 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_1__core__o + wire input 36 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_1__core__oe + wire input 37 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_1__pad__i + wire input 38 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 149 \sdr_dq_1__pad__o + wire output 39 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 150 \sdr_dq_1__pad__oe + wire output 40 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 151 \sdr_dq_2__core__i + wire output 41 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_2__core__o + wire input 42 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_2__core__oe + wire input 43 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_2__pad__i + wire input 44 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 155 \sdr_dq_2__pad__o + wire output 45 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 156 \sdr_dq_2__pad__oe + wire output 46 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 157 \sdr_dq_3__core__i + wire output 47 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_3__core__o + wire input 48 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_3__core__oe + wire input 49 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_3__pad__i + wire input 50 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 161 \sdr_dq_3__pad__o + wire output 51 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 162 \sdr_dq_3__pad__oe + wire output 52 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 163 \sdr_dq_4__core__i + wire output 53 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sdr_dq_4__core__o + wire input 54 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 165 \sdr_dq_4__core__oe + wire input 55 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 166 \sdr_dq_4__pad__i + wire input 56 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \sdr_dq_4__pad__o + wire output 57 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \sdr_dq_4__pad__oe + wire output 58 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \sdr_dq_5__core__i + wire output 59 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 170 \sdr_dq_5__core__o + wire input 60 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 171 \sdr_dq_5__core__oe + wire input 61 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 172 \sdr_dq_5__pad__i + wire input 62 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \sdr_dq_5__pad__o + wire output 63 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \sdr_dq_5__pad__oe + wire output 64 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \sdr_dq_6__core__i + wire output 65 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 176 \sdr_dq_6__core__o + wire input 66 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 177 \sdr_dq_6__core__oe + wire input 67 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 178 \sdr_dq_6__pad__i + wire input 68 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \sdr_dq_6__pad__o + wire output 69 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \sdr_dq_6__pad__oe + wire output 70 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \sdr_dq_7__core__i + wire output 71 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 182 \sdr_dq_7__core__o + wire input 72 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 183 \sdr_dq_7__core__oe + wire input 73 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 184 \sdr_dq_7__pad__i + wire input 74 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \sdr_dq_7__pad__o + wire output 75 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \sdr_dq_7__pad__oe + wire output 76 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sdr_dq_8__core__i + wire output 121 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 232 \sdr_dq_8__core__o + wire input 122 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 233 \sdr_dq_8__core__oe + wire input 123 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 234 \sdr_dq_8__pad__i + wire input 124 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sdr_dq_8__pad__o + wire output 125 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sdr_dq_8__pad__oe + wire output 126 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sdr_dq_9__core__i + wire output 127 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 238 \sdr_dq_9__core__o + wire input 128 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 239 \sdr_dq_9__core__oe + wire input 129 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 240 \sdr_dq_9__pad__i + wire input 130 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sdr_dq_9__pad__o + wire output 131 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sdr_dq_9__pad__oe + wire output 132 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 215 \sdr_ras_n__core__o + wire input 105 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \sdr_ras_n__pad__o + wire output 106 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 219 \sdr_we_n__core__o + wire input 109 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + wire output 110 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire \ti_coresync_clk attribute \module_not_derived 1 - attribute \src "libresoc.v:194923.7-194929.4" - cell \pll \pll - connect \clk_24_i \pll_clk_24_i - connect \clk_pll_o \pll_clk_pll_o - connect \clk_sel_i \clk_sel_i - connect \pll_18_o \pll_pll_18_o - connect \pll_lck_o \pll_lck_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:194930.6-195243.4" + attribute \src "libresoc.v:194657.6-194970.4" cell \ti \ti connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -368829,2054 +368530,1912 @@ module \test_issuer connect \sdr_we_n__core__o \sdr_we_n__core__o connect \sdr_we_n__pad__o \sdr_we_n__pad__o end - connect \ti_coresync_clk \pll_clk_pll_o - connect \pllclk_rst \rst - connect \pll_18_o \pll_pll_18_o - connect \pll_clk_24_i \clk - connect \pllclk_clk \pll_clk_pll_o + connect \ti_coresync_clk \clk end -attribute \src "libresoc.v:195253.1-200575.10" +attribute \src "libresoc.v:194976.1-200172.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" module \ti - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $0\core_asmcode$next[7:0]$13574 - attribute \src "libresoc.v:197683.3-197684.41" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 8 $0\core_asmcode$next[7:0]$13561 + attribute \src "libresoc.v:197205.3-197206.41" wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:198494.3-198538.6" - wire $0\core_bigendian_i$10$next[0:0]$13369 - attribute \src "libresoc.v:197813.3-197814.57" - wire $0\core_bigendian_i$10[0:0]$13294 - attribute \src "libresoc.v:195528.7-195528.35" - wire $0\core_bigendian_i$10[0:0]$13787 - attribute \src "libresoc.v:199257.3-199269.6" + attribute \src "libresoc.v:198018.3-198053.6" + wire $0\core_bigendian_i$10$next[0:0]$13357 + attribute \src "libresoc.v:197335.3-197336.57" + wire $0\core_bigendian_i$10[0:0]$13293 + attribute \src "libresoc.v:195253.7-195253.35" + wire $0\core_bigendian_i$10[0:0]$13715 + attribute \src "libresoc.v:198699.3-198711.6" wire width 3 $0\core_cia__ren[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 64 $0\core_core_core_cia$next[63:0]$13575 - attribute \src "libresoc.v:197757.3-197758.53" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 64 $0\core_core_core_cia$next[63:0]$13562 + attribute \src "libresoc.v:197279.3-197280.53" wire width 64 $0\core_core_core_cia[63:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$13576 - attribute \src "libresoc.v:197801.3-197802.57" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$13563 + attribute \src "libresoc.v:197323.3-197324.57" wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$13577 - attribute \src "libresoc.v:197803.3-197804.63" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$13564 + attribute \src "libresoc.v:197325.3-197326.63" wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$13578 - attribute \src "libresoc.v:197805.3-197806.57" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$13565 + attribute \src "libresoc.v:197327.3-197328.57" wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_exc_$signal$3$next[0:0]$13579 - attribute \src "libresoc.v:197783.3-197784.75" - wire $0\core_core_core_exc_$signal$3[0:0]$13272 - attribute \src "libresoc.v:195554.7-195554.44" - wire $0\core_core_core_exc_$signal$3[0:0]$13795 - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_exc_$signal$4$next[0:0]$13580 - attribute \src "libresoc.v:197785.3-197786.75" - wire $0\core_core_core_exc_$signal$4[0:0]$13274 - attribute \src "libresoc.v:195558.7-195558.44" - wire $0\core_core_core_exc_$signal$4[0:0]$13797 - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_exc_$signal$5$next[0:0]$13581 - attribute \src "libresoc.v:197787.3-197788.75" - wire $0\core_core_core_exc_$signal$5[0:0]$13276 - attribute \src "libresoc.v:195562.7-195562.44" - wire $0\core_core_core_exc_$signal$5[0:0]$13799 - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_exc_$signal$6$next[0:0]$13582 - attribute \src "libresoc.v:197789.3-197790.75" - wire $0\core_core_core_exc_$signal$6[0:0]$13278 - attribute \src "libresoc.v:195566.7-195566.44" - wire $0\core_core_core_exc_$signal$6[0:0]$13801 - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_exc_$signal$7$next[0:0]$13583 - attribute \src "libresoc.v:197793.3-197794.75" - wire $0\core_core_core_exc_$signal$7[0:0]$13281 - attribute \src "libresoc.v:195570.7-195570.44" - wire $0\core_core_core_exc_$signal$7[0:0]$13803 - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_exc_$signal$8$next[0:0]$13584 - attribute \src "libresoc.v:197795.3-197796.75" - wire $0\core_core_core_exc_$signal$8[0:0]$13283 - attribute \src "libresoc.v:195574.7-195574.44" - wire $0\core_core_core_exc_$signal$8[0:0]$13805 - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_exc_$signal$9$next[0:0]$13585 - attribute \src "libresoc.v:197797.3-197798.75" - wire $0\core_core_core_exc_$signal$9[0:0]$13285 - attribute \src "libresoc.v:195578.7-195578.44" - wire $0\core_core_core_exc_$signal$9[0:0]$13807 - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_exc_$signal$next[0:0]$13586 - attribute \src "libresoc.v:197781.3-197782.71" - wire $0\core_core_core_exc_$signal[0:0]$13270 - attribute \src "libresoc.v:195552.7-195552.42" - wire $0\core_core_core_exc_$signal[0:0]$13793 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 14 $0\core_core_core_fn_unit$next[13:0]$13587 - attribute \src "libresoc.v:197763.3-197764.61" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$13566 + attribute \src "libresoc.v:197305.3-197306.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13271 + attribute \src "libresoc.v:195279.7-195279.44" + wire $0\core_core_core_exc_$signal$3[0:0]$13723 + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$13567 + attribute \src "libresoc.v:197307.3-197308.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13273 + attribute \src "libresoc.v:195283.7-195283.44" + wire $0\core_core_core_exc_$signal$4[0:0]$13725 + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$13568 + attribute \src "libresoc.v:197309.3-197310.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13275 + attribute \src "libresoc.v:195287.7-195287.44" + wire $0\core_core_core_exc_$signal$5[0:0]$13727 + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$13569 + attribute \src "libresoc.v:197311.3-197312.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13277 + attribute \src "libresoc.v:195291.7-195291.44" + wire $0\core_core_core_exc_$signal$6[0:0]$13729 + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$13570 + attribute \src "libresoc.v:197315.3-197316.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13280 + attribute \src "libresoc.v:195295.7-195295.44" + wire $0\core_core_core_exc_$signal$7[0:0]$13731 + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$13571 + attribute \src "libresoc.v:197317.3-197318.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13282 + attribute \src "libresoc.v:195299.7-195299.44" + wire $0\core_core_core_exc_$signal$8[0:0]$13733 + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$13572 + attribute \src "libresoc.v:197319.3-197320.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13284 + attribute \src "libresoc.v:195303.7-195303.44" + wire $0\core_core_core_exc_$signal$9[0:0]$13735 + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_exc_$signal$next[0:0]$13573 + attribute \src "libresoc.v:197303.3-197304.71" + wire $0\core_core_core_exc_$signal[0:0]$13269 + attribute \src "libresoc.v:195277.7-195277.42" + wire $0\core_core_core_exc_$signal[0:0]$13721 + attribute \src "libresoc.v:200001.3-200122.6" + wire width 14 $0\core_core_core_fn_unit$next[13:0]$13574 + attribute \src "libresoc.v:197285.3-197286.61" wire width 14 $0\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$13588 - attribute \src "libresoc.v:197777.3-197778.69" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$13575 + attribute \src "libresoc.v:197299.3-197300.69" wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 32 $0\core_core_core_insn$next[31:0]$13589 - attribute \src "libresoc.v:197759.3-197760.55" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 32 $0\core_core_core_insn$next[31:0]$13576 + attribute \src "libresoc.v:197281.3-197282.55" wire width 32 $0\core_core_core_insn[31:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$13590 - attribute \src "libresoc.v:197761.3-197762.65" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$13577 + attribute \src "libresoc.v:197283.3-197284.65" wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_is_32bit$next[0:0]$13591 - attribute \src "libresoc.v:197809.3-197810.63" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_is_32bit$next[0:0]$13578 + attribute \src "libresoc.v:197331.3-197332.63" wire $0\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 64 $0\core_core_core_msr$next[63:0]$13592 - attribute \src "libresoc.v:197755.3-197756.53" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 64 $0\core_core_core_msr$next[63:0]$13579 + attribute \src "libresoc.v:197277.3-197278.53" wire width 64 $0\core_core_core_msr[63:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_oe$next[0:0]$13593 - attribute \src "libresoc.v:197773.3-197774.51" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_oe$next[0:0]$13580 + attribute \src "libresoc.v:197295.3-197296.51" wire $0\core_core_core_oe[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_oe_ok$next[0:0]$13594 - attribute \src "libresoc.v:197775.3-197776.57" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_oe_ok$next[0:0]$13581 + attribute \src "libresoc.v:197297.3-197298.57" wire $0\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_rc$next[0:0]$13595 - attribute \src "libresoc.v:197767.3-197768.51" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_rc$next[0:0]$13582 + attribute \src "libresoc.v:197289.3-197290.51" wire $0\core_core_core_rc[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_core_rc_ok$next[0:0]$13596 - attribute \src "libresoc.v:197771.3-197772.57" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_core_rc_ok$next[0:0]$13583 + attribute \src "libresoc.v:197293.3-197294.57" wire $0\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$13597 - attribute \src "libresoc.v:197799.3-197800.63" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$13584 + attribute \src "libresoc.v:197321.3-197322.63" wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $0\core_core_core_traptype$next[7:0]$13598 - attribute \src "libresoc.v:197779.3-197780.63" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$13585 + attribute \src "libresoc.v:197301.3-197302.63" wire width 8 $0\core_core_core_traptype[7:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $0\core_core_cr_in1$next[6:0]$13599 - attribute \src "libresoc.v:197737.3-197738.49" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $0\core_core_cr_in1$next[6:0]$13586 + attribute \src "libresoc.v:197259.3-197260.49" wire width 7 $0\core_core_cr_in1[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_cr_in1_ok$next[0:0]$13600 - attribute \src "libresoc.v:197739.3-197740.55" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_cr_in1_ok$next[0:0]$13587 + attribute \src "libresoc.v:197261.3-197262.55" wire $0\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $0\core_core_cr_in2$1$next[6:0]$13601 - attribute \src "libresoc.v:197745.3-197746.55" - wire width 7 $0\core_core_cr_in2$1[6:0]$13250 - attribute \src "libresoc.v:195736.13-195736.41" - wire width 7 $0\core_core_cr_in2$1[6:0]$13824 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $0\core_core_cr_in2$next[6:0]$13602 - attribute \src "libresoc.v:197741.3-197742.49" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $0\core_core_cr_in2$1$next[6:0]$13588 + attribute \src "libresoc.v:197267.3-197268.55" + wire width 7 $0\core_core_cr_in2$1[6:0]$13249 + attribute \src "libresoc.v:195461.13-195461.41" + wire width 7 $0\core_core_cr_in2$1[6:0]$13752 + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $0\core_core_cr_in2$next[6:0]$13589 + attribute \src "libresoc.v:197263.3-197264.49" wire width 7 $0\core_core_cr_in2[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$13603 - attribute \src "libresoc.v:197749.3-197750.61" - wire $0\core_core_cr_in2_ok$2[0:0]$13253 - attribute \src "libresoc.v:195744.7-195744.37" - wire $0\core_core_cr_in2_ok$2[0:0]$13827 - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_cr_in2_ok$next[0:0]$13604 - attribute \src "libresoc.v:197743.3-197744.55" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$13590 + attribute \src "libresoc.v:197271.3-197272.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13252 + attribute \src "libresoc.v:195469.7-195469.37" + wire $0\core_core_cr_in2_ok$2[0:0]$13755 + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_cr_in2_ok$next[0:0]$13591 + attribute \src "libresoc.v:197265.3-197266.55" wire $0\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $0\core_core_cr_out$next[6:0]$13605 - attribute \src "libresoc.v:197751.3-197752.49" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $0\core_core_cr_out$next[6:0]$13592 + attribute \src "libresoc.v:197273.3-197274.49" wire width 7 $0\core_core_cr_out[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_cr_wr_ok$next[0:0]$13606 - attribute \src "libresoc.v:197807.3-197808.53" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_cr_wr_ok$next[0:0]$13593 + attribute \src "libresoc.v:197329.3-197330.53" wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $0\core_core_dststep$next[6:0]$13323 - attribute \src "libresoc.v:197673.3-197674.51" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $0\core_core_dststep$next[6:0]$13322 + attribute \src "libresoc.v:197195.3-197196.51" wire width 7 $0\core_core_dststep[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $0\core_core_ea$next[6:0]$13607 - attribute \src "libresoc.v:197689.3-197690.41" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $0\core_core_ea$next[6:0]$13594 + attribute \src "libresoc.v:197211.3-197212.41" wire width 7 $0\core_core_ea[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $0\core_core_fast1$next[2:0]$13608 - attribute \src "libresoc.v:197719.3-197720.47" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 3 $0\core_core_fast1$next[2:0]$13595 + attribute \src "libresoc.v:197241.3-197242.47" wire width 3 $0\core_core_fast1[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_fast1_ok$next[0:0]$13609 - attribute \src "libresoc.v:197721.3-197722.53" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_fast1_ok$next[0:0]$13596 + attribute \src "libresoc.v:197243.3-197244.53" wire $0\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $0\core_core_fast2$next[2:0]$13610 - attribute \src "libresoc.v:197723.3-197724.47" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 3 $0\core_core_fast2$next[2:0]$13597 + attribute \src "libresoc.v:197245.3-197246.47" wire width 3 $0\core_core_fast2[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_fast2_ok$next[0:0]$13611 - attribute \src "libresoc.v:197727.3-197728.53" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_fast2_ok$next[0:0]$13598 + attribute \src "libresoc.v:197249.3-197250.53" wire $0\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $0\core_core_fasto1$next[2:0]$13612 - attribute \src "libresoc.v:197729.3-197730.49" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 3 $0\core_core_fasto1$next[2:0]$13599 + attribute \src "libresoc.v:197251.3-197252.49" wire width 3 $0\core_core_fasto1[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $0\core_core_fasto2$next[2:0]$13613 - attribute \src "libresoc.v:197733.3-197734.49" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 3 $0\core_core_fasto2$next[2:0]$13600 + attribute \src "libresoc.v:197255.3-197256.49" wire width 3 $0\core_core_fasto2[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_lk$next[0:0]$13614 - attribute \src "libresoc.v:197765.3-197766.41" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_lk$next[0:0]$13601 + attribute \src "libresoc.v:197287.3-197288.41" wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $0\core_core_maxvl$next[6:0]$13324 - attribute \src "libresoc.v:197679.3-197680.47" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $0\core_core_maxvl$next[6:0]$13323 + attribute \src "libresoc.v:197201.3-197202.47" wire width 7 $0\core_core_maxvl[6:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $0\core_core_pc$next[63:0]$13325 - attribute \src "libresoc.v:197651.3-197652.41" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 64 $0\core_core_pc$next[63:0]$13324 + attribute \src "libresoc.v:197173.3-197174.41" wire width 64 $0\core_core_pc[63:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $0\core_core_reg1$next[6:0]$13615 - attribute \src "libresoc.v:197693.3-197694.45" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $0\core_core_reg1$next[6:0]$13602 + attribute \src "libresoc.v:197215.3-197216.45" wire width 7 $0\core_core_reg1[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_reg1_ok$next[0:0]$13616 - attribute \src "libresoc.v:197695.3-197696.51" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_reg1_ok$next[0:0]$13603 + attribute \src "libresoc.v:197217.3-197218.51" wire $0\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $0\core_core_reg2$next[6:0]$13617 - attribute \src "libresoc.v:197697.3-197698.45" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $0\core_core_reg2$next[6:0]$13604 + attribute \src "libresoc.v:197219.3-197220.45" wire width 7 $0\core_core_reg2[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_reg2_ok$next[0:0]$13618 - attribute \src "libresoc.v:197699.3-197700.51" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_reg2_ok$next[0:0]$13605 + attribute \src "libresoc.v:197221.3-197222.51" wire $0\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $0\core_core_reg3$next[6:0]$13619 - attribute \src "libresoc.v:197701.3-197702.45" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $0\core_core_reg3$next[6:0]$13606 + attribute \src "libresoc.v:197223.3-197224.45" wire width 7 $0\core_core_reg3[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_reg3_ok$next[0:0]$13620 - attribute \src "libresoc.v:197705.3-197706.51" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_reg3_ok$next[0:0]$13607 + attribute \src "libresoc.v:197227.3-197228.51" wire $0\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $0\core_core_rego$next[6:0]$13621 - attribute \src "libresoc.v:197685.3-197686.45" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $0\core_core_rego$next[6:0]$13608 + attribute \src "libresoc.v:197207.3-197208.45" wire width 7 $0\core_core_rego[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 10 $0\core_core_spr1$next[9:0]$13622 - attribute \src "libresoc.v:197711.3-197712.45" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 10 $0\core_core_spr1$next[9:0]$13609 + attribute \src "libresoc.v:197233.3-197234.45" wire width 10 $0\core_core_spr1[9:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_core_spr1_ok$next[0:0]$13623 - attribute \src "libresoc.v:197713.3-197714.51" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_core_spr1_ok$next[0:0]$13610 + attribute \src "libresoc.v:197235.3-197236.51" wire $0\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 10 $0\core_core_spro$next[9:0]$13624 - attribute \src "libresoc.v:197707.3-197708.45" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 10 $0\core_core_spro$next[9:0]$13611 + attribute \src "libresoc.v:197229.3-197230.45" wire width 10 $0\core_core_spro[9:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $0\core_core_srcstep$next[6:0]$13326 - attribute \src "libresoc.v:197675.3-197676.51" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $0\core_core_srcstep$next[6:0]$13325 + attribute \src "libresoc.v:197197.3-197198.51" wire width 7 $0\core_core_srcstep[6:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 2 $0\core_core_subvl$next[1:0]$13327 - attribute \src "libresoc.v:197671.3-197672.47" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 2 $0\core_core_subvl$next[1:0]$13326 + attribute \src "libresoc.v:197193.3-197194.47" wire width 2 $0\core_core_subvl[1:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 2 $0\core_core_svstep$next[1:0]$13328 - attribute \src "libresoc.v:197669.3-197670.49" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 2 $0\core_core_svstep$next[1:0]$13327 + attribute \src "libresoc.v:197191.3-197192.49" wire width 2 $0\core_core_svstep[1:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $0\core_core_vl$next[6:0]$13329 - attribute \src "libresoc.v:197677.3-197678.41" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $0\core_core_vl$next[6:0]$13328 + attribute \src "libresoc.v:197199.3-197200.41" wire width 7 $0\core_core_vl[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $0\core_core_xer_in$next[2:0]$13625 - attribute \src "libresoc.v:197715.3-197716.49" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 3 $0\core_core_xer_in$next[2:0]$13612 + attribute \src "libresoc.v:197237.3-197238.49" wire width 3 $0\core_core_xer_in[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_cr_out_ok$next[0:0]$13626 - attribute \src "libresoc.v:197753.3-197754.45" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_cr_out_ok$next[0:0]$13613 + attribute \src "libresoc.v:197275.3-197276.45" wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:198786.3-198795.6" - wire width 64 $0\core_data_i$12[63:0]$13388 - attribute \src "libresoc.v:199388.3-199467.6" + attribute \src "libresoc.v:198228.3-198237.6" + wire width 64 $0\core_data_i$12[63:0]$13371 + attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $0\core_data_i[63:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $0\core_dec$next[63:0]$13330 - attribute \src "libresoc.v:197667.3-197668.33" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 64 $0\core_dec$next[63:0]$13329 + attribute \src "libresoc.v:197189.3-197190.33" wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:198903.3-198912.6" + attribute \src "libresoc.v:198345.3-198354.6" wire width 5 $0\core_dmi__addr[4:0] - attribute \src "libresoc.v:198913.3-198922.6" + attribute \src "libresoc.v:198355.3-198364.6" wire $0\core_dmi__ren[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_ea_ok$next[0:0]$13627 - attribute \src "libresoc.v:197691.3-197692.37" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_ea_ok$next[0:0]$13614 + attribute \src "libresoc.v:197213.3-197214.37" wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire $0\core_eint$next[0:0]$13331 - attribute \src "libresoc.v:197665.3-197666.35" + attribute \src "libresoc.v:197926.3-197981.6" + wire $0\core_eint$next[0:0]$13330 + attribute \src "libresoc.v:197187.3-197188.35" wire $0\core_eint[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_fasto1_ok$next[0:0]$13628 - attribute \src "libresoc.v:197731.3-197732.45" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_fasto1_ok$next[0:0]$13615 + attribute \src "libresoc.v:197253.3-197254.45" wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_fasto2_ok$next[0:0]$13629 - attribute \src "libresoc.v:197735.3-197736.45" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_fasto2_ok$next[0:0]$13616 + attribute \src "libresoc.v:197257.3-197258.45" wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:198952.3-198961.6" + attribute \src "libresoc.v:198394.3-198403.6" wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:198991.3-199000.6" + attribute \src "libresoc.v:198433.3-198442.6" wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "libresoc.v:199111.3-199133.6" - wire width 3 $0\core_issue__addr$13[2:0]$13428 - attribute \src "libresoc.v:199030.3-199048.6" + attribute \src "libresoc.v:198553.3-198575.6" + wire width 3 $0\core_issue__addr$13[2:0]$13411 + attribute \src "libresoc.v:198472.3-198490.6" wire width 3 $0\core_issue__addr[2:0] - attribute \src "libresoc.v:199157.3-199179.6" + attribute \src "libresoc.v:198599.3-198621.6" wire width 64 $0\core_issue__data_i[63:0] - attribute \src "libresoc.v:199049.3-199067.6" + attribute \src "libresoc.v:198491.3-198509.6" wire $0\core_issue__ren[0:0] - attribute \src "libresoc.v:199134.3-199156.6" + attribute \src "libresoc.v:198576.3-198598.6" wire $0\core_issue__wen[0:0] - attribute \src "libresoc.v:198832.3-198847.6" + attribute \src "libresoc.v:198274.3-198289.6" wire $0\core_issue_i[0:0] - attribute \src "libresoc.v:198807.3-198831.6" + attribute \src "libresoc.v:198249.3-198273.6" wire $0\core_ivalid_i[0:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $0\core_msr$next[63:0]$13332 - attribute \src "libresoc.v:197663.3-197664.33" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 64 $0\core_msr$next[63:0]$13331 + attribute \src "libresoc.v:197185.3-197186.33" wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:199468.3-199483.6" + attribute \src "libresoc.v:198926.3-198941.6" wire width 3 $0\core_msr__ren[2:0] - attribute \src "libresoc.v:198469.3-198493.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$13364 - attribute \src "libresoc.v:197835.3-197836.47" + attribute \src "libresoc.v:197982.3-198017.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13353 + attribute \src "libresoc.v:197357.3-197358.47" wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_rego_ok$next[0:0]$13630 - attribute \src "libresoc.v:197687.3-197688.41" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_rego_ok$next[0:0]$13617 + attribute \src "libresoc.v:197209.3-197210.41" wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_spro_ok$next[0:0]$13631 - attribute \src "libresoc.v:197709.3-197710.41" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_spro_ok$next[0:0]$13618 + attribute \src "libresoc.v:197231.3-197232.41" wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:200047.3-200093.6" + attribute \src "libresoc.v:199525.3-199579.6" wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:199295.3-199307.6" + attribute \src "libresoc.v:198737.3-198749.6" wire width 3 $0\core_sv__ren[2:0] - attribute \src "libresoc.v:198539.3-198583.6" - wire $0\core_sv_a_nz$next[0:0]$13374 - attribute \src "libresoc.v:197791.3-197792.41" + attribute \src "libresoc.v:198054.3-198089.6" + wire $0\core_sv_a_nz$next[0:0]$13361 + attribute \src "libresoc.v:197313.3-197314.41" wire $0\core_sv_a_nz[0:0] - attribute \src "libresoc.v:198776.3-198785.6" - wire width 3 $0\core_wen$11[2:0]$13385 - attribute \src "libresoc.v:199308.3-199387.6" + attribute \src "libresoc.v:198218.3-198227.6" + wire width 3 $0\core_wen$11[2:0]$13368 + attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $0\core_wen[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $0\core_xer_out$next[0:0]$13632 - attribute \src "libresoc.v:197717.3-197718.41" + attribute \src "libresoc.v:200001.3-200122.6" + wire $0\core_xer_out$next[0:0]$13619 + attribute \src "libresoc.v:197239.3-197240.41" wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:197849.3-197850.43" + attribute \src "libresoc.v:197371.3-197372.43" wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $0\cur_cur_dststep$next[6:0]$13469 - attribute \src "libresoc.v:197833.3-197834.47" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $0\cur_cur_dststep$next[6:0]$13452 + attribute \src "libresoc.v:197355.3-197356.47" wire width 7 $0\cur_cur_dststep[6:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $0\cur_cur_maxvl$next[6:0]$13470 - attribute \src "libresoc.v:197841.3-197842.43" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $0\cur_cur_maxvl$next[6:0]$13453 + attribute \src "libresoc.v:197363.3-197364.43" wire width 7 $0\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $0\cur_cur_srcstep$next[6:0]$13471 - attribute \src "libresoc.v:197837.3-197838.47" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $0\cur_cur_srcstep$next[6:0]$13454 + attribute \src "libresoc.v:197359.3-197360.47" wire width 7 $0\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 2 $0\cur_cur_subvl$next[1:0]$13472 - attribute \src "libresoc.v:197831.3-197832.43" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 2 $0\cur_cur_subvl$next[1:0]$13455 + attribute \src "libresoc.v:197353.3-197354.43" wire width 2 $0\cur_cur_subvl[1:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 2 $0\cur_cur_svstep$next[1:0]$13473 - attribute \src "libresoc.v:197829.3-197830.45" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 2 $0\cur_cur_svstep$next[1:0]$13456 + attribute \src "libresoc.v:197351.3-197352.45" wire width 2 $0\cur_cur_svstep[1:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $0\cur_cur_vl$next[6:0]$13474 - attribute \src "libresoc.v:197839.3-197840.37" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $0\cur_cur_vl$next[6:0]$13457 + attribute \src "libresoc.v:197361.3-197362.37" wire width 7 $0\cur_cur_vl[6:0] - attribute \src "libresoc.v:198962.3-198970.6" - wire $0\d_cr_delay$next[0:0]$13410 - attribute \src "libresoc.v:197725.3-197726.37" + attribute \src "libresoc.v:198404.3-198412.6" + wire $0\d_cr_delay$next[0:0]$13393 + attribute \src "libresoc.v:197247.3-197248.37" wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:198923.3-198931.6" - wire $0\d_reg_delay$next[0:0]$13404 - attribute \src "libresoc.v:197747.3-197748.39" + attribute \src "libresoc.v:198365.3-198373.6" + wire $0\d_reg_delay$next[0:0]$13387 + attribute \src "libresoc.v:197269.3-197270.39" wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:199001.3-199009.6" - wire $0\d_xer_delay$next[0:0]$13416 - attribute \src "libresoc.v:197703.3-197704.39" + attribute \src "libresoc.v:198443.3-198451.6" + wire $0\d_xer_delay$next[0:0]$13399 + attribute \src "libresoc.v:197225.3-197226.39" wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:200094.3-200140.6" + attribute \src "libresoc.v:199580.3-199634.6" wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:198981.3-198990.6" + attribute \src "libresoc.v:198423.3-198432.6" wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:198971.3-198980.6" + attribute \src "libresoc.v:198413.3-198422.6" wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:198942.3-198951.6" + attribute \src "libresoc.v:198384.3-198393.6" wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:198932.3-198941.6" + attribute \src "libresoc.v:198374.3-198383.6" wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:199020.3-199029.6" + attribute \src "libresoc.v:198462.3-198471.6" wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:199010.3-199019.6" + attribute \src "libresoc.v:198452.3-198461.6" wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:198386.3-198394.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13317 - attribute \src "libresoc.v:197661.3-197662.45" + attribute \src "libresoc.v:197908.3-197916.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13316 + attribute \src "libresoc.v:197183.3-197184.45" wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:199484.3-199492.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$13454 - attribute \src "libresoc.v:197655.3-197656.39" + attribute \src "libresoc.v:198942.3-198950.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13437 + attribute \src "libresoc.v:197177.3-197178.39" wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:198395.3-198403.6" - wire $0\dbg_dmi_req_i$next[0:0]$13320 - attribute \src "libresoc.v:197659.3-197660.43" + attribute \src "libresoc.v:197917.3-197925.6" + wire $0\dbg_dmi_req_i$next[0:0]$13319 + attribute \src "libresoc.v:197181.3-197182.43" wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:199223.3-199231.6" - wire $0\dbg_dmi_we_i$next[0:0]$13438 - attribute \src "libresoc.v:197657.3-197658.41" + attribute \src "libresoc.v:198665.3-198673.6" + wire $0\dbg_dmi_we_i$next[0:0]$13421 + attribute \src "libresoc.v:197179.3-197180.41" wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:199180.3-199199.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$13433 - attribute \src "libresoc.v:197649.3-197650.41" + attribute \src "libresoc.v:198622.3-198641.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13416 + attribute \src "libresoc.v:197171.3-197172.41" wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:200526.3-200534.6" - wire $0\dec2_cur_eint$next[0:0]$13779 - attribute \src "libresoc.v:197853.3-197854.43" + attribute \src "libresoc.v:200123.3-200131.6" + wire $0\dec2_cur_eint$next[0:0]$13707 + attribute \src "libresoc.v:197375.3-197376.43" wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:199750.3-199774.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$13517 - attribute \src "libresoc.v:197823.3-197824.41" + attribute \src "libresoc.v:199208.3-199232.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13500 + attribute \src "libresoc.v:197345.3-197346.41" wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:199597.3-199617.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$13464 - attribute \src "libresoc.v:197843.3-197844.39" + attribute \src "libresoc.v:199055.3-199075.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13447 + attribute \src "libresoc.v:197365.3-197366.39" wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:199798.3-199832.6" - wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13526 - attribute \src "libresoc.v:197819.3-197820.53" + attribute \src "libresoc.v:199256.3-199290.6" + wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13509 + attribute \src "libresoc.v:197341.3-197342.53" wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:200535.3-200544.6" - wire width 2 $0\delay$next[1:0]$13782 - attribute \src "libresoc.v:197851.3-197852.27" + attribute \src "libresoc.v:200132.3-200141.6" + wire width 2 $0\delay$next[1:0]$13710 + attribute \src "libresoc.v:197373.3-197374.27" wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:198848.3-198882.6" - wire $0\exec_fsm_state$next[0:0]$13394 - attribute \src "libresoc.v:197769.3-197770.45" + attribute \src "libresoc.v:198290.3-198324.6" + wire $0\exec_fsm_state$next[0:0]$13377 + attribute \src "libresoc.v:197291.3-197292.45" wire $0\exec_fsm_state[0:0] - attribute \src "libresoc.v:198796.3-198806.6" + attribute \src "libresoc.v:198238.3-198248.6" wire $0\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:198672.3-198698.6" + attribute \src "libresoc.v:198090.3-198124.6" wire $0\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:198699.3-198734.6" + attribute \src "libresoc.v:198125.3-198168.6" wire $0\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198883.3-198902.6" + attribute \src "libresoc.v:198325.3-198344.6" wire $0\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:199696.3-199749.6" - wire width 2 $0\fetch_fsm_state$next[1:0]$13509 - attribute \src "libresoc.v:197825.3-197826.47" + attribute \src "libresoc.v:199154.3-199207.6" + wire width 2 $0\fetch_fsm_state$next[1:0]$13492 + attribute \src "libresoc.v:197347.3-197348.47" wire width 2 $0\fetch_fsm_state[1:0] - attribute \src "libresoc.v:200380.3-200394.6" + attribute \src "libresoc.v:199898.3-199912.6" wire $0\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:199833.3-199855.6" + attribute \src "libresoc.v:199291.3-199313.6" wire $0\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:199493.3-199503.6" + attribute \src "libresoc.v:198951.3-198961.6" wire $0\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:199932.3-199947.6" + attribute \src "libresoc.v:199401.3-199416.6" wire $0\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:199068.3-199095.6" - wire width 2 $0\fsm_state$next[1:0]$13423 - attribute \src "libresoc.v:197681.3-197682.35" + attribute \src "libresoc.v:198510.3-198537.6" + wire width 2 $0\fsm_state$next[1:0]$13406 + attribute \src "libresoc.v:197203.3-197204.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:199504.3-199519.6" + attribute \src "libresoc.v:198962.3-198977.6" wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:199529.3-199562.6" + attribute \src "libresoc.v:198987.3-199020.6" wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199563.3-199596.6" + attribute \src "libresoc.v:199021.3-199054.6" wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:195254.7-195254.20" + attribute \src "libresoc.v:194977.7-194977.20" wire $0\initial[0:0] - attribute \src "libresoc.v:198584.3-198629.6" + attribute \src "libresoc.v:199913.3-199958.6" wire $0\insn_done[0:0] - attribute \src "libresoc.v:198735.3-198775.6" + attribute \src "libresoc.v:198169.3-198217.6" wire $0\is_last[0:0] - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $0\issue_fsm_state$next[2:0]$13534 - attribute \src "libresoc.v:197817.3-197818.47" + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $0\issue_fsm_state$next[2:0]$13517 + attribute \src "libresoc.v:197339.3-197340.47" wire width 3 $0\issue_fsm_state[2:0] - attribute \src "libresoc.v:199520.3-199528.6" - wire $0\jtag_dmi0__ack_o$next[0:0]$13459 - attribute \src "libresoc.v:197653.3-197654.49" + attribute \src "libresoc.v:198978.3-198986.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$13442 + attribute \src "libresoc.v:197175.3-197176.49" wire $0\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:199687.3-199695.6" - wire width 64 $0\jtag_dmi0__dout$next[63:0]$13506 - attribute \src "libresoc.v:197855.3-197856.47" + attribute \src "libresoc.v:199145.3-199153.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13489 + attribute \src "libresoc.v:197377.3-197378.47" wire width 64 $0\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:199657.3-199686.6" - wire $0\msr_read$next[0:0]$13500 - attribute \src "libresoc.v:197827.3-197828.33" + attribute \src "libresoc.v:199115.3-199144.6" + wire $0\msr_read$next[0:0]$13483 + attribute \src "libresoc.v:197349.3-197350.33" wire $0\msr_read[0:0] - attribute \src "libresoc.v:199096.3-199110.6" + attribute \src "libresoc.v:198538.3-198552.6" wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $0\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $0\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $0\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $0\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $0\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $0\new_svstate_vl[6:0] - attribute \src "libresoc.v:199200.3-199222.6" + attribute \src "libresoc.v:198642.3-198664.6" wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:199775.3-199797.6" - wire width 64 $0\nia$next[63:0]$13522 - attribute \src "libresoc.v:197821.3-197822.23" + attribute \src "libresoc.v:199233.3-199255.6" + wire width 64 $0\nia$next[63:0]$13505 + attribute \src "libresoc.v:197343.3-197344.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:199241.3-199256.6" + attribute \src "libresoc.v:198683.3-198698.6" wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:200141.3-200223.6" - wire $0\pc_changed$next[0:0]$13550 - attribute \src "libresoc.v:197815.3-197816.37" + attribute \src "libresoc.v:199635.3-199725.6" + wire $0\pc_changed$next[0:0]$13534 + attribute \src "libresoc.v:197337.3-197338.37" wire $0\pc_changed[0:0] - attribute \src "libresoc.v:199232.3-199240.6" - wire $0\pc_ok_delay$next[0:0]$13441 - attribute \src "libresoc.v:197847.3-197848.39" + attribute \src "libresoc.v:198674.3-198682.6" + wire $0\pc_ok_delay$next[0:0]$13424 + attribute \src "libresoc.v:197369.3-197370.39" wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:198630.3-198648.6" + attribute \src "libresoc.v:199959.3-199977.6" wire $0\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:198649.3-198671.6" + attribute \src "libresoc.v:199978.3-200000.6" wire $0\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:200297.3-200379.6" - wire $0\sv_changed$next[0:0]$13562 - attribute \src "libresoc.v:197811.3-197812.37" + attribute \src "libresoc.v:199807.3-199897.6" + wire $0\sv_changed$next[0:0]$13546 + attribute \src "libresoc.v:197333.3-197334.37" wire $0\sv_changed[0:0] - attribute \src "libresoc.v:199279.3-199294.6" + attribute \src "libresoc.v:198721.3-198736.6" wire width 64 $0\svstate[63:0] - attribute \src "libresoc.v:199270.3-199278.6" - wire $0\svstate_ok_delay$next[0:0]$13446 - attribute \src "libresoc.v:197845.3-197846.49" + attribute \src "libresoc.v:198712.3-198720.6" + wire $0\svstate_ok_delay$next[0:0]$13429 + attribute \src "libresoc.v:197367.3-197368.49" wire $0\svstate_ok_delay[0:0] - attribute \src "libresoc.v:200224.3-200296.6" + attribute \src "libresoc.v:199726.3-199806.6" wire $0\update_svstate[0:0] - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $10\issue_fsm_state$next[2:0]$13544 - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $11\issue_fsm_state$next[2:0]$13545 - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $12\issue_fsm_state$next[2:0]$13546 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $1\core_asmcode$next[7:0]$13633 - attribute \src "libresoc.v:195522.13-195522.33" + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $10\issue_fsm_state$next[2:0]$13527 + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $11\issue_fsm_state$next[2:0]$13528 + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $12\issue_fsm_state$next[2:0]$13529 + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $13\issue_fsm_state$next[2:0]$13530 + attribute \src "libresoc.v:200001.3-200122.6" + wire width 8 $1\core_asmcode$next[7:0]$13620 + attribute \src "libresoc.v:195247.13-195247.33" wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:198494.3-198538.6" - wire $1\core_bigendian_i$10$next[0:0]$13370 - attribute \src "libresoc.v:199257.3-199269.6" + attribute \src "libresoc.v:198018.3-198053.6" + wire $1\core_bigendian_i$10$next[0:0]$13358 + attribute \src "libresoc.v:198699.3-198711.6" wire width 3 $1\core_cia__ren[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 64 $1\core_core_core_cia$next[63:0]$13634 - attribute \src "libresoc.v:195536.14-195536.55" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 64 $1\core_core_core_cia$next[63:0]$13621 + attribute \src "libresoc.v:195261.14-195261.55" wire width 64 $1\core_core_core_cia[63:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$13635 - attribute \src "libresoc.v:195540.13-195540.41" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$13622 + attribute \src "libresoc.v:195265.13-195265.41" wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$13636 - attribute \src "libresoc.v:195544.7-195544.37" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$13623 + attribute \src "libresoc.v:195269.7-195269.37" wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$13637 - attribute \src "libresoc.v:195548.13-195548.41" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$13624 + attribute \src "libresoc.v:195273.13-195273.41" wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_exc_$signal$3$next[0:0]$13638 - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_exc_$signal$4$next[0:0]$13639 - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_exc_$signal$5$next[0:0]$13640 - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_exc_$signal$6$next[0:0]$13641 - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_exc_$signal$7$next[0:0]$13642 - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_exc_$signal$8$next[0:0]$13643 - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_exc_$signal$9$next[0:0]$13644 - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_exc_$signal$next[0:0]$13645 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 14 $1\core_core_core_fn_unit$next[13:0]$13646 - attribute \src "libresoc.v:195599.14-195599.47" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$13625 + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$13626 + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$13627 + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$13628 + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$13629 + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$13630 + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$13631 + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_exc_$signal$next[0:0]$13632 + attribute \src "libresoc.v:200001.3-200122.6" + wire width 14 $1\core_core_core_fn_unit$next[13:0]$13633 + attribute \src "libresoc.v:195324.14-195324.47" wire width 14 $1\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$13647 - attribute \src "libresoc.v:195607.13-195607.46" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$13634 + attribute \src "libresoc.v:195332.13-195332.46" wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 32 $1\core_core_core_insn$next[31:0]$13648 - attribute \src "libresoc.v:195611.14-195611.41" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 32 $1\core_core_core_insn$next[31:0]$13635 + attribute \src "libresoc.v:195336.14-195336.41" wire width 32 $1\core_core_core_insn[31:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$13649 - attribute \src "libresoc.v:195690.13-195690.45" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$13636 + attribute \src "libresoc.v:195415.13-195415.45" wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_is_32bit$next[0:0]$13650 - attribute \src "libresoc.v:195694.7-195694.37" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_is_32bit$next[0:0]$13637 + attribute \src "libresoc.v:195419.7-195419.37" wire $1\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 64 $1\core_core_core_msr$next[63:0]$13651 - attribute \src "libresoc.v:195698.14-195698.55" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 64 $1\core_core_core_msr$next[63:0]$13638 + attribute \src "libresoc.v:195423.14-195423.55" wire width 64 $1\core_core_core_msr[63:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_oe$next[0:0]$13652 - attribute \src "libresoc.v:195702.7-195702.31" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_oe$next[0:0]$13639 + attribute \src "libresoc.v:195427.7-195427.31" wire $1\core_core_core_oe[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_oe_ok$next[0:0]$13653 - attribute \src "libresoc.v:195706.7-195706.34" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_oe_ok$next[0:0]$13640 + attribute \src "libresoc.v:195431.7-195431.34" wire $1\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_rc$next[0:0]$13654 - attribute \src "libresoc.v:195710.7-195710.31" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_rc$next[0:0]$13641 + attribute \src "libresoc.v:195435.7-195435.31" wire $1\core_core_core_rc[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_core_rc_ok$next[0:0]$13655 - attribute \src "libresoc.v:195714.7-195714.34" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_core_rc_ok$next[0:0]$13642 + attribute \src "libresoc.v:195439.7-195439.34" wire $1\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$13656 - attribute \src "libresoc.v:195718.14-195718.48" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$13643 + attribute \src "libresoc.v:195443.14-195443.48" wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $1\core_core_core_traptype$next[7:0]$13657 - attribute \src "libresoc.v:195722.13-195722.44" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$13644 + attribute \src "libresoc.v:195447.13-195447.44" wire width 8 $1\core_core_core_traptype[7:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $1\core_core_cr_in1$next[6:0]$13658 - attribute \src "libresoc.v:195726.13-195726.37" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $1\core_core_cr_in1$next[6:0]$13645 + attribute \src "libresoc.v:195451.13-195451.37" wire width 7 $1\core_core_cr_in1[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_cr_in1_ok$next[0:0]$13659 - attribute \src "libresoc.v:195730.7-195730.33" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_cr_in1_ok$next[0:0]$13646 + attribute \src "libresoc.v:195455.7-195455.33" wire $1\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $1\core_core_cr_in2$1$next[6:0]$13660 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $1\core_core_cr_in2$next[6:0]$13661 - attribute \src "libresoc.v:195734.13-195734.37" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $1\core_core_cr_in2$1$next[6:0]$13647 + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $1\core_core_cr_in2$next[6:0]$13648 + attribute \src "libresoc.v:195459.13-195459.37" wire width 7 $1\core_core_cr_in2[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$13662 - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_cr_in2_ok$next[0:0]$13663 - attribute \src "libresoc.v:195742.7-195742.33" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$13649 + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_cr_in2_ok$next[0:0]$13650 + attribute \src "libresoc.v:195467.7-195467.33" wire $1\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $1\core_core_cr_out$next[6:0]$13664 - attribute \src "libresoc.v:195750.13-195750.37" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $1\core_core_cr_out$next[6:0]$13651 + attribute \src "libresoc.v:195475.13-195475.37" wire width 7 $1\core_core_cr_out[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_cr_wr_ok$next[0:0]$13665 - attribute \src "libresoc.v:195754.7-195754.32" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_cr_wr_ok$next[0:0]$13652 + attribute \src "libresoc.v:195479.7-195479.32" wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $1\core_core_dststep$next[6:0]$13333 - attribute \src "libresoc.v:195758.13-195758.38" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $1\core_core_dststep$next[6:0]$13332 + attribute \src "libresoc.v:195483.13-195483.38" wire width 7 $1\core_core_dststep[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $1\core_core_ea$next[6:0]$13666 - attribute \src "libresoc.v:195762.13-195762.33" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $1\core_core_ea$next[6:0]$13653 + attribute \src "libresoc.v:195487.13-195487.33" wire width 7 $1\core_core_ea[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $1\core_core_fast1$next[2:0]$13667 - attribute \src "libresoc.v:195766.13-195766.35" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 3 $1\core_core_fast1$next[2:0]$13654 + attribute \src "libresoc.v:195491.13-195491.35" wire width 3 $1\core_core_fast1[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_fast1_ok$next[0:0]$13668 - attribute \src "libresoc.v:195770.7-195770.32" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_fast1_ok$next[0:0]$13655 + attribute \src "libresoc.v:195495.7-195495.32" wire $1\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $1\core_core_fast2$next[2:0]$13669 - attribute \src "libresoc.v:195774.13-195774.35" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 3 $1\core_core_fast2$next[2:0]$13656 + attribute \src "libresoc.v:195499.13-195499.35" wire width 3 $1\core_core_fast2[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_fast2_ok$next[0:0]$13670 - attribute \src "libresoc.v:195778.7-195778.32" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_fast2_ok$next[0:0]$13657 + attribute \src "libresoc.v:195503.7-195503.32" wire $1\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $1\core_core_fasto1$next[2:0]$13671 - attribute \src "libresoc.v:195782.13-195782.36" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 3 $1\core_core_fasto1$next[2:0]$13658 + attribute \src "libresoc.v:195507.13-195507.36" wire width 3 $1\core_core_fasto1[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $1\core_core_fasto2$next[2:0]$13672 - attribute \src "libresoc.v:195786.13-195786.36" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 3 $1\core_core_fasto2$next[2:0]$13659 + attribute \src "libresoc.v:195511.13-195511.36" wire width 3 $1\core_core_fasto2[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_lk$next[0:0]$13673 - attribute \src "libresoc.v:195790.7-195790.26" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_lk$next[0:0]$13660 + attribute \src "libresoc.v:195515.7-195515.26" wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $1\core_core_maxvl$next[6:0]$13334 - attribute \src "libresoc.v:195794.13-195794.36" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $1\core_core_maxvl$next[6:0]$13333 + attribute \src "libresoc.v:195519.13-195519.36" wire width 7 $1\core_core_maxvl[6:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $1\core_core_pc$next[63:0]$13335 - attribute \src "libresoc.v:195798.14-195798.49" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 64 $1\core_core_pc$next[63:0]$13334 + attribute \src "libresoc.v:195523.14-195523.49" wire width 64 $1\core_core_pc[63:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $1\core_core_reg1$next[6:0]$13674 - attribute \src "libresoc.v:195802.13-195802.35" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $1\core_core_reg1$next[6:0]$13661 + attribute \src "libresoc.v:195527.13-195527.35" wire width 7 $1\core_core_reg1[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_reg1_ok$next[0:0]$13675 - attribute \src "libresoc.v:195806.7-195806.31" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_reg1_ok$next[0:0]$13662 + attribute \src "libresoc.v:195531.7-195531.31" wire $1\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $1\core_core_reg2$next[6:0]$13676 - attribute \src "libresoc.v:195810.13-195810.35" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $1\core_core_reg2$next[6:0]$13663 + attribute \src "libresoc.v:195535.13-195535.35" wire width 7 $1\core_core_reg2[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_reg2_ok$next[0:0]$13677 - attribute \src "libresoc.v:195814.7-195814.31" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_reg2_ok$next[0:0]$13664 + attribute \src "libresoc.v:195539.7-195539.31" wire $1\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $1\core_core_reg3$next[6:0]$13678 - attribute \src "libresoc.v:195818.13-195818.35" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $1\core_core_reg3$next[6:0]$13665 + attribute \src "libresoc.v:195543.13-195543.35" wire width 7 $1\core_core_reg3[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_reg3_ok$next[0:0]$13679 - attribute \src "libresoc.v:195822.7-195822.31" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_reg3_ok$next[0:0]$13666 + attribute \src "libresoc.v:195547.7-195547.31" wire $1\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $1\core_core_rego$next[6:0]$13680 - attribute \src "libresoc.v:195826.13-195826.35" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 7 $1\core_core_rego$next[6:0]$13667 + attribute \src "libresoc.v:195551.13-195551.35" wire width 7 $1\core_core_rego[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 10 $1\core_core_spr1$next[9:0]$13681 - attribute \src "libresoc.v:195944.13-195944.37" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 10 $1\core_core_spr1$next[9:0]$13668 + attribute \src "libresoc.v:195567.13-195567.37" wire width 10 $1\core_core_spr1[9:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_core_spr1_ok$next[0:0]$13682 - attribute \src "libresoc.v:195948.7-195948.31" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_core_spr1_ok$next[0:0]$13669 + attribute \src "libresoc.v:195571.7-195571.31" wire $1\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 10 $1\core_core_spro$next[9:0]$13683 - attribute \src "libresoc.v:196066.13-196066.37" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 10 $1\core_core_spro$next[9:0]$13670 + attribute \src "libresoc.v:195587.13-195587.37" wire width 10 $1\core_core_spro[9:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $1\core_core_srcstep$next[6:0]$13336 - attribute \src "libresoc.v:196070.13-196070.38" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $1\core_core_srcstep$next[6:0]$13335 + attribute \src "libresoc.v:195591.13-195591.38" wire width 7 $1\core_core_srcstep[6:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 2 $1\core_core_subvl$next[1:0]$13337 - attribute \src "libresoc.v:196074.13-196074.35" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 2 $1\core_core_subvl$next[1:0]$13336 + attribute \src "libresoc.v:195595.13-195595.35" wire width 2 $1\core_core_subvl[1:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 2 $1\core_core_svstep$next[1:0]$13338 - attribute \src "libresoc.v:196078.13-196078.36" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 2 $1\core_core_svstep$next[1:0]$13337 + attribute \src "libresoc.v:195599.13-195599.36" wire width 2 $1\core_core_svstep[1:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $1\core_core_vl$next[6:0]$13339 - attribute \src "libresoc.v:196084.13-196084.33" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $1\core_core_vl$next[6:0]$13338 + attribute \src "libresoc.v:195605.13-195605.33" wire width 7 $1\core_core_vl[6:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $1\core_core_xer_in$next[2:0]$13684 - attribute \src "libresoc.v:196088.13-196088.36" + attribute \src "libresoc.v:200001.3-200122.6" + wire width 3 $1\core_core_xer_in$next[2:0]$13671 + attribute \src "libresoc.v:195609.13-195609.36" wire width 3 $1\core_core_xer_in[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_cr_out_ok$next[0:0]$13685 - attribute \src "libresoc.v:196096.7-196096.28" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_cr_out_ok$next[0:0]$13672 + attribute \src "libresoc.v:195617.7-195617.28" wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:198786.3-198795.6" - wire width 64 $1\core_data_i$12[63:0]$13389 - attribute \src "libresoc.v:199388.3-199467.6" + attribute \src "libresoc.v:198228.3-198237.6" + wire width 64 $1\core_data_i$12[63:0]$13372 + attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $1\core_data_i[63:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $1\core_dec$next[63:0]$13340 - attribute \src "libresoc.v:196112.14-196112.45" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 64 $1\core_dec$next[63:0]$13339 + attribute \src "libresoc.v:195633.14-195633.45" wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:198903.3-198912.6" + attribute \src "libresoc.v:198345.3-198354.6" wire width 5 $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:198913.3-198922.6" + attribute \src "libresoc.v:198355.3-198364.6" wire $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_ea_ok$next[0:0]$13686 - attribute \src "libresoc.v:196122.7-196122.24" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_ea_ok$next[0:0]$13673 + attribute \src "libresoc.v:195643.7-195643.24" wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire $1\core_eint$next[0:0]$13341 - attribute \src "libresoc.v:196126.7-196126.23" + attribute \src "libresoc.v:197926.3-197981.6" + wire $1\core_eint$next[0:0]$13340 + attribute \src "libresoc.v:195647.7-195647.23" wire $1\core_eint[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_fasto1_ok$next[0:0]$13687 - attribute \src "libresoc.v:196130.7-196130.28" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_fasto1_ok$next[0:0]$13674 + attribute \src "libresoc.v:195651.7-195651.28" wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_fasto2_ok$next[0:0]$13688 - attribute \src "libresoc.v:196134.7-196134.28" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_fasto2_ok$next[0:0]$13675 + attribute \src "libresoc.v:195655.7-195655.28" wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:198952.3-198961.6" + attribute \src "libresoc.v:198394.3-198403.6" wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:198991.3-199000.6" + attribute \src "libresoc.v:198433.3-198442.6" wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:199111.3-199133.6" - wire width 3 $1\core_issue__addr$13[2:0]$13429 - attribute \src "libresoc.v:199030.3-199048.6" + attribute \src "libresoc.v:198553.3-198575.6" + wire width 3 $1\core_issue__addr$13[2:0]$13412 + attribute \src "libresoc.v:198472.3-198490.6" wire width 3 $1\core_issue__addr[2:0] - attribute \src "libresoc.v:199157.3-199179.6" + attribute \src "libresoc.v:198599.3-198621.6" wire width 64 $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:199049.3-199067.6" + attribute \src "libresoc.v:198491.3-198509.6" wire $1\core_issue__ren[0:0] - attribute \src "libresoc.v:199134.3-199156.6" + attribute \src "libresoc.v:198576.3-198598.6" wire $1\core_issue__wen[0:0] - attribute \src "libresoc.v:198832.3-198847.6" + attribute \src "libresoc.v:198274.3-198289.6" wire $1\core_issue_i[0:0] - attribute \src "libresoc.v:198807.3-198831.6" + attribute \src "libresoc.v:198249.3-198273.6" wire $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $1\core_msr$next[63:0]$13342 - attribute \src "libresoc.v:196162.14-196162.45" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 64 $1\core_msr$next[63:0]$13341 + attribute \src "libresoc.v:195683.14-195683.45" wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:199468.3-199483.6" + attribute \src "libresoc.v:198926.3-198941.6" wire width 3 $1\core_msr__ren[2:0] - attribute \src "libresoc.v:198469.3-198493.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$13365 - attribute \src "libresoc.v:196170.14-196170.37" + attribute \src "libresoc.v:197982.3-198017.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13354 + attribute \src "libresoc.v:195691.14-195691.37" wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_rego_ok$next[0:0]$13689 - attribute \src "libresoc.v:196174.7-196174.26" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_rego_ok$next[0:0]$13676 + attribute \src "libresoc.v:195695.7-195695.26" wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_spro_ok$next[0:0]$13690 - attribute \src "libresoc.v:196178.7-196178.26" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_spro_ok$next[0:0]$13677 + attribute \src "libresoc.v:195699.7-195699.26" wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:200047.3-200093.6" + attribute \src "libresoc.v:199525.3-199579.6" wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:199295.3-199307.6" + attribute \src "libresoc.v:198737.3-198749.6" wire width 3 $1\core_sv__ren[2:0] - attribute \src "libresoc.v:198539.3-198583.6" - wire $1\core_sv_a_nz$next[0:0]$13375 - attribute \src "libresoc.v:196190.7-196190.26" + attribute \src "libresoc.v:198054.3-198089.6" + wire $1\core_sv_a_nz$next[0:0]$13362 + attribute \src "libresoc.v:195711.7-195711.26" wire $1\core_sv_a_nz[0:0] - attribute \src "libresoc.v:198776.3-198785.6" - wire width 3 $1\core_wen$11[2:0]$13386 - attribute \src "libresoc.v:199308.3-199387.6" + attribute \src "libresoc.v:198218.3-198227.6" + wire width 3 $1\core_wen$11[2:0]$13369 + attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $1\core_wen[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $1\core_xer_out$next[0:0]$13691 - attribute \src "libresoc.v:196200.7-196200.26" + attribute \src "libresoc.v:200001.3-200122.6" + wire $1\core_xer_out$next[0:0]$13678 + attribute \src "libresoc.v:195721.7-195721.26" wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:196206.7-196206.30" + attribute \src "libresoc.v:195727.7-195727.30" wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $1\cur_cur_dststep$next[6:0]$13475 - attribute \src "libresoc.v:196212.13-196212.36" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $1\cur_cur_dststep$next[6:0]$13458 + attribute \src "libresoc.v:195733.13-195733.36" wire width 7 $1\cur_cur_dststep[6:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $1\cur_cur_maxvl$next[6:0]$13476 - attribute \src "libresoc.v:196216.13-196216.34" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $1\cur_cur_maxvl$next[6:0]$13459 + attribute \src "libresoc.v:195737.13-195737.34" wire width 7 $1\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $1\cur_cur_srcstep$next[6:0]$13477 - attribute \src "libresoc.v:196220.13-196220.36" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $1\cur_cur_srcstep$next[6:0]$13460 + attribute \src "libresoc.v:195741.13-195741.36" wire width 7 $1\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 2 $1\cur_cur_subvl$next[1:0]$13478 - attribute \src "libresoc.v:196224.13-196224.33" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 2 $1\cur_cur_subvl$next[1:0]$13461 + attribute \src "libresoc.v:195745.13-195745.33" wire width 2 $1\cur_cur_subvl[1:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 2 $1\cur_cur_svstep$next[1:0]$13479 - attribute \src "libresoc.v:196228.13-196228.34" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 2 $1\cur_cur_svstep$next[1:0]$13462 + attribute \src "libresoc.v:195749.13-195749.34" wire width 2 $1\cur_cur_svstep[1:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $1\cur_cur_vl$next[6:0]$13480 - attribute \src "libresoc.v:196232.13-196232.31" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $1\cur_cur_vl$next[6:0]$13463 + attribute \src "libresoc.v:195753.13-195753.31" wire width 7 $1\cur_cur_vl[6:0] - attribute \src "libresoc.v:198962.3-198970.6" - wire $1\d_cr_delay$next[0:0]$13411 - attribute \src "libresoc.v:196236.7-196236.24" + attribute \src "libresoc.v:198404.3-198412.6" + wire $1\d_cr_delay$next[0:0]$13394 + attribute \src "libresoc.v:195757.7-195757.24" wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:198923.3-198931.6" - wire $1\d_reg_delay$next[0:0]$13405 - attribute \src "libresoc.v:196240.7-196240.25" + attribute \src "libresoc.v:198365.3-198373.6" + wire $1\d_reg_delay$next[0:0]$13388 + attribute \src "libresoc.v:195761.7-195761.25" wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:199001.3-199009.6" - wire $1\d_xer_delay$next[0:0]$13417 - attribute \src "libresoc.v:196244.7-196244.25" + attribute \src "libresoc.v:198443.3-198451.6" + wire $1\d_xer_delay$next[0:0]$13400 + attribute \src "libresoc.v:195765.7-195765.25" wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:200094.3-200140.6" + attribute \src "libresoc.v:199580.3-199634.6" wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:198981.3-198990.6" + attribute \src "libresoc.v:198423.3-198432.6" wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:198971.3-198980.6" + attribute \src "libresoc.v:198413.3-198422.6" wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:198942.3-198951.6" + attribute \src "libresoc.v:198384.3-198393.6" wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:198932.3-198941.6" + attribute \src "libresoc.v:198374.3-198383.6" wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:199020.3-199029.6" + attribute \src "libresoc.v:198462.3-198471.6" wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:199010.3-199019.6" + attribute \src "libresoc.v:198452.3-198461.6" wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:198386.3-198394.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13318 - attribute \src "libresoc.v:196292.13-196292.34" + attribute \src "libresoc.v:197908.3-197916.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13317 + attribute \src "libresoc.v:195813.13-195813.34" wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:199484.3-199492.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$13455 - attribute \src "libresoc.v:196296.14-196296.48" + attribute \src "libresoc.v:198942.3-198950.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13438 + attribute \src "libresoc.v:195817.14-195817.48" wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:198395.3-198403.6" - wire $1\dbg_dmi_req_i$next[0:0]$13321 - attribute \src "libresoc.v:196302.7-196302.27" + attribute \src "libresoc.v:197917.3-197925.6" + wire $1\dbg_dmi_req_i$next[0:0]$13320 + attribute \src "libresoc.v:195823.7-195823.27" wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:199223.3-199231.6" - wire $1\dbg_dmi_we_i$next[0:0]$13439 - attribute \src "libresoc.v:196306.7-196306.26" + attribute \src "libresoc.v:198665.3-198673.6" + wire $1\dbg_dmi_we_i$next[0:0]$13422 + attribute \src "libresoc.v:195827.7-195827.26" wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:199180.3-199199.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$13434 - attribute \src "libresoc.v:196360.14-196360.49" + attribute \src "libresoc.v:198622.3-198641.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13417 + attribute \src "libresoc.v:195881.14-195881.49" wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:200526.3-200534.6" - wire $1\dec2_cur_eint$next[0:0]$13780 - attribute \src "libresoc.v:196364.7-196364.27" + attribute \src "libresoc.v:200123.3-200131.6" + wire $1\dec2_cur_eint$next[0:0]$13708 + attribute \src "libresoc.v:195885.7-195885.27" wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:199750.3-199774.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$13518 - attribute \src "libresoc.v:196368.14-196368.49" + attribute \src "libresoc.v:199208.3-199232.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13501 + attribute \src "libresoc.v:195889.14-195889.49" wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:199597.3-199617.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$13465 - attribute \src "libresoc.v:196372.14-196372.48" + attribute \src "libresoc.v:199055.3-199075.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13448 + attribute \src "libresoc.v:195893.14-195893.48" wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:199798.3-199832.6" - wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13527 - attribute \src "libresoc.v:196524.14-196524.40" + attribute \src "libresoc.v:199256.3-199290.6" + wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13510 + attribute \src "libresoc.v:196045.14-196045.40" wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:200535.3-200544.6" - wire width 2 $1\delay$next[1:0]$13783 - attribute \src "libresoc.v:196794.13-196794.25" + attribute \src "libresoc.v:200132.3-200141.6" + wire width 2 $1\delay$next[1:0]$13711 + attribute \src "libresoc.v:196315.13-196315.25" wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:198848.3-198882.6" - wire $1\exec_fsm_state$next[0:0]$13395 - attribute \src "libresoc.v:196810.7-196810.28" + attribute \src "libresoc.v:198290.3-198324.6" + wire $1\exec_fsm_state$next[0:0]$13378 + attribute \src "libresoc.v:196331.7-196331.28" wire $1\exec_fsm_state[0:0] - attribute \src "libresoc.v:198796.3-198806.6" + attribute \src "libresoc.v:198238.3-198248.6" wire $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:198672.3-198698.6" + attribute \src "libresoc.v:198090.3-198124.6" wire $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:198699.3-198734.6" + attribute \src "libresoc.v:198125.3-198168.6" wire $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198883.3-198902.6" + attribute \src "libresoc.v:198325.3-198344.6" wire $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:199696.3-199749.6" - wire width 2 $1\fetch_fsm_state$next[1:0]$13510 - attribute \src "libresoc.v:196822.13-196822.35" + attribute \src "libresoc.v:199154.3-199207.6" + wire width 2 $1\fetch_fsm_state$next[1:0]$13493 + attribute \src "libresoc.v:196343.13-196343.35" wire width 2 $1\fetch_fsm_state[1:0] - attribute \src "libresoc.v:200380.3-200394.6" + attribute \src "libresoc.v:199898.3-199912.6" wire $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:199833.3-199855.6" + attribute \src "libresoc.v:199291.3-199313.6" wire $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:199493.3-199503.6" + attribute \src "libresoc.v:198951.3-198961.6" wire $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:199932.3-199947.6" + attribute \src "libresoc.v:199401.3-199416.6" wire $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:199068.3-199095.6" - wire width 2 $1\fsm_state$next[1:0]$13424 - attribute \src "libresoc.v:196834.13-196834.29" + attribute \src "libresoc.v:198510.3-198537.6" + wire width 2 $1\fsm_state$next[1:0]$13407 + attribute \src "libresoc.v:196355.13-196355.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:199504.3-199519.6" + attribute \src "libresoc.v:198962.3-198977.6" wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:199529.3-199562.6" + attribute \src "libresoc.v:198987.3-199020.6" wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199563.3-199596.6" + attribute \src "libresoc.v:199021.3-199054.6" wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198584.3-198629.6" + attribute \src "libresoc.v:199913.3-199958.6" wire $1\insn_done[0:0] - attribute \src "libresoc.v:198735.3-198775.6" + attribute \src "libresoc.v:198169.3-198217.6" wire $1\is_last[0:0] - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $1\issue_fsm_state$next[2:0]$13535 - attribute \src "libresoc.v:197094.13-197094.35" + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $1\issue_fsm_state$next[2:0]$13518 + attribute \src "libresoc.v:196615.13-196615.35" wire width 3 $1\issue_fsm_state[2:0] - attribute \src "libresoc.v:199520.3-199528.6" - wire $1\jtag_dmi0__ack_o$next[0:0]$13460 - attribute \src "libresoc.v:197098.7-197098.30" + attribute \src "libresoc.v:198978.3-198986.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$13443 + attribute \src "libresoc.v:196619.7-196619.30" wire $1\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:199687.3-199695.6" - wire width 64 $1\jtag_dmi0__dout$next[63:0]$13507 - attribute \src "libresoc.v:197106.14-197106.52" + attribute \src "libresoc.v:199145.3-199153.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13490 + attribute \src "libresoc.v:196627.14-196627.52" wire width 64 $1\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:199657.3-199686.6" - wire $1\msr_read$next[0:0]$13501 - attribute \src "libresoc.v:197146.7-197146.22" + attribute \src "libresoc.v:199115.3-199144.6" + wire $1\msr_read$next[0:0]$13484 + attribute \src "libresoc.v:196667.7-196667.22" wire $1\msr_read[0:0] - attribute \src "libresoc.v:199096.3-199110.6" + attribute \src "libresoc.v:198538.3-198552.6" wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $1\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $1\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $1\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $1\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $1\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:199200.3-199222.6" + attribute \src "libresoc.v:198642.3-198664.6" wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:199775.3-199797.6" - wire width 64 $1\nia$next[63:0]$13523 - attribute \src "libresoc.v:197186.14-197186.40" + attribute \src "libresoc.v:199233.3-199255.6" + wire width 64 $1\nia$next[63:0]$13506 + attribute \src "libresoc.v:196707.14-196707.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:199241.3-199256.6" + attribute \src "libresoc.v:198683.3-198698.6" wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:200141.3-200223.6" - wire $1\pc_changed$next[0:0]$13551 - attribute \src "libresoc.v:197192.7-197192.24" + attribute \src "libresoc.v:199635.3-199725.6" + wire $1\pc_changed$next[0:0]$13535 + attribute \src "libresoc.v:196713.7-196713.24" wire $1\pc_changed[0:0] - attribute \src "libresoc.v:199232.3-199240.6" - wire $1\pc_ok_delay$next[0:0]$13442 - attribute \src "libresoc.v:197202.7-197202.25" + attribute \src "libresoc.v:198674.3-198682.6" + wire $1\pc_ok_delay$next[0:0]$13425 + attribute \src "libresoc.v:196723.7-196723.25" wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:198630.3-198648.6" + attribute \src "libresoc.v:199959.3-199977.6" wire $1\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:198649.3-198671.6" + attribute \src "libresoc.v:199978.3-200000.6" wire $1\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:200297.3-200379.6" - wire $1\sv_changed$next[0:0]$13563 - attribute \src "libresoc.v:197502.7-197502.24" + attribute \src "libresoc.v:199807.3-199897.6" + wire $1\sv_changed$next[0:0]$13547 + attribute \src "libresoc.v:197023.7-197023.24" wire $1\sv_changed[0:0] - attribute \src "libresoc.v:199279.3-199294.6" + attribute \src "libresoc.v:198721.3-198736.6" wire width 64 $1\svstate[63:0] - attribute \src "libresoc.v:199270.3-199278.6" - wire $1\svstate_ok_delay$next[0:0]$13447 - attribute \src "libresoc.v:197512.7-197512.30" + attribute \src "libresoc.v:198712.3-198720.6" + wire $1\svstate_ok_delay$next[0:0]$13430 + attribute \src "libresoc.v:197033.7-197033.30" wire $1\svstate_ok_delay[0:0] - attribute \src "libresoc.v:200224.3-200296.6" + attribute \src "libresoc.v:199726.3-199806.6" wire $1\update_svstate[0:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $2\core_asmcode$next[7:0]$13692 - attribute \src "libresoc.v:198494.3-198538.6" - wire $2\core_bigendian_i$10$next[0:0]$13371 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 64 $2\core_core_core_cia$next[63:0]$13693 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$13694 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$13695 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$13696 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_exc_$signal$3$next[0:0]$13697 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_exc_$signal$4$next[0:0]$13698 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_exc_$signal$5$next[0:0]$13699 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_exc_$signal$6$next[0:0]$13700 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_exc_$signal$7$next[0:0]$13701 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_exc_$signal$8$next[0:0]$13702 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_exc_$signal$9$next[0:0]$13703 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_exc_$signal$next[0:0]$13704 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 14 $2\core_core_core_fn_unit$next[13:0]$13705 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$13706 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 32 $2\core_core_core_insn$next[31:0]$13707 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$13708 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_is_32bit$next[0:0]$13709 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 64 $2\core_core_core_msr$next[63:0]$13710 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_oe$next[0:0]$13711 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_oe_ok$next[0:0]$13712 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_rc$next[0:0]$13713 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_core_rc_ok$next[0:0]$13714 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$13715 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 8 $2\core_core_core_traptype$next[7:0]$13716 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $2\core_core_cr_in1$next[6:0]$13717 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_cr_in1_ok$next[0:0]$13718 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $2\core_core_cr_in2$1$next[6:0]$13719 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $2\core_core_cr_in2$next[6:0]$13720 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$13721 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_cr_in2_ok$next[0:0]$13722 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $2\core_core_cr_out$next[6:0]$13723 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_cr_wr_ok$next[0:0]$13724 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $2\core_core_dststep$next[6:0]$13343 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $2\core_core_ea$next[6:0]$13725 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $2\core_core_fast1$next[2:0]$13726 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_fast1_ok$next[0:0]$13727 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $2\core_core_fast2$next[2:0]$13728 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_fast2_ok$next[0:0]$13729 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $2\core_core_fasto1$next[2:0]$13730 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $2\core_core_fasto2$next[2:0]$13731 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_lk$next[0:0]$13732 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $2\core_core_maxvl$next[6:0]$13344 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $2\core_core_pc$next[63:0]$13345 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $2\core_core_reg1$next[6:0]$13733 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_reg1_ok$next[0:0]$13734 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $2\core_core_reg2$next[6:0]$13735 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_reg2_ok$next[0:0]$13736 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $2\core_core_reg3$next[6:0]$13737 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_reg3_ok$next[0:0]$13738 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 7 $2\core_core_rego$next[6:0]$13739 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 10 $2\core_core_spr1$next[9:0]$13740 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_core_spr1_ok$next[0:0]$13741 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 10 $2\core_core_spro$next[9:0]$13742 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $2\core_core_srcstep$next[6:0]$13346 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 2 $2\core_core_subvl$next[1:0]$13347 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 2 $2\core_core_svstep$next[1:0]$13348 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $2\core_core_vl$next[6:0]$13349 - attribute \src "libresoc.v:200395.3-200525.6" - wire width 3 $2\core_core_xer_in$next[2:0]$13743 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_cr_out_ok$next[0:0]$13744 - attribute \src "libresoc.v:199388.3-199467.6" + attribute \src "libresoc.v:198018.3-198053.6" + wire $2\core_bigendian_i$10$next[0:0]$13359 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$13679 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$13680 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$13681 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$13682 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$13683 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$13684 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$13685 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$13686 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_core_exc_$signal$next[0:0]$13687 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_core_oe_ok$next[0:0]$13688 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_core_rc_ok$next[0:0]$13689 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_cr_in1_ok$next[0:0]$13690 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$13691 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_cr_in2_ok$next[0:0]$13692 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_cr_wr_ok$next[0:0]$13693 + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $2\core_core_dststep$next[6:0]$13342 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_fast1_ok$next[0:0]$13694 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_fast2_ok$next[0:0]$13695 + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $2\core_core_maxvl$next[6:0]$13343 + attribute \src "libresoc.v:197926.3-197981.6" + wire width 64 $2\core_core_pc$next[63:0]$13344 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_reg1_ok$next[0:0]$13696 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_reg2_ok$next[0:0]$13697 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_reg3_ok$next[0:0]$13698 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_core_spr1_ok$next[0:0]$13699 + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $2\core_core_srcstep$next[6:0]$13345 + attribute \src "libresoc.v:197926.3-197981.6" + wire width 2 $2\core_core_subvl$next[1:0]$13346 + attribute \src "libresoc.v:197926.3-197981.6" + wire width 2 $2\core_core_svstep$next[1:0]$13347 + attribute \src "libresoc.v:197926.3-197981.6" + wire width 7 $2\core_core_vl$next[6:0]$13348 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_cr_out_ok$next[0:0]$13700 + attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $2\core_data_i[63:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $2\core_dec$next[63:0]$13350 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_ea_ok$next[0:0]$13745 - attribute \src "libresoc.v:198404.3-198468.6" - wire $2\core_eint$next[0:0]$13351 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_fasto1_ok$next[0:0]$13746 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_fasto2_ok$next[0:0]$13747 - attribute \src "libresoc.v:198832.3-198847.6" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 64 $2\core_dec$next[63:0]$13349 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_ea_ok$next[0:0]$13701 + attribute \src "libresoc.v:197926.3-197981.6" + wire $2\core_eint$next[0:0]$13350 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_fasto1_ok$next[0:0]$13702 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_fasto2_ok$next[0:0]$13703 + attribute \src "libresoc.v:198274.3-198289.6" wire $2\core_issue_i[0:0] - attribute \src "libresoc.v:198807.3-198831.6" + attribute \src "libresoc.v:198249.3-198273.6" wire $2\core_ivalid_i[0:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $2\core_msr$next[63:0]$13352 - attribute \src "libresoc.v:199468.3-199483.6" + attribute \src "libresoc.v:197926.3-197981.6" + wire width 64 $2\core_msr$next[63:0]$13351 + attribute \src "libresoc.v:198926.3-198941.6" wire width 3 $2\core_msr__ren[2:0] - attribute \src "libresoc.v:198469.3-198493.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$13366 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_rego_ok$next[0:0]$13748 - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_spro_ok$next[0:0]$13749 - attribute \src "libresoc.v:200047.3-200093.6" + attribute \src "libresoc.v:197982.3-198017.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13355 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_rego_ok$next[0:0]$13704 + attribute \src "libresoc.v:200001.3-200122.6" + wire $2\core_spro_ok$next[0:0]$13705 + attribute \src "libresoc.v:199525.3-199579.6" wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:198539.3-198583.6" - wire $2\core_sv_a_nz$next[0:0]$13376 - attribute \src "libresoc.v:199308.3-199387.6" + attribute \src "libresoc.v:198054.3-198089.6" + wire $2\core_sv_a_nz$next[0:0]$13363 + attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $2\core_wen[2:0] - attribute \src "libresoc.v:200395.3-200525.6" - wire $2\core_xer_out$next[0:0]$13750 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $2\cur_cur_dststep$next[6:0]$13481 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $2\cur_cur_maxvl$next[6:0]$13482 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $2\cur_cur_srcstep$next[6:0]$13483 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 2 $2\cur_cur_subvl$next[1:0]$13484 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 2 $2\cur_cur_svstep$next[1:0]$13485 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $2\cur_cur_vl$next[6:0]$13486 - attribute \src "libresoc.v:200094.3-200140.6" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $2\cur_cur_dststep$next[6:0]$13464 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $2\cur_cur_maxvl$next[6:0]$13465 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $2\cur_cur_srcstep$next[6:0]$13466 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 2 $2\cur_cur_subvl$next[1:0]$13467 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 2 $2\cur_cur_svstep$next[1:0]$13468 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $2\cur_cur_vl$next[6:0]$13469 + attribute \src "libresoc.v:199580.3-199634.6" wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:199180.3-199199.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$13435 - attribute \src "libresoc.v:199750.3-199774.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$13519 - attribute \src "libresoc.v:199597.3-199617.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$13466 - attribute \src "libresoc.v:199798.3-199832.6" - wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13528 - attribute \src "libresoc.v:198848.3-198882.6" - wire $2\exec_fsm_state$next[0:0]$13396 - attribute \src "libresoc.v:198699.3-198734.6" + attribute \src "libresoc.v:198622.3-198641.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13418 + attribute \src "libresoc.v:199208.3-199232.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13502 + attribute \src "libresoc.v:199055.3-199075.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13449 + attribute \src "libresoc.v:199256.3-199290.6" + wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13511 + attribute \src "libresoc.v:198290.3-198324.6" + wire $2\exec_fsm_state$next[0:0]$13379 + attribute \src "libresoc.v:198125.3-198168.6" wire $2\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198883.3-198902.6" + attribute \src "libresoc.v:198325.3-198344.6" wire $2\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:199696.3-199749.6" - wire width 2 $2\fetch_fsm_state$next[1:0]$13511 - attribute \src "libresoc.v:199932.3-199947.6" + attribute \src "libresoc.v:199154.3-199207.6" + wire width 2 $2\fetch_fsm_state$next[1:0]$13494 + attribute \src "libresoc.v:199401.3-199416.6" wire $2\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:199068.3-199095.6" - wire width 2 $2\fsm_state$next[1:0]$13425 - attribute \src "libresoc.v:199504.3-199519.6" + attribute \src "libresoc.v:198510.3-198537.6" + wire width 2 $2\fsm_state$next[1:0]$13408 + attribute \src "libresoc.v:198962.3-198977.6" wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:199529.3-199562.6" + attribute \src "libresoc.v:198987.3-199020.6" wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199563.3-199596.6" + attribute \src "libresoc.v:199021.3-199054.6" wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198584.3-198629.6" + attribute \src "libresoc.v:199913.3-199958.6" wire $2\insn_done[0:0] - attribute \src "libresoc.v:198735.3-198775.6" + attribute \src "libresoc.v:198169.3-198217.6" wire $2\is_last[0:0] - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $2\issue_fsm_state$next[2:0]$13536 - attribute \src "libresoc.v:199657.3-199686.6" - wire $2\msr_read$next[0:0]$13502 - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $2\issue_fsm_state$next[2:0]$13519 + attribute \src "libresoc.v:199115.3-199144.6" + wire $2\msr_read$next[0:0]$13485 + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $2\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $2\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $2\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $2\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $2\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $2\new_svstate_vl[6:0] - attribute \src "libresoc.v:199775.3-199797.6" - wire width 64 $2\nia$next[63:0]$13524 - attribute \src "libresoc.v:199241.3-199256.6" + attribute \src "libresoc.v:199233.3-199255.6" + wire width 64 $2\nia$next[63:0]$13507 + attribute \src "libresoc.v:198683.3-198698.6" wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:200141.3-200223.6" - wire $2\pc_changed$next[0:0]$13552 - attribute \src "libresoc.v:200297.3-200379.6" - wire $2\sv_changed$next[0:0]$13564 - attribute \src "libresoc.v:199279.3-199294.6" + attribute \src "libresoc.v:199635.3-199725.6" + wire $2\pc_changed$next[0:0]$13536 + attribute \src "libresoc.v:199807.3-199897.6" + wire $2\sv_changed$next[0:0]$13548 + attribute \src "libresoc.v:198721.3-198736.6" wire width 64 $2\svstate[63:0] - attribute \src "libresoc.v:200224.3-200296.6" + attribute \src "libresoc.v:199726.3-199806.6" wire $2\update_svstate[0:0] - attribute \src "libresoc.v:198494.3-198538.6" - wire $3\core_bigendian_i$10$next[0:0]$13372 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$13751 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_core_exc_$signal$3$next[0:0]$13752 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_core_exc_$signal$4$next[0:0]$13753 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_core_exc_$signal$5$next[0:0]$13754 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_core_exc_$signal$6$next[0:0]$13755 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_core_exc_$signal$7$next[0:0]$13756 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_core_exc_$signal$8$next[0:0]$13757 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_core_exc_$signal$9$next[0:0]$13758 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_core_exc_$signal$next[0:0]$13759 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_core_oe_ok$next[0:0]$13760 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_core_rc_ok$next[0:0]$13761 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_cr_in1_ok$next[0:0]$13762 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$13763 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_cr_in2_ok$next[0:0]$13764 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_cr_wr_ok$next[0:0]$13765 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $3\core_core_dststep$next[6:0]$13353 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_fast1_ok$next[0:0]$13766 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_fast2_ok$next[0:0]$13767 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $3\core_core_maxvl$next[6:0]$13354 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $3\core_core_pc$next[63:0]$13355 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_reg1_ok$next[0:0]$13768 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_reg2_ok$next[0:0]$13769 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_reg3_ok$next[0:0]$13770 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_core_spr1_ok$next[0:0]$13771 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $3\core_core_srcstep$next[6:0]$13356 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 2 $3\core_core_subvl$next[1:0]$13357 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 2 $3\core_core_svstep$next[1:0]$13358 - attribute \src "libresoc.v:198404.3-198468.6" - wire width 7 $3\core_core_vl$next[6:0]$13359 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_cr_out_ok$next[0:0]$13772 - attribute \src "libresoc.v:199388.3-199467.6" + attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $3\core_data_i[63:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $3\core_dec$next[63:0]$13360 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_ea_ok$next[0:0]$13773 - attribute \src "libresoc.v:198404.3-198468.6" - wire $3\core_eint$next[0:0]$13361 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_fasto1_ok$next[0:0]$13774 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_fasto2_ok$next[0:0]$13775 - attribute \src "libresoc.v:198807.3-198831.6" + attribute \src "libresoc.v:198249.3-198273.6" wire $3\core_ivalid_i[0:0] - attribute \src "libresoc.v:198404.3-198468.6" - wire width 64 $3\core_msr$next[63:0]$13362 - attribute \src "libresoc.v:198469.3-198493.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$13367 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_rego_ok$next[0:0]$13776 - attribute \src "libresoc.v:200395.3-200525.6" - wire $3\core_spro_ok$next[0:0]$13777 - attribute \src "libresoc.v:200047.3-200093.6" + attribute \src "libresoc.v:199525.3-199579.6" wire $3\core_stopped_i[0:0] - attribute \src "libresoc.v:198539.3-198583.6" - wire $3\core_sv_a_nz$next[0:0]$13377 - attribute \src "libresoc.v:199308.3-199387.6" + attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $3\core_wen[2:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $3\cur_cur_dststep$next[6:0]$13487 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $3\cur_cur_maxvl$next[6:0]$13488 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $3\cur_cur_srcstep$next[6:0]$13489 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 2 $3\cur_cur_subvl$next[1:0]$13490 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 2 $3\cur_cur_svstep$next[1:0]$13491 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $3\cur_cur_vl$next[6:0]$13492 - attribute \src "libresoc.v:200094.3-200140.6" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $3\cur_cur_dststep$next[6:0]$13470 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $3\cur_cur_maxvl$next[6:0]$13471 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $3\cur_cur_srcstep$next[6:0]$13472 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 2 $3\cur_cur_subvl$next[1:0]$13473 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 2 $3\cur_cur_svstep$next[1:0]$13474 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $3\cur_cur_vl$next[6:0]$13475 + attribute \src "libresoc.v:199580.3-199634.6" wire $3\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:199750.3-199774.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$13520 - attribute \src "libresoc.v:199597.3-199617.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$13467 - attribute \src "libresoc.v:199798.3-199832.6" - wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13529 - attribute \src "libresoc.v:198848.3-198882.6" - wire $3\exec_fsm_state$next[0:0]$13397 - attribute \src "libresoc.v:199696.3-199749.6" - wire width 2 $3\fetch_fsm_state$next[1:0]$13512 - attribute \src "libresoc.v:199529.3-199562.6" + attribute \src "libresoc.v:199208.3-199232.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13503 + attribute \src "libresoc.v:199055.3-199075.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13450 + attribute \src "libresoc.v:199256.3-199290.6" + wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13512 + attribute \src "libresoc.v:198290.3-198324.6" + wire $3\exec_fsm_state$next[0:0]$13380 + attribute \src "libresoc.v:199154.3-199207.6" + wire width 2 $3\fetch_fsm_state$next[1:0]$13495 + attribute \src "libresoc.v:198987.3-199020.6" wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199563.3-199596.6" + attribute \src "libresoc.v:199021.3-199054.6" wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198584.3-198629.6" + attribute \src "libresoc.v:199913.3-199958.6" wire $3\insn_done[0:0] - attribute \src "libresoc.v:198735.3-198775.6" + attribute \src "libresoc.v:198169.3-198217.6" wire $3\is_last[0:0] - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $3\issue_fsm_state$next[2:0]$13537 - attribute \src "libresoc.v:199657.3-199686.6" - wire $3\msr_read$next[0:0]$13503 - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $3\issue_fsm_state$next[2:0]$13520 + attribute \src "libresoc.v:199115.3-199144.6" + wire $3\msr_read$next[0:0]$13486 + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $3\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $3\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $3\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $3\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $3\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $3\new_svstate_vl[6:0] - attribute \src "libresoc.v:200141.3-200223.6" - wire $3\pc_changed$next[0:0]$13553 - attribute \src "libresoc.v:200297.3-200379.6" - wire $3\sv_changed$next[0:0]$13565 - attribute \src "libresoc.v:200224.3-200296.6" + attribute \src "libresoc.v:199635.3-199725.6" + wire $3\pc_changed$next[0:0]$13537 + attribute \src "libresoc.v:199807.3-199897.6" + wire $3\sv_changed$next[0:0]$13549 + attribute \src "libresoc.v:199726.3-199806.6" wire $3\update_svstate[0:0] - attribute \src "libresoc.v:199388.3-199467.6" + attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $4\core_data_i[63:0] - attribute \src "libresoc.v:199308.3-199387.6" + attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $4\core_wen[2:0] - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $4\cur_cur_dststep$next[6:0]$13493 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $4\cur_cur_maxvl$next[6:0]$13494 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $4\cur_cur_srcstep$next[6:0]$13495 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 2 $4\cur_cur_subvl$next[1:0]$13496 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 2 $4\cur_cur_svstep$next[1:0]$13497 - attribute \src "libresoc.v:199618.3-199656.6" - wire width 7 $4\cur_cur_vl$next[6:0]$13498 - attribute \src "libresoc.v:198848.3-198882.6" - wire $4\exec_fsm_state$next[0:0]$13398 - attribute \src "libresoc.v:199696.3-199749.6" - wire width 2 $4\fetch_fsm_state$next[1:0]$13513 - attribute \src "libresoc.v:199529.3-199562.6" + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $4\cur_cur_dststep$next[6:0]$13476 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $4\cur_cur_maxvl$next[6:0]$13477 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $4\cur_cur_srcstep$next[6:0]$13478 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 2 $4\cur_cur_subvl$next[1:0]$13479 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 2 $4\cur_cur_svstep$next[1:0]$13480 + attribute \src "libresoc.v:199076.3-199114.6" + wire width 7 $4\cur_cur_vl$next[6:0]$13481 + attribute \src "libresoc.v:198290.3-198324.6" + wire $4\exec_fsm_state$next[0:0]$13381 + attribute \src "libresoc.v:199154.3-199207.6" + wire width 2 $4\fetch_fsm_state$next[1:0]$13496 + attribute \src "libresoc.v:198987.3-199020.6" wire $4\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199563.3-199596.6" + attribute \src "libresoc.v:199021.3-199054.6" wire $4\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198584.3-198629.6" + attribute \src "libresoc.v:199913.3-199958.6" wire $4\insn_done[0:0] - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $4\issue_fsm_state$next[2:0]$13538 - attribute \src "libresoc.v:199657.3-199686.6" - wire $4\msr_read$next[0:0]$13504 - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $4\issue_fsm_state$next[2:0]$13521 + attribute \src "libresoc.v:199115.3-199144.6" + wire $4\msr_read$next[0:0]$13487 + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $4\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $4\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $4\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $4\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $4\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $4\new_svstate_vl[6:0] - attribute \src "libresoc.v:200141.3-200223.6" - wire $4\pc_changed$next[0:0]$13554 - attribute \src "libresoc.v:200297.3-200379.6" - wire $4\sv_changed$next[0:0]$13566 - attribute \src "libresoc.v:200224.3-200296.6" + attribute \src "libresoc.v:199635.3-199725.6" + wire $4\pc_changed$next[0:0]$13538 + attribute \src "libresoc.v:199807.3-199897.6" + wire $4\sv_changed$next[0:0]$13550 + attribute \src "libresoc.v:199726.3-199806.6" wire $4\update_svstate[0:0] - attribute \src "libresoc.v:199388.3-199467.6" + attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $5\core_data_i[63:0] - attribute \src "libresoc.v:199308.3-199387.6" + attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $5\core_wen[2:0] - attribute \src "libresoc.v:198848.3-198882.6" - wire $5\exec_fsm_state$next[0:0]$13399 - attribute \src "libresoc.v:199696.3-199749.6" - wire width 2 $5\fetch_fsm_state$next[1:0]$13514 - attribute \src "libresoc.v:198584.3-198629.6" + attribute \src "libresoc.v:198290.3-198324.6" + wire $5\exec_fsm_state$next[0:0]$13382 + attribute \src "libresoc.v:199154.3-199207.6" + wire width 2 $5\fetch_fsm_state$next[1:0]$13497 + attribute \src "libresoc.v:199913.3-199958.6" wire $5\insn_done[0:0] - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $5\issue_fsm_state$next[2:0]$13539 - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $5\issue_fsm_state$next[2:0]$13522 + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $5\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $5\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $5\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $5\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $5\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $5\new_svstate_vl[6:0] - attribute \src "libresoc.v:200141.3-200223.6" - wire $5\pc_changed$next[0:0]$13555 - attribute \src "libresoc.v:200297.3-200379.6" - wire $5\sv_changed$next[0:0]$13567 - attribute \src "libresoc.v:200224.3-200296.6" + attribute \src "libresoc.v:199635.3-199725.6" + wire $5\pc_changed$next[0:0]$13539 + attribute \src "libresoc.v:199807.3-199897.6" + wire $5\sv_changed$next[0:0]$13551 + attribute \src "libresoc.v:199726.3-199806.6" wire $5\update_svstate[0:0] - attribute \src "libresoc.v:199388.3-199467.6" + attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $6\core_data_i[63:0] - attribute \src "libresoc.v:199308.3-199387.6" + attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $6\core_wen[2:0] - attribute \src "libresoc.v:199696.3-199749.6" - wire width 2 $6\fetch_fsm_state$next[1:0]$13515 - attribute \src "libresoc.v:198584.3-198629.6" + attribute \src "libresoc.v:199154.3-199207.6" + wire width 2 $6\fetch_fsm_state$next[1:0]$13498 + attribute \src "libresoc.v:199913.3-199958.6" wire $6\insn_done[0:0] - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $6\issue_fsm_state$next[2:0]$13540 - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $6\issue_fsm_state$next[2:0]$13523 + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $6\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $6\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:200141.3-200223.6" - wire $6\pc_changed$next[0:0]$13556 - attribute \src "libresoc.v:200297.3-200379.6" - wire $6\sv_changed$next[0:0]$13568 - attribute \src "libresoc.v:200224.3-200296.6" + attribute \src "libresoc.v:199635.3-199725.6" + wire $6\pc_changed$next[0:0]$13540 + attribute \src "libresoc.v:199807.3-199897.6" + wire $6\sv_changed$next[0:0]$13552 + attribute \src "libresoc.v:199726.3-199806.6" wire $6\update_svstate[0:0] - attribute \src "libresoc.v:199388.3-199467.6" + attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $7\core_data_i[63:0] - attribute \src "libresoc.v:199308.3-199387.6" + attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $7\core_wen[2:0] - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $7\issue_fsm_state$next[2:0]$13541 - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $7\issue_fsm_state$next[2:0]$13524 + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $7\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199856.3-199931.6" + attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $7\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:200141.3-200223.6" - wire $7\pc_changed$next[0:0]$13557 - attribute \src "libresoc.v:200297.3-200379.6" - wire $7\sv_changed$next[0:0]$13569 - attribute \src "libresoc.v:200224.3-200296.6" + attribute \src "libresoc.v:199635.3-199725.6" + wire $7\pc_changed$next[0:0]$13541 + attribute \src "libresoc.v:199807.3-199897.6" + wire $7\sv_changed$next[0:0]$13553 + attribute \src "libresoc.v:199726.3-199806.6" wire $7\update_svstate[0:0] - attribute \src "libresoc.v:199388.3-199467.6" + attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $8\core_data_i[63:0] - attribute \src "libresoc.v:199308.3-199387.6" + attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $8\core_wen[2:0] - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $8\issue_fsm_state$next[2:0]$13542 - attribute \src "libresoc.v:200141.3-200223.6" - wire $8\pc_changed$next[0:0]$13558 - attribute \src "libresoc.v:200297.3-200379.6" - wire $8\sv_changed$next[0:0]$13570 - attribute \src "libresoc.v:199388.3-199467.6" + attribute \src "libresoc.v:199417.3-199524.6" + wire width 3 $8\issue_fsm_state$next[2:0]$13525 + attribute \src "libresoc.v:199635.3-199725.6" + wire $8\pc_changed$next[0:0]$13542 + attribute \src "libresoc.v:199807.3-199897.6" + wire $8\sv_changed$next[0:0]$13554 + attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $9\core_data_i[63:0] - attribute \src "libresoc.v:199308.3-199387.6" + attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $9\core_wen[2:0] - attribute \src "libresoc.v:199948.3-200046.6" - wire width 3 $9\issue_fsm_state$next[2:0]$13543 - attribute \src "libresoc.v:200141.3-200223.6" - wire $9\pc_changed$next[0:0]$13559 - attribute \src "libresoc.v:200297.3-200379.6" - wire $9\sv_changed$next[0:0]$13571 - attribute \src "libresoc.v:197529.19-197529.108" - wire width 65 $add$libresoc.v:197529$13083_Y - attribute \src "libresoc.v:197541.19-197541.112" - wire width 8 $add$libresoc.v:197541$13094_Y - attribute \src "libresoc.v:197542.19-197542.112" - wire width 8 $add$libresoc.v:197542$13095_Y - attribute \src "libresoc.v:197612.19-197612.116" - wire width 65 $add$libresoc.v:197612$13165_Y - attribute \src "libresoc.v:197646.18-197646.107" - wire width 65 $add$libresoc.v:197646$13198_Y - attribute \src "libresoc.v:197534.19-197534.104" - wire $and$libresoc.v:197534$13088_Y - attribute \src "libresoc.v:197537.19-197537.104" - wire $and$libresoc.v:197537$13091_Y - attribute \src "libresoc.v:197545.19-197545.104" - wire $and$libresoc.v:197545$13098_Y - attribute \src "libresoc.v:197548.19-197548.104" - wire $and$libresoc.v:197548$13101_Y - attribute \src "libresoc.v:197550.19-197550.111" - wire $and$libresoc.v:197550$13103_Y - attribute \src "libresoc.v:197553.19-197553.104" - wire $and$libresoc.v:197553$13106_Y - attribute \src "libresoc.v:197559.19-197559.104" - wire $and$libresoc.v:197559$13111_Y - attribute \src "libresoc.v:197562.19-197562.104" - wire $and$libresoc.v:197562$13114_Y - attribute \src "libresoc.v:197565.19-197565.104" - wire $and$libresoc.v:197565$13117_Y - attribute \src "libresoc.v:197568.19-197568.104" - wire $and$libresoc.v:197568$13120_Y - attribute \src "libresoc.v:197571.19-197571.104" - wire $and$libresoc.v:197571$13123_Y - attribute \src "libresoc.v:197574.19-197574.104" - wire $and$libresoc.v:197574$13126_Y - attribute \src "libresoc.v:197575.19-197575.115" - wire width 3 $and$libresoc.v:197575$13127_Y - attribute \src "libresoc.v:197579.19-197579.104" - wire $and$libresoc.v:197579$13131_Y - attribute \src "libresoc.v:197582.19-197582.104" - wire $and$libresoc.v:197582$13134_Y - attribute \src "libresoc.v:197588.19-197588.104" - wire $and$libresoc.v:197588$13139_Y - attribute \src "libresoc.v:197591.19-197591.104" - wire $and$libresoc.v:197591$13142_Y - attribute \src "libresoc.v:197592.19-197592.115" - wire width 3 $and$libresoc.v:197592$13143_Y - attribute \src "libresoc.v:197595.19-197595.111" - wire $and$libresoc.v:197595$13146_Y - attribute \src "libresoc.v:197600.19-197600.104" - wire $and$libresoc.v:197600$13151_Y - attribute \src "libresoc.v:197603.19-197603.104" - wire $and$libresoc.v:197603$13154_Y - attribute \src "libresoc.v:197618.18-197618.109" - wire $and$libresoc.v:197618$13171_Y - attribute \src "libresoc.v:197624.18-197624.101" - wire $and$libresoc.v:197624$13178_Y - attribute \src "libresoc.v:197626.18-197626.109" - wire $and$libresoc.v:197626$13180_Y - attribute \src "libresoc.v:197629.18-197629.101" - wire $and$libresoc.v:197629$13183_Y - attribute \src "libresoc.v:197635.18-197635.101" - wire $and$libresoc.v:197635$13188_Y - attribute \src "libresoc.v:197637.18-197637.109" - wire $and$libresoc.v:197637$13190_Y - attribute \src "libresoc.v:197640.18-197640.101" - wire $and$libresoc.v:197640$13193_Y - attribute \src "libresoc.v:197549.19-197549.108" - wire $eq$libresoc.v:197549$13102_Y - attribute \src "libresoc.v:197594.19-197594.108" - wire $eq$libresoc.v:197594$13145_Y - attribute \src "libresoc.v:197604.19-197604.116" - wire $eq$libresoc.v:197604$13155_Y - attribute \src "libresoc.v:197625.18-197625.107" - wire $eq$libresoc.v:197625$13179_Y - attribute \src "libresoc.v:197636.18-197636.107" - wire $eq$libresoc.v:197636$13189_Y - attribute \src "libresoc.v:197609.19-197609.114" - wire width 64 $extend$libresoc.v:197609$13160_Y - attribute \src "libresoc.v:197610.19-197610.113" - wire width 64 $extend$libresoc.v:197610$13162_Y - attribute \src "libresoc.v:197621.18-197621.109" - wire width 64 $extend$libresoc.v:197621$13174_Y - attribute \src "libresoc.v:197530.19-197530.106" - wire width 7 $mul$libresoc.v:197530$13084_Y - attribute \src "libresoc.v:197647.18-197647.110" - wire width 7 $mul$libresoc.v:197647$13199_Y - attribute \src "libresoc.v:197598.18-197598.102" - wire $ne$libresoc.v:197598$13149_Y - attribute \src "libresoc.v:197606.19-197606.123" - wire $ne$libresoc.v:197606$13157_Y - attribute \src "libresoc.v:197616.18-197616.102" - wire $ne$libresoc.v:197616$13169_Y - attribute \src "libresoc.v:197532.19-197532.107" - wire $not$libresoc.v:197532$13086_Y - attribute \src "libresoc.v:197533.19-197533.109" - wire $not$libresoc.v:197533$13087_Y - attribute \src "libresoc.v:197535.19-197535.107" - wire $not$libresoc.v:197535$13089_Y - attribute \src "libresoc.v:197536.19-197536.109" - wire $not$libresoc.v:197536$13090_Y - attribute \src "libresoc.v:197543.19-197543.107" - wire $not$libresoc.v:197543$13096_Y - attribute \src "libresoc.v:197544.19-197544.109" - wire $not$libresoc.v:197544$13097_Y - attribute \src "libresoc.v:197546.19-197546.107" - wire $not$libresoc.v:197546$13099_Y - attribute \src "libresoc.v:197547.19-197547.109" - wire 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$not$libresoc.v:197569$13121_Y - attribute \src "libresoc.v:197570.19-197570.109" - wire $not$libresoc.v:197570$13122_Y - attribute \src "libresoc.v:197572.19-197572.107" - wire $not$libresoc.v:197572$13124_Y - attribute \src "libresoc.v:197573.19-197573.109" - wire $not$libresoc.v:197573$13125_Y - attribute \src "libresoc.v:197577.19-197577.107" - wire $not$libresoc.v:197577$13129_Y - attribute \src "libresoc.v:197578.19-197578.109" - wire $not$libresoc.v:197578$13130_Y - attribute \src "libresoc.v:197580.19-197580.107" - wire $not$libresoc.v:197580$13132_Y - attribute \src "libresoc.v:197581.19-197581.109" - wire $not$libresoc.v:197581$13133_Y - attribute \src "libresoc.v:197586.19-197586.107" - wire $not$libresoc.v:197586$13137_Y - attribute \src "libresoc.v:197587.19-197587.109" - wire $not$libresoc.v:197587$13138_Y - attribute \src "libresoc.v:197589.19-197589.107" - wire $not$libresoc.v:197589$13140_Y - attribute \src "libresoc.v:197590.19-197590.109" - wire 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$not$libresoc.v:197139$13169_Y + attribute \src "libresoc.v:197141.18-197141.97" + wire $not$libresoc.v:197141$13171_Y + attribute \src "libresoc.v:197142.18-197142.102" + wire $not$libresoc.v:197142$13172_Y + attribute \src "libresoc.v:197144.18-197144.106" + wire $not$libresoc.v:197144$13175_Y + attribute \src "libresoc.v:197145.18-197145.108" + wire $not$libresoc.v:197145$13176_Y + attribute \src "libresoc.v:197149.18-197149.106" + wire $not$libresoc.v:197149$13180_Y + attribute \src "libresoc.v:197150.18-197150.108" + wire $not$libresoc.v:197150$13181_Y + attribute \src "libresoc.v:197155.18-197155.106" + wire $not$libresoc.v:197155$13185_Y + attribute \src "libresoc.v:197156.18-197156.108" + wire $not$libresoc.v:197156$13186_Y + attribute \src "libresoc.v:197160.18-197160.106" + wire $not$libresoc.v:197160$13190_Y + attribute \src "libresoc.v:197161.18-197161.108" + wire $not$libresoc.v:197161$13191_Y + attribute \src "libresoc.v:197166.18-197166.99" + wire $not$libresoc.v:197166$13195_Y + attribute \src "libresoc.v:197167.18-197167.99" + wire $not$libresoc.v:197167$13196_Y + attribute \src "libresoc.v:197059.19-197059.113" + wire $or$libresoc.v:197059$13090_Y + attribute \src "libresoc.v:197061.19-197061.106" + wire $or$libresoc.v:197061$13091_Y + attribute \src "libresoc.v:197076.19-197076.113" + wire $or$libresoc.v:197076$13106_Y + attribute \src "libresoc.v:197078.19-197078.106" + wire $or$libresoc.v:197078$13107_Y + attribute \src "libresoc.v:197105.19-197105.113" + wire $or$libresoc.v:197105$13134_Y + attribute \src "libresoc.v:197107.19-197107.106" + wire $or$libresoc.v:197107$13135_Y + attribute \src "libresoc.v:197136.18-197136.110" + wire $or$libresoc.v:197136$13166_Y + attribute \src "libresoc.v:197137.18-197137.100" + wire $or$libresoc.v:197137$13167_Y + attribute \src "libresoc.v:197152.18-197152.112" + wire $or$libresoc.v:197152$13183_Y + attribute \src "libresoc.v:197154.18-197154.104" + wire $or$libresoc.v:197154$13184_Y + attribute \src "libresoc.v:197163.18-197163.112" + wire $or$libresoc.v:197163$13193_Y + attribute \src "libresoc.v:197165.18-197165.104" + wire $or$libresoc.v:197165$13194_Y + attribute \src "libresoc.v:197127.19-197127.211" + wire width 64 $pos$libresoc.v:197127$13155_Y + attribute \src "libresoc.v:197131.19-197131.114" + wire width 64 $pos$libresoc.v:197131$13160_Y + attribute \src "libresoc.v:197132.19-197132.113" + wire width 64 $pos$libresoc.v:197132$13162_Y + attribute \src "libresoc.v:197143.18-197143.109" + wire width 64 $pos$libresoc.v:197143$13174_Y + attribute \src "libresoc.v:197098.19-197098.93" + wire $reduce_or$libresoc.v:197098$13127_Y + attribute \src "libresoc.v:197115.19-197115.93" + wire $reduce_or$libresoc.v:197115$13143_Y + attribute \src "libresoc.v:197052.18-197052.41" + wire width 64 $shr$libresoc.v:197052$13083_Y + attribute \src "libresoc.v:197170.18-197170.40" + wire width 64 $shr$libresoc.v:197170$13199_Y + attribute \src "libresoc.v:197133.19-197133.116" + wire width 65 $sub$libresoc.v:197133$13163_Y + attribute \src "libresoc.v:197134.18-197134.101" + wire width 3 $sub$libresoc.v:197134$13164_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" wire width 65 \$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" wire width 65 \$101 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" wire width 7 \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:523" wire width 8 \$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:523" wire width 8 \$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:524" wire width 8 \$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:524" wire width 8 \$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:586" wire \$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" wire \$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$192 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:737" - wire width 3 \$195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - wire \$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" + wire width 3 \$197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" wire \$212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$224 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$226 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$228 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" - wire width 3 \$229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:830" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" - wire \$232 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:765" + wire width 3 \$231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$234 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" wire \$238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$240 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$246 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$248 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:831" wire width 3 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" + wire \$252 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$252 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" - wire \$254 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" + wire width 64 \$254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:762" wire \$256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" wire \$258 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:831" wire width 3 \$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" + wire \$260 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \$262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1010" - wire width 65 \$264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1010" - wire width 65 \$265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \$264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1040" + wire width 65 \$266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1040" wire width 65 \$267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" - wire width 65 \$268 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1056" + wire width 65 \$269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1056" + wire width 65 \$270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" wire \$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" wire \$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" wire \$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" wire \$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:352" wire width 65 \$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:352" wire width 65 \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:54" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" wire width 32 \$95 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" wire width 7 \$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:54" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" wire width 32 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 294 \TAP_bus__tck @@ -370886,19 +370445,19 @@ module \ti wire output 285 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 295 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" wire output 3 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" - wire input 312 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" + wire input 1 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 \core_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 \core_asmcode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:237" wire input 4 \core_bigendian_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire \core_bigendian_i$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire \core_bigendian_i$10$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_cia__data_o @@ -371199,119 +370758,17 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_rego$next attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \core_core_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" @@ -371321,119 +370778,17 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_spr1_ok$next attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \core_core_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" @@ -371450,7 +370805,7 @@ module \ti wire width 2 \core_core_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" wire width 2 \core_core_svstep$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire \core_core_terminate_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \core_core_vl @@ -371460,9 +370815,9 @@ module \ti wire width 3 \core_core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 \core_core_xer_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" wire \core_corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire \core_coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_cr_out_ok @@ -371526,9 +370881,9 @@ module \ti wire \core_issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \core_issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" wire \core_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" wire \core_ivalid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \core_msr @@ -371538,9 +370893,9 @@ module \ti wire width 64 \core_msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_msr__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" wire width 32 \core_raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" wire width 32 \core_raw_insn_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_rego_ok @@ -371552,15 +370907,15 @@ module \ti wire \core_spro_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_state_nia_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" wire \core_stopped_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_sv__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire \core_sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire \core_sv_a_nz$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire \core_wb_dcache_en @@ -371572,8 +370927,8 @@ module \ti wire \core_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire \core_xer_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" - wire input 2 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" + wire input 312 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \cu_st__rel_o_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" @@ -371604,17 +370959,17 @@ module \ti wire width 7 \cur_cur_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \cur_cur_vl$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:965" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:995" wire \d_cr_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:965" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:995" wire \d_cr_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:955" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:985" wire \d_reg_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:955" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:985" wire \d_reg_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:975" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1005" wire \d_xer_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:975" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1005" wire \d_xer_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \dbg_core_dbg_core_dbg_dststep @@ -372162,242 +371517,242 @@ module \ti wire width 3 \dec2_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:799" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:799" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" wire width 2 \delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 155 \eint_0__core__i + wire output 282 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \eint_0__pad__i + wire input 151 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 156 \eint_1__core__i + wire output 283 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 25 \eint_1__pad__i + wire input 152 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 157 \eint_2__core__i + wire output 284 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" + wire input 153 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" wire \exec_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" wire \exec_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:889" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:919" wire \exec_insn_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:888" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:918" wire \exec_insn_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:893" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:923" wire \exec_pc_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:892" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:922" wire \exec_pc_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" wire width 2 \fetch_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" wire width 2 \fetch_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:907" wire \fetch_insn_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:906" wire \fetch_insn_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:903" wire \fetch_pc_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:902" wire \fetch_pc_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" wire width 2 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 164 \gpio_e10__core__i + wire output 236 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e10__core__o + wire input 106 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 35 \gpio_e10__core__oe + wire input 107 \gpio_e10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e10__pad__i + wire input 105 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 165 \gpio_e10__pad__o + wire output 237 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \gpio_e10__pad__oe + wire output 238 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \gpio_e11__core__i + wire output 239 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 37 \gpio_e11__core__o + wire input 109 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_e11__core__oe + wire input 110 \gpio_e11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 36 \gpio_e11__pad__i + wire input 108 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \gpio_e11__pad__o + wire output 240 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_e11__pad__oe + wire output 241 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_e12__core__i + wire output 242 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_e12__core__o + wire input 112 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 41 \gpio_e12__core__oe + wire input 113 \gpio_e12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_e12__pad__i + wire input 111 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_e12__pad__o + wire output 243 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_e12__pad__oe + wire output 244 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e13__core__i + wire output 245 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 43 \gpio_e13__core__o + wire input 115 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_e13__core__oe + wire input 116 \gpio_e13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 42 \gpio_e13__pad__i + wire input 114 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e13__pad__o + wire output 246 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e13__pad__oe + wire output 247 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e14__core__i + wire output 248 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_e14__core__o + wire input 118 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 47 \gpio_e14__core__oe + wire input 119 \gpio_e14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_e14__pad__i + wire input 117 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e14__pad__o + wire output 249 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e14__pad__oe + wire output 250 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e15__core__i + wire output 251 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 49 \gpio_e15__core__o + wire input 121 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_e15__core__oe + wire input 122 \gpio_e15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 48 \gpio_e15__pad__i + wire input 120 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e15__pad__o + wire output 252 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e15__pad__oe + wire output 253 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 158 \gpio_e8__core__i + wire output 230 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e8__core__o + wire input 100 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 29 \gpio_e8__core__oe + wire input 101 \gpio_e8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e8__pad__i + wire input 99 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 159 \gpio_e8__pad__o + wire output 231 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 160 \gpio_e8__pad__oe + wire output 232 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 161 \gpio_e9__core__i + wire output 233 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 31 \gpio_e9__core__o + wire input 103 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e9__core__oe + wire input 104 \gpio_e9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 30 \gpio_e9__pad__i + wire input 102 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 162 \gpio_e9__pad__o + wire output 234 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 163 \gpio_e9__pad__oe + wire output 235 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_s0__core__i + wire output 254 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_s0__core__o + wire input 124 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 53 \gpio_s0__core__oe + wire input 125 \gpio_s0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_s0__pad__i + wire input 123 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_s0__pad__o + wire output 255 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_s0__pad__oe + wire output 256 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_s1__core__i + wire output 257 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 55 \gpio_s1__core__o + wire input 127 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_s1__core__oe + wire input 128 \gpio_s1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 54 \gpio_s1__pad__i + wire input 126 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_s1__pad__o + wire output 258 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_s1__pad__oe + wire output 259 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_s2__core__i + wire output 260 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_s2__core__o + wire input 130 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 59 \gpio_s2__core__oe + wire input 131 \gpio_s2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_s2__pad__i + wire input 129 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_s2__pad__o + wire output 261 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_s2__pad__oe + wire output 262 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_s3__core__i + wire output 263 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 61 \gpio_s3__core__o + wire input 133 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \gpio_s3__core__oe + wire input 134 \gpio_s3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 60 \gpio_s3__pad__i + wire input 132 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_s3__pad__o + wire output 264 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_s3__pad__oe + wire output 265 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_s4__core__i + wire output 266 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \gpio_s4__core__o + wire input 136 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 65 \gpio_s4__core__oe + wire input 137 \gpio_s4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \gpio_s4__pad__i + wire input 135 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_s4__pad__o + wire output 267 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_s4__pad__oe + wire output 268 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s5__core__i + wire output 269 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \gpio_s5__core__o + wire input 139 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \gpio_s5__core__oe + wire input 140 \gpio_s5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \gpio_s5__pad__i + wire input 138 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s5__pad__o + wire output 270 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s5__pad__oe + wire output 271 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s6__core__i + wire output 272 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \gpio_s6__core__o + wire input 142 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \gpio_s6__core__oe + wire input 143 \gpio_s6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \gpio_s6__pad__i + wire input 141 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s6__pad__o + wire output 273 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s6__pad__oe + wire output 274 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s7__core__i + wire output 275 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \gpio_s7__core__o + wire input 145 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \gpio_s7__core__oe + wire input 146 \gpio_s7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \gpio_s7__pad__i + wire input 144 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s7__pad__o + wire output 276 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s7__pad__oe + wire output 277 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 18 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" @@ -372454,19 +371809,19 @@ module \ti wire \imem_f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \imem_wb_icache_en - attribute \src "libresoc.v:195254.7-195254.15" + attribute \src "libresoc.v:194977.7-194977.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:267" wire \insn_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 305 \int_level_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667" wire \is_last - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:866" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:896" wire \is_svp64_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire width 3 \issue_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire width 3 \issue_fsm_state$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__ack_o @@ -372501,42 +371856,42 @@ module \ti attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 290 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \mspi0_clk__core__o + wire input 24 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \mspi0_clk__pad__o + wire output 155 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \mspi0_cs_n__core__o + wire input 25 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \mspi0_cs_n__pad__o + wire output 156 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \mspi0_miso__core__i + wire output 158 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \mspi0_miso__pad__i + wire input 27 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \mspi0_mosi__core__o + wire input 26 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \mspi0_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + wire output 157 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" wire \msr_read$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \mtwi_scl__core__o + wire input 150 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \mtwi_scl__pad__o + wire output 281 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \mtwi_sda__core__i + wire output 278 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \mtwi_sda__core__o + wire input 148 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \mtwi_sda__core__oe + wire input 149 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \mtwi_sda__pad__i + wire input 147 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \mtwi_sda__pad__o + wire output 279 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1008" + wire output 280 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" wire width 64 \new_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \new_svstate_dststep @@ -372550,345 +371905,345 @@ module \ti wire width 2 \new_svstate_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \new_svstate_vl - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1025" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:522" wire width 7 \next_dststep - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" wire width 7 \next_srcstep - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:885" wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:885" wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:866" wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:866" wire \pc_changed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 7 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 6 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:234" wire width 64 output 5 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" wire \pc_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" wire \por_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:881" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:911" wire \pred_insn_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:910" wire \pred_insn_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:885" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:915" wire \pred_mask_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:914" wire \pred_mask_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" - wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" + wire input 2 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_a_0__core__o + wire input 53 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sdr_a_0__pad__o + wire output 184 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_a_10__core__o + wire input 71 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_a_10__pad__o + wire output 202 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_a_11__core__o + wire input 72 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_a_11__pad__o + wire output 203 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_a_12__core__o + wire input 73 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_a_12__pad__o + wire output 204 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_a_1__core__o + wire input 54 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sdr_a_1__pad__o + wire output 185 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_a_2__core__o + wire input 55 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sdr_a_2__pad__o + wire output 186 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_a_3__core__o + wire input 56 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sdr_a_3__pad__o + wire output 187 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_a_4__core__o + wire input 57 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sdr_a_4__pad__o + wire output 188 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_a_5__core__o + wire input 58 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sdr_a_5__pad__o + wire output 189 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_a_6__core__o + wire input 59 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sdr_a_6__pad__o + wire output 190 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_a_7__core__o + wire input 60 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_a_7__pad__o + wire output 191 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_a_8__core__o + wire input 61 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_a_8__pad__o + wire output 192 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_a_9__core__o + wire input 62 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_a_9__pad__o + wire output 193 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_ba_0__core__o + wire input 63 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_ba_0__pad__o + wire output 194 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_ba_1__core__o + wire input 64 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_ba_1__pad__o + wire output 195 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_cas_n__core__o + wire input 68 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_cas_n__pad__o + wire output 199 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_cke__core__o + wire input 66 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_cke__pad__o + wire output 197 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_clock__core__o + wire input 65 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_clock__pad__o + wire output 196 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_cs_n__core__o + wire input 70 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_cs_n__pad__o + wire output 201 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \sdr_dm_0__core__o + wire input 28 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \sdr_dm_0__pad__o + wire output 159 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_dm_1__core__o + wire input 74 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dm_1__pad__o + wire output 205 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \sdr_dq_0__core__i + wire output 160 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \sdr_dq_0__core__o + wire input 30 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \sdr_dq_0__core__oe + wire input 31 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \sdr_dq_0__pad__i + wire input 29 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \sdr_dq_0__pad__o + wire output 161 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \sdr_dq_0__pad__oe + wire output 162 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_10__core__i + wire output 212 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_dq_10__core__o + wire input 82 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dq_10__core__oe + wire input 83 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_dq_10__pad__i + wire input 81 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_10__pad__o + wire output 213 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_10__pad__oe + wire output 214 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_11__core__i + wire output 215 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dq_11__core__o + wire input 85 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_11__core__oe + wire input 86 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dq_11__pad__i + wire input 84 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_dq_11__pad__o + wire output 216 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_dq_11__pad__oe + wire output 217 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dq_12__core__i + wire output 218 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dq_12__core__o + wire input 88 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dq_12__core__oe + wire input 89 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_12__pad__i + wire input 87 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_dq_12__pad__o + wire output 219 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_dq_12__pad__oe + wire output 220 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_dq_13__core__i + wire output 221 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_13__core__o + wire input 91 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_13__core__oe + wire input 92 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_13__pad__i + wire input 90 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_dq_13__pad__o + wire output 222 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_dq_13__pad__oe + wire output 223 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_14__core__i + wire output 224 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_14__core__o + wire input 94 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_14__core__oe + wire input 95 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_14__pad__i + wire input 93 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_dq_14__pad__o + wire output 225 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_dq_14__pad__oe + wire output 226 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_dq_15__core__i + wire output 227 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_15__core__o + wire input 97 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_15__core__oe + wire input 98 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_15__pad__i + wire input 96 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_dq_15__pad__o + wire output 228 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_dq_15__pad__oe + wire output 229 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \sdr_dq_1__core__i + wire output 163 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \sdr_dq_1__core__o + wire input 33 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sdr_dq_1__core__oe + wire input 34 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \sdr_dq_1__pad__i + wire input 32 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \sdr_dq_1__pad__o + wire output 164 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \sdr_dq_1__pad__oe + wire output 165 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \sdr_dq_2__core__i + wire output 166 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sdr_dq_2__core__o + wire input 36 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sdr_dq_2__core__oe + wire input 37 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sdr_dq_2__pad__i + wire input 35 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \sdr_dq_2__pad__o + wire output 167 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \sdr_dq_2__pad__oe + wire output 168 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \sdr_dq_3__core__i + wire output 169 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sdr_dq_3__core__o + wire input 39 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sdr_dq_3__core__oe + wire input 40 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sdr_dq_3__pad__i + wire input 38 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \sdr_dq_3__pad__o + wire output 170 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \sdr_dq_3__pad__oe + wire output 171 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \sdr_dq_4__core__i + wire output 172 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sdr_dq_4__core__o + wire input 42 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sdr_dq_4__core__oe + wire input 43 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sdr_dq_4__pad__i + wire input 41 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \sdr_dq_4__pad__o + wire output 173 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \sdr_dq_4__pad__oe + wire output 174 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sdr_dq_5__core__i + wire output 175 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sdr_dq_5__core__o + wire input 45 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sdr_dq_5__core__oe + wire input 46 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sdr_dq_5__pad__i + wire input 44 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sdr_dq_5__pad__o + wire output 176 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sdr_dq_5__pad__oe + wire output 177 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sdr_dq_6__core__i + wire output 178 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sdr_dq_6__core__o + wire input 48 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sdr_dq_6__core__oe + wire input 49 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sdr_dq_6__pad__i + wire input 47 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sdr_dq_6__pad__o + wire output 179 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sdr_dq_6__pad__oe + wire output 180 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sdr_dq_7__core__i + wire output 181 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_7__core__o + wire input 51 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_7__core__oe + wire input 52 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dq_7__pad__i + wire input 50 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sdr_dq_7__pad__o + wire output 182 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sdr_dq_7__pad__oe + wire output 183 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_8__core__i + wire output 206 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_dq_8__core__o + wire input 76 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_dq_8__core__oe + wire input 77 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_dq_8__pad__i + wire input 75 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_8__pad__o + wire output 207 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_8__pad__oe + wire output 208 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_9__core__i + wire output 209 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_dq_9__core__o + wire input 79 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_dq_9__core__oe + wire input 80 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_dq_9__pad__i + wire input 78 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_9__pad__o + wire output 210 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_9__pad__oe + wire output 211 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_ras_n__core__o + wire input 67 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_ras_n__pad__o + wire output 198 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_we_n__core__o + wire input 69 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:837" + wire output 200 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" wire \sv_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:837" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" wire \sv_changed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" wire width 64 \svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \svstate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \svstate_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" wire \svstate_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" wire \svstate_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" wire \ti_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:506" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire \update_svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \xics_icp_core_irq_o @@ -372900,8 +372255,8 @@ module \ti wire width 8 \xics_ics_icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" - cell $add $add$libresoc.v:197529$13083 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + cell $add $add$libresoc.v:197050$13081 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -372909,10 +372264,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:197529$13083_Y + connect \Y $add$libresoc.v:197050$13081_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - cell $add $add$libresoc.v:197541$13094 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:523" + cell $add $add$libresoc.v:197062$13092 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -372920,10 +372275,10 @@ module \ti parameter \Y_WIDTH 8 connect \A \cur_cur_srcstep connect \B 1'1 - connect \Y $add$libresoc.v:197541$13094_Y + connect \Y $add$libresoc.v:197062$13092_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516" - cell $add $add$libresoc.v:197542$13095 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:524" + cell $add $add$libresoc.v:197063$13093 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -372931,10 +372286,10 @@ module \ti parameter \Y_WIDTH 8 connect \A \cur_cur_dststep connect \B 1'1 - connect \Y $add$libresoc.v:197542$13095_Y + connect \Y $add$libresoc.v:197063$13093_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" - cell $add $add$libresoc.v:197612$13165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1056" + cell $add $add$libresoc.v:197135$13165 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -372942,10 +372297,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $add$libresoc.v:197612$13165_Y + connect \Y $add$libresoc.v:197135$13165_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344" - cell $add $add$libresoc.v:197646$13198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:352" + cell $add $add$libresoc.v:197168$13197 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -372953,10 +372308,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:197646$13198_Y + connect \Y $add$libresoc.v:197168$13197_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $and $and$libresoc.v:197534$13088 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $and $and$libresoc.v:197055$13086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -372964,10 +372319,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$106 connect \B \$108 - connect \Y $and$libresoc.v:197534$13088_Y + connect \Y $and$libresoc.v:197055$13086_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $and $and$libresoc.v:197537$13091 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $and $and$libresoc.v:197058$13089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -372975,10 +372330,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$112 connect \B \$114 - connect \Y $and$libresoc.v:197537$13091_Y + connect \Y $and$libresoc.v:197058$13089_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $and $and$libresoc.v:197545$13098 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $and $and$libresoc.v:197066$13096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -372986,10 +372341,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$130 connect \B \$132 - connect \Y $and$libresoc.v:197545$13098_Y + connect \Y $and$libresoc.v:197066$13096_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $and $and$libresoc.v:197548$13101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $and $and$libresoc.v:197069$13099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -372997,10 +372352,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$136 connect \B \$138 - connect \Y $and$libresoc.v:197548$13101_Y + connect \Y $and$libresoc.v:197069$13099_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" - cell $and $and$libresoc.v:197550$13103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + cell $and $and$libresoc.v:197071$13101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373008,87 +372363,87 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$142 - connect \Y $and$libresoc.v:197550$13103_Y + connect \Y $and$libresoc.v:197071$13101_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $and $and$libresoc.v:197553$13106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $and $and$libresoc.v:197075$13105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$146 - connect \B \$148 - connect \Y $and$libresoc.v:197553$13106_Y + connect \A \$148 + connect \B \$150 + connect \Y $and$libresoc.v:197075$13105_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $and $and$libresoc.v:197559$13111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $and $and$libresoc.v:197081$13110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$158 - connect \B \$160 - connect \Y $and$libresoc.v:197559$13111_Y + connect \A \$160 + connect \B \$162 + connect \Y $and$libresoc.v:197081$13110_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $and $and$libresoc.v:197562$13114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $and $and$libresoc.v:197084$13113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$164 - connect \B \$166 - connect \Y $and$libresoc.v:197562$13114_Y + connect \A \$166 + connect \B \$168 + connect \Y $and$libresoc.v:197084$13113_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $and $and$libresoc.v:197565$13117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $and $and$libresoc.v:197087$13116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$170 - connect \B \$172 - connect \Y $and$libresoc.v:197565$13117_Y + connect \A \$172 + connect \B \$174 + connect \Y $and$libresoc.v:197087$13116_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $and $and$libresoc.v:197568$13120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $and $and$libresoc.v:197090$13119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$176 - connect \B \$178 - connect \Y $and$libresoc.v:197568$13120_Y + connect \A \$178 + connect \B \$180 + connect \Y $and$libresoc.v:197090$13119_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $and $and$libresoc.v:197571$13123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $and $and$libresoc.v:197093$13122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$182 - connect \B \$184 - connect \Y $and$libresoc.v:197571$13123_Y + connect \A \$184 + connect \B \$186 + connect \Y $and$libresoc.v:197093$13122_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $and $and$libresoc.v:197574$13126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $and $and$libresoc.v:197096$13125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$188 - connect \B \$190 - connect \Y $and$libresoc.v:197574$13126_Y + connect \A \$190 + connect \B \$192 + connect \Y $and$libresoc.v:197096$13125_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:737" - cell $and $and$libresoc.v:197575$13127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" + cell $and $and$libresoc.v:197097$13126 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -373096,54 +372451,54 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 1'1 - connect \Y $and$libresoc.v:197575$13127_Y + connect \Y $and$libresoc.v:197097$13126_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $and $and$libresoc.v:197579$13131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $and $and$libresoc.v:197101$13130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$198 - connect \B \$200 - connect \Y $and$libresoc.v:197579$13131_Y + connect \A \$200 + connect \B \$202 + connect \Y $and$libresoc.v:197101$13130_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $and $and$libresoc.v:197582$13134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $and $and$libresoc.v:197104$13133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$204 - connect \B \$206 - connect \Y $and$libresoc.v:197582$13134_Y + connect \A \$206 + connect \B \$208 + connect \Y $and$libresoc.v:197104$13133_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $and $and$libresoc.v:197588$13139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $and $and$libresoc.v:197110$13138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$216 - connect \B \$218 - connect \Y $and$libresoc.v:197588$13139_Y + connect \A \$218 + connect \B \$220 + connect \Y $and$libresoc.v:197110$13138_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $and $and$libresoc.v:197591$13142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $and $and$libresoc.v:197113$13141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$222 - connect \B \$224 - connect \Y $and$libresoc.v:197591$13142_Y + connect \A \$224 + connect \B \$226 + connect \Y $and$libresoc.v:197113$13141_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" - cell $and $and$libresoc.v:197592$13143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:765" + cell $and $and$libresoc.v:197114$13142 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -373151,43 +372506,43 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 3'100 - connect \Y $and$libresoc.v:197592$13143_Y + connect \Y $and$libresoc.v:197114$13142_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" - cell $and $and$libresoc.v:197595$13146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + cell $and $and$libresoc.v:197117$13145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_svp64_mode - connect \B \$232 - connect \Y $and$libresoc.v:197595$13146_Y + connect \B \$234 + connect \Y $and$libresoc.v:197117$13145_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $and $and$libresoc.v:197600$13151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $and $and$libresoc.v:197122$13150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$238 - connect \B \$240 - connect \Y $and$libresoc.v:197600$13151_Y + connect \A \$240 + connect \B \$242 + connect \Y $and$libresoc.v:197122$13150_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $and $and$libresoc.v:197603$13154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $and $and$libresoc.v:197125$13153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$244 - connect \B \$246 - connect \Y $and$libresoc.v:197603$13154_Y + connect \A \$246 + connect \B \$248 + connect \Y $and$libresoc.v:197125$13153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:197618$13171 + cell $and $and$libresoc.v:197140$13170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373195,10 +372550,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_cu_st__rel_o connect \B \$34 - connect \Y $and$libresoc.v:197618$13171_Y + connect \Y $and$libresoc.v:197140$13170_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $and $and$libresoc.v:197624$13178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $and $and$libresoc.v:197146$13177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373206,10 +372561,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:197624$13178_Y + connect \Y $and$libresoc.v:197146$13177_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" - cell $and $and$libresoc.v:197626$13180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + cell $and $and$libresoc.v:197148$13179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373217,10 +372572,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$50 - connect \Y $and$libresoc.v:197626$13180_Y + connect \Y $and$libresoc.v:197148$13179_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $and $and$libresoc.v:197629$13183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $and $and$libresoc.v:197151$13182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373228,10 +372583,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$54 connect \B \$56 - connect \Y $and$libresoc.v:197629$13183_Y + connect \Y $and$libresoc.v:197151$13182_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $and $and$libresoc.v:197635$13188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $and $and$libresoc.v:197157$13187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373239,10 +372594,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$66 connect \B \$68 - connect \Y $and$libresoc.v:197635$13188_Y + connect \Y $and$libresoc.v:197157$13187_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" - cell $and $and$libresoc.v:197637$13190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + cell $and $and$libresoc.v:197159$13189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373250,10 +372605,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$72 - connect \Y $and$libresoc.v:197637$13190_Y + connect \Y $and$libresoc.v:197159$13189_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $and $and$libresoc.v:197640$13193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $and $and$libresoc.v:197162$13192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373261,10 +372616,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:197640$13193_Y + connect \Y $and$libresoc.v:197162$13192_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" - cell $eq $eq$libresoc.v:197549$13102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + cell $eq $eq$libresoc.v:197070$13100 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373272,10 +372627,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197549$13102_Y + connect \Y $eq$libresoc.v:197070$13100_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" - cell $eq $eq$libresoc.v:197594$13145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + cell $eq $eq$libresoc.v:197116$13144 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373283,10 +372638,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197594$13145_Y + connect \Y $eq$libresoc.v:197116$13144_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" - cell $eq $eq$libresoc.v:197604$13155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" + cell $eq $eq$libresoc.v:197126$13154 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373294,10 +372649,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \next_srcstep connect \B \cur_cur_vl - connect \Y $eq$libresoc.v:197604$13155_Y + connect \Y $eq$libresoc.v:197126$13154_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" - cell $eq $eq$libresoc.v:197625$13179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + cell $eq $eq$libresoc.v:197147$13178 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373305,10 +372660,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197625$13179_Y + connect \Y $eq$libresoc.v:197147$13178_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" - cell $eq $eq$libresoc.v:197636$13189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + cell $eq $eq$libresoc.v:197158$13188 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373316,34 +372671,34 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197636$13189_Y + connect \Y $eq$libresoc.v:197158$13188_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:197609$13160 + cell $pos $extend$libresoc.v:197131$13159 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \core_full_rd2__data_o - connect \Y $extend$libresoc.v:197609$13160_Y + connect \Y $extend$libresoc.v:197131$13159_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:197610$13162 + cell $pos $extend$libresoc.v:197132$13161 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \core_full_rd__data_o - connect \Y $extend$libresoc.v:197610$13162_Y + connect \Y $extend$libresoc.v:197132$13161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $extend$libresoc.v:197621$13174 + cell $pos $extend$libresoc.v:197143$13173 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \svstate_i - connect \Y $extend$libresoc.v:197621$13174_Y + connect \Y $extend$libresoc.v:197143$13173_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:197530$13084 + cell $mul $mul$libresoc.v:197051$13082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373351,10 +372706,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \$100 [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:197530$13084_Y + connect \Y $mul$libresoc.v:197051$13082_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:197647$13199 + cell $mul $mul$libresoc.v:197169$13198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373362,10 +372717,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:197647$13199_Y + connect \Y $mul$libresoc.v:197169$13198_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" - cell $ne $ne$libresoc.v:197598$13149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:830" + cell $ne $ne$libresoc.v:197119$13147 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -373373,10 +372728,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B 1'0 - connect \Y $ne$libresoc.v:197598$13149_Y + connect \Y $ne$libresoc.v:197119$13147_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" - cell $ne $ne$libresoc.v:197606$13157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:762" + cell $ne $ne$libresoc.v:197128$13156 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373384,10 +372739,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_core_core_insn_type connect \B 7'0000001 - connect \Y $ne$libresoc.v:197606$13157_Y + connect \Y $ne$libresoc.v:197128$13156_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806" - cell $ne $ne$libresoc.v:197616$13169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" + cell $ne $ne$libresoc.v:197138$13168 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -373395,410 +372750,418 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B \$30 - connect \Y $ne$libresoc.v:197616$13169_Y + connect \Y $ne$libresoc.v:197138$13168_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197532$13086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197053$13084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197532$13086_Y + connect \Y $not$libresoc.v:197053$13084_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197533$13087 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197054$13085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197533$13087_Y + connect \Y $not$libresoc.v:197054$13085_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197535$13089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197056$13087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197535$13089_Y + connect \Y $not$libresoc.v:197056$13087_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197536$13090 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197057$13088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197536$13090_Y + connect \Y $not$libresoc.v:197057$13088_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197543$13096 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197064$13094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197543$13096_Y + connect \Y $not$libresoc.v:197064$13094_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197544$13097 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197065$13095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197544$13097_Y + connect \Y $not$libresoc.v:197065$13095_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197546$13099 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197067$13097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197546$13099_Y + connect \Y $not$libresoc.v:197067$13097_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197547$13100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197068$13098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197547$13100_Y + connect \Y $not$libresoc.v:197068$13098_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:586" + cell $not $not$libresoc.v:197072$13102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_svp64_mode + connect \Y $not$libresoc.v:197072$13102_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197551$13104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197073$13103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197551$13104_Y + connect \Y $not$libresoc.v:197073$13103_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197552$13105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197074$13104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197552$13105_Y + connect \Y $not$libresoc.v:197074$13104_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197557$13109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197079$13108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197557$13109_Y + connect \Y $not$libresoc.v:197079$13108_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197558$13110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197080$13109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197558$13110_Y + connect \Y $not$libresoc.v:197080$13109_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197560$13112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197082$13111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197560$13112_Y + connect \Y $not$libresoc.v:197082$13111_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197561$13113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197083$13112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197561$13113_Y + connect \Y $not$libresoc.v:197083$13112_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197563$13115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197085$13114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197563$13115_Y + connect \Y $not$libresoc.v:197085$13114_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197564$13116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197086$13115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197564$13116_Y + connect \Y $not$libresoc.v:197086$13115_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197566$13118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197088$13117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197566$13118_Y + connect \Y $not$libresoc.v:197088$13117_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197567$13119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197089$13118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197567$13119_Y + connect \Y $not$libresoc.v:197089$13118_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197569$13121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197091$13120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197569$13121_Y + connect \Y $not$libresoc.v:197091$13120_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197570$13122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197092$13121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197570$13122_Y + connect \Y $not$libresoc.v:197092$13121_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197572$13124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197094$13123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197572$13124_Y + connect \Y $not$libresoc.v:197094$13123_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197573$13125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197095$13124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197573$13125_Y + connect \Y $not$libresoc.v:197095$13124_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197577$13129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197099$13128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197577$13129_Y + connect \Y $not$libresoc.v:197099$13128_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197578$13130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197100$13129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197578$13130_Y + connect \Y $not$libresoc.v:197100$13129_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197580$13132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197102$13131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197580$13132_Y + connect \Y $not$libresoc.v:197102$13131_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197581$13133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197103$13132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197581$13133_Y + connect \Y $not$libresoc.v:197103$13132_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197586$13137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197108$13136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197586$13137_Y + connect \Y $not$libresoc.v:197108$13136_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197587$13138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197109$13137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197587$13138_Y + connect \Y $not$libresoc.v:197109$13137_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197589$13140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197111$13139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197589$13140_Y + connect \Y $not$libresoc.v:197111$13139_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197590$13141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197112$13140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197590$13141_Y + connect \Y $not$libresoc.v:197112$13140_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" - cell $not $not$libresoc.v:197596$13147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" + cell $not $not$libresoc.v:197118$13146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:197596$13147_Y + connect \Y $not$libresoc.v:197118$13146_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197597$13148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197120$13148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197597$13148_Y + connect \Y $not$libresoc.v:197120$13148_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197599$13150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197121$13149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197599$13150_Y + connect \Y $not$libresoc.v:197121$13149_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197601$13152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197123$13151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197601$13152_Y + connect \Y $not$libresoc.v:197123$13151_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197602$13153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197124$13152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197602$13153_Y + connect \Y $not$libresoc.v:197124$13152_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" - cell $not $not$libresoc.v:197607$13158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" + cell $not $not$libresoc.v:197129$13157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:197607$13158_Y + connect \Y $not$libresoc.v:197129$13157_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" - cell $not $not$libresoc.v:197608$13159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" + cell $not $not$libresoc.v:197130$13158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:197608$13159_Y + connect \Y $not$libresoc.v:197130$13158_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:197617$13170 + cell $not $not$libresoc.v:197139$13169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:197617$13170_Y + connect \Y $not$libresoc.v:197139$13169_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" - cell $not $not$libresoc.v:197619$13172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" + cell $not $not$libresoc.v:197141$13171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_i_ok - connect \Y $not$libresoc.v:197619$13172_Y + connect \Y $not$libresoc.v:197141$13171_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" - cell $not $not$libresoc.v:197620$13173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" + cell $not $not$libresoc.v:197142$13172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \svstate_i_ok - connect \Y $not$libresoc.v:197620$13173_Y + connect \Y $not$libresoc.v:197142$13172_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197622$13176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197144$13175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197622$13176_Y + connect \Y $not$libresoc.v:197144$13175_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197623$13177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197145$13176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197623$13177_Y + connect \Y $not$libresoc.v:197145$13176_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197627$13181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197149$13180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197627$13181_Y + connect \Y $not$libresoc.v:197149$13180_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197628$13182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197150$13181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197628$13182_Y + connect \Y $not$libresoc.v:197150$13181_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197633$13186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197155$13185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197633$13186_Y + connect \Y $not$libresoc.v:197155$13185_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $not $not$libresoc.v:197634$13187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + cell $not $not$libresoc.v:197156$13186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197634$13187_Y + connect \Y $not$libresoc.v:197156$13186_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197638$13191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197160$13190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197638$13191_Y + connect \Y $not$libresoc.v:197160$13190_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - cell $not $not$libresoc.v:197639$13192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + cell $not $not$libresoc.v:197161$13191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197639$13192_Y + connect \Y $not$libresoc.v:197161$13191_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" - cell $not $not$libresoc.v:197644$13196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" + cell $not $not$libresoc.v:197166$13195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:197644$13196_Y + connect \Y $not$libresoc.v:197166$13195_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" - cell $not $not$libresoc.v:197645$13197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" + cell $not $not$libresoc.v:197167$13196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:197645$13197_Y + connect \Y $not$libresoc.v:197167$13196_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" - cell $or $or$libresoc.v:197538$13092 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + cell $or $or$libresoc.v:197059$13090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373806,10 +373169,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197538$13092_Y + connect \Y $or$libresoc.v:197059$13090_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" - cell $or $or$libresoc.v:197540$13093 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" + cell $or $or$libresoc.v:197061$13091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373817,10 +373180,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$120 connect \B \is_last - connect \Y $or$libresoc.v:197540$13093_Y + connect \Y $or$libresoc.v:197061$13091_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" - cell $or $or$libresoc.v:197554$13107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + cell $or $or$libresoc.v:197076$13106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373828,21 +373191,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197554$13107_Y + connect \Y $or$libresoc.v:197076$13106_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" - cell $or $or$libresoc.v:197556$13108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" + cell $or $or$libresoc.v:197078$13107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$154 + connect \A \$156 connect \B \is_last - connect \Y $or$libresoc.v:197556$13108_Y + connect \Y $or$libresoc.v:197078$13107_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" - cell $or $or$libresoc.v:197583$13135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + cell $or $or$libresoc.v:197105$13134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373850,21 +373213,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197583$13135_Y + connect \Y $or$libresoc.v:197105$13134_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" - cell $or $or$libresoc.v:197585$13136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" + cell $or $or$libresoc.v:197107$13135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$212 + connect \A \$214 connect \B \is_last - connect \Y $or$libresoc.v:197585$13136_Y + connect \Y $or$libresoc.v:197107$13135_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806" - cell $or $or$libresoc.v:197614$13167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" + cell $or $or$libresoc.v:197136$13166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373872,10 +373235,10 @@ module \ti parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:197614$13167_Y + connect \Y $or$libresoc.v:197136$13166_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806" - cell $or $or$libresoc.v:197615$13168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" + cell $or $or$libresoc.v:197137$13167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373883,10 +373246,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$28 connect \B \rst - connect \Y $or$libresoc.v:197615$13168_Y + connect \Y $or$libresoc.v:197137$13167_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" - cell $or $or$libresoc.v:197630$13184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + cell $or $or$libresoc.v:197152$13183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373894,10 +373257,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197630$13184_Y + connect \Y $or$libresoc.v:197152$13183_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" - cell $or $or$libresoc.v:197632$13185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" + cell $or $or$libresoc.v:197154$13184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373905,10 +373268,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$62 connect \B \is_last - connect \Y $or$libresoc.v:197632$13185_Y + connect \Y $or$libresoc.v:197154$13184_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" - cell $or $or$libresoc.v:197641$13194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + cell $or $or$libresoc.v:197163$13193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373916,10 +373279,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197641$13194_Y + connect \Y $or$libresoc.v:197163$13193_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645" - cell $or $or$libresoc.v:197643$13195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" + cell $or $or$libresoc.v:197165$13194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373927,58 +373290,58 @@ module \ti parameter \Y_WIDTH 1 connect \A \$84 connect \B \is_last - connect \Y $or$libresoc.v:197643$13195_Y + connect \Y $or$libresoc.v:197165$13194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:197605$13156 + cell $pos $pos$libresoc.v:197127$13155 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } - connect \Y $pos$libresoc.v:197605$13156_Y + connect \Y $pos$libresoc.v:197127$13155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:197609$13161 + cell $pos $pos$libresoc.v:197131$13160 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:197609$13160_Y - connect \Y $pos$libresoc.v:197609$13161_Y + connect \A $extend$libresoc.v:197131$13159_Y + connect \Y $pos$libresoc.v:197131$13160_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:197610$13163 + cell $pos $pos$libresoc.v:197132$13162 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:197610$13162_Y - connect \Y $pos$libresoc.v:197610$13163_Y + connect \A $extend$libresoc.v:197132$13161_Y + connect \Y $pos$libresoc.v:197132$13162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" - cell $pos $pos$libresoc.v:197621$13175 + cell $pos $pos$libresoc.v:197143$13174 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:197621$13174_Y - connect \Y $pos$libresoc.v:197621$13175_Y + connect \A $extend$libresoc.v:197143$13173_Y + connect \Y $pos$libresoc.v:197143$13174_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:197576$13128 + cell $reduce_or $reduce_or$libresoc.v:197098$13127 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$195 - connect \Y $reduce_or$libresoc.v:197576$13128_Y + connect \A \$197 + connect \Y $reduce_or$libresoc.v:197098$13127_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:197593$13144 + cell $reduce_or $reduce_or$libresoc.v:197115$13143 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$229 - connect \Y $reduce_or$libresoc.v:197593$13144_Y + connect \A \$231 + connect \Y $reduce_or$libresoc.v:197115$13143_Y end - attribute \src "libresoc.v:197531.18-197531.41" - cell $shr $shr$libresoc.v:197531$13085 + attribute \src "libresoc.v:197052.18-197052.41" + cell $shr $shr$libresoc.v:197052$13083 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -373986,10 +373349,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$103 - connect \Y $shr$libresoc.v:197531$13085_Y + connect \Y $shr$libresoc.v:197052$13083_Y end - attribute \src "libresoc.v:197648.18-197648.40" - cell $shr $shr$libresoc.v:197648$13200 + attribute \src "libresoc.v:197170.18-197170.40" + cell $shr $shr$libresoc.v:197170$13199 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -373997,10 +373360,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$96 - connect \Y $shr$libresoc.v:197648$13200_Y + connect \Y $shr$libresoc.v:197170$13199_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1010" - cell $sub $sub$libresoc.v:197611$13164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1040" + cell $sub $sub$libresoc.v:197133$13163 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -374008,10 +373371,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $sub$libresoc.v:197611$13164_Y + connect \Y $sub$libresoc.v:197133$13163_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801" - cell $sub $sub$libresoc.v:197613$13166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:831" + cell $sub $sub$libresoc.v:197134$13164 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -374019,10 +373382,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 - connect \Y $sub$libresoc.v:197613$13166_Y + connect \Y $sub$libresoc.v:197134$13164_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:197857.8-197955.4" + attribute \src "libresoc.v:197379.8-197477.4" cell \core \core connect \bigendian_i \core_bigendian_i$10 connect \cia__data_o \core_cia__data_o @@ -374123,7 +373486,7 @@ module \ti connect \wen$10 \core_wen$11 end attribute \module_not_derived 1 - attribute \src "libresoc.v:197956.7-197987.4" + attribute \src "libresoc.v:197478.7-197509.4" cell \dbg \dbg connect \clk \clk connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep @@ -374157,7 +373520,7 @@ module \ti connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:197988.8-198055.4" + attribute \src "libresoc.v:197510.8-197577.4" cell \dec2 \dec2 connect \asmcode \dec2_asmcode connect \bigendian \dec2_bigendian @@ -374227,7 +373590,7 @@ module \ti connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:198056.8-198072.4" + attribute \src "libresoc.v:197578.8-197594.4" cell \imem \imem connect \a_pc_i \imem_a_pc_i connect \a_valid_i \imem_a_valid_i @@ -374246,7 +373609,7 @@ module \ti connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:198073.8-198356.4" + attribute \src "libresoc.v:197595.8-197878.4" cell \jtag \jtag connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -374532,7 +373895,7 @@ module \ti connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:198357.12-198371.4" + attribute \src "libresoc.v:197879.12-197893.4" cell \xics_icp \xics_icp connect \clk \clk connect \core_irq_o \xics_icp_core_irq_o @@ -374549,7 +373912,7 @@ module \ti connect \rst \rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:198372.12-198385.4" + attribute \src "libresoc.v:197894.12-197907.4" cell \xics_ics \xics_ics connect \clk \clk connect \icp_o_pri \xics_ics_icp_o_pri @@ -374564,1582 +373927,1582 @@ module \ti connect \int_level_i \int_level_i connect \rst \rst end - attribute \src "libresoc.v:195254.7-195254.20" - process $proc$libresoc.v:195254$13784 + attribute \src "libresoc.v:194977.7-194977.20" + process $proc$libresoc.v:194977$13712 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:195522.13-195522.33" - process $proc$libresoc.v:195522$13785 + attribute \src "libresoc.v:195247.13-195247.33" + process $proc$libresoc.v:195247$13713 assign { } { } assign $1\core_asmcode[7:0] 8'00000000 sync always sync init update \core_asmcode $1\core_asmcode[7:0] end - attribute \src "libresoc.v:195528.7-195528.35" - process $proc$libresoc.v:195528$13786 + attribute \src "libresoc.v:195253.7-195253.35" + process $proc$libresoc.v:195253$13714 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13787 1'0 + assign $0\core_bigendian_i$10[0:0]$13715 1'0 sync always sync init - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13787 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13715 end - attribute \src "libresoc.v:195536.14-195536.55" - process $proc$libresoc.v:195536$13788 + attribute \src "libresoc.v:195261.14-195261.55" + process $proc$libresoc.v:195261$13716 assign { } { } assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_cia $1\core_core_core_cia[63:0] end - attribute \src "libresoc.v:195540.13-195540.41" - process $proc$libresoc.v:195540$13789 + attribute \src "libresoc.v:195265.13-195265.41" + process $proc$libresoc.v:195265$13717 assign { } { } assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always sync init update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:195544.7-195544.37" - process $proc$libresoc.v:195544$13790 + attribute \src "libresoc.v:195269.7-195269.37" + process $proc$libresoc.v:195269$13718 assign { } { } assign $1\core_core_core_cr_rd_ok[0:0] 1'0 sync always sync init update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:195548.13-195548.41" - process $proc$libresoc.v:195548$13791 + attribute \src "libresoc.v:195273.13-195273.41" + process $proc$libresoc.v:195273$13719 assign { } { } assign $1\core_core_core_cr_wr[7:0] 8'00000000 sync always sync init update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:195552.7-195552.42" - process $proc$libresoc.v:195552$13792 + attribute \src "libresoc.v:195277.7-195277.42" + process $proc$libresoc.v:195277$13720 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13793 1'0 + assign $0\core_core_core_exc_$signal[0:0]$13721 1'0 sync always sync init - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13793 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13721 end - attribute \src "libresoc.v:195554.7-195554.44" - process $proc$libresoc.v:195554$13794 + attribute \src "libresoc.v:195279.7-195279.44" + process $proc$libresoc.v:195279$13722 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13795 1'0 + assign $0\core_core_core_exc_$signal$3[0:0]$13723 1'0 sync always sync init - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13795 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13723 end - attribute \src "libresoc.v:195558.7-195558.44" - process $proc$libresoc.v:195558$13796 + attribute \src "libresoc.v:195283.7-195283.44" + process $proc$libresoc.v:195283$13724 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13797 1'0 + assign $0\core_core_core_exc_$signal$4[0:0]$13725 1'0 sync always sync init - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13797 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13725 end - attribute \src "libresoc.v:195562.7-195562.44" - process $proc$libresoc.v:195562$13798 + attribute \src "libresoc.v:195287.7-195287.44" + process $proc$libresoc.v:195287$13726 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13799 1'0 + assign $0\core_core_core_exc_$signal$5[0:0]$13727 1'0 sync always sync init - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13799 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13727 end - attribute \src "libresoc.v:195566.7-195566.44" - process $proc$libresoc.v:195566$13800 + attribute \src "libresoc.v:195291.7-195291.44" + process $proc$libresoc.v:195291$13728 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13801 1'0 + assign $0\core_core_core_exc_$signal$6[0:0]$13729 1'0 sync always sync init - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13801 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13729 end - attribute \src "libresoc.v:195570.7-195570.44" - process $proc$libresoc.v:195570$13802 + attribute \src "libresoc.v:195295.7-195295.44" + process $proc$libresoc.v:195295$13730 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13803 1'0 + assign $0\core_core_core_exc_$signal$7[0:0]$13731 1'0 sync always sync init - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13803 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13731 end - attribute \src "libresoc.v:195574.7-195574.44" - process $proc$libresoc.v:195574$13804 + attribute \src "libresoc.v:195299.7-195299.44" + process $proc$libresoc.v:195299$13732 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13805 1'0 + assign $0\core_core_core_exc_$signal$8[0:0]$13733 1'0 sync always sync init - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13805 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13733 end - attribute \src "libresoc.v:195578.7-195578.44" - process $proc$libresoc.v:195578$13806 + attribute \src "libresoc.v:195303.7-195303.44" + process $proc$libresoc.v:195303$13734 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13807 1'0 + assign $0\core_core_core_exc_$signal$9[0:0]$13735 1'0 sync always sync init - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13807 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13735 end - attribute \src "libresoc.v:195599.14-195599.47" - process $proc$libresoc.v:195599$13808 + attribute \src "libresoc.v:195324.14-195324.47" + process $proc$libresoc.v:195324$13736 assign { } { } assign $1\core_core_core_fn_unit[13:0] 14'00000000000000 sync always sync init update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:195607.13-195607.46" - process $proc$libresoc.v:195607$13809 + attribute \src "libresoc.v:195332.13-195332.46" + process $proc$libresoc.v:195332$13737 assign { } { } assign $1\core_core_core_input_carry[1:0] 2'00 sync always sync init update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:195611.14-195611.41" - process $proc$libresoc.v:195611$13810 + attribute \src "libresoc.v:195336.14-195336.41" + process $proc$libresoc.v:195336$13738 assign { } { } assign $1\core_core_core_insn[31:0] 0 sync always sync init update \core_core_core_insn $1\core_core_core_insn[31:0] end - attribute \src "libresoc.v:195690.13-195690.45" - process $proc$libresoc.v:195690$13811 + attribute \src "libresoc.v:195415.13-195415.45" + process $proc$libresoc.v:195415$13739 assign { } { } assign $1\core_core_core_insn_type[6:0] 7'0000000 sync always sync init update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:195694.7-195694.37" - process $proc$libresoc.v:195694$13812 + attribute \src "libresoc.v:195419.7-195419.37" + process $proc$libresoc.v:195419$13740 assign { } { } assign $1\core_core_core_is_32bit[0:0] 1'0 sync always sync init update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:195698.14-195698.55" - process $proc$libresoc.v:195698$13813 + attribute \src "libresoc.v:195423.14-195423.55" + process $proc$libresoc.v:195423$13741 assign { } { } assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_msr $1\core_core_core_msr[63:0] end - attribute \src "libresoc.v:195702.7-195702.31" - process $proc$libresoc.v:195702$13814 + attribute \src "libresoc.v:195427.7-195427.31" + process $proc$libresoc.v:195427$13742 assign { } { } assign $1\core_core_core_oe[0:0] 1'0 sync always sync init update \core_core_core_oe $1\core_core_core_oe[0:0] end - attribute \src "libresoc.v:195706.7-195706.34" - process $proc$libresoc.v:195706$13815 + attribute \src "libresoc.v:195431.7-195431.34" + process $proc$libresoc.v:195431$13743 assign { } { } assign $1\core_core_core_oe_ok[0:0] 1'0 sync always sync init update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:195710.7-195710.31" - process $proc$libresoc.v:195710$13816 + attribute \src "libresoc.v:195435.7-195435.31" + process $proc$libresoc.v:195435$13744 assign { } { } assign $1\core_core_core_rc[0:0] 1'0 sync always sync init update \core_core_core_rc $1\core_core_core_rc[0:0] end - attribute \src "libresoc.v:195714.7-195714.34" - process $proc$libresoc.v:195714$13817 + attribute \src "libresoc.v:195439.7-195439.34" + process $proc$libresoc.v:195439$13745 assign { } { } assign $1\core_core_core_rc_ok[0:0] 1'0 sync always sync init update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:195718.14-195718.48" - process $proc$libresoc.v:195718$13818 + attribute \src "libresoc.v:195443.14-195443.48" + process $proc$libresoc.v:195443$13746 assign { } { } assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 sync always sync init update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:195722.13-195722.44" - process $proc$libresoc.v:195722$13819 + attribute \src "libresoc.v:195447.13-195447.44" + process $proc$libresoc.v:195447$13747 assign { } { } assign $1\core_core_core_traptype[7:0] 8'00000000 sync always sync init update \core_core_core_traptype $1\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:195726.13-195726.37" - process $proc$libresoc.v:195726$13820 + attribute \src "libresoc.v:195451.13-195451.37" + process $proc$libresoc.v:195451$13748 assign { } { } assign $1\core_core_cr_in1[6:0] 7'0000000 sync always sync init update \core_core_cr_in1 $1\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:195730.7-195730.33" - process $proc$libresoc.v:195730$13821 + attribute \src "libresoc.v:195455.7-195455.33" + process $proc$libresoc.v:195455$13749 assign { } { } assign $1\core_core_cr_in1_ok[0:0] 1'0 sync always sync init update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:195734.13-195734.37" - process $proc$libresoc.v:195734$13822 + attribute \src "libresoc.v:195459.13-195459.37" + process $proc$libresoc.v:195459$13750 assign { } { } assign $1\core_core_cr_in2[6:0] 7'0000000 sync always sync init update \core_core_cr_in2 $1\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:195736.13-195736.41" - process $proc$libresoc.v:195736$13823 + attribute \src "libresoc.v:195461.13-195461.41" + process $proc$libresoc.v:195461$13751 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$13824 7'0000000 + assign $0\core_core_cr_in2$1[6:0]$13752 7'0000000 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13824 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13752 end - attribute \src "libresoc.v:195742.7-195742.33" - process $proc$libresoc.v:195742$13825 + attribute \src "libresoc.v:195467.7-195467.33" + process $proc$libresoc.v:195467$13753 assign { } { } assign $1\core_core_cr_in2_ok[0:0] 1'0 sync always sync init update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:195744.7-195744.37" - process $proc$libresoc.v:195744$13826 + attribute \src "libresoc.v:195469.7-195469.37" + process $proc$libresoc.v:195469$13754 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13827 1'0 + assign $0\core_core_cr_in2_ok$2[0:0]$13755 1'0 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13827 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13755 end - attribute \src "libresoc.v:195750.13-195750.37" - process $proc$libresoc.v:195750$13828 + attribute \src "libresoc.v:195475.13-195475.37" + process $proc$libresoc.v:195475$13756 assign { } { } assign $1\core_core_cr_out[6:0] 7'0000000 sync always sync init update \core_core_cr_out $1\core_core_cr_out[6:0] end - attribute \src "libresoc.v:195754.7-195754.32" - process $proc$libresoc.v:195754$13829 + attribute \src "libresoc.v:195479.7-195479.32" + process $proc$libresoc.v:195479$13757 assign { } { } assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:195758.13-195758.38" - process $proc$libresoc.v:195758$13830 + attribute \src "libresoc.v:195483.13-195483.38" + process $proc$libresoc.v:195483$13758 assign { } { } assign $1\core_core_dststep[6:0] 7'0000000 sync always sync init update \core_core_dststep $1\core_core_dststep[6:0] end - attribute \src "libresoc.v:195762.13-195762.33" - process $proc$libresoc.v:195762$13831 + attribute \src "libresoc.v:195487.13-195487.33" + process $proc$libresoc.v:195487$13759 assign { } { } assign $1\core_core_ea[6:0] 7'0000000 sync always sync init update \core_core_ea $1\core_core_ea[6:0] end - attribute \src "libresoc.v:195766.13-195766.35" - process $proc$libresoc.v:195766$13832 + attribute \src "libresoc.v:195491.13-195491.35" + process $proc$libresoc.v:195491$13760 assign { } { } assign $1\core_core_fast1[2:0] 3'000 sync always sync init update \core_core_fast1 $1\core_core_fast1[2:0] end - attribute \src "libresoc.v:195770.7-195770.32" - process $proc$libresoc.v:195770$13833 + attribute \src "libresoc.v:195495.7-195495.32" + process $proc$libresoc.v:195495$13761 assign { } { } assign $1\core_core_fast1_ok[0:0] 1'0 sync always sync init update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:195774.13-195774.35" - process $proc$libresoc.v:195774$13834 + attribute \src "libresoc.v:195499.13-195499.35" + process $proc$libresoc.v:195499$13762 assign { } { } assign $1\core_core_fast2[2:0] 3'000 sync always sync init update \core_core_fast2 $1\core_core_fast2[2:0] end - attribute \src "libresoc.v:195778.7-195778.32" - process $proc$libresoc.v:195778$13835 + attribute \src "libresoc.v:195503.7-195503.32" + process $proc$libresoc.v:195503$13763 assign { } { } assign $1\core_core_fast2_ok[0:0] 1'0 sync always sync init update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:195782.13-195782.36" - process $proc$libresoc.v:195782$13836 + attribute \src "libresoc.v:195507.13-195507.36" + process $proc$libresoc.v:195507$13764 assign { } { } assign $1\core_core_fasto1[2:0] 3'000 sync always sync init update \core_core_fasto1 $1\core_core_fasto1[2:0] end - attribute \src "libresoc.v:195786.13-195786.36" - process $proc$libresoc.v:195786$13837 + attribute \src "libresoc.v:195511.13-195511.36" + process $proc$libresoc.v:195511$13765 assign { } { } assign $1\core_core_fasto2[2:0] 3'000 sync always sync init update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "libresoc.v:195790.7-195790.26" - process $proc$libresoc.v:195790$13838 + attribute \src "libresoc.v:195515.7-195515.26" + process $proc$libresoc.v:195515$13766 assign { } { } assign $1\core_core_lk[0:0] 1'0 sync always sync init update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "libresoc.v:195794.13-195794.36" - process $proc$libresoc.v:195794$13839 + attribute \src "libresoc.v:195519.13-195519.36" + process $proc$libresoc.v:195519$13767 assign { } { } assign $1\core_core_maxvl[6:0] 7'0000000 sync always sync init update \core_core_maxvl $1\core_core_maxvl[6:0] end - attribute \src "libresoc.v:195798.14-195798.49" - process $proc$libresoc.v:195798$13840 + attribute \src "libresoc.v:195523.14-195523.49" + process $proc$libresoc.v:195523$13768 assign { } { } assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_pc $1\core_core_pc[63:0] end - attribute \src "libresoc.v:195802.13-195802.35" - process $proc$libresoc.v:195802$13841 + attribute \src "libresoc.v:195527.13-195527.35" + process $proc$libresoc.v:195527$13769 assign { } { } assign $1\core_core_reg1[6:0] 7'0000000 sync always sync init update \core_core_reg1 $1\core_core_reg1[6:0] end - attribute \src "libresoc.v:195806.7-195806.31" - process $proc$libresoc.v:195806$13842 + attribute \src "libresoc.v:195531.7-195531.31" + process $proc$libresoc.v:195531$13770 assign { } { } assign $1\core_core_reg1_ok[0:0] 1'0 sync always sync init update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:195810.13-195810.35" - process $proc$libresoc.v:195810$13843 + attribute \src "libresoc.v:195535.13-195535.35" + process $proc$libresoc.v:195535$13771 assign { } { } assign $1\core_core_reg2[6:0] 7'0000000 sync always sync init update \core_core_reg2 $1\core_core_reg2[6:0] end - attribute \src "libresoc.v:195814.7-195814.31" - process $proc$libresoc.v:195814$13844 + attribute \src "libresoc.v:195539.7-195539.31" + process $proc$libresoc.v:195539$13772 assign { } { } assign $1\core_core_reg2_ok[0:0] 1'0 sync always sync init update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:195818.13-195818.35" - process $proc$libresoc.v:195818$13845 + attribute \src "libresoc.v:195543.13-195543.35" + process $proc$libresoc.v:195543$13773 assign { } { } assign $1\core_core_reg3[6:0] 7'0000000 sync always sync init update \core_core_reg3 $1\core_core_reg3[6:0] end - attribute \src "libresoc.v:195822.7-195822.31" - process $proc$libresoc.v:195822$13846 + attribute \src "libresoc.v:195547.7-195547.31" + process $proc$libresoc.v:195547$13774 assign { } { } assign $1\core_core_reg3_ok[0:0] 1'0 sync always sync init update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:195826.13-195826.35" - process $proc$libresoc.v:195826$13847 + attribute \src "libresoc.v:195551.13-195551.35" + process $proc$libresoc.v:195551$13775 assign { } { } assign $1\core_core_rego[6:0] 7'0000000 sync always sync init update \core_core_rego $1\core_core_rego[6:0] end - attribute \src "libresoc.v:195944.13-195944.37" - process $proc$libresoc.v:195944$13848 + attribute \src "libresoc.v:195567.13-195567.37" + process $proc$libresoc.v:195567$13776 assign { } { } assign $1\core_core_spr1[9:0] 10'0000000000 sync always sync init update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "libresoc.v:195948.7-195948.31" - process $proc$libresoc.v:195948$13849 + attribute \src "libresoc.v:195571.7-195571.31" + process $proc$libresoc.v:195571$13777 assign { } { } assign $1\core_core_spr1_ok[0:0] 1'0 sync always sync init update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:196066.13-196066.37" - process $proc$libresoc.v:196066$13850 + attribute \src "libresoc.v:195587.13-195587.37" + process $proc$libresoc.v:195587$13778 assign { } { } assign $1\core_core_spro[9:0] 10'0000000000 sync always sync init update \core_core_spro $1\core_core_spro[9:0] end - attribute \src "libresoc.v:196070.13-196070.38" - process $proc$libresoc.v:196070$13851 + attribute \src "libresoc.v:195591.13-195591.38" + process $proc$libresoc.v:195591$13779 assign { } { } assign $1\core_core_srcstep[6:0] 7'0000000 sync always sync init update \core_core_srcstep $1\core_core_srcstep[6:0] end - attribute \src "libresoc.v:196074.13-196074.35" - process $proc$libresoc.v:196074$13852 + attribute \src "libresoc.v:195595.13-195595.35" + process $proc$libresoc.v:195595$13780 assign { } { } assign $1\core_core_subvl[1:0] 2'00 sync always sync init update \core_core_subvl $1\core_core_subvl[1:0] end - attribute \src "libresoc.v:196078.13-196078.36" - process $proc$libresoc.v:196078$13853 + attribute \src "libresoc.v:195599.13-195599.36" + process $proc$libresoc.v:195599$13781 assign { } { } assign $1\core_core_svstep[1:0] 2'00 sync always sync init update \core_core_svstep $1\core_core_svstep[1:0] end - attribute \src "libresoc.v:196084.13-196084.33" - process $proc$libresoc.v:196084$13854 + attribute \src "libresoc.v:195605.13-195605.33" + process $proc$libresoc.v:195605$13782 assign { } { } assign $1\core_core_vl[6:0] 7'0000000 sync always sync init update \core_core_vl $1\core_core_vl[6:0] end - attribute \src "libresoc.v:196088.13-196088.36" - process $proc$libresoc.v:196088$13855 + attribute \src "libresoc.v:195609.13-195609.36" + process $proc$libresoc.v:195609$13783 assign { } { } assign $1\core_core_xer_in[2:0] 3'000 sync always sync init update \core_core_xer_in $1\core_core_xer_in[2:0] end - attribute \src "libresoc.v:196096.7-196096.28" - process $proc$libresoc.v:196096$13856 + attribute \src "libresoc.v:195617.7-195617.28" + process $proc$libresoc.v:195617$13784 assign { } { } assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:196112.14-196112.45" - process $proc$libresoc.v:196112$13857 + attribute \src "libresoc.v:195633.14-195633.45" + process $proc$libresoc.v:195633$13785 assign { } { } assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_dec $1\core_dec[63:0] end - attribute \src "libresoc.v:196122.7-196122.24" - process $proc$libresoc.v:196122$13858 + attribute \src "libresoc.v:195643.7-195643.24" + process $proc$libresoc.v:195643$13786 assign { } { } assign $1\core_ea_ok[0:0] 1'0 sync always sync init update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "libresoc.v:196126.7-196126.23" - process $proc$libresoc.v:196126$13859 + attribute \src "libresoc.v:195647.7-195647.23" + process $proc$libresoc.v:195647$13787 assign { } { } assign $1\core_eint[0:0] 1'0 sync always sync init update \core_eint $1\core_eint[0:0] end - attribute \src "libresoc.v:196130.7-196130.28" - process $proc$libresoc.v:196130$13860 + attribute \src "libresoc.v:195651.7-195651.28" + process $proc$libresoc.v:195651$13788 assign { } { } assign $1\core_fasto1_ok[0:0] 1'0 sync always sync init update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:196134.7-196134.28" - process $proc$libresoc.v:196134$13861 + attribute \src "libresoc.v:195655.7-195655.28" + process $proc$libresoc.v:195655$13789 assign { } { } assign $1\core_fasto2_ok[0:0] 1'0 sync always sync init update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:196162.14-196162.45" - process $proc$libresoc.v:196162$13862 + attribute \src "libresoc.v:195683.14-195683.45" + process $proc$libresoc.v:195683$13790 assign { } { } assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:196170.14-196170.37" - process $proc$libresoc.v:196170$13863 + attribute \src "libresoc.v:195691.14-195691.37" + process $proc$libresoc.v:195691$13791 assign { } { } assign $1\core_raw_insn_i[31:0] 0 sync always sync init update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:196174.7-196174.26" - process $proc$libresoc.v:196174$13864 + attribute \src "libresoc.v:195695.7-195695.26" + process $proc$libresoc.v:195695$13792 assign { } { } assign $1\core_rego_ok[0:0] 1'0 sync always sync init update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "libresoc.v:196178.7-196178.26" - process $proc$libresoc.v:196178$13865 + attribute \src "libresoc.v:195699.7-195699.26" + process $proc$libresoc.v:195699$13793 assign { } { } assign $1\core_spro_ok[0:0] 1'0 sync always sync init update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "libresoc.v:196190.7-196190.26" - process $proc$libresoc.v:196190$13866 + attribute \src "libresoc.v:195711.7-195711.26" + process $proc$libresoc.v:195711$13794 assign { } { } assign $1\core_sv_a_nz[0:0] 1'0 sync always sync init update \core_sv_a_nz $1\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:196200.7-196200.26" - process $proc$libresoc.v:196200$13867 + attribute \src "libresoc.v:195721.7-195721.26" + process $proc$libresoc.v:195721$13795 assign { } { } assign $1\core_xer_out[0:0] 1'0 sync always sync init update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:196206.7-196206.30" - process $proc$libresoc.v:196206$13868 + attribute \src "libresoc.v:195727.7-195727.30" + process $proc$libresoc.v:195727$13796 assign { } { } assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:196212.13-196212.36" - process $proc$libresoc.v:196212$13869 + attribute \src "libresoc.v:195733.13-195733.36" + process $proc$libresoc.v:195733$13797 assign { } { } assign $1\cur_cur_dststep[6:0] 7'0000000 sync always sync init update \cur_cur_dststep $1\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:196216.13-196216.34" - process $proc$libresoc.v:196216$13870 + attribute \src "libresoc.v:195737.13-195737.34" + process $proc$libresoc.v:195737$13798 assign { } { } assign $1\cur_cur_maxvl[6:0] 7'0000000 sync always sync init update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:196220.13-196220.36" - process $proc$libresoc.v:196220$13871 + attribute \src "libresoc.v:195741.13-195741.36" + process $proc$libresoc.v:195741$13799 assign { } { } assign $1\cur_cur_srcstep[6:0] 7'0000000 sync always sync init update \cur_cur_srcstep $1\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:196224.13-196224.33" - process $proc$libresoc.v:196224$13872 + attribute \src "libresoc.v:195745.13-195745.33" + process $proc$libresoc.v:195745$13800 assign { } { } assign $1\cur_cur_subvl[1:0] 2'00 sync always sync init update \cur_cur_subvl $1\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:196228.13-196228.34" - process $proc$libresoc.v:196228$13873 + attribute \src "libresoc.v:195749.13-195749.34" + process $proc$libresoc.v:195749$13801 assign { } { } assign $1\cur_cur_svstep[1:0] 2'00 sync always sync init update \cur_cur_svstep $1\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:196232.13-196232.31" - process $proc$libresoc.v:196232$13874 + attribute \src "libresoc.v:195753.13-195753.31" + process $proc$libresoc.v:195753$13802 assign { } { } assign $1\cur_cur_vl[6:0] 7'0000000 sync always sync init update \cur_cur_vl $1\cur_cur_vl[6:0] end - attribute \src "libresoc.v:196236.7-196236.24" - process $proc$libresoc.v:196236$13875 + attribute \src "libresoc.v:195757.7-195757.24" + process $proc$libresoc.v:195757$13803 assign { } { } assign $1\d_cr_delay[0:0] 1'0 sync always sync init update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "libresoc.v:196240.7-196240.25" - process $proc$libresoc.v:196240$13876 + attribute \src "libresoc.v:195761.7-195761.25" + process $proc$libresoc.v:195761$13804 assign { } { } assign $1\d_reg_delay[0:0] 1'0 sync always sync init update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:196244.7-196244.25" - process $proc$libresoc.v:196244$13877 + attribute \src "libresoc.v:195765.7-195765.25" + process $proc$libresoc.v:195765$13805 assign { } { } assign $1\d_xer_delay[0:0] 1'0 sync always sync init update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "libresoc.v:196292.13-196292.34" - process $proc$libresoc.v:196292$13878 + attribute \src "libresoc.v:195813.13-195813.34" + process $proc$libresoc.v:195813$13806 assign { } { } assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:196296.14-196296.48" - process $proc$libresoc.v:196296$13879 + attribute \src "libresoc.v:195817.14-195817.48" + process $proc$libresoc.v:195817$13807 assign { } { } assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:196302.7-196302.27" - process $proc$libresoc.v:196302$13880 + attribute \src "libresoc.v:195823.7-195823.27" + process $proc$libresoc.v:195823$13808 assign { } { } assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:196306.7-196306.26" - process $proc$libresoc.v:196306$13881 + attribute \src "libresoc.v:195827.7-195827.26" + process $proc$libresoc.v:195827$13809 assign { } { } assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:196360.14-196360.49" - process $proc$libresoc.v:196360$13882 + attribute \src "libresoc.v:195881.14-195881.49" + process $proc$libresoc.v:195881$13810 assign { } { } assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:196364.7-196364.27" - process $proc$libresoc.v:196364$13883 + attribute \src "libresoc.v:195885.7-195885.27" + process $proc$libresoc.v:195885$13811 assign { } { } assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:196368.14-196368.49" - process $proc$libresoc.v:196368$13884 + attribute \src "libresoc.v:195889.14-195889.49" + process $proc$libresoc.v:195889$13812 assign { } { } assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:196372.14-196372.48" - process $proc$libresoc.v:196372$13885 + attribute \src "libresoc.v:195893.14-195893.48" + process $proc$libresoc.v:195893$13813 assign { } { } assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:196524.14-196524.40" - process $proc$libresoc.v:196524$13886 + attribute \src "libresoc.v:196045.14-196045.40" + process $proc$libresoc.v:196045$13814 assign { } { } assign $1\dec2_raw_opcode_in[31:0] 0 sync always sync init update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:196794.13-196794.25" - process $proc$libresoc.v:196794$13887 + attribute \src "libresoc.v:196315.13-196315.25" + process $proc$libresoc.v:196315$13815 assign { } { } assign $1\delay[1:0] 2'11 sync always sync init update \delay $1\delay[1:0] end - attribute \src "libresoc.v:196810.7-196810.28" - process $proc$libresoc.v:196810$13888 + attribute \src "libresoc.v:196331.7-196331.28" + process $proc$libresoc.v:196331$13816 assign { } { } assign $1\exec_fsm_state[0:0] 1'0 sync always sync init update \exec_fsm_state $1\exec_fsm_state[0:0] end - attribute \src "libresoc.v:196822.13-196822.35" - process $proc$libresoc.v:196822$13889 + attribute \src "libresoc.v:196343.13-196343.35" + process $proc$libresoc.v:196343$13817 assign { } { } assign $1\fetch_fsm_state[1:0] 2'00 sync always sync init update \fetch_fsm_state $1\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:196834.13-196834.29" - process $proc$libresoc.v:196834$13890 + attribute \src "libresoc.v:196355.13-196355.29" + process $proc$libresoc.v:196355$13818 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:197094.13-197094.35" - process $proc$libresoc.v:197094$13891 + attribute \src "libresoc.v:196615.13-196615.35" + process $proc$libresoc.v:196615$13819 assign { } { } assign $1\issue_fsm_state[2:0] 3'000 sync always sync init update \issue_fsm_state $1\issue_fsm_state[2:0] end - attribute \src "libresoc.v:197098.7-197098.30" - process $proc$libresoc.v:197098$13892 + attribute \src "libresoc.v:196619.7-196619.30" + process $proc$libresoc.v:196619$13820 assign { } { } assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:197106.14-197106.52" - process $proc$libresoc.v:197106$13893 + attribute \src "libresoc.v:196627.14-196627.52" + process $proc$libresoc.v:196627$13821 assign { } { } assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:197146.7-197146.22" - process $proc$libresoc.v:197146$13894 + attribute \src "libresoc.v:196667.7-196667.22" + process $proc$libresoc.v:196667$13822 assign { } { } assign $1\msr_read[0:0] 1'1 sync always sync init update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:197186.14-197186.40" - process $proc$libresoc.v:197186$13895 + attribute \src "libresoc.v:196707.14-196707.40" + process $proc$libresoc.v:196707$13823 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:197192.7-197192.24" - process $proc$libresoc.v:197192$13896 + attribute \src "libresoc.v:196713.7-196713.24" + process $proc$libresoc.v:196713$13824 assign { } { } assign $1\pc_changed[0:0] 1'0 sync always sync init update \pc_changed $1\pc_changed[0:0] end - attribute \src "libresoc.v:197202.7-197202.25" - process $proc$libresoc.v:197202$13897 + attribute \src "libresoc.v:196723.7-196723.25" + process $proc$libresoc.v:196723$13825 assign { } { } assign $1\pc_ok_delay[0:0] 1'0 sync always sync init update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "libresoc.v:197502.7-197502.24" - process $proc$libresoc.v:197502$13898 + attribute \src "libresoc.v:197023.7-197023.24" + process $proc$libresoc.v:197023$13826 assign { } { } assign $1\sv_changed[0:0] 1'0 sync always sync init update \sv_changed $1\sv_changed[0:0] end - attribute \src "libresoc.v:197512.7-197512.30" - process $proc$libresoc.v:197512$13899 + attribute \src "libresoc.v:197033.7-197033.30" + process $proc$libresoc.v:197033$13827 assign { } { } assign $1\svstate_ok_delay[0:0] 1'0 sync always sync init update \svstate_ok_delay $1\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:197649.3-197650.41" - process $proc$libresoc.v:197649$13201 + attribute \src "libresoc.v:197171.3-197172.41" + process $proc$libresoc.v:197171$13200 assign { } { } assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next sync posedge \clk update \dec2_cur_dec $0\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:197651.3-197652.41" - process $proc$libresoc.v:197651$13202 + attribute \src "libresoc.v:197173.3-197174.41" + process $proc$libresoc.v:197173$13201 assign { } { } assign $0\core_core_pc[63:0] \core_core_pc$next sync posedge \clk update \core_core_pc $0\core_core_pc[63:0] end - attribute \src "libresoc.v:197653.3-197654.49" - process $proc$libresoc.v:197653$13203 + attribute \src "libresoc.v:197175.3-197176.49" + process $proc$libresoc.v:197175$13202 assign { } { } assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next sync posedge \clk update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:197655.3-197656.39" - process $proc$libresoc.v:197655$13204 + attribute \src "libresoc.v:197177.3-197178.39" + process $proc$libresoc.v:197177$13203 assign { } { } assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next sync posedge \clk update \dbg_dmi_din $0\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:197657.3-197658.41" - process $proc$libresoc.v:197657$13205 + attribute \src "libresoc.v:197179.3-197180.41" + process $proc$libresoc.v:197179$13204 assign { } { } assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next sync posedge \clk update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:197659.3-197660.43" - process $proc$libresoc.v:197659$13206 + attribute \src "libresoc.v:197181.3-197182.43" + process $proc$libresoc.v:197181$13205 assign { } { } assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next sync posedge \clk update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:197661.3-197662.45" - process $proc$libresoc.v:197661$13207 + attribute \src "libresoc.v:197183.3-197184.45" + process $proc$libresoc.v:197183$13206 assign { } { } assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next sync posedge \clk update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:197663.3-197664.33" - process $proc$libresoc.v:197663$13208 + attribute \src "libresoc.v:197185.3-197186.33" + process $proc$libresoc.v:197185$13207 assign { } { } assign $0\core_msr[63:0] \core_msr$next sync posedge \clk update \core_msr $0\core_msr[63:0] end - attribute \src "libresoc.v:197665.3-197666.35" - process $proc$libresoc.v:197665$13209 + attribute \src "libresoc.v:197187.3-197188.35" + process $proc$libresoc.v:197187$13208 assign { } { } assign $0\core_eint[0:0] \core_eint$next sync posedge \clk update \core_eint $0\core_eint[0:0] end - attribute \src "libresoc.v:197667.3-197668.33" - process $proc$libresoc.v:197667$13210 + attribute \src "libresoc.v:197189.3-197190.33" + process $proc$libresoc.v:197189$13209 assign { } { } assign $0\core_dec[63:0] \core_dec$next sync posedge \clk update \core_dec $0\core_dec[63:0] end - attribute \src "libresoc.v:197669.3-197670.49" - process $proc$libresoc.v:197669$13211 + attribute \src "libresoc.v:197191.3-197192.49" + process $proc$libresoc.v:197191$13210 assign { } { } assign $0\core_core_svstep[1:0] \core_core_svstep$next sync posedge \clk update \core_core_svstep $0\core_core_svstep[1:0] end - attribute \src "libresoc.v:197671.3-197672.47" - process $proc$libresoc.v:197671$13212 + attribute \src "libresoc.v:197193.3-197194.47" + process $proc$libresoc.v:197193$13211 assign { } { } assign $0\core_core_subvl[1:0] \core_core_subvl$next sync posedge \clk update \core_core_subvl $0\core_core_subvl[1:0] end - attribute \src "libresoc.v:197673.3-197674.51" - process $proc$libresoc.v:197673$13213 + attribute \src "libresoc.v:197195.3-197196.51" + process $proc$libresoc.v:197195$13212 assign { } { } assign $0\core_core_dststep[6:0] \core_core_dststep$next sync posedge \clk update \core_core_dststep $0\core_core_dststep[6:0] end - attribute \src "libresoc.v:197675.3-197676.51" - process $proc$libresoc.v:197675$13214 + attribute \src "libresoc.v:197197.3-197198.51" + process $proc$libresoc.v:197197$13213 assign { } { } assign $0\core_core_srcstep[6:0] \core_core_srcstep$next sync posedge \clk update \core_core_srcstep $0\core_core_srcstep[6:0] end - attribute \src "libresoc.v:197677.3-197678.41" - process $proc$libresoc.v:197677$13215 + attribute \src "libresoc.v:197199.3-197200.41" + process $proc$libresoc.v:197199$13214 assign { } { } assign $0\core_core_vl[6:0] \core_core_vl$next sync posedge \clk update \core_core_vl $0\core_core_vl[6:0] end - attribute \src "libresoc.v:197679.3-197680.47" - process $proc$libresoc.v:197679$13216 + attribute \src "libresoc.v:197201.3-197202.47" + process $proc$libresoc.v:197201$13215 assign { } { } assign $0\core_core_maxvl[6:0] \core_core_maxvl$next sync posedge \clk update \core_core_maxvl $0\core_core_maxvl[6:0] end - attribute \src "libresoc.v:197681.3-197682.35" - process $proc$libresoc.v:197681$13217 + attribute \src "libresoc.v:197203.3-197204.35" + process $proc$libresoc.v:197203$13216 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:197683.3-197684.41" - process $proc$libresoc.v:197683$13218 + attribute \src "libresoc.v:197205.3-197206.41" + process $proc$libresoc.v:197205$13217 assign { } { } assign $0\core_asmcode[7:0] \core_asmcode$next sync posedge \clk update \core_asmcode $0\core_asmcode[7:0] end - attribute \src "libresoc.v:197685.3-197686.45" - process $proc$libresoc.v:197685$13219 + attribute \src "libresoc.v:197207.3-197208.45" + process $proc$libresoc.v:197207$13218 assign { } { } assign $0\core_core_rego[6:0] \core_core_rego$next sync posedge \clk update \core_core_rego $0\core_core_rego[6:0] end - attribute \src "libresoc.v:197687.3-197688.41" - process $proc$libresoc.v:197687$13220 + attribute \src "libresoc.v:197209.3-197210.41" + process $proc$libresoc.v:197209$13219 assign { } { } assign $0\core_rego_ok[0:0] \core_rego_ok$next sync posedge \clk update \core_rego_ok $0\core_rego_ok[0:0] end - attribute \src "libresoc.v:197689.3-197690.41" - process $proc$libresoc.v:197689$13221 + attribute \src "libresoc.v:197211.3-197212.41" + process $proc$libresoc.v:197211$13220 assign { } { } assign $0\core_core_ea[6:0] \core_core_ea$next sync posedge \clk update \core_core_ea $0\core_core_ea[6:0] end - attribute \src "libresoc.v:197691.3-197692.37" - process $proc$libresoc.v:197691$13222 + attribute \src "libresoc.v:197213.3-197214.37" + process $proc$libresoc.v:197213$13221 assign { } { } assign $0\core_ea_ok[0:0] \core_ea_ok$next sync posedge \clk update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "libresoc.v:197693.3-197694.45" - process $proc$libresoc.v:197693$13223 + attribute \src "libresoc.v:197215.3-197216.45" + process $proc$libresoc.v:197215$13222 assign { } { } assign $0\core_core_reg1[6:0] \core_core_reg1$next sync posedge \clk update \core_core_reg1 $0\core_core_reg1[6:0] end - attribute \src "libresoc.v:197695.3-197696.51" - process $proc$libresoc.v:197695$13224 + attribute \src "libresoc.v:197217.3-197218.51" + process $proc$libresoc.v:197217$13223 assign { } { } assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next sync posedge \clk update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:197697.3-197698.45" - process $proc$libresoc.v:197697$13225 + attribute \src "libresoc.v:197219.3-197220.45" + process $proc$libresoc.v:197219$13224 assign { } { } assign $0\core_core_reg2[6:0] \core_core_reg2$next sync posedge \clk update \core_core_reg2 $0\core_core_reg2[6:0] end - attribute \src "libresoc.v:197699.3-197700.51" - process $proc$libresoc.v:197699$13226 + attribute \src "libresoc.v:197221.3-197222.51" + process $proc$libresoc.v:197221$13225 assign { } { } assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next sync posedge \clk update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:197701.3-197702.45" - process $proc$libresoc.v:197701$13227 + attribute \src "libresoc.v:197223.3-197224.45" + process $proc$libresoc.v:197223$13226 assign { } { } assign $0\core_core_reg3[6:0] \core_core_reg3$next sync posedge \clk update \core_core_reg3 $0\core_core_reg3[6:0] end - attribute \src "libresoc.v:197703.3-197704.39" - process $proc$libresoc.v:197703$13228 + attribute \src "libresoc.v:197225.3-197226.39" + process $proc$libresoc.v:197225$13227 assign { } { } assign $0\d_xer_delay[0:0] \d_xer_delay$next sync posedge \clk update \d_xer_delay $0\d_xer_delay[0:0] end - attribute \src "libresoc.v:197705.3-197706.51" - process $proc$libresoc.v:197705$13229 + attribute \src "libresoc.v:197227.3-197228.51" + process $proc$libresoc.v:197227$13228 assign { } { } assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next sync posedge \clk update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:197707.3-197708.45" - process $proc$libresoc.v:197707$13230 + attribute \src "libresoc.v:197229.3-197230.45" + process $proc$libresoc.v:197229$13229 assign { } { } assign $0\core_core_spro[9:0] \core_core_spro$next sync posedge \clk update \core_core_spro $0\core_core_spro[9:0] end - attribute \src "libresoc.v:197709.3-197710.41" - process $proc$libresoc.v:197709$13231 + attribute \src "libresoc.v:197231.3-197232.41" + process $proc$libresoc.v:197231$13230 assign { } { } assign $0\core_spro_ok[0:0] \core_spro_ok$next sync posedge \clk update \core_spro_ok $0\core_spro_ok[0:0] end - attribute \src "libresoc.v:197711.3-197712.45" - process $proc$libresoc.v:197711$13232 + attribute \src "libresoc.v:197233.3-197234.45" + process $proc$libresoc.v:197233$13231 assign { } { } assign $0\core_core_spr1[9:0] \core_core_spr1$next sync posedge \clk update \core_core_spr1 $0\core_core_spr1[9:0] end - attribute \src "libresoc.v:197713.3-197714.51" - process $proc$libresoc.v:197713$13233 + attribute \src "libresoc.v:197235.3-197236.51" + process $proc$libresoc.v:197235$13232 assign { } { } assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next sync posedge \clk update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:197715.3-197716.49" - process $proc$libresoc.v:197715$13234 + attribute \src "libresoc.v:197237.3-197238.49" + process $proc$libresoc.v:197237$13233 assign { } { } assign $0\core_core_xer_in[2:0] \core_core_xer_in$next sync posedge \clk update \core_core_xer_in $0\core_core_xer_in[2:0] end - attribute \src "libresoc.v:197717.3-197718.41" - process $proc$libresoc.v:197717$13235 + attribute \src "libresoc.v:197239.3-197240.41" + process $proc$libresoc.v:197239$13234 assign { } { } assign $0\core_xer_out[0:0] \core_xer_out$next sync posedge \clk update \core_xer_out $0\core_xer_out[0:0] end - attribute \src "libresoc.v:197719.3-197720.47" - process $proc$libresoc.v:197719$13236 + attribute \src "libresoc.v:197241.3-197242.47" + process $proc$libresoc.v:197241$13235 assign { } { } assign $0\core_core_fast1[2:0] \core_core_fast1$next sync posedge \clk update \core_core_fast1 $0\core_core_fast1[2:0] end - attribute \src "libresoc.v:197721.3-197722.53" - process $proc$libresoc.v:197721$13237 + attribute \src "libresoc.v:197243.3-197244.53" + process $proc$libresoc.v:197243$13236 assign { } { } assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next sync posedge \clk update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:197723.3-197724.47" - process $proc$libresoc.v:197723$13238 + attribute \src "libresoc.v:197245.3-197246.47" + process $proc$libresoc.v:197245$13237 assign { } { } assign $0\core_core_fast2[2:0] \core_core_fast2$next sync posedge \clk update \core_core_fast2 $0\core_core_fast2[2:0] end - attribute \src "libresoc.v:197725.3-197726.37" - process $proc$libresoc.v:197725$13239 + attribute \src "libresoc.v:197247.3-197248.37" + process $proc$libresoc.v:197247$13238 assign { } { } assign $0\d_cr_delay[0:0] \d_cr_delay$next sync posedge \clk update \d_cr_delay $0\d_cr_delay[0:0] end - attribute \src "libresoc.v:197727.3-197728.53" - process $proc$libresoc.v:197727$13240 + attribute \src "libresoc.v:197249.3-197250.53" + process $proc$libresoc.v:197249$13239 assign { } { } assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next sync posedge \clk update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:197729.3-197730.49" - process $proc$libresoc.v:197729$13241 + attribute \src "libresoc.v:197251.3-197252.49" + process $proc$libresoc.v:197251$13240 assign { } { } assign $0\core_core_fasto1[2:0] \core_core_fasto1$next sync posedge \clk update \core_core_fasto1 $0\core_core_fasto1[2:0] end - attribute \src "libresoc.v:197731.3-197732.45" - process $proc$libresoc.v:197731$13242 + attribute \src "libresoc.v:197253.3-197254.45" + process $proc$libresoc.v:197253$13241 assign { } { } assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next sync posedge \clk update \core_fasto1_ok $0\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:197733.3-197734.49" - process $proc$libresoc.v:197733$13243 + attribute \src "libresoc.v:197255.3-197256.49" + process $proc$libresoc.v:197255$13242 assign { } { } assign $0\core_core_fasto2[2:0] \core_core_fasto2$next sync posedge \clk update \core_core_fasto2 $0\core_core_fasto2[2:0] end - attribute \src "libresoc.v:197735.3-197736.45" - process $proc$libresoc.v:197735$13244 + attribute \src "libresoc.v:197257.3-197258.45" + process $proc$libresoc.v:197257$13243 assign { } { } assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next sync posedge \clk update \core_fasto2_ok $0\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:197737.3-197738.49" - process $proc$libresoc.v:197737$13245 + attribute \src "libresoc.v:197259.3-197260.49" + process $proc$libresoc.v:197259$13244 assign { } { } assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next sync posedge \clk update \core_core_cr_in1 $0\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:197739.3-197740.55" - process $proc$libresoc.v:197739$13246 + attribute \src "libresoc.v:197261.3-197262.55" + process $proc$libresoc.v:197261$13245 assign { } { } assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next sync posedge \clk update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:197741.3-197742.49" - process $proc$libresoc.v:197741$13247 + attribute \src "libresoc.v:197263.3-197264.49" + process $proc$libresoc.v:197263$13246 assign { } { } assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next sync posedge \clk update \core_core_cr_in2 $0\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:197743.3-197744.55" - process $proc$libresoc.v:197743$13248 + attribute \src "libresoc.v:197265.3-197266.55" + process $proc$libresoc.v:197265$13247 assign { } { } assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next sync posedge \clk update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:197745.3-197746.55" - process $proc$libresoc.v:197745$13249 + attribute \src "libresoc.v:197267.3-197268.55" + process $proc$libresoc.v:197267$13248 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$13250 \core_core_cr_in2$1$next + assign $0\core_core_cr_in2$1[6:0]$13249 \core_core_cr_in2$1$next sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13250 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13249 end - attribute \src "libresoc.v:197747.3-197748.39" - process $proc$libresoc.v:197747$13251 + attribute \src "libresoc.v:197269.3-197270.39" + process $proc$libresoc.v:197269$13250 assign { } { } assign $0\d_reg_delay[0:0] \d_reg_delay$next sync posedge \clk update \d_reg_delay $0\d_reg_delay[0:0] end - attribute \src "libresoc.v:197749.3-197750.61" - process $proc$libresoc.v:197749$13252 + attribute \src "libresoc.v:197271.3-197272.61" + process $proc$libresoc.v:197271$13251 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13253 \core_core_cr_in2_ok$2$next + assign $0\core_core_cr_in2_ok$2[0:0]$13252 \core_core_cr_in2_ok$2$next sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13253 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13252 end - attribute \src "libresoc.v:197751.3-197752.49" - process $proc$libresoc.v:197751$13254 + attribute \src "libresoc.v:197273.3-197274.49" + process $proc$libresoc.v:197273$13253 assign { } { } assign $0\core_core_cr_out[6:0] \core_core_cr_out$next sync posedge \clk update \core_core_cr_out $0\core_core_cr_out[6:0] end - attribute \src "libresoc.v:197753.3-197754.45" - process $proc$libresoc.v:197753$13255 + attribute \src "libresoc.v:197275.3-197276.45" + process $proc$libresoc.v:197275$13254 assign { } { } assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next sync posedge \clk update \core_cr_out_ok $0\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:197755.3-197756.53" - process $proc$libresoc.v:197755$13256 + attribute \src "libresoc.v:197277.3-197278.53" + process $proc$libresoc.v:197277$13255 assign { } { } assign $0\core_core_core_msr[63:0] \core_core_core_msr$next sync posedge \clk update \core_core_core_msr $0\core_core_core_msr[63:0] end - attribute \src "libresoc.v:197757.3-197758.53" - process $proc$libresoc.v:197757$13257 + attribute \src "libresoc.v:197279.3-197280.53" + process $proc$libresoc.v:197279$13256 assign { } { } assign $0\core_core_core_cia[63:0] \core_core_core_cia$next sync posedge \clk update \core_core_core_cia $0\core_core_core_cia[63:0] end - attribute \src "libresoc.v:197759.3-197760.55" - process $proc$libresoc.v:197759$13258 + attribute \src "libresoc.v:197281.3-197282.55" + process $proc$libresoc.v:197281$13257 assign { } { } assign $0\core_core_core_insn[31:0] \core_core_core_insn$next sync posedge \clk update \core_core_core_insn $0\core_core_core_insn[31:0] end - attribute \src "libresoc.v:197761.3-197762.65" - process $proc$libresoc.v:197761$13259 + attribute \src "libresoc.v:197283.3-197284.65" + process $proc$libresoc.v:197283$13258 assign { } { } assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next sync posedge \clk update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:197763.3-197764.61" - process $proc$libresoc.v:197763$13260 + attribute \src "libresoc.v:197285.3-197286.61" + process $proc$libresoc.v:197285$13259 assign { } { } assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next sync posedge \clk update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:197765.3-197766.41" - process $proc$libresoc.v:197765$13261 + attribute \src "libresoc.v:197287.3-197288.41" + process $proc$libresoc.v:197287$13260 assign { } { } assign $0\core_core_lk[0:0] \core_core_lk$next sync posedge \clk update \core_core_lk $0\core_core_lk[0:0] end - attribute \src "libresoc.v:197767.3-197768.51" - process $proc$libresoc.v:197767$13262 + attribute \src "libresoc.v:197289.3-197290.51" + process $proc$libresoc.v:197289$13261 assign { } { } assign $0\core_core_core_rc[0:0] \core_core_core_rc$next sync posedge \clk update \core_core_core_rc $0\core_core_core_rc[0:0] end - attribute \src "libresoc.v:197769.3-197770.45" - process $proc$libresoc.v:197769$13263 + attribute \src "libresoc.v:197291.3-197292.45" + process $proc$libresoc.v:197291$13262 assign { } { } assign $0\exec_fsm_state[0:0] \exec_fsm_state$next sync posedge \clk update \exec_fsm_state $0\exec_fsm_state[0:0] end - attribute \src "libresoc.v:197771.3-197772.57" - process $proc$libresoc.v:197771$13264 + attribute \src "libresoc.v:197293.3-197294.57" + process $proc$libresoc.v:197293$13263 assign { } { } assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next sync posedge \clk update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:197773.3-197774.51" - process $proc$libresoc.v:197773$13265 + attribute \src "libresoc.v:197295.3-197296.51" + process $proc$libresoc.v:197295$13264 assign { } { } assign $0\core_core_core_oe[0:0] \core_core_core_oe$next sync posedge \clk update \core_core_core_oe $0\core_core_core_oe[0:0] end - attribute \src "libresoc.v:197775.3-197776.57" - process $proc$libresoc.v:197775$13266 + attribute \src "libresoc.v:197297.3-197298.57" + process $proc$libresoc.v:197297$13265 assign { } { } assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next sync posedge \clk update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:197777.3-197778.69" - process $proc$libresoc.v:197777$13267 + attribute \src "libresoc.v:197299.3-197300.69" + process $proc$libresoc.v:197299$13266 assign { } { } assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next sync posedge \clk update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:197779.3-197780.63" - process $proc$libresoc.v:197779$13268 + attribute \src "libresoc.v:197301.3-197302.63" + process $proc$libresoc.v:197301$13267 assign { } { } assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next sync posedge \clk update \core_core_core_traptype $0\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:197781.3-197782.71" - process $proc$libresoc.v:197781$13269 + attribute \src "libresoc.v:197303.3-197304.71" + process $proc$libresoc.v:197303$13268 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13270 \core_core_core_exc_$signal$next + assign $0\core_core_core_exc_$signal[0:0]$13269 \core_core_core_exc_$signal$next sync posedge \clk - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13270 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13269 end - attribute \src "libresoc.v:197783.3-197784.75" - process $proc$libresoc.v:197783$13271 + attribute \src "libresoc.v:197305.3-197306.75" + process $proc$libresoc.v:197305$13270 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13272 \core_core_core_exc_$signal$3$next + assign $0\core_core_core_exc_$signal$3[0:0]$13271 \core_core_core_exc_$signal$3$next sync posedge \clk - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13272 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13271 end - attribute \src "libresoc.v:197785.3-197786.75" - process $proc$libresoc.v:197785$13273 + attribute \src "libresoc.v:197307.3-197308.75" + process $proc$libresoc.v:197307$13272 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13274 \core_core_core_exc_$signal$4$next + assign $0\core_core_core_exc_$signal$4[0:0]$13273 \core_core_core_exc_$signal$4$next sync posedge \clk - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13274 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13273 end - attribute \src "libresoc.v:197787.3-197788.75" - process $proc$libresoc.v:197787$13275 + attribute \src "libresoc.v:197309.3-197310.75" + process $proc$libresoc.v:197309$13274 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13276 \core_core_core_exc_$signal$5$next + assign $0\core_core_core_exc_$signal$5[0:0]$13275 \core_core_core_exc_$signal$5$next sync posedge \clk - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13276 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13275 end - attribute \src "libresoc.v:197789.3-197790.75" - process $proc$libresoc.v:197789$13277 + attribute \src "libresoc.v:197311.3-197312.75" + process $proc$libresoc.v:197311$13276 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13278 \core_core_core_exc_$signal$6$next + assign $0\core_core_core_exc_$signal$6[0:0]$13277 \core_core_core_exc_$signal$6$next sync posedge \clk - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13278 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13277 end - attribute \src "libresoc.v:197791.3-197792.41" - process $proc$libresoc.v:197791$13279 + attribute \src "libresoc.v:197313.3-197314.41" + process $proc$libresoc.v:197313$13278 assign { } { } assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next sync posedge \clk update \core_sv_a_nz $0\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:197793.3-197794.75" - process $proc$libresoc.v:197793$13280 + attribute \src "libresoc.v:197315.3-197316.75" + process $proc$libresoc.v:197315$13279 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13281 \core_core_core_exc_$signal$7$next + assign $0\core_core_core_exc_$signal$7[0:0]$13280 \core_core_core_exc_$signal$7$next sync posedge \clk - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13281 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13280 end - attribute \src "libresoc.v:197795.3-197796.75" - process $proc$libresoc.v:197795$13282 + attribute \src "libresoc.v:197317.3-197318.75" + process $proc$libresoc.v:197317$13281 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13283 \core_core_core_exc_$signal$8$next + assign $0\core_core_core_exc_$signal$8[0:0]$13282 \core_core_core_exc_$signal$8$next sync posedge \clk - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13283 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13282 end - attribute \src "libresoc.v:197797.3-197798.75" - process $proc$libresoc.v:197797$13284 + attribute \src "libresoc.v:197319.3-197320.75" + process $proc$libresoc.v:197319$13283 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13285 \core_core_core_exc_$signal$9$next + assign $0\core_core_core_exc_$signal$9[0:0]$13284 \core_core_core_exc_$signal$9$next sync posedge \clk - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13285 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13284 end - attribute \src "libresoc.v:197799.3-197800.63" - process $proc$libresoc.v:197799$13286 + attribute \src "libresoc.v:197321.3-197322.63" + process $proc$libresoc.v:197321$13285 assign { } { } assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next sync posedge \clk update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:197801.3-197802.57" - process $proc$libresoc.v:197801$13287 + attribute \src "libresoc.v:197323.3-197324.57" + process $proc$libresoc.v:197323$13286 assign { } { } assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next sync posedge \clk update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:197803.3-197804.63" - process $proc$libresoc.v:197803$13288 + attribute \src "libresoc.v:197325.3-197326.63" + process $proc$libresoc.v:197325$13287 assign { } { } assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next sync posedge \clk update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:197805.3-197806.57" - process $proc$libresoc.v:197805$13289 + attribute \src "libresoc.v:197327.3-197328.57" + process $proc$libresoc.v:197327$13288 assign { } { } assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next sync posedge \clk update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:197807.3-197808.53" - process $proc$libresoc.v:197807$13290 + attribute \src "libresoc.v:197329.3-197330.53" + process $proc$libresoc.v:197329$13289 assign { } { } assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next sync posedge \clk update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:197809.3-197810.63" - process $proc$libresoc.v:197809$13291 + attribute \src "libresoc.v:197331.3-197332.63" + process $proc$libresoc.v:197331$13290 assign { } { } assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next sync posedge \clk update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:197811.3-197812.37" - process $proc$libresoc.v:197811$13292 + attribute \src "libresoc.v:197333.3-197334.37" + process $proc$libresoc.v:197333$13291 assign { } { } assign $0\sv_changed[0:0] \sv_changed$next sync posedge \clk update \sv_changed $0\sv_changed[0:0] end - attribute \src "libresoc.v:197813.3-197814.57" - process $proc$libresoc.v:197813$13293 + attribute \src "libresoc.v:197335.3-197336.57" + process $proc$libresoc.v:197335$13292 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13294 \core_bigendian_i$10$next + assign $0\core_bigendian_i$10[0:0]$13293 \core_bigendian_i$10$next sync posedge \clk - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13294 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13293 end - attribute \src "libresoc.v:197815.3-197816.37" - process $proc$libresoc.v:197815$13295 + attribute \src "libresoc.v:197337.3-197338.37" + process $proc$libresoc.v:197337$13294 assign { } { } assign $0\pc_changed[0:0] \pc_changed$next sync posedge \clk update \pc_changed $0\pc_changed[0:0] end - attribute \src "libresoc.v:197817.3-197818.47" - process $proc$libresoc.v:197817$13296 + attribute \src "libresoc.v:197339.3-197340.47" + process $proc$libresoc.v:197339$13295 assign { } { } assign $0\issue_fsm_state[2:0] \issue_fsm_state$next sync posedge \clk update \issue_fsm_state $0\issue_fsm_state[2:0] end - attribute \src "libresoc.v:197819.3-197820.53" - process $proc$libresoc.v:197819$13297 + attribute \src "libresoc.v:197341.3-197342.53" + process $proc$libresoc.v:197341$13296 assign { } { } assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next sync posedge \clk update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:197821.3-197822.23" - process $proc$libresoc.v:197821$13298 + attribute \src "libresoc.v:197343.3-197344.23" + process $proc$libresoc.v:197343$13297 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:197823.3-197824.41" - process $proc$libresoc.v:197823$13299 + attribute \src "libresoc.v:197345.3-197346.41" + process $proc$libresoc.v:197345$13298 assign { } { } assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next sync posedge \clk update \dec2_cur_msr $0\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:197825.3-197826.47" - process $proc$libresoc.v:197825$13300 + attribute \src "libresoc.v:197347.3-197348.47" + process $proc$libresoc.v:197347$13299 assign { } { } assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next sync posedge \clk update \fetch_fsm_state $0\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:197827.3-197828.33" - process $proc$libresoc.v:197827$13301 + attribute \src "libresoc.v:197349.3-197350.33" + process $proc$libresoc.v:197349$13300 assign { } { } assign $0\msr_read[0:0] \msr_read$next sync posedge \clk update \msr_read $0\msr_read[0:0] end - attribute \src "libresoc.v:197829.3-197830.45" - process $proc$libresoc.v:197829$13302 + attribute \src "libresoc.v:197351.3-197352.45" + process $proc$libresoc.v:197351$13301 assign { } { } assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next sync posedge \clk update \cur_cur_svstep $0\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:197831.3-197832.43" - process $proc$libresoc.v:197831$13303 + attribute \src "libresoc.v:197353.3-197354.43" + process $proc$libresoc.v:197353$13302 assign { } { } assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next sync posedge \clk update \cur_cur_subvl $0\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:197833.3-197834.47" - process $proc$libresoc.v:197833$13304 + attribute \src "libresoc.v:197355.3-197356.47" + process $proc$libresoc.v:197355$13303 assign { } { } assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next sync posedge \clk update \cur_cur_dststep $0\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:197835.3-197836.47" - process $proc$libresoc.v:197835$13305 + attribute \src "libresoc.v:197357.3-197358.47" + process $proc$libresoc.v:197357$13304 assign { } { } assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next sync posedge \clk update \core_raw_insn_i $0\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:197837.3-197838.47" - process $proc$libresoc.v:197837$13306 + attribute \src "libresoc.v:197359.3-197360.47" + process $proc$libresoc.v:197359$13305 assign { } { } assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next sync posedge \clk update \cur_cur_srcstep $0\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:197839.3-197840.37" - process $proc$libresoc.v:197839$13307 + attribute \src "libresoc.v:197361.3-197362.37" + process $proc$libresoc.v:197361$13306 assign { } { } assign $0\cur_cur_vl[6:0] \cur_cur_vl$next sync posedge \clk update \cur_cur_vl $0\cur_cur_vl[6:0] end - attribute \src "libresoc.v:197841.3-197842.43" - process $proc$libresoc.v:197841$13308 + attribute \src "libresoc.v:197363.3-197364.43" + process $proc$libresoc.v:197363$13307 assign { } { } assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next sync posedge \clk update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:197843.3-197844.39" - process $proc$libresoc.v:197843$13309 + attribute \src "libresoc.v:197365.3-197366.39" + process $proc$libresoc.v:197365$13308 assign { } { } assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next sync posedge \clk update \dec2_cur_pc $0\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:197845.3-197846.49" - process $proc$libresoc.v:197845$13310 + attribute \src "libresoc.v:197367.3-197368.49" + process $proc$libresoc.v:197367$13309 assign { } { } assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next sync posedge \clk update \svstate_ok_delay $0\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:197847.3-197848.39" - process $proc$libresoc.v:197847$13311 + attribute \src "libresoc.v:197369.3-197370.39" + process $proc$libresoc.v:197369$13310 assign { } { } assign $0\pc_ok_delay[0:0] \pc_ok_delay$next sync posedge \clk update \pc_ok_delay $0\pc_ok_delay[0:0] end - attribute \src "libresoc.v:197849.3-197850.43" - process $proc$libresoc.v:197849$13312 + attribute \src "libresoc.v:197371.3-197372.43" + process $proc$libresoc.v:197371$13311 assign { } { } assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o sync posedge \clk update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:197851.3-197852.27" - process $proc$libresoc.v:197851$13313 + attribute \src "libresoc.v:197373.3-197374.27" + process $proc$libresoc.v:197373$13312 assign { } { } assign $0\delay[1:0] \delay$next sync posedge \por_clk update \delay $0\delay[1:0] end - attribute \src "libresoc.v:197853.3-197854.43" - process $proc$libresoc.v:197853$13314 + attribute \src "libresoc.v:197375.3-197376.43" + process $proc$libresoc.v:197375$13313 assign { } { } assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next sync posedge \clk update \dec2_cur_eint $0\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:197855.3-197856.47" - process $proc$libresoc.v:197855$13315 + attribute \src "libresoc.v:197377.3-197378.47" + process $proc$libresoc.v:197377$13314 assign { } { } assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next sync posedge \clk update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:198386.3-198394.6" - process $proc$libresoc.v:198386$13316 + attribute \src "libresoc.v:197908.3-197916.6" + process $proc$libresoc.v:197908$13315 assign { } { } assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$13317 $1\dbg_dmi_addr_i$next[3:0]$13318 - attribute \src "libresoc.v:198387.5-198387.29" + assign $0\dbg_dmi_addr_i$next[3:0]$13316 $1\dbg_dmi_addr_i$next[3:0]$13317 + attribute \src "libresoc.v:197909.5-197909.29" switch \initial - attribute \src "libresoc.v:198387.9-198387.17" + attribute \src "libresoc.v:197909.9-197909.17" case 1'1 case end @@ -376148,21 +375511,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$13318 4'0000 + assign $1\dbg_dmi_addr_i$next[3:0]$13317 4'0000 case - assign $1\dbg_dmi_addr_i$next[3:0]$13318 \jtag_dmi0__addr_i + assign $1\dbg_dmi_addr_i$next[3:0]$13317 \jtag_dmi0__addr_i end sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13317 + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13316 end - attribute \src "libresoc.v:198395.3-198403.6" - process $proc$libresoc.v:198395$13319 + attribute \src "libresoc.v:197917.3-197925.6" + process $proc$libresoc.v:197917$13318 assign { } { } assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$13320 $1\dbg_dmi_req_i$next[0:0]$13321 - attribute \src "libresoc.v:198396.5-198396.29" + assign $0\dbg_dmi_req_i$next[0:0]$13319 $1\dbg_dmi_req_i$next[0:0]$13320 + attribute \src "libresoc.v:197918.5-197918.29" switch \initial - attribute \src "libresoc.v:198396.9-198396.17" + attribute \src "libresoc.v:197918.9-197918.17" case 1'1 case end @@ -376171,15 +375534,15 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$13321 1'0 + assign $1\dbg_dmi_req_i$next[0:0]$13320 1'0 case - assign $1\dbg_dmi_req_i$next[0:0]$13321 \jtag_dmi0__req_i + assign $1\dbg_dmi_req_i$next[0:0]$13320 \jtag_dmi0__req_i end sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13320 + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13319 end - attribute \src "libresoc.v:198404.3-198468.6" - process $proc$libresoc.v:198404$13322 + attribute \src "libresoc.v:197926.3-197981.6" + process $proc$libresoc.v:197926$13321 assign { } { } assign { } { } assign { } { } @@ -376210,135 +375573,86 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_dststep$next[6:0]$13323 $3\core_core_dststep$next[6:0]$13353 - assign $0\core_core_maxvl$next[6:0]$13324 $3\core_core_maxvl$next[6:0]$13354 - assign $0\core_core_pc$next[63:0]$13325 $3\core_core_pc$next[63:0]$13355 - assign $0\core_core_srcstep$next[6:0]$13326 $3\core_core_srcstep$next[6:0]$13356 - assign $0\core_core_subvl$next[1:0]$13327 $3\core_core_subvl$next[1:0]$13357 - assign $0\core_core_svstep$next[1:0]$13328 $3\core_core_svstep$next[1:0]$13358 - assign $0\core_core_vl$next[6:0]$13329 $3\core_core_vl$next[6:0]$13359 - assign $0\core_dec$next[63:0]$13330 $3\core_dec$next[63:0]$13360 - assign $0\core_eint$next[0:0]$13331 $3\core_eint$next[0:0]$13361 - assign $0\core_msr$next[63:0]$13332 $3\core_msr$next[63:0]$13362 - attribute \src "libresoc.v:198405.5-198405.29" + assign $0\core_core_dststep$next[6:0]$13322 $2\core_core_dststep$next[6:0]$13342 + assign $0\core_core_maxvl$next[6:0]$13323 $2\core_core_maxvl$next[6:0]$13343 + assign $0\core_core_pc$next[63:0]$13324 $2\core_core_pc$next[63:0]$13344 + assign $0\core_core_srcstep$next[6:0]$13325 $2\core_core_srcstep$next[6:0]$13345 + assign $0\core_core_subvl$next[1:0]$13326 $2\core_core_subvl$next[1:0]$13346 + assign $0\core_core_svstep$next[1:0]$13327 $2\core_core_svstep$next[1:0]$13347 + assign $0\core_core_vl$next[6:0]$13328 $2\core_core_vl$next[6:0]$13348 + assign $0\core_dec$next[63:0]$13329 $2\core_dec$next[63:0]$13349 + assign $0\core_eint$next[0:0]$13330 $2\core_eint$next[0:0]$13350 + assign $0\core_msr$next[63:0]$13331 $2\core_msr$next[63:0]$13351 + attribute \src "libresoc.v:197927.5-197927.29" switch \initial - attribute \src "libresoc.v:198405.9-198405.17" + attribute \src "libresoc.v:197927.9-197927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 - assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13335 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13339 \core_core_vl - assign $1\core_dec$next[63:0]$13340 \core_dec - assign $1\core_eint$next[0:0]$13341 \core_eint - assign $1\core_msr$next[63:0]$13342 \core_msr + assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13334 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13338 \core_core_vl + assign $1\core_dec$next[63:0]$13339 \core_dec + assign $1\core_eint$next[0:0]$13340 \core_eint + assign $1\core_msr$next[63:0]$13341 \core_msr attribute \src "libresoc.v:0.0-0.0" case 3'001 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\core_core_dststep$next[6:0]$13333 $2\core_core_dststep$next[6:0]$13343 - assign $1\core_core_maxvl$next[6:0]$13334 $2\core_core_maxvl$next[6:0]$13344 - assign $1\core_core_pc$next[63:0]$13335 $2\core_core_pc$next[63:0]$13345 - assign $1\core_core_srcstep$next[6:0]$13336 $2\core_core_srcstep$next[6:0]$13346 - assign $1\core_core_subvl$next[1:0]$13337 $2\core_core_subvl$next[1:0]$13347 - assign $1\core_core_svstep$next[1:0]$13338 $2\core_core_svstep$next[1:0]$13348 - assign $1\core_core_vl$next[6:0]$13339 $2\core_core_vl$next[6:0]$13349 - assign $1\core_dec$next[63:0]$13340 $2\core_dec$next[63:0]$13350 - assign $1\core_eint$next[0:0]$13341 $2\core_eint$next[0:0]$13351 - assign $1\core_msr$next[63:0]$13342 $2\core_msr$next[63:0]$13352 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_core_maxvl$next[6:0]$13344 $2\core_core_vl$next[6:0]$13349 $2\core_core_srcstep$next[6:0]$13346 $2\core_core_dststep$next[6:0]$13343 $2\core_core_subvl$next[1:0]$13347 $2\core_core_svstep$next[1:0]$13348 $2\core_dec$next[63:0]$13350 $2\core_eint$next[0:0]$13351 $2\core_msr$next[63:0]$13352 $2\core_core_pc$next[63:0]$13345 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } - case - assign $2\core_core_dststep$next[6:0]$13343 \core_core_dststep - assign $2\core_core_maxvl$next[6:0]$13344 \core_core_maxvl - assign $2\core_core_pc$next[63:0]$13345 \core_core_pc - assign $2\core_core_srcstep$next[6:0]$13346 \core_core_srcstep - assign $2\core_core_subvl$next[1:0]$13347 \core_core_subvl - assign $2\core_core_svstep$next[1:0]$13348 \core_core_svstep - assign $2\core_core_vl$next[6:0]$13349 \core_core_vl - assign $2\core_dec$next[63:0]$13350 \core_dec - assign $2\core_eint$next[0:0]$13351 \core_eint - assign $2\core_msr$next[63:0]$13352 \core_msr - end + assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13334 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13338 \core_core_vl + assign $1\core_dec$next[63:0]$13339 \core_dec + assign $1\core_eint$next[0:0]$13340 \core_eint + assign $1\core_msr$next[63:0]$13341 \core_msr attribute \src "libresoc.v:0.0-0.0" case 3'011 - assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13335 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13339 \core_core_vl - assign $1\core_dec$next[63:0]$13340 \core_dec - assign $1\core_eint$next[0:0]$13341 \core_eint - assign $1\core_msr$next[63:0]$13342 \core_msr + assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13334 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13338 \core_core_vl + assign $1\core_dec$next[63:0]$13339 \core_dec + assign $1\core_eint$next[0:0]$13340 \core_eint + assign $1\core_msr$next[63:0]$13341 \core_msr attribute \src "libresoc.v:0.0-0.0" case 3'100 - assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13335 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13339 \core_core_vl - assign $1\core_dec$next[63:0]$13340 \core_dec - assign $1\core_eint$next[0:0]$13341 \core_eint - assign $1\core_msr$next[63:0]$13342 \core_msr - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13335 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13339 \core_core_vl - assign $1\core_dec$next[63:0]$13340 \core_dec - assign $1\core_eint$next[0:0]$13341 \core_eint - assign $1\core_msr$next[63:0]$13342 \core_msr + assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13334 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13338 \core_core_vl + assign $1\core_dec$next[63:0]$13339 \core_dec + assign $1\core_eint$next[0:0]$13340 \core_eint + assign $1\core_msr$next[63:0]$13341 \core_msr attribute \src "libresoc.v:0.0-0.0" case 3'101 - assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13335 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13339 \core_core_vl - assign $1\core_dec$next[63:0]$13340 \core_dec - assign $1\core_eint$next[0:0]$13341 \core_eint - assign $1\core_msr$next[63:0]$13342 \core_msr + assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13334 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13338 \core_core_vl + assign $1\core_dec$next[63:0]$13339 \core_dec + assign $1\core_eint$next[0:0]$13340 \core_eint + assign $1\core_msr$next[63:0]$13341 \core_msr attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'010 assign { } { } assign { } { } assign { } { } @@ -376349,18 +375663,18 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_maxvl$next[6:0]$13334 $1\core_core_vl$next[6:0]$13339 $1\core_core_srcstep$next[6:0]$13336 $1\core_core_dststep$next[6:0]$13333 $1\core_core_subvl$next[1:0]$13337 $1\core_core_svstep$next[1:0]$13338 $1\core_dec$next[63:0]$13340 $1\core_eint$next[0:0]$13341 $1\core_msr$next[63:0]$13342 $1\core_core_pc$next[63:0]$13335 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $1\core_core_maxvl$next[6:0]$13333 $1\core_core_vl$next[6:0]$13338 $1\core_core_srcstep$next[6:0]$13335 $1\core_core_dststep$next[6:0]$13332 $1\core_core_subvl$next[1:0]$13336 $1\core_core_svstep$next[1:0]$13337 $1\core_dec$next[63:0]$13339 $1\core_eint$next[0:0]$13340 $1\core_msr$next[63:0]$13341 $1\core_core_pc$next[63:0]$13334 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13335 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13339 \core_core_vl - assign $1\core_dec$next[63:0]$13340 \core_dec - assign $1\core_eint$next[0:0]$13341 \core_eint - assign $1\core_msr$next[63:0]$13342 \core_msr + assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13334 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13338 \core_core_vl + assign $1\core_dec$next[63:0]$13339 \core_dec + assign $1\core_eint$next[0:0]$13340 \core_eint + assign $1\core_msr$next[63:0]$13341 \core_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -376376,355 +375690,196 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_core_pc$next[63:0]$13355 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$13362 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$13361 1'0 - assign $3\core_dec$next[63:0]$13360 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_core_svstep$next[1:0]$13358 2'00 - assign $3\core_core_subvl$next[1:0]$13357 2'00 - assign $3\core_core_dststep$next[6:0]$13353 7'0000000 - assign $3\core_core_srcstep$next[6:0]$13356 7'0000000 - assign $3\core_core_vl$next[6:0]$13359 7'0000000 - assign $3\core_core_maxvl$next[6:0]$13354 7'0000000 + assign $2\core_core_pc$next[63:0]$13344 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\core_msr$next[63:0]$13351 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\core_eint$next[0:0]$13350 1'0 + assign $2\core_dec$next[63:0]$13349 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\core_core_svstep$next[1:0]$13347 2'00 + assign $2\core_core_subvl$next[1:0]$13346 2'00 + assign $2\core_core_dststep$next[6:0]$13342 7'0000000 + assign $2\core_core_srcstep$next[6:0]$13345 7'0000000 + assign $2\core_core_vl$next[6:0]$13348 7'0000000 + assign $2\core_core_maxvl$next[6:0]$13343 7'0000000 case - assign $3\core_core_dststep$next[6:0]$13353 $1\core_core_dststep$next[6:0]$13333 - assign $3\core_core_maxvl$next[6:0]$13354 $1\core_core_maxvl$next[6:0]$13334 - assign $3\core_core_pc$next[63:0]$13355 $1\core_core_pc$next[63:0]$13335 - assign $3\core_core_srcstep$next[6:0]$13356 $1\core_core_srcstep$next[6:0]$13336 - assign $3\core_core_subvl$next[1:0]$13357 $1\core_core_subvl$next[1:0]$13337 - assign $3\core_core_svstep$next[1:0]$13358 $1\core_core_svstep$next[1:0]$13338 - assign $3\core_core_vl$next[6:0]$13359 $1\core_core_vl$next[6:0]$13339 - assign $3\core_dec$next[63:0]$13360 $1\core_dec$next[63:0]$13340 - assign $3\core_eint$next[0:0]$13361 $1\core_eint$next[0:0]$13341 - assign $3\core_msr$next[63:0]$13362 $1\core_msr$next[63:0]$13342 + assign $2\core_core_dststep$next[6:0]$13342 $1\core_core_dststep$next[6:0]$13332 + assign $2\core_core_maxvl$next[6:0]$13343 $1\core_core_maxvl$next[6:0]$13333 + assign $2\core_core_pc$next[63:0]$13344 $1\core_core_pc$next[63:0]$13334 + assign $2\core_core_srcstep$next[6:0]$13345 $1\core_core_srcstep$next[6:0]$13335 + assign $2\core_core_subvl$next[1:0]$13346 $1\core_core_subvl$next[1:0]$13336 + assign $2\core_core_svstep$next[1:0]$13347 $1\core_core_svstep$next[1:0]$13337 + assign $2\core_core_vl$next[6:0]$13348 $1\core_core_vl$next[6:0]$13338 + assign $2\core_dec$next[63:0]$13349 $1\core_dec$next[63:0]$13339 + assign $2\core_eint$next[0:0]$13350 $1\core_eint$next[0:0]$13340 + assign $2\core_msr$next[63:0]$13351 $1\core_msr$next[63:0]$13341 end sync always - update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13323 - update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13324 - update \core_core_pc$next $0\core_core_pc$next[63:0]$13325 - update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13326 - update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13327 - update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13328 - update \core_core_vl$next $0\core_core_vl$next[6:0]$13329 - update \core_dec$next $0\core_dec$next[63:0]$13330 - update \core_eint$next $0\core_eint$next[0:0]$13331 - update \core_msr$next $0\core_msr$next[63:0]$13332 + update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13322 + update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13323 + update \core_core_pc$next $0\core_core_pc$next[63:0]$13324 + update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13325 + update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13326 + update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13327 + update \core_core_vl$next $0\core_core_vl$next[6:0]$13328 + update \core_dec$next $0\core_dec$next[63:0]$13329 + update \core_eint$next $0\core_eint$next[0:0]$13330 + update \core_msr$next $0\core_msr$next[63:0]$13331 end - attribute \src "libresoc.v:198469.3-198493.6" - process $proc$libresoc.v:198469$13363 + attribute \src "libresoc.v:197982.3-198017.6" + process $proc$libresoc.v:197982$13352 assign { } { } assign { } { } assign { } { } - assign $0\core_raw_insn_i$next[31:0]$13364 $3\core_raw_insn_i$next[31:0]$13367 - attribute \src "libresoc.v:198470.5-198470.29" + assign $0\core_raw_insn_i$next[31:0]$13353 $2\core_raw_insn_i$next[31:0]$13355 + attribute \src "libresoc.v:197983.5-197983.29" switch \initial - attribute \src "libresoc.v:198470.9-198470.17" + attribute \src "libresoc.v:197983.9-197983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 - assign $1\core_raw_insn_i$next[31:0]$13365 \core_raw_insn_i + assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i attribute \src "libresoc.v:0.0-0.0" case 3'001 + assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case 3'010 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13365 $2\core_raw_insn_i$next[31:0]$13366 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_raw_insn_i$next[31:0]$13366 \dec2_raw_opcode_in - case - assign $2\core_raw_insn_i$next[31:0]$13366 \core_raw_insn_i - end + assign $1\core_raw_insn_i$next[31:0]$13354 \dec2_raw_opcode_in case - assign $1\core_raw_insn_i$next[31:0]$13365 \core_raw_insn_i + assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_raw_insn_i$next[31:0]$13367 0 + assign $2\core_raw_insn_i$next[31:0]$13355 0 case - assign $3\core_raw_insn_i$next[31:0]$13367 $1\core_raw_insn_i$next[31:0]$13365 + assign $2\core_raw_insn_i$next[31:0]$13355 $1\core_raw_insn_i$next[31:0]$13354 end sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13364 + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13353 end - attribute \src "libresoc.v:198494.3-198538.6" - process $proc$libresoc.v:198494$13368 + attribute \src "libresoc.v:198018.3-198053.6" + process $proc$libresoc.v:198018$13356 assign { } { } assign { } { } assign { } { } - assign $0\core_bigendian_i$10$next[0:0]$13369 $3\core_bigendian_i$10$next[0:0]$13372 - attribute \src "libresoc.v:198495.5-198495.29" + assign $0\core_bigendian_i$10$next[0:0]$13357 $2\core_bigendian_i$10$next[0:0]$13359 + attribute \src "libresoc.v:198019.5-198019.29" switch \initial - attribute \src "libresoc.v:198495.9-198495.17" + attribute \src "libresoc.v:198019.9-198019.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 - assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10 + assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" case 3'001 - assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13370 $2\core_bigendian_i$10$next[0:0]$13371 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_bigendian_i$10$next[0:0]$13371 \core_bigendian_i - case - assign $2\core_bigendian_i$10$next[0:0]$13371 \core_bigendian_i$10 - end + assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" case 3'011 - assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10 + assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" case 3'100 - assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10 + assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" case 3'101 - assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10 + assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'010 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i + assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i case - assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10 + assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_bigendian_i$10$next[0:0]$13372 1'0 + assign $2\core_bigendian_i$10$next[0:0]$13359 1'0 case - assign $3\core_bigendian_i$10$next[0:0]$13372 $1\core_bigendian_i$10$next[0:0]$13370 + assign $2\core_bigendian_i$10$next[0:0]$13359 $1\core_bigendian_i$10$next[0:0]$13358 end sync always - update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13369 + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13357 end - attribute \src "libresoc.v:198539.3-198583.6" - process $proc$libresoc.v:198539$13373 + attribute \src "libresoc.v:198054.3-198089.6" + process $proc$libresoc.v:198054$13360 assign { } { } assign { } { } assign { } { } - assign $0\core_sv_a_nz$next[0:0]$13374 $3\core_sv_a_nz$next[0:0]$13377 - attribute \src "libresoc.v:198540.5-198540.29" + assign $0\core_sv_a_nz$next[0:0]$13361 $2\core_sv_a_nz$next[0:0]$13363 + attribute \src "libresoc.v:198055.5-198055.29" switch \initial - attribute \src "libresoc.v:198540.9-198540.17" + attribute \src "libresoc.v:198055.9-198055.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 - assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz attribute \src "libresoc.v:0.0-0.0" case 3'001 - assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13375 $2\core_sv_a_nz$next[0:0]$13376 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_sv_a_nz$next[0:0]$13376 \dec2_sv_a_nz - case - assign $2\core_sv_a_nz$next[0:0]$13376 \core_sv_a_nz - end + assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz attribute \src "libresoc.v:0.0-0.0" case 3'011 - assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz attribute \src "libresoc.v:0.0-0.0" case 3'100 - assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz attribute \src "libresoc.v:0.0-0.0" case 3'101 - assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'010 assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13375 \dec2_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13362 \dec2_sv_a_nz case - assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_sv_a_nz$next[0:0]$13377 1'0 - case - assign $3\core_sv_a_nz$next[0:0]$13377 $1\core_sv_a_nz$next[0:0]$13375 - end - sync always - update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13374 - end - attribute \src "libresoc.v:198584.3-198629.6" - process $proc$libresoc.v:198584$13378 - assign { } { } - assign { } { } - assign { } { } - assign $0\insn_done[0:0] $4\insn_done[0:0] - attribute \src "libresoc.v:198585.5-198585.29" - switch \initial - attribute \src "libresoc.v:198585.9-198585.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - switch \issue_fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign $1\insn_done[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\insn_done[0:0] $2\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\insn_done[0:0] $3\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" - switch \$234 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\insn_done[0:0] 1'1 - case - assign $3\insn_done[0:0] 1'0 - end - case - assign $2\insn_done[0:0] 1'0 - end - case - assign $1\insn_done[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" - switch \exec_fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 1'0 - assign $4\insn_done[0:0] $1\insn_done[0:0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\insn_done[0:0] $5\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" - switch \$236 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\insn_done[0:0] $6\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" - switch \exec_pc_ready_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\insn_done[0:0] 1'1 - case - assign $6\insn_done[0:0] $1\insn_done[0:0] - end - case - assign $5\insn_done[0:0] $1\insn_done[0:0] - end + assign $2\core_sv_a_nz$next[0:0]$13363 1'0 case - assign $4\insn_done[0:0] $1\insn_done[0:0] + assign $2\core_sv_a_nz$next[0:0]$13363 $1\core_sv_a_nz$next[0:0]$13362 end sync always - update \insn_done $0\insn_done[0:0] + update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13361 end - attribute \src "libresoc.v:198630.3-198648.6" - process $proc$libresoc.v:198630$13379 - assign { } { } - assign { } { } - assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:198631.5-198631.29" - switch \initial - attribute \src "libresoc.v:198631.9-198631.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - switch \issue_fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign $1\pred_insn_valid_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign $1\pred_insn_valid_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\pred_insn_valid_i[0:0] 1'1 - case - assign $1\pred_insn_valid_i[0:0] 1'0 - end - sync always - update \pred_insn_valid_i $0\pred_insn_valid_i[0:0] - end - attribute \src "libresoc.v:198649.3-198671.6" - process $proc$libresoc.v:198649$13380 - assign { } { } - assign { } { } - assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:198650.5-198650.29" - switch \initial - attribute \src "libresoc.v:198650.9-198650.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - switch \issue_fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign $1\pred_mask_ready_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign $1\pred_mask_ready_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign $1\pred_mask_ready_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\pred_mask_ready_i[0:0] 1'1 - case - assign $1\pred_mask_ready_i[0:0] 1'0 - end - sync always - update \pred_mask_ready_i $0\pred_mask_ready_i[0:0] - end - attribute \src "libresoc.v:198672.3-198698.6" - process $proc$libresoc.v:198672$13381 + attribute \src "libresoc.v:198090.3-198124.6" + process $proc$libresoc.v:198090$13364 assign { } { } assign { } { } assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:198673.5-198673.29" + attribute \src "libresoc.v:198091.5-198091.29" switch \initial - attribute \src "libresoc.v:198673.9-198673.17" + attribute \src "libresoc.v:198091.9-198091.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 @@ -376739,7 +375894,13 @@ module \ti case 3'100 assign $1\exec_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\exec_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'010 + assign $1\exec_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } assign $1\exec_insn_valid_i[0:0] 1'1 case @@ -376748,18 +375909,18 @@ module \ti sync always update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] end - attribute \src "libresoc.v:198699.3-198734.6" - process $proc$libresoc.v:198699$13382 + attribute \src "libresoc.v:198125.3-198168.6" + process $proc$libresoc.v:198125$13365 assign { } { } assign { } { } assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198700.5-198700.29" + attribute \src "libresoc.v:198126.5-198126.29" switch \initial - attribute \src "libresoc.v:198700.9-198700.17" + attribute \src "libresoc.v:198126.9-198126.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 @@ -376774,14 +375935,20 @@ module \ti case 3'100 assign $1\exec_pc_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\exec_pc_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'110 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 assign { } { } assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - switch \$242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + switch \$244 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -376795,18 +375962,18 @@ module \ti sync always update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] end - attribute \src "libresoc.v:198735.3-198775.6" - process $proc$libresoc.v:198735$13383 + attribute \src "libresoc.v:198169.3-198217.6" + process $proc$libresoc.v:198169$13366 assign { } { } assign { } { } assign $0\is_last[0:0] $1\is_last[0:0] - attribute \src "libresoc.v:198736.5-198736.29" + attribute \src "libresoc.v:198170.5-198170.29" switch \initial - attribute \src "libresoc.v:198736.9-198736.17" + attribute \src "libresoc.v:198170.9-198170.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 @@ -376821,24 +375988,30 @@ module \ti case 3'100 assign $1\is_last[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\is_last[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'110 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 assign { } { } assign $1\is_last[0:0] $2\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - switch \$248 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + switch \$250 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\is_last[0:0] $3\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\is_last[0:0] \$250 + assign $3\is_last[0:0] \$252 case assign $3\is_last[0:0] 1'0 end @@ -376851,64 +376024,64 @@ module \ti sync always update \is_last $0\is_last[0:0] end - attribute \src "libresoc.v:198776.3-198785.6" - process $proc$libresoc.v:198776$13384 + attribute \src "libresoc.v:198218.3-198227.6" + process $proc$libresoc.v:198218$13367 assign { } { } assign { } { } - assign $0\core_wen$11[2:0]$13385 $1\core_wen$11[2:0]$13386 - attribute \src "libresoc.v:198777.5-198777.29" + assign $0\core_wen$11[2:0]$13368 $1\core_wen$11[2:0]$13369 + attribute \src "libresoc.v:198219.5-198219.29" switch \initial - attribute \src "libresoc.v:198777.9-198777.17" + attribute \src "libresoc.v:198219.9-198219.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:722" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_wen$11[2:0]$13386 3'100 + assign $1\core_wen$11[2:0]$13369 3'100 case - assign $1\core_wen$11[2:0]$13386 3'000 + assign $1\core_wen$11[2:0]$13369 3'000 end sync always - update \core_wen$11 $0\core_wen$11[2:0]$13385 + update \core_wen$11 $0\core_wen$11[2:0]$13368 end - attribute \src "libresoc.v:198786.3-198795.6" - process $proc$libresoc.v:198786$13387 + attribute \src "libresoc.v:198228.3-198237.6" + process $proc$libresoc.v:198228$13370 assign { } { } assign { } { } - assign $0\core_data_i$12[63:0]$13388 $1\core_data_i$12[63:0]$13389 - attribute \src "libresoc.v:198787.5-198787.29" + assign $0\core_data_i$12[63:0]$13371 $1\core_data_i$12[63:0]$13372 + attribute \src "libresoc.v:198229.5-198229.29" switch \initial - attribute \src "libresoc.v:198787.9-198787.17" + attribute \src "libresoc.v:198229.9-198229.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:722" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_data_i$12[63:0]$13389 \$252 + assign $1\core_data_i$12[63:0]$13372 \$254 case - assign $1\core_data_i$12[63:0]$13389 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_data_i$12[63:0]$13372 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \core_data_i$12 $0\core_data_i$12[63:0]$13388 + update \core_data_i$12 $0\core_data_i$12[63:0]$13371 end - attribute \src "libresoc.v:198796.3-198806.6" - process $proc$libresoc.v:198796$13390 + attribute \src "libresoc.v:198238.3-198248.6" + process $proc$libresoc.v:198238$13373 assign { } { } assign { } { } assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:198797.5-198797.29" + attribute \src "libresoc.v:198239.5-198239.29" switch \initial - attribute \src "libresoc.v:198797.9-198797.17" + attribute \src "libresoc.v:198239.9-198239.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 @@ -376920,24 +376093,24 @@ module \ti sync always update \exec_insn_ready_o $0\exec_insn_ready_o[0:0] end - attribute \src "libresoc.v:198807.3-198831.6" - process $proc$libresoc.v:198807$13391 + attribute \src "libresoc.v:198249.3-198273.6" + process $proc$libresoc.v:198249$13374 assign { } { } assign { } { } assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:198808.5-198808.29" + attribute \src "libresoc.v:198250.5-198250.29" switch \initial - attribute \src "libresoc.v:198808.9-198808.17" + attribute \src "libresoc.v:198250.9-198250.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -376950,8 +376123,8 @@ module \ti case 1'1 assign { } { } assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" - switch \$254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:762" + switch \$256 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -376965,24 +376138,24 @@ module \ti sync always update \core_ivalid_i $0\core_ivalid_i[0:0] end - attribute \src "libresoc.v:198832.3-198847.6" - process $proc$libresoc.v:198832$13392 + attribute \src "libresoc.v:198274.3-198289.6" + process $proc$libresoc.v:198274$13375 assign { } { } assign { } { } assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "libresoc.v:198833.5-198833.29" + attribute \src "libresoc.v:198275.5-198275.29" switch \initial - attribute \src "libresoc.v:198833.9-198833.17" + attribute \src "libresoc.v:198275.9-198275.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_issue_i[0:0] $2\core_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -376997,82 +376170,82 @@ module \ti sync always update \core_issue_i $0\core_issue_i[0:0] end - attribute \src "libresoc.v:198848.3-198882.6" - process $proc$libresoc.v:198848$13393 + attribute \src "libresoc.v:198290.3-198324.6" + process $proc$libresoc.v:198290$13376 assign { } { } assign { } { } assign { } { } - assign $0\exec_fsm_state$next[0:0]$13394 $5\exec_fsm_state$next[0:0]$13399 - attribute \src "libresoc.v:198849.5-198849.29" + assign $0\exec_fsm_state$next[0:0]$13377 $5\exec_fsm_state$next[0:0]$13382 + attribute \src "libresoc.v:198291.5-198291.29" switch \initial - attribute \src "libresoc.v:198849.9-198849.17" + attribute \src "libresoc.v:198291.9-198291.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13395 $2\exec_fsm_state$next[0:0]$13396 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + assign $1\exec_fsm_state$next[0:0]$13378 $2\exec_fsm_state$next[0:0]$13379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\exec_fsm_state$next[0:0]$13396 1'1 + assign $2\exec_fsm_state$next[0:0]$13379 1'1 case - assign $2\exec_fsm_state$next[0:0]$13396 \exec_fsm_state + assign $2\exec_fsm_state$next[0:0]$13379 \exec_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13395 $3\exec_fsm_state$next[0:0]$13397 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" - switch \$256 + assign $1\exec_fsm_state$next[0:0]$13378 $3\exec_fsm_state$next[0:0]$13380 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" + switch \$258 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\exec_fsm_state$next[0:0]$13397 $4\exec_fsm_state$next[0:0]$13398 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" + assign $3\exec_fsm_state$next[0:0]$13380 $4\exec_fsm_state$next[0:0]$13381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\exec_fsm_state$next[0:0]$13398 1'0 + assign $4\exec_fsm_state$next[0:0]$13381 1'0 case - assign $4\exec_fsm_state$next[0:0]$13398 \exec_fsm_state + assign $4\exec_fsm_state$next[0:0]$13381 \exec_fsm_state end case - assign $3\exec_fsm_state$next[0:0]$13397 \exec_fsm_state + assign $3\exec_fsm_state$next[0:0]$13380 \exec_fsm_state end case - assign $1\exec_fsm_state$next[0:0]$13395 \exec_fsm_state + assign $1\exec_fsm_state$next[0:0]$13378 \exec_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\exec_fsm_state$next[0:0]$13399 1'0 + assign $5\exec_fsm_state$next[0:0]$13382 1'0 case - assign $5\exec_fsm_state$next[0:0]$13399 $1\exec_fsm_state$next[0:0]$13395 + assign $5\exec_fsm_state$next[0:0]$13382 $1\exec_fsm_state$next[0:0]$13378 end sync always - update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13394 + update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13377 end - attribute \src "libresoc.v:198883.3-198902.6" - process $proc$libresoc.v:198883$13400 + attribute \src "libresoc.v:198325.3-198344.6" + process $proc$libresoc.v:198325$13383 assign { } { } assign { } { } assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:198884.5-198884.29" + attribute \src "libresoc.v:198326.5-198326.29" switch \initial - attribute \src "libresoc.v:198884.9-198884.17" + attribute \src "libresoc.v:198326.9-198326.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 @@ -377081,8 +376254,8 @@ module \ti case 1'1 assign { } { } assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" - switch \$258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" + switch \$260 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -377096,18 +376269,18 @@ module \ti sync always update \exec_pc_valid_o $0\exec_pc_valid_o[0:0] end - attribute \src "libresoc.v:198903.3-198912.6" - process $proc$libresoc.v:198903$13401 + attribute \src "libresoc.v:198345.3-198354.6" + process $proc$libresoc.v:198345$13384 assign { } { } assign { } { } assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:198904.5-198904.29" + attribute \src "libresoc.v:198346.5-198346.29" switch \initial - attribute \src "libresoc.v:198904.9-198904.17" + attribute \src "libresoc.v:198346.9-198346.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377119,18 +376292,18 @@ module \ti sync always update \core_dmi__addr $0\core_dmi__addr[4:0] end - attribute \src "libresoc.v:198913.3-198922.6" - process $proc$libresoc.v:198913$13402 + attribute \src "libresoc.v:198355.3-198364.6" + process $proc$libresoc.v:198355$13385 assign { } { } assign { } { } assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:198914.5-198914.29" + attribute \src "libresoc.v:198356.5-198356.29" switch \initial - attribute \src "libresoc.v:198914.9-198914.17" + attribute \src "libresoc.v:198356.9-198356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377142,14 +376315,14 @@ module \ti sync always update \core_dmi__ren $0\core_dmi__ren[0:0] end - attribute \src "libresoc.v:198923.3-198931.6" - process $proc$libresoc.v:198923$13403 + attribute \src "libresoc.v:198365.3-198373.6" + process $proc$libresoc.v:198365$13386 assign { } { } assign { } { } - assign $0\d_reg_delay$next[0:0]$13404 $1\d_reg_delay$next[0:0]$13405 - attribute \src "libresoc.v:198924.5-198924.29" + assign $0\d_reg_delay$next[0:0]$13387 $1\d_reg_delay$next[0:0]$13388 + attribute \src "libresoc.v:198366.5-198366.29" switch \initial - attribute \src "libresoc.v:198924.9-198924.17" + attribute \src "libresoc.v:198366.9-198366.17" case 1'1 case end @@ -377158,25 +376331,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_reg_delay$next[0:0]$13405 1'0 + assign $1\d_reg_delay$next[0:0]$13388 1'0 case - assign $1\d_reg_delay$next[0:0]$13405 \dbg_d_gpr_req + assign $1\d_reg_delay$next[0:0]$13388 \dbg_d_gpr_req end sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13404 + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13387 end - attribute \src "libresoc.v:198932.3-198941.6" - process $proc$libresoc.v:198932$13406 + attribute \src "libresoc.v:198374.3-198383.6" + process $proc$libresoc.v:198374$13389 assign { } { } assign { } { } assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:198933.5-198933.29" + attribute \src "libresoc.v:198375.5-198375.29" switch \initial - attribute \src "libresoc.v:198933.9-198933.17" + attribute \src "libresoc.v:198375.9-198375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:987" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377188,18 +376361,18 @@ module \ti sync always update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end - attribute \src "libresoc.v:198942.3-198951.6" - process $proc$libresoc.v:198942$13407 + attribute \src "libresoc.v:198384.3-198393.6" + process $proc$libresoc.v:198384$13390 assign { } { } assign { } { } assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:198943.5-198943.29" + attribute \src "libresoc.v:198385.5-198385.29" switch \initial - attribute \src "libresoc.v:198943.9-198943.17" + attribute \src "libresoc.v:198385.9-198385.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:987" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377211,18 +376384,18 @@ module \ti sync always update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end - attribute \src "libresoc.v:198952.3-198961.6" - process $proc$libresoc.v:198952$13408 + attribute \src "libresoc.v:198394.3-198403.6" + process $proc$libresoc.v:198394$13391 assign { } { } assign { } { } assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:198953.5-198953.29" + attribute \src "libresoc.v:198395.5-198395.29" switch \initial - attribute \src "libresoc.v:198953.9-198953.17" + attribute \src "libresoc.v:198395.9-198395.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:963" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993" switch \dbg_d_cr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377234,14 +376407,14 @@ module \ti sync always update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] end - attribute \src "libresoc.v:198962.3-198970.6" - process $proc$libresoc.v:198962$13409 + attribute \src "libresoc.v:198404.3-198412.6" + process $proc$libresoc.v:198404$13392 assign { } { } assign { } { } - assign $0\d_cr_delay$next[0:0]$13410 $1\d_cr_delay$next[0:0]$13411 - attribute \src "libresoc.v:198963.5-198963.29" + assign $0\d_cr_delay$next[0:0]$13393 $1\d_cr_delay$next[0:0]$13394 + attribute \src "libresoc.v:198405.5-198405.29" switch \initial - attribute \src "libresoc.v:198963.9-198963.17" + attribute \src "libresoc.v:198405.9-198405.17" case 1'1 case end @@ -377250,48 +376423,48 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_cr_delay$next[0:0]$13411 1'0 + assign $1\d_cr_delay$next[0:0]$13394 1'0 case - assign $1\d_cr_delay$next[0:0]$13411 \dbg_d_cr_req + assign $1\d_cr_delay$next[0:0]$13394 \dbg_d_cr_req end sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13410 + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13393 end - attribute \src "libresoc.v:198971.3-198980.6" - process $proc$libresoc.v:198971$13412 + attribute \src "libresoc.v:198413.3-198422.6" + process $proc$libresoc.v:198413$13395 assign { } { } assign { } { } assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:198972.5-198972.29" + attribute \src "libresoc.v:198414.5-198414.29" switch \initial - attribute \src "libresoc.v:198972.9-198972.17" + attribute \src "libresoc.v:198414.9-198414.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:967" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:997" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_cr_data[63:0] \$260 + assign $1\dbg_d_cr_data[63:0] \$262 case assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end - attribute \src "libresoc.v:198981.3-198990.6" - process $proc$libresoc.v:198981$13413 + attribute \src "libresoc.v:198423.3-198432.6" + process $proc$libresoc.v:198423$13396 assign { } { } assign { } { } assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:198982.5-198982.29" + attribute \src "libresoc.v:198424.5-198424.29" switch \initial - attribute \src "libresoc.v:198982.9-198982.17" + attribute \src "libresoc.v:198424.9-198424.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:967" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:997" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377303,18 +376476,18 @@ module \ti sync always update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end - attribute \src "libresoc.v:198991.3-199000.6" - process $proc$libresoc.v:198991$13414 + attribute \src "libresoc.v:198433.3-198442.6" + process $proc$libresoc.v:198433$13397 assign { } { } assign { } { } assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:198992.5-198992.29" + attribute \src "libresoc.v:198434.5-198434.29" switch \initial - attribute \src "libresoc.v:198992.9-198992.17" + attribute \src "libresoc.v:198434.9-198434.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:973" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1003" switch \dbg_d_xer_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377326,14 +376499,14 @@ module \ti sync always update \core_full_rd__ren $0\core_full_rd__ren[2:0] end - attribute \src "libresoc.v:199001.3-199009.6" - process $proc$libresoc.v:199001$13415 + attribute \src "libresoc.v:198443.3-198451.6" + process $proc$libresoc.v:198443$13398 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$13416 $1\d_xer_delay$next[0:0]$13417 - attribute \src "libresoc.v:199002.5-199002.29" + assign $0\d_xer_delay$next[0:0]$13399 $1\d_xer_delay$next[0:0]$13400 + attribute \src "libresoc.v:198444.5-198444.29" switch \initial - attribute \src "libresoc.v:199002.9-199002.17" + attribute \src "libresoc.v:198444.9-198444.17" case 1'1 case end @@ -377342,48 +376515,48 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_xer_delay$next[0:0]$13417 1'0 + assign $1\d_xer_delay$next[0:0]$13400 1'0 case - assign $1\d_xer_delay$next[0:0]$13417 \dbg_d_xer_req + assign $1\d_xer_delay$next[0:0]$13400 \dbg_d_xer_req end sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13416 + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13399 end - attribute \src "libresoc.v:199010.3-199019.6" - process $proc$libresoc.v:199010$13418 + attribute \src "libresoc.v:198452.3-198461.6" + process $proc$libresoc.v:198452$13401 assign { } { } assign { } { } assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:199011.5-199011.29" + attribute \src "libresoc.v:198453.5-198453.29" switch \initial - attribute \src "libresoc.v:199011.9-199011.17" + attribute \src "libresoc.v:198453.9-198453.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1007" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_xer_data[63:0] \$262 + assign $1\dbg_d_xer_data[63:0] \$264 case assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end - attribute \src "libresoc.v:199020.3-199029.6" - process $proc$libresoc.v:199020$13419 + attribute \src "libresoc.v:198462.3-198471.6" + process $proc$libresoc.v:198462$13402 assign { } { } assign { } { } assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:199021.5-199021.29" + attribute \src "libresoc.v:198463.5-198463.29" switch \initial - attribute \src "libresoc.v:199021.9-199021.17" + attribute \src "libresoc.v:198463.9-198463.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1007" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377395,18 +376568,18 @@ module \ti sync always update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end - attribute \src "libresoc.v:199030.3-199048.6" - process $proc$libresoc.v:199030$13420 + attribute \src "libresoc.v:198472.3-198490.6" + process $proc$libresoc.v:198472$13403 assign { } { } assign { } { } assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "libresoc.v:199031.5-199031.29" + attribute \src "libresoc.v:198473.5-198473.29" switch \initial - attribute \src "libresoc.v:199031.9-199031.17" + attribute \src "libresoc.v:198473.9-198473.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -377425,18 +376598,18 @@ module \ti sync always update \core_issue__addr $0\core_issue__addr[2:0] end - attribute \src "libresoc.v:199049.3-199067.6" - process $proc$libresoc.v:199049$13421 + attribute \src "libresoc.v:198491.3-198509.6" + process $proc$libresoc.v:198491$13404 assign { } { } assign { } { } assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "libresoc.v:199050.5-199050.29" + attribute \src "libresoc.v:198492.5-198492.29" switch \initial - attribute \src "libresoc.v:199050.9-199050.17" + attribute \src "libresoc.v:198492.9-198492.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -377455,63 +376628,63 @@ module \ti sync always update \core_issue__ren $0\core_issue__ren[0:0] end - attribute \src "libresoc.v:199068.3-199095.6" - process $proc$libresoc.v:199068$13422 + attribute \src "libresoc.v:198510.3-198537.6" + process $proc$libresoc.v:198510$13405 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$13423 $2\fsm_state$next[1:0]$13425 - attribute \src "libresoc.v:199069.5-199069.29" + assign $0\fsm_state$next[1:0]$13406 $2\fsm_state$next[1:0]$13408 + attribute \src "libresoc.v:198511.5-198511.29" switch \initial - attribute \src "libresoc.v:199069.9-199069.17" + attribute \src "libresoc.v:198511.9-198511.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$13424 2'01 + assign $1\fsm_state$next[1:0]$13407 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$13424 2'10 + assign $1\fsm_state$next[1:0]$13407 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$13424 2'11 + assign $1\fsm_state$next[1:0]$13407 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fsm_state$next[1:0]$13424 2'00 + assign $1\fsm_state$next[1:0]$13407 2'00 case - assign $1\fsm_state$next[1:0]$13424 \fsm_state + assign $1\fsm_state$next[1:0]$13407 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$13425 2'00 + assign $2\fsm_state$next[1:0]$13408 2'00 case - assign $2\fsm_state$next[1:0]$13425 $1\fsm_state$next[1:0]$13424 + assign $2\fsm_state$next[1:0]$13408 $1\fsm_state$next[1:0]$13407 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$13423 + update \fsm_state$next $0\fsm_state$next[1:0]$13406 end - attribute \src "libresoc.v:199096.3-199110.6" - process $proc$libresoc.v:199096$13426 + attribute \src "libresoc.v:198538.3-198552.6" + process $proc$libresoc.v:198538$13409 assign { } { } assign { } { } assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:199097.5-199097.29" + attribute \src "libresoc.v:198539.5-198539.29" switch \initial - attribute \src "libresoc.v:199097.9-199097.17" + attribute \src "libresoc.v:198539.9-198539.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -377519,58 +376692,58 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\new_dec[63:0] \$264 [63:0] + assign $1\new_dec[63:0] \$266 [63:0] case assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_dec $0\new_dec[63:0] end - attribute \src "libresoc.v:199111.3-199133.6" - process $proc$libresoc.v:199111$13427 + attribute \src "libresoc.v:198553.3-198575.6" + process $proc$libresoc.v:198553$13410 assign { } { } assign { } { } - assign $0\core_issue__addr$13[2:0]$13428 $1\core_issue__addr$13[2:0]$13429 - attribute \src "libresoc.v:199112.5-199112.29" + assign $0\core_issue__addr$13[2:0]$13411 $1\core_issue__addr$13[2:0]$13412 + attribute \src "libresoc.v:198554.5-198554.29" switch \initial - attribute \src "libresoc.v:199112.9-199112.17" + attribute \src "libresoc.v:198554.9-198554.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $1\core_issue__addr$13[2:0]$13429 3'000 + assign $1\core_issue__addr$13[2:0]$13412 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_issue__addr$13[2:0]$13429 3'110 + assign $1\core_issue__addr$13[2:0]$13412 3'110 attribute \src "libresoc.v:0.0-0.0" case 2'10 - assign $1\core_issue__addr$13[2:0]$13429 3'000 + assign $1\core_issue__addr$13[2:0]$13412 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_issue__addr$13[2:0]$13429 3'111 + assign $1\core_issue__addr$13[2:0]$13412 3'111 case - assign $1\core_issue__addr$13[2:0]$13429 3'000 + assign $1\core_issue__addr$13[2:0]$13412 3'000 end sync always - update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13428 + update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13411 end - attribute \src "libresoc.v:199134.3-199156.6" - process $proc$libresoc.v:199134$13430 + attribute \src "libresoc.v:198576.3-198598.6" + process $proc$libresoc.v:198576$13413 assign { } { } assign { } { } assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "libresoc.v:199135.5-199135.29" + attribute \src "libresoc.v:198577.5-198577.29" switch \initial - attribute \src "libresoc.v:199135.9-199135.17" + attribute \src "libresoc.v:198577.9-198577.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -377592,18 +376765,18 @@ module \ti sync always update \core_issue__wen $0\core_issue__wen[0:0] end - attribute \src "libresoc.v:199157.3-199179.6" - process $proc$libresoc.v:199157$13431 + attribute \src "libresoc.v:198599.3-198621.6" + process $proc$libresoc.v:198599$13414 assign { } { } assign { } { } assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:199158.5-199158.29" + attribute \src "libresoc.v:198600.5-198600.29" switch \initial - attribute \src "libresoc.v:199158.9-199158.17" + attribute \src "libresoc.v:198600.9-198600.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -377625,54 +376798,54 @@ module \ti sync always update \core_issue__data_i $0\core_issue__data_i[63:0] end - attribute \src "libresoc.v:199180.3-199199.6" - process $proc$libresoc.v:199180$13432 + attribute \src "libresoc.v:198622.3-198641.6" + process $proc$libresoc.v:198622$13415 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$13433 $2\dec2_cur_dec$next[63:0]$13435 - attribute \src "libresoc.v:199181.5-199181.29" + assign $0\dec2_cur_dec$next[63:0]$13416 $2\dec2_cur_dec$next[63:0]$13418 + attribute \src "libresoc.v:198623.5-198623.29" switch \initial - attribute \src "libresoc.v:199181.9-199181.17" + attribute \src "libresoc.v:198623.9-198623.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $1\dec2_cur_dec$next[63:0]$13434 \dec2_cur_dec + assign $1\dec2_cur_dec$next[63:0]$13417 \dec2_cur_dec attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$13434 \new_dec + assign $1\dec2_cur_dec$next[63:0]$13417 \new_dec case - assign $1\dec2_cur_dec$next[63:0]$13434 \dec2_cur_dec + assign $1\dec2_cur_dec$next[63:0]$13417 \dec2_cur_dec end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$13435 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dec2_cur_dec$next[63:0]$13418 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dec2_cur_dec$next[63:0]$13435 $1\dec2_cur_dec$next[63:0]$13434 + assign $2\dec2_cur_dec$next[63:0]$13418 $1\dec2_cur_dec$next[63:0]$13417 end sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13433 + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13416 end - attribute \src "libresoc.v:199200.3-199222.6" - process $proc$libresoc.v:199200$13436 + attribute \src "libresoc.v:198642.3-198664.6" + process $proc$libresoc.v:198642$13419 assign { } { } assign { } { } assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:199201.5-199201.29" + attribute \src "libresoc.v:198643.5-198643.29" switch \initial - attribute \src "libresoc.v:199201.9-199201.17" + attribute \src "libresoc.v:198643.9-198643.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -377686,21 +376859,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\new_tb[63:0] \$267 [63:0] + assign $1\new_tb[63:0] \$269 [63:0] case assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_tb $0\new_tb[63:0] end - attribute \src "libresoc.v:199223.3-199231.6" - process $proc$libresoc.v:199223$13437 + attribute \src "libresoc.v:198665.3-198673.6" + process $proc$libresoc.v:198665$13420 assign { } { } assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$13438 $1\dbg_dmi_we_i$next[0:0]$13439 - attribute \src "libresoc.v:199224.5-199224.29" + assign $0\dbg_dmi_we_i$next[0:0]$13421 $1\dbg_dmi_we_i$next[0:0]$13422 + attribute \src "libresoc.v:198666.5-198666.29" switch \initial - attribute \src "libresoc.v:199224.9-199224.17" + attribute \src "libresoc.v:198666.9-198666.17" case 1'1 case end @@ -377709,21 +376882,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$13439 1'0 + assign $1\dbg_dmi_we_i$next[0:0]$13422 1'0 case - assign $1\dbg_dmi_we_i$next[0:0]$13439 \jtag_dmi0__we_i + assign $1\dbg_dmi_we_i$next[0:0]$13422 \jtag_dmi0__we_i end sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13438 + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13421 end - attribute \src "libresoc.v:199232.3-199240.6" - process $proc$libresoc.v:199232$13440 + attribute \src "libresoc.v:198674.3-198682.6" + process $proc$libresoc.v:198674$13423 assign { } { } assign { } { } - assign $0\pc_ok_delay$next[0:0]$13441 $1\pc_ok_delay$next[0:0]$13442 - attribute \src "libresoc.v:199233.5-199233.29" + assign $0\pc_ok_delay$next[0:0]$13424 $1\pc_ok_delay$next[0:0]$13425 + attribute \src "libresoc.v:198675.5-198675.29" switch \initial - attribute \src "libresoc.v:199233.9-199233.17" + attribute \src "libresoc.v:198675.9-198675.17" case 1'1 case end @@ -377732,26 +376905,26 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\pc_ok_delay$next[0:0]$13442 1'0 + assign $1\pc_ok_delay$next[0:0]$13425 1'0 case - assign $1\pc_ok_delay$next[0:0]$13442 \$38 + assign $1\pc_ok_delay$next[0:0]$13425 \$38 end sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13441 + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13424 end - attribute \src "libresoc.v:199241.3-199256.6" - process $proc$libresoc.v:199241$13443 + attribute \src "libresoc.v:198683.3-198698.6" + process $proc$libresoc.v:198683$13426 assign { } { } assign { } { } assign { } { } assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:199242.5-199242.29" + attribute \src "libresoc.v:198684.5-198684.29" switch \initial - attribute \src "libresoc.v:199242.9-199242.17" + attribute \src "libresoc.v:198684.9-198684.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377760,7 +376933,7 @@ module \ti case assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:73" switch \pc_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377772,18 +376945,18 @@ module \ti sync always update \pc $0\pc[63:0] end - attribute \src "libresoc.v:199257.3-199269.6" - process $proc$libresoc.v:199257$13444 + attribute \src "libresoc.v:198699.3-198711.6" + process $proc$libresoc.v:198699$13427 assign { } { } assign { } { } assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] - attribute \src "libresoc.v:199258.5-199258.29" + attribute \src "libresoc.v:198700.5-198700.29" switch \initial - attribute \src "libresoc.v:199258.9-199258.17" + attribute \src "libresoc.v:198700.9-198700.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377796,14 +376969,14 @@ module \ti sync always update \core_cia__ren $0\core_cia__ren[2:0] end - attribute \src "libresoc.v:199270.3-199278.6" - process $proc$libresoc.v:199270$13445 + attribute \src "libresoc.v:198712.3-198720.6" + process $proc$libresoc.v:198712$13428 assign { } { } assign { } { } - assign $0\svstate_ok_delay$next[0:0]$13446 $1\svstate_ok_delay$next[0:0]$13447 - attribute \src "libresoc.v:199271.5-199271.29" + assign $0\svstate_ok_delay$next[0:0]$13429 $1\svstate_ok_delay$next[0:0]$13430 + attribute \src "libresoc.v:198713.5-198713.29" switch \initial - attribute \src "libresoc.v:199271.9-199271.17" + attribute \src "libresoc.v:198713.9-198713.17" case 1'1 case end @@ -377812,26 +376985,26 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\svstate_ok_delay$next[0:0]$13447 1'0 + assign $1\svstate_ok_delay$next[0:0]$13430 1'0 case - assign $1\svstate_ok_delay$next[0:0]$13447 \$40 + assign $1\svstate_ok_delay$next[0:0]$13430 \$40 end sync always - update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13446 + update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13429 end - attribute \src "libresoc.v:199279.3-199294.6" - process $proc$libresoc.v:199279$13448 + attribute \src "libresoc.v:198721.3-198736.6" + process $proc$libresoc.v:198721$13431 assign { } { } assign { } { } assign { } { } assign $0\svstate[63:0] $2\svstate[63:0] - attribute \src "libresoc.v:199280.5-199280.29" + attribute \src "libresoc.v:198722.5-198722.29" switch \initial - attribute \src "libresoc.v:199280.9-199280.17" + attribute \src "libresoc.v:198722.9-198722.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377840,7 +377013,7 @@ module \ti case assign $1\svstate[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:73" switch \svstate_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377852,18 +377025,18 @@ module \ti sync always update \svstate $0\svstate[63:0] end - attribute \src "libresoc.v:199295.3-199307.6" - process $proc$libresoc.v:199295$13449 + attribute \src "libresoc.v:198737.3-198749.6" + process $proc$libresoc.v:198737$13432 assign { } { } assign { } { } assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] - attribute \src "libresoc.v:199296.5-199296.29" + attribute \src "libresoc.v:198738.5-198738.29" switch \initial - attribute \src "libresoc.v:199296.9-199296.17" + attribute \src "libresoc.v:198738.9-198738.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377876,24 +377049,24 @@ module \ti sync always update \core_sv__ren $0\core_sv__ren[2:0] end - attribute \src "libresoc.v:199308.3-199387.6" - process $proc$libresoc.v:199308$13450 + attribute \src "libresoc.v:198750.3-198837.6" + process $proc$libresoc.v:198750$13433 assign { } { } assign { } { } assign $0\core_wen[2:0] $1\core_wen[2:0] - attribute \src "libresoc.v:199309.5-199309.29" + attribute \src "libresoc.v:198751.5-198751.29" switch \initial - attribute \src "libresoc.v:199309.9-199309.17" + attribute \src "libresoc.v:198751.9-198751.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_wen[2:0] $2\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377902,7 +377075,7 @@ module \ti case assign { } { } assign $2\core_wen[2:0] $3\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377916,13 +377089,13 @@ module \ti case 3'001 assign { } { } assign $1\core_wen[2:0] $4\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:555" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_wen[2:0] $5\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377941,25 +377114,31 @@ module \ti case 3'100 assign $1\core_wen[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\core_wen[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'110 + assign $1\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 assign { } { } assign $1\core_wen[2:0] $6\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_wen[2:0] $7\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_wen[2:0] $8\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" switch { \$64 \$60 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -377978,7 +377157,7 @@ module \ti case assign { } { } assign $6\core_wen[2:0] $9\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:712" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -377994,24 +377173,24 @@ module \ti sync always update \core_wen $0\core_wen[2:0] end - attribute \src "libresoc.v:199388.3-199467.6" - process $proc$libresoc.v:199388$13451 + attribute \src "libresoc.v:198838.3-198925.6" + process $proc$libresoc.v:198838$13434 assign { } { } assign { } { } assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "libresoc.v:199389.5-199389.29" + attribute \src "libresoc.v:198839.5-198839.29" switch \initial - attribute \src "libresoc.v:199389.9-199389.17" + attribute \src "libresoc.v:198839.9-198839.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_data_i[63:0] $2\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378020,7 +377199,7 @@ module \ti case assign { } { } assign $2\core_data_i[63:0] $3\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378034,13 +377213,13 @@ module \ti case 3'001 assign { } { } assign $1\core_data_i[63:0] $4\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:555" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_data_i[63:0] $5\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" switch \$74 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378059,25 +377238,31 @@ module \ti case 3'100 assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'110 + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 assign { } { } assign $1\core_data_i[63:0] $6\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$80 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_data_i[63:0] $7\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_data_i[63:0] $8\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" switch { \$86 \$82 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -378096,7 +377281,7 @@ module \ti case assign { } { } assign $6\core_data_i[63:0] $9\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:712" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378112,24 +377297,24 @@ module \ti sync always update \core_data_i $0\core_data_i[63:0] end - attribute \src "libresoc.v:199468.3-199483.6" - process $proc$libresoc.v:199468$13452 + attribute \src "libresoc.v:198926.3-198941.6" + process $proc$libresoc.v:198926$13435 assign { } { } assign { } { } assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] - attribute \src "libresoc.v:199469.5-199469.29" + attribute \src "libresoc.v:198927.5-198927.29" switch \initial - attribute \src "libresoc.v:199469.9-199469.17" + attribute \src "libresoc.v:198927.9-198927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378144,14 +377329,14 @@ module \ti sync always update \core_msr__ren $0\core_msr__ren[2:0] end - attribute \src "libresoc.v:199484.3-199492.6" - process $proc$libresoc.v:199484$13453 + attribute \src "libresoc.v:198942.3-198950.6" + process $proc$libresoc.v:198942$13436 assign { } { } assign { } { } - assign $0\dbg_dmi_din$next[63:0]$13454 $1\dbg_dmi_din$next[63:0]$13455 - attribute \src "libresoc.v:199485.5-199485.29" + assign $0\dbg_dmi_din$next[63:0]$13437 $1\dbg_dmi_din$next[63:0]$13438 + attribute \src "libresoc.v:198943.5-198943.29" switch \initial - attribute \src "libresoc.v:199485.9-199485.17" + attribute \src "libresoc.v:198943.9-198943.17" case 1'1 case end @@ -378160,25 +377345,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_din$next[63:0]$13455 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbg_dmi_din$next[63:0]$13438 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\dbg_dmi_din$next[63:0]$13455 \jtag_dmi0__din + assign $1\dbg_dmi_din$next[63:0]$13438 \jtag_dmi0__din end sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13454 + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13437 end - attribute \src "libresoc.v:199493.3-199503.6" - process $proc$libresoc.v:199493$13456 + attribute \src "libresoc.v:198951.3-198961.6" + process $proc$libresoc.v:198951$13439 assign { } { } assign { } { } assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:199494.5-199494.29" + attribute \src "libresoc.v:198952.5-198952.29" switch \initial - attribute \src "libresoc.v:199494.9-199494.17" + attribute \src "libresoc.v:198952.9-198952.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -378190,24 +377375,24 @@ module \ti sync always update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] end - attribute \src "libresoc.v:199504.3-199519.6" - process $proc$libresoc.v:199504$13457 + attribute \src "libresoc.v:198962.3-198977.6" + process $proc$libresoc.v:198962$13440 assign { } { } assign { } { } assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:199505.5-199505.29" + attribute \src "libresoc.v:198963.5-198963.29" switch \initial - attribute \src "libresoc.v:199505.9-199505.17" + attribute \src "libresoc.v:198963.9-198963.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378222,14 +377407,14 @@ module \ti sync always update \imem_a_pc_i $0\imem_a_pc_i[47:0] end - attribute \src "libresoc.v:199520.3-199528.6" - process $proc$libresoc.v:199520$13458 + attribute \src "libresoc.v:198978.3-198986.6" + process $proc$libresoc.v:198978$13441 assign { } { } assign { } { } - assign $0\jtag_dmi0__ack_o$next[0:0]$13459 $1\jtag_dmi0__ack_o$next[0:0]$13460 - attribute \src "libresoc.v:199521.5-199521.29" + assign $0\jtag_dmi0__ack_o$next[0:0]$13442 $1\jtag_dmi0__ack_o$next[0:0]$13443 + attribute \src "libresoc.v:198979.5-198979.29" switch \initial - attribute \src "libresoc.v:199521.9-199521.17" + attribute \src "libresoc.v:198979.9-198979.17" case 1'1 case end @@ -378238,31 +377423,31 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__ack_o$next[0:0]$13460 1'0 + assign $1\jtag_dmi0__ack_o$next[0:0]$13443 1'0 case - assign $1\jtag_dmi0__ack_o$next[0:0]$13460 \dbg_dmi_ack_o + assign $1\jtag_dmi0__ack_o$next[0:0]$13443 \dbg_dmi_ack_o end sync always - update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13459 + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13442 end - attribute \src "libresoc.v:199529.3-199562.6" - process $proc$libresoc.v:199529$13461 + attribute \src "libresoc.v:198987.3-199020.6" + process $proc$libresoc.v:198987$13444 assign { } { } assign { } { } assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199530.5-199530.29" + attribute \src "libresoc.v:198988.5-198988.29" switch \initial - attribute \src "libresoc.v:199530.9-199530.17" + attribute \src "libresoc.v:198988.9-198988.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378275,7 +377460,7 @@ module \ti case 2'01 assign { } { } assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378288,7 +377473,7 @@ module \ti case 2'11 assign { } { } assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378303,24 +377488,24 @@ module \ti sync always update \imem_a_valid_i $0\imem_a_valid_i[0:0] end - attribute \src "libresoc.v:199563.3-199596.6" - process $proc$libresoc.v:199563$13462 + attribute \src "libresoc.v:199021.3-199054.6" + process $proc$libresoc.v:199021$13445 assign { } { } assign { } { } assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:199564.5-199564.29" + attribute \src "libresoc.v:199022.5-199022.29" switch \initial - attribute \src "libresoc.v:199564.9-199564.17" + attribute \src "libresoc.v:199022.9-199022.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378333,7 +377518,7 @@ module \ti case 2'01 assign { } { } assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378346,7 +377531,7 @@ module \ti case 2'11 assign { } { } assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378361,50 +377546,50 @@ module \ti sync always update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "libresoc.v:199597.3-199617.6" - process $proc$libresoc.v:199597$13463 + attribute \src "libresoc.v:199055.3-199075.6" + process $proc$libresoc.v:199055$13446 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_pc$next[63:0]$13464 $3\dec2_cur_pc$next[63:0]$13467 - attribute \src "libresoc.v:199598.5-199598.29" + assign $0\dec2_cur_pc$next[63:0]$13447 $3\dec2_cur_pc$next[63:0]$13450 + attribute \src "libresoc.v:199056.5-199056.29" switch \initial - attribute \src "libresoc.v:199598.9-199598.17" + attribute \src "libresoc.v:199056.9-199056.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$13465 $2\dec2_cur_pc$next[63:0]$13466 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" + assign $1\dec2_cur_pc$next[63:0]$13448 $2\dec2_cur_pc$next[63:0]$13449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_pc$next[63:0]$13466 \pc + assign $2\dec2_cur_pc$next[63:0]$13449 \pc case - assign $2\dec2_cur_pc$next[63:0]$13466 \dec2_cur_pc + assign $2\dec2_cur_pc$next[63:0]$13449 \dec2_cur_pc end case - assign $1\dec2_cur_pc$next[63:0]$13465 \dec2_cur_pc + assign $1\dec2_cur_pc$next[63:0]$13448 \dec2_cur_pc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$13467 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_pc$next[63:0]$13450 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_pc$next[63:0]$13467 $1\dec2_cur_pc$next[63:0]$13465 + assign $3\dec2_cur_pc$next[63:0]$13450 $1\dec2_cur_pc$next[63:0]$13448 end sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13464 + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13447 end - attribute \src "libresoc.v:199618.3-199656.6" - process $proc$libresoc.v:199618$13468 + attribute \src "libresoc.v:199076.3-199114.6" + process $proc$libresoc.v:199076$13451 assign { } { } assign { } { } assign { } { } @@ -378429,19 +377614,19 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\cur_cur_dststep$next[6:0]$13469 $4\cur_cur_dststep$next[6:0]$13493 - assign $0\cur_cur_maxvl$next[6:0]$13470 $4\cur_cur_maxvl$next[6:0]$13494 - assign $0\cur_cur_srcstep$next[6:0]$13471 $4\cur_cur_srcstep$next[6:0]$13495 - assign $0\cur_cur_subvl$next[1:0]$13472 $4\cur_cur_subvl$next[1:0]$13496 - assign $0\cur_cur_svstep$next[1:0]$13473 $4\cur_cur_svstep$next[1:0]$13497 - assign $0\cur_cur_vl$next[6:0]$13474 $4\cur_cur_vl$next[6:0]$13498 - attribute \src "libresoc.v:199619.5-199619.29" + assign $0\cur_cur_dststep$next[6:0]$13452 $4\cur_cur_dststep$next[6:0]$13476 + assign $0\cur_cur_maxvl$next[6:0]$13453 $4\cur_cur_maxvl$next[6:0]$13477 + assign $0\cur_cur_srcstep$next[6:0]$13454 $4\cur_cur_srcstep$next[6:0]$13478 + assign $0\cur_cur_subvl$next[1:0]$13455 $4\cur_cur_subvl$next[1:0]$13479 + assign $0\cur_cur_svstep$next[1:0]$13456 $4\cur_cur_svstep$next[1:0]$13480 + assign $0\cur_cur_vl$next[6:0]$13457 $4\cur_cur_vl$next[6:0]$13481 + attribute \src "libresoc.v:199077.5-199077.29" switch \initial - attribute \src "libresoc.v:199619.9-199619.17" + attribute \src "libresoc.v:199077.9-199077.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -378451,13 +377636,13 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\cur_cur_dststep$next[6:0]$13475 $2\cur_cur_dststep$next[6:0]$13481 - assign $1\cur_cur_maxvl$next[6:0]$13476 $2\cur_cur_maxvl$next[6:0]$13482 - assign $1\cur_cur_srcstep$next[6:0]$13477 $2\cur_cur_srcstep$next[6:0]$13483 - assign $1\cur_cur_subvl$next[1:0]$13478 $2\cur_cur_subvl$next[1:0]$13484 - assign $1\cur_cur_svstep$next[1:0]$13479 $2\cur_cur_svstep$next[1:0]$13485 - assign $1\cur_cur_vl$next[6:0]$13480 $2\cur_cur_vl$next[6:0]$13486 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" + assign $1\cur_cur_dststep$next[6:0]$13458 $2\cur_cur_dststep$next[6:0]$13464 + assign $1\cur_cur_maxvl$next[6:0]$13459 $2\cur_cur_maxvl$next[6:0]$13465 + assign $1\cur_cur_srcstep$next[6:0]$13460 $2\cur_cur_srcstep$next[6:0]$13466 + assign $1\cur_cur_subvl$next[1:0]$13461 $2\cur_cur_subvl$next[1:0]$13467 + assign $1\cur_cur_svstep$next[1:0]$13462 $2\cur_cur_svstep$next[1:0]$13468 + assign $1\cur_cur_vl$next[6:0]$13463 $2\cur_cur_vl$next[6:0]$13469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378467,24 +377652,24 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\cur_cur_maxvl$next[6:0]$13482 $2\cur_cur_vl$next[6:0]$13486 $2\cur_cur_srcstep$next[6:0]$13483 $2\cur_cur_dststep$next[6:0]$13481 $2\cur_cur_subvl$next[1:0]$13484 $2\cur_cur_svstep$next[1:0]$13485 } \svstate [31:0] + assign { $2\cur_cur_maxvl$next[6:0]$13465 $2\cur_cur_vl$next[6:0]$13469 $2\cur_cur_srcstep$next[6:0]$13466 $2\cur_cur_dststep$next[6:0]$13464 $2\cur_cur_subvl$next[1:0]$13467 $2\cur_cur_svstep$next[1:0]$13468 } \svstate [31:0] case - assign $2\cur_cur_dststep$next[6:0]$13481 \cur_cur_dststep - assign $2\cur_cur_maxvl$next[6:0]$13482 \cur_cur_maxvl - assign $2\cur_cur_srcstep$next[6:0]$13483 \cur_cur_srcstep - assign $2\cur_cur_subvl$next[1:0]$13484 \cur_cur_subvl - assign $2\cur_cur_svstep$next[1:0]$13485 \cur_cur_svstep - assign $2\cur_cur_vl$next[6:0]$13486 \cur_cur_vl + assign $2\cur_cur_dststep$next[6:0]$13464 \cur_cur_dststep + assign $2\cur_cur_maxvl$next[6:0]$13465 \cur_cur_maxvl + assign $2\cur_cur_srcstep$next[6:0]$13466 \cur_cur_srcstep + assign $2\cur_cur_subvl$next[1:0]$13467 \cur_cur_subvl + assign $2\cur_cur_svstep$next[1:0]$13468 \cur_cur_svstep + assign $2\cur_cur_vl$next[6:0]$13469 \cur_cur_vl end case - assign $1\cur_cur_dststep$next[6:0]$13475 \cur_cur_dststep - assign $1\cur_cur_maxvl$next[6:0]$13476 \cur_cur_maxvl - assign $1\cur_cur_srcstep$next[6:0]$13477 \cur_cur_srcstep - assign $1\cur_cur_subvl$next[1:0]$13478 \cur_cur_subvl - assign $1\cur_cur_svstep$next[1:0]$13479 \cur_cur_svstep - assign $1\cur_cur_vl$next[6:0]$13480 \cur_cur_vl + assign $1\cur_cur_dststep$next[6:0]$13458 \cur_cur_dststep + assign $1\cur_cur_maxvl$next[6:0]$13459 \cur_cur_maxvl + assign $1\cur_cur_srcstep$next[6:0]$13460 \cur_cur_srcstep + assign $1\cur_cur_subvl$next[1:0]$13461 \cur_cur_subvl + assign $1\cur_cur_svstep$next[1:0]$13462 \cur_cur_svstep + assign $1\cur_cur_vl$next[6:0]$13463 \cur_cur_vl end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:722" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378494,14 +377679,14 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $3\cur_cur_maxvl$next[6:0]$13488 $3\cur_cur_vl$next[6:0]$13492 $3\cur_cur_srcstep$next[6:0]$13489 $3\cur_cur_dststep$next[6:0]$13487 $3\cur_cur_subvl$next[1:0]$13490 $3\cur_cur_svstep$next[1:0]$13491 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } + assign { $3\cur_cur_maxvl$next[6:0]$13471 $3\cur_cur_vl$next[6:0]$13475 $3\cur_cur_srcstep$next[6:0]$13472 $3\cur_cur_dststep$next[6:0]$13470 $3\cur_cur_subvl$next[1:0]$13473 $3\cur_cur_svstep$next[1:0]$13474 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } case - assign $3\cur_cur_dststep$next[6:0]$13487 $1\cur_cur_dststep$next[6:0]$13475 - assign $3\cur_cur_maxvl$next[6:0]$13488 $1\cur_cur_maxvl$next[6:0]$13476 - assign $3\cur_cur_srcstep$next[6:0]$13489 $1\cur_cur_srcstep$next[6:0]$13477 - assign $3\cur_cur_subvl$next[1:0]$13490 $1\cur_cur_subvl$next[1:0]$13478 - assign $3\cur_cur_svstep$next[1:0]$13491 $1\cur_cur_svstep$next[1:0]$13479 - assign $3\cur_cur_vl$next[6:0]$13492 $1\cur_cur_vl$next[6:0]$13480 + assign $3\cur_cur_dststep$next[6:0]$13470 $1\cur_cur_dststep$next[6:0]$13458 + assign $3\cur_cur_maxvl$next[6:0]$13471 $1\cur_cur_maxvl$next[6:0]$13459 + assign $3\cur_cur_srcstep$next[6:0]$13472 $1\cur_cur_srcstep$next[6:0]$13460 + assign $3\cur_cur_subvl$next[1:0]$13473 $1\cur_cur_subvl$next[1:0]$13461 + assign $3\cur_cur_svstep$next[1:0]$13474 $1\cur_cur_svstep$next[1:0]$13462 + assign $3\cur_cur_vl$next[6:0]$13475 $1\cur_cur_vl$next[6:0]$13463 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -378513,91 +377698,91 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $4\cur_cur_svstep$next[1:0]$13497 2'00 - assign $4\cur_cur_subvl$next[1:0]$13496 2'00 - assign $4\cur_cur_dststep$next[6:0]$13493 7'0000000 - assign $4\cur_cur_srcstep$next[6:0]$13495 7'0000000 - assign $4\cur_cur_vl$next[6:0]$13498 7'0000000 - assign $4\cur_cur_maxvl$next[6:0]$13494 7'0000000 + assign $4\cur_cur_svstep$next[1:0]$13480 2'00 + assign $4\cur_cur_subvl$next[1:0]$13479 2'00 + assign $4\cur_cur_dststep$next[6:0]$13476 7'0000000 + assign $4\cur_cur_srcstep$next[6:0]$13478 7'0000000 + assign $4\cur_cur_vl$next[6:0]$13481 7'0000000 + assign $4\cur_cur_maxvl$next[6:0]$13477 7'0000000 case - assign $4\cur_cur_dststep$next[6:0]$13493 $3\cur_cur_dststep$next[6:0]$13487 - assign $4\cur_cur_maxvl$next[6:0]$13494 $3\cur_cur_maxvl$next[6:0]$13488 - assign $4\cur_cur_srcstep$next[6:0]$13495 $3\cur_cur_srcstep$next[6:0]$13489 - assign $4\cur_cur_subvl$next[1:0]$13496 $3\cur_cur_subvl$next[1:0]$13490 - assign $4\cur_cur_svstep$next[1:0]$13497 $3\cur_cur_svstep$next[1:0]$13491 - assign $4\cur_cur_vl$next[6:0]$13498 $3\cur_cur_vl$next[6:0]$13492 + assign $4\cur_cur_dststep$next[6:0]$13476 $3\cur_cur_dststep$next[6:0]$13470 + assign $4\cur_cur_maxvl$next[6:0]$13477 $3\cur_cur_maxvl$next[6:0]$13471 + assign $4\cur_cur_srcstep$next[6:0]$13478 $3\cur_cur_srcstep$next[6:0]$13472 + assign $4\cur_cur_subvl$next[1:0]$13479 $3\cur_cur_subvl$next[1:0]$13473 + assign $4\cur_cur_svstep$next[1:0]$13480 $3\cur_cur_svstep$next[1:0]$13474 + assign $4\cur_cur_vl$next[6:0]$13481 $3\cur_cur_vl$next[6:0]$13475 end sync always - update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13469 - update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13470 - update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13471 - update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13472 - update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13473 - update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13474 + update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13452 + update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13453 + update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13454 + update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13455 + update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13456 + update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13457 end - attribute \src "libresoc.v:199657.3-199686.6" - process $proc$libresoc.v:199657$13499 + attribute \src "libresoc.v:199115.3-199144.6" + process $proc$libresoc.v:199115$13482 assign { } { } assign { } { } assign { } { } - assign $0\msr_read$next[0:0]$13500 $4\msr_read$next[0:0]$13504 - attribute \src "libresoc.v:199658.5-199658.29" + assign $0\msr_read$next[0:0]$13483 $4\msr_read$next[0:0]$13487 + attribute \src "libresoc.v:199116.5-199116.29" switch \initial - attribute \src "libresoc.v:199658.9-199658.17" + attribute \src "libresoc.v:199116.9-199116.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\msr_read$next[0:0]$13501 $2\msr_read$next[0:0]$13502 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" + assign $1\msr_read$next[0:0]$13484 $2\msr_read$next[0:0]$13485 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_read$next[0:0]$13502 1'0 + assign $2\msr_read$next[0:0]$13485 1'0 case - assign $2\msr_read$next[0:0]$13502 \msr_read + assign $2\msr_read$next[0:0]$13485 \msr_read end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\msr_read$next[0:0]$13501 $3\msr_read$next[0:0]$13503 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" + assign $1\msr_read$next[0:0]$13484 $3\msr_read$next[0:0]$13486 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" switch \$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr_read$next[0:0]$13503 1'1 + assign $3\msr_read$next[0:0]$13486 1'1 case - assign $3\msr_read$next[0:0]$13503 \msr_read + assign $3\msr_read$next[0:0]$13486 \msr_read end case - assign $1\msr_read$next[0:0]$13501 \msr_read + assign $1\msr_read$next[0:0]$13484 \msr_read end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr_read$next[0:0]$13504 1'1 + assign $4\msr_read$next[0:0]$13487 1'1 case - assign $4\msr_read$next[0:0]$13504 $1\msr_read$next[0:0]$13501 + assign $4\msr_read$next[0:0]$13487 $1\msr_read$next[0:0]$13484 end sync always - update \msr_read$next $0\msr_read$next[0:0]$13500 + update \msr_read$next $0\msr_read$next[0:0]$13483 end - attribute \src "libresoc.v:199687.3-199695.6" - process $proc$libresoc.v:199687$13505 + attribute \src "libresoc.v:199145.3-199153.6" + process $proc$libresoc.v:199145$13488 assign { } { } assign { } { } - assign $0\jtag_dmi0__dout$next[63:0]$13506 $1\jtag_dmi0__dout$next[63:0]$13507 - attribute \src "libresoc.v:199688.5-199688.29" + assign $0\jtag_dmi0__dout$next[63:0]$13489 $1\jtag_dmi0__dout$next[63:0]$13490 + attribute \src "libresoc.v:199146.5-199146.29" switch \initial - attribute \src "libresoc.v:199688.9-199688.17" + attribute \src "libresoc.v:199146.9-199146.17" case 1'1 case end @@ -378606,239 +377791,239 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__dout$next[63:0]$13507 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_dmi0__dout$next[63:0]$13490 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\jtag_dmi0__dout$next[63:0]$13507 \dbg_dmi_dout + assign $1\jtag_dmi0__dout$next[63:0]$13490 \dbg_dmi_dout end sync always - update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13506 + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13489 end - attribute \src "libresoc.v:199696.3-199749.6" - process $proc$libresoc.v:199696$13508 + attribute \src "libresoc.v:199154.3-199207.6" + process $proc$libresoc.v:199154$13491 assign { } { } assign { } { } assign { } { } - assign $0\fetch_fsm_state$next[1:0]$13509 $6\fetch_fsm_state$next[1:0]$13515 - attribute \src "libresoc.v:199697.5-199697.29" + assign $0\fetch_fsm_state$next[1:0]$13492 $6\fetch_fsm_state$next[1:0]$13498 + attribute \src "libresoc.v:199155.5-199155.29" switch \initial - attribute \src "libresoc.v:199697.9-199697.17" + attribute \src "libresoc.v:199155.9-199155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13510 $2\fetch_fsm_state$next[1:0]$13511 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" + assign $1\fetch_fsm_state$next[1:0]$13493 $2\fetch_fsm_state$next[1:0]$13494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fetch_fsm_state$next[1:0]$13511 2'01 + assign $2\fetch_fsm_state$next[1:0]$13494 2'01 case - assign $2\fetch_fsm_state$next[1:0]$13511 \fetch_fsm_state + assign $2\fetch_fsm_state$next[1:0]$13494 \fetch_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13510 $3\fetch_fsm_state$next[1:0]$13512 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + assign $1\fetch_fsm_state$next[1:0]$13493 $3\fetch_fsm_state$next[1:0]$13495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\fetch_fsm_state$next[1:0]$13512 \fetch_fsm_state + assign $3\fetch_fsm_state$next[1:0]$13495 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\fetch_fsm_state$next[1:0]$13512 2'10 + assign $3\fetch_fsm_state$next[1:0]$13495 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13510 $4\fetch_fsm_state$next[1:0]$13513 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" + assign $1\fetch_fsm_state$next[1:0]$13493 $4\fetch_fsm_state$next[1:0]$13496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\fetch_fsm_state$next[1:0]$13513 \fetch_fsm_state + assign $4\fetch_fsm_state$next[1:0]$13496 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\fetch_fsm_state$next[1:0]$13513 2'10 + assign $4\fetch_fsm_state$next[1:0]$13496 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13510 $5\fetch_fsm_state$next[1:0]$13514 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:377" + assign $1\fetch_fsm_state$next[1:0]$13493 $5\fetch_fsm_state$next[1:0]$13497 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385" switch \fetch_insn_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fetch_fsm_state$next[1:0]$13514 2'00 + assign $5\fetch_fsm_state$next[1:0]$13497 2'00 case - assign $5\fetch_fsm_state$next[1:0]$13514 \fetch_fsm_state + assign $5\fetch_fsm_state$next[1:0]$13497 \fetch_fsm_state end case - assign $1\fetch_fsm_state$next[1:0]$13510 \fetch_fsm_state + assign $1\fetch_fsm_state$next[1:0]$13493 \fetch_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fetch_fsm_state$next[1:0]$13515 2'00 + assign $6\fetch_fsm_state$next[1:0]$13498 2'00 case - assign $6\fetch_fsm_state$next[1:0]$13515 $1\fetch_fsm_state$next[1:0]$13510 + assign $6\fetch_fsm_state$next[1:0]$13498 $1\fetch_fsm_state$next[1:0]$13493 end sync always - update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13509 + update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13492 end - attribute \src "libresoc.v:199750.3-199774.6" - process $proc$libresoc.v:199750$13516 + attribute \src "libresoc.v:199208.3-199232.6" + process $proc$libresoc.v:199208$13499 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_msr$next[63:0]$13517 $3\dec2_cur_msr$next[63:0]$13520 - attribute \src "libresoc.v:199751.5-199751.29" + assign $0\dec2_cur_msr$next[63:0]$13500 $3\dec2_cur_msr$next[63:0]$13503 + attribute \src "libresoc.v:199209.5-199209.29" switch \initial - attribute \src "libresoc.v:199751.9-199751.17" + attribute \src "libresoc.v:199209.9-199209.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $1\dec2_cur_msr$next[63:0]$13518 \dec2_cur_msr + assign $1\dec2_cur_msr$next[63:0]$13501 \dec2_cur_msr attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$13518 $2\dec2_cur_msr$next[63:0]$13519 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" + assign $1\dec2_cur_msr$next[63:0]$13501 $2\dec2_cur_msr$next[63:0]$13502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" switch \$90 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_msr$next[63:0]$13519 \core_msr__data_o + assign $2\dec2_cur_msr$next[63:0]$13502 \core_msr__data_o case - assign $2\dec2_cur_msr$next[63:0]$13519 \dec2_cur_msr + assign $2\dec2_cur_msr$next[63:0]$13502 \dec2_cur_msr end case - assign $1\dec2_cur_msr$next[63:0]$13518 \dec2_cur_msr + assign $1\dec2_cur_msr$next[63:0]$13501 \dec2_cur_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$13520 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_msr$next[63:0]$13503 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_msr$next[63:0]$13520 $1\dec2_cur_msr$next[63:0]$13518 + assign $3\dec2_cur_msr$next[63:0]$13503 $1\dec2_cur_msr$next[63:0]$13501 end sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13517 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13500 end - attribute \src "libresoc.v:199775.3-199797.6" - process $proc$libresoc.v:199775$13521 + attribute \src "libresoc.v:199233.3-199255.6" + process $proc$libresoc.v:199233$13504 assign { } { } assign { } { } - assign $0\nia$next[63:0]$13522 $1\nia$next[63:0]$13523 - attribute \src "libresoc.v:199776.5-199776.29" + assign $0\nia$next[63:0]$13505 $1\nia$next[63:0]$13506 + attribute \src "libresoc.v:199234.5-199234.29" switch \initial - attribute \src "libresoc.v:199776.9-199776.17" + attribute \src "libresoc.v:199234.9-199234.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $1\nia$next[63:0]$13523 \nia + assign $1\nia$next[63:0]$13506 \nia attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\nia$next[63:0]$13523 $2\nia$next[63:0]$13524 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + assign $1\nia$next[63:0]$13506 $2\nia$next[63:0]$13507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\nia$next[63:0]$13524 \nia + assign $2\nia$next[63:0]$13507 \nia attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\nia$next[63:0]$13524 \$92 [63:0] + assign $2\nia$next[63:0]$13507 \$92 [63:0] end case - assign $1\nia$next[63:0]$13523 \nia + assign $1\nia$next[63:0]$13506 \nia end sync always - update \nia$next $0\nia$next[63:0]$13522 + update \nia$next $0\nia$next[63:0]$13505 end - attribute \src "libresoc.v:199798.3-199832.6" - process $proc$libresoc.v:199798$13525 + attribute \src "libresoc.v:199256.3-199290.6" + process $proc$libresoc.v:199256$13508 assign { } { } assign { } { } - assign $0\dec2_raw_opcode_in$next[31:0]$13526 $1\dec2_raw_opcode_in$next[31:0]$13527 - attribute \src "libresoc.v:199799.5-199799.29" + assign $0\dec2_raw_opcode_in$next[31:0]$13509 $1\dec2_raw_opcode_in$next[31:0]$13510 + attribute \src "libresoc.v:199257.5-199257.29" switch \initial - attribute \src "libresoc.v:199799.9-199799.17" + attribute \src "libresoc.v:199257.9-199257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $1\dec2_raw_opcode_in$next[31:0]$13527 \dec2_raw_opcode_in + assign $1\dec2_raw_opcode_in$next[31:0]$13510 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13527 $2\dec2_raw_opcode_in$next[31:0]$13528 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + assign $1\dec2_raw_opcode_in$next[31:0]$13510 $2\dec2_raw_opcode_in$next[31:0]$13511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\dec2_raw_opcode_in$next[31:0]$13528 \dec2_raw_opcode_in + assign $2\dec2_raw_opcode_in$next[31:0]$13511 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dec2_raw_opcode_in$next[31:0]$13528 \$95 + assign $2\dec2_raw_opcode_in$next[31:0]$13511 \$95 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13527 $3\dec2_raw_opcode_in$next[31:0]$13529 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" + assign $1\dec2_raw_opcode_in$next[31:0]$13510 $3\dec2_raw_opcode_in$next[31:0]$13512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\dec2_raw_opcode_in$next[31:0]$13529 \dec2_raw_opcode_in + assign $3\dec2_raw_opcode_in$next[31:0]$13512 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\dec2_raw_opcode_in$next[31:0]$13529 \$99 + assign $3\dec2_raw_opcode_in$next[31:0]$13512 \$99 end case - assign $1\dec2_raw_opcode_in$next[31:0]$13527 \dec2_raw_opcode_in + assign $1\dec2_raw_opcode_in$next[31:0]$13510 \dec2_raw_opcode_in end sync always - update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13526 + update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13509 end - attribute \src "libresoc.v:199833.3-199855.6" - process $proc$libresoc.v:199833$13530 + attribute \src "libresoc.v:199291.3-199313.6" + process $proc$libresoc.v:199291$13513 assign { } { } assign { } { } assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:199834.5-199834.29" + attribute \src "libresoc.v:199292.5-199292.29" switch \initial - attribute \src "libresoc.v:199834.9-199834.17" + attribute \src "libresoc.v:199292.9-199292.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -378859,8 +378044,8 @@ module \ti sync always update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] end - attribute \src "libresoc.v:199856.3-199931.6" - process $proc$libresoc.v:199856$13531 + attribute \src "libresoc.v:199314.3-199400.6" + process $proc$libresoc.v:199314$13514 assign { } { } assign { } { } assign { } { } @@ -378874,13 +378059,13 @@ module \ti assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0] assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0] assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:199857.5-199857.29" + attribute \src "libresoc.v:199315.5-199315.29" switch \initial - attribute \src "libresoc.v:199857.9-199857.17" + attribute \src "libresoc.v:199315.9-199315.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 @@ -378896,7 +378081,7 @@ module \ti assign $1\new_svstate_subvl[1:0] $2\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $2\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $2\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378920,7 +378105,7 @@ module \ti assign $2\new_svstate_subvl[1:0] $3\new_svstate_subvl[1:0] assign $2\new_svstate_svstep[1:0] $3\new_svstate_svstep[1:0] assign $2\new_svstate_vl[6:0] $3\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378965,6 +378150,14 @@ module \ti assign $1\new_svstate_svstep[1:0] \cur_cur_svstep assign $1\new_svstate_vl[6:0] \cur_cur_vl attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\new_svstate_dststep[6:0] \cur_cur_dststep assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl @@ -378973,7 +378166,15 @@ module \ti assign $1\new_svstate_svstep[1:0] \cur_cur_svstep assign $1\new_svstate_vl[6:0] \cur_cur_vl attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'110 + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" + case 3'111 assign { } { } assign { } { } assign { } { } @@ -378986,7 +378187,7 @@ module \ti assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$116 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -378998,7 +378199,7 @@ module \ti assign $4\new_svstate_vl[6:0] \cur_cur_vl assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0] assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379006,7 +378207,7 @@ module \ti assign { } { } assign $5\new_svstate_dststep[6:0] $6\new_svstate_dststep[6:0] assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" switch { \$122 \$118 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -379014,8 +378215,10 @@ module \ti assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep attribute \src "libresoc.v:0.0-0.0" case 2'1- - assign $6\new_svstate_dststep[6:0] \cur_cur_dststep - assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign { } { } + assign { } { } + assign $6\new_svstate_srcstep[6:0] 7'0000000 + assign $6\new_svstate_dststep[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -379041,7 +378244,7 @@ module \ti assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0] assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0] assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379077,24 +378280,24 @@ module \ti update \new_svstate_svstep $0\new_svstate_svstep[1:0] update \new_svstate_vl $0\new_svstate_vl[6:0] end - attribute \src "libresoc.v:199932.3-199947.6" - process $proc$libresoc.v:199932$13532 + attribute \src "libresoc.v:199401.3-199416.6" + process $proc$libresoc.v:199401$13515 assign { } { } assign { } { } assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:199933.5-199933.29" + attribute \src "libresoc.v:199402.5-199402.29" switch \initial - attribute \src "libresoc.v:199933.9-199933.17" + attribute \src "libresoc.v:199402.9-199402.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\fetch_pc_valid_i[0:0] $2\fetch_pc_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379109,180 +378312,193 @@ module \ti sync always update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] end - attribute \src "libresoc.v:199948.3-200046.6" - process $proc$libresoc.v:199948$13533 + attribute \src "libresoc.v:199417.3-199524.6" + process $proc$libresoc.v:199417$13516 assign { } { } assign { } { } assign { } { } - assign $0\issue_fsm_state$next[2:0]$13534 $12\issue_fsm_state$next[2:0]$13546 - attribute \src "libresoc.v:199949.5-199949.29" + assign $0\issue_fsm_state$next[2:0]$13517 $13\issue_fsm_state$next[2:0]$13530 + attribute \src "libresoc.v:199418.5-199418.29" switch \initial - attribute \src "libresoc.v:199949.9-199949.17" + attribute \src "libresoc.v:199418.9-199418.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13535 $2\issue_fsm_state$next[2:0]$13536 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + assign $1\issue_fsm_state$next[2:0]$13518 $2\issue_fsm_state$next[2:0]$13519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$140 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\issue_fsm_state$next[2:0]$13536 $3\issue_fsm_state$next[2:0]$13537 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:528" + assign $2\issue_fsm_state$next[2:0]$13519 $3\issue_fsm_state$next[2:0]$13520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536" switch \fetch_pc_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\issue_fsm_state$next[2:0]$13537 3'001 + assign $3\issue_fsm_state$next[2:0]$13520 3'001 case - assign $3\issue_fsm_state$next[2:0]$13537 \issue_fsm_state + assign $3\issue_fsm_state$next[2:0]$13520 \issue_fsm_state end case - assign $2\issue_fsm_state$next[2:0]$13536 \issue_fsm_state + assign $2\issue_fsm_state$next[2:0]$13519 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13535 $4\issue_fsm_state$next[2:0]$13538 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" + assign $1\issue_fsm_state$next[2:0]$13518 $4\issue_fsm_state$next[2:0]$13521 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:555" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\issue_fsm_state$next[2:0]$13538 $5\issue_fsm_state$next[2:0]$13539 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" + assign $4\issue_fsm_state$next[2:0]$13521 $5\issue_fsm_state$next[2:0]$13522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" switch \$144 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\issue_fsm_state$next[2:0]$13539 3'000 + assign $5\issue_fsm_state$next[2:0]$13522 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $5\issue_fsm_state$next[2:0]$13539 3'010 + assign $5\issue_fsm_state$next[2:0]$13522 3'010 end case - assign $4\issue_fsm_state$next[2:0]$13538 \issue_fsm_state + assign $4\issue_fsm_state$next[2:0]$13521 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13535 $6\issue_fsm_state$next[2:0]$13540 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:575" + assign $1\issue_fsm_state$next[2:0]$13518 $6\issue_fsm_state$next[2:0]$13523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:576" switch \pred_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\issue_fsm_state$next[2:0]$13540 3'100 + assign $6\issue_fsm_state$next[2:0]$13523 3'100 case - assign $6\issue_fsm_state$next[2:0]$13540 \issue_fsm_state + assign $6\issue_fsm_state$next[2:0]$13523 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13535 $7\issue_fsm_state$next[2:0]$13541 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" + assign $1\issue_fsm_state$next[2:0]$13518 $7\issue_fsm_state$next[2:0]$13524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:581" switch \pred_mask_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\issue_fsm_state$next[2:0]$13541 3'010 + assign $7\issue_fsm_state$next[2:0]$13524 3'101 + case + assign $7\issue_fsm_state$next[2:0]$13524 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$13518 $8\issue_fsm_state$next[2:0]$13525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:586" + switch \$146 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\issue_fsm_state$next[2:0]$13525 3'010 case - assign $7\issue_fsm_state$next[2:0]$13541 \issue_fsm_state + assign $8\issue_fsm_state$next[2:0]$13525 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13535 $8\issue_fsm_state$next[2:0]$13542 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621" + assign $1\issue_fsm_state$next[2:0]$13518 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$13518 $9\issue_fsm_state$next[2:0]$13526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" switch \exec_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\issue_fsm_state$next[2:0]$13542 3'101 + assign $9\issue_fsm_state$next[2:0]$13526 3'111 case - assign $8\issue_fsm_state$next[2:0]$13542 \issue_fsm_state + assign $9\issue_fsm_state$next[2:0]$13526 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'111 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13535 $9\issue_fsm_state$next[2:0]$13543 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - switch \$150 + assign $1\issue_fsm_state$next[2:0]$13518 $10\issue_fsm_state$next[2:0]$13527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + switch \$152 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\issue_fsm_state$next[2:0]$13543 $10\issue_fsm_state$next[2:0]$13544 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629" + assign $10\issue_fsm_state$next[2:0]$13527 $11\issue_fsm_state$next[2:0]$13528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\issue_fsm_state$next[2:0]$13544 $11\issue_fsm_state$next[2:0]$13545 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" - switch { \$156 \$152 } + assign $11\issue_fsm_state$next[2:0]$13528 $12\issue_fsm_state$next[2:0]$13529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + switch { \$158 \$154 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $11\issue_fsm_state$next[2:0]$13545 3'000 + assign $12\issue_fsm_state$next[2:0]$13529 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $11\issue_fsm_state$next[2:0]$13545 3'000 + assign $12\issue_fsm_state$next[2:0]$13529 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $11\issue_fsm_state$next[2:0]$13545 3'110 + assign $12\issue_fsm_state$next[2:0]$13529 3'101 end case - assign $10\issue_fsm_state$next[2:0]$13544 \issue_fsm_state + assign $11\issue_fsm_state$next[2:0]$13528 \issue_fsm_state end case - assign $9\issue_fsm_state$next[2:0]$13543 \issue_fsm_state + assign $10\issue_fsm_state$next[2:0]$13527 \issue_fsm_state end - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\issue_fsm_state$next[2:0]$13535 3'010 case - assign $1\issue_fsm_state$next[2:0]$13535 \issue_fsm_state + assign $1\issue_fsm_state$next[2:0]$13518 \issue_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $12\issue_fsm_state$next[2:0]$13546 3'000 + assign $13\issue_fsm_state$next[2:0]$13530 3'000 case - assign $12\issue_fsm_state$next[2:0]$13546 $1\issue_fsm_state$next[2:0]$13535 + assign $13\issue_fsm_state$next[2:0]$13530 $1\issue_fsm_state$next[2:0]$13518 end sync always - update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13534 + update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13517 end - attribute \src "libresoc.v:200047.3-200093.6" - process $proc$libresoc.v:200047$13547 + attribute \src "libresoc.v:199525.3-199579.6" + process $proc$libresoc.v:199525$13531 assign { } { } assign { } { } assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:200048.5-200048.29" + attribute \src "libresoc.v:199526.5-199526.29" switch \initial - attribute \src "libresoc.v:200048.9-200048.17" + attribute \src "libresoc.v:199526.9-199526.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - switch \$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + switch \$164 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\core_stopped_i[0:0] 1'0 @@ -379301,14 +378517,20 @@ module \ti case 3'100 assign $1\core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'110 + assign $1\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 assign { } { } assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - switch \$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + switch \$170 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\core_stopped_i[0:0] 1'0 @@ -379323,25 +378545,25 @@ module \ti sync always update \core_stopped_i $0\core_stopped_i[0:0] end - attribute \src "libresoc.v:200094.3-200140.6" - process $proc$libresoc.v:200094$13548 + attribute \src "libresoc.v:199580.3-199634.6" + process $proc$libresoc.v:199580$13532 assign { } { } assign { } { } assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:200095.5-200095.29" + attribute \src "libresoc.v:199581.5-199581.29" switch \initial - attribute \src "libresoc.v:200095.9-200095.17" + attribute \src "libresoc.v:199581.9-199581.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - switch \$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + switch \$176 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\dbg_core_stopped_i[0:0] 1'0 @@ -379360,14 +378582,20 @@ module \ti case 3'100 assign $1\dbg_core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\dbg_core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'110 + assign $1\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 assign { } { } assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - switch \$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + switch \$182 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\dbg_core_stopped_i[0:0] 1'0 @@ -379382,144 +378610,150 @@ module \ti sync always update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end - attribute \src "libresoc.v:200141.3-200223.6" - process $proc$libresoc.v:200141$13549 + attribute \src "libresoc.v:199635.3-199725.6" + process $proc$libresoc.v:199635$13533 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\pc_changed$next[0:0]$13550 $9\pc_changed$next[0:0]$13559 - attribute \src "libresoc.v:200142.5-200142.29" + assign $0\pc_changed$next[0:0]$13534 $9\pc_changed$next[0:0]$13543 + attribute \src "libresoc.v:199636.5-199636.29" switch \initial - attribute \src "libresoc.v:200142.9-200142.17" + attribute \src "libresoc.v:199636.9-199636.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\pc_changed$next[0:0]$13551 $2\pc_changed$next[0:0]$13552 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - switch \$186 + assign $1\pc_changed$next[0:0]$13535 $2\pc_changed$next[0:0]$13536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + switch \$188 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\pc_changed$next[0:0]$13552 \pc_changed + assign $2\pc_changed$next[0:0]$13536 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\pc_changed$next[0:0]$13552 $3\pc_changed$next[0:0]$13553 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535" + assign $2\pc_changed$next[0:0]$13536 $3\pc_changed$next[0:0]$13537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\pc_changed$next[0:0]$13553 1'1 + assign $3\pc_changed$next[0:0]$13537 1'1 case - assign $3\pc_changed$next[0:0]$13553 \pc_changed + assign $3\pc_changed$next[0:0]$13537 \pc_changed end end attribute \src "libresoc.v:0.0-0.0" case 3'001 - assign $1\pc_changed$next[0:0]$13551 \pc_changed + assign $1\pc_changed$next[0:0]$13535 \pc_changed attribute \src "libresoc.v:0.0-0.0" case 3'011 - assign $1\pc_changed$next[0:0]$13551 \pc_changed + assign $1\pc_changed$next[0:0]$13535 \pc_changed attribute \src "libresoc.v:0.0-0.0" case 3'100 - assign $1\pc_changed$next[0:0]$13551 \pc_changed + assign $1\pc_changed$next[0:0]$13535 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\pc_changed$next[0:0]$13535 \pc_changed attribute \src "libresoc.v:0.0-0.0" case 3'010 - assign $1\pc_changed$next[0:0]$13551 \pc_changed + assign $1\pc_changed$next[0:0]$13535 \pc_changed attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'110 + assign $1\pc_changed$next[0:0]$13535 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'111 assign { } { } - assign $1\pc_changed$next[0:0]$13551 $4\pc_changed$next[0:0]$13554 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - switch \$192 + assign $1\pc_changed$next[0:0]$13535 $4\pc_changed$next[0:0]$13538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + switch \$194 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\pc_changed$next[0:0]$13554 \pc_changed + assign $4\pc_changed$next[0:0]$13538 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\pc_changed$next[0:0]$13554 $5\pc_changed$next[0:0]$13555 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:671" + assign $4\pc_changed$next[0:0]$13538 $5\pc_changed$next[0:0]$13539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:712" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\pc_changed$next[0:0]$13555 1'1 + assign $5\pc_changed$next[0:0]$13539 1'1 case - assign $5\pc_changed$next[0:0]$13555 \pc_changed + assign $5\pc_changed$next[0:0]$13539 \pc_changed end end case - assign $1\pc_changed$next[0:0]$13551 \pc_changed + assign $1\pc_changed$next[0:0]$13535 \pc_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\pc_changed$next[0:0]$13556 $7\pc_changed$next[0:0]$13557 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + assign $6\pc_changed$next[0:0]$13540 $7\pc_changed$next[0:0]$13541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\pc_changed$next[0:0]$13557 1'0 + assign $7\pc_changed$next[0:0]$13541 1'0 case - assign $7\pc_changed$next[0:0]$13557 $1\pc_changed$next[0:0]$13551 + assign $7\pc_changed$next[0:0]$13541 $1\pc_changed$next[0:0]$13535 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\pc_changed$next[0:0]$13556 $8\pc_changed$next[0:0]$13558 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:737" - switch \$194 + assign $6\pc_changed$next[0:0]$13540 $8\pc_changed$next[0:0]$13542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" + switch \$196 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\pc_changed$next[0:0]$13558 1'1 + assign $8\pc_changed$next[0:0]$13542 1'1 case - assign $8\pc_changed$next[0:0]$13558 $1\pc_changed$next[0:0]$13551 + assign $8\pc_changed$next[0:0]$13542 $1\pc_changed$next[0:0]$13535 end case - assign $6\pc_changed$next[0:0]$13556 $1\pc_changed$next[0:0]$13551 + assign $6\pc_changed$next[0:0]$13540 $1\pc_changed$next[0:0]$13535 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\pc_changed$next[0:0]$13559 1'0 + assign $9\pc_changed$next[0:0]$13543 1'0 case - assign $9\pc_changed$next[0:0]$13559 $6\pc_changed$next[0:0]$13556 + assign $9\pc_changed$next[0:0]$13543 $6\pc_changed$next[0:0]$13540 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$13550 + update \pc_changed$next $0\pc_changed$next[0:0]$13534 end - attribute \src "libresoc.v:200224.3-200296.6" - process $proc$libresoc.v:200224$13560 + attribute \src "libresoc.v:199726.3-199806.6" + process $proc$libresoc.v:199726$13544 assign { } { } assign { } { } assign $0\update_svstate[0:0] $1\update_svstate[0:0] - attribute \src "libresoc.v:200225.5-200225.29" + attribute \src "libresoc.v:199727.5-199727.29" switch \initial - attribute \src "libresoc.v:200225.9-200225.17" + attribute \src "libresoc.v:199727.9-199727.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\update_svstate[0:0] $2\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - switch \$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + switch \$204 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\update_svstate[0:0] 1'0 @@ -379527,7 +378761,7 @@ module \ti case assign { } { } assign $2\update_svstate[0:0] $3\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379547,32 +378781,39 @@ module \ti case 3'100 assign $1\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'110 + assign $1\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 assign { } { } assign $1\update_svstate[0:0] $4\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - switch \$208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + switch \$210 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\update_svstate[0:0] $5\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\update_svstate[0:0] $6\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" - switch { \$214 \$210 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + switch { \$216 \$212 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $6\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'1- - assign $6\update_svstate[0:0] 1'0 + assign { } { } + assign $6\update_svstate[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -379585,7 +378826,7 @@ module \ti case assign { } { } assign $4\update_svstate[0:0] $7\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379601,137 +378842,143 @@ module \ti sync always update \update_svstate $0\update_svstate[0:0] end - attribute \src "libresoc.v:200297.3-200379.6" - process $proc$libresoc.v:200297$13561 + attribute \src "libresoc.v:199807.3-199897.6" + process $proc$libresoc.v:199807$13545 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sv_changed$next[0:0]$13562 $9\sv_changed$next[0:0]$13571 - attribute \src "libresoc.v:200298.5-200298.29" + assign $0\sv_changed$next[0:0]$13546 $9\sv_changed$next[0:0]$13555 + attribute \src "libresoc.v:199808.5-199808.29" switch \initial - attribute \src "libresoc.v:200298.9-200298.17" + attribute \src "libresoc.v:199808.9-199808.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\sv_changed$next[0:0]$13563 $2\sv_changed$next[0:0]$13564 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - switch \$220 + assign $1\sv_changed$next[0:0]$13547 $2\sv_changed$next[0:0]$13548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" + switch \$222 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\sv_changed$next[0:0]$13564 \sv_changed + assign $2\sv_changed$next[0:0]$13548 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\sv_changed$next[0:0]$13564 $3\sv_changed$next[0:0]$13565 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + assign $2\sv_changed$next[0:0]$13548 $3\sv_changed$next[0:0]$13549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv_changed$next[0:0]$13565 1'1 + assign $3\sv_changed$next[0:0]$13549 1'1 case - assign $3\sv_changed$next[0:0]$13565 \sv_changed + assign $3\sv_changed$next[0:0]$13549 \sv_changed end end attribute \src "libresoc.v:0.0-0.0" case 3'001 - assign $1\sv_changed$next[0:0]$13563 \sv_changed + assign $1\sv_changed$next[0:0]$13547 \sv_changed attribute \src "libresoc.v:0.0-0.0" case 3'011 - assign $1\sv_changed$next[0:0]$13563 \sv_changed + assign $1\sv_changed$next[0:0]$13547 \sv_changed attribute \src "libresoc.v:0.0-0.0" case 3'100 - assign $1\sv_changed$next[0:0]$13563 \sv_changed + assign $1\sv_changed$next[0:0]$13547 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\sv_changed$next[0:0]$13547 \sv_changed attribute \src "libresoc.v:0.0-0.0" case 3'010 - assign $1\sv_changed$next[0:0]$13563 \sv_changed + assign $1\sv_changed$next[0:0]$13547 \sv_changed attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'110 + assign $1\sv_changed$next[0:0]$13547 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'111 assign { } { } - assign $1\sv_changed$next[0:0]$13563 $4\sv_changed$next[0:0]$13566 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" - switch \$226 + assign $1\sv_changed$next[0:0]$13547 $4\sv_changed$next[0:0]$13550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + switch \$228 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\sv_changed$next[0:0]$13566 \sv_changed + assign $4\sv_changed$next[0:0]$13550 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\sv_changed$next[0:0]$13566 $5\sv_changed$next[0:0]$13567 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675" + assign $4\sv_changed$next[0:0]$13550 $5\sv_changed$next[0:0]$13551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv_changed$next[0:0]$13567 1'1 + assign $5\sv_changed$next[0:0]$13551 1'1 case - assign $5\sv_changed$next[0:0]$13567 \sv_changed + assign $5\sv_changed$next[0:0]$13551 \sv_changed end end case - assign $1\sv_changed$next[0:0]$13563 \sv_changed + assign $1\sv_changed$next[0:0]$13547 \sv_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\sv_changed$next[0:0]$13568 $7\sv_changed$next[0:0]$13569 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + assign $6\sv_changed$next[0:0]$13552 $7\sv_changed$next[0:0]$13553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv_changed$next[0:0]$13569 1'0 + assign $7\sv_changed$next[0:0]$13553 1'0 case - assign $7\sv_changed$next[0:0]$13569 $1\sv_changed$next[0:0]$13563 + assign $7\sv_changed$next[0:0]$13553 $1\sv_changed$next[0:0]$13547 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv_changed$next[0:0]$13568 $8\sv_changed$next[0:0]$13570 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" - switch \$228 + assign $6\sv_changed$next[0:0]$13552 $8\sv_changed$next[0:0]$13554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:765" + switch \$230 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\sv_changed$next[0:0]$13570 1'1 + assign $8\sv_changed$next[0:0]$13554 1'1 case - assign $8\sv_changed$next[0:0]$13570 $1\sv_changed$next[0:0]$13563 + assign $8\sv_changed$next[0:0]$13554 $1\sv_changed$next[0:0]$13547 end case - assign $6\sv_changed$next[0:0]$13568 $1\sv_changed$next[0:0]$13563 + assign $6\sv_changed$next[0:0]$13552 $1\sv_changed$next[0:0]$13547 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\sv_changed$next[0:0]$13571 1'0 + assign $9\sv_changed$next[0:0]$13555 1'0 case - assign $9\sv_changed$next[0:0]$13571 $6\sv_changed$next[0:0]$13568 + assign $9\sv_changed$next[0:0]$13555 $6\sv_changed$next[0:0]$13552 end sync always - update \sv_changed$next $0\sv_changed$next[0:0]$13562 + update \sv_changed$next $0\sv_changed$next[0:0]$13546 end - attribute \src "libresoc.v:200380.3-200394.6" - process $proc$libresoc.v:200380$13572 + attribute \src "libresoc.v:199898.3-199912.6" + process $proc$libresoc.v:199898$13556 assign { } { } assign { } { } assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:200381.5-200381.29" + attribute \src "libresoc.v:199899.5-199899.29" switch \initial - attribute \src "libresoc.v:200381.9-200381.17" + attribute \src "libresoc.v:199899.9-199899.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 @@ -379746,8 +378993,144 @@ module \ti sync always update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] end - attribute \src "libresoc.v:200395.3-200525.6" - process $proc$libresoc.v:200395$13573 + attribute \src "libresoc.v:199913.3-199958.6" + process $proc$libresoc.v:199913$13557 + assign { } { } + assign { } { } + assign { } { } + assign $0\insn_done[0:0] $4\insn_done[0:0] + attribute \src "libresoc.v:199914.5-199914.29" + switch \initial + attribute \src "libresoc.v:199914.9-199914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\insn_done[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\insn_done[0:0] $2\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:555" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\insn_done[0:0] $3\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + switch \$236 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\insn_done[0:0] 1'1 + case + assign $3\insn_done[0:0] 1'0 + end + case + assign $2\insn_done[0:0] 1'0 + end + case + assign $1\insn_done[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign $4\insn_done[0:0] $1\insn_done[0:0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\insn_done[0:0] $5\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" + switch \$238 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\insn_done[0:0] $6\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" + switch \exec_pc_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\insn_done[0:0] 1'1 + case + assign $6\insn_done[0:0] $1\insn_done[0:0] + end + case + assign $5\insn_done[0:0] $1\insn_done[0:0] + end + case + assign $4\insn_done[0:0] $1\insn_done[0:0] + end + sync always + update \insn_done $0\insn_done[0:0] + end + attribute \src "libresoc.v:199959.3-199977.6" + process $proc$libresoc.v:199959$13558 + assign { } { } + assign { } { } + assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0] + attribute \src "libresoc.v:199960.5-199960.29" + switch \initial + attribute \src "libresoc.v:199960.9-199960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\pred_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\pred_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\pred_insn_valid_i[0:0] 1'1 + case + assign $1\pred_insn_valid_i[0:0] 1'0 + end + sync always + update \pred_insn_valid_i $0\pred_insn_valid_i[0:0] + end + attribute \src "libresoc.v:199978.3-200000.6" + process $proc$libresoc.v:199978$13559 + assign { } { } + assign { } { } + assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0] + attribute \src "libresoc.v:199979.5-199979.29" + switch \initial + attribute \src "libresoc.v:199979.9-199979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\pred_mask_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\pred_mask_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\pred_mask_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\pred_mask_ready_i[0:0] 1'1 + case + assign $1\pred_mask_ready_i[0:0] 1'0 + end + sync always + update \pred_mask_ready_i $0\pred_mask_ready_i[0:0] + end + attribute \src "libresoc.v:200001.3-200122.6" + process $proc$libresoc.v:200001$13560 assign { } { } assign { } { } assign { } { } @@ -379866,11 +379249,11 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_asmcode$next[7:0]$13574 $1\core_asmcode$next[7:0]$13633 - assign $0\core_core_core_cia$next[63:0]$13575 $1\core_core_core_cia$next[63:0]$13634 - assign $0\core_core_core_cr_rd$next[7:0]$13576 $1\core_core_core_cr_rd$next[7:0]$13635 + assign $0\core_asmcode$next[7:0]$13561 $1\core_asmcode$next[7:0]$13620 + assign $0\core_core_core_cia$next[63:0]$13562 $1\core_core_core_cia$next[63:0]$13621 + assign $0\core_core_core_cr_rd$next[7:0]$13563 $1\core_core_core_cr_rd$next[7:0]$13622 assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$13578 $1\core_core_core_cr_wr$next[7:0]$13637 + assign $0\core_core_core_cr_wr$next[7:0]$13565 $1\core_core_core_cr_wr$next[7:0]$13624 assign { } { } assign { } { } assign { } { } @@ -379879,639 +379262,394 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_core_fn_unit$next[13:0]$13587 $1\core_core_core_fn_unit$next[13:0]$13646 - assign $0\core_core_core_input_carry$next[1:0]$13588 $1\core_core_core_input_carry$next[1:0]$13647 - assign $0\core_core_core_insn$next[31:0]$13589 $1\core_core_core_insn$next[31:0]$13648 - assign $0\core_core_core_insn_type$next[6:0]$13590 $1\core_core_core_insn_type$next[6:0]$13649 - assign $0\core_core_core_is_32bit$next[0:0]$13591 $1\core_core_core_is_32bit$next[0:0]$13650 - assign $0\core_core_core_msr$next[63:0]$13592 $1\core_core_core_msr$next[63:0]$13651 - assign $0\core_core_core_oe$next[0:0]$13593 $1\core_core_core_oe$next[0:0]$13652 + assign $0\core_core_core_fn_unit$next[13:0]$13574 $1\core_core_core_fn_unit$next[13:0]$13633 + assign $0\core_core_core_input_carry$next[1:0]$13575 $1\core_core_core_input_carry$next[1:0]$13634 + assign $0\core_core_core_insn$next[31:0]$13576 $1\core_core_core_insn$next[31:0]$13635 + assign $0\core_core_core_insn_type$next[6:0]$13577 $1\core_core_core_insn_type$next[6:0]$13636 + assign $0\core_core_core_is_32bit$next[0:0]$13578 $1\core_core_core_is_32bit$next[0:0]$13637 + assign $0\core_core_core_msr$next[63:0]$13579 $1\core_core_core_msr$next[63:0]$13638 + assign $0\core_core_core_oe$next[0:0]$13580 $1\core_core_core_oe$next[0:0]$13639 assign { } { } - assign $0\core_core_core_rc$next[0:0]$13595 $1\core_core_core_rc$next[0:0]$13654 + assign $0\core_core_core_rc$next[0:0]$13582 $1\core_core_core_rc$next[0:0]$13641 assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$13597 $1\core_core_core_trapaddr$next[12:0]$13656 - assign $0\core_core_core_traptype$next[7:0]$13598 $1\core_core_core_traptype$next[7:0]$13657 - assign $0\core_core_cr_in1$next[6:0]$13599 $1\core_core_cr_in1$next[6:0]$13658 + assign $0\core_core_core_trapaddr$next[12:0]$13584 $1\core_core_core_trapaddr$next[12:0]$13643 + assign $0\core_core_core_traptype$next[7:0]$13585 $1\core_core_core_traptype$next[7:0]$13644 + assign $0\core_core_cr_in1$next[6:0]$13586 $1\core_core_cr_in1$next[6:0]$13645 assign { } { } - assign $0\core_core_cr_in2$1$next[6:0]$13601 $1\core_core_cr_in2$1$next[6:0]$13660 - assign $0\core_core_cr_in2$next[6:0]$13602 $1\core_core_cr_in2$next[6:0]$13661 + assign $0\core_core_cr_in2$1$next[6:0]$13588 $1\core_core_cr_in2$1$next[6:0]$13647 + assign $0\core_core_cr_in2$next[6:0]$13589 $1\core_core_cr_in2$next[6:0]$13648 assign { } { } assign { } { } - assign $0\core_core_cr_out$next[6:0]$13605 $1\core_core_cr_out$next[6:0]$13664 + assign $0\core_core_cr_out$next[6:0]$13592 $1\core_core_cr_out$next[6:0]$13651 assign { } { } - assign $0\core_core_ea$next[6:0]$13607 $1\core_core_ea$next[6:0]$13666 - assign $0\core_core_fast1$next[2:0]$13608 $1\core_core_fast1$next[2:0]$13667 + assign $0\core_core_ea$next[6:0]$13594 $1\core_core_ea$next[6:0]$13653 + assign $0\core_core_fast1$next[2:0]$13595 $1\core_core_fast1$next[2:0]$13654 assign { } { } - assign $0\core_core_fast2$next[2:0]$13610 $1\core_core_fast2$next[2:0]$13669 + assign $0\core_core_fast2$next[2:0]$13597 $1\core_core_fast2$next[2:0]$13656 assign { } { } - assign $0\core_core_fasto1$next[2:0]$13612 $1\core_core_fasto1$next[2:0]$13671 - assign $0\core_core_fasto2$next[2:0]$13613 $1\core_core_fasto2$next[2:0]$13672 - assign $0\core_core_lk$next[0:0]$13614 $1\core_core_lk$next[0:0]$13673 - assign $0\core_core_reg1$next[6:0]$13615 $1\core_core_reg1$next[6:0]$13674 + assign $0\core_core_fasto1$next[2:0]$13599 $1\core_core_fasto1$next[2:0]$13658 + assign $0\core_core_fasto2$next[2:0]$13600 $1\core_core_fasto2$next[2:0]$13659 + assign $0\core_core_lk$next[0:0]$13601 $1\core_core_lk$next[0:0]$13660 + assign $0\core_core_reg1$next[6:0]$13602 $1\core_core_reg1$next[6:0]$13661 assign { } { } - assign $0\core_core_reg2$next[6:0]$13617 $1\core_core_reg2$next[6:0]$13676 + assign $0\core_core_reg2$next[6:0]$13604 $1\core_core_reg2$next[6:0]$13663 assign { } { } - assign $0\core_core_reg3$next[6:0]$13619 $1\core_core_reg3$next[6:0]$13678 + assign $0\core_core_reg3$next[6:0]$13606 $1\core_core_reg3$next[6:0]$13665 assign { } { } - assign $0\core_core_rego$next[6:0]$13621 $1\core_core_rego$next[6:0]$13680 - assign $0\core_core_spr1$next[9:0]$13622 $1\core_core_spr1$next[9:0]$13681 + assign $0\core_core_rego$next[6:0]$13608 $1\core_core_rego$next[6:0]$13667 + assign $0\core_core_spr1$next[9:0]$13609 $1\core_core_spr1$next[9:0]$13668 assign { } { } - assign $0\core_core_spro$next[9:0]$13624 $1\core_core_spro$next[9:0]$13683 - assign $0\core_core_xer_in$next[2:0]$13625 $1\core_core_xer_in$next[2:0]$13684 + assign $0\core_core_spro$next[9:0]$13611 $1\core_core_spro$next[9:0]$13670 + assign $0\core_core_xer_in$next[2:0]$13612 $1\core_core_xer_in$next[2:0]$13671 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\core_xer_out$next[0:0]$13632 $1\core_xer_out$next[0:0]$13691 - assign $0\core_core_core_cr_rd_ok$next[0:0]$13577 $3\core_core_core_cr_rd_ok$next[0:0]$13751 - assign $0\core_core_core_exc_$signal$3$next[0:0]$13579 $3\core_core_core_exc_$signal$3$next[0:0]$13752 - assign $0\core_core_core_exc_$signal$4$next[0:0]$13580 $3\core_core_core_exc_$signal$4$next[0:0]$13753 - assign $0\core_core_core_exc_$signal$5$next[0:0]$13581 $3\core_core_core_exc_$signal$5$next[0:0]$13754 - assign $0\core_core_core_exc_$signal$6$next[0:0]$13582 $3\core_core_core_exc_$signal$6$next[0:0]$13755 - assign $0\core_core_core_exc_$signal$7$next[0:0]$13583 $3\core_core_core_exc_$signal$7$next[0:0]$13756 - assign $0\core_core_core_exc_$signal$8$next[0:0]$13584 $3\core_core_core_exc_$signal$8$next[0:0]$13757 - assign $0\core_core_core_exc_$signal$9$next[0:0]$13585 $3\core_core_core_exc_$signal$9$next[0:0]$13758 - assign $0\core_core_core_exc_$signal$next[0:0]$13586 $3\core_core_core_exc_$signal$next[0:0]$13759 - assign $0\core_core_core_oe_ok$next[0:0]$13594 $3\core_core_core_oe_ok$next[0:0]$13760 - assign $0\core_core_core_rc_ok$next[0:0]$13596 $3\core_core_core_rc_ok$next[0:0]$13761 - assign $0\core_core_cr_in1_ok$next[0:0]$13600 $3\core_core_cr_in1_ok$next[0:0]$13762 - assign $0\core_core_cr_in2_ok$2$next[0:0]$13603 $3\core_core_cr_in2_ok$2$next[0:0]$13763 - assign $0\core_core_cr_in2_ok$next[0:0]$13604 $3\core_core_cr_in2_ok$next[0:0]$13764 - assign $0\core_core_cr_wr_ok$next[0:0]$13606 $3\core_core_cr_wr_ok$next[0:0]$13765 - assign $0\core_core_fast1_ok$next[0:0]$13609 $3\core_core_fast1_ok$next[0:0]$13766 - assign $0\core_core_fast2_ok$next[0:0]$13611 $3\core_core_fast2_ok$next[0:0]$13767 - assign $0\core_core_reg1_ok$next[0:0]$13616 $3\core_core_reg1_ok$next[0:0]$13768 - assign $0\core_core_reg2_ok$next[0:0]$13618 $3\core_core_reg2_ok$next[0:0]$13769 - assign $0\core_core_reg3_ok$next[0:0]$13620 $3\core_core_reg3_ok$next[0:0]$13770 - assign $0\core_core_spr1_ok$next[0:0]$13623 $3\core_core_spr1_ok$next[0:0]$13771 - assign $0\core_cr_out_ok$next[0:0]$13626 $3\core_cr_out_ok$next[0:0]$13772 - assign $0\core_ea_ok$next[0:0]$13627 $3\core_ea_ok$next[0:0]$13773 - assign $0\core_fasto1_ok$next[0:0]$13628 $3\core_fasto1_ok$next[0:0]$13774 - assign $0\core_fasto2_ok$next[0:0]$13629 $3\core_fasto2_ok$next[0:0]$13775 - assign $0\core_rego_ok$next[0:0]$13630 $3\core_rego_ok$next[0:0]$13776 - assign $0\core_spro_ok$next[0:0]$13631 $3\core_spro_ok$next[0:0]$13777 - attribute \src "libresoc.v:200396.5-200396.29" + assign $0\core_xer_out$next[0:0]$13619 $1\core_xer_out$next[0:0]$13678 + assign $0\core_core_core_cr_rd_ok$next[0:0]$13564 $2\core_core_core_cr_rd_ok$next[0:0]$13679 + assign $0\core_core_core_exc_$signal$3$next[0:0]$13566 $2\core_core_core_exc_$signal$3$next[0:0]$13680 + assign $0\core_core_core_exc_$signal$4$next[0:0]$13567 $2\core_core_core_exc_$signal$4$next[0:0]$13681 + assign $0\core_core_core_exc_$signal$5$next[0:0]$13568 $2\core_core_core_exc_$signal$5$next[0:0]$13682 + assign $0\core_core_core_exc_$signal$6$next[0:0]$13569 $2\core_core_core_exc_$signal$6$next[0:0]$13683 + assign $0\core_core_core_exc_$signal$7$next[0:0]$13570 $2\core_core_core_exc_$signal$7$next[0:0]$13684 + assign $0\core_core_core_exc_$signal$8$next[0:0]$13571 $2\core_core_core_exc_$signal$8$next[0:0]$13685 + assign $0\core_core_core_exc_$signal$9$next[0:0]$13572 $2\core_core_core_exc_$signal$9$next[0:0]$13686 + assign $0\core_core_core_exc_$signal$next[0:0]$13573 $2\core_core_core_exc_$signal$next[0:0]$13687 + assign $0\core_core_core_oe_ok$next[0:0]$13581 $2\core_core_core_oe_ok$next[0:0]$13688 + assign $0\core_core_core_rc_ok$next[0:0]$13583 $2\core_core_core_rc_ok$next[0:0]$13689 + assign $0\core_core_cr_in1_ok$next[0:0]$13587 $2\core_core_cr_in1_ok$next[0:0]$13690 + assign $0\core_core_cr_in2_ok$2$next[0:0]$13590 $2\core_core_cr_in2_ok$2$next[0:0]$13691 + assign $0\core_core_cr_in2_ok$next[0:0]$13591 $2\core_core_cr_in2_ok$next[0:0]$13692 + assign $0\core_core_cr_wr_ok$next[0:0]$13593 $2\core_core_cr_wr_ok$next[0:0]$13693 + assign $0\core_core_fast1_ok$next[0:0]$13596 $2\core_core_fast1_ok$next[0:0]$13694 + assign $0\core_core_fast2_ok$next[0:0]$13598 $2\core_core_fast2_ok$next[0:0]$13695 + assign $0\core_core_reg1_ok$next[0:0]$13603 $2\core_core_reg1_ok$next[0:0]$13696 + assign $0\core_core_reg2_ok$next[0:0]$13605 $2\core_core_reg2_ok$next[0:0]$13697 + assign $0\core_core_reg3_ok$next[0:0]$13607 $2\core_core_reg3_ok$next[0:0]$13698 + assign $0\core_core_spr1_ok$next[0:0]$13610 $2\core_core_spr1_ok$next[0:0]$13699 + assign $0\core_cr_out_ok$next[0:0]$13613 $2\core_cr_out_ok$next[0:0]$13700 + assign $0\core_ea_ok$next[0:0]$13614 $2\core_ea_ok$next[0:0]$13701 + assign $0\core_fasto1_ok$next[0:0]$13615 $2\core_fasto1_ok$next[0:0]$13702 + assign $0\core_fasto2_ok$next[0:0]$13616 $2\core_fasto2_ok$next[0:0]$13703 + assign $0\core_rego_ok$next[0:0]$13617 $2\core_rego_ok$next[0:0]$13704 + assign $0\core_spro_ok$next[0:0]$13618 $2\core_spro_ok$next[0:0]$13705 + attribute \src "libresoc.v:200002.5-200002.29" switch \initial - attribute \src "libresoc.v:200396.9-200396.17" + attribute \src "libresoc.v:200002.9-200002.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 - assign $1\core_asmcode$next[7:0]$13633 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$13666 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13673 \core_core_lk - assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$13680 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13683 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13691 \core_xer_out + assign $1\core_asmcode$next[7:0]$13620 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13621 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13622 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13623 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13624 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13625 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13626 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13627 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13628 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13629 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13653 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13660 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13667 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13670 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13675 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13676 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13677 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13678 \core_xer_out attribute \src "libresoc.v:0.0-0.0" case 3'001 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\core_asmcode$next[7:0]$13633 $2\core_asmcode$next[7:0]$13692 - assign $1\core_core_core_cia$next[63:0]$13634 $2\core_core_core_cia$next[63:0]$13693 - assign $1\core_core_core_cr_rd$next[7:0]$13635 $2\core_core_core_cr_rd$next[7:0]$13694 - assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 $2\core_core_core_cr_rd_ok$next[0:0]$13695 - assign $1\core_core_core_cr_wr$next[7:0]$13637 $2\core_core_core_cr_wr$next[7:0]$13696 - assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 $2\core_core_core_exc_$signal$3$next[0:0]$13697 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 $2\core_core_core_exc_$signal$4$next[0:0]$13698 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 $2\core_core_core_exc_$signal$5$next[0:0]$13699 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 $2\core_core_core_exc_$signal$6$next[0:0]$13700 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 $2\core_core_core_exc_$signal$7$next[0:0]$13701 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 $2\core_core_core_exc_$signal$8$next[0:0]$13702 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 $2\core_core_core_exc_$signal$9$next[0:0]$13703 - assign $1\core_core_core_exc_$signal$next[0:0]$13645 $2\core_core_core_exc_$signal$next[0:0]$13704 - assign $1\core_core_core_fn_unit$next[13:0]$13646 $2\core_core_core_fn_unit$next[13:0]$13705 - assign $1\core_core_core_input_carry$next[1:0]$13647 $2\core_core_core_input_carry$next[1:0]$13706 - assign $1\core_core_core_insn$next[31:0]$13648 $2\core_core_core_insn$next[31:0]$13707 - assign $1\core_core_core_insn_type$next[6:0]$13649 $2\core_core_core_insn_type$next[6:0]$13708 - assign $1\core_core_core_is_32bit$next[0:0]$13650 $2\core_core_core_is_32bit$next[0:0]$13709 - assign $1\core_core_core_msr$next[63:0]$13651 $2\core_core_core_msr$next[63:0]$13710 - assign $1\core_core_core_oe$next[0:0]$13652 $2\core_core_core_oe$next[0:0]$13711 - assign $1\core_core_core_oe_ok$next[0:0]$13653 $2\core_core_core_oe_ok$next[0:0]$13712 - assign $1\core_core_core_rc$next[0:0]$13654 $2\core_core_core_rc$next[0:0]$13713 - assign $1\core_core_core_rc_ok$next[0:0]$13655 $2\core_core_core_rc_ok$next[0:0]$13714 - assign $1\core_core_core_trapaddr$next[12:0]$13656 $2\core_core_core_trapaddr$next[12:0]$13715 - assign $1\core_core_core_traptype$next[7:0]$13657 $2\core_core_core_traptype$next[7:0]$13716 - assign $1\core_core_cr_in1$next[6:0]$13658 $2\core_core_cr_in1$next[6:0]$13717 - assign $1\core_core_cr_in1_ok$next[0:0]$13659 $2\core_core_cr_in1_ok$next[0:0]$13718 - assign $1\core_core_cr_in2$1$next[6:0]$13660 $2\core_core_cr_in2$1$next[6:0]$13719 - assign $1\core_core_cr_in2$next[6:0]$13661 $2\core_core_cr_in2$next[6:0]$13720 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 $2\core_core_cr_in2_ok$2$next[0:0]$13721 - assign $1\core_core_cr_in2_ok$next[0:0]$13663 $2\core_core_cr_in2_ok$next[0:0]$13722 - assign $1\core_core_cr_out$next[6:0]$13664 $2\core_core_cr_out$next[6:0]$13723 - assign $1\core_core_cr_wr_ok$next[0:0]$13665 $2\core_core_cr_wr_ok$next[0:0]$13724 - assign $1\core_core_ea$next[6:0]$13666 $2\core_core_ea$next[6:0]$13725 - assign $1\core_core_fast1$next[2:0]$13667 $2\core_core_fast1$next[2:0]$13726 - assign $1\core_core_fast1_ok$next[0:0]$13668 $2\core_core_fast1_ok$next[0:0]$13727 - assign $1\core_core_fast2$next[2:0]$13669 $2\core_core_fast2$next[2:0]$13728 - assign $1\core_core_fast2_ok$next[0:0]$13670 $2\core_core_fast2_ok$next[0:0]$13729 - assign $1\core_core_fasto1$next[2:0]$13671 $2\core_core_fasto1$next[2:0]$13730 - assign $1\core_core_fasto2$next[2:0]$13672 $2\core_core_fasto2$next[2:0]$13731 - assign $1\core_core_lk$next[0:0]$13673 $2\core_core_lk$next[0:0]$13732 - assign $1\core_core_reg1$next[6:0]$13674 $2\core_core_reg1$next[6:0]$13733 - assign $1\core_core_reg1_ok$next[0:0]$13675 $2\core_core_reg1_ok$next[0:0]$13734 - assign $1\core_core_reg2$next[6:0]$13676 $2\core_core_reg2$next[6:0]$13735 - assign $1\core_core_reg2_ok$next[0:0]$13677 $2\core_core_reg2_ok$next[0:0]$13736 - assign $1\core_core_reg3$next[6:0]$13678 $2\core_core_reg3$next[6:0]$13737 - assign $1\core_core_reg3_ok$next[0:0]$13679 $2\core_core_reg3_ok$next[0:0]$13738 - assign $1\core_core_rego$next[6:0]$13680 $2\core_core_rego$next[6:0]$13739 - assign $1\core_core_spr1$next[9:0]$13681 $2\core_core_spr1$next[9:0]$13740 - assign $1\core_core_spr1_ok$next[0:0]$13682 $2\core_core_spr1_ok$next[0:0]$13741 - assign $1\core_core_spro$next[9:0]$13683 $2\core_core_spro$next[9:0]$13742 - assign $1\core_core_xer_in$next[2:0]$13684 $2\core_core_xer_in$next[2:0]$13743 - assign $1\core_cr_out_ok$next[0:0]$13685 $2\core_cr_out_ok$next[0:0]$13744 - assign $1\core_ea_ok$next[0:0]$13686 $2\core_ea_ok$next[0:0]$13745 - assign $1\core_fasto1_ok$next[0:0]$13687 $2\core_fasto1_ok$next[0:0]$13746 - assign $1\core_fasto2_ok$next[0:0]$13688 $2\core_fasto2_ok$next[0:0]$13747 - assign $1\core_rego_ok$next[0:0]$13689 $2\core_rego_ok$next[0:0]$13748 - assign $1\core_spro_ok$next[0:0]$13690 $2\core_spro_ok$next[0:0]$13749 - assign $1\core_xer_out$next[0:0]$13691 $2\core_xer_out$next[0:0]$13750 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$13709 $2\core_core_cr_wr_ok$next[0:0]$13724 $2\core_core_core_cr_wr$next[7:0]$13696 $2\core_core_core_cr_rd_ok$next[0:0]$13695 $2\core_core_core_cr_rd$next[7:0]$13694 $2\core_core_core_trapaddr$next[12:0]$13715 $2\core_core_core_exc_$signal$9$next[0:0]$13703 $2\core_core_core_exc_$signal$8$next[0:0]$13702 $2\core_core_core_exc_$signal$7$next[0:0]$13701 $2\core_core_core_exc_$signal$6$next[0:0]$13700 $2\core_core_core_exc_$signal$5$next[0:0]$13699 $2\core_core_core_exc_$signal$4$next[0:0]$13698 $2\core_core_core_exc_$signal$3$next[0:0]$13697 $2\core_core_core_exc_$signal$next[0:0]$13704 $2\core_core_core_traptype$next[7:0]$13716 $2\core_core_core_input_carry$next[1:0]$13706 $2\core_core_core_oe_ok$next[0:0]$13712 $2\core_core_core_oe$next[0:0]$13711 $2\core_core_core_rc_ok$next[0:0]$13714 $2\core_core_core_rc$next[0:0]$13713 $2\core_core_lk$next[0:0]$13732 $2\core_core_core_fn_unit$next[13:0]$13705 $2\core_core_core_insn_type$next[6:0]$13708 $2\core_core_core_insn$next[31:0]$13707 $2\core_core_core_cia$next[63:0]$13693 $2\core_core_core_msr$next[63:0]$13710 $2\core_cr_out_ok$next[0:0]$13744 $2\core_core_cr_out$next[6:0]$13723 $2\core_core_cr_in2_ok$2$next[0:0]$13721 $2\core_core_cr_in2$1$next[6:0]$13719 $2\core_core_cr_in2_ok$next[0:0]$13722 $2\core_core_cr_in2$next[6:0]$13720 $2\core_core_cr_in1_ok$next[0:0]$13718 $2\core_core_cr_in1$next[6:0]$13717 $2\core_fasto2_ok$next[0:0]$13747 $2\core_core_fasto2$next[2:0]$13731 $2\core_fasto1_ok$next[0:0]$13746 $2\core_core_fasto1$next[2:0]$13730 $2\core_core_fast2_ok$next[0:0]$13729 $2\core_core_fast2$next[2:0]$13728 $2\core_core_fast1_ok$next[0:0]$13727 $2\core_core_fast1$next[2:0]$13726 $2\core_xer_out$next[0:0]$13750 $2\core_core_xer_in$next[2:0]$13743 $2\core_core_spr1_ok$next[0:0]$13741 $2\core_core_spr1$next[9:0]$13740 $2\core_spro_ok$next[0:0]$13749 $2\core_core_spro$next[9:0]$13742 $2\core_core_reg3_ok$next[0:0]$13738 $2\core_core_reg3$next[6:0]$13737 $2\core_core_reg2_ok$next[0:0]$13736 $2\core_core_reg2$next[6:0]$13735 $2\core_core_reg1_ok$next[0:0]$13734 $2\core_core_reg1$next[6:0]$13733 $2\core_ea_ok$next[0:0]$13745 $2\core_core_ea$next[6:0]$13725 $2\core_rego_ok$next[0:0]$13748 $2\core_core_rego$next[6:0]$13739 $2\core_asmcode$next[7:0]$13692 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } - case - assign $2\core_asmcode$next[7:0]$13692 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$13693 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$13694 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$13695 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$13696 \core_core_core_cr_wr - assign $2\core_core_core_exc_$signal$3$next[0:0]$13697 \core_core_core_exc_$signal$3 - assign $2\core_core_core_exc_$signal$4$next[0:0]$13698 \core_core_core_exc_$signal$4 - assign $2\core_core_core_exc_$signal$5$next[0:0]$13699 \core_core_core_exc_$signal$5 - assign $2\core_core_core_exc_$signal$6$next[0:0]$13700 \core_core_core_exc_$signal$6 - assign $2\core_core_core_exc_$signal$7$next[0:0]$13701 \core_core_core_exc_$signal$7 - assign $2\core_core_core_exc_$signal$8$next[0:0]$13702 \core_core_core_exc_$signal$8 - assign $2\core_core_core_exc_$signal$9$next[0:0]$13703 \core_core_core_exc_$signal$9 - assign $2\core_core_core_exc_$signal$next[0:0]$13704 \core_core_core_exc_$signal - assign $2\core_core_core_fn_unit$next[13:0]$13705 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$13706 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$13707 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$13708 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$13709 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$13710 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$13711 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$13712 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$13713 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$13714 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$13715 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[7:0]$13716 \core_core_core_traptype - assign $2\core_core_cr_in1$next[6:0]$13717 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$13718 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[6:0]$13719 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[6:0]$13720 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$13721 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$13722 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[6:0]$13723 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$13724 \core_core_cr_wr_ok - assign $2\core_core_ea$next[6:0]$13725 \core_core_ea - assign $2\core_core_fast1$next[2:0]$13726 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$13727 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$13728 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$13729 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$13730 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$13731 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$13732 \core_core_lk - assign $2\core_core_reg1$next[6:0]$13733 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$13734 \core_core_reg1_ok - assign $2\core_core_reg2$next[6:0]$13735 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$13736 \core_core_reg2_ok - assign $2\core_core_reg3$next[6:0]$13737 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$13738 \core_core_reg3_ok - assign $2\core_core_rego$next[6:0]$13739 \core_core_rego - assign $2\core_core_spr1$next[9:0]$13740 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$13741 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$13742 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$13743 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$13744 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$13745 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$13746 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$13747 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$13748 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$13749 \core_spro_ok - assign $2\core_xer_out$next[0:0]$13750 \core_xer_out - end + assign $1\core_asmcode$next[7:0]$13620 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13621 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13622 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13623 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13624 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13625 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13626 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13627 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13628 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13629 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13653 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13660 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13667 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13670 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13675 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13676 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13677 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13678 \core_xer_out attribute \src "libresoc.v:0.0-0.0" case 3'011 - assign $1\core_asmcode$next[7:0]$13633 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$13666 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13673 \core_core_lk - assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$13680 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13683 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13691 \core_xer_out + assign $1\core_asmcode$next[7:0]$13620 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13621 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13622 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13623 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13624 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13625 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13626 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13627 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13628 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13629 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13653 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13660 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13667 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13670 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13675 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13676 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13677 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13678 \core_xer_out attribute \src "libresoc.v:0.0-0.0" case 3'100 - assign $1\core_asmcode$next[7:0]$13633 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$13666 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13673 \core_core_lk - assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$13680 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13683 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13691 \core_xer_out - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign $1\core_asmcode$next[7:0]$13633 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$13666 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13673 \core_core_lk - assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$13680 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13683 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13691 \core_xer_out + assign $1\core_asmcode$next[7:0]$13620 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13621 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13622 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13623 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13624 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13625 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13626 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13627 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13628 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13629 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13653 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13660 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13667 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13670 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13675 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13676 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13677 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13678 \core_xer_out attribute \src "libresoc.v:0.0-0.0" case 3'101 - assign $1\core_asmcode$next[7:0]$13633 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$13666 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13673 \core_core_lk - assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$13680 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13683 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13691 \core_xer_out + assign $1\core_asmcode$next[7:0]$13620 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13621 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13622 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13623 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13624 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13625 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13626 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13627 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13628 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13629 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13653 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13660 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13667 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13670 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13675 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13676 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13677 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13678 \core_xer_out attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'010 assign { } { } assign { } { } assign { } { } @@ -380571,67 +379709,67 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_core_is_32bit$next[0:0]$13650 $1\core_core_cr_wr_ok$next[0:0]$13665 $1\core_core_core_cr_wr$next[7:0]$13637 $1\core_core_core_cr_rd_ok$next[0:0]$13636 $1\core_core_core_cr_rd$next[7:0]$13635 $1\core_core_core_trapaddr$next[12:0]$13656 $1\core_core_core_exc_$signal$9$next[0:0]$13644 $1\core_core_core_exc_$signal$8$next[0:0]$13643 $1\core_core_core_exc_$signal$7$next[0:0]$13642 $1\core_core_core_exc_$signal$6$next[0:0]$13641 $1\core_core_core_exc_$signal$5$next[0:0]$13640 $1\core_core_core_exc_$signal$4$next[0:0]$13639 $1\core_core_core_exc_$signal$3$next[0:0]$13638 $1\core_core_core_exc_$signal$next[0:0]$13645 $1\core_core_core_traptype$next[7:0]$13657 $1\core_core_core_input_carry$next[1:0]$13647 $1\core_core_core_oe_ok$next[0:0]$13653 $1\core_core_core_oe$next[0:0]$13652 $1\core_core_core_rc_ok$next[0:0]$13655 $1\core_core_core_rc$next[0:0]$13654 $1\core_core_lk$next[0:0]$13673 $1\core_core_core_fn_unit$next[13:0]$13646 $1\core_core_core_insn_type$next[6:0]$13649 $1\core_core_core_insn$next[31:0]$13648 $1\core_core_core_cia$next[63:0]$13634 $1\core_core_core_msr$next[63:0]$13651 $1\core_cr_out_ok$next[0:0]$13685 $1\core_core_cr_out$next[6:0]$13664 $1\core_core_cr_in2_ok$2$next[0:0]$13662 $1\core_core_cr_in2$1$next[6:0]$13660 $1\core_core_cr_in2_ok$next[0:0]$13663 $1\core_core_cr_in2$next[6:0]$13661 $1\core_core_cr_in1_ok$next[0:0]$13659 $1\core_core_cr_in1$next[6:0]$13658 $1\core_fasto2_ok$next[0:0]$13688 $1\core_core_fasto2$next[2:0]$13672 $1\core_fasto1_ok$next[0:0]$13687 $1\core_core_fasto1$next[2:0]$13671 $1\core_core_fast2_ok$next[0:0]$13670 $1\core_core_fast2$next[2:0]$13669 $1\core_core_fast1_ok$next[0:0]$13668 $1\core_core_fast1$next[2:0]$13667 $1\core_xer_out$next[0:0]$13691 $1\core_core_xer_in$next[2:0]$13684 $1\core_core_spr1_ok$next[0:0]$13682 $1\core_core_spr1$next[9:0]$13681 $1\core_spro_ok$next[0:0]$13690 $1\core_core_spro$next[9:0]$13683 $1\core_core_reg3_ok$next[0:0]$13679 $1\core_core_reg3$next[6:0]$13678 $1\core_core_reg2_ok$next[0:0]$13677 $1\core_core_reg2$next[6:0]$13676 $1\core_core_reg1_ok$next[0:0]$13675 $1\core_core_reg1$next[6:0]$13674 $1\core_ea_ok$next[0:0]$13686 $1\core_core_ea$next[6:0]$13666 $1\core_rego_ok$next[0:0]$13689 $1\core_core_rego$next[6:0]$13680 $1\core_asmcode$next[7:0]$13633 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $1\core_core_core_is_32bit$next[0:0]$13637 $1\core_core_cr_wr_ok$next[0:0]$13652 $1\core_core_core_cr_wr$next[7:0]$13624 $1\core_core_core_cr_rd_ok$next[0:0]$13623 $1\core_core_core_cr_rd$next[7:0]$13622 $1\core_core_core_trapaddr$next[12:0]$13643 $1\core_core_core_exc_$signal$9$next[0:0]$13631 $1\core_core_core_exc_$signal$8$next[0:0]$13630 $1\core_core_core_exc_$signal$7$next[0:0]$13629 $1\core_core_core_exc_$signal$6$next[0:0]$13628 $1\core_core_core_exc_$signal$5$next[0:0]$13627 $1\core_core_core_exc_$signal$4$next[0:0]$13626 $1\core_core_core_exc_$signal$3$next[0:0]$13625 $1\core_core_core_exc_$signal$next[0:0]$13632 $1\core_core_core_traptype$next[7:0]$13644 $1\core_core_core_input_carry$next[1:0]$13634 $1\core_core_core_oe_ok$next[0:0]$13640 $1\core_core_core_oe$next[0:0]$13639 $1\core_core_core_rc_ok$next[0:0]$13642 $1\core_core_core_rc$next[0:0]$13641 $1\core_core_lk$next[0:0]$13660 $1\core_core_core_fn_unit$next[13:0]$13633 $1\core_core_core_insn_type$next[6:0]$13636 $1\core_core_core_insn$next[31:0]$13635 $1\core_core_core_cia$next[63:0]$13621 $1\core_core_core_msr$next[63:0]$13638 $1\core_cr_out_ok$next[0:0]$13672 $1\core_core_cr_out$next[6:0]$13651 $1\core_core_cr_in2_ok$2$next[0:0]$13649 $1\core_core_cr_in2$1$next[6:0]$13647 $1\core_core_cr_in2_ok$next[0:0]$13650 $1\core_core_cr_in2$next[6:0]$13648 $1\core_core_cr_in1_ok$next[0:0]$13646 $1\core_core_cr_in1$next[6:0]$13645 $1\core_fasto2_ok$next[0:0]$13675 $1\core_core_fasto2$next[2:0]$13659 $1\core_fasto1_ok$next[0:0]$13674 $1\core_core_fasto1$next[2:0]$13658 $1\core_core_fast2_ok$next[0:0]$13657 $1\core_core_fast2$next[2:0]$13656 $1\core_core_fast1_ok$next[0:0]$13655 $1\core_core_fast1$next[2:0]$13654 $1\core_xer_out$next[0:0]$13678 $1\core_core_xer_in$next[2:0]$13671 $1\core_core_spr1_ok$next[0:0]$13669 $1\core_core_spr1$next[9:0]$13668 $1\core_spro_ok$next[0:0]$13677 $1\core_core_spro$next[9:0]$13670 $1\core_core_reg3_ok$next[0:0]$13666 $1\core_core_reg3$next[6:0]$13665 $1\core_core_reg2_ok$next[0:0]$13664 $1\core_core_reg2$next[6:0]$13663 $1\core_core_reg1_ok$next[0:0]$13662 $1\core_core_reg1$next[6:0]$13661 $1\core_ea_ok$next[0:0]$13673 $1\core_core_ea$next[6:0]$13653 $1\core_rego_ok$next[0:0]$13676 $1\core_core_rego$next[6:0]$13667 $1\core_asmcode$next[7:0]$13620 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $1\core_asmcode$next[7:0]$13633 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$13666 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13673 \core_core_lk - assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$13680 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13683 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13691 \core_xer_out + assign $1\core_asmcode$next[7:0]$13620 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13621 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13622 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13623 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13624 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13625 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13626 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13627 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13628 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13629 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13653 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13660 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13667 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13670 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13675 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13676 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13677 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13678 \core_xer_out end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -380664,131 +379802,131 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_rego_ok$next[0:0]$13776 1'0 - assign $3\core_ea_ok$next[0:0]$13773 1'0 - assign $3\core_core_reg1_ok$next[0:0]$13768 1'0 - assign $3\core_core_reg2_ok$next[0:0]$13769 1'0 - assign $3\core_core_reg3_ok$next[0:0]$13770 1'0 - assign $3\core_spro_ok$next[0:0]$13777 1'0 - assign $3\core_core_spr1_ok$next[0:0]$13771 1'0 - assign $3\core_core_fast1_ok$next[0:0]$13766 1'0 - assign $3\core_core_fast2_ok$next[0:0]$13767 1'0 - assign $3\core_fasto1_ok$next[0:0]$13774 1'0 - assign $3\core_fasto2_ok$next[0:0]$13775 1'0 - assign $3\core_core_cr_in1_ok$next[0:0]$13762 1'0 - assign $3\core_core_cr_in2_ok$next[0:0]$13764 1'0 - assign $3\core_core_cr_in2_ok$2$next[0:0]$13763 1'0 - assign $3\core_cr_out_ok$next[0:0]$13772 1'0 - assign $3\core_core_core_rc_ok$next[0:0]$13761 1'0 - assign $3\core_core_core_oe_ok$next[0:0]$13760 1'0 - assign $3\core_core_core_exc_$signal$next[0:0]$13759 1'0 - assign $3\core_core_core_exc_$signal$3$next[0:0]$13752 1'0 - assign $3\core_core_core_exc_$signal$4$next[0:0]$13753 1'0 - assign $3\core_core_core_exc_$signal$5$next[0:0]$13754 1'0 - assign $3\core_core_core_exc_$signal$6$next[0:0]$13755 1'0 - assign $3\core_core_core_exc_$signal$7$next[0:0]$13756 1'0 - assign $3\core_core_core_exc_$signal$8$next[0:0]$13757 1'0 - assign $3\core_core_core_exc_$signal$9$next[0:0]$13758 1'0 - assign $3\core_core_core_cr_rd_ok$next[0:0]$13751 1'0 - assign $3\core_core_cr_wr_ok$next[0:0]$13765 1'0 + assign $2\core_rego_ok$next[0:0]$13704 1'0 + assign $2\core_ea_ok$next[0:0]$13701 1'0 + assign $2\core_core_reg1_ok$next[0:0]$13696 1'0 + assign $2\core_core_reg2_ok$next[0:0]$13697 1'0 + assign $2\core_core_reg3_ok$next[0:0]$13698 1'0 + assign $2\core_spro_ok$next[0:0]$13705 1'0 + assign $2\core_core_spr1_ok$next[0:0]$13699 1'0 + assign $2\core_core_fast1_ok$next[0:0]$13694 1'0 + assign $2\core_core_fast2_ok$next[0:0]$13695 1'0 + assign $2\core_fasto1_ok$next[0:0]$13702 1'0 + assign $2\core_fasto2_ok$next[0:0]$13703 1'0 + assign $2\core_core_cr_in1_ok$next[0:0]$13690 1'0 + assign $2\core_core_cr_in2_ok$next[0:0]$13692 1'0 + assign $2\core_core_cr_in2_ok$2$next[0:0]$13691 1'0 + assign $2\core_cr_out_ok$next[0:0]$13700 1'0 + assign $2\core_core_core_rc_ok$next[0:0]$13689 1'0 + assign $2\core_core_core_oe_ok$next[0:0]$13688 1'0 + assign $2\core_core_core_exc_$signal$next[0:0]$13687 1'0 + assign $2\core_core_core_exc_$signal$3$next[0:0]$13680 1'0 + assign $2\core_core_core_exc_$signal$4$next[0:0]$13681 1'0 + assign $2\core_core_core_exc_$signal$5$next[0:0]$13682 1'0 + assign $2\core_core_core_exc_$signal$6$next[0:0]$13683 1'0 + assign $2\core_core_core_exc_$signal$7$next[0:0]$13684 1'0 + assign $2\core_core_core_exc_$signal$8$next[0:0]$13685 1'0 + assign $2\core_core_core_exc_$signal$9$next[0:0]$13686 1'0 + assign $2\core_core_core_cr_rd_ok$next[0:0]$13679 1'0 + assign $2\core_core_cr_wr_ok$next[0:0]$13693 1'0 case - assign $3\core_core_core_cr_rd_ok$next[0:0]$13751 $1\core_core_core_cr_rd_ok$next[0:0]$13636 - assign $3\core_core_core_exc_$signal$3$next[0:0]$13752 $1\core_core_core_exc_$signal$3$next[0:0]$13638 - assign $3\core_core_core_exc_$signal$4$next[0:0]$13753 $1\core_core_core_exc_$signal$4$next[0:0]$13639 - assign $3\core_core_core_exc_$signal$5$next[0:0]$13754 $1\core_core_core_exc_$signal$5$next[0:0]$13640 - assign $3\core_core_core_exc_$signal$6$next[0:0]$13755 $1\core_core_core_exc_$signal$6$next[0:0]$13641 - assign $3\core_core_core_exc_$signal$7$next[0:0]$13756 $1\core_core_core_exc_$signal$7$next[0:0]$13642 - assign $3\core_core_core_exc_$signal$8$next[0:0]$13757 $1\core_core_core_exc_$signal$8$next[0:0]$13643 - assign $3\core_core_core_exc_$signal$9$next[0:0]$13758 $1\core_core_core_exc_$signal$9$next[0:0]$13644 - assign $3\core_core_core_exc_$signal$next[0:0]$13759 $1\core_core_core_exc_$signal$next[0:0]$13645 - assign $3\core_core_core_oe_ok$next[0:0]$13760 $1\core_core_core_oe_ok$next[0:0]$13653 - assign $3\core_core_core_rc_ok$next[0:0]$13761 $1\core_core_core_rc_ok$next[0:0]$13655 - assign $3\core_core_cr_in1_ok$next[0:0]$13762 $1\core_core_cr_in1_ok$next[0:0]$13659 - assign $3\core_core_cr_in2_ok$2$next[0:0]$13763 $1\core_core_cr_in2_ok$2$next[0:0]$13662 - assign $3\core_core_cr_in2_ok$next[0:0]$13764 $1\core_core_cr_in2_ok$next[0:0]$13663 - assign $3\core_core_cr_wr_ok$next[0:0]$13765 $1\core_core_cr_wr_ok$next[0:0]$13665 - assign $3\core_core_fast1_ok$next[0:0]$13766 $1\core_core_fast1_ok$next[0:0]$13668 - assign $3\core_core_fast2_ok$next[0:0]$13767 $1\core_core_fast2_ok$next[0:0]$13670 - assign $3\core_core_reg1_ok$next[0:0]$13768 $1\core_core_reg1_ok$next[0:0]$13675 - assign $3\core_core_reg2_ok$next[0:0]$13769 $1\core_core_reg2_ok$next[0:0]$13677 - assign $3\core_core_reg3_ok$next[0:0]$13770 $1\core_core_reg3_ok$next[0:0]$13679 - assign $3\core_core_spr1_ok$next[0:0]$13771 $1\core_core_spr1_ok$next[0:0]$13682 - assign $3\core_cr_out_ok$next[0:0]$13772 $1\core_cr_out_ok$next[0:0]$13685 - assign $3\core_ea_ok$next[0:0]$13773 $1\core_ea_ok$next[0:0]$13686 - assign $3\core_fasto1_ok$next[0:0]$13774 $1\core_fasto1_ok$next[0:0]$13687 - assign $3\core_fasto2_ok$next[0:0]$13775 $1\core_fasto2_ok$next[0:0]$13688 - assign $3\core_rego_ok$next[0:0]$13776 $1\core_rego_ok$next[0:0]$13689 - assign $3\core_spro_ok$next[0:0]$13777 $1\core_spro_ok$next[0:0]$13690 + assign $2\core_core_core_cr_rd_ok$next[0:0]$13679 $1\core_core_core_cr_rd_ok$next[0:0]$13623 + assign $2\core_core_core_exc_$signal$3$next[0:0]$13680 $1\core_core_core_exc_$signal$3$next[0:0]$13625 + assign $2\core_core_core_exc_$signal$4$next[0:0]$13681 $1\core_core_core_exc_$signal$4$next[0:0]$13626 + assign $2\core_core_core_exc_$signal$5$next[0:0]$13682 $1\core_core_core_exc_$signal$5$next[0:0]$13627 + assign $2\core_core_core_exc_$signal$6$next[0:0]$13683 $1\core_core_core_exc_$signal$6$next[0:0]$13628 + assign $2\core_core_core_exc_$signal$7$next[0:0]$13684 $1\core_core_core_exc_$signal$7$next[0:0]$13629 + assign $2\core_core_core_exc_$signal$8$next[0:0]$13685 $1\core_core_core_exc_$signal$8$next[0:0]$13630 + assign $2\core_core_core_exc_$signal$9$next[0:0]$13686 $1\core_core_core_exc_$signal$9$next[0:0]$13631 + assign $2\core_core_core_exc_$signal$next[0:0]$13687 $1\core_core_core_exc_$signal$next[0:0]$13632 + assign $2\core_core_core_oe_ok$next[0:0]$13688 $1\core_core_core_oe_ok$next[0:0]$13640 + assign $2\core_core_core_rc_ok$next[0:0]$13689 $1\core_core_core_rc_ok$next[0:0]$13642 + assign $2\core_core_cr_in1_ok$next[0:0]$13690 $1\core_core_cr_in1_ok$next[0:0]$13646 + assign $2\core_core_cr_in2_ok$2$next[0:0]$13691 $1\core_core_cr_in2_ok$2$next[0:0]$13649 + assign $2\core_core_cr_in2_ok$next[0:0]$13692 $1\core_core_cr_in2_ok$next[0:0]$13650 + assign $2\core_core_cr_wr_ok$next[0:0]$13693 $1\core_core_cr_wr_ok$next[0:0]$13652 + assign $2\core_core_fast1_ok$next[0:0]$13694 $1\core_core_fast1_ok$next[0:0]$13655 + assign $2\core_core_fast2_ok$next[0:0]$13695 $1\core_core_fast2_ok$next[0:0]$13657 + assign $2\core_core_reg1_ok$next[0:0]$13696 $1\core_core_reg1_ok$next[0:0]$13662 + assign $2\core_core_reg2_ok$next[0:0]$13697 $1\core_core_reg2_ok$next[0:0]$13664 + assign $2\core_core_reg3_ok$next[0:0]$13698 $1\core_core_reg3_ok$next[0:0]$13666 + assign $2\core_core_spr1_ok$next[0:0]$13699 $1\core_core_spr1_ok$next[0:0]$13669 + assign $2\core_cr_out_ok$next[0:0]$13700 $1\core_cr_out_ok$next[0:0]$13672 + assign $2\core_ea_ok$next[0:0]$13701 $1\core_ea_ok$next[0:0]$13673 + assign $2\core_fasto1_ok$next[0:0]$13702 $1\core_fasto1_ok$next[0:0]$13674 + assign $2\core_fasto2_ok$next[0:0]$13703 $1\core_fasto2_ok$next[0:0]$13675 + assign $2\core_rego_ok$next[0:0]$13704 $1\core_rego_ok$next[0:0]$13676 + assign $2\core_spro_ok$next[0:0]$13705 $1\core_spro_ok$next[0:0]$13677 end sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$13574 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13575 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13576 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13577 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13578 - update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13579 - update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13580 - update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13581 - update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13582 - update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13583 - update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13584 - update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13585 - update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13586 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13587 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13588 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13589 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13590 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13591 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13592 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13593 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13594 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13595 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13596 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13597 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13598 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13599 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13600 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13601 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13602 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13603 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13604 - update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13605 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13606 - update \core_core_ea$next $0\core_core_ea$next[6:0]$13607 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13608 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13609 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13610 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13611 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13612 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13613 - update \core_core_lk$next $0\core_core_lk$next[0:0]$13614 - update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13615 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13616 - update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13617 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13618 - update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13619 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13620 - update \core_core_rego$next $0\core_core_rego$next[6:0]$13621 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13622 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13623 - update \core_core_spro$next $0\core_core_spro$next[9:0]$13624 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13625 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13626 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13627 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13628 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13629 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13630 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13631 - update \core_xer_out$next $0\core_xer_out$next[0:0]$13632 - end - attribute \src "libresoc.v:200526.3-200534.6" - process $proc$libresoc.v:200526$13778 - assign { } { } - assign { } { } - assign $0\dec2_cur_eint$next[0:0]$13779 $1\dec2_cur_eint$next[0:0]$13780 - attribute \src "libresoc.v:200527.5-200527.29" - switch \initial - attribute \src "libresoc.v:200527.9-200527.17" + update \core_asmcode$next $0\core_asmcode$next[7:0]$13561 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13562 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13563 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13564 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13565 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13566 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13567 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13568 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13569 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13570 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13571 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13572 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13573 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13574 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13575 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13576 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13577 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13578 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13579 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13580 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13581 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13582 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13583 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13584 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13585 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13586 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13587 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13588 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13589 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13590 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13591 + update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13592 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13593 + update \core_core_ea$next $0\core_core_ea$next[6:0]$13594 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13595 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13596 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13597 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13598 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13599 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13600 + update \core_core_lk$next $0\core_core_lk$next[0:0]$13601 + update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13602 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13603 + update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13604 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13605 + update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13606 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13607 + update \core_core_rego$next $0\core_core_rego$next[6:0]$13608 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13609 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13610 + update \core_core_spro$next $0\core_core_spro$next[9:0]$13611 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13612 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13613 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13614 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13615 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13616 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13617 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13618 + update \core_xer_out$next $0\core_xer_out$next[0:0]$13619 + end + attribute \src "libresoc.v:200123.3-200131.6" + process $proc$libresoc.v:200123$13706 + assign { } { } + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$13707 $1\dec2_cur_eint$next[0:0]$13708 + attribute \src "libresoc.v:200124.5-200124.29" + switch \initial + attribute \src "libresoc.v:200124.9-200124.17" case 1'1 case end @@ -380797,163 +379935,164 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dec2_cur_eint$next[0:0]$13780 1'0 + assign $1\dec2_cur_eint$next[0:0]$13708 1'0 case - assign $1\dec2_cur_eint$next[0:0]$13780 \xics_icp_core_irq_o + assign $1\dec2_cur_eint$next[0:0]$13708 \xics_icp_core_irq_o end sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13779 + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13707 end - attribute \src "libresoc.v:200535.3-200544.6" - process $proc$libresoc.v:200535$13781 + attribute \src "libresoc.v:200132.3-200141.6" + process $proc$libresoc.v:200132$13709 assign { } { } assign { } { } - assign $0\delay$next[1:0]$13782 $1\delay$next[1:0]$13783 - attribute \src "libresoc.v:200536.5-200536.29" + assign $0\delay$next[1:0]$13710 $1\delay$next[1:0]$13711 + attribute \src "libresoc.v:200133.5-200133.29" switch \initial - attribute \src "libresoc.v:200536.9-200536.17" + attribute \src "libresoc.v:200133.9-200133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:830" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\delay$next[1:0]$13783 \$25 [1:0] + assign $1\delay$next[1:0]$13711 \$25 [1:0] case - assign $1\delay$next[1:0]$13783 \delay + assign $1\delay$next[1:0]$13711 \delay end sync always - update \delay$next $0\delay$next[1:0]$13782 + update \delay$next $0\delay$next[1:0]$13710 end - connect \$101 $add$libresoc.v:197529$13083_Y - connect \$103 $mul$libresoc.v:197530$13084_Y - connect \$99 $shr$libresoc.v:197531$13085_Y [31:0] - connect \$106 $not$libresoc.v:197532$13086_Y - connect \$108 $not$libresoc.v:197533$13087_Y - connect \$110 $and$libresoc.v:197534$13088_Y - connect \$112 $not$libresoc.v:197535$13089_Y - connect \$114 $not$libresoc.v:197536$13090_Y - connect \$116 $and$libresoc.v:197537$13091_Y - connect \$118 $or$libresoc.v:197538$13092_Y + connect \$101 $add$libresoc.v:197050$13081_Y + connect \$103 $mul$libresoc.v:197051$13082_Y + connect \$99 $shr$libresoc.v:197052$13083_Y [31:0] + connect \$106 $not$libresoc.v:197053$13084_Y + connect \$108 $not$libresoc.v:197054$13085_Y + connect \$110 $and$libresoc.v:197055$13086_Y + connect \$112 $not$libresoc.v:197056$13087_Y + connect \$114 $not$libresoc.v:197057$13088_Y + connect \$116 $and$libresoc.v:197058$13089_Y + connect \$118 $or$libresoc.v:197059$13090_Y connect \$120 1'1 - connect \$122 $or$libresoc.v:197540$13093_Y - connect \$125 $add$libresoc.v:197541$13094_Y - connect \$128 $add$libresoc.v:197542$13095_Y - connect \$130 $not$libresoc.v:197543$13096_Y - connect \$132 $not$libresoc.v:197544$13097_Y - connect \$134 $and$libresoc.v:197545$13098_Y - connect \$136 $not$libresoc.v:197546$13099_Y - connect \$138 $not$libresoc.v:197547$13100_Y - connect \$140 $and$libresoc.v:197548$13101_Y - connect \$142 $eq$libresoc.v:197549$13102_Y - connect \$144 $and$libresoc.v:197550$13103_Y - connect \$146 $not$libresoc.v:197551$13104_Y - connect \$148 $not$libresoc.v:197552$13105_Y - connect \$150 $and$libresoc.v:197553$13106_Y - connect \$152 $or$libresoc.v:197554$13107_Y - connect \$154 1'1 - connect \$156 $or$libresoc.v:197556$13108_Y - connect \$158 $not$libresoc.v:197557$13109_Y - connect \$160 $not$libresoc.v:197558$13110_Y - connect \$162 $and$libresoc.v:197559$13111_Y - connect \$164 $not$libresoc.v:197560$13112_Y - connect \$166 $not$libresoc.v:197561$13113_Y - connect \$168 $and$libresoc.v:197562$13114_Y - connect \$170 $not$libresoc.v:197563$13115_Y - connect \$172 $not$libresoc.v:197564$13116_Y - connect \$174 $and$libresoc.v:197565$13117_Y - connect \$176 $not$libresoc.v:197566$13118_Y - connect \$178 $not$libresoc.v:197567$13119_Y - connect \$180 $and$libresoc.v:197568$13120_Y - connect \$182 $not$libresoc.v:197569$13121_Y - connect \$184 $not$libresoc.v:197570$13122_Y - connect \$186 $and$libresoc.v:197571$13123_Y - connect \$188 $not$libresoc.v:197572$13124_Y - connect \$190 $not$libresoc.v:197573$13125_Y - connect \$192 $and$libresoc.v:197574$13126_Y - connect \$195 $and$libresoc.v:197575$13127_Y - connect \$194 $reduce_or$libresoc.v:197576$13128_Y - connect \$198 $not$libresoc.v:197577$13129_Y - connect \$200 $not$libresoc.v:197578$13130_Y - connect \$202 $and$libresoc.v:197579$13131_Y - connect \$204 $not$libresoc.v:197580$13132_Y - connect \$206 $not$libresoc.v:197581$13133_Y - connect \$208 $and$libresoc.v:197582$13134_Y - connect \$210 $or$libresoc.v:197583$13135_Y - connect \$212 1'1 - connect \$214 $or$libresoc.v:197585$13136_Y - connect \$216 $not$libresoc.v:197586$13137_Y - connect \$218 $not$libresoc.v:197587$13138_Y - connect \$220 $and$libresoc.v:197588$13139_Y - connect \$222 $not$libresoc.v:197589$13140_Y - connect \$224 $not$libresoc.v:197590$13141_Y - connect \$226 $and$libresoc.v:197591$13142_Y - connect \$229 $and$libresoc.v:197592$13143_Y - connect \$228 $reduce_or$libresoc.v:197593$13144_Y - connect \$232 $eq$libresoc.v:197594$13145_Y - connect \$234 $and$libresoc.v:197595$13146_Y - connect \$236 $not$libresoc.v:197596$13147_Y - connect \$238 $not$libresoc.v:197597$13148_Y - connect \$23 $ne$libresoc.v:197598$13149_Y - connect \$240 $not$libresoc.v:197599$13150_Y - connect \$242 $and$libresoc.v:197600$13151_Y - connect \$244 $not$libresoc.v:197601$13152_Y - connect \$246 $not$libresoc.v:197602$13153_Y - connect \$248 $and$libresoc.v:197603$13154_Y - connect \$250 $eq$libresoc.v:197604$13155_Y - connect \$252 $pos$libresoc.v:197605$13156_Y - connect \$254 $ne$libresoc.v:197606$13157_Y - connect \$256 $not$libresoc.v:197607$13158_Y - connect \$258 $not$libresoc.v:197608$13159_Y - connect \$260 $pos$libresoc.v:197609$13161_Y - connect \$262 $pos$libresoc.v:197610$13163_Y - connect \$265 $sub$libresoc.v:197611$13164_Y - connect \$268 $add$libresoc.v:197612$13165_Y - connect \$26 $sub$libresoc.v:197613$13166_Y - connect \$28 $or$libresoc.v:197614$13167_Y - connect \$30 $or$libresoc.v:197615$13168_Y - connect \$32 $ne$libresoc.v:197616$13169_Y - connect \$34 $not$libresoc.v:197617$13170_Y - connect \$36 $and$libresoc.v:197618$13171_Y - connect \$38 $not$libresoc.v:197619$13172_Y - connect \$40 $not$libresoc.v:197620$13173_Y - connect \$42 $pos$libresoc.v:197621$13175_Y - connect \$44 $not$libresoc.v:197622$13176_Y - connect \$46 $not$libresoc.v:197623$13177_Y - connect \$48 $and$libresoc.v:197624$13178_Y - connect \$50 $eq$libresoc.v:197625$13179_Y - connect \$52 $and$libresoc.v:197626$13180_Y - connect \$54 $not$libresoc.v:197627$13181_Y - connect \$56 $not$libresoc.v:197628$13182_Y - connect \$58 $and$libresoc.v:197629$13183_Y - connect \$60 $or$libresoc.v:197630$13184_Y + connect \$122 $or$libresoc.v:197061$13091_Y + connect \$125 $add$libresoc.v:197062$13092_Y + connect \$128 $add$libresoc.v:197063$13093_Y + connect \$130 $not$libresoc.v:197064$13094_Y + connect \$132 $not$libresoc.v:197065$13095_Y + connect \$134 $and$libresoc.v:197066$13096_Y + connect \$136 $not$libresoc.v:197067$13097_Y + connect \$138 $not$libresoc.v:197068$13098_Y + connect \$140 $and$libresoc.v:197069$13099_Y + connect \$142 $eq$libresoc.v:197070$13100_Y + connect \$144 $and$libresoc.v:197071$13101_Y + connect \$146 $not$libresoc.v:197072$13102_Y + connect \$148 $not$libresoc.v:197073$13103_Y + connect \$150 $not$libresoc.v:197074$13104_Y + connect \$152 $and$libresoc.v:197075$13105_Y + connect \$154 $or$libresoc.v:197076$13106_Y + connect \$156 1'1 + connect \$158 $or$libresoc.v:197078$13107_Y + connect \$160 $not$libresoc.v:197079$13108_Y + connect \$162 $not$libresoc.v:197080$13109_Y + connect \$164 $and$libresoc.v:197081$13110_Y + connect \$166 $not$libresoc.v:197082$13111_Y + connect \$168 $not$libresoc.v:197083$13112_Y + connect \$170 $and$libresoc.v:197084$13113_Y + connect \$172 $not$libresoc.v:197085$13114_Y + connect \$174 $not$libresoc.v:197086$13115_Y + connect \$176 $and$libresoc.v:197087$13116_Y + connect \$178 $not$libresoc.v:197088$13117_Y + connect \$180 $not$libresoc.v:197089$13118_Y + connect \$182 $and$libresoc.v:197090$13119_Y + connect \$184 $not$libresoc.v:197091$13120_Y + connect \$186 $not$libresoc.v:197092$13121_Y + connect \$188 $and$libresoc.v:197093$13122_Y + connect \$190 $not$libresoc.v:197094$13123_Y + connect \$192 $not$libresoc.v:197095$13124_Y + connect \$194 $and$libresoc.v:197096$13125_Y + connect \$197 $and$libresoc.v:197097$13126_Y + connect \$196 $reduce_or$libresoc.v:197098$13127_Y + connect \$200 $not$libresoc.v:197099$13128_Y + connect \$202 $not$libresoc.v:197100$13129_Y + connect \$204 $and$libresoc.v:197101$13130_Y + connect \$206 $not$libresoc.v:197102$13131_Y + connect \$208 $not$libresoc.v:197103$13132_Y + connect \$210 $and$libresoc.v:197104$13133_Y + connect \$212 $or$libresoc.v:197105$13134_Y + connect \$214 1'1 + connect \$216 $or$libresoc.v:197107$13135_Y + connect \$218 $not$libresoc.v:197108$13136_Y + connect \$220 $not$libresoc.v:197109$13137_Y + connect \$222 $and$libresoc.v:197110$13138_Y + connect \$224 $not$libresoc.v:197111$13139_Y + connect \$226 $not$libresoc.v:197112$13140_Y + connect \$228 $and$libresoc.v:197113$13141_Y + connect \$231 $and$libresoc.v:197114$13142_Y + connect \$230 $reduce_or$libresoc.v:197115$13143_Y + connect \$234 $eq$libresoc.v:197116$13144_Y + connect \$236 $and$libresoc.v:197117$13145_Y + connect \$238 $not$libresoc.v:197118$13146_Y + connect \$23 $ne$libresoc.v:197119$13147_Y + connect \$240 $not$libresoc.v:197120$13148_Y + connect \$242 $not$libresoc.v:197121$13149_Y + connect \$244 $and$libresoc.v:197122$13150_Y + connect \$246 $not$libresoc.v:197123$13151_Y + connect \$248 $not$libresoc.v:197124$13152_Y + connect \$250 $and$libresoc.v:197125$13153_Y + connect \$252 $eq$libresoc.v:197126$13154_Y + connect \$254 $pos$libresoc.v:197127$13155_Y + connect \$256 $ne$libresoc.v:197128$13156_Y + connect \$258 $not$libresoc.v:197129$13157_Y + connect \$260 $not$libresoc.v:197130$13158_Y + connect \$262 $pos$libresoc.v:197131$13160_Y + connect \$264 $pos$libresoc.v:197132$13162_Y + connect \$267 $sub$libresoc.v:197133$13163_Y + connect \$26 $sub$libresoc.v:197134$13164_Y + connect \$270 $add$libresoc.v:197135$13165_Y + connect \$28 $or$libresoc.v:197136$13166_Y + connect \$30 $or$libresoc.v:197137$13167_Y + connect \$32 $ne$libresoc.v:197138$13168_Y + connect \$34 $not$libresoc.v:197139$13169_Y + connect \$36 $and$libresoc.v:197140$13170_Y + connect \$38 $not$libresoc.v:197141$13171_Y + connect \$40 $not$libresoc.v:197142$13172_Y + connect \$42 $pos$libresoc.v:197143$13174_Y + connect \$44 $not$libresoc.v:197144$13175_Y + connect \$46 $not$libresoc.v:197145$13176_Y + connect \$48 $and$libresoc.v:197146$13177_Y + connect \$50 $eq$libresoc.v:197147$13178_Y + connect \$52 $and$libresoc.v:197148$13179_Y + connect \$54 $not$libresoc.v:197149$13180_Y + connect \$56 $not$libresoc.v:197150$13181_Y + connect \$58 $and$libresoc.v:197151$13182_Y + connect \$60 $or$libresoc.v:197152$13183_Y connect \$62 1'1 - connect \$64 $or$libresoc.v:197632$13185_Y - connect \$66 $not$libresoc.v:197633$13186_Y - connect \$68 $not$libresoc.v:197634$13187_Y - connect \$70 $and$libresoc.v:197635$13188_Y - connect \$72 $eq$libresoc.v:197636$13189_Y - connect \$74 $and$libresoc.v:197637$13190_Y - connect \$76 $not$libresoc.v:197638$13191_Y - connect \$78 $not$libresoc.v:197639$13192_Y - connect \$80 $and$libresoc.v:197640$13193_Y - connect \$82 $or$libresoc.v:197641$13194_Y + connect \$64 $or$libresoc.v:197154$13184_Y + connect \$66 $not$libresoc.v:197155$13185_Y + connect \$68 $not$libresoc.v:197156$13186_Y + connect \$70 $and$libresoc.v:197157$13187_Y + connect \$72 $eq$libresoc.v:197158$13188_Y + connect \$74 $and$libresoc.v:197159$13189_Y + connect \$76 $not$libresoc.v:197160$13190_Y + connect \$78 $not$libresoc.v:197161$13191_Y + connect \$80 $and$libresoc.v:197162$13192_Y + connect \$82 $or$libresoc.v:197163$13193_Y connect \$84 1'1 - connect \$86 $or$libresoc.v:197643$13195_Y - connect \$88 $not$libresoc.v:197644$13196_Y - connect \$90 $not$libresoc.v:197645$13197_Y - connect \$93 $add$libresoc.v:197646$13198_Y - connect \$96 $mul$libresoc.v:197647$13199_Y - connect \$95 $shr$libresoc.v:197648$13200_Y [31:0] + connect \$86 $or$libresoc.v:197165$13194_Y + connect \$88 $not$libresoc.v:197166$13195_Y + connect \$90 $not$libresoc.v:197167$13196_Y + connect \$93 $add$libresoc.v:197168$13197_Y + connect \$96 $mul$libresoc.v:197169$13198_Y + connect \$95 $shr$libresoc.v:197170$13199_Y [31:0] connect \$25 \$26 connect \$92 \$93 connect \$100 \$101 connect \$124 \$125 connect \$127 \$128 - connect \$264 \$265 - connect \$267 \$268 + connect \$266 \$267 + connect \$269 \$270 connect \dec2_sv_a_nz 1'0 connect \svstate_i_ok 1'0 connect \svstate_i 0 @@ -380978,485 +380117,485 @@ module \ti connect \por_clk \clk connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } end -attribute \src "libresoc.v:200579.1-201770.10" +attribute \src "libresoc.v:200176.1-201367.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" attribute \generator "nMigen" module \trap0 - attribute \src "libresoc.v:201315.3-201316.25" + attribute \src "libresoc.v:200912.3-200913.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:201313.3-201314.41" + attribute \src "libresoc.v:200910.3-200911.41" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:201673.3-201681.6" - wire $0\alu_l_r_alu$next[0:0]$14105 - attribute \src "libresoc.v:201241.3-201242.39" + attribute \src "libresoc.v:201270.3-201278.6" + wire $0\alu_l_r_alu$next[0:0]$14033 + attribute \src "libresoc.v:200838.3-200839.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14031 - attribute \src "libresoc.v:201281.3-201282.61" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$13959 + attribute \src "libresoc.v:200878.3-200879.61" wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14032 - attribute \src "libresoc.v:201275.3-201276.69" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$13960 + attribute \src "libresoc.v:200872.3-200873.69" wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14033 - attribute \src "libresoc.v:201277.3-201278.63" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$13961 + attribute \src "libresoc.v:200874.3-200875.63" wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14034 - attribute \src "libresoc.v:201273.3-201274.73" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$13962 + attribute \src "libresoc.v:200870.3-200871.73" wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14035 - attribute \src "libresoc.v:201283.3-201284.71" + attribute \src "libresoc.v:201093.3-201110.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$13963 + attribute \src "libresoc.v:200880.3-200881.71" wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14036 - attribute \src "libresoc.v:201289.3-201290.71" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$13964 + attribute \src "libresoc.v:200886.3-200887.71" wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14037 - attribute \src "libresoc.v:201279.3-201280.61" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$13965 + attribute \src "libresoc.v:200876.3-200877.61" wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14038 - attribute \src "libresoc.v:201287.3-201288.71" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$13966 + attribute \src "libresoc.v:200884.3-200885.71" wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14039 - attribute \src "libresoc.v:201285.3-201286.71" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$13967 + attribute \src "libresoc.v:200882.3-200883.71" wire width 8 $0\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:201664.3-201672.6" - wire $0\alui_l_r_alui$next[0:0]$14102 - attribute \src "libresoc.v:201243.3-201244.43" + attribute \src "libresoc.v:201261.3-201269.6" + wire $0\alui_l_r_alui$next[0:0]$14030 + attribute \src "libresoc.v:200840.3-200841.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:201514.3-201535.6" - wire width 64 $0\data_r0__o$next[63:0]$14050 - attribute \src "libresoc.v:201269.3-201270.37" + attribute \src "libresoc.v:201111.3-201132.6" + wire width 64 $0\data_r0__o$next[63:0]$13978 + attribute \src "libresoc.v:200866.3-200867.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:201514.3-201535.6" - wire $0\data_r0__o_ok$next[0:0]$14051 - attribute \src "libresoc.v:201271.3-201272.43" + attribute \src "libresoc.v:201111.3-201132.6" + wire $0\data_r0__o_ok$next[0:0]$13979 + attribute \src "libresoc.v:200868.3-200869.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:201536.3-201557.6" - wire width 64 $0\data_r1__fast1$next[63:0]$14058 - attribute \src "libresoc.v:201265.3-201266.45" + attribute \src "libresoc.v:201133.3-201154.6" + wire width 64 $0\data_r1__fast1$next[63:0]$13986 + attribute \src "libresoc.v:200862.3-200863.45" wire width 64 $0\data_r1__fast1[63:0] - attribute \src "libresoc.v:201536.3-201557.6" - wire $0\data_r1__fast1_ok$next[0:0]$14059 - attribute \src "libresoc.v:201267.3-201268.51" + attribute \src "libresoc.v:201133.3-201154.6" + wire $0\data_r1__fast1_ok$next[0:0]$13987 + attribute \src "libresoc.v:200864.3-200865.51" wire $0\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:201558.3-201579.6" - wire width 64 $0\data_r2__fast2$next[63:0]$14066 - attribute \src "libresoc.v:201261.3-201262.45" + attribute \src "libresoc.v:201155.3-201176.6" + wire width 64 $0\data_r2__fast2$next[63:0]$13994 + attribute \src "libresoc.v:200858.3-200859.45" wire width 64 $0\data_r2__fast2[63:0] - attribute \src "libresoc.v:201558.3-201579.6" - wire $0\data_r2__fast2_ok$next[0:0]$14067 - attribute \src "libresoc.v:201263.3-201264.51" + attribute \src "libresoc.v:201155.3-201176.6" + wire $0\data_r2__fast2_ok$next[0:0]$13995 + attribute \src "libresoc.v:200860.3-200861.51" wire $0\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:201580.3-201601.6" - wire width 64 $0\data_r3__nia$next[63:0]$14074 - attribute \src "libresoc.v:201257.3-201258.41" + attribute \src "libresoc.v:201177.3-201198.6" + wire width 64 $0\data_r3__nia$next[63:0]$14002 + attribute \src "libresoc.v:200854.3-200855.41" wire width 64 $0\data_r3__nia[63:0] - attribute \src "libresoc.v:201580.3-201601.6" - wire $0\data_r3__nia_ok$next[0:0]$14075 - attribute \src "libresoc.v:201259.3-201260.47" + attribute \src "libresoc.v:201177.3-201198.6" + wire $0\data_r3__nia_ok$next[0:0]$14003 + attribute \src "libresoc.v:200856.3-200857.47" wire $0\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:201602.3-201623.6" - wire width 64 $0\data_r4__msr$next[63:0]$14082 - attribute \src "libresoc.v:201253.3-201254.41" + attribute \src "libresoc.v:201199.3-201220.6" + wire width 64 $0\data_r4__msr$next[63:0]$14010 + attribute \src "libresoc.v:200850.3-200851.41" wire width 64 $0\data_r4__msr[63:0] - attribute \src "libresoc.v:201602.3-201623.6" - wire $0\data_r4__msr_ok$next[0:0]$14083 - attribute \src "libresoc.v:201255.3-201256.47" + attribute \src "libresoc.v:201199.3-201220.6" + wire $0\data_r4__msr_ok$next[0:0]$14011 + attribute \src "libresoc.v:200852.3-200853.47" wire $0\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:201682.3-201691.6" + attribute \src "libresoc.v:201279.3-201288.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:201692.3-201701.6" + attribute \src "libresoc.v:201289.3-201298.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:201702.3-201711.6" + attribute \src "libresoc.v:201299.3-201308.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:201712.3-201721.6" + attribute \src "libresoc.v:201309.3-201318.6" wire width 64 $0\dest4_o[63:0] - attribute \src "libresoc.v:201722.3-201731.6" + attribute \src "libresoc.v:201319.3-201328.6" wire width 64 $0\dest5_o[63:0] - attribute \src "libresoc.v:200580.7-200580.20" + attribute \src "libresoc.v:200177.7-200177.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201451.3-201459.6" - wire $0\opc_l_r_opc$next[0:0]$14016 - attribute \src "libresoc.v:201299.3-201300.39" + attribute \src "libresoc.v:201048.3-201056.6" + wire $0\opc_l_r_opc$next[0:0]$13944 + attribute \src "libresoc.v:200896.3-200897.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:201442.3-201450.6" - wire $0\opc_l_s_opc$next[0:0]$14013 - attribute \src "libresoc.v:201301.3-201302.39" + attribute \src "libresoc.v:201039.3-201047.6" + wire $0\opc_l_s_opc$next[0:0]$13941 + attribute \src "libresoc.v:200898.3-200899.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:201732.3-201740.6" - wire width 5 $0\prev_wr_go$next[4:0]$14113 - attribute \src "libresoc.v:201311.3-201312.37" + attribute \src "libresoc.v:201329.3-201337.6" + wire width 5 $0\prev_wr_go$next[4:0]$14041 + attribute \src "libresoc.v:200908.3-200909.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:201396.3-201405.6" + attribute \src "libresoc.v:200993.3-201002.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:201487.3-201495.6" - wire width 5 $0\req_l_r_req$next[4:0]$14028 - attribute \src "libresoc.v:201291.3-201292.39" + attribute \src "libresoc.v:201084.3-201092.6" + wire width 5 $0\req_l_r_req$next[4:0]$13956 + attribute \src "libresoc.v:200888.3-200889.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:201478.3-201486.6" - wire width 5 $0\req_l_s_req$next[4:0]$14025 - attribute \src "libresoc.v:201293.3-201294.39" + attribute \src "libresoc.v:201075.3-201083.6" + wire width 5 $0\req_l_s_req$next[4:0]$13953 + attribute \src "libresoc.v:200890.3-200891.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:201415.3-201423.6" - wire $0\rok_l_r_rdok$next[0:0]$14004 - attribute \src "libresoc.v:201307.3-201308.41" + attribute \src "libresoc.v:201012.3-201020.6" + wire $0\rok_l_r_rdok$next[0:0]$13932 + attribute \src "libresoc.v:200904.3-200905.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:201406.3-201414.6" - wire $0\rok_l_s_rdok$next[0:0]$14001 - attribute \src "libresoc.v:201309.3-201310.41" + attribute \src "libresoc.v:201003.3-201011.6" + wire $0\rok_l_s_rdok$next[0:0]$13929 + attribute \src "libresoc.v:200906.3-200907.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:201433.3-201441.6" - wire $0\rst_l_r_rst$next[0:0]$14010 - attribute \src "libresoc.v:201303.3-201304.39" + attribute \src "libresoc.v:201030.3-201038.6" + wire $0\rst_l_r_rst$next[0:0]$13938 + attribute \src "libresoc.v:200900.3-200901.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:201424.3-201432.6" - wire $0\rst_l_s_rst$next[0:0]$14007 - attribute \src "libresoc.v:201305.3-201306.39" + attribute \src "libresoc.v:201021.3-201029.6" + wire $0\rst_l_s_rst$next[0:0]$13935 + attribute \src "libresoc.v:200902.3-200903.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:201469.3-201477.6" - wire width 4 $0\src_l_r_src$next[3:0]$14022 - attribute \src "libresoc.v:201295.3-201296.39" + attribute \src "libresoc.v:201066.3-201074.6" + wire width 4 $0\src_l_r_src$next[3:0]$13950 + attribute \src "libresoc.v:200892.3-200893.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:201460.3-201468.6" - wire width 4 $0\src_l_s_src$next[3:0]$14019 - attribute \src "libresoc.v:201297.3-201298.39" + attribute \src "libresoc.v:201057.3-201065.6" + wire width 4 $0\src_l_s_src$next[3:0]$13947 + attribute \src "libresoc.v:200894.3-200895.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:201624.3-201633.6" - wire width 64 $0\src_r0$next[63:0]$14090 - attribute \src "libresoc.v:201251.3-201252.29" + attribute \src "libresoc.v:201221.3-201230.6" + wire width 64 $0\src_r0$next[63:0]$14018 + attribute \src "libresoc.v:200848.3-200849.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:201634.3-201643.6" - wire width 64 $0\src_r1$next[63:0]$14093 - attribute \src "libresoc.v:201249.3-201250.29" + attribute \src "libresoc.v:201231.3-201240.6" + wire width 64 $0\src_r1$next[63:0]$14021 + attribute \src "libresoc.v:200846.3-200847.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:201644.3-201653.6" - wire width 64 $0\src_r2$next[63:0]$14096 - attribute \src "libresoc.v:201247.3-201248.29" + attribute \src "libresoc.v:201241.3-201250.6" + wire width 64 $0\src_r2$next[63:0]$14024 + attribute \src "libresoc.v:200844.3-200845.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:201654.3-201663.6" - wire width 64 $0\src_r3$next[63:0]$14099 - attribute \src "libresoc.v:201245.3-201246.29" + attribute \src "libresoc.v:201251.3-201260.6" + wire width 64 $0\src_r3$next[63:0]$14027 + attribute \src "libresoc.v:200842.3-200843.29" wire width 64 $0\src_r3[63:0] - attribute \src "libresoc.v:200706.7-200706.24" + attribute \src "libresoc.v:200303.7-200303.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:200716.7-200716.26" + attribute \src "libresoc.v:200313.7-200313.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:201673.3-201681.6" - wire $1\alu_l_r_alu$next[0:0]$14106 - attribute \src "libresoc.v:200724.7-200724.25" + attribute \src "libresoc.v:201270.3-201278.6" + wire $1\alu_l_r_alu$next[0:0]$14034 + attribute \src "libresoc.v:200321.7-200321.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14040 - attribute \src "libresoc.v:200760.14-200760.59" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$13968 + attribute \src "libresoc.v:200357.14-200357.59" wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14041 - attribute \src "libresoc.v:200779.14-200779.51" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$13969 + attribute \src "libresoc.v:200376.14-200376.51" wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14042 - attribute \src "libresoc.v:200783.14-200783.45" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$13970 + attribute \src "libresoc.v:200380.14-200380.45" wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14043 - attribute \src "libresoc.v:200862.13-200862.49" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$13971 + attribute \src "libresoc.v:200459.13-200459.49" wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14044 - attribute \src "libresoc.v:200866.7-200866.41" + attribute \src "libresoc.v:201093.3-201110.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$13972 + attribute \src "libresoc.v:200463.7-200463.41" wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14045 - attribute \src "libresoc.v:200870.13-200870.48" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$13973 + attribute \src "libresoc.v:200467.13-200467.48" wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14046 - attribute \src "libresoc.v:200874.14-200874.59" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$13974 + attribute \src "libresoc.v:200471.14-200471.59" wire width 64 $1\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14047 - attribute \src "libresoc.v:200878.14-200878.52" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13975 + attribute \src "libresoc.v:200475.14-200475.52" wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:201496.3-201513.6" - wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14048 - attribute \src "libresoc.v:200882.13-200882.48" + attribute \src "libresoc.v:201093.3-201110.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$13976 + attribute \src "libresoc.v:200479.13-200479.48" wire width 8 $1\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:201664.3-201672.6" - wire $1\alui_l_r_alui$next[0:0]$14103 - attribute \src "libresoc.v:200888.7-200888.27" + attribute \src "libresoc.v:201261.3-201269.6" + wire $1\alui_l_r_alui$next[0:0]$14031 + attribute \src "libresoc.v:200485.7-200485.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:201514.3-201535.6" - wire width 64 $1\data_r0__o$next[63:0]$14052 - attribute \src "libresoc.v:200920.14-200920.47" + attribute \src "libresoc.v:201111.3-201132.6" + wire width 64 $1\data_r0__o$next[63:0]$13980 + attribute \src "libresoc.v:200517.14-200517.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:201514.3-201535.6" - wire $1\data_r0__o_ok$next[0:0]$14053 - attribute \src "libresoc.v:200924.7-200924.27" + attribute \src "libresoc.v:201111.3-201132.6" + wire $1\data_r0__o_ok$next[0:0]$13981 + attribute \src "libresoc.v:200521.7-200521.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:201536.3-201557.6" - wire width 64 $1\data_r1__fast1$next[63:0]$14060 - attribute \src "libresoc.v:200928.14-200928.51" + attribute \src "libresoc.v:201133.3-201154.6" + wire width 64 $1\data_r1__fast1$next[63:0]$13988 + attribute \src "libresoc.v:200525.14-200525.51" wire width 64 $1\data_r1__fast1[63:0] - attribute \src "libresoc.v:201536.3-201557.6" - wire $1\data_r1__fast1_ok$next[0:0]$14061 - attribute \src "libresoc.v:200932.7-200932.31" + attribute \src "libresoc.v:201133.3-201154.6" + wire $1\data_r1__fast1_ok$next[0:0]$13989 + attribute \src "libresoc.v:200529.7-200529.31" wire $1\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:201558.3-201579.6" - wire width 64 $1\data_r2__fast2$next[63:0]$14068 - attribute \src "libresoc.v:200936.14-200936.51" + attribute \src "libresoc.v:201155.3-201176.6" + wire width 64 $1\data_r2__fast2$next[63:0]$13996 + attribute \src "libresoc.v:200533.14-200533.51" wire width 64 $1\data_r2__fast2[63:0] - attribute \src "libresoc.v:201558.3-201579.6" - wire $1\data_r2__fast2_ok$next[0:0]$14069 - attribute \src "libresoc.v:200940.7-200940.31" + attribute \src "libresoc.v:201155.3-201176.6" + wire $1\data_r2__fast2_ok$next[0:0]$13997 + attribute \src "libresoc.v:200537.7-200537.31" wire $1\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:201580.3-201601.6" - wire width 64 $1\data_r3__nia$next[63:0]$14076 - attribute \src "libresoc.v:200944.14-200944.49" + attribute \src "libresoc.v:201177.3-201198.6" + wire width 64 $1\data_r3__nia$next[63:0]$14004 + attribute \src "libresoc.v:200541.14-200541.49" wire width 64 $1\data_r3__nia[63:0] - attribute \src "libresoc.v:201580.3-201601.6" - wire $1\data_r3__nia_ok$next[0:0]$14077 - attribute \src "libresoc.v:200948.7-200948.29" + attribute \src "libresoc.v:201177.3-201198.6" + wire $1\data_r3__nia_ok$next[0:0]$14005 + attribute \src "libresoc.v:200545.7-200545.29" wire $1\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:201602.3-201623.6" - wire width 64 $1\data_r4__msr$next[63:0]$14084 - attribute \src "libresoc.v:200952.14-200952.49" + attribute \src "libresoc.v:201199.3-201220.6" + wire width 64 $1\data_r4__msr$next[63:0]$14012 + attribute \src "libresoc.v:200549.14-200549.49" wire width 64 $1\data_r4__msr[63:0] - attribute \src "libresoc.v:201602.3-201623.6" - wire $1\data_r4__msr_ok$next[0:0]$14085 - attribute \src "libresoc.v:200956.7-200956.29" + attribute \src "libresoc.v:201199.3-201220.6" + wire $1\data_r4__msr_ok$next[0:0]$14013 + attribute \src "libresoc.v:200553.7-200553.29" wire $1\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:201682.3-201691.6" + attribute \src "libresoc.v:201279.3-201288.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:201692.3-201701.6" + attribute \src "libresoc.v:201289.3-201298.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:201702.3-201711.6" + attribute \src "libresoc.v:201299.3-201308.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:201712.3-201721.6" + attribute \src "libresoc.v:201309.3-201318.6" wire width 64 $1\dest4_o[63:0] - attribute \src "libresoc.v:201722.3-201731.6" + attribute \src "libresoc.v:201319.3-201328.6" wire width 64 $1\dest5_o[63:0] - attribute \src "libresoc.v:201451.3-201459.6" - wire $1\opc_l_r_opc$next[0:0]$14017 - attribute \src "libresoc.v:200987.7-200987.25" + attribute \src "libresoc.v:201048.3-201056.6" + wire $1\opc_l_r_opc$next[0:0]$13945 + attribute \src "libresoc.v:200584.7-200584.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:201442.3-201450.6" - wire $1\opc_l_s_opc$next[0:0]$14014 - attribute \src "libresoc.v:200991.7-200991.25" + attribute \src "libresoc.v:201039.3-201047.6" + wire $1\opc_l_s_opc$next[0:0]$13942 + attribute \src "libresoc.v:200588.7-200588.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:201732.3-201740.6" - wire width 5 $1\prev_wr_go$next[4:0]$14114 - attribute \src "libresoc.v:201103.13-201103.31" + attribute \src "libresoc.v:201329.3-201337.6" + wire width 5 $1\prev_wr_go$next[4:0]$14042 + attribute \src "libresoc.v:200700.13-200700.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:201396.3-201405.6" + attribute \src "libresoc.v:200993.3-201002.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:201487.3-201495.6" - wire width 5 $1\req_l_r_req$next[4:0]$14029 - attribute \src "libresoc.v:201111.13-201111.32" + attribute \src "libresoc.v:201084.3-201092.6" + wire width 5 $1\req_l_r_req$next[4:0]$13957 + attribute \src "libresoc.v:200708.13-200708.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:201478.3-201486.6" - wire width 5 $1\req_l_s_req$next[4:0]$14026 - attribute \src "libresoc.v:201115.13-201115.32" + attribute \src "libresoc.v:201075.3-201083.6" + wire width 5 $1\req_l_s_req$next[4:0]$13954 + attribute \src "libresoc.v:200712.13-200712.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:201415.3-201423.6" - wire $1\rok_l_r_rdok$next[0:0]$14005 - attribute \src "libresoc.v:201127.7-201127.26" + attribute \src "libresoc.v:201012.3-201020.6" + wire $1\rok_l_r_rdok$next[0:0]$13933 + attribute \src "libresoc.v:200724.7-200724.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:201406.3-201414.6" - wire $1\rok_l_s_rdok$next[0:0]$14002 - attribute \src "libresoc.v:201131.7-201131.26" + attribute \src "libresoc.v:201003.3-201011.6" + wire $1\rok_l_s_rdok$next[0:0]$13930 + attribute \src "libresoc.v:200728.7-200728.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:201433.3-201441.6" - wire $1\rst_l_r_rst$next[0:0]$14011 - attribute \src "libresoc.v:201135.7-201135.25" + attribute \src "libresoc.v:201030.3-201038.6" + wire $1\rst_l_r_rst$next[0:0]$13939 + attribute \src "libresoc.v:200732.7-200732.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:201424.3-201432.6" - wire $1\rst_l_s_rst$next[0:0]$14008 - attribute \src "libresoc.v:201139.7-201139.25" + attribute \src "libresoc.v:201021.3-201029.6" + wire $1\rst_l_s_rst$next[0:0]$13936 + attribute \src "libresoc.v:200736.7-200736.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:201469.3-201477.6" - wire width 4 $1\src_l_r_src$next[3:0]$14023 - attribute \src "libresoc.v:201155.13-201155.31" + attribute \src "libresoc.v:201066.3-201074.6" + wire width 4 $1\src_l_r_src$next[3:0]$13951 + attribute \src "libresoc.v:200752.13-200752.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:201460.3-201468.6" - wire width 4 $1\src_l_s_src$next[3:0]$14020 - attribute \src "libresoc.v:201159.13-201159.31" + attribute \src "libresoc.v:201057.3-201065.6" + wire width 4 $1\src_l_s_src$next[3:0]$13948 + attribute \src "libresoc.v:200756.13-200756.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:201624.3-201633.6" - wire width 64 $1\src_r0$next[63:0]$14091 - attribute \src "libresoc.v:201163.14-201163.43" + attribute \src "libresoc.v:201221.3-201230.6" + wire width 64 $1\src_r0$next[63:0]$14019 + attribute \src "libresoc.v:200760.14-200760.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:201634.3-201643.6" - wire width 64 $1\src_r1$next[63:0]$14094 - attribute \src "libresoc.v:201167.14-201167.43" + attribute \src "libresoc.v:201231.3-201240.6" + wire width 64 $1\src_r1$next[63:0]$14022 + attribute \src "libresoc.v:200764.14-200764.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:201644.3-201653.6" - wire width 64 $1\src_r2$next[63:0]$14097 - attribute \src "libresoc.v:201171.14-201171.43" + attribute \src "libresoc.v:201241.3-201250.6" + wire width 64 $1\src_r2$next[63:0]$14025 + attribute \src "libresoc.v:200768.14-200768.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:201654.3-201663.6" - wire width 64 $1\src_r3$next[63:0]$14100 - attribute \src "libresoc.v:201175.14-201175.43" + attribute \src "libresoc.v:201251.3-201260.6" + wire width 64 $1\src_r3$next[63:0]$14028 + attribute \src "libresoc.v:200772.14-200772.43" wire width 64 $1\src_r3[63:0] - attribute \src "libresoc.v:201514.3-201535.6" - wire width 64 $2\data_r0__o$next[63:0]$14054 - attribute \src "libresoc.v:201514.3-201535.6" - wire $2\data_r0__o_ok$next[0:0]$14055 - attribute \src "libresoc.v:201536.3-201557.6" - wire width 64 $2\data_r1__fast1$next[63:0]$14062 - attribute \src "libresoc.v:201536.3-201557.6" - wire $2\data_r1__fast1_ok$next[0:0]$14063 - attribute \src "libresoc.v:201558.3-201579.6" - wire width 64 $2\data_r2__fast2$next[63:0]$14070 - attribute \src "libresoc.v:201558.3-201579.6" - wire $2\data_r2__fast2_ok$next[0:0]$14071 - attribute \src "libresoc.v:201580.3-201601.6" - wire width 64 $2\data_r3__nia$next[63:0]$14078 - attribute \src "libresoc.v:201580.3-201601.6" - wire $2\data_r3__nia_ok$next[0:0]$14079 - attribute \src "libresoc.v:201602.3-201623.6" - wire width 64 $2\data_r4__msr$next[63:0]$14086 - attribute \src "libresoc.v:201602.3-201623.6" - wire $2\data_r4__msr_ok$next[0:0]$14087 - attribute \src "libresoc.v:201514.3-201535.6" - wire $3\data_r0__o_ok$next[0:0]$14056 - attribute \src "libresoc.v:201536.3-201557.6" - wire $3\data_r1__fast1_ok$next[0:0]$14064 - attribute \src "libresoc.v:201558.3-201579.6" - wire $3\data_r2__fast2_ok$next[0:0]$14072 - attribute \src "libresoc.v:201580.3-201601.6" - wire $3\data_r3__nia_ok$next[0:0]$14080 - attribute \src "libresoc.v:201602.3-201623.6" - wire $3\data_r4__msr_ok$next[0:0]$14088 - attribute \src "libresoc.v:201181.18-201181.112" - wire width 4 $and$libresoc.v:201181$13901_Y - attribute \src "libresoc.v:201182.19-201182.125" - wire $and$libresoc.v:201182$13902_Y - attribute \src "libresoc.v:201183.19-201183.125" - wire $and$libresoc.v:201183$13903_Y - attribute \src "libresoc.v:201184.19-201184.125" - wire $and$libresoc.v:201184$13904_Y - attribute \src "libresoc.v:201185.19-201185.125" - wire $and$libresoc.v:201185$13905_Y - attribute \src "libresoc.v:201186.19-201186.125" - wire $and$libresoc.v:201186$13906_Y - attribute \src "libresoc.v:201187.19-201187.157" - wire width 5 $and$libresoc.v:201187$13907_Y - attribute \src "libresoc.v:201188.19-201188.121" - wire width 5 $and$libresoc.v:201188$13908_Y - attribute \src "libresoc.v:201189.19-201189.127" - wire $and$libresoc.v:201189$13909_Y - attribute \src "libresoc.v:201190.19-201190.127" - wire $and$libresoc.v:201190$13910_Y - attribute \src "libresoc.v:201191.18-201191.110" - wire $and$libresoc.v:201191$13911_Y - attribute \src "libresoc.v:201192.19-201192.127" - wire $and$libresoc.v:201192$13912_Y - attribute \src "libresoc.v:201193.19-201193.127" - wire $and$libresoc.v:201193$13913_Y - attribute \src "libresoc.v:201194.19-201194.127" - wire $and$libresoc.v:201194$13914_Y - attribute \src "libresoc.v:201196.18-201196.98" - wire $and$libresoc.v:201196$13916_Y - attribute \src "libresoc.v:201198.18-201198.100" - wire $and$libresoc.v:201198$13918_Y - attribute \src "libresoc.v:201199.18-201199.171" - wire width 5 $and$libresoc.v:201199$13919_Y - attribute \src "libresoc.v:201201.18-201201.119" - wire width 5 $and$libresoc.v:201201$13921_Y - attribute \src "libresoc.v:201204.18-201204.116" - wire $and$libresoc.v:201204$13924_Y - attribute \src "libresoc.v:201208.17-201208.123" - wire $and$libresoc.v:201208$13928_Y - attribute \src "libresoc.v:201210.18-201210.113" - wire $and$libresoc.v:201210$13930_Y - attribute \src "libresoc.v:201211.18-201211.125" - wire width 5 $and$libresoc.v:201211$13931_Y - attribute \src "libresoc.v:201213.18-201213.112" - wire $and$libresoc.v:201213$13933_Y - attribute \src "libresoc.v:201215.18-201215.127" - wire $and$libresoc.v:201215$13935_Y - attribute \src "libresoc.v:201216.18-201216.127" - wire $and$libresoc.v:201216$13936_Y - attribute \src "libresoc.v:201217.18-201217.117" - wire $and$libresoc.v:201217$13937_Y - attribute \src "libresoc.v:201222.18-201222.131" - wire $and$libresoc.v:201222$13942_Y - attribute \src "libresoc.v:201223.18-201223.124" - wire width 5 $and$libresoc.v:201223$13943_Y - attribute \src "libresoc.v:201226.18-201226.116" - wire $and$libresoc.v:201226$13946_Y - attribute \src "libresoc.v:201227.18-201227.120" - wire $and$libresoc.v:201227$13947_Y - attribute \src "libresoc.v:201228.18-201228.120" - wire $and$libresoc.v:201228$13948_Y - attribute \src "libresoc.v:201229.18-201229.118" - wire $and$libresoc.v:201229$13949_Y - attribute \src "libresoc.v:201230.18-201230.118" - wire $and$libresoc.v:201230$13950_Y - attribute \src "libresoc.v:201236.18-201236.135" - wire $and$libresoc.v:201236$13956_Y - attribute \src "libresoc.v:201237.18-201237.133" - wire $and$libresoc.v:201237$13957_Y - attribute \src "libresoc.v:201238.18-201238.160" - wire width 4 $and$libresoc.v:201238$13958_Y - attribute \src "libresoc.v:201239.18-201239.112" - wire width 4 $and$libresoc.v:201239$13959_Y - attribute \src "libresoc.v:201212.18-201212.113" - wire $eq$libresoc.v:201212$13932_Y - attribute \src "libresoc.v:201214.18-201214.119" - wire $eq$libresoc.v:201214$13934_Y - attribute \src "libresoc.v:201195.18-201195.97" - wire $not$libresoc.v:201195$13915_Y - attribute \src "libresoc.v:201197.18-201197.99" - wire $not$libresoc.v:201197$13917_Y - attribute \src "libresoc.v:201200.18-201200.113" - wire width 5 $not$libresoc.v:201200$13920_Y - attribute \src "libresoc.v:201203.18-201203.106" - wire $not$libresoc.v:201203$13923_Y - attribute \src "libresoc.v:201209.18-201209.121" - wire $not$libresoc.v:201209$13929_Y - attribute \src "libresoc.v:201224.17-201224.113" - wire width 4 $not$libresoc.v:201224$13944_Y - attribute \src "libresoc.v:201240.18-201240.114" - wire width 4 $not$libresoc.v:201240$13960_Y - attribute \src "libresoc.v:201207.18-201207.112" - wire $or$libresoc.v:201207$13927_Y - attribute \src "libresoc.v:201218.18-201218.122" - wire $or$libresoc.v:201218$13938_Y - attribute \src "libresoc.v:201219.18-201219.124" - wire $or$libresoc.v:201219$13939_Y - attribute \src "libresoc.v:201220.18-201220.181" - wire width 5 $or$libresoc.v:201220$13940_Y - attribute \src "libresoc.v:201221.18-201221.168" - wire width 4 $or$libresoc.v:201221$13941_Y - attribute \src "libresoc.v:201225.18-201225.120" - wire width 5 $or$libresoc.v:201225$13945_Y - attribute \src "libresoc.v:201235.17-201235.117" - wire width 4 $or$libresoc.v:201235$13955_Y - attribute \src "libresoc.v:201180.17-201180.104" - wire $reduce_and$libresoc.v:201180$13900_Y - attribute \src "libresoc.v:201202.18-201202.106" - wire $reduce_or$libresoc.v:201202$13922_Y - attribute \src "libresoc.v:201205.18-201205.113" - wire $reduce_or$libresoc.v:201205$13925_Y - attribute \src "libresoc.v:201206.18-201206.112" - wire $reduce_or$libresoc.v:201206$13926_Y - attribute \src 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"libresoc.v:201177.3-201198.6" + wire width 64 $2\data_r3__nia$next[63:0]$14006 + attribute \src "libresoc.v:201177.3-201198.6" + wire $2\data_r3__nia_ok$next[0:0]$14007 + attribute \src "libresoc.v:201199.3-201220.6" + wire width 64 $2\data_r4__msr$next[63:0]$14014 + attribute \src "libresoc.v:201199.3-201220.6" + wire $2\data_r4__msr_ok$next[0:0]$14015 + attribute \src "libresoc.v:201111.3-201132.6" + wire $3\data_r0__o_ok$next[0:0]$13984 + attribute \src "libresoc.v:201133.3-201154.6" + wire $3\data_r1__fast1_ok$next[0:0]$13992 + attribute \src "libresoc.v:201155.3-201176.6" + wire $3\data_r2__fast2_ok$next[0:0]$14000 + attribute \src "libresoc.v:201177.3-201198.6" + wire $3\data_r3__nia_ok$next[0:0]$14008 + attribute \src "libresoc.v:201199.3-201220.6" + wire $3\data_r4__msr_ok$next[0:0]$14016 + attribute \src "libresoc.v:200778.18-200778.112" + wire width 4 $and$libresoc.v:200778$13829_Y + attribute \src "libresoc.v:200779.19-200779.125" + wire $and$libresoc.v:200779$13830_Y + attribute \src "libresoc.v:200780.19-200780.125" + wire $and$libresoc.v:200780$13831_Y + attribute \src "libresoc.v:200781.19-200781.125" + wire $and$libresoc.v:200781$13832_Y + attribute \src "libresoc.v:200782.19-200782.125" + wire $and$libresoc.v:200782$13833_Y + attribute \src "libresoc.v:200783.19-200783.125" + wire $and$libresoc.v:200783$13834_Y + attribute \src "libresoc.v:200784.19-200784.157" + wire width 5 $and$libresoc.v:200784$13835_Y + attribute \src "libresoc.v:200785.19-200785.121" + wire width 5 $and$libresoc.v:200785$13836_Y + attribute \src "libresoc.v:200786.19-200786.127" + wire $and$libresoc.v:200786$13837_Y + attribute \src "libresoc.v:200787.19-200787.127" + wire $and$libresoc.v:200787$13838_Y + attribute \src "libresoc.v:200788.18-200788.110" + wire $and$libresoc.v:200788$13839_Y + attribute \src "libresoc.v:200789.19-200789.127" + wire $and$libresoc.v:200789$13840_Y + attribute \src "libresoc.v:200790.19-200790.127" + wire $and$libresoc.v:200790$13841_Y + attribute \src "libresoc.v:200791.19-200791.127" + wire $and$libresoc.v:200791$13842_Y + attribute \src "libresoc.v:200793.18-200793.98" + wire $and$libresoc.v:200793$13844_Y + attribute \src "libresoc.v:200795.18-200795.100" + wire $and$libresoc.v:200795$13846_Y + attribute \src "libresoc.v:200796.18-200796.171" + wire width 5 $and$libresoc.v:200796$13847_Y + attribute \src "libresoc.v:200798.18-200798.119" + wire width 5 $and$libresoc.v:200798$13849_Y + attribute \src "libresoc.v:200801.18-200801.116" + wire $and$libresoc.v:200801$13852_Y + attribute \src "libresoc.v:200805.17-200805.123" + wire $and$libresoc.v:200805$13856_Y + attribute \src "libresoc.v:200807.18-200807.113" + wire $and$libresoc.v:200807$13858_Y + attribute \src "libresoc.v:200808.18-200808.125" + wire width 5 $and$libresoc.v:200808$13859_Y + attribute \src "libresoc.v:200810.18-200810.112" + wire $and$libresoc.v:200810$13861_Y + attribute \src "libresoc.v:200812.18-200812.127" + wire $and$libresoc.v:200812$13863_Y + attribute \src "libresoc.v:200813.18-200813.127" + wire $and$libresoc.v:200813$13864_Y + attribute \src "libresoc.v:200814.18-200814.117" + wire $and$libresoc.v:200814$13865_Y + attribute \src "libresoc.v:200819.18-200819.131" + wire $and$libresoc.v:200819$13870_Y + attribute \src "libresoc.v:200820.18-200820.124" + wire width 5 $and$libresoc.v:200820$13871_Y + attribute \src "libresoc.v:200823.18-200823.116" + wire $and$libresoc.v:200823$13874_Y + attribute \src "libresoc.v:200824.18-200824.120" + wire $and$libresoc.v:200824$13875_Y + attribute \src "libresoc.v:200825.18-200825.120" + wire $and$libresoc.v:200825$13876_Y + attribute \src "libresoc.v:200826.18-200826.118" + wire $and$libresoc.v:200826$13877_Y + attribute \src "libresoc.v:200827.18-200827.118" + wire $and$libresoc.v:200827$13878_Y + attribute \src "libresoc.v:200833.18-200833.135" + wire $and$libresoc.v:200833$13884_Y + attribute \src "libresoc.v:200834.18-200834.133" + wire $and$libresoc.v:200834$13885_Y + attribute \src "libresoc.v:200835.18-200835.160" + wire width 4 $and$libresoc.v:200835$13886_Y + attribute \src "libresoc.v:200836.18-200836.112" + wire width 4 $and$libresoc.v:200836$13887_Y + attribute \src "libresoc.v:200809.18-200809.113" + wire $eq$libresoc.v:200809$13860_Y + attribute \src "libresoc.v:200811.18-200811.119" + wire $eq$libresoc.v:200811$13862_Y + attribute \src "libresoc.v:200792.18-200792.97" + wire $not$libresoc.v:200792$13843_Y + attribute \src "libresoc.v:200794.18-200794.99" + wire $not$libresoc.v:200794$13845_Y + attribute \src "libresoc.v:200797.18-200797.113" + wire width 5 $not$libresoc.v:200797$13848_Y + attribute \src "libresoc.v:200800.18-200800.106" + wire $not$libresoc.v:200800$13851_Y + attribute \src "libresoc.v:200806.18-200806.121" + wire $not$libresoc.v:200806$13857_Y + attribute \src "libresoc.v:200821.17-200821.113" + wire width 4 $not$libresoc.v:200821$13872_Y + attribute \src "libresoc.v:200837.18-200837.114" + wire width 4 $not$libresoc.v:200837$13888_Y + attribute \src "libresoc.v:200804.18-200804.112" + wire $or$libresoc.v:200804$13855_Y + attribute \src "libresoc.v:200815.18-200815.122" + wire $or$libresoc.v:200815$13866_Y + attribute \src "libresoc.v:200816.18-200816.124" + wire $or$libresoc.v:200816$13867_Y + attribute \src "libresoc.v:200817.18-200817.181" + wire width 5 $or$libresoc.v:200817$13868_Y + attribute \src "libresoc.v:200818.18-200818.168" + wire width 4 $or$libresoc.v:200818$13869_Y + attribute \src "libresoc.v:200822.18-200822.120" + wire width 5 $or$libresoc.v:200822$13873_Y + attribute \src "libresoc.v:200832.17-200832.117" + wire width 4 $or$libresoc.v:200832$13883_Y + attribute \src "libresoc.v:200777.17-200777.104" + wire $reduce_and$libresoc.v:200777$13828_Y + attribute \src "libresoc.v:200799.18-200799.106" + wire $reduce_or$libresoc.v:200799$13850_Y + attribute \src "libresoc.v:200802.18-200802.113" + wire $reduce_or$libresoc.v:200802$13853_Y + attribute \src "libresoc.v:200803.18-200803.112" + wire $reduce_or$libresoc.v:200803$13854_Y + attribute \src "libresoc.v:200828.18-200828.118" + wire width 64 $ternary$libresoc.v:200828$13879_Y + attribute \src "libresoc.v:200829.18-200829.118" + wire width 64 $ternary$libresoc.v:200829$13880_Y + attribute \src "libresoc.v:200830.18-200830.118" + wire width 64 $ternary$libresoc.v:200830$13881_Y + attribute \src "libresoc.v:200831.18-200831.118" + wire width 64 $ternary$libresoc.v:200831$13882_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -381769,9 +380908,9 @@ module \trap0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 12 \cu_busy_o @@ -381849,7 +380988,7 @@ module \trap0 wire output 24 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \fast2_ok - attribute \src "libresoc.v:200580.7-200580.15" + attribute \src "libresoc.v:200177.7-200177.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \msr_ok @@ -382054,7 +381193,7 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:201181$13901 + cell $and $and$libresoc.v:200778$13829 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -382062,10 +381201,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:201181$13901_Y + connect \Y $and$libresoc.v:200778$13829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:201182$13902 + cell $and $and$libresoc.v:200779$13830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382073,10 +381212,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:201182$13902_Y + connect \Y $and$libresoc.v:200779$13830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:201183$13903 + cell $and $and$libresoc.v:200780$13831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382084,10 +381223,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:201183$13903_Y + connect \Y $and$libresoc.v:200780$13831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:201184$13904 + cell $and $and$libresoc.v:200781$13832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382095,10 +381234,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:201184$13904_Y + connect \Y $and$libresoc.v:200781$13832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:201185$13905 + cell $and $and$libresoc.v:200782$13833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382106,10 +381245,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:201185$13905_Y + connect \Y $and$libresoc.v:200782$13833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:201186$13906 + cell $and $and$libresoc.v:200783$13834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382117,10 +381256,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:201186$13906_Y + connect \Y $and$libresoc.v:200783$13834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:201187$13907 + cell $and $and$libresoc.v:200784$13835 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382128,10 +381267,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$libresoc.v:201187$13907_Y + connect \Y $and$libresoc.v:200784$13835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:201188$13908 + cell $and $and$libresoc.v:200785$13836 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382139,10 +381278,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \$111 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:201188$13908_Y + connect \Y $and$libresoc.v:200785$13836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:201189$13909 + cell $and $and$libresoc.v:200786$13837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382150,10 +381289,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:201189$13909_Y + connect \Y $and$libresoc.v:200786$13837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:201190$13910 + cell $and $and$libresoc.v:200787$13838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382161,10 +381300,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:201190$13910_Y + connect \Y $and$libresoc.v:200787$13838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:201191$13911 + cell $and $and$libresoc.v:200788$13839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382172,10 +381311,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:201191$13911_Y + connect \Y $and$libresoc.v:200788$13839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:201192$13912 + cell $and $and$libresoc.v:200789$13840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382183,10 +381322,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:201192$13912_Y + connect \Y $and$libresoc.v:200789$13840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:201193$13913 + cell $and $and$libresoc.v:200790$13841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382194,10 +381333,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:201193$13913_Y + connect \Y $and$libresoc.v:200790$13841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:201194$13914 + cell $and $and$libresoc.v:200791$13842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382205,10 +381344,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:201194$13914_Y + connect \Y $and$libresoc.v:200791$13842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:201196$13916 + cell $and $and$libresoc.v:200793$13844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382216,10 +381355,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:201196$13916_Y + connect \Y $and$libresoc.v:200793$13844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:201198$13918 + cell $and $and$libresoc.v:200795$13846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382227,10 +381366,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:201198$13918_Y + connect \Y $and$libresoc.v:200795$13846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:201199$13919 + cell $and $and$libresoc.v:200796$13847 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382238,10 +381377,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:201199$13919_Y + connect \Y $and$libresoc.v:200796$13847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:201201$13921 + cell $and $and$libresoc.v:200798$13849 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382249,10 +381388,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:201201$13921_Y + connect \Y $and$libresoc.v:200798$13849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:201204$13924 + cell $and $and$libresoc.v:200801$13852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382260,10 +381399,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:201204$13924_Y + connect \Y $and$libresoc.v:200801$13852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:201208$13928 + cell $and $and$libresoc.v:200805$13856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382271,10 +381410,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:201208$13928_Y + connect \Y $and$libresoc.v:200805$13856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:201210$13930 + cell $and $and$libresoc.v:200807$13858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382282,10 +381421,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:201210$13930_Y + connect \Y $and$libresoc.v:200807$13858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:201211$13931 + cell $and $and$libresoc.v:200808$13859 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382293,10 +381432,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:201211$13931_Y + connect \Y $and$libresoc.v:200808$13859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:201213$13933 + cell $and $and$libresoc.v:200810$13861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382304,10 +381443,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:201213$13933_Y + connect \Y $and$libresoc.v:200810$13861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:201215$13935 + cell $and $and$libresoc.v:200812$13863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382315,10 +381454,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_trap0_n_ready_i - connect \Y $and$libresoc.v:201215$13935_Y + connect \Y $and$libresoc.v:200812$13863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:201216$13936 + cell $and $and$libresoc.v:200813$13864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382326,10 +381465,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_trap0_n_valid_o - connect \Y $and$libresoc.v:201216$13936_Y + connect \Y $and$libresoc.v:200813$13864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:201217$13937 + cell $and $and$libresoc.v:200814$13865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382337,10 +381476,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:201217$13937_Y + connect \Y $and$libresoc.v:200814$13865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:201222$13942 + cell $and $and$libresoc.v:200819$13870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382348,10 +381487,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:201222$13942_Y + connect \Y $and$libresoc.v:200819$13870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:201223$13943 + cell $and $and$libresoc.v:200820$13871 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382359,10 +381498,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:201223$13943_Y + connect \Y $and$libresoc.v:200820$13871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:201226$13946 + cell $and $and$libresoc.v:200823$13874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382370,10 +381509,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:201226$13946_Y + connect \Y $and$libresoc.v:200823$13874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:201227$13947 + cell $and $and$libresoc.v:200824$13875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382381,10 +381520,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:201227$13947_Y + connect \Y $and$libresoc.v:200824$13875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:201228$13948 + cell $and $and$libresoc.v:200825$13876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382392,10 +381531,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:201228$13948_Y + connect \Y $and$libresoc.v:200825$13876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:201229$13949 + cell $and $and$libresoc.v:200826$13877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382403,10 +381542,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:201229$13949_Y + connect \Y $and$libresoc.v:200826$13877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:201230$13950 + cell $and $and$libresoc.v:200827$13878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382414,10 +381553,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \msr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:201230$13950_Y + connect \Y $and$libresoc.v:200827$13878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:201236$13956 + cell $and $and$libresoc.v:200833$13884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382425,10 +381564,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:201236$13956_Y + connect \Y $and$libresoc.v:200833$13884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:201237$13957 + cell $and $and$libresoc.v:200834$13885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382436,10 +381575,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:201237$13957_Y + connect \Y $and$libresoc.v:200834$13885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:201238$13958 + cell $and $and$libresoc.v:200835$13886 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -382447,10 +381586,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:201238$13958_Y + connect \Y $and$libresoc.v:200835$13886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:201239$13959 + cell $and $and$libresoc.v:200836$13887 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -382458,10 +381597,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$93 connect \B 4'1111 - connect \Y $and$libresoc.v:201239$13959_Y + connect \Y $and$libresoc.v:200836$13887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:201212$13932 + cell $eq $eq$libresoc.v:200809$13860 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382469,10 +381608,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:201212$13932_Y + connect \Y $eq$libresoc.v:200809$13860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:201214$13934 + cell $eq $eq$libresoc.v:200811$13862 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382480,66 +381619,66 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:201214$13934_Y + connect \Y $eq$libresoc.v:200811$13862_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:201195$13915 + cell $not $not$libresoc.v:200792$13843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:201195$13915_Y + connect \Y $not$libresoc.v:200792$13843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:201197$13917 + cell $not $not$libresoc.v:200794$13845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:201197$13917_Y + connect \Y $not$libresoc.v:200794$13845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:201200$13920 + cell $not $not$libresoc.v:200797$13848 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:201200$13920_Y + connect \Y $not$libresoc.v:200797$13848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:201203$13923 + cell $not $not$libresoc.v:200800$13851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:201203$13923_Y + connect \Y $not$libresoc.v:200800$13851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:201209$13929 + cell $not $not$libresoc.v:200806$13857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_ready_i - connect \Y $not$libresoc.v:201209$13929_Y + connect \Y $not$libresoc.v:200806$13857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:201224$13944 + cell $not $not$libresoc.v:200821$13872 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:201224$13944_Y + connect \Y $not$libresoc.v:200821$13872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:201240$13960 + cell $not $not$libresoc.v:200837$13888 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:201240$13960_Y + connect \Y $not$libresoc.v:200837$13888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:201207$13927 + cell $or $or$libresoc.v:200804$13855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382547,10 +381686,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:201207$13927_Y + connect \Y $or$libresoc.v:200804$13855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:201218$13938 + cell $or $or$libresoc.v:200815$13866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382558,10 +381697,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:201218$13938_Y + connect \Y $or$libresoc.v:200815$13866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:201219$13939 + cell $or $or$libresoc.v:200816$13867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382569,10 +381708,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:201219$13939_Y + connect \Y $or$libresoc.v:200816$13867_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:201220$13940 + cell $or $or$libresoc.v:200817$13868 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382580,10 +381719,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:201220$13940_Y + connect \Y $or$libresoc.v:200817$13868_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:201221$13941 + cell $or $or$libresoc.v:200818$13869 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -382591,10 +381730,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:201221$13941_Y + connect \Y $or$libresoc.v:200818$13869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:201225$13945 + cell $or $or$libresoc.v:200822$13873 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382602,10 +381741,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:201225$13945_Y + connect \Y $or$libresoc.v:200822$13873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:201235$13955 + cell $or $or$libresoc.v:200832$13883 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -382613,74 +381752,74 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:201235$13955_Y + connect \Y $or$libresoc.v:200832$13883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:201180$13900 + cell $reduce_and $reduce_and$libresoc.v:200777$13828 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:201180$13900_Y + connect \Y $reduce_and$libresoc.v:200777$13828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:201202$13922 + cell $reduce_or $reduce_or$libresoc.v:200799$13850 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:201202$13922_Y + connect \Y $reduce_or$libresoc.v:200799$13850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:201205$13925 + cell $reduce_or $reduce_or$libresoc.v:200802$13853 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:201205$13925_Y + connect \Y $reduce_or$libresoc.v:200802$13853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:201206$13926 + cell $reduce_or $reduce_or$libresoc.v:200803$13854 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:201206$13926_Y + connect \Y $reduce_or$libresoc.v:200803$13854_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:201231$13951 + cell $mux $ternary$libresoc.v:200828$13879 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:201231$13951_Y + connect \Y $ternary$libresoc.v:200828$13879_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:201232$13952 + cell $mux $ternary$libresoc.v:200829$13880 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:201232$13952_Y + connect \Y $ternary$libresoc.v:200829$13880_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:201233$13953 + cell $mux $ternary$libresoc.v:200830$13881 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:201233$13953_Y + connect \Y $ternary$libresoc.v:200830$13881_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:201234$13954 + cell $mux $ternary$libresoc.v:200831$13882 parameter \WIDTH 64 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:201234$13954_Y + connect \Y $ternary$libresoc.v:200831$13882_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:201317.14-201323.4" + attribute \src "libresoc.v:200914.14-200920.4" cell \alu_l$45 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382689,7 +381828,7 @@ module \trap0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:201324.13-201354.4" + attribute \src "libresoc.v:200921.13-200951.4" cell \alu_trap0 \alu_trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382722,7 +381861,7 @@ module \trap0 connect \trap_op__traptype \alu_trap0_trap_op__traptype end attribute \module_not_derived 1 - attribute \src "libresoc.v:201355.15-201361.4" + attribute \src "libresoc.v:200952.15-200958.4" cell \alui_l$44 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382731,7 +381870,7 @@ module \trap0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:201362.14-201368.4" + attribute \src "libresoc.v:200959.14-200965.4" cell \opc_l$40 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382740,7 +381879,7 @@ module \trap0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:201369.14-201375.4" + attribute \src "libresoc.v:200966.14-200972.4" cell \req_l$41 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382749,7 +381888,7 @@ module \trap0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:201376.14-201382.4" + attribute \src "libresoc.v:200973.14-200979.4" cell \rok_l$43 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382758,7 +381897,7 @@ module \trap0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:201383.14-201388.4" + attribute \src "libresoc.v:200980.14-200985.4" cell \rst_l$42 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382766,7 +381905,7 @@ module \trap0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:201389.14-201395.4" + attribute \src "libresoc.v:200986.14-200992.4" cell \src_l$39 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382774,592 +381913,592 @@ module \trap0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:200580.7-200580.20" - process $proc$libresoc.v:200580$14115 + attribute \src "libresoc.v:200177.7-200177.20" + process $proc$libresoc.v:200177$14043 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:200706.7-200706.24" - process $proc$libresoc.v:200706$14116 + attribute \src "libresoc.v:200303.7-200303.24" + process $proc$libresoc.v:200303$14044 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:200716.7-200716.26" - process $proc$libresoc.v:200716$14117 + attribute \src "libresoc.v:200313.7-200313.26" + process $proc$libresoc.v:200313$14045 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:200724.7-200724.25" - process $proc$libresoc.v:200724$14118 + attribute \src "libresoc.v:200321.7-200321.25" + process $proc$libresoc.v:200321$14046 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:200760.14-200760.59" - process $proc$libresoc.v:200760$14119 + attribute \src "libresoc.v:200357.14-200357.59" + process $proc$libresoc.v:200357$14047 assign { } { } assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:200779.14-200779.51" - process $proc$libresoc.v:200779$14120 + attribute \src "libresoc.v:200376.14-200376.51" + process $proc$libresoc.v:200376$14048 assign { } { } assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:200783.14-200783.45" - process $proc$libresoc.v:200783$14121 + attribute \src "libresoc.v:200380.14-200380.45" + process $proc$libresoc.v:200380$14049 assign { } { } assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:200862.13-200862.49" - process $proc$libresoc.v:200862$14122 + attribute \src "libresoc.v:200459.13-200459.49" + process $proc$libresoc.v:200459$14050 assign { } { } assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:200866.7-200866.41" - process $proc$libresoc.v:200866$14123 + attribute \src "libresoc.v:200463.7-200463.41" + process $proc$libresoc.v:200463$14051 assign { } { } assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:200870.13-200870.48" - process $proc$libresoc.v:200870$14124 + attribute \src "libresoc.v:200467.13-200467.48" + process $proc$libresoc.v:200467$14052 assign { } { } assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:200874.14-200874.59" - process $proc$libresoc.v:200874$14125 + attribute \src "libresoc.v:200471.14-200471.59" + process $proc$libresoc.v:200471$14053 assign { } { } assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:200878.14-200878.52" - process $proc$libresoc.v:200878$14126 + attribute \src "libresoc.v:200475.14-200475.52" + process $proc$libresoc.v:200475$14054 assign { } { } assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:200882.13-200882.48" - process $proc$libresoc.v:200882$14127 + attribute \src "libresoc.v:200479.13-200479.48" + process $proc$libresoc.v:200479$14055 assign { } { } assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:200888.7-200888.27" - process $proc$libresoc.v:200888$14128 + attribute \src "libresoc.v:200485.7-200485.27" + process $proc$libresoc.v:200485$14056 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:200920.14-200920.47" - process $proc$libresoc.v:200920$14129 + attribute \src "libresoc.v:200517.14-200517.47" + process $proc$libresoc.v:200517$14057 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:200924.7-200924.27" - process $proc$libresoc.v:200924$14130 + attribute \src "libresoc.v:200521.7-200521.27" + process $proc$libresoc.v:200521$14058 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:200928.14-200928.51" - process $proc$libresoc.v:200928$14131 + attribute \src "libresoc.v:200525.14-200525.51" + process $proc$libresoc.v:200525$14059 assign { } { } assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast1 $1\data_r1__fast1[63:0] end - attribute \src "libresoc.v:200932.7-200932.31" - process $proc$libresoc.v:200932$14132 + attribute \src "libresoc.v:200529.7-200529.31" + process $proc$libresoc.v:200529$14060 assign { } { } assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:200936.14-200936.51" - process $proc$libresoc.v:200936$14133 + attribute \src "libresoc.v:200533.14-200533.51" + process $proc$libresoc.v:200533$14061 assign { } { } assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast2 $1\data_r2__fast2[63:0] end - attribute \src "libresoc.v:200940.7-200940.31" - process $proc$libresoc.v:200940$14134 + attribute \src "libresoc.v:200537.7-200537.31" + process $proc$libresoc.v:200537$14062 assign { } { } assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:200944.14-200944.49" - process $proc$libresoc.v:200944$14135 + attribute \src "libresoc.v:200541.14-200541.49" + process $proc$libresoc.v:200541$14063 assign { } { } assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r3__nia $1\data_r3__nia[63:0] end - attribute \src "libresoc.v:200948.7-200948.29" - process $proc$libresoc.v:200948$14136 + attribute \src "libresoc.v:200545.7-200545.29" + process $proc$libresoc.v:200545$14064 assign { } { } assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:200952.14-200952.49" - process $proc$libresoc.v:200952$14137 + attribute \src "libresoc.v:200549.14-200549.49" + process $proc$libresoc.v:200549$14065 assign { } { } assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r4__msr $1\data_r4__msr[63:0] end - attribute \src "libresoc.v:200956.7-200956.29" - process $proc$libresoc.v:200956$14138 + attribute \src "libresoc.v:200553.7-200553.29" + process $proc$libresoc.v:200553$14066 assign { } { } assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:200987.7-200987.25" - process $proc$libresoc.v:200987$14139 + attribute \src "libresoc.v:200584.7-200584.25" + process $proc$libresoc.v:200584$14067 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:200991.7-200991.25" - process $proc$libresoc.v:200991$14140 + attribute \src "libresoc.v:200588.7-200588.25" + process $proc$libresoc.v:200588$14068 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:201103.13-201103.31" - process $proc$libresoc.v:201103$14141 + attribute \src "libresoc.v:200700.13-200700.31" + process $proc$libresoc.v:200700$14069 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:201111.13-201111.32" - process $proc$libresoc.v:201111$14142 + attribute \src "libresoc.v:200708.13-200708.32" + process $proc$libresoc.v:200708$14070 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:201115.13-201115.32" - process $proc$libresoc.v:201115$14143 + attribute \src "libresoc.v:200712.13-200712.32" + process $proc$libresoc.v:200712$14071 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:201127.7-201127.26" - process $proc$libresoc.v:201127$14144 + attribute \src "libresoc.v:200724.7-200724.26" + process $proc$libresoc.v:200724$14072 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:201131.7-201131.26" - process $proc$libresoc.v:201131$14145 + attribute \src "libresoc.v:200728.7-200728.26" + process $proc$libresoc.v:200728$14073 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:201135.7-201135.25" - process $proc$libresoc.v:201135$14146 + attribute \src "libresoc.v:200732.7-200732.25" + process $proc$libresoc.v:200732$14074 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:201139.7-201139.25" - process $proc$libresoc.v:201139$14147 + attribute \src "libresoc.v:200736.7-200736.25" + process $proc$libresoc.v:200736$14075 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:201155.13-201155.31" - process $proc$libresoc.v:201155$14148 + attribute \src "libresoc.v:200752.13-200752.31" + process $proc$libresoc.v:200752$14076 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:201159.13-201159.31" - process $proc$libresoc.v:201159$14149 + attribute \src "libresoc.v:200756.13-200756.31" + process $proc$libresoc.v:200756$14077 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:201163.14-201163.43" - process $proc$libresoc.v:201163$14150 + attribute \src "libresoc.v:200760.14-200760.43" + process $proc$libresoc.v:200760$14078 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:201167.14-201167.43" - process $proc$libresoc.v:201167$14151 + attribute \src "libresoc.v:200764.14-200764.43" + process $proc$libresoc.v:200764$14079 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:201171.14-201171.43" - process $proc$libresoc.v:201171$14152 + attribute \src "libresoc.v:200768.14-200768.43" + process $proc$libresoc.v:200768$14080 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:201175.14-201175.43" - process $proc$libresoc.v:201175$14153 + attribute \src "libresoc.v:200772.14-200772.43" + process $proc$libresoc.v:200772$14081 assign { } { } assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r3 $1\src_r3[63:0] end - attribute \src "libresoc.v:201241.3-201242.39" - process $proc$libresoc.v:201241$13961 + attribute \src "libresoc.v:200838.3-200839.39" + process $proc$libresoc.v:200838$13889 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:201243.3-201244.43" - process $proc$libresoc.v:201243$13962 + attribute \src "libresoc.v:200840.3-200841.43" + process $proc$libresoc.v:200840$13890 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:201245.3-201246.29" - process $proc$libresoc.v:201245$13963 + attribute \src "libresoc.v:200842.3-200843.29" + process $proc$libresoc.v:200842$13891 assign { } { } assign $0\src_r3[63:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[63:0] end - attribute \src "libresoc.v:201247.3-201248.29" - process $proc$libresoc.v:201247$13964 + attribute \src "libresoc.v:200844.3-200845.29" + process $proc$libresoc.v:200844$13892 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:201249.3-201250.29" - process $proc$libresoc.v:201249$13965 + attribute \src "libresoc.v:200846.3-200847.29" + process $proc$libresoc.v:200846$13893 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:201251.3-201252.29" - process $proc$libresoc.v:201251$13966 + attribute \src "libresoc.v:200848.3-200849.29" + process $proc$libresoc.v:200848$13894 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:201253.3-201254.41" - process $proc$libresoc.v:201253$13967 + attribute \src "libresoc.v:200850.3-200851.41" + process $proc$libresoc.v:200850$13895 assign { } { } assign $0\data_r4__msr[63:0] \data_r4__msr$next sync posedge \coresync_clk update \data_r4__msr $0\data_r4__msr[63:0] end - attribute \src "libresoc.v:201255.3-201256.47" - process $proc$libresoc.v:201255$13968 + attribute \src "libresoc.v:200852.3-200853.47" + process $proc$libresoc.v:200852$13896 assign { } { } assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next sync posedge \coresync_clk update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:201257.3-201258.41" - process $proc$libresoc.v:201257$13969 + attribute \src "libresoc.v:200854.3-200855.41" + process $proc$libresoc.v:200854$13897 assign { } { } assign $0\data_r3__nia[63:0] \data_r3__nia$next sync posedge \coresync_clk update \data_r3__nia $0\data_r3__nia[63:0] end - attribute \src "libresoc.v:201259.3-201260.47" - process $proc$libresoc.v:201259$13970 + attribute \src "libresoc.v:200856.3-200857.47" + process $proc$libresoc.v:200856$13898 assign { } { } assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next sync posedge \coresync_clk update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:201261.3-201262.45" - process $proc$libresoc.v:201261$13971 + attribute \src "libresoc.v:200858.3-200859.45" + process $proc$libresoc.v:200858$13899 assign { } { } assign $0\data_r2__fast2[63:0] \data_r2__fast2$next sync posedge \coresync_clk update \data_r2__fast2 $0\data_r2__fast2[63:0] end - attribute \src "libresoc.v:201263.3-201264.51" - process $proc$libresoc.v:201263$13972 + attribute \src "libresoc.v:200860.3-200861.51" + process $proc$libresoc.v:200860$13900 assign { } { } assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next sync posedge \coresync_clk update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:201265.3-201266.45" - process $proc$libresoc.v:201265$13973 + attribute \src "libresoc.v:200862.3-200863.45" + process $proc$libresoc.v:200862$13901 assign { } { } assign $0\data_r1__fast1[63:0] \data_r1__fast1$next sync posedge \coresync_clk update \data_r1__fast1 $0\data_r1__fast1[63:0] end - attribute \src "libresoc.v:201267.3-201268.51" - process $proc$libresoc.v:201267$13974 + attribute \src "libresoc.v:200864.3-200865.51" + process $proc$libresoc.v:200864$13902 assign { } { } assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next sync posedge \coresync_clk update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:201269.3-201270.37" - process $proc$libresoc.v:201269$13975 + attribute \src "libresoc.v:200866.3-200867.37" + process $proc$libresoc.v:200866$13903 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:201271.3-201272.43" - process $proc$libresoc.v:201271$13976 + attribute \src "libresoc.v:200868.3-200869.43" + process $proc$libresoc.v:200868$13904 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:201273.3-201274.73" - process $proc$libresoc.v:201273$13977 + attribute \src "libresoc.v:200870.3-200871.73" + process $proc$libresoc.v:200870$13905 assign { } { } assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:201275.3-201276.69" - process $proc$libresoc.v:201275$13978 + attribute \src "libresoc.v:200872.3-200873.69" + process $proc$libresoc.v:200872$13906 assign { } { } assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next sync posedge \coresync_clk update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:201277.3-201278.63" - process $proc$libresoc.v:201277$13979 + attribute \src "libresoc.v:200874.3-200875.63" + process $proc$libresoc.v:200874$13907 assign { } { } assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:201279.3-201280.61" - process $proc$libresoc.v:201279$13980 + attribute \src "libresoc.v:200876.3-200877.61" + process $proc$libresoc.v:200876$13908 assign { } { } assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next sync posedge \coresync_clk update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:201281.3-201282.61" - process $proc$libresoc.v:201281$13981 + attribute \src "libresoc.v:200878.3-200879.61" + process $proc$libresoc.v:200878$13909 assign { } { } assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next sync posedge \coresync_clk update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:201283.3-201284.71" - process $proc$libresoc.v:201283$13982 + attribute \src "libresoc.v:200880.3-200881.71" + process $proc$libresoc.v:200880$13910 assign { } { } assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next sync posedge \coresync_clk update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:201285.3-201286.71" - process $proc$libresoc.v:201285$13983 + attribute \src "libresoc.v:200882.3-200883.71" + process $proc$libresoc.v:200882$13911 assign { } { } assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next sync posedge \coresync_clk update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:201287.3-201288.71" - process $proc$libresoc.v:201287$13984 + attribute \src "libresoc.v:200884.3-200885.71" + process $proc$libresoc.v:200884$13912 assign { } { } assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next sync posedge \coresync_clk update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:201289.3-201290.71" - process $proc$libresoc.v:201289$13985 + attribute \src "libresoc.v:200886.3-200887.71" + process $proc$libresoc.v:200886$13913 assign { } { } assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next sync posedge \coresync_clk update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:201291.3-201292.39" - process $proc$libresoc.v:201291$13986 + attribute \src "libresoc.v:200888.3-200889.39" + process $proc$libresoc.v:200888$13914 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:201293.3-201294.39" - process $proc$libresoc.v:201293$13987 + attribute \src "libresoc.v:200890.3-200891.39" + process $proc$libresoc.v:200890$13915 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:201295.3-201296.39" - process $proc$libresoc.v:201295$13988 + attribute \src "libresoc.v:200892.3-200893.39" + process $proc$libresoc.v:200892$13916 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:201297.3-201298.39" - process $proc$libresoc.v:201297$13989 + attribute \src "libresoc.v:200894.3-200895.39" + process $proc$libresoc.v:200894$13917 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:201299.3-201300.39" - process $proc$libresoc.v:201299$13990 + attribute \src "libresoc.v:200896.3-200897.39" + process $proc$libresoc.v:200896$13918 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:201301.3-201302.39" - process $proc$libresoc.v:201301$13991 + attribute \src "libresoc.v:200898.3-200899.39" + process $proc$libresoc.v:200898$13919 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:201303.3-201304.39" - process $proc$libresoc.v:201303$13992 + attribute \src "libresoc.v:200900.3-200901.39" + process $proc$libresoc.v:200900$13920 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:201305.3-201306.39" - process $proc$libresoc.v:201305$13993 + attribute \src "libresoc.v:200902.3-200903.39" + process $proc$libresoc.v:200902$13921 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:201307.3-201308.41" - process $proc$libresoc.v:201307$13994 + attribute \src "libresoc.v:200904.3-200905.41" + process $proc$libresoc.v:200904$13922 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:201309.3-201310.41" - process $proc$libresoc.v:201309$13995 + attribute \src "libresoc.v:200906.3-200907.41" + process $proc$libresoc.v:200906$13923 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:201311.3-201312.37" - process $proc$libresoc.v:201311$13996 + attribute \src "libresoc.v:200908.3-200909.37" + process $proc$libresoc.v:200908$13924 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:201313.3-201314.41" - process $proc$libresoc.v:201313$13997 + attribute \src "libresoc.v:200910.3-200911.41" + process $proc$libresoc.v:200910$13925 assign { } { } assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:201315.3-201316.25" - process $proc$libresoc.v:201315$13998 + attribute \src "libresoc.v:200912.3-200913.25" + process $proc$libresoc.v:200912$13926 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:201396.3-201405.6" - process $proc$libresoc.v:201396$13999 + attribute \src "libresoc.v:200993.3-201002.6" + process $proc$libresoc.v:200993$13927 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:201397.5-201397.29" + attribute \src "libresoc.v:200994.5-200994.29" switch \initial - attribute \src "libresoc.v:201397.9-201397.17" + attribute \src "libresoc.v:200994.9-200994.17" case 1'1 case end @@ -383375,14 +382514,14 @@ module \trap0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:201406.3-201414.6" - process $proc$libresoc.v:201406$14000 + attribute \src "libresoc.v:201003.3-201011.6" + process $proc$libresoc.v:201003$13928 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$14001 $1\rok_l_s_rdok$next[0:0]$14002 - attribute \src "libresoc.v:201407.5-201407.29" + assign $0\rok_l_s_rdok$next[0:0]$13929 $1\rok_l_s_rdok$next[0:0]$13930 + attribute \src "libresoc.v:201004.5-201004.29" switch \initial - attribute \src "libresoc.v:201407.9-201407.17" + attribute \src "libresoc.v:201004.9-201004.17" case 1'1 case end @@ -383391,21 +382530,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$14002 1'0 + assign $1\rok_l_s_rdok$next[0:0]$13930 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$14002 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$13930 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14001 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13929 end - attribute \src "libresoc.v:201415.3-201423.6" - process $proc$libresoc.v:201415$14003 + attribute \src "libresoc.v:201012.3-201020.6" + process $proc$libresoc.v:201012$13931 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$14004 $1\rok_l_r_rdok$next[0:0]$14005 - attribute \src "libresoc.v:201416.5-201416.29" + assign $0\rok_l_r_rdok$next[0:0]$13932 $1\rok_l_r_rdok$next[0:0]$13933 + attribute \src "libresoc.v:201013.5-201013.29" switch \initial - attribute \src "libresoc.v:201416.9-201416.17" + attribute \src "libresoc.v:201013.9-201013.17" case 1'1 case end @@ -383414,21 +382553,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$14005 1'1 + assign $1\rok_l_r_rdok$next[0:0]$13933 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$14005 \$65 + assign $1\rok_l_r_rdok$next[0:0]$13933 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14004 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13932 end - attribute \src "libresoc.v:201424.3-201432.6" - process $proc$libresoc.v:201424$14006 + attribute \src "libresoc.v:201021.3-201029.6" + process $proc$libresoc.v:201021$13934 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$14007 $1\rst_l_s_rst$next[0:0]$14008 - attribute \src "libresoc.v:201425.5-201425.29" + assign $0\rst_l_s_rst$next[0:0]$13935 $1\rst_l_s_rst$next[0:0]$13936 + attribute \src "libresoc.v:201022.5-201022.29" switch \initial - attribute \src "libresoc.v:201425.9-201425.17" + attribute \src "libresoc.v:201022.9-201022.17" case 1'1 case end @@ -383437,21 +382576,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$14008 1'0 + assign $1\rst_l_s_rst$next[0:0]$13936 1'0 case - assign $1\rst_l_s_rst$next[0:0]$14008 \all_rd + assign $1\rst_l_s_rst$next[0:0]$13936 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14007 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13935 end - attribute \src "libresoc.v:201433.3-201441.6" - process $proc$libresoc.v:201433$14009 + attribute \src "libresoc.v:201030.3-201038.6" + process $proc$libresoc.v:201030$13937 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$14010 $1\rst_l_r_rst$next[0:0]$14011 - attribute \src "libresoc.v:201434.5-201434.29" + assign $0\rst_l_r_rst$next[0:0]$13938 $1\rst_l_r_rst$next[0:0]$13939 + attribute \src "libresoc.v:201031.5-201031.29" switch \initial - attribute \src "libresoc.v:201434.9-201434.17" + attribute \src "libresoc.v:201031.9-201031.17" case 1'1 case end @@ -383460,21 +382599,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$14011 1'1 + assign $1\rst_l_r_rst$next[0:0]$13939 1'1 case - assign $1\rst_l_r_rst$next[0:0]$14011 \rst_r + assign $1\rst_l_r_rst$next[0:0]$13939 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14010 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13938 end - attribute \src "libresoc.v:201442.3-201450.6" - process $proc$libresoc.v:201442$14012 + attribute \src "libresoc.v:201039.3-201047.6" + process $proc$libresoc.v:201039$13940 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$14013 $1\opc_l_s_opc$next[0:0]$14014 - attribute \src "libresoc.v:201443.5-201443.29" + assign $0\opc_l_s_opc$next[0:0]$13941 $1\opc_l_s_opc$next[0:0]$13942 + attribute \src "libresoc.v:201040.5-201040.29" switch \initial - attribute \src "libresoc.v:201443.9-201443.17" + attribute \src "libresoc.v:201040.9-201040.17" case 1'1 case end @@ -383483,21 +382622,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$14014 1'0 + assign $1\opc_l_s_opc$next[0:0]$13942 1'0 case - assign $1\opc_l_s_opc$next[0:0]$14014 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$13942 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14013 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13941 end - attribute \src "libresoc.v:201451.3-201459.6" - process $proc$libresoc.v:201451$14015 + attribute \src "libresoc.v:201048.3-201056.6" + process $proc$libresoc.v:201048$13943 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$14016 $1\opc_l_r_opc$next[0:0]$14017 - attribute \src "libresoc.v:201452.5-201452.29" + assign $0\opc_l_r_opc$next[0:0]$13944 $1\opc_l_r_opc$next[0:0]$13945 + attribute \src "libresoc.v:201049.5-201049.29" switch \initial - attribute \src "libresoc.v:201452.9-201452.17" + attribute \src "libresoc.v:201049.9-201049.17" case 1'1 case end @@ -383506,21 +382645,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$14017 1'1 + assign $1\opc_l_r_opc$next[0:0]$13945 1'1 case - assign $1\opc_l_r_opc$next[0:0]$14017 \req_done + assign $1\opc_l_r_opc$next[0:0]$13945 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14016 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13944 end - attribute \src "libresoc.v:201460.3-201468.6" - process $proc$libresoc.v:201460$14018 + attribute \src "libresoc.v:201057.3-201065.6" + process $proc$libresoc.v:201057$13946 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$14019 $1\src_l_s_src$next[3:0]$14020 - attribute \src "libresoc.v:201461.5-201461.29" + assign $0\src_l_s_src$next[3:0]$13947 $1\src_l_s_src$next[3:0]$13948 + attribute \src "libresoc.v:201058.5-201058.29" switch \initial - attribute \src "libresoc.v:201461.9-201461.17" + attribute \src "libresoc.v:201058.9-201058.17" case 1'1 case end @@ -383529,21 +382668,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[3:0]$14020 4'0000 + assign $1\src_l_s_src$next[3:0]$13948 4'0000 case - assign $1\src_l_s_src$next[3:0]$14020 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[3:0]$13948 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14019 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$13947 end - attribute \src "libresoc.v:201469.3-201477.6" - process $proc$libresoc.v:201469$14021 + attribute \src "libresoc.v:201066.3-201074.6" + process $proc$libresoc.v:201066$13949 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$14022 $1\src_l_r_src$next[3:0]$14023 - attribute \src "libresoc.v:201470.5-201470.29" + assign $0\src_l_r_src$next[3:0]$13950 $1\src_l_r_src$next[3:0]$13951 + attribute \src "libresoc.v:201067.5-201067.29" switch \initial - attribute \src "libresoc.v:201470.9-201470.17" + attribute \src "libresoc.v:201067.9-201067.17" case 1'1 case end @@ -383552,21 +382691,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$14023 4'1111 + assign $1\src_l_r_src$next[3:0]$13951 4'1111 case - assign $1\src_l_r_src$next[3:0]$14023 \reset_r + assign $1\src_l_r_src$next[3:0]$13951 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14022 + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$13950 end - attribute \src "libresoc.v:201478.3-201486.6" - process $proc$libresoc.v:201478$14024 + attribute \src "libresoc.v:201075.3-201083.6" + process $proc$libresoc.v:201075$13952 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$14025 $1\req_l_s_req$next[4:0]$14026 - attribute \src "libresoc.v:201479.5-201479.29" + assign $0\req_l_s_req$next[4:0]$13953 $1\req_l_s_req$next[4:0]$13954 + attribute \src "libresoc.v:201076.5-201076.29" switch \initial - attribute \src "libresoc.v:201479.9-201479.17" + attribute \src "libresoc.v:201076.9-201076.17" case 1'1 case end @@ -383575,21 +382714,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$14026 5'00000 + assign $1\req_l_s_req$next[4:0]$13954 5'00000 case - assign $1\req_l_s_req$next[4:0]$14026 \$67 + assign $1\req_l_s_req$next[4:0]$13954 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14025 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$13953 end - attribute \src "libresoc.v:201487.3-201495.6" - process $proc$libresoc.v:201487$14027 + attribute \src "libresoc.v:201084.3-201092.6" + process $proc$libresoc.v:201084$13955 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$14028 $1\req_l_r_req$next[4:0]$14029 - attribute \src "libresoc.v:201488.5-201488.29" + assign $0\req_l_r_req$next[4:0]$13956 $1\req_l_r_req$next[4:0]$13957 + attribute \src "libresoc.v:201085.5-201085.29" switch \initial - attribute \src "libresoc.v:201488.9-201488.17" + attribute \src "libresoc.v:201085.9-201085.17" case 1'1 case end @@ -383598,15 +382737,15 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$14029 5'11111 + assign $1\req_l_r_req$next[4:0]$13957 5'11111 case - assign $1\req_l_r_req$next[4:0]$14029 \$69 + assign $1\req_l_r_req$next[4:0]$13957 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14028 + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$13956 end - attribute \src "libresoc.v:201496.3-201513.6" - process $proc$libresoc.v:201496$14030 + attribute \src "libresoc.v:201093.3-201110.6" + process $proc$libresoc.v:201093$13958 assign { } { } assign { } { } assign { } { } @@ -383625,18 +382764,18 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$14031 $1\alu_trap0_trap_op__cia$next[63:0]$14040 - assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14032 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14041 - assign $0\alu_trap0_trap_op__insn$next[31:0]$14033 $1\alu_trap0_trap_op__insn$next[31:0]$14042 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14034 $1\alu_trap0_trap_op__insn_type$next[6:0]$14043 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14035 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14044 - assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14036 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14045 - assign $0\alu_trap0_trap_op__msr$next[63:0]$14037 $1\alu_trap0_trap_op__msr$next[63:0]$14046 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14038 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14047 - assign $0\alu_trap0_trap_op__traptype$next[7:0]$14039 $1\alu_trap0_trap_op__traptype$next[7:0]$14048 - attribute \src "libresoc.v:201497.5-201497.29" + assign $0\alu_trap0_trap_op__cia$next[63:0]$13959 $1\alu_trap0_trap_op__cia$next[63:0]$13968 + assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$13960 $1\alu_trap0_trap_op__fn_unit$next[13:0]$13969 + assign $0\alu_trap0_trap_op__insn$next[31:0]$13961 $1\alu_trap0_trap_op__insn$next[31:0]$13970 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$13962 $1\alu_trap0_trap_op__insn_type$next[6:0]$13971 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$13963 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13972 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$13964 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$13973 + assign $0\alu_trap0_trap_op__msr$next[63:0]$13965 $1\alu_trap0_trap_op__msr$next[63:0]$13974 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$13966 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13975 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$13967 $1\alu_trap0_trap_op__traptype$next[7:0]$13976 + attribute \src "libresoc.v:201094.5-201094.29" switch \initial - attribute \src "libresoc.v:201497.9-201497.17" + attribute \src "libresoc.v:201094.9-201094.17" case 1'1 case end @@ -383653,43 +382792,43 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14045 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14047 $1\alu_trap0_trap_op__traptype$next[7:0]$14048 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14044 $1\alu_trap0_trap_op__cia$next[63:0]$14040 $1\alu_trap0_trap_op__msr$next[63:0]$14046 $1\alu_trap0_trap_op__insn$next[31:0]$14042 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14041 $1\alu_trap0_trap_op__insn_type$next[6:0]$14043 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$13973 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13975 $1\alu_trap0_trap_op__traptype$next[7:0]$13976 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13972 $1\alu_trap0_trap_op__cia$next[63:0]$13968 $1\alu_trap0_trap_op__msr$next[63:0]$13974 $1\alu_trap0_trap_op__insn$next[31:0]$13970 $1\alu_trap0_trap_op__fn_unit$next[13:0]$13969 $1\alu_trap0_trap_op__insn_type$next[6:0]$13971 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case - assign $1\alu_trap0_trap_op__cia$next[63:0]$14040 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14041 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$14042 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14043 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14044 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14045 \alu_trap0_trap_op__ldst_exc - assign $1\alu_trap0_trap_op__msr$next[63:0]$14046 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14047 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[7:0]$14048 \alu_trap0_trap_op__traptype + assign $1\alu_trap0_trap_op__cia$next[63:0]$13968 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$13969 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$13970 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$13971 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$13972 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$13973 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$13974 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$13975 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$13976 \alu_trap0_trap_op__traptype end sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14031 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14032 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14033 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14034 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14035 - update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14036 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14037 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14038 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14039 + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$13959 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$13960 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$13961 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$13962 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$13963 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$13964 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$13965 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$13966 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$13967 end - attribute \src "libresoc.v:201514.3-201535.6" - process $proc$libresoc.v:201514$14049 + attribute \src "libresoc.v:201111.3-201132.6" + process $proc$libresoc.v:201111$13977 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$14050 $2\data_r0__o$next[63:0]$14054 + assign $0\data_r0__o$next[63:0]$13978 $2\data_r0__o$next[63:0]$13982 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$14051 $3\data_r0__o_ok$next[0:0]$14056 - attribute \src "libresoc.v:201515.5-201515.29" + assign $0\data_r0__o_ok$next[0:0]$13979 $3\data_r0__o_ok$next[0:0]$13984 + attribute \src "libresoc.v:201112.5-201112.29" switch \initial - attribute \src "libresoc.v:201515.9-201515.17" + attribute \src "libresoc.v:201112.9-201112.17" case 1'1 case end @@ -383699,10 +382838,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$14053 $1\data_r0__o$next[63:0]$14052 } { \o_ok \alu_trap0_o } + assign { $1\data_r0__o_ok$next[0:0]$13981 $1\data_r0__o$next[63:0]$13980 } { \o_ok \alu_trap0_o } case - assign $1\data_r0__o$next[63:0]$14052 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$14053 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$13980 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$13981 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -383710,38 +382849,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$14055 $2\data_r0__o$next[63:0]$14054 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$13983 $2\data_r0__o$next[63:0]$13982 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$14054 $1\data_r0__o$next[63:0]$14052 - assign $2\data_r0__o_ok$next[0:0]$14055 $1\data_r0__o_ok$next[0:0]$14053 + assign $2\data_r0__o$next[63:0]$13982 $1\data_r0__o$next[63:0]$13980 + assign $2\data_r0__o_ok$next[0:0]$13983 $1\data_r0__o_ok$next[0:0]$13981 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$14056 1'0 + assign $3\data_r0__o_ok$next[0:0]$13984 1'0 case - assign $3\data_r0__o_ok$next[0:0]$14056 $2\data_r0__o_ok$next[0:0]$14055 + assign $3\data_r0__o_ok$next[0:0]$13984 $2\data_r0__o_ok$next[0:0]$13983 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$14050 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14051 + update \data_r0__o$next $0\data_r0__o$next[63:0]$13978 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13979 end - attribute \src "libresoc.v:201536.3-201557.6" - process $proc$libresoc.v:201536$14057 + attribute \src "libresoc.v:201133.3-201154.6" + process $proc$libresoc.v:201133$13985 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__fast1$next[63:0]$14058 $2\data_r1__fast1$next[63:0]$14062 + assign $0\data_r1__fast1$next[63:0]$13986 $2\data_r1__fast1$next[63:0]$13990 assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$14059 $3\data_r1__fast1_ok$next[0:0]$14064 - attribute \src "libresoc.v:201537.5-201537.29" + assign $0\data_r1__fast1_ok$next[0:0]$13987 $3\data_r1__fast1_ok$next[0:0]$13992 + attribute \src "libresoc.v:201134.5-201134.29" switch \initial - attribute \src "libresoc.v:201537.9-201537.17" + attribute \src "libresoc.v:201134.9-201134.17" case 1'1 case end @@ -383751,10 +382890,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$14061 $1\data_r1__fast1$next[63:0]$14060 } { \fast1_ok \alu_trap0_fast1 } + assign { $1\data_r1__fast1_ok$next[0:0]$13989 $1\data_r1__fast1$next[63:0]$13988 } { \fast1_ok \alu_trap0_fast1 } case - assign $1\data_r1__fast1$next[63:0]$14060 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$14061 \data_r1__fast1_ok + assign $1\data_r1__fast1$next[63:0]$13988 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$13989 \data_r1__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -383762,38 +382901,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$14063 $2\data_r1__fast1$next[63:0]$14062 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__fast1_ok$next[0:0]$13991 $2\data_r1__fast1$next[63:0]$13990 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast1$next[63:0]$14062 $1\data_r1__fast1$next[63:0]$14060 - assign $2\data_r1__fast1_ok$next[0:0]$14063 $1\data_r1__fast1_ok$next[0:0]$14061 + assign $2\data_r1__fast1$next[63:0]$13990 $1\data_r1__fast1$next[63:0]$13988 + assign $2\data_r1__fast1_ok$next[0:0]$13991 $1\data_r1__fast1_ok$next[0:0]$13989 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$14064 1'0 + assign $3\data_r1__fast1_ok$next[0:0]$13992 1'0 case - assign $3\data_r1__fast1_ok$next[0:0]$14064 $2\data_r1__fast1_ok$next[0:0]$14063 + assign $3\data_r1__fast1_ok$next[0:0]$13992 $2\data_r1__fast1_ok$next[0:0]$13991 end sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14058 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14059 + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$13986 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$13987 end - attribute \src "libresoc.v:201558.3-201579.6" - process $proc$libresoc.v:201558$14065 + attribute \src "libresoc.v:201155.3-201176.6" + process $proc$libresoc.v:201155$13993 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast2$next[63:0]$14066 $2\data_r2__fast2$next[63:0]$14070 + assign $0\data_r2__fast2$next[63:0]$13994 $2\data_r2__fast2$next[63:0]$13998 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$14067 $3\data_r2__fast2_ok$next[0:0]$14072 - attribute \src "libresoc.v:201559.5-201559.29" + assign $0\data_r2__fast2_ok$next[0:0]$13995 $3\data_r2__fast2_ok$next[0:0]$14000 + attribute \src "libresoc.v:201156.5-201156.29" switch \initial - attribute \src "libresoc.v:201559.9-201559.17" + attribute \src "libresoc.v:201156.9-201156.17" case 1'1 case end @@ -383803,10 +382942,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$14069 $1\data_r2__fast2$next[63:0]$14068 } { \fast2_ok \alu_trap0_fast2 } + assign { $1\data_r2__fast2_ok$next[0:0]$13997 $1\data_r2__fast2$next[63:0]$13996 } { \fast2_ok \alu_trap0_fast2 } case - assign $1\data_r2__fast2$next[63:0]$14068 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$14069 \data_r2__fast2_ok + assign $1\data_r2__fast2$next[63:0]$13996 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$13997 \data_r2__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -383814,38 +382953,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$14071 $2\data_r2__fast2$next[63:0]$14070 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast2_ok$next[0:0]$13999 $2\data_r2__fast2$next[63:0]$13998 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast2$next[63:0]$14070 $1\data_r2__fast2$next[63:0]$14068 - assign $2\data_r2__fast2_ok$next[0:0]$14071 $1\data_r2__fast2_ok$next[0:0]$14069 + assign $2\data_r2__fast2$next[63:0]$13998 $1\data_r2__fast2$next[63:0]$13996 + assign $2\data_r2__fast2_ok$next[0:0]$13999 $1\data_r2__fast2_ok$next[0:0]$13997 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$14072 1'0 + assign $3\data_r2__fast2_ok$next[0:0]$14000 1'0 case - assign $3\data_r2__fast2_ok$next[0:0]$14072 $2\data_r2__fast2_ok$next[0:0]$14071 + assign $3\data_r2__fast2_ok$next[0:0]$14000 $2\data_r2__fast2_ok$next[0:0]$13999 end sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14066 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14067 + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$13994 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$13995 end - attribute \src "libresoc.v:201580.3-201601.6" - process $proc$libresoc.v:201580$14073 + attribute \src "libresoc.v:201177.3-201198.6" + process $proc$libresoc.v:201177$14001 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__nia$next[63:0]$14074 $2\data_r3__nia$next[63:0]$14078 + assign $0\data_r3__nia$next[63:0]$14002 $2\data_r3__nia$next[63:0]$14006 assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$14075 $3\data_r3__nia_ok$next[0:0]$14080 - attribute \src "libresoc.v:201581.5-201581.29" + assign $0\data_r3__nia_ok$next[0:0]$14003 $3\data_r3__nia_ok$next[0:0]$14008 + attribute \src "libresoc.v:201178.5-201178.29" switch \initial - attribute \src "libresoc.v:201581.9-201581.17" + attribute \src "libresoc.v:201178.9-201178.17" case 1'1 case end @@ -383855,10 +382994,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$14077 $1\data_r3__nia$next[63:0]$14076 } { \nia_ok \alu_trap0_nia } + assign { $1\data_r3__nia_ok$next[0:0]$14005 $1\data_r3__nia$next[63:0]$14004 } { \nia_ok \alu_trap0_nia } case - assign $1\data_r3__nia$next[63:0]$14076 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$14077 \data_r3__nia_ok + assign $1\data_r3__nia$next[63:0]$14004 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14005 \data_r3__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -383866,38 +383005,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$14079 $2\data_r3__nia$next[63:0]$14078 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r3__nia_ok$next[0:0]$14007 $2\data_r3__nia$next[63:0]$14006 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$14078 $1\data_r3__nia$next[63:0]$14076 - assign $2\data_r3__nia_ok$next[0:0]$14079 $1\data_r3__nia_ok$next[0:0]$14077 + assign $2\data_r3__nia$next[63:0]$14006 $1\data_r3__nia$next[63:0]$14004 + assign $2\data_r3__nia_ok$next[0:0]$14007 $1\data_r3__nia_ok$next[0:0]$14005 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$14080 1'0 + assign $3\data_r3__nia_ok$next[0:0]$14008 1'0 case - assign $3\data_r3__nia_ok$next[0:0]$14080 $2\data_r3__nia_ok$next[0:0]$14079 + assign $3\data_r3__nia_ok$next[0:0]$14008 $2\data_r3__nia_ok$next[0:0]$14007 end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14074 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14075 + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14002 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14003 end - attribute \src "libresoc.v:201602.3-201623.6" - process $proc$libresoc.v:201602$14081 + attribute \src "libresoc.v:201199.3-201220.6" + process $proc$libresoc.v:201199$14009 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__msr$next[63:0]$14082 $2\data_r4__msr$next[63:0]$14086 + assign $0\data_r4__msr$next[63:0]$14010 $2\data_r4__msr$next[63:0]$14014 assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$14083 $3\data_r4__msr_ok$next[0:0]$14088 - attribute \src "libresoc.v:201603.5-201603.29" + assign $0\data_r4__msr_ok$next[0:0]$14011 $3\data_r4__msr_ok$next[0:0]$14016 + attribute \src "libresoc.v:201200.5-201200.29" switch \initial - attribute \src "libresoc.v:201603.9-201603.17" + attribute \src "libresoc.v:201200.9-201200.17" case 1'1 case end @@ -383907,10 +383046,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$14085 $1\data_r4__msr$next[63:0]$14084 } { \msr_ok \alu_trap0_msr } + assign { $1\data_r4__msr_ok$next[0:0]$14013 $1\data_r4__msr$next[63:0]$14012 } { \msr_ok \alu_trap0_msr } case - assign $1\data_r4__msr$next[63:0]$14084 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$14085 \data_r4__msr_ok + assign $1\data_r4__msr$next[63:0]$14012 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14013 \data_r4__msr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -383918,32 +383057,32 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$14087 $2\data_r4__msr$next[63:0]$14086 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r4__msr_ok$next[0:0]$14015 $2\data_r4__msr$next[63:0]$14014 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$14086 $1\data_r4__msr$next[63:0]$14084 - assign $2\data_r4__msr_ok$next[0:0]$14087 $1\data_r4__msr_ok$next[0:0]$14085 + assign $2\data_r4__msr$next[63:0]$14014 $1\data_r4__msr$next[63:0]$14012 + assign $2\data_r4__msr_ok$next[0:0]$14015 $1\data_r4__msr_ok$next[0:0]$14013 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$14088 1'0 + assign $3\data_r4__msr_ok$next[0:0]$14016 1'0 case - assign $3\data_r4__msr_ok$next[0:0]$14088 $2\data_r4__msr_ok$next[0:0]$14087 + assign $3\data_r4__msr_ok$next[0:0]$14016 $2\data_r4__msr_ok$next[0:0]$14015 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14082 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14083 + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14010 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14011 end - attribute \src "libresoc.v:201624.3-201633.6" - process $proc$libresoc.v:201624$14089 + attribute \src "libresoc.v:201221.3-201230.6" + process $proc$libresoc.v:201221$14017 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$14090 $1\src_r0$next[63:0]$14091 - attribute \src "libresoc.v:201625.5-201625.29" + assign $0\src_r0$next[63:0]$14018 $1\src_r0$next[63:0]$14019 + attribute \src "libresoc.v:201222.5-201222.29" switch \initial - attribute \src "libresoc.v:201625.9-201625.17" + attribute \src "libresoc.v:201222.9-201222.17" case 1'1 case end @@ -383952,21 +383091,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$14091 \src1_i + assign $1\src_r0$next[63:0]$14019 \src1_i case - assign $1\src_r0$next[63:0]$14091 \src_r0 + assign $1\src_r0$next[63:0]$14019 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$14090 + update \src_r0$next $0\src_r0$next[63:0]$14018 end - attribute \src "libresoc.v:201634.3-201643.6" - process $proc$libresoc.v:201634$14092 + attribute \src "libresoc.v:201231.3-201240.6" + process $proc$libresoc.v:201231$14020 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$14093 $1\src_r1$next[63:0]$14094 - attribute \src "libresoc.v:201635.5-201635.29" + assign $0\src_r1$next[63:0]$14021 $1\src_r1$next[63:0]$14022 + attribute \src "libresoc.v:201232.5-201232.29" switch \initial - attribute \src "libresoc.v:201635.9-201635.17" + attribute \src "libresoc.v:201232.9-201232.17" case 1'1 case end @@ -383975,21 +383114,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$14094 \src2_i + assign $1\src_r1$next[63:0]$14022 \src2_i case - assign $1\src_r1$next[63:0]$14094 \src_r1 + assign $1\src_r1$next[63:0]$14022 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$14093 + update \src_r1$next $0\src_r1$next[63:0]$14021 end - attribute \src "libresoc.v:201644.3-201653.6" - process $proc$libresoc.v:201644$14095 + attribute \src "libresoc.v:201241.3-201250.6" + process $proc$libresoc.v:201241$14023 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$14096 $1\src_r2$next[63:0]$14097 - attribute \src "libresoc.v:201645.5-201645.29" + assign $0\src_r2$next[63:0]$14024 $1\src_r2$next[63:0]$14025 + attribute \src "libresoc.v:201242.5-201242.29" switch \initial - attribute \src "libresoc.v:201645.9-201645.17" + attribute \src "libresoc.v:201242.9-201242.17" case 1'1 case end @@ -383998,21 +383137,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$14097 \src3_i + assign $1\src_r2$next[63:0]$14025 \src3_i case - assign $1\src_r2$next[63:0]$14097 \src_r2 + assign $1\src_r2$next[63:0]$14025 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$14096 + update \src_r2$next $0\src_r2$next[63:0]$14024 end - attribute \src "libresoc.v:201654.3-201663.6" - process $proc$libresoc.v:201654$14098 + attribute \src "libresoc.v:201251.3-201260.6" + process $proc$libresoc.v:201251$14026 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$14099 $1\src_r3$next[63:0]$14100 - attribute \src "libresoc.v:201655.5-201655.29" + assign $0\src_r3$next[63:0]$14027 $1\src_r3$next[63:0]$14028 + attribute \src "libresoc.v:201252.5-201252.29" switch \initial - attribute \src "libresoc.v:201655.9-201655.17" + attribute \src "libresoc.v:201252.9-201252.17" case 1'1 case end @@ -384021,21 +383160,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$14100 \src4_i + assign $1\src_r3$next[63:0]$14028 \src4_i case - assign $1\src_r3$next[63:0]$14100 \src_r3 + assign $1\src_r3$next[63:0]$14028 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[63:0]$14099 + update \src_r3$next $0\src_r3$next[63:0]$14027 end - attribute \src "libresoc.v:201664.3-201672.6" - process $proc$libresoc.v:201664$14101 + attribute \src "libresoc.v:201261.3-201269.6" + process $proc$libresoc.v:201261$14029 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$14102 $1\alui_l_r_alui$next[0:0]$14103 - attribute \src "libresoc.v:201665.5-201665.29" + assign $0\alui_l_r_alui$next[0:0]$14030 $1\alui_l_r_alui$next[0:0]$14031 + attribute \src "libresoc.v:201262.5-201262.29" switch \initial - attribute \src "libresoc.v:201665.9-201665.17" + attribute \src "libresoc.v:201262.9-201262.17" case 1'1 case end @@ -384044,21 +383183,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$14103 1'1 + assign $1\alui_l_r_alui$next[0:0]$14031 1'1 case - assign $1\alui_l_r_alui$next[0:0]$14103 \$89 + assign $1\alui_l_r_alui$next[0:0]$14031 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14102 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14030 end - attribute \src "libresoc.v:201673.3-201681.6" - process $proc$libresoc.v:201673$14104 + attribute \src "libresoc.v:201270.3-201278.6" + process $proc$libresoc.v:201270$14032 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$14105 $1\alu_l_r_alu$next[0:0]$14106 - attribute \src "libresoc.v:201674.5-201674.29" + assign $0\alu_l_r_alu$next[0:0]$14033 $1\alu_l_r_alu$next[0:0]$14034 + attribute \src "libresoc.v:201271.5-201271.29" switch \initial - attribute \src "libresoc.v:201674.9-201674.17" + attribute \src "libresoc.v:201271.9-201271.17" case 1'1 case end @@ -384067,21 +383206,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$14106 1'1 + assign $1\alu_l_r_alu$next[0:0]$14034 1'1 case - assign $1\alu_l_r_alu$next[0:0]$14106 \$91 + assign $1\alu_l_r_alu$next[0:0]$14034 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14105 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14033 end - attribute \src "libresoc.v:201682.3-201691.6" - process $proc$libresoc.v:201682$14107 + attribute \src "libresoc.v:201279.3-201288.6" + process $proc$libresoc.v:201279$14035 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:201683.5-201683.29" + attribute \src "libresoc.v:201280.5-201280.29" switch \initial - attribute \src "libresoc.v:201683.9-201683.17" + attribute \src "libresoc.v:201280.9-201280.17" case 1'1 case end @@ -384097,14 +383236,14 @@ module \trap0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:201692.3-201701.6" - process $proc$libresoc.v:201692$14108 + attribute \src "libresoc.v:201289.3-201298.6" + process $proc$libresoc.v:201289$14036 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:201693.5-201693.29" + attribute \src "libresoc.v:201290.5-201290.29" switch \initial - attribute \src "libresoc.v:201693.9-201693.17" + attribute \src "libresoc.v:201290.9-201290.17" case 1'1 case end @@ -384120,14 +383259,14 @@ module \trap0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:201702.3-201711.6" - process $proc$libresoc.v:201702$14109 + attribute \src "libresoc.v:201299.3-201308.6" + process $proc$libresoc.v:201299$14037 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:201703.5-201703.29" + attribute \src "libresoc.v:201300.5-201300.29" switch \initial - attribute \src "libresoc.v:201703.9-201703.17" + attribute \src "libresoc.v:201300.9-201300.17" case 1'1 case end @@ -384143,14 +383282,14 @@ module \trap0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:201712.3-201721.6" - process $proc$libresoc.v:201712$14110 + attribute \src "libresoc.v:201309.3-201318.6" + process $proc$libresoc.v:201309$14038 assign { } { } assign { } { } assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "libresoc.v:201713.5-201713.29" + attribute \src "libresoc.v:201310.5-201310.29" switch \initial - attribute \src "libresoc.v:201713.9-201713.17" + attribute \src "libresoc.v:201310.9-201310.17" case 1'1 case end @@ -384166,14 +383305,14 @@ module \trap0 sync always update \dest4_o $0\dest4_o[63:0] end - attribute \src "libresoc.v:201722.3-201731.6" - process $proc$libresoc.v:201722$14111 + attribute \src "libresoc.v:201319.3-201328.6" + process $proc$libresoc.v:201319$14039 assign { } { } assign { } { } assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "libresoc.v:201723.5-201723.29" + attribute \src "libresoc.v:201320.5-201320.29" switch \initial - attribute \src "libresoc.v:201723.9-201723.17" + attribute \src "libresoc.v:201320.9-201320.17" case 1'1 case end @@ -384189,14 +383328,14 @@ module \trap0 sync always update \dest5_o $0\dest5_o[63:0] end - attribute \src "libresoc.v:201732.3-201740.6" - process $proc$libresoc.v:201732$14112 + attribute \src "libresoc.v:201329.3-201337.6" + process $proc$libresoc.v:201329$14040 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$14113 $1\prev_wr_go$next[4:0]$14114 - attribute \src "libresoc.v:201733.5-201733.29" + assign $0\prev_wr_go$next[4:0]$14041 $1\prev_wr_go$next[4:0]$14042 + attribute \src "libresoc.v:201330.5-201330.29" switch \initial - attribute \src "libresoc.v:201733.9-201733.17" + attribute \src "libresoc.v:201330.9-201330.17" case 1'1 case end @@ -384205,74 +383344,74 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$14114 5'00000 - case - assign $1\prev_wr_go$next[4:0]$14114 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14113 - end - connect \$5 $reduce_and$libresoc.v:201180$13900_Y - connect \$99 $and$libresoc.v:201181$13901_Y - connect \$101 $and$libresoc.v:201182$13902_Y - connect \$103 $and$libresoc.v:201183$13903_Y - connect \$105 $and$libresoc.v:201184$13904_Y - connect \$107 $and$libresoc.v:201185$13905_Y - connect \$109 $and$libresoc.v:201186$13906_Y - connect \$111 $and$libresoc.v:201187$13907_Y - connect \$113 $and$libresoc.v:201188$13908_Y - connect \$115 $and$libresoc.v:201189$13909_Y - connect \$117 $and$libresoc.v:201190$13910_Y - connect \$11 $and$libresoc.v:201191$13911_Y - connect \$119 $and$libresoc.v:201192$13912_Y - connect \$121 $and$libresoc.v:201193$13913_Y - connect \$123 $and$libresoc.v:201194$13914_Y - connect \$13 $not$libresoc.v:201195$13915_Y - connect \$15 $and$libresoc.v:201196$13916_Y - connect \$17 $not$libresoc.v:201197$13917_Y - connect \$19 $and$libresoc.v:201198$13918_Y - connect \$21 $and$libresoc.v:201199$13919_Y - connect \$25 $not$libresoc.v:201200$13920_Y - connect \$27 $and$libresoc.v:201201$13921_Y - connect \$24 $reduce_or$libresoc.v:201202$13922_Y - connect \$23 $not$libresoc.v:201203$13923_Y - connect \$31 $and$libresoc.v:201204$13924_Y - connect \$33 $reduce_or$libresoc.v:201205$13925_Y - connect \$35 $reduce_or$libresoc.v:201206$13926_Y - connect \$37 $or$libresoc.v:201207$13927_Y - connect \$3 $and$libresoc.v:201208$13928_Y - connect \$39 $not$libresoc.v:201209$13929_Y - connect \$41 $and$libresoc.v:201210$13930_Y - connect \$43 $and$libresoc.v:201211$13931_Y - connect \$45 $eq$libresoc.v:201212$13932_Y - connect \$47 $and$libresoc.v:201213$13933_Y - connect \$49 $eq$libresoc.v:201214$13934_Y - connect \$51 $and$libresoc.v:201215$13935_Y - connect \$53 $and$libresoc.v:201216$13936_Y - connect \$55 $and$libresoc.v:201217$13937_Y - connect \$57 $or$libresoc.v:201218$13938_Y - connect \$59 $or$libresoc.v:201219$13939_Y - connect \$61 $or$libresoc.v:201220$13940_Y - connect \$63 $or$libresoc.v:201221$13941_Y - connect \$65 $and$libresoc.v:201222$13942_Y - connect \$67 $and$libresoc.v:201223$13943_Y - connect \$6 $not$libresoc.v:201224$13944_Y - connect \$69 $or$libresoc.v:201225$13945_Y - connect \$71 $and$libresoc.v:201226$13946_Y - connect \$73 $and$libresoc.v:201227$13947_Y - connect \$75 $and$libresoc.v:201228$13948_Y - connect \$77 $and$libresoc.v:201229$13949_Y - connect \$79 $and$libresoc.v:201230$13950_Y - connect \$81 $ternary$libresoc.v:201231$13951_Y - connect \$83 $ternary$libresoc.v:201232$13952_Y - connect \$85 $ternary$libresoc.v:201233$13953_Y - connect \$87 $ternary$libresoc.v:201234$13954_Y - connect \$8 $or$libresoc.v:201235$13955_Y - connect \$89 $and$libresoc.v:201236$13956_Y - connect \$91 $and$libresoc.v:201237$13957_Y - connect \$93 $and$libresoc.v:201238$13958_Y - connect \$95 $and$libresoc.v:201239$13959_Y - connect \$97 $not$libresoc.v:201240$13960_Y + assign $1\prev_wr_go$next[4:0]$14042 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14042 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14041 + end + connect \$5 $reduce_and$libresoc.v:200777$13828_Y + connect \$99 $and$libresoc.v:200778$13829_Y + connect \$101 $and$libresoc.v:200779$13830_Y + connect \$103 $and$libresoc.v:200780$13831_Y + connect \$105 $and$libresoc.v:200781$13832_Y + connect \$107 $and$libresoc.v:200782$13833_Y + connect \$109 $and$libresoc.v:200783$13834_Y + connect \$111 $and$libresoc.v:200784$13835_Y + connect \$113 $and$libresoc.v:200785$13836_Y + connect \$115 $and$libresoc.v:200786$13837_Y + connect \$117 $and$libresoc.v:200787$13838_Y + connect \$11 $and$libresoc.v:200788$13839_Y + connect \$119 $and$libresoc.v:200789$13840_Y + connect \$121 $and$libresoc.v:200790$13841_Y + connect \$123 $and$libresoc.v:200791$13842_Y + connect \$13 $not$libresoc.v:200792$13843_Y + connect \$15 $and$libresoc.v:200793$13844_Y + connect \$17 $not$libresoc.v:200794$13845_Y + connect \$19 $and$libresoc.v:200795$13846_Y + connect \$21 $and$libresoc.v:200796$13847_Y + connect \$25 $not$libresoc.v:200797$13848_Y + connect \$27 $and$libresoc.v:200798$13849_Y + connect \$24 $reduce_or$libresoc.v:200799$13850_Y + connect \$23 $not$libresoc.v:200800$13851_Y + connect \$31 $and$libresoc.v:200801$13852_Y + connect \$33 $reduce_or$libresoc.v:200802$13853_Y + connect \$35 $reduce_or$libresoc.v:200803$13854_Y + connect \$37 $or$libresoc.v:200804$13855_Y + connect \$3 $and$libresoc.v:200805$13856_Y + connect \$39 $not$libresoc.v:200806$13857_Y + connect \$41 $and$libresoc.v:200807$13858_Y + connect \$43 $and$libresoc.v:200808$13859_Y + connect \$45 $eq$libresoc.v:200809$13860_Y + connect \$47 $and$libresoc.v:200810$13861_Y + connect \$49 $eq$libresoc.v:200811$13862_Y + connect \$51 $and$libresoc.v:200812$13863_Y + connect \$53 $and$libresoc.v:200813$13864_Y + connect \$55 $and$libresoc.v:200814$13865_Y + connect \$57 $or$libresoc.v:200815$13866_Y + connect \$59 $or$libresoc.v:200816$13867_Y + connect \$61 $or$libresoc.v:200817$13868_Y + connect \$63 $or$libresoc.v:200818$13869_Y + connect \$65 $and$libresoc.v:200819$13870_Y + connect \$67 $and$libresoc.v:200820$13871_Y + connect \$6 $not$libresoc.v:200821$13872_Y + connect \$69 $or$libresoc.v:200822$13873_Y + connect \$71 $and$libresoc.v:200823$13874_Y + connect \$73 $and$libresoc.v:200824$13875_Y + connect \$75 $and$libresoc.v:200825$13876_Y + connect \$77 $and$libresoc.v:200826$13877_Y + connect \$79 $and$libresoc.v:200827$13878_Y + connect \$81 $ternary$libresoc.v:200828$13879_Y + connect \$83 $ternary$libresoc.v:200829$13880_Y + connect \$85 $ternary$libresoc.v:200830$13881_Y + connect \$87 $ternary$libresoc.v:200831$13882_Y + connect \$8 $or$libresoc.v:200832$13883_Y + connect \$89 $and$libresoc.v:200833$13884_Y + connect \$91 $and$libresoc.v:200834$13885_Y + connect \$93 $and$libresoc.v:200835$13886_Y + connect \$95 $and$libresoc.v:200836$13887_Y + connect \$97 $not$libresoc.v:200837$13888_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$113 @@ -384303,37 +383442,37 @@ module \trap0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:201774.1-201832.10" +attribute \src "libresoc.v:201371.1-201429.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" attribute \generator "nMigen" module \upd_l - attribute \src "libresoc.v:201775.7-201775.20" + attribute \src "libresoc.v:201372.7-201372.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201820.3-201828.6" - wire $0\q_int$next[0:0]$14164 - attribute \src "libresoc.v:201818.3-201819.27" + attribute \src "libresoc.v:201417.3-201425.6" + wire $0\q_int$next[0:0]$14092 + attribute \src "libresoc.v:201415.3-201416.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:201820.3-201828.6" - wire $1\q_int$next[0:0]$14165 - attribute \src "libresoc.v:201797.7-201797.19" + attribute \src "libresoc.v:201417.3-201425.6" + wire $1\q_int$next[0:0]$14093 + attribute \src "libresoc.v:201394.7-201394.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:201810.17-201810.96" - wire $and$libresoc.v:201810$14154_Y - attribute \src "libresoc.v:201815.17-201815.96" - wire $and$libresoc.v:201815$14159_Y - attribute \src "libresoc.v:201812.18-201812.93" - wire $not$libresoc.v:201812$14156_Y - attribute \src "libresoc.v:201814.17-201814.92" - wire $not$libresoc.v:201814$14158_Y - attribute \src "libresoc.v:201817.17-201817.92" - wire $not$libresoc.v:201817$14161_Y - attribute \src "libresoc.v:201811.18-201811.98" - wire $or$libresoc.v:201811$14155_Y - attribute \src "libresoc.v:201813.18-201813.99" - wire $or$libresoc.v:201813$14157_Y - attribute \src "libresoc.v:201816.17-201816.97" - wire $or$libresoc.v:201816$14160_Y + attribute \src "libresoc.v:201407.17-201407.96" + wire $and$libresoc.v:201407$14082_Y + attribute \src "libresoc.v:201412.17-201412.96" + wire $and$libresoc.v:201412$14087_Y + attribute \src "libresoc.v:201409.18-201409.93" + wire $not$libresoc.v:201409$14084_Y + attribute \src "libresoc.v:201411.17-201411.92" + wire $not$libresoc.v:201411$14086_Y + attribute \src "libresoc.v:201414.17-201414.92" + wire $not$libresoc.v:201414$14089_Y + attribute \src "libresoc.v:201408.18-201408.98" + wire $or$libresoc.v:201408$14083_Y + attribute \src "libresoc.v:201410.18-201410.99" + wire $or$libresoc.v:201410$14085_Y + attribute \src "libresoc.v:201413.17-201413.97" + wire $or$libresoc.v:201413$14088_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -384350,11 +383489,11 @@ module \upd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:201775.7-201775.15" + attribute \src "libresoc.v:201372.7-201372.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -384371,7 +383510,7 @@ module \upd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:201810$14154 + cell $and $and$libresoc.v:201407$14082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384379,10 +383518,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:201810$14154_Y + connect \Y $and$libresoc.v:201407$14082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:201815$14159 + cell $and $and$libresoc.v:201412$14087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384390,34 +383529,34 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:201815$14159_Y + connect \Y $and$libresoc.v:201412$14087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:201812$14156 + cell $not $not$libresoc.v:201409$14084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd - connect \Y $not$libresoc.v:201812$14156_Y + connect \Y $not$libresoc.v:201409$14084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:201814$14158 + cell $not $not$libresoc.v:201411$14086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:201814$14158_Y + connect \Y $not$libresoc.v:201411$14086_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:201817$14161 + cell $not $not$libresoc.v:201414$14089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:201817$14161_Y + connect \Y $not$libresoc.v:201414$14089_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:201811$14155 + cell $or $or$libresoc.v:201408$14083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384425,10 +383564,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_upd - connect \Y $or$libresoc.v:201811$14155_Y + connect \Y $or$libresoc.v:201408$14083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:201813$14157 + cell $or $or$libresoc.v:201410$14085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384436,10 +383575,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_upd connect \B \q_int - connect \Y $or$libresoc.v:201813$14157_Y + connect \Y $or$libresoc.v:201410$14085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:201816$14160 + cell $or $or$libresoc.v:201413$14088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384447,39 +383586,39 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_upd - connect \Y $or$libresoc.v:201816$14160_Y + connect \Y $or$libresoc.v:201413$14088_Y end - attribute \src "libresoc.v:201775.7-201775.20" - process $proc$libresoc.v:201775$14166 + attribute \src "libresoc.v:201372.7-201372.20" + process $proc$libresoc.v:201372$14094 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201797.7-201797.19" - process $proc$libresoc.v:201797$14167 + attribute \src "libresoc.v:201394.7-201394.19" + process $proc$libresoc.v:201394$14095 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:201818.3-201819.27" - process $proc$libresoc.v:201818$14162 + attribute \src "libresoc.v:201415.3-201416.27" + process $proc$libresoc.v:201415$14090 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:201820.3-201828.6" - process $proc$libresoc.v:201820$14163 + attribute \src "libresoc.v:201417.3-201425.6" + process $proc$libresoc.v:201417$14091 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14164 $1\q_int$next[0:0]$14165 - attribute \src "libresoc.v:201821.5-201821.29" + assign $0\q_int$next[0:0]$14092 $1\q_int$next[0:0]$14093 + attribute \src "libresoc.v:201418.5-201418.29" switch \initial - attribute \src "libresoc.v:201821.9-201821.17" + attribute \src "libresoc.v:201418.9-201418.17" case 1'1 case end @@ -384488,56 +383627,56 @@ module \upd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14165 1'0 + assign $1\q_int$next[0:0]$14093 1'0 case - assign $1\q_int$next[0:0]$14165 \$5 + assign $1\q_int$next[0:0]$14093 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14164 + update \q_int$next $0\q_int$next[0:0]$14092 end - connect \$9 $and$libresoc.v:201810$14154_Y - connect \$11 $or$libresoc.v:201811$14155_Y - connect \$13 $not$libresoc.v:201812$14156_Y - connect \$15 $or$libresoc.v:201813$14157_Y - connect \$1 $not$libresoc.v:201814$14158_Y - connect \$3 $and$libresoc.v:201815$14159_Y - connect \$5 $or$libresoc.v:201816$14160_Y - connect \$7 $not$libresoc.v:201817$14161_Y + connect \$9 $and$libresoc.v:201407$14082_Y + connect \$11 $or$libresoc.v:201408$14083_Y + connect \$13 $not$libresoc.v:201409$14084_Y + connect \$15 $or$libresoc.v:201410$14085_Y + connect \$1 $not$libresoc.v:201411$14086_Y + connect \$3 $and$libresoc.v:201412$14087_Y + connect \$5 $or$libresoc.v:201413$14088_Y + connect \$7 $not$libresoc.v:201414$14089_Y connect \qlq_upd \$15 connect \qn_upd \$13 connect \q_upd \$11 end -attribute \src "libresoc.v:201836.1-201894.10" +attribute \src "libresoc.v:201433.1-201491.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" attribute \generator "nMigen" module \valid_l - attribute \src "libresoc.v:201837.7-201837.20" + attribute \src "libresoc.v:201434.7-201434.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201882.3-201890.6" - wire $0\q_int$next[0:0]$14178 - attribute \src "libresoc.v:201880.3-201881.27" + attribute \src "libresoc.v:201479.3-201487.6" + wire $0\q_int$next[0:0]$14106 + attribute \src "libresoc.v:201477.3-201478.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:201882.3-201890.6" - wire $1\q_int$next[0:0]$14179 - attribute \src "libresoc.v:201859.7-201859.19" + attribute \src "libresoc.v:201479.3-201487.6" + wire $1\q_int$next[0:0]$14107 + attribute \src "libresoc.v:201456.7-201456.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:201872.17-201872.96" - wire $and$libresoc.v:201872$14168_Y - attribute \src "libresoc.v:201877.17-201877.96" - wire $and$libresoc.v:201877$14173_Y - attribute \src "libresoc.v:201874.18-201874.95" - wire $not$libresoc.v:201874$14170_Y - attribute \src "libresoc.v:201876.17-201876.94" - wire $not$libresoc.v:201876$14172_Y - attribute \src "libresoc.v:201879.17-201879.94" - wire $not$libresoc.v:201879$14175_Y - attribute \src "libresoc.v:201873.18-201873.100" - wire $or$libresoc.v:201873$14169_Y - attribute \src "libresoc.v:201875.18-201875.101" - wire $or$libresoc.v:201875$14171_Y - attribute \src "libresoc.v:201878.17-201878.99" - wire $or$libresoc.v:201878$14174_Y + attribute \src "libresoc.v:201469.17-201469.96" + wire $and$libresoc.v:201469$14096_Y + attribute \src "libresoc.v:201474.17-201474.96" + wire $and$libresoc.v:201474$14101_Y + attribute \src "libresoc.v:201471.18-201471.95" + wire $not$libresoc.v:201471$14098_Y + attribute \src "libresoc.v:201473.17-201473.94" + wire $not$libresoc.v:201473$14100_Y + attribute \src "libresoc.v:201476.17-201476.94" + wire $not$libresoc.v:201476$14103_Y + attribute \src "libresoc.v:201470.18-201470.100" + wire $or$libresoc.v:201470$14097_Y + attribute \src "libresoc.v:201472.18-201472.101" + wire $or$libresoc.v:201472$14099_Y + attribute \src "libresoc.v:201475.17-201475.99" + wire $or$libresoc.v:201475$14102_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -384554,11 +383693,11 @@ module \valid_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:201837.7-201837.15" + attribute \src "libresoc.v:201434.7-201434.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -384575,7 +383714,7 @@ module \valid_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:201872$14168 + cell $and $and$libresoc.v:201469$14096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384583,10 +383722,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:201872$14168_Y + connect \Y $and$libresoc.v:201469$14096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:201877$14173 + cell $and $and$libresoc.v:201474$14101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384594,34 +383733,34 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:201877$14173_Y + connect \Y $and$libresoc.v:201474$14101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:201874$14170 + cell $not $not$libresoc.v:201471$14098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid - connect \Y $not$libresoc.v:201874$14170_Y + connect \Y $not$libresoc.v:201471$14098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:201876$14172 + cell $not $not$libresoc.v:201473$14100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:201876$14172_Y + connect \Y $not$libresoc.v:201473$14100_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:201879$14175 + cell $not $not$libresoc.v:201476$14103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:201879$14175_Y + connect \Y $not$libresoc.v:201476$14103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:201873$14169 + cell $or $or$libresoc.v:201470$14097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384629,10 +383768,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_valid - connect \Y $or$libresoc.v:201873$14169_Y + connect \Y $or$libresoc.v:201470$14097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:201875$14171 + cell $or $or$libresoc.v:201472$14099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384640,10 +383779,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_valid connect \B \q_int - connect \Y $or$libresoc.v:201875$14171_Y + connect \Y $or$libresoc.v:201472$14099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:201878$14174 + cell $or $or$libresoc.v:201475$14102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384651,39 +383790,39 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_valid - connect \Y $or$libresoc.v:201878$14174_Y + connect \Y $or$libresoc.v:201475$14102_Y end - attribute \src "libresoc.v:201837.7-201837.20" - process $proc$libresoc.v:201837$14180 + attribute \src "libresoc.v:201434.7-201434.20" + process $proc$libresoc.v:201434$14108 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201859.7-201859.19" - process $proc$libresoc.v:201859$14181 + attribute \src "libresoc.v:201456.7-201456.19" + process $proc$libresoc.v:201456$14109 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:201880.3-201881.27" - process $proc$libresoc.v:201880$14176 + attribute \src "libresoc.v:201477.3-201478.27" + process $proc$libresoc.v:201477$14104 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:201882.3-201890.6" - process $proc$libresoc.v:201882$14177 + attribute \src "libresoc.v:201479.3-201487.6" + process $proc$libresoc.v:201479$14105 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14178 $1\q_int$next[0:0]$14179 - attribute \src "libresoc.v:201883.5-201883.29" + assign $0\q_int$next[0:0]$14106 $1\q_int$next[0:0]$14107 + attribute \src "libresoc.v:201480.5-201480.29" switch \initial - attribute \src "libresoc.v:201883.9-201883.17" + attribute \src "libresoc.v:201480.9-201480.17" case 1'1 case end @@ -384692,56 +383831,56 @@ module \valid_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14179 1'0 + assign $1\q_int$next[0:0]$14107 1'0 case - assign $1\q_int$next[0:0]$14179 \$5 + assign $1\q_int$next[0:0]$14107 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14178 + update \q_int$next $0\q_int$next[0:0]$14106 end - connect \$9 $and$libresoc.v:201872$14168_Y - connect \$11 $or$libresoc.v:201873$14169_Y - connect \$13 $not$libresoc.v:201874$14170_Y - connect \$15 $or$libresoc.v:201875$14171_Y - connect \$1 $not$libresoc.v:201876$14172_Y - connect \$3 $and$libresoc.v:201877$14173_Y - connect \$5 $or$libresoc.v:201878$14174_Y - connect \$7 $not$libresoc.v:201879$14175_Y + connect \$9 $and$libresoc.v:201469$14096_Y + connect \$11 $or$libresoc.v:201470$14097_Y + connect \$13 $not$libresoc.v:201471$14098_Y + connect \$15 $or$libresoc.v:201472$14099_Y + connect \$1 $not$libresoc.v:201473$14100_Y + connect \$3 $and$libresoc.v:201474$14101_Y + connect \$5 $or$libresoc.v:201475$14102_Y + connect \$7 $not$libresoc.v:201476$14103_Y connect \qlq_valid \$15 connect \qn_valid \$13 connect \q_valid \$11 end -attribute \src "libresoc.v:201898.1-201956.10" +attribute \src "libresoc.v:201495.1-201553.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" attribute \generator "nMigen" module \wri_l - attribute \src "libresoc.v:201899.7-201899.20" + attribute \src "libresoc.v:201496.7-201496.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201944.3-201952.6" - wire $0\q_int$next[0:0]$14192 - attribute \src "libresoc.v:201942.3-201943.27" + attribute \src "libresoc.v:201541.3-201549.6" + wire $0\q_int$next[0:0]$14120 + attribute \src "libresoc.v:201539.3-201540.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:201944.3-201952.6" - wire $1\q_int$next[0:0]$14193 - attribute \src "libresoc.v:201921.7-201921.19" + attribute \src "libresoc.v:201541.3-201549.6" + wire $1\q_int$next[0:0]$14121 + attribute \src "libresoc.v:201518.7-201518.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:201934.17-201934.96" - wire $and$libresoc.v:201934$14182_Y - attribute \src "libresoc.v:201939.17-201939.96" - wire $and$libresoc.v:201939$14187_Y - attribute \src "libresoc.v:201936.18-201936.93" - wire $not$libresoc.v:201936$14184_Y - attribute \src "libresoc.v:201938.17-201938.92" - wire $not$libresoc.v:201938$14186_Y - attribute \src "libresoc.v:201941.17-201941.92" - wire $not$libresoc.v:201941$14189_Y - attribute \src "libresoc.v:201935.18-201935.98" - wire $or$libresoc.v:201935$14183_Y - attribute \src "libresoc.v:201937.18-201937.99" - wire $or$libresoc.v:201937$14185_Y - attribute \src "libresoc.v:201940.17-201940.97" - wire $or$libresoc.v:201940$14188_Y + attribute \src "libresoc.v:201531.17-201531.96" + wire $and$libresoc.v:201531$14110_Y + attribute \src "libresoc.v:201536.17-201536.96" + wire $and$libresoc.v:201536$14115_Y + attribute \src "libresoc.v:201533.18-201533.93" + wire $not$libresoc.v:201533$14112_Y + attribute \src "libresoc.v:201535.17-201535.92" + wire $not$libresoc.v:201535$14114_Y + attribute \src "libresoc.v:201538.17-201538.92" + wire $not$libresoc.v:201538$14117_Y + attribute \src "libresoc.v:201532.18-201532.98" + wire $or$libresoc.v:201532$14111_Y + attribute \src "libresoc.v:201534.18-201534.99" + wire $or$libresoc.v:201534$14113_Y + attribute \src "libresoc.v:201537.17-201537.97" + wire $or$libresoc.v:201537$14116_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -384758,11 +383897,11 @@ module \wri_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst - attribute \src "libresoc.v:201899.7-201899.15" + attribute \src "libresoc.v:201496.7-201496.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -384779,7 +383918,7 @@ module \wri_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:201934$14182 + cell $and $and$libresoc.v:201531$14110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384787,10 +383926,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:201934$14182_Y + connect \Y $and$libresoc.v:201531$14110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:201939$14187 + cell $and $and$libresoc.v:201536$14115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384798,34 +383937,34 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:201939$14187_Y + connect \Y $and$libresoc.v:201536$14115_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:201936$14184 + cell $not $not$libresoc.v:201533$14112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri - connect \Y $not$libresoc.v:201936$14184_Y + connect \Y $not$libresoc.v:201533$14112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:201938$14186 + cell $not $not$libresoc.v:201535$14114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:201938$14186_Y + connect \Y $not$libresoc.v:201535$14114_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:201941$14189 + cell $not $not$libresoc.v:201538$14117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:201941$14189_Y + connect \Y $not$libresoc.v:201538$14117_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:201935$14183 + cell $or $or$libresoc.v:201532$14111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384833,10 +383972,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_wri - connect \Y $or$libresoc.v:201935$14183_Y + connect \Y $or$libresoc.v:201532$14111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:201937$14185 + cell $or $or$libresoc.v:201534$14113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384844,10 +383983,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_wri connect \B \q_int - connect \Y $or$libresoc.v:201937$14185_Y + connect \Y $or$libresoc.v:201534$14113_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:201940$14188 + cell $or $or$libresoc.v:201537$14116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384855,39 +383994,39 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_wri - connect \Y $or$libresoc.v:201940$14188_Y + connect \Y $or$libresoc.v:201537$14116_Y end - attribute \src "libresoc.v:201899.7-201899.20" - process $proc$libresoc.v:201899$14194 + attribute \src "libresoc.v:201496.7-201496.20" + process $proc$libresoc.v:201496$14122 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201921.7-201921.19" - process $proc$libresoc.v:201921$14195 + attribute \src "libresoc.v:201518.7-201518.19" + process $proc$libresoc.v:201518$14123 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:201942.3-201943.27" - process $proc$libresoc.v:201942$14190 + attribute \src "libresoc.v:201539.3-201540.27" + process $proc$libresoc.v:201539$14118 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:201944.3-201952.6" - process $proc$libresoc.v:201944$14191 + attribute \src "libresoc.v:201541.3-201549.6" + process $proc$libresoc.v:201541$14119 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14192 $1\q_int$next[0:0]$14193 - attribute \src "libresoc.v:201945.5-201945.29" + assign $0\q_int$next[0:0]$14120 $1\q_int$next[0:0]$14121 + attribute \src "libresoc.v:201542.5-201542.29" switch \initial - attribute \src "libresoc.v:201945.9-201945.17" + attribute \src "libresoc.v:201542.9-201542.17" case 1'1 case end @@ -384896,54 +384035,54 @@ module \wri_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14193 1'0 + assign $1\q_int$next[0:0]$14121 1'0 case - assign $1\q_int$next[0:0]$14193 \$5 + assign $1\q_int$next[0:0]$14121 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14192 + update \q_int$next $0\q_int$next[0:0]$14120 end - connect \$9 $and$libresoc.v:201934$14182_Y - connect \$11 $or$libresoc.v:201935$14183_Y - connect \$13 $not$libresoc.v:201936$14184_Y - connect \$15 $or$libresoc.v:201937$14185_Y - connect \$1 $not$libresoc.v:201938$14186_Y - connect \$3 $and$libresoc.v:201939$14187_Y - connect \$5 $or$libresoc.v:201940$14188_Y - connect \$7 $not$libresoc.v:201941$14189_Y + connect \$9 $and$libresoc.v:201531$14110_Y + connect \$11 $or$libresoc.v:201532$14111_Y + connect \$13 $not$libresoc.v:201533$14112_Y + connect \$15 $or$libresoc.v:201534$14113_Y + connect \$1 $not$libresoc.v:201535$14114_Y + connect \$3 $and$libresoc.v:201536$14115_Y + connect \$5 $or$libresoc.v:201537$14116_Y + connect \$7 $not$libresoc.v:201538$14117_Y connect \qlq_wri \$15 connect \qn_wri \$13 connect \q_wri \$11 end -attribute \src "libresoc.v:201960.1-202026.10" +attribute \src "libresoc.v:201557.1-201623.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" attribute \generator "nMigen" module \wrpick_CR_cr_a - attribute \src "libresoc.v:202005.17-202005.91" - wire $not$libresoc.v:202005$14196_Y - attribute \src "libresoc.v:202007.18-202007.93" - wire $not$libresoc.v:202007$14198_Y - attribute \src "libresoc.v:202009.18-202009.93" - wire $not$libresoc.v:202009$14200_Y - attribute \src "libresoc.v:202010.17-202010.89" - wire width 6 $not$libresoc.v:202010$14201_Y - attribute \src "libresoc.v:202012.18-202012.93" - wire $not$libresoc.v:202012$14203_Y - attribute \src "libresoc.v:202015.17-202015.91" - wire $not$libresoc.v:202015$14206_Y - attribute \src "libresoc.v:202006.18-202006.106" - wire $reduce_or$libresoc.v:202006$14197_Y - attribute \src "libresoc.v:202008.18-202008.106" - wire $reduce_or$libresoc.v:202008$14199_Y - attribute \src "libresoc.v:202011.18-202011.106" - wire $reduce_or$libresoc.v:202011$14202_Y - attribute \src "libresoc.v:202013.18-202013.90" - wire $reduce_or$libresoc.v:202013$14204_Y - attribute \src "libresoc.v:202014.17-202014.103" - wire $reduce_or$libresoc.v:202014$14205_Y - attribute \src "libresoc.v:202016.17-202016.105" - wire $reduce_or$libresoc.v:202016$14207_Y + attribute \src "libresoc.v:201602.17-201602.91" + wire $not$libresoc.v:201602$14124_Y + attribute \src "libresoc.v:201604.18-201604.93" + wire $not$libresoc.v:201604$14126_Y + attribute \src "libresoc.v:201606.18-201606.93" + wire $not$libresoc.v:201606$14128_Y + attribute \src "libresoc.v:201607.17-201607.89" + wire width 6 $not$libresoc.v:201607$14129_Y + attribute \src "libresoc.v:201609.18-201609.93" + wire $not$libresoc.v:201609$14131_Y + attribute \src "libresoc.v:201612.17-201612.91" + wire $not$libresoc.v:201612$14134_Y + attribute \src "libresoc.v:201603.18-201603.106" + wire $reduce_or$libresoc.v:201603$14125_Y + attribute \src "libresoc.v:201605.18-201605.106" + wire $reduce_or$libresoc.v:201605$14127_Y + attribute \src "libresoc.v:201608.18-201608.106" + wire $reduce_or$libresoc.v:201608$14130_Y + attribute \src "libresoc.v:201610.18-201610.90" + wire $reduce_or$libresoc.v:201610$14132_Y + attribute \src "libresoc.v:201611.17-201611.103" + wire $reduce_or$libresoc.v:201611$14133_Y + attribute \src "libresoc.v:201613.17-201613.105" + wire $reduce_or$libresoc.v:201613$14135_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -384989,113 +384128,113 @@ module \wrpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202005$14196 + cell $not $not$libresoc.v:201602$14124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:202005$14196_Y + connect \Y $not$libresoc.v:201602$14124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202007$14198 + cell $not $not$libresoc.v:201604$14126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:202007$14198_Y + connect \Y $not$libresoc.v:201604$14126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202009$14200 + cell $not $not$libresoc.v:201606$14128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:202009$14200_Y + connect \Y $not$libresoc.v:201606$14128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:202010$14201 + cell $not $not$libresoc.v:201607$14129 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:202010$14201_Y + connect \Y $not$libresoc.v:201607$14129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202012$14203 + cell $not $not$libresoc.v:201609$14131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:202012$14203_Y + connect \Y $not$libresoc.v:201609$14131_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202015$14206 + cell $not $not$libresoc.v:201612$14134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:202015$14206_Y + connect \Y $not$libresoc.v:201612$14134_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202006$14197 + cell $reduce_or $reduce_or$libresoc.v:201603$14125 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:202006$14197_Y + connect \Y $reduce_or$libresoc.v:201603$14125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202008$14199 + cell $reduce_or $reduce_or$libresoc.v:201605$14127 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:202008$14199_Y + connect \Y $reduce_or$libresoc.v:201605$14127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202011$14202 + cell $reduce_or $reduce_or$libresoc.v:201608$14130 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:202011$14202_Y + connect \Y $reduce_or$libresoc.v:201608$14130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:202013$14204 + cell $reduce_or $reduce_or$libresoc.v:201610$14132 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:202013$14204_Y + connect \Y $reduce_or$libresoc.v:201610$14132_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202014$14205 + cell $reduce_or $reduce_or$libresoc.v:201611$14133 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:202014$14205_Y + connect \Y $reduce_or$libresoc.v:201611$14133_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202016$14207 + cell $reduce_or $reduce_or$libresoc.v:201613$14135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:202016$14207_Y - end - connect \$7 $not$libresoc.v:202005$14196_Y - connect \$12 $reduce_or$libresoc.v:202006$14197_Y - connect \$11 $not$libresoc.v:202007$14198_Y - connect \$16 $reduce_or$libresoc.v:202008$14199_Y - connect \$15 $not$libresoc.v:202009$14200_Y - connect \$1 $not$libresoc.v:202010$14201_Y - connect \$20 $reduce_or$libresoc.v:202011$14202_Y - connect \$19 $not$libresoc.v:202012$14203_Y - connect \$23 $reduce_or$libresoc.v:202013$14204_Y - connect \$4 $reduce_or$libresoc.v:202014$14205_Y - connect \$3 $not$libresoc.v:202015$14206_Y - connect \$8 $reduce_or$libresoc.v:202016$14207_Y + connect \Y $reduce_or$libresoc.v:201613$14135_Y + end + connect \$7 $not$libresoc.v:201602$14124_Y + connect \$12 $reduce_or$libresoc.v:201603$14125_Y + connect \$11 $not$libresoc.v:201604$14126_Y + connect \$16 $reduce_or$libresoc.v:201605$14127_Y + connect \$15 $not$libresoc.v:201606$14128_Y + connect \$1 $not$libresoc.v:201607$14129_Y + connect \$20 $reduce_or$libresoc.v:201608$14130_Y + connect \$19 $not$libresoc.v:201609$14131_Y + connect \$23 $reduce_or$libresoc.v:201610$14132_Y + connect \$4 $reduce_or$libresoc.v:201611$14133_Y + connect \$3 $not$libresoc.v:201612$14134_Y + connect \$8 $reduce_or$libresoc.v:201613$14135_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -385106,15 +384245,15 @@ module \wrpick_CR_cr_a connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:202030.1-202051.10" +attribute \src "libresoc.v:201627.1-201648.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" attribute \generator "nMigen" module \wrpick_CR_full_cr - attribute \src "libresoc.v:202045.17-202045.89" - wire $not$libresoc.v:202045$14208_Y - attribute \src "libresoc.v:202046.17-202046.89" - wire $reduce_or$libresoc.v:202046$14209_Y + attribute \src "libresoc.v:201642.17-201642.89" + wire $not$libresoc.v:201642$14136_Y + attribute \src "libresoc.v:201643.17-201643.89" + wire $reduce_or$libresoc.v:201643$14137_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -385130,53 +384269,53 @@ module \wrpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:202045$14208 + cell $not $not$libresoc.v:201642$14136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:202045$14208_Y + connect \Y $not$libresoc.v:201642$14136_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:202046$14209 + cell $reduce_or $reduce_or$libresoc.v:201643$14137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:202046$14209_Y + connect \Y $reduce_or$libresoc.v:201643$14137_Y end - connect \$1 $not$libresoc.v:202045$14208_Y - connect \$3 $reduce_or$libresoc.v:202046$14209_Y + connect \$1 $not$libresoc.v:201642$14136_Y + connect \$3 $reduce_or$libresoc.v:201643$14137_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:202055.1-202112.10" +attribute \src "libresoc.v:201652.1-201709.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" attribute \generator "nMigen" module \wrpick_FAST_fast1 - attribute \src "libresoc.v:202094.17-202094.91" - wire $not$libresoc.v:202094$14210_Y - attribute \src "libresoc.v:202096.18-202096.93" - wire $not$libresoc.v:202096$14212_Y - attribute \src "libresoc.v:202098.18-202098.93" - wire $not$libresoc.v:202098$14214_Y - attribute \src "libresoc.v:202099.17-202099.89" - wire width 5 $not$libresoc.v:202099$14215_Y - attribute \src "libresoc.v:202102.17-202102.91" - wire $not$libresoc.v:202102$14218_Y - attribute \src "libresoc.v:202095.18-202095.106" - wire $reduce_or$libresoc.v:202095$14211_Y - attribute \src "libresoc.v:202097.18-202097.106" - wire $reduce_or$libresoc.v:202097$14213_Y - attribute \src "libresoc.v:202100.18-202100.90" - wire $reduce_or$libresoc.v:202100$14216_Y - attribute \src "libresoc.v:202101.17-202101.103" - wire $reduce_or$libresoc.v:202101$14217_Y - attribute \src "libresoc.v:202103.17-202103.105" - wire $reduce_or$libresoc.v:202103$14219_Y + attribute \src "libresoc.v:201691.17-201691.91" + wire $not$libresoc.v:201691$14138_Y + attribute \src "libresoc.v:201693.18-201693.93" + wire $not$libresoc.v:201693$14140_Y + attribute \src "libresoc.v:201695.18-201695.93" + wire $not$libresoc.v:201695$14142_Y + attribute \src "libresoc.v:201696.17-201696.89" + wire width 5 $not$libresoc.v:201696$14143_Y + attribute \src "libresoc.v:201699.17-201699.91" + wire $not$libresoc.v:201699$14146_Y + attribute \src "libresoc.v:201692.18-201692.106" + wire $reduce_or$libresoc.v:201692$14139_Y + attribute \src "libresoc.v:201694.18-201694.106" + wire $reduce_or$libresoc.v:201694$14141_Y + attribute \src "libresoc.v:201697.18-201697.90" + wire $reduce_or$libresoc.v:201697$14144_Y + attribute \src "libresoc.v:201698.17-201698.103" + wire $reduce_or$libresoc.v:201698$14145_Y + attribute \src "libresoc.v:201700.17-201700.105" + wire $reduce_or$libresoc.v:201700$14147_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -385216,95 +384355,95 @@ module \wrpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202094$14210 + cell $not $not$libresoc.v:201691$14138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:202094$14210_Y + connect \Y $not$libresoc.v:201691$14138_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202096$14212 + cell $not $not$libresoc.v:201693$14140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:202096$14212_Y + connect \Y $not$libresoc.v:201693$14140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202098$14214 + cell $not $not$libresoc.v:201695$14142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:202098$14214_Y + connect \Y $not$libresoc.v:201695$14142_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:202099$14215 + cell $not $not$libresoc.v:201696$14143 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i - connect \Y $not$libresoc.v:202099$14215_Y + connect \Y $not$libresoc.v:201696$14143_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202102$14218 + cell $not $not$libresoc.v:201699$14146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:202102$14218_Y + connect \Y $not$libresoc.v:201699$14146_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202095$14211 + cell $reduce_or $reduce_or$libresoc.v:201692$14139 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:202095$14211_Y + connect \Y $reduce_or$libresoc.v:201692$14139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202097$14213 + cell $reduce_or $reduce_or$libresoc.v:201694$14141 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:202097$14213_Y + connect \Y $reduce_or$libresoc.v:201694$14141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:202100$14216 + cell $reduce_or $reduce_or$libresoc.v:201697$14144 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:202100$14216_Y + connect \Y $reduce_or$libresoc.v:201697$14144_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202101$14217 + cell $reduce_or $reduce_or$libresoc.v:201698$14145 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:202101$14217_Y + connect \Y $reduce_or$libresoc.v:201698$14145_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202103$14219 + cell $reduce_or $reduce_or$libresoc.v:201700$14147 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:202103$14219_Y - end - connect \$7 $not$libresoc.v:202094$14210_Y - connect \$12 $reduce_or$libresoc.v:202095$14211_Y - connect \$11 $not$libresoc.v:202096$14212_Y - connect \$16 $reduce_or$libresoc.v:202097$14213_Y - connect \$15 $not$libresoc.v:202098$14214_Y - connect \$1 $not$libresoc.v:202099$14215_Y - connect \$19 $reduce_or$libresoc.v:202100$14216_Y - connect \$4 $reduce_or$libresoc.v:202101$14217_Y - connect \$3 $not$libresoc.v:202102$14218_Y - connect \$8 $reduce_or$libresoc.v:202103$14219_Y + connect \Y $reduce_or$libresoc.v:201700$14147_Y + end + connect \$7 $not$libresoc.v:201691$14138_Y + connect \$12 $reduce_or$libresoc.v:201692$14139_Y + connect \$11 $not$libresoc.v:201693$14140_Y + connect \$16 $reduce_or$libresoc.v:201694$14141_Y + connect \$15 $not$libresoc.v:201695$14142_Y + connect \$1 $not$libresoc.v:201696$14143_Y + connect \$19 $reduce_or$libresoc.v:201697$14144_Y + connect \$4 $reduce_or$libresoc.v:201698$14145_Y + connect \$3 $not$libresoc.v:201699$14146_Y + connect \$8 $reduce_or$libresoc.v:201700$14147_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 @@ -385314,51 +384453,51 @@ module \wrpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:202116.1-202218.10" +attribute \src "libresoc.v:201713.1-201815.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" attribute \generator "nMigen" module \wrpick_INT_o - attribute \src "libresoc.v:202185.17-202185.91" - wire $not$libresoc.v:202185$14220_Y - attribute \src "libresoc.v:202187.18-202187.93" - wire $not$libresoc.v:202187$14222_Y - attribute \src "libresoc.v:202189.18-202189.93" - wire $not$libresoc.v:202189$14224_Y - attribute \src "libresoc.v:202190.17-202190.89" - wire width 10 $not$libresoc.v:202190$14225_Y - attribute \src "libresoc.v:202192.18-202192.93" - wire $not$libresoc.v:202192$14227_Y - attribute \src "libresoc.v:202194.18-202194.93" - wire $not$libresoc.v:202194$14229_Y - attribute \src "libresoc.v:202196.18-202196.93" - wire $not$libresoc.v:202196$14231_Y - attribute \src "libresoc.v:202198.18-202198.93" - wire $not$libresoc.v:202198$14233_Y - attribute \src "libresoc.v:202200.18-202200.93" - wire $not$libresoc.v:202200$14235_Y - attribute \src "libresoc.v:202203.17-202203.91" - wire $not$libresoc.v:202203$14238_Y - attribute \src "libresoc.v:202186.18-202186.106" - wire $reduce_or$libresoc.v:202186$14221_Y - attribute \src "libresoc.v:202188.18-202188.106" - wire $reduce_or$libresoc.v:202188$14223_Y - attribute \src "libresoc.v:202191.18-202191.106" - wire $reduce_or$libresoc.v:202191$14226_Y - attribute \src "libresoc.v:202193.18-202193.106" - wire $reduce_or$libresoc.v:202193$14228_Y - attribute \src "libresoc.v:202195.18-202195.106" - wire $reduce_or$libresoc.v:202195$14230_Y - attribute \src "libresoc.v:202197.18-202197.106" - wire $reduce_or$libresoc.v:202197$14232_Y - attribute \src "libresoc.v:202199.18-202199.106" - wire $reduce_or$libresoc.v:202199$14234_Y - attribute \src "libresoc.v:202201.18-202201.90" - wire $reduce_or$libresoc.v:202201$14236_Y - attribute \src "libresoc.v:202202.17-202202.103" - wire $reduce_or$libresoc.v:202202$14237_Y - attribute \src "libresoc.v:202204.17-202204.105" - wire $reduce_or$libresoc.v:202204$14239_Y + attribute \src "libresoc.v:201782.17-201782.91" + wire $not$libresoc.v:201782$14148_Y + attribute \src "libresoc.v:201784.18-201784.93" + wire $not$libresoc.v:201784$14150_Y + attribute \src "libresoc.v:201786.18-201786.93" + wire $not$libresoc.v:201786$14152_Y + attribute \src "libresoc.v:201787.17-201787.89" + wire width 10 $not$libresoc.v:201787$14153_Y + attribute \src "libresoc.v:201789.18-201789.93" + wire $not$libresoc.v:201789$14155_Y + attribute \src "libresoc.v:201791.18-201791.93" + wire $not$libresoc.v:201791$14157_Y + attribute \src "libresoc.v:201793.18-201793.93" + wire $not$libresoc.v:201793$14159_Y + attribute \src "libresoc.v:201795.18-201795.93" + wire $not$libresoc.v:201795$14161_Y + attribute \src "libresoc.v:201797.18-201797.93" + wire $not$libresoc.v:201797$14163_Y + attribute \src "libresoc.v:201800.17-201800.91" + wire $not$libresoc.v:201800$14166_Y + attribute \src "libresoc.v:201783.18-201783.106" + wire $reduce_or$libresoc.v:201783$14149_Y + attribute \src "libresoc.v:201785.18-201785.106" + wire $reduce_or$libresoc.v:201785$14151_Y + attribute \src "libresoc.v:201788.18-201788.106" + wire $reduce_or$libresoc.v:201788$14154_Y + attribute \src "libresoc.v:201790.18-201790.106" + wire $reduce_or$libresoc.v:201790$14156_Y + attribute \src "libresoc.v:201792.18-201792.106" + wire $reduce_or$libresoc.v:201792$14158_Y + attribute \src "libresoc.v:201794.18-201794.106" + wire $reduce_or$libresoc.v:201794$14160_Y + attribute \src "libresoc.v:201796.18-201796.106" + wire $reduce_or$libresoc.v:201796$14162_Y + attribute \src "libresoc.v:201798.18-201798.90" + wire $reduce_or$libresoc.v:201798$14164_Y + attribute \src "libresoc.v:201799.17-201799.103" + wire $reduce_or$libresoc.v:201799$14165_Y + attribute \src "libresoc.v:201801.17-201801.105" + wire $reduce_or$libresoc.v:201801$14167_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 10 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -385428,185 +384567,185 @@ module \wrpick_INT_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202185$14220 + cell $not $not$libresoc.v:201782$14148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:202185$14220_Y + connect \Y $not$libresoc.v:201782$14148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202187$14222 + cell $not $not$libresoc.v:201784$14150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:202187$14222_Y + connect \Y $not$libresoc.v:201784$14150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202189$14224 + cell $not $not$libresoc.v:201786$14152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:202189$14224_Y + connect \Y $not$libresoc.v:201786$14152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:202190$14225 + cell $not $not$libresoc.v:201787$14153 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 connect \A \i - connect \Y $not$libresoc.v:202190$14225_Y + connect \Y $not$libresoc.v:201787$14153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202192$14227 + cell $not $not$libresoc.v:201789$14155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:202192$14227_Y + connect \Y $not$libresoc.v:201789$14155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202194$14229 + cell $not $not$libresoc.v:201791$14157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:202194$14229_Y + connect \Y $not$libresoc.v:201791$14157_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202196$14231 + cell $not $not$libresoc.v:201793$14159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:202196$14231_Y + connect \Y $not$libresoc.v:201793$14159_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202198$14233 + cell $not $not$libresoc.v:201795$14161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:202198$14233_Y + connect \Y $not$libresoc.v:201795$14161_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202200$14235 + cell $not $not$libresoc.v:201797$14163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 - connect \Y $not$libresoc.v:202200$14235_Y + connect \Y $not$libresoc.v:201797$14163_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202203$14238 + cell $not $not$libresoc.v:201800$14166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:202203$14238_Y + connect \Y $not$libresoc.v:201800$14166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202186$14221 + cell $reduce_or $reduce_or$libresoc.v:201783$14149 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:202186$14221_Y + connect \Y $reduce_or$libresoc.v:201783$14149_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202188$14223 + cell $reduce_or $reduce_or$libresoc.v:201785$14151 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:202188$14223_Y + connect \Y $reduce_or$libresoc.v:201785$14151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202191$14226 + cell $reduce_or $reduce_or$libresoc.v:201788$14154 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:202191$14226_Y + connect \Y $reduce_or$libresoc.v:201788$14154_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202193$14228 + cell $reduce_or $reduce_or$libresoc.v:201790$14156 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:202193$14228_Y + connect \Y $reduce_or$libresoc.v:201790$14156_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202195$14230 + cell $reduce_or $reduce_or$libresoc.v:201792$14158 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:202195$14230_Y + connect \Y $reduce_or$libresoc.v:201792$14158_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202197$14232 + cell $reduce_or $reduce_or$libresoc.v:201794$14160 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:202197$14232_Y + connect \Y $reduce_or$libresoc.v:201794$14160_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202199$14234 + cell $reduce_or $reduce_or$libresoc.v:201796$14162 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:202199$14234_Y + connect \Y $reduce_or$libresoc.v:201796$14162_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:202201$14236 + cell $reduce_or $reduce_or$libresoc.v:201798$14164 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:202201$14236_Y + connect \Y $reduce_or$libresoc.v:201798$14164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202202$14237 + cell $reduce_or $reduce_or$libresoc.v:201799$14165 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:202202$14237_Y + connect \Y $reduce_or$libresoc.v:201799$14165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202204$14239 + cell $reduce_or $reduce_or$libresoc.v:201801$14167 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:202204$14239_Y - end - connect \$7 $not$libresoc.v:202185$14220_Y - connect \$12 $reduce_or$libresoc.v:202186$14221_Y - connect \$11 $not$libresoc.v:202187$14222_Y - connect \$16 $reduce_or$libresoc.v:202188$14223_Y - connect \$15 $not$libresoc.v:202189$14224_Y - connect \$1 $not$libresoc.v:202190$14225_Y - connect \$20 $reduce_or$libresoc.v:202191$14226_Y - connect \$19 $not$libresoc.v:202192$14227_Y - connect \$24 $reduce_or$libresoc.v:202193$14228_Y - connect \$23 $not$libresoc.v:202194$14229_Y - connect \$28 $reduce_or$libresoc.v:202195$14230_Y - connect \$27 $not$libresoc.v:202196$14231_Y - connect \$32 $reduce_or$libresoc.v:202197$14232_Y - connect \$31 $not$libresoc.v:202198$14233_Y - connect \$36 $reduce_or$libresoc.v:202199$14234_Y - connect \$35 $not$libresoc.v:202200$14235_Y - connect \$39 $reduce_or$libresoc.v:202201$14236_Y - connect \$4 $reduce_or$libresoc.v:202202$14237_Y - connect \$3 $not$libresoc.v:202203$14238_Y - connect \$8 $reduce_or$libresoc.v:202204$14239_Y + connect \Y $reduce_or$libresoc.v:201801$14167_Y + end + connect \$7 $not$libresoc.v:201782$14148_Y + connect \$12 $reduce_or$libresoc.v:201783$14149_Y + connect \$11 $not$libresoc.v:201784$14150_Y + connect \$16 $reduce_or$libresoc.v:201785$14151_Y + connect \$15 $not$libresoc.v:201786$14152_Y + connect \$1 $not$libresoc.v:201787$14153_Y + connect \$20 $reduce_or$libresoc.v:201788$14154_Y + connect \$19 $not$libresoc.v:201789$14155_Y + connect \$24 $reduce_or$libresoc.v:201790$14156_Y + connect \$23 $not$libresoc.v:201791$14157_Y + connect \$28 $reduce_or$libresoc.v:201792$14158_Y + connect \$27 $not$libresoc.v:201793$14159_Y + connect \$32 $reduce_or$libresoc.v:201794$14160_Y + connect \$31 $not$libresoc.v:201795$14161_Y + connect \$36 $reduce_or$libresoc.v:201796$14162_Y + connect \$35 $not$libresoc.v:201797$14163_Y + connect \$39 $reduce_or$libresoc.v:201798$14164_Y + connect \$4 $reduce_or$libresoc.v:201799$14165_Y + connect \$3 $not$libresoc.v:201800$14166_Y + connect \$8 $reduce_or$libresoc.v:201801$14167_Y connect \en_o \$39 connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t9 \$35 @@ -385621,15 +384760,15 @@ module \wrpick_INT_o connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:202222.1-202243.10" +attribute \src "libresoc.v:201819.1-201840.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" attribute \generator "nMigen" module \wrpick_SPR_spr1 - attribute \src "libresoc.v:202237.17-202237.89" - wire $not$libresoc.v:202237$14240_Y - attribute \src "libresoc.v:202238.17-202238.89" - wire $reduce_or$libresoc.v:202238$14241_Y + attribute \src "libresoc.v:201834.17-201834.89" + wire $not$libresoc.v:201834$14168_Y + attribute \src "libresoc.v:201835.17-201835.89" + wire $reduce_or$libresoc.v:201835$14169_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -385645,37 +384784,37 @@ module \wrpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:202237$14240 + cell $not $not$libresoc.v:201834$14168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:202237$14240_Y + connect \Y $not$libresoc.v:201834$14168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:202238$14241 + cell $reduce_or $reduce_or$libresoc.v:201835$14169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:202238$14241_Y + connect \Y $reduce_or$libresoc.v:201835$14169_Y end - connect \$1 $not$libresoc.v:202237$14240_Y - connect \$3 $reduce_or$libresoc.v:202238$14241_Y + connect \$1 $not$libresoc.v:201834$14168_Y + connect \$3 $reduce_or$libresoc.v:201835$14169_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:202247.1-202268.10" +attribute \src "libresoc.v:201844.1-201865.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" attribute \generator "nMigen" module \wrpick_STATE_msr - attribute \src "libresoc.v:202262.17-202262.89" - wire $not$libresoc.v:202262$14242_Y - attribute \src "libresoc.v:202263.17-202263.89" - wire $reduce_or$libresoc.v:202263$14243_Y + attribute \src "libresoc.v:201859.17-201859.89" + wire $not$libresoc.v:201859$14170_Y + attribute \src "libresoc.v:201860.17-201860.89" + wire $reduce_or$libresoc.v:201860$14171_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -385691,41 +384830,41 @@ module \wrpick_STATE_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:202262$14242 + cell $not $not$libresoc.v:201859$14170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:202262$14242_Y + connect \Y $not$libresoc.v:201859$14170_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:202263$14243 + cell $reduce_or $reduce_or$libresoc.v:201860$14171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:202263$14243_Y + connect \Y $reduce_or$libresoc.v:201860$14171_Y end - connect \$1 $not$libresoc.v:202262$14242_Y - connect \$3 $reduce_or$libresoc.v:202263$14243_Y + connect \$1 $not$libresoc.v:201859$14170_Y + connect \$3 $reduce_or$libresoc.v:201860$14171_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:202272.1-202302.10" +attribute \src "libresoc.v:201869.1-201899.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" attribute \generator "nMigen" module \wrpick_STATE_nia - attribute \src "libresoc.v:202293.17-202293.89" - wire width 2 $not$libresoc.v:202293$14244_Y - attribute \src "libresoc.v:202295.17-202295.91" - wire $not$libresoc.v:202295$14246_Y - attribute \src "libresoc.v:202294.17-202294.103" - wire $reduce_or$libresoc.v:202294$14245_Y - attribute \src "libresoc.v:202296.17-202296.89" - wire $reduce_or$libresoc.v:202296$14247_Y + attribute \src "libresoc.v:201890.17-201890.89" + wire width 2 $not$libresoc.v:201890$14172_Y + attribute \src "libresoc.v:201892.17-201892.91" + wire $not$libresoc.v:201892$14174_Y + attribute \src "libresoc.v:201891.17-201891.103" + wire $reduce_or$libresoc.v:201891$14173_Y + attribute \src "libresoc.v:201893.17-201893.89" + wire $reduce_or$libresoc.v:201893$14175_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -385747,64 +384886,64 @@ module \wrpick_STATE_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:202293$14244 + cell $not $not$libresoc.v:201890$14172 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:202293$14244_Y + connect \Y $not$libresoc.v:201890$14172_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202295$14246 + cell $not $not$libresoc.v:201892$14174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:202295$14246_Y + connect \Y $not$libresoc.v:201892$14174_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202294$14245 + cell $reduce_or $reduce_or$libresoc.v:201891$14173 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:202294$14245_Y + connect \Y $reduce_or$libresoc.v:201891$14173_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:202296$14247 + cell $reduce_or $reduce_or$libresoc.v:201893$14175 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:202296$14247_Y + connect \Y $reduce_or$libresoc.v:201893$14175_Y end - connect \$1 $not$libresoc.v:202293$14244_Y - connect \$4 $reduce_or$libresoc.v:202294$14245_Y - connect \$3 $not$libresoc.v:202295$14246_Y - connect \$7 $reduce_or$libresoc.v:202296$14247_Y + connect \$1 $not$libresoc.v:201890$14172_Y + connect \$4 $reduce_or$libresoc.v:201891$14173_Y + connect \$3 $not$libresoc.v:201892$14174_Y + connect \$7 $reduce_or$libresoc.v:201893$14175_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:202306.1-202345.10" +attribute \src "libresoc.v:201903.1-201942.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" attribute \generator "nMigen" module \wrpick_XER_xer_ca - attribute \src "libresoc.v:202333.17-202333.91" - wire $not$libresoc.v:202333$14248_Y - attribute \src "libresoc.v:202335.17-202335.89" - wire width 3 $not$libresoc.v:202335$14250_Y - attribute \src "libresoc.v:202337.17-202337.91" - wire $not$libresoc.v:202337$14252_Y - attribute \src "libresoc.v:202334.18-202334.90" - wire $reduce_or$libresoc.v:202334$14249_Y - attribute \src "libresoc.v:202336.17-202336.103" - wire $reduce_or$libresoc.v:202336$14251_Y - attribute \src "libresoc.v:202338.17-202338.105" - wire $reduce_or$libresoc.v:202338$14253_Y + attribute \src "libresoc.v:201930.17-201930.91" + wire $not$libresoc.v:201930$14176_Y + attribute \src "libresoc.v:201932.17-201932.89" + wire width 3 $not$libresoc.v:201932$14178_Y + attribute \src "libresoc.v:201934.17-201934.91" + wire $not$libresoc.v:201934$14180_Y + attribute \src "libresoc.v:201931.18-201931.90" + wire $reduce_or$libresoc.v:201931$14177_Y + attribute \src "libresoc.v:201933.17-201933.103" + wire $reduce_or$libresoc.v:201933$14179_Y + attribute \src "libresoc.v:201935.17-201935.105" + wire $reduce_or$libresoc.v:201935$14181_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -385832,59 +384971,59 @@ module \wrpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202333$14248 + cell $not $not$libresoc.v:201930$14176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:202333$14248_Y + connect \Y $not$libresoc.v:201930$14176_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:202335$14250 + cell $not $not$libresoc.v:201932$14178 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:202335$14250_Y + connect \Y $not$libresoc.v:201932$14178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202337$14252 + cell $not $not$libresoc.v:201934$14180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:202337$14252_Y + connect \Y $not$libresoc.v:201934$14180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:202334$14249 + cell $reduce_or $reduce_or$libresoc.v:201931$14177 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:202334$14249_Y + connect \Y $reduce_or$libresoc.v:201931$14177_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202336$14251 + cell $reduce_or $reduce_or$libresoc.v:201933$14179 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:202336$14251_Y + connect \Y $reduce_or$libresoc.v:201933$14179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202338$14253 + cell $reduce_or $reduce_or$libresoc.v:201935$14181 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:202338$14253_Y - end - connect \$7 $not$libresoc.v:202333$14248_Y - connect \$11 $reduce_or$libresoc.v:202334$14249_Y - connect \$1 $not$libresoc.v:202335$14250_Y - connect \$4 $reduce_or$libresoc.v:202336$14251_Y - connect \$3 $not$libresoc.v:202337$14252_Y - connect \$8 $reduce_or$libresoc.v:202338$14253_Y + connect \Y $reduce_or$libresoc.v:201935$14181_Y + end + connect \$7 $not$libresoc.v:201930$14176_Y + connect \$11 $reduce_or$libresoc.v:201931$14177_Y + connect \$1 $not$libresoc.v:201932$14178_Y + connect \$4 $reduce_or$libresoc.v:201933$14179_Y + connect \$3 $not$libresoc.v:201934$14180_Y + connect \$8 $reduce_or$libresoc.v:201935$14181_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -385892,27 +385031,27 @@ module \wrpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:202349.1-202397.10" +attribute \src "libresoc.v:201946.1-201994.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" attribute \generator "nMigen" module \wrpick_XER_xer_ov - attribute \src "libresoc.v:202382.17-202382.91" - wire $not$libresoc.v:202382$14254_Y - attribute \src "libresoc.v:202384.18-202384.93" - wire $not$libresoc.v:202384$14256_Y - attribute \src "libresoc.v:202386.17-202386.89" - wire width 4 $not$libresoc.v:202386$14258_Y - attribute \src "libresoc.v:202388.17-202388.91" - wire $not$libresoc.v:202388$14260_Y - attribute \src "libresoc.v:202383.18-202383.106" - wire $reduce_or$libresoc.v:202383$14255_Y - attribute \src "libresoc.v:202385.18-202385.90" - wire $reduce_or$libresoc.v:202385$14257_Y - attribute \src "libresoc.v:202387.17-202387.103" - wire $reduce_or$libresoc.v:202387$14259_Y - attribute \src "libresoc.v:202389.17-202389.105" - wire $reduce_or$libresoc.v:202389$14261_Y + attribute \src "libresoc.v:201979.17-201979.91" + wire $not$libresoc.v:201979$14182_Y + attribute \src "libresoc.v:201981.18-201981.93" + wire $not$libresoc.v:201981$14184_Y + attribute \src "libresoc.v:201983.17-201983.89" + wire width 4 $not$libresoc.v:201983$14186_Y + attribute \src "libresoc.v:201985.17-201985.91" + wire $not$libresoc.v:201985$14188_Y + attribute \src "libresoc.v:201980.18-201980.106" + wire $reduce_or$libresoc.v:201980$14183_Y + attribute \src "libresoc.v:201982.18-201982.90" + wire $reduce_or$libresoc.v:201982$14185_Y + attribute \src "libresoc.v:201984.17-201984.103" + wire $reduce_or$libresoc.v:201984$14187_Y + attribute \src "libresoc.v:201986.17-201986.105" + wire $reduce_or$libresoc.v:201986$14189_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -385946,77 +385085,77 @@ module \wrpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202382$14254 + cell $not $not$libresoc.v:201979$14182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:202382$14254_Y + connect \Y $not$libresoc.v:201979$14182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202384$14256 + cell $not $not$libresoc.v:201981$14184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:202384$14256_Y + connect \Y $not$libresoc.v:201981$14184_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:202386$14258 + cell $not $not$libresoc.v:201983$14186 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:202386$14258_Y + connect \Y $not$libresoc.v:201983$14186_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202388$14260 + cell $not $not$libresoc.v:201985$14188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:202388$14260_Y + connect \Y $not$libresoc.v:201985$14188_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202383$14255 + cell $reduce_or $reduce_or$libresoc.v:201980$14183 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:202383$14255_Y + connect \Y $reduce_or$libresoc.v:201980$14183_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:202385$14257 + cell $reduce_or $reduce_or$libresoc.v:201982$14185 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:202385$14257_Y + connect \Y $reduce_or$libresoc.v:201982$14185_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202387$14259 + cell $reduce_or $reduce_or$libresoc.v:201984$14187 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:202387$14259_Y + connect \Y $reduce_or$libresoc.v:201984$14187_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202389$14261 + cell $reduce_or $reduce_or$libresoc.v:201986$14189 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:202389$14261_Y - end - connect \$7 $not$libresoc.v:202382$14254_Y - connect \$12 $reduce_or$libresoc.v:202383$14255_Y - connect \$11 $not$libresoc.v:202384$14256_Y - connect \$15 $reduce_or$libresoc.v:202385$14257_Y - connect \$1 $not$libresoc.v:202386$14258_Y - connect \$4 $reduce_or$libresoc.v:202387$14259_Y - connect \$3 $not$libresoc.v:202388$14260_Y - connect \$8 $reduce_or$libresoc.v:202389$14261_Y + connect \Y $reduce_or$libresoc.v:201986$14189_Y + end + connect \$7 $not$libresoc.v:201979$14182_Y + connect \$12 $reduce_or$libresoc.v:201980$14183_Y + connect \$11 $not$libresoc.v:201981$14184_Y + connect \$15 $reduce_or$libresoc.v:201982$14185_Y + connect \$1 $not$libresoc.v:201983$14186_Y + connect \$4 $reduce_or$libresoc.v:201984$14187_Y + connect \$3 $not$libresoc.v:201985$14188_Y + connect \$8 $reduce_or$libresoc.v:201986$14189_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -386025,27 +385164,27 @@ module \wrpick_XER_xer_ov connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:202401.1-202449.10" +attribute \src "libresoc.v:201998.1-202046.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" attribute \generator "nMigen" module \wrpick_XER_xer_so - attribute \src "libresoc.v:202434.17-202434.91" - wire $not$libresoc.v:202434$14262_Y - attribute \src "libresoc.v:202436.18-202436.93" - wire $not$libresoc.v:202436$14264_Y - attribute \src "libresoc.v:202438.17-202438.89" - wire width 4 $not$libresoc.v:202438$14266_Y - attribute \src "libresoc.v:202440.17-202440.91" - wire $not$libresoc.v:202440$14268_Y - attribute \src "libresoc.v:202435.18-202435.106" - wire $reduce_or$libresoc.v:202435$14263_Y - attribute \src "libresoc.v:202437.18-202437.90" - wire $reduce_or$libresoc.v:202437$14265_Y - attribute \src "libresoc.v:202439.17-202439.103" - wire $reduce_or$libresoc.v:202439$14267_Y - attribute \src "libresoc.v:202441.17-202441.105" - wire $reduce_or$libresoc.v:202441$14269_Y + attribute \src "libresoc.v:202031.17-202031.91" + wire $not$libresoc.v:202031$14190_Y + attribute \src "libresoc.v:202033.18-202033.93" + wire $not$libresoc.v:202033$14192_Y + attribute \src "libresoc.v:202035.17-202035.89" + wire width 4 $not$libresoc.v:202035$14194_Y + attribute \src "libresoc.v:202037.17-202037.91" + wire $not$libresoc.v:202037$14196_Y + attribute \src "libresoc.v:202032.18-202032.106" + wire $reduce_or$libresoc.v:202032$14191_Y + attribute \src "libresoc.v:202034.18-202034.90" + wire $reduce_or$libresoc.v:202034$14193_Y + attribute \src "libresoc.v:202036.17-202036.103" + wire $reduce_or$libresoc.v:202036$14195_Y + attribute \src "libresoc.v:202038.17-202038.105" + wire $reduce_or$libresoc.v:202038$14197_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -386079,77 +385218,77 @@ module \wrpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202434$14262 + cell $not $not$libresoc.v:202031$14190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:202434$14262_Y + connect \Y $not$libresoc.v:202031$14190_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202436$14264 + cell $not $not$libresoc.v:202033$14192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:202436$14264_Y + connect \Y $not$libresoc.v:202033$14192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:202438$14266 + cell $not $not$libresoc.v:202035$14194 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:202438$14266_Y + connect \Y $not$libresoc.v:202035$14194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:202440$14268 + cell $not $not$libresoc.v:202037$14196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:202440$14268_Y + connect \Y $not$libresoc.v:202037$14196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202435$14263 + cell $reduce_or $reduce_or$libresoc.v:202032$14191 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:202435$14263_Y + connect \Y $reduce_or$libresoc.v:202032$14191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:202437$14265 + cell $reduce_or $reduce_or$libresoc.v:202034$14193 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:202437$14265_Y + connect \Y $reduce_or$libresoc.v:202034$14193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202439$14267 + cell $reduce_or $reduce_or$libresoc.v:202036$14195 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:202439$14267_Y + connect \Y $reduce_or$libresoc.v:202036$14195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:202441$14269 + cell $reduce_or $reduce_or$libresoc.v:202038$14197 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:202441$14269_Y - end - connect \$7 $not$libresoc.v:202434$14262_Y - connect \$12 $reduce_or$libresoc.v:202435$14263_Y - connect \$11 $not$libresoc.v:202436$14264_Y - connect \$15 $reduce_or$libresoc.v:202437$14265_Y - connect \$1 $not$libresoc.v:202438$14266_Y - connect \$4 $reduce_or$libresoc.v:202439$14267_Y - connect \$3 $not$libresoc.v:202440$14268_Y - connect \$8 $reduce_or$libresoc.v:202441$14269_Y + connect \Y $reduce_or$libresoc.v:202038$14197_Y + end + connect \$7 $not$libresoc.v:202031$14190_Y + connect \$12 $reduce_or$libresoc.v:202032$14191_Y + connect \$11 $not$libresoc.v:202033$14192_Y + connect \$15 $reduce_or$libresoc.v:202034$14193_Y + connect \$1 $not$libresoc.v:202035$14194_Y + connect \$4 $reduce_or$libresoc.v:202036$14195_Y + connect \$3 $not$libresoc.v:202037$14196_Y + connect \$8 $reduce_or$libresoc.v:202038$14197_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -386158,67 +385297,67 @@ module \wrpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:202453.1-202773.10" +attribute \src "libresoc.v:202050.1-202370.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer" attribute \generator "nMigen" module \xer - attribute \src "libresoc.v:202454.7-202454.20" + attribute \src "libresoc.v:202051.7-202051.20" wire $0\initial[0:0] - attribute \src "libresoc.v:202733.3-202741.6" - wire width 3 $0\ren_delay$11$next[2:0]$14293 - attribute \src "libresoc.v:202631.3-202632.43" - wire width 3 $0\ren_delay$11[2:0]$14282 - attribute \src "libresoc.v:202590.13-202590.34" - wire width 3 $0\ren_delay$11[2:0]$14299 - attribute \src "libresoc.v:202695.3-202703.6" - wire width 3 $0\ren_delay$18$next[2:0]$14285 - attribute \src "libresoc.v:202629.3-202630.43" - wire width 3 $0\ren_delay$18[2:0]$14280 - attribute \src "libresoc.v:202594.13-202594.34" - wire width 3 $0\ren_delay$18[2:0]$14301 - attribute \src "libresoc.v:202714.3-202722.6" - wire width 3 $0\ren_delay$next[2:0]$14289 - attribute \src "libresoc.v:202633.3-202634.35" + attribute \src "libresoc.v:202330.3-202338.6" + wire width 3 $0\ren_delay$11$next[2:0]$14221 + attribute \src "libresoc.v:202228.3-202229.43" + wire width 3 $0\ren_delay$11[2:0]$14210 + attribute \src "libresoc.v:202187.13-202187.34" + wire width 3 $0\ren_delay$11[2:0]$14227 + attribute \src "libresoc.v:202292.3-202300.6" + wire width 3 $0\ren_delay$18$next[2:0]$14213 + attribute \src "libresoc.v:202226.3-202227.43" + wire width 3 $0\ren_delay$18[2:0]$14208 + attribute \src "libresoc.v:202191.13-202191.34" + wire width 3 $0\ren_delay$18[2:0]$14229 + attribute \src "libresoc.v:202311.3-202319.6" + wire width 3 $0\ren_delay$next[2:0]$14217 + attribute \src "libresoc.v:202230.3-202231.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:202723.3-202732.6" + attribute \src "libresoc.v:202320.3-202329.6" wire width 2 $0\src1__data_o[1:0] - attribute \src "libresoc.v:202742.3-202751.6" + attribute \src "libresoc.v:202339.3-202348.6" wire width 2 $0\src2__data_o[1:0] - attribute \src "libresoc.v:202704.3-202713.6" + attribute \src "libresoc.v:202301.3-202310.6" wire width 2 $0\src3__data_o[1:0] - attribute \src "libresoc.v:202733.3-202741.6" - wire width 3 $1\ren_delay$11$next[2:0]$14294 - attribute \src "libresoc.v:202695.3-202703.6" - wire width 3 $1\ren_delay$18$next[2:0]$14286 - attribute \src "libresoc.v:202714.3-202722.6" - wire width 3 $1\ren_delay$next[2:0]$14290 - attribute \src "libresoc.v:202588.13-202588.29" + attribute \src "libresoc.v:202330.3-202338.6" + wire width 3 $1\ren_delay$11$next[2:0]$14222 + attribute \src "libresoc.v:202292.3-202300.6" + wire width 3 $1\ren_delay$18$next[2:0]$14214 + attribute \src "libresoc.v:202311.3-202319.6" + wire width 3 $1\ren_delay$next[2:0]$14218 + attribute \src "libresoc.v:202185.13-202185.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:202723.3-202732.6" + attribute \src "libresoc.v:202320.3-202329.6" wire width 2 $1\src1__data_o[1:0] - attribute \src "libresoc.v:202742.3-202751.6" + attribute \src "libresoc.v:202339.3-202348.6" wire width 2 $1\src2__data_o[1:0] - attribute \src "libresoc.v:202704.3-202713.6" + attribute \src "libresoc.v:202301.3-202310.6" wire width 2 $1\src3__data_o[1:0] - attribute \src "libresoc.v:202620.17-202620.109" - wire width 2 $or$libresoc.v:202620$14270_Y - attribute \src "libresoc.v:202622.18-202622.126" - wire width 2 $or$libresoc.v:202622$14272_Y - attribute \src "libresoc.v:202623.18-202623.111" - wire width 2 $or$libresoc.v:202623$14273_Y - attribute \src "libresoc.v:202625.18-202625.126" - wire width 2 $or$libresoc.v:202625$14275_Y - attribute \src "libresoc.v:202626.18-202626.111" - wire width 2 $or$libresoc.v:202626$14276_Y - attribute \src "libresoc.v:202628.17-202628.125" - wire width 2 $or$libresoc.v:202628$14278_Y - attribute \src "libresoc.v:202621.18-202621.100" - wire $reduce_or$libresoc.v:202621$14271_Y - attribute \src "libresoc.v:202624.18-202624.100" - wire $reduce_or$libresoc.v:202624$14274_Y - attribute \src "libresoc.v:202627.17-202627.95" - wire $reduce_or$libresoc.v:202627$14277_Y + attribute \src "libresoc.v:202217.17-202217.109" + wire width 2 $or$libresoc.v:202217$14198_Y + attribute \src "libresoc.v:202219.18-202219.126" + wire width 2 $or$libresoc.v:202219$14200_Y + attribute \src "libresoc.v:202220.18-202220.111" + wire width 2 $or$libresoc.v:202220$14201_Y + attribute \src "libresoc.v:202222.18-202222.126" + wire width 2 $or$libresoc.v:202222$14203_Y + attribute \src "libresoc.v:202223.18-202223.111" + wire width 2 $or$libresoc.v:202223$14204_Y + attribute \src "libresoc.v:202225.17-202225.125" + wire width 2 $or$libresoc.v:202225$14206_Y + attribute \src "libresoc.v:202218.18-202218.100" + wire $reduce_or$libresoc.v:202218$14199_Y + attribute \src "libresoc.v:202221.18-202221.100" + wire $reduce_or$libresoc.v:202221$14202_Y + attribute \src "libresoc.v:202224.17-202224.95" + wire $reduce_or$libresoc.v:202224$14205_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -386237,9 +385376,9 @@ module \xer wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 10 \data_i @@ -386255,7 +385394,7 @@ module \xer wire width 6 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \full_wr__wen - attribute \src "libresoc.v:202454.7-202454.15" + attribute \src "libresoc.v:202051.7-202051.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest10__data_i @@ -386384,7 +385523,7 @@ module \xer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:202620$14270 + cell $or $or$libresoc.v:202217$14198 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -386392,10 +385531,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src10__data_o connect \B \$7 - connect \Y $or$libresoc.v:202620$14270_Y + connect \Y $or$libresoc.v:202217$14198_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:202622$14272 + cell $or $or$libresoc.v:202219$14200 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -386403,10 +385542,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src21__data_o connect \B \reg_2_src22__data_o - connect \Y $or$libresoc.v:202622$14272_Y + connect \Y $or$libresoc.v:202219$14200_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:202623$14273 + cell $or $or$libresoc.v:202220$14201 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -386414,10 +385553,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src20__data_o connect \B \$14 - connect \Y $or$libresoc.v:202623$14273_Y + connect \Y $or$libresoc.v:202220$14201_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:202625$14275 + cell $or $or$libresoc.v:202222$14203 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -386425,10 +385564,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src31__data_o connect \B \reg_2_src32__data_o - connect \Y $or$libresoc.v:202625$14275_Y + connect \Y $or$libresoc.v:202222$14203_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:202626$14276 + cell $or $or$libresoc.v:202223$14204 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -386436,10 +385575,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src30__data_o connect \B \$21 - connect \Y $or$libresoc.v:202626$14276_Y + connect \Y $or$libresoc.v:202223$14204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:202628$14278 + cell $or $or$libresoc.v:202225$14206 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -386447,34 +385586,34 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src11__data_o connect \B \reg_2_src12__data_o - connect \Y $or$libresoc.v:202628$14278_Y + connect \Y $or$libresoc.v:202225$14206_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:202621$14271 + cell $reduce_or $reduce_or$libresoc.v:202218$14199 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$11 - connect \Y $reduce_or$libresoc.v:202621$14271_Y + connect \Y $reduce_or$libresoc.v:202218$14199_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:202624$14274 + cell $reduce_or $reduce_or$libresoc.v:202221$14202 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$18 - connect \Y $reduce_or$libresoc.v:202624$14274_Y + connect \Y $reduce_or$libresoc.v:202221$14202_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:202627$14277 + cell $reduce_or $reduce_or$libresoc.v:202224$14205 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:202627$14277_Y + connect \Y $reduce_or$libresoc.v:202224$14205_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:202635.15-202654.4" + attribute \src "libresoc.v:202232.15-202251.4" cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -386496,7 +385635,7 @@ module \xer connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:202655.15-202674.4" + attribute \src "libresoc.v:202252.15-202271.4" cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -386518,7 +385657,7 @@ module \xer connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:202675.15-202694.4" + attribute \src "libresoc.v:202272.15-202291.4" cell \reg_2$134 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -386539,67 +385678,67 @@ module \xer connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end - attribute \src "libresoc.v:202454.7-202454.20" - process $proc$libresoc.v:202454$14296 + attribute \src "libresoc.v:202051.7-202051.20" + process $proc$libresoc.v:202051$14224 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:202588.13-202588.29" - process $proc$libresoc.v:202588$14297 + attribute \src "libresoc.v:202185.13-202185.29" + process $proc$libresoc.v:202185$14225 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:202590.13-202590.34" - process $proc$libresoc.v:202590$14298 + attribute \src "libresoc.v:202187.13-202187.34" + process $proc$libresoc.v:202187$14226 assign { } { } - assign $0\ren_delay$11[2:0]$14299 3'000 + assign $0\ren_delay$11[2:0]$14227 3'000 sync always sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$14299 + update \ren_delay$11 $0\ren_delay$11[2:0]$14227 end - attribute \src "libresoc.v:202594.13-202594.34" - process $proc$libresoc.v:202594$14300 + attribute \src "libresoc.v:202191.13-202191.34" + process $proc$libresoc.v:202191$14228 assign { } { } - assign $0\ren_delay$18[2:0]$14301 3'000 + assign $0\ren_delay$18[2:0]$14229 3'000 sync always sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$14301 + update \ren_delay$18 $0\ren_delay$18[2:0]$14229 end - attribute \src "libresoc.v:202629.3-202630.43" - process $proc$libresoc.v:202629$14279 + attribute \src "libresoc.v:202226.3-202227.43" + process $proc$libresoc.v:202226$14207 assign { } { } - assign $0\ren_delay$18[2:0]$14280 \ren_delay$18$next + assign $0\ren_delay$18[2:0]$14208 \ren_delay$18$next sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$14280 + update \ren_delay$18 $0\ren_delay$18[2:0]$14208 end - attribute \src "libresoc.v:202631.3-202632.43" - process $proc$libresoc.v:202631$14281 + attribute \src "libresoc.v:202228.3-202229.43" + process $proc$libresoc.v:202228$14209 assign { } { } - assign $0\ren_delay$11[2:0]$14282 \ren_delay$11$next + assign $0\ren_delay$11[2:0]$14210 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$14282 + update \ren_delay$11 $0\ren_delay$11[2:0]$14210 end - attribute \src "libresoc.v:202633.3-202634.35" - process $proc$libresoc.v:202633$14283 + attribute \src "libresoc.v:202230.3-202231.35" + process $proc$libresoc.v:202230$14211 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:202695.3-202703.6" - process $proc$libresoc.v:202695$14284 + attribute \src "libresoc.v:202292.3-202300.6" + process $proc$libresoc.v:202292$14212 assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$14285 $1\ren_delay$18$next[2:0]$14286 - attribute \src "libresoc.v:202696.5-202696.29" + assign $0\ren_delay$18$next[2:0]$14213 $1\ren_delay$18$next[2:0]$14214 + attribute \src "libresoc.v:202293.5-202293.29" switch \initial - attribute \src "libresoc.v:202696.9-202696.17" + attribute \src "libresoc.v:202293.9-202293.17" case 1'1 case end @@ -386608,21 +385747,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$14286 3'000 + assign $1\ren_delay$18$next[2:0]$14214 3'000 case - assign $1\ren_delay$18$next[2:0]$14286 \src3__ren + assign $1\ren_delay$18$next[2:0]$14214 \src3__ren end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14285 + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14213 end - attribute \src "libresoc.v:202704.3-202713.6" - process $proc$libresoc.v:202704$14287 + attribute \src "libresoc.v:202301.3-202310.6" + process $proc$libresoc.v:202301$14215 assign { } { } assign { } { } assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "libresoc.v:202705.5-202705.29" + attribute \src "libresoc.v:202302.5-202302.29" switch \initial - attribute \src "libresoc.v:202705.9-202705.17" + attribute \src "libresoc.v:202302.9-202302.17" case 1'1 case end @@ -386638,14 +385777,14 @@ module \xer sync always update \src3__data_o $0\src3__data_o[1:0] end - attribute \src "libresoc.v:202714.3-202722.6" - process $proc$libresoc.v:202714$14288 + attribute \src "libresoc.v:202311.3-202319.6" + process $proc$libresoc.v:202311$14216 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$14289 $1\ren_delay$next[2:0]$14290 - attribute \src "libresoc.v:202715.5-202715.29" + assign $0\ren_delay$next[2:0]$14217 $1\ren_delay$next[2:0]$14218 + attribute \src "libresoc.v:202312.5-202312.29" switch \initial - attribute \src "libresoc.v:202715.9-202715.17" + attribute \src "libresoc.v:202312.9-202312.17" case 1'1 case end @@ -386654,21 +385793,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$14290 3'000 + assign $1\ren_delay$next[2:0]$14218 3'000 case - assign $1\ren_delay$next[2:0]$14290 \src1__ren + assign $1\ren_delay$next[2:0]$14218 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$14289 + update \ren_delay$next $0\ren_delay$next[2:0]$14217 end - attribute \src "libresoc.v:202723.3-202732.6" - process $proc$libresoc.v:202723$14291 + attribute \src "libresoc.v:202320.3-202329.6" + process $proc$libresoc.v:202320$14219 assign { } { } assign { } { } assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "libresoc.v:202724.5-202724.29" + attribute \src "libresoc.v:202321.5-202321.29" switch \initial - attribute \src "libresoc.v:202724.9-202724.17" + attribute \src "libresoc.v:202321.9-202321.17" case 1'1 case end @@ -386684,14 +385823,14 @@ module \xer sync always update \src1__data_o $0\src1__data_o[1:0] end - attribute \src "libresoc.v:202733.3-202741.6" - process $proc$libresoc.v:202733$14292 + attribute \src "libresoc.v:202330.3-202338.6" + process $proc$libresoc.v:202330$14220 assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$14293 $1\ren_delay$11$next[2:0]$14294 - attribute \src "libresoc.v:202734.5-202734.29" + assign $0\ren_delay$11$next[2:0]$14221 $1\ren_delay$11$next[2:0]$14222 + attribute \src "libresoc.v:202331.5-202331.29" switch \initial - attribute \src "libresoc.v:202734.9-202734.17" + attribute \src "libresoc.v:202331.9-202331.17" case 1'1 case end @@ -386700,21 +385839,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$14294 3'000 + assign $1\ren_delay$11$next[2:0]$14222 3'000 case - assign $1\ren_delay$11$next[2:0]$14294 \src2__ren + assign $1\ren_delay$11$next[2:0]$14222 \src2__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14293 + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14221 end - attribute \src "libresoc.v:202742.3-202751.6" - process $proc$libresoc.v:202742$14295 + attribute \src "libresoc.v:202339.3-202348.6" + process $proc$libresoc.v:202339$14223 assign { } { } assign { } { } assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "libresoc.v:202743.5-202743.29" + attribute \src "libresoc.v:202340.5-202340.29" switch \initial - attribute \src "libresoc.v:202743.9-202743.17" + attribute \src "libresoc.v:202340.9-202340.17" case 1'1 case end @@ -386730,15 +385869,15 @@ module \xer sync always update \src2__data_o $0\src2__data_o[1:0] end - connect \$9 $or$libresoc.v:202620$14270_Y - connect \$12 $reduce_or$libresoc.v:202621$14271_Y - connect \$14 $or$libresoc.v:202622$14272_Y - connect \$16 $or$libresoc.v:202623$14273_Y - connect \$19 $reduce_or$libresoc.v:202624$14274_Y - connect \$21 $or$libresoc.v:202625$14275_Y - connect \$23 $or$libresoc.v:202626$14276_Y - connect \$5 $reduce_or$libresoc.v:202627$14277_Y - connect \$7 $or$libresoc.v:202628$14278_Y + connect \$9 $or$libresoc.v:202217$14198_Y + connect \$12 $reduce_or$libresoc.v:202218$14199_Y + connect \$14 $or$libresoc.v:202219$14200_Y + connect \$16 $or$libresoc.v:202220$14201_Y + connect \$19 $reduce_or$libresoc.v:202221$14202_Y + connect \$21 $or$libresoc.v:202222$14203_Y + connect \$23 $or$libresoc.v:202223$14204_Y + connect \$5 $reduce_or$libresoc.v:202224$14205_Y + connect \$7 $or$libresoc.v:202225$14206_Y connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 @@ -386761,153 +385900,153 @@ module \xer connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:202777.1-203094.10" +attribute \src "libresoc.v:202374.1-202691.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:202958.3-202986.6" + attribute \src "libresoc.v:202555.3-202583.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:203009.3-203017.6" - wire $0\core_irq_o$next[0:0]$14337 - attribute \src "libresoc.v:202897.3-202898.37" + attribute \src "libresoc.v:202606.3-202614.6" + wire $0\core_irq_o$next[0:0]$14265 + attribute \src "libresoc.v:202494.3-202495.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire width 8 $0\cppr$10[7:0]$14341 - attribute \src "libresoc.v:202911.3-202926.6" - wire width 8 $0\cppr$next[7:0]$14320 - attribute \src "libresoc.v:202901.3-202902.25" + attribute \src "libresoc.v:202625.3-202687.6" + wire width 8 $0\cppr$10[7:0]$14269 + attribute \src "libresoc.v:202508.3-202523.6" + wire width 8 $0\cppr$next[7:0]$14248 + attribute \src "libresoc.v:202498.3-202499.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:203018.3-203027.6" + attribute \src "libresoc.v:202615.3-202624.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:202778.7-202778.20" + attribute \src "libresoc.v:202375.7-202375.20" wire $0\initial[0:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire $0\irq$12[0:0]$14342 - attribute \src "libresoc.v:202911.3-202926.6" - wire $0\irq$next[0:0]$14321 - attribute \src "libresoc.v:202905.3-202906.23" + attribute \src "libresoc.v:202625.3-202687.6" + wire $0\irq$12[0:0]$14270 + attribute \src "libresoc.v:202508.3-202523.6" + wire $0\irq$next[0:0]$14249 + attribute \src "libresoc.v:202502.3-202503.23" wire $0\irq[0:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire width 8 $0\mfrr$11[7:0]$14343 - attribute \src "libresoc.v:202911.3-202926.6" - wire width 8 $0\mfrr$next[7:0]$14322 - attribute \src "libresoc.v:202903.3-202904.25" + attribute \src "libresoc.v:202625.3-202687.6" + wire width 8 $0\mfrr$11[7:0]$14271 + attribute \src "libresoc.v:202508.3-202523.6" + wire width 8 $0\mfrr$next[7:0]$14250 + attribute \src "libresoc.v:202500.3-202501.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:202997.3-203008.6" + attribute \src "libresoc.v:202594.3-202605.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:202987.3-202996.6" + attribute \src "libresoc.v:202584.3-202593.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire $0\wb_ack$14[0:0]$14344 - attribute \src "libresoc.v:202911.3-202926.6" - wire $0\wb_ack$next[0:0]$14323 - attribute \src "libresoc.v:202909.3-202910.29" + attribute \src "libresoc.v:202625.3-202687.6" + wire $0\wb_ack$14[0:0]$14272 + attribute \src "libresoc.v:202508.3-202523.6" + wire $0\wb_ack$next[0:0]$14251 + attribute \src "libresoc.v:202506.3-202507.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire width 32 $0\wb_rd_data$13[31:0]$14345 - attribute \src "libresoc.v:202911.3-202926.6" - wire width 32 $0\wb_rd_data$next[31:0]$14324 - attribute \src "libresoc.v:202907.3-202908.37" + attribute \src "libresoc.v:202625.3-202687.6" + wire width 32 $0\wb_rd_data$13[31:0]$14273 + attribute \src "libresoc.v:202508.3-202523.6" + wire width 32 $0\wb_rd_data$next[31:0]$14252 + attribute \src "libresoc.v:202504.3-202505.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:202927.3-202957.6" + attribute \src "libresoc.v:202524.3-202554.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire width 24 $0\xisr$9[23:0]$14346 - attribute \src "libresoc.v:202911.3-202926.6" - wire width 24 $0\xisr$next[23:0]$14325 - attribute \src "libresoc.v:202899.3-202900.25" + attribute \src "libresoc.v:202625.3-202687.6" + wire width 24 $0\xisr$9[23:0]$14274 + attribute \src "libresoc.v:202508.3-202523.6" + wire width 24 $0\xisr$next[23:0]$14253 + attribute \src "libresoc.v:202496.3-202497.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:202958.3-202986.6" + attribute \src "libresoc.v:202555.3-202583.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:203009.3-203017.6" - wire $1\core_irq_o$next[0:0]$14338 - attribute \src "libresoc.v:202807.7-202807.24" + attribute \src "libresoc.v:202606.3-202614.6" + wire $1\core_irq_o$next[0:0]$14266 + attribute \src "libresoc.v:202404.7-202404.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire width 8 $1\cppr$10[7:0]$14347 - attribute \src "libresoc.v:202911.3-202926.6" - wire width 8 $1\cppr$next[7:0]$14326 - attribute \src "libresoc.v:202811.13-202811.25" + attribute \src "libresoc.v:202625.3-202687.6" + wire width 8 $1\cppr$10[7:0]$14275 + attribute \src "libresoc.v:202508.3-202523.6" + wire width 8 $1\cppr$next[7:0]$14254 + attribute \src "libresoc.v:202408.13-202408.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:203018.3-203027.6" + attribute \src "libresoc.v:202615.3-202624.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire $1\irq$12[0:0]$14357 - attribute \src "libresoc.v:202911.3-202926.6" - wire $1\irq$next[0:0]$14327 - attribute \src "libresoc.v:202840.7-202840.17" + attribute \src "libresoc.v:202625.3-202687.6" + wire $1\irq$12[0:0]$14285 + attribute \src "libresoc.v:202508.3-202523.6" + wire $1\irq$next[0:0]$14255 + attribute \src "libresoc.v:202437.7-202437.17" wire $1\irq[0:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire width 8 $1\mfrr$11[7:0]$14348 - attribute \src "libresoc.v:202911.3-202926.6" - wire width 8 $1\mfrr$next[7:0]$14328 - attribute \src "libresoc.v:202848.13-202848.25" + attribute \src "libresoc.v:202625.3-202687.6" + wire width 8 $1\mfrr$11[7:0]$14276 + attribute \src "libresoc.v:202508.3-202523.6" + wire width 8 $1\mfrr$next[7:0]$14256 + attribute \src "libresoc.v:202445.13-202445.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:202997.3-203008.6" + attribute \src "libresoc.v:202594.3-202605.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:202987.3-202996.6" + attribute \src "libresoc.v:202584.3-202593.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire $1\wb_ack$14[0:0]$14349 - attribute \src "libresoc.v:202911.3-202926.6" - wire $1\wb_ack$next[0:0]$14329 - attribute \src "libresoc.v:202862.7-202862.20" + attribute \src "libresoc.v:202625.3-202687.6" + wire $1\wb_ack$14[0:0]$14277 + attribute \src "libresoc.v:202508.3-202523.6" + wire $1\wb_ack$next[0:0]$14257 + attribute \src "libresoc.v:202459.7-202459.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:202911.3-202926.6" - wire width 32 $1\wb_rd_data$next[31:0]$14330 - attribute \src "libresoc.v:202870.14-202870.32" + attribute \src "libresoc.v:202508.3-202523.6" + wire width 32 $1\wb_rd_data$next[31:0]$14258 + attribute \src "libresoc.v:202467.14-202467.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:202927.3-202957.6" + attribute \src "libresoc.v:202524.3-202554.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire width 24 $1\xisr$9[23:0]$14354 - attribute \src "libresoc.v:202911.3-202926.6" - wire width 24 $1\xisr$next[23:0]$14331 - attribute \src "libresoc.v:202880.14-202880.31" + attribute \src "libresoc.v:202625.3-202687.6" + wire width 24 $1\xisr$9[23:0]$14282 + attribute \src "libresoc.v:202508.3-202523.6" + wire width 24 $1\xisr$next[23:0]$14259 + attribute \src "libresoc.v:202477.14-202477.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:202958.3-202986.6" + attribute \src "libresoc.v:202555.3-202583.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire width 8 $2\cppr$10[7:0]$14350 - attribute \src "libresoc.v:203028.3-203090.6" - wire width 8 $2\mfrr$11[7:0]$14351 - attribute \src "libresoc.v:202927.3-202957.6" + attribute \src "libresoc.v:202625.3-202687.6" + wire width 8 $2\cppr$10[7:0]$14278 + attribute \src "libresoc.v:202625.3-202687.6" + wire width 8 $2\mfrr$11[7:0]$14279 + attribute \src "libresoc.v:202524.3-202554.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire width 24 $2\xisr$9[23:0]$14355 - attribute \src "libresoc.v:202958.3-202986.6" + attribute \src "libresoc.v:202625.3-202687.6" + wire width 24 $2\xisr$9[23:0]$14283 + attribute \src "libresoc.v:202555.3-202583.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire width 8 $3\cppr$10[7:0]$14352 - attribute \src "libresoc.v:203028.3-203090.6" - wire width 8 $3\mfrr$11[7:0]$14353 - attribute \src "libresoc.v:202927.3-202957.6" + attribute \src "libresoc.v:202625.3-202687.6" + wire width 8 $3\cppr$10[7:0]$14280 + attribute \src "libresoc.v:202625.3-202687.6" + wire width 8 $3\mfrr$11[7:0]$14281 + attribute \src "libresoc.v:202524.3-202554.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:203028.3-203090.6" - wire width 8 $4\cppr$10[7:0]$14356 - attribute \src "libresoc.v:202927.3-202957.6" + attribute \src "libresoc.v:202625.3-202687.6" + wire width 8 $4\cppr$10[7:0]$14284 + attribute \src "libresoc.v:202524.3-202554.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202887.18-202887.116" - wire $and$libresoc.v:202887$14302_Y - attribute \src "libresoc.v:202891.18-202891.116" - wire $and$libresoc.v:202891$14306_Y - attribute \src "libresoc.v:202893.18-202893.116" - wire $and$libresoc.v:202893$14308_Y - attribute \src "libresoc.v:202896.17-202896.109" - wire $and$libresoc.v:202896$14311_Y - attribute \src "libresoc.v:202892.18-202892.110" - wire $eq$libresoc.v:202892$14307_Y - attribute \src "libresoc.v:202889.18-202889.114" - wire $lt$libresoc.v:202889$14304_Y - attribute \src "libresoc.v:202890.18-202890.109" - wire $lt$libresoc.v:202890$14305_Y - attribute \src "libresoc.v:202895.18-202895.114" - wire $lt$libresoc.v:202895$14310_Y - attribute \src "libresoc.v:202888.18-202888.109" - wire $ne$libresoc.v:202888$14303_Y - attribute \src "libresoc.v:202894.18-202894.109" - wire $ne$libresoc.v:202894$14309_Y + attribute \src "libresoc.v:202484.18-202484.116" + wire $and$libresoc.v:202484$14230_Y + attribute \src "libresoc.v:202488.18-202488.116" + wire $and$libresoc.v:202488$14234_Y + attribute \src "libresoc.v:202490.18-202490.116" + wire $and$libresoc.v:202490$14236_Y + attribute \src "libresoc.v:202493.17-202493.109" + wire $and$libresoc.v:202493$14239_Y + attribute \src "libresoc.v:202489.18-202489.110" + wire $eq$libresoc.v:202489$14235_Y + attribute \src "libresoc.v:202486.18-202486.114" + wire $lt$libresoc.v:202486$14232_Y + attribute \src "libresoc.v:202487.18-202487.109" + wire $lt$libresoc.v:202487$14233_Y + attribute \src "libresoc.v:202492.18-202492.114" + wire $lt$libresoc.v:202492$14238_Y + attribute \src "libresoc.v:202485.18-202485.109" + wire $ne$libresoc.v:202485$14231_Y + attribute \src "libresoc.v:202491.18-202491.109" + wire $ne$libresoc.v:202491$14237_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -386932,10 +386071,10 @@ module \xics_icp wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 13 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" - wire output 4 \core_irq_o + wire output 3 \core_irq_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \core_irq_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" @@ -386963,10 +386102,10 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 10 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 input 3 \ics_i_pri + wire width 8 input 2 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 input 2 \ics_i_src - attribute \src "libresoc.v:202778.7-202778.15" + wire width 4 input 1 \ics_i_src + attribute \src "libresoc.v:202375.7-202375.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -386988,8 +386127,8 @@ module \xics_icp wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" - wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" + wire input 4 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" @@ -387017,7 +386156,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:202887$14302 + cell $and $and$libresoc.v:202484$14230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387025,10 +386164,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:202887$14302_Y + connect \Y $and$libresoc.v:202484$14230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:202891$14306 + cell $and $and$libresoc.v:202488$14234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387036,10 +386175,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:202891$14306_Y + connect \Y $and$libresoc.v:202488$14234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:202893$14308 + cell $and $and$libresoc.v:202490$14236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387047,10 +386186,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:202893$14308_Y + connect \Y $and$libresoc.v:202490$14236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:202896$14311 + cell $and $and$libresoc.v:202493$14239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387058,10 +386197,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:202896$14311_Y + connect \Y $and$libresoc.v:202493$14239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:202892$14307 + cell $eq $eq$libresoc.v:202489$14235 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -387069,10 +386208,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:202892$14307_Y + connect \Y $eq$libresoc.v:202489$14235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:202889$14304 + cell $lt $lt$libresoc.v:202486$14232 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -387080,10 +386219,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:202889$14304_Y + connect \Y $lt$libresoc.v:202486$14232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:202890$14305 + cell $lt $lt$libresoc.v:202487$14233 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -387091,10 +386230,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:202890$14305_Y + connect \Y $lt$libresoc.v:202487$14233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:202895$14310 + cell $lt $lt$libresoc.v:202492$14238 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -387102,10 +386241,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:202895$14310_Y + connect \Y $lt$libresoc.v:202492$14238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:202888$14303 + cell $ne $ne$libresoc.v:202485$14231 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -387113,10 +386252,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:202888$14303_Y + connect \Y $ne$libresoc.v:202485$14231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:202894$14309 + cell $ne $ne$libresoc.v:202491$14237 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -387124,123 +386263,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:202894$14309_Y + connect \Y $ne$libresoc.v:202491$14237_Y end - attribute \src "libresoc.v:202778.7-202778.20" - process $proc$libresoc.v:202778$14358 + attribute \src "libresoc.v:202375.7-202375.20" + process $proc$libresoc.v:202375$14286 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:202807.7-202807.24" - process $proc$libresoc.v:202807$14359 + attribute \src "libresoc.v:202404.7-202404.24" + process $proc$libresoc.v:202404$14287 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:202811.13-202811.25" - process $proc$libresoc.v:202811$14360 + attribute \src "libresoc.v:202408.13-202408.25" + process $proc$libresoc.v:202408$14288 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:202840.7-202840.17" - process $proc$libresoc.v:202840$14361 + attribute \src "libresoc.v:202437.7-202437.17" + process $proc$libresoc.v:202437$14289 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:202848.13-202848.25" - process $proc$libresoc.v:202848$14362 + attribute \src "libresoc.v:202445.13-202445.25" + process $proc$libresoc.v:202445$14290 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:202862.7-202862.20" - process $proc$libresoc.v:202862$14363 + attribute \src "libresoc.v:202459.7-202459.20" + process $proc$libresoc.v:202459$14291 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:202870.14-202870.32" - process $proc$libresoc.v:202870$14364 + attribute \src "libresoc.v:202467.14-202467.32" + process $proc$libresoc.v:202467$14292 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:202880.14-202880.31" - process $proc$libresoc.v:202880$14365 + attribute \src "libresoc.v:202477.14-202477.31" + process $proc$libresoc.v:202477$14293 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:202897.3-202898.37" - process $proc$libresoc.v:202897$14312 + attribute \src "libresoc.v:202494.3-202495.37" + process $proc$libresoc.v:202494$14240 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:202899.3-202900.25" - process $proc$libresoc.v:202899$14313 + attribute \src "libresoc.v:202496.3-202497.25" + process $proc$libresoc.v:202496$14241 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:202901.3-202902.25" - process $proc$libresoc.v:202901$14314 + attribute \src "libresoc.v:202498.3-202499.25" + process $proc$libresoc.v:202498$14242 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:202903.3-202904.25" - process $proc$libresoc.v:202903$14315 + attribute \src "libresoc.v:202500.3-202501.25" + process $proc$libresoc.v:202500$14243 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:202905.3-202906.23" - process $proc$libresoc.v:202905$14316 + attribute \src "libresoc.v:202502.3-202503.23" + process $proc$libresoc.v:202502$14244 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:202907.3-202908.37" - process $proc$libresoc.v:202907$14317 + attribute \src "libresoc.v:202504.3-202505.37" + process $proc$libresoc.v:202504$14245 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:202909.3-202910.29" - process $proc$libresoc.v:202909$14318 + attribute \src "libresoc.v:202506.3-202507.29" + process $proc$libresoc.v:202506$14246 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:202911.3-202926.6" - process $proc$libresoc.v:202911$14319 + attribute \src "libresoc.v:202508.3-202523.6" + process $proc$libresoc.v:202508$14247 assign { } { } assign { } { } assign { } { } @@ -387248,15 +386387,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$14320 $1\cppr$next[7:0]$14326 - assign $0\irq$next[0:0]$14321 $1\irq$next[0:0]$14327 - assign $0\mfrr$next[7:0]$14322 $1\mfrr$next[7:0]$14328 - assign $0\wb_ack$next[0:0]$14323 $1\wb_ack$next[0:0]$14329 - assign $0\wb_rd_data$next[31:0]$14324 $1\wb_rd_data$next[31:0]$14330 - assign $0\xisr$next[23:0]$14325 $1\xisr$next[23:0]$14331 - attribute \src "libresoc.v:202912.5-202912.29" + assign $0\cppr$next[7:0]$14248 $1\cppr$next[7:0]$14254 + assign $0\irq$next[0:0]$14249 $1\irq$next[0:0]$14255 + assign $0\mfrr$next[7:0]$14250 $1\mfrr$next[7:0]$14256 + assign $0\wb_ack$next[0:0]$14251 $1\wb_ack$next[0:0]$14257 + assign $0\wb_rd_data$next[31:0]$14252 $1\wb_rd_data$next[31:0]$14258 + assign $0\xisr$next[23:0]$14253 $1\xisr$next[23:0]$14259 + attribute \src "libresoc.v:202509.5-202509.29" switch \initial - attribute \src "libresoc.v:202912.9-202912.17" + attribute \src "libresoc.v:202509.9-202509.17" case 1'1 case end @@ -387270,36 +386409,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$14331 24'000000000000000000000000 - assign $1\cppr$next[7:0]$14326 8'00000000 - assign $1\mfrr$next[7:0]$14328 8'11111111 - assign $1\irq$next[0:0]$14327 1'0 - assign $1\wb_rd_data$next[31:0]$14330 0 - assign $1\wb_ack$next[0:0]$14329 1'0 + assign $1\xisr$next[23:0]$14259 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14254 8'00000000 + assign $1\mfrr$next[7:0]$14256 8'11111111 + assign $1\irq$next[0:0]$14255 1'0 + assign $1\wb_rd_data$next[31:0]$14258 0 + assign $1\wb_ack$next[0:0]$14257 1'0 case - assign $1\cppr$next[7:0]$14326 \cppr$2 - assign $1\irq$next[0:0]$14327 \irq$4 - assign $1\mfrr$next[7:0]$14328 \mfrr$3 - assign $1\wb_ack$next[0:0]$14329 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$14330 \wb_rd_data$5 - assign $1\xisr$next[23:0]$14331 \xisr$1 + assign $1\cppr$next[7:0]$14254 \cppr$2 + assign $1\irq$next[0:0]$14255 \irq$4 + assign $1\mfrr$next[7:0]$14256 \mfrr$3 + assign $1\wb_ack$next[0:0]$14257 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14258 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14259 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$14320 - update \irq$next $0\irq$next[0:0]$14321 - update \mfrr$next $0\mfrr$next[7:0]$14322 - update \wb_ack$next $0\wb_ack$next[0:0]$14323 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14324 - update \xisr$next $0\xisr$next[23:0]$14325 + update \cppr$next $0\cppr$next[7:0]$14248 + update \irq$next $0\irq$next[0:0]$14249 + update \mfrr$next $0\mfrr$next[7:0]$14250 + update \wb_ack$next $0\wb_ack$next[0:0]$14251 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14252 + update \xisr$next $0\xisr$next[23:0]$14253 end - attribute \src "libresoc.v:202927.3-202957.6" - process $proc$libresoc.v:202927$14332 + attribute \src "libresoc.v:202524.3-202554.6" + process $proc$libresoc.v:202524$14260 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202928.5-202928.29" + attribute \src "libresoc.v:202525.5-202525.29" switch \initial - attribute \src "libresoc.v:202928.9-202928.17" + attribute \src "libresoc.v:202525.9-202525.17" case 1'1 case end @@ -387346,14 +386485,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:202958.3-202986.6" - process $proc$libresoc.v:202958$14333 + attribute \src "libresoc.v:202555.3-202583.6" + process $proc$libresoc.v:202555$14261 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:202959.5-202959.29" + attribute \src "libresoc.v:202556.5-202556.29" switch \initial - attribute \src "libresoc.v:202959.9-202959.17" + attribute \src "libresoc.v:202556.9-202556.17" case 1'1 case end @@ -387396,14 +386535,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:202987.3-202996.6" - process $proc$libresoc.v:202987$14334 + attribute \src "libresoc.v:202584.3-202593.6" + process $proc$libresoc.v:202584$14262 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:202988.5-202988.29" + attribute \src "libresoc.v:202585.5-202585.29" switch \initial - attribute \src "libresoc.v:202988.9-202988.17" + attribute \src "libresoc.v:202585.9-202585.17" case 1'1 case end @@ -387419,13 +386558,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:202997.3-203008.6" - process $proc$libresoc.v:202997$14335 + attribute \src "libresoc.v:202594.3-202605.6" + process $proc$libresoc.v:202594$14263 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:202998.5-202998.29" + attribute \src "libresoc.v:202595.5-202595.29" switch \initial - attribute \src "libresoc.v:202998.9-202998.17" + attribute \src "libresoc.v:202595.9-202595.17" case 1'1 case end @@ -387443,14 +386582,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:203009.3-203017.6" - process $proc$libresoc.v:203009$14336 + attribute \src "libresoc.v:202606.3-202614.6" + process $proc$libresoc.v:202606$14264 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$14337 $1\core_irq_o$next[0:0]$14338 - attribute \src "libresoc.v:203010.5-203010.29" + assign $0\core_irq_o$next[0:0]$14265 $1\core_irq_o$next[0:0]$14266 + attribute \src "libresoc.v:202607.5-202607.29" switch \initial - attribute \src "libresoc.v:203010.9-203010.17" + attribute \src "libresoc.v:202607.9-202607.17" case 1'1 case end @@ -387459,21 +386598,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$14338 1'0 + assign $1\core_irq_o$next[0:0]$14266 1'0 case - assign $1\core_irq_o$next[0:0]$14338 \irq + assign $1\core_irq_o$next[0:0]$14266 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$14337 + update \core_irq_o$next $0\core_irq_o$next[0:0]$14265 end - attribute \src "libresoc.v:203018.3-203027.6" - process $proc$libresoc.v:203018$14339 + attribute \src "libresoc.v:202615.3-202624.6" + process $proc$libresoc.v:202615$14267 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:203019.5-203019.29" + attribute \src "libresoc.v:202616.5-202616.29" switch \initial - attribute \src "libresoc.v:203019.9-203019.17" + attribute \src "libresoc.v:202616.9-202616.17" case 1'1 case end @@ -387489,8 +386628,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:203028.3-203090.6" - process $proc$libresoc.v:203028$14340 + attribute \src "libresoc.v:202625.3-202687.6" + process $proc$libresoc.v:202625$14268 assign { } { } assign { } { } assign { } { } @@ -387500,18 +386639,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$14343 $1\mfrr$11[7:0]$14348 - assign $0\wb_ack$14[0:0]$14344 $1\wb_ack$14[0:0]$14349 + assign $0\mfrr$11[7:0]$14271 $1\mfrr$11[7:0]$14276 + assign $0\wb_ack$14[0:0]$14272 $1\wb_ack$14[0:0]$14277 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$14346 $2\xisr$9[23:0]$14355 - assign $0\cppr$10[7:0]$14341 $4\cppr$10[7:0]$14356 - assign $0\wb_rd_data$13[31:0]$14345 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$14342 $1\irq$12[0:0]$14357 - attribute \src "libresoc.v:203029.5-203029.29" + assign $0\xisr$9[23:0]$14274 $2\xisr$9[23:0]$14283 + assign $0\cppr$10[7:0]$14269 $4\cppr$10[7:0]$14284 + assign $0\wb_rd_data$13[31:0]$14273 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14270 $1\irq$12[0:0]$14285 + attribute \src "libresoc.v:202626.5-202626.29" switch \initial - attribute \src "libresoc.v:203029.9-203029.17" + attribute \src "libresoc.v:202626.9-202626.17" case 1'1 case end @@ -387522,712 +386661,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$14349 1'1 - assign $1\cppr$10[7:0]$14347 $2\cppr$10[7:0]$14350 - assign $1\mfrr$11[7:0]$14348 $2\mfrr$11[7:0]$14351 + assign $1\wb_ack$14[0:0]$14277 1'1 + assign $1\cppr$10[7:0]$14275 $2\cppr$10[7:0]$14278 + assign $1\mfrr$11[7:0]$14276 $2\mfrr$11[7:0]$14279 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$14350 $3\cppr$10[7:0]$14352 - assign $2\mfrr$11[7:0]$14351 $3\mfrr$11[7:0]$14353 + assign $2\cppr$10[7:0]$14278 $3\cppr$10[7:0]$14280 + assign $2\mfrr$11[7:0]$14279 $3\mfrr$11[7:0]$14281 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$14353 \mfrr - assign $3\cppr$10[7:0]$14352 \be_in [31:24] + assign $3\mfrr$11[7:0]$14281 \mfrr + assign $3\cppr$10[7:0]$14280 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$14353 \mfrr - assign $3\cppr$10[7:0]$14352 \be_in [31:24] + assign $3\mfrr$11[7:0]$14281 \mfrr + assign $3\cppr$10[7:0]$14280 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$14352 \cppr + assign $3\cppr$10[7:0]$14280 \cppr assign { } { } - assign $3\mfrr$11[7:0]$14353 \be_in [31:24] + assign $3\mfrr$11[7:0]$14281 \be_in [31:24] case - assign $3\cppr$10[7:0]$14352 \cppr - assign $3\mfrr$11[7:0]$14353 \mfrr + assign $3\cppr$10[7:0]$14280 \cppr + assign $3\mfrr$11[7:0]$14281 \mfrr end case - assign $2\cppr$10[7:0]$14350 \cppr - assign $2\mfrr$11[7:0]$14351 \mfrr + assign $2\cppr$10[7:0]$14278 \cppr + assign $2\mfrr$11[7:0]$14279 \mfrr end case - assign $1\cppr$10[7:0]$14347 \cppr - assign $1\mfrr$11[7:0]$14348 \mfrr - assign $1\wb_ack$14[0:0]$14349 1'0 + assign $1\cppr$10[7:0]$14275 \cppr + assign $1\mfrr$11[7:0]$14276 \mfrr + assign $1\wb_ack$14[0:0]$14277 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$14354 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$14282 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$14354 24'000000000000000000000000 + assign $1\xisr$9[23:0]$14282 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$14355 24'000000000000000000000010 + assign $2\xisr$9[23:0]$14283 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$14355 $1\xisr$9[23:0]$14354 + assign $2\xisr$9[23:0]$14283 $1\xisr$9[23:0]$14282 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$14356 \min_pri + assign $4\cppr$10[7:0]$14284 \min_pri case - assign $4\cppr$10[7:0]$14356 $1\cppr$10[7:0]$14347 + assign $4\cppr$10[7:0]$14284 $1\cppr$10[7:0]$14275 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$14357 1'1 + assign $1\irq$12[0:0]$14285 1'1 case - assign $1\irq$12[0:0]$14357 1'0 + assign $1\irq$12[0:0]$14285 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$14341 - update \irq$12 $0\irq$12[0:0]$14342 - update \mfrr$11 $0\mfrr$11[7:0]$14343 - update \wb_ack$14 $0\wb_ack$14[0:0]$14344 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14345 - update \xisr$9 $0\xisr$9[23:0]$14346 + update \cppr$10 $0\cppr$10[7:0]$14269 + update \irq$12 $0\irq$12[0:0]$14270 + update \mfrr$11 $0\mfrr$11[7:0]$14271 + update \wb_ack$14 $0\wb_ack$14[0:0]$14272 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14273 + update \xisr$9 $0\xisr$9[23:0]$14274 end - connect \$15 $and$libresoc.v:202887$14302_Y - connect \$17 $ne$libresoc.v:202888$14303_Y - connect \$19 $lt$libresoc.v:202889$14304_Y - connect \$21 $lt$libresoc.v:202890$14305_Y - connect \$23 $and$libresoc.v:202891$14306_Y - connect \$25 $eq$libresoc.v:202892$14307_Y - connect \$27 $and$libresoc.v:202893$14308_Y - connect \$29 $ne$libresoc.v:202894$14309_Y - connect \$31 $lt$libresoc.v:202895$14310_Y - connect \$7 $and$libresoc.v:202896$14311_Y + connect \$15 $and$libresoc.v:202484$14230_Y + connect \$17 $ne$libresoc.v:202485$14231_Y + connect \$19 $lt$libresoc.v:202486$14232_Y + connect \$21 $lt$libresoc.v:202487$14233_Y + connect \$23 $and$libresoc.v:202488$14234_Y + connect \$25 $eq$libresoc.v:202489$14235_Y + connect \$27 $and$libresoc.v:202490$14236_Y + connect \$29 $ne$libresoc.v:202491$14237_Y + connect \$31 $lt$libresoc.v:202492$14238_Y + connect \$7 $and$libresoc.v:202493$14239_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:203098.1-204147.10" +attribute \src "libresoc.v:202695.1-203744.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:204028.3-204077.6" + attribute \src "libresoc.v:203625.3-203674.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:203739.3-203748.6" + attribute \src "libresoc.v:203336.3-203345.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:203948.3-203957.6" + attribute \src "libresoc.v:203545.3-203554.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:203968.3-203977.6" + attribute \src "libresoc.v:203565.3-203574.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:203988.3-203997.6" + attribute \src "libresoc.v:203585.3-203594.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:204008.3-204017.6" + attribute \src "libresoc.v:203605.3-203614.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:204078.3-204087.6" + attribute \src "libresoc.v:203675.3-203684.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:204098.3-204107.6" + attribute \src "libresoc.v:203695.3-203704.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:203759.3-203768.6" + attribute \src "libresoc.v:203356.3-203365.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:203779.3-203788.6" + attribute \src "libresoc.v:203376.3-203385.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:203799.3-203808.6" + attribute \src "libresoc.v:203396.3-203405.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:203828.3-203837.6" + attribute \src "libresoc.v:203425.3-203434.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:203848.3-203857.6" + attribute \src "libresoc.v:203445.3-203454.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:203868.3-203877.6" + attribute \src "libresoc.v:203465.3-203474.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:203888.3-203897.6" + attribute \src "libresoc.v:203485.3-203494.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:203908.3-203917.6" + attribute \src "libresoc.v:203505.3-203514.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:203928.3-203937.6" + attribute \src "libresoc.v:203525.3-203534.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:203729.3-203738.6" + attribute \src "libresoc.v:203326.3-203335.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:203938.3-203947.6" + attribute \src "libresoc.v:203535.3-203544.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:203958.3-203967.6" + attribute \src "libresoc.v:203555.3-203564.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:203978.3-203987.6" + attribute \src "libresoc.v:203575.3-203584.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:203998.3-204007.6" + attribute \src "libresoc.v:203595.3-203604.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:204018.3-204027.6" + attribute \src "libresoc.v:203615.3-203624.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:204088.3-204097.6" + attribute \src "libresoc.v:203685.3-203694.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:203749.3-203758.6" + attribute \src "libresoc.v:203346.3-203355.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:203769.3-203778.6" + attribute \src "libresoc.v:203366.3-203375.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:203789.3-203798.6" + attribute \src "libresoc.v:203386.3-203395.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:203809.3-203818.6" + attribute \src "libresoc.v:203406.3-203415.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:203838.3-203847.6" + attribute \src "libresoc.v:203435.3-203444.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:203858.3-203867.6" + attribute \src "libresoc.v:203455.3-203464.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:203878.3-203887.6" + attribute \src "libresoc.v:203475.3-203484.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:203898.3-203907.6" + attribute \src "libresoc.v:203495.3-203504.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:203918.3-203927.6" + attribute \src "libresoc.v:203515.3-203524.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:204108.3-204117.6" + attribute \src "libresoc.v:203705.3-203714.6" wire $0\ibit[0:0] - attribute \src "libresoc.v:203603.3-203604.25" + attribute \src "libresoc.v:203200.3-203201.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:203601.3-203602.28" + attribute \src "libresoc.v:203198.3-203199.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:204127.3-204135.6" - wire $0\ics_wb__ack$next[0:0]$14612 - attribute \src "libresoc.v:203637.3-203638.39" + attribute \src "libresoc.v:203724.3-203732.6" + wire $0\ics_wb__ack$next[0:0]$14540 + attribute \src "libresoc.v:203234.3-203235.39" wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:204118.3-204126.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$14609 - attribute \src "libresoc.v:203639.3-203640.43" + attribute \src "libresoc.v:203715.3-203723.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$14537 + attribute \src "libresoc.v:203236.3-203237.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:203099.7-203099.20" + attribute \src "libresoc.v:202696.7-202696.20" wire $0\initial[0:0] - attribute \src "libresoc.v:203819.3-203827.6" - wire width 16 $0\int_level_l$next[15:0]$14581 - attribute \src "libresoc.v:203641.3-203642.39" + attribute \src "libresoc.v:203416.3-203424.6" + wire width 16 $0\int_level_l$next[15:0]$14509 + attribute \src "libresoc.v:203238.3-203239.39" wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive0_pri$next[7:0]$14491 - attribute \src "libresoc.v:203605.3-203606.35" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive0_pri$next[7:0]$14419 + attribute \src "libresoc.v:203202.3-203203.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive10_pri$next[7:0]$14492 - attribute \src "libresoc.v:203625.3-203626.37" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive10_pri$next[7:0]$14420 + attribute \src "libresoc.v:203222.3-203223.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive11_pri$next[7:0]$14493 - attribute \src "libresoc.v:203627.3-203628.37" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive11_pri$next[7:0]$14421 + attribute \src "libresoc.v:203224.3-203225.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive12_pri$next[7:0]$14494 - attribute \src "libresoc.v:203629.3-203630.37" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive12_pri$next[7:0]$14422 + attribute \src "libresoc.v:203226.3-203227.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive13_pri$next[7:0]$14495 - attribute \src "libresoc.v:203631.3-203632.37" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive13_pri$next[7:0]$14423 + attribute \src "libresoc.v:203228.3-203229.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive14_pri$next[7:0]$14496 - attribute \src "libresoc.v:203633.3-203634.37" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive14_pri$next[7:0]$14424 + attribute \src "libresoc.v:203230.3-203231.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive15_pri$next[7:0]$14497 - attribute \src "libresoc.v:203635.3-203636.37" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive15_pri$next[7:0]$14425 + attribute \src "libresoc.v:203232.3-203233.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive1_pri$next[7:0]$14498 - attribute \src "libresoc.v:203607.3-203608.35" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive1_pri$next[7:0]$14426 + attribute \src "libresoc.v:203204.3-203205.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive2_pri$next[7:0]$14499 - attribute \src "libresoc.v:203609.3-203610.35" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive2_pri$next[7:0]$14427 + attribute \src "libresoc.v:203206.3-203207.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive3_pri$next[7:0]$14500 - attribute \src "libresoc.v:203611.3-203612.35" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive3_pri$next[7:0]$14428 + attribute \src "libresoc.v:203208.3-203209.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive4_pri$next[7:0]$14501 - attribute \src "libresoc.v:203613.3-203614.35" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive4_pri$next[7:0]$14429 + attribute \src "libresoc.v:203210.3-203211.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive5_pri$next[7:0]$14502 - attribute \src "libresoc.v:203615.3-203616.35" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive5_pri$next[7:0]$14430 + attribute \src "libresoc.v:203212.3-203213.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive6_pri$next[7:0]$14503 - attribute \src "libresoc.v:203617.3-203618.35" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive6_pri$next[7:0]$14431 + attribute \src "libresoc.v:203214.3-203215.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive7_pri$next[7:0]$14504 - attribute \src "libresoc.v:203619.3-203620.35" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive7_pri$next[7:0]$14432 + attribute \src "libresoc.v:203216.3-203217.35" wire width 8 $0\xive7_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive8_pri$next[7:0]$14505 - attribute \src "libresoc.v:203621.3-203622.35" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive8_pri$next[7:0]$14433 + attribute \src "libresoc.v:203218.3-203219.35" wire width 8 $0\xive8_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $0\xive9_pri$next[7:0]$14506 - attribute \src "libresoc.v:203623.3-203624.35" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $0\xive9_pri$next[7:0]$14434 + attribute \src "libresoc.v:203220.3-203221.35" wire width 8 $0\xive9_pri[7:0] - attribute \src "libresoc.v:204028.3-204077.6" + attribute \src "libresoc.v:203625.3-203674.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:203739.3-203748.6" + attribute \src "libresoc.v:203336.3-203345.6" wire width 4 $1\cur_idx0[3:0] - attribute \src "libresoc.v:203948.3-203957.6" + attribute \src "libresoc.v:203545.3-203554.6" wire width 4 $1\cur_idx10[3:0] - attribute \src "libresoc.v:203968.3-203977.6" + attribute \src "libresoc.v:203565.3-203574.6" wire width 4 $1\cur_idx11[3:0] - attribute \src "libresoc.v:203988.3-203997.6" + attribute \src "libresoc.v:203585.3-203594.6" wire width 4 $1\cur_idx12[3:0] - attribute \src "libresoc.v:204008.3-204017.6" + attribute \src "libresoc.v:203605.3-203614.6" wire width 4 $1\cur_idx13[3:0] - attribute \src "libresoc.v:204078.3-204087.6" + attribute \src "libresoc.v:203675.3-203684.6" wire width 4 $1\cur_idx14[3:0] - attribute \src "libresoc.v:204098.3-204107.6" + attribute \src "libresoc.v:203695.3-203704.6" wire width 4 $1\cur_idx15[3:0] - attribute \src "libresoc.v:203759.3-203768.6" + attribute \src "libresoc.v:203356.3-203365.6" wire width 4 $1\cur_idx1[3:0] - attribute \src "libresoc.v:203779.3-203788.6" + attribute \src "libresoc.v:203376.3-203385.6" wire width 4 $1\cur_idx2[3:0] - attribute \src "libresoc.v:203799.3-203808.6" + attribute \src "libresoc.v:203396.3-203405.6" wire width 4 $1\cur_idx3[3:0] - attribute \src "libresoc.v:203828.3-203837.6" + attribute \src "libresoc.v:203425.3-203434.6" wire width 4 $1\cur_idx4[3:0] - attribute \src "libresoc.v:203848.3-203857.6" + attribute \src "libresoc.v:203445.3-203454.6" wire width 4 $1\cur_idx5[3:0] - attribute \src "libresoc.v:203868.3-203877.6" + attribute \src "libresoc.v:203465.3-203474.6" wire width 4 $1\cur_idx6[3:0] - attribute \src "libresoc.v:203888.3-203897.6" + attribute \src "libresoc.v:203485.3-203494.6" wire width 4 $1\cur_idx7[3:0] - attribute \src "libresoc.v:203908.3-203917.6" + attribute \src "libresoc.v:203505.3-203514.6" wire width 4 $1\cur_idx8[3:0] - attribute \src "libresoc.v:203928.3-203937.6" + attribute \src "libresoc.v:203525.3-203534.6" wire width 4 $1\cur_idx9[3:0] - attribute \src "libresoc.v:203729.3-203738.6" + attribute \src "libresoc.v:203326.3-203335.6" wire width 8 $1\cur_pri0[7:0] - attribute \src "libresoc.v:203938.3-203947.6" + attribute \src "libresoc.v:203535.3-203544.6" wire width 8 $1\cur_pri10[7:0] - attribute \src "libresoc.v:203958.3-203967.6" + attribute \src "libresoc.v:203555.3-203564.6" wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:203978.3-203987.6" + attribute \src "libresoc.v:203575.3-203584.6" wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:203998.3-204007.6" + attribute \src "libresoc.v:203595.3-203604.6" wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:204018.3-204027.6" + attribute \src "libresoc.v:203615.3-203624.6" wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:204088.3-204097.6" + attribute \src "libresoc.v:203685.3-203694.6" wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:203749.3-203758.6" + attribute \src "libresoc.v:203346.3-203355.6" wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:203769.3-203778.6" + attribute \src "libresoc.v:203366.3-203375.6" wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:203789.3-203798.6" + attribute \src "libresoc.v:203386.3-203395.6" wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:203809.3-203818.6" + attribute \src "libresoc.v:203406.3-203415.6" wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:203838.3-203847.6" + attribute \src "libresoc.v:203435.3-203444.6" wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:203858.3-203867.6" + attribute \src "libresoc.v:203455.3-203464.6" wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:203878.3-203887.6" + attribute \src "libresoc.v:203475.3-203484.6" wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:203898.3-203907.6" + attribute \src "libresoc.v:203495.3-203504.6" wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:203918.3-203927.6" + attribute \src "libresoc.v:203515.3-203524.6" wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:204108.3-204117.6" + attribute \src "libresoc.v:203705.3-203714.6" wire $1\ibit[0:0] - attribute \src "libresoc.v:203380.13-203380.30" + attribute \src "libresoc.v:202977.13-202977.30" wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:203385.13-203385.29" + attribute \src "libresoc.v:202982.13-202982.29" wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:204127.3-204135.6" - wire $1\ics_wb__ack$next[0:0]$14613 - attribute \src "libresoc.v:203394.7-203394.25" + attribute \src "libresoc.v:203724.3-203732.6" + wire $1\ics_wb__ack$next[0:0]$14541 + attribute \src "libresoc.v:202991.7-202991.25" wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:204118.3-204126.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$14610 - attribute \src "libresoc.v:203403.14-203403.35" + attribute \src "libresoc.v:203715.3-203723.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$14538 + attribute \src "libresoc.v:203000.14-203000.35" wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:203819.3-203827.6" - wire width 16 $1\int_level_l$next[15:0]$14582 - attribute \src "libresoc.v:203415.14-203415.36" + attribute \src "libresoc.v:203416.3-203424.6" + wire width 16 $1\int_level_l$next[15:0]$14510 + attribute \src "libresoc.v:203012.14-203012.36" wire width 16 $1\int_level_l[15:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive0_pri$next[7:0]$14507 - attribute \src "libresoc.v:203435.13-203435.30" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive0_pri$next[7:0]$14435 + attribute \src "libresoc.v:203032.13-203032.30" wire width 8 $1\xive0_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive10_pri$next[7:0]$14508 - attribute \src "libresoc.v:203439.13-203439.31" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive10_pri$next[7:0]$14436 + attribute \src "libresoc.v:203036.13-203036.31" wire width 8 $1\xive10_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive11_pri$next[7:0]$14509 - attribute \src "libresoc.v:203443.13-203443.31" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive11_pri$next[7:0]$14437 + attribute \src "libresoc.v:203040.13-203040.31" wire width 8 $1\xive11_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive12_pri$next[7:0]$14510 - attribute \src "libresoc.v:203447.13-203447.31" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive12_pri$next[7:0]$14438 + attribute \src "libresoc.v:203044.13-203044.31" wire width 8 $1\xive12_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive13_pri$next[7:0]$14511 - attribute \src "libresoc.v:203451.13-203451.31" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive13_pri$next[7:0]$14439 + attribute \src "libresoc.v:203048.13-203048.31" wire width 8 $1\xive13_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive14_pri$next[7:0]$14512 - attribute \src "libresoc.v:203455.13-203455.31" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive14_pri$next[7:0]$14440 + attribute \src "libresoc.v:203052.13-203052.31" wire width 8 $1\xive14_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive15_pri$next[7:0]$14513 - attribute \src "libresoc.v:203459.13-203459.31" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive15_pri$next[7:0]$14441 + attribute \src "libresoc.v:203056.13-203056.31" wire width 8 $1\xive15_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive1_pri$next[7:0]$14514 - attribute \src "libresoc.v:203463.13-203463.30" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive1_pri$next[7:0]$14442 + attribute \src "libresoc.v:203060.13-203060.30" wire width 8 $1\xive1_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive2_pri$next[7:0]$14515 - attribute \src "libresoc.v:203467.13-203467.30" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive2_pri$next[7:0]$14443 + attribute \src "libresoc.v:203064.13-203064.30" wire width 8 $1\xive2_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive3_pri$next[7:0]$14516 - attribute \src "libresoc.v:203471.13-203471.30" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive3_pri$next[7:0]$14444 + attribute \src "libresoc.v:203068.13-203068.30" wire width 8 $1\xive3_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive4_pri$next[7:0]$14517 - attribute \src "libresoc.v:203475.13-203475.30" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive4_pri$next[7:0]$14445 + attribute \src "libresoc.v:203072.13-203072.30" wire width 8 $1\xive4_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive5_pri$next[7:0]$14518 - attribute \src "libresoc.v:203479.13-203479.30" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive5_pri$next[7:0]$14446 + attribute \src "libresoc.v:203076.13-203076.30" wire width 8 $1\xive5_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive6_pri$next[7:0]$14519 - attribute \src "libresoc.v:203483.13-203483.30" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive6_pri$next[7:0]$14447 + attribute \src "libresoc.v:203080.13-203080.30" wire width 8 $1\xive6_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive7_pri$next[7:0]$14520 - attribute \src "libresoc.v:203487.13-203487.30" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive7_pri$next[7:0]$14448 + attribute \src "libresoc.v:203084.13-203084.30" wire width 8 $1\xive7_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive8_pri$next[7:0]$14521 - attribute \src "libresoc.v:203491.13-203491.30" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive8_pri$next[7:0]$14449 + attribute \src "libresoc.v:203088.13-203088.30" wire width 8 $1\xive8_pri[7:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $1\xive9_pri$next[7:0]$14522 - attribute \src "libresoc.v:203495.13-203495.30" + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $1\xive9_pri$next[7:0]$14450 + attribute \src "libresoc.v:203092.13-203092.30" wire width 8 $1\xive9_pri[7:0] - attribute \src "libresoc.v:204028.3-204077.6" + attribute \src "libresoc.v:203625.3-203674.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive0_pri$next[7:0]$14523 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive10_pri$next[7:0]$14524 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive11_pri$next[7:0]$14525 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive12_pri$next[7:0]$14526 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive13_pri$next[7:0]$14527 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive14_pri$next[7:0]$14528 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive15_pri$next[7:0]$14529 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive1_pri$next[7:0]$14530 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive2_pri$next[7:0]$14531 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive3_pri$next[7:0]$14532 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive4_pri$next[7:0]$14533 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive5_pri$next[7:0]$14534 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive6_pri$next[7:0]$14535 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive7_pri$next[7:0]$14536 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive8_pri$next[7:0]$14537 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $2\xive9_pri$next[7:0]$14538 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive0_pri$next[7:0]$14539 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive10_pri$next[7:0]$14540 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive11_pri$next[7:0]$14541 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive12_pri$next[7:0]$14542 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive13_pri$next[7:0]$14543 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive14_pri$next[7:0]$14544 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive15_pri$next[7:0]$14545 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive1_pri$next[7:0]$14546 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive2_pri$next[7:0]$14547 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive3_pri$next[7:0]$14548 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive4_pri$next[7:0]$14549 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive5_pri$next[7:0]$14550 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive6_pri$next[7:0]$14551 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive7_pri$next[7:0]$14552 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive8_pri$next[7:0]$14553 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $3\xive9_pri$next[7:0]$14554 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive0_pri$next[7:0]$14555 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive10_pri$next[7:0]$14556 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive11_pri$next[7:0]$14557 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive12_pri$next[7:0]$14558 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive13_pri$next[7:0]$14559 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive14_pri$next[7:0]$14560 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive15_pri$next[7:0]$14561 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive1_pri$next[7:0]$14562 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive2_pri$next[7:0]$14563 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive3_pri$next[7:0]$14564 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive4_pri$next[7:0]$14565 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive5_pri$next[7:0]$14566 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive6_pri$next[7:0]$14567 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive7_pri$next[7:0]$14568 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive8_pri$next[7:0]$14569 - attribute \src "libresoc.v:203643.3-203728.6" - wire width 8 $4\xive9_pri$next[7:0]$14570 - attribute \src "libresoc.v:203500.19-203500.113" - wire $and$libresoc.v:203500$14368_Y - attribute \src "libresoc.v:203502.19-203502.114" - wire $and$libresoc.v:203502$14370_Y - attribute \src "libresoc.v:203504.19-203504.114" - wire $and$libresoc.v:203504$14372_Y - attribute \src "libresoc.v:203506.19-203506.114" - wire $and$libresoc.v:203506$14374_Y - attribute \src "libresoc.v:203508.19-203508.114" - wire $and$libresoc.v:203508$14376_Y - attribute \src "libresoc.v:203510.19-203510.114" - wire $and$libresoc.v:203510$14378_Y - attribute \src "libresoc.v:203512.19-203512.114" - wire $and$libresoc.v:203512$14380_Y - attribute \src "libresoc.v:203515.19-203515.114" - wire $and$libresoc.v:203515$14383_Y - attribute \src "libresoc.v:203517.19-203517.114" - wire $and$libresoc.v:203517$14385_Y - attribute \src "libresoc.v:203519.19-203519.114" - wire $and$libresoc.v:203519$14387_Y - attribute \src "libresoc.v:203522.19-203522.114" - wire $and$libresoc.v:203522$14390_Y - attribute \src "libresoc.v:203524.19-203524.114" - wire $and$libresoc.v:203524$14392_Y - attribute \src "libresoc.v:203526.19-203526.114" - wire $and$libresoc.v:203526$14394_Y - attribute \src "libresoc.v:203528.19-203528.114" - wire $and$libresoc.v:203528$14396_Y - attribute \src "libresoc.v:203530.19-203530.115" - wire $and$libresoc.v:203530$14398_Y - attribute \src "libresoc.v:203532.19-203532.115" - wire $and$libresoc.v:203532$14400_Y - attribute \src "libresoc.v:203534.19-203534.115" - wire $and$libresoc.v:203534$14402_Y - attribute \src "libresoc.v:203537.19-203537.115" - wire $and$libresoc.v:203537$14405_Y - attribute \src "libresoc.v:203539.19-203539.115" - wire $and$libresoc.v:203539$14407_Y - attribute \src "libresoc.v:203541.19-203541.115" - wire $and$libresoc.v:203541$14409_Y - attribute \src "libresoc.v:203544.19-203544.115" - wire $and$libresoc.v:203544$14412_Y - attribute \src "libresoc.v:203546.19-203546.115" - wire $and$libresoc.v:203546$14414_Y - attribute \src "libresoc.v:203548.19-203548.115" - wire $and$libresoc.v:203548$14416_Y - attribute \src "libresoc.v:203550.19-203550.115" - wire $and$libresoc.v:203550$14418_Y - attribute \src "libresoc.v:203552.19-203552.115" - wire $and$libresoc.v:203552$14420_Y - attribute \src "libresoc.v:203555.19-203555.115" - wire $and$libresoc.v:203555$14423_Y - attribute \src "libresoc.v:203579.17-203579.115" - wire $and$libresoc.v:203579$14447_Y - attribute \src "libresoc.v:203587.18-203587.112" - wire $and$libresoc.v:203587$14455_Y - attribute \src "libresoc.v:203589.18-203589.112" - wire $and$libresoc.v:203589$14457_Y - attribute \src "libresoc.v:203591.18-203591.112" - wire $and$libresoc.v:203591$14459_Y - attribute \src "libresoc.v:203593.18-203593.112" - wire $and$libresoc.v:203593$14461_Y - attribute \src "libresoc.v:203596.18-203596.112" - wire $and$libresoc.v:203596$14464_Y - attribute \src "libresoc.v:203598.18-203598.112" - wire $and$libresoc.v:203598$14466_Y - attribute \src "libresoc.v:203600.18-203600.112" - wire $and$libresoc.v:203600$14468_Y - attribute \src "libresoc.v:203514.18-203514.109" - wire $eq$libresoc.v:203514$14382_Y - attribute \src "libresoc.v:203536.18-203536.109" - wire $eq$libresoc.v:203536$14404_Y - attribute \src "libresoc.v:203553.17-203553.114" - wire $eq$libresoc.v:203553$14421_Y - attribute \src "libresoc.v:203556.19-203556.110" - wire $eq$libresoc.v:203556$14424_Y - attribute \src "libresoc.v:203558.18-203558.109" - wire $eq$libresoc.v:203558$14426_Y - attribute \src "libresoc.v:203560.18-203560.109" - wire $eq$libresoc.v:203560$14428_Y - attribute \src "libresoc.v:203562.18-203562.109" - wire $eq$libresoc.v:203562$14430_Y - attribute \src "libresoc.v:203564.18-203564.109" - wire $eq$libresoc.v:203564$14432_Y - attribute \src "libresoc.v:203566.18-203566.109" - wire $eq$libresoc.v:203566$14434_Y - attribute \src "libresoc.v:203568.17-203568.114" - wire $eq$libresoc.v:203568$14436_Y - attribute \src "libresoc.v:203569.18-203569.109" - wire $eq$libresoc.v:203569$14437_Y - attribute \src "libresoc.v:203571.18-203571.109" - wire $eq$libresoc.v:203571$14439_Y - attribute \src "libresoc.v:203573.18-203573.110" - wire $eq$libresoc.v:203573$14441_Y - attribute \src "libresoc.v:203575.18-203575.110" - wire $eq$libresoc.v:203575$14443_Y - attribute \src "libresoc.v:203577.18-203577.110" - wire $eq$libresoc.v:203577$14445_Y - attribute \src "libresoc.v:203580.18-203580.110" - wire $eq$libresoc.v:203580$14448_Y - attribute \src "libresoc.v:203582.18-203582.110" - wire $eq$libresoc.v:203582$14450_Y - attribute \src "libresoc.v:203584.18-203584.110" - wire $eq$libresoc.v:203584$14452_Y - attribute \src "libresoc.v:203595.17-203595.108" - wire $eq$libresoc.v:203595$14463_Y - attribute \src "libresoc.v:203499.18-203499.111" - wire $lt$libresoc.v:203499$14367_Y - attribute \src "libresoc.v:203501.19-203501.112" - wire $lt$libresoc.v:203501$14369_Y - attribute \src "libresoc.v:203503.19-203503.112" - wire $lt$libresoc.v:203503$14371_Y - attribute \src "libresoc.v:203505.19-203505.112" - wire $lt$libresoc.v:203505$14373_Y - attribute \src "libresoc.v:203507.19-203507.112" - wire $lt$libresoc.v:203507$14375_Y - attribute \src "libresoc.v:203509.19-203509.112" - wire $lt$libresoc.v:203509$14377_Y - attribute \src "libresoc.v:203511.19-203511.112" - wire $lt$libresoc.v:203511$14379_Y - attribute \src "libresoc.v:203513.19-203513.112" - wire $lt$libresoc.v:203513$14381_Y - attribute \src "libresoc.v:203516.19-203516.112" - wire $lt$libresoc.v:203516$14384_Y - attribute \src "libresoc.v:203518.19-203518.112" - wire $lt$libresoc.v:203518$14386_Y - attribute \src "libresoc.v:203521.19-203521.112" - wire $lt$libresoc.v:203521$14389_Y - attribute \src "libresoc.v:203523.19-203523.112" - wire $lt$libresoc.v:203523$14391_Y - attribute \src "libresoc.v:203525.19-203525.112" - wire $lt$libresoc.v:203525$14393_Y - attribute \src "libresoc.v:203527.19-203527.112" - wire $lt$libresoc.v:203527$14395_Y - attribute \src "libresoc.v:203529.19-203529.113" - wire $lt$libresoc.v:203529$14397_Y - attribute \src "libresoc.v:203531.19-203531.113" - wire $lt$libresoc.v:203531$14399_Y - attribute \src "libresoc.v:203533.19-203533.114" - wire $lt$libresoc.v:203533$14401_Y - attribute \src "libresoc.v:203535.19-203535.114" - wire $lt$libresoc.v:203535$14403_Y - attribute \src "libresoc.v:203538.19-203538.114" - wire $lt$libresoc.v:203538$14406_Y - attribute \src "libresoc.v:203540.19-203540.114" - wire $lt$libresoc.v:203540$14408_Y - attribute \src "libresoc.v:203543.19-203543.114" - wire $lt$libresoc.v:203543$14411_Y - attribute \src "libresoc.v:203545.19-203545.114" - wire $lt$libresoc.v:203545$14413_Y - attribute \src "libresoc.v:203547.19-203547.114" - wire $lt$libresoc.v:203547$14415_Y - attribute \src "libresoc.v:203549.19-203549.114" - wire $lt$libresoc.v:203549$14417_Y - attribute \src "libresoc.v:203551.19-203551.114" - wire $lt$libresoc.v:203551$14419_Y - attribute \src "libresoc.v:203554.19-203554.114" - wire $lt$libresoc.v:203554$14422_Y - attribute \src "libresoc.v:203588.18-203588.110" - wire $lt$libresoc.v:203588$14456_Y - attribute \src "libresoc.v:203590.18-203590.110" - wire $lt$libresoc.v:203590$14458_Y - attribute \src "libresoc.v:203592.18-203592.111" - wire $lt$libresoc.v:203592$14460_Y - attribute \src "libresoc.v:203594.18-203594.111" - wire $lt$libresoc.v:203594$14462_Y - attribute \src "libresoc.v:203597.18-203597.111" - wire $lt$libresoc.v:203597$14465_Y - attribute \src "libresoc.v:203599.18-203599.111" - wire $lt$libresoc.v:203599$14467_Y - attribute \src "libresoc.v:203586.18-203586.40" - wire width 16 $shr$libresoc.v:203586$14454_Y - attribute \src "libresoc.v:203498.17-203498.114" - wire width 8 $ternary$libresoc.v:203498$14366_Y - attribute \src "libresoc.v:203520.18-203520.116" - wire width 8 $ternary$libresoc.v:203520$14388_Y - attribute \src "libresoc.v:203542.18-203542.116" - wire width 8 $ternary$libresoc.v:203542$14410_Y - attribute \src "libresoc.v:203557.19-203557.118" - wire width 8 $ternary$libresoc.v:203557$14425_Y - attribute \src "libresoc.v:203559.18-203559.116" - wire width 8 $ternary$libresoc.v:203559$14427_Y - attribute \src "libresoc.v:203561.18-203561.116" - wire width 8 $ternary$libresoc.v:203561$14429_Y - attribute \src "libresoc.v:203563.18-203563.116" - wire width 8 $ternary$libresoc.v:203563$14431_Y - attribute \src "libresoc.v:203565.18-203565.116" - wire width 8 $ternary$libresoc.v:203565$14433_Y - attribute \src "libresoc.v:203567.18-203567.116" - wire width 8 $ternary$libresoc.v:203567$14435_Y - attribute \src "libresoc.v:203570.18-203570.116" - wire width 8 $ternary$libresoc.v:203570$14438_Y - attribute \src "libresoc.v:203572.18-203572.116" - wire width 8 $ternary$libresoc.v:203572$14440_Y - attribute \src "libresoc.v:203574.18-203574.117" - wire width 8 $ternary$libresoc.v:203574$14442_Y - attribute \src "libresoc.v:203576.18-203576.117" - wire width 8 $ternary$libresoc.v:203576$14444_Y - attribute \src "libresoc.v:203578.18-203578.117" - wire width 8 $ternary$libresoc.v:203578$14446_Y - attribute \src "libresoc.v:203581.18-203581.117" - wire width 8 $ternary$libresoc.v:203581$14449_Y - attribute \src "libresoc.v:203583.18-203583.117" - wire width 8 $ternary$libresoc.v:203583$14451_Y - attribute \src "libresoc.v:203585.18-203585.117" - wire width 8 $ternary$libresoc.v:203585$14453_Y + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive0_pri$next[7:0]$14451 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive10_pri$next[7:0]$14452 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive11_pri$next[7:0]$14453 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive12_pri$next[7:0]$14454 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive13_pri$next[7:0]$14455 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive14_pri$next[7:0]$14456 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive15_pri$next[7:0]$14457 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive1_pri$next[7:0]$14458 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive2_pri$next[7:0]$14459 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive3_pri$next[7:0]$14460 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive4_pri$next[7:0]$14461 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive5_pri$next[7:0]$14462 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive6_pri$next[7:0]$14463 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive7_pri$next[7:0]$14464 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive8_pri$next[7:0]$14465 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $2\xive9_pri$next[7:0]$14466 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive0_pri$next[7:0]$14467 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive10_pri$next[7:0]$14468 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive11_pri$next[7:0]$14469 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive12_pri$next[7:0]$14470 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive13_pri$next[7:0]$14471 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive14_pri$next[7:0]$14472 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive15_pri$next[7:0]$14473 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive1_pri$next[7:0]$14474 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive2_pri$next[7:0]$14475 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive3_pri$next[7:0]$14476 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive4_pri$next[7:0]$14477 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive5_pri$next[7:0]$14478 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive6_pri$next[7:0]$14479 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive7_pri$next[7:0]$14480 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive8_pri$next[7:0]$14481 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $3\xive9_pri$next[7:0]$14482 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive0_pri$next[7:0]$14483 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive10_pri$next[7:0]$14484 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive11_pri$next[7:0]$14485 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive12_pri$next[7:0]$14486 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive13_pri$next[7:0]$14487 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive14_pri$next[7:0]$14488 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive15_pri$next[7:0]$14489 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive1_pri$next[7:0]$14490 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive2_pri$next[7:0]$14491 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive3_pri$next[7:0]$14492 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive4_pri$next[7:0]$14493 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive5_pri$next[7:0]$14494 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive6_pri$next[7:0]$14495 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive7_pri$next[7:0]$14496 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive8_pri$next[7:0]$14497 + attribute \src "libresoc.v:203240.3-203325.6" + wire width 8 $4\xive9_pri$next[7:0]$14498 + attribute \src "libresoc.v:203097.19-203097.113" + wire $and$libresoc.v:203097$14296_Y + attribute \src "libresoc.v:203099.19-203099.114" + wire $and$libresoc.v:203099$14298_Y + attribute \src "libresoc.v:203101.19-203101.114" + wire $and$libresoc.v:203101$14300_Y + attribute \src "libresoc.v:203103.19-203103.114" + wire $and$libresoc.v:203103$14302_Y + attribute \src "libresoc.v:203105.19-203105.114" + wire $and$libresoc.v:203105$14304_Y + attribute \src "libresoc.v:203107.19-203107.114" + wire $and$libresoc.v:203107$14306_Y + attribute \src "libresoc.v:203109.19-203109.114" + wire $and$libresoc.v:203109$14308_Y + attribute \src "libresoc.v:203112.19-203112.114" + wire $and$libresoc.v:203112$14311_Y + attribute \src "libresoc.v:203114.19-203114.114" + wire $and$libresoc.v:203114$14313_Y + attribute \src "libresoc.v:203116.19-203116.114" + wire $and$libresoc.v:203116$14315_Y + attribute \src "libresoc.v:203119.19-203119.114" + wire $and$libresoc.v:203119$14318_Y + attribute \src "libresoc.v:203121.19-203121.114" + wire $and$libresoc.v:203121$14320_Y + attribute \src "libresoc.v:203123.19-203123.114" + wire $and$libresoc.v:203123$14322_Y + attribute \src "libresoc.v:203125.19-203125.114" + wire $and$libresoc.v:203125$14324_Y + attribute \src "libresoc.v:203127.19-203127.115" + wire $and$libresoc.v:203127$14326_Y + attribute \src "libresoc.v:203129.19-203129.115" + wire $and$libresoc.v:203129$14328_Y + attribute \src "libresoc.v:203131.19-203131.115" + wire $and$libresoc.v:203131$14330_Y + attribute \src "libresoc.v:203134.19-203134.115" + wire $and$libresoc.v:203134$14333_Y + attribute \src "libresoc.v:203136.19-203136.115" + wire $and$libresoc.v:203136$14335_Y + attribute \src "libresoc.v:203138.19-203138.115" + wire $and$libresoc.v:203138$14337_Y + attribute \src "libresoc.v:203141.19-203141.115" + wire $and$libresoc.v:203141$14340_Y + attribute \src "libresoc.v:203143.19-203143.115" + wire $and$libresoc.v:203143$14342_Y + attribute \src "libresoc.v:203145.19-203145.115" + wire $and$libresoc.v:203145$14344_Y + attribute \src "libresoc.v:203147.19-203147.115" + wire $and$libresoc.v:203147$14346_Y + attribute \src "libresoc.v:203149.19-203149.115" + wire $and$libresoc.v:203149$14348_Y + attribute \src "libresoc.v:203152.19-203152.115" + wire $and$libresoc.v:203152$14351_Y + attribute \src "libresoc.v:203176.17-203176.115" + wire $and$libresoc.v:203176$14375_Y + attribute \src "libresoc.v:203184.18-203184.112" + wire $and$libresoc.v:203184$14383_Y + attribute \src "libresoc.v:203186.18-203186.112" + wire $and$libresoc.v:203186$14385_Y + attribute \src "libresoc.v:203188.18-203188.112" + wire $and$libresoc.v:203188$14387_Y + attribute \src "libresoc.v:203190.18-203190.112" + wire $and$libresoc.v:203190$14389_Y + attribute \src "libresoc.v:203193.18-203193.112" + wire $and$libresoc.v:203193$14392_Y + attribute \src "libresoc.v:203195.18-203195.112" + wire $and$libresoc.v:203195$14394_Y + attribute \src "libresoc.v:203197.18-203197.112" + wire $and$libresoc.v:203197$14396_Y + attribute \src "libresoc.v:203111.18-203111.109" + wire $eq$libresoc.v:203111$14310_Y + attribute \src "libresoc.v:203133.18-203133.109" + wire $eq$libresoc.v:203133$14332_Y + attribute \src "libresoc.v:203150.17-203150.114" + wire $eq$libresoc.v:203150$14349_Y + attribute \src "libresoc.v:203153.19-203153.110" + wire $eq$libresoc.v:203153$14352_Y + attribute \src "libresoc.v:203155.18-203155.109" + wire $eq$libresoc.v:203155$14354_Y + attribute \src "libresoc.v:203157.18-203157.109" + wire $eq$libresoc.v:203157$14356_Y + attribute \src "libresoc.v:203159.18-203159.109" + wire $eq$libresoc.v:203159$14358_Y + attribute \src "libresoc.v:203161.18-203161.109" + wire $eq$libresoc.v:203161$14360_Y + attribute \src "libresoc.v:203163.18-203163.109" + wire $eq$libresoc.v:203163$14362_Y + attribute \src "libresoc.v:203165.17-203165.114" + wire $eq$libresoc.v:203165$14364_Y + attribute \src "libresoc.v:203166.18-203166.109" + wire $eq$libresoc.v:203166$14365_Y + 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"libresoc.v:203102.19-203102.112" + wire $lt$libresoc.v:203102$14301_Y + attribute \src "libresoc.v:203104.19-203104.112" + wire $lt$libresoc.v:203104$14303_Y + attribute \src "libresoc.v:203106.19-203106.112" + wire $lt$libresoc.v:203106$14305_Y + attribute \src "libresoc.v:203108.19-203108.112" + wire $lt$libresoc.v:203108$14307_Y + attribute \src "libresoc.v:203110.19-203110.112" + wire $lt$libresoc.v:203110$14309_Y + attribute \src "libresoc.v:203113.19-203113.112" + wire $lt$libresoc.v:203113$14312_Y + attribute \src "libresoc.v:203115.19-203115.112" + wire $lt$libresoc.v:203115$14314_Y + attribute \src "libresoc.v:203118.19-203118.112" + wire $lt$libresoc.v:203118$14317_Y + attribute \src "libresoc.v:203120.19-203120.112" + wire $lt$libresoc.v:203120$14319_Y + attribute \src "libresoc.v:203122.19-203122.112" + wire $lt$libresoc.v:203122$14321_Y + attribute \src "libresoc.v:203124.19-203124.112" + wire $lt$libresoc.v:203124$14323_Y + attribute \src "libresoc.v:203126.19-203126.113" + wire $lt$libresoc.v:203126$14325_Y + attribute \src "libresoc.v:203128.19-203128.113" + wire $lt$libresoc.v:203128$14327_Y + attribute \src "libresoc.v:203130.19-203130.114" + wire $lt$libresoc.v:203130$14329_Y + attribute \src "libresoc.v:203132.19-203132.114" + wire $lt$libresoc.v:203132$14331_Y + attribute \src "libresoc.v:203135.19-203135.114" + wire $lt$libresoc.v:203135$14334_Y + attribute \src "libresoc.v:203137.19-203137.114" + wire $lt$libresoc.v:203137$14336_Y + attribute \src "libresoc.v:203140.19-203140.114" + wire $lt$libresoc.v:203140$14339_Y + attribute \src "libresoc.v:203142.19-203142.114" + wire $lt$libresoc.v:203142$14341_Y + attribute \src "libresoc.v:203144.19-203144.114" + wire $lt$libresoc.v:203144$14343_Y + attribute \src "libresoc.v:203146.19-203146.114" + wire $lt$libresoc.v:203146$14345_Y + attribute \src "libresoc.v:203148.19-203148.114" + wire $lt$libresoc.v:203148$14347_Y + attribute \src "libresoc.v:203151.19-203151.114" + wire $lt$libresoc.v:203151$14350_Y + attribute \src "libresoc.v:203185.18-203185.110" + wire $lt$libresoc.v:203185$14384_Y + attribute \src "libresoc.v:203187.18-203187.110" + wire $lt$libresoc.v:203187$14386_Y + attribute \src "libresoc.v:203189.18-203189.111" + wire $lt$libresoc.v:203189$14388_Y + attribute \src "libresoc.v:203191.18-203191.111" + wire $lt$libresoc.v:203191$14390_Y + attribute \src "libresoc.v:203194.18-203194.111" + wire $lt$libresoc.v:203194$14393_Y + attribute \src "libresoc.v:203196.18-203196.111" + wire $lt$libresoc.v:203196$14395_Y + attribute \src "libresoc.v:203183.18-203183.40" + wire width 16 $shr$libresoc.v:203183$14382_Y + attribute \src "libresoc.v:203095.17-203095.114" + wire width 8 $ternary$libresoc.v:203095$14294_Y + attribute \src "libresoc.v:203117.18-203117.116" + wire width 8 $ternary$libresoc.v:203117$14316_Y + attribute \src "libresoc.v:203139.18-203139.116" + wire width 8 $ternary$libresoc.v:203139$14338_Y + attribute \src "libresoc.v:203154.19-203154.118" + wire width 8 $ternary$libresoc.v:203154$14353_Y + attribute \src "libresoc.v:203156.18-203156.116" + wire width 8 $ternary$libresoc.v:203156$14355_Y + attribute \src "libresoc.v:203158.18-203158.116" + wire width 8 $ternary$libresoc.v:203158$14357_Y + attribute \src "libresoc.v:203160.18-203160.116" + wire width 8 $ternary$libresoc.v:203160$14359_Y + attribute \src "libresoc.v:203162.18-203162.116" + wire width 8 $ternary$libresoc.v:203162$14361_Y + attribute \src "libresoc.v:203164.18-203164.116" + wire width 8 $ternary$libresoc.v:203164$14363_Y + attribute \src "libresoc.v:203167.18-203167.116" + wire width 8 $ternary$libresoc.v:203167$14366_Y + attribute \src "libresoc.v:203169.18-203169.116" + wire width 8 $ternary$libresoc.v:203169$14368_Y + attribute \src "libresoc.v:203171.18-203171.117" + wire width 8 $ternary$libresoc.v:203171$14370_Y + attribute \src "libresoc.v:203173.18-203173.117" + wire width 8 $ternary$libresoc.v:203173$14372_Y + attribute \src "libresoc.v:203175.18-203175.117" + wire width 8 $ternary$libresoc.v:203175$14374_Y + attribute \src "libresoc.v:203178.18-203178.117" + wire width 8 $ternary$libresoc.v:203178$14377_Y + attribute \src "libresoc.v:203180.18-203180.117" + wire width 8 $ternary$libresoc.v:203180$14379_Y + attribute \src "libresoc.v:203182.18-203182.117" + wire width 8 $ternary$libresoc.v:203182$14381_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -388438,7 +387577,7 @@ module \xics_ics wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 12 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 @@ -388507,11 +387646,11 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:314" wire \ibit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 output 3 \icp_o_pri + wire width 8 output 2 \icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" wire width 8 \icp_o_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 output 2 \icp_o_src + wire width 4 output 1 \icp_o_src attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \icp_o_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" @@ -388536,7 +387675,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:203099.7-203099.15" + attribute \src "libresoc.v:202696.7-202696.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -388556,8 +387695,8 @@ module \xics_ics wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" - wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" + wire input 3 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" @@ -388625,7 +387764,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203500$14368 + cell $and $and$libresoc.v:203097$14296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388633,10 +387772,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:203500$14368_Y + connect \Y $and$libresoc.v:203097$14296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203502$14370 + cell $and $and$libresoc.v:203099$14298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388644,10 +387783,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:203502$14370_Y + connect \Y $and$libresoc.v:203099$14298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203504$14372 + cell $and $and$libresoc.v:203101$14300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388655,10 +387794,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:203504$14372_Y + connect \Y $and$libresoc.v:203101$14300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203506$14374 + cell $and $and$libresoc.v:203103$14302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388666,10 +387805,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:203506$14374_Y + connect \Y $and$libresoc.v:203103$14302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203508$14376 + cell $and $and$libresoc.v:203105$14304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388677,10 +387816,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:203508$14376_Y + connect \Y $and$libresoc.v:203105$14304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203510$14378 + cell $and $and$libresoc.v:203107$14306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388688,10 +387827,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:203510$14378_Y + connect \Y $and$libresoc.v:203107$14306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203512$14380 + cell $and $and$libresoc.v:203109$14308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388699,10 +387838,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:203512$14380_Y + connect \Y $and$libresoc.v:203109$14308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203515$14383 + cell $and $and$libresoc.v:203112$14311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388710,10 +387849,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:203515$14383_Y + connect \Y $and$libresoc.v:203112$14311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203517$14385 + cell $and $and$libresoc.v:203114$14313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388721,10 +387860,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:203517$14385_Y + connect \Y $and$libresoc.v:203114$14313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203519$14387 + cell $and $and$libresoc.v:203116$14315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388732,10 +387871,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:203519$14387_Y + connect \Y $and$libresoc.v:203116$14315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203522$14390 + cell $and $and$libresoc.v:203119$14318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388743,10 +387882,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:203522$14390_Y + connect \Y $and$libresoc.v:203119$14318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203524$14392 + cell $and $and$libresoc.v:203121$14320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388754,10 +387893,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:203524$14392_Y + connect \Y $and$libresoc.v:203121$14320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203526$14394 + cell $and $and$libresoc.v:203123$14322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388765,10 +387904,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:203526$14394_Y + connect \Y $and$libresoc.v:203123$14322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203528$14396 + cell $and $and$libresoc.v:203125$14324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388776,10 +387915,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:203528$14396_Y + connect \Y $and$libresoc.v:203125$14324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203530$14398 + cell $and $and$libresoc.v:203127$14326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388787,10 +387926,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:203530$14398_Y + connect \Y $and$libresoc.v:203127$14326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203532$14400 + cell $and $and$libresoc.v:203129$14328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388798,10 +387937,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:203532$14400_Y + connect \Y $and$libresoc.v:203129$14328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203534$14402 + cell $and $and$libresoc.v:203131$14330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388809,10 +387948,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:203534$14402_Y + connect \Y $and$libresoc.v:203131$14330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203537$14405 + cell $and $and$libresoc.v:203134$14333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388820,10 +387959,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:203537$14405_Y + connect \Y $and$libresoc.v:203134$14333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203539$14407 + cell $and $and$libresoc.v:203136$14335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388831,10 +387970,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:203539$14407_Y + connect \Y $and$libresoc.v:203136$14335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203541$14409 + cell $and $and$libresoc.v:203138$14337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388842,10 +387981,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:203541$14409_Y + connect \Y $and$libresoc.v:203138$14337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203544$14412 + cell $and $and$libresoc.v:203141$14340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388853,10 +387992,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:203544$14412_Y + connect \Y $and$libresoc.v:203141$14340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203546$14414 + cell $and $and$libresoc.v:203143$14342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388864,10 +388003,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:203546$14414_Y + connect \Y $and$libresoc.v:203143$14342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203548$14416 + cell $and $and$libresoc.v:203145$14344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388875,10 +388014,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:203548$14416_Y + connect \Y $and$libresoc.v:203145$14344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203550$14418 + cell $and $and$libresoc.v:203147$14346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388886,10 +388025,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:203550$14418_Y + connect \Y $and$libresoc.v:203147$14346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203552$14420 + cell $and $and$libresoc.v:203149$14348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388897,10 +388036,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:203552$14420_Y + connect \Y $and$libresoc.v:203149$14348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203555$14423 + cell $and $and$libresoc.v:203152$14351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388908,10 +388047,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:203555$14423_Y + connect \Y $and$libresoc.v:203152$14351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:203579$14447 + cell $and $and$libresoc.v:203176$14375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388919,10 +388058,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:203579$14447_Y + connect \Y $and$libresoc.v:203176$14375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:203587$14455 + cell $and $and$libresoc.v:203184$14383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388930,10 +388069,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:203587$14455_Y + connect \Y $and$libresoc.v:203184$14383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203589$14457 + cell $and $and$libresoc.v:203186$14385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388941,10 +388080,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:203589$14457_Y + connect \Y $and$libresoc.v:203186$14385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203591$14459 + cell $and $and$libresoc.v:203188$14387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388952,10 +388091,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:203591$14459_Y + connect \Y $and$libresoc.v:203188$14387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203593$14461 + cell $and $and$libresoc.v:203190$14389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388963,10 +388102,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:203593$14461_Y + connect \Y $and$libresoc.v:203190$14389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203596$14464 + cell $and $and$libresoc.v:203193$14392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388974,10 +388113,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:203596$14464_Y + connect \Y $and$libresoc.v:203193$14392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203598$14466 + cell $and $and$libresoc.v:203195$14394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388985,10 +388124,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:203598$14466_Y + connect \Y $and$libresoc.v:203195$14394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:203600$14468 + cell $and $and$libresoc.v:203197$14396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388996,10 +388135,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:203600$14468_Y + connect \Y $and$libresoc.v:203197$14396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203514$14382 + cell $eq $eq$libresoc.v:203111$14310 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389007,10 +388146,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203514$14382_Y + connect \Y $eq$libresoc.v:203111$14310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203536$14404 + cell $eq $eq$libresoc.v:203133$14332 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389018,10 +388157,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203536$14404_Y + connect \Y $eq$libresoc.v:203133$14332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:203553$14421 + cell $eq $eq$libresoc.v:203150$14349 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -389029,10 +388168,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:203553$14421_Y + connect \Y $eq$libresoc.v:203150$14349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203556$14424 + cell $eq $eq$libresoc.v:203153$14352 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389040,10 +388179,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:203556$14424_Y + connect \Y $eq$libresoc.v:203153$14352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203558$14426 + cell $eq $eq$libresoc.v:203155$14354 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389051,10 +388190,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203558$14426_Y + connect \Y $eq$libresoc.v:203155$14354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203560$14428 + cell $eq $eq$libresoc.v:203157$14356 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389062,10 +388201,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203560$14428_Y + connect \Y $eq$libresoc.v:203157$14356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203562$14430 + cell $eq $eq$libresoc.v:203159$14358 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389073,10 +388212,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203562$14430_Y + connect \Y $eq$libresoc.v:203159$14358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203564$14432 + cell $eq $eq$libresoc.v:203161$14360 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389084,10 +388223,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203564$14432_Y + connect \Y $eq$libresoc.v:203161$14360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203566$14434 + cell $eq $eq$libresoc.v:203163$14362 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389095,10 +388234,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203566$14434_Y + connect \Y $eq$libresoc.v:203163$14362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:203568$14436 + cell $eq $eq$libresoc.v:203165$14364 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -389106,10 +388245,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:203568$14436_Y + connect \Y $eq$libresoc.v:203165$14364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203569$14437 + cell $eq $eq$libresoc.v:203166$14365 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389117,10 +388256,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203569$14437_Y + connect \Y $eq$libresoc.v:203166$14365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203571$14439 + cell $eq $eq$libresoc.v:203168$14367 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389128,10 +388267,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203571$14439_Y + connect \Y $eq$libresoc.v:203168$14367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203573$14441 + cell $eq $eq$libresoc.v:203170$14369 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389139,10 +388278,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203573$14441_Y + connect \Y $eq$libresoc.v:203170$14369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203575$14443 + cell $eq $eq$libresoc.v:203172$14371 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389150,10 +388289,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203575$14443_Y + connect \Y $eq$libresoc.v:203172$14371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203577$14445 + cell $eq $eq$libresoc.v:203174$14373 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389161,10 +388300,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203577$14445_Y + connect \Y $eq$libresoc.v:203174$14373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203580$14448 + cell $eq $eq$libresoc.v:203177$14376 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389172,10 +388311,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203580$14448_Y + connect \Y $eq$libresoc.v:203177$14376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203582$14450 + cell $eq $eq$libresoc.v:203179$14378 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389183,10 +388322,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203582$14450_Y + connect \Y $eq$libresoc.v:203179$14378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203584$14452 + cell $eq $eq$libresoc.v:203181$14380 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389194,10 +388333,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203584$14452_Y + connect \Y $eq$libresoc.v:203181$14380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:203595$14463 + cell $eq $eq$libresoc.v:203192$14391 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389205,10 +388344,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:203595$14463_Y + connect \Y $eq$libresoc.v:203192$14391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203499$14367 + cell $lt $lt$libresoc.v:203096$14295 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389216,10 +388355,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:203499$14367_Y + connect \Y $lt$libresoc.v:203096$14295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203501$14369 + cell $lt $lt$libresoc.v:203098$14297 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389227,10 +388366,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:203501$14369_Y + connect \Y $lt$libresoc.v:203098$14297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203503$14371 + cell $lt $lt$libresoc.v:203100$14299 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389238,10 +388377,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:203503$14371_Y + connect \Y $lt$libresoc.v:203100$14299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203505$14373 + cell $lt $lt$libresoc.v:203102$14301 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389249,10 +388388,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:203505$14373_Y + connect \Y $lt$libresoc.v:203102$14301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203507$14375 + cell $lt $lt$libresoc.v:203104$14303 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389260,10 +388399,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:203507$14375_Y + connect \Y $lt$libresoc.v:203104$14303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203509$14377 + cell $lt $lt$libresoc.v:203106$14305 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389271,10 +388410,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:203509$14377_Y + connect \Y $lt$libresoc.v:203106$14305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203511$14379 + cell $lt $lt$libresoc.v:203108$14307 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389282,10 +388421,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:203511$14379_Y + connect \Y $lt$libresoc.v:203108$14307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203513$14381 + cell $lt $lt$libresoc.v:203110$14309 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389293,10 +388432,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:203513$14381_Y + connect \Y $lt$libresoc.v:203110$14309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203516$14384 + cell $lt $lt$libresoc.v:203113$14312 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389304,10 +388443,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:203516$14384_Y + connect \Y $lt$libresoc.v:203113$14312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203518$14386 + cell $lt $lt$libresoc.v:203115$14314 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389315,10 +388454,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:203518$14386_Y + connect \Y $lt$libresoc.v:203115$14314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203521$14389 + cell $lt $lt$libresoc.v:203118$14317 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389326,10 +388465,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:203521$14389_Y + connect \Y $lt$libresoc.v:203118$14317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203523$14391 + cell $lt $lt$libresoc.v:203120$14319 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389337,10 +388476,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:203523$14391_Y + connect \Y $lt$libresoc.v:203120$14319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203525$14393 + cell $lt $lt$libresoc.v:203122$14321 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389348,10 +388487,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:203525$14393_Y + connect \Y $lt$libresoc.v:203122$14321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203527$14395 + cell $lt $lt$libresoc.v:203124$14323 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389359,10 +388498,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:203527$14395_Y + connect \Y $lt$libresoc.v:203124$14323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203529$14397 + cell $lt $lt$libresoc.v:203126$14325 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389370,10 +388509,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:203529$14397_Y + connect \Y $lt$libresoc.v:203126$14325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203531$14399 + cell $lt $lt$libresoc.v:203128$14327 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389381,10 +388520,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:203531$14399_Y + connect \Y $lt$libresoc.v:203128$14327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203533$14401 + cell $lt $lt$libresoc.v:203130$14329 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389392,10 +388531,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:203533$14401_Y + connect \Y $lt$libresoc.v:203130$14329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203535$14403 + cell $lt $lt$libresoc.v:203132$14331 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389403,10 +388542,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:203535$14403_Y + connect \Y $lt$libresoc.v:203132$14331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203538$14406 + cell $lt $lt$libresoc.v:203135$14334 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389414,10 +388553,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:203538$14406_Y + connect \Y $lt$libresoc.v:203135$14334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203540$14408 + cell $lt $lt$libresoc.v:203137$14336 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389425,10 +388564,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:203540$14408_Y + connect \Y $lt$libresoc.v:203137$14336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203543$14411 + cell $lt $lt$libresoc.v:203140$14339 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389436,10 +388575,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:203543$14411_Y + connect \Y $lt$libresoc.v:203140$14339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203545$14413 + cell $lt $lt$libresoc.v:203142$14341 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389447,10 +388586,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:203545$14413_Y + connect \Y $lt$libresoc.v:203142$14341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203547$14415 + cell $lt $lt$libresoc.v:203144$14343 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389458,10 +388597,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:203547$14415_Y + connect \Y $lt$libresoc.v:203144$14343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203549$14417 + cell $lt $lt$libresoc.v:203146$14345 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389469,10 +388608,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:203549$14417_Y + connect \Y $lt$libresoc.v:203146$14345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203551$14419 + cell $lt $lt$libresoc.v:203148$14347 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389480,10 +388619,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:203551$14419_Y + connect \Y $lt$libresoc.v:203148$14347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203554$14422 + cell $lt $lt$libresoc.v:203151$14350 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389491,10 +388630,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:203554$14422_Y + connect \Y $lt$libresoc.v:203151$14350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203588$14456 + cell $lt $lt$libresoc.v:203185$14384 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389502,10 +388641,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:203588$14456_Y + connect \Y $lt$libresoc.v:203185$14384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203590$14458 + cell $lt $lt$libresoc.v:203187$14386 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389513,10 +388652,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:203590$14458_Y + connect \Y $lt$libresoc.v:203187$14386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203592$14460 + cell $lt $lt$libresoc.v:203189$14388 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389524,10 +388663,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:203592$14460_Y + connect \Y $lt$libresoc.v:203189$14388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203594$14462 + cell $lt $lt$libresoc.v:203191$14390 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389535,10 +388674,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:203594$14462_Y + connect \Y $lt$libresoc.v:203191$14390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203597$14465 + cell $lt $lt$libresoc.v:203194$14393 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389546,10 +388685,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:203597$14465_Y + connect \Y $lt$libresoc.v:203194$14393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:203599$14467 + cell $lt $lt$libresoc.v:203196$14395 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389557,10 +388696,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:203599$14467_Y + connect \Y $lt$libresoc.v:203196$14395_Y end - attribute \src "libresoc.v:203586.18-203586.40" - cell $shr $shr$libresoc.v:203586$14454 + attribute \src "libresoc.v:203183.18-203183.40" + cell $shr $shr$libresoc.v:203183$14382 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -389568,469 +388707,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:203586$14454_Y + connect \Y $shr$libresoc.v:203183$14382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203498$14366 + cell $mux $ternary$libresoc.v:203095$14294 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:203498$14366_Y + connect \Y $ternary$libresoc.v:203095$14294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203520$14388 + cell $mux $ternary$libresoc.v:203117$14316 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:203520$14388_Y + connect \Y $ternary$libresoc.v:203117$14316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203542$14410 + cell $mux $ternary$libresoc.v:203139$14338 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:203542$14410_Y + connect \Y $ternary$libresoc.v:203139$14338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203557$14425 + cell $mux $ternary$libresoc.v:203154$14353 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:203557$14425_Y + connect \Y $ternary$libresoc.v:203154$14353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203559$14427 + cell $mux $ternary$libresoc.v:203156$14355 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:203559$14427_Y + connect \Y $ternary$libresoc.v:203156$14355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203561$14429 + cell $mux $ternary$libresoc.v:203158$14357 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:203561$14429_Y + connect \Y $ternary$libresoc.v:203158$14357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203563$14431 + cell $mux $ternary$libresoc.v:203160$14359 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:203563$14431_Y + connect \Y $ternary$libresoc.v:203160$14359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203565$14433 + cell $mux $ternary$libresoc.v:203162$14361 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:203565$14433_Y + connect \Y $ternary$libresoc.v:203162$14361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203567$14435 + cell $mux $ternary$libresoc.v:203164$14363 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:203567$14435_Y + connect \Y $ternary$libresoc.v:203164$14363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203570$14438 + cell $mux $ternary$libresoc.v:203167$14366 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:203570$14438_Y + connect \Y $ternary$libresoc.v:203167$14366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203572$14440 + cell $mux $ternary$libresoc.v:203169$14368 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:203572$14440_Y + connect \Y $ternary$libresoc.v:203169$14368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203574$14442 + cell $mux $ternary$libresoc.v:203171$14370 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:203574$14442_Y + connect \Y $ternary$libresoc.v:203171$14370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203576$14444 + cell $mux $ternary$libresoc.v:203173$14372 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:203576$14444_Y + connect \Y $ternary$libresoc.v:203173$14372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203578$14446 + cell $mux $ternary$libresoc.v:203175$14374 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:203578$14446_Y + connect \Y $ternary$libresoc.v:203175$14374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203581$14449 + cell $mux $ternary$libresoc.v:203178$14377 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:203581$14449_Y + connect \Y $ternary$libresoc.v:203178$14377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203583$14451 + cell $mux $ternary$libresoc.v:203180$14379 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:203583$14451_Y + connect \Y $ternary$libresoc.v:203180$14379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:203585$14453 + cell $mux $ternary$libresoc.v:203182$14381 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:203585$14453_Y + connect \Y $ternary$libresoc.v:203182$14381_Y end - attribute \src "libresoc.v:203099.7-203099.20" - process $proc$libresoc.v:203099$14614 + attribute \src "libresoc.v:202696.7-202696.20" + process $proc$libresoc.v:202696$14542 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:203380.13-203380.30" - process $proc$libresoc.v:203380$14615 + attribute \src "libresoc.v:202977.13-202977.30" + process $proc$libresoc.v:202977$14543 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:203385.13-203385.29" - process $proc$libresoc.v:203385$14616 + attribute \src "libresoc.v:202982.13-202982.29" + process $proc$libresoc.v:202982$14544 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:203394.7-203394.25" - process $proc$libresoc.v:203394$14617 + attribute \src "libresoc.v:202991.7-202991.25" + process $proc$libresoc.v:202991$14545 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:203403.14-203403.35" - process $proc$libresoc.v:203403$14618 + attribute \src "libresoc.v:203000.14-203000.35" + process $proc$libresoc.v:203000$14546 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:203415.14-203415.36" - process $proc$libresoc.v:203415$14619 + attribute \src "libresoc.v:203012.14-203012.36" + process $proc$libresoc.v:203012$14547 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:203435.13-203435.30" - process $proc$libresoc.v:203435$14620 + attribute \src "libresoc.v:203032.13-203032.30" + process $proc$libresoc.v:203032$14548 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:203439.13-203439.31" - process $proc$libresoc.v:203439$14621 + attribute \src "libresoc.v:203036.13-203036.31" + process $proc$libresoc.v:203036$14549 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:203443.13-203443.31" - process $proc$libresoc.v:203443$14622 + attribute \src "libresoc.v:203040.13-203040.31" + process $proc$libresoc.v:203040$14550 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:203447.13-203447.31" - process $proc$libresoc.v:203447$14623 + attribute \src "libresoc.v:203044.13-203044.31" + process $proc$libresoc.v:203044$14551 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:203451.13-203451.31" - process $proc$libresoc.v:203451$14624 + attribute \src "libresoc.v:203048.13-203048.31" + process $proc$libresoc.v:203048$14552 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:203455.13-203455.31" - process $proc$libresoc.v:203455$14625 + attribute \src "libresoc.v:203052.13-203052.31" + process $proc$libresoc.v:203052$14553 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:203459.13-203459.31" - process $proc$libresoc.v:203459$14626 + attribute \src "libresoc.v:203056.13-203056.31" + process $proc$libresoc.v:203056$14554 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:203463.13-203463.30" - process $proc$libresoc.v:203463$14627 + attribute \src "libresoc.v:203060.13-203060.30" + process $proc$libresoc.v:203060$14555 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:203467.13-203467.30" - process $proc$libresoc.v:203467$14628 + attribute \src "libresoc.v:203064.13-203064.30" + process $proc$libresoc.v:203064$14556 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:203471.13-203471.30" - process $proc$libresoc.v:203471$14629 + attribute \src "libresoc.v:203068.13-203068.30" + process $proc$libresoc.v:203068$14557 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:203475.13-203475.30" - process $proc$libresoc.v:203475$14630 + attribute \src "libresoc.v:203072.13-203072.30" + process $proc$libresoc.v:203072$14558 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:203479.13-203479.30" - process $proc$libresoc.v:203479$14631 + attribute \src "libresoc.v:203076.13-203076.30" + process $proc$libresoc.v:203076$14559 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:203483.13-203483.30" - process $proc$libresoc.v:203483$14632 + attribute \src "libresoc.v:203080.13-203080.30" + process $proc$libresoc.v:203080$14560 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:203487.13-203487.30" - process $proc$libresoc.v:203487$14633 + attribute \src "libresoc.v:203084.13-203084.30" + process $proc$libresoc.v:203084$14561 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:203491.13-203491.30" - process $proc$libresoc.v:203491$14634 + attribute \src "libresoc.v:203088.13-203088.30" + process $proc$libresoc.v:203088$14562 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:203495.13-203495.30" - process $proc$libresoc.v:203495$14635 + attribute \src "libresoc.v:203092.13-203092.30" + process $proc$libresoc.v:203092$14563 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:203601.3-203602.28" - process $proc$libresoc.v:203601$14469 + attribute \src "libresoc.v:203198.3-203199.28" + process $proc$libresoc.v:203198$14397 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "libresoc.v:203603.3-203604.25" - process $proc$libresoc.v:203603$14470 + attribute \src "libresoc.v:203200.3-203201.25" + process $proc$libresoc.v:203200$14398 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "libresoc.v:203605.3-203606.35" - process $proc$libresoc.v:203605$14471 + attribute \src "libresoc.v:203202.3-203203.35" + process $proc$libresoc.v:203202$14399 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "libresoc.v:203607.3-203608.35" - process $proc$libresoc.v:203607$14472 + attribute \src "libresoc.v:203204.3-203205.35" + process $proc$libresoc.v:203204$14400 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "libresoc.v:203609.3-203610.35" - process $proc$libresoc.v:203609$14473 + attribute \src "libresoc.v:203206.3-203207.35" + process $proc$libresoc.v:203206$14401 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "libresoc.v:203611.3-203612.35" - process $proc$libresoc.v:203611$14474 + attribute \src "libresoc.v:203208.3-203209.35" + process $proc$libresoc.v:203208$14402 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "libresoc.v:203613.3-203614.35" - process $proc$libresoc.v:203613$14475 + attribute \src "libresoc.v:203210.3-203211.35" + process $proc$libresoc.v:203210$14403 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "libresoc.v:203615.3-203616.35" - process $proc$libresoc.v:203615$14476 + attribute \src "libresoc.v:203212.3-203213.35" + process $proc$libresoc.v:203212$14404 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "libresoc.v:203617.3-203618.35" - process $proc$libresoc.v:203617$14477 + attribute \src "libresoc.v:203214.3-203215.35" + process $proc$libresoc.v:203214$14405 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "libresoc.v:203619.3-203620.35" - process $proc$libresoc.v:203619$14478 + attribute \src "libresoc.v:203216.3-203217.35" + process $proc$libresoc.v:203216$14406 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "libresoc.v:203621.3-203622.35" - process $proc$libresoc.v:203621$14479 + attribute \src "libresoc.v:203218.3-203219.35" + process $proc$libresoc.v:203218$14407 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "libresoc.v:203623.3-203624.35" - process $proc$libresoc.v:203623$14480 + attribute \src "libresoc.v:203220.3-203221.35" + process $proc$libresoc.v:203220$14408 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "libresoc.v:203625.3-203626.37" - process $proc$libresoc.v:203625$14481 + attribute \src "libresoc.v:203222.3-203223.37" + process $proc$libresoc.v:203222$14409 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "libresoc.v:203627.3-203628.37" - process $proc$libresoc.v:203627$14482 + attribute \src "libresoc.v:203224.3-203225.37" + process $proc$libresoc.v:203224$14410 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "libresoc.v:203629.3-203630.37" - process $proc$libresoc.v:203629$14483 + attribute \src "libresoc.v:203226.3-203227.37" + process $proc$libresoc.v:203226$14411 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "libresoc.v:203631.3-203632.37" - process $proc$libresoc.v:203631$14484 + attribute \src "libresoc.v:203228.3-203229.37" + process $proc$libresoc.v:203228$14412 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "libresoc.v:203633.3-203634.37" - process $proc$libresoc.v:203633$14485 + attribute \src "libresoc.v:203230.3-203231.37" + process $proc$libresoc.v:203230$14413 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "libresoc.v:203635.3-203636.37" - process $proc$libresoc.v:203635$14486 + attribute \src "libresoc.v:203232.3-203233.37" + process $proc$libresoc.v:203232$14414 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "libresoc.v:203637.3-203638.39" - process $proc$libresoc.v:203637$14487 + attribute \src "libresoc.v:203234.3-203235.39" + process $proc$libresoc.v:203234$14415 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "libresoc.v:203639.3-203640.43" - process $proc$libresoc.v:203639$14488 + attribute \src "libresoc.v:203236.3-203237.43" + process $proc$libresoc.v:203236$14416 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:203641.3-203642.39" - process $proc$libresoc.v:203641$14489 + attribute \src "libresoc.v:203238.3-203239.39" + process $proc$libresoc.v:203238$14417 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "libresoc.v:203643.3-203728.6" - process $proc$libresoc.v:203643$14490 + attribute \src "libresoc.v:203240.3-203325.6" + process $proc$libresoc.v:203240$14418 assign { } { } assign { } { } assign { } { } @@ -390079,25 +389218,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$14491 $4\xive0_pri$next[7:0]$14555 - assign $0\xive10_pri$next[7:0]$14492 $4\xive10_pri$next[7:0]$14556 - assign $0\xive11_pri$next[7:0]$14493 $4\xive11_pri$next[7:0]$14557 - assign $0\xive12_pri$next[7:0]$14494 $4\xive12_pri$next[7:0]$14558 - assign $0\xive13_pri$next[7:0]$14495 $4\xive13_pri$next[7:0]$14559 - assign $0\xive14_pri$next[7:0]$14496 $4\xive14_pri$next[7:0]$14560 - assign $0\xive15_pri$next[7:0]$14497 $4\xive15_pri$next[7:0]$14561 - assign $0\xive1_pri$next[7:0]$14498 $4\xive1_pri$next[7:0]$14562 - assign $0\xive2_pri$next[7:0]$14499 $4\xive2_pri$next[7:0]$14563 - assign $0\xive3_pri$next[7:0]$14500 $4\xive3_pri$next[7:0]$14564 - assign $0\xive4_pri$next[7:0]$14501 $4\xive4_pri$next[7:0]$14565 - assign $0\xive5_pri$next[7:0]$14502 $4\xive5_pri$next[7:0]$14566 - assign $0\xive6_pri$next[7:0]$14503 $4\xive6_pri$next[7:0]$14567 - assign $0\xive7_pri$next[7:0]$14504 $4\xive7_pri$next[7:0]$14568 - assign $0\xive8_pri$next[7:0]$14505 $4\xive8_pri$next[7:0]$14569 - assign $0\xive9_pri$next[7:0]$14506 $4\xive9_pri$next[7:0]$14570 - attribute \src "libresoc.v:203644.5-203644.29" + assign $0\xive0_pri$next[7:0]$14419 $4\xive0_pri$next[7:0]$14483 + assign $0\xive10_pri$next[7:0]$14420 $4\xive10_pri$next[7:0]$14484 + assign $0\xive11_pri$next[7:0]$14421 $4\xive11_pri$next[7:0]$14485 + assign $0\xive12_pri$next[7:0]$14422 $4\xive12_pri$next[7:0]$14486 + assign $0\xive13_pri$next[7:0]$14423 $4\xive13_pri$next[7:0]$14487 + assign $0\xive14_pri$next[7:0]$14424 $4\xive14_pri$next[7:0]$14488 + assign $0\xive15_pri$next[7:0]$14425 $4\xive15_pri$next[7:0]$14489 + assign $0\xive1_pri$next[7:0]$14426 $4\xive1_pri$next[7:0]$14490 + assign $0\xive2_pri$next[7:0]$14427 $4\xive2_pri$next[7:0]$14491 + assign $0\xive3_pri$next[7:0]$14428 $4\xive3_pri$next[7:0]$14492 + assign $0\xive4_pri$next[7:0]$14429 $4\xive4_pri$next[7:0]$14493 + assign $0\xive5_pri$next[7:0]$14430 $4\xive5_pri$next[7:0]$14494 + assign $0\xive6_pri$next[7:0]$14431 $4\xive6_pri$next[7:0]$14495 + assign $0\xive7_pri$next[7:0]$14432 $4\xive7_pri$next[7:0]$14496 + assign $0\xive8_pri$next[7:0]$14433 $4\xive8_pri$next[7:0]$14497 + assign $0\xive9_pri$next[7:0]$14434 $4\xive9_pri$next[7:0]$14498 + attribute \src "libresoc.v:203241.5-203241.29" switch \initial - attribute \src "libresoc.v:203644.9-203644.17" + attribute \src "libresoc.v:203241.9-203241.17" case 1'1 case end @@ -390121,22 +389260,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$14507 $2\xive0_pri$next[7:0]$14523 - assign $1\xive10_pri$next[7:0]$14508 $2\xive10_pri$next[7:0]$14524 - assign $1\xive11_pri$next[7:0]$14509 $2\xive11_pri$next[7:0]$14525 - assign $1\xive12_pri$next[7:0]$14510 $2\xive12_pri$next[7:0]$14526 - assign $1\xive13_pri$next[7:0]$14511 $2\xive13_pri$next[7:0]$14527 - assign $1\xive14_pri$next[7:0]$14512 $2\xive14_pri$next[7:0]$14528 - assign $1\xive15_pri$next[7:0]$14513 $2\xive15_pri$next[7:0]$14529 - assign $1\xive1_pri$next[7:0]$14514 $2\xive1_pri$next[7:0]$14530 - assign $1\xive2_pri$next[7:0]$14515 $2\xive2_pri$next[7:0]$14531 - assign $1\xive3_pri$next[7:0]$14516 $2\xive3_pri$next[7:0]$14532 - assign $1\xive4_pri$next[7:0]$14517 $2\xive4_pri$next[7:0]$14533 - assign $1\xive5_pri$next[7:0]$14518 $2\xive5_pri$next[7:0]$14534 - assign $1\xive6_pri$next[7:0]$14519 $2\xive6_pri$next[7:0]$14535 - assign $1\xive7_pri$next[7:0]$14520 $2\xive7_pri$next[7:0]$14536 - assign $1\xive8_pri$next[7:0]$14521 $2\xive8_pri$next[7:0]$14537 - assign $1\xive9_pri$next[7:0]$14522 $2\xive9_pri$next[7:0]$14538 + assign $1\xive0_pri$next[7:0]$14435 $2\xive0_pri$next[7:0]$14451 + assign $1\xive10_pri$next[7:0]$14436 $2\xive10_pri$next[7:0]$14452 + assign $1\xive11_pri$next[7:0]$14437 $2\xive11_pri$next[7:0]$14453 + assign $1\xive12_pri$next[7:0]$14438 $2\xive12_pri$next[7:0]$14454 + assign $1\xive13_pri$next[7:0]$14439 $2\xive13_pri$next[7:0]$14455 + assign $1\xive14_pri$next[7:0]$14440 $2\xive14_pri$next[7:0]$14456 + assign $1\xive15_pri$next[7:0]$14441 $2\xive15_pri$next[7:0]$14457 + assign $1\xive1_pri$next[7:0]$14442 $2\xive1_pri$next[7:0]$14458 + assign $1\xive2_pri$next[7:0]$14443 $2\xive2_pri$next[7:0]$14459 + assign $1\xive3_pri$next[7:0]$14444 $2\xive3_pri$next[7:0]$14460 + assign $1\xive4_pri$next[7:0]$14445 $2\xive4_pri$next[7:0]$14461 + assign $1\xive5_pri$next[7:0]$14446 $2\xive5_pri$next[7:0]$14462 + assign $1\xive6_pri$next[7:0]$14447 $2\xive6_pri$next[7:0]$14463 + assign $1\xive7_pri$next[7:0]$14448 $2\xive7_pri$next[7:0]$14464 + assign $1\xive8_pri$next[7:0]$14449 $2\xive8_pri$next[7:0]$14465 + assign $1\xive9_pri$next[7:0]$14450 $2\xive9_pri$next[7:0]$14466 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -390157,381 +389296,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$14523 $3\xive0_pri$next[7:0]$14539 - assign $2\xive10_pri$next[7:0]$14524 $3\xive10_pri$next[7:0]$14540 - assign $2\xive11_pri$next[7:0]$14525 $3\xive11_pri$next[7:0]$14541 - assign $2\xive12_pri$next[7:0]$14526 $3\xive12_pri$next[7:0]$14542 - assign $2\xive13_pri$next[7:0]$14527 $3\xive13_pri$next[7:0]$14543 - assign $2\xive14_pri$next[7:0]$14528 $3\xive14_pri$next[7:0]$14544 - assign $2\xive15_pri$next[7:0]$14529 $3\xive15_pri$next[7:0]$14545 - assign $2\xive1_pri$next[7:0]$14530 $3\xive1_pri$next[7:0]$14546 - assign $2\xive2_pri$next[7:0]$14531 $3\xive2_pri$next[7:0]$14547 - assign $2\xive3_pri$next[7:0]$14532 $3\xive3_pri$next[7:0]$14548 - assign $2\xive4_pri$next[7:0]$14533 $3\xive4_pri$next[7:0]$14549 - assign $2\xive5_pri$next[7:0]$14534 $3\xive5_pri$next[7:0]$14550 - assign $2\xive6_pri$next[7:0]$14535 $3\xive6_pri$next[7:0]$14551 - assign $2\xive7_pri$next[7:0]$14536 $3\xive7_pri$next[7:0]$14552 - assign $2\xive8_pri$next[7:0]$14537 $3\xive8_pri$next[7:0]$14553 - assign $2\xive9_pri$next[7:0]$14538 $3\xive9_pri$next[7:0]$14554 + assign $2\xive0_pri$next[7:0]$14451 $3\xive0_pri$next[7:0]$14467 + assign $2\xive10_pri$next[7:0]$14452 $3\xive10_pri$next[7:0]$14468 + assign $2\xive11_pri$next[7:0]$14453 $3\xive11_pri$next[7:0]$14469 + assign $2\xive12_pri$next[7:0]$14454 $3\xive12_pri$next[7:0]$14470 + assign $2\xive13_pri$next[7:0]$14455 $3\xive13_pri$next[7:0]$14471 + assign $2\xive14_pri$next[7:0]$14456 $3\xive14_pri$next[7:0]$14472 + assign $2\xive15_pri$next[7:0]$14457 $3\xive15_pri$next[7:0]$14473 + assign $2\xive1_pri$next[7:0]$14458 $3\xive1_pri$next[7:0]$14474 + assign $2\xive2_pri$next[7:0]$14459 $3\xive2_pri$next[7:0]$14475 + assign $2\xive3_pri$next[7:0]$14460 $3\xive3_pri$next[7:0]$14476 + assign $2\xive4_pri$next[7:0]$14461 $3\xive4_pri$next[7:0]$14477 + assign $2\xive5_pri$next[7:0]$14462 $3\xive5_pri$next[7:0]$14478 + assign $2\xive6_pri$next[7:0]$14463 $3\xive6_pri$next[7:0]$14479 + assign $2\xive7_pri$next[7:0]$14464 $3\xive7_pri$next[7:0]$14480 + assign $2\xive8_pri$next[7:0]$14465 $3\xive8_pri$next[7:0]$14481 + assign $2\xive9_pri$next[7:0]$14466 $3\xive9_pri$next[7:0]$14482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive0_pri$next[7:0]$14539 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive0_pri$next[7:0]$14467 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive1_pri$next[7:0]$14546 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive1_pri$next[7:0]$14474 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive2_pri$next[7:0]$14547 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive2_pri$next[7:0]$14475 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive3_pri$next[7:0]$14548 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive3_pri$next[7:0]$14476 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive4_pri$next[7:0]$14549 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive4_pri$next[7:0]$14477 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive5_pri$next[7:0]$14550 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive5_pri$next[7:0]$14478 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive6_pri$next[7:0]$14551 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive6_pri$next[7:0]$14479 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive7_pri$next[7:0]$14552 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive7_pri$next[7:0]$14480 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive8_pri$next[7:0]$14553 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive8_pri$next[7:0]$14481 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14554 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14482 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive10_pri$next[7:0]$14540 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive10_pri$next[7:0]$14468 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive11_pri$next[7:0]$14541 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive11_pri$next[7:0]$14469 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive12_pri$next[7:0]$14542 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive12_pri$next[7:0]$14470 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive13_pri$next[7:0]$14543 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive13_pri$next[7:0]$14471 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive14_pri$next[7:0]$14544 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive14_pri$next[7:0]$14472 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri - assign $3\xive15_pri$next[7:0]$14545 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri + assign $3\xive15_pri$next[7:0]$14473 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$14539 \xive0_pri - assign $3\xive10_pri$next[7:0]$14540 \xive10_pri - assign $3\xive11_pri$next[7:0]$14541 \xive11_pri - assign $3\xive12_pri$next[7:0]$14542 \xive12_pri - assign $3\xive13_pri$next[7:0]$14543 \xive13_pri - assign $3\xive14_pri$next[7:0]$14544 \xive14_pri - assign $3\xive15_pri$next[7:0]$14545 \xive15_pri - assign $3\xive1_pri$next[7:0]$14546 \xive1_pri - assign $3\xive2_pri$next[7:0]$14547 \xive2_pri - assign $3\xive3_pri$next[7:0]$14548 \xive3_pri - assign $3\xive4_pri$next[7:0]$14549 \xive4_pri - assign $3\xive5_pri$next[7:0]$14550 \xive5_pri - assign $3\xive6_pri$next[7:0]$14551 \xive6_pri - assign $3\xive7_pri$next[7:0]$14552 \xive7_pri - assign $3\xive8_pri$next[7:0]$14553 \xive8_pri - assign $3\xive9_pri$next[7:0]$14554 \xive9_pri + assign $3\xive0_pri$next[7:0]$14467 \xive0_pri + assign $3\xive10_pri$next[7:0]$14468 \xive10_pri + assign $3\xive11_pri$next[7:0]$14469 \xive11_pri + assign $3\xive12_pri$next[7:0]$14470 \xive12_pri + assign $3\xive13_pri$next[7:0]$14471 \xive13_pri + assign $3\xive14_pri$next[7:0]$14472 \xive14_pri + assign $3\xive15_pri$next[7:0]$14473 \xive15_pri + assign $3\xive1_pri$next[7:0]$14474 \xive1_pri + assign $3\xive2_pri$next[7:0]$14475 \xive2_pri + assign $3\xive3_pri$next[7:0]$14476 \xive3_pri + assign $3\xive4_pri$next[7:0]$14477 \xive4_pri + assign $3\xive5_pri$next[7:0]$14478 \xive5_pri + assign $3\xive6_pri$next[7:0]$14479 \xive6_pri + assign $3\xive7_pri$next[7:0]$14480 \xive7_pri + assign $3\xive8_pri$next[7:0]$14481 \xive8_pri + assign $3\xive9_pri$next[7:0]$14482 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$14523 \xive0_pri - assign $2\xive10_pri$next[7:0]$14524 \xive10_pri - assign $2\xive11_pri$next[7:0]$14525 \xive11_pri - assign $2\xive12_pri$next[7:0]$14526 \xive12_pri - assign $2\xive13_pri$next[7:0]$14527 \xive13_pri - assign $2\xive14_pri$next[7:0]$14528 \xive14_pri - assign $2\xive15_pri$next[7:0]$14529 \xive15_pri - assign $2\xive1_pri$next[7:0]$14530 \xive1_pri - assign $2\xive2_pri$next[7:0]$14531 \xive2_pri - assign $2\xive3_pri$next[7:0]$14532 \xive3_pri - assign $2\xive4_pri$next[7:0]$14533 \xive4_pri - assign $2\xive5_pri$next[7:0]$14534 \xive5_pri - assign $2\xive6_pri$next[7:0]$14535 \xive6_pri - assign $2\xive7_pri$next[7:0]$14536 \xive7_pri - assign $2\xive8_pri$next[7:0]$14537 \xive8_pri - assign $2\xive9_pri$next[7:0]$14538 \xive9_pri + assign $2\xive0_pri$next[7:0]$14451 \xive0_pri + assign $2\xive10_pri$next[7:0]$14452 \xive10_pri + assign $2\xive11_pri$next[7:0]$14453 \xive11_pri + assign $2\xive12_pri$next[7:0]$14454 \xive12_pri + assign $2\xive13_pri$next[7:0]$14455 \xive13_pri + assign $2\xive14_pri$next[7:0]$14456 \xive14_pri + assign $2\xive15_pri$next[7:0]$14457 \xive15_pri + assign $2\xive1_pri$next[7:0]$14458 \xive1_pri + assign $2\xive2_pri$next[7:0]$14459 \xive2_pri + assign $2\xive3_pri$next[7:0]$14460 \xive3_pri + assign $2\xive4_pri$next[7:0]$14461 \xive4_pri + assign $2\xive5_pri$next[7:0]$14462 \xive5_pri + assign $2\xive6_pri$next[7:0]$14463 \xive6_pri + assign $2\xive7_pri$next[7:0]$14464 \xive7_pri + assign $2\xive8_pri$next[7:0]$14465 \xive8_pri + assign $2\xive9_pri$next[7:0]$14466 \xive9_pri end case - assign $1\xive0_pri$next[7:0]$14507 \xive0_pri - assign $1\xive10_pri$next[7:0]$14508 \xive10_pri - assign $1\xive11_pri$next[7:0]$14509 \xive11_pri - assign $1\xive12_pri$next[7:0]$14510 \xive12_pri - assign $1\xive13_pri$next[7:0]$14511 \xive13_pri - assign $1\xive14_pri$next[7:0]$14512 \xive14_pri - assign $1\xive15_pri$next[7:0]$14513 \xive15_pri - assign $1\xive1_pri$next[7:0]$14514 \xive1_pri - assign $1\xive2_pri$next[7:0]$14515 \xive2_pri - assign $1\xive3_pri$next[7:0]$14516 \xive3_pri - assign $1\xive4_pri$next[7:0]$14517 \xive4_pri - assign $1\xive5_pri$next[7:0]$14518 \xive5_pri - assign $1\xive6_pri$next[7:0]$14519 \xive6_pri - assign $1\xive7_pri$next[7:0]$14520 \xive7_pri - assign $1\xive8_pri$next[7:0]$14521 \xive8_pri - assign $1\xive9_pri$next[7:0]$14522 \xive9_pri + assign $1\xive0_pri$next[7:0]$14435 \xive0_pri + assign $1\xive10_pri$next[7:0]$14436 \xive10_pri + assign $1\xive11_pri$next[7:0]$14437 \xive11_pri + assign $1\xive12_pri$next[7:0]$14438 \xive12_pri + assign $1\xive13_pri$next[7:0]$14439 \xive13_pri + assign $1\xive14_pri$next[7:0]$14440 \xive14_pri + assign $1\xive15_pri$next[7:0]$14441 \xive15_pri + assign $1\xive1_pri$next[7:0]$14442 \xive1_pri + assign $1\xive2_pri$next[7:0]$14443 \xive2_pri + assign $1\xive3_pri$next[7:0]$14444 \xive3_pri + assign $1\xive4_pri$next[7:0]$14445 \xive4_pri + assign $1\xive5_pri$next[7:0]$14446 \xive5_pri + assign $1\xive6_pri$next[7:0]$14447 \xive6_pri + assign $1\xive7_pri$next[7:0]$14448 \xive7_pri + assign $1\xive8_pri$next[7:0]$14449 \xive8_pri + assign $1\xive9_pri$next[7:0]$14450 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -390553,66 +389692,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$14555 8'11111111 - assign $4\xive1_pri$next[7:0]$14562 8'11111111 - assign $4\xive2_pri$next[7:0]$14563 8'11111111 - assign $4\xive3_pri$next[7:0]$14564 8'11111111 - assign $4\xive4_pri$next[7:0]$14565 8'11111111 - assign $4\xive5_pri$next[7:0]$14566 8'11111111 - assign $4\xive6_pri$next[7:0]$14567 8'11111111 - assign $4\xive7_pri$next[7:0]$14568 8'11111111 - assign $4\xive8_pri$next[7:0]$14569 8'11111111 - assign $4\xive9_pri$next[7:0]$14570 8'11111111 - assign $4\xive10_pri$next[7:0]$14556 8'11111111 - assign $4\xive11_pri$next[7:0]$14557 8'11111111 - assign $4\xive12_pri$next[7:0]$14558 8'11111111 - assign $4\xive13_pri$next[7:0]$14559 8'11111111 - assign $4\xive14_pri$next[7:0]$14560 8'11111111 - assign $4\xive15_pri$next[7:0]$14561 8'11111111 + assign $4\xive0_pri$next[7:0]$14483 8'11111111 + assign $4\xive1_pri$next[7:0]$14490 8'11111111 + assign $4\xive2_pri$next[7:0]$14491 8'11111111 + assign $4\xive3_pri$next[7:0]$14492 8'11111111 + assign $4\xive4_pri$next[7:0]$14493 8'11111111 + assign $4\xive5_pri$next[7:0]$14494 8'11111111 + assign $4\xive6_pri$next[7:0]$14495 8'11111111 + assign $4\xive7_pri$next[7:0]$14496 8'11111111 + assign $4\xive8_pri$next[7:0]$14497 8'11111111 + assign $4\xive9_pri$next[7:0]$14498 8'11111111 + assign $4\xive10_pri$next[7:0]$14484 8'11111111 + assign $4\xive11_pri$next[7:0]$14485 8'11111111 + assign $4\xive12_pri$next[7:0]$14486 8'11111111 + assign $4\xive13_pri$next[7:0]$14487 8'11111111 + assign $4\xive14_pri$next[7:0]$14488 8'11111111 + assign $4\xive15_pri$next[7:0]$14489 8'11111111 case - assign $4\xive0_pri$next[7:0]$14555 $1\xive0_pri$next[7:0]$14507 - assign $4\xive10_pri$next[7:0]$14556 $1\xive10_pri$next[7:0]$14508 - assign $4\xive11_pri$next[7:0]$14557 $1\xive11_pri$next[7:0]$14509 - assign $4\xive12_pri$next[7:0]$14558 $1\xive12_pri$next[7:0]$14510 - assign $4\xive13_pri$next[7:0]$14559 $1\xive13_pri$next[7:0]$14511 - assign $4\xive14_pri$next[7:0]$14560 $1\xive14_pri$next[7:0]$14512 - assign $4\xive15_pri$next[7:0]$14561 $1\xive15_pri$next[7:0]$14513 - assign $4\xive1_pri$next[7:0]$14562 $1\xive1_pri$next[7:0]$14514 - assign $4\xive2_pri$next[7:0]$14563 $1\xive2_pri$next[7:0]$14515 - assign $4\xive3_pri$next[7:0]$14564 $1\xive3_pri$next[7:0]$14516 - assign $4\xive4_pri$next[7:0]$14565 $1\xive4_pri$next[7:0]$14517 - assign $4\xive5_pri$next[7:0]$14566 $1\xive5_pri$next[7:0]$14518 - assign $4\xive6_pri$next[7:0]$14567 $1\xive6_pri$next[7:0]$14519 - assign $4\xive7_pri$next[7:0]$14568 $1\xive7_pri$next[7:0]$14520 - assign $4\xive8_pri$next[7:0]$14569 $1\xive8_pri$next[7:0]$14521 - assign $4\xive9_pri$next[7:0]$14570 $1\xive9_pri$next[7:0]$14522 + assign $4\xive0_pri$next[7:0]$14483 $1\xive0_pri$next[7:0]$14435 + assign $4\xive10_pri$next[7:0]$14484 $1\xive10_pri$next[7:0]$14436 + assign $4\xive11_pri$next[7:0]$14485 $1\xive11_pri$next[7:0]$14437 + assign $4\xive12_pri$next[7:0]$14486 $1\xive12_pri$next[7:0]$14438 + assign $4\xive13_pri$next[7:0]$14487 $1\xive13_pri$next[7:0]$14439 + assign $4\xive14_pri$next[7:0]$14488 $1\xive14_pri$next[7:0]$14440 + assign $4\xive15_pri$next[7:0]$14489 $1\xive15_pri$next[7:0]$14441 + assign $4\xive1_pri$next[7:0]$14490 $1\xive1_pri$next[7:0]$14442 + assign $4\xive2_pri$next[7:0]$14491 $1\xive2_pri$next[7:0]$14443 + assign $4\xive3_pri$next[7:0]$14492 $1\xive3_pri$next[7:0]$14444 + assign $4\xive4_pri$next[7:0]$14493 $1\xive4_pri$next[7:0]$14445 + assign $4\xive5_pri$next[7:0]$14494 $1\xive5_pri$next[7:0]$14446 + assign $4\xive6_pri$next[7:0]$14495 $1\xive6_pri$next[7:0]$14447 + assign $4\xive7_pri$next[7:0]$14496 $1\xive7_pri$next[7:0]$14448 + assign $4\xive8_pri$next[7:0]$14497 $1\xive8_pri$next[7:0]$14449 + assign $4\xive9_pri$next[7:0]$14498 $1\xive9_pri$next[7:0]$14450 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$14491 - update \xive10_pri$next $0\xive10_pri$next[7:0]$14492 - update \xive11_pri$next $0\xive11_pri$next[7:0]$14493 - update \xive12_pri$next $0\xive12_pri$next[7:0]$14494 - update \xive13_pri$next $0\xive13_pri$next[7:0]$14495 - update \xive14_pri$next $0\xive14_pri$next[7:0]$14496 - update \xive15_pri$next $0\xive15_pri$next[7:0]$14497 - update \xive1_pri$next $0\xive1_pri$next[7:0]$14498 - update \xive2_pri$next $0\xive2_pri$next[7:0]$14499 - update \xive3_pri$next $0\xive3_pri$next[7:0]$14500 - update \xive4_pri$next $0\xive4_pri$next[7:0]$14501 - update \xive5_pri$next $0\xive5_pri$next[7:0]$14502 - update \xive6_pri$next $0\xive6_pri$next[7:0]$14503 - update \xive7_pri$next $0\xive7_pri$next[7:0]$14504 - update \xive8_pri$next $0\xive8_pri$next[7:0]$14505 - update \xive9_pri$next $0\xive9_pri$next[7:0]$14506 + update \xive0_pri$next $0\xive0_pri$next[7:0]$14419 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14420 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14421 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14422 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14423 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14424 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14425 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14426 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14427 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14428 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14429 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14430 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14431 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14432 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14433 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14434 end - attribute \src "libresoc.v:203729.3-203738.6" - process $proc$libresoc.v:203729$14571 + attribute \src "libresoc.v:203326.3-203335.6" + process $proc$libresoc.v:203326$14499 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:203730.5-203730.29" + attribute \src "libresoc.v:203327.5-203327.29" switch \initial - attribute \src "libresoc.v:203730.9-203730.17" + attribute \src "libresoc.v:203327.9-203327.17" case 1'1 case end @@ -390628,14 +389767,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:203739.3-203748.6" - process $proc$libresoc.v:203739$14572 + attribute \src "libresoc.v:203336.3-203345.6" + process $proc$libresoc.v:203336$14500 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:203740.5-203740.29" + attribute \src "libresoc.v:203337.5-203337.29" switch \initial - attribute \src "libresoc.v:203740.9-203740.17" + attribute \src "libresoc.v:203337.9-203337.17" case 1'1 case end @@ -390651,14 +389790,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:203749.3-203758.6" - process $proc$libresoc.v:203749$14573 + attribute \src "libresoc.v:203346.3-203355.6" + process $proc$libresoc.v:203346$14501 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:203750.5-203750.29" + attribute \src "libresoc.v:203347.5-203347.29" switch \initial - attribute \src "libresoc.v:203750.9-203750.17" + attribute \src "libresoc.v:203347.9-203347.17" case 1'1 case end @@ -390674,14 +389813,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:203759.3-203768.6" - process $proc$libresoc.v:203759$14574 + attribute \src "libresoc.v:203356.3-203365.6" + process $proc$libresoc.v:203356$14502 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:203760.5-203760.29" + attribute \src "libresoc.v:203357.5-203357.29" switch \initial - attribute \src "libresoc.v:203760.9-203760.17" + attribute \src "libresoc.v:203357.9-203357.17" case 1'1 case end @@ -390697,14 +389836,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:203769.3-203778.6" - process $proc$libresoc.v:203769$14575 + attribute \src "libresoc.v:203366.3-203375.6" + process $proc$libresoc.v:203366$14503 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:203770.5-203770.29" + attribute \src "libresoc.v:203367.5-203367.29" switch \initial - attribute \src "libresoc.v:203770.9-203770.17" + attribute \src "libresoc.v:203367.9-203367.17" case 1'1 case end @@ -390720,14 +389859,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:203779.3-203788.6" - process $proc$libresoc.v:203779$14576 + attribute \src "libresoc.v:203376.3-203385.6" + process $proc$libresoc.v:203376$14504 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:203780.5-203780.29" + attribute \src "libresoc.v:203377.5-203377.29" switch \initial - attribute \src "libresoc.v:203780.9-203780.17" + attribute \src "libresoc.v:203377.9-203377.17" case 1'1 case end @@ -390743,14 +389882,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:203789.3-203798.6" - process $proc$libresoc.v:203789$14577 + attribute \src "libresoc.v:203386.3-203395.6" + process $proc$libresoc.v:203386$14505 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:203790.5-203790.29" + attribute \src "libresoc.v:203387.5-203387.29" switch \initial - attribute \src "libresoc.v:203790.9-203790.17" + attribute \src "libresoc.v:203387.9-203387.17" case 1'1 case end @@ -390766,14 +389905,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:203799.3-203808.6" - process $proc$libresoc.v:203799$14578 + attribute \src "libresoc.v:203396.3-203405.6" + process $proc$libresoc.v:203396$14506 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:203800.5-203800.29" + attribute \src "libresoc.v:203397.5-203397.29" switch \initial - attribute \src "libresoc.v:203800.9-203800.17" + attribute \src "libresoc.v:203397.9-203397.17" case 1'1 case end @@ -390789,14 +389928,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:203809.3-203818.6" - process $proc$libresoc.v:203809$14579 + attribute \src "libresoc.v:203406.3-203415.6" + process $proc$libresoc.v:203406$14507 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:203810.5-203810.29" + attribute \src "libresoc.v:203407.5-203407.29" switch \initial - attribute \src "libresoc.v:203810.9-203810.17" + attribute \src "libresoc.v:203407.9-203407.17" case 1'1 case end @@ -390812,14 +389951,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:203819.3-203827.6" - process $proc$libresoc.v:203819$14580 + attribute \src "libresoc.v:203416.3-203424.6" + process $proc$libresoc.v:203416$14508 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$14581 $1\int_level_l$next[15:0]$14582 - attribute \src "libresoc.v:203820.5-203820.29" + assign $0\int_level_l$next[15:0]$14509 $1\int_level_l$next[15:0]$14510 + attribute \src "libresoc.v:203417.5-203417.29" switch \initial - attribute \src "libresoc.v:203820.9-203820.17" + attribute \src "libresoc.v:203417.9-203417.17" case 1'1 case end @@ -390828,21 +389967,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$14582 16'0000000000000000 + assign $1\int_level_l$next[15:0]$14510 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$14582 \int_level_i + assign $1\int_level_l$next[15:0]$14510 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$14581 + update \int_level_l$next $0\int_level_l$next[15:0]$14509 end - attribute \src "libresoc.v:203828.3-203837.6" - process $proc$libresoc.v:203828$14583 + attribute \src "libresoc.v:203425.3-203434.6" + process $proc$libresoc.v:203425$14511 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:203829.5-203829.29" + attribute \src "libresoc.v:203426.5-203426.29" switch \initial - attribute \src "libresoc.v:203829.9-203829.17" + attribute \src "libresoc.v:203426.9-203426.17" case 1'1 case end @@ -390858,14 +389997,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:203838.3-203847.6" - process $proc$libresoc.v:203838$14584 + attribute \src "libresoc.v:203435.3-203444.6" + process $proc$libresoc.v:203435$14512 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:203839.5-203839.29" + attribute \src "libresoc.v:203436.5-203436.29" switch \initial - attribute \src "libresoc.v:203839.9-203839.17" + attribute \src "libresoc.v:203436.9-203436.17" case 1'1 case end @@ -390881,14 +390020,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:203848.3-203857.6" - process $proc$libresoc.v:203848$14585 + attribute \src "libresoc.v:203445.3-203454.6" + process $proc$libresoc.v:203445$14513 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:203849.5-203849.29" + attribute \src "libresoc.v:203446.5-203446.29" switch \initial - attribute \src "libresoc.v:203849.9-203849.17" + attribute \src "libresoc.v:203446.9-203446.17" case 1'1 case end @@ -390904,14 +390043,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:203858.3-203867.6" - process $proc$libresoc.v:203858$14586 + attribute \src "libresoc.v:203455.3-203464.6" + process $proc$libresoc.v:203455$14514 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:203859.5-203859.29" + attribute \src "libresoc.v:203456.5-203456.29" switch \initial - attribute \src "libresoc.v:203859.9-203859.17" + attribute \src "libresoc.v:203456.9-203456.17" case 1'1 case end @@ -390927,14 +390066,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:203868.3-203877.6" - process $proc$libresoc.v:203868$14587 + attribute \src "libresoc.v:203465.3-203474.6" + process $proc$libresoc.v:203465$14515 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:203869.5-203869.29" + attribute \src "libresoc.v:203466.5-203466.29" switch \initial - attribute \src "libresoc.v:203869.9-203869.17" + attribute \src "libresoc.v:203466.9-203466.17" case 1'1 case end @@ -390950,14 +390089,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:203878.3-203887.6" - process $proc$libresoc.v:203878$14588 + attribute \src "libresoc.v:203475.3-203484.6" + process $proc$libresoc.v:203475$14516 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:203879.5-203879.29" + attribute \src "libresoc.v:203476.5-203476.29" switch \initial - attribute \src "libresoc.v:203879.9-203879.17" + attribute \src "libresoc.v:203476.9-203476.17" case 1'1 case end @@ -390973,14 +390112,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:203888.3-203897.6" - process $proc$libresoc.v:203888$14589 + attribute \src "libresoc.v:203485.3-203494.6" + process $proc$libresoc.v:203485$14517 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:203889.5-203889.29" + attribute \src "libresoc.v:203486.5-203486.29" switch \initial - attribute \src "libresoc.v:203889.9-203889.17" + attribute \src "libresoc.v:203486.9-203486.17" case 1'1 case end @@ -390996,14 +390135,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:203898.3-203907.6" - process $proc$libresoc.v:203898$14590 + attribute \src "libresoc.v:203495.3-203504.6" + process $proc$libresoc.v:203495$14518 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:203899.5-203899.29" + attribute \src "libresoc.v:203496.5-203496.29" switch \initial - attribute \src "libresoc.v:203899.9-203899.17" + attribute \src "libresoc.v:203496.9-203496.17" case 1'1 case end @@ -391019,14 +390158,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:203908.3-203917.6" - process $proc$libresoc.v:203908$14591 + attribute \src "libresoc.v:203505.3-203514.6" + process $proc$libresoc.v:203505$14519 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:203909.5-203909.29" + attribute \src "libresoc.v:203506.5-203506.29" switch \initial - attribute \src "libresoc.v:203909.9-203909.17" + attribute \src "libresoc.v:203506.9-203506.17" case 1'1 case end @@ -391042,14 +390181,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:203918.3-203927.6" - process $proc$libresoc.v:203918$14592 + attribute \src "libresoc.v:203515.3-203524.6" + process $proc$libresoc.v:203515$14520 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:203919.5-203919.29" + attribute \src "libresoc.v:203516.5-203516.29" switch \initial - attribute \src "libresoc.v:203919.9-203919.17" + attribute \src "libresoc.v:203516.9-203516.17" case 1'1 case end @@ -391065,14 +390204,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:203928.3-203937.6" - process $proc$libresoc.v:203928$14593 + attribute \src "libresoc.v:203525.3-203534.6" + process $proc$libresoc.v:203525$14521 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:203929.5-203929.29" + attribute \src "libresoc.v:203526.5-203526.29" switch \initial - attribute \src "libresoc.v:203929.9-203929.17" + attribute \src "libresoc.v:203526.9-203526.17" case 1'1 case end @@ -391088,14 +390227,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:203938.3-203947.6" - process $proc$libresoc.v:203938$14594 + attribute \src "libresoc.v:203535.3-203544.6" + process $proc$libresoc.v:203535$14522 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:203939.5-203939.29" + attribute \src "libresoc.v:203536.5-203536.29" switch \initial - attribute \src "libresoc.v:203939.9-203939.17" + attribute \src "libresoc.v:203536.9-203536.17" case 1'1 case end @@ -391111,14 +390250,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:203948.3-203957.6" - process $proc$libresoc.v:203948$14595 + attribute \src "libresoc.v:203545.3-203554.6" + process $proc$libresoc.v:203545$14523 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:203949.5-203949.29" + attribute \src "libresoc.v:203546.5-203546.29" switch \initial - attribute \src "libresoc.v:203949.9-203949.17" + attribute \src "libresoc.v:203546.9-203546.17" case 1'1 case end @@ -391134,14 +390273,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:203958.3-203967.6" - process $proc$libresoc.v:203958$14596 + attribute \src "libresoc.v:203555.3-203564.6" + process $proc$libresoc.v:203555$14524 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:203959.5-203959.29" + attribute \src "libresoc.v:203556.5-203556.29" switch \initial - attribute \src "libresoc.v:203959.9-203959.17" + attribute \src "libresoc.v:203556.9-203556.17" case 1'1 case end @@ -391157,14 +390296,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:203968.3-203977.6" - process $proc$libresoc.v:203968$14597 + attribute \src "libresoc.v:203565.3-203574.6" + process $proc$libresoc.v:203565$14525 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:203969.5-203969.29" + attribute \src "libresoc.v:203566.5-203566.29" switch \initial - attribute \src "libresoc.v:203969.9-203969.17" + attribute \src "libresoc.v:203566.9-203566.17" case 1'1 case end @@ -391180,14 +390319,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:203978.3-203987.6" - process $proc$libresoc.v:203978$14598 + attribute \src "libresoc.v:203575.3-203584.6" + process $proc$libresoc.v:203575$14526 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:203979.5-203979.29" + attribute \src "libresoc.v:203576.5-203576.29" switch \initial - attribute \src "libresoc.v:203979.9-203979.17" + attribute \src "libresoc.v:203576.9-203576.17" case 1'1 case end @@ -391203,14 +390342,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:203988.3-203997.6" - process $proc$libresoc.v:203988$14599 + attribute \src "libresoc.v:203585.3-203594.6" + process $proc$libresoc.v:203585$14527 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:203989.5-203989.29" + attribute \src "libresoc.v:203586.5-203586.29" switch \initial - attribute \src "libresoc.v:203989.9-203989.17" + attribute \src "libresoc.v:203586.9-203586.17" case 1'1 case end @@ -391226,14 +390365,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:203998.3-204007.6" - process $proc$libresoc.v:203998$14600 + attribute \src "libresoc.v:203595.3-203604.6" + process $proc$libresoc.v:203595$14528 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:203999.5-203999.29" + attribute \src "libresoc.v:203596.5-203596.29" switch \initial - attribute \src "libresoc.v:203999.9-203999.17" + attribute \src "libresoc.v:203596.9-203596.17" case 1'1 case end @@ -391249,14 +390388,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:204008.3-204017.6" - process $proc$libresoc.v:204008$14601 + attribute \src "libresoc.v:203605.3-203614.6" + process $proc$libresoc.v:203605$14529 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:204009.5-204009.29" + attribute \src "libresoc.v:203606.5-203606.29" switch \initial - attribute \src "libresoc.v:204009.9-204009.17" + attribute \src "libresoc.v:203606.9-203606.17" case 1'1 case end @@ -391272,14 +390411,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:204018.3-204027.6" - process $proc$libresoc.v:204018$14602 + attribute \src "libresoc.v:203615.3-203624.6" + process $proc$libresoc.v:203615$14530 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:204019.5-204019.29" + attribute \src "libresoc.v:203616.5-203616.29" switch \initial - attribute \src "libresoc.v:204019.9-204019.17" + attribute \src "libresoc.v:203616.9-203616.17" case 1'1 case end @@ -391295,14 +390434,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:204028.3-204077.6" - process $proc$libresoc.v:204028$14603 + attribute \src "libresoc.v:203625.3-203674.6" + process $proc$libresoc.v:203625$14531 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:204029.5-204029.29" + attribute \src "libresoc.v:203626.5-203626.29" switch \initial - attribute \src "libresoc.v:204029.9-204029.17" + attribute \src "libresoc.v:203626.9-203626.17" case 1'1 case end @@ -391395,14 +390534,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:204078.3-204087.6" - process $proc$libresoc.v:204078$14604 + attribute \src "libresoc.v:203675.3-203684.6" + process $proc$libresoc.v:203675$14532 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:204079.5-204079.29" + attribute \src "libresoc.v:203676.5-203676.29" switch \initial - attribute \src "libresoc.v:204079.9-204079.17" + attribute \src "libresoc.v:203676.9-203676.17" case 1'1 case end @@ -391418,14 +390557,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:204088.3-204097.6" - process $proc$libresoc.v:204088$14605 + attribute \src "libresoc.v:203685.3-203694.6" + process $proc$libresoc.v:203685$14533 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:204089.5-204089.29" + attribute \src "libresoc.v:203686.5-203686.29" switch \initial - attribute \src "libresoc.v:204089.9-204089.17" + attribute \src "libresoc.v:203686.9-203686.17" case 1'1 case end @@ -391441,14 +390580,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:204098.3-204107.6" - process $proc$libresoc.v:204098$14606 + attribute \src "libresoc.v:203695.3-203704.6" + process $proc$libresoc.v:203695$14534 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:204099.5-204099.29" + attribute \src "libresoc.v:203696.5-203696.29" switch \initial - attribute \src "libresoc.v:204099.9-204099.17" + attribute \src "libresoc.v:203696.9-203696.17" case 1'1 case end @@ -391464,14 +390603,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:204108.3-204117.6" - process $proc$libresoc.v:204108$14607 + attribute \src "libresoc.v:203705.3-203714.6" + process $proc$libresoc.v:203705$14535 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:204109.5-204109.29" + attribute \src "libresoc.v:203706.5-203706.29" switch \initial - attribute \src "libresoc.v:204109.9-204109.17" + attribute \src "libresoc.v:203706.9-203706.17" case 1'1 case end @@ -391487,14 +390626,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:204118.3-204126.6" - process $proc$libresoc.v:204118$14608 + attribute \src "libresoc.v:203715.3-203723.6" + process $proc$libresoc.v:203715$14536 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$14609 $1\ics_wb__dat_r$next[31:0]$14610 - attribute \src "libresoc.v:204119.5-204119.29" + assign $0\ics_wb__dat_r$next[31:0]$14537 $1\ics_wb__dat_r$next[31:0]$14538 + attribute \src "libresoc.v:203716.5-203716.29" switch \initial - attribute \src "libresoc.v:204119.9-204119.17" + attribute \src "libresoc.v:203716.9-203716.17" case 1'1 case end @@ -391503,21 +390642,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$14610 0 + assign $1\ics_wb__dat_r$next[31:0]$14538 0 case - assign $1\ics_wb__dat_r$next[31:0]$14610 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$14538 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14609 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14537 end - attribute \src "libresoc.v:204127.3-204135.6" - process $proc$libresoc.v:204127$14611 + attribute \src "libresoc.v:203724.3-203732.6" + process $proc$libresoc.v:203724$14539 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$14612 $1\ics_wb__ack$next[0:0]$14613 - attribute \src "libresoc.v:204128.5-204128.29" + assign $0\ics_wb__ack$next[0:0]$14540 $1\ics_wb__ack$next[0:0]$14541 + attribute \src "libresoc.v:203725.5-203725.29" switch \initial - attribute \src "libresoc.v:204128.9-204128.17" + attribute \src "libresoc.v:203725.9-203725.17" case 1'1 case end @@ -391526,116 +390665,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$14613 1'0 - case - assign $1\ics_wb__ack$next[0:0]$14613 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14612 - end - connect \$7 $ternary$libresoc.v:203498$14366_Y - connect \$99 $lt$libresoc.v:203499$14367_Y - connect \$101 $and$libresoc.v:203500$14368_Y - connect \$103 $lt$libresoc.v:203501$14369_Y - connect \$105 $and$libresoc.v:203502$14370_Y - connect \$107 $lt$libresoc.v:203503$14371_Y - connect \$109 $and$libresoc.v:203504$14372_Y - connect \$111 $lt$libresoc.v:203505$14373_Y - connect \$113 $and$libresoc.v:203506$14374_Y - connect \$115 $lt$libresoc.v:203507$14375_Y - connect \$117 $and$libresoc.v:203508$14376_Y - connect \$119 $lt$libresoc.v:203509$14377_Y - connect \$121 $and$libresoc.v:203510$14378_Y - connect \$123 $lt$libresoc.v:203511$14379_Y - connect \$125 $and$libresoc.v:203512$14380_Y - connect \$127 $lt$libresoc.v:203513$14381_Y - connect \$12 $eq$libresoc.v:203514$14382_Y - connect \$129 $and$libresoc.v:203515$14383_Y - connect \$131 $lt$libresoc.v:203516$14384_Y - connect \$133 $and$libresoc.v:203517$14385_Y - connect \$135 $lt$libresoc.v:203518$14386_Y - connect \$137 $and$libresoc.v:203519$14387_Y - connect \$11 $ternary$libresoc.v:203520$14388_Y - connect \$139 $lt$libresoc.v:203521$14389_Y - connect \$141 $and$libresoc.v:203522$14390_Y - connect \$143 $lt$libresoc.v:203523$14391_Y - connect \$145 $and$libresoc.v:203524$14392_Y - connect \$147 $lt$libresoc.v:203525$14393_Y - connect \$149 $and$libresoc.v:203526$14394_Y - connect \$151 $lt$libresoc.v:203527$14395_Y - connect \$153 $and$libresoc.v:203528$14396_Y - connect \$155 $lt$libresoc.v:203529$14397_Y - connect \$157 $and$libresoc.v:203530$14398_Y - connect \$159 $lt$libresoc.v:203531$14399_Y - connect \$161 $and$libresoc.v:203532$14400_Y - connect \$163 $lt$libresoc.v:203533$14401_Y - connect \$165 $and$libresoc.v:203534$14402_Y - connect \$167 $lt$libresoc.v:203535$14403_Y - connect \$16 $eq$libresoc.v:203536$14404_Y - connect \$169 $and$libresoc.v:203537$14405_Y - connect \$171 $lt$libresoc.v:203538$14406_Y - connect \$173 $and$libresoc.v:203539$14407_Y - connect \$175 $lt$libresoc.v:203540$14408_Y - connect \$177 $and$libresoc.v:203541$14409_Y - connect \$15 $ternary$libresoc.v:203542$14410_Y - connect \$179 $lt$libresoc.v:203543$14411_Y - connect \$181 $and$libresoc.v:203544$14412_Y - connect \$183 $lt$libresoc.v:203545$14413_Y - connect \$185 $and$libresoc.v:203546$14414_Y - connect \$187 $lt$libresoc.v:203547$14415_Y - connect \$189 $and$libresoc.v:203548$14416_Y - connect \$191 $lt$libresoc.v:203549$14417_Y - connect \$193 $and$libresoc.v:203550$14418_Y - connect \$195 $lt$libresoc.v:203551$14419_Y - connect \$197 $and$libresoc.v:203552$14420_Y - connect \$1 $eq$libresoc.v:203553$14421_Y - connect \$199 $lt$libresoc.v:203554$14422_Y - connect \$201 $and$libresoc.v:203555$14423_Y - connect \$204 $eq$libresoc.v:203556$14424_Y - connect \$203 $ternary$libresoc.v:203557$14425_Y - connect \$20 $eq$libresoc.v:203558$14426_Y - connect \$19 $ternary$libresoc.v:203559$14427_Y - connect \$24 $eq$libresoc.v:203560$14428_Y - connect \$23 $ternary$libresoc.v:203561$14429_Y - connect \$28 $eq$libresoc.v:203562$14430_Y - connect \$27 $ternary$libresoc.v:203563$14431_Y - connect \$32 $eq$libresoc.v:203564$14432_Y - connect \$31 $ternary$libresoc.v:203565$14433_Y - connect \$36 $eq$libresoc.v:203566$14434_Y - connect \$35 $ternary$libresoc.v:203567$14435_Y - connect \$3 $eq$libresoc.v:203568$14436_Y - connect \$40 $eq$libresoc.v:203569$14437_Y - connect \$39 $ternary$libresoc.v:203570$14438_Y - connect \$44 $eq$libresoc.v:203571$14439_Y - connect \$43 $ternary$libresoc.v:203572$14440_Y - connect \$48 $eq$libresoc.v:203573$14441_Y - connect \$47 $ternary$libresoc.v:203574$14442_Y - connect \$52 $eq$libresoc.v:203575$14443_Y - connect \$51 $ternary$libresoc.v:203576$14444_Y - connect \$56 $eq$libresoc.v:203577$14445_Y - connect \$55 $ternary$libresoc.v:203578$14446_Y - connect \$5 $and$libresoc.v:203579$14447_Y - connect \$60 $eq$libresoc.v:203580$14448_Y - connect \$59 $ternary$libresoc.v:203581$14449_Y - connect \$64 $eq$libresoc.v:203582$14450_Y - connect \$63 $ternary$libresoc.v:203583$14451_Y - connect \$68 $eq$libresoc.v:203584$14452_Y - connect \$67 $ternary$libresoc.v:203585$14453_Y - connect \$71 $shr$libresoc.v:203586$14454_Y [0] - connect \$73 $and$libresoc.v:203587$14455_Y - connect \$75 $lt$libresoc.v:203588$14456_Y - connect \$77 $and$libresoc.v:203589$14457_Y - connect \$79 $lt$libresoc.v:203590$14458_Y - connect \$81 $and$libresoc.v:203591$14459_Y - connect \$83 $lt$libresoc.v:203592$14460_Y - connect \$85 $and$libresoc.v:203593$14461_Y - connect \$87 $lt$libresoc.v:203594$14462_Y - connect \$8 $eq$libresoc.v:203595$14463_Y - connect \$89 $and$libresoc.v:203596$14464_Y - connect \$91 $lt$libresoc.v:203597$14465_Y - connect \$93 $and$libresoc.v:203598$14466_Y - connect \$95 $lt$libresoc.v:203599$14467_Y - connect \$97 $and$libresoc.v:203600$14468_Y + assign $1\ics_wb__ack$next[0:0]$14541 1'0 + case + assign $1\ics_wb__ack$next[0:0]$14541 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14540 + end + connect \$7 $ternary$libresoc.v:203095$14294_Y + connect \$99 $lt$libresoc.v:203096$14295_Y + connect \$101 $and$libresoc.v:203097$14296_Y + connect \$103 $lt$libresoc.v:203098$14297_Y + connect \$105 $and$libresoc.v:203099$14298_Y + connect \$107 $lt$libresoc.v:203100$14299_Y + connect \$109 $and$libresoc.v:203101$14300_Y + connect \$111 $lt$libresoc.v:203102$14301_Y + connect \$113 $and$libresoc.v:203103$14302_Y + connect \$115 $lt$libresoc.v:203104$14303_Y + connect \$117 $and$libresoc.v:203105$14304_Y + connect \$119 $lt$libresoc.v:203106$14305_Y + connect \$121 $and$libresoc.v:203107$14306_Y + connect \$123 $lt$libresoc.v:203108$14307_Y + connect \$125 $and$libresoc.v:203109$14308_Y + connect \$127 $lt$libresoc.v:203110$14309_Y + connect \$12 $eq$libresoc.v:203111$14310_Y + connect \$129 $and$libresoc.v:203112$14311_Y + connect \$131 $lt$libresoc.v:203113$14312_Y + connect \$133 $and$libresoc.v:203114$14313_Y + connect \$135 $lt$libresoc.v:203115$14314_Y + connect \$137 $and$libresoc.v:203116$14315_Y + connect \$11 $ternary$libresoc.v:203117$14316_Y + connect \$139 $lt$libresoc.v:203118$14317_Y + connect \$141 $and$libresoc.v:203119$14318_Y + connect \$143 $lt$libresoc.v:203120$14319_Y + connect \$145 $and$libresoc.v:203121$14320_Y + connect \$147 $lt$libresoc.v:203122$14321_Y + connect \$149 $and$libresoc.v:203123$14322_Y + connect \$151 $lt$libresoc.v:203124$14323_Y + connect \$153 $and$libresoc.v:203125$14324_Y + connect \$155 $lt$libresoc.v:203126$14325_Y + connect \$157 $and$libresoc.v:203127$14326_Y + connect \$159 $lt$libresoc.v:203128$14327_Y + connect \$161 $and$libresoc.v:203129$14328_Y + connect \$163 $lt$libresoc.v:203130$14329_Y + connect \$165 $and$libresoc.v:203131$14330_Y + connect \$167 $lt$libresoc.v:203132$14331_Y + connect \$16 $eq$libresoc.v:203133$14332_Y + connect \$169 $and$libresoc.v:203134$14333_Y + connect \$171 $lt$libresoc.v:203135$14334_Y + connect \$173 $and$libresoc.v:203136$14335_Y + connect \$175 $lt$libresoc.v:203137$14336_Y + connect \$177 $and$libresoc.v:203138$14337_Y + connect \$15 $ternary$libresoc.v:203139$14338_Y + connect \$179 $lt$libresoc.v:203140$14339_Y + connect \$181 $and$libresoc.v:203141$14340_Y + connect \$183 $lt$libresoc.v:203142$14341_Y + connect \$185 $and$libresoc.v:203143$14342_Y + connect \$187 $lt$libresoc.v:203144$14343_Y + connect \$189 $and$libresoc.v:203145$14344_Y + connect \$191 $lt$libresoc.v:203146$14345_Y + connect \$193 $and$libresoc.v:203147$14346_Y + connect \$195 $lt$libresoc.v:203148$14347_Y + connect \$197 $and$libresoc.v:203149$14348_Y + connect \$1 $eq$libresoc.v:203150$14349_Y + connect \$199 $lt$libresoc.v:203151$14350_Y + connect \$201 $and$libresoc.v:203152$14351_Y + connect \$204 $eq$libresoc.v:203153$14352_Y + connect \$203 $ternary$libresoc.v:203154$14353_Y + connect \$20 $eq$libresoc.v:203155$14354_Y + connect \$19 $ternary$libresoc.v:203156$14355_Y + connect \$24 $eq$libresoc.v:203157$14356_Y + connect \$23 $ternary$libresoc.v:203158$14357_Y + connect \$28 $eq$libresoc.v:203159$14358_Y + connect \$27 $ternary$libresoc.v:203160$14359_Y + connect \$32 $eq$libresoc.v:203161$14360_Y + connect \$31 $ternary$libresoc.v:203162$14361_Y + connect \$36 $eq$libresoc.v:203163$14362_Y + connect \$35 $ternary$libresoc.v:203164$14363_Y + connect \$3 $eq$libresoc.v:203165$14364_Y + connect \$40 $eq$libresoc.v:203166$14365_Y + connect \$39 $ternary$libresoc.v:203167$14366_Y + connect \$44 $eq$libresoc.v:203168$14367_Y + connect \$43 $ternary$libresoc.v:203169$14368_Y + connect \$48 $eq$libresoc.v:203170$14369_Y + connect \$47 $ternary$libresoc.v:203171$14370_Y + connect \$52 $eq$libresoc.v:203172$14371_Y + connect \$51 $ternary$libresoc.v:203173$14372_Y + connect \$56 $eq$libresoc.v:203174$14373_Y + connect \$55 $ternary$libresoc.v:203175$14374_Y + connect \$5 $and$libresoc.v:203176$14375_Y + connect \$60 $eq$libresoc.v:203177$14376_Y + connect \$59 $ternary$libresoc.v:203178$14377_Y + connect \$64 $eq$libresoc.v:203179$14378_Y + connect \$63 $ternary$libresoc.v:203180$14379_Y + connect \$68 $eq$libresoc.v:203181$14380_Y + connect \$67 $ternary$libresoc.v:203182$14381_Y + connect \$71 $shr$libresoc.v:203183$14382_Y [0] + connect \$73 $and$libresoc.v:203184$14383_Y + connect \$75 $lt$libresoc.v:203185$14384_Y + connect \$77 $and$libresoc.v:203186$14385_Y + connect \$79 $lt$libresoc.v:203187$14386_Y + connect \$81 $and$libresoc.v:203188$14387_Y + connect \$83 $lt$libresoc.v:203189$14388_Y + connect \$85 $and$libresoc.v:203190$14389_Y + connect \$87 $lt$libresoc.v:203191$14390_Y + connect \$8 $eq$libresoc.v:203192$14391_Y + connect \$89 $and$libresoc.v:203193$14392_Y + connect \$91 $lt$libresoc.v:203194$14393_Y + connect \$93 $and$libresoc.v:203195$14394_Y + connect \$95 $lt$libresoc.v:203196$14395_Y + connect \$97 $and$libresoc.v:203197$14396_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000