From: Andrew Cagney Date: Mon, 8 Dec 1997 23:44:11 +0000 (+0000) Subject: Fix typo, REP_S was refering to REP_E register. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=38d0ccc27a51c0aabd0c04754ade7cc3c08df395;p=binutils-gdb.git Fix typo, REP_S was refering to REP_E register. Add test. --- diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index fb753282fa1..347585089f9 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,7 @@ +Tue Dec 9 10:28:31 1997 Andrew Cagney + + * d10v_sim.h (RPT_S): Index cregs with RPT_S_CR not RPT_E_CR. + Mon Dec 8 12:58:33 1997 Andrew Cagney * simops.c (OP_5F00): From Martin Hunt . Change diff --git a/sim/d10v/d10v_sim.h b/sim/d10v/d10v_sim.h index b05a60a4702..59787f15e63 100644 --- a/sim/d10v/d10v_sim.h +++ b/sim/d10v/d10v_sim.h @@ -146,7 +146,7 @@ enum #define BPSW (0 + State.cregs[PSW_CR]) #define BPC (State.cregs[BPC_CR]) #define RPT_C (State.cregs[RPT_C_CR]) -#define RPT_S (State.cregs[RPT_E_CR]) +#define RPT_S (State.cregs[RPT_S_CR]) #define RPT_E (State.cregs[RPT_E_CR]) #define MOD_S (0 + State.cregs[MOD_S_CR]) #define MOD_E (0 + State.cregs[MOD_E_CR]) diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog index c76a7b2398c..874b6f520da 100644 --- a/sim/testsuite/d10v-elf/ChangeLog +++ b/sim/testsuite/d10v-elf/ChangeLog @@ -1,3 +1,7 @@ +Tue Dec 9 10:41:44 1997 Andrew Cagney + + * t-rep.s: Check rep repeats correct number of times. + Fri Dec 5 10:11:18 1997 Andrew Cagney * t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S.