From: lkcl <lkcl@web>
Date: Wed, 20 Jul 2022 14:15:26 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1158
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3904e17a153b8b9d8fbdda318c547abc28fb1f12;p=libreriscv.git

---

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index d89411225..dcb01bdc5 100644
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -51,8 +51,9 @@ full context save/restore (see SVSRR0).  It contains (and permits setting of):
   instruction unless this bit is set, in which case REMAP "persists".
   Reset (cleared) on use of the `setvl` instruction if used to
   alter VL or MVL.
-* hphint - Horizontal Parallelism Hint. In Vertical First Mode
-   hardware **MAY** perform up to this many elements in parallel
+* hphint - Horizontal Parallelism Hint. Indicates that
+  no Hazards exist between these elements. In Vertical First Mode
+   hardware **MUST** perform this many elements in parallel
    per instruction. Set to zero to indicate "no hint".
 * SVme - REMAP enable bits, indicating which register is to be
  REMAPed.  RA, RB, RC, RT or EA.
@@ -86,11 +87,18 @@ The main effect of SUBVL is that predication bits are applied per
 **group**, rather than by individual element.  Legal values are 1 to 4.
 Illegal values raise an exception.
 
+**Horizontal Parallelism**
+
+A problem exists for hardware where it may not be able to detect
+that a programmer (or compiler) knows of opportunities for parallelism
+and lack of overlap between loops.
+
 For hphint, the number chosen must be consistently
 executed **every time**. Hardware is not permitted to execute five
 computations for one instruction then three on the next.
-hphint is a hint from the compiler to hardware that up to this
-many elements may be safely executed in parallel.
+hphint is a hint from the compiler to hardware that exactly this
+many elements may be safely executed in parallel, without hazards
+(including Memory accesses).
 Interestingly, when hphint is set equal to VL, it is in effect
 as if Vertical First mode were not set, because the hardware is
 given the option to run through all elements in an instruction.
@@ -101,6 +109,8 @@ except that the hardware may *choose* the number of elements.
 should be done only with due care and respect for the fact that SVSTATE
 has exactly the same peer-level status as a Program Counter.*
 
+**SVSTATE SPR**
+
 The format of the SVSTATE SPR is as follows:
 
 | Field | Name     | Description           |
@@ -117,7 +127,8 @@ The format of the SVSTATE SPR is as follows:
 | 38:39 | mo0      | REMAP RT SVSHAPE0-3    |
 | 40:41 | mo1      | REMAP EA SVSHAPE0-3    |
 | 42:46 | SVme     | REMAP enable (RA-RT)  |
-| 47:61 | rsvd     | reserved              |
+| 47:t4 | rsvd     | reserved              |
+| 55:61 | hphint   | Horizontal Hint       |
 | 62    | RMpst    | REMAP persistence     |
 | 63    | vfirst   | Vertical First mode   |