From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 Jul 2020 19:56:55 +0000 (+0100)
Subject: update comments
X-Git-Tag: semi_working_ecp5~610
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=390db632b52d1fb4ba880762cb13c4ba1dd38839;p=soc.git

update comments
---

diff --git a/src/soc/litex/sim.py b/src/soc/litex/sim.py
index 9640c58a..1a4a2d66 100644
--- a/src/soc/litex/sim.py
+++ b/src/soc/litex/sim.py
@@ -63,7 +63,7 @@ class SoCSMP(SoCCore):
 
         # SoCCore --------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
-            cpu_type                 = "microwatt", # XXX use None for now libre_soc
+            cpu_type                 = "microwatt", # XXX use microwatt
             cpu_variant              = cpu_variant,
             cpu_cls                  = LibreSOC,
             uart_name                = "sim",