From: lkcl Date: Fri, 12 Feb 2021 02:53:25 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~206 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39168a06c45a038c047a4afd9e7304b8fc85075d;p=libreriscv.git --- diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn index b75d310ce..245fb40a1 100644 --- a/3d_gpu/architecture/dynamic_simd.mdwn +++ b/3d_gpu/architecture/dynamic_simd.mdwn @@ -50,3 +50,5 @@ A much more intelligent approach is needed. What we actually want is: where behind the scenes the above laborious for-loops (conceptually) are created, hidden, behind the scenes, looking to all intents and purposes however that this is exactly like any other nmigen Signal. This means that nmigen needs to "understand" the partitioning, in m.If, m.Else and m.Switch, at the bare minimum. + +Analysis of the internals of nmigen shows that m.If, m.Else and m.Switch are all redirected to `Value.cases'. Within that function Mux and other "global" functions (similar to python operator functions). The hypothesis is therefore proposed that if `Value.mux` is added in an identical way to how `operator.add` calls `__add__` this may turn out to be all that (or most of what) is needed.