From: Hans-Peter Nilsson Date: Tue, 6 Dec 2005 22:42:43 +0000 (+0000) Subject: * cris/cpuv10.h, cris/cpuv32.h, cris/cris-desc.c, cris/cris-opc.h, X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=392753ae2fe917d5657d4fd1749250e6f574f088;p=binutils-gdb.git * cris/cpuv10.h, cris/cpuv32.h, cris/cris-desc.c, cris/cris-opc.h, cris/decodev10.c, cris/decodev10.h, cris/decodev32.c, cris/decodev32.h, cris/modelv10.c, cris/modelv32.c, cris/semcrisv10f-switch.c, cris/semcrisv32f-switch.c: Regenerate. --- diff --git a/sim/cris/cpuv10.h b/sim/cris/cpuv10.h index 52c1b747204..871b3f33785 100644 --- a/sim/cris/cpuv10.h +++ b/sim/cris/cpuv10.h @@ -293,6 +293,11 @@ union sem_fields { IADDR i_o_pcrel; UINT f_operand2; } sfmt_bcc_b; + struct { /* */ + UINT f_memmode; + unsigned char in_h_gr_SI_14; + unsigned char out_h_gr_SI_14; + } sfmt_move_m_spplus_p8; struct { /* */ INT f_s8; UINT f_operand2; @@ -302,17 +307,12 @@ union sem_fields { INT f_indir_pc__dword; UINT f_operand2; unsigned char out_Pd; - } sfmt_move_c_sprv10_p8; + } sfmt_move_c_sprv10_p9; struct { /* */ INT f_indir_pc__word; UINT f_operand2; unsigned char out_Pd; - } sfmt_move_c_sprv10_p4; - struct { /* */ - INT f_indir_pc__byte; - UINT f_operand2; - unsigned char out_Pd; - } sfmt_move_c_sprv10_p0; + } sfmt_move_c_sprv10_p5; struct { /* */ INT f_s6; UINT f_operand2; @@ -784,27 +784,7 @@ struct scache { f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ -#define EXTRACT_IFMT_MOVE_C_SPRV10_P0_VARS \ - UINT f_operand2; \ - INT f_indir_pc__byte; \ - UINT f_mode; \ - UINT f_opcode; \ - UINT f_size; \ - UINT f_operand1; \ - /* Contents of trailing part of insn. */ \ - UINT word_1; \ - unsigned int length; -#define EXTRACT_IFMT_MOVE_C_SPRV10_P0_CODE \ - length = 4; \ - word_1 = GETIMEMUSI (current_cpu, pc + 2); \ - f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ - f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ - f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ - f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ - f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ - -#define EXTRACT_IFMT_MOVE_C_SPRV10_P4_VARS \ +#define EXTRACT_IFMT_MOVE_C_SPRV10_P5_VARS \ UINT f_operand2; \ INT f_indir_pc__word; \ UINT f_mode; \ @@ -814,7 +794,7 @@ struct scache { /* Contents of trailing part of insn. */ \ UINT word_1; \ unsigned int length; -#define EXTRACT_IFMT_MOVE_C_SPRV10_P4_CODE \ +#define EXTRACT_IFMT_MOVE_C_SPRV10_P5_CODE \ length = 4; \ word_1 = GETIMEMUSI (current_cpu, pc + 2); \ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ @@ -824,7 +804,7 @@ struct scache { f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ -#define EXTRACT_IFMT_MOVE_C_SPRV10_P8_VARS \ +#define EXTRACT_IFMT_MOVE_C_SPRV10_P9_VARS \ INT f_indir_pc__dword; \ UINT f_operand2; \ UINT f_mode; \ @@ -834,7 +814,7 @@ struct scache { /* Contents of trailing part of insn. */ \ UINT word_1; \ unsigned int length; -#define EXTRACT_IFMT_MOVE_C_SPRV10_P8_CODE \ +#define EXTRACT_IFMT_MOVE_C_SPRV10_P9_CODE \ length = 6; \ word_1 = GETIMEMUSI (current_cpu, pc + 2); \ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ diff --git a/sim/cris/cpuv32.h b/sim/cris/cpuv32.h index 93c942519ac..fc78a0b71d9 100644 --- a/sim/cris/cpuv32.h +++ b/sim/cris/cpuv32.h @@ -452,7 +452,7 @@ union sem_fields { INT f_indir_pc__dword; UINT f_operand2; unsigned char out_Pd; - } sfmt_move_c_sprv32_p0; + } sfmt_move_c_sprv32_p2; struct { /* */ INT f_s6; UINT f_operand2; @@ -882,7 +882,7 @@ struct scache { f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ -#define EXTRACT_IFMT_MOVE_C_SPRV32_P0_VARS \ +#define EXTRACT_IFMT_MOVE_C_SPRV32_P2_VARS \ INT f_indir_pc__dword; \ UINT f_operand2; \ UINT f_mode; \ @@ -892,7 +892,7 @@ struct scache { /* Contents of trailing part of insn. */ \ UINT word_1; \ unsigned int length; -#define EXTRACT_IFMT_MOVE_C_SPRV32_P0_CODE \ +#define EXTRACT_IFMT_MOVE_C_SPRV32_P2_CODE \ length = 6; \ word_1 = GETIMEMUSI (current_cpu, pc + 2); \ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ diff --git a/sim/cris/cris-desc.c b/sim/cris/cris-desc.c index e83c7c48600..2f724011de8 100644 --- a/sim/cris/cris-desc.c +++ b/sim/cris/cris-desc.c @@ -1349,31 +1349,11 @@ static const CGEN_IBASE cris_cgen_insn_table[MAX_INSNS] = CRIS_INSN_MOVE_M_SPRV32, "move-m-sprv32", "move", 16, { 0, { { { (1<> 0) & (15 << 0))); + unsigned int val = (((insn >> 12) & (15 << 0))); switch (val) { case 0 : /* fall through */ @@ -2056,13 +2055,65 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 12 : /* fall through */ case 13 : /* fall through */ case 14 : - if ((base_insn & 0xbf0) == 0x960) - { itype = CRISV10F_INSN_ADDO_M_D_M; goto extract_sfmt_addo_m_d_m; } - itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; + { + unsigned int val = (((insn >> 0) & (15 << 0))); + switch (val) + { + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : /* fall through */ + case 4 : /* fall through */ + case 5 : /* fall through */ + case 6 : /* fall through */ + case 7 : /* fall through */ + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : /* fall through */ + case 12 : /* fall through */ + case 13 : /* fall through */ + case 14 : + if ((base_insn & 0xbf0) == 0x960) + { itype = CRISV10F_INSN_ADDO_M_D_M; goto extract_sfmt_addo_m_d_m; } + itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; + case 15 : + if ((base_insn & 0xfff) == 0xd6f) + { itype = CRISV10F_INSN_ADDO_CD; goto extract_sfmt_addo_cd; } + itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } case 15 : - if ((base_insn & 0xfff) == 0xd6f) - { itype = CRISV10F_INSN_ADDO_CD; goto extract_sfmt_addo_cd; } - itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; + { + unsigned int val = (((insn >> 0) & (15 << 0))); + switch (val) + { + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : /* fall through */ + case 4 : /* fall through */ + case 5 : /* fall through */ + case 6 : /* fall through */ + case 7 : /* fall through */ + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : /* fall through */ + case 12 : /* fall through */ + case 13 : /* fall through */ + case 14 : + if ((base_insn & 0xbf0) == 0x960) + { itype = CRISV10F_INSN_ADDO_M_D_M; goto extract_sfmt_addo_m_d_m; } + itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; + case 15 : + if ((base_insn & 0xffff) == 0xfd6f) + { itype = CRISV10F_INSN_BDAP_32_PC; goto extract_sfmt_bdap_32_pc; } + itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } @@ -2360,78 +2411,36 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 227 : { - unsigned int val = (((insn >> 12) & (15 << 0))); + unsigned int val = (((insn >> 11) & (15 << 1)) | ((insn >> 0) & (1 << 0))); switch (val) { - case 0 : - { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) - { - case 0 : /* fall through */ - case 1 : /* fall through */ - case 2 : /* fall through */ - case 3 : /* fall through */ - case 4 : /* fall through */ - case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : - if ((base_insn & 0xbf0) == 0xa30) - { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } - itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : - if ((base_insn & 0xffff) == 0xe3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P0; goto extract_sfmt_move_c_sprv10_p0; } - itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 1 : - { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) - { - case 0 : /* fall through */ - case 1 : /* fall through */ - case 2 : /* fall through */ - case 3 : /* fall through */ - case 4 : /* fall through */ - case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : - if ((base_insn & 0xbf0) == 0xa30) - { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } - itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : - if ((base_insn & 0xffff) == 0x1e3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P1; goto extract_sfmt_move_c_sprv10_p0; } - itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - } - } + case 0 : /* fall through */ case 2 : /* fall through */ case 3 : /* fall through */ - case 6 : + case 4 : /* fall through */ + case 5 : /* fall through */ + case 6 : /* fall through */ + case 7 : /* fall through */ + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 12 : /* fall through */ + case 13 : /* fall through */ + case 14 : /* fall through */ + case 17 : /* fall through */ + case 18 : /* fall through */ + case 20 : /* fall through */ + case 22 : /* fall through */ + case 24 : /* fall through */ + case 26 : /* fall through */ + case 28 : /* fall through */ + case 30 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 4 : + case 1 : { - unsigned int val = (((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 1) & (7 << 0))); switch (val) { case 0 : /* fall through */ @@ -2440,28 +2449,20 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 3 : /* fall through */ case 4 : /* fall through */ case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : + case 6 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : - if ((base_insn & 0xffff) == 0x4e3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P4; goto extract_sfmt_move_c_sprv10_p4; } + case 7 : + if ((base_insn & 0xffff) == 0xe3f) + { itype = CRISV10F_INSN_MOVE_M_PCPLUS_P0; goto extract_sfmt_move_m_pcplus_p0; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 5 : + case 11 : { - unsigned int val = (((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 1) & (7 << 0))); switch (val) { case 0 : /* fall through */ @@ -2470,28 +2471,20 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 3 : /* fall through */ case 4 : /* fall through */ case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : + case 6 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : + case 7 : if ((base_insn & 0xffff) == 0x5e3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P5; goto extract_sfmt_move_c_sprv10_p4; } + { itype = CRISV10F_INSN_MOVE_C_SPRV10_P5; goto extract_sfmt_move_c_sprv10_p5; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 7 : + case 15 : { - unsigned int val = (((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 1) & (7 << 0))); switch (val) { case 0 : /* fall through */ @@ -2500,28 +2493,20 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 3 : /* fall through */ case 4 : /* fall through */ case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : + case 6 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : + case 7 : if ((base_insn & 0xffff) == 0x7e3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P7; goto extract_sfmt_move_c_sprv10_p8; } + { itype = CRISV10F_INSN_MOVE_C_SPRV10_P7; goto extract_sfmt_move_c_sprv10_p9; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 8 : + case 16 : { - unsigned int val = (((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 1) & (7 << 0))); switch (val) { case 0 : /* fall through */ @@ -2530,28 +2515,20 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 3 : /* fall through */ case 4 : /* fall through */ case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : + case 6 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : - if ((base_insn & 0xffff) == 0x8e3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P8; goto extract_sfmt_move_c_sprv10_p8; } + case 7 : + if ((base_insn & 0xffff) == 0x8e3e) + { itype = CRISV10F_INSN_MOVE_M_SPPLUS_P8; goto extract_sfmt_move_m_spplus_p8; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 9 : + case 19 : { - unsigned int val = (((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 1) & (7 << 0))); switch (val) { case 0 : /* fall through */ @@ -2560,28 +2537,20 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 3 : /* fall through */ case 4 : /* fall through */ case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : + case 6 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : + case 7 : if ((base_insn & 0xffff) == 0x9e3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P9; goto extract_sfmt_move_c_sprv10_p8; } + { itype = CRISV10F_INSN_MOVE_C_SPRV10_P9; goto extract_sfmt_move_c_sprv10_p9; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 10 : + case 21 : { - unsigned int val = (((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 1) & (7 << 0))); switch (val) { case 0 : /* fall through */ @@ -2590,28 +2559,20 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 3 : /* fall through */ case 4 : /* fall through */ case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : + case 6 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : + case 7 : if ((base_insn & 0xffff) == 0xae3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P10; goto extract_sfmt_move_c_sprv10_p8; } + { itype = CRISV10F_INSN_MOVE_C_SPRV10_P10; goto extract_sfmt_move_c_sprv10_p9; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 11 : + case 23 : { - unsigned int val = (((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 1) & (7 << 0))); switch (val) { case 0 : /* fall through */ @@ -2620,28 +2581,20 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 3 : /* fall through */ case 4 : /* fall through */ case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : + case 6 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : + case 7 : if ((base_insn & 0xffff) == 0xbe3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P11; goto extract_sfmt_move_c_sprv10_p8; } + { itype = CRISV10F_INSN_MOVE_C_SPRV10_P11; goto extract_sfmt_move_c_sprv10_p9; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 12 : + case 25 : { - unsigned int val = (((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 1) & (7 << 0))); switch (val) { case 0 : /* fall through */ @@ -2650,28 +2603,20 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 3 : /* fall through */ case 4 : /* fall through */ case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : + case 6 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : + case 7 : if ((base_insn & 0xffff) == 0xce3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P12; goto extract_sfmt_move_c_sprv10_p8; } + { itype = CRISV10F_INSN_MOVE_C_SPRV10_P12; goto extract_sfmt_move_c_sprv10_p9; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 13 : + case 27 : { - unsigned int val = (((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 1) & (7 << 0))); switch (val) { case 0 : /* fall through */ @@ -2680,28 +2625,20 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 3 : /* fall through */ case 4 : /* fall through */ case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : + case 6 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : + case 7 : if ((base_insn & 0xffff) == 0xde3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P13; goto extract_sfmt_move_c_sprv10_p8; } + { itype = CRISV10F_INSN_MOVE_C_SPRV10_P13; goto extract_sfmt_move_c_sprv10_p9; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 14 : + case 29 : { - unsigned int val = (((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 1) & (7 << 0))); switch (val) { case 0 : /* fall through */ @@ -2710,28 +2647,20 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 3 : /* fall through */ case 4 : /* fall through */ case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : + case 6 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : + case 7 : if ((base_insn & 0xffff) == 0xee3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P14; goto extract_sfmt_move_c_sprv10_p8; } + { itype = CRISV10F_INSN_MOVE_C_SPRV10_P14; goto extract_sfmt_move_c_sprv10_p9; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 15 : + case 31 : { - unsigned int val = (((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 1) & (7 << 0))); switch (val) { case 0 : /* fall through */ @@ -2740,21 +2669,13 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 3 : /* fall through */ case 4 : /* fall through */ case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : + case 6 : if ((base_insn & 0xbf0) == 0xa30) { itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : + case 7 : if ((base_insn & 0xffff) == 0xfe3f) - { itype = CRISV10F_INSN_MOVE_C_SPRV10_P15; goto extract_sfmt_move_c_sprv10_p8; } + { itype = CRISV10F_INSN_MOVE_C_SPRV10_P15; goto extract_sfmt_move_c_sprv10_p9; } itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -4191,41 +4112,11 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_sfmt_move_c_sprv10_p0: - { - const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f - UINT f_operand2; - INT f_indir_pc__byte; - /* Contents of trailing part of insn. */ - UINT word_1; - - word_1 = GETIMEMUSI (current_cpu, pc + 2); - f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); - f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); - - /* Record the fields for the semantic handler. */ - FLD (f_indir_pc__byte) = f_indir_pc__byte; - FLD (f_operand2) = f_operand2; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_c_sprv10_p0", "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, "f_operand2 0x%x", 'x', f_operand2, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (out_Pd) = f_operand2; - } -#endif -#undef FLD - return idesc; - } - - extract_sfmt_move_c_sprv10_p4: + extract_sfmt_move_c_sprv10_p5: { const IDESC *idesc = &crisv10f_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p5.f UINT f_operand2; INT f_indir_pc__word; /* Contents of trailing part of insn. */ @@ -4238,7 +4129,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_indir_pc__word) = f_indir_pc__word; FLD (f_operand2) = f_operand2; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_c_sprv10_p4", "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, "f_operand2 0x%x", 'x', f_operand2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_c_sprv10_p5", "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, "f_operand2 0x%x", 'x', f_operand2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -4251,11 +4142,11 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_sfmt_move_c_sprv10_p8: + extract_sfmt_move_c_sprv10_p9: { const IDESC *idesc = &crisv10f_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f INT f_indir_pc__dword; UINT f_operand2; /* Contents of trailing part of insn. */ @@ -4268,7 +4159,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_indir_pc__dword) = f_indir_pc__dword; FLD (f_operand2) = f_operand2; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_c_sprv10_p8", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, "f_operand2 0x%x", 'x', f_operand2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_c_sprv10_p9", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, "f_operand2 0x%x", 'x', f_operand2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -4718,7 +4609,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &crisv10f_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f INT f_indir_pc__dword; /* Contents of trailing part of insn. */ UINT word_1; @@ -5954,7 +5845,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &crisv10f_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f INT f_indir_pc__dword; UINT f_operand2; /* Contents of trailing part of insn. */ @@ -6268,6 +6159,80 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, { } #endif +#undef FLD + return idesc; + } + + extract_sfmt_bdap_32_pc: + { + const IDESC *idesc = &crisv10f_insn_data[itype]; + CGEN_INSN_INT insn = base_insn; +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f + INT f_indir_pc__dword; + /* Contents of trailing part of insn. */ + UINT word_1; + + word_1 = GETIMEMUSI (current_cpu, pc + 2); + f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_indir_pc__dword) = f_indir_pc__dword; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bdap_32_pc", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_move_m_pcplus_p0: + { + const IDESC *idesc = &crisv10f_insn_data[itype]; + CGEN_INSN_INT insn = base_insn; +#define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f + UINT f_memmode; + + f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); + + /* Record the fields for the semantic handler. */ + FLD (f_memmode) = f_memmode; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_m_pcplus_p0", "f_memmode 0x%x", 'x', f_memmode, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_move_m_spplus_p8: + { + const IDESC *idesc = &crisv10f_insn_data[itype]; + CGEN_INSN_INT insn = base_insn; +#define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f + UINT f_memmode; + + f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); + + /* Record the fields for the semantic handler. */ + FLD (f_memmode) = f_memmode; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_m_spplus_p8", "f_memmode 0x%x", 'x', f_memmode, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_h_gr_SI_14) = 14; + FLD (out_h_gr_SI_14) = 14; + } +#endif #undef FLD return idesc; } @@ -6490,7 +6455,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &crisv10f_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f INT f_indir_pc__dword; /* Contents of trailing part of insn. */ UINT word_1; diff --git a/sim/cris/decodev10.h b/sim/cris/decodev10.h index f5aa822fd68..0fe0b083c64 100644 --- a/sim/cris/decodev10.h +++ b/sim/cris/decodev10.h @@ -47,8 +47,7 @@ typedef enum crisv10f_insn_type { , CRISV10F_INSN_CMPU_M_W_M, CRISV10F_INSN_CMPUCBR, CRISV10F_INSN_CMPUCWR, CRISV10F_INSN_MOVE_M_B_M , CRISV10F_INSN_MOVE_M_W_M, CRISV10F_INSN_MOVE_M_D_M, CRISV10F_INSN_MOVS_M_B_M, CRISV10F_INSN_MOVS_M_W_M , CRISV10F_INSN_MOVU_M_B_M, CRISV10F_INSN_MOVU_M_W_M, CRISV10F_INSN_MOVE_R_SPRV10, CRISV10F_INSN_MOVE_SPR_RV10 - , CRISV10F_INSN_RET_TYPE, CRISV10F_INSN_MOVE_M_SPRV10, CRISV10F_INSN_MOVE_C_SPRV10_P0, CRISV10F_INSN_MOVE_C_SPRV10_P1 - , CRISV10F_INSN_MOVE_C_SPRV10_P4, CRISV10F_INSN_MOVE_C_SPRV10_P5, CRISV10F_INSN_MOVE_C_SPRV10_P8, CRISV10F_INSN_MOVE_C_SPRV10_P9 + , CRISV10F_INSN_RET_TYPE, CRISV10F_INSN_MOVE_M_SPRV10, CRISV10F_INSN_MOVE_C_SPRV10_P5, CRISV10F_INSN_MOVE_C_SPRV10_P9 , CRISV10F_INSN_MOVE_C_SPRV10_P10, CRISV10F_INSN_MOVE_C_SPRV10_P11, CRISV10F_INSN_MOVE_C_SPRV10_P12, CRISV10F_INSN_MOVE_C_SPRV10_P13 , CRISV10F_INSN_MOVE_C_SPRV10_P7, CRISV10F_INSN_MOVE_C_SPRV10_P14, CRISV10F_INSN_MOVE_C_SPRV10_P15, CRISV10F_INSN_MOVE_SPR_MV10 , CRISV10F_INSN_SBFS, CRISV10F_INSN_MOVEM_R_M, CRISV10F_INSN_MOVEM_M_R, CRISV10F_INSN_MOVEM_M_PC @@ -83,10 +82,11 @@ typedef enum crisv10f_insn_type { , CRISV10F_INSN_BOUND_R_W_R, CRISV10F_INSN_BOUND_R_D_R, CRISV10F_INSN_BOUND_M_B_M, CRISV10F_INSN_BOUND_M_W_M , CRISV10F_INSN_BOUND_M_D_M, CRISV10F_INSN_BOUND_CB, CRISV10F_INSN_BOUND_CW, CRISV10F_INSN_BOUND_CD , CRISV10F_INSN_SCC, CRISV10F_INSN_LZ, CRISV10F_INSN_ADDOQ, CRISV10F_INSN_BDAPQPC - , CRISV10F_INSN_ADDO_M_B_M, CRISV10F_INSN_ADDO_M_W_M, CRISV10F_INSN_ADDO_M_D_M, CRISV10F_INSN_ADDO_CB - , CRISV10F_INSN_ADDO_CW, CRISV10F_INSN_ADDO_CD, CRISV10F_INSN_DIP_M, CRISV10F_INSN_DIP_C - , CRISV10F_INSN_ADDI_ACR_B_R, CRISV10F_INSN_ADDI_ACR_W_R, CRISV10F_INSN_ADDI_ACR_D_R, CRISV10F_INSN_BIAP_PC_B_R - , CRISV10F_INSN_BIAP_PC_W_R, CRISV10F_INSN_BIAP_PC_D_R, CRISV10F_INSN__MAX + , CRISV10F_INSN_BDAP_32_PC, CRISV10F_INSN_MOVE_M_PCPLUS_P0, CRISV10F_INSN_MOVE_M_SPPLUS_P8, CRISV10F_INSN_ADDO_M_B_M + , CRISV10F_INSN_ADDO_M_W_M, CRISV10F_INSN_ADDO_M_D_M, CRISV10F_INSN_ADDO_CB, CRISV10F_INSN_ADDO_CW + , CRISV10F_INSN_ADDO_CD, CRISV10F_INSN_DIP_M, CRISV10F_INSN_DIP_C, CRISV10F_INSN_ADDI_ACR_B_R + , CRISV10F_INSN_ADDI_ACR_W_R, CRISV10F_INSN_ADDI_ACR_D_R, CRISV10F_INSN_BIAP_PC_B_R, CRISV10F_INSN_BIAP_PC_W_R + , CRISV10F_INSN_BIAP_PC_D_R, CRISV10F_INSN__MAX } CRISV10F_INSN_TYPE; /* Enum declaration for semantic formats in cpu family crisv10f. */ @@ -99,27 +99,27 @@ typedef enum crisv10f_sfmt_type { , CRISV10F_SFMT_CMPCWR, CRISV10F_SFMT_CMPCDR, CRISV10F_SFMT_CMPQ, CRISV10F_SFMT_CMPUCBR , CRISV10F_SFMT_CMPUCWR, CRISV10F_SFMT_MOVE_M_B_M, CRISV10F_SFMT_MOVE_M_W_M, CRISV10F_SFMT_MOVE_M_D_M , CRISV10F_SFMT_MOVS_M_B_M, CRISV10F_SFMT_MOVS_M_W_M, CRISV10F_SFMT_MOVE_R_SPRV10, CRISV10F_SFMT_MOVE_SPR_RV10 - , CRISV10F_SFMT_RET_TYPE, CRISV10F_SFMT_MOVE_M_SPRV10, CRISV10F_SFMT_MOVE_C_SPRV10_P0, CRISV10F_SFMT_MOVE_C_SPRV10_P4 - , CRISV10F_SFMT_MOVE_C_SPRV10_P8, CRISV10F_SFMT_MOVE_SPR_MV10, CRISV10F_SFMT_SBFS, CRISV10F_SFMT_MOVEM_R_M - , CRISV10F_SFMT_MOVEM_M_R, CRISV10F_SFMT_MOVEM_M_PC, CRISV10F_SFMT_ADD_B_R, CRISV10F_SFMT_ADD_D_R - , CRISV10F_SFMT_ADD_M_B_M, CRISV10F_SFMT_ADD_M_W_M, CRISV10F_SFMT_ADD_M_D_M, CRISV10F_SFMT_ADDCBR - , CRISV10F_SFMT_ADDCWR, CRISV10F_SFMT_ADDCDR, CRISV10F_SFMT_ADDCPC, CRISV10F_SFMT_ADDS_M_B_M - , CRISV10F_SFMT_ADDS_M_W_M, CRISV10F_SFMT_ADDSCBR, CRISV10F_SFMT_ADDSCWR, CRISV10F_SFMT_ADDSPCPC - , CRISV10F_SFMT_ADDI_B_R, CRISV10F_SFMT_NEG_B_R, CRISV10F_SFMT_NEG_D_R, CRISV10F_SFMT_TEST_M_B_M - , CRISV10F_SFMT_TEST_M_W_M, CRISV10F_SFMT_TEST_M_D_M, CRISV10F_SFMT_MOVE_R_M_B_M, CRISV10F_SFMT_MOVE_R_M_W_M - , CRISV10F_SFMT_MOVE_R_M_D_M, CRISV10F_SFMT_MULS_B, CRISV10F_SFMT_MSTEP, CRISV10F_SFMT_DSTEP - , CRISV10F_SFMT_AND_B_R, CRISV10F_SFMT_AND_W_R, CRISV10F_SFMT_AND_D_R, CRISV10F_SFMT_AND_M_B_M - , CRISV10F_SFMT_AND_M_W_M, CRISV10F_SFMT_AND_M_D_M, CRISV10F_SFMT_ANDCBR, CRISV10F_SFMT_ANDCWR - , CRISV10F_SFMT_ANDCDR, CRISV10F_SFMT_ANDQ, CRISV10F_SFMT_SWAP, CRISV10F_SFMT_ASRR_B_R - , CRISV10F_SFMT_ASRQ, CRISV10F_SFMT_LSRR_B_R, CRISV10F_SFMT_LSRR_D_R, CRISV10F_SFMT_BTST - , CRISV10F_SFMT_BTSTQ, CRISV10F_SFMT_SETF, CRISV10F_SFMT_BCC_B, CRISV10F_SFMT_BA_B - , CRISV10F_SFMT_BCC_W, CRISV10F_SFMT_BA_W, CRISV10F_SFMT_JUMP_R, CRISV10F_SFMT_JUMP_M - , CRISV10F_SFMT_JUMP_C, CRISV10F_SFMT_BREAK, CRISV10F_SFMT_BOUND_M_B_M, CRISV10F_SFMT_BOUND_M_W_M - , CRISV10F_SFMT_BOUND_M_D_M, CRISV10F_SFMT_BOUND_CB, CRISV10F_SFMT_BOUND_CW, CRISV10F_SFMT_BOUND_CD - , CRISV10F_SFMT_SCC, CRISV10F_SFMT_ADDOQ, CRISV10F_SFMT_BDAPQPC, CRISV10F_SFMT_ADDO_M_B_M - , CRISV10F_SFMT_ADDO_M_W_M, CRISV10F_SFMT_ADDO_M_D_M, CRISV10F_SFMT_ADDO_CB, CRISV10F_SFMT_ADDO_CW - , CRISV10F_SFMT_ADDO_CD, CRISV10F_SFMT_DIP_M, CRISV10F_SFMT_DIP_C, CRISV10F_SFMT_ADDI_ACR_B_R - , CRISV10F_SFMT_BIAP_PC_B_R + , CRISV10F_SFMT_RET_TYPE, CRISV10F_SFMT_MOVE_M_SPRV10, CRISV10F_SFMT_MOVE_C_SPRV10_P5, CRISV10F_SFMT_MOVE_C_SPRV10_P9 + , CRISV10F_SFMT_MOVE_SPR_MV10, CRISV10F_SFMT_SBFS, CRISV10F_SFMT_MOVEM_R_M, CRISV10F_SFMT_MOVEM_M_R + , CRISV10F_SFMT_MOVEM_M_PC, CRISV10F_SFMT_ADD_B_R, CRISV10F_SFMT_ADD_D_R, CRISV10F_SFMT_ADD_M_B_M + , CRISV10F_SFMT_ADD_M_W_M, CRISV10F_SFMT_ADD_M_D_M, CRISV10F_SFMT_ADDCBR, CRISV10F_SFMT_ADDCWR + , CRISV10F_SFMT_ADDCDR, CRISV10F_SFMT_ADDCPC, CRISV10F_SFMT_ADDS_M_B_M, CRISV10F_SFMT_ADDS_M_W_M + , CRISV10F_SFMT_ADDSCBR, CRISV10F_SFMT_ADDSCWR, CRISV10F_SFMT_ADDSPCPC, CRISV10F_SFMT_ADDI_B_R + , CRISV10F_SFMT_NEG_B_R, CRISV10F_SFMT_NEG_D_R, CRISV10F_SFMT_TEST_M_B_M, CRISV10F_SFMT_TEST_M_W_M + , CRISV10F_SFMT_TEST_M_D_M, CRISV10F_SFMT_MOVE_R_M_B_M, CRISV10F_SFMT_MOVE_R_M_W_M, CRISV10F_SFMT_MOVE_R_M_D_M + , CRISV10F_SFMT_MULS_B, CRISV10F_SFMT_MSTEP, CRISV10F_SFMT_DSTEP, CRISV10F_SFMT_AND_B_R + , CRISV10F_SFMT_AND_W_R, CRISV10F_SFMT_AND_D_R, CRISV10F_SFMT_AND_M_B_M, CRISV10F_SFMT_AND_M_W_M + , CRISV10F_SFMT_AND_M_D_M, CRISV10F_SFMT_ANDCBR, CRISV10F_SFMT_ANDCWR, CRISV10F_SFMT_ANDCDR + , CRISV10F_SFMT_ANDQ, CRISV10F_SFMT_SWAP, CRISV10F_SFMT_ASRR_B_R, CRISV10F_SFMT_ASRQ + , CRISV10F_SFMT_LSRR_B_R, CRISV10F_SFMT_LSRR_D_R, CRISV10F_SFMT_BTST, CRISV10F_SFMT_BTSTQ + , CRISV10F_SFMT_SETF, CRISV10F_SFMT_BCC_B, CRISV10F_SFMT_BA_B, CRISV10F_SFMT_BCC_W + , CRISV10F_SFMT_BA_W, CRISV10F_SFMT_JUMP_R, CRISV10F_SFMT_JUMP_M, CRISV10F_SFMT_JUMP_C + , CRISV10F_SFMT_BREAK, CRISV10F_SFMT_BOUND_M_B_M, CRISV10F_SFMT_BOUND_M_W_M, CRISV10F_SFMT_BOUND_M_D_M + , CRISV10F_SFMT_BOUND_CB, CRISV10F_SFMT_BOUND_CW, CRISV10F_SFMT_BOUND_CD, CRISV10F_SFMT_SCC + , CRISV10F_SFMT_ADDOQ, CRISV10F_SFMT_BDAPQPC, CRISV10F_SFMT_BDAP_32_PC, CRISV10F_SFMT_MOVE_M_PCPLUS_P0 + , CRISV10F_SFMT_MOVE_M_SPPLUS_P8, CRISV10F_SFMT_ADDO_M_B_M, CRISV10F_SFMT_ADDO_M_W_M, CRISV10F_SFMT_ADDO_M_D_M + , CRISV10F_SFMT_ADDO_CB, CRISV10F_SFMT_ADDO_CW, CRISV10F_SFMT_ADDO_CD, CRISV10F_SFMT_DIP_M + , CRISV10F_SFMT_DIP_C, CRISV10F_SFMT_ADDI_ACR_B_R, CRISV10F_SFMT_BIAP_PC_B_R } CRISV10F_SFMT_TYPE; /* Function unit handlers (user written). */ diff --git a/sim/cris/decodev32.c b/sim/cris/decodev32.c index aa9d353690f..f118915cf74 100644 --- a/sim/cris/decodev32.c +++ b/sim/cris/decodev32.c @@ -92,22 +92,18 @@ static const struct insn_sem crisv32f_insn_sem[] = { CRIS_INSN_MOVE_R_SPRV32, CRISV32F_INSN_MOVE_R_SPRV32, CRISV32F_SFMT_MOVE_R_SPRV32 }, { CRIS_INSN_MOVE_SPR_RV32, CRISV32F_INSN_MOVE_SPR_RV32, CRISV32F_SFMT_MOVE_SPR_RV32 }, { CRIS_INSN_MOVE_M_SPRV32, CRISV32F_INSN_MOVE_M_SPRV32, CRISV32F_SFMT_MOVE_M_SPRV32 }, - { CRIS_INSN_MOVE_C_SPRV32_P0, CRISV32F_INSN_MOVE_C_SPRV32_P0, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P1, CRISV32F_INSN_MOVE_C_SPRV32_P1, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P2, CRISV32F_INSN_MOVE_C_SPRV32_P2, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P3, CRISV32F_INSN_MOVE_C_SPRV32_P3, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P4, CRISV32F_INSN_MOVE_C_SPRV32_P4, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P5, CRISV32F_INSN_MOVE_C_SPRV32_P5, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P6, CRISV32F_INSN_MOVE_C_SPRV32_P6, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P7, CRISV32F_INSN_MOVE_C_SPRV32_P7, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P8, CRISV32F_INSN_MOVE_C_SPRV32_P8, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P9, CRISV32F_INSN_MOVE_C_SPRV32_P9, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P10, CRISV32F_INSN_MOVE_C_SPRV32_P10, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P11, CRISV32F_INSN_MOVE_C_SPRV32_P11, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P12, CRISV32F_INSN_MOVE_C_SPRV32_P12, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P13, CRISV32F_INSN_MOVE_C_SPRV32_P13, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P14, CRISV32F_INSN_MOVE_C_SPRV32_P14, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, - { CRIS_INSN_MOVE_C_SPRV32_P15, CRISV32F_INSN_MOVE_C_SPRV32_P15, CRISV32F_SFMT_MOVE_C_SPRV32_P0 }, + { CRIS_INSN_MOVE_C_SPRV32_P2, CRISV32F_INSN_MOVE_C_SPRV32_P2, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, + { CRIS_INSN_MOVE_C_SPRV32_P3, CRISV32F_INSN_MOVE_C_SPRV32_P3, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, + { CRIS_INSN_MOVE_C_SPRV32_P5, CRISV32F_INSN_MOVE_C_SPRV32_P5, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, + { CRIS_INSN_MOVE_C_SPRV32_P6, CRISV32F_INSN_MOVE_C_SPRV32_P6, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, + { CRIS_INSN_MOVE_C_SPRV32_P7, CRISV32F_INSN_MOVE_C_SPRV32_P7, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, + { CRIS_INSN_MOVE_C_SPRV32_P9, CRISV32F_INSN_MOVE_C_SPRV32_P9, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, + { CRIS_INSN_MOVE_C_SPRV32_P10, CRISV32F_INSN_MOVE_C_SPRV32_P10, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, + { CRIS_INSN_MOVE_C_SPRV32_P11, CRISV32F_INSN_MOVE_C_SPRV32_P11, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, + { CRIS_INSN_MOVE_C_SPRV32_P12, CRISV32F_INSN_MOVE_C_SPRV32_P12, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, + { CRIS_INSN_MOVE_C_SPRV32_P13, CRISV32F_INSN_MOVE_C_SPRV32_P13, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, + { CRIS_INSN_MOVE_C_SPRV32_P14, CRISV32F_INSN_MOVE_C_SPRV32_P14, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, + { CRIS_INSN_MOVE_C_SPRV32_P15, CRISV32F_INSN_MOVE_C_SPRV32_P15, CRISV32F_SFMT_MOVE_C_SPRV32_P2 }, { CRIS_INSN_MOVE_SPR_MV32, CRISV32F_INSN_MOVE_SPR_MV32, CRISV32F_SFMT_MOVE_SPR_MV32 }, { CRIS_INSN_MOVE_SS_R, CRISV32F_INSN_MOVE_SS_R, CRISV32F_SFMT_MOVE_SS_R }, { CRIS_INSN_MOVE_R_SS, CRISV32F_INSN_MOVE_R_SS, CRISV32F_SFMT_MOVE_R_SS }, @@ -1773,66 +1769,13 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 12) & (15 << 0))); switch (val) { - case 0 : - { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) - { - case 0 : /* fall through */ - case 1 : /* fall through */ - case 2 : /* fall through */ - case 3 : /* fall through */ - case 4 : /* fall through */ - case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : - if ((base_insn & 0xbf0) == 0xa30) - { itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32; } - itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : - if ((base_insn & 0xffff) == 0xe3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P0; goto extract_sfmt_move_c_sprv32_p0; } - itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 1 : - { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) - { - case 0 : /* fall through */ - case 1 : /* fall through */ - case 2 : /* fall through */ - case 3 : /* fall through */ - case 4 : /* fall through */ - case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : - if ((base_insn & 0xbf0) == 0xa30) - { itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32; } - itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : - if ((base_insn & 0xffff) == 0x1e3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P1; goto extract_sfmt_move_c_sprv32_p0; } - itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - } - } + case 0 : /* fall through */ + case 1 : /* fall through */ + case 4 : /* fall through */ + case 8 : + if ((base_insn & 0xbf0) == 0xa30) + { itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32; } + itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 2 : { unsigned int val = (((insn >> 0) & (15 << 0))); @@ -1858,7 +1801,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0x2e3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P2; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P2; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -1888,37 +1831,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0x3e3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P3; goto extract_sfmt_move_c_sprv32_p0; } - itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 4 : - { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) - { - case 0 : /* fall through */ - case 1 : /* fall through */ - case 2 : /* fall through */ - case 3 : /* fall through */ - case 4 : /* fall through */ - case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : - if ((base_insn & 0xbf0) == 0xa30) - { itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32; } - itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : - if ((base_insn & 0xffff) == 0x4e3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P4; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P3; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -1948,7 +1861,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0x5e3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P5; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P5; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -1978,7 +1891,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0x6e3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P6; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P6; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -2008,37 +1921,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0x7e3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P7; goto extract_sfmt_move_c_sprv32_p0; } - itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 8 : - { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) - { - case 0 : /* fall through */ - case 1 : /* fall through */ - case 2 : /* fall through */ - case 3 : /* fall through */ - case 4 : /* fall through */ - case 5 : /* fall through */ - case 6 : /* fall through */ - case 7 : /* fall through */ - case 8 : /* fall through */ - case 9 : /* fall through */ - case 10 : /* fall through */ - case 11 : /* fall through */ - case 12 : /* fall through */ - case 13 : /* fall through */ - case 14 : - if ((base_insn & 0xbf0) == 0xa30) - { itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32; } - itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; - case 15 : - if ((base_insn & 0xffff) == 0x8e3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P8; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P7; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -2068,7 +1951,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0x9e3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P9; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P9; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -2098,7 +1981,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0xae3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P10; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P10; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -2128,7 +2011,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0xbe3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P11; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P11; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -2158,7 +2041,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0xce3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P12; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P12; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -2188,7 +2071,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0xde3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P13; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P13; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -2218,7 +2101,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0xee3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P14; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P14; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -2248,7 +2131,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 15 : if ((base_insn & 0xffff) == 0xfe3f) - { itype = CRISV32F_INSN_MOVE_C_SPRV32_P15; goto extract_sfmt_move_c_sprv32_p0; } + { itype = CRISV32F_INSN_MOVE_C_SPRV32_P15; goto extract_sfmt_move_c_sprv32_p2; } itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; } @@ -3640,11 +3523,11 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_sfmt_move_c_sprv32_p0: + extract_sfmt_move_c_sprv32_p2: { const IDESC *idesc = &crisv32f_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f INT f_indir_pc__dword; UINT f_operand2; /* Contents of trailing part of insn. */ @@ -3657,7 +3540,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_indir_pc__dword) = f_indir_pc__dword; FLD (f_operand2) = f_operand2; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_c_sprv32_p0", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, "f_operand2 0x%x", 'x', f_operand2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_c_sprv32_p2", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, "f_operand2 0x%x", 'x', f_operand2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5456,7 +5339,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &crisv32f_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f INT f_indir_pc__dword; UINT f_operand2; /* Contents of trailing part of insn. */ diff --git a/sim/cris/decodev32.h b/sim/cris/decodev32.h index 5975c20ae57..88ee5ca7aec 100644 --- a/sim/cris/decodev32.h +++ b/sim/cris/decodev32.h @@ -46,9 +46,8 @@ typedef enum crisv32f_insn_type { , CRISV32F_INSN_CMPSCWR, CRISV32F_INSN_CMPU_M_B_M, CRISV32F_INSN_CMPU_M_W_M, CRISV32F_INSN_CMPUCBR , CRISV32F_INSN_CMPUCWR, CRISV32F_INSN_MOVE_M_B_M, CRISV32F_INSN_MOVE_M_W_M, CRISV32F_INSN_MOVE_M_D_M , CRISV32F_INSN_MOVS_M_B_M, CRISV32F_INSN_MOVS_M_W_M, CRISV32F_INSN_MOVU_M_B_M, CRISV32F_INSN_MOVU_M_W_M - , CRISV32F_INSN_MOVE_R_SPRV32, CRISV32F_INSN_MOVE_SPR_RV32, CRISV32F_INSN_MOVE_M_SPRV32, CRISV32F_INSN_MOVE_C_SPRV32_P0 - , CRISV32F_INSN_MOVE_C_SPRV32_P1, CRISV32F_INSN_MOVE_C_SPRV32_P2, CRISV32F_INSN_MOVE_C_SPRV32_P3, CRISV32F_INSN_MOVE_C_SPRV32_P4 - , CRISV32F_INSN_MOVE_C_SPRV32_P5, CRISV32F_INSN_MOVE_C_SPRV32_P6, CRISV32F_INSN_MOVE_C_SPRV32_P7, CRISV32F_INSN_MOVE_C_SPRV32_P8 + , CRISV32F_INSN_MOVE_R_SPRV32, CRISV32F_INSN_MOVE_SPR_RV32, CRISV32F_INSN_MOVE_M_SPRV32, CRISV32F_INSN_MOVE_C_SPRV32_P2 + , CRISV32F_INSN_MOVE_C_SPRV32_P3, CRISV32F_INSN_MOVE_C_SPRV32_P5, CRISV32F_INSN_MOVE_C_SPRV32_P6, CRISV32F_INSN_MOVE_C_SPRV32_P7 , CRISV32F_INSN_MOVE_C_SPRV32_P9, CRISV32F_INSN_MOVE_C_SPRV32_P10, CRISV32F_INSN_MOVE_C_SPRV32_P11, CRISV32F_INSN_MOVE_C_SPRV32_P12 , CRISV32F_INSN_MOVE_C_SPRV32_P13, CRISV32F_INSN_MOVE_C_SPRV32_P14, CRISV32F_INSN_MOVE_C_SPRV32_P15, CRISV32F_INSN_MOVE_SPR_MV32 , CRISV32F_INSN_MOVE_SS_R, CRISV32F_INSN_MOVE_R_SS, CRISV32F_INSN_MOVEM_R_M_V32, CRISV32F_INSN_MOVEM_M_R_V32 @@ -100,7 +99,7 @@ typedef enum crisv32f_sfmt_type { , CRISV32F_SFMT_CMP_M_D_M, CRISV32F_SFMT_CMPCBR, CRISV32F_SFMT_CMPCWR, CRISV32F_SFMT_CMPCDR , CRISV32F_SFMT_CMPQ, CRISV32F_SFMT_CMPUCBR, CRISV32F_SFMT_CMPUCWR, CRISV32F_SFMT_MOVE_M_B_M , CRISV32F_SFMT_MOVE_M_W_M, CRISV32F_SFMT_MOVE_M_D_M, CRISV32F_SFMT_MOVS_M_B_M, CRISV32F_SFMT_MOVS_M_W_M - , CRISV32F_SFMT_MOVE_R_SPRV32, CRISV32F_SFMT_MOVE_SPR_RV32, CRISV32F_SFMT_MOVE_M_SPRV32, CRISV32F_SFMT_MOVE_C_SPRV32_P0 + , CRISV32F_SFMT_MOVE_R_SPRV32, CRISV32F_SFMT_MOVE_SPR_RV32, CRISV32F_SFMT_MOVE_M_SPRV32, CRISV32F_SFMT_MOVE_C_SPRV32_P2 , CRISV32F_SFMT_MOVE_SPR_MV32, CRISV32F_SFMT_MOVE_SS_R, CRISV32F_SFMT_MOVE_R_SS, CRISV32F_SFMT_MOVEM_R_M_V32 , CRISV32F_SFMT_MOVEM_M_R_V32, CRISV32F_SFMT_ADD_B_R, CRISV32F_SFMT_ADD_D_R, CRISV32F_SFMT_ADD_M_B_M , CRISV32F_SFMT_ADD_M_W_M, CRISV32F_SFMT_ADD_M_D_M, CRISV32F_SFMT_ADDCBR, CRISV32F_SFMT_ADDCWR diff --git a/sim/cris/modelv10.c b/sim/cris/modelv10.c index 05643b56878..78b16318e77 100644 --- a/sim/cris/modelv10.c +++ b/sim/cris/modelv10.c @@ -947,73 +947,10 @@ model_crisv10_move_m_sprv10 (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_crisv10_move_c_sprv10_p0 (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced); - } - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced); - } - return cycles; -#undef FLD -} - -static int -model_crisv10_move_c_sprv10_p1 (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced); - } - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced); - } - return cycles; -#undef FLD -} - -static int -model_crisv10_move_c_sprv10_p4 (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced); - } - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced); - } - return cycles; -#undef FLD -} - static int model_crisv10_move_c_sprv10_p5 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p5.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1031,31 +968,10 @@ model_crisv10_move_c_sprv10_p5 (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_crisv10_move_c_sprv10_p8 (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced); - } - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced); - } - return cycles; -#undef FLD -} - static int model_crisv10_move_c_sprv10_p9 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1076,7 +992,7 @@ model_crisv10_move_c_sprv10_p9 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv10_move_c_sprv10_p10 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1097,7 +1013,7 @@ model_crisv10_move_c_sprv10_p10 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv10_move_c_sprv10_p11 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1118,7 +1034,7 @@ model_crisv10_move_c_sprv10_p11 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv10_move_c_sprv10_p12 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1139,7 +1055,7 @@ model_crisv10_move_c_sprv10_p12 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv10_move_c_sprv10_p13 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1160,7 +1076,7 @@ model_crisv10_move_c_sprv10_p13 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv10_move_c_sprv10_p7 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1181,7 +1097,7 @@ model_crisv10_move_c_sprv10_p7 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv10_move_c_sprv10_p14 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1202,7 +1118,7 @@ model_crisv10_move_c_sprv10_p14 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv10_move_c_sprv10_p15 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1503,7 +1419,7 @@ model_crisv10_addcdr (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv10_addcpc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3368,7 +3284,7 @@ model_crisv10_jump_m (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv10_jump_c (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3640,6 +3556,69 @@ model_crisv10_bdapqpc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_crisv10_bdap_32_pc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced); + } + return cycles; +#undef FLD +} + +static int +model_crisv10_move_m_pcplus_p0 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced); + } + return cycles; +#undef FLD +} + +static int +model_crisv10_move_m_spplus_p8 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced); + } + return cycles; +#undef FLD +} + static int model_crisv10_addo_m_b_m (SIM_CPU *current_cpu, void *sem_arg) { @@ -3790,7 +3769,7 @@ model_crisv10_dip_m (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv10_dip_c (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3964,11 +3943,7 @@ static const INSN_TIMING crisv10_timing[] = { { CRISV10F_INSN_MOVE_SPR_RV10, model_crisv10_move_spr_rv10, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, { CRISV10F_INSN_RET_TYPE, model_crisv10_ret_type, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, { CRISV10F_INSN_MOVE_M_SPRV10, model_crisv10_move_m_sprv10, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, - { CRISV10F_INSN_MOVE_C_SPRV10_P0, model_crisv10_move_c_sprv10_p0, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, - { CRISV10F_INSN_MOVE_C_SPRV10_P1, model_crisv10_move_c_sprv10_p1, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, - { CRISV10F_INSN_MOVE_C_SPRV10_P4, model_crisv10_move_c_sprv10_p4, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, { CRISV10F_INSN_MOVE_C_SPRV10_P5, model_crisv10_move_c_sprv10_p5, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, - { CRISV10F_INSN_MOVE_C_SPRV10_P8, model_crisv10_move_c_sprv10_p8, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, { CRISV10F_INSN_MOVE_C_SPRV10_P9, model_crisv10_move_c_sprv10_p9, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, { CRISV10F_INSN_MOVE_C_SPRV10_P10, model_crisv10_move_c_sprv10_p10, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, { CRISV10F_INSN_MOVE_C_SPRV10_P11, model_crisv10_move_c_sprv10_p11, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, @@ -4106,6 +4081,9 @@ static const INSN_TIMING crisv10_timing[] = { { CRISV10F_INSN_LZ, model_crisv10_lz, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, { CRISV10F_INSN_ADDOQ, model_crisv10_addoq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, { CRISV10F_INSN_BDAPQPC, model_crisv10_bdapqpc, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, + { CRISV10F_INSN_BDAP_32_PC, model_crisv10_bdap_32_pc, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, + { CRISV10F_INSN_MOVE_M_PCPLUS_P0, model_crisv10_move_m_pcplus_p0, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, + { CRISV10F_INSN_MOVE_M_SPPLUS_P8, model_crisv10_move_m_spplus_p8, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, { CRISV10F_INSN_ADDO_M_B_M, model_crisv10_addo_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, { CRISV10F_INSN_ADDO_M_W_M, model_crisv10_addo_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, { CRISV10F_INSN_ADDO_M_D_M, model_crisv10_addo_m_d_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } }, diff --git a/sim/cris/modelv32.c b/sim/cris/modelv32.c index b38983f6c54..174c64146f2 100644 --- a/sim/cris/modelv32.c +++ b/sim/cris/modelv32.c @@ -1276,60 +1276,10 @@ model_crisv32_move_m_sprv32 (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_crisv32_move_c_sprv32_p0 (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced); - } - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_Rs = -1; - INT out_Pd = -1; - out_Pd = FLD (out_Pd); - referenced |= 1 << 1; - cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd); - } - return cycles; -#undef FLD -} - -static int -model_crisv32_move_c_sprv32_p1 (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced); - } - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_Rs = -1; - INT out_Pd = -1; - out_Pd = FLD (out_Pd); - referenced |= 1 << 1; - cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd); - } - return cycles; -#undef FLD -} - static int model_crisv32_move_c_sprv32_p2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1354,32 +1304,7 @@ model_crisv32_move_c_sprv32_p2 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_move_c_sprv32_p3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced); - } - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_Rs = -1; - INT out_Pd = -1; - out_Pd = FLD (out_Pd); - referenced |= 1 << 1; - cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd); - } - return cycles; -#undef FLD -} - -static int -model_crisv32_move_c_sprv32_p4 (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1404,7 +1329,7 @@ model_crisv32_move_c_sprv32_p4 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_move_c_sprv32_p5 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1429,7 +1354,7 @@ model_crisv32_move_c_sprv32_p5 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_move_c_sprv32_p6 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1454,32 +1379,7 @@ model_crisv32_move_c_sprv32_p6 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_move_c_sprv32_p7 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced); - } - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_Rs = -1; - INT out_Pd = -1; - out_Pd = FLD (out_Pd); - referenced |= 1 << 1; - cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd); - } - return cycles; -#undef FLD -} - -static int -model_crisv32_move_c_sprv32_p8 (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1504,7 +1404,7 @@ model_crisv32_move_c_sprv32_p8 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_move_c_sprv32_p9 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1529,7 +1429,7 @@ model_crisv32_move_c_sprv32_p9 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_move_c_sprv32_p10 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1554,7 +1454,7 @@ model_crisv32_move_c_sprv32_p10 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_move_c_sprv32_p11 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1579,7 +1479,7 @@ model_crisv32_move_c_sprv32_p11 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_move_c_sprv32_p12 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1604,7 +1504,7 @@ model_crisv32_move_c_sprv32_p12 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_move_c_sprv32_p13 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1629,7 +1529,7 @@ model_crisv32_move_c_sprv32_p13 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_move_c_sprv32_p14 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1654,7 +1554,7 @@ model_crisv32_move_c_sprv32_p14 (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_move_c_sprv32_p15 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4986,7 +4886,7 @@ model_crisv32_jas_r (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_jas_c (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5119,7 +5019,7 @@ model_crisv32_jasc_r (SIM_CPU *current_cpu, void *sem_arg) static int model_crisv32_jasc_c (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5827,15 +5727,11 @@ static const INSN_TIMING crisv32_timing[] = { { CRISV32F_INSN_MOVE_R_SPRV32, model_crisv32_move_r_sprv32, { { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, { CRISV32F_INSN_MOVE_SPR_RV32, model_crisv32_move_spr_rv32, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } }, { CRISV32F_INSN_MOVE_M_SPRV32, model_crisv32_move_m_sprv32, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, - { CRISV32F_INSN_MOVE_C_SPRV32_P0, model_crisv32_move_c_sprv32_p0, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, - { CRISV32F_INSN_MOVE_C_SPRV32_P1, model_crisv32_move_c_sprv32_p1, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, { CRISV32F_INSN_MOVE_C_SPRV32_P2, model_crisv32_move_c_sprv32_p2, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, { CRISV32F_INSN_MOVE_C_SPRV32_P3, model_crisv32_move_c_sprv32_p3, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, - { CRISV32F_INSN_MOVE_C_SPRV32_P4, model_crisv32_move_c_sprv32_p4, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, { CRISV32F_INSN_MOVE_C_SPRV32_P5, model_crisv32_move_c_sprv32_p5, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, { CRISV32F_INSN_MOVE_C_SPRV32_P6, model_crisv32_move_c_sprv32_p6, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, { CRISV32F_INSN_MOVE_C_SPRV32_P7, model_crisv32_move_c_sprv32_p7, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, - { CRISV32F_INSN_MOVE_C_SPRV32_P8, model_crisv32_move_c_sprv32_p8, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, { CRISV32F_INSN_MOVE_C_SPRV32_P9, model_crisv32_move_c_sprv32_p9, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, { CRISV32F_INSN_MOVE_C_SPRV32_P10, model_crisv32_move_c_sprv32_p10, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, { CRISV32F_INSN_MOVE_C_SPRV32_P11, model_crisv32_move_c_sprv32_p11, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } }, diff --git a/sim/cris/semcrisv10f-switch.c b/sim/cris/semcrisv10f-switch.c index 1479916f9f4..7f901655ff0 100644 --- a/sim/cris/semcrisv10f-switch.c +++ b/sim/cris/semcrisv10f-switch.c @@ -86,11 +86,7 @@ with this program; if not, write to the Free Software Foundation, Inc., { CRISV10F_INSN_MOVE_SPR_RV10, && case_sem_INSN_MOVE_SPR_RV10 }, { CRISV10F_INSN_RET_TYPE, && case_sem_INSN_RET_TYPE }, { CRISV10F_INSN_MOVE_M_SPRV10, && case_sem_INSN_MOVE_M_SPRV10 }, - { CRISV10F_INSN_MOVE_C_SPRV10_P0, && case_sem_INSN_MOVE_C_SPRV10_P0 }, - { CRISV10F_INSN_MOVE_C_SPRV10_P1, && case_sem_INSN_MOVE_C_SPRV10_P1 }, - { CRISV10F_INSN_MOVE_C_SPRV10_P4, && case_sem_INSN_MOVE_C_SPRV10_P4 }, { CRISV10F_INSN_MOVE_C_SPRV10_P5, && case_sem_INSN_MOVE_C_SPRV10_P5 }, - { CRISV10F_INSN_MOVE_C_SPRV10_P8, && case_sem_INSN_MOVE_C_SPRV10_P8 }, { CRISV10F_INSN_MOVE_C_SPRV10_P9, && case_sem_INSN_MOVE_C_SPRV10_P9 }, { CRISV10F_INSN_MOVE_C_SPRV10_P10, && case_sem_INSN_MOVE_C_SPRV10_P10 }, { CRISV10F_INSN_MOVE_C_SPRV10_P11, && case_sem_INSN_MOVE_C_SPRV10_P11 }, @@ -228,6 +224,9 @@ with this program; if not, write to the Free Software Foundation, Inc., { CRISV10F_INSN_LZ, && case_sem_INSN_LZ }, { CRISV10F_INSN_ADDOQ, && case_sem_INSN_ADDOQ }, { CRISV10F_INSN_BDAPQPC, && case_sem_INSN_BDAPQPC }, + { CRISV10F_INSN_BDAP_32_PC, && case_sem_INSN_BDAP_32_PC }, + { CRISV10F_INSN_MOVE_M_PCPLUS_P0, && case_sem_INSN_MOVE_M_PCPLUS_P0 }, + { CRISV10F_INSN_MOVE_M_SPPLUS_P8, && case_sem_INSN_MOVE_M_SPPLUS_P8 }, { CRISV10F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M }, { CRISV10F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M }, { CRISV10F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M }, @@ -3183,55 +3182,43 @@ cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special regi SI tmp_newval; tmp_prno = FLD (f_operand2); tmp_newval = GET_H_SR (FLD (f_operand2)); -if (EQSI (tmp_prno, 0)) { +if (EQSI (tmp_prno, 5)) { { SI tmp_oldregval; tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1)); { - SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); + SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } } - else if (EQSI (tmp_prno, 1)) { -{ - SI tmp_oldregval; - tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1)); + else if (EQSI (tmp_prno, 9)) { { - SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); + SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } -} - else if (EQSI (tmp_prno, 4)) { -{ - SI tmp_oldregval; - tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1)); + else if (EQSI (tmp_prno, 10)) { { - SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); + SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } -} - else if (EQSI (tmp_prno, 5)) { -{ - SI tmp_oldregval; - tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1)); + else if (EQSI (tmp_prno, 11)) { { - SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); + SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } -} - else if (EQSI (tmp_prno, 8)) { + else if (EQSI (tmp_prno, 12)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3239,7 +3226,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 9)) { + else if (EQSI (tmp_prno, 13)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3247,31 +3234,43 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 10)) { + else if (EQSI (tmp_prno, 0)) { +{ + SI tmp_oldregval; + tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1)); { - SI opval = tmp_newval; + SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 11)) { +} + else if (EQSI (tmp_prno, 1)) { +{ + SI tmp_oldregval; + tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1)); { - SI opval = tmp_newval; + SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 12)) { +} + else if (EQSI (tmp_prno, 4)) { +{ + SI tmp_oldregval; + tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1)); { - SI opval = tmp_newval; + SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 13)) { +} + else if (EQSI (tmp_prno, 8)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3377,51 +3376,7 @@ cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register"); SI tmp_rno; SI tmp_newval; tmp_rno = FLD (f_operand2); -if (EQSI (tmp_rno, 0)) { - tmp_newval = EXTQISI (({ SI tmp_addr; - QI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32))); -; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; })); -} - else if (EQSI (tmp_rno, 1)) { - tmp_newval = EXTQISI (({ SI tmp_addr; - QI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32))); -; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; })); -} - else if (EQSI (tmp_rno, 4)) { +if (EQSI (tmp_rno, 5)) { tmp_newval = EXTHISI (({ SI tmp_addr; HI tmp_tmp_mem; BI tmp_postinc; @@ -3436,56 +3391,12 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; })); -} - else if (EQSI (tmp_rno, 5)) { - tmp_newval = EXTHISI (({ SI tmp_addr; - HI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32))); -; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 2); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } } ; tmp_tmp_mem; })); -} - else if (EQSI (tmp_rno, 8)) { - tmp_newval = ({ SI tmp_addr; - SI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32))); -; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; }); } else if (EQSI (tmp_rno, 9)) { tmp_newval = ({ SI tmp_addr; @@ -3502,7 +3413,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3524,7 +3435,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3546,7 +3457,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3568,7 +3479,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3590,7 +3501,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3612,7 +3523,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3634,7 +3545,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3656,151 +3567,18 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } } -; tmp_tmp_mem; }); -} - else { -cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); -} - { - SI opval = tmp_newval; - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - - abuf->written = written; -#undef FLD -} - NEXT (vpc); - - CASE (sem, INSN_MOVE_C_SPRV10_P0) : /* move ${sconst8},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - { - SI opval = FLD (f_indir_pc__byte); - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - -#undef FLD -} - NEXT (vpc); - - CASE (sem, INSN_MOVE_C_SPRV10_P1) : /* move ${sconst8},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - { - SI opval = FLD (f_indir_pc__byte); - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - -#undef FLD -} - NEXT (vpc); - - CASE (sem, INSN_MOVE_C_SPRV10_P4) : /* move ${sconst16},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - { - SI opval = FLD (f_indir_pc__word); - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - -#undef FLD -} - NEXT (vpc); - - CASE (sem, INSN_MOVE_C_SPRV10_P5) : /* move ${sconst16},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ +; tmp_tmp_mem; }); +} + else { +cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); +} { - SI opval = FLD (f_indir_pc__word); + SI opval = tmp_newval; SET_H_SR (FLD (f_operand2), opval); TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); } @@ -3818,22 +3596,23 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); } } + abuf->written = written; #undef FLD } NEXT (vpc); - CASE (sem, INSN_MOVE_C_SPRV10_P8) : /* move ${const32},${Pd} */ + CASE (sem, INSN_MOVE_C_SPRV10_P5) : /* move ${sconst16},${Pd} */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p5.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 6); + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { { - SI opval = FLD (f_indir_pc__dword); + SI opval = FLD (f_indir_pc__word); SET_H_SR (FLD (f_operand2), opval); TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); } @@ -3859,7 +3638,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3892,7 +3671,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3925,7 +3704,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3958,7 +3737,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3991,7 +3770,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4024,7 +3803,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4057,7 +3836,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4090,7 +3869,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4131,7 +3910,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SI tmp_rno; tmp_rno = FLD (f_operand2); -if (EQSI (tmp_rno, 0)) { +if (EQSI (tmp_rno, 5)) { { SI tmp_addr; BI tmp_postinc; @@ -4141,9 +3920,9 @@ if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + HI opval = GET_H_SR (FLD (f_operand2)); + SETMEMHI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4163,16 +3942,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + HI opval = GET_H_SR (FLD (f_operand2)); + SETMEMHI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); + tmp_addr = ADDSI (tmp_addr, 2); } { SI opval = tmp_addr; @@ -4184,7 +3963,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 1)) { + else if (EQSI (tmp_rno, 9)) { { SI tmp_addr; BI tmp_postinc; @@ -4194,9 +3973,9 @@ if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4216,16 +3995,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); + tmp_addr = ADDSI (tmp_addr, 4); } { SI opval = tmp_addr; @@ -4237,7 +4016,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 4)) { + else if (EQSI (tmp_rno, 10)) { { SI tmp_addr; BI tmp_postinc; @@ -4247,9 +4026,9 @@ if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - HI opval = GET_H_SR (FLD (f_operand2)); - SETMEMHI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 11); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4269,16 +4048,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - HI opval = GET_H_SR (FLD (f_operand2)); - SETMEMHI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 11); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 2); + tmp_addr = ADDSI (tmp_addr, 4); } { SI opval = tmp_addr; @@ -4290,7 +4069,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 5)) { + else if (EQSI (tmp_rno, 11)) { { SI tmp_addr; BI tmp_postinc; @@ -4300,9 +4079,9 @@ if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - HI opval = GET_H_SR (FLD (f_operand2)); - SETMEMHI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 11); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4322,16 +4101,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - HI opval = GET_H_SR (FLD (f_operand2)); - SETMEMHI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 11); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 2); + tmp_addr = ADDSI (tmp_addr, 4); } { SI opval = tmp_addr; @@ -4343,7 +4122,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 8)) { + else if (EQSI (tmp_rno, 12)) { { SI tmp_addr; BI tmp_postinc; @@ -4396,7 +4175,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 9)) { + else if (EQSI (tmp_rno, 13)) { { SI tmp_addr; BI tmp_postinc; @@ -4449,7 +4228,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 10)) { + else if (EQSI (tmp_rno, 0)) { { SI tmp_addr; BI tmp_postinc; @@ -4459,9 +4238,9 @@ if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4481,16 +4260,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); + tmp_addr = ADDSI (tmp_addr, 1); } { SI opval = tmp_addr; @@ -4502,7 +4281,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 11)) { + else if (EQSI (tmp_rno, 1)) { { SI tmp_addr; BI tmp_postinc; @@ -4512,9 +4291,9 @@ if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4534,16 +4313,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); + tmp_addr = ADDSI (tmp_addr, 1); } { SI opval = tmp_addr; @@ -4555,7 +4334,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 12)) { + else if (EQSI (tmp_rno, 4)) { { SI tmp_addr; BI tmp_postinc; @@ -4565,9 +4344,9 @@ if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + HI opval = GET_H_SR (FLD (f_operand2)); + SETMEMHI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4587,16 +4366,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + HI opval = GET_H_SR (FLD (f_operand2)); + SETMEMHI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); + tmp_addr = ADDSI (tmp_addr, 2); } { SI opval = tmp_addr; @@ -4608,7 +4387,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 13)) { + else if (EQSI (tmp_rno, 8)) { { SI tmp_addr; BI tmp_postinc; @@ -6210,7 +5989,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -12632,7 +12411,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -13656,6 +13435,152 @@ cris_flush_simulator_decode_cache (current_cpu, pc); } NEXT (vpc); + CASE (sem, INSN_BDAP_32_PC) : /* bdap ${sconst32},PC */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 6); + +{ + SI tmp_newpc; + SI tmp_oldpc; + SI tmp_offs; + tmp_offs = FLD (f_indir_pc__dword); + tmp_oldpc = ADDSI (pc, 6); + tmp_newpc = ADDSI (tmp_oldpc, tmp_offs); + { + SI opval = tmp_newpc; + CPU (h_prefixreg_pre_v32) = opval; + TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval); + } + { + BI opval = 1; + SET_H_INSN_PREFIXED_P (opval); + TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MOVE_M_PCPLUS_P0) : /* move [PC+],P0 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (GET_H_INSN_PREFIXED_P ()) { +{ + QI tmp_dummy; + tmp_dummy = ({ SI tmp_addr; + QI tmp_tmp_mem; + BI tmp_postinc; + tmp_postinc = FLD (f_memmode); +; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (pc) : (CPU (h_prefixreg_pre_v32))); +; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); +; if (NEBI (tmp_postinc, 0)) { +{ +if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { + tmp_addr = ADDSI (tmp_addr, 1); +} + { + USI opval = tmp_addr; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +; tmp_tmp_mem; }); +{ + { + BI opval = 0; + CPU (h_xbit) = opval; + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); + } + { + BI opval = 0; + SET_H_INSN_PREFIXED_P (opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); + } +} +} +} else { +cgen_rtx_error (current_cpu, "move [PC+],P0 without prefix is not implemented"); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MOVE_M_SPPLUS_P8) : /* move [SP+],P8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (GET_H_INSN_PREFIXED_P ()) { +{ + SI tmp_dummy; + tmp_dummy = ({ SI tmp_addr; + SI tmp_tmp_mem; + BI tmp_postinc; + tmp_postinc = FLD (f_memmode); +; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (((UINT) 14))) : (CPU (h_prefixreg_pre_v32))); +; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); +; if (NEBI (tmp_postinc, 0)) { +{ +if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { + tmp_addr = ADDSI (tmp_addr, 4); +} + { + SI opval = tmp_addr; + SET_H_GR (((UINT) 14), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} +; tmp_tmp_mem; }); +{ + { + BI opval = 0; + CPU (h_xbit) = opval; + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); + } + { + BI opval = 0; + SET_H_INSN_PREFIXED_P (opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); + } +} +} +} else { +cgen_rtx_error (current_cpu, "move [SP+],P8 without prefix is not implemented"); +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); @@ -13930,7 +13855,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); diff --git a/sim/cris/semcrisv32f-switch.c b/sim/cris/semcrisv32f-switch.c index 106b71825c2..65c1c0ab86d 100644 --- a/sim/cris/semcrisv32f-switch.c +++ b/sim/cris/semcrisv32f-switch.c @@ -83,15 +83,11 @@ with this program; if not, write to the Free Software Foundation, Inc., { CRISV32F_INSN_MOVE_R_SPRV32, && case_sem_INSN_MOVE_R_SPRV32 }, { CRISV32F_INSN_MOVE_SPR_RV32, && case_sem_INSN_MOVE_SPR_RV32 }, { CRISV32F_INSN_MOVE_M_SPRV32, && case_sem_INSN_MOVE_M_SPRV32 }, - { CRISV32F_INSN_MOVE_C_SPRV32_P0, && case_sem_INSN_MOVE_C_SPRV32_P0 }, - { CRISV32F_INSN_MOVE_C_SPRV32_P1, && case_sem_INSN_MOVE_C_SPRV32_P1 }, { CRISV32F_INSN_MOVE_C_SPRV32_P2, && case_sem_INSN_MOVE_C_SPRV32_P2 }, { CRISV32F_INSN_MOVE_C_SPRV32_P3, && case_sem_INSN_MOVE_C_SPRV32_P3 }, - { CRISV32F_INSN_MOVE_C_SPRV32_P4, && case_sem_INSN_MOVE_C_SPRV32_P4 }, { CRISV32F_INSN_MOVE_C_SPRV32_P5, && case_sem_INSN_MOVE_C_SPRV32_P5 }, { CRISV32F_INSN_MOVE_C_SPRV32_P6, && case_sem_INSN_MOVE_C_SPRV32_P6 }, { CRISV32F_INSN_MOVE_C_SPRV32_P7, && case_sem_INSN_MOVE_C_SPRV32_P7 }, - { CRISV32F_INSN_MOVE_C_SPRV32_P8, && case_sem_INSN_MOVE_C_SPRV32_P8 }, { CRISV32F_INSN_MOVE_C_SPRV32_P9, && case_sem_INSN_MOVE_C_SPRV32_P9 }, { CRISV32F_INSN_MOVE_C_SPRV32_P10, && case_sem_INSN_MOVE_C_SPRV32_P10 }, { CRISV32F_INSN_MOVE_C_SPRV32_P11, && case_sem_INSN_MOVE_C_SPRV32_P11 }, @@ -3113,7 +3109,7 @@ cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special regi SI tmp_newval; tmp_prno = FLD (f_operand2); tmp_newval = GET_H_SR (FLD (f_operand2)); -if (EQSI (tmp_prno, 0)) { +if (EQSI (tmp_prno, 2)) { { SI tmp_oldregval; tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); @@ -3125,7 +3121,7 @@ if (EQSI (tmp_prno, 0)) { } } } - else if (EQSI (tmp_prno, 1)) { + else if (EQSI (tmp_prno, 3)) { { SI tmp_oldregval; tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); @@ -3137,43 +3133,31 @@ if (EQSI (tmp_prno, 0)) { } } } - else if (EQSI (tmp_prno, 2)) { -{ - SI tmp_oldregval; - tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); + else if (EQSI (tmp_prno, 5)) { { - SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); + SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } -} - else if (EQSI (tmp_prno, 3)) { -{ - SI tmp_oldregval; - tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); + else if (EQSI (tmp_prno, 6)) { { - SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); + SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } -} - else if (EQSI (tmp_prno, 4)) { -{ - SI tmp_oldregval; - tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); + else if (EQSI (tmp_prno, 7)) { { - SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); + SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } -} - else if (EQSI (tmp_prno, 5)) { + else if (EQSI (tmp_prno, 9)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3181,7 +3165,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 6)) { + else if (EQSI (tmp_prno, 10)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3189,7 +3173,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 7)) { + else if (EQSI (tmp_prno, 11)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3197,7 +3181,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 8)) { + else if (EQSI (tmp_prno, 12)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3205,7 +3189,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 9)) { + else if (EQSI (tmp_prno, 13)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3213,7 +3197,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 10)) { + else if (EQSI (tmp_prno, 14)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3221,7 +3205,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 11)) { + else if (EQSI (tmp_prno, 15)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3229,31 +3213,43 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 12)) { + else if (EQSI (tmp_prno, 0)) { +{ + SI tmp_oldregval; + tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); { - SI opval = tmp_newval; + SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 13)) { +} + else if (EQSI (tmp_prno, 1)) { +{ + SI tmp_oldregval; + tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); { - SI opval = tmp_newval; + SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 14)) { +} + else if (EQSI (tmp_prno, 4)) { +{ + SI tmp_oldregval; + tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); { - SI opval = tmp_newval; + SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 15)) { +} + else if (EQSI (tmp_prno, 8)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3296,7 +3292,7 @@ cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register"); SI tmp_rno; SI tmp_newval; tmp_rno = FLD (f_operand2); -if (EQSI (tmp_rno, 0)) { +if (EQSI (tmp_rno, 2)) { tmp_newval = EXTQISI (({ SI tmp_addr; QI tmp_tmp_mem; BI tmp_postinc; @@ -3311,51 +3307,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; })); -} - else if (EQSI (tmp_rno, 1)) { - tmp_newval = EXTQISI (({ SI tmp_addr; - QI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); -; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; })); -} - else if (EQSI (tmp_rno, 2)) { - tmp_newval = EXTQISI (({ SI tmp_addr; - QI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); -; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3377,29 +3329,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; })); -} - else if (EQSI (tmp_rno, 4)) { - tmp_newval = EXTHISI (({ SI tmp_addr; - HI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); -; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 2); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3421,7 +3351,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3443,7 +3373,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3465,29 +3395,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; }); -} - else if (EQSI (tmp_rno, 8)) { - tmp_newval = ({ SI tmp_addr; - SI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); -; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3509,7 +3417,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3531,7 +3439,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3553,7 +3461,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3575,7 +3483,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3597,7 +3505,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3619,7 +3527,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3641,7 +3549,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3671,72 +3579,6 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); } abuf->written = written; -#undef FLD -} - NEXT (vpc); - - CASE (sem, INSN_MOVE_C_SPRV32_P0) : /* move ${const32},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 6); - -{ - { - SI opval = FLD (f_indir_pc__dword); - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - -#undef FLD -} - NEXT (vpc); - - CASE (sem, INSN_MOVE_C_SPRV32_P1) : /* move ${const32},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 6); - -{ - { - SI opval = FLD (f_indir_pc__dword); - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - #undef FLD } NEXT (vpc); @@ -3745,7 +3587,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3778,40 +3620,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 6); - -{ - { - SI opval = FLD (f_indir_pc__dword); - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - -#undef FLD -} - NEXT (vpc); - - CASE (sem, INSN_MOVE_C_SPRV32_P4) : /* move ${const32},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3844,7 +3653,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3877,7 +3686,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3910,40 +3719,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 6); - -{ - { - SI opval = FLD (f_indir_pc__dword); - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - -#undef FLD -} - NEXT (vpc); - - CASE (sem, INSN_MOVE_C_SPRV32_P8) : /* move ${const32},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3976,7 +3752,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4009,7 +3785,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4042,7 +3818,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4075,7 +3851,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4108,7 +3884,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4141,7 +3917,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4174,7 +3950,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4215,7 +3991,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SI tmp_rno; tmp_rno = FLD (f_operand2); -if (EQSI (tmp_rno, 0)) { +if (EQSI (tmp_rno, 2)) { { SI tmp_addr; BI tmp_postinc; @@ -4268,7 +4044,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 1)) { + else if (EQSI (tmp_rno, 3)) { { SI tmp_addr; BI tmp_postinc; @@ -4321,7 +4097,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 2)) { + else if (EQSI (tmp_rno, 5)) { { SI tmp_addr; BI tmp_postinc; @@ -4331,9 +4107,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4353,16 +4129,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); + tmp_addr = ADDSI (tmp_addr, 4); } { SI opval = tmp_addr; @@ -4374,7 +4150,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 3)) { + else if (EQSI (tmp_rno, 6)) { { SI tmp_addr; BI tmp_postinc; @@ -4384,9 +4160,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4406,16 +4182,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); + tmp_addr = ADDSI (tmp_addr, 4); } { SI opval = tmp_addr; @@ -4427,7 +4203,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 4)) { + else if (EQSI (tmp_rno, 7)) { { SI tmp_addr; BI tmp_postinc; @@ -4437,9 +4213,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - HI opval = GET_H_SR (FLD (f_operand2)); - SETMEMHI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 11); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4459,16 +4235,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - HI opval = GET_H_SR (FLD (f_operand2)); - SETMEMHI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 11); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 2); + tmp_addr = ADDSI (tmp_addr, 4); } { SI opval = tmp_addr; @@ -4480,7 +4256,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 5)) { + else if (EQSI (tmp_rno, 9)) { { SI tmp_addr; BI tmp_postinc; @@ -4533,7 +4309,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 6)) { + else if (EQSI (tmp_rno, 10)) { { SI tmp_addr; BI tmp_postinc; @@ -4586,7 +4362,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 7)) { + else if (EQSI (tmp_rno, 11)) { { SI tmp_addr; BI tmp_postinc; @@ -4639,7 +4415,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 8)) { + else if (EQSI (tmp_rno, 12)) { { SI tmp_addr; BI tmp_postinc; @@ -4692,7 +4468,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 9)) { + else if (EQSI (tmp_rno, 13)) { { SI tmp_addr; BI tmp_postinc; @@ -4745,7 +4521,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 10)) { + else if (EQSI (tmp_rno, 14)) { { SI tmp_addr; BI tmp_postinc; @@ -4798,7 +4574,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 11)) { + else if (EQSI (tmp_rno, 15)) { { SI tmp_addr; BI tmp_postinc; @@ -4851,7 +4627,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 12)) { + else if (EQSI (tmp_rno, 0)) { { SI tmp_addr; BI tmp_postinc; @@ -4861,9 +4637,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4883,16 +4659,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); + tmp_addr = ADDSI (tmp_addr, 1); } { SI opval = tmp_addr; @@ -4904,7 +4680,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 13)) { + else if (EQSI (tmp_rno, 1)) { { SI tmp_addr; BI tmp_postinc; @@ -4914,9 +4690,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4936,16 +4712,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); + tmp_addr = ADDSI (tmp_addr, 1); } { SI opval = tmp_addr; @@ -4957,7 +4733,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 14)) { + else if (EQSI (tmp_rno, 4)) { { SI tmp_addr; BI tmp_postinc; @@ -4967,9 +4743,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + HI opval = GET_H_SR (FLD (f_operand2)); + SETMEMHI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4989,16 +4765,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + HI opval = GET_H_SR (FLD (f_operand2)); + SETMEMHI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); + tmp_addr = ADDSI (tmp_addr, 2); } { SI opval = tmp_addr; @@ -5010,7 +4786,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 15)) { + else if (EQSI (tmp_rno, 8)) { { SI tmp_addr; BI tmp_postinc; @@ -12986,7 +12762,7 @@ cris_flush_simulator_decode_cache (current_cpu, pc); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -13155,7 +12931,7 @@ cris_flush_simulator_decode_cache (current_cpu, pc); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT