From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 29 May 2020 12:31:29 +0000 (+0100)
Subject: create rising pulse from ALU valid
X-Git-Tag: div_pipeline~752
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=394495c07f31a1b785cc951b97e6f9c69bb07a2c;p=soc.git

create rising pulse from ALU valid
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index f17fb6bb..4ef26bb3 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -177,6 +177,14 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.comb += wr_any.eq(self.wr.go.bool())
         m.d.comb += req_done.eq(rst_l.q & wr_any)
 
+        # create rising pulse from alu valid condition.
+        alu_done = Signal(reset_less=True)
+        alu_done_dly = Signal(reset_less=True)
+        alu_pulse = Signal(reset_less=True)
+        m.d.comb += alu_done.eq(self.alu.n.valid_o)
+        m.d.sync += alu_done_dly.eq(alu_done)
+        m.d.comb += alu_pulse.eq(alu_done & ~alu_done_dly)
+
         # shadow/go_die
         reset = Signal(reset_less=True)
         rst_r = Signal(reset_less=True) # reset latch off