From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 14 Feb 2019 01:08:32 +0000 (-0800)
Subject: Use module->addLut()
X-Git-Tag: working-ls180~1237^2~337
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=396da54b5297e644087c63cd7bfb244e7ae81e3a;p=yosys.git

Use module->addLut()
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 62354498c..931d2fd36 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -227,11 +227,7 @@ void AigerReader::parse_xaiger()
                     RTLIL::Cell *output_cell = module->cell(stringf("\\n%d_and", rootNodeID));
                     log_assert(output_cell);
                     module->remove(output_cell);
-					RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
-					cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
-					cell->parameters["\\LUT"] = std::move(lut_mask);
-					cell->setPort("\\A", input_sig);
-					cell->setPort("\\Y", output_sig);
+					module->addLut(NEW_ID, input_sig, output_sig, std::move(lut_mask));
                 }
             }
             else if (c == 'n') {