From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 Jun 2018 05:59:45 +0000 (+0100)
Subject: add images
X-Git-Tag: convert-csv-opcode-to-binary~5313
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3974405d2fac2abac88d7ea150069d059781d463;p=libreriscv.git

add images
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index bcc69b37c..dca373267 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -443,12 +443,12 @@ for (int i = 0; i < VL; ++i)
 \frame{\frametitle{What's the downside(s) of SV?}
  \begin{itemize}
    \item EVERY register operation is inherently parallelised\\
-	     (scalar ops are just vectors of length 1)
+	     (scalar ops are just vectors of length 1)\vspace{8pt}
    \item An extra pipeline phase is pretty much essential\\
-         for fast low-latency implementations
+         for fast low-latency implementations\vspace{8pt}
    \item Assuming an instruction FIFO, N ops could be taken off\\
          of a parallel op per cycle (avoids filling entire FIFO;\\
-         also is less work per cycle: lower complexity / latency)
+         also is less work per cycle: lower complexity / latency)\vspace{8pt}
    \item With zeroing off, skipping non-predicated elements is hard:\\
          it is however an optimisation (and could be skipped).
   \end{itemize}