From: Gabe Black <gabeblack@google.com>
Date: Thu, 2 May 2019 08:33:31 +0000 (-0700)
Subject: cpu, sim: Return PortProxy &s from all the proxy accessors.
X-Git-Tag: v19.0.0.0~797
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39896bd265cfab20ab512cf4bceed7b38eca9d91;p=gem5.git

cpu, sim: Return PortProxy &s from all the proxy accessors.

This is a step towards merging the accessors for SE and FS modes.

Change-Id: I76818ab88b97097ac363e243be9cc1911b283090
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18579
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index ed8add662..46ade24bb 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -146,7 +146,7 @@ class CheckerThreadContext : public ThreadContext
 
     PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
 
-    FSTranslatingPortProxy &
+    PortProxy &
     getVirtProxy() override
     {
         return actualTC->getVirtProxy();
@@ -164,7 +164,7 @@ class CheckerThreadContext : public ThreadContext
         actualTC->connectMemPorts(tc);
     }
 
-    SETranslatingPortProxy &
+    PortProxy &
     getMemProxy() override
     {
         return actualTC->getMemProxy();
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index e5f01871b..a3698cf2e 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -132,7 +132,7 @@ class O3ThreadContext : public ThreadContext
 
     PortProxy &getPhysProxy() override { return thread->getPhysProxy(); }
 
-    FSTranslatingPortProxy &getVirtProxy() override;
+    PortProxy &getVirtProxy() override;
 
     void
     initMemProxies(ThreadContext *tc) override
@@ -140,7 +140,7 @@ class O3ThreadContext : public ThreadContext
         thread->initMemProxies(tc);
     }
 
-    SETranslatingPortProxy &
+    PortProxy &
     getMemProxy() override
     {
         return thread->getMemProxy();
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 58dee9814..e05721b99 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -54,7 +54,7 @@
 #include "debug/O3CPU.hh"
 
 template <class Impl>
-FSTranslatingPortProxy&
+PortProxy&
 O3ThreadContext<Impl>::getVirtProxy()
 {
     return thread->getVirtProxy();
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 8b5e49a3e..991c6bd80 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -216,18 +216,14 @@ class SimpleThread : public ThreadState, public ThreadContext
     }
 
     PortProxy &getPhysProxy() override { return ThreadState::getPhysProxy(); }
-    FSTranslatingPortProxy &
-    getVirtProxy() override
-    {
-        return ThreadState::getVirtProxy();
-    }
+    PortProxy &getVirtProxy() override { return ThreadState::getVirtProxy(); }
 
     void initMemProxies(ThreadContext *tc) override
     {
         ThreadState::initMemProxies(tc);
     }
 
-    SETranslatingPortProxy &
+    PortProxy &
     getMemProxy() override
     {
         return ThreadState::getMemProxy();
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index bdf5a0086..f8b69d096 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -65,8 +65,6 @@ class BaseTLB;
 class CheckerCPU;
 class Checkpoint;
 class EndQuiesceEvent;
-class SETranslatingPortProxy;
-class FSTranslatingPortProxy;
 class PortProxy;
 class Process;
 class System;
@@ -152,7 +150,7 @@ class ThreadContext
 
     virtual PortProxy &getPhysProxy() = 0;
 
-    virtual FSTranslatingPortProxy &getVirtProxy() = 0;
+    virtual PortProxy &getVirtProxy() = 0;
 
     /**
      * Initialise the physical and virtual port proxies and tie them to
@@ -162,7 +160,7 @@ class ThreadContext
      */
     virtual void initMemProxies(ThreadContext *tc) = 0;
 
-    virtual SETranslatingPortProxy &getMemProxy() = 0;
+    virtual PortProxy &getMemProxy() = 0;
 
     virtual Process *getProcessPtr() = 0;
 
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index acb297113..c9fc56487 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -133,7 +133,7 @@ ThreadState::getPhysProxy()
     return *physProxy;
 }
 
-FSTranslatingPortProxy &
+PortProxy &
 ThreadState::getVirtProxy()
 {
     assert(FullSystem);
@@ -141,7 +141,7 @@ ThreadState::getVirtProxy()
     return *virtProxy;
 }
 
-SETranslatingPortProxy &
+PortProxy &
 ThreadState::getMemProxy()
 {
     assert(!FullSystem);
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 200633922..e00c86f55 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -47,6 +47,9 @@ namespace Kernel {
 
 class Checkpoint;
 
+class FSTranslatingPortProxy;
+class SETranslatingPortProxy;
+
 /**
  *  Struct for holding general thread state that is needed across CPU
  *  models.  This includes things such as pointers to the process,
@@ -100,7 +103,7 @@ struct ThreadState : public Serializable {
 
     PortProxy &getPhysProxy();
 
-    FSTranslatingPortProxy &getVirtProxy();
+    PortProxy &getVirtProxy();
 
     Process *getProcessPtr() { return process; }
 
@@ -119,7 +122,7 @@ struct ThreadState : public Serializable {
         }
     }
 
-    SETranslatingPortProxy &getMemProxy();
+    PortProxy &getMemProxy();
 
     /** Reads the number of instructions functionally executed and
      * committed.
diff --git a/src/sim/process.cc b/src/sim/process.cc
index f647467b8..81f2cd6aa 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -161,7 +161,9 @@ Process::clone(ThreadContext *otc, ThreadContext *ntc,
          */
         delete np->pTable;
         np->pTable = pTable;
-        ntc->getMemProxy().setPageTable(np->pTable);
+        auto &proxy = dynamic_cast<SETranslatingPortProxy &>(
+                ntc->getMemProxy());
+        proxy.setPageTable(np->pTable);
 
         np->memState = memState;
     } else {