From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 11 Feb 2020 15:55:37 +0000 (+0100)
Subject: soc/add_uart: fix bridge
X-Git-Tag: 24jan2021_ls180~677^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=399b65fa1739916f97b7ce28be585cb3c7eed1ca;p=litex.git

soc/add_uart: fix bridge
---

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 42eab475..c448ebf8 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -876,7 +876,7 @@ class LiteXSoC(SoC):
                 pads     = self.platform.request("serial"),
                 clk_freq = self.sys_clk_freq,
                 baudrate = baudrate)
-            self.bus.master(name="uart_bridge", master=self.uart.wishbone)
+            self.bus.add_master(name="uart_bridge", master=self.uart.wishbone)
         elif name == "crossover":
             self.submodules.uart = uart.UARTCrossover()
         else: