From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sat, 29 Feb 2020 20:46:54 +0000 (-0500)
Subject: Move enums to a separate file
X-Git-Tag: div_pipeline~1807
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=399eba99cfd6f5fcef1fa5a79acc590031a1edde;p=soc.git

Move enums to a separate file
---

diff --git a/src/decoder/power_enums.py b/src/decoder/power_enums.py
new file mode 100644
index 00000000..687c1ca8
--- /dev/null
+++ b/src/decoder/power_enums.py
@@ -0,0 +1,79 @@
+from enum import Enum, unique
+
+
+@unique
+class Function(Enum):
+    ALU = 0
+    LDST = 1
+
+
+@unique
+class InternalOp(Enum):
+    OP_ADD = 0
+    OP_AND = 1
+    OP_B = 2
+    OP_BC = 3
+    OP_CMP = 4
+    OP_LOAD = 5
+    OP_MUL_L64 = 6
+    OP_OR = 7
+    OP_RLC = 8
+    OP_STORE = 9
+    OP_TDI = 10
+    OP_XOR = 11
+
+
+@unique
+class In1Sel(Enum):
+    RA = 0
+    RA_OR_ZERO = 1
+    NONE = 2
+    SPR = 3
+
+
+@unique
+class In2Sel(Enum):
+    CONST_SI = 0
+    CONST_SI_HI = 1
+    CONST_UI = 2
+    CONST_UI_HI = 3
+    CONST_LI = 4
+    CONST_BD = 5
+    CONST_SH32 = 6
+    RB = 7
+
+
+@unique
+class In3Sel(Enum):
+    NONE = 0
+    RS = 1
+
+
+@unique
+class OutSel(Enum):
+    RT = 0
+    RA = 1
+    NONE = 2
+    SPR = 3
+
+
+@unique
+class LdstLen(Enum):
+    NONE = 0
+    is1B = 1
+    is2B = 2
+    is4B = 3
+
+
+@unique
+class RC(Enum):
+    NONE = 0
+    ONE = 1
+    RC = 2
+
+
+@unique
+class CryIn(Enum):
+    ZERO = 0
+    ONE = 1
+    CA = 2
diff --git a/src/decoder/power_major_decoder.py b/src/decoder/power_major_decoder.py
index 2f1e5297..ddcfcce2 100644
--- a/src/decoder/power_major_decoder.py
+++ b/src/decoder/power_major_decoder.py
@@ -1,85 +1,8 @@
 from nmigen import Module, Elaboratable, Signal
 import csv
 import os
-from enum import Enum, unique
-
-
-@unique
-class Function(Enum):
-    ALU = 0
-    LDST = 1
-
-
-@unique
-class InternalOp(Enum):
-    OP_ADD = 0
-    OP_AND = 1
-    OP_B = 2
-    OP_BC = 3
-    OP_CMP = 4
-    OP_LOAD = 5
-    OP_MUL_L64 = 6
-    OP_OR = 7
-    OP_RLC = 8
-    OP_STORE = 9
-    OP_TDI = 10
-    OP_XOR = 11
-
-
-@unique
-class In1Sel(Enum):
-    RA = 0
-    RA_OR_ZERO = 1
-    NONE = 2
-    SPR = 3
-
-
-@unique
-class In2Sel(Enum):
-    CONST_SI = 0
-    CONST_SI_HI = 1
-    CONST_UI = 2
-    CONST_UI_HI = 3
-    CONST_LI = 4
-    CONST_BD = 5
-    CONST_SH32 = 6
-    RB = 7
-
-
-@unique
-class In3Sel(Enum):
-    NONE = 0
-    RS = 1
-
-
-@unique
-class OutSel(Enum):
-    RT = 0
-    RA = 1
-    NONE = 2
-    SPR = 3
-
-
-@unique
-class LdstLen(Enum):
-    NONE = 0
-    is1B = 1
-    is2B = 2
-    is4B = 3
-
-
-@unique
-class RC(Enum):
-    NONE = 0
-    ONE = 1
-    RC = 2
-
-
-@unique
-class CryIn(Enum):
-    ZERO = 0
-    ONE = 1
-    CA = 2
+from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
+                         OutSel, RC, LdstLen, CryIn)
 
 
 # names of the fields in major.csv that don't correspond to an enum
diff --git a/src/decoder/test/test_power_major_decoder.py b/src/decoder/test/test_power_major_decoder.py
index 1f8374d1..0cc46173 100644
--- a/src/decoder/test/test_power_major_decoder.py
+++ b/src/decoder/test/test_power_major_decoder.py
@@ -5,11 +5,10 @@ from nmigen.cli import rtlil
 import sys
 import unittest
 sys.path.append("../")
-from power_major_decoder import (PowerMajorDecoder, Function,
-                                 In1Sel, In2Sel, In3Sel, OutSel,
-                                 LdstLen, RC, CryIn,
-                                 single_bit_flags, get_signal_name,
-                                 InternalOp, major_opcodes)
+from power_major_decoder import (PowerMajorDecoder, single_bit_flags,
+                                 get_signal_name, major_opcodes)
+from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
+                         OutSel, RC, LdstLen, CryIn)
 
 
 class DecoderTestCase(FHDLTestCase):