From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Sep 2019 18:38:19 +0000 (-0700)
Subject: Fix nusers condition in ffP
X-Git-Tag: working-ls180~1039^2~184
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39a5d046ea5fe1021520d285723ef0b02dca4d17;p=yosys.git

Fix nusers condition in ffP
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index bb3bf90bd..adf30b45a 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -228,6 +228,8 @@ code sigC sigP
 endcode
 
 match ffPmux
+	if param(dsp, \PREG).as_int() == 0
+	if nusers(sigP) == 2
 	select ffPmux->type.in($mux)
 	choice <IdString> BA {\B, \A}
 	// new-value net must have exactly two users: dsp and ffP
@@ -253,13 +255,14 @@ endcode
 
 match ffP
 	if param(dsp, \PREG).as_int() == 0
+	if nusers(sigP) == 2
 	select ffP->type.in($dff)
 	// DSP48E1 does not support clock inversion
 	select param(ffP, \CLK_POLARITY).as_bool()
-	select nusers(port(ffP, \D)) == 2
 	filter GetSize(port(ffP, \D)) >= GetSize(sigP)
 	slice offset GetSize(port(ffP, \D))
-	filter offset+GetSize(sigP) <= GetSize(port(ffP, \D)) && port(ffP, \D).extract(offset, GetSize(sigP)) == sigP
+	filter offset+GetSize(sigP) <= GetSize(port(ffP, \D))
+	filter port(ffP, \D).extract(offset, GetSize(sigP)) == sigP
 	// Check ffPmux (when present) is a $dff enable mux
 	filter !ffPmux || port(ffP, \Q) == port(ffPmux, ffPenpol ? \A : \B)
 	optional