From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Sun, 11 Apr 2021 04:33:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~1077^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39aa8fe6afffc451215d46ebae5a7eb8694cd474;p=libreriscv.git

---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 8bd65546a..f5b960132 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -221,11 +221,11 @@ and therefore have no value are marked with 'NOT'
 
 ## Images of wires on FPGA and on ft232r
 
-Image of JTAG jumper wire connections on ULX3S FPGA side
+Image of JTAG jumper wire connections on ULX3S FPGA side:
 
 [[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="500x" ]] 
 
-Image of JTAG jumper wire connections on ft232r side
+Image of JTAG jumper wire connections on ft232r side:
 
 [[!img HDL_workflow/ft232r_jtag_wires.jpg size="500x" ]]