From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 7 Nov 2020 12:07:33 +0000 (+0000)
Subject: add io_in/io_out zero/one to help transition to new niolib ioring
X-Git-Tag: partial-core-ls180-gdsii~25
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39acfdd787a4372a524b600658ce736f86785488;p=soclayout.git

add io_in/io_out zero/one to help transition to new niolib ioring
---

diff --git a/experiments9/non_generated/ls180.vst b/experiments9/non_generated/ls180.vst
index 38b2dc8..81e6766 100644
--- a/experiments9/non_generated/ls180.vst
+++ b/experiments9/non_generated/ls180.vst
@@ -80,6 +80,13 @@ architecture structural of ls180 is
          );
   end component;
 
+  component one_x0
+    port ( q  : out bit
+         ; vdd : in bit
+         ; vss : in bit
+         );
+  end component;
+
 begin
 
   zero_0 : zero_x0
@@ -88,7 +95,17 @@ begin
            , vss => vss
            );
 
+  zero_1 : zero_x0
+  port map ( nq  => io_in
+           , vdd => vdd
+           , vss => vss
+           );
 
+  one_0 : one_x0
+  port map ( q  => io_out
+           , vdd => vdd
+           , vss => vss
+           );
 
 end structural;