From: whitequark <whitequark@whitequark.org>
Date: Mon, 13 May 2019 15:34:13 +0000 (+0000)
Subject: hdl.ir: during port propagation, defs should take priority over uses.
X-Git-Tag: locally_working~253
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39bc59c924c39b8e813c392a36e41fb279a9b1d2;p=nmigen.git

hdl.ir: during port propagation, defs should take priority over uses.
---

diff --git a/nmigen/hdl/ir.py b/nmigen/hdl/ir.py
index 6c05018..21c78b5 100644
--- a/nmigen/hdl/ir.py
+++ b/nmigen/hdl/ir.py
@@ -445,11 +445,6 @@ class Fragment:
         for sig in uses:
             if sig in defs:
                 lca  = reduce(lca_of, uses[sig], defs[sig])
-
-                frag = defs[sig]
-                while frag != lca:
-                    frag.add_ports(sig, dir="o")
-                    frag = parent[frag]
             else:
                 lca  = reduce(lca_of, uses[sig])
 
@@ -460,6 +455,12 @@ class Fragment:
                     frag.add_ports(sig, dir="i")
                     frag = parent[frag]
 
+            if sig in defs:
+                frag = defs[sig]
+                while frag != lca:
+                    frag.add_ports(sig, dir="o")
+                    frag = parent[frag]
+
         for sig in ios:
             frag = ios[sig]
             while frag is not None:
diff --git a/nmigen/test/test_hdl_ir.py b/nmigen/test/test_hdl_ir.py
index 34a31e6..0e96662 100644
--- a/nmigen/test/test_hdl_ir.py
+++ b/nmigen/test/test_hdl_ir.py
@@ -156,6 +156,27 @@ class FragmentPortsTestCase(FHDLTestCase):
             (self.c2, "o"),
         ]))
 
+    def test_output_from_subfragment_2(self):
+        f1 = Fragment()
+        f1.add_statements(
+            self.c1.eq(self.s1)
+        )
+        f2 = Fragment()
+        f2.add_statements(
+            self.c2.eq(self.s1)
+        )
+        f1.add_subfragment(f2)
+        f3 = Fragment()
+        f3.add_statements(
+            self.s1.eq(0)
+        )
+        f2.add_subfragment(f3)
+
+        f1._propagate_ports(ports=(), all_undef_as_ports=True)
+        self.assertEqual(f2.ports, SignalDict([
+            (self.s1, "o"),
+        ]))
+
     def test_input_output_sibling(self):
         f1 = Fragment()
         f2 = Fragment()