From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 31 Mar 2022 01:31:37 +0000 (+0100)
Subject: remove {err} feature from Tercel
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39bcfa3642204d9f8cd970164f408d465ccfcd07;p=ls2.git

remove {err} feature from Tercel
---

diff --git a/src/ls2.py b/src/ls2.py
index 92c990b..f3ad84d 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -390,6 +390,7 @@ class DDR3SoC(SoC, Elaboratable):
 
         # SPI controller
         if spi_0_pins is not None and fpga in ['sim',
+                                             'isim',
                                              'rcs_arctic_tern_bmc_card',
                                              'versa_ecp5',
                                              'versa_ecp5_85',
@@ -411,7 +412,7 @@ class DDR3SoC(SoC, Elaboratable):
             # The main SPI Flash (SPI 1) should be set to at
             # least 28 bits (256MB) to allow the use of large 4BA devices.
             self.spi0 = Tercel(data_width=32, spi_region_addr_width=24,
-                               features={'stall', 'err'},
+                               features={'stall'},
                                clk_freq=clk_freq,
                                pins=spi_0_pins,
                                lattice_ecp5_usrmclk=spi0_is_lattice_ecp5_clk)
@@ -669,6 +670,7 @@ def build_platform(fpga, firmware):
     # Get SPI resource pins
     spi_0_pins = None
     if platform is not None and fpga in ['rcs_arctic_tern_bmc_card',
+                                         'isim',
                                          'arty_a7',
                                          'versa_ecp5_85',
                                          'versa_ecp5']: