From: Mark Alexander Date: Sat, 28 Dec 1996 06:51:58 +0000 (+0000) Subject: * gencode.c (build_instruction): Work around MSVC++ code gen bug X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39bf0ef4e6797058928dc5c8fe44fb3a26d4f5c4;p=binutils-gdb.git * gencode.c (build_instruction): Work around MSVC++ code gen bug that messes up arithmetic shifts. --- diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index c4f7709ca0c..fc6c3cfdf98 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,8 @@ +Fri Dec 27 22:48:51 1996 Mark Alexander + + * gencode.c (build_instruction): Work around MSVC++ code gen bug + that messes up arithmetic shifts. + Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com) * support.h: Use _WIN32 instead of __WIN32__. Also add defs for diff --git a/sim/mips/gencode.c b/sim/mips/gencode.c index 023c99dd445..4f7a32703a7 100644 --- a/sim/mips/gencode.c +++ b/sim/mips/gencode.c @@ -1680,6 +1680,11 @@ build_instruction (doisa, features, mips16, insn) exit(9); } + /* Work around an MSC code generation bug by precomputing a value + * with the sign bit set. */ + if (insn->flags & ARITHMETIC) + printf(" %s highbit = (%s)1 << %d;\n", ltype, ltype, bits - 1); + /* If register specified shift, then extract the relevant shift amount: */ if (insn->flags & REG) printf(" op1 &= 0x%02X;\n",(bits - 1)); @@ -1701,7 +1706,7 @@ build_instruction (doisa, features, mips16, insn) since that would cause an undefined shift of the number of bits in the type. */ if (insn->flags & ARITHMETIC) - printf(" GPR[destreg] |= (op1 != 0 && (op2 & ((%s)1 << %d)) ? ((((%s)1 << op1) - 1) << (%d - op1)) : 0);\n",ltype,(bits - 1),ltype,bits); + printf(" GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((%s)1 << op1) - 1) << (%d - op1)) : 0);\n",ltype,bits); /* Ensure WORD values are sign-extended into 64bit registers */ if ((bits == 32) && (gprlen == 64))