From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Thu, 25 Jun 2020 12:20:47 +0000 (+0200)
Subject: Add sub-assign and and-assign tests
X-Git-Tag: working-ls180~445^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39c39848a21dc4f4a2c3b17842d854047ba6c16f;p=yosys.git

Add sub-assign and and-assign tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---

diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys
index 56fbac9de..b18923c7b 100644
--- a/tests/opt/opt_expr_combined_assign.ys
+++ b/tests/opt/opt_expr_combined_assign.ys
@@ -47,3 +47,37 @@ equiv_opt -assert opt_expr -fine
 design -load postopt
 
 select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+        a -= i;
+        a -= j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b11111111;
+initial begin
+        a &= i;
+        a &= j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$and r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i