From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 3 Apr 2020 15:12:56 +0000 (+0100)
Subject: add bit-wise OR and AND
X-Git-Tag: div_pipeline~1556
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39c8314f9a14fb5351a9dcbc8bd37753bdcd0fee;p=soc.git

add bit-wise OR and AND
---

diff --git a/libreriscv b/libreriscv
index 620efa21..df8dbe52 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 620efa218f922eba23b19189109bec785a624a82
+Subproject commit df8dbe52a4a201d4e23e50de5ffd84c01b54cb57
diff --git a/src/soc/decoder/power_pseudo.py b/src/soc/decoder/power_pseudo.py
index 78add9ef..07715f6e 100644
--- a/src/soc/decoder/power_pseudo.py
+++ b/src/soc/decoder/power_pseudo.py
@@ -73,6 +73,10 @@ cmpi = """
 RA[0:1] <- 0b11
 """
 
+cmpi = """
+in_range <-  (x | y) & (a | b)
+in_range <-  (x + y) - (a + b)
+"""
 
 #code = testreg
 #code = cnttzd
diff --git a/src/soc/decoder/pseudo/lexer.py b/src/soc/decoder/pseudo/lexer.py
index 992ab7b6..86b04efd 100644
--- a/src/soc/decoder/pseudo/lexer.py
+++ b/src/soc/decoder/pseudo/lexer.py
@@ -252,6 +252,8 @@ class PowerLexer:
         'MULT',
         'DIV',
         'APPEND',
+        'BITOR',
+        'BITAND',
         'RETURN',
         'WS',
         'NEWLINE',
@@ -300,6 +302,8 @@ class PowerLexer:
     t_COMMA = r','
     t_SEMICOLON = r';'
     t_APPEND = r'\|\|'
+    t_BITOR = r'\|'
+    t_BITAND = r'\&'
 
     # Ply nicely documented how to do this.
 
diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py
index 8ce1b8c2..e752aff8 100644
--- a/src/soc/decoder/pseudo/parser.py
+++ b/src/soc/decoder/pseudo/parser.py
@@ -95,6 +95,8 @@ def make_eq_compare(arg):
     return ast.Compare(left, [ast.Eq()], [right])
 
 binary_ops = {
+    "&": ast.BitAnd(),
+    "|": ast.BitOr(),
     "+": ast.Add(),
     "-": ast.Sub(),
     "*": ast.Mult(),
@@ -128,6 +130,7 @@ def check_concat(node): # checks if the comparison is already a concat
 class PowerParser:
 
     precedence = (
+        ("left", "BITOR", "BITAND"),
         ("left", "EQ", "GT", "LT", "LE", "GE", "LTU", "GTU"),
         ("left", "PLUS", "MINUS"),
         ("left", "MULT", "DIV"),
@@ -338,6 +341,8 @@ class PowerParser:
                       | comparison GTU comparison
                       | comparison LT comparison
                       | comparison GT comparison
+                      | comparison BITOR comparison
+                      | comparison BITAND comparison
                       | PLUS comparison
                       | MINUS comparison
                       | comparison APPEND comparison
diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index 5a188330..05cf2b21 100644
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -102,7 +102,7 @@ class SelectableInt:
             assert other.bits == self.bits
             other = other.value
         if isinstance(other, int):
-            return other <= self.value
+            return onebit(other <= self.value)
         assert False
 
     def __gt__(self, other):
@@ -110,7 +110,7 @@ class SelectableInt:
             assert other.bits == self.bits
             other = other.value
         if isinstance(other, int):
-            return other > self.value
+            return onebit(other > self.value)
         assert False
 
     def __lt__(self, other):
@@ -118,7 +118,7 @@ class SelectableInt:
             assert other.bits == self.bits
             other = other.value
         if isinstance(other, int):
-            return other < self.value
+            return onebit(other < self.value)
         assert False
 
     def __eq__(self, other):
@@ -126,26 +126,29 @@ class SelectableInt:
             assert other.bits == self.bits
             other = other.value
         if isinstance(other, int):
-            return other == self.value
+            return onebit(other == self.value)
         assert False
 
     def __repr__(self):
         return "SelectableInt(value={:x}, bits={})".format(self.value,
                                                            self.bits)
 
+def onebit(bit):
+    return SelectableInt(1 if bit else 0, 1)
+
 def selectltu(lhs, rhs):
     """ less-than (unsigned)
     """
     if isinstance(rhs, SelectableInt):
         rhs = rhs.value
-    return lhs.value < rhs
+    return onebit(lhs.value < rhs)
 
 def selectgtu(lhs, rhs):
     """ greater-than (unsigned)
     """
     if isinstance(rhs, SelectableInt):
         rhs = rhs.value
-    return lhs.value > rhs
+    return onebit(lhs.value > rhs)
 
 
 # XXX this probably isn't needed...