From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Jul 2019 19:43:58 +0000 (+0100)
Subject: add code comments
X-Git-Tag: ls180-24jan2020~692
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39d242aa9a791b815e2382f48971ad607f9ba832;p=ieee754fpu.git

add code comments
---

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index 8f449c8b..41ae9a9a 100644
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -110,6 +110,7 @@ class FPCVTFloatToIntMod(Elaboratable):
             with m.Else():
                 m.d.comb += self.o.z.eq((1<<mz)-1) # NaN overflow
 
+        # zero exponent: definitely out of range of INT.  zero...
         with m.Elif(a1.exp_n127):
             m.d.comb += self.o.z.eq(0)
 
@@ -160,8 +161,9 @@ class FPCVTFloatToIntMod(Elaboratable):
             with m.Else():
                 m.d.comb += mround.eq(msr.m_out[3:])
 
+            # check sign
             with m.If(signed & a1.s):
-                m.d.comb += self.o.z.eq(-mround)
+                m.d.comb += self.o.z.eq(-mround) # inverted
             with m.Else():
                 m.d.comb += self.o.z.eq(mround)