From: whitequark Date: Thu, 13 Dec 2018 09:19:16 +0000 (+0000) Subject: fhdl.cd: add tests. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=39ee54c6bfcb9f71fe2edc8812d45b88fc55d769;p=nmigen.git fhdl.cd: add tests. --- diff --git a/nmigen/fhdl/cd.py b/nmigen/fhdl/cd.py index 5e21220..a838c21 100644 --- a/nmigen/fhdl/cd.py +++ b/nmigen/fhdl/cd.py @@ -32,9 +32,10 @@ class ClockDomain: """ def __init__(self, name=None, reset_less=False, async_reset=False): if name is None: - name = tracer.get_var_name() - if name is None: - raise ValueError("Clock domain name must be specified explicitly") + try: + name = tracer.get_var_name() + except tracer.NameNotFound: + raise ValueError("Clock domain name must be specified explicitly") if name.startswith("cd_"): name = name[3:] self.name = name diff --git a/nmigen/test/test_fhdl_cd.py b/nmigen/test/test_fhdl_cd.py new file mode 100644 index 0000000..8b453de --- /dev/null +++ b/nmigen/test/test_fhdl_cd.py @@ -0,0 +1,33 @@ +from ..fhdl.cd import * +from .tools import * + + +class ClockDomainCase(FHDLTestCase): + def test_name(self): + pix = ClockDomain() + self.assertEqual(pix.name, "pix") + cd_pix = ClockDomain() + self.assertEqual(pix.name, "pix") + dom = [ClockDomain("foo")][0] + self.assertEqual(dom.name, "foo") + with self.assertRaises(ValueError, + msg="Clock domain name must be specified explicitly"): + ClockDomain() + + def test_with_reset(self): + pix = ClockDomain() + self.assertIsNotNone(pix.clk) + self.assertIsNotNone(pix.rst) + self.assertFalse(pix.async_reset) + + def test_without_reset(self): + pix = ClockDomain(reset_less=True) + self.assertIsNotNone(pix.clk) + self.assertIsNone(pix.rst) + self.assertFalse(pix.async_reset) + + def test_async_reset(self): + pix = ClockDomain(async_reset=True) + self.assertIsNotNone(pix.clk) + self.assertIsNotNone(pix.rst) + self.assertTrue(pix.async_reset) diff --git a/nmigen/test/test_fhdl_dsl.py b/nmigen/test/test_fhdl_dsl.py index 7da25cf..b4ad259 100644 --- a/nmigen/test/test_fhdl_dsl.py +++ b/nmigen/test/test_fhdl_dsl.py @@ -1,4 +1,3 @@ -import unittest from contextlib import contextmanager from ..fhdl.ast import * @@ -16,14 +15,6 @@ class DSLTestCase(FHDLTestCase): self.c3 = Signal() self.w1 = Signal(4) - @contextmanager - def assertRaises(self, exception, msg=None): - with super().assertRaises(exception) as cm: - yield - if msg is not None: - # WTF? unittest.assertRaises is completely broken. - self.assertEqual(str(cm.exception), msg) - def test_d_comb(self): m = Module() m.d.comb += self.c1.eq(1) diff --git a/nmigen/test/test_fhdl_ir.py b/nmigen/test/test_fhdl_ir.py index c59464c..708acec 100644 --- a/nmigen/test/test_fhdl_ir.py +++ b/nmigen/test/test_fhdl_ir.py @@ -1,10 +1,9 @@ -import unittest +from ..fhdl.ast import * +from ..fhdl.ir import * +from .tools import * -from nmigen.fhdl.ast import * -from nmigen.fhdl.ir import * - -class FragmentPortsTestCase(unittest.TestCase): +class FragmentPortsTestCase(FHDLTestCase): def setUp(self): self.s1 = Signal() self.s2 = Signal() diff --git a/nmigen/test/test_fhdl_value.py b/nmigen/test/test_fhdl_value.py index 9c7dbde..892b5e0 100644 --- a/nmigen/test/test_fhdl_value.py +++ b/nmigen/test/test_fhdl_value.py @@ -1,9 +1,8 @@ -import unittest +from ..fhdl.ast import * +from .tools import * -from nmigen.fhdl.ast import * - -class ValueTestCase(unittest.TestCase): +class ValueTestCase(FHDLTestCase): def test_wrap(self): self.assertIsInstance(Value.wrap(0), Const) self.assertIsInstance(Value.wrap(True), Const) @@ -58,7 +57,7 @@ class ValueTestCase(unittest.TestCase): Const(31)["str"] -class ConstTestCase(unittest.TestCase): +class ConstTestCase(FHDLTestCase): def test_shape(self): self.assertEqual(Const(0).shape(), (0, False)) self.assertEqual(Const(1).shape(), (1, False)) @@ -83,7 +82,7 @@ class ConstTestCase(unittest.TestCase): hash(Const(0)) -class OperatorTestCase(unittest.TestCase): +class OperatorTestCase(FHDLTestCase): def test_invert(self): v = ~Const(0, 4) self.assertEqual(repr(v), "(~ (const 4'd0))") @@ -225,7 +224,7 @@ class OperatorTestCase(unittest.TestCase): hash(Const(0) + Const(0)) -class SliceTestCase(unittest.TestCase): +class SliceTestCase(FHDLTestCase): def test_shape(self): s1 = Const(10)[2] self.assertEqual(s1.shape(), (1, False)) @@ -237,7 +236,7 @@ class SliceTestCase(unittest.TestCase): self.assertEqual(repr(s1), "(slice (const 4'd10) 2:3)") -class CatTestCase(unittest.TestCase): +class CatTestCase(FHDLTestCase): def test_shape(self): c1 = Cat(Const(10)) self.assertEqual(c1.shape(), (4, False)) @@ -251,7 +250,7 @@ class CatTestCase(unittest.TestCase): self.assertEqual(repr(c1), "(cat (const 4'd10) (const 1'd1))") -class ReplTestCase(unittest.TestCase): +class ReplTestCase(FHDLTestCase): def test_shape(self): r1 = Repl(Const(10), 3) self.assertEqual(r1.shape(), (12, False)) @@ -267,7 +266,7 @@ class ReplTestCase(unittest.TestCase): self.assertEqual(repr(r1), "(repl (const 4'd10) 3)") -class SignalTestCase(unittest.TestCase): +class SignalTestCase(FHDLTestCase): def test_shape(self): s1 = Signal() self.assertEqual(s1.shape(), (1, False)) @@ -328,7 +327,7 @@ class SignalTestCase(unittest.TestCase): self.assertEqual(s5.shape(), (4, False)) -class ClockSignalTestCase(unittest.TestCase): +class ClockSignalTestCase(FHDLTestCase): def test_domain(self): s1 = ClockSignal() self.assertEqual(s1.domain, "sync") @@ -343,7 +342,7 @@ class ClockSignalTestCase(unittest.TestCase): self.assertEqual(repr(s1), "(clk sync)") -class ResetSignalTestCase(unittest.TestCase): +class ResetSignalTestCase(FHDLTestCase): def test_domain(self): s1 = ResetSignal() self.assertEqual(s1.domain, "sync") diff --git a/nmigen/test/test_fhdl_xfrm.py b/nmigen/test/test_fhdl_xfrm.py index aad4525..0e1d3fa 100644 --- a/nmigen/test/test_fhdl_xfrm.py +++ b/nmigen/test/test_fhdl_xfrm.py @@ -1,6 +1,3 @@ -import re -import unittest - from ..fhdl.ast import * from ..fhdl.ir import * from ..fhdl.xfrm import *