From: whitequark Date: Wed, 26 Aug 2020 10:18:02 +0000 (+0000) Subject: vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a175a829ce3056e70f0177a25aaf6fd59c1816d;p=nmigen.git vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate. Fixes #438 (again). --- diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py index cb95dfd..136ab18 100644 --- a/nmigen/vendor/xilinx_7series.py +++ b/nmigen/vendor/xilinx_7series.py @@ -317,10 +317,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): ready = Signal() m.submodules += Instance("STARTUPE2", o_EOS=ready) m.domains += ClockDomain("sync", reset_less=self.default_rst is None) - # Actually use BUFGCTRL configured as BUFGCE, since using BUFGCE causes sim/synth - # mismatches with Vivado 2019.2, and the suggested workaround (SIM_DEVICE parameter) - # breaks Vivado 2017.4. + # Actually use BUFGCTRL configured as BUFGCE, since using BUFGCE causes + # sim/synth mismatches with Vivado 2019.2, and the suggested workaround + # (SIM_DEVICE parameter) breaks Vivado 2017.4. m.submodules += Instance("BUFGCTRL", + p_SIM_DEVICE="7SERIES", i_I0=clk_i, i_S0=C(1, 1), i_CE0=ready, i_IGNORE0=C(0, 1), i_I1=C(1, 1), i_S1=C(0, 1), i_CE1=C(0, 1), i_IGNORE1=C(1, 1), o_O=ClockSignal("sync") diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py index 937b346..0969ccb 100644 --- a/nmigen/vendor/xilinx_ultrascale.py +++ b/nmigen/vendor/xilinx_ultrascale.py @@ -168,12 +168,10 @@ class XilinxUltraScalePlatform(TemplatedPlatform): ready = Signal() m.submodules += Instance("STARTUPE3", o_EOS=ready) m.domains += ClockDomain("sync", reset_less=self.default_rst is None) - # Actually use BUFGCTRL configured as BUFGCE, since using BUFGCE causes sim/synth - # mismatches with Vivado 2019.2, and the suggested workaround (SIM_DEVICE parameter) - # breaks Vivado 2017.4. - m.submodules += Instance("BUFGCTRL", - i_I0=clk_i, i_S0=C(1, 1), i_CE0=ready, i_IGNORE0=C(0, 1), - i_I1=C(1, 1), i_S1=C(0, 1), i_CE1=C(0, 1), i_IGNORE1=C(1, 1), + m.submodules += Instance("BUFGCE", + p_SIM_DEVICE="ULTRASCALE", + i_CE=ready, + i_I=clk_i, o_O=ClockSignal("sync") ) if self.default_rst is not None: