From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Oct 2019 03:38:58 +0000 (+0000)
Subject: back.rtlil: it is not necessary to match binop operand width.
X-Git-Tag: v0.1rc1~45
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a1dae591b72f9bfa1c9572b1f5ff780f12c1e87;p=nmigen.git

back.rtlil: it is not necessary to match binop operand width.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index e7ec34c..298d2f9 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -490,7 +490,6 @@ class _RHSValueCompiler(_ValueCompiler):
             rhs_wire = self(rhs)
         else:
             lhs_sign = rhs_sign = True
-            lhs_bits = rhs_bits = max(lhs_bits, rhs_bits)
             lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
             rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
         res_bits, res_sign = value.shape()