From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Sun, 1 Nov 2020 21:40:25 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1893
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a1fb0d31972b6d9a40d59abfe6ac65fe75c5efe;p=libreriscv.git

---

diff --git a/HDL_workflow/fpga.mdwn b/HDL_workflow/fpga.mdwn
index c258a4ef7..a5d090a26 100644
--- a/HDL_workflow/fpga.mdwn
+++ b/HDL_workflow/fpga.mdwn
@@ -49,8 +49,8 @@ and to end up learning the hard way by destroying the FPGA.
 Connecting the dots:
 
 
-litex platform file
-```litex-boards/litex_boards/platforms/ulx3s.py
+litex platform file litex-boards/litex_boards/platforms/ulx3s.py
+```
 ("gpio", 0,
     Subsignal("p", Pins("B11")),
     Subsignal("n", Pins("C11")),
@@ -63,16 +63,17 @@ litex platform file
 ),
 ```
 
-ulx3s contstraints file
-```github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342
+ulx3s contstraints file github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342
+```
 LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
 LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
 LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
 LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
 ```
 
-```https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf
+ULX3S FPGA Schematic https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf
 
+```
 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.