From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 13 Oct 2015 15:17:12 +0000 (+0200)
Subject: Added write_smt2 -wires
X-Git-Tag: yosys-0.6~118
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a22b31bdad32c7cecdbbe3f13fc282c794dfdbd;p=yosys.git

Added write_smt2 -wires
---

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index a544aa7d8..a51a82709 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -32,7 +32,7 @@ struct Smt2Worker
 	CellTypes ct;
 	SigMap sigmap;
 	RTLIL::Module *module;
-	bool bvmode, memmode, regsmode, verbose;
+	bool bvmode, memmode, regsmode, wiresmode, verbose;
 	int idcounter;
 
 	std::vector<std::string> decls, trans;
@@ -44,8 +44,9 @@ struct Smt2Worker
 	std::map<Cell*, int> memarrays;
 	std::map<int, int> bvsizes;
 
-	Smt2Worker(RTLIL::Module *module, bool bvmode, bool memmode, bool regsmode, bool verbose) :
-			ct(module->design), sigmap(module), module(module), bvmode(bvmode), memmode(memmode), regsmode(regsmode), verbose(verbose), idcounter(0)
+	Smt2Worker(RTLIL::Module *module, bool bvmode, bool memmode, bool regsmode, bool wiresmode, bool verbose) :
+			ct(module->design), sigmap(module), module(module), bvmode(bvmode), memmode(memmode),
+			regsmode(regsmode), wiresmode(wiresmode), verbose(verbose), idcounter(0)
 	{
 		decls.push_back(stringf("(declare-sort |%s_s| 0)\n", log_id(module)));
 
@@ -488,7 +489,7 @@ struct Smt2Worker
 				for (auto bit : SigSpec(wire))
 					if (reg_bits.count(bit))
 						is_register = true;
-			if (wire->port_id || is_register || wire->get_bool_attribute("\\keep")) {
+			if (wire->port_id || is_register || wire->get_bool_attribute("\\keep") || (wiresmode && wire->name[0] == '\\')) {
 				RTLIL::SigSpec sig = sigmap(wire);
 				if (wire->port_input)
 					decls.push_back(stringf("; yosys-smt2-input %s %d\n", log_id(wire), wire->width));
@@ -496,7 +497,7 @@ struct Smt2Worker
 					decls.push_back(stringf("; yosys-smt2-output %s %d\n", log_id(wire), wire->width));
 				if (is_register)
 					decls.push_back(stringf("; yosys-smt2-register %s %d\n", log_id(wire), wire->width));
-				if (wire->get_bool_attribute("\\keep"))
+				if (wire->get_bool_attribute("\\keep") || (wiresmode && wire->name[0] == '\\'))
 					decls.push_back(stringf("; yosys-smt2-wire %s %d\n", log_id(wire), wire->width));
 				if (bvmode && GetSize(sig) > 1) {
 					decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n",
@@ -695,6 +696,9 @@ struct Smt2Backend : public Backend {
 		log("    -regs\n");
 		log("        also create '<mod>_n' functions for all registers.\n");
 		log("\n");
+		log("    -wires\n");
+		log("        also create '<mod>_n' functions for all public wires.\n");
+		log("\n");
 		log("    -tpl <template_file>\n");
 		log("        use the given template file. the line containing only the token '%%%%'\n");
 		log("        is replaced with the regular output of this command.\n");
@@ -751,7 +755,7 @@ struct Smt2Backend : public Backend {
 	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
 	{
 		std::ifstream template_f;
-		bool bvmode = false, memmode = false, regsmode = false, verbose = false;
+		bool bvmode = false, memmode = false, regsmode = false, wiresmode = false, verbose = false;
 
 		log_header("Executing SMT2 backend.\n");
 
@@ -777,6 +781,10 @@ struct Smt2Backend : public Backend {
 				regsmode = true;
 				continue;
 			}
+			if (args[argidx] == "-wires") {
+				wiresmode = true;
+				continue;
+			}
 			if (args[argidx] == "-verbose") {
 				verbose = true;
 				continue;
@@ -806,7 +814,7 @@ struct Smt2Backend : public Backend {
 
 			log("Creating SMT-LIBv2 representation of module %s.\n", log_id(module));
 
-			Smt2Worker worker(module, bvmode, memmode, regsmode, verbose);
+			Smt2Worker worker(module, bvmode, memmode, regsmode, wiresmode, verbose);
 			worker.run();
 			worker.write(*f);
 		}