From: lkcl Date: Mon, 7 Mar 2022 14:18:30 +0000 (+0000) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~3132 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a299141c392c2cce3c634b7a071f124ec5ca329;p=libreriscv.git --- diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index 495c9245e..937eb72a0 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -317,26 +317,33 @@ uint_xlen_t bmextrev(RA, RB, sh) # grevlut -generalised reverse combined with a LUT2 and allowing +generalised reverse combined with a pair of LUT2s and allowing zero when RA=0 provides a wide range of instructions and a means to set regular 64 bit patterns in one 32 bit instruction. +the two LUT2s are applied left-half (when not swapping) +and right-half (when swapping) so as to allow a wider +range of options + ``` lut2(imm, a, b): idx = b << 1 | a return imm[idx] # idx by LSB0 order -dorow(imm, step_i, chunksize): +dorow(imm8, step_i, chunksize): for j in 0 to 63: + if (j&chunk_size) == 0 + imm = imm8[0..3] + else + imm = imm8[4..7] step_o[j] = lut2(imm, step_i[j], step_i[j ^ chunk_size]) return step_o -uint64_t grevlut64(uint64_t RA, uint64_t RB, uint8 lut2) +uint64_t grevlut64(uint64_t RA, uint64_t RB, uint8 imm) { uint64_t x = RA; int shamt = RB & 63; - int imm = lut2 & 0b1111; for i in 0 to 6 step = 1<