From: Florent Kermarrec Date: Fri, 26 Apr 2019 21:49:06 +0000 (+0200) Subject: .gitmodules: use our VexRiscv-verilog X-Git-Tag: 24jan2021_ls180~1266 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a2e28361350800f9225a0194c968f9f2f755322;p=litex.git .gitmodules: use our VexRiscv-verilog --- diff --git a/.gitmodules b/.gitmodules index 584a052d..89798374 100644 --- a/.gitmodules +++ b/.gitmodules @@ -15,4 +15,4 @@ url = https://github.com/enjoy-digital/tapcfg [submodule "litex/soc/cores/cpu/vexriscv/verilog"] path = litex/soc/cores/cpu/vexriscv/verilog - url = https://github.com/m-labs/VexRiscv-verilog.git + url = https://github.com/enjoy-digital/VexRiscv-verilog.git diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog index ebe40646..66faa6ec 160000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -1 +1 @@ -Subproject commit ebe4064653bc143bf92a0ccdd1099173620fcbf5 +Subproject commit 66faa6ece6551abac424146f9a27960ba10f4cf8