From: David Shah <davey1576@gmail.com>
Date: Mon, 16 Jul 2018 13:56:12 +0000 (+0200)
Subject: ecp5: Fixing miscellaneous sim model issues
X-Git-Tag: yosys-0.8~55^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a3558acce25807d6ce75280cc3f43aeb52974df;p=yosys.git

ecp5: Fixing miscellaneous sim model issues

Signed-off-by: David Shah <davey1576@gmail.com>
---

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index cf1446a52..1700694e8 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -232,13 +232,13 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 			always @(posedge muxclk, posedge muxlsr)
 				if (muxlsr)
 					Q <= srval;
-				else
+				else if (muxce)
 					Q <= DI;
 		end else begin
 			always @(posedge muxclk)
 				if (muxlsr)
 					Q <= srval;
-				else
+				else if (muxce)
 					Q <= DI;
 		end
 	endgenerate