From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 15 Aug 2017 00:15:56 +0000 (-0700)
Subject: Updated PGEN model to have level triggered reset (matches actual hardware behavior
X-Git-Tag: yosys-0.8~344^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a404be62a7b7fcc435857e20aa6c528f373b81c;p=yosys.git

Updated PGEN model to have level triggered reset (matches actual hardware behavior
---

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 5d9d67750..6fba941a0 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -741,10 +741,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 	localparam COUNT_MAX =  PATTERN_LEN - 1'h1;
 
 	reg[3:0] count = 0;
-	always @(posedge CLK) begin
-		if(!nRST) begin
-			count	<= COUNT_MAX;
-		end
+	always @(posedge CLK, negedge nRST) begin
+
+		if(!nRST)
+			count	<= 0;
 
 		else begin
 			count	<= count - 1'h1;