From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Mar 2019 19:40:57 +0000 (-0800)
Subject: Fix error for wire decl in always block, fixes #763
X-Git-Tag: yosys-0.9~274^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a51714451dbd5a0aec5d5167429f899950f2c4e;p=yosys.git

Fix error for wire decl in always block, fixes #763

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 2d591b29d..13383845a 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -544,7 +544,11 @@ struct AST_INTERNAL::ProcessGenerator
 			break;
 
 		case AST_WIRE:
-			log_file_error(ast->filename, ast->linenum, "Found wire declaration in block without label!\n");
+			log_file_error(ast->filename, ast->linenum, "Found reg declaration in block without label!\n");
+			break;
+
+		case AST_ASSIGN:
+			log_file_error(ast->filename, ast->linenum, "Found continous assignment in always/initial block!\n");
 			break;
 
 		case AST_PARAMETER: