From: lkcl <lkcl@web>
Date: Sun, 29 Aug 2021 11:10:55 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~282
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a56ed229372fa59e1933ce1291ec0f490dbe623;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index f5a2175ce..6e2470a0d 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -119,9 +119,9 @@ in the decoder is greatly increased.
 
 # Single Predication
 
-This is a standard mode normally found in Vector ISAs.  every element in rvery source Vector and in the destination uses the same bit of one single predicate mask.
+This is a standard mode normally found in Vector ISAs.  every element in every source Vector and in the destination uses the same bit of one single predicate mask.
 
-Note however that in SVSTATE, implementors MUST increment both srcstep and dststep, and that the two must be equal at all times.
+In SVSTATE, for Single-predication, implementors MUST increment both srcstep and dststep: unlike Twin-Predication the two must be equal at all times.
 
 # Twin Predication