From: Diego H <diego@symbioticeda.com>
Date: Tue, 26 Nov 2019 23:14:41 +0000 (-0600)
Subject: Adjusting Vivado's BRAM min bits threshold for RAMB18E1
X-Git-Tag: working-ls180~926^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a5a65829cc593965304537ddcb4d6d1d3e3ca8b;p=yosys.git

Adjusting Vivado's BRAM min bits threshold for RAMB18E1
---

diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt
index f1161114e..ee961fff8 100644
--- a/techlibs/xilinx/xc7_xcu_brams.txt
+++ b/techlibs/xilinx/xc7_xcu_brams.txt
@@ -81,7 +81,7 @@ match $__XILINX_RAMB36_SDP
 endmatch
 
 match $__XILINX_RAMB18_SDP
-  min bits 4096
+  min bits 1024
   min efficiency 5
   shuffle_enable B
   make_transp
@@ -97,9 +97,12 @@ match $__XILINX_RAMB36_TDP
 endmatch
 
 match $__XILINX_RAMB18_TDP
-  min bits 4096
+  min bits 1024
   min efficiency 5
   shuffle_enable B
   make_transp
 endmatch
 
+# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),
+# v1.14 ed., p 29-30, July, 2019.
+