From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 18 Nov 2019 13:19:49 +0000 (+0000)
Subject: arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
X-Git-Tag: v19.0.0.0~216
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a5ff476ffdcfcef2a6d0427d9add590984596e7;p=gem5.git

arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs

gem5-ARM is not using floatRegs anymore and moved towards the
vecRegs register file (which is used for SIMD&FP + SVE instructions)

Change-Id: I41cfbe10565e4e0db838f98626310a5b14edadb9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23103
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index eef2dfe27..7ed62f283 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -1123,7 +1123,7 @@ VldMultOp64::VldMultOp64(const char *mnem, ExtMachInst machInst,
                          uint8_t numStructElems, uint8_t numRegs, bool wb) :
     PredMacroOp(mnem, machInst, __opClass)
 {
-    RegIndex vx = NumFloatV8ArchRegs / 4;
+    RegIndex vx = NumVecV8ArchRegs;
     RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
     bool baseIsSP = isSP((IntRegIndex) rnsp);
 
@@ -1208,7 +1208,7 @@ VstMultOp64::VstMultOp64(const char *mnem, ExtMachInst machInst,
                          uint8_t numStructElems, uint8_t numRegs, bool wb) :
     PredMacroOp(mnem, machInst, __opClass)
 {
-    RegIndex vx = NumFloatV8ArchRegs / 4;
+    RegIndex vx = NumVecV8ArchRegs;
     RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
     bool baseIsSP = isSP((IntRegIndex) rnsp);
 
@@ -1297,7 +1297,7 @@ VldSingleOp64::VldSingleOp64(const char *mnem, ExtMachInst machInst,
     wb(false), replicate(false)
 
 {
-    RegIndex vx = NumFloatV8ArchRegs / 4;
+    RegIndex vx = NumVecV8ArchRegs;
     RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
     bool baseIsSP = isSP((IntRegIndex) rnsp);
 
@@ -1370,7 +1370,7 @@ VstSingleOp64::VstSingleOp64(const char *mnem, ExtMachInst machInst,
     eSize(0), dataSize(0), numStructElems(0), index(0),
     wb(false), replicate(false)
 {
-    RegIndex vx = NumFloatV8ArchRegs / 4;
+    RegIndex vx = NumVecV8ArchRegs;
     RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
     bool baseIsSP = isSP((IntRegIndex) rnsp);
 
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 2ac97441d..cff138ce4 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -51,7 +51,7 @@ static_assert(NUM_XREGS == 31, "Unexpected number of aarch64 int. regs.");
 
 // The KVM interface accesses vector registers of 4 single precision
 // floats instead of individual registers.
-constexpr static unsigned NUM_QREGS = NumFloatV8ArchRegs / 4;
+constexpr static unsigned NUM_QREGS = NumVecV8ArchRegs;
 static_assert(NUM_QREGS == 32, "Unexpected number of aarch64 vector regs.");
 
 #define EXTRACT_FIELD(v, name) \
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 84f382b9c..1c9ec262a 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -82,7 +82,6 @@ using VecPredRegContainer = VecPredReg::Container;
 const int NumIntArchRegs = NUM_ARCH_INTREGS;
 // The number of single precision floating point registers
 const int NumFloatV7ArchRegs  = 64;
-const int NumFloatV8ArchRegs  = 128;
 const int NumVecV7ArchRegs  = 64;
 const int NumVecV8ArchRegs  = 32;
 const int NumVecSpecialRegs = 8;