From: lkcl <lkcl@web>
Date: Mon, 4 Jul 2022 09:00:12 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1365
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a828f040a58922d52d390f5b8528e25b787185c;p=libreriscv.git

---

diff --git a/3d_gpu/layouts/coriolis2_180nm.mdwn b/3d_gpu/layouts/coriolis2_180nm.mdwn
index 068af11b9..694303e41 100644
--- a/3d_gpu/layouts/coriolis2_180nm.mdwn
+++ b/3d_gpu/layouts/coriolis2_180nm.mdwn
@@ -70,7 +70,16 @@ to ensure complete consistency across
 * IO Ring
 * JTAG Boundary Scan
 
-JTAG 
+JTAG also contains a Wishbone Master for direct access to Memory
+and also a DMI Interface for controlling the core.  In simulations
+a JTAG client was implemented both in nmigen HDL as well as
+verilator.  The exact same openocd scripts and direct
+JTAG connectivity using jtagremote can then be used on:
+
+* nmigen HDL simulations
+* verilator simulations
+* FPGA
+* ls180 ASIC
 
 [[!img 180nm_Oct2020/ls180.svg size="400x" ]]