From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 20:23:07 +0000 (-0700)
Subject: Wrap A and B in sigmap
X-Git-Tag: working-ls180~1163^2~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a87dc35242598b6951fb70d4302ede60c2a96b2;p=yosys.git

Wrap A and B in sigmap
---

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 23e14f7f5..294f0d57e 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -366,8 +366,8 @@ struct WreduceWorker
 		}
 
 		if (cell->type.in("$add", "$sub")) {
-			SigSpec A = cell->getPort("\\A");
-			SigSpec B = cell->getPort("\\B");
+			SigSpec A = mi.sigmap(cell->getPort("\\A"));
+			SigSpec B = mi.sigmap(cell->getPort("\\B"));
 			bool sub = cell->type == "$sub";
 
 			int i;