From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 13:36:46 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2326
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a976ae143c45a846e706aee7fbae4d1e725fa5d;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 82a15b226..b9ee7598f 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -485,7 +485,9 @@ are at an astonishing four levels of cache (L1 to L4).
 
 It should therefore come as no surprise that attempts are being made
 to move (distribute) processing closer to the DRAM Memory, firmly
-on the *opposite* side of the main CPU's L1/2/3/4 Caches.  However
+on the *opposite* side of the main CPU's L1/2/3/4 Caches,
+where a simple `LOAD-COMPUTE-STORE-LOOP` workload easily illustrates
+why this approach is compelling.  However
 the alarm bells ring here at the keyword "distributed", because by
 moving the processing down next to the Memory, even onto
 the same die as the DRAM, the speed of any