From: Cesar Strauss <cestrauss@gmail.com>
Date: Sat, 6 Mar 2021 17:12:08 +0000 (-0300)
Subject: Do not reset pc_changed and sv_changed at instruction end
X-Git-Tag: convert-csv-opcode-to-binary~102
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ab66da614173dfcd34f9c7047295cabbe0fa4b3;p=soc.git

Do not reset pc_changed and sv_changed at instruction end

We need these outputs to hold stable, so the Issue FSM can know whether
it can return to the Simple-V loop, or must return to Fetch. A good place
to reset these is at the start, before any instruction is executed.
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 877c7382..f1e197ea 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -369,6 +369,8 @@ class TestIssuerInternal(Elaboratable):
                 with m.If(exec_insn_valid_i):
                     comb += core_ivalid_i.eq(1)  # instruction is valid
                     comb += core_issue_i.eq(1)  # and issued
+                    sync += sv_changed.eq(0)
+                    sync += pc_changed.eq(0)
                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 
             # instruction started: must wait till it finishes
@@ -385,8 +387,6 @@ class TestIssuerInternal(Elaboratable):
                     sync += core.e.eq(0)
                     sync += core.raw_insn_i.eq(0)
                     sync += core.bigendian_i.eq(0)
-                    sync += sv_changed.eq(0)
-                    sync += pc_changed.eq(0)
                     comb += exec_pc_valid_o.eq(1)
                     with m.If(exec_pc_ready_i):
                         m.next = "INSN_START"  # back to fetch