From: Clifford Wolf Date: Thu, 31 May 2018 16:09:31 +0000 (+0200) Subject: Bugfix in handling of array instances with empty ports X-Git-Tag: yosys-0.8~79 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ab79a231b1b31f1177df2c1351643eda4e9553b;p=yosys.git Bugfix in handling of array instances with empty ports Signed-off-by: Clifford Wolf --- diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 18dfa7184..bfb8e7f95 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -258,7 +258,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check if (mod->wires_.count(portname) == 0) log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); int port_size = mod->wires_.at(portname)->width; - if (conn_size == port_size) + if (conn_size == port_size || conn_size == 0) continue; if (conn_size != port_size*num) log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));