From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 18:21:03 +0000 (-0700)
Subject: Add +/xilinx/cells_box.v containing models for ABC boxes
X-Git-Tag: working-ls180~1208^2~342
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ac4977b70a373cdabaa72e5f08050f49a3d4046;p=yosys.git

Add +/xilinx/cells_box.v containing models for ABC boxes
---

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 432bb0770..43be55d51 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_box.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
diff --git a/techlibs/xilinx/cells_box.v b/techlibs/xilinx/cells_box.v
new file mode 100644
index 000000000..7805e6306
--- /dev/null
+++ b/techlibs/xilinx/cells_box.v
@@ -0,0 +1,10 @@
+(* abc_box_id = 1 *)
+module MUXF7(output O, input I0, I1, S);
+  assign O = S ? I1 : I0;
+endmodule
+
+(* abc_box_id = 2 *)
+module MUXF8(output O, input I0, I1, S);
+  assign O = S ? I1 : I0;
+endmodule
+