From: Steve Reinhardt Date: Sun, 1 Jul 2007 03:35:42 +0000 (-0700) Subject: Make CPU models use new LoadLockedReq/StoreCondReq commands. X-Git-Tag: m5_2.0_beta4~195^2~50^2~17 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ad761bc8e89ff034fbf5ec6d8e9661e1025dcd7;p=gem5.git Make CPU models use new LoadLockedReq/StoreCondReq commands. --HG-- extra : convert_revision : ab78d9d1d88c3698edfd653d71c8882e1272b781 --- diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index d964b9f9f..be9224099 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -643,7 +643,10 @@ LSQUnit::read(Request *req, T &data, int load_idx) // if we the cache is not blocked, do cache access if (!lsq->cacheBlocked()) { PacketPtr data_pkt = - new Packet(req, MemCmd::ReadReq, Packet::Broadcast); + new Packet(req, + (req->isLocked() ? + MemCmd::LoadLockedReq : MemCmd::ReadReq), + Packet::Broadcast); data_pkt->dataStatic(load_inst->memData); LSQSenderState *state = new LSQSenderState; diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 810a6d29f..5ae1cc0e4 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -647,7 +647,9 @@ LSQUnit::writebackStores() memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); - MemCmd command = req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq; + MemCmd command = + req->isSwap() ? MemCmd::SwapReq : + (req->isLocked() ? MemCmd::WriteReq : MemCmd::StoreCondReq); PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast); data_pkt->dataStatic(inst->memData); diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index d9e0d04ac..ba40e9ce1 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -632,7 +632,11 @@ OzoneLWLSQ::read(RequestPtr req, T &data, int load_idx) DPRINTF(OzoneLSQ, "Doing timing access for inst PC %#x\n", inst->readPC()); - PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); + PacketPtr data_pkt = + new Packet(req, + (req->isLocked() ? + MemCmd::LoadLockedReq : Packet::ReadReq), + Packet::Broadcast); data_pkt->dataStatic(inst->memData); LSQSenderState *state = new LSQSenderState; diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index e3000288c..82191312a 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -587,7 +587,10 @@ OzoneLWLSQ::writebackStores() memcpy(inst->memData, (uint8_t *)&(*sq_it).data, req->getSize()); - PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); + MemCmd command = + req->isSwap() ? MemCmd::SwapReq : + (req->isLocked() ? MemCmd::WriteReq : MemCmd::StoreCondReq); + PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast); data_pkt->dataStatic(inst->memData); LSQSenderState *state = new LSQSenderState; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 8e8da2fa2..01eb4873e 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -280,7 +280,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) // Now do the access. if (fault == NoFault) { - Packet pkt = Packet(req, MemCmd::ReadReq, Packet::Broadcast); + Packet pkt = + Packet(req, + req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, + Packet::Broadcast); pkt.dataStatic(&data); if (req->isMmapedIpr()) @@ -370,23 +373,24 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) // Now do the access. if (fault == NoFault) { - Packet pkt = - Packet(req, req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq, - Packet::Broadcast); - pkt.dataStatic(&data); - + MemCmd cmd = MemCmd::WriteReq; // default bool do_access = true; // flag to suppress cache access if (req->isLocked()) { + cmd = MemCmd::StoreCondReq; do_access = TheISA::handleLockedWrite(thread, req); + } else if (req->isSwap()) { + cmd = MemCmd::SwapReq; + if (req->isCondSwap()) { + assert(res); + req->setExtraData(*res); + } } - if (req->isCondSwap()) { - assert(res); - req->setExtraData(*res); - } - if (do_access) { + Packet pkt = Packet(req, cmd, Packet::Broadcast); + pkt.dataStatic(&data); + if (req->isMmapedIpr()) { dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt); } else { @@ -395,12 +399,14 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) } dcache_access = true; assert(!pkt.isError()); + + if (req->isSwap()) { + assert(res); + *res = pkt.get(); + } } - if (req->isSwap()) { - assert(res); - *res = pkt.get(); - } else if (res) { + if (res && !req->isSwap()) { *res = req->getExtraData(); } } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index b4e4a4433..77df2c05d 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -260,7 +260,10 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) // Now do the access. if (fault == NoFault) { PacketPtr pkt = - new Packet(req, MemCmd::ReadReq, Packet::Broadcast); + new Packet(req, + (req->isLocked() ? + MemCmd::LoadLockedReq : MemCmd::ReadReq), + Packet::Broadcast); pkt->dataDynamic(new T); if (!dcachePort.sendTiming(pkt)) { @@ -350,25 +353,27 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) // Now do the access. if (fault == NoFault) { - assert(dcache_pkt == NULL); - if (req->isSwap()) - dcache_pkt = new Packet(req, MemCmd::SwapReq, Packet::Broadcast); - else - dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast); - dcache_pkt->allocate(); - dcache_pkt->set(data); - + MemCmd cmd = MemCmd::WriteReq; // default bool do_access = true; // flag to suppress cache access + assert(dcache_pkt == NULL); + if (req->isLocked()) { + cmd = MemCmd::StoreCondReq; do_access = TheISA::handleLockedWrite(thread, req); - } - if (req->isCondSwap()) { - assert(res); - req->setExtraData(*res); + } else if (req->isSwap()) { + cmd = MemCmd::SwapReq; + if (req->isCondSwap()) { + assert(res); + req->setExtraData(*res); + } } if (do_access) { + dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast); + dcache_pkt->allocate(); + dcache_pkt->set(data); + if (!dcachePort.sendTiming(dcache_pkt)) { _status = DcacheRetry; } else { @@ -609,7 +614,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) Fault fault = curStaticInst->completeAcc(pkt, this, traceData); - if (pkt->isRead() && pkt->req->isLocked()) { + if (pkt->isRead() && pkt->isLocked()) { TheISA::handleLockedRead(thread, pkt->req); }