From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Mar 2020 13:51:03 +0000 (-0700)
Subject: verilog: add test
X-Git-Tag: working-ls180~753^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ada82639ffd559da8d3f89664ac279ab2280dae;p=yosys.git

verilog: add test
---

diff --git a/tests/various/src.ys b/tests/various/src.ys
new file mode 100644
index 000000000..89d6700ca
--- /dev/null
+++ b/tests/various/src.ys
@@ -0,0 +1,8 @@
+logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1
+logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1
+read_verilog <<EOT
+module top(input i, output o, p);
+always @* o <= i;
+always @* p = i;
+endmodule
+EOT